-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.2 (lin64) Build 5239630 Fri Nov 08 22:34:34 MST 2024
-- Date        : Mon Apr 13 17:52:03 2026
-- Host        : jim running 64-bit Ubuntu 24.04.3 LTS
-- Command     : write_vhdl -force -mode funcsim
--               /home/mpsitech/fpgacode/zudvk/wskd/wskd.gen/sources_1/bd/design_1/ip/design_1_Vsp_core_0_0/design_1_Vsp_core_0_0_sim_netlist.vhdl
-- Design      : design_1_Vsp_core_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xczu1cg-sbva484-1-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Axislave_v1_0 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[4]\ : out STD_LOGIC;
    \stateRecv_reg[0]_0\ : out STD_LOGIC;
    \stateOp_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[4]_0\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \stateOp_reg[4]_1\ : out STD_LOGIC;
    recvAXIS_tdata : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \resid_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ixRetbufCrc_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[5]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[5]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateRecv_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[5]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \recvAXIS_tdata_sig_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \stateOp_reg[4]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[4]_3\ : out STD_LOGIC;
    \ixRetbufCrc_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \recvAXIS_tdata_sig_reg[7]_1\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \stateOp_reg[3]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
    \stateOp_reg[4]_4\ : out STD_LOGIC;
    \resid_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \tixVCommand_reg[0]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    apuAXIL_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    recvAXIS_tlast : out STD_LOGIC;
    \stateOp_reg[4]_5\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
    \tixVCommand_reg[0]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \len_reg[2]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \stateOp_reg[5]_3\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \stateOp_reg[4]_6\ : out STD_LOGIC_VECTOR ( 30 downto 0 );
    \stateOp_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateSend_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[5]_4\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \stateOp_reg[5]_5\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \tixVController_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \tixVCommand_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \stateSend_reg[2]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[4]_7\ : out STD_LOGIC_VECTOR ( 28 downto 0 );
    \stateOp_reg[4]_8\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[4]_9\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_4\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_5\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_6\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_7\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_8\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_4\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_5\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_6\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_7\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_8\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_9\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_10\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_11\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_12\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_13\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_14\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_15\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ixRetbufCrc_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_16\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_17\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_18\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ixRetbufCrc_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_19\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_20\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \TCapt_reg[7]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \lastAXIS_tkeep_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \stateOp_reg[1]_9\ : out STD_LOGIC_VECTOR ( 45 downto 0 );
    \tixVBuffer_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \crc_imd_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \stateOp_reg[4]_10\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \TCapt_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \crc_imd_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \NWrB_reg[7]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
    \stateOp_reg[4]_11\ : out STD_LOGIC;
    \stateOp_reg[4]_12\ : out STD_LOGIC;
    \NWrB_reg[15]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \NWrB_reg[23]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \NWrB_reg[31]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \NWrA_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \NWrA_reg[15]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \NWrA_reg[23]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \NWrA_reg[31]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \tixVController_reg[3]\ : out STD_LOGIC;
    \tixVController_reg[3]_0\ : out STD_LOGIC;
    \tixVController_reg[7]_0\ : out STD_LOGIC;
    \stateOp_reg[4]_13\ : out STD_LOGIC_VECTOR ( 24 downto 0 );
    \recvAXIS_tdata_sig_reg[7]_2\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \opbuf_reg[3][7]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \opbuf_reg[1][7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \opbuf_reg[0][7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \stateOp_reg[5]_6\ : out STD_LOGIC;
    \stateOp_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \opbuf_reg[2][7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \recvAXIS_tdata_sig_reg[47]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \recvAXIS_tdata_sig_reg[7]_3\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \recvAXIS_tdata_sig_reg[7]_4\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \recvAXIS_tdata_sig_reg[7]_5\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \recvAXIS_tdata_sig_reg[7]_6\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \stateOp_reg[4]_14\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[0]_0\ : out STD_LOGIC;
    \stateRecv_reg[0]_1\ : out STD_LOGIC;
    AXIS_tlast : out STD_LOGIC;
    AXIS_tvalid : out STD_LOGIC;
    \recvAXIS_tdata_sig_reg[15]_0\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    \stateOp_reg[2]_1\ : out STD_LOGIC;
    \stateOp_reg[5]_7\ : out STD_LOGIC;
    commok_sig_reg : out STD_LOGIC;
    reqReset_sig_reg : out STD_LOGIC;
    \rxlen_reg[0]\ : out STD_LOGIC;
    \crc_imd_reg[7]_1\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
    recvAXIS_tlast_sig_reg_0 : out STD_LOGIC;
    crc_imd041_out : out STD_LOGIC;
    crc_imd043_out : out STD_LOGIC;
    \crc_imd_reg[12]\ : out STD_LOGIC;
    \crc_imd_reg[12]_0\ : out STD_LOGIC;
    \crc_imd_reg[13]\ : out STD_LOGIC;
    \crc_imd_reg[11]\ : out STD_LOGIC;
    \crc_imd_reg[3]\ : out STD_LOGIC;
    \txAXIS_tdata_reg[13]\ : out STD_LOGIC;
    crc_imd0172_out : out STD_LOGIC;
    crc_imd0112_out : out STD_LOGIC;
    \crc_imd_reg[15]\ : out STD_LOGIC;
    crc_imd042_out : out STD_LOGIC;
    crc_imd0115_out : out STD_LOGIC;
    crc_imd0174_out : out STD_LOGIC;
    crc_imd0118_out : out STD_LOGIC;
    crc_imd0173_out : out STD_LOGIC;
    \crcAXIS_tkeep_reg[0]\ : out STD_LOGIC;
    crc_imd0148_out : out STD_LOGIC;
    crc_imd0121_out : out STD_LOGIC;
    crc_imd0176_out : out STD_LOGIC;
    crc_imd0100_out : out STD_LOGIC;
    crc_imd0124_out : out STD_LOGIC;
    crc_imd066_out : out STD_LOGIC;
    crc_imd0175_out : out STD_LOGIC;
    crc_imd065_out : out STD_LOGIC;
    crc_imd0165_out : out STD_LOGIC;
    crc_imd0202_out : out STD_LOGIC;
    crc_imd083_out : out STD_LOGIC;
    crc_imd0198_out : out STD_LOGIC;
    crc_imd0200_out : out STD_LOGIC;
    crc_imd086_out : out STD_LOGIC;
    crc_imd0152_out : out STD_LOGIC;
    crc_imd087_out : out STD_LOGIC;
    \txAXIS_tdata_reg[7]\ : out STD_LOGIC;
    crc_imd081_out : out STD_LOGIC;
    crc_imd0149_out : out STD_LOGIC;
    crc_imd085_out : out STD_LOGIC;
    crc_imd0150_out : out STD_LOGIC;
    crc_imd0151_out : out STD_LOGIC;
    crc_imd069_out : out STD_LOGIC;
    crc_imd068_out : out STD_LOGIC;
    crc_imd067_out : out STD_LOGIC;
    p_136_in : out STD_LOGIC;
    crcAXIS_tlast_sig_reg : out STD_LOGIC;
    AXIL_wready_sig_reg_0 : out STD_LOGIC;
    AXIL_awready_sig_reg_0 : out STD_LOGIC;
    AXIL_arready : out STD_LOGIC;
    AXIL_bvalid_sig_reg_0 : out STD_LOGIC;
    apuAXIL_rvalid : out STD_LOGIC;
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    crcAXIS_tlast_sig_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \invbuf_reg[9][0]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \invbuf_reg[9][0]_0\ : in STD_LOGIC;
    \invbuf_reg[9][0]_1\ : in STD_LOGIC;
    \invbuf_reg[9][0]_2\ : in STD_LOGIC;
    \invbuf_reg[9][0]_3\ : in STD_LOGIC;
    \invbuf_reg[9][0]_4\ : in STD_LOGIC;
    \invbuf_reg[9][0]_5\ : in STD_LOGIC;
    \lastAXIS_tkeep_reg[1]\ : in STD_LOGIC;
    \stateOp_reg[0]_1\ : in STD_LOGIC;
    \stateOp_reg[0]_2\ : in STD_LOGIC;
    \wordcntLast_reg[28]\ : in STD_LOGIC;
    \stateOp_reg[0]_3\ : in STD_LOGIC;
    \retbuf_reg[0][7]\ : in STD_LOGIC;
    \retbuf_reg[0][7]_0\ : in STD_LOGIC;
    \retbuf_reg[0][7]_1\ : in STD_LOGIC;
    \retbuf_reg[0][7]_2\ : in STD_LOGIC;
    \retbuf_reg[0][7]_3\ : in STD_LOGIC;
    \retbuf_reg[3][7]\ : in STD_LOGIC;
    \retbuf_reg[3][7]_0\ : in STD_LOGIC;
    \retbuf_reg[3][7]_1\ : in STD_LOGIC;
    \retbuf_reg[4][7]\ : in STD_LOGIC;
    \retbuf_reg[4][7]_0\ : in STD_LOGIC;
    \retbuf_reg[4][7]_1\ : in STD_LOGIC;
    \retbuf_reg[7][7]\ : in STD_LOGIC;
    \retbuf_reg[7][7]_0\ : in STD_LOGIC;
    \retbuf_reg[7][7]_1\ : in STD_LOGIC;
    \invbuf_reg[7][0]\ : in STD_LOGIC;
    \invbuf_reg[7][0]_0\ : in STD_LOGIC;
    commok_sig_reg_0 : in STD_LOGIC;
    \wordcntLast_reg[28]_0\ : in STD_LOGIC;
    \wordcntLast_reg[28]_1\ : in STD_LOGIC;
    \wordcntCrcLast_reg[24]\ : in STD_LOGIC;
    \retbuf_reg[15][0]\ : in STD_LOGIC;
    reqReset_sig_reg_0 : in STD_LOGIC;
    \retbuf_reg[15][0]_0\ : in STD_LOGIC;
    \retbuf_reg[15][0]_1\ : in STD_LOGIC;
    reqReset_sig_reg_1 : in STD_LOGIC;
    \pollbuf_reg[3][5]\ : in STD_LOGIC;
    \pollbuf_reg[3][5]_0\ : in STD_LOGIC;
    \pollbuf_reg[1][7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \retbuf_reg[39][7]\ : in STD_LOGIC;
    \retbuf_reg[39][7]_0\ : in STD_LOGIC;
    \retbuf_reg[39][7]_1\ : in STD_LOGIC;
    \retbuf_reg[39][7]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \retbuf_reg[39][7]_3\ : in STD_LOGIC;
    \pollbuf_reg[2][3]\ : in STD_LOGIC;
    \pollbuf_reg[2][3]_0\ : in STD_LOGIC;
    \pollbuf_reg[2][3]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[56]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[56]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[56]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[48]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[48]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[48]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[40]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[32]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[32]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \txAXIS_tdata_reg[32]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[24]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[16]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[16]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[8]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[8]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[8]_1\ : in STD_LOGIC;
    \retbuf_reg[35][0]\ : in STD_LOGIC;
    \retbuf_reg[36][7]\ : in STD_LOGIC;
    \retbuf_reg[4][7]_2\ : in STD_LOGIC;
    \retbuf_reg[36][7]_0\ : in STD_LOGIC;
    \retbuf_reg[37][7]\ : in STD_LOGIC;
    \retbuf_reg[38][7]\ : in STD_LOGIC;
    \retbuf_reg[38][7]_0\ : in STD_LOGIC;
    \lastAXIS_tkeep_reg[1]_0\ : in STD_LOGIC;
    \lastAXIS_tkeep_reg[5]\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[7]\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[3]\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[3]_0\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[0]_0\ : in STD_LOGIC;
    \pollbuf_reg[3][1]\ : in STD_LOGIC;
    \ixRetbufCrc_reg[0]_0\ : in STD_LOGIC;
    \ixRetbufCrc_reg[2]\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[6]\ : in STD_LOGIC;
    \lastAXIS_tkeep_reg[2]\ : in STD_LOGIC;
    \stateOp_next_reg[5]\ : in STD_LOGIC;
    \stateOp_next_reg[5]_0\ : in STD_LOGIC;
    \stateOp_next_reg[4]\ : in STD_LOGIC;
    \stateOp_next_reg[1]\ : in STD_LOGIC;
    \stateOp_next_reg[5]_1\ : in STD_LOGIC;
    \resid_reg[0]_21\ : in STD_LOGIC;
    \resid_reg[1]\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[4]\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[7]_0\ : in STD_LOGIC;
    \wordcnt_reg[1]_0\ : in STD_LOGIC;
    txlast1 : in STD_LOGIC_VECTOR ( 29 downto 0 );
    \wordcnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \crcAXIS_tkeep_reg[3]_1\ : in STD_LOGIC;
    \stateOp_reg[0]_4\ : in STD_LOGIC;
    \stateOp_reg[0]_5\ : in STD_LOGIC;
    crcAXIS_tlast_sig_reg_1 : in STD_LOGIC;
    crcAXIS_tlast_sig_reg_2 : in STD_LOGIC;
    \stateOp_next_reg[0]\ : in STD_LOGIC;
    crcAXIS_tlast_sig_i_8_0 : in STD_LOGIC;
    crcAXIS_tlast_sig_i_8_1 : in STD_LOGIC;
    crcAXIS_tlast_sig_i_8_2 : in STD_LOGIC;
    \wordcnt_reg[0]_1\ : in STD_LOGIC;
    \wordcnt_reg[0]_2\ : in STD_LOGIC;
    \stateOp_reg[0]_6\ : in STD_LOGIC;
    \stateOp_reg[0]_7\ : in STD_LOGIC;
    \pollbuf_reg[0][7]\ : in STD_LOGIC;
    \pollbuf_reg[0][7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \pollbuf_reg[0][7]_1\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[0]_1\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[0]_2\ : in STD_LOGIC;
    \wordcntLast_reg[0]\ : in STD_LOGIC;
    \wordcntLast_reg[0]_0\ : in STD_LOGIC;
    \wordcntLast_reg[0]_1\ : in STD_LOGIC;
    \wordcntLast_reg[0]_2\ : in STD_LOGIC;
    \retbuf_reg[1][0]\ : in STD_LOGIC;
    \retbuf_reg[1][0]_0\ : in STD_LOGIC;
    \retbuf_reg[1][0]_1\ : in STD_LOGIC;
    \retbuf_reg[1][0]_2\ : in STD_LOGIC;
    \retbuf_reg[2][0]\ : in STD_LOGIC;
    \retbuf_reg[5][0]\ : in STD_LOGIC;
    \retbuf_reg[5][0]_0\ : in STD_LOGIC;
    \retbuf_reg[6][0]\ : in STD_LOGIC;
    \retbuf_reg[8][0]\ : in STD_LOGIC;
    \retbuf_reg[9][0]\ : in STD_LOGIC;
    \retbuf_reg[10][0]\ : in STD_LOGIC;
    \retbuf_reg[11][0]\ : in STD_LOGIC;
    \retbuf_reg[12][0]\ : in STD_LOGIC;
    \retbuf_reg[13][0]\ : in STD_LOGIC;
    \retbuf_reg[14][0]\ : in STD_LOGIC;
    \retbuf_reg[15][0]_2\ : in STD_LOGIC;
    \retbuf_reg[16][0]\ : in STD_LOGIC;
    \retbuf_reg[16][0]_0\ : in STD_LOGIC;
    \retbuf_reg[16][0]_1\ : in STD_LOGIC;
    \retbuf_reg[17][0]\ : in STD_LOGIC;
    \retbuf_reg[18][0]\ : in STD_LOGIC;
    \retbuf_reg[19][0]\ : in STD_LOGIC;
    \retbuf_reg[20][0]\ : in STD_LOGIC;
    \retbuf_reg[21][0]\ : in STD_LOGIC;
    \retbuf_reg[22][0]\ : in STD_LOGIC;
    \retbuf_reg[23][0]\ : in STD_LOGIC;
    \retbuf_reg[24][0]\ : in STD_LOGIC;
    \retbuf_reg[25][0]\ : in STD_LOGIC;
    \retbuf_reg[26][0]\ : in STD_LOGIC;
    \retbuf_reg[27][0]\ : in STD_LOGIC;
    \retbuf_reg[28][0]\ : in STD_LOGIC;
    \retbuf_reg[29][0]\ : in STD_LOGIC;
    \retbuf_reg[29][0]_0\ : in STD_LOGIC;
    \retbuf_reg[30][0]\ : in STD_LOGIC;
    \retbuf_reg[30][0]_0\ : in STD_LOGIC;
    \retbuf_reg[31][0]\ : in STD_LOGIC;
    \retbuf_reg[32][0]\ : in STD_LOGIC;
    \retbuf_reg[33][0]\ : in STD_LOGIC;
    \retbuf_reg[34][0]\ : in STD_LOGIC;
    \retbuf_reg[34][0]_0\ : in STD_LOGIC;
    \retbuf_reg[4][7]_3\ : in STD_LOGIC;
    \retbuf_reg[3][7]_2\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \retbuf_reg[4][7]_4\ : in STD_LOGIC;
    \retbuf_reg[4][7]_5\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[7]_1\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
    \crcAXIS_tkeep_reg[7]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[0]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[0]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[0]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[2]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[2]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[2]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[4]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[4]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[4]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[4]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[6]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[6]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[6]_1\ : in STD_LOGIC;
    \pollbuf_reg[2][4]\ : in STD_LOGIC;
    \pollbuf_reg[2][3]_2\ : in STD_LOGIC;
    \pollbuf_reg[2][7]\ : in STD_LOGIC;
    \retbuf_reg[7][7]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \retbuf_reg[7][5]\ : in STD_LOGIC;
    \retbuf_reg[7][5]_0\ : in STD_LOGIC;
    \retbuf_reg[6][5]\ : in STD_LOGIC;
    \retbuf_reg[6][5]_0\ : in STD_LOGIC;
    vidtrackGetInfoPtr0Seqbuf : in STD_LOGIC_VECTOR ( 0 to 0 );
    \retbuf_reg[6][5]_1\ : in STD_LOGIC;
    \retbuf_reg[3][2]\ : in STD_LOGIC;
    \retbuf_reg[3][2]_0\ : in STD_LOGIC;
    \retbuf_reg[3][3]\ : in STD_LOGIC;
    \retbuf_reg[3][3]_0\ : in STD_LOGIC;
    \retbuf_reg[3][6]\ : in STD_LOGIC;
    \retbuf_reg[3][6]_0\ : in STD_LOGIC;
    \retbuf_reg[3][7]_3\ : in STD_LOGIC;
    \retbuf_reg[3][7]_4\ : in STD_LOGIC;
    \retbuf_reg[0][0]\ : in STD_LOGIC;
    vidtrackGetInfoTixVState : in STD_LOGIC_VECTOR ( 0 to 0 );
    \retbuf_reg[0][0]_0\ : in STD_LOGIC;
    \retbuf_reg[15][7]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \retbuf_reg[15][1]\ : in STD_LOGIC;
    \retbuf_reg[12][7]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \retbuf_reg[14][0]_0\ : in STD_LOGIC;
    \retbuf_reg[13][0]_0\ : in STD_LOGIC;
    \retbuf_reg[12][0]_0\ : in STD_LOGIC;
    \retbuf_reg[8][7]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \retbuf_reg[11][4]\ : in STD_LOGIC;
    \retbuf_reg[10][0]_0\ : in STD_LOGIC;
    \retbuf_reg[9][0]_0\ : in STD_LOGIC;
    \retbuf_reg[8][0]_0\ : in STD_LOGIC;
    \retbuf_reg[7][4]\ : in STD_LOGIC;
    \retbuf_reg[4][0]\ : in STD_LOGIC;
    \retbuf_reg[2][7]\ : in STD_LOGIC;
    \retbuf_reg[2][7]_0\ : in STD_LOGIC;
    \retbuf_reg[0][2]\ : in STD_LOGIC;
    \retbuf_reg[4][0]_0\ : in STD_LOGIC;
    \retbuf_reg[4][0]_1\ : in STD_LOGIC;
    \retbuf_reg[4][1]\ : in STD_LOGIC;
    \retbuf_reg[4][1]_0\ : in STD_LOGIC;
    \retbuf_reg[4][2]\ : in STD_LOGIC;
    \retbuf_reg[4][2]_0\ : in STD_LOGIC;
    \retbuf_reg[4][3]\ : in STD_LOGIC;
    \retbuf_reg[4][3]_0\ : in STD_LOGIC;
    \retbuf_reg[0][2]_0\ : in STD_LOGIC;
    \retbuf_reg[0][2]_1\ : in STD_LOGIC;
    \retbuf_reg[0][7]_4\ : in STD_LOGIC;
    \rxlen_reg[0]_0\ : in STD_LOGIC;
    \rxlen_reg[0]_1\ : in STD_LOGIC;
    \rxlen_reg[0]_2\ : in STD_LOGIC;
    plusOp : in STD_LOGIC_VECTOR ( 28 downto 0 );
    \wordcntCrcLast_reg[0]\ : in STD_LOGIC;
    \wordcntCrcLast_reg[1]\ : in STD_LOGIC;
    O : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \wordcntCrcLast_reg[2]\ : in STD_LOGIC;
    \wordcntCrcLast_reg[16]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \wordcntCrcLast_reg[24]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \invbuf_reg[9][0]_6\ : in STD_LOGIC;
    \len_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \len_reg[15]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \len_reg[23]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \len_reg[31]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \tixVController_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \tixVBuffer_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \stateOp_reg[1]_10\ : in STD_LOGIC;
    \stateOp_reg[1]_11\ : in STD_LOGIC;
    \stateOp_reg[1]_12\ : in STD_LOGIC;
    \stateOp_reg[2]_2\ : in STD_LOGIC;
    \stateOp_reg[2]_3\ : in STD_LOGIC;
    \txAXIS_tdata_reg[5]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[5]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[5]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[5]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[5]_3\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[16]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[16]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[16]_3\ : in STD_LOGIC;
    \txAXIS_tdata_reg[16]_4\ : in STD_LOGIC;
    \txAXIS_tdata_reg[17]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[17]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[17]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[18]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[18]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[18]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[19]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[19]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[23]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \txAXIS_tdata_reg[19]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[19]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[20]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[20]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[20]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[21]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[21]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[21]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[22]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[22]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[22]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[23]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[23]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[23]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[24]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[24]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[29]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \txAXIS_tdata_reg[24]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[25]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[25]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[25]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[26]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[26]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[26]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[27]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[27]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[27]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[28]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[28]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[28]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[29]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[29]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[29]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[30]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[30]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[30]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[31]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[31]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[31]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[32]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[32]_3\ : in STD_LOGIC;
    \txAXIS_tdata_reg[33]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[33]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[34]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[34]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[35]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[35]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[36]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[36]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[37]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[37]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[38]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[38]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[39]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[39]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[48]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[48]_3\ : in STD_LOGIC;
    \txAXIS_tdata_reg[48]_4\ : in STD_LOGIC;
    \txAXIS_tdata_reg[48]_5\ : in STD_LOGIC;
    \txAXIS_tdata_reg[49]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[49]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[49]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[50]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[50]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[50]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[51]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[51]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[51]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[52]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[52]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[52]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[53]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[53]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[53]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[54]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[54]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[54]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[55]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[55]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[55]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[56]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[56]_3\ : in STD_LOGIC;
    \txAXIS_tdata_reg[56]_4\ : in STD_LOGIC;
    \txAXIS_tdata_reg[57]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[57]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[57]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[58]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[58]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[59]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[59]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[60]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[60]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[60]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[61]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[61]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[61]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[62]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[62]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[63]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[63]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[63]_1\ : in STD_LOGIC;
    \stateOp_reg[3]_1\ : in STD_LOGIC;
    \stateOp_reg[4]_15\ : in STD_LOGIC;
    \stateOp_reg[4]_16\ : in STD_LOGIC;
    \tixVBufxfop_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \txlen_reg[0]\ : in STD_LOGIC;
    \wordcntLast_reg[3]\ : in STD_LOGIC;
    commok_sig_reg_1 : in STD_LOGIC;
    \stateOp_reg[0]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateOp_reg[0]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    stateOp_reg : in STD_LOGIC;
    \stateOp_reg[0]_10\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[0]_3\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[0]_4\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[0]_5\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[0]_6\ : in STD_LOGIC;
    crcAXIS_tlast_sig_reg_3 : in STD_LOGIC;
    \crc_imd_reg[4]\ : in STD_LOGIC;
    crcAXIS_tlast_sig_i_6_0 : in STD_LOGIC;
    \wordcnt_reg[0]_3\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[0]_7\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[0]_11\ : in STD_LOGIC;
    \stateOp_reg[0]_12\ : in STD_LOGIC;
    \stateOp_reg[0]_13\ : in STD_LOGIC;
    \sendAXIL_rdata_reg[63]_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \stateOp[3]_i_3_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[3]_2\ : in STD_LOGIC;
    \stateOp_reg[1]_13\ : in STD_LOGIC;
    crcAXIS_tlast_sig_i_6_1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    crcAXIS_tlast_sig_reg_4 : in STD_LOGIC;
    commok_sig_reg_2 : in STD_LOGIC;
    commok_sig_reg_3 : in STD_LOGIC;
    reqResetFromHostif : in STD_LOGIC;
    \rxlen_reg[0]_3\ : in STD_LOGIC;
    \rxlen_reg[0]_4\ : in STD_LOGIC;
    \crc_imd_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \crc_imd_reg[0]_0\ : in STD_LOGIC;
    \crc_imd_reg[9]\ : in STD_LOGIC;
    \crc_imd_reg[2]_0\ : in STD_LOGIC;
    \crc_imd_reg[2]_1\ : in STD_LOGIC;
    \crc_imd_reg[4]_0\ : in STD_LOGIC;
    \crc_imd_reg[8]\ : in STD_LOGIC;
    \crc_imd_reg[8]_0\ : in STD_LOGIC;
    p_10_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    \crc_imd_reg[0]_1\ : in STD_LOGIC;
    \crc_imd_reg[1]\ : in STD_LOGIC;
    \crc_imd[1]_i_4_0\ : in STD_LOGIC;
    \crc_imd_reg[1]_0\ : in STD_LOGIC;
    \crc_imd_reg[0]_2\ : in STD_LOGIC;
    \crc_imd_reg[2]_2\ : in STD_LOGIC;
    \crc_imd_reg[8]_1\ : in STD_LOGIC;
    \crc_imd_reg[1]_1\ : in STD_LOGIC;
    \crc_imd[15]_i_41_0\ : in STD_LOGIC;
    \crc_imd[14]_i_5\ : in STD_LOGIC;
    \crc_imd[12]_i_3\ : in STD_LOGIC;
    \crc_imd[14]_i_5_0\ : in STD_LOGIC;
    \crc_imd[12]_i_3_0\ : in STD_LOGIC;
    apuAXIL_wvalid : in STD_LOGIC;
    AXIL_rvalid_sig_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    aclk_sig : in STD_LOGIC;
    apuAXIL_awvalid : in STD_LOGIC;
    apuAXIL_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    apuAXIL_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    apuAXIL_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    apuAXIL_bready : in STD_LOGIC;
    apuAXIL_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
    apuAXIL_arvalid : in STD_LOGIC;
    recvAXIS_tlast_sig_reg_i_2_0 : in STD_LOGIC_VECTOR ( 28 downto 0 );
    apuAXIL_rready : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Axislave_v1_0 : entity is "Axislave_v1_0";
end design_1_Vsp_core_0_0_Axislave_v1_0;

architecture STRUCTURE of design_1_Vsp_core_0_0_Axislave_v1_0 is
  signal AXIL_araddr_sig : STD_LOGIC_VECTOR ( 5 downto 4 );
  signal \^axil_arready\ : STD_LOGIC;
  signal AXIL_arready_sig0 : STD_LOGIC;
  signal AXIL_awready_sig0 : STD_LOGIC;
  signal AXIL_awready_sig_i_1_n_0 : STD_LOGIC;
  signal \^axil_awready_sig_reg_0\ : STD_LOGIC;
  signal AXIL_bvalid_sig_i_1_n_0 : STD_LOGIC;
  signal \^axil_bvalid_sig_reg_0\ : STD_LOGIC;
  signal AXIL_rvalid_sig_i_1_n_0 : STD_LOGIC;
  signal \AXIL_wdata_sig[15]_i_1_n_0\ : STD_LOGIC;
  signal \AXIL_wdata_sig[23]_i_1_n_0\ : STD_LOGIC;
  signal \AXIL_wdata_sig[31]_i_1_n_0\ : STD_LOGIC;
  signal \AXIL_wdata_sig[39]_i_1_n_0\ : STD_LOGIC;
  signal \AXIL_wdata_sig[47]_i_1_n_0\ : STD_LOGIC;
  signal \AXIL_wdata_sig[55]_i_1_n_0\ : STD_LOGIC;
  signal \AXIL_wdata_sig[63]_i_1_n_0\ : STD_LOGIC;
  signal \AXIL_wdata_sig[7]_i_1_n_0\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[0]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[10]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[11]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[12]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[13]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[14]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[15]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[16]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[17]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[18]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[19]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[1]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[20]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[21]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[22]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[23]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[24]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[25]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[26]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[27]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[28]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[29]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[30]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[31]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[32]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[33]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[34]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[35]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[36]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[37]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[38]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[39]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[40]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[41]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[42]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[43]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[44]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[45]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[46]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[47]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[48]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[49]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[4]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[50]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[51]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[52]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[53]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[54]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[55]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[56]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[57]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[58]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[59]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[5]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[60]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[61]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[62]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[63]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[6]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[7]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[8]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[9]\ : STD_LOGIC;
  signal AXIL_wready_sig_i_1_n_0 : STD_LOGIC;
  signal \^axil_wready_sig_reg_0\ : STD_LOGIC;
  signal AXIS_tdata : STD_LOGIC_VECTOR ( 63 downto 8 );
  signal ackRxtx : STD_LOGIC;
  signal \apuAXIL_rdata[63]_INST_0_i_1_n_0\ : STD_LOGIC;
  signal \^apuaxil_rvalid\ : STD_LOGIC;
  signal \awdone_i_1__0_n_0\ : STD_LOGIC;
  signal awdone_reg_n_0 : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[5]_i_2_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_3_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_4_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_7_n_0\ : STD_LOGIC;
  signal crcAXIS_tlast_sig_i_10_n_0 : STD_LOGIC;
  signal crcAXIS_tlast_sig_i_11_n_0 : STD_LOGIC;
  signal crcAXIS_tlast_sig_i_12_n_0 : STD_LOGIC;
  signal crcAXIS_tlast_sig_i_3_n_0 : STD_LOGIC;
  signal crcAXIS_tlast_sig_i_6_n_0 : STD_LOGIC;
  signal crcAXIS_tlast_sig_i_8_n_0 : STD_LOGIC;
  signal \^crc_imd0112_out\ : STD_LOGIC;
  signal \^crc_imd0115_out\ : STD_LOGIC;
  signal \^crc_imd0118_out\ : STD_LOGIC;
  signal \^crc_imd0172_out\ : STD_LOGIC;
  signal \^crc_imd0173_out\ : STD_LOGIC;
  signal \^crc_imd0174_out\ : STD_LOGIC;
  signal \^crc_imd041_out\ : STD_LOGIC;
  signal \^crc_imd042_out\ : STD_LOGIC;
  signal \^crc_imd043_out\ : STD_LOGIC;
  signal \crc_imd[0]_i_10_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_11_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_12_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_13_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_14_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_15_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_16_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_18_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_19_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_20_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_2_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_3_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_4_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_5_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_6_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_7_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_8_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_9_n_0\ : STD_LOGIC;
  signal \crc_imd[10]_i_11_n_0\ : STD_LOGIC;
  signal \crc_imd[10]_i_14_n_0\ : STD_LOGIC;
  signal \crc_imd[10]_i_17_n_0\ : STD_LOGIC;
  signal \crc_imd[11]_i_12_n_0\ : STD_LOGIC;
  signal \crc_imd[11]_i_13_n_0\ : STD_LOGIC;
  signal \crc_imd[11]_i_16_n_0\ : STD_LOGIC;
  signal \crc_imd[11]_i_17_n_0\ : STD_LOGIC;
  signal \crc_imd[11]_i_18_n_0\ : STD_LOGIC;
  signal \crc_imd[12]_i_11_n_0\ : STD_LOGIC;
  signal \crc_imd[12]_i_13_n_0\ : STD_LOGIC;
  signal \crc_imd[12]_i_17_n_0\ : STD_LOGIC;
  signal \crc_imd[13]_i_11_n_0\ : STD_LOGIC;
  signal \crc_imd[13]_i_12_n_0\ : STD_LOGIC;
  signal \crc_imd[13]_i_13_n_0\ : STD_LOGIC;
  signal \crc_imd[13]_i_14_n_0\ : STD_LOGIC;
  signal \crc_imd[14]_i_16_n_0\ : STD_LOGIC;
  signal \crc_imd[14]_i_18_n_0\ : STD_LOGIC;
  signal \crc_imd[14]_i_19_n_0\ : STD_LOGIC;
  signal \crc_imd[14]_i_22_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_10_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_11_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_16_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_17_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_18_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_19_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_21_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_22_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_23_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_27_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_28_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_29_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_30_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_31_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_33_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_34_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_35_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_36_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_37_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_38_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_39_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_40_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_41_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_42_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_47_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_48_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_51_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_53_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_54_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_55_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_60_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_61_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_62_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_63_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_64_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_65_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_66_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_67_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_68_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_6_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_71_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_72_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_73_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_75_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_77_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_78_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_79_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_7_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_8_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_9_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_10_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_12_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_13_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_14_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_15_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_16_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_17_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_18_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_19_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_20_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_21_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_22_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_23_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_24_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_25_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_27_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_28_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_29_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_2_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_3_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_4_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_5_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_6_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_7_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_8_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_9_n_0\ : STD_LOGIC;
  signal \crc_imd[2]_i_2_n_0\ : STD_LOGIC;
  signal \crc_imd[2]_i_4_n_0\ : STD_LOGIC;
  signal \crc_imd[2]_i_6_n_0\ : STD_LOGIC;
  signal \crc_imd[2]_i_8_n_0\ : STD_LOGIC;
  signal \crc_imd[2]_i_9_n_0\ : STD_LOGIC;
  signal \crc_imd[3]_i_5_n_0\ : STD_LOGIC;
  signal \crc_imd[3]_i_6_n_0\ : STD_LOGIC;
  signal \crc_imd[3]_i_7_n_0\ : STD_LOGIC;
  signal \crc_imd[4]_i_2_n_0\ : STD_LOGIC;
  signal \crc_imd[4]_i_4_n_0\ : STD_LOGIC;
  signal \crc_imd[4]_i_6_n_0\ : STD_LOGIC;
  signal \crc_imd[4]_i_7_n_0\ : STD_LOGIC;
  signal \crc_imd[4]_i_8_n_0\ : STD_LOGIC;
  signal \crc_imd[5]_i_7_n_0\ : STD_LOGIC;
  signal \crc_imd[5]_i_8_n_0\ : STD_LOGIC;
  signal \crc_imd[6]_i_10_n_0\ : STD_LOGIC;
  signal \crc_imd[6]_i_11_n_0\ : STD_LOGIC;
  signal \crc_imd[6]_i_12_n_0\ : STD_LOGIC;
  signal \crc_imd[7]_i_11_n_0\ : STD_LOGIC;
  signal \crc_imd[7]_i_16_n_0\ : STD_LOGIC;
  signal \crc_imd[7]_i_17_n_0\ : STD_LOGIC;
  signal \crc_imd[7]_i_25_n_0\ : STD_LOGIC;
  signal \crc_imd[8]_i_10_n_0\ : STD_LOGIC;
  signal \crc_imd[8]_i_11_n_0\ : STD_LOGIC;
  signal \crc_imd[8]_i_12_n_0\ : STD_LOGIC;
  signal \crc_imd[8]_i_13_n_0\ : STD_LOGIC;
  signal \crc_imd[8]_i_16_n_0\ : STD_LOGIC;
  signal \crc_imd[8]_i_17_n_0\ : STD_LOGIC;
  signal \crc_imd[8]_i_19_n_0\ : STD_LOGIC;
  signal \crc_imd[8]_i_4_n_0\ : STD_LOGIC;
  signal \crc_imd[8]_i_5_n_0\ : STD_LOGIC;
  signal \crc_imd[8]_i_9_n_0\ : STD_LOGIC;
  signal \crc_imd[9]_i_12_n_0\ : STD_LOGIC;
  signal \crc_imd[9]_i_13_n_0\ : STD_LOGIC;
  signal \crc_imd[9]_i_15_n_0\ : STD_LOGIC;
  signal \crc_imd[9]_i_16_n_0\ : STD_LOGIC;
  signal \crc_imd[9]_i_17_n_0\ : STD_LOGIC;
  signal \crc_imd[9]_i_18_n_0\ : STD_LOGIC;
  signal \crc_imd[9]_i_3_n_0\ : STD_LOGIC;
  signal \crc_imd[9]_i_4_n_0\ : STD_LOGIC;
  signal \crc_imd[9]_i_5_n_0\ : STD_LOGIC;
  signal \crc_imd[9]_i_8_n_0\ : STD_LOGIC;
  signal i : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \i[0]_i_1__11_n_0\ : STD_LOGIC;
  signal \i[10]_i_1__2_n_0\ : STD_LOGIC;
  signal \i[11]_i_1__1_n_0\ : STD_LOGIC;
  signal \i[12]_i_1__1_n_0\ : STD_LOGIC;
  signal \i[12]_i_2_n_0\ : STD_LOGIC;
  signal \i[13]_i_1__1_n_0\ : STD_LOGIC;
  signal \i[13]_i_2__1_n_0\ : STD_LOGIC;
  signal \i[14]_i_1_n_0\ : STD_LOGIC;
  signal \i[15]_i_1_n_0\ : STD_LOGIC;
  signal \i[15]_i_2_n_0\ : STD_LOGIC;
  signal \i[15]_i_3_n_0\ : STD_LOGIC;
  signal \i[15]_i_4_n_0\ : STD_LOGIC;
  signal \i[15]_i_5_n_0\ : STD_LOGIC;
  signal \i[1]_i_1__10_n_0\ : STD_LOGIC;
  signal \i[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \i[3]_i_1__6_n_0\ : STD_LOGIC;
  signal \i[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \i[5]_i_1__5_n_0\ : STD_LOGIC;
  signal \i[5]_i_2__4_n_0\ : STD_LOGIC;
  signal \i[6]_i_1__5_n_0\ : STD_LOGIC;
  signal \i[7]_i_1__5_n_0\ : STD_LOGIC;
  signal \i[8]_i_1__4_n_0\ : STD_LOGIC;
  signal \i[9]_i_1__3_n_0\ : STD_LOGIC;
  signal \i[9]_i_2__3_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_4_n_0\ : STD_LOGIC;
  signal ixBlkWrite : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \myCrc/crc_imd0132_out\ : STD_LOGIC;
  signal \myCrc/crc_imd0135_out\ : STD_LOGIC;
  signal \myCrc/p_29_out\ : STD_LOGIC_VECTOR ( 9 to 9 );
  signal \myCrc/p_31_out\ : STD_LOGIC_VECTOR ( 8 to 8 );
  signal p_0_in : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal p_1_in0 : STD_LOGIC;
  signal p_33_in : STD_LOGIC;
  signal \recvAXIL_rdata[63]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIL_rdata[63]_i_2_n_0\ : STD_LOGIC;
  signal \recvAXIL_rdata_reg_n_0_[63]\ : STD_LOGIC;
  signal \^recvaxis_tdata\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \recvAXIS_tdata_sig[0]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[10]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[11]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[12]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[13]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[14]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[15]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[16]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[17]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[18]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[19]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[1]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[20]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[21]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[22]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[23]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[24]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[25]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[26]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[27]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[28]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[29]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[2]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[30]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[31]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[32]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[33]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[34]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[35]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[36]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[37]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[38]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[39]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[3]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[40]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[41]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[42]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[43]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[44]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[45]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[46]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[47]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[48]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[49]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[4]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[50]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[51]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[52]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[53]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[54]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[55]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[56]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[57]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[58]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[59]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[5]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[60]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[61]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[62]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[63]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[63]_i_2_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[63]_i_3_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[6]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[7]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[8]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[9]_i_1_n_0\ : STD_LOGIC;
  signal \^recvaxis_tdata_sig_reg[15]_0\ : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \^recvaxis_tlast\ : STD_LOGIC;
  signal recvAXIS_tlast_sig0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_10_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_11_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_12_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_13_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_14_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_15_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_16_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_17_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_18_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_19_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_1_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_20_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_21_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_22_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_23_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_4_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_5_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_6_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_7_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_8_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_i_9_n_0 : STD_LOGIC;
  signal \^recvaxis_tlast_sig_reg_0\ : STD_LOGIC;
  signal recvAXIS_tlast_sig_reg_i_2_n_6 : STD_LOGIC;
  signal recvAXIS_tlast_sig_reg_i_2_n_7 : STD_LOGIC;
  signal recvAXIS_tlast_sig_reg_i_3_n_0 : STD_LOGIC;
  signal recvAXIS_tlast_sig_reg_i_3_n_1 : STD_LOGIC;
  signal recvAXIS_tlast_sig_reg_i_3_n_2 : STD_LOGIC;
  signal recvAXIS_tlast_sig_reg_i_3_n_3 : STD_LOGIC;
  signal recvAXIS_tlast_sig_reg_i_3_n_4 : STD_LOGIC;
  signal recvAXIS_tlast_sig_reg_i_3_n_5 : STD_LOGIC;
  signal recvAXIS_tlast_sig_reg_i_3_n_6 : STD_LOGIC;
  signal recvAXIS_tlast_sig_reg_i_3_n_7 : STD_LOGIC;
  signal recvStrbToStart_i_1_n_0 : STD_LOGIC;
  signal recvStrbToStart_i_2_n_0 : STD_LOGIC;
  signal recvStrbToStart_i_3_n_0 : STD_LOGIC;
  signal recvStrbToStart_reg_n_0 : STD_LOGIC;
  signal recvStrbToStop_i_1_n_0 : STD_LOGIC;
  signal recvStrbToStop_i_2_n_0 : STD_LOGIC;
  signal recvStrbToStop_i_3_n_0 : STD_LOGIC;
  signal recvStrbToStop_reg_n_0 : STD_LOGIC;
  signal req : STD_LOGIC;
  signal \retbuf[0][2]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[10][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[11][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[12][0]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[12][4]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[12][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[13][1]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[13][2]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[13][3]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[13][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[14][1]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[14][4]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[14][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[15][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[16][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[4][0]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[4][3]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[7][6]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[7][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[8][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_3__0_n_0\ : STD_LOGIC;
  signal \retbuf[9][5]_i_2_n_0\ : STD_LOGIC;
  signal rxAXIS_tdata : STD_LOGIC_VECTOR ( 63 downto 1 );
  signal rxlen : STD_LOGIC;
  signal \rxlen[0]_i_4_n_0\ : STD_LOGIC;
  signal sendAXIL_rdata : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \sendAXIL_rdata[0]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[10]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[11]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[12]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[13]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[14]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[15]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[16]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[17]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[18]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[19]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[1]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[20]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[21]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[22]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[23]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[24]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[25]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[26]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[27]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[28]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[29]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[2]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[30]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[31]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[32]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[33]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[34]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[35]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[36]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[37]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[38]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[39]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[3]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[40]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[41]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[42]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[43]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[44]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[45]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[46]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[47]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[48]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[49]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[4]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[50]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[51]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[52]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[53]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[54]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[55]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[56]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[57]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[58]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[59]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[5]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[60]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[61]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[62]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[63]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[63]_i_2_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[63]_i_3_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[63]_i_4_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[63]_i_5_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[6]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[7]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[8]_i_1_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[9]_i_1_n_0\ : STD_LOGIC;
  signal sendStrbToStart0 : STD_LOGIC;
  signal sendStrbToStart_i_10_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_11_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_12_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_13_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_14_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_15_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_16_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_17_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_18_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_19_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_1_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_20_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_21_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_2_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_3_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_4_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_5_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_6_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_7_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_8_n_0 : STD_LOGIC;
  signal sendStrbToStart_i_9_n_0 : STD_LOGIC;
  signal sendStrbToStart_reg_n_0 : STD_LOGIC;
  signal sendStrbToStop_i_1_n_0 : STD_LOGIC;
  signal sendStrbToStop_i_2_n_0 : STD_LOGIC;
  signal sendStrbToStop_i_3_n_0 : STD_LOGIC;
  signal sendStrbToStop_i_4_n_0 : STD_LOGIC;
  signal sendStrbToStop_i_5_n_0 : STD_LOGIC;
  signal sendStrbToStop_reg_n_0 : STD_LOGIC;
  signal \stateOp[0]_i_2_n_0\ : STD_LOGIC;
  signal \stateOp[0]_i_4_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_10_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_4__1_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_9_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_5__1_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_3_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_6_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_7_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_6_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_7_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_18_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_4_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_5_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_6_n_0\ : STD_LOGIC;
  signal \^stateop_reg[0]_0\ : STD_LOGIC;
  signal \^stateop_reg[4]\ : STD_LOGIC;
  signal \^stateop_reg[4]_0\ : STD_LOGIC;
  signal \^stateop_reg[4]_1\ : STD_LOGIC;
  signal \^stateop_reg[4]_11\ : STD_LOGIC;
  signal \^stateop_reg[4]_12\ : STD_LOGIC;
  signal \^stateop_reg[4]_3\ : STD_LOGIC;
  signal \^stateop_reg[4]_4\ : STD_LOGIC;
  signal \^stateop_reg[5]_6\ : STD_LOGIC;
  signal stateRecv : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \stateRecv[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateRecv[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_10_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_12_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_1_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_2_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_3_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_4_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_5_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_6__0_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_7_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_8_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_9__0_n_0\ : STD_LOGIC;
  signal \^staterecv_reg[0]_0\ : STD_LOGIC;
  signal \^staterecv_reg[0]_1\ : STD_LOGIC;
  signal stateSend : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \stateSend[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateSend[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_10_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_11_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_13_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_14_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_15_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_16_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_17_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_18_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_19_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_1_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_20_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_21_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_22_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_23_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_24_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_25_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_26_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_27_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_28_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_29_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_2_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_30_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_31_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_32_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_33_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_34_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_35_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_36_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_37_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_38_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_39_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_3_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_40_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_41_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_42_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_43_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_44_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_45_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_46_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_47_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_48_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_4_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_5_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_6_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_7_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_9_n_0\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12_n_0\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12_n_1\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12_n_2\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12_n_3\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12_n_4\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12_n_5\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12_n_6\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12_n_7\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_8_n_6\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_8_n_7\ : STD_LOGIC;
  signal stateTo : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \stateTo[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateTo[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateTo[1]_i_2_n_0\ : STD_LOGIC;
  signal \stateTo[1]_i_4_n_0\ : STD_LOGIC;
  signal \stateTo[1]_i_5_n_0\ : STD_LOGIC;
  signal \stateTo[1]_i_6_n_0\ : STD_LOGIC;
  signal strbRead : STD_LOGIC;
  signal \^txaxis_tdata_reg[13]\ : STD_LOGIC;
  signal txAXIS_tready : STD_LOGIC;
  signal \wdone_i_1__0_n_0\ : STD_LOGIC;
  signal wdone_reg_n_0 : STD_LOGIC;
  signal wordcnt0 : STD_LOGIC;
  signal \wordcntLast[2]_i_3_n_0\ : STD_LOGIC;
  signal \wordcnt[0]__0_i_1_n_0\ : STD_LOGIC;
  signal \wordcnt[0]__0_i_4_n_0\ : STD_LOGIC;
  signal \wordcnt[0]__0_i_5_n_0\ : STD_LOGIC;
  signal \wordcnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \wordcnt[0]_i_2_n_0\ : STD_LOGIC;
  signal \wordcnt[0]_i_4_n_0\ : STD_LOGIC;
  signal \wordcnt[0]_i_6_n_0\ : STD_LOGIC;
  signal \wordcnt[30]_i_3_n_0\ : STD_LOGIC;
  signal \wordcnt[30]_i_4__0_n_0\ : STD_LOGIC;
  signal \wordcnt[30]_i_5_n_0\ : STD_LOGIC;
  signal wordcnt_reg : STD_LOGIC_VECTOR ( 30 downto 0 );
  signal \wordcnt_reg[0]__0_i_3_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_8\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_8\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[10]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[11]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[12]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[13]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[14]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[15]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_8\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_8\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[17]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[18]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[19]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[1]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[20]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[21]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[22]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[23]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[25]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[26]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[27]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[28]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[29]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[2]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[30]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[3]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[4]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[5]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[6]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[7]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_8\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_8\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[9]__0_n_0\ : STD_LOGIC;
  signal NLW_recvAXIS_tlast_sig_reg_i_2_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal NLW_recvAXIS_tlast_sig_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_recvAXIS_tlast_sig_reg_i_3_O_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateSend_reg[2]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateSend_reg[2]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_stateSend_reg[2]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_wordcnt_reg[24]__0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_wordcnt_reg[24]__0_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_wordcnt_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_wordcnt_reg[24]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of AXIL_rvalid_sig_i_1 : label is "soft_lutpair2133";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[0]_INST_0\ : label is "soft_lutpair2186";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[10]_INST_0\ : label is "soft_lutpair2188";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[11]_INST_0\ : label is "soft_lutpair2183";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[12]_INST_0\ : label is "soft_lutpair2189";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[13]_INST_0\ : label is "soft_lutpair2182";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[14]_INST_0\ : label is "soft_lutpair2189";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[15]_INST_0\ : label is "soft_lutpair2182";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[16]_INST_0\ : label is "soft_lutpair2190";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[17]_INST_0\ : label is "soft_lutpair2181";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[18]_INST_0\ : label is "soft_lutpair2190";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[19]_INST_0\ : label is "soft_lutpair2181";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[1]_INST_0\ : label is "soft_lutpair2185";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[20]_INST_0\ : label is "soft_lutpair2191";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[21]_INST_0\ : label is "soft_lutpair2180";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[22]_INST_0\ : label is "soft_lutpair2191";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[23]_INST_0\ : label is "soft_lutpair2180";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[24]_INST_0\ : label is "soft_lutpair2192";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[25]_INST_0\ : label is "soft_lutpair2179";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[26]_INST_0\ : label is "soft_lutpair2192";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[27]_INST_0\ : label is "soft_lutpair2179";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[28]_INST_0\ : label is "soft_lutpair2193";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[29]_INST_0\ : label is "soft_lutpair2178";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[2]_INST_0\ : label is "soft_lutpair2186";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[30]_INST_0\ : label is "soft_lutpair2193";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[31]_INST_0\ : label is "soft_lutpair2178";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[32]_INST_0\ : label is "soft_lutpair2194";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[33]_INST_0\ : label is "soft_lutpair2177";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[34]_INST_0\ : label is "soft_lutpair2194";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[35]_INST_0\ : label is "soft_lutpair2177";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[36]_INST_0\ : label is "soft_lutpair2195";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[37]_INST_0\ : label is "soft_lutpair2176";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[38]_INST_0\ : label is "soft_lutpair2195";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[39]_INST_0\ : label is "soft_lutpair2176";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[3]_INST_0\ : label is "soft_lutpair2185";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[40]_INST_0\ : label is "soft_lutpair2196";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[41]_INST_0\ : label is "soft_lutpair2175";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[42]_INST_0\ : label is "soft_lutpair2196";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[43]_INST_0\ : label is "soft_lutpair2175";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[44]_INST_0\ : label is "soft_lutpair2197";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[45]_INST_0\ : label is "soft_lutpair2174";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[46]_INST_0\ : label is "soft_lutpair2197";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[47]_INST_0\ : label is "soft_lutpair2174";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[48]_INST_0\ : label is "soft_lutpair2198";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[49]_INST_0\ : label is "soft_lutpair2173";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[4]_INST_0\ : label is "soft_lutpair2187";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[50]_INST_0\ : label is "soft_lutpair2198";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[51]_INST_0\ : label is "soft_lutpair2173";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[52]_INST_0\ : label is "soft_lutpair2199";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[53]_INST_0\ : label is "soft_lutpair2172";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[54]_INST_0\ : label is "soft_lutpair2199";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[55]_INST_0\ : label is "soft_lutpair2172";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[56]_INST_0\ : label is "soft_lutpair2200";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[57]_INST_0\ : label is "soft_lutpair2171";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[58]_INST_0\ : label is "soft_lutpair2200";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[59]_INST_0\ : label is "soft_lutpair2171";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[5]_INST_0\ : label is "soft_lutpair2184";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[60]_INST_0\ : label is "soft_lutpair2201";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[61]_INST_0\ : label is "soft_lutpair2170";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[62]_INST_0\ : label is "soft_lutpair2201";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[63]_INST_0\ : label is "soft_lutpair2170";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[6]_INST_0\ : label is "soft_lutpair2187";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[7]_INST_0\ : label is "soft_lutpair2184";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[8]_INST_0\ : label is "soft_lutpair2188";
  attribute SOFT_HLUTNM of \apuAXIL_rdata[9]_INST_0\ : label is "soft_lutpair2183";
  attribute SOFT_HLUTNM of \crcAXIS_tkeep[5]_i_2\ : label is "soft_lutpair2057";
  attribute SOFT_HLUTNM of crcAXIS_tlast_sig_i_12 : label is "soft_lutpair2000";
  attribute SOFT_HLUTNM of \crc_imd[0]_i_11\ : label is "soft_lutpair2168";
  attribute SOFT_HLUTNM of \crc_imd[0]_i_19\ : label is "soft_lutpair2015";
  attribute SOFT_HLUTNM of \crc_imd[10]_i_15\ : label is "soft_lutpair2018";
  attribute SOFT_HLUTNM of \crc_imd[11]_i_13\ : label is "soft_lutpair2022";
  attribute SOFT_HLUTNM of \crc_imd[11]_i_5\ : label is "soft_lutpair2017";
  attribute SOFT_HLUTNM of \crc_imd[11]_i_8\ : label is "soft_lutpair2166";
  attribute SOFT_HLUTNM of \crc_imd[12]_i_16\ : label is "soft_lutpair2025";
  attribute SOFT_HLUTNM of \crc_imd[12]_i_5\ : label is "soft_lutpair2016";
  attribute SOFT_HLUTNM of \crc_imd[13]_i_18\ : label is "soft_lutpair2022";
  attribute SOFT_HLUTNM of \crc_imd[13]_i_5\ : label is "soft_lutpair2031";
  attribute SOFT_HLUTNM of \crc_imd[13]_i_8\ : label is "soft_lutpair2166";
  attribute SOFT_HLUTNM of \crc_imd[14]_i_3\ : label is "soft_lutpair2014";
  attribute SOFT_HLUTNM of \crc_imd[14]_i_7\ : label is "soft_lutpair2030";
  attribute SOFT_HLUTNM of \crc_imd[14]_i_8\ : label is "soft_lutpair2028";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_18\ : label is "soft_lutpair2167";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_19\ : label is "soft_lutpair2027";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_25\ : label is "soft_lutpair2020";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_27\ : label is "soft_lutpair2167";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_31\ : label is "soft_lutpair2168";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_33\ : label is "soft_lutpair2032";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_38\ : label is "soft_lutpair2019";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_3__0\ : label is "soft_lutpair2012";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_48\ : label is "soft_lutpair2024";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_55\ : label is "soft_lutpair2031";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_65\ : label is "soft_lutpair2029";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_67\ : label is "soft_lutpair2111";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_73\ : label is "soft_lutpair2016";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_79\ : label is "soft_lutpair2019";
  attribute SOFT_HLUTNM of \crc_imd[1]_i_18\ : label is "soft_lutpair2026";
  attribute SOFT_HLUTNM of \crc_imd[1]_i_23\ : label is "soft_lutpair2015";
  attribute SOFT_HLUTNM of \crc_imd[1]_i_24\ : label is "soft_lutpair2021";
  attribute SOFT_HLUTNM of \crc_imd[1]_i_8\ : label is "soft_lutpair2030";
  attribute SOFT_HLUTNM of \crc_imd[1]_i_9\ : label is "soft_lutpair2017";
  attribute SOFT_HLUTNM of \crc_imd[2]_i_7\ : label is "soft_lutpair2024";
  attribute SOFT_HLUTNM of \crc_imd[6]_i_12\ : label is "soft_lutpair2018";
  attribute SOFT_HLUTNM of \crc_imd[6]_i_7\ : label is "soft_lutpair2020";
  attribute SOFT_HLUTNM of \crc_imd[7]_i_13\ : label is "soft_lutpair2026";
  attribute SOFT_HLUTNM of \crc_imd[7]_i_16\ : label is "soft_lutpair2023";
  attribute SOFT_HLUTNM of \crc_imd[7]_i_21\ : label is "soft_lutpair2029";
  attribute SOFT_HLUTNM of \crc_imd[8]_i_12\ : label is "soft_lutpair2025";
  attribute SOFT_HLUTNM of \crc_imd[8]_i_6\ : label is "soft_lutpair2023";
  attribute SOFT_HLUTNM of \crc_imd[8]_i_7\ : label is "soft_lutpair2027";
  attribute SOFT_HLUTNM of \crc_imd[8]_i_8\ : label is "soft_lutpair2021";
  attribute SOFT_HLUTNM of \crc_imd[8]_i_9\ : label is "soft_lutpair2111";
  attribute SOFT_HLUTNM of \crc_imd[9]_i_12\ : label is "soft_lutpair2028";
  attribute SOFT_HLUTNM of \crc_imd[9]_i_19\ : label is "soft_lutpair2032";
  attribute SOFT_HLUTNM of \i[0]_i_1__11\ : label is "soft_lutpair2129";
  attribute SOFT_HLUTNM of \i[10]_i_1__2\ : label is "soft_lutpair2046";
  attribute SOFT_HLUTNM of \i[11]_i_1__1\ : label is "soft_lutpair2046";
  attribute SOFT_HLUTNM of \i[12]_i_2\ : label is "soft_lutpair2132";
  attribute SOFT_HLUTNM of \i[13]_i_1__1\ : label is "soft_lutpair2129";
  attribute SOFT_HLUTNM of \i[14]_i_1\ : label is "soft_lutpair2130";
  attribute SOFT_HLUTNM of \i[15]_i_2\ : label is "soft_lutpair2130";
  attribute SOFT_HLUTNM of \i[15]_i_3\ : label is "soft_lutpair2131";
  attribute SOFT_HLUTNM of \i[15]_i_5\ : label is "soft_lutpair2131";
  attribute SOFT_HLUTNM of \i[1]_i_1__10\ : label is "soft_lutpair2169";
  attribute SOFT_HLUTNM of \i[2]_i_1__6\ : label is "soft_lutpair2044";
  attribute SOFT_HLUTNM of \i[3]_i_1__6\ : label is "soft_lutpair2044";
  attribute SOFT_HLUTNM of \i[5]_i_1__5\ : label is "soft_lutpair2169";
  attribute SOFT_HLUTNM of \i[6]_i_1__5\ : label is "soft_lutpair2132";
  attribute SOFT_HLUTNM of \i[7]_i_1__5\ : label is "soft_lutpair2045";
  attribute SOFT_HLUTNM of \i[8]_i_1__4\ : label is "soft_lutpair2045";
  attribute SOFT_HLUTNM of \invbuf[7][0]_i_1\ : label is "soft_lutpair2052";
  attribute SOFT_HLUTNM of \invbuf[7][1]_i_1\ : label is "soft_lutpair2054";
  attribute SOFT_HLUTNM of \invbuf[7][2]_i_1\ : label is "soft_lutpair2051";
  attribute SOFT_HLUTNM of \invbuf[7][3]_i_1\ : label is "soft_lutpair2050";
  attribute SOFT_HLUTNM of \invbuf[7][4]_i_1\ : label is "soft_lutpair2049";
  attribute SOFT_HLUTNM of \invbuf[7][5]_i_1\ : label is "soft_lutpair2048";
  attribute SOFT_HLUTNM of \invbuf[7][6]_i_1\ : label is "soft_lutpair2053";
  attribute SOFT_HLUTNM of \invbuf[7][7]_i_1\ : label is "soft_lutpair2047";
  attribute SOFT_HLUTNM of \invbuf[9][5]_i_1\ : label is "soft_lutpair2007";
  attribute SOFT_HLUTNM of \invbuf[9][6]_i_1\ : label is "soft_lutpair2008";
  attribute SOFT_HLUTNM of \invbuf[9][7]_i_2\ : label is "soft_lutpair2009";
  attribute SOFT_HLUTNM of \ixRetbufCrc[0]_i_1\ : label is "soft_lutpair2003";
  attribute SOFT_HLUTNM of \ixRetbufCrc[1]_i_1\ : label is "soft_lutpair2088";
  attribute SOFT_HLUTNM of \ixRetbufCrc[2]_i_1\ : label is "soft_lutpair2002";
  attribute SOFT_HLUTNM of \ixRetbufCrc[3]_i_1\ : label is "soft_lutpair2056";
  attribute SOFT_HLUTNM of \ixRetbufCrc[4]_i_1\ : label is "soft_lutpair2074";
  attribute SOFT_HLUTNM of \ixRetbufCrc[5]_i_1\ : label is "soft_lutpair2001";
  attribute SOFT_HLUTNM of \ixRetbufCrc[5]_i_2\ : label is "soft_lutpair2056";
  attribute SOFT_HLUTNM of \lastAXIS_tkeep[1]_i_1\ : label is "soft_lutpair2001";
  attribute SOFT_HLUTNM of \lastAXIS_tkeep[2]_i_1__0\ : label is "soft_lutpair2002";
  attribute SOFT_HLUTNM of \lastAXIS_tkeep[7]_i_1\ : label is "soft_lutpair2003";
  attribute SOFT_HLUTNM of \len[0]_i_1\ : label is "soft_lutpair2202";
  attribute SOFT_HLUTNM of \len[10]_i_1\ : label is "soft_lutpair2207";
  attribute SOFT_HLUTNM of \len[11]_i_1\ : label is "soft_lutpair2207";
  attribute SOFT_HLUTNM of \len[12]_i_1\ : label is "soft_lutpair2208";
  attribute SOFT_HLUTNM of \len[13]_i_1\ : label is "soft_lutpair2208";
  attribute SOFT_HLUTNM of \len[14]_i_1\ : label is "soft_lutpair2209";
  attribute SOFT_HLUTNM of \len[15]_i_1\ : label is "soft_lutpair2209";
  attribute SOFT_HLUTNM of \len[16]_i_1\ : label is "soft_lutpair2210";
  attribute SOFT_HLUTNM of \len[17]_i_1\ : label is "soft_lutpair2210";
  attribute SOFT_HLUTNM of \len[18]_i_1\ : label is "soft_lutpair2211";
  attribute SOFT_HLUTNM of \len[19]_i_1\ : label is "soft_lutpair2211";
  attribute SOFT_HLUTNM of \len[1]_i_1\ : label is "soft_lutpair2202";
  attribute SOFT_HLUTNM of \len[20]_i_1\ : label is "soft_lutpair2212";
  attribute SOFT_HLUTNM of \len[21]_i_1\ : label is "soft_lutpair2212";
  attribute SOFT_HLUTNM of \len[22]_i_1\ : label is "soft_lutpair2213";
  attribute SOFT_HLUTNM of \len[23]_i_1\ : label is "soft_lutpair2213";
  attribute SOFT_HLUTNM of \len[24]_i_1\ : label is "soft_lutpair2214";
  attribute SOFT_HLUTNM of \len[25]_i_1\ : label is "soft_lutpair2214";
  attribute SOFT_HLUTNM of \len[26]_i_1\ : label is "soft_lutpair2215";
  attribute SOFT_HLUTNM of \len[27]_i_1\ : label is "soft_lutpair2215";
  attribute SOFT_HLUTNM of \len[28]_i_1\ : label is "soft_lutpair2216";
  attribute SOFT_HLUTNM of \len[29]_i_1\ : label is "soft_lutpair2216";
  attribute SOFT_HLUTNM of \len[2]_i_1\ : label is "soft_lutpair2203";
  attribute SOFT_HLUTNM of \len[30]_i_1\ : label is "soft_lutpair2217";
  attribute SOFT_HLUTNM of \len[31]_i_1\ : label is "soft_lutpair2217";
  attribute SOFT_HLUTNM of \len[3]_i_1\ : label is "soft_lutpair2203";
  attribute SOFT_HLUTNM of \len[4]_i_1\ : label is "soft_lutpair2204";
  attribute SOFT_HLUTNM of \len[5]_i_1\ : label is "soft_lutpair2204";
  attribute SOFT_HLUTNM of \len[6]_i_1\ : label is "soft_lutpair2205";
  attribute SOFT_HLUTNM of \len[7]_i_1\ : label is "soft_lutpair2205";
  attribute SOFT_HLUTNM of \len[8]_i_1\ : label is "soft_lutpair2206";
  attribute SOFT_HLUTNM of \len[9]_i_1\ : label is "soft_lutpair2206";
  attribute SOFT_HLUTNM of \opbuf[0][0]_i_1\ : label is "soft_lutpair2105";
  attribute SOFT_HLUTNM of \opbuf[0][1]_i_1\ : label is "soft_lutpair2108";
  attribute SOFT_HLUTNM of \opbuf[0][2]_i_1\ : label is "soft_lutpair2106";
  attribute SOFT_HLUTNM of \opbuf[0][3]_i_1\ : label is "soft_lutpair2109";
  attribute SOFT_HLUTNM of \opbuf[0][4]_i_1\ : label is "soft_lutpair2110";
  attribute SOFT_HLUTNM of \opbuf[0][5]_i_1\ : label is "soft_lutpair2007";
  attribute SOFT_HLUTNM of \opbuf[0][6]_i_1\ : label is "soft_lutpair2008";
  attribute SOFT_HLUTNM of \opbuf[0][7]_i_2\ : label is "soft_lutpair2009";
  attribute SOFT_HLUTNM of \opbuf[1][0]_i_1\ : label is "soft_lutpair2091";
  attribute SOFT_HLUTNM of \opbuf[1][1]_i_1\ : label is "soft_lutpair2093";
  attribute SOFT_HLUTNM of \opbuf[1][2]_i_1\ : label is "soft_lutpair2095";
  attribute SOFT_HLUTNM of \opbuf[1][3]_i_1\ : label is "soft_lutpair2097";
  attribute SOFT_HLUTNM of \opbuf[1][4]_i_1\ : label is "soft_lutpair2099";
  attribute SOFT_HLUTNM of \opbuf[1][5]_i_1\ : label is "soft_lutpair2101";
  attribute SOFT_HLUTNM of \opbuf[1][6]_i_1\ : label is "soft_lutpair2103";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_1\ : label is "soft_lutpair2105";
  attribute SOFT_HLUTNM of \opbuf[2][0]_i_1\ : label is "soft_lutpair2090";
  attribute SOFT_HLUTNM of \opbuf[2][1]_i_1\ : label is "soft_lutpair2092";
  attribute SOFT_HLUTNM of \opbuf[2][2]_i_1\ : label is "soft_lutpair2094";
  attribute SOFT_HLUTNM of \opbuf[2][3]_i_1\ : label is "soft_lutpair2096";
  attribute SOFT_HLUTNM of \opbuf[2][4]_i_1\ : label is "soft_lutpair2098";
  attribute SOFT_HLUTNM of \opbuf[2][5]_i_1\ : label is "soft_lutpair2100";
  attribute SOFT_HLUTNM of \opbuf[2][6]_i_1\ : label is "soft_lutpair2102";
  attribute SOFT_HLUTNM of \opbuf[2][7]_i_1\ : label is "soft_lutpair2089";
  attribute SOFT_HLUTNM of \opbuf[3][0]_i_1\ : label is "soft_lutpair2052";
  attribute SOFT_HLUTNM of \opbuf[3][1]_i_1\ : label is "soft_lutpair2054";
  attribute SOFT_HLUTNM of \opbuf[3][2]_i_1\ : label is "soft_lutpair2051";
  attribute SOFT_HLUTNM of \opbuf[3][3]_i_1\ : label is "soft_lutpair2050";
  attribute SOFT_HLUTNM of \opbuf[3][4]_i_1\ : label is "soft_lutpair2049";
  attribute SOFT_HLUTNM of \opbuf[3][5]_i_1\ : label is "soft_lutpair2048";
  attribute SOFT_HLUTNM of \opbuf[3][6]_i_1\ : label is "soft_lutpair2053";
  attribute SOFT_HLUTNM of \opbuf[3][7]_i_1\ : label is "soft_lutpair2047";
  attribute SOFT_HLUTNM of \opbuf[4][0]_i_1\ : label is "soft_lutpair2090";
  attribute SOFT_HLUTNM of \opbuf[4][1]_i_1\ : label is "soft_lutpair2092";
  attribute SOFT_HLUTNM of \opbuf[4][2]_i_1\ : label is "soft_lutpair2094";
  attribute SOFT_HLUTNM of \opbuf[4][3]_i_1\ : label is "soft_lutpair2096";
  attribute SOFT_HLUTNM of \opbuf[4][4]_i_1\ : label is "soft_lutpair2098";
  attribute SOFT_HLUTNM of \opbuf[4][5]_i_1\ : label is "soft_lutpair2100";
  attribute SOFT_HLUTNM of \opbuf[4][6]_i_1\ : label is "soft_lutpair2102";
  attribute SOFT_HLUTNM of \opbuf[4][7]_i_1\ : label is "soft_lutpair2104";
  attribute SOFT_HLUTNM of \opbuf[5][4]_i_1\ : label is "soft_lutpair2110";
  attribute SOFT_HLUTNM of \opbuf[5][5]_i_1\ : label is "soft_lutpair2109";
  attribute SOFT_HLUTNM of \opbuf[5][6]_i_1\ : label is "soft_lutpair2108";
  attribute SOFT_HLUTNM of \opbuf[5][7]_i_1\ : label is "soft_lutpair2089";
  attribute SOFT_HLUTNM of \opbuf[6][0]_i_1\ : label is "soft_lutpair2091";
  attribute SOFT_HLUTNM of \opbuf[6][1]_i_1\ : label is "soft_lutpair2093";
  attribute SOFT_HLUTNM of \opbuf[6][2]_i_1\ : label is "soft_lutpair2095";
  attribute SOFT_HLUTNM of \opbuf[6][3]_i_1\ : label is "soft_lutpair2097";
  attribute SOFT_HLUTNM of \opbuf[6][4]_i_1\ : label is "soft_lutpair2099";
  attribute SOFT_HLUTNM of \opbuf[6][5]_i_1\ : label is "soft_lutpair2101";
  attribute SOFT_HLUTNM of \opbuf[6][6]_i_1\ : label is "soft_lutpair2103";
  attribute SOFT_HLUTNM of \opbuf[6][7]_i_1\ : label is "soft_lutpair2104";
  attribute SOFT_HLUTNM of \pollbuf[0][0]_i_1\ : label is "soft_lutpair2062";
  attribute SOFT_HLUTNM of \pollbuf[0][1]_i_1\ : label is "soft_lutpair2062";
  attribute SOFT_HLUTNM of \pollbuf[0][2]_i_1\ : label is "soft_lutpair2061";
  attribute SOFT_HLUTNM of \pollbuf[0][3]_i_1\ : label is "soft_lutpair2061";
  attribute SOFT_HLUTNM of \pollbuf[0][4]_i_1\ : label is "soft_lutpair2060";
  attribute SOFT_HLUTNM of \pollbuf[0][5]_i_1\ : label is "soft_lutpair2060";
  attribute SOFT_HLUTNM of \pollbuf[0][6]_i_1\ : label is "soft_lutpair2059";
  attribute SOFT_HLUTNM of \pollbuf[0][7]_i_2\ : label is "soft_lutpair2059";
  attribute SOFT_HLUTNM of \pollbuf[1][0]_i_1\ : label is "soft_lutpair2066";
  attribute SOFT_HLUTNM of \pollbuf[1][1]_i_1\ : label is "soft_lutpair2066";
  attribute SOFT_HLUTNM of \pollbuf[1][2]_i_1\ : label is "soft_lutpair2065";
  attribute SOFT_HLUTNM of \pollbuf[1][3]_i_1\ : label is "soft_lutpair2065";
  attribute SOFT_HLUTNM of \pollbuf[1][4]_i_1\ : label is "soft_lutpair2064";
  attribute SOFT_HLUTNM of \pollbuf[1][5]_i_1\ : label is "soft_lutpair2064";
  attribute SOFT_HLUTNM of \pollbuf[1][6]_i_1\ : label is "soft_lutpair2063";
  attribute SOFT_HLUTNM of \pollbuf[1][7]_i_1\ : label is "soft_lutpair2063";
  attribute SOFT_HLUTNM of \pollbuf[2][3]_i_1\ : label is "soft_lutpair2151";
  attribute SOFT_HLUTNM of \pollbuf[2][4]_i_1\ : label is "soft_lutpair2075";
  attribute SOFT_HLUTNM of \pollbuf[2][7]_i_1\ : label is "soft_lutpair2152";
  attribute SOFT_HLUTNM of \pollbuf[3][0]_i_1\ : label is "soft_lutpair2134";
  attribute SOFT_HLUTNM of \pollbuf[3][1]_i_1\ : label is "soft_lutpair2151";
  attribute SOFT_HLUTNM of \pollbuf[3][2]_i_1\ : label is "soft_lutpair2134";
  attribute SOFT_HLUTNM of \pollbuf[3][3]_i_1\ : label is "soft_lutpair2005";
  attribute SOFT_HLUTNM of \pollbuf[3][4]_i_1\ : label is "soft_lutpair2150";
  attribute SOFT_HLUTNM of \pollbuf[3][5]_i_1\ : label is "soft_lutpair2005";
  attribute SOFT_HLUTNM of \recvAXIL_rdata[63]_i_2\ : label is "soft_lutpair2120";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[10]_i_1\ : label is "soft_lutpair2248";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[11]_i_1\ : label is "soft_lutpair2247";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[12]_i_1\ : label is "soft_lutpair2247";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[13]_i_1\ : label is "soft_lutpair2246";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[14]_i_1\ : label is "soft_lutpair2114";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[15]_i_1\ : label is "soft_lutpair2118";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[16]_i_1\ : label is "soft_lutpair2246";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[17]_i_1\ : label is "soft_lutpair2245";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[18]_i_1\ : label is "soft_lutpair2245";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[19]_i_1\ : label is "soft_lutpair2244";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[1]_i_1\ : label is "soft_lutpair2251";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[20]_i_1\ : label is "soft_lutpair2244";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[21]_i_1\ : label is "soft_lutpair2123";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[22]_i_1\ : label is "soft_lutpair2243";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[23]_i_1\ : label is "soft_lutpair2243";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[24]_i_1\ : label is "soft_lutpair2242";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[25]_i_1\ : label is "soft_lutpair2117";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[26]_i_1\ : label is "soft_lutpair2242";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[27]_i_1\ : label is "soft_lutpair2128";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[28]_i_1\ : label is "soft_lutpair2241";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[29]_i_1\ : label is "soft_lutpair2121";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[2]_i_1\ : label is "soft_lutpair2251";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[30]_i_1\ : label is "soft_lutpair2241";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[31]_i_1\ : label is "soft_lutpair2116";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[32]_i_1\ : label is "soft_lutpair2240";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[33]_i_1\ : label is "soft_lutpair2240";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[34]_i_1\ : label is "soft_lutpair2239";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[35]_i_1\ : label is "soft_lutpair2239";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[36]_i_1\ : label is "soft_lutpair2238";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[37]_i_1\ : label is "soft_lutpair2238";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[38]_i_1\ : label is "soft_lutpair2112";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[39]_i_1\ : label is "soft_lutpair2122";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[3]_i_1\ : label is "soft_lutpair2127";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[40]_i_1\ : label is "soft_lutpair2115";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[41]_i_1\ : label is "soft_lutpair2125";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[42]_i_1\ : label is "soft_lutpair2237";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[43]_i_1\ : label is "soft_lutpair2237";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[44]_i_1\ : label is "soft_lutpair2236";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[45]_i_1\ : label is "soft_lutpair2236";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[46]_i_1\ : label is "soft_lutpair2235";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[47]_i_1\ : label is "soft_lutpair2235";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[48]_i_1\ : label is "soft_lutpair2234";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[49]_i_1\ : label is "soft_lutpair2234";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[4]_i_1\ : label is "soft_lutpair2250";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[50]_i_1\ : label is "soft_lutpair2233";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[51]_i_1\ : label is "soft_lutpair2233";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[52]_i_1\ : label is "soft_lutpair2232";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[53]_i_1\ : label is "soft_lutpair2232";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[54]_i_1\ : label is "soft_lutpair2231";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[55]_i_1\ : label is "soft_lutpair2231";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[56]_i_1\ : label is "soft_lutpair2230";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[57]_i_1\ : label is "soft_lutpair2230";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[58]_i_1\ : label is "soft_lutpair2229";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[59]_i_1\ : label is "soft_lutpair2126";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[5]_i_1\ : label is "soft_lutpair2124";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[60]_i_1\ : label is "soft_lutpair2113";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[61]_i_1\ : label is "soft_lutpair2229";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[62]_i_1\ : label is "soft_lutpair2119";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[63]_i_2\ : label is "soft_lutpair2058";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[6]_i_1\ : label is "soft_lutpair2250";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[7]_i_1\ : label is "soft_lutpair2249";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[8]_i_1\ : label is "soft_lutpair2249";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[9]_i_1\ : label is "soft_lutpair2248";
  attribute SOFT_HLUTNM of recvStrbToStart_i_2 : label is "soft_lutpair2035";
  attribute SOFT_HLUTNM of recvStrbToStart_i_3 : label is "soft_lutpair2034";
  attribute SOFT_HLUTNM of recvStrbToStop_i_3 : label is "soft_lutpair2058";
  attribute SOFT_HLUTNM of \resid[0]_i_1\ : label is "soft_lutpair2088";
  attribute SOFT_HLUTNM of \resid[2]_i_1\ : label is "soft_lutpair2057";
  attribute SOFT_HLUTNM of \retbuf[10][5]_i_2\ : label is "soft_lutpair2073";
  attribute SOFT_HLUTNM of \retbuf[11][5]_i_2\ : label is "soft_lutpair2072";
  attribute SOFT_HLUTNM of \retbuf[12][0]_i_2\ : label is "soft_lutpair2071";
  attribute SOFT_HLUTNM of \retbuf[12][4]_i_2\ : label is "soft_lutpair2071";
  attribute SOFT_HLUTNM of \retbuf[12][5]_i_2\ : label is "soft_lutpair2072";
  attribute SOFT_HLUTNM of \retbuf[13][1]_i_2\ : label is "soft_lutpair2069";
  attribute SOFT_HLUTNM of \retbuf[13][2]_i_2\ : label is "soft_lutpair2069";
  attribute SOFT_HLUTNM of \retbuf[13][3]_i_2\ : label is "soft_lutpair2070";
  attribute SOFT_HLUTNM of \retbuf[13][5]_i_2\ : label is "soft_lutpair2070";
  attribute SOFT_HLUTNM of \retbuf[14][1]_i_2\ : label is "soft_lutpair2067";
  attribute SOFT_HLUTNM of \retbuf[14][4]_i_2\ : label is "soft_lutpair2068";
  attribute SOFT_HLUTNM of \retbuf[14][5]_i_2\ : label is "soft_lutpair2068";
  attribute SOFT_HLUTNM of \retbuf[15][5]_i_2\ : label is "soft_lutpair2067";
  attribute SOFT_HLUTNM of \retbuf[1][7]_i_9\ : label is "soft_lutpair2006";
  attribute SOFT_HLUTNM of \retbuf[7][7]_i_5\ : label is "soft_lutpair2006";
  attribute SOFT_HLUTNM of \retbuf[8][5]_i_2\ : label is "soft_lutpair2074";
  attribute SOFT_HLUTNM of \retbuf[9][5]_i_2\ : label is "soft_lutpair2073";
  attribute SOFT_HLUTNM of \sendAXIL_rdata[0]_i_1\ : label is "soft_lutpair2036";
  attribute SOFT_HLUTNM of \sendAXIL_rdata[1]_i_1\ : label is "soft_lutpair2037";
  attribute SOFT_HLUTNM of \sendAXIL_rdata[2]_i_1\ : label is "soft_lutpair2038";
  attribute SOFT_HLUTNM of \sendAXIL_rdata[3]_i_1\ : label is "soft_lutpair2039";
  attribute SOFT_HLUTNM of \sendAXIL_rdata[4]_i_1\ : label is "soft_lutpair2040";
  attribute SOFT_HLUTNM of \sendAXIL_rdata[5]_i_1\ : label is "soft_lutpair2041";
  attribute SOFT_HLUTNM of \sendAXIL_rdata[6]_i_1\ : label is "soft_lutpair2042";
  attribute SOFT_HLUTNM of sendStrbToStart_i_10 : label is "soft_lutpair2126";
  attribute SOFT_HLUTNM of sendStrbToStart_i_12 : label is "soft_lutpair2128";
  attribute SOFT_HLUTNM of sendStrbToStart_i_14 : label is "soft_lutpair2122";
  attribute SOFT_HLUTNM of sendStrbToStart_i_16 : label is "soft_lutpair2124";
  attribute SOFT_HLUTNM of sendStrbToStart_i_18 : label is "soft_lutpair2125";
  attribute SOFT_HLUTNM of sendStrbToStart_i_19 : label is "soft_lutpair2127";
  attribute SOFT_HLUTNM of sendStrbToStart_i_20 : label is "soft_lutpair2121";
  attribute SOFT_HLUTNM of sendStrbToStart_i_21 : label is "soft_lutpair2123";
  attribute SOFT_HLUTNM of sendStrbToStart_i_4 : label is "soft_lutpair2107";
  attribute SOFT_HLUTNM of sendStrbToStop_i_4 : label is "soft_lutpair2040";
  attribute SOFT_HLUTNM of \stateOp[1]_i_10\ : label is "soft_lutpair2041";
  attribute SOFT_HLUTNM of \stateOp[1]_i_5\ : label is "soft_lutpair2038";
  attribute SOFT_HLUTNM of \stateOp[1]_i_9\ : label is "soft_lutpair2039";
  attribute SOFT_HLUTNM of \stateOp[3]_i_2\ : label is "soft_lutpair2010";
  attribute SOFT_HLUTNM of \stateOp[4]_i_7\ : label is "soft_lutpair2106";
  attribute SOFT_HLUTNM of \stateOp[5]_i_18\ : label is "soft_lutpair2107";
  attribute SOFT_HLUTNM of \stateOp_i_1__1\ : label is "soft_lutpair2014";
  attribute SOFT_HLUTNM of \stateOp_next[1]_i_1\ : label is "soft_lutpair2011";
  attribute SOFT_HLUTNM of \stateOp_next[3]_i_1\ : label is "soft_lutpair2011";
  attribute SOFT_HLUTNM of \stateOp_next[4]_i_1\ : label is "soft_lutpair2004";
  attribute SOFT_HLUTNM of \stateOp_next[5]_i_2\ : label is "soft_lutpair2004";
  attribute SOFT_HLUTNM of \stateRecv[2]_i_12\ : label is "soft_lutpair2033";
  attribute SOFT_HLUTNM of \stateRecv[2]_i_3\ : label is "soft_lutpair2034";
  attribute SOFT_HLUTNM of \stateRecv[2]_i_5\ : label is "soft_lutpair2035";
  attribute SOFT_HLUTNM of \stateRecv[2]_i_8\ : label is "soft_lutpair2013";
  attribute SOFT_HLUTNM of \stateSend[2]_i_29\ : label is "soft_lutpair2117";
  attribute SOFT_HLUTNM of \stateSend[2]_i_3\ : label is "soft_lutpair2120";
  attribute SOFT_HLUTNM of \stateSend[2]_i_31\ : label is "soft_lutpair2119";
  attribute SOFT_HLUTNM of \stateSend[2]_i_33\ : label is "soft_lutpair2113";
  attribute SOFT_HLUTNM of \stateSend[2]_i_35\ : label is "soft_lutpair2115";
  attribute SOFT_HLUTNM of \stateSend[2]_i_4\ : label is "soft_lutpair2037";
  attribute SOFT_HLUTNM of \stateSend[2]_i_45\ : label is "soft_lutpair2116";
  attribute SOFT_HLUTNM of \stateSend[2]_i_46\ : label is "soft_lutpair2118";
  attribute SOFT_HLUTNM of \stateSend[2]_i_47\ : label is "soft_lutpair2112";
  attribute SOFT_HLUTNM of \stateSend[2]_i_48\ : label is "soft_lutpair2114";
  attribute SOFT_HLUTNM of \stateSend[2]_i_5\ : label is "soft_lutpair2033";
  attribute SOFT_HLUTNM of \stateSend[2]_i_6\ : label is "soft_lutpair2042";
  attribute SOFT_HLUTNM of \stateTo[0]_i_1\ : label is "soft_lutpair2043";
  attribute SOFT_HLUTNM of \stateTo[1]_i_2\ : label is "soft_lutpair2043";
  attribute SOFT_HLUTNM of \tixVBuffer[0]_i_1\ : label is "soft_lutpair2221";
  attribute SOFT_HLUTNM of \tixVBuffer[1]_i_1\ : label is "soft_lutpair2221";
  attribute SOFT_HLUTNM of \tixVBuffer[2]_i_1\ : label is "soft_lutpair2222";
  attribute SOFT_HLUTNM of \tixVBuffer[3]_i_1\ : label is "soft_lutpair2222";
  attribute SOFT_HLUTNM of \tixVBuffer[4]_i_1\ : label is "soft_lutpair2223";
  attribute SOFT_HLUTNM of \tixVBuffer[5]_i_1\ : label is "soft_lutpair2223";
  attribute SOFT_HLUTNM of \tixVBuffer[6]_i_1\ : label is "soft_lutpair2224";
  attribute SOFT_HLUTNM of \tixVBuffer[7]_i_2\ : label is "soft_lutpair2224";
  attribute SOFT_HLUTNM of \tixVCommand[0]_i_1\ : label is "soft_lutpair2228";
  attribute SOFT_HLUTNM of \tixVCommand[1]_i_1\ : label is "soft_lutpair2225";
  attribute SOFT_HLUTNM of \tixVCommand[2]_i_1\ : label is "soft_lutpair2225";
  attribute SOFT_HLUTNM of \tixVCommand[3]_i_1\ : label is "soft_lutpair2226";
  attribute SOFT_HLUTNM of \tixVCommand[4]_i_1\ : label is "soft_lutpair2226";
  attribute SOFT_HLUTNM of \tixVCommand[5]_i_1\ : label is "soft_lutpair2227";
  attribute SOFT_HLUTNM of \tixVCommand[6]_i_1\ : label is "soft_lutpair2227";
  attribute SOFT_HLUTNM of \tixVCommand[7]_i_1\ : label is "soft_lutpair2228";
  attribute SOFT_HLUTNM of \tixVController[0]_i_1\ : label is "soft_lutpair2087";
  attribute SOFT_HLUTNM of \tixVController[1]_i_1\ : label is "soft_lutpair2152";
  attribute SOFT_HLUTNM of \tixVController[2]_i_1\ : label is "soft_lutpair2218";
  attribute SOFT_HLUTNM of \tixVController[3]_i_1\ : label is "soft_lutpair2218";
  attribute SOFT_HLUTNM of \tixVController[4]_i_1\ : label is "soft_lutpair2219";
  attribute SOFT_HLUTNM of \tixVController[5]_i_1\ : label is "soft_lutpair2219";
  attribute SOFT_HLUTNM of \tixVController[6]_i_1\ : label is "soft_lutpair2220";
  attribute SOFT_HLUTNM of \tixVController[7]_i_2\ : label is "soft_lutpair2220";
  attribute SOFT_HLUTNM of \txAXIS_tdata[31]_i_1__0\ : label is "soft_lutpair2055";
  attribute SOFT_HLUTNM of \txAXIS_tdata[32]_i_1\ : label is "soft_lutpair2010";
  attribute SOFT_HLUTNM of \txAXIS_tdata[47]_i_1\ : label is "soft_lutpair2055";
  attribute SOFT_HLUTNM of validCrc_sig_i_2 : label is "soft_lutpair2012";
  attribute SOFT_HLUTNM of \wordcntCrcLast[0]_i_1\ : label is "soft_lutpair2075";
  attribute SOFT_HLUTNM of \wordcntCrcLast[10]_i_1\ : label is "soft_lutpair2080";
  attribute SOFT_HLUTNM of \wordcntCrcLast[11]_i_1\ : label is "soft_lutpair2080";
  attribute SOFT_HLUTNM of \wordcntCrcLast[12]_i_1\ : label is "soft_lutpair2081";
  attribute SOFT_HLUTNM of \wordcntCrcLast[13]_i_1\ : label is "soft_lutpair2081";
  attribute SOFT_HLUTNM of \wordcntCrcLast[14]_i_1\ : label is "soft_lutpair2082";
  attribute SOFT_HLUTNM of \wordcntCrcLast[15]_i_1\ : label is "soft_lutpair2082";
  attribute SOFT_HLUTNM of \wordcntCrcLast[16]_i_1\ : label is "soft_lutpair2083";
  attribute SOFT_HLUTNM of \wordcntCrcLast[17]_i_1\ : label is "soft_lutpair2083";
  attribute SOFT_HLUTNM of \wordcntCrcLast[18]_i_1\ : label is "soft_lutpair2084";
  attribute SOFT_HLUTNM of \wordcntCrcLast[19]_i_1\ : label is "soft_lutpair2084";
  attribute SOFT_HLUTNM of \wordcntCrcLast[1]_i_1\ : label is "soft_lutpair2076";
  attribute SOFT_HLUTNM of \wordcntCrcLast[20]_i_1\ : label is "soft_lutpair2085";
  attribute SOFT_HLUTNM of \wordcntCrcLast[21]_i_1\ : label is "soft_lutpair2085";
  attribute SOFT_HLUTNM of \wordcntCrcLast[22]_i_1\ : label is "soft_lutpair2086";
  attribute SOFT_HLUTNM of \wordcntCrcLast[23]_i_1\ : label is "soft_lutpair2086";
  attribute SOFT_HLUTNM of \wordcntCrcLast[24]_i_2\ : label is "soft_lutpair2087";
  attribute SOFT_HLUTNM of \wordcntCrcLast[3]_i_1\ : label is "soft_lutpair2076";
  attribute SOFT_HLUTNM of \wordcntCrcLast[4]_i_1\ : label is "soft_lutpair2077";
  attribute SOFT_HLUTNM of \wordcntCrcLast[5]_i_1\ : label is "soft_lutpair2077";
  attribute SOFT_HLUTNM of \wordcntCrcLast[6]_i_1\ : label is "soft_lutpair2078";
  attribute SOFT_HLUTNM of \wordcntCrcLast[7]_i_1\ : label is "soft_lutpair2078";
  attribute SOFT_HLUTNM of \wordcntCrcLast[8]_i_1\ : label is "soft_lutpair2079";
  attribute SOFT_HLUTNM of \wordcntCrcLast[9]_i_1\ : label is "soft_lutpair2079";
  attribute SOFT_HLUTNM of \wordcntLast[10]_i_1\ : label is "soft_lutpair2156";
  attribute SOFT_HLUTNM of \wordcntLast[11]_i_1\ : label is "soft_lutpair2157";
  attribute SOFT_HLUTNM of \wordcntLast[12]_i_1\ : label is "soft_lutpair2157";
  attribute SOFT_HLUTNM of \wordcntLast[13]_i_1\ : label is "soft_lutpair2158";
  attribute SOFT_HLUTNM of \wordcntLast[14]_i_1\ : label is "soft_lutpair2158";
  attribute SOFT_HLUTNM of \wordcntLast[15]_i_1\ : label is "soft_lutpair2159";
  attribute SOFT_HLUTNM of \wordcntLast[16]_i_1\ : label is "soft_lutpair2159";
  attribute SOFT_HLUTNM of \wordcntLast[17]_i_1\ : label is "soft_lutpair2160";
  attribute SOFT_HLUTNM of \wordcntLast[18]_i_1\ : label is "soft_lutpair2160";
  attribute SOFT_HLUTNM of \wordcntLast[19]_i_1\ : label is "soft_lutpair2161";
  attribute SOFT_HLUTNM of \wordcntLast[20]_i_1\ : label is "soft_lutpair2161";
  attribute SOFT_HLUTNM of \wordcntLast[21]_i_1\ : label is "soft_lutpair2162";
  attribute SOFT_HLUTNM of \wordcntLast[22]_i_1\ : label is "soft_lutpair2162";
  attribute SOFT_HLUTNM of \wordcntLast[23]_i_1\ : label is "soft_lutpair2163";
  attribute SOFT_HLUTNM of \wordcntLast[24]_i_1\ : label is "soft_lutpair2163";
  attribute SOFT_HLUTNM of \wordcntLast[25]_i_1\ : label is "soft_lutpair2164";
  attribute SOFT_HLUTNM of \wordcntLast[26]_i_1\ : label is "soft_lutpair2164";
  attribute SOFT_HLUTNM of \wordcntLast[27]_i_1\ : label is "soft_lutpair2165";
  attribute SOFT_HLUTNM of \wordcntLast[28]_i_2\ : label is "soft_lutpair2165";
  attribute SOFT_HLUTNM of \wordcntLast[3]_i_1\ : label is "soft_lutpair2153";
  attribute SOFT_HLUTNM of \wordcntLast[4]_i_1\ : label is "soft_lutpair2153";
  attribute SOFT_HLUTNM of \wordcntLast[5]_i_1\ : label is "soft_lutpair2154";
  attribute SOFT_HLUTNM of \wordcntLast[6]_i_1\ : label is "soft_lutpair2154";
  attribute SOFT_HLUTNM of \wordcntLast[7]_i_1\ : label is "soft_lutpair2155";
  attribute SOFT_HLUTNM of \wordcntLast[8]_i_1\ : label is "soft_lutpair2155";
  attribute SOFT_HLUTNM of \wordcntLast[9]_i_1\ : label is "soft_lutpair2156";
  attribute SOFT_HLUTNM of \wordcnt[0]_i_1__2\ : label is "soft_lutpair2150";
  attribute SOFT_HLUTNM of \wordcnt[0]_i_4\ : label is "soft_lutpair2036";
  attribute SOFT_HLUTNM of \wordcnt[0]_i_5\ : label is "soft_lutpair2133";
  attribute SOFT_HLUTNM of \wordcnt[10]_i_1__0\ : label is "soft_lutpair2139";
  attribute SOFT_HLUTNM of \wordcnt[11]_i_1__0\ : label is "soft_lutpair2140";
  attribute SOFT_HLUTNM of \wordcnt[12]_i_1__0\ : label is "soft_lutpair2140";
  attribute SOFT_HLUTNM of \wordcnt[13]_i_1__0\ : label is "soft_lutpair2141";
  attribute SOFT_HLUTNM of \wordcnt[14]_i_1__0\ : label is "soft_lutpair2141";
  attribute SOFT_HLUTNM of \wordcnt[15]_i_1__0\ : label is "soft_lutpair2142";
  attribute SOFT_HLUTNM of \wordcnt[16]_i_1__0\ : label is "soft_lutpair2142";
  attribute SOFT_HLUTNM of \wordcnt[17]_i_1__0\ : label is "soft_lutpair2143";
  attribute SOFT_HLUTNM of \wordcnt[18]_i_1__0\ : label is "soft_lutpair2143";
  attribute SOFT_HLUTNM of \wordcnt[19]_i_1__0\ : label is "soft_lutpair2144";
  attribute SOFT_HLUTNM of \wordcnt[1]_i_1__0\ : label is "soft_lutpair2135";
  attribute SOFT_HLUTNM of \wordcnt[20]_i_1__0\ : label is "soft_lutpair2144";
  attribute SOFT_HLUTNM of \wordcnt[21]_i_1__0\ : label is "soft_lutpair2145";
  attribute SOFT_HLUTNM of \wordcnt[22]_i_1__0\ : label is "soft_lutpair2145";
  attribute SOFT_HLUTNM of \wordcnt[23]_i_1__0\ : label is "soft_lutpair2146";
  attribute SOFT_HLUTNM of \wordcnt[24]_i_1__0\ : label is "soft_lutpair2146";
  attribute SOFT_HLUTNM of \wordcnt[25]_i_1__0\ : label is "soft_lutpair2147";
  attribute SOFT_HLUTNM of \wordcnt[26]_i_1__0\ : label is "soft_lutpair2147";
  attribute SOFT_HLUTNM of \wordcnt[27]_i_1__0\ : label is "soft_lutpair2148";
  attribute SOFT_HLUTNM of \wordcnt[28]_i_1__0\ : label is "soft_lutpair2148";
  attribute SOFT_HLUTNM of \wordcnt[29]_i_1__0\ : label is "soft_lutpair2149";
  attribute SOFT_HLUTNM of \wordcnt[2]_i_1__0\ : label is "soft_lutpair2135";
  attribute SOFT_HLUTNM of \wordcnt[30]_i_2__0\ : label is "soft_lutpair2149";
  attribute SOFT_HLUTNM of \wordcnt[30]_i_4__0\ : label is "soft_lutpair2000";
  attribute SOFT_HLUTNM of \wordcnt[30]_i_5\ : label is "soft_lutpair2013";
  attribute SOFT_HLUTNM of \wordcnt[3]_i_1__0\ : label is "soft_lutpair2136";
  attribute SOFT_HLUTNM of \wordcnt[4]_i_1__0\ : label is "soft_lutpair2136";
  attribute SOFT_HLUTNM of \wordcnt[5]_i_1__0\ : label is "soft_lutpair2137";
  attribute SOFT_HLUTNM of \wordcnt[6]_i_1__0\ : label is "soft_lutpair2137";
  attribute SOFT_HLUTNM of \wordcnt[7]_i_1__0\ : label is "soft_lutpair2138";
  attribute SOFT_HLUTNM of \wordcnt[8]_i_1__0\ : label is "soft_lutpair2138";
  attribute SOFT_HLUTNM of \wordcnt[9]_i_1__0\ : label is "soft_lutpair2139";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \wordcnt_reg[0]__0_i_3\ : label is 16;
  attribute ADDER_THRESHOLD of \wordcnt_reg[0]_i_3\ : label is 16;
  attribute ADDER_THRESHOLD of \wordcnt_reg[16]__0_i_1\ : label is 16;
  attribute ADDER_THRESHOLD of \wordcnt_reg[16]_i_1\ : label is 16;
  attribute ADDER_THRESHOLD of \wordcnt_reg[24]__0_i_1\ : label is 16;
  attribute ADDER_THRESHOLD of \wordcnt_reg[24]_i_1\ : label is 16;
  attribute ADDER_THRESHOLD of \wordcnt_reg[8]__0_i_1\ : label is 16;
  attribute ADDER_THRESHOLD of \wordcnt_reg[8]_i_1\ : label is 16;
begin
  AXIL_arready <= \^axil_arready\;
  AXIL_awready_sig_reg_0 <= \^axil_awready_sig_reg_0\;
  AXIL_bvalid_sig_reg_0 <= \^axil_bvalid_sig_reg_0\;
  AXIL_wready_sig_reg_0 <= \^axil_wready_sig_reg_0\;
  apuAXIL_rvalid <= \^apuaxil_rvalid\;
  crc_imd0112_out <= \^crc_imd0112_out\;
  crc_imd0115_out <= \^crc_imd0115_out\;
  crc_imd0118_out <= \^crc_imd0118_out\;
  crc_imd0172_out <= \^crc_imd0172_out\;
  crc_imd0173_out <= \^crc_imd0173_out\;
  crc_imd0174_out <= \^crc_imd0174_out\;
  crc_imd041_out <= \^crc_imd041_out\;
  crc_imd042_out <= \^crc_imd042_out\;
  crc_imd043_out <= \^crc_imd043_out\;
  recvAXIS_tdata(5 downto 0) <= \^recvaxis_tdata\(5 downto 0);
  \recvAXIS_tdata_sig_reg[15]_0\(12 downto 0) <= \^recvaxis_tdata_sig_reg[15]_0\(12 downto 0);
  recvAXIS_tlast <= \^recvaxis_tlast\;
  recvAXIS_tlast_sig_reg_0 <= \^recvaxis_tlast_sig_reg_0\;
  \stateOp_reg[0]_0\ <= \^stateop_reg[0]_0\;
  \stateOp_reg[4]\ <= \^stateop_reg[4]\;
  \stateOp_reg[4]_0\ <= \^stateop_reg[4]_0\;
  \stateOp_reg[4]_1\ <= \^stateop_reg[4]_1\;
  \stateOp_reg[4]_11\ <= \^stateop_reg[4]_11\;
  \stateOp_reg[4]_12\ <= \^stateop_reg[4]_12\;
  \stateOp_reg[4]_3\ <= \^stateop_reg[4]_3\;
  \stateOp_reg[4]_4\ <= \^stateop_reg[4]_4\;
  \stateOp_reg[5]_6\ <= \^stateop_reg[5]_6\;
  \stateRecv_reg[0]_0\ <= \^staterecv_reg[0]_0\;
  \stateRecv_reg[0]_1\ <= \^staterecv_reg[0]_1\;
  \txAXIS_tdata_reg[13]\ <= \^txaxis_tdata_reg[13]\;
\AXIL_araddr_sig_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => AXIL_arready_sig0,
      D => apuAXIL_araddr(0),
      Q => AXIL_araddr_sig(4),
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_araddr_sig_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => AXIL_arready_sig0,
      D => apuAXIL_araddr(1),
      Q => AXIL_araddr_sig(5),
      R => AXIL_rvalid_sig_reg_0(0)
    );
AXIL_arready_sig_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^apuaxil_rvalid\,
      I1 => apuAXIL_arvalid,
      I2 => \^axil_arready\,
      O => AXIL_arready_sig0
    );
AXIL_arready_sig_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => AXIL_arready_sig0,
      Q => \^axil_arready\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_awaddr_sig[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => apuAXIL_awvalid,
      I1 => awdone_reg_n_0,
      I2 => \^axil_awready_sig_reg_0\,
      O => AXIL_awready_sig0
    );
\AXIL_awaddr_sig_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => AXIL_awready_sig0,
      D => apuAXIL_awaddr(0),
      Q => ixBlkWrite(0),
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_awaddr_sig_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => AXIL_awready_sig0,
      D => apuAXIL_awaddr(1),
      Q => ixBlkWrite(1),
      R => AXIL_rvalid_sig_reg_0(0)
    );
AXIL_awready_sig_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^axil_awready_sig_reg_0\,
      I1 => awdone_reg_n_0,
      I2 => apuAXIL_awvalid,
      O => AXIL_awready_sig_i_1_n_0
    );
AXIL_awready_sig_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => AXIL_awready_sig_i_1_n_0,
      Q => \^axil_awready_sig_reg_0\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
AXIL_bvalid_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"111FFFFFEEE0EEE0"
    )
        port map (
      I0 => \^axil_wready_sig_reg_0\,
      I1 => wdone_reg_n_0,
      I2 => awdone_reg_n_0,
      I3 => \^axil_awready_sig_reg_0\,
      I4 => apuAXIL_bready,
      I5 => \^axil_bvalid_sig_reg_0\,
      O => AXIL_bvalid_sig_i_1_n_0
    );
AXIL_bvalid_sig_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => AXIL_bvalid_sig_i_1_n_0,
      Q => \^axil_bvalid_sig_reg_0\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
AXIL_rvalid_sig_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F8"
    )
        port map (
      I0 => \^axil_arready\,
      I1 => apuAXIL_arvalid,
      I2 => \^apuaxil_rvalid\,
      I3 => apuAXIL_rready,
      O => AXIL_rvalid_sig_i_1_n_0
    );
AXIL_rvalid_sig_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => AXIL_rvalid_sig_i_1_n_0,
      Q => \^apuaxil_rvalid\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => apuAXIL_wstrb(1),
      I1 => wdone_reg_n_0,
      I2 => \^axil_wready_sig_reg_0\,
      I3 => apuAXIL_wvalid,
      O => \AXIL_wdata_sig[15]_i_1_n_0\
    );
\AXIL_wdata_sig[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => apuAXIL_wstrb(2),
      I1 => wdone_reg_n_0,
      I2 => \^axil_wready_sig_reg_0\,
      I3 => apuAXIL_wvalid,
      O => \AXIL_wdata_sig[23]_i_1_n_0\
    );
\AXIL_wdata_sig[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => apuAXIL_wstrb(3),
      I1 => wdone_reg_n_0,
      I2 => \^axil_wready_sig_reg_0\,
      I3 => apuAXIL_wvalid,
      O => \AXIL_wdata_sig[31]_i_1_n_0\
    );
\AXIL_wdata_sig[39]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => apuAXIL_wstrb(4),
      I1 => wdone_reg_n_0,
      I2 => \^axil_wready_sig_reg_0\,
      I3 => apuAXIL_wvalid,
      O => \AXIL_wdata_sig[39]_i_1_n_0\
    );
\AXIL_wdata_sig[47]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => apuAXIL_wstrb(5),
      I1 => wdone_reg_n_0,
      I2 => \^axil_wready_sig_reg_0\,
      I3 => apuAXIL_wvalid,
      O => \AXIL_wdata_sig[47]_i_1_n_0\
    );
\AXIL_wdata_sig[55]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => apuAXIL_wstrb(6),
      I1 => wdone_reg_n_0,
      I2 => \^axil_wready_sig_reg_0\,
      I3 => apuAXIL_wvalid,
      O => \AXIL_wdata_sig[55]_i_1_n_0\
    );
\AXIL_wdata_sig[63]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => apuAXIL_wstrb(7),
      I1 => wdone_reg_n_0,
      I2 => \^axil_wready_sig_reg_0\,
      I3 => apuAXIL_wvalid,
      O => \AXIL_wdata_sig[63]_i_1_n_0\
    );
\AXIL_wdata_sig[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => apuAXIL_wstrb(0),
      I1 => wdone_reg_n_0,
      I2 => \^axil_wready_sig_reg_0\,
      I3 => apuAXIL_wvalid,
      O => \AXIL_wdata_sig[7]_i_1_n_0\
    );
\AXIL_wdata_sig_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1_n_0\,
      D => apuAXIL_wdata(0),
      Q => \AXIL_wdata_sig_reg_n_0_[0]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1_n_0\,
      D => apuAXIL_wdata(10),
      Q => \AXIL_wdata_sig_reg_n_0_[10]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1_n_0\,
      D => apuAXIL_wdata(11),
      Q => \AXIL_wdata_sig_reg_n_0_[11]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1_n_0\,
      D => apuAXIL_wdata(12),
      Q => \AXIL_wdata_sig_reg_n_0_[12]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1_n_0\,
      D => apuAXIL_wdata(13),
      Q => \AXIL_wdata_sig_reg_n_0_[13]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1_n_0\,
      D => apuAXIL_wdata(14),
      Q => \AXIL_wdata_sig_reg_n_0_[14]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1_n_0\,
      D => apuAXIL_wdata(15),
      Q => \AXIL_wdata_sig_reg_n_0_[15]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1_n_0\,
      D => apuAXIL_wdata(16),
      Q => \AXIL_wdata_sig_reg_n_0_[16]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1_n_0\,
      D => apuAXIL_wdata(17),
      Q => \AXIL_wdata_sig_reg_n_0_[17]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1_n_0\,
      D => apuAXIL_wdata(18),
      Q => \AXIL_wdata_sig_reg_n_0_[18]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1_n_0\,
      D => apuAXIL_wdata(19),
      Q => \AXIL_wdata_sig_reg_n_0_[19]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1_n_0\,
      D => apuAXIL_wdata(1),
      Q => \AXIL_wdata_sig_reg_n_0_[1]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1_n_0\,
      D => apuAXIL_wdata(20),
      Q => \AXIL_wdata_sig_reg_n_0_[20]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1_n_0\,
      D => apuAXIL_wdata(21),
      Q => \AXIL_wdata_sig_reg_n_0_[21]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1_n_0\,
      D => apuAXIL_wdata(22),
      Q => \AXIL_wdata_sig_reg_n_0_[22]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1_n_0\,
      D => apuAXIL_wdata(23),
      Q => \AXIL_wdata_sig_reg_n_0_[23]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1_n_0\,
      D => apuAXIL_wdata(24),
      Q => \AXIL_wdata_sig_reg_n_0_[24]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1_n_0\,
      D => apuAXIL_wdata(25),
      Q => \AXIL_wdata_sig_reg_n_0_[25]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1_n_0\,
      D => apuAXIL_wdata(26),
      Q => \AXIL_wdata_sig_reg_n_0_[26]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1_n_0\,
      D => apuAXIL_wdata(27),
      Q => \AXIL_wdata_sig_reg_n_0_[27]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1_n_0\,
      D => apuAXIL_wdata(28),
      Q => \AXIL_wdata_sig_reg_n_0_[28]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1_n_0\,
      D => apuAXIL_wdata(29),
      Q => \AXIL_wdata_sig_reg_n_0_[29]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1_n_0\,
      D => apuAXIL_wdata(2),
      Q => p_0_in(0),
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1_n_0\,
      D => apuAXIL_wdata(30),
      Q => \AXIL_wdata_sig_reg_n_0_[30]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1_n_0\,
      D => apuAXIL_wdata(31),
      Q => \AXIL_wdata_sig_reg_n_0_[31]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[39]_i_1_n_0\,
      D => apuAXIL_wdata(32),
      Q => \AXIL_wdata_sig_reg_n_0_[32]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[39]_i_1_n_0\,
      D => apuAXIL_wdata(33),
      Q => \AXIL_wdata_sig_reg_n_0_[33]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[39]_i_1_n_0\,
      D => apuAXIL_wdata(34),
      Q => \AXIL_wdata_sig_reg_n_0_[34]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[39]_i_1_n_0\,
      D => apuAXIL_wdata(35),
      Q => \AXIL_wdata_sig_reg_n_0_[35]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[39]_i_1_n_0\,
      D => apuAXIL_wdata(36),
      Q => \AXIL_wdata_sig_reg_n_0_[36]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[39]_i_1_n_0\,
      D => apuAXIL_wdata(37),
      Q => \AXIL_wdata_sig_reg_n_0_[37]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[39]_i_1_n_0\,
      D => apuAXIL_wdata(38),
      Q => \AXIL_wdata_sig_reg_n_0_[38]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[39]_i_1_n_0\,
      D => apuAXIL_wdata(39),
      Q => \AXIL_wdata_sig_reg_n_0_[39]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1_n_0\,
      D => apuAXIL_wdata(3),
      Q => p_0_in(1),
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[47]_i_1_n_0\,
      D => apuAXIL_wdata(40),
      Q => \AXIL_wdata_sig_reg_n_0_[40]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[47]_i_1_n_0\,
      D => apuAXIL_wdata(41),
      Q => \AXIL_wdata_sig_reg_n_0_[41]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[47]_i_1_n_0\,
      D => apuAXIL_wdata(42),
      Q => \AXIL_wdata_sig_reg_n_0_[42]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[47]_i_1_n_0\,
      D => apuAXIL_wdata(43),
      Q => \AXIL_wdata_sig_reg_n_0_[43]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[47]_i_1_n_0\,
      D => apuAXIL_wdata(44),
      Q => \AXIL_wdata_sig_reg_n_0_[44]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[47]_i_1_n_0\,
      D => apuAXIL_wdata(45),
      Q => \AXIL_wdata_sig_reg_n_0_[45]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[47]_i_1_n_0\,
      D => apuAXIL_wdata(46),
      Q => \AXIL_wdata_sig_reg_n_0_[46]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[47]_i_1_n_0\,
      D => apuAXIL_wdata(47),
      Q => \AXIL_wdata_sig_reg_n_0_[47]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[55]_i_1_n_0\,
      D => apuAXIL_wdata(48),
      Q => \AXIL_wdata_sig_reg_n_0_[48]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[55]_i_1_n_0\,
      D => apuAXIL_wdata(49),
      Q => \AXIL_wdata_sig_reg_n_0_[49]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1_n_0\,
      D => apuAXIL_wdata(4),
      Q => \AXIL_wdata_sig_reg_n_0_[4]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[55]_i_1_n_0\,
      D => apuAXIL_wdata(50),
      Q => \AXIL_wdata_sig_reg_n_0_[50]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[55]_i_1_n_0\,
      D => apuAXIL_wdata(51),
      Q => \AXIL_wdata_sig_reg_n_0_[51]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[55]_i_1_n_0\,
      D => apuAXIL_wdata(52),
      Q => \AXIL_wdata_sig_reg_n_0_[52]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[55]_i_1_n_0\,
      D => apuAXIL_wdata(53),
      Q => \AXIL_wdata_sig_reg_n_0_[53]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[55]_i_1_n_0\,
      D => apuAXIL_wdata(54),
      Q => \AXIL_wdata_sig_reg_n_0_[54]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[55]_i_1_n_0\,
      D => apuAXIL_wdata(55),
      Q => \AXIL_wdata_sig_reg_n_0_[55]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[63]_i_1_n_0\,
      D => apuAXIL_wdata(56),
      Q => \AXIL_wdata_sig_reg_n_0_[56]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[63]_i_1_n_0\,
      D => apuAXIL_wdata(57),
      Q => \AXIL_wdata_sig_reg_n_0_[57]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[63]_i_1_n_0\,
      D => apuAXIL_wdata(58),
      Q => \AXIL_wdata_sig_reg_n_0_[58]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[63]_i_1_n_0\,
      D => apuAXIL_wdata(59),
      Q => \AXIL_wdata_sig_reg_n_0_[59]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1_n_0\,
      D => apuAXIL_wdata(5),
      Q => \AXIL_wdata_sig_reg_n_0_[5]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[63]_i_1_n_0\,
      D => apuAXIL_wdata(60),
      Q => \AXIL_wdata_sig_reg_n_0_[60]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[63]_i_1_n_0\,
      D => apuAXIL_wdata(61),
      Q => \AXIL_wdata_sig_reg_n_0_[61]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[63]_i_1_n_0\,
      D => apuAXIL_wdata(62),
      Q => \AXIL_wdata_sig_reg_n_0_[62]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[63]_i_1_n_0\,
      D => apuAXIL_wdata(63),
      Q => \AXIL_wdata_sig_reg_n_0_[63]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1_n_0\,
      D => apuAXIL_wdata(6),
      Q => \AXIL_wdata_sig_reg_n_0_[6]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1_n_0\,
      D => apuAXIL_wdata(7),
      Q => \AXIL_wdata_sig_reg_n_0_[7]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1_n_0\,
      D => apuAXIL_wdata(8),
      Q => \AXIL_wdata_sig_reg_n_0_[8]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\AXIL_wdata_sig_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1_n_0\,
      D => apuAXIL_wdata(9),
      Q => \AXIL_wdata_sig_reg_n_0_[9]\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
AXIL_wready_sig_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => wdone_reg_n_0,
      I1 => \^axil_wready_sig_reg_0\,
      I2 => apuAXIL_wvalid,
      O => AXIL_wready_sig_i_1_n_0
    );
AXIL_wready_sig_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => AXIL_wready_sig_i_1_n_0,
      Q => \^axil_wready_sig_reg_0\,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\apuAXIL_rdata[0]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(0),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(0)
    );
\apuAXIL_rdata[10]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(10),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(10)
    );
\apuAXIL_rdata[11]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(11),
      O => apuAXIL_rdata(11)
    );
\apuAXIL_rdata[12]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(12),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(12)
    );
\apuAXIL_rdata[13]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(13),
      O => apuAXIL_rdata(13)
    );
\apuAXIL_rdata[14]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(14),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(14)
    );
\apuAXIL_rdata[15]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(15),
      O => apuAXIL_rdata(15)
    );
\apuAXIL_rdata[16]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(16),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(16)
    );
\apuAXIL_rdata[17]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(17),
      O => apuAXIL_rdata(17)
    );
\apuAXIL_rdata[18]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(18),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(18)
    );
\apuAXIL_rdata[19]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(19),
      O => apuAXIL_rdata(19)
    );
\apuAXIL_rdata[1]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(1),
      O => apuAXIL_rdata(1)
    );
\apuAXIL_rdata[20]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(20),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(20)
    );
\apuAXIL_rdata[21]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(21),
      O => apuAXIL_rdata(21)
    );
\apuAXIL_rdata[22]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(22),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(22)
    );
\apuAXIL_rdata[23]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(23),
      O => apuAXIL_rdata(23)
    );
\apuAXIL_rdata[24]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(24),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(24)
    );
\apuAXIL_rdata[25]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(25),
      O => apuAXIL_rdata(25)
    );
\apuAXIL_rdata[26]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(26),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(26)
    );
\apuAXIL_rdata[27]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(27),
      O => apuAXIL_rdata(27)
    );
\apuAXIL_rdata[28]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(28),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(28)
    );
\apuAXIL_rdata[29]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(29),
      O => apuAXIL_rdata(29)
    );
\apuAXIL_rdata[2]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(2),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(2)
    );
\apuAXIL_rdata[30]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(30),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(30)
    );
\apuAXIL_rdata[31]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(31),
      O => apuAXIL_rdata(31)
    );
\apuAXIL_rdata[32]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(32),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(32)
    );
\apuAXIL_rdata[33]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(33),
      O => apuAXIL_rdata(33)
    );
\apuAXIL_rdata[34]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(34),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(34)
    );
\apuAXIL_rdata[35]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(35),
      O => apuAXIL_rdata(35)
    );
\apuAXIL_rdata[36]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(36),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(36)
    );
\apuAXIL_rdata[37]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(37),
      O => apuAXIL_rdata(37)
    );
\apuAXIL_rdata[38]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(38),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(38)
    );
\apuAXIL_rdata[39]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(39),
      O => apuAXIL_rdata(39)
    );
\apuAXIL_rdata[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(3),
      O => apuAXIL_rdata(3)
    );
\apuAXIL_rdata[40]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(40),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(40)
    );
\apuAXIL_rdata[41]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(41),
      O => apuAXIL_rdata(41)
    );
\apuAXIL_rdata[42]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(42),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(42)
    );
\apuAXIL_rdata[43]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(43),
      O => apuAXIL_rdata(43)
    );
\apuAXIL_rdata[44]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(44),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(44)
    );
\apuAXIL_rdata[45]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(45),
      O => apuAXIL_rdata(45)
    );
\apuAXIL_rdata[46]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(46),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(46)
    );
\apuAXIL_rdata[47]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(47),
      O => apuAXIL_rdata(47)
    );
\apuAXIL_rdata[48]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(48),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(48)
    );
\apuAXIL_rdata[49]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(49),
      O => apuAXIL_rdata(49)
    );
\apuAXIL_rdata[4]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(4),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(4)
    );
\apuAXIL_rdata[50]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(50),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(50)
    );
\apuAXIL_rdata[51]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(51),
      O => apuAXIL_rdata(51)
    );
\apuAXIL_rdata[52]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(52),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(52)
    );
\apuAXIL_rdata[53]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(53),
      O => apuAXIL_rdata(53)
    );
\apuAXIL_rdata[54]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(54),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(54)
    );
\apuAXIL_rdata[55]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(55),
      O => apuAXIL_rdata(55)
    );
\apuAXIL_rdata[56]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(56),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(56)
    );
\apuAXIL_rdata[57]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(57),
      O => apuAXIL_rdata(57)
    );
\apuAXIL_rdata[58]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(58),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(58)
    );
\apuAXIL_rdata[59]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(59),
      O => apuAXIL_rdata(59)
    );
\apuAXIL_rdata[5]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(5),
      O => apuAXIL_rdata(5)
    );
\apuAXIL_rdata[60]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(60),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(60)
    );
\apuAXIL_rdata[61]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(61),
      O => apuAXIL_rdata(61)
    );
\apuAXIL_rdata[62]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(62),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(62)
    );
\apuAXIL_rdata[63]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(63),
      O => apuAXIL_rdata(63)
    );
\apuAXIL_rdata[63]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE0FB03FFC8F64F"
    )
        port map (
      I0 => Q(0),
      I1 => Q(2),
      I2 => Q(4),
      I3 => Q(5),
      I4 => Q(3),
      I5 => Q(1),
      O => \apuAXIL_rdata[63]_INST_0_i_1_n_0\
    );
\apuAXIL_rdata[6]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(6),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(6)
    );
\apuAXIL_rdata[7]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(7),
      O => apuAXIL_rdata(7)
    );
\apuAXIL_rdata[8]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sendAXIL_rdata(8),
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => apuAXIL_rdata(8)
    );
\apuAXIL_rdata[9]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[63]\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(9),
      O => apuAXIL_rdata(9)
    );
\awdone_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"777F777F777F0000"
    )
        port map (
      I0 => \^axil_bvalid_sig_reg_0\,
      I1 => apuAXIL_bready,
      I2 => wdone_reg_n_0,
      I3 => \^axil_wready_sig_reg_0\,
      I4 => awdone_reg_n_0,
      I5 => \^axil_awready_sig_reg_0\,
      O => \awdone_i_1__0_n_0\
    );
awdone_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \awdone_i_1__0_n_0\,
      Q => awdone_reg_n_0,
      R => AXIL_rvalid_sig_reg_0(0)
    );
commok_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F088F008008800"
    )
        port map (
      I0 => \^staterecv_reg[0]_0\,
      I1 => commok_sig_reg_0,
      I2 => \stateOp[0]_i_2_n_0\,
      I3 => \^stateop_reg[4]_4\,
      I4 => commok_sig_reg_2,
      I5 => commok_sig_reg_3,
      O => commok_sig_reg
    );
\crcAXIS_tkeep[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7555FFFF77777777"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \crcAXIS_tkeep_reg[7]_2\,
      I2 => crcAXIS_tlast_sig_reg_0(0),
      I3 => \crcAXIS_tkeep_reg[3]\,
      I4 => \crcAXIS_tkeep_reg[0]_0\,
      I5 => \crcAXIS_tkeep_reg[3]_0\,
      O => \lastAXIS_tkeep_reg[7]\(0)
    );
\crcAXIS_tkeep[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFB3B3B3BFBFBFBF"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[7]_1\(0),
      I1 => \^stateop_reg[4]_0\,
      I2 => \crcAXIS_tkeep_reg[7]_2\,
      I3 => crcAXIS_tlast_sig_reg_0(0),
      I4 => \crcAXIS_tkeep_reg[3]\,
      I5 => \crcAXIS_tkeep_reg[3]_0\,
      O => \lastAXIS_tkeep_reg[7]\(1)
    );
\crcAXIS_tkeep[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF0D0D0D"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[3]\,
      I1 => \stateOp_next_reg[5]\,
      I2 => \crcAXIS_tkeep_reg[3]_0\,
      I3 => \crcAXIS_tkeep_reg[7]_1\(1),
      I4 => \crcAXIS_tkeep_reg[7]_2\,
      I5 => \crcAXIS_tkeep[3]_i_4__0_n_0\,
      O => \lastAXIS_tkeep_reg[7]\(2)
    );
\crcAXIS_tkeep[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF07FF07FF07"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[3]\,
      I1 => \crcAXIS_tkeep_reg[3]_1\,
      I2 => \crcAXIS_tkeep_reg[3]_0\,
      I3 => \crcAXIS_tkeep[3]_i_4__0_n_0\,
      I4 => \crcAXIS_tkeep_reg[7]_1\(2),
      I5 => \crcAXIS_tkeep_reg[7]_2\,
      O => \lastAXIS_tkeep_reg[7]\(3)
    );
\crcAXIS_tkeep[3]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8000FFFF"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[3]\,
      I1 => \crcAXIS_tkeep_reg[3]_0\,
      I2 => crcAXIS_tlast_sig_reg_0(0),
      I3 => \crcAXIS_tkeep_reg[0]_0\,
      I4 => \^stateop_reg[4]_0\,
      O => \crcAXIS_tkeep[3]_i_4__0_n_0\
    );
\crcAXIS_tkeep[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => \crcAXIS_tkeep[5]_i_2_n_0\,
      I1 => \crcAXIS_tkeep_reg[7]\,
      I2 => \crcAXIS_tkeep_reg[4]\,
      I3 => \crcAXIS_tkeep_reg[7]_1\(3),
      I4 => \crcAXIS_tkeep_reg[7]_2\,
      O => \lastAXIS_tkeep_reg[7]\(4)
    );
\crcAXIS_tkeep[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[7]_2\,
      I1 => \crcAXIS_tkeep_reg[7]_1\(4),
      I2 => \crcAXIS_tkeep[5]_i_2_n_0\,
      O => \lastAXIS_tkeep_reg[7]\(5)
    );
\crcAXIS_tkeep[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D0FF"
    )
        port map (
      I0 => \lastAXIS_tkeep_reg[1]_0\,
      I1 => \lastAXIS_tkeep_reg[5]\,
      I2 => \crcAXIS_tkeep_reg[7]\,
      I3 => \^stateop_reg[4]_0\,
      O => \crcAXIS_tkeep[5]_i_2_n_0\
    );
\crcAXIS_tkeep[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFD0FFD0FFD0FF"
    )
        port map (
      I0 => \lastAXIS_tkeep_reg[1]_0\,
      I1 => \crcAXIS_tkeep_reg[6]\,
      I2 => \crcAXIS_tkeep_reg[7]\,
      I3 => \^stateop_reg[4]_0\,
      I4 => \crcAXIS_tkeep_reg[7]_1\(5),
      I5 => \crcAXIS_tkeep_reg[7]_2\,
      O => \lastAXIS_tkeep_reg[7]\(6)
    );
\crcAXIS_tkeep[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F5F3F0FFF5F3F"
    )
        port map (
      I0 => \crcAXIS_tkeep[7]_i_3_n_0\,
      I1 => \crcAXIS_tkeep[7]_i_4_n_0\,
      I2 => \^stateop_reg[4]_0\,
      I3 => \crcAXIS_tkeep_reg[0]_1\,
      I4 => \crcAXIS_tkeep_reg[0]_2\,
      I5 => \crcAXIS_tkeep[7]_i_7_n_0\,
      O => \stateSend_reg[2]_1\(0)
    );
\crcAXIS_tkeep[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF70FF70FF70FF"
    )
        port map (
      I0 => \lastAXIS_tkeep_reg[1]_0\,
      I1 => \crcAXIS_tkeep_reg[7]_0\,
      I2 => \crcAXIS_tkeep_reg[7]\,
      I3 => \^stateop_reg[4]_0\,
      I4 => \crcAXIS_tkeep_reg[7]_1\(6),
      I5 => \crcAXIS_tkeep_reg[7]_2\,
      O => \lastAXIS_tkeep_reg[7]\(7)
    );
\crcAXIS_tkeep[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFFFFFBFFF0000"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      I2 => stateSend(0),
      I3 => crcAXIS_tlast_sig_reg_0(0),
      I4 => \crcAXIS_tkeep_reg[0]_6\,
      I5 => \crcAXIS_tkeep_reg[0]_7\(0),
      O => \crcAXIS_tkeep[7]_i_3_n_0\
    );
\crcAXIS_tkeep[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"080008FF08FF08FF"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[0]_3\,
      I1 => \crcAXIS_tkeep_reg[0]_4\,
      I2 => \crcAXIS_tkeep_reg[0]_5\,
      I3 => \crcAXIS_tkeep_reg[0]_6\,
      I4 => \^staterecv_reg[0]_0\,
      I5 => CO(0),
      O => \crcAXIS_tkeep[7]_i_4_n_0\
    );
\crcAXIS_tkeep[7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAA8AAAAAAAAA"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[0]_6\,
      I1 => stateRecv(1),
      I2 => stateRecv(2),
      I3 => stateRecv(0),
      I4 => crcAXIS_tlast_sig_reg_0(0),
      I5 => CO(0),
      O => \crcAXIS_tkeep[7]_i_7_n_0\
    );
crcAXIS_tlast_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C5FFFFFFC5FF0000"
    )
        port map (
      I0 => crcAXIS_tlast_sig_reg_4,
      I1 => crcAXIS_tlast_sig_reg_0(0),
      I2 => Q(5),
      I3 => \^stateop_reg[4]_1\,
      I4 => crcAXIS_tlast_sig_i_3_n_0,
      I5 => crcAXIS_tlast_sig_reg_3,
      O => \stateOp_reg[5]_7\
    );
crcAXIS_tlast_sig_i_10: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFFFFFFFFF70FF"
    )
        port map (
      I0 => crcAXIS_tlast_sig_reg_0(0),
      I1 => \^staterecv_reg[0]_0\,
      I2 => Q(1),
      I3 => crcAXIS_tlast_sig_i_6_0,
      I4 => Q(3),
      I5 => Q(2),
      O => crcAXIS_tlast_sig_i_10_n_0
    );
crcAXIS_tlast_sig_i_11: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0777077700000777"
    )
        port map (
      I0 => crcAXIS_tlast_sig_i_8_0,
      I1 => \stateOp[5]_i_18_n_0\,
      I2 => crcAXIS_tlast_sig_i_8_1,
      I3 => \txAXIS_tdata_reg[8]_1\,
      I4 => crcAXIS_tlast_sig_i_8_2,
      I5 => crcAXIS_tlast_sig_i_12_n_0,
      O => crcAXIS_tlast_sig_i_11_n_0
    );
crcAXIS_tlast_sig_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => stateRecv(1),
      I1 => stateRecv(2),
      I2 => stateRecv(0),
      I3 => crcAXIS_tlast_sig_reg_0(0),
      O => crcAXIS_tlast_sig_i_12_n_0
    );
crcAXIS_tlast_sig_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBFFFFFBBBFBBBF"
    )
        port map (
      I0 => crcAXIS_tlast_sig_i_6_n_0,
      I1 => \^stateop_reg[4]_1\,
      I2 => crcAXIS_tlast_sig_reg_1,
      I3 => Q(5),
      I4 => crcAXIS_tlast_sig_i_8_n_0,
      I5 => crcAXIS_tlast_sig_reg_2,
      O => crcAXIS_tlast_sig_i_3_n_0
    );
crcAXIS_tlast_sig_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000075AA75"
    )
        port map (
      I0 => Q(3),
      I1 => \stateOp[3]_i_7_n_0\,
      I2 => \^staterecv_reg[0]_0\,
      I3 => Q(4),
      I4 => \wordcntLast_reg[0]_2\,
      I5 => crcAXIS_tlast_sig_i_10_n_0,
      O => crcAXIS_tlast_sig_i_6_n_0
    );
crcAXIS_tlast_sig_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FAFAFAFAFFFFCFFF"
    )
        port map (
      I0 => crcAXIS_tlast_sig_i_11_n_0,
      I1 => CO(0),
      I2 => Q(5),
      I3 => \stateOp_next_reg[0]\,
      I4 => crcAXIS_tlast_sig_i_12_n_0,
      I5 => Q(2),
      O => crcAXIS_tlast_sig_i_8_n_0
    );
\crc_imd[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \crc_imd[0]_i_2_n_0\,
      I1 => \crc_imd[0]_i_3_n_0\,
      I2 => \crc_imd[0]_i_4_n_0\,
      I3 => \crc_imd[0]_i_5_n_0\,
      I4 => \crc_imd[0]_i_6_n_0\,
      I5 => \crc_imd[0]_i_7_n_0\,
      O => \crc_imd_reg[7]_1\(0)
    );
\crc_imd[0]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => AXIS_tdata(35),
      I1 => AXIS_tdata(19),
      I2 => AXIS_tdata(56),
      I3 => AXIS_tdata(38),
      I4 => AXIS_tdata(53),
      I5 => AXIS_tdata(17),
      O => \crc_imd[0]_i_10_n_0\
    );
\crc_imd[0]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \crc_imd[15]_i_33_n_0\,
      I1 => \crc_imd[15]_i_64_n_0\,
      O => \crc_imd[0]_i_11_n_0\
    );
\crc_imd[0]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(53),
      I1 => rxAXIS_tdata(53),
      I2 => \sendAXIL_rdata_reg[63]_0\(54),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(54),
      I5 => stateOp_reg,
      O => \crc_imd[0]_i_12_n_0\
    );
\crc_imd[0]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[9]_i_13_n_0\,
      I1 => \crc_imd[15]_i_71_n_0\,
      I2 => AXIS_tdata(30),
      I3 => AXIS_tdata(27),
      I4 => \crc_imd[14]_i_5_0\,
      I5 => \crc_imd[2]_i_6_n_0\,
      O => \crc_imd[0]_i_13_n_0\
    );
\crc_imd[0]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[1]\,
      I1 => \crc_imd[15]_i_39_n_0\,
      I2 => AXIS_tdata(22),
      I3 => \crc_imd[15]_i_63_n_0\,
      I4 => \crc_imd[15]_i_38_n_0\,
      I5 => \crc_imd[0]_i_18_n_0\,
      O => \crc_imd[0]_i_14_n_0\
    );
\crc_imd[0]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F44B0BBB0BB4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => \^recvaxis_tdata\(5),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(15),
      I4 => \retbuf_reg[15][7]\(7),
      I5 => AXIS_tdata(16),
      O => \crc_imd[0]_i_15_n_0\
    );
\crc_imd[0]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[1]_0\,
      I1 => \crc_imd[15]_i_79_n_0\,
      I2 => \crc_imd[0]_i_19_n_0\,
      I3 => \crc_imd[0]_i_20_n_0\,
      I4 => AXIS_tdata(21),
      I5 => \crc_imd[15]_i_77_n_0\,
      O => \crc_imd[0]_i_16_n_0\
    );
\crc_imd[0]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(53),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(53),
      O => AXIS_tdata(53)
    );
\crc_imd[0]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[15]_i_47_n_0\,
      I1 => \crc_imd[15]_i_75_n_0\,
      I2 => AXIS_tdata(39),
      I3 => AXIS_tdata(37),
      I4 => \crc_imd[15]_i_55_n_0\,
      I5 => AXIS_tdata(19),
      O => \crc_imd[0]_i_18_n_0\
    );
\crc_imd[0]_i_19\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \crc_imd[15]_i_75_n_0\,
      I1 => \crc_imd[9]_i_16_n_0\,
      I2 => \crc_imd[15]_i_47_n_0\,
      I3 => \crc_imd[1]_i_10_n_0\,
      O => \crc_imd[0]_i_19_n_0\
    );
\crc_imd[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000600"
    )
        port map (
      I0 => \crc_imd[15]_i_16_n_0\,
      I1 => \crc_imd[15]_i_17_n_0\,
      I2 => \crc_imd_reg[0]\(2),
      I3 => \crc_imd_reg[0]_0\,
      I4 => \crc_imd_reg[0]\(1),
      I5 => \^recvaxis_tlast_sig_reg_0\,
      O => \crc_imd[0]_i_2_n_0\
    );
\crc_imd[0]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"65AA65659A559A9A"
    )
        port map (
      I0 => \retbuf_reg[15][7]\(14),
      I1 => stateOp_reg,
      I2 => rxAXIS_tdata(6),
      I3 => \crc_imd_reg[4]\,
      I4 => \sendAXIL_rdata_reg[63]_0\(6),
      I5 => AXIS_tdata(23),
      O => \crc_imd[0]_i_20_n_0\
    );
\crc_imd[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800000800080800"
    )
        port map (
      I0 => \crc_imd_reg[0]\(1),
      I1 => \crc_imd_reg[0]_0\,
      I2 => \crc_imd_reg[0]\(2),
      I3 => \crc_imd[15]_i_18_n_0\,
      I4 => \crc_imd[15]_i_17_n_0\,
      I5 => \crc_imd[9]_i_12_n_0\,
      O => \crc_imd[0]_i_3_n_0\
    );
\crc_imd[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28828228"
    )
        port map (
      I0 => \crc_imd_reg[0]_2\,
      I1 => \crc_imd[15]_i_23_n_0\,
      I2 => \crc_imd[0]_i_8_n_0\,
      I3 => \crc_imd[15]_i_21_n_0\,
      I4 => AXIS_tdata(29),
      O => \crc_imd[0]_i_4_n_0\
    );
\crc_imd[0]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28828228"
    )
        port map (
      I0 => \crc_imd_reg[8]_1\,
      I1 => \crc_imd[15]_i_31_n_0\,
      I2 => \crc_imd[0]_i_9_n_0\,
      I3 => \crc_imd[15]_i_28_n_0\,
      I4 => \crc_imd[0]_i_10_n_0\,
      O => \crc_imd[0]_i_5_n_0\
    );
\crc_imd[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[2]_2\,
      I1 => \crc_imd[15]_i_34_n_0\,
      I2 => \crc_imd[0]_i_11_n_0\,
      I3 => \crc_imd[0]_i_12_n_0\,
      I4 => \crc_imd[0]_i_13_n_0\,
      I5 => \crc_imd[15]_i_23_n_0\,
      O => \crc_imd[0]_i_6_n_0\
    );
\crc_imd[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEAAEAEEA"
    )
        port map (
      I0 => \crc_imd[0]_i_14_n_0\,
      I1 => \crc_imd_reg[0]_1\,
      I2 => \crc_imd[1]_i_25_n_0\,
      I3 => \crc_imd[15]_i_27_n_0\,
      I4 => \crc_imd[0]_i_15_n_0\,
      I5 => \crc_imd[0]_i_16_n_0\,
      O => \crc_imd[0]_i_7_n_0\
    );
\crc_imd[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"65AA65659A559A9A"
    )
        port map (
      I0 => \crc_imd[15]_i_22_n_0\,
      I1 => stateOp_reg,
      I2 => \^recvaxis_tdata\(3),
      I3 => \crc_imd_reg[4]\,
      I4 => \sendAXIL_rdata_reg[63]_0\(11),
      I5 => \retbuf_reg[15][7]\(3),
      O => \crc_imd[0]_i_8_n_0\
    );
\crc_imd[0]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \crc_imd[15]_i_60_n_0\,
      I1 => \crc_imd[15]_i_79_n_0\,
      I2 => \crc_imd[15]_i_62_n_0\,
      I3 => \crc_imd[1]_i_20_n_0\,
      I4 => \crc_imd[15]_i_63_n_0\,
      O => \crc_imd[0]_i_9_n_0\
    );
\crc_imd[10]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \crc_imd[12]_i_3\,
      I1 => \^recvaxis_tdata_sig_reg[15]_0\(11),
      I2 => AXIS_tdata(17),
      I3 => \retbuf_reg[15][7]\(6),
      I4 => AXIS_tdata(16),
      O => crc_imd065_out
    );
\crc_imd[10]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => AXIS_tdata(20),
      I1 => AXIS_tdata(21),
      I2 => AXIS_tdata(22),
      I3 => AXIS_tdata(24),
      I4 => AXIS_tdata(41),
      I5 => AXIS_tdata(38),
      O => \crc_imd[10]_i_11_n_0\
    );
\crc_imd[10]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(40),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(40),
      O => AXIS_tdata(40)
    );
\crc_imd[10]_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(32),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(32),
      O => AXIS_tdata(32)
    );
\crc_imd[10]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F44B0BBB0BB4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(28),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(28),
      I4 => AXIS_tdata(31),
      I5 => \crc_imd[10]_i_17_n_0\,
      O => \crc_imd[10]_i_14_n_0\
    );
\crc_imd[10]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(24),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(24),
      O => AXIS_tdata(24)
    );
\crc_imd[10]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(33),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(33),
      O => AXIS_tdata(33)
    );
\crc_imd[10]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(49),
      I1 => rxAXIS_tdata(49),
      I2 => \sendAXIL_rdata_reg[63]_0\(48),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(48),
      I5 => stateOp_reg,
      O => \crc_imd[10]_i_17_n_0\
    );
\crc_imd[10]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => \^recvaxis_tdata\(0),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(0),
      O => \^recvaxis_tdata_sig_reg[15]_0\(0)
    );
\crc_imd[10]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \crc_imd[10]_i_11_n_0\,
      I1 => \crc_imd[15]_i_19_n_0\,
      I2 => AXIS_tdata(23),
      I3 => \crc_imd[15]_i_73_n_0\,
      I4 => AXIS_tdata(40),
      O => crc_imd0148_out
    );
\crc_imd[10]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => AXIS_tdata(32),
      I1 => AXIS_tdata(46),
      I2 => \crc_imd[10]_i_14_n_0\,
      I3 => \crc_imd[7]_i_11_n_0\,
      I4 => \crc_imd[1]_i_24_n_0\,
      I5 => \crc_imd[12]_i_3_0\,
      O => \^crc_imd0172_out\
    );
\crc_imd[10]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => AXIS_tdata(24),
      I1 => \crc_imd[9]_i_12_n_0\,
      I2 => \crc_imd[15]_i_19_n_0\,
      I3 => \crc_imd[1]_i_20_n_0\,
      I4 => \crc_imd[11]_i_13_n_0\,
      O => crc_imd081_out
    );
\crc_imd[10]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[14]_i_5\,
      I1 => \crc_imd[15]_i_34_n_0\,
      I2 => AXIS_tdata(16),
      I3 => AXIS_tdata(30),
      I4 => AXIS_tdata(33),
      I5 => AXIS_tdata(32),
      O => \^crc_imd0112_out\
    );
\crc_imd[11]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[15]_0\(7),
      I1 => \crc_imd[2]_i_6_n_0\,
      I2 => \retbuf_reg[15][7]\(15),
      I3 => \crc_imd[4]_i_6_n_0\,
      O => \^crc_imd042_out\
    );
\crc_imd[11]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \crc_imd[1]_i_9_n_0\,
      I1 => \retbuf_reg[15][7]\(7),
      I2 => AXIS_tdata(18),
      I3 => \^recvaxis_tdata_sig_reg[15]_0\(12),
      I4 => AXIS_tdata(17),
      O => crc_imd066_out
    );
\crc_imd[11]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6966999969666966"
    )
        port map (
      I0 => \crc_imd[15]_i_62_n_0\,
      I1 => \retbuf_reg[15][7]\(11),
      I2 => stateOp_reg,
      I3 => rxAXIS_tdata(3),
      I4 => \crc_imd_reg[4]\,
      I5 => \sendAXIL_rdata_reg[63]_0\(3),
      O => \crc_imd[11]_i_12_n_0\
    );
\crc_imd[11]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A6A655A6"
    )
        port map (
      I0 => \crc_imd[9]_i_13_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(25),
      I2 => \crc_imd_reg[4]\,
      I3 => rxAXIS_tdata(25),
      I4 => stateOp_reg,
      O => \crc_imd[11]_i_13_n_0\
    );
\crc_imd[11]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(41),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(41),
      O => AXIS_tdata(41)
    );
\crc_imd[11]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(42),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(42),
      O => AXIS_tdata(42)
    );
\crc_imd[11]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(49),
      I1 => rxAXIS_tdata(49),
      I2 => \sendAXIL_rdata_reg[63]_0\(50),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(50),
      I5 => stateOp_reg,
      O => \crc_imd[11]_i_16_n_0\
    );
\crc_imd[11]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(47),
      I1 => rxAXIS_tdata(47),
      I2 => \sendAXIL_rdata_reg[63]_0\(33),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(33),
      I5 => stateOp_reg,
      O => \crc_imd[11]_i_17_n_0\
    );
\crc_imd[11]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(34),
      I1 => rxAXIS_tdata(34),
      I2 => \sendAXIL_rdata_reg[63]_0\(33),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(33),
      I5 => stateOp_reg,
      O => \crc_imd[11]_i_18_n_0\
    );
\crc_imd[11]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(1),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(1),
      O => \^recvaxis_tdata_sig_reg[15]_0\(1)
    );
\crc_imd[11]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[11]_i_12_n_0\,
      I1 => \crc_imd[11]_i_13_n_0\,
      I2 => AXIS_tdata(22),
      I3 => AXIS_tdata(23),
      I4 => AXIS_tdata(41),
      I5 => AXIS_tdata(42),
      O => crc_imd0149_out
    );
\crc_imd[11]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[11]_i_16_n_0\,
      I1 => \crc_imd[15]_i_41_0\,
      I2 => \crc_imd[14]_i_5_0\,
      I3 => \crc_imd[11]_i_17_n_0\,
      I4 => \crc_imd[7]_i_11_n_0\,
      I5 => \crc_imd[1]_i_21_n_0\,
      O => \^crc_imd0173_out\
    );
\crc_imd[11]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \crc_imd[1]_i_22_n_0\,
      I1 => \crc_imd[13]_i_14_n_0\,
      I2 => \crc_imd[15]_i_63_n_0\,
      O => crc_imd083_out
    );
\crc_imd[11]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => AXIS_tdata(17),
      I1 => AXIS_tdata(31),
      I2 => \crc_imd[15]_i_34_n_0\,
      I3 => \crc_imd[12]_i_3\,
      I4 => \crc_imd[11]_i_18_n_0\,
      O => \^crc_imd0115_out\
    );
\crc_imd[12]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[15]_0\(2),
      I1 => \retbuf_reg[15][7]\(10),
      I2 => \^recvaxis_tdata_sig_reg[15]_0\(0),
      I3 => AXIS_tdata(18),
      I4 => \retbuf_reg[15][7]\(8),
      I5 => AXIS_tdata(19),
      O => crc_imd067_out
    );
\crc_imd[12]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => AXIS_tdata(43),
      I1 => \crc_imd[15]_i_48_n_0\,
      I2 => AXIS_tdata(26),
      I3 => AXIS_tdata(23),
      I4 => AXIS_tdata(42),
      I5 => AXIS_tdata(24),
      O => \crc_imd[12]_i_11_n_0\
    );
\crc_imd[12]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(51),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(51),
      O => AXIS_tdata(51)
    );
\crc_imd[12]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"65AA65659A559A9A"
    )
        port map (
      I0 => \crc_imd[12]_i_17_n_0\,
      I1 => stateOp_reg,
      I2 => rxAXIS_tdata(50),
      I3 => \crc_imd_reg[4]\,
      I4 => \sendAXIL_rdata_reg[63]_0\(50),
      I5 => AXIS_tdata(30),
      O => \crc_imd[12]_i_13_n_0\
    );
\crc_imd[12]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(34),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(34),
      O => AXIS_tdata(34)
    );
\crc_imd[12]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(35),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(35),
      O => AXIS_tdata(35)
    );
\crc_imd[12]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(26),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(26),
      O => AXIS_tdata(26)
    );
\crc_imd[12]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(34),
      I1 => rxAXIS_tdata(34),
      I2 => \sendAXIL_rdata_reg[63]_0\(32),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(32),
      I5 => stateOp_reg,
      O => \crc_imd[12]_i_17_n_0\
    );
\crc_imd[12]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(2),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(2),
      O => \^recvaxis_tdata_sig_reg[15]_0\(2)
    );
\crc_imd[12]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \crc_imd[1]_i_20_n_0\,
      I1 => \crc_imd[2]_i_6_n_0\,
      I2 => \crc_imd[12]_i_11_n_0\,
      O => crc_imd0150_out
    );
\crc_imd[12]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => AXIS_tdata(51),
      I1 => AXIS_tdata(17),
      I2 => \crc_imd[12]_i_13_n_0\,
      I3 => \crc_imd[1]_i_21_n_0\,
      I4 => \crc_imd[14]_i_5\,
      I5 => \crc_imd[12]_i_3\,
      O => \^crc_imd0174_out\
    );
\crc_imd[12]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => AXIS_tdata(27),
      I1 => \crc_imd[12]_i_3_0\,
      I2 => \crc_imd[9]_i_13_n_0\,
      I3 => \crc_imd[8]_i_12_n_0\,
      O => crc_imd085_out
    );
\crc_imd[12]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[15]_i_47_n_0\,
      I1 => \crc_imd[1]_i_12_n_0\,
      I2 => AXIS_tdata(34),
      I3 => AXIS_tdata(16),
      I4 => AXIS_tdata(35),
      I5 => AXIS_tdata(18),
      O => \^crc_imd0118_out\
    );
\crc_imd[13]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[15]_0\(1),
      I1 => \retbuf_reg[15][7]\(11),
      I2 => \^recvaxis_tdata_sig_reg[15]_0\(3),
      I3 => AXIS_tdata(20),
      I4 => \retbuf_reg[15][7]\(9),
      I5 => AXIS_tdata(19),
      O => crc_imd068_out
    );
\crc_imd[13]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => AXIS_tdata(43),
      I1 => \crc_imd[9]_i_12_n_0\,
      I2 => AXIS_tdata(23),
      I3 => AXIS_tdata(27),
      I4 => AXIS_tdata(44),
      I5 => AXIS_tdata(25),
      O => \crc_imd[13]_i_11_n_0\
    );
\crc_imd[13]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(51),
      I1 => rxAXIS_tdata(51),
      I2 => \sendAXIL_rdata_reg[63]_0\(52),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(52),
      I5 => stateOp_reg,
      O => \crc_imd[13]_i_12_n_0\
    );
\crc_imd[13]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(35),
      I1 => rxAXIS_tdata(35),
      I2 => \sendAXIL_rdata_reg[63]_0\(33),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(33),
      I5 => stateOp_reg,
      O => \crc_imd[13]_i_13_n_0\
    );
\crc_imd[13]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6966999969666966"
    )
        port map (
      I0 => \crc_imd[2]_i_6_n_0\,
      I1 => \retbuf_reg[15][7]\(15),
      I2 => stateOp_reg,
      I3 => \^recvaxis_tdata\(1),
      I4 => \crc_imd_reg[4]\,
      I5 => \sendAXIL_rdata_reg[63]_0\(7),
      O => \crc_imd[13]_i_14_n_0\
    );
\crc_imd[13]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(17),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(17),
      O => AXIS_tdata(17)
    );
\crc_imd[13]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(19),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(19),
      O => AXIS_tdata(19)
    );
\crc_imd[13]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(43),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(43),
      O => AXIS_tdata(43)
    );
\crc_imd[13]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(25),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(25),
      O => AXIS_tdata(25)
    );
\crc_imd[13]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(3),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(3),
      O => \^recvaxis_tdata_sig_reg[15]_0\(3)
    );
\crc_imd[13]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \crc_imd[7]_i_17_n_0\,
      I1 => \crc_imd[15]_i_48_n_0\,
      I2 => \crc_imd[13]_i_11_n_0\,
      O => crc_imd0151_out
    );
\crc_imd[13]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[13]_i_12_n_0\,
      I1 => \crc_imd[1]_i_9_n_0\,
      I2 => \^txaxis_tdata_reg[13]\,
      I3 => \crc_imd[13]_i_13_n_0\,
      I4 => \crc_imd[1]_i_21_n_0\,
      I5 => \crc_imd[15]_i_75_n_0\,
      O => crc_imd0175_out
    );
\crc_imd[13]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \crc_imd[0]_i_8_n_0\,
      I1 => \crc_imd[13]_i_14_n_0\,
      O => crc_imd086_out
    );
\crc_imd[13]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \crc_imd[15]_i_41_0\,
      I1 => AXIS_tdata(17),
      I2 => \crc_imd[14]_i_18_n_0\,
      I3 => \crc_imd[15]_i_47_n_0\,
      I4 => \crc_imd[1]_i_14_n_0\,
      O => crc_imd0121_out
    );
\crc_imd[14]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \crc_imd[14]_i_18_n_0\,
      I1 => \crc_imd[15]_i_75_n_0\,
      I2 => \crc_imd[14]_i_19_n_0\,
      O => crc_imd0176_out
    );
\crc_imd[14]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \crc_imd[14]_i_5\,
      I1 => \crc_imd[4]_i_6_n_0\,
      I2 => AXIS_tdata(28),
      I3 => AXIS_tdata(29),
      O => crc_imd087_out
    );
\crc_imd[14]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => AXIS_tdata(37),
      I1 => AXIS_tdata(20),
      I2 => \crc_imd[1]_i_10_n_0\,
      I3 => \crc_imd[15]_i_47_n_0\,
      I4 => \crc_imd[14]_i_22_n_0\,
      O => crc_imd0124_out
    );
\crc_imd[14]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[15]_0\(2),
      I1 => \retbuf_reg[15][7]\(12),
      I2 => \^recvaxis_tdata_sig_reg[15]_0\(4),
      I3 => AXIS_tdata(21),
      I4 => AXIS_tdata(20),
      I5 => \retbuf_reg[15][7]\(10),
      O => crc_imd069_out
    );
\crc_imd[14]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(44),
      I1 => rxAXIS_tdata(44),
      I2 => \sendAXIL_rdata_reg[63]_0\(28),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(28),
      I5 => stateOp_reg,
      O => \crc_imd[14]_i_16_n_0\
    );
\crc_imd[14]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"65AA65659A559A9A"
    )
        port map (
      I0 => \retbuf_reg[15][7]\(10),
      I1 => stateOp_reg,
      I2 => rxAXIS_tdata(2),
      I3 => \crc_imd_reg[4]\,
      I4 => \sendAXIL_rdata_reg[63]_0\(2),
      I5 => AXIS_tdata(19),
      O => \crc_imd[14]_i_18_n_0\
    );
\crc_imd[14]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => AXIS_tdata(36),
      I1 => \crc_imd[1]_i_24_n_0\,
      I2 => AXIS_tdata(34),
      I3 => AXIS_tdata(16),
      I4 => AXIS_tdata(53),
      I5 => AXIS_tdata(52),
      O => \crc_imd[14]_i_19_n_0\
    );
\crc_imd[14]_i_20\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(28),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(28),
      O => AXIS_tdata(28)
    );
\crc_imd[14]_i_21\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(37),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(37),
      O => AXIS_tdata(37)
    );
\crc_imd[14]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(36),
      I1 => rxAXIS_tdata(36),
      I2 => \sendAXIL_rdata_reg[63]_0\(18),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(18),
      I5 => stateOp_reg,
      O => \crc_imd[14]_i_22_n_0\
    );
\crc_imd[14]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(36),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(36),
      O => AXIS_tdata(36)
    );
\crc_imd[14]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(52),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(52),
      O => AXIS_tdata(52)
    );
\crc_imd[14]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FF20"
    )
        port map (
      I0 => \^recvaxis_tlast\,
      I1 => stateOp_reg,
      I2 => \^staterecv_reg[0]_0\,
      I3 => crcAXIS_tlast_sig_reg_3,
      I4 => \crc_imd_reg[0]_0\,
      O => \^recvaxis_tlast_sig_reg_0\
    );
\crc_imd[14]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(4),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(4),
      O => \^recvaxis_tdata_sig_reg[15]_0\(4)
    );
\crc_imd[14]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(5),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(5),
      O => \^recvaxis_tdata_sig_reg[15]_0\(5)
    );
\crc_imd[14]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[8]_i_12_n_0\,
      I1 => AXIS_tdata(45),
      I2 => \crc_imd[15]_i_48_n_0\,
      I3 => \crc_imd[14]_i_16_n_0\,
      I4 => \crc_imd[7]_i_17_n_0\,
      I5 => \crc_imd[14]_i_5_0\,
      O => crc_imd0152_out
    );
\crc_imd[15]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[2]_2\,
      I1 => \crc_imd[15]_i_33_n_0\,
      I2 => \crc_imd[15]_i_34_n_0\,
      I3 => \crc_imd[15]_i_35_n_0\,
      I4 => \crc_imd[15]_i_36_n_0\,
      I5 => \crc_imd[15]_i_37_n_0\,
      O => \crc_imd[15]_i_10_n_0\
    );
\crc_imd[15]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF8228"
    )
        port map (
      I0 => \crc_imd_reg[1]\,
      I1 => \crc_imd[15]_i_38_n_0\,
      I2 => \crc_imd[15]_i_39_n_0\,
      I3 => \crc_imd[15]_i_40_n_0\,
      I4 => \crc_imd[15]_i_41_n_0\,
      I5 => \crc_imd[15]_i_42_n_0\,
      O => \crc_imd[15]_i_11_n_0\
    );
\crc_imd[15]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2222222222222A22"
    )
        port map (
      I0 => \crc_imd_reg[0]\(0),
      I1 => \crc_imd_reg[4]\,
      I2 => stateRecv(1),
      I3 => stateRecv(2),
      I4 => stateRecv(0),
      I5 => stateOp_reg,
      O => \crcAXIS_tkeep_reg[0]\
    );
\crc_imd[15]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6966999969666966"
    )
        port map (
      I0 => \crc_imd[1]_i_13_n_0\,
      I1 => \retbuf_reg[15][7]\(15),
      I2 => stateOp_reg,
      I3 => \^recvaxis_tdata\(1),
      I4 => \crc_imd_reg[4]\,
      I5 => \sendAXIL_rdata_reg[63]_0\(7),
      O => \crc_imd[15]_i_16_n_0\
    );
\crc_imd[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \crc_imd[15]_i_47_n_0\,
      I1 => \crc_imd[1]_i_10_n_0\,
      I2 => \crc_imd[1]_i_8_n_0\,
      O => \crc_imd[15]_i_17_n_0\
    );
\crc_imd[15]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \crc_imd[15]_i_21_n_0\,
      I1 => \crc_imd_reg[1]_1\,
      O => \crc_imd[15]_i_18_n_0\
    );
\crc_imd[15]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DD0D22F2"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(6),
      I1 => \crc_imd_reg[4]\,
      I2 => rxAXIS_tdata(6),
      I3 => stateOp_reg,
      I4 => \retbuf_reg[15][7]\(14),
      O => \crc_imd[15]_i_19_n_0\
    );
\crc_imd[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \crc_imd[15]_i_6_n_0\,
      I1 => \crc_imd[15]_i_7_n_0\,
      I2 => \crc_imd[15]_i_8_n_0\,
      I3 => \crc_imd[15]_i_9_n_0\,
      I4 => \crc_imd[15]_i_10_n_0\,
      I5 => \crc_imd[15]_i_11_n_0\,
      O => \crc_imd_reg[7]_1\(6)
    );
\crc_imd[15]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[15]_i_48_n_0\,
      I1 => \crc_imd[7]_i_16_n_0\,
      I2 => \crc_imd[12]_i_3_0\,
      I3 => \crc_imd[2]_i_6_n_0\,
      I4 => \crc_imd[15]_i_41_0\,
      I5 => \crc_imd[1]_i_24_n_0\,
      O => \crc_imd[15]_i_21_n_0\
    );
\crc_imd[15]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(27),
      I1 => rxAXIS_tdata(27),
      I2 => \sendAXIL_rdata_reg[63]_0\(28),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(28),
      I5 => stateOp_reg,
      O => \crc_imd[15]_i_22_n_0\
    );
\crc_imd[15]_i_23\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \crc_imd[15]_i_35_n_0\,
      I1 => \crc_imd[15]_i_51_n_0\,
      O => \crc_imd[15]_i_23_n_0\
    );
\crc_imd[15]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(30),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(30),
      O => AXIS_tdata(30)
    );
\crc_imd[15]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DD0D22F2"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(13),
      I1 => \crc_imd_reg[4]\,
      I2 => rxAXIS_tdata(13),
      I3 => stateOp_reg,
      I4 => \retbuf_reg[15][7]\(5),
      O => \^txaxis_tdata_reg[13]\
    );
\crc_imd[15]_i_27\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \crc_imd_reg[1]_1\,
      I1 => \crc_imd[9]_i_13_n_0\,
      I2 => \crc_imd[7]_i_17_n_0\,
      O => \crc_imd[15]_i_27_n_0\
    );
\crc_imd[15]_i_28\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => AXIS_tdata(59),
      I1 => \crc_imd[15]_i_53_n_0\,
      I2 => \crc_imd[8]_i_11_n_0\,
      I3 => \crc_imd[15]_i_54_n_0\,
      O => \crc_imd[15]_i_28_n_0\
    );
\crc_imd[15]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[15]_i_55_n_0\,
      I1 => \crc_imd[1]_i_24_n_0\,
      I2 => AXIS_tdata(20),
      I3 => AXIS_tdata(54),
      I4 => AXIS_tdata(18),
      I5 => AXIS_tdata(56),
      O => \crc_imd[15]_i_29_n_0\
    );
\crc_imd[15]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[15]_i_60_n_0\,
      I1 => \crc_imd[15]_i_61_n_0\,
      I2 => \crc_imd[15]_i_62_n_0\,
      I3 => \crc_imd[1]_i_20_n_0\,
      I4 => \crc_imd[15]_i_63_n_0\,
      I5 => \crc_imd[1]_i_15_n_0\,
      O => \crc_imd[15]_i_30_n_0\
    );
\crc_imd[15]_i_31\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \crc_imd[15]_i_64_n_0\,
      I1 => \crc_imd[15]_i_33_n_0\,
      I2 => \crc_imd[15]_i_65_n_0\,
      O => \crc_imd[15]_i_31_n_0\
    );
\crc_imd[15]_i_33\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A6A655A6"
    )
        port map (
      I0 => \crc_imd[15]_i_66_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(55),
      I2 => \crc_imd_reg[4]\,
      I3 => rxAXIS_tdata(55),
      I4 => stateOp_reg,
      O => \crc_imd[15]_i_33_n_0\
    );
\crc_imd[15]_i_34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6966999969666966"
    )
        port map (
      I0 => \crc_imd[1]_i_12_n_0\,
      I1 => \retbuf_reg[15][7]\(5),
      I2 => stateOp_reg,
      I3 => rxAXIS_tdata(13),
      I4 => \crc_imd_reg[4]\,
      I5 => \sendAXIL_rdata_reg[63]_0\(13),
      O => \crc_imd[15]_i_34_n_0\
    );
\crc_imd[15]_i_35\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[15]_i_62_n_0\,
      I1 => \crc_imd[15]_i_61_n_0\,
      I2 => \crc_imd[1]_i_20_n_0\,
      I3 => \crc_imd[15]_i_63_n_0\,
      I4 => \crc_imd[15]_i_67_n_0\,
      I5 => \crc_imd[15]_i_68_n_0\,
      O => \crc_imd[15]_i_35_n_0\
    );
\crc_imd[15]_i_36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[14]_i_5\,
      I1 => \crc_imd[7]_i_11_n_0\,
      I2 => AXIS_tdata(47),
      I3 => AXIS_tdata(48),
      I4 => \crc_imd[12]_i_3_0\,
      I5 => \crc_imd[15]_i_48_n_0\,
      O => \crc_imd[15]_i_36_n_0\
    );
\crc_imd[15]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6966999969666966"
    )
        port map (
      I0 => \crc_imd[15]_i_39_n_0\,
      I1 => AXIS_tdata(54),
      I2 => stateOp_reg,
      I3 => rxAXIS_tdata(53),
      I4 => \crc_imd_reg[4]\,
      I5 => \sendAXIL_rdata_reg[63]_0\(53),
      O => \crc_imd[15]_i_37_n_0\
    );
\crc_imd[15]_i_38\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \crc_imd[1]_i_15_n_0\,
      I1 => \crc_imd[15]_i_21_n_0\,
      I2 => \crc_imd_reg[1]_1\,
      I3 => AXIS_tdata(45),
      I4 => AXIS_tdata(47),
      O => \crc_imd[15]_i_38_n_0\
    );
\crc_imd[15]_i_39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F44B0BBB0BB4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(46),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(46),
      I4 => \crc_imd[15]_i_71_n_0\,
      I5 => \crc_imd[15]_i_51_n_0\,
      O => \crc_imd[15]_i_39_n_0\
    );
\crc_imd[15]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => stateRecv(0),
      I1 => stateRecv(2),
      I2 => stateRecv(1),
      O => \^staterecv_reg[0]_0\
    );
\crc_imd[15]_i_40\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[15]_i_62_n_0\,
      I1 => \crc_imd[15]_i_72_n_0\,
      I2 => \crc_imd[15]_i_73_n_0\,
      I3 => AXIS_tdata(38),
      I4 => \crc_imd[15]_i_75_n_0\,
      I5 => \crc_imd[12]_i_3\,
      O => \crc_imd[15]_i_40_n_0\
    );
\crc_imd[15]_i_41\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28828228"
    )
        port map (
      I0 => \crc_imd_reg[0]_1\,
      I1 => \crc_imd[1]_i_25_n_0\,
      I2 => \crc_imd[15]_i_21_n_0\,
      I3 => \crc_imd[1]_i_4_0\,
      I4 => AXIS_tdata(16),
      O => \crc_imd[15]_i_41_n_0\
    );
\crc_imd[15]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[1]_0\,
      I1 => \crc_imd[15]_i_67_n_0\,
      I2 => \crc_imd[15]_i_77_n_0\,
      I3 => \crc_imd[15]_i_78_n_0\,
      I4 => \crc_imd[1]_i_18_n_0\,
      I5 => \crc_imd[15]_i_79_n_0\,
      O => \crc_imd[15]_i_42_n_0\
    );
\crc_imd[15]_i_47\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F44B0BBB0BB4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => \^recvaxis_tdata\(0),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(0),
      I4 => \retbuf_reg[15][7]\(8),
      I5 => \crc_imd[1]_i_9_n_0\,
      O => \crc_imd[15]_i_47_n_0\
    );
\crc_imd[15]_i_48\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DD0D22F2"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(8),
      I1 => \crc_imd_reg[4]\,
      I2 => rxAXIS_tdata(8),
      I3 => stateOp_reg,
      I4 => \retbuf_reg[15][7]\(0),
      O => \crc_imd[15]_i_48_n_0\
    );
\crc_imd[15]_i_51\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => AXIS_tdata(24),
      I1 => \crc_imd[1]_i_22_n_0\,
      I2 => \crc_imd[1]_i_21_n_0\,
      I3 => \crc_imd[11]_i_18_n_0\,
      I4 => AXIS_tdata(32),
      I5 => \crc_imd[1]_i_14_n_0\,
      O => \crc_imd[15]_i_51_n_0\
    );
\crc_imd[15]_i_52\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(59),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(59),
      O => AXIS_tdata(59)
    );
\crc_imd[15]_i_53\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(58),
      I1 => rxAXIS_tdata(58),
      I2 => \sendAXIL_rdata_reg[63]_0\(57),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(57),
      I5 => stateOp_reg,
      O => \crc_imd[15]_i_53_n_0\
    );
\crc_imd[15]_i_54\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(61),
      I1 => rxAXIS_tdata(61),
      I2 => \sendAXIL_rdata_reg[63]_0\(60),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(60),
      I5 => stateOp_reg,
      O => \crc_imd[15]_i_54_n_0\
    );
\crc_imd[15]_i_55\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DD0D22F2"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(3),
      I1 => \crc_imd_reg[4]\,
      I2 => rxAXIS_tdata(3),
      I3 => stateOp_reg,
      I4 => \retbuf_reg[15][7]\(11),
      O => \crc_imd[15]_i_55_n_0\
    );
\crc_imd[15]_i_56\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(20),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(20),
      O => AXIS_tdata(20)
    );
\crc_imd[15]_i_57\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(54),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(54),
      O => AXIS_tdata(54)
    );
\crc_imd[15]_i_58\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(18),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(18),
      O => AXIS_tdata(18)
    );
\crc_imd[15]_i_59\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(56),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(56),
      O => AXIS_tdata(56)
    );
\crc_imd[15]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF9600"
    )
        port map (
      I0 => \retbuf_reg[15][7]\(7),
      I1 => \crc_imd[15]_i_16_n_0\,
      I2 => \crc_imd[15]_i_17_n_0\,
      I3 => \crc_imd_reg[9]\,
      I4 => \^recvaxis_tlast_sig_reg_0\,
      O => \crc_imd[15]_i_6_n_0\
    );
\crc_imd[15]_i_60\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => AXIS_tdata(32),
      I1 => \crc_imd[11]_i_18_n_0\,
      I2 => \crc_imd[1]_i_21_n_0\,
      I3 => \crc_imd[1]_i_22_n_0\,
      I4 => AXIS_tdata(24),
      O => \crc_imd[15]_i_60_n_0\
    );
\crc_imd[15]_i_61\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(37),
      I1 => rxAXIS_tdata(37),
      I2 => \sendAXIL_rdata_reg[63]_0\(38),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(38),
      I5 => stateOp_reg,
      O => \crc_imd[15]_i_61_n_0\
    );
\crc_imd[15]_i_62\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(21),
      I1 => rxAXIS_tdata(21),
      I2 => \sendAXIL_rdata_reg[63]_0\(39),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(39),
      I5 => stateOp_reg,
      O => \crc_imd[15]_i_62_n_0\
    );
\crc_imd[15]_i_63\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6696669699996696"
    )
        port map (
      I0 => \crc_imd[15]_i_19_n_0\,
      I1 => \crc_imd[9]_i_12_n_0\,
      I2 => \sendAXIL_rdata_reg[63]_0\(23),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(23),
      I5 => stateOp_reg,
      O => \crc_imd[15]_i_63_n_0\
    );
\crc_imd[15]_i_64\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6696669699996696"
    )
        port map (
      I0 => AXIS_tdata(45),
      I1 => AXIS_tdata(47),
      I2 => \sendAXIL_rdata_reg[63]_0\(48),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(48),
      I5 => stateOp_reg,
      O => \crc_imd[15]_i_64_n_0\
    );
\crc_imd[15]_i_65\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A6A655A6"
    )
        port map (
      I0 => \crc_imd[15]_i_71_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(46),
      I2 => \crc_imd_reg[4]\,
      I3 => rxAXIS_tdata(46),
      I4 => stateOp_reg,
      O => \crc_imd[15]_i_65_n_0\
    );
\crc_imd[15]_i_66\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \crc_imd[11]_i_16_n_0\,
      I1 => \crc_imd[13]_i_12_n_0\,
      O => \crc_imd[15]_i_66_n_0\
    );
\crc_imd[15]_i_67\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \crc_imd[9]_i_16_n_0\,
      I1 => \crc_imd[15]_i_75_n_0\,
      O => \crc_imd[15]_i_67_n_0\
    );
\crc_imd[15]_i_68\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \crc_imd[15]_i_73_n_0\,
      I1 => \crc_imd[15]_i_55_n_0\,
      I2 => \crc_imd[1]_i_9_n_0\,
      I3 => \crc_imd[12]_i_3\,
      O => \crc_imd[15]_i_68_n_0\
    );
\crc_imd[15]_i_69\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(47),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(47),
      O => AXIS_tdata(47)
    );
\crc_imd[15]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800000800080800"
    )
        port map (
      I0 => \crc_imd_reg[0]\(1),
      I1 => \crc_imd_reg[0]_0\,
      I2 => \crc_imd_reg[0]\(2),
      I3 => \crc_imd[15]_i_18_n_0\,
      I4 => \crc_imd[15]_i_17_n_0\,
      I5 => \crc_imd[15]_i_19_n_0\,
      O => \crc_imd[15]_i_7_n_0\
    );
\crc_imd[15]_i_70\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(48),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(48),
      O => AXIS_tdata(48)
    );
\crc_imd[15]_i_71\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6696669699996696"
    )
        port map (
      I0 => \crc_imd[5]_i_8_n_0\,
      I1 => \crc_imd[6]_i_11_n_0\,
      I2 => \sendAXIL_rdata_reg[63]_0\(40),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(40),
      I5 => stateOp_reg,
      O => \crc_imd[15]_i_71_n_0\
    );
\crc_imd[15]_i_72\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => AXIS_tdata(22),
      I1 => \crc_imd[1]_i_8_n_0\,
      I2 => AXIS_tdata(23),
      I3 => \crc_imd[9]_i_12_n_0\,
      I4 => \crc_imd[15]_i_19_n_0\,
      O => \crc_imd[15]_i_72_n_0\
    );
\crc_imd[15]_i_73\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DD0D22F2"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(2),
      I1 => \crc_imd_reg[4]\,
      I2 => rxAXIS_tdata(2),
      I3 => stateOp_reg,
      I4 => \retbuf_reg[15][7]\(10),
      O => \crc_imd[15]_i_73_n_0\
    );
\crc_imd[15]_i_74\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(38),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(38),
      O => AXIS_tdata(38)
    );
\crc_imd[15]_i_75\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(17),
      I1 => rxAXIS_tdata(17),
      I2 => \sendAXIL_rdata_reg[63]_0\(18),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(18),
      I5 => stateOp_reg,
      O => \crc_imd[15]_i_75_n_0\
    );
\crc_imd[15]_i_77\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F44B0BBB0BB4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(24),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(24),
      I4 => \crc_imd[1]_i_22_n_0\,
      I5 => \crc_imd[1]_i_21_n_0\,
      O => \crc_imd[15]_i_77_n_0\
    );
\crc_imd[15]_i_78\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6966999969666966"
    )
        port map (
      I0 => \crc_imd[15]_i_47_n_0\,
      I1 => \retbuf_reg[15][7]\(10),
      I2 => stateOp_reg,
      I3 => rxAXIS_tdata(2),
      I4 => \crc_imd_reg[4]\,
      I5 => \sendAXIL_rdata_reg[63]_0\(2),
      O => \crc_imd[15]_i_78_n_0\
    );
\crc_imd[15]_i_79\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \crc_imd_reg[1]_1\,
      I1 => \crc_imd[15]_i_21_n_0\,
      I2 => \crc_imd[1]_i_15_n_0\,
      O => \crc_imd[15]_i_79_n_0\
    );
\crc_imd[15]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[0]_2\,
      I1 => \crc_imd[15]_i_21_n_0\,
      I2 => \crc_imd[15]_i_22_n_0\,
      I3 => \crc_imd[15]_i_23_n_0\,
      I4 => AXIS_tdata(30),
      I5 => \^txaxis_tdata_reg[13]\,
      O => \crc_imd[15]_i_8_n_0\
    );
\crc_imd[15]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[8]_1\,
      I1 => \crc_imd[15]_i_27_n_0\,
      I2 => \crc_imd[15]_i_28_n_0\,
      I3 => \crc_imd[15]_i_29_n_0\,
      I4 => \crc_imd[15]_i_30_n_0\,
      I5 => \crc_imd[15]_i_31_n_0\,
      O => \crc_imd[15]_i_9_n_0\
    );
\crc_imd[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \crc_imd[1]_i_2_n_0\,
      I1 => \crc_imd[1]_i_3_n_0\,
      I2 => \crc_imd[1]_i_4_n_0\,
      I3 => \crc_imd[1]_i_5_n_0\,
      I4 => \crc_imd[1]_i_6_n_0\,
      I5 => \crc_imd[1]_i_7_n_0\,
      O => \crc_imd_reg[7]_1\(1)
    );
\crc_imd[1]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"65AA65659A559A9A"
    )
        port map (
      I0 => \retbuf_reg[15][7]\(11),
      I1 => stateOp_reg,
      I2 => rxAXIS_tdata(3),
      I3 => \crc_imd_reg[4]\,
      I4 => \sendAXIL_rdata_reg[63]_0\(3),
      I5 => \crc_imd[15]_i_73_n_0\,
      O => \crc_imd[1]_i_10_n_0\
    );
\crc_imd[1]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"65AA65659A559A9A"
    )
        port map (
      I0 => \crc_imd[1]_i_24_n_0\,
      I1 => stateOp_reg,
      I2 => \^recvaxis_tdata\(5),
      I3 => \crc_imd_reg[4]\,
      I4 => \sendAXIL_rdata_reg[63]_0\(15),
      I5 => \retbuf_reg[15][7]\(7),
      O => \crc_imd[1]_i_12_n_0\
    );
\crc_imd[1]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6966999969666966"
    )
        port map (
      I0 => \crc_imd[9]_i_12_n_0\,
      I1 => \retbuf_reg[15][7]\(14),
      I2 => stateOp_reg,
      I3 => rxAXIS_tdata(6),
      I4 => \crc_imd_reg[4]\,
      I5 => \sendAXIL_rdata_reg[63]_0\(6),
      O => \crc_imd[1]_i_13_n_0\
    );
\crc_imd[1]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(36),
      I1 => rxAXIS_tdata(36),
      I2 => \sendAXIL_rdata_reg[63]_0\(35),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(35),
      I5 => stateOp_reg,
      O => \crc_imd[1]_i_14_n_0\
    );
\crc_imd[1]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"65AA65659A559A9A"
    )
        port map (
      I0 => AXIS_tdata(30),
      I1 => stateOp_reg,
      I2 => rxAXIS_tdata(29),
      I3 => \crc_imd_reg[4]\,
      I4 => \sendAXIL_rdata_reg[63]_0\(29),
      I5 => \crc_imd[15]_i_22_n_0\,
      O => \crc_imd[1]_i_15_n_0\
    );
\crc_imd[1]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[6]_i_12_n_0\,
      I1 => \crc_imd[11]_i_18_n_0\,
      I2 => \crc_imd[0]_i_15_n_0\,
      I3 => \crc_imd[9]_i_13_n_0\,
      I4 => \crc_imd[7]_i_17_n_0\,
      I5 => \crc_imd[1]_i_4_0\,
      O => \crc_imd[1]_i_16_n_0\
    );
\crc_imd[1]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[15]_i_28_n_0\,
      I1 => \crc_imd[15]_i_79_n_0\,
      I2 => \crc_imd[15]_i_66_n_0\,
      I3 => \crc_imd[1]_i_27_n_0\,
      I4 => \crc_imd[8]_i_19_n_0\,
      I5 => \crc_imd[15]_i_64_n_0\,
      O => \crc_imd[1]_i_17_n_0\
    );
\crc_imd[1]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A6A655A6"
    )
        port map (
      I0 => \crc_imd[15]_i_63_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(22),
      I2 => \crc_imd_reg[4]\,
      I3 => rxAXIS_tdata(22),
      I4 => stateOp_reg,
      O => \crc_imd[1]_i_18_n_0\
    );
\crc_imd[1]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[15]_i_35_n_0\,
      I1 => \crc_imd[15]_i_33_n_0\,
      I2 => \crc_imd[14]_i_5\,
      I3 => AXIS_tdata(45),
      I4 => \crc_imd[15]_i_21_n_0\,
      I5 => \crc_imd[15]_i_22_n_0\,
      O => \crc_imd[1]_i_19_n_0\
    );
\crc_imd[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF69960000"
    )
        port map (
      I0 => \crc_imd[1]_i_8_n_0\,
      I1 => \crc_imd[1]_i_9_n_0\,
      I2 => \crc_imd[1]_i_10_n_0\,
      I3 => \crc_imd[15]_i_16_n_0\,
      I4 => \crc_imd_reg[9]\,
      I5 => \^recvaxis_tlast_sig_reg_0\,
      O => \crc_imd[1]_i_2_n_0\
    );
\crc_imd[1]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A6A655A6"
    )
        port map (
      I0 => \crc_imd[1]_i_8_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(22),
      I2 => \crc_imd_reg[4]\,
      I3 => rxAXIS_tdata(22),
      I4 => stateOp_reg,
      O => \crc_imd[1]_i_20_n_0\
    );
\crc_imd[1]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(16),
      I1 => rxAXIS_tdata(16),
      I2 => \sendAXIL_rdata_reg[63]_0\(31),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(31),
      I5 => stateOp_reg,
      O => \crc_imd[1]_i_21_n_0\
    );
\crc_imd[1]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(25),
      I1 => rxAXIS_tdata(25),
      I2 => \sendAXIL_rdata_reg[63]_0\(26),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(26),
      I5 => stateOp_reg,
      O => \crc_imd[1]_i_22_n_0\
    );
\crc_imd[1]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \crc_imd[15]_i_79_n_0\,
      I1 => \crc_imd[1]_i_10_n_0\,
      I2 => \crc_imd[15]_i_47_n_0\,
      I3 => \crc_imd[9]_i_16_n_0\,
      I4 => \crc_imd[15]_i_75_n_0\,
      O => \crc_imd[1]_i_23_n_0\
    );
\crc_imd[1]_i_24\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DD0D22F2"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(14),
      I1 => \crc_imd_reg[4]\,
      I2 => rxAXIS_tdata(14),
      I3 => stateOp_reg,
      I4 => \retbuf_reg[15][7]\(6),
      O => \crc_imd[1]_i_24_n_0\
    );
\crc_imd[1]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[1]_i_20_n_0\,
      I1 => \crc_imd[15]_i_63_n_0\,
      I2 => \crc_imd[15]_i_67_n_0\,
      I3 => \crc_imd[15]_i_47_n_0\,
      I4 => \crc_imd[1]_i_10_n_0\,
      I5 => AXIS_tdata(21),
      O => \crc_imd[1]_i_25_n_0\
    );
\crc_imd[1]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[15]_i_38_n_0\,
      I1 => \crc_imd[1]_i_28_n_0\,
      I2 => \crc_imd[1]_i_29_n_0\,
      I3 => \crc_imd[15]_i_19_n_0\,
      I4 => AXIS_tdata(23),
      I5 => \crc_imd[15]_i_51_n_0\,
      O => \myCrc/crc_imd0132_out\
    );
\crc_imd[1]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"65AA65659A559A9A"
    )
        port map (
      I0 => \crc_imd[15]_i_75_n_0\,
      I1 => stateOp_reg,
      I2 => \^recvaxis_tdata\(0),
      I3 => \crc_imd_reg[4]\,
      I4 => \sendAXIL_rdata_reg[63]_0\(0),
      I5 => \retbuf_reg[15][7]\(8),
      O => \crc_imd[1]_i_27_n_0\
    );
\crc_imd[1]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[15]_i_67_n_0\,
      I1 => \crc_imd[15]_i_61_n_0\,
      I2 => \crc_imd[1]_i_8_n_0\,
      I3 => AXIS_tdata(46),
      I4 => \crc_imd[15]_i_47_n_0\,
      I5 => \crc_imd[15]_i_73_n_0\,
      O => \crc_imd[1]_i_28_n_0\
    );
\crc_imd[1]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"65AA65659A559A9A"
    )
        port map (
      I0 => AXIS_tdata(44),
      I1 => stateOp_reg,
      I2 => rxAXIS_tdata(42),
      I3 => \crc_imd_reg[4]\,
      I4 => \sendAXIL_rdata_reg[63]_0\(42),
      I5 => \crc_imd[5]_i_8_n_0\,
      O => \crc_imd[1]_i_29_n_0\
    );
\crc_imd[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[2]_0\,
      I1 => \crc_imd_reg[1]_1\,
      I2 => \crc_imd[1]_i_12_n_0\,
      I3 => \crc_imd[15]_i_17_n_0\,
      I4 => \crc_imd[1]_i_13_n_0\,
      I5 => \crc_imd[7]_i_17_n_0\,
      O => \crc_imd[1]_i_3_n_0\
    );
\crc_imd[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28828228"
    )
        port map (
      I0 => \crc_imd_reg[0]_2\,
      I1 => \crc_imd[1]_i_14_n_0\,
      I2 => \crc_imd[1]_i_15_n_0\,
      I3 => \crc_imd[15]_i_35_n_0\,
      I4 => \crc_imd[1]_i_16_n_0\,
      O => \crc_imd[1]_i_4_n_0\
    );
\crc_imd[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"90FFFF6090609060"
    )
        port map (
      I0 => \crc_imd[1]_i_17_n_0\,
      I1 => \crc_imd[1]_i_18_n_0\,
      I2 => \crc_imd_reg[8]_1\,
      I3 => \crc_imd[15]_i_37_n_0\,
      I4 => \crc_imd[1]_i_19_n_0\,
      I5 => \crc_imd_reg[2]_2\,
      O => \crc_imd[1]_i_5_n_0\
    );
\crc_imd[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[1]_0\,
      I1 => \crc_imd[1]_i_20_n_0\,
      I2 => \crc_imd[1]_i_21_n_0\,
      I3 => AXIS_tdata(21),
      I4 => \crc_imd[1]_i_22_n_0\,
      I5 => \crc_imd[1]_i_23_n_0\,
      O => \crc_imd[1]_i_6_n_0\
    );
\crc_imd[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF960096009600"
    )
        port map (
      I0 => \crc_imd[1]_i_24_n_0\,
      I1 => \crc_imd[15]_i_27_n_0\,
      I2 => \crc_imd[1]_i_25_n_0\,
      I3 => \crc_imd_reg[0]_1\,
      I4 => \myCrc/crc_imd0132_out\,
      I5 => \crc_imd_reg[1]\,
      O => \crc_imd[1]_i_7_n_0\
    );
\crc_imd[1]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DD0D22F2"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(4),
      I1 => \crc_imd_reg[4]\,
      I2 => rxAXIS_tdata(4),
      I3 => stateOp_reg,
      I4 => \retbuf_reg[15][7]\(12),
      O => \crc_imd[1]_i_8_n_0\
    );
\crc_imd[1]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DD0D22F2"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(1),
      I1 => \crc_imd_reg[4]\,
      I2 => rxAXIS_tdata(1),
      I3 => stateOp_reg,
      I4 => \retbuf_reg[15][7]\(9),
      O => \crc_imd[1]_i_9_n_0\
    );
\crc_imd[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFEA"
    )
        port map (
      I0 => \crc_imd[2]_i_2_n_0\,
      I1 => \^crc_imd041_out\,
      I2 => \crc_imd_reg[2]_0\,
      I3 => \crc_imd[2]_i_4_n_0\,
      I4 => \crc_imd_reg[2]_1\,
      O => \crc_imd_reg[7]_1\(2)
    );
\crc_imd[2]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(39),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(39),
      O => AXIS_tdata(39)
    );
\crc_imd[2]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(57),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(57),
      O => AXIS_tdata(57)
    );
\crc_imd[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF69960000"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[15]_0\(1),
      I1 => \^recvaxis_tdata_sig_reg[15]_0\(0),
      I2 => \retbuf_reg[15][7]\(9),
      I3 => \retbuf_reg[15][7]\(8),
      I4 => \crc_imd_reg[9]\,
      I5 => \^recvaxis_tlast_sig_reg_0\,
      O => \crc_imd[2]_i_2_n_0\
    );
\crc_imd[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[15]_0\(6),
      I1 => \crc_imd[2]_i_6_n_0\,
      I2 => \retbuf_reg[15][7]\(14),
      I3 => AXIS_tdata(8),
      I4 => \retbuf_reg[15][7]\(0),
      O => \^crc_imd041_out\
    );
\crc_imd[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
        port map (
      I0 => \crc_imd_reg[2]_2\,
      I1 => \^crc_imd0172_out\,
      I2 => \crc_imd[2]_i_8_n_0\,
      I3 => \^crc_imd0112_out\,
      I4 => \crc_imd_reg[0]_2\,
      O => \crc_imd[2]_i_4_n_0\
    );
\crc_imd[2]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DD0D22F2"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(9),
      I1 => \crc_imd_reg[4]\,
      I2 => rxAXIS_tdata(9),
      I3 => stateOp_reg,
      I4 => \retbuf_reg[15][7]\(1),
      O => \crc_imd[2]_i_6_n_0\
    );
\crc_imd[2]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(8),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(8),
      O => AXIS_tdata(8)
    );
\crc_imd[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[8]_1\,
      I1 => \crc_imd[15]_i_61_n_0\,
      I2 => \crc_imd[14]_i_22_n_0\,
      I3 => \crc_imd[9]_i_12_n_0\,
      I4 => \crc_imd[1]_i_20_n_0\,
      I5 => \crc_imd[2]_i_9_n_0\,
      O => \crc_imd[2]_i_8_n_0\
    );
\crc_imd[2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => AXIS_tdata(56),
      I1 => \crc_imd[15]_i_47_n_0\,
      I2 => AXIS_tdata(39),
      I3 => AXIS_tdata(57),
      I4 => AXIS_tdata(40),
      I5 => AXIS_tdata(54),
      O => \crc_imd[2]_i_9_n_0\
    );
\crc_imd[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \^crc_imd042_out\,
      I1 => \crc_imd_reg[2]_0\,
      I2 => \crc_imd_reg[0]_2\,
      I3 => \^crc_imd0115_out\,
      I4 => \crc_imd[3]_i_5_n_0\,
      O => \crc_imd_reg[15]\
    );
\crc_imd[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF960096009600"
    )
        port map (
      I0 => \crc_imd[3]_i_6_n_0\,
      I1 => \crc_imd[15]_i_53_n_0\,
      I2 => \crc_imd[15]_i_61_n_0\,
      I3 => \crc_imd_reg[8]_1\,
      I4 => \^crc_imd0173_out\,
      I5 => \crc_imd_reg[2]_2\,
      O => \crc_imd[3]_i_5_n_0\
    );
\crc_imd[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[14]_i_18_n_0\,
      I1 => \crc_imd[3]_i_7_n_0\,
      I2 => AXIS_tdata(24),
      I3 => AXIS_tdata(41),
      I4 => \crc_imd[15]_i_63_n_0\,
      I5 => \crc_imd[1]_i_9_n_0\,
      O => \crc_imd[3]_i_6_n_0\
    );
\crc_imd[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(55),
      I1 => rxAXIS_tdata(55),
      I2 => \sendAXIL_rdata_reg[63]_0\(39),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(39),
      I5 => stateOp_reg,
      O => \crc_imd[3]_i_7_n_0\
    );
\crc_imd[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFEA"
    )
        port map (
      I0 => \crc_imd[4]_i_2_n_0\,
      I1 => \^crc_imd043_out\,
      I2 => \crc_imd_reg[2]_0\,
      I3 => \crc_imd[4]_i_4_n_0\,
      I4 => \crc_imd_reg[4]_0\,
      O => \crc_imd_reg[7]_1\(3)
    );
\crc_imd[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF69960000"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[15]_0\(2),
      I1 => \^recvaxis_tdata_sig_reg[15]_0\(3),
      I2 => \retbuf_reg[15][7]\(10),
      I3 => \retbuf_reg[15][7]\(11),
      I4 => \crc_imd_reg[9]\,
      I5 => \^recvaxis_tlast_sig_reg_0\,
      O => \crc_imd[4]_i_2_n_0\
    );
\crc_imd[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22F2DD0DDD0D22F2"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(11),
      I1 => \crc_imd_reg[4]\,
      I2 => \^recvaxis_tdata\(3),
      I3 => stateOp_reg,
      I4 => \retbuf_reg[15][7]\(3),
      I5 => \crc_imd[4]_i_6_n_0\,
      O => \^crc_imd043_out\
    );
\crc_imd[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
        port map (
      I0 => \crc_imd_reg[2]_2\,
      I1 => \^crc_imd0174_out\,
      I2 => \crc_imd[4]_i_7_n_0\,
      I3 => \^crc_imd0118_out\,
      I4 => \crc_imd_reg[0]_2\,
      O => \crc_imd[4]_i_4_n_0\
    );
\crc_imd[4]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DD0D22F2"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(10),
      I1 => \crc_imd_reg[4]\,
      I2 => \^recvaxis_tdata\(2),
      I3 => stateOp_reg,
      I4 => \retbuf_reg[15][7]\(2),
      O => \crc_imd[4]_i_6_n_0\
    );
\crc_imd[4]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[8]_1\,
      I1 => \crc_imd[1]_i_10_n_0\,
      I2 => \crc_imd[8]_i_19_n_0\,
      I3 => \crc_imd[15]_i_19_n_0\,
      I4 => \crc_imd[4]_i_8_n_0\,
      I5 => \crc_imd[11]_i_13_n_0\,
      O => \crc_imd[4]_i_7_n_0\
    );
\crc_imd[4]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => AXIS_tdata(42),
      I1 => AXIS_tdata(40),
      I2 => AXIS_tdata(58),
      I3 => AXIS_tdata(59),
      I4 => AXIS_tdata(38),
      I5 => AXIS_tdata(24),
      O => \crc_imd[4]_i_8_n_0\
    );
\crc_imd[4]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(58),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(58),
      O => AXIS_tdata(58)
    );
\crc_imd[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF69960000"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[15]_0\(4),
      I1 => \^recvaxis_tdata_sig_reg[15]_0\(3),
      I2 => \retbuf_reg[15][7]\(12),
      I3 => \retbuf_reg[15][7]\(11),
      I4 => \crc_imd_reg[9]\,
      I5 => \^recvaxis_tlast_sig_reg_0\,
      O => \crc_imd_reg[12]\
    );
\crc_imd[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[11]_i_12_n_0\,
      I1 => \crc_imd[1]_i_8_n_0\,
      I2 => \crc_imd[6]_i_12_n_0\,
      I3 => \crc_imd[5]_i_7_n_0\,
      I4 => \crc_imd[13]_i_14_n_0\,
      I5 => \crc_imd[5]_i_8_n_0\,
      O => crc_imd0198_out
    );
\crc_imd[5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(60),
      I1 => rxAXIS_tdata(60),
      I2 => \sendAXIL_rdata_reg[63]_0\(59),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(59),
      I5 => stateOp_reg,
      O => \crc_imd[5]_i_7_n_0\
    );
\crc_imd[5]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(43),
      I1 => rxAXIS_tdata(43),
      I2 => \sendAXIL_rdata_reg[63]_0\(41),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(41),
      I5 => stateOp_reg,
      O => \crc_imd[5]_i_8_n_0\
    );
\crc_imd[6]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6966999969666966"
    )
        port map (
      I0 => \crc_imd[1]_i_20_n_0\,
      I1 => \retbuf_reg[15][7]\(13),
      I2 => stateOp_reg,
      I3 => rxAXIS_tdata(5),
      I4 => \crc_imd_reg[4]\,
      I5 => \sendAXIL_rdata_reg[63]_0\(5),
      O => \crc_imd[6]_i_10_n_0\
    );
\crc_imd[6]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(42),
      I1 => rxAXIS_tdata(42),
      I2 => \sendAXIL_rdata_reg[63]_0\(44),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(44),
      I5 => stateOp_reg,
      O => \crc_imd[6]_i_11_n_0\
    );
\crc_imd[6]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A6A655A6"
    )
        port map (
      I0 => \crc_imd[1]_i_22_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(24),
      I2 => \crc_imd_reg[4]\,
      I3 => rxAXIS_tdata(24),
      I4 => stateOp_reg,
      O => \crc_imd[6]_i_12_n_0\
    );
\crc_imd[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF69960000"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[15]_0\(5),
      I1 => \^recvaxis_tdata_sig_reg[15]_0\(4),
      I2 => \retbuf_reg[15][7]\(12),
      I3 => \retbuf_reg[15][7]\(13),
      I4 => \crc_imd_reg[9]\,
      I5 => \^recvaxis_tlast_sig_reg_0\,
      O => \crc_imd_reg[12]_0\
    );
\crc_imd[6]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(13),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(13),
      O => \^recvaxis_tdata_sig_reg[15]_0\(10)
    );
\crc_imd[6]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => \^recvaxis_tdata\(4),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(12),
      O => \^recvaxis_tdata_sig_reg[15]_0\(9)
    );
\crc_imd[6]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[15]_i_54_n_0\,
      I1 => \crc_imd[6]_i_10_n_0\,
      I2 => \crc_imd[12]_i_3_0\,
      I3 => AXIS_tdata(27),
      I4 => \crc_imd[6]_i_11_n_0\,
      I5 => \crc_imd[6]_i_12_n_0\,
      O => crc_imd0200_out
    );
\crc_imd[7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF69960000"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[15]_0\(5),
      I1 => \^recvaxis_tdata_sig_reg[15]_0\(6),
      I2 => \retbuf_reg[15][7]\(13),
      I3 => \retbuf_reg[15][7]\(14),
      I4 => \crc_imd_reg[9]\,
      I5 => \^recvaxis_tlast_sig_reg_0\,
      O => \crc_imd_reg[13]\
    );
\crc_imd[7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(29),
      I1 => rxAXIS_tdata(29),
      I2 => \sendAXIL_rdata_reg[63]_0\(30),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(30),
      I5 => stateOp_reg,
      O => \crc_imd[7]_i_11_n_0\
    );
\crc_imd[7]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => \^recvaxis_tdata\(3),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(11),
      O => \^recvaxis_tdata_sig_reg[15]_0\(8)
    );
\crc_imd[7]_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(22),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(22),
      O => AXIS_tdata(22)
    );
\crc_imd[7]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(21),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(21),
      O => AXIS_tdata(21)
    );
\crc_imd[7]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DD0D22F2"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(7),
      I1 => \crc_imd_reg[4]\,
      I2 => \^recvaxis_tdata\(1),
      I3 => stateOp_reg,
      I4 => \retbuf_reg[15][7]\(15),
      O => \crc_imd[7]_i_16_n_0\
    );
\crc_imd[7]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F44B0BBB0BB4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => \^recvaxis_tdata\(2),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(10),
      I4 => \retbuf_reg[15][7]\(2),
      I5 => \crc_imd[2]_i_6_n_0\,
      O => \crc_imd[7]_i_17_n_0\
    );
\crc_imd[7]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(29),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(29),
      O => AXIS_tdata(29)
    );
\crc_imd[7]_i_19\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(27),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(27),
      O => AXIS_tdata(27)
    );
\crc_imd[7]_i_20\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(45),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(45),
      O => AXIS_tdata(45)
    );
\crc_imd[7]_i_21\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(46),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(46),
      O => AXIS_tdata(46)
    );
\crc_imd[7]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[15]_i_67_n_0\,
      I1 => \crc_imd[0]_i_12_n_0\,
      I2 => AXIS_tdata(35),
      I3 => AXIS_tdata(37),
      I4 => \crc_imd[15]_i_41_0\,
      I5 => \crc_imd[15]_i_55_n_0\,
      O => crc_imd0165_out
    );
\crc_imd[7]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[0]_i_8_n_0\,
      I1 => AXIS_tdata(43),
      I2 => AXIS_tdata(45),
      I3 => \crc_imd[7]_i_25_n_0\,
      I4 => \crc_imd[15]_i_63_n_0\,
      I5 => \crc_imd[1]_i_22_n_0\,
      O => crc_imd0202_out
    );
\crc_imd[7]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[1]_i_10_n_0\,
      I1 => \crc_imd[15]_i_61_n_0\,
      I2 => AXIS_tdata(19),
      I3 => AXIS_tdata(21),
      I4 => \crc_imd[1]_i_9_n_0\,
      I5 => \crc_imd[1]_i_8_n_0\,
      O => crc_imd0100_out
    );
\crc_imd[7]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(62),
      I1 => rxAXIS_tdata(62),
      I2 => \sendAXIL_rdata_reg[63]_0\(61),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(61),
      I5 => stateOp_reg,
      O => \crc_imd[7]_i_25_n_0\
    );
\crc_imd[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28828228"
    )
        port map (
      I0 => \crc_imd_reg[1]_0\,
      I1 => \retbuf_reg[15][7]\(3),
      I2 => \crc_imd[7]_i_11_n_0\,
      I3 => \^txaxis_tdata_reg[13]\,
      I4 => \^recvaxis_tdata_sig_reg[15]_0\(8),
      O => \crc_imd_reg[3]\
    );
\crc_imd[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[0]_1\,
      I1 => \retbuf_reg[15][7]\(11),
      I2 => \^recvaxis_tdata_sig_reg[15]_0\(3),
      I3 => AXIS_tdata(22),
      I4 => \crc_imd[9]_i_12_n_0\,
      I5 => AXIS_tdata(21),
      O => \crc_imd_reg[11]\
    );
\crc_imd[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[7]_i_16_n_0\,
      I1 => \crc_imd[7]_i_17_n_0\,
      I2 => AXIS_tdata(29),
      I3 => AXIS_tdata(27),
      I4 => AXIS_tdata(45),
      I5 => AXIS_tdata(46),
      O => \txAXIS_tdata_reg[7]\
    );
\crc_imd[7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(14),
      I1 => rxAXIS_tdata(14),
      I2 => \sendAXIL_rdata_reg[63]_0\(13),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(13),
      I5 => stateOp_reg,
      O => p_136_in
    );
\crc_imd[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \crc_imd_reg[8]\,
      I1 => \^recvaxis_tlast_sig_reg_0\,
      I2 => \crc_imd_reg[8]_0\,
      I3 => \crc_imd[8]_i_4_n_0\,
      I4 => \crc_imd[8]_i_5_n_0\,
      O => \crc_imd_reg[7]_1\(4)
    );
\crc_imd[8]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[14]_i_5\,
      I1 => \crc_imd[15]_i_22_n_0\,
      I2 => AXIS_tdata(44),
      I3 => AXIS_tdata(29),
      I4 => \crc_imd[9]_i_13_n_0\,
      I5 => AXIS_tdata(46),
      O => \crc_imd[8]_i_10_n_0\
    );
\crc_imd[8]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(63),
      I1 => rxAXIS_tdata(63),
      I2 => \sendAXIL_rdata_reg[63]_0\(62),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(62),
      I5 => stateOp_reg,
      O => \crc_imd[8]_i_11_n_0\
    );
\crc_imd[8]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A6A655A6"
    )
        port map (
      I0 => \crc_imd[15]_i_19_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(26),
      I2 => \crc_imd_reg[4]\,
      I3 => rxAXIS_tdata(26),
      I4 => stateOp_reg,
      O => \crc_imd[8]_i_12_n_0\
    );
\crc_imd[8]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[0]_2\,
      I1 => \crc_imd[9]_i_12_n_0\,
      I2 => \crc_imd[1]_i_20_n_0\,
      I3 => \crc_imd[8]_i_19_n_0\,
      I4 => \crc_imd[1]_i_10_n_0\,
      I5 => AXIS_tdata(38),
      O => \crc_imd[8]_i_13_n_0\
    );
\crc_imd[8]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[12]_i_3_0\,
      I1 => \crc_imd_reg[1]_1\,
      I2 => AXIS_tdata(30),
      I3 => AXIS_tdata(28),
      I4 => AXIS_tdata(47),
      I5 => AXIS_tdata(46),
      O => \myCrc/crc_imd0135_out\
    );
\crc_imd[8]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[15]_0\(4),
      I1 => \^recvaxis_tdata_sig_reg[15]_0\(6),
      I2 => AXIS_tdata(22),
      I3 => AXIS_tdata(23),
      I4 => \retbuf_reg[15][7]\(12),
      I5 => \retbuf_reg[15][7]\(14),
      O => \myCrc/p_31_out\(8)
    );
\crc_imd[8]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[1]_0\,
      I1 => AXIS_tdata(30),
      I2 => AXIS_tdata(31),
      I3 => \retbuf_reg[15][7]\(4),
      I4 => \^recvaxis_tdata_sig_reg[15]_0\(9),
      I5 => \crc_imd[1]_i_24_n_0\,
      O => \crc_imd[8]_i_16_n_0\
    );
\crc_imd[8]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[1]_i_8_n_0\,
      I1 => \crc_imd[12]_i_3\,
      I2 => AXIS_tdata(54),
      I3 => AXIS_tdata(38),
      I4 => AXIS_tdata(55),
      I5 => AXIS_tdata(21),
      O => \crc_imd[8]_i_17_n_0\
    );
\crc_imd[8]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(44),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(44),
      O => AXIS_tdata(44)
    );
\crc_imd[8]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(20),
      I1 => rxAXIS_tdata(20),
      I2 => \sendAXIL_rdata_reg[63]_0\(39),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(39),
      I5 => stateOp_reg,
      O => \crc_imd[8]_i_19_n_0\
    );
\crc_imd[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEAAEAEEA"
    )
        port map (
      I0 => \crc_imd[8]_i_9_n_0\,
      I1 => \crc_imd_reg[8]_1\,
      I2 => \crc_imd[8]_i_10_n_0\,
      I3 => \crc_imd[8]_i_11_n_0\,
      I4 => \crc_imd[8]_i_12_n_0\,
      I5 => \crc_imd[8]_i_13_n_0\,
      O => \crc_imd[8]_i_4_n_0\
    );
\crc_imd[8]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \crc_imd_reg[1]\,
      I1 => \myCrc/crc_imd0135_out\,
      I2 => \crc_imd_reg[0]_1\,
      I3 => \myCrc/p_31_out\(8),
      I4 => \crc_imd[8]_i_16_n_0\,
      O => \crc_imd[8]_i_5_n_0\
    );
\crc_imd[8]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => \^recvaxis_tdata\(1),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(7),
      O => \^recvaxis_tdata_sig_reg[15]_0\(7)
    );
\crc_imd[8]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(6),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(6),
      O => \^recvaxis_tdata_sig_reg[15]_0\(6)
    );
\crc_imd[8]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(14),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(14),
      O => \^recvaxis_tdata_sig_reg[15]_0\(11)
    );
\crc_imd[8]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \crc_imd_reg[2]_2\,
      I1 => \crc_imd[8]_i_17_n_0\,
      I2 => \crc_imd[9]_i_16_n_0\,
      I3 => \crc_imd[14]_i_22_n_0\,
      O => \crc_imd[8]_i_9_n_0\
    );
\crc_imd[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF8"
    )
        port map (
      I0 => p_10_out(0),
      I1 => \crc_imd_reg[9]\,
      I2 => \^recvaxis_tlast_sig_reg_0\,
      I3 => \crc_imd[9]_i_3_n_0\,
      I4 => \crc_imd[9]_i_4_n_0\,
      I5 => \crc_imd[9]_i_5_n_0\,
      O => \crc_imd_reg[7]_1\(5)
    );
\crc_imd[9]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(16),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(16),
      O => AXIS_tdata(16)
    );
\crc_imd[9]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(23),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(23),
      O => AXIS_tdata(23)
    );
\crc_imd[9]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DD0D22F2"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(5),
      I1 => \crc_imd_reg[4]\,
      I2 => rxAXIS_tdata(5),
      I3 => stateOp_reg,
      I4 => \retbuf_reg[15][7]\(13),
      O => \crc_imd[9]_i_12_n_0\
    );
\crc_imd[9]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6966999969666966"
    )
        port map (
      I0 => \crc_imd[15]_i_48_n_0\,
      I1 => \retbuf_reg[15][7]\(15),
      I2 => stateOp_reg,
      I3 => \^recvaxis_tdata\(1),
      I4 => \crc_imd_reg[4]\,
      I5 => \sendAXIL_rdata_reg[63]_0\(7),
      O => \crc_imd[9]_i_13_n_0\
    );
\crc_imd[9]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[1]_i_24_n_0\,
      I1 => \crc_imd_reg[1]_1\,
      I2 => AXIS_tdata(31),
      I3 => AXIS_tdata(29),
      I4 => AXIS_tdata(47),
      I5 => AXIS_tdata(32),
      O => \myCrc/p_29_out\(9)
    );
\crc_imd[9]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[9]_i_12_n_0\,
      I1 => \crc_imd[1]_i_9_n_0\,
      I2 => AXIS_tdata(37),
      I3 => AXIS_tdata(22),
      I4 => AXIS_tdata(55),
      I5 => AXIS_tdata(40),
      O => \crc_imd[9]_i_15_n_0\
    );
\crc_imd[9]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005A005A3311CC1E"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[63]_0\(19),
      I1 => rxAXIS_tdata(19),
      I2 => \sendAXIL_rdata_reg[63]_0\(20),
      I3 => \crc_imd_reg[4]\,
      I4 => rxAXIS_tdata(20),
      I5 => stateOp_reg,
      O => \crc_imd[9]_i_16_n_0\
    );
\crc_imd[9]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[8]_1\,
      I1 => \crc_imd[15]_i_64_n_0\,
      I2 => \crc_imd[1]_i_15_n_0\,
      I3 => \crc_imd[13]_i_14_n_0\,
      I4 => AXIS_tdata(63),
      I5 => \^txaxis_tdata_reg[13]\,
      O => \crc_imd[9]_i_17_n_0\
    );
\crc_imd[9]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[0]_2\,
      I1 => \crc_imd[15]_i_55_n_0\,
      I2 => \crc_imd[15]_i_62_n_0\,
      I3 => \crc_imd[15]_i_63_n_0\,
      I4 => \crc_imd[1]_i_8_n_0\,
      I5 => AXIS_tdata(24),
      O => \crc_imd[9]_i_18_n_0\
    );
\crc_imd[9]_i_19\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(55),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(55),
      O => AXIS_tdata(55)
    );
\crc_imd[9]_i_20\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(63),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(63),
      O => AXIS_tdata(63)
    );
\crc_imd[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF69960000"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[15]_0\(0),
      I1 => \^recvaxis_tdata_sig_reg[15]_0\(12),
      I2 => \retbuf_reg[15][7]\(8),
      I3 => \retbuf_reg[15][7]\(7),
      I4 => \crc_imd_reg[2]_0\,
      I5 => \crc_imd[9]_i_8_n_0\,
      O => \crc_imd[9]_i_3_n_0\
    );
\crc_imd[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[1]_0\,
      I1 => \retbuf_reg[15][7]\(7),
      I2 => \^recvaxis_tdata_sig_reg[15]_0\(12),
      I3 => AXIS_tdata(31),
      I4 => \^txaxis_tdata_reg[13]\,
      I5 => AXIS_tdata(16),
      O => \crc_imd[9]_i_4_n_0\
    );
\crc_imd[9]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF960096009600"
    )
        port map (
      I0 => AXIS_tdata(23),
      I1 => \crc_imd[9]_i_12_n_0\,
      I2 => \crc_imd[9]_i_13_n_0\,
      I3 => \crc_imd_reg[0]_1\,
      I4 => \myCrc/p_29_out\(9),
      I5 => \crc_imd_reg[1]\,
      O => \crc_imd[9]_i_5_n_0\
    );
\crc_imd[9]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => \^recvaxis_tdata\(5),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(15),
      O => \^recvaxis_tdata_sig_reg[15]_0\(12)
    );
\crc_imd[9]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF8228"
    )
        port map (
      I0 => \crc_imd_reg[2]_2\,
      I1 => \crc_imd[9]_i_15_n_0\,
      I2 => \crc_imd[9]_i_16_n_0\,
      I3 => \crc_imd[15]_i_62_n_0\,
      I4 => \crc_imd[9]_i_17_n_0\,
      I5 => \crc_imd[9]_i_18_n_0\,
      O => \crc_imd[9]_i_8_n_0\
    );
\crc_imd[9]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stateOp_reg,
      I1 => rxAXIS_tdata(31),
      I2 => \crc_imd_reg[4]\,
      I3 => \sendAXIL_rdata_reg[63]_0\(31),
      O => AXIS_tdata(31)
    );
\i[0]_i_1__11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => i(0),
      I1 => \i[15]_i_5_n_0\,
      O => \i[0]_i_1__11_n_0\
    );
\i[10]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => i(9),
      I1 => \i[12]_i_2_n_0\,
      I2 => i(10),
      I3 => \i[15]_i_5_n_0\,
      O => \i[10]_i_1__2_n_0\
    );
\i[11]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"14444444"
    )
        port map (
      I0 => \i[15]_i_5_n_0\,
      I1 => i(11),
      I2 => i(10),
      I3 => i(9),
      I4 => \i[12]_i_2_n_0\,
      O => \i[11]_i_1__1_n_0\
    );
\i[12]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => i(11),
      I1 => i(10),
      I2 => i(9),
      I3 => \i[12]_i_2_n_0\,
      I4 => i(12),
      I5 => \i[15]_i_5_n_0\,
      O => \i[12]_i_1__1_n_0\
    );
\i[12]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => i(8),
      I1 => i(7),
      I2 => \i[9]_i_2__3_n_0\,
      I3 => i(6),
      O => \i[12]_i_2_n_0\
    );
\i[13]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1444"
    )
        port map (
      I0 => \i[15]_i_5_n_0\,
      I1 => i(13),
      I2 => \i[13]_i_2__1_n_0\,
      I3 => i(12),
      O => \i[13]_i_1__1_n_0\
    );
\i[13]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => i(11),
      I1 => i(10),
      I2 => i(9),
      I3 => \i[12]_i_2_n_0\,
      O => \i[13]_i_2__1_n_0\
    );
\i[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \i[15]_i_4_n_0\,
      I1 => i(14),
      I2 => \i[15]_i_5_n_0\,
      O => \i[14]_i_1_n_0\
    );
\i[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F0F1FFFFFFFFFF"
    )
        port map (
      I0 => sendStrbToStop_reg_n_0,
      I1 => recvStrbToStop_reg_n_0,
      I2 => \i[15]_i_3_n_0\,
      I3 => stateTo(1),
      I4 => stateTo(0),
      I5 => req,
      O => \i[15]_i_1_n_0\
    );
\i[15]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => i(14),
      I1 => \i[15]_i_4_n_0\,
      I2 => i(15),
      I3 => \i[15]_i_5_n_0\,
      O => \i[15]_i_2_n_0\
    );
\i[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => recvStrbToStart_reg_n_0,
      I1 => sendStrbToStart_reg_n_0,
      O => \i[15]_i_3_n_0\
    );
\i[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => i(13),
      I1 => i(11),
      I2 => i(10),
      I3 => i(9),
      I4 => \i[12]_i_2_n_0\,
      I5 => i(12),
      O => \i[15]_i_4_n_0\
    );
\i[15]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => sendStrbToStart_reg_n_0,
      I1 => recvStrbToStart_reg_n_0,
      I2 => stateTo(1),
      I3 => req,
      O => \i[15]_i_5_n_0\
    );
\i[1]_i_1__10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => i(1),
      I1 => i(0),
      I2 => \i[15]_i_5_n_0\,
      O => \i[1]_i_1__10_n_0\
    );
\i[2]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => i(1),
      I1 => i(0),
      I2 => i(2),
      I3 => \i[15]_i_5_n_0\,
      O => \i[2]_i_1__6_n_0\
    );
\i[3]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => i(2),
      I1 => i(0),
      I2 => i(1),
      I3 => i(3),
      I4 => \i[15]_i_5_n_0\,
      O => \i[3]_i_1__6_n_0\
    );
\i[4]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => i(3),
      I1 => i(1),
      I2 => i(0),
      I3 => i(2),
      I4 => i(4),
      I5 => \i[15]_i_5_n_0\,
      O => \i[4]_i_1__6_n_0\
    );
\i[5]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"09"
    )
        port map (
      I0 => \i[5]_i_2__4_n_0\,
      I1 => i(5),
      I2 => \i[15]_i_5_n_0\,
      O => \i[5]_i_1__5_n_0\
    );
\i[5]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => i(3),
      I1 => i(1),
      I2 => i(0),
      I3 => i(2),
      I4 => i(4),
      O => \i[5]_i_2__4_n_0\
    );
\i[6]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"09"
    )
        port map (
      I0 => \i[9]_i_2__3_n_0\,
      I1 => i(6),
      I2 => \i[15]_i_5_n_0\,
      O => \i[6]_i_1__5_n_0\
    );
\i[7]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00D2"
    )
        port map (
      I0 => i(6),
      I1 => \i[9]_i_2__3_n_0\,
      I2 => i(7),
      I3 => \i[15]_i_5_n_0\,
      O => \i[7]_i_1__5_n_0\
    );
\i[8]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44144444"
    )
        port map (
      I0 => \i[15]_i_5_n_0\,
      I1 => i(8),
      I2 => i(7),
      I3 => \i[9]_i_2__3_n_0\,
      I4 => i(6),
      O => \i[8]_i_1__4_n_0\
    );
\i[9]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F7FF0800"
    )
        port map (
      I0 => i(8),
      I1 => i(7),
      I2 => \i[9]_i_2__3_n_0\,
      I3 => i(6),
      I4 => i(9),
      I5 => \i[15]_i_5_n_0\,
      O => \i[9]_i_1__3_n_0\
    );
\i[9]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => i(4),
      I1 => i(2),
      I2 => i(0),
      I3 => i(1),
      I4 => i(3),
      I5 => i(5),
      O => \i[9]_i_2__3_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[0]_i_1__11_n_0\,
      Q => i(0)
    );
\i_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[10]_i_1__2_n_0\,
      Q => i(10)
    );
\i_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[11]_i_1__1_n_0\,
      Q => i(11)
    );
\i_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[12]_i_1__1_n_0\,
      Q => i(12)
    );
\i_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[13]_i_1__1_n_0\,
      Q => i(13)
    );
\i_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[14]_i_1_n_0\,
      Q => i(14)
    );
\i_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[15]_i_2_n_0\,
      Q => i(15)
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[1]_i_1__10_n_0\,
      Q => i(1)
    );
\i_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[2]_i_1__6_n_0\,
      Q => i(2)
    );
\i_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[3]_i_1__6_n_0\,
      Q => i(3)
    );
\i_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[4]_i_1__6_n_0\,
      Q => i(4)
    );
\i_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[5]_i_1__5_n_0\,
      Q => i(5)
    );
\i_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[6]_i_1__5_n_0\,
      Q => i(6)
    );
\i_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[7]_i_1__5_n_0\,
      Q => i(7)
    );
\i_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[8]_i_1__4_n_0\,
      Q => i(8)
    );
\i_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \i[9]_i_1__3_n_0\,
      Q => i(9)
    );
\invbuf[0][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000800FFFFFFFF"
    )
        port map (
      I0 => \^staterecv_reg[0]_0\,
      I1 => \invbuf_reg[7][0]\,
      I2 => Q(0),
      I3 => Q(2),
      I4 => \invbuf_reg[7][0]_0\,
      I5 => \^stateop_reg[4]_1\,
      O => \stateOp_reg[0]\(0)
    );
\invbuf[7][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \^recvaxis_tdata\(0),
      I1 => \invbuf_reg[7][0]\,
      I2 => rxAXIS_tdata(56),
      I3 => \^stateop_reg[4]_1\,
      O => \recvAXIS_tdata_sig_reg[7]_1\(0)
    );
\invbuf[7][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => rxAXIS_tdata(1),
      I1 => \invbuf_reg[7][0]\,
      I2 => rxAXIS_tdata(57),
      I3 => \^stateop_reg[4]_1\,
      O => \recvAXIS_tdata_sig_reg[7]_1\(1)
    );
\invbuf[7][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => rxAXIS_tdata(2),
      I1 => \invbuf_reg[7][0]\,
      I2 => rxAXIS_tdata(58),
      I3 => \^stateop_reg[4]_1\,
      O => \recvAXIS_tdata_sig_reg[7]_1\(2)
    );
\invbuf[7][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => rxAXIS_tdata(3),
      I1 => \invbuf_reg[7][0]\,
      I2 => rxAXIS_tdata(59),
      I3 => \^stateop_reg[4]_1\,
      O => \recvAXIS_tdata_sig_reg[7]_1\(3)
    );
\invbuf[7][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => rxAXIS_tdata(4),
      I1 => \invbuf_reg[7][0]\,
      I2 => rxAXIS_tdata(60),
      I3 => \^stateop_reg[4]_1\,
      O => \recvAXIS_tdata_sig_reg[7]_1\(4)
    );
\invbuf[7][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => rxAXIS_tdata(5),
      I1 => \invbuf_reg[7][0]\,
      I2 => rxAXIS_tdata(61),
      I3 => \^stateop_reg[4]_1\,
      O => \recvAXIS_tdata_sig_reg[7]_1\(5)
    );
\invbuf[7][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => rxAXIS_tdata(6),
      I1 => \invbuf_reg[7][0]\,
      I2 => rxAXIS_tdata(62),
      I3 => \^stateop_reg[4]_1\,
      O => \recvAXIS_tdata_sig_reg[7]_1\(6)
    );
\invbuf[7][7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \^recvaxis_tdata\(1),
      I1 => \invbuf_reg[7][0]\,
      I2 => rxAXIS_tdata(63),
      I3 => \^stateop_reg[4]_1\,
      O => \recvAXIS_tdata_sig_reg[7]_1\(7)
    );
\invbuf[9][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888A808"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => \^recvaxis_tdata\(0),
      I2 => \invbuf_reg[9][0]_1\,
      I3 => rxAXIS_tdata(8),
      I4 => \invbuf_reg[9][0]_6\,
      O => \recvAXIS_tdata_sig_reg[7]_2\(0)
    );
\invbuf[9][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888A808"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => rxAXIS_tdata(1),
      I2 => \invbuf_reg[9][0]_1\,
      I3 => rxAXIS_tdata(9),
      I4 => \invbuf_reg[9][0]_6\,
      O => \recvAXIS_tdata_sig_reg[7]_2\(1)
    );
\invbuf[9][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888A808"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => rxAXIS_tdata(2),
      I2 => \invbuf_reg[9][0]_1\,
      I3 => \^recvaxis_tdata\(2),
      I4 => \invbuf_reg[9][0]_6\,
      O => \recvAXIS_tdata_sig_reg[7]_2\(2)
    );
\invbuf[9][3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888A808"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => rxAXIS_tdata(3),
      I2 => \invbuf_reg[9][0]_1\,
      I3 => \^recvaxis_tdata\(3),
      I4 => \invbuf_reg[9][0]_6\,
      O => \recvAXIS_tdata_sig_reg[7]_2\(3)
    );
\invbuf[9][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888A808"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => rxAXIS_tdata(4),
      I2 => \invbuf_reg[9][0]_1\,
      I3 => \^recvaxis_tdata\(4),
      I4 => \invbuf_reg[9][0]_6\,
      O => \recvAXIS_tdata_sig_reg[7]_2\(4)
    );
\invbuf[9][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888A808"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(5),
      I2 => \invbuf_reg[9][0]_1\,
      I3 => rxAXIS_tdata(13),
      I4 => \invbuf_reg[9][0]_6\,
      O => \recvAXIS_tdata_sig_reg[7]_2\(5)
    );
\invbuf[9][6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888A808"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(6),
      I2 => \invbuf_reg[9][0]_1\,
      I3 => rxAXIS_tdata(14),
      I4 => \invbuf_reg[9][0]_6\,
      O => \recvAXIS_tdata_sig_reg[7]_2\(6)
    );
\invbuf[9][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00002000FFFFFFFF"
    )
        port map (
      I0 => \invbuf_reg[9][0]\,
      I1 => \invbuf[9][7]_i_4_n_0\,
      I2 => Q(1),
      I3 => \invbuf_reg[9][0]_0\,
      I4 => Q(5),
      I5 => \^stateop_reg[4]\,
      O => E(0)
    );
\invbuf[9][7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888A808"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => \^recvaxis_tdata\(1),
      I2 => \invbuf_reg[9][0]_1\,
      I3 => \^recvaxis_tdata\(5),
      I4 => \invbuf_reg[9][0]_6\,
      O => \recvAXIS_tdata_sig_reg[7]_2\(7)
    );
\invbuf[9][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFDFFFFFFFF"
    )
        port map (
      I0 => \invbuf_reg[9][0]_1\,
      I1 => \invbuf_reg[9][0]_2\,
      I2 => \invbuf_reg[9][0]_3\,
      I3 => \invbuf_reg[9][0]_4\,
      I4 => \invbuf_reg[9][0]_5\,
      I5 => \^staterecv_reg[0]_0\,
      O => \invbuf[9][7]_i_4_n_0\
    );
\ixRetbufCrc[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \ixRetbufCrc_reg[0]_0\,
      O => \tixVCommand_reg[0]\(0)
    );
\ixRetbufCrc[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \pollbuf_reg[3][1]\,
      O => \tixVCommand_reg[0]\(1)
    );
\ixRetbufCrc[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \ixRetbufCrc_reg[2]\,
      O => \tixVCommand_reg[0]\(2)
    );
\ixRetbufCrc[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[1][7]\(0),
      I1 => \pollbuf_reg[3][5]_0\,
      I2 => \pollbuf_reg[3][5]\,
      I3 => \^stateop_reg[4]_0\,
      O => \tixVCommand_reg[0]\(3)
    );
\ixRetbufCrc[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \retbuf_reg[7][7]_0\,
      I1 => \^stateop_reg[4]_0\,
      O => \tixVCommand_reg[0]\(4)
    );
\ixRetbufCrc[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \lastAXIS_tkeep_reg[1]\,
      I1 => \^stateop_reg[4]_0\,
      O => \stateOp_reg[5]\(0)
    );
\ixRetbufCrc[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \pollbuf_reg[1][7]\(0),
      I1 => \pollbuf_reg[3][5]_0\,
      I2 => \pollbuf_reg[3][5]\,
      I3 => \^stateop_reg[4]_0\,
      O => \tixVCommand_reg[0]\(5)
    );
\lastAXIS_tkeep[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF7FFFFF"
    )
        port map (
      I0 => \lastAXIS_tkeep_reg[1]\,
      I1 => \ixRetbufCrc_reg[2]\,
      I2 => \pollbuf_reg[3][1]\,
      I3 => \ixRetbufCrc_reg[0]_0\,
      I4 => \^stateop_reg[4]_0\,
      O => \stateOp_reg[4]_5\(0)
    );
\lastAXIS_tkeep[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7A2FFFF"
    )
        port map (
      I0 => \lastAXIS_tkeep_reg[1]\,
      I1 => \ixRetbufCrc_reg[2]\,
      I2 => \lastAXIS_tkeep_reg[2]\,
      I3 => \stateOp_next_reg[5]\,
      I4 => \^stateop_reg[4]_0\,
      O => \stateOp_reg[4]_5\(1)
    );
\lastAXIS_tkeep[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D0FFDFFF"
    )
        port map (
      I0 => \ixRetbufCrc_reg[2]\,
      I1 => \ixRetbufCrc_reg[0]_0\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \^stateop_reg[4]_0\,
      I4 => \crcAXIS_tkeep_reg[3]_1\,
      O => \stateOp_reg[4]_5\(2)
    );
\lastAXIS_tkeep[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFF0EFF0EFFFEFF"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[4]\,
      I1 => \lastAXIS_tkeep_reg[5]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \^stateop_reg[4]_0\,
      I4 => \ixRetbufCrc_reg[2]\,
      I5 => \ixRetbufCrc_reg[0]_0\,
      O => \stateOp_reg[4]_5\(3)
    );
\lastAXIS_tkeep[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C1FFFFFFC1FF00FF"
    )
        port map (
      I0 => \pollbuf_reg[3][1]\,
      I1 => \ixRetbufCrc_reg[0]_0\,
      I2 => \ixRetbufCrc_reg[2]\,
      I3 => \^stateop_reg[4]_0\,
      I4 => \lastAXIS_tkeep_reg[1]\,
      I5 => \lastAXIS_tkeep_reg[5]\,
      O => \stateOp_reg[4]_5\(4)
    );
\lastAXIS_tkeep[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C1FFFFFFC1FF00FF"
    )
        port map (
      I0 => \pollbuf_reg[3][1]\,
      I1 => \ixRetbufCrc_reg[0]_0\,
      I2 => \ixRetbufCrc_reg[2]\,
      I3 => \^stateop_reg[4]_0\,
      I4 => \lastAXIS_tkeep_reg[1]\,
      I5 => \crcAXIS_tkeep_reg[6]\,
      O => \stateOp_reg[4]_5\(5)
    );
\lastAXIS_tkeep[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8F8F0FFF"
    )
        port map (
      I0 => \ixRetbufCrc_reg[2]\,
      I1 => \ixRetbufCrc_reg[0]_0\,
      I2 => \^stateop_reg[4]_0\,
      I3 => \crcAXIS_tkeep_reg[7]_0\,
      I4 => \lastAXIS_tkeep_reg[1]\,
      O => \stateOp_reg[4]_5\(6)
    );
\len[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(0),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(0)
    );
\len[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(2),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(10)
    );
\len[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(3),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(11)
    );
\len[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(4),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(12)
    );
\len[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(5),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(13)
    );
\len[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(6),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(14)
    );
\len[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(7),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(15)
    );
\len[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[23]\(0),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(16)
    );
\len[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[23]\(1),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(17)
    );
\len[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[23]\(2),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(18)
    );
\len[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[23]\(3),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(19)
    );
\len[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(1),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(1)
    );
\len[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[23]\(4),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(20)
    );
\len[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[23]\(5),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(21)
    );
\len[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[23]\(6),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(22)
    );
\len[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[23]\(7),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(23)
    );
\len[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[31]\(0),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(24)
    );
\len[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[31]\(1),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(25)
    );
\len[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[31]\(2),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(26)
    );
\len[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[31]\(3),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(27)
    );
\len[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[31]\(4),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(28)
    );
\len[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[31]\(5),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(29)
    );
\len[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(2),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(2)
    );
\len[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[31]\(6),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(30)
    );
\len[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[31]\(7),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(31)
    );
\len[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(3),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(3)
    );
\len[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(4),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(4)
    );
\len[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(5),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(5)
    );
\len[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(6),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(6)
    );
\len[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(7),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(7)
    );
\len[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(0),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(8)
    );
\len[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(1),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[3][7]\(9)
    );
\opbuf[0][0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => \^recvaxis_tdata\(0),
      O => D(0)
    );
\opbuf[0][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(1),
      O => D(1)
    );
\opbuf[0][2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(2),
      O => D(2)
    );
\opbuf[0][3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(3),
      O => D(3)
    );
\opbuf[0][4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(4),
      O => D(4)
    );
\opbuf[0][5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(5),
      O => D(5)
    );
\opbuf[0][6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(6),
      O => D(6)
    );
\opbuf[0][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04000000FFFFFFFF"
    )
        port map (
      I0 => stateRecv(1),
      I1 => stateRecv(2),
      I2 => stateRecv(0),
      I3 => \invbuf_reg[7][0]\,
      I4 => commok_sig_reg_0,
      I5 => \^stateop_reg[4]_1\,
      O => \stateRecv_reg[1]_0\(0)
    );
\opbuf[0][7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => \^recvaxis_tdata\(1),
      O => D(7)
    );
\opbuf[0][7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAA8A"
    )
        port map (
      I0 => \stateOp[0]_i_2_n_0\,
      I1 => Q(4),
      I2 => commok_sig_reg_1,
      I3 => Q(2),
      I4 => Q(5),
      I5 => Q(0),
      O => \^stateop_reg[4]_1\
    );
\opbuf[1][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => \^recvaxis_tdata\(0),
      I2 => \invbuf_reg[7][0]\,
      I3 => rxAXIS_tdata(8),
      O => \recvAXIS_tdata_sig_reg[7]_6\(0)
    );
\opbuf[1][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(1),
      I2 => \invbuf_reg[7][0]\,
      I3 => rxAXIS_tdata(9),
      O => \recvAXIS_tdata_sig_reg[7]_6\(1)
    );
\opbuf[1][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(2),
      I2 => \invbuf_reg[7][0]\,
      I3 => \^recvaxis_tdata\(2),
      O => \recvAXIS_tdata_sig_reg[7]_6\(2)
    );
\opbuf[1][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(3),
      I2 => \invbuf_reg[7][0]\,
      I3 => \^recvaxis_tdata\(3),
      O => \recvAXIS_tdata_sig_reg[7]_6\(3)
    );
\opbuf[1][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(4),
      I2 => \invbuf_reg[7][0]\,
      I3 => \^recvaxis_tdata\(4),
      O => \recvAXIS_tdata_sig_reg[7]_6\(4)
    );
\opbuf[1][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(5),
      I2 => \invbuf_reg[7][0]\,
      I3 => rxAXIS_tdata(13),
      O => \recvAXIS_tdata_sig_reg[7]_6\(5)
    );
\opbuf[1][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(6),
      I2 => \invbuf_reg[7][0]\,
      I3 => rxAXIS_tdata(14),
      O => \recvAXIS_tdata_sig_reg[7]_6\(6)
    );
\opbuf[1][7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => \^recvaxis_tdata\(1),
      I2 => \invbuf_reg[7][0]\,
      I3 => \^recvaxis_tdata\(5),
      O => \recvAXIS_tdata_sig_reg[7]_6\(7)
    );
\opbuf[2][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => \^recvaxis_tdata\(0),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(16),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_3\(0)
    );
\opbuf[2][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(1),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(17),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_3\(1)
    );
\opbuf[2][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(2),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(18),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_3\(2)
    );
\opbuf[2][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(3),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(19),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_3\(3)
    );
\opbuf[2][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(4),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(20),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_3\(4)
    );
\opbuf[2][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(5),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(21),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_3\(5)
    );
\opbuf[2][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(6),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(22),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_3\(6)
    );
\opbuf[2][7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => \^recvaxis_tdata\(1),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(23),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_3\(7)
    );
\opbuf[3][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \^recvaxis_tdata\(0),
      I1 => \invbuf_reg[7][0]\,
      I2 => rxAXIS_tdata(24),
      I3 => \^stateop_reg[4]_1\,
      O => \recvAXIS_tdata_sig_reg[7]_0\(0)
    );
\opbuf[3][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8C80"
    )
        port map (
      I0 => rxAXIS_tdata(25),
      I1 => \^stateop_reg[4]_1\,
      I2 => \invbuf_reg[7][0]\,
      I3 => rxAXIS_tdata(1),
      O => \recvAXIS_tdata_sig_reg[7]_0\(1)
    );
\opbuf[3][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => rxAXIS_tdata(2),
      I1 => \invbuf_reg[7][0]\,
      I2 => rxAXIS_tdata(26),
      I3 => \^stateop_reg[4]_1\,
      O => \recvAXIS_tdata_sig_reg[7]_0\(2)
    );
\opbuf[3][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => rxAXIS_tdata(3),
      I1 => \invbuf_reg[7][0]\,
      I2 => rxAXIS_tdata(27),
      I3 => \^stateop_reg[4]_1\,
      O => \recvAXIS_tdata_sig_reg[7]_0\(3)
    );
\opbuf[3][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => rxAXIS_tdata(4),
      I1 => \invbuf_reg[7][0]\,
      I2 => rxAXIS_tdata(28),
      I3 => \^stateop_reg[4]_1\,
      O => \recvAXIS_tdata_sig_reg[7]_0\(4)
    );
\opbuf[3][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => rxAXIS_tdata(5),
      I1 => \invbuf_reg[7][0]\,
      I2 => rxAXIS_tdata(29),
      I3 => \^stateop_reg[4]_1\,
      O => \recvAXIS_tdata_sig_reg[7]_0\(5)
    );
\opbuf[3][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8C80"
    )
        port map (
      I0 => rxAXIS_tdata(30),
      I1 => \^stateop_reg[4]_1\,
      I2 => \invbuf_reg[7][0]\,
      I3 => rxAXIS_tdata(6),
      O => \recvAXIS_tdata_sig_reg[7]_0\(6)
    );
\opbuf[3][7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \^recvaxis_tdata\(1),
      I1 => \invbuf_reg[7][0]\,
      I2 => rxAXIS_tdata(31),
      I3 => \^stateop_reg[4]_1\,
      O => \recvAXIS_tdata_sig_reg[7]_0\(7)
    );
\opbuf[4][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => \^recvaxis_tdata\(0),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(32),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_4\(0)
    );
\opbuf[4][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(1),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(33),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_4\(1)
    );
\opbuf[4][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(2),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(34),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_4\(2)
    );
\opbuf[4][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(3),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(35),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_4\(3)
    );
\opbuf[4][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(4),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(36),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_4\(4)
    );
\opbuf[4][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(5),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(37),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_4\(5)
    );
\opbuf[4][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(6),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(38),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_4\(6)
    );
\opbuf[4][7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => \^recvaxis_tdata\(1),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(39),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_4\(7)
    );
\opbuf[5][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B080"
    )
        port map (
      I0 => rxAXIS_tdata(40),
      I1 => \invbuf_reg[7][0]\,
      I2 => \^stateop_reg[4]_1\,
      I3 => \^recvaxis_tdata\(0),
      O => \recvAXIS_tdata_sig_reg[47]_0\(0)
    );
\opbuf[5][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B080"
    )
        port map (
      I0 => rxAXIS_tdata(41),
      I1 => \invbuf_reg[7][0]\,
      I2 => \^stateop_reg[4]_1\,
      I3 => rxAXIS_tdata(1),
      O => \recvAXIS_tdata_sig_reg[47]_0\(1)
    );
\opbuf[5][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(2),
      I2 => \invbuf_reg[7][0]\,
      I3 => rxAXIS_tdata(42),
      O => \recvAXIS_tdata_sig_reg[47]_0\(2)
    );
\opbuf[5][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B080"
    )
        port map (
      I0 => rxAXIS_tdata(43),
      I1 => \invbuf_reg[7][0]\,
      I2 => \^stateop_reg[4]_1\,
      I3 => rxAXIS_tdata(3),
      O => \recvAXIS_tdata_sig_reg[47]_0\(3)
    );
\opbuf[5][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(4),
      I2 => \invbuf_reg[7][0]\,
      I3 => rxAXIS_tdata(44),
      O => \recvAXIS_tdata_sig_reg[47]_0\(4)
    );
\opbuf[5][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B080"
    )
        port map (
      I0 => rxAXIS_tdata(45),
      I1 => \invbuf_reg[7][0]\,
      I2 => \^stateop_reg[4]_1\,
      I3 => rxAXIS_tdata(5),
      O => \recvAXIS_tdata_sig_reg[47]_0\(5)
    );
\opbuf[5][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B080"
    )
        port map (
      I0 => rxAXIS_tdata(46),
      I1 => \invbuf_reg[7][0]\,
      I2 => \^stateop_reg[4]_1\,
      I3 => rxAXIS_tdata(6),
      O => \recvAXIS_tdata_sig_reg[47]_0\(6)
    );
\opbuf[5][7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A80"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => rxAXIS_tdata(47),
      I2 => \invbuf_reg[7][0]\,
      I3 => \^recvaxis_tdata\(1),
      O => \recvAXIS_tdata_sig_reg[47]_0\(7)
    );
\opbuf[6][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => \^recvaxis_tdata\(0),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(48),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_5\(0)
    );
\opbuf[6][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(1),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(49),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_5\(1)
    );
\opbuf[6][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(2),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(50),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_5\(2)
    );
\opbuf[6][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(3),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(51),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_5\(3)
    );
\opbuf[6][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(4),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(52),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_5\(4)
    );
\opbuf[6][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(5),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(53),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_5\(5)
    );
\opbuf[6][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => rxAXIS_tdata(6),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(54),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_5\(6)
    );
\opbuf[6][7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C088"
    )
        port map (
      I0 => \^recvaxis_tdata\(1),
      I1 => \^stateop_reg[4]_1\,
      I2 => rxAXIS_tdata(55),
      I3 => \invbuf_reg[7][0]\,
      O => \recvAXIS_tdata_sig_reg[7]_5\(7)
    );
\pollbuf[0][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[0][7]_0\(0),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVController_reg[7]\(0)
    );
\pollbuf[0][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[0][7]_0\(1),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVController_reg[7]\(1)
    );
\pollbuf[0][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[0][7]_0\(2),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVController_reg[7]\(2)
    );
\pollbuf[0][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[0][7]_0\(3),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVController_reg[7]\(3)
    );
\pollbuf[0][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[0][7]_0\(4),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVController_reg[7]\(4)
    );
\pollbuf[0][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[0][7]_0\(5),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVController_reg[7]\(5)
    );
\pollbuf[0][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[0][7]_0\(6),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVController_reg[7]\(6)
    );
\pollbuf[0][7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D0000000FFFFFFFF"
    )
        port map (
      I0 => \pollbuf_reg[2][3]\,
      I1 => \pollbuf_reg[2][3]_0\,
      I2 => \pollbuf_reg[2][3]_1\,
      I3 => Q(2),
      I4 => Q(0),
      I5 => \^stateop_reg[4]_3\,
      O => \stateOp_reg[2]\(0)
    );
\pollbuf[0][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[0][7]_0\(7),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVController_reg[7]\(7)
    );
\pollbuf[1][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[1][7]\(0),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVCommand_reg[7]\(0)
    );
\pollbuf[1][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[1][7]\(1),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVCommand_reg[7]\(1)
    );
\pollbuf[1][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[1][7]\(2),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVCommand_reg[7]\(2)
    );
\pollbuf[1][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[1][7]\(3),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVCommand_reg[7]\(3)
    );
\pollbuf[1][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[1][7]\(4),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVCommand_reg[7]\(4)
    );
\pollbuf[1][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[1][7]\(5),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVCommand_reg[7]\(5)
    );
\pollbuf[1][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[1][7]\(6),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVCommand_reg[7]\(6)
    );
\pollbuf[1][7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\,
      I1 => \pollbuf_reg[1][7]\(7),
      I2 => \pollbuf_reg[0][7]_1\,
      I3 => \^stateop_reg[4]_3\,
      O => \tixVCommand_reg[7]\(7)
    );
\pollbuf[2][3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \pollbuf_reg[2][3]_2\,
      I1 => \^stateop_reg[4]_3\,
      I2 => \pollbuf_reg[2][3]_0\,
      O => \tixVBuffer_reg[1]\(0)
    );
\pollbuf[2][4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \pollbuf_reg[2][4]\,
      O => \tixVBuffer_reg[1]\(1)
    );
\pollbuf[2][7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \pollbuf_reg[2][7]\,
      I1 => \^stateop_reg[4]_3\,
      I2 => \pollbuf_reg[2][3]_0\,
      O => \tixVBuffer_reg[1]\(2)
    );
\pollbuf[3][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \ixRetbufCrc_reg[0]_0\,
      I2 => \pollbuf_reg[2][3]_0\,
      O => \tixVCommand_reg[0]_0\(0)
    );
\pollbuf[3][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \pollbuf_reg[3][1]\,
      I2 => \pollbuf_reg[2][3]_0\,
      O => \tixVCommand_reg[0]_0\(1)
    );
\pollbuf[3][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \ixRetbufCrc_reg[2]\,
      I2 => \pollbuf_reg[2][3]_0\,
      O => \tixVCommand_reg[0]_0\(2)
    );
\pollbuf[3][3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08000000"
    )
        port map (
      I0 => \pollbuf_reg[1][7]\(0),
      I1 => \pollbuf_reg[3][5]_0\,
      I2 => \pollbuf_reg[3][5]\,
      I3 => \^stateop_reg[4]_3\,
      I4 => \pollbuf_reg[2][3]_0\,
      O => \tixVCommand_reg[0]_0\(3)
    );
\pollbuf[3][4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \retbuf_reg[7][7]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => \pollbuf_reg[2][3]_0\,
      O => \tixVCommand_reg[0]_0\(4)
    );
\pollbuf[3][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \pollbuf_reg[1][7]\(0),
      I1 => \pollbuf_reg[3][5]_0\,
      I2 => \pollbuf_reg[3][5]\,
      I3 => \^stateop_reg[4]_3\,
      I4 => \pollbuf_reg[2][3]_0\,
      O => \tixVCommand_reg[0]_0\(5)
    );
\recvAXIL_rdata[63]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF000004000000"
    )
        port map (
      I0 => stateRecv(0),
      I1 => stateRecv(1),
      I2 => stateRecv(2),
      I3 => \recvAXIL_rdata[63]_i_2_n_0\,
      I4 => p_1_in0,
      I5 => \recvAXIL_rdata_reg_n_0_[63]\,
      O => \recvAXIL_rdata[63]_i_1_n_0\
    );
\recvAXIL_rdata[63]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => AXIL_araddr_sig(5),
      I1 => apuAXIL_arvalid,
      I2 => \^axil_arready\,
      I3 => AXIL_araddr_sig(4),
      O => \recvAXIL_rdata[63]_i_2_n_0\
    );
\recvAXIL_rdata_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIL_rdata[63]_i_1_n_0\,
      Q => \recvAXIL_rdata_reg_n_0_[63]\
    );
\recvAXIS_tdata_sig[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[0]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[0]_i_1_n_0\
    );
\recvAXIS_tdata_sig[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[10]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[10]_i_1_n_0\
    );
\recvAXIS_tdata_sig[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[11]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[11]_i_1_n_0\
    );
\recvAXIS_tdata_sig[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[12]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[12]_i_1_n_0\
    );
\recvAXIS_tdata_sig[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[13]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[13]_i_1_n_0\
    );
\recvAXIS_tdata_sig[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[14]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[14]_i_1_n_0\
    );
\recvAXIS_tdata_sig[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[15]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[15]_i_1_n_0\
    );
\recvAXIS_tdata_sig[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[16]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[16]_i_1_n_0\
    );
\recvAXIS_tdata_sig[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[17]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[17]_i_1_n_0\
    );
\recvAXIS_tdata_sig[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[18]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[18]_i_1_n_0\
    );
\recvAXIS_tdata_sig[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[19]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[19]_i_1_n_0\
    );
\recvAXIS_tdata_sig[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[1]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[1]_i_1_n_0\
    );
\recvAXIS_tdata_sig[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[20]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[20]_i_1_n_0\
    );
\recvAXIS_tdata_sig[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[21]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[21]_i_1_n_0\
    );
\recvAXIS_tdata_sig[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[22]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[22]_i_1_n_0\
    );
\recvAXIS_tdata_sig[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[23]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[23]_i_1_n_0\
    );
\recvAXIS_tdata_sig[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[24]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[24]_i_1_n_0\
    );
\recvAXIS_tdata_sig[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[25]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[25]_i_1_n_0\
    );
\recvAXIS_tdata_sig[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[26]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[26]_i_1_n_0\
    );
\recvAXIS_tdata_sig[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[27]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[27]_i_1_n_0\
    );
\recvAXIS_tdata_sig[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[28]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[28]_i_1_n_0\
    );
\recvAXIS_tdata_sig[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[29]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[29]_i_1_n_0\
    );
\recvAXIS_tdata_sig[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in(0),
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[2]_i_1_n_0\
    );
\recvAXIS_tdata_sig[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[30]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[30]_i_1_n_0\
    );
\recvAXIS_tdata_sig[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[31]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[31]_i_1_n_0\
    );
\recvAXIS_tdata_sig[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[32]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[32]_i_1_n_0\
    );
\recvAXIS_tdata_sig[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[33]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[33]_i_1_n_0\
    );
\recvAXIS_tdata_sig[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[34]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[34]_i_1_n_0\
    );
\recvAXIS_tdata_sig[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[35]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[35]_i_1_n_0\
    );
\recvAXIS_tdata_sig[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[36]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[36]_i_1_n_0\
    );
\recvAXIS_tdata_sig[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[37]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[37]_i_1_n_0\
    );
\recvAXIS_tdata_sig[38]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[38]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[38]_i_1_n_0\
    );
\recvAXIS_tdata_sig[39]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[39]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[39]_i_1_n_0\
    );
\recvAXIS_tdata_sig[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in(1),
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[3]_i_1_n_0\
    );
\recvAXIS_tdata_sig[40]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[40]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[40]_i_1_n_0\
    );
\recvAXIS_tdata_sig[41]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[41]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[41]_i_1_n_0\
    );
\recvAXIS_tdata_sig[42]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[42]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[42]_i_1_n_0\
    );
\recvAXIS_tdata_sig[43]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[43]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[43]_i_1_n_0\
    );
\recvAXIS_tdata_sig[44]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[44]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[44]_i_1_n_0\
    );
\recvAXIS_tdata_sig[45]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[45]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[45]_i_1_n_0\
    );
\recvAXIS_tdata_sig[46]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[46]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[46]_i_1_n_0\
    );
\recvAXIS_tdata_sig[47]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[47]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[47]_i_1_n_0\
    );
\recvAXIS_tdata_sig[48]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[48]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[48]_i_1_n_0\
    );
\recvAXIS_tdata_sig[49]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[49]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[49]_i_1_n_0\
    );
\recvAXIS_tdata_sig[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[4]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[4]_i_1_n_0\
    );
\recvAXIS_tdata_sig[50]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[50]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[50]_i_1_n_0\
    );
\recvAXIS_tdata_sig[51]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[51]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[51]_i_1_n_0\
    );
\recvAXIS_tdata_sig[52]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[52]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[52]_i_1_n_0\
    );
\recvAXIS_tdata_sig[53]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[53]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[53]_i_1_n_0\
    );
\recvAXIS_tdata_sig[54]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[54]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[54]_i_1_n_0\
    );
\recvAXIS_tdata_sig[55]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[55]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[55]_i_1_n_0\
    );
\recvAXIS_tdata_sig[56]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[56]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[56]_i_1_n_0\
    );
\recvAXIS_tdata_sig[57]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[57]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[57]_i_1_n_0\
    );
\recvAXIS_tdata_sig[58]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[58]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[58]_i_1_n_0\
    );
\recvAXIS_tdata_sig[59]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[59]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[59]_i_1_n_0\
    );
\recvAXIS_tdata_sig[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[5]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[5]_i_1_n_0\
    );
\recvAXIS_tdata_sig[60]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[60]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[60]_i_1_n_0\
    );
\recvAXIS_tdata_sig[61]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[61]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[61]_i_1_n_0\
    );
\recvAXIS_tdata_sig[62]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[62]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[62]_i_1_n_0\
    );
\recvAXIS_tdata_sig[63]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => stateRecv(0),
      I1 => \recvAXIS_tdata_sig[63]_i_3_n_0\,
      I2 => p_1_in0,
      O => \recvAXIS_tdata_sig[63]_i_1_n_0\
    );
\recvAXIS_tdata_sig[63]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[63]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[63]_i_2_n_0\
    );
\recvAXIS_tdata_sig[63]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000000000"
    )
        port map (
      I0 => \^axil_bvalid_sig_reg_0\,
      I1 => apuAXIL_bready,
      I2 => ixBlkWrite(1),
      I3 => ixBlkWrite(0),
      I4 => stateRecv(2),
      I5 => stateRecv(1),
      O => \recvAXIS_tdata_sig[63]_i_3_n_0\
    );
\recvAXIS_tdata_sig[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[6]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[6]_i_1_n_0\
    );
\recvAXIS_tdata_sig[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[7]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[7]_i_1_n_0\
    );
\recvAXIS_tdata_sig[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[8]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[8]_i_1_n_0\
    );
\recvAXIS_tdata_sig[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[9]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[9]_i_1_n_0\
    );
\recvAXIS_tdata_sig_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[0]_i_1_n_0\,
      Q => \^recvaxis_tdata\(0)
    );
\recvAXIS_tdata_sig_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[10]_i_1_n_0\,
      Q => \^recvaxis_tdata\(2)
    );
\recvAXIS_tdata_sig_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[11]_i_1_n_0\,
      Q => \^recvaxis_tdata\(3)
    );
\recvAXIS_tdata_sig_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[12]_i_1_n_0\,
      Q => \^recvaxis_tdata\(4)
    );
\recvAXIS_tdata_sig_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[13]_i_1_n_0\,
      Q => rxAXIS_tdata(13)
    );
\recvAXIS_tdata_sig_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[14]_i_1_n_0\,
      Q => rxAXIS_tdata(14)
    );
\recvAXIS_tdata_sig_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[15]_i_1_n_0\,
      Q => \^recvaxis_tdata\(5)
    );
\recvAXIS_tdata_sig_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[16]_i_1_n_0\,
      Q => rxAXIS_tdata(16)
    );
\recvAXIS_tdata_sig_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[17]_i_1_n_0\,
      Q => rxAXIS_tdata(17)
    );
\recvAXIS_tdata_sig_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[18]_i_1_n_0\,
      Q => rxAXIS_tdata(18)
    );
\recvAXIS_tdata_sig_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[19]_i_1_n_0\,
      Q => rxAXIS_tdata(19)
    );
\recvAXIS_tdata_sig_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[1]_i_1_n_0\,
      Q => rxAXIS_tdata(1)
    );
\recvAXIS_tdata_sig_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[20]_i_1_n_0\,
      Q => rxAXIS_tdata(20)
    );
\recvAXIS_tdata_sig_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[21]_i_1_n_0\,
      Q => rxAXIS_tdata(21)
    );
\recvAXIS_tdata_sig_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[22]_i_1_n_0\,
      Q => rxAXIS_tdata(22)
    );
\recvAXIS_tdata_sig_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[23]_i_1_n_0\,
      Q => rxAXIS_tdata(23)
    );
\recvAXIS_tdata_sig_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[24]_i_1_n_0\,
      Q => rxAXIS_tdata(24)
    );
\recvAXIS_tdata_sig_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[25]_i_1_n_0\,
      Q => rxAXIS_tdata(25)
    );
\recvAXIS_tdata_sig_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[26]_i_1_n_0\,
      Q => rxAXIS_tdata(26)
    );
\recvAXIS_tdata_sig_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[27]_i_1_n_0\,
      Q => rxAXIS_tdata(27)
    );
\recvAXIS_tdata_sig_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[28]_i_1_n_0\,
      Q => rxAXIS_tdata(28)
    );
\recvAXIS_tdata_sig_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[29]_i_1_n_0\,
      Q => rxAXIS_tdata(29)
    );
\recvAXIS_tdata_sig_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[2]_i_1_n_0\,
      Q => rxAXIS_tdata(2)
    );
\recvAXIS_tdata_sig_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[30]_i_1_n_0\,
      Q => rxAXIS_tdata(30)
    );
\recvAXIS_tdata_sig_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[31]_i_1_n_0\,
      Q => rxAXIS_tdata(31)
    );
\recvAXIS_tdata_sig_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[32]_i_1_n_0\,
      Q => rxAXIS_tdata(32)
    );
\recvAXIS_tdata_sig_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[33]_i_1_n_0\,
      Q => rxAXIS_tdata(33)
    );
\recvAXIS_tdata_sig_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[34]_i_1_n_0\,
      Q => rxAXIS_tdata(34)
    );
\recvAXIS_tdata_sig_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[35]_i_1_n_0\,
      Q => rxAXIS_tdata(35)
    );
\recvAXIS_tdata_sig_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[36]_i_1_n_0\,
      Q => rxAXIS_tdata(36)
    );
\recvAXIS_tdata_sig_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[37]_i_1_n_0\,
      Q => rxAXIS_tdata(37)
    );
\recvAXIS_tdata_sig_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[38]_i_1_n_0\,
      Q => rxAXIS_tdata(38)
    );
\recvAXIS_tdata_sig_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[39]_i_1_n_0\,
      Q => rxAXIS_tdata(39)
    );
\recvAXIS_tdata_sig_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[3]_i_1_n_0\,
      Q => rxAXIS_tdata(3)
    );
\recvAXIS_tdata_sig_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[40]_i_1_n_0\,
      Q => rxAXIS_tdata(40)
    );
\recvAXIS_tdata_sig_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[41]_i_1_n_0\,
      Q => rxAXIS_tdata(41)
    );
\recvAXIS_tdata_sig_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[42]_i_1_n_0\,
      Q => rxAXIS_tdata(42)
    );
\recvAXIS_tdata_sig_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[43]_i_1_n_0\,
      Q => rxAXIS_tdata(43)
    );
\recvAXIS_tdata_sig_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[44]_i_1_n_0\,
      Q => rxAXIS_tdata(44)
    );
\recvAXIS_tdata_sig_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[45]_i_1_n_0\,
      Q => rxAXIS_tdata(45)
    );
\recvAXIS_tdata_sig_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[46]_i_1_n_0\,
      Q => rxAXIS_tdata(46)
    );
\recvAXIS_tdata_sig_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[47]_i_1_n_0\,
      Q => rxAXIS_tdata(47)
    );
\recvAXIS_tdata_sig_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[48]_i_1_n_0\,
      Q => rxAXIS_tdata(48)
    );
\recvAXIS_tdata_sig_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[49]_i_1_n_0\,
      Q => rxAXIS_tdata(49)
    );
\recvAXIS_tdata_sig_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[4]_i_1_n_0\,
      Q => rxAXIS_tdata(4)
    );
\recvAXIS_tdata_sig_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[50]_i_1_n_0\,
      Q => rxAXIS_tdata(50)
    );
\recvAXIS_tdata_sig_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[51]_i_1_n_0\,
      Q => rxAXIS_tdata(51)
    );
\recvAXIS_tdata_sig_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[52]_i_1_n_0\,
      Q => rxAXIS_tdata(52)
    );
\recvAXIS_tdata_sig_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[53]_i_1_n_0\,
      Q => rxAXIS_tdata(53)
    );
\recvAXIS_tdata_sig_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[54]_i_1_n_0\,
      Q => rxAXIS_tdata(54)
    );
\recvAXIS_tdata_sig_reg[55]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[55]_i_1_n_0\,
      Q => rxAXIS_tdata(55)
    );
\recvAXIS_tdata_sig_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[56]_i_1_n_0\,
      Q => rxAXIS_tdata(56)
    );
\recvAXIS_tdata_sig_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[57]_i_1_n_0\,
      Q => rxAXIS_tdata(57)
    );
\recvAXIS_tdata_sig_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[58]_i_1_n_0\,
      Q => rxAXIS_tdata(58)
    );
\recvAXIS_tdata_sig_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[59]_i_1_n_0\,
      Q => rxAXIS_tdata(59)
    );
\recvAXIS_tdata_sig_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[5]_i_1_n_0\,
      Q => rxAXIS_tdata(5)
    );
\recvAXIS_tdata_sig_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[60]_i_1_n_0\,
      Q => rxAXIS_tdata(60)
    );
\recvAXIS_tdata_sig_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[61]_i_1_n_0\,
      Q => rxAXIS_tdata(61)
    );
\recvAXIS_tdata_sig_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[62]_i_1_n_0\,
      Q => rxAXIS_tdata(62)
    );
\recvAXIS_tdata_sig_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[63]_i_2_n_0\,
      Q => rxAXIS_tdata(63)
    );
\recvAXIS_tdata_sig_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[6]_i_1_n_0\,
      Q => rxAXIS_tdata(6)
    );
\recvAXIS_tdata_sig_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[7]_i_1_n_0\,
      Q => \^recvaxis_tdata\(1)
    );
\recvAXIS_tdata_sig_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[8]_i_1_n_0\,
      Q => rxAXIS_tdata(8)
    );
\recvAXIS_tdata_sig_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \recvAXIS_tdata_sig[9]_i_1_n_0\,
      Q => rxAXIS_tdata(9)
    );
recvAXIS_tlast_sig_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F08000"
    )
        port map (
      I0 => stateRecv(0),
      I1 => \recvAXIS_tdata_sig[63]_i_3_n_0\,
      I2 => p_1_in0,
      I3 => recvAXIS_tlast_sig0,
      I4 => \^recvaxis_tlast\,
      O => recvAXIS_tlast_sig_i_1_n_0
    );
recvAXIS_tlast_sig_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => recvAXIS_tlast_sig_i_19_n_0,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(12),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => \wordcnt_reg[12]__0_n_0\,
      O => recvAXIS_tlast_sig_i_10_n_0
    );
recvAXIS_tlast_sig_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => recvAXIS_tlast_sig_i_20_n_0,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(10),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => \wordcnt_reg[10]__0_n_0\,
      O => recvAXIS_tlast_sig_i_11_n_0
    );
recvAXIS_tlast_sig_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => recvAXIS_tlast_sig_i_21_n_0,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(6),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => \wordcnt_reg[6]__0_n_0\,
      O => recvAXIS_tlast_sig_i_12_n_0
    );
recvAXIS_tlast_sig_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => recvAXIS_tlast_sig_i_22_n_0,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(4),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => \wordcnt_reg[4]__0_n_0\,
      O => recvAXIS_tlast_sig_i_13_n_0
    );
recvAXIS_tlast_sig_i_14: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000B847"
    )
        port map (
      I0 => \rxlen_reg[0]_4\,
      I1 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I2 => recvAXIS_tlast_sig_reg_i_2_0(0),
      I3 => \wordcnt_reg[0]__0_n_0\,
      I4 => recvAXIS_tlast_sig_i_23_n_0,
      O => recvAXIS_tlast_sig_i_14_n_0
    );
recvAXIS_tlast_sig_i_15: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(25),
      I1 => \wordcnt_reg[25]__0_n_0\,
      I2 => recvAXIS_tlast_sig_reg_i_2_0(26),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => \wordcnt_reg[26]__0_n_0\,
      O => recvAXIS_tlast_sig_i_15_n_0
    );
recvAXIS_tlast_sig_i_16: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(22),
      I1 => \wordcnt_reg[22]__0_n_0\,
      I2 => recvAXIS_tlast_sig_reg_i_2_0(23),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => \wordcnt_reg[23]__0_n_0\,
      O => recvAXIS_tlast_sig_i_16_n_0
    );
recvAXIS_tlast_sig_i_17: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(18),
      I1 => \wordcnt_reg[18]__0_n_0\,
      I2 => recvAXIS_tlast_sig_reg_i_2_0(20),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => \wordcnt_reg[20]__0_n_0\,
      O => recvAXIS_tlast_sig_i_17_n_0
    );
recvAXIS_tlast_sig_i_18: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(15),
      I1 => \wordcnt_reg[15]__0_n_0\,
      I2 => recvAXIS_tlast_sig_reg_i_2_0(17),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => \wordcnt_reg[17]__0_n_0\,
      O => recvAXIS_tlast_sig_i_18_n_0
    );
recvAXIS_tlast_sig_i_19: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(13),
      I1 => \wordcnt_reg[13]__0_n_0\,
      I2 => recvAXIS_tlast_sig_reg_i_2_0(14),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => \wordcnt_reg[14]__0_n_0\,
      O => recvAXIS_tlast_sig_i_19_n_0
    );
recvAXIS_tlast_sig_i_20: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(9),
      I1 => \wordcnt_reg[9]__0_n_0\,
      I2 => recvAXIS_tlast_sig_reg_i_2_0(11),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => \wordcnt_reg[11]__0_n_0\,
      O => recvAXIS_tlast_sig_i_20_n_0
    );
recvAXIS_tlast_sig_i_21: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(7),
      I1 => \wordcnt_reg[7]__0_n_0\,
      I2 => recvAXIS_tlast_sig_reg_i_2_0(8),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => \wordcnt_reg[8]__0_n_0\,
      O => recvAXIS_tlast_sig_i_21_n_0
    );
recvAXIS_tlast_sig_i_22: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(3),
      I1 => \wordcnt_reg[3]__0_n_0\,
      I2 => recvAXIS_tlast_sig_reg_i_2_0(5),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => \wordcnt_reg[5]__0_n_0\,
      O => recvAXIS_tlast_sig_i_22_n_0
    );
recvAXIS_tlast_sig_i_23: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF6FCCF6"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(1),
      I1 => \wordcnt_reg[1]__0_n_0\,
      I2 => recvAXIS_tlast_sig_reg_i_2_0(2),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => \wordcnt_reg[2]__0_n_0\,
      O => recvAXIS_tlast_sig_i_23_n_0
    );
recvAXIS_tlast_sig_i_4: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wordcnt_reg[30]__0_n_0\,
      O => recvAXIS_tlast_sig_i_4_n_0
    );
recvAXIS_tlast_sig_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000090005050009"
    )
        port map (
      I0 => \wordcnt_reg[28]__0_n_0\,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(28),
      I2 => \wordcnt_reg[29]__0_n_0\,
      I3 => recvAXIS_tlast_sig_reg_i_2_0(27),
      I4 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I5 => \wordcnt_reg[27]__0_n_0\,
      O => recvAXIS_tlast_sig_i_5_n_0
    );
recvAXIS_tlast_sig_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => recvAXIS_tlast_sig_i_15_n_0,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(24),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => \wordcnt_reg[24]__0_n_0\,
      O => recvAXIS_tlast_sig_i_6_n_0
    );
recvAXIS_tlast_sig_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => recvAXIS_tlast_sig_i_16_n_0,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(21),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => \wordcnt_reg[21]__0_n_0\,
      O => recvAXIS_tlast_sig_i_7_n_0
    );
recvAXIS_tlast_sig_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => recvAXIS_tlast_sig_i_17_n_0,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(19),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => \wordcnt_reg[19]__0_n_0\,
      O => recvAXIS_tlast_sig_i_8_n_0
    );
recvAXIS_tlast_sig_i_9: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => recvAXIS_tlast_sig_i_18_n_0,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(16),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => \wordcnt_reg[16]__0_n_0\,
      O => recvAXIS_tlast_sig_i_9_n_0
    );
recvAXIS_tlast_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => recvAXIS_tlast_sig_i_1_n_0,
      Q => \^recvaxis_tlast\
    );
recvAXIS_tlast_sig_reg_i_2: unisim.vcomponents.CARRY8
     port map (
      CI => recvAXIS_tlast_sig_reg_i_3_n_0,
      CI_TOP => '0',
      CO(7 downto 3) => NLW_recvAXIS_tlast_sig_reg_i_2_CO_UNCONNECTED(7 downto 3),
      CO(2) => recvAXIS_tlast_sig0,
      CO(1) => recvAXIS_tlast_sig_reg_i_2_n_6,
      CO(0) => recvAXIS_tlast_sig_reg_i_2_n_7,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => NLW_recvAXIS_tlast_sig_reg_i_2_O_UNCONNECTED(7 downto 0),
      S(7 downto 3) => B"00000",
      S(2) => recvAXIS_tlast_sig_i_4_n_0,
      S(1) => recvAXIS_tlast_sig_i_5_n_0,
      S(0) => recvAXIS_tlast_sig_i_6_n_0
    );
recvAXIS_tlast_sig_reg_i_3: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => recvAXIS_tlast_sig_reg_i_3_n_0,
      CO(6) => recvAXIS_tlast_sig_reg_i_3_n_1,
      CO(5) => recvAXIS_tlast_sig_reg_i_3_n_2,
      CO(4) => recvAXIS_tlast_sig_reg_i_3_n_3,
      CO(3) => recvAXIS_tlast_sig_reg_i_3_n_4,
      CO(2) => recvAXIS_tlast_sig_reg_i_3_n_5,
      CO(1) => recvAXIS_tlast_sig_reg_i_3_n_6,
      CO(0) => recvAXIS_tlast_sig_reg_i_3_n_7,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => NLW_recvAXIS_tlast_sig_reg_i_3_O_UNCONNECTED(7 downto 0),
      S(7) => recvAXIS_tlast_sig_i_7_n_0,
      S(6) => recvAXIS_tlast_sig_i_8_n_0,
      S(5) => recvAXIS_tlast_sig_i_9_n_0,
      S(4) => recvAXIS_tlast_sig_i_10_n_0,
      S(3) => recvAXIS_tlast_sig_i_11_n_0,
      S(2) => recvAXIS_tlast_sig_i_12_n_0,
      S(1) => recvAXIS_tlast_sig_i_13_n_0,
      S(0) => recvAXIS_tlast_sig_i_14_n_0
    );
recvStrbToStart_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BF00B000"
    )
        port map (
      I0 => \stateRecv[2]_i_3_n_0\,
      I1 => recvStrbToStart_i_2_n_0,
      I2 => recvStrbToStart_i_3_n_0,
      I3 => p_1_in0,
      I4 => recvStrbToStart_reg_n_0,
      O => recvStrbToStart_i_1_n_0
    );
recvStrbToStart_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF53F"
    )
        port map (
      I0 => p_33_in,
      I1 => \recvAXIL_rdata[63]_i_2_n_0\,
      I2 => stateRecv(1),
      I3 => stateRecv(2),
      I4 => stateRecv(0),
      O => recvStrbToStart_i_2_n_0
    );
recvStrbToStart_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FFFDDD"
    )
        port map (
      I0 => \stateRecv[2]_i_10_n_0\,
      I1 => \wordcnt[0]__0_i_4_n_0\,
      I2 => stateRecv(0),
      I3 => stateRecv(2),
      I4 => stateRecv(1),
      O => recvStrbToStart_i_3_n_0
    );
recvStrbToStart_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => recvStrbToStart_i_1_n_0,
      Q => recvStrbToStart_reg_n_0
    );
recvStrbToStop_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C080CFF0C080C00"
    )
        port map (
      I0 => \recvAXIS_tdata_sig[63]_i_3_n_0\,
      I1 => stateRecv(0),
      I2 => recvStrbToStop_i_2_n_0,
      I3 => \stateRecv[2]_i_7_n_0\,
      I4 => recvStrbToStop_i_3_n_0,
      I5 => recvStrbToStop_reg_n_0,
      O => recvStrbToStop_i_1_n_0
    );
recvStrbToStop_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F000000FFFFFFFF"
    )
        port map (
      I0 => stateRecv(2),
      I1 => stateRecv(1),
      I2 => stateRecv(0),
      I3 => stateTo(1),
      I4 => stateTo(0),
      I5 => \stateRecv[2]_i_9__0_n_0\,
      O => recvStrbToStop_i_2_n_0
    );
recvStrbToStop_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF8F"
    )
        port map (
      I0 => stateRecv(0),
      I1 => \recvAXIS_tdata_sig[63]_i_3_n_0\,
      I2 => p_1_in0,
      I3 => stateRecv(2),
      O => recvStrbToStop_i_3_n_0
    );
recvStrbToStop_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => recvStrbToStop_i_1_n_0,
      Q => recvStrbToStop_reg_n_0
    );
reqReset_sig_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F080"
    )
        port map (
      I0 => reqReset_sig_reg_0,
      I1 => reqReset_sig_reg_1,
      I2 => \^stateop_reg[4]_1\,
      I3 => reqResetFromHostif,
      O => reqReset_sig_reg
    );
\resid[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88C0"
    )
        port map (
      I0 => \ixRetbufCrc_reg[0]_0\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \resid_reg[0]_21\,
      I3 => \lastAXIS_tkeep_reg[1]\,
      O => \stateOp_reg[5]_3\(0)
    );
\resid[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000700FF000700"
    )
        port map (
      I0 => \resid_reg[0]_21\,
      I1 => \resid_reg[1]\,
      I2 => \crcAXIS_tkeep_reg[4]\,
      I3 => \^stateop_reg[4]_0\,
      I4 => \lastAXIS_tkeep_reg[1]\,
      I5 => \lastAXIS_tkeep_reg[2]\,
      O => \stateOp_reg[5]_3\(1)
    );
\resid[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \lastAXIS_tkeep_reg[1]_0\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      O => \stateOp_reg[5]_5\(0)
    );
\resid[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0E00FE00FE000E00"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[4]\,
      I1 => \lastAXIS_tkeep_reg[5]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \^stateop_reg[4]_0\,
      I4 => \ixRetbufCrc_reg[2]\,
      I5 => \pollbuf_reg[3][1]\,
      O => \stateOp_reg[5]_3\(2)
    );
\retbuf[0][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000A202AAAAA202"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \retbuf_reg[0][0]\,
      I2 => \retbuf_reg[6][5]\,
      I3 => vidtrackGetInfoTixVState(0),
      I4 => \retbuf_reg[4][7]_2\,
      I5 => \retbuf_reg[0][0]_0\,
      O => \crc_imd_reg[2]\(0)
    );
\retbuf[0][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFA820"
    )
        port map (
      I0 => \^stateop_reg[4]_12\,
      I1 => \retbuf_reg[0][2]\,
      I2 => \retbuf_reg[15][7]\(2),
      I3 => \retbuf_reg[15][7]\(10),
      I4 => \retbuf[0][2]_i_2_n_0\,
      O => \crc_imd_reg[2]\(1)
    );
\retbuf[0][2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000400"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_3\,
      I2 => \retbuf_reg[0][2]_0\,
      I3 => \retbuf_reg[0][2]_1\,
      I4 => \retbuf_reg[6][5]\,
      O => \retbuf[0][2]_i_2_n_0\
    );
\retbuf[0][7]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00400000"
    )
        port map (
      I0 => \retbuf_reg[6][5]\,
      I1 => \retbuf_reg[0][2]_1\,
      I2 => \retbuf_reg[0][7]_4\,
      I3 => \retbuf_reg[4][7]_2\,
      I4 => \^stateop_reg[4]_3\,
      O => \tixVController_reg[7]_0\
    );
\retbuf[0][7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"75550000FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg[0][7]\,
      I1 => \retbuf_reg[0][7]_0\,
      I2 => \retbuf_reg[0][7]_1\,
      I3 => \retbuf_reg[0][7]_2\,
      I4 => \retbuf_reg[0][7]_3\,
      I5 => \^stateop_reg[4]_0\,
      O => \resid_reg[0]\(0)
    );
\retbuf[0][7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \retbuf_reg[4][7]_2\,
      O => \^stateop_reg[4]_12\
    );
\retbuf[10][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(4),
      I2 => \retbuf_reg[15][7]\(0),
      I3 => \retbuf_reg[10][0]_0\,
      I4 => \retbuf_reg[15][7]\(8),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[15]\(0)
    );
\retbuf[10][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(5),
      I2 => \retbuf_reg[15][7]\(1),
      I3 => \retbuf_reg[10][0]_0\,
      I4 => \retbuf_reg[15][7]\(9),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[15]\(1)
    );
\retbuf[10][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(6),
      I2 => \retbuf_reg[15][7]\(2),
      I3 => \retbuf_reg[10][0]_0\,
      I4 => \retbuf_reg[15][7]\(10),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[15]\(2)
    );
\retbuf[10][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(7),
      I2 => \retbuf_reg[15][7]\(3),
      I3 => \retbuf_reg[10][0]_0\,
      I4 => \retbuf_reg[15][7]\(11),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[15]\(3)
    );
\retbuf[10][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(8),
      I2 => \retbuf_reg[15][7]\(4),
      I3 => \retbuf_reg[10][0]_0\,
      I4 => \retbuf_reg[15][7]\(12),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[15]\(4)
    );
\retbuf[10][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[10][5]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(5),
      I2 => \retbuf_reg[10][0]_0\,
      I3 => \retbuf_reg[15][7]\(13),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[15]\(5)
    );
\retbuf[10][5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[8][7]\(9),
      O => \retbuf[10][5]_i_2_n_0\
    );
\retbuf[10][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(10),
      I2 => \retbuf_reg[15][7]\(6),
      I3 => \retbuf_reg[10][0]_0\,
      I4 => \retbuf_reg[15][7]\(14),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[15]\(6)
    );
\retbuf[10][7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAABAAA"
    )
        port map (
      I0 => \retbuf[8][7]_i_3__0_n_0\,
      I1 => \retbuf_reg[1][0]_0\,
      I2 => \retbuf_reg[10][0]\,
      I3 => Q(1),
      I4 => Q(5),
      O => \stateOp_reg[1]_3\(0)
    );
\retbuf[10][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(11),
      I2 => \retbuf_reg[15][7]\(7),
      I3 => \retbuf_reg[10][0]_0\,
      I4 => \retbuf_reg[15][7]\(15),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[15]\(7)
    );
\retbuf[11][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(0),
      I2 => \retbuf_reg[15][7]\(4),
      I3 => \retbuf_reg[11][4]\,
      I4 => \retbuf_reg[15][7]\(12),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[7]\(0)
    );
\retbuf[11][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[11][5]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(5),
      I2 => \retbuf_reg[11][4]\,
      I3 => \retbuf_reg[15][7]\(13),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[7]\(1)
    );
\retbuf[11][5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[8][7]\(1),
      O => \retbuf[11][5]_i_2_n_0\
    );
\retbuf[11][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(2),
      I2 => \retbuf_reg[15][7]\(6),
      I3 => \retbuf_reg[11][4]\,
      I4 => \retbuf_reg[15][7]\(14),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[7]\(2)
    );
\retbuf[11][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAABAAAAA"
    )
        port map (
      I0 => \retbuf[8][7]_i_3__0_n_0\,
      I1 => \retbuf_reg[1][0]_0\,
      I2 => \retbuf_reg[4][7]_0\,
      I3 => \retbuf_reg[11][0]\,
      I4 => Q(1),
      I5 => Q(5),
      O => \stateOp_reg[1]_4\(0)
    );
\retbuf[11][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(3),
      I2 => \retbuf_reg[15][7]\(7),
      I3 => \retbuf_reg[11][4]\,
      I4 => \retbuf_reg[15][7]\(15),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[7]\(3)
    );
\retbuf[12][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[12][0]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(0),
      I2 => \retbuf_reg[12][0]_0\,
      I3 => \retbuf_reg[15][7]\(8),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[31]\(0)
    );
\retbuf[12][0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[12][7]\(20),
      O => \retbuf[12][0]_i_2_n_0\
    );
\retbuf[12][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(21),
      I2 => \retbuf_reg[15][7]\(1),
      I3 => \retbuf_reg[12][0]_0\,
      I4 => \retbuf_reg[15][7]\(9),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[31]\(1)
    );
\retbuf[12][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(22),
      I2 => \retbuf_reg[15][7]\(2),
      I3 => \retbuf_reg[12][0]_0\,
      I4 => \retbuf_reg[15][7]\(10),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[31]\(2)
    );
\retbuf[12][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(23),
      I2 => \retbuf_reg[15][7]\(3),
      I3 => \retbuf_reg[12][0]_0\,
      I4 => \retbuf_reg[15][7]\(11),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[31]\(3)
    );
\retbuf[12][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[12][4]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(4),
      I2 => \retbuf_reg[12][0]_0\,
      I3 => \retbuf_reg[15][7]\(12),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[31]\(4)
    );
\retbuf[12][4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[12][7]\(24),
      O => \retbuf[12][4]_i_2_n_0\
    );
\retbuf[12][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[12][5]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(5),
      I2 => \retbuf_reg[12][0]_0\,
      I3 => \retbuf_reg[15][7]\(13),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[31]\(5)
    );
\retbuf[12][5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[12][7]\(25),
      O => \retbuf[12][5]_i_2_n_0\
    );
\retbuf[12][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(26),
      I2 => \retbuf_reg[15][7]\(6),
      I3 => \retbuf_reg[12][0]_0\,
      I4 => \retbuf_reg[15][7]\(14),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[31]\(6)
    );
\retbuf[12][7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAABAAA"
    )
        port map (
      I0 => \retbuf[8][7]_i_3__0_n_0\,
      I1 => \retbuf_reg[1][0]_0\,
      I2 => \retbuf_reg[12][0]\,
      I3 => Q(1),
      I4 => Q(5),
      O => \stateOp_reg[1]_5\(0)
    );
\retbuf[12][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(27),
      I2 => \retbuf_reg[15][7]\(7),
      I3 => \retbuf_reg[12][0]_0\,
      I4 => \retbuf_reg[15][7]\(15),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[31]\(7)
    );
\retbuf[13][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(12),
      I2 => \retbuf_reg[15][7]\(0),
      I3 => \retbuf_reg[13][0]_0\,
      I4 => \retbuf_reg[15][7]\(8),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[23]\(0)
    );
\retbuf[13][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[13][1]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(1),
      I2 => \retbuf_reg[13][0]_0\,
      I3 => \retbuf_reg[15][7]\(9),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[23]\(1)
    );
\retbuf[13][1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[12][7]\(13),
      O => \retbuf[13][1]_i_2_n_0\
    );
\retbuf[13][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[13][2]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(2),
      I2 => \retbuf_reg[13][0]_0\,
      I3 => \retbuf_reg[15][7]\(10),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[23]\(2)
    );
\retbuf[13][2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[12][7]\(14),
      O => \retbuf[13][2]_i_2_n_0\
    );
\retbuf[13][3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[13][3]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(3),
      I2 => \retbuf_reg[13][0]_0\,
      I3 => \retbuf_reg[15][7]\(11),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[23]\(3)
    );
\retbuf[13][3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[12][7]\(15),
      O => \retbuf[13][3]_i_2_n_0\
    );
\retbuf[13][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(16),
      I2 => \retbuf_reg[15][7]\(4),
      I3 => \retbuf_reg[13][0]_0\,
      I4 => \retbuf_reg[15][7]\(12),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[23]\(4)
    );
\retbuf[13][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[13][5]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(5),
      I2 => \retbuf_reg[13][0]_0\,
      I3 => \retbuf_reg[15][7]\(13),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[23]\(5)
    );
\retbuf[13][5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[12][7]\(17),
      O => \retbuf[13][5]_i_2_n_0\
    );
\retbuf[13][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(18),
      I2 => \retbuf_reg[15][7]\(6),
      I3 => \retbuf_reg[13][0]_0\,
      I4 => \retbuf_reg[15][7]\(14),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[23]\(6)
    );
\retbuf[13][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAABAAAAA"
    )
        port map (
      I0 => \retbuf[8][7]_i_3__0_n_0\,
      I1 => \retbuf_reg[1][0]_0\,
      I2 => \retbuf_reg[4][7]_0\,
      I3 => \retbuf_reg[13][0]\,
      I4 => Q(1),
      I5 => Q(5),
      O => \stateOp_reg[1]_6\(0)
    );
\retbuf[13][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(19),
      I2 => \retbuf_reg[15][7]\(7),
      I3 => \retbuf_reg[13][0]_0\,
      I4 => \retbuf_reg[15][7]\(15),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[23]\(7)
    );
\retbuf[14][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(4),
      I2 => \retbuf_reg[15][7]\(0),
      I3 => \retbuf_reg[14][0]_0\,
      I4 => \retbuf_reg[15][7]\(8),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[15]\(0)
    );
\retbuf[14][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[14][1]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(1),
      I2 => \retbuf_reg[14][0]_0\,
      I3 => \retbuf_reg[15][7]\(9),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[15]\(1)
    );
\retbuf[14][1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[12][7]\(5),
      O => \retbuf[14][1]_i_2_n_0\
    );
\retbuf[14][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(6),
      I2 => \retbuf_reg[15][7]\(2),
      I3 => \retbuf_reg[14][0]_0\,
      I4 => \retbuf_reg[15][7]\(10),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[15]\(2)
    );
\retbuf[14][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(7),
      I2 => \retbuf_reg[15][7]\(3),
      I3 => \retbuf_reg[14][0]_0\,
      I4 => \retbuf_reg[15][7]\(11),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[15]\(3)
    );
\retbuf[14][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[14][4]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(4),
      I2 => \retbuf_reg[14][0]_0\,
      I3 => \retbuf_reg[15][7]\(12),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[15]\(4)
    );
\retbuf[14][4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[12][7]\(8),
      O => \retbuf[14][4]_i_2_n_0\
    );
\retbuf[14][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[14][5]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(5),
      I2 => \retbuf_reg[14][0]_0\,
      I3 => \retbuf_reg[15][7]\(13),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[15]\(5)
    );
\retbuf[14][5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[12][7]\(9),
      O => \retbuf[14][5]_i_2_n_0\
    );
\retbuf[14][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(10),
      I2 => \retbuf_reg[15][7]\(6),
      I3 => \retbuf_reg[14][0]_0\,
      I4 => \retbuf_reg[15][7]\(14),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[15]\(6)
    );
\retbuf[14][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABAAAAAAA"
    )
        port map (
      I0 => \retbuf[8][7]_i_3__0_n_0\,
      I1 => \retbuf_reg[1][0]_0\,
      I2 => Q(1),
      I3 => \retbuf_reg[4][7]_0\,
      I4 => \retbuf_reg[14][0]\,
      I5 => Q(5),
      O => \stateOp_reg[1]_7\(0)
    );
\retbuf[14][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(11),
      I2 => \retbuf_reg[15][7]\(7),
      I3 => \retbuf_reg[14][0]_0\,
      I4 => \retbuf_reg[15][7]\(15),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[15]\(7)
    );
\retbuf[15][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8FFF88888888888"
    )
        port map (
      I0 => \pollbuf_reg[3][5]_0\,
      I1 => \^stateop_reg[4]_11\,
      I2 => \retbuf_reg[15][7]\(1),
      I3 => \retbuf_reg[15][1]\,
      I4 => \retbuf_reg[15][7]\(9),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[7]\(0)
    );
\retbuf[15][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8FFF88888888888"
    )
        port map (
      I0 => \pollbuf_reg[3][5]_0\,
      I1 => \^stateop_reg[4]_11\,
      I2 => \retbuf_reg[15][7]\(2),
      I3 => \retbuf_reg[15][1]\,
      I4 => \retbuf_reg[15][7]\(10),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[7]\(1)
    );
\retbuf[15][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8FFF88888888888"
    )
        port map (
      I0 => \pollbuf_reg[3][5]_0\,
      I1 => \^stateop_reg[4]_11\,
      I2 => \retbuf_reg[15][7]\(3),
      I3 => \retbuf_reg[15][1]\,
      I4 => \retbuf_reg[15][7]\(11),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[7]\(2)
    );
\retbuf[15][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(0),
      I2 => \retbuf_reg[15][7]\(4),
      I3 => \retbuf_reg[15][1]\,
      I4 => \retbuf_reg[15][7]\(12),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[7]\(3)
    );
\retbuf[15][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[15][5]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(5),
      I2 => \retbuf_reg[15][1]\,
      I3 => \retbuf_reg[15][7]\(13),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[7]\(4)
    );
\retbuf[15][5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[12][7]\(1),
      O => \retbuf[15][5]_i_2_n_0\
    );
\retbuf[15][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(2),
      I2 => \retbuf_reg[15][7]\(6),
      I3 => \retbuf_reg[15][1]\,
      I4 => \retbuf_reg[15][7]\(14),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[7]\(5)
    );
\retbuf[15][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAABAAAAA"
    )
        port map (
      I0 => \retbuf[8][7]_i_3__0_n_0\,
      I1 => \retbuf_reg[1][0]_0\,
      I2 => \retbuf_reg[4][7]_0\,
      I3 => \retbuf_reg[15][0]_2\,
      I4 => Q(1),
      I5 => Q(5),
      O => \stateOp_reg[1]_8\(0)
    );
\retbuf[15][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[12][7]\(3),
      I2 => \retbuf_reg[15][7]\(7),
      I3 => \retbuf_reg[15][1]\,
      I4 => \retbuf_reg[15][7]\(15),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrB_reg[7]\(6)
    );
\retbuf[16][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEFEE"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]\,
      I2 => \retbuf_reg[16][0]_0\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[16][0]_1\,
      I5 => Q(5),
      O => \resid_reg[0]_3\(0)
    );
\retbuf[16][7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0400FFFF"
    )
        port map (
      I0 => \pollbuf_reg[3][5]\,
      I1 => \pollbuf_reg[3][5]_0\,
      I2 => \pollbuf_reg[1][7]\(0),
      I3 => reqReset_sig_reg_0,
      I4 => \^stateop_reg[4]\,
      O => \retbuf[16][7]_i_3_n_0\
    );
\retbuf[17][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABAAABBBB"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[17][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[16][0]_0\,
      I5 => Q(5),
      O => \resid_reg[0]_4\(0)
    );
\retbuf[18][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBABABA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[17][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[18][0]\,
      I5 => Q(5),
      O => \resid_reg[0]_5\(0)
    );
\retbuf[19][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBABABA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[18][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[19][0]\,
      I5 => Q(5),
      O => \resid_reg[0]_6\(0)
    );
\retbuf[1][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5D5D5DFF5D5D5D5D"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => \stateOp_reg[0]_4\,
      I2 => \retbuf_reg[1][0]\,
      I3 => \retbuf_reg[1][0]_0\,
      I4 => \retbuf_reg[1][0]_1\,
      I5 => \retbuf_reg[1][0]_2\,
      O => \stateOp_reg[4]_8\(0)
    );
\retbuf[1][7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \retbuf_reg[4][7]_2\,
      O => \^stateop_reg[4]_11\
    );
\retbuf[20][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBABABA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[19][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[20][0]\,
      I5 => Q(5),
      O => \resid_reg[0]_7\(0)
    );
\retbuf[21][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBABABA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[20][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[21][0]\,
      I5 => Q(5),
      O => \resid_reg[0]_8\(0)
    );
\retbuf[22][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBABABA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[21][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[22][0]\,
      I5 => Q(5),
      O => \resid_reg[0]_9\(0)
    );
\retbuf[23][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBABABA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[22][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[23][0]\,
      I5 => Q(5),
      O => \resid_reg[0]_10\(0)
    );
\retbuf[24][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBABABA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[23][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[24][0]\,
      I5 => Q(5),
      O => \resid_reg[0]_11\(0)
    );
\retbuf[25][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBABABA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[24][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[25][0]\,
      I5 => Q(5),
      O => \resid_reg[0]_12\(0)
    );
\retbuf[26][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBABABA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[25][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[26][0]\,
      I5 => Q(5),
      O => \resid_reg[0]_13\(0)
    );
\retbuf[27][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBABABA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[26][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[27][0]\,
      I5 => Q(5),
      O => \resid_reg[0]_14\(0)
    );
\retbuf[28][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBABABA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[27][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[28][0]\,
      I5 => Q(5),
      O => \resid_reg[0]_15\(0)
    );
\retbuf[29][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAAE"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[39][7]_2\(1),
      I2 => \retbuf_reg[29][0]\,
      I3 => \retbuf_reg[16][0]_1\,
      I4 => \retbuf_reg[29][0]_0\,
      I5 => Q(5),
      O => \ixRetbufCrc_reg[3]\(0)
    );
\retbuf[2][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5D5D5DFF5D5D5D5D"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => \stateOp_reg[0]_4\,
      I2 => \retbuf_reg[1][0]\,
      I3 => \retbuf_reg[1][0]_0\,
      I4 => \retbuf_reg[2][0]\,
      I5 => \retbuf_reg[1][0]_2\,
      O => \stateOp_reg[4]_9\(0)
    );
\retbuf[2][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A820FFFFA820A820"
    )
        port map (
      I0 => \^stateop_reg[4]_12\,
      I1 => \retbuf_reg[2][7]\,
      I2 => \retbuf_reg[15][7]\(7),
      I3 => \retbuf_reg[15][7]\(15),
      I4 => \retbuf_reg[2][7]_0\,
      I5 => \^stateop_reg[4]_11\,
      O => \crc_imd_reg[7]_0\(0)
    );
\retbuf[30][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBABABA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[30][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[30][0]_0\,
      I5 => Q(5),
      O => \resid_reg[0]_16\(0)
    );
\retbuf[31][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABABBBABA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[30][0]_0\,
      I3 => \retbuf_reg[31][0]\,
      I4 => \txAXIS_tdata_reg[32]_0\(0),
      I5 => Q(5),
      O => \resid_reg[0]_17\(0)
    );
\retbuf[32][6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAA8A"
    )
        port map (
      I0 => \stateOp[0]_i_2_n_0\,
      I1 => Q(4),
      I2 => commok_sig_reg_1,
      I3 => Q(2),
      I4 => Q(5),
      I5 => Q(0),
      O => \^stateop_reg[4]_4\
    );
\retbuf[32][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABAAABBBB"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[32][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[31][0]\,
      I5 => Q(5),
      O => \resid_reg[0]_18\(0)
    );
\retbuf[33][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAABBAB"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[39][7]_2\(0),
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[33][0]\,
      I5 => Q(5),
      O => \ixRetbufCrc_reg[0]\(0)
    );
\retbuf[34][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBBBAAA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[34][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[34][0]_0\,
      I5 => Q(5),
      O => \resid_reg[0]_19\(0)
    );
\retbuf[35][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBABABA"
    )
        port map (
      I0 => \retbuf[16][7]_i_3_n_0\,
      I1 => \retbuf_reg[16][0]_1\,
      I2 => \retbuf_reg[34][0]\,
      I3 => \txAXIS_tdata_reg[32]_0\(0),
      I4 => \retbuf_reg[35][0]\,
      I5 => Q(5),
      O => \resid_reg[0]_20\(0)
    );
\retbuf[36][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000EA00FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg[35][0]\,
      I1 => \txAXIS_tdata_reg[32]_0\(0),
      I2 => \retbuf_reg[36][7]\,
      I3 => \retbuf_reg[4][7]_2\,
      I4 => \retbuf_reg[36][7]_0\,
      I5 => \^stateop_reg[4]_0\,
      O => \resid_reg[0]_0\(0)
    );
\retbuf[37][7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000F800FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg[37][7]\,
      I1 => \txAXIS_tdata_reg[32]_0\(0),
      I2 => \retbuf_reg[36][7]\,
      I3 => \retbuf_reg[4][7]_2\,
      I4 => \retbuf_reg[36][7]_0\,
      I5 => \^stateop_reg[4]_0\,
      O => \resid_reg[0]_1\(0)
    );
\retbuf[38][7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF080000FFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata_reg[32]_0\(0),
      I1 => \retbuf_reg[38][7]\,
      I2 => \retbuf_reg[39][7]_3\,
      I3 => \retbuf_reg[37][7]\,
      I4 => \retbuf_reg[38][7]_0\,
      I5 => \^stateop_reg[4]_0\,
      O => \resid_reg[0]_2\(0)
    );
\retbuf[39][7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000020FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg[39][7]\,
      I1 => \retbuf_reg[39][7]_0\,
      I2 => \retbuf_reg[39][7]_1\,
      I3 => \retbuf_reg[39][7]_2\(2),
      I4 => \retbuf_reg[39][7]_3\,
      I5 => \^stateop_reg[4]_0\,
      O => \ixRetbufCrc_reg[4]_0\(0)
    );
\retbuf[3][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000A202AAAAA202"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => \retbuf_reg[3][2]\,
      I2 => \retbuf_reg[6][5]\,
      I3 => \retbuf_reg[3][7]_2\(1),
      I4 => \retbuf_reg[4][7]_2\,
      I5 => \retbuf_reg[3][2]_0\,
      O => \TCapt_reg[15]\(0)
    );
\retbuf[3][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000A202AAAAA202"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => \retbuf_reg[3][3]\,
      I2 => \retbuf_reg[6][5]\,
      I3 => \retbuf_reg[3][7]_2\(2),
      I4 => \retbuf_reg[4][7]_2\,
      I5 => \retbuf_reg[3][3]_0\,
      O => \TCapt_reg[15]\(1)
    );
\retbuf[3][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000A202AAAAA202"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => \retbuf_reg[3][6]\,
      I2 => \retbuf_reg[6][5]\,
      I3 => \retbuf_reg[3][7]_2\(3),
      I4 => \retbuf_reg[4][7]_2\,
      I5 => \retbuf_reg[3][6]_0\,
      O => \TCapt_reg[15]\(2)
    );
\retbuf[3][7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F110000FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg[3][7]\,
      I1 => \retbuf_reg[3][7]_0\,
      I2 => \retbuf_reg[3][7]_1\,
      I3 => \retbuf_reg[0][7]_2\,
      I4 => \retbuf_reg[0][7]_3\,
      I5 => \^stateop_reg[4]_1\,
      O => \ixRetbufCrc_reg[4]\(0)
    );
\retbuf[3][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000A202AAAAA202"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => \retbuf_reg[3][7]_3\,
      I2 => \retbuf_reg[6][5]\,
      I3 => \retbuf_reg[3][7]_2\(4),
      I4 => \retbuf_reg[4][7]_2\,
      I5 => \retbuf_reg[3][7]_4\,
      O => \TCapt_reg[15]\(3)
    );
\retbuf[4][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFA820"
    )
        port map (
      I0 => \^stateop_reg[4]_12\,
      I1 => \retbuf_reg[4][0]\,
      I2 => \retbuf_reg[15][7]\(0),
      I3 => \retbuf_reg[15][7]\(8),
      I4 => \retbuf[4][0]_i_2_n_0\,
      O => \TCapt_reg[7]\(0)
    );
\retbuf[4][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4040404040404044"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_3\,
      I2 => \retbuf_reg[4][0]_0\,
      I3 => \retbuf_reg[6][5]\,
      I4 => \pollbuf_reg[0][7]_0\(3),
      I5 => \retbuf_reg[4][0]_1\,
      O => \retbuf[4][0]_i_2_n_0\
    );
\retbuf[4][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4040404040404044"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_3\,
      I2 => \retbuf_reg[4][1]\,
      I3 => \retbuf_reg[6][5]\,
      I4 => \pollbuf_reg[0][7]_0\(3),
      I5 => \retbuf_reg[4][1]_0\,
      O => \tixVController_reg[3]\
    );
\retbuf[4][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4040404040404044"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_3\,
      I2 => \retbuf_reg[4][2]\,
      I3 => \retbuf_reg[6][5]\,
      I4 => \pollbuf_reg[0][7]_0\(3),
      I5 => \retbuf_reg[4][2]_0\,
      O => \tixVController_reg[3]_0\
    );
\retbuf[4][3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFA820"
    )
        port map (
      I0 => \^stateop_reg[4]_12\,
      I1 => \retbuf_reg[4][0]\,
      I2 => \retbuf_reg[15][7]\(3),
      I3 => \retbuf_reg[15][7]\(11),
      I4 => \retbuf[4][3]_i_2_n_0\,
      O => \TCapt_reg[7]\(1)
    );
\retbuf[4][3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4040404040404044"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_3\,
      I2 => \retbuf_reg[4][3]\,
      I3 => \retbuf_reg[6][5]\,
      I4 => \pollbuf_reg[0][7]_0\(3),
      I5 => \retbuf_reg[4][3]_0\,
      O => \retbuf[4][3]_i_2_n_0\
    );
\retbuf[4][7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF100000FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg[4][7]\,
      I1 => Q(5),
      I2 => \retbuf_reg[4][7]_0\,
      I3 => \retbuf_reg[4][7]_1\,
      I4 => \retbuf_reg[0][7]_3\,
      I5 => \^stateop_reg[4]\,
      O => \stateOp_reg[5]_0\(0)
    );
\retbuf[4][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00F4000000F400"
    )
        port map (
      I0 => \retbuf_reg[4][7]_3\,
      I1 => \retbuf_reg[3][7]_2\(0),
      I2 => \retbuf_reg[4][7]_4\,
      I3 => \^stateop_reg[4]\,
      I4 => \retbuf_reg[4][7]_2\,
      I5 => \retbuf_reg[4][7]_5\,
      O => \TCapt_reg[7]\(2)
    );
\retbuf[5][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5D5D5D5D5DFF5D5D"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => \stateOp_reg[0]_4\,
      I2 => \retbuf_reg[5][0]\,
      I3 => \retbuf_reg[5][0]_0\,
      I4 => Q(1),
      I5 => Q(5),
      O => \stateOp_reg[1]\(0)
    );
\retbuf[6][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A02AAAA8A02"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => \retbuf_reg[6][5]\,
      I2 => \retbuf_reg[6][5]_0\,
      I3 => vidtrackGetInfoPtr0Seqbuf(0),
      I4 => \retbuf_reg[4][7]_2\,
      I5 => \retbuf_reg[6][5]_1\,
      O => \stateOp_reg[4]_10\(0)
    );
\retbuf[6][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5D5D5D5D5DFF5D5D"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => \stateOp_reg[0]_4\,
      I2 => \retbuf_reg[5][0]\,
      I3 => \retbuf_reg[6][0]\,
      I4 => Q(1),
      I5 => Q(5),
      O => \stateOp_reg[1]_0\(0)
    );
\retbuf[7][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[7][7]_2\(0),
      I2 => \retbuf_reg[15][7]\(4),
      I3 => \retbuf_reg[7][4]\,
      I4 => \retbuf_reg[15][7]\(12),
      I5 => \^stateop_reg[4]_12\,
      O => \crc_imd_reg[7]\(0)
    );
\retbuf[7][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000A808AAAAA808"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => \retbuf_reg[7][7]_2\(1),
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[7][5]\,
      I4 => \retbuf_reg[4][7]_2\,
      I5 => \retbuf_reg[7][5]_0\,
      O => \crc_imd_reg[7]\(1)
    );
\retbuf[7][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[7][7]_2\(2),
      I2 => \retbuf_reg[15][7]\(6),
      I3 => \retbuf_reg[7][4]\,
      I4 => \retbuf_reg[15][7]\(14),
      I5 => \^stateop_reg[4]_12\,
      O => \crc_imd_reg[7]\(2)
    );
\retbuf[7][6]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \pollbuf_reg[3][5]_0\,
      I1 => \retbuf_reg[4][7]_2\,
      I2 => \^stateop_reg[4]_3\,
      O => \retbuf[7][6]_i_2_n_0\
    );
\retbuf[7][7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FD550000FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg[7][7]\,
      I1 => \retbuf_reg[7][7]_0\,
      I2 => \retbuf_reg[7][7]_1\,
      I3 => \retbuf_reg[0][7]_1\,
      I4 => \retbuf_reg[0][7]_3\,
      I5 => \^stateop_reg[4]_1\,
      O => \stateOp_reg[5]_1\(0)
    );
\retbuf[7][7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[7][7]_i_5_n_0\,
      I1 => \retbuf_reg[15][7]\(7),
      I2 => \retbuf_reg[7][4]\,
      I3 => \retbuf_reg[15][7]\(15),
      I4 => \^stateop_reg[4]_12\,
      O => \crc_imd_reg[7]\(3)
    );
\retbuf[7][7]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04440400"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_3\,
      I2 => \retbuf_reg[7][5]\,
      I3 => \pollbuf_reg[3][5]_0\,
      I4 => \retbuf_reg[7][7]_2\(3),
      O => \retbuf[7][7]_i_5_n_0\
    );
\retbuf[8][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(20),
      I2 => \retbuf_reg[15][7]\(0),
      I3 => \retbuf_reg[8][0]_0\,
      I4 => \retbuf_reg[15][7]\(8),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[31]\(0)
    );
\retbuf[8][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(21),
      I2 => \retbuf_reg[15][7]\(1),
      I3 => \retbuf_reg[8][0]_0\,
      I4 => \retbuf_reg[15][7]\(9),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[31]\(1)
    );
\retbuf[8][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(22),
      I2 => \retbuf_reg[15][7]\(2),
      I3 => \retbuf_reg[8][0]_0\,
      I4 => \retbuf_reg[15][7]\(10),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[31]\(2)
    );
\retbuf[8][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(23),
      I2 => \retbuf_reg[15][7]\(3),
      I3 => \retbuf_reg[8][0]_0\,
      I4 => \retbuf_reg[15][7]\(11),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[31]\(3)
    );
\retbuf[8][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(24),
      I2 => \retbuf_reg[15][7]\(4),
      I3 => \retbuf_reg[8][0]_0\,
      I4 => \retbuf_reg[15][7]\(12),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[31]\(4)
    );
\retbuf[8][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[8][5]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(5),
      I2 => \retbuf_reg[8][0]_0\,
      I3 => \retbuf_reg[15][7]\(13),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[31]\(5)
    );
\retbuf[8][5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[8][7]\(25),
      O => \retbuf[8][5]_i_2_n_0\
    );
\retbuf[8][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(26),
      I2 => \retbuf_reg[15][7]\(6),
      I3 => \retbuf_reg[8][0]_0\,
      I4 => \retbuf_reg[15][7]\(14),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[31]\(6)
    );
\retbuf[8][7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAABAAA"
    )
        port map (
      I0 => \retbuf[8][7]_i_3__0_n_0\,
      I1 => \retbuf_reg[1][0]_0\,
      I2 => \retbuf_reg[8][0]\,
      I3 => Q(1),
      I4 => Q(5),
      O => \stateOp_reg[1]_1\(0)
    );
\retbuf[8][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(27),
      I2 => \retbuf_reg[15][7]\(7),
      I3 => \retbuf_reg[8][0]_0\,
      I4 => \retbuf_reg[15][7]\(15),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[31]\(7)
    );
\retbuf[8][7]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00004404FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg[15][0]\,
      I1 => reqReset_sig_reg_0,
      I2 => \retbuf_reg[15][0]_0\,
      I3 => \retbuf_reg[15][0]_1\,
      I4 => reqReset_sig_reg_1,
      I5 => \^stateop_reg[4]\,
      O => \retbuf[8][7]_i_3__0_n_0\
    );
\retbuf[9][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(12),
      I2 => \retbuf_reg[15][7]\(0),
      I3 => \retbuf_reg[9][0]_0\,
      I4 => \retbuf_reg[15][7]\(8),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[23]\(0)
    );
\retbuf[9][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(13),
      I2 => \retbuf_reg[15][7]\(1),
      I3 => \retbuf_reg[9][0]_0\,
      I4 => \retbuf_reg[15][7]\(9),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[23]\(1)
    );
\retbuf[9][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(14),
      I2 => \retbuf_reg[15][7]\(2),
      I3 => \retbuf_reg[9][0]_0\,
      I4 => \retbuf_reg[15][7]\(10),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[23]\(2)
    );
\retbuf[9][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(15),
      I2 => \retbuf_reg[15][7]\(3),
      I3 => \retbuf_reg[9][0]_0\,
      I4 => \retbuf_reg[15][7]\(11),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[23]\(3)
    );
\retbuf[9][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(16),
      I2 => \retbuf_reg[15][7]\(4),
      I3 => \retbuf_reg[9][0]_0\,
      I4 => \retbuf_reg[15][7]\(12),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[23]\(4)
    );
\retbuf[9][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEAAAAA"
    )
        port map (
      I0 => \retbuf[9][5]_i_2_n_0\,
      I1 => \retbuf_reg[15][7]\(5),
      I2 => \retbuf_reg[9][0]_0\,
      I3 => \retbuf_reg[15][7]\(13),
      I4 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[23]\(5)
    );
\retbuf[9][5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \retbuf_reg[4][7]_2\,
      I1 => \^stateop_reg[4]_0\,
      I2 => \pollbuf_reg[3][5]_0\,
      I3 => \retbuf_reg[8][7]\(17),
      O => \retbuf[9][5]_i_2_n_0\
    );
\retbuf[9][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(18),
      I2 => \retbuf_reg[15][7]\(6),
      I3 => \retbuf_reg[9][0]_0\,
      I4 => \retbuf_reg[15][7]\(14),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[23]\(6)
    );
\retbuf[9][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAABAAAAA"
    )
        port map (
      I0 => \retbuf[8][7]_i_3__0_n_0\,
      I1 => \retbuf_reg[1][0]_0\,
      I2 => \retbuf_reg[4][7]_0\,
      I3 => \retbuf_reg[9][0]\,
      I4 => Q(1),
      I5 => Q(5),
      O => \stateOp_reg[1]_2\(0)
    );
\retbuf[9][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \retbuf[7][6]_i_2_n_0\,
      I1 => \retbuf_reg[8][7]\(19),
      I2 => \retbuf_reg[15][7]\(7),
      I3 => \retbuf_reg[9][0]_0\,
      I4 => \retbuf_reg[15][7]\(15),
      I5 => \^stateop_reg[4]_12\,
      O => \NWrA_reg[23]\(7)
    );
\rxlen[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFAA20AA"
    )
        port map (
      I0 => rxlen,
      I1 => \rxlen_reg[0]_3\,
      I2 => \rxlen[0]_i_4_n_0\,
      I3 => \^stateop_reg[4]\,
      I4 => \rxlen_reg[0]_4\,
      O => \rxlen_reg[0]\
    );
\rxlen[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00080008000800"
    )
        port map (
      I0 => \rxlen_reg[0]_0\,
      I1 => \rxlen_reg[0]_1\,
      I2 => Q(5),
      I3 => \^stateop_reg[4]\,
      I4 => \rxlen_reg[0]_2\,
      I5 => \wordcntLast_reg[0]_2\,
      O => rxlen
    );
\rxlen[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEAAAAAAAAAAAAF"
    )
        port map (
      I0 => \stateOp[5]_i_18_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(2),
      I4 => Q(3),
      I5 => Q(4),
      O => \rxlen[0]_i_4_n_0\
    );
\sendAXIL_rdata[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(0),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[0]_i_1_n_0\
    );
\sendAXIL_rdata[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(10),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[10]_i_1_n_0\
    );
\sendAXIL_rdata[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(11),
      O => \sendAXIL_rdata[11]_i_1_n_0\
    );
\sendAXIL_rdata[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(12),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[12]_i_1_n_0\
    );
\sendAXIL_rdata[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(13),
      O => \sendAXIL_rdata[13]_i_1_n_0\
    );
\sendAXIL_rdata[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(14),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[14]_i_1_n_0\
    );
\sendAXIL_rdata[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(15),
      O => \sendAXIL_rdata[15]_i_1_n_0\
    );
\sendAXIL_rdata[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(16),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[16]_i_1_n_0\
    );
\sendAXIL_rdata[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(17),
      O => \sendAXIL_rdata[17]_i_1_n_0\
    );
\sendAXIL_rdata[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(18),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[18]_i_1_n_0\
    );
\sendAXIL_rdata[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(19),
      O => \sendAXIL_rdata[19]_i_1_n_0\
    );
\sendAXIL_rdata[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(1),
      O => \sendAXIL_rdata[1]_i_1_n_0\
    );
\sendAXIL_rdata[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(20),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[20]_i_1_n_0\
    );
\sendAXIL_rdata[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(21),
      O => \sendAXIL_rdata[21]_i_1_n_0\
    );
\sendAXIL_rdata[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(22),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[22]_i_1_n_0\
    );
\sendAXIL_rdata[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(23),
      O => \sendAXIL_rdata[23]_i_1_n_0\
    );
\sendAXIL_rdata[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(24),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[24]_i_1_n_0\
    );
\sendAXIL_rdata[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(25),
      O => \sendAXIL_rdata[25]_i_1_n_0\
    );
\sendAXIL_rdata[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(26),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[26]_i_1_n_0\
    );
\sendAXIL_rdata[27]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(27),
      O => \sendAXIL_rdata[27]_i_1_n_0\
    );
\sendAXIL_rdata[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(28),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[28]_i_1_n_0\
    );
\sendAXIL_rdata[29]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(29),
      O => \sendAXIL_rdata[29]_i_1_n_0\
    );
\sendAXIL_rdata[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(2),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[2]_i_1_n_0\
    );
\sendAXIL_rdata[30]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(30),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[30]_i_1_n_0\
    );
\sendAXIL_rdata[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(31),
      O => \sendAXIL_rdata[31]_i_1_n_0\
    );
\sendAXIL_rdata[32]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(32),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[32]_i_1_n_0\
    );
\sendAXIL_rdata[33]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(33),
      O => \sendAXIL_rdata[33]_i_1_n_0\
    );
\sendAXIL_rdata[34]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(34),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[34]_i_1_n_0\
    );
\sendAXIL_rdata[35]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(35),
      O => \sendAXIL_rdata[35]_i_1_n_0\
    );
\sendAXIL_rdata[36]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(36),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[36]_i_1_n_0\
    );
\sendAXIL_rdata[37]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(37),
      O => \sendAXIL_rdata[37]_i_1_n_0\
    );
\sendAXIL_rdata[38]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(38),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[38]_i_1_n_0\
    );
\sendAXIL_rdata[39]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(39),
      O => \sendAXIL_rdata[39]_i_1_n_0\
    );
\sendAXIL_rdata[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(3),
      O => \sendAXIL_rdata[3]_i_1_n_0\
    );
\sendAXIL_rdata[40]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(40),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[40]_i_1_n_0\
    );
\sendAXIL_rdata[41]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(41),
      O => \sendAXIL_rdata[41]_i_1_n_0\
    );
\sendAXIL_rdata[42]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(42),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[42]_i_1_n_0\
    );
\sendAXIL_rdata[43]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(43),
      O => \sendAXIL_rdata[43]_i_1_n_0\
    );
\sendAXIL_rdata[44]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(44),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[44]_i_1_n_0\
    );
\sendAXIL_rdata[45]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(45),
      O => \sendAXIL_rdata[45]_i_1_n_0\
    );
\sendAXIL_rdata[46]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(46),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[46]_i_1_n_0\
    );
\sendAXIL_rdata[47]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(47),
      O => \sendAXIL_rdata[47]_i_1_n_0\
    );
\sendAXIL_rdata[48]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(48),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[48]_i_1_n_0\
    );
\sendAXIL_rdata[49]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(49),
      O => \sendAXIL_rdata[49]_i_1_n_0\
    );
\sendAXIL_rdata[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(4),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[4]_i_1_n_0\
    );
\sendAXIL_rdata[50]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(50),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[50]_i_1_n_0\
    );
\sendAXIL_rdata[51]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(51),
      O => \sendAXIL_rdata[51]_i_1_n_0\
    );
\sendAXIL_rdata[52]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(52),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[52]_i_1_n_0\
    );
\sendAXIL_rdata[53]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(53),
      O => \sendAXIL_rdata[53]_i_1_n_0\
    );
\sendAXIL_rdata[54]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(54),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[54]_i_1_n_0\
    );
\sendAXIL_rdata[55]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(55),
      O => \sendAXIL_rdata[55]_i_1_n_0\
    );
\sendAXIL_rdata[56]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(56),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[56]_i_1_n_0\
    );
\sendAXIL_rdata[57]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(57),
      O => \sendAXIL_rdata[57]_i_1_n_0\
    );
\sendAXIL_rdata[58]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(58),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[58]_i_1_n_0\
    );
\sendAXIL_rdata[59]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(59),
      O => \sendAXIL_rdata[59]_i_1_n_0\
    );
\sendAXIL_rdata[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(5),
      O => \sendAXIL_rdata[5]_i_1_n_0\
    );
\sendAXIL_rdata[60]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(60),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[60]_i_1_n_0\
    );
\sendAXIL_rdata[61]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(61),
      O => \sendAXIL_rdata[61]_i_1_n_0\
    );
\sendAXIL_rdata[62]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(62),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[62]_i_1_n_0\
    );
\sendAXIL_rdata[63]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F00FF40FFFFFFFF"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      I2 => stateSend(0),
      I3 => \sendAXIL_rdata[63]_i_3_n_0\,
      I4 => \sendAXIL_rdata[63]_i_4_n_0\,
      I5 => \sendAXIL_rdata[63]_i_5_n_0\,
      O => \sendAXIL_rdata[63]_i_1_n_0\
    );
\sendAXIL_rdata[63]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(63),
      O => \sendAXIL_rdata[63]_i_2_n_0\
    );
\sendAXIL_rdata[63]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040000000"
    )
        port map (
      I0 => AXIL_araddr_sig(4),
      I1 => \^axil_arready\,
      I2 => apuAXIL_arvalid,
      I3 => AXIL_araddr_sig(5),
      I4 => stateSend(1),
      I5 => stateSend(2),
      O => \sendAXIL_rdata[63]_i_3_n_0\
    );
\sendAXIL_rdata[63]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFFFEF7FDDFFFFB"
    )
        port map (
      I0 => Q(0),
      I1 => Q(5),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(3),
      I5 => Q(2),
      O => \sendAXIL_rdata[63]_i_4_n_0\
    );
\sendAXIL_rdata[63]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000AAA8AAA8AAA8"
    )
        port map (
      I0 => \stateSend[2]_i_9_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => stateTo(0),
      I5 => stateTo(1),
      O => \sendAXIL_rdata[63]_i_5_n_0\
    );
\sendAXIL_rdata[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(6),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[6]_i_1_n_0\
    );
\sendAXIL_rdata[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(7),
      O => \sendAXIL_rdata[7]_i_1_n_0\
    );
\sendAXIL_rdata[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[63]_0\(8),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[8]_i_1_n_0\
    );
\sendAXIL_rdata[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[63]_0\(9),
      O => \sendAXIL_rdata[9]_i_1_n_0\
    );
\sendAXIL_rdata_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[0]_i_1_n_0\,
      Q => sendAXIL_rdata(0)
    );
\sendAXIL_rdata_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[10]_i_1_n_0\,
      Q => sendAXIL_rdata(10)
    );
\sendAXIL_rdata_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[11]_i_1_n_0\,
      Q => sendAXIL_rdata(11)
    );
\sendAXIL_rdata_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[12]_i_1_n_0\,
      Q => sendAXIL_rdata(12)
    );
\sendAXIL_rdata_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[13]_i_1_n_0\,
      Q => sendAXIL_rdata(13)
    );
\sendAXIL_rdata_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[14]_i_1_n_0\,
      Q => sendAXIL_rdata(14)
    );
\sendAXIL_rdata_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[15]_i_1_n_0\,
      Q => sendAXIL_rdata(15)
    );
\sendAXIL_rdata_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[16]_i_1_n_0\,
      Q => sendAXIL_rdata(16)
    );
\sendAXIL_rdata_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[17]_i_1_n_0\,
      Q => sendAXIL_rdata(17)
    );
\sendAXIL_rdata_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[18]_i_1_n_0\,
      Q => sendAXIL_rdata(18)
    );
\sendAXIL_rdata_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[19]_i_1_n_0\,
      Q => sendAXIL_rdata(19)
    );
\sendAXIL_rdata_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[1]_i_1_n_0\,
      Q => sendAXIL_rdata(1)
    );
\sendAXIL_rdata_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[20]_i_1_n_0\,
      Q => sendAXIL_rdata(20)
    );
\sendAXIL_rdata_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[21]_i_1_n_0\,
      Q => sendAXIL_rdata(21)
    );
\sendAXIL_rdata_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[22]_i_1_n_0\,
      Q => sendAXIL_rdata(22)
    );
\sendAXIL_rdata_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[23]_i_1_n_0\,
      Q => sendAXIL_rdata(23)
    );
\sendAXIL_rdata_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[24]_i_1_n_0\,
      Q => sendAXIL_rdata(24)
    );
\sendAXIL_rdata_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[25]_i_1_n_0\,
      Q => sendAXIL_rdata(25)
    );
\sendAXIL_rdata_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[26]_i_1_n_0\,
      Q => sendAXIL_rdata(26)
    );
\sendAXIL_rdata_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[27]_i_1_n_0\,
      Q => sendAXIL_rdata(27)
    );
\sendAXIL_rdata_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[28]_i_1_n_0\,
      Q => sendAXIL_rdata(28)
    );
\sendAXIL_rdata_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[29]_i_1_n_0\,
      Q => sendAXIL_rdata(29)
    );
\sendAXIL_rdata_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[2]_i_1_n_0\,
      Q => sendAXIL_rdata(2)
    );
\sendAXIL_rdata_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[30]_i_1_n_0\,
      Q => sendAXIL_rdata(30)
    );
\sendAXIL_rdata_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[31]_i_1_n_0\,
      Q => sendAXIL_rdata(31)
    );
\sendAXIL_rdata_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[32]_i_1_n_0\,
      Q => sendAXIL_rdata(32)
    );
\sendAXIL_rdata_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[33]_i_1_n_0\,
      Q => sendAXIL_rdata(33)
    );
\sendAXIL_rdata_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[34]_i_1_n_0\,
      Q => sendAXIL_rdata(34)
    );
\sendAXIL_rdata_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[35]_i_1_n_0\,
      Q => sendAXIL_rdata(35)
    );
\sendAXIL_rdata_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[36]_i_1_n_0\,
      Q => sendAXIL_rdata(36)
    );
\sendAXIL_rdata_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[37]_i_1_n_0\,
      Q => sendAXIL_rdata(37)
    );
\sendAXIL_rdata_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[38]_i_1_n_0\,
      Q => sendAXIL_rdata(38)
    );
\sendAXIL_rdata_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[39]_i_1_n_0\,
      Q => sendAXIL_rdata(39)
    );
\sendAXIL_rdata_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[3]_i_1_n_0\,
      Q => sendAXIL_rdata(3)
    );
\sendAXIL_rdata_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[40]_i_1_n_0\,
      Q => sendAXIL_rdata(40)
    );
\sendAXIL_rdata_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[41]_i_1_n_0\,
      Q => sendAXIL_rdata(41)
    );
\sendAXIL_rdata_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[42]_i_1_n_0\,
      Q => sendAXIL_rdata(42)
    );
\sendAXIL_rdata_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[43]_i_1_n_0\,
      Q => sendAXIL_rdata(43)
    );
\sendAXIL_rdata_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[44]_i_1_n_0\,
      Q => sendAXIL_rdata(44)
    );
\sendAXIL_rdata_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[45]_i_1_n_0\,
      Q => sendAXIL_rdata(45)
    );
\sendAXIL_rdata_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[46]_i_1_n_0\,
      Q => sendAXIL_rdata(46)
    );
\sendAXIL_rdata_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[47]_i_1_n_0\,
      Q => sendAXIL_rdata(47)
    );
\sendAXIL_rdata_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[48]_i_1_n_0\,
      Q => sendAXIL_rdata(48)
    );
\sendAXIL_rdata_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[49]_i_1_n_0\,
      Q => sendAXIL_rdata(49)
    );
\sendAXIL_rdata_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[4]_i_1_n_0\,
      Q => sendAXIL_rdata(4)
    );
\sendAXIL_rdata_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[50]_i_1_n_0\,
      Q => sendAXIL_rdata(50)
    );
\sendAXIL_rdata_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[51]_i_1_n_0\,
      Q => sendAXIL_rdata(51)
    );
\sendAXIL_rdata_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[52]_i_1_n_0\,
      Q => sendAXIL_rdata(52)
    );
\sendAXIL_rdata_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[53]_i_1_n_0\,
      Q => sendAXIL_rdata(53)
    );
\sendAXIL_rdata_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[54]_i_1_n_0\,
      Q => sendAXIL_rdata(54)
    );
\sendAXIL_rdata_reg[55]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[55]_i_1_n_0\,
      Q => sendAXIL_rdata(55)
    );
\sendAXIL_rdata_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[56]_i_1_n_0\,
      Q => sendAXIL_rdata(56)
    );
\sendAXIL_rdata_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[57]_i_1_n_0\,
      Q => sendAXIL_rdata(57)
    );
\sendAXIL_rdata_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[58]_i_1_n_0\,
      Q => sendAXIL_rdata(58)
    );
\sendAXIL_rdata_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[59]_i_1_n_0\,
      Q => sendAXIL_rdata(59)
    );
\sendAXIL_rdata_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[5]_i_1_n_0\,
      Q => sendAXIL_rdata(5)
    );
\sendAXIL_rdata_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[60]_i_1_n_0\,
      Q => sendAXIL_rdata(60)
    );
\sendAXIL_rdata_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[61]_i_1_n_0\,
      Q => sendAXIL_rdata(61)
    );
\sendAXIL_rdata_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[62]_i_1_n_0\,
      Q => sendAXIL_rdata(62)
    );
\sendAXIL_rdata_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[63]_i_2_n_0\,
      Q => sendAXIL_rdata(63)
    );
\sendAXIL_rdata_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[6]_i_1_n_0\,
      Q => sendAXIL_rdata(6)
    );
\sendAXIL_rdata_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[7]_i_1_n_0\,
      Q => sendAXIL_rdata(7)
    );
\sendAXIL_rdata_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[8]_i_1_n_0\,
      Q => sendAXIL_rdata(8)
    );
\sendAXIL_rdata_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[63]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \sendAXIL_rdata[9]_i_1_n_0\,
      Q => sendAXIL_rdata(9)
    );
sendStrbToStart_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"37F7000037070000"
    )
        port map (
      I0 => stateSend(2),
      I1 => sendStrbToStart_i_2_n_0,
      I2 => sendStrbToStart_i_3_n_0,
      I3 => sendStrbToStart_i_4_n_0,
      I4 => \sendAXIL_rdata[63]_i_5_n_0\,
      I5 => sendStrbToStart_reg_n_0,
      O => sendStrbToStart_i_1_n_0
    );
sendStrbToStart_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[59]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[58]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[47]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[1]\,
      O => sendStrbToStart_i_10_n_0
    );
sendStrbToStart_i_11: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFBFFF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[38]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[9]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[49]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[55]\,
      I4 => sendStrbToStart_i_18_n_0,
      O => sendStrbToStart_i_11_n_0
    );
sendStrbToStart_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[27]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[26]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[32]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[8]\,
      O => sendStrbToStart_i_12_n_0
    );
sendStrbToStart_i_13: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[23]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[33]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[35]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[53]\,
      I4 => sendStrbToStart_i_19_n_0,
      O => sendStrbToStart_i_13_n_0
    );
sendStrbToStart_i_14: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[39]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[17]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[37]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[13]\,
      O => sendStrbToStart_i_14_n_0
    );
sendStrbToStart_i_15: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[6]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[12]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[16]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[18]\,
      I4 => sendStrbToStart_i_20_n_0,
      O => sendStrbToStart_i_15_n_0
    );
sendStrbToStart_i_16: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[63]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[5]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[61]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[57]\,
      O => sendStrbToStart_i_16_n_0
    );
sendStrbToStart_i_17: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[22]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[28]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[0]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[30]\,
      I4 => sendStrbToStart_i_21_n_0,
      O => sendStrbToStart_i_17_n_0
    );
sendStrbToStart_i_18: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[41]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[42]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[45]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[40]\,
      O => sendStrbToStart_i_18_n_0
    );
sendStrbToStart_i_19: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => p_0_in(1),
      I1 => \AXIL_wdata_sig_reg_n_0_[14]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[51]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[52]\,
      O => sendStrbToStart_i_19_n_0
    );
sendStrbToStart_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAAFFFFFFFF3FFF"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_4_n_0\,
      I1 => \stateSend[2]_i_3_n_0\,
      I2 => sendStrbToStart0,
      I3 => stateSend(2),
      I4 => stateSend(1),
      I5 => stateSend(0),
      O => sendStrbToStart_i_2_n_0
    );
sendStrbToStart_i_20: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[31]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[29]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[25]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[24]\,
      O => sendStrbToStart_i_20_n_0
    );
sendStrbToStart_i_21: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[21]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[19]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[15]\,
      I3 => p_0_in(0),
      O => sendStrbToStart_i_21_n_0
    );
sendStrbToStart_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFBFFFF"
    )
        port map (
      I0 => sendStrbToStart_i_5_n_0,
      I1 => stateSend(0),
      I2 => stateSend(1),
      I3 => \stateRecv[2]_i_12_n_0\,
      I4 => ixBlkWrite(1),
      I5 => ixBlkWrite(0),
      O => sendStrbToStart_i_3_n_0
    );
sendStrbToStart_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2666"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      I2 => stateSend(0),
      I3 => \sendAXIL_rdata[63]_i_4_n_0\,
      O => sendStrbToStart_i_4_n_0
    );
sendStrbToStart_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => sendStrbToStart_i_6_n_0,
      I1 => sendStrbToStart_i_7_n_0,
      I2 => sendStrbToStart_i_8_n_0,
      I3 => sendStrbToStart_i_9_n_0,
      O => sendStrbToStart_i_5_n_0
    );
sendStrbToStart_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => sendStrbToStart_i_10_n_0,
      I1 => \AXIL_wdata_sig_reg_n_0_[46]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[44]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[43]\,
      I4 => \AXIL_wdata_sig_reg_n_0_[4]\,
      I5 => sendStrbToStart_i_11_n_0,
      O => sendStrbToStart_i_6_n_0
    );
sendStrbToStart_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => sendStrbToStart_i_12_n_0,
      I1 => \AXIL_wdata_sig_reg_n_0_[62]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[54]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[7]\,
      I4 => \AXIL_wdata_sig_reg_n_0_[60]\,
      I5 => sendStrbToStart_i_13_n_0,
      O => sendStrbToStart_i_7_n_0
    );
sendStrbToStart_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFB"
    )
        port map (
      I0 => sendStrbToStart_i_14_n_0,
      I1 => \AXIL_wdata_sig_reg_n_0_[11]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[10]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[36]\,
      I4 => \AXIL_wdata_sig_reg_n_0_[34]\,
      I5 => sendStrbToStart_i_15_n_0,
      O => sendStrbToStart_i_8_n_0
    );
sendStrbToStart_i_9: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => sendStrbToStart_i_16_n_0,
      I1 => \AXIL_wdata_sig_reg_n_0_[56]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[50]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[48]\,
      I4 => \AXIL_wdata_sig_reg_n_0_[20]\,
      I5 => sendStrbToStart_i_17_n_0,
      O => sendStrbToStart_i_9_n_0
    );
sendStrbToStart_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => sendStrbToStart_i_1_n_0,
      Q => sendStrbToStart_reg_n_0
    );
sendStrbToStop_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAAAAA8AAAAA"
    )
        port map (
      I0 => sendStrbToStop_i_2_n_0,
      I1 => sendStrbToStop_i_3_n_0,
      I2 => \sendAXIL_rdata[63]_i_5_n_0\,
      I3 => sendStrbToStop_i_4_n_0,
      I4 => sendStrbToStop_i_5_n_0,
      I5 => sendStrbToStop_reg_n_0,
      O => sendStrbToStop_i_1_n_0
    );
sendStrbToStop_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5F5C0C0C00000000"
    )
        port map (
      I0 => \stateSend[2]_i_5_n_0\,
      I1 => \sendAXIL_rdata[63]_i_3_n_0\,
      I2 => stateSend(0),
      I3 => \stateSend[2]_i_3_n_0\,
      I4 => \stateSend[2]_i_6_n_0\,
      I5 => \sendAXIL_rdata[63]_i_5_n_0\,
      O => sendStrbToStop_i_2_n_0
    );
sendStrbToStop_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400040007000400"
    )
        port map (
      I0 => \stateSend[2]_i_5_n_0\,
      I1 => stateSend(0),
      I2 => stateSend(1),
      I3 => stateSend(2),
      I4 => \stateSend[2]_i_3_n_0\,
      I5 => sendStrbToStart0,
      O => sendStrbToStop_i_3_n_0
    );
sendStrbToStop_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      I2 => stateSend(0),
      O => sendStrbToStop_i_4_n_0
    );
sendStrbToStop_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFDFDFDFCFDFDFDF"
    )
        port map (
      I0 => stateSend(0),
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => AXIL_araddr_sig(5),
      I4 => strbRead,
      I5 => AXIL_araddr_sig(4),
      O => sendStrbToStop_i_5_n_0
    );
sendStrbToStop_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => sendStrbToStop_i_1_n_0,
      Q => sendStrbToStop_reg_n_0
    );
\stateOp[0]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000002A2AAAA02A2"
    )
        port map (
      I0 => \stateOp[0]_i_2_n_0\,
      I1 => \stateOp_reg[0]_6\,
      I2 => Q(4),
      I3 => \stateOp[0]_i_4_n_0\,
      I4 => Q(5),
      I5 => \stateOp_reg[0]_7\,
      O => \stateOp_reg[5]_4\(0)
    );
\stateOp[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BF00BFBFBFBFBFBF"
    )
        port map (
      I0 => \^stateop_reg[0]_0\,
      I1 => \stateOp_reg[0]_8\(0),
      I2 => \stateOp_reg[0]_8\(1),
      I3 => \^staterecv_reg[0]_1\,
      I4 => \stateOp_reg[0]_9\(0),
      I5 => \stateOp_reg[0]_9\(1),
      O => \stateOp[0]_i_2_n_0\
    );
\stateOp[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A0FEFEF0F0F0A0"
    )
        port map (
      I0 => Q(3),
      I1 => \stateOp[4]_i_6_n_0\,
      I2 => Q(0),
      I3 => crcAXIS_tlast_sig_reg_3,
      I4 => Q(1),
      I5 => Q(2),
      O => \stateOp[0]_i_4_n_0\
    );
\stateOp[1]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      O => \stateOp[1]_i_10_n_0\
    );
\stateOp[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F1FFFF00000000"
    )
        port map (
      I0 => \stateOp_reg[1]_10\,
      I1 => \stateOp_reg[1]_11\,
      I2 => \stateOp[1]_i_4__1_n_0\,
      I3 => Q(5),
      I4 => \stateOp_reg[1]_12\,
      I5 => \^stateop_reg[4]\,
      O => \stateOp_reg[5]_4\(1)
    );
\stateOp[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEFFFFFFF0FFFF"
    )
        port map (
      I0 => \^staterecv_reg[0]_0\,
      I1 => stateOp_reg,
      I2 => txAXIS_tready,
      I3 => \stateOp_reg[0]_10\,
      I4 => ackRxtx,
      I5 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => \^staterecv_reg[0]_1\
    );
\stateOp[1]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CC0E0C0C"
    )
        port map (
      I0 => \stateOp_reg[0]_11\,
      I1 => \sendAXIL_rdata[63]_i_4_n_0\,
      I2 => \stateOp_reg[0]_12\,
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => ackRxtx,
      I5 => \stateOp_reg[0]_13\,
      O => \^stateop_reg[0]_0\
    );
\stateOp[1]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"800000008000A000"
    )
        port map (
      I0 => \stateOp_reg[1]_13\,
      I1 => crcAXIS_tlast_sig_reg_0(0),
      I2 => Q(0),
      I3 => Q(2),
      I4 => Q(1),
      I5 => \stateOp[3]_i_7_n_0\,
      O => \stateOp[1]_i_4__1_n_0\
    );
\stateOp[1]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => stateSend(0),
      I1 => stateSend(1),
      I2 => stateSend(2),
      O => txAXIS_tready
    );
\stateOp[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7C007C007CFF7C00"
    )
        port map (
      I0 => stateRecv(0),
      I1 => stateRecv(2),
      I2 => stateRecv(1),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => \stateOp[1]_i_9_n_0\,
      I5 => \stateOp[1]_i_10_n_0\,
      O => ackRxtx
    );
\stateOp[1]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => stateSend(1),
      I1 => stateSend(2),
      I2 => stateSend(0),
      O => \stateOp[1]_i_9_n_0\
    );
\stateOp[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0020AAAA002A"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => \stateOp[2]_i_2__1_n_0\,
      I2 => Q(4),
      I3 => Q(5),
      I4 => \stateOp_reg[2]_2\,
      I5 => \stateOp_reg[2]_3\,
      O => \stateOp_reg[5]_4\(2)
    );
\stateOp[2]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCAA33AACC303333"
    )
        port map (
      I0 => \stateOp[2]_i_5__1_n_0\,
      I1 => Q(1),
      I2 => crcAXIS_tlast_sig_reg_3,
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(3),
      O => \stateOp[2]_i_2__1_n_0\
    );
\stateOp[2]_i_5__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FEFFFEF"
    )
        port map (
      I0 => crcAXIS_tlast_sig_reg_0(0),
      I1 => \stateOp[3]_i_3_0\(0),
      I2 => Q(0),
      I3 => Q(1),
      I4 => \stateOp[4]_i_6_n_0\,
      O => \stateOp[2]_i_5__1_n_0\
    );
\stateOp[2]_i_8__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CFBBFF33"
    )
        port map (
      I0 => \stateOp[3]_i_7_n_0\,
      I1 => Q(2),
      I2 => crcAXIS_tlast_sig_reg_0(0),
      I3 => Q(1),
      I4 => Q(0),
      O => \stateOp_reg[2]_1\
    );
\stateOp[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"888888888AAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \stateOp[3]_i_3_n_0\,
      I2 => \stateOp[3]_i_4__0_n_0\,
      I3 => Q(3),
      I4 => Q(2),
      I5 => \stateOp_reg[3]_1\,
      O => \stateOp_reg[5]_4\(3)
    );
\stateOp[3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => Q(5),
      O => \^stateop_reg[5]_6\
    );
\stateOp[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFA0520000"
    )
        port map (
      I0 => Q(0),
      I1 => crcAXIS_tlast_sig_reg_3,
      I2 => Q(1),
      I3 => Q(2),
      I4 => \stateOp_reg[3]_2\,
      I5 => \stateOp[3]_i_6_n_0\,
      O => \stateOp[3]_i_3_n_0\
    );
\stateOp[3]_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => Q(0),
      I1 => \stateOp[3]_i_7_n_0\,
      I2 => Q(1),
      O => \stateOp[3]_i_4__0_n_0\
    );
\stateOp[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAA8A"
    )
        port map (
      I0 => \stateOp[4]_i_3__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => \stateOp[3]_i_3_0\(0),
      I4 => crcAXIS_tlast_sig_reg_0(0),
      I5 => Q(2),
      O => \stateOp[3]_i_6_n_0\
    );
\stateOp[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFD"
    )
        port map (
      I0 => \stateOp[4]_i_6_n_0\,
      I1 => crcAXIS_tlast_sig_i_6_1(3),
      I2 => crcAXIS_tlast_sig_i_6_1(2),
      I3 => \pollbuf_reg[0][7]_1\,
      I4 => crcAXIS_tlast_sig_i_6_1(1),
      I5 => crcAXIS_tlast_sig_i_6_1(0),
      O => \stateOp[3]_i_7_n_0\
    );
\stateOp[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44444440"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \stateOp[4]_i_3__0_n_0\,
      I3 => \stateOp_reg[4]_15\,
      I4 => \stateOp_reg[4]_16\,
      O => \stateOp_reg[5]_4\(4)
    );
\stateOp[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAA8A"
    )
        port map (
      I0 => \stateOp[0]_i_2_n_0\,
      I1 => Q(4),
      I2 => commok_sig_reg_1,
      I3 => Q(2),
      I4 => Q(5),
      I5 => Q(0),
      O => \^stateop_reg[4]\
    );
\stateOp[4]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0088880080888888"
    )
        port map (
      I0 => Q(4),
      I1 => Q(3),
      I2 => \stateOp[4]_i_6_n_0\,
      I3 => Q(0),
      I4 => Q(1),
      I5 => Q(2),
      O => \stateOp[4]_i_3__0_n_0\
    );
\stateOp[4]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => rxAXIS_tdata(3),
      I1 => rxAXIS_tdata(1),
      I2 => \^recvaxis_tdata\(1),
      I3 => rxAXIS_tdata(5),
      I4 => \stateOp[4]_i_7_n_0\,
      O => \stateOp[4]_i_6_n_0\
    );
\stateOp[4]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^recvaxis_tdata\(0),
      I1 => rxAXIS_tdata(2),
      I2 => rxAXIS_tdata(4),
      I3 => rxAXIS_tdata(6),
      O => \stateOp[4]_i_7_n_0\
    );
\stateOp[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEEFEFEEEEEEEEE"
    )
        port map (
      I0 => \stateOp_reg[0]_4\,
      I1 => \stateOp[5]_i_4_n_0\,
      I2 => \stateOp[5]_i_5_n_0\,
      I3 => \stateOp[5]_i_6_n_0\,
      I4 => \stateOp_reg[0]_5\,
      I5 => \stateOp_reg[0]_2\,
      O => \stateOp_reg[3]_0\(0)
    );
\stateOp[5]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => stateSend(0),
      I1 => stateSend(1),
      I2 => stateSend(2),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => \stateOp[5]_i_18_n_0\
    );
\stateOp[5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0001FFFF"
    )
        port map (
      I0 => \stateOp_reg[0]_1\,
      I1 => \stateOp_reg[0]_2\,
      I2 => \wordcntLast_reg[28]\,
      I3 => \stateOp_reg[0]_3\,
      I4 => \^stateop_reg[4]_0\,
      O => \stateOp[5]_i_4_n_0\
    );
\stateOp[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAAC0FFFFFFFF"
    )
        port map (
      I0 => \stateOp[5]_i_18_n_0\,
      I1 => crcAXIS_tlast_sig_reg_0(0),
      I2 => \^staterecv_reg[0]_0\,
      I3 => \stateOp_reg[0]_3\,
      I4 => \stateOp_reg[0]_5\,
      I5 => \stateOp_reg[0]_1\,
      O => \stateOp[5]_i_5_n_0\
    );
\stateOp[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata_reg[8]_1\,
      I1 => \wordcntLast_reg[28]\,
      I2 => \stateOp_reg[0]_1\,
      I3 => \^staterecv_reg[0]_0\,
      I4 => \stateOp_reg[0]_3\,
      I5 => txAXIS_tready,
      O => \stateOp[5]_i_6_n_0\
    );
\stateOp[5]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAA8A"
    )
        port map (
      I0 => \stateOp[0]_i_2_n_0\,
      I1 => Q(4),
      I2 => commok_sig_reg_1,
      I3 => Q(2),
      I4 => Q(5),
      I5 => Q(0),
      O => \^stateop_reg[4]_0\
    );
\stateOp_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5155"
    )
        port map (
      I0 => crcAXIS_tlast_sig_reg_3,
      I1 => \^staterecv_reg[0]_0\,
      I2 => stateOp_reg,
      I3 => \^recvaxis_tlast\,
      O => crcAXIS_tlast_sig_reg
    );
\stateOp_next[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \stateOp_next_reg[5]_0\,
      I1 => \stateOp_next_reg[4]\,
      I2 => \stateOp_next_reg[1]\,
      I3 => \stateOp_next_reg[5]_1\,
      I4 => \^stateop_reg[4]\,
      O => \len_reg[2]\(0)
    );
\stateOp_next[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA08A8"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => \stateOp_next_reg[1]\,
      I2 => \stateOp_next_reg[5]_0\,
      I3 => \stateOp_next_reg[5]\,
      I4 => \stateOp_next_reg[5]_1\,
      O => \len_reg[2]\(1)
    );
\stateOp_next[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \stateOp_next_reg[5]_0\,
      I1 => \stateOp_next_reg[5]\,
      I2 => \stateOp_next_reg[5]_1\,
      I3 => \^stateop_reg[4]\,
      O => \len_reg[2]\(2)
    );
\stateOp_next[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40504000"
    )
        port map (
      I0 => \stateOp_next_reg[5]_1\,
      I1 => \stateOp_next_reg[5]\,
      I2 => \^stateop_reg[4]\,
      I3 => \stateOp_next_reg[5]_0\,
      I4 => \stateOp_next_reg[4]\,
      O => \len_reg[2]\(3)
    );
\stateOp_next[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555555555555D555"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => \stateOp_next_reg[0]\,
      I2 => Q(2),
      I3 => Q(0),
      I4 => Q(1),
      I5 => Q(5),
      O => \stateOp_reg[2]_0\(0)
    );
\stateOp_next[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \stateOp_next_reg[5]_0\,
      I1 => \stateOp_next_reg[5]\,
      I2 => \^stateop_reg[4]\,
      I3 => \stateOp_next_reg[5]_1\,
      O => \len_reg[2]\(4)
    );
\stateRecv[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"06FF060006000600"
    )
        port map (
      I0 => stateRecv(2),
      I1 => stateRecv(1),
      I2 => stateRecv(0),
      I3 => p_1_in0,
      I4 => req,
      I5 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      O => \stateRecv[0]_i_1_n_0\
    );
\stateRecv[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA2A2A2A2A2A2A00"
    )
        port map (
      I0 => \stateRecv[2]_i_9__0_n_0\,
      I1 => stateTo(0),
      I2 => stateTo(1),
      I3 => stateRecv(0),
      I4 => stateRecv(1),
      I5 => stateRecv(2),
      O => p_1_in0
    );
\stateRecv[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCC4C0CCCCC0"
    )
        port map (
      I0 => \^recvaxis_tlast\,
      I1 => \stateRecv[2]_i_9__0_n_0\,
      I2 => \stateSend[2]_i_10_n_0\,
      I3 => stateRecv(0),
      I4 => stateRecv(1),
      I5 => stateRecv(2),
      O => \stateRecv[1]_i_1_n_0\
    );
\stateRecv[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFEFFFFFFFE"
    )
        port map (
      I0 => \stateRecv[2]_i_3_n_0\,
      I1 => \stateRecv[2]_i_4_n_0\,
      I2 => \stateRecv[2]_i_5_n_0\,
      I3 => \stateRecv[2]_i_6__0_n_0\,
      I4 => \stateRecv[2]_i_7_n_0\,
      I5 => \stateRecv[2]_i_8_n_0\,
      O => \stateRecv[2]_i_1_n_0\
    );
\stateRecv[2]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFBFFFFFF"
    )
        port map (
      I0 => sendStrbToStart_i_5_n_0,
      I1 => stateRecv(0),
      I2 => ixBlkWrite(0),
      I3 => \^axil_bvalid_sig_reg_0\,
      I4 => apuAXIL_bready,
      I5 => ixBlkWrite(1),
      O => \stateRecv[2]_i_10_n_0\
    );
\stateRecv[2]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002080409000040"
    )
        port map (
      I0 => Q(3),
      I1 => Q(1),
      I2 => Q(5),
      I3 => Q(4),
      I4 => Q(2),
      I5 => Q(0),
      O => p_33_in
    );
\stateRecv[2]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^axil_bvalid_sig_reg_0\,
      I1 => apuAXIL_bready,
      O => \stateRecv[2]_i_12_n_0\
    );
\stateRecv[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCC8CCC0C0C0"
    )
        port map (
      I0 => \^recvaxis_tlast\,
      I1 => \stateRecv[2]_i_9__0_n_0\,
      I2 => \stateSend[2]_i_10_n_0\,
      I3 => stateRecv(0),
      I4 => stateRecv(1),
      I5 => stateRecv(2),
      O => \stateRecv[2]_i_2_n_0\
    );
\stateRecv[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => stateRecv(2),
      I1 => stateRecv(1),
      I2 => \stateRecv[2]_i_10_n_0\,
      O => \stateRecv[2]_i_3_n_0\
    );
\stateRecv[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0400FFFF"
    )
        port map (
      I0 => stateRecv(0),
      I1 => stateRecv(1),
      I2 => stateRecv(2),
      I3 => \recvAXIL_rdata[63]_i_2_n_0\,
      I4 => p_1_in0,
      O => \stateRecv[2]_i_4_n_0\
    );
\stateRecv[2]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => stateRecv(1),
      I1 => stateRecv(0),
      I2 => stateRecv(2),
      I3 => p_33_in,
      O => \stateRecv[2]_i_5_n_0\
    );
\stateRecv[2]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => stateRecv(1),
      I1 => stateRecv(2),
      I2 => ixBlkWrite(0),
      I3 => ixBlkWrite(1),
      I4 => \stateRecv[2]_i_12_n_0\,
      I5 => stateRecv(0),
      O => \stateRecv[2]_i_6__0_n_0\
    );
\stateRecv[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \stateSend[2]_i_11_n_0\,
      I1 => ixBlkWrite(0),
      I2 => \stateRecv[2]_i_12_n_0\,
      I3 => ixBlkWrite(1),
      I4 => stateRecv(1),
      I5 => stateRecv(2),
      O => \stateRecv[2]_i_7_n_0\
    );
\stateRecv[2]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => stateRecv(2),
      I1 => stateRecv(0),
      O => \stateRecv[2]_i_8_n_0\
    );
\stateRecv[2]_i_9__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004082209000020"
    )
        port map (
      I0 => Q(1),
      I1 => Q(3),
      I2 => Q(5),
      I3 => Q(4),
      I4 => Q(2),
      I5 => Q(0),
      O => \stateRecv[2]_i_9__0_n_0\
    );
\stateRecv_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateRecv[2]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \stateRecv[0]_i_1_n_0\,
      Q => stateRecv(0)
    );
\stateRecv_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateRecv[2]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \stateRecv[1]_i_1_n_0\,
      Q => stateRecv(1)
    );
\stateRecv_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateRecv[2]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \stateRecv[2]_i_2_n_0\,
      Q => stateRecv(2)
    );
\stateSend[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAA002A002A002A"
    )
        port map (
      I0 => \stateSend[2]_i_9_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => stateTo(1),
      I5 => stateTo(0),
      O => \stateSend[0]_i_1_n_0\
    );
\stateSend[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCCCC0CCCC40"
    )
        port map (
      I0 => sendStrbToStart0,
      I1 => \stateSend[2]_i_9_n_0\,
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      I5 => \stateSend[2]_i_10_n_0\,
      O => \stateSend[1]_i_1_n_0\
    );
\stateSend[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF8B00"
    )
        port map (
      I0 => \stateSend[2]_i_3_n_0\,
      I1 => \stateSend[2]_i_4_n_0\,
      I2 => \stateSend[2]_i_5_n_0\,
      I3 => \stateSend[2]_i_6_n_0\,
      I4 => \stateSend[2]_i_7_n_0\,
      I5 => \sendAXIL_rdata[63]_i_1_n_0\,
      O => \stateSend[2]_i_1_n_0\
    );
\stateSend[2]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateTo(1),
      I1 => stateTo(0),
      O => \stateSend[2]_i_10_n_0\
    );
\stateSend[2]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \stateSend[2]_i_16_n_0\,
      I1 => \stateSend[2]_i_17_n_0\,
      I2 => \stateSend[2]_i_18_n_0\,
      I3 => \stateSend[2]_i_19_n_0\,
      O => \stateSend[2]_i_11_n_0\
    );
\stateSend[2]_i_13\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcnt_reg(30),
      O => \stateSend[2]_i_13_n_0\
    );
\stateSend[2]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000090005050009"
    )
        port map (
      I0 => wordcnt_reg(28),
      I1 => recvAXIS_tlast_sig_reg_i_2_0(28),
      I2 => wordcnt_reg(29),
      I3 => recvAXIS_tlast_sig_reg_i_2_0(27),
      I4 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I5 => wordcnt_reg(27),
      O => \stateSend[2]_i_14_n_0\
    );
\stateSend[2]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => \stateSend[2]_i_28_n_0\,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(25),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => wordcnt_reg(25),
      O => \stateSend[2]_i_15_n_0\
    );
\stateSend[2]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFBFFF"
    )
        port map (
      I0 => \stateSend[2]_i_29_n_0\,
      I1 => \AXIL_wdata_sig_reg_n_0_[4]\,
      I2 => p_0_in(0),
      I3 => \AXIL_wdata_sig_reg_n_0_[18]\,
      I4 => \AXIL_wdata_sig_reg_n_0_[23]\,
      I5 => \stateSend[2]_i_30_n_0\,
      O => \stateSend[2]_i_16_n_0\
    );
\stateSend[2]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \stateSend[2]_i_31_n_0\,
      I1 => \AXIL_wdata_sig_reg_n_0_[52]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[48]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[49]\,
      I4 => \AXIL_wdata_sig_reg_n_0_[13]\,
      I5 => \stateSend[2]_i_32_n_0\,
      O => \stateSend[2]_i_17_n_0\
    );
\stateSend[2]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEFFFFFF"
    )
        port map (
      I0 => \stateSend[2]_i_33_n_0\,
      I1 => \AXIL_wdata_sig_reg_n_0_[61]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[51]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[42]\,
      I4 => \AXIL_wdata_sig_reg_n_0_[34]\,
      I5 => \stateSend[2]_i_34_n_0\,
      O => \stateSend[2]_i_18_n_0\
    );
\stateSend[2]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => \stateSend[2]_i_35_n_0\,
      I1 => \AXIL_wdata_sig_reg_n_0_[53]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[43]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[30]\,
      I4 => \AXIL_wdata_sig_reg_n_0_[21]\,
      I5 => \stateSend[2]_i_36_n_0\,
      O => \stateSend[2]_i_19_n_0\
    );
\stateSend[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCCCCCC0C080"
    )
        port map (
      I0 => sendStrbToStart0,
      I1 => \stateSend[2]_i_9_n_0\,
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      I5 => \stateSend[2]_i_10_n_0\,
      O => \stateSend[2]_i_2_n_0\
    );
\stateSend[2]_i_20\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => \stateSend[2]_i_37_n_0\,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(22),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => wordcnt_reg(22),
      O => \stateSend[2]_i_20_n_0\
    );
\stateSend[2]_i_21\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => \stateSend[2]_i_38_n_0\,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(19),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => wordcnt_reg(19),
      O => \stateSend[2]_i_21_n_0\
    );
\stateSend[2]_i_22\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => \stateSend[2]_i_39_n_0\,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(15),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => wordcnt_reg(15),
      O => \stateSend[2]_i_22_n_0\
    );
\stateSend[2]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => \stateSend[2]_i_40_n_0\,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(12),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => wordcnt_reg(12),
      O => \stateSend[2]_i_23_n_0\
    );
\stateSend[2]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => \stateSend[2]_i_41_n_0\,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(10),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => wordcnt_reg(10),
      O => \stateSend[2]_i_24_n_0\
    );
\stateSend[2]_i_25\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => \stateSend[2]_i_42_n_0\,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(7),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => wordcnt_reg(7),
      O => \stateSend[2]_i_25_n_0\
    );
\stateSend[2]_i_26\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => \stateSend[2]_i_43_n_0\,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(4),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => wordcnt_reg(4),
      O => \stateSend[2]_i_26_n_0\
    );
\stateSend[2]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"08A2"
    )
        port map (
      I0 => \stateSend[2]_i_44_n_0\,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(1),
      I2 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I3 => wordcnt_reg(1),
      O => \stateSend[2]_i_27_n_0\
    );
\stateSend[2]_i_28\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(24),
      I1 => wordcnt_reg(24),
      I2 => recvAXIS_tlast_sig_reg_i_2_0(26),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => wordcnt_reg(26),
      O => \stateSend[2]_i_28_n_0\
    );
\stateSend[2]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[25]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[17]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[26]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[5]\,
      O => \stateSend[2]_i_29_n_0\
    );
\stateSend[2]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^axil_arready\,
      I1 => apuAXIL_arvalid,
      I2 => AXIL_araddr_sig(5),
      I3 => AXIL_araddr_sig(4),
      O => \stateSend[2]_i_3_n_0\
    );
\stateSend[2]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFBFF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[47]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[20]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[37]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[44]\,
      I4 => \stateSend[2]_i_45_n_0\,
      O => \stateSend[2]_i_30_n_0\
    );
\stateSend[2]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[62]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[16]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[54]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[50]\,
      O => \stateSend[2]_i_31_n_0\
    );
\stateSend[2]_i_32\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEFF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[27]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[35]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[11]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[8]\,
      I4 => \stateSend[2]_i_46_n_0\,
      O => \stateSend[2]_i_32_n_0\
    );
\stateSend[2]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[60]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[56]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[59]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[55]\,
      O => \stateSend[2]_i_33_n_0\
    );
\stateSend[2]_i_34\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF7FF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[6]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[32]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[33]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[46]\,
      I4 => \stateSend[2]_i_47_n_0\,
      O => \stateSend[2]_i_34_n_0\
    );
\stateSend[2]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[40]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[0]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[22]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[63]\,
      O => \stateSend[2]_i_35_n_0\
    );
\stateSend[2]_i_36\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[9]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[10]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[1]\,
      I3 => p_0_in(1),
      I4 => \stateSend[2]_i_48_n_0\,
      O => \stateSend[2]_i_36_n_0\
    );
\stateSend[2]_i_37\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(21),
      I1 => wordcnt_reg(21),
      I2 => recvAXIS_tlast_sig_reg_i_2_0(23),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => wordcnt_reg(23),
      O => \stateSend[2]_i_37_n_0\
    );
\stateSend[2]_i_38\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(18),
      I1 => wordcnt_reg(18),
      I2 => recvAXIS_tlast_sig_reg_i_2_0(20),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => wordcnt_reg(20),
      O => \stateSend[2]_i_38_n_0\
    );
\stateSend[2]_i_39\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(16),
      I1 => wordcnt_reg(16),
      I2 => recvAXIS_tlast_sig_reg_i_2_0(17),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => wordcnt_reg(17),
      O => \stateSend[2]_i_39_n_0\
    );
\stateSend[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      I2 => stateSend(0),
      O => \stateSend[2]_i_4_n_0\
    );
\stateSend[2]_i_40\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(13),
      I1 => wordcnt_reg(13),
      I2 => recvAXIS_tlast_sig_reg_i_2_0(14),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => wordcnt_reg(14),
      O => \stateSend[2]_i_40_n_0\
    );
\stateSend[2]_i_41\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(9),
      I1 => wordcnt_reg(9),
      I2 => recvAXIS_tlast_sig_reg_i_2_0(11),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => wordcnt_reg(11),
      O => \stateSend[2]_i_41_n_0\
    );
\stateSend[2]_i_42\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(6),
      I1 => wordcnt_reg(6),
      I2 => recvAXIS_tlast_sig_reg_i_2_0(8),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => wordcnt_reg(8),
      O => \stateSend[2]_i_42_n_0\
    );
\stateSend[2]_i_43\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00903309"
    )
        port map (
      I0 => recvAXIS_tlast_sig_reg_i_2_0(3),
      I1 => wordcnt_reg(3),
      I2 => recvAXIS_tlast_sig_reg_i_2_0(5),
      I3 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I4 => wordcnt_reg(5),
      O => \stateSend[2]_i_43_n_0\
    );
\stateSend[2]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000C300A5A500C3"
    )
        port map (
      I0 => \rxlen_reg[0]_4\,
      I1 => recvAXIS_tlast_sig_reg_i_2_0(0),
      I2 => wordcnt_reg(0),
      I3 => recvAXIS_tlast_sig_reg_i_2_0(2),
      I4 => \apuAXIL_rdata[63]_INST_0_i_1_n_0\,
      I5 => wordcnt_reg(2),
      O => \stateSend[2]_i_44_n_0\
    );
\stateSend[2]_i_45\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[31]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[29]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[58]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[57]\,
      O => \stateSend[2]_i_45_n_0\
    );
\stateSend[2]_i_46\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[15]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[7]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[36]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[24]\,
      O => \stateSend[2]_i_46_n_0\
    );
\stateSend[2]_i_47\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[38]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[39]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[45]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[41]\,
      O => \stateSend[2]_i_47_n_0\
    );
\stateSend[2]_i_48\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[14]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[12]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[28]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[19]\,
      O => \stateSend[2]_i_48_n_0\
    );
\stateSend[2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFFFFFF"
    )
        port map (
      I0 => ixBlkWrite(0),
      I1 => ixBlkWrite(1),
      I2 => \^axil_bvalid_sig_reg_0\,
      I3 => apuAXIL_bready,
      I4 => \stateSend[2]_i_11_n_0\,
      O => \stateSend[2]_i_5_n_0\
    );
\stateSend[2]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      O => \stateSend[2]_i_6_n_0\
    );
\stateSend[2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => stateSend(2),
      I1 => sendStrbToStart_i_3_n_0,
      O => \stateSend[2]_i_7_n_0\
    );
\stateSend[2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0218070C02060F1C"
    )
        port map (
      I0 => Q(1),
      I1 => Q(3),
      I2 => Q(5),
      I3 => Q(4),
      I4 => Q(2),
      I5 => Q(0),
      O => \stateSend[2]_i_9_n_0\
    );
\stateSend_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSend[2]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \stateSend[0]_i_1_n_0\,
      Q => stateSend(0)
    );
\stateSend_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSend[2]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \stateSend[1]_i_1_n_0\,
      Q => stateSend(1)
    );
\stateSend_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSend[2]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \stateSend[2]_i_2_n_0\,
      Q => stateSend(2)
    );
\stateSend_reg[2]_i_12\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \stateSend_reg[2]_i_12_n_0\,
      CO(6) => \stateSend_reg[2]_i_12_n_1\,
      CO(5) => \stateSend_reg[2]_i_12_n_2\,
      CO(4) => \stateSend_reg[2]_i_12_n_3\,
      CO(3) => \stateSend_reg[2]_i_12_n_4\,
      CO(2) => \stateSend_reg[2]_i_12_n_5\,
      CO(1) => \stateSend_reg[2]_i_12_n_6\,
      CO(0) => \stateSend_reg[2]_i_12_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_stateSend_reg[2]_i_12_O_UNCONNECTED\(7 downto 0),
      S(7) => \stateSend[2]_i_20_n_0\,
      S(6) => \stateSend[2]_i_21_n_0\,
      S(5) => \stateSend[2]_i_22_n_0\,
      S(4) => \stateSend[2]_i_23_n_0\,
      S(3) => \stateSend[2]_i_24_n_0\,
      S(2) => \stateSend[2]_i_25_n_0\,
      S(1) => \stateSend[2]_i_26_n_0\,
      S(0) => \stateSend[2]_i_27_n_0\
    );
\stateSend_reg[2]_i_8\: unisim.vcomponents.CARRY8
     port map (
      CI => \stateSend_reg[2]_i_12_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_stateSend_reg[2]_i_8_CO_UNCONNECTED\(7 downto 3),
      CO(2) => sendStrbToStart0,
      CO(1) => \stateSend_reg[2]_i_8_n_6\,
      CO(0) => \stateSend_reg[2]_i_8_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_stateSend_reg[2]_i_8_O_UNCONNECTED\(7 downto 0),
      S(7 downto 3) => B"00000",
      S(2) => \stateSend[2]_i_13_n_0\,
      S(1) => \stateSend[2]_i_14_n_0\,
      S(0) => \stateSend[2]_i_15_n_0\
    );
\stateTo[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => req,
      I1 => stateTo(1),
      I2 => stateTo(0),
      O => \stateTo[0]_i_1_n_0\
    );
\stateTo[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55FD57FF55FD55FF"
    )
        port map (
      I0 => req,
      I1 => sendStrbToStart_reg_n_0,
      I2 => recvStrbToStart_reg_n_0,
      I3 => stateTo(1),
      I4 => stateTo(0),
      I5 => \stateTo[1]_i_4_n_0\,
      O => \stateTo[1]_i_1_n_0\
    );
\stateTo[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"080808A8"
    )
        port map (
      I0 => req,
      I1 => stateTo(0),
      I2 => stateTo(1),
      I3 => recvStrbToStop_reg_n_0,
      I4 => sendStrbToStop_reg_n_0,
      O => \stateTo[1]_i_2_n_0\
    );
\stateTo[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"007F059E001F41AA"
    )
        port map (
      I0 => Q(3),
      I1 => Q(0),
      I2 => Q(2),
      I3 => Q(5),
      I4 => Q(4),
      I5 => Q(1),
      O => req
    );
\stateTo[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEFEEEEFE"
    )
        port map (
      I0 => sendStrbToStop_reg_n_0,
      I1 => recvStrbToStop_reg_n_0,
      I2 => i(15),
      I3 => \i[15]_i_4_n_0\,
      I4 => i(14),
      I5 => \stateTo[1]_i_5_n_0\,
      O => \stateTo[1]_i_4_n_0\
    );
\stateTo[1]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFDFF7F"
    )
        port map (
      I0 => i(12),
      I1 => \i[12]_i_2_n_0\,
      I2 => i(9),
      I3 => \stateTo[1]_i_6_n_0\,
      I4 => i(10),
      O => \stateTo[1]_i_5_n_0\
    );
\stateTo[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFEF"
    )
        port map (
      I0 => \i[9]_i_2__3_n_0\,
      I1 => i(7),
      I2 => i(11),
      I3 => i(8),
      I4 => i(6),
      I5 => i(13),
      O => \stateTo[1]_i_6_n_0\
    );
\stateTo_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateTo[1]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \stateTo[0]_i_1_n_0\,
      Q => stateTo(0)
    );
\stateTo_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateTo[1]_i_1_n_0\,
      CLR => AXIL_rvalid_sig_reg_0(0),
      D => \stateTo[1]_i_2_n_0\,
      Q => stateTo(1)
    );
\tixVBuffer[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(0),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[0][7]\(0)
    );
\tixVBuffer[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(1),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[0][7]\(1)
    );
\tixVBuffer[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(2),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[0][7]\(2)
    );
\tixVBuffer[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(3),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[0][7]\(3)
    );
\tixVBuffer[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(4),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[0][7]\(4)
    );
\tixVBuffer[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(5),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[0][7]\(5)
    );
\tixVBuffer[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(6),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[0][7]\(6)
    );
\tixVBuffer[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(7),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[0][7]\(7)
    );
\tixVCommand[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(0),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[2][7]\(0)
    );
\tixVCommand[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(1),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[2][7]\(1)
    );
\tixVCommand[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(2),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[2][7]\(2)
    );
\tixVCommand[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(3),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[2][7]\(3)
    );
\tixVCommand[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(4),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[2][7]\(4)
    );
\tixVCommand[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(5),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[2][7]\(5)
    );
\tixVCommand[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(6),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[2][7]\(6)
    );
\tixVCommand[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(7),
      I1 => \^stateop_reg[4]\,
      O => \opbuf_reg[2][7]\(7)
    );
\tixVController[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_1\(0),
      I1 => \^stateop_reg[4]_3\,
      O => \opbuf_reg[1][7]\(0)
    );
\tixVController[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_1\(1),
      I1 => \^stateop_reg[4]_3\,
      O => \opbuf_reg[1][7]\(1)
    );
\tixVController[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_1\(2),
      I1 => \^stateop_reg[4]_3\,
      O => \opbuf_reg[1][7]\(2)
    );
\tixVController[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_1\(3),
      I1 => \^stateop_reg[4]_3\,
      O => \opbuf_reg[1][7]\(3)
    );
\tixVController[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_1\(4),
      I1 => \^stateop_reg[4]_3\,
      O => \opbuf_reg[1][7]\(4)
    );
\tixVController[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_1\(5),
      I1 => \^stateop_reg[4]_3\,
      O => \opbuf_reg[1][7]\(5)
    );
\tixVController[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_1\(6),
      I1 => \^stateop_reg[4]_3\,
      O => \opbuf_reg[1][7]\(6)
    );
\tixVController[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_1\(7),
      I1 => \^stateop_reg[4]_3\,
      O => \opbuf_reg[1][7]\(7)
    );
\txAXIS_tdata[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA8A"
    )
        port map (
      I0 => \^stateop_reg[4]_4\,
      I1 => \txAXIS_tdata_reg[0]\,
      I2 => \txAXIS_tdata_reg[0]_0\,
      I3 => \txAXIS_tdata_reg[0]_1\,
      O => \stateOp_reg[1]_9\(0)
    );
\txAXIS_tdata[15]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04005555FFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata_reg[8]\,
      I1 => \txAXIS_tdata_reg[8]_0\,
      I2 => Q(3),
      I3 => \txAXIS_tdata_reg[8]_1\,
      I4 => Q(2),
      I5 => \^stateop_reg[4]_4\,
      O => \stateOp_reg[3]\(0)
    );
\txAXIS_tdata[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4044404044444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[16]_1\,
      I3 => \txAXIS_tdata_reg[16]_2\,
      I4 => \txAXIS_tdata_reg[16]_3\,
      I5 => \txAXIS_tdata_reg[16]_4\,
      O => \stateOp_reg[1]_9\(6)
    );
\txAXIS_tdata[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4044404044444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[17]\,
      I3 => \txAXIS_tdata_reg[17]_0\,
      I4 => \txAXIS_tdata_reg[16]_3\,
      I5 => \txAXIS_tdata_reg[17]_1\,
      O => \stateOp_reg[1]_9\(7)
    );
\txAXIS_tdata[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4044404044444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[18]\,
      I3 => \txAXIS_tdata_reg[18]_0\,
      I4 => \txAXIS_tdata_reg[16]_3\,
      I5 => \txAXIS_tdata_reg[18]_1\,
      O => \stateOp_reg[1]_9\(8)
    );
\txAXIS_tdata[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8A8AAA8AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[19]\,
      I2 => \txAXIS_tdata_reg[19]_0\,
      I3 => \txAXIS_tdata_reg[23]\(0),
      I4 => \txAXIS_tdata_reg[19]_1\,
      I5 => \txAXIS_tdata_reg[19]_2\,
      O => \stateOp_reg[1]_9\(9)
    );
\txAXIS_tdata[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8A8AAA8AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[20]\,
      I2 => \txAXIS_tdata_reg[20]_0\,
      I3 => \txAXIS_tdata_reg[23]\(1),
      I4 => \txAXIS_tdata_reg[19]_1\,
      I5 => \txAXIS_tdata_reg[20]_1\,
      O => \stateOp_reg[1]_9\(10)
    );
\txAXIS_tdata[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4044404044444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[21]\,
      I3 => \txAXIS_tdata_reg[21]_0\,
      I4 => \txAXIS_tdata_reg[16]_3\,
      I5 => \txAXIS_tdata_reg[21]_1\,
      O => \stateOp_reg[1]_9\(11)
    );
\txAXIS_tdata[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4044404044444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[22]\,
      I3 => \txAXIS_tdata_reg[22]_0\,
      I4 => \txAXIS_tdata_reg[16]_3\,
      I5 => \txAXIS_tdata_reg[22]_1\,
      O => \stateOp_reg[1]_9\(12)
    );
\txAXIS_tdata[23]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04044404FFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata_reg[32]_1\,
      I1 => \txAXIS_tdata_reg[16]\,
      I2 => \txAXIS_tdata_reg[32]\,
      I3 => \txAXIS_tdata_reg[16]_0\,
      I4 => Q(2),
      I5 => \^stateop_reg[4]\,
      O => \stateOp_reg[3]\(1)
    );
\txAXIS_tdata[23]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8A8AAA8AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[23]_0\,
      I2 => \txAXIS_tdata_reg[23]_1\,
      I3 => \txAXIS_tdata_reg[23]\(2),
      I4 => \txAXIS_tdata_reg[19]_1\,
      I5 => \txAXIS_tdata_reg[23]_2\,
      O => \stateOp_reg[1]_9\(13)
    );
\txAXIS_tdata[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8A8AAA8AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[24]_0\,
      I2 => \txAXIS_tdata_reg[24]_1\,
      I3 => \txAXIS_tdata_reg[29]\(0),
      I4 => \txAXIS_tdata_reg[19]_1\,
      I5 => \txAXIS_tdata_reg[24]_2\,
      O => \stateOp_reg[1]_9\(14)
    );
\txAXIS_tdata[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8A8AAA8AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[25]\,
      I2 => \txAXIS_tdata_reg[25]_0\,
      I3 => \txAXIS_tdata_reg[29]\(1),
      I4 => \txAXIS_tdata_reg[19]_1\,
      I5 => \txAXIS_tdata_reg[25]_1\,
      O => \stateOp_reg[1]_9\(15)
    );
\txAXIS_tdata[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA88A8AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[26]\,
      I2 => \txAXIS_tdata_reg[29]\(2),
      I3 => \txAXIS_tdata_reg[19]_1\,
      I4 => \txAXIS_tdata_reg[26]_0\,
      I5 => \txAXIS_tdata_reg[26]_1\,
      O => \stateOp_reg[1]_9\(16)
    );
\txAXIS_tdata[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8A8AAA8AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[27]\,
      I2 => \txAXIS_tdata_reg[27]_0\,
      I3 => \txAXIS_tdata_reg[29]\(3),
      I4 => \txAXIS_tdata_reg[19]_1\,
      I5 => \txAXIS_tdata_reg[27]_1\,
      O => \stateOp_reg[1]_9\(17)
    );
\txAXIS_tdata[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA88A8AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[28]\,
      I2 => \txAXIS_tdata_reg[29]\(4),
      I3 => \txAXIS_tdata_reg[19]_1\,
      I4 => \txAXIS_tdata_reg[28]_0\,
      I5 => \txAXIS_tdata_reg[28]_1\,
      O => \stateOp_reg[1]_9\(18)
    );
\txAXIS_tdata[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA88A8AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[29]_0\,
      I2 => \txAXIS_tdata_reg[29]\(5),
      I3 => \txAXIS_tdata_reg[19]_1\,
      I4 => \txAXIS_tdata_reg[29]_1\,
      I5 => \txAXIS_tdata_reg[29]_2\,
      O => \stateOp_reg[1]_9\(19)
    );
\txAXIS_tdata[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA8AAAA"
    )
        port map (
      I0 => \^stateop_reg[4]_4\,
      I1 => \txAXIS_tdata_reg[2]\,
      I2 => \txAXIS_tdata_reg[2]_0\,
      I3 => \txAXIS_tdata_reg[2]_1\,
      I4 => \txAXIS_tdata_reg[0]_0\,
      I5 => \txAXIS_tdata_reg[0]_1\,
      O => \stateOp_reg[1]_9\(1)
    );
\txAXIS_tdata[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888A88AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[30]\,
      I2 => \txAXIS_tdata_reg[30]_0\,
      I3 => Q(1),
      I4 => Q(2),
      I5 => \txAXIS_tdata_reg[30]_1\,
      O => \stateOp_reg[1]_9\(20)
    );
\txAXIS_tdata[31]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D0FF"
    )
        port map (
      I0 => \txAXIS_tdata_reg[24]\,
      I1 => \txAXIS_tdata_reg[56]\,
      I2 => \txAXIS_tdata_reg[56]_1\,
      I3 => \^stateop_reg[4]_4\,
      O => \stateOp_reg[3]\(2)
    );
\txAXIS_tdata[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888A88AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[31]\,
      I2 => \txAXIS_tdata_reg[31]_0\,
      I3 => Q(1),
      I4 => Q(2),
      I5 => \txAXIS_tdata_reg[31]_1\,
      O => \stateOp_reg[1]_9\(21)
    );
\txAXIS_tdata[32]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00044404"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[32]_2\,
      I3 => Q(1),
      I4 => \txAXIS_tdata_reg[32]_3\,
      O => \stateOp_reg[1]_9\(22)
    );
\txAXIS_tdata[33]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00044404"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[33]\,
      I3 => Q(1),
      I4 => \txAXIS_tdata_reg[33]_0\,
      O => \stateOp_reg[1]_9\(23)
    );
\txAXIS_tdata[34]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00044404"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[34]\,
      I3 => Q(1),
      I4 => \txAXIS_tdata_reg[34]_0\,
      O => \stateOp_reg[1]_9\(24)
    );
\txAXIS_tdata[35]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00044404"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[35]\,
      I3 => Q(1),
      I4 => \txAXIS_tdata_reg[35]_0\,
      O => \stateOp_reg[1]_9\(25)
    );
\txAXIS_tdata[36]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00044404"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[36]\,
      I3 => Q(1),
      I4 => \txAXIS_tdata_reg[36]_0\,
      O => \stateOp_reg[1]_9\(26)
    );
\txAXIS_tdata[37]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00044404"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[37]\,
      I3 => Q(1),
      I4 => \txAXIS_tdata_reg[37]_0\,
      O => \stateOp_reg[1]_9\(27)
    );
\txAXIS_tdata[38]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00044404"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[38]\,
      I3 => Q(1),
      I4 => \txAXIS_tdata_reg[38]_0\,
      O => \stateOp_reg[1]_9\(28)
    );
\txAXIS_tdata[39]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00005575FFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata_reg[32]\,
      I1 => \txAXIS_tdata_reg[32]_0\(1),
      I2 => \txAXIS_tdata_reg[32]_0\(2),
      I3 => Q(2),
      I4 => \txAXIS_tdata_reg[32]_1\,
      I5 => \^stateop_reg[4]\,
      O => \stateOp_reg[3]\(3)
    );
\txAXIS_tdata[39]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00044404"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[39]\,
      I3 => Q(1),
      I4 => \txAXIS_tdata_reg[39]_0\,
      O => \stateOp_reg[1]_9\(29)
    );
\txAXIS_tdata[47]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \txAXIS_tdata_reg[40]\,
      I1 => \^stateop_reg[4]_4\,
      O => \stateOp_reg[3]\(4)
    );
\txAXIS_tdata[48]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440444444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[48]_2\,
      I3 => \txAXIS_tdata_reg[48]_3\,
      I4 => \txAXIS_tdata_reg[48]_4\,
      I5 => \txAXIS_tdata_reg[48]_5\,
      O => \stateOp_reg[1]_9\(30)
    );
\txAXIS_tdata[49]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440444444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[48]_2\,
      I3 => \txAXIS_tdata_reg[49]\,
      I4 => \txAXIS_tdata_reg[49]_0\,
      I5 => \txAXIS_tdata_reg[49]_1\,
      O => \stateOp_reg[1]_9\(31)
    );
\txAXIS_tdata[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA8AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[4]_1\,
      I1 => \txAXIS_tdata_reg[4]\,
      I2 => \txAXIS_tdata_reg[4]_0\,
      I3 => \txAXIS_tdata_reg[4]_1\,
      I4 => \txAXIS_tdata_reg[4]_2\,
      I5 => \txAXIS_tdata_reg[0]_0\,
      O => \stateOp_reg[1]_9\(2)
    );
\txAXIS_tdata[50]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440444444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[48]_2\,
      I3 => \txAXIS_tdata_reg[50]\,
      I4 => \txAXIS_tdata_reg[50]_0\,
      I5 => \txAXIS_tdata_reg[50]_1\,
      O => \stateOp_reg[1]_9\(32)
    );
\txAXIS_tdata[51]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440444444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[48]_2\,
      I3 => \txAXIS_tdata_reg[51]\,
      I4 => \txAXIS_tdata_reg[51]_0\,
      I5 => \txAXIS_tdata_reg[51]_1\,
      O => \stateOp_reg[1]_9\(33)
    );
\txAXIS_tdata[52]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440444444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[48]_2\,
      I3 => \txAXIS_tdata_reg[52]\,
      I4 => \txAXIS_tdata_reg[52]_0\,
      I5 => \txAXIS_tdata_reg[52]_1\,
      O => \stateOp_reg[1]_9\(34)
    );
\txAXIS_tdata[53]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440444444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[48]_2\,
      I3 => \txAXIS_tdata_reg[53]\,
      I4 => \txAXIS_tdata_reg[53]_0\,
      I5 => \txAXIS_tdata_reg[53]_1\,
      O => \stateOp_reg[1]_9\(35)
    );
\txAXIS_tdata[54]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440444444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[48]_2\,
      I3 => \txAXIS_tdata_reg[54]\,
      I4 => \txAXIS_tdata_reg[54]_0\,
      I5 => \txAXIS_tdata_reg[54]_1\,
      O => \stateOp_reg[1]_9\(36)
    );
\txAXIS_tdata[55]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFA20000FFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata_reg[48]\,
      I1 => \txAXIS_tdata_reg[48]_0\,
      I2 => \txAXIS_tdata_reg[48]_1\,
      I3 => \txAXIS_tdata_reg[56]\,
      I4 => \txAXIS_tdata_reg[56]_1\,
      I5 => \^stateop_reg[4]\,
      O => \stateOp_reg[3]\(5)
    );
\txAXIS_tdata[55]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000440444444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => \txAXIS_tdata_reg[48]_2\,
      I3 => \txAXIS_tdata_reg[55]\,
      I4 => \txAXIS_tdata_reg[55]_0\,
      I5 => \txAXIS_tdata_reg[55]_1\,
      O => \stateOp_reg[1]_9\(37)
    );
\txAXIS_tdata[56]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0020AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[56]_2\,
      I2 => Q(1),
      I3 => Q(2),
      I4 => \txAXIS_tdata_reg[56]_3\,
      I5 => \txAXIS_tdata_reg[56]_4\,
      O => \stateOp_reg[1]_9\(38)
    );
\txAXIS_tdata[57]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0020AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[57]\,
      I2 => Q(1),
      I3 => Q(2),
      I4 => \txAXIS_tdata_reg[57]_0\,
      I5 => \txAXIS_tdata_reg[57]_1\,
      O => \stateOp_reg[1]_9\(39)
    );
\txAXIS_tdata[58]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000040044444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => Q(1),
      I3 => Q(4),
      I4 => \txAXIS_tdata_reg[58]\,
      I5 => \txAXIS_tdata_reg[58]_0\,
      O => \stateOp_reg[1]_9\(40)
    );
\txAXIS_tdata[59]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000040044444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => Q(1),
      I3 => Q(4),
      I4 => \txAXIS_tdata_reg[59]\,
      I5 => \txAXIS_tdata_reg[59]_0\,
      O => \stateOp_reg[1]_9\(41)
    );
\txAXIS_tdata[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20AA2020AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[5]\,
      I2 => \txAXIS_tdata_reg[5]_0\,
      I3 => \txAXIS_tdata_reg[5]_1\,
      I4 => \txAXIS_tdata_reg[5]_2\,
      I5 => \txAXIS_tdata_reg[5]_3\,
      O => \stateOp_reg[1]_9\(3)
    );
\txAXIS_tdata[60]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0020AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[60]\,
      I2 => Q(1),
      I3 => Q(2),
      I4 => \txAXIS_tdata_reg[60]_0\,
      I5 => \txAXIS_tdata_reg[60]_1\,
      O => \stateOp_reg[1]_9\(42)
    );
\txAXIS_tdata[61]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0020AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[61]\,
      I2 => Q(1),
      I3 => Q(2),
      I4 => \txAXIS_tdata_reg[61]_0\,
      I5 => \txAXIS_tdata_reg[61]_1\,
      O => \stateOp_reg[1]_9\(43)
    );
\txAXIS_tdata[62]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000040044444444"
    )
        port map (
      I0 => Q(5),
      I1 => \^stateop_reg[4]\,
      I2 => Q(1),
      I3 => Q(4),
      I4 => \txAXIS_tdata_reg[62]\,
      I5 => \txAXIS_tdata_reg[62]_0\,
      O => \stateOp_reg[1]_9\(44)
    );
\txAXIS_tdata[63]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FE00FFFF"
    )
        port map (
      I0 => \txAXIS_tdata_reg[56]\,
      I1 => \txAXIS_tdata_reg[56]_0\,
      I2 => Q(3),
      I3 => \txAXIS_tdata_reg[56]_1\,
      I4 => \^stateop_reg[4]\,
      O => \stateOp_reg[3]\(6)
    );
\txAXIS_tdata[63]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0020AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[63]\,
      I2 => Q(1),
      I3 => Q(2),
      I4 => \txAXIS_tdata_reg[63]_0\,
      I5 => \txAXIS_tdata_reg[63]_1\,
      O => \stateOp_reg[1]_9\(45)
    );
\txAXIS_tdata[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA8AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[4]_4\,
      I1 => \txAXIS_tdata_reg[6]\,
      I2 => \txAXIS_tdata_reg[4]_0\,
      I3 => \txAXIS_tdata_reg[6]_0\,
      I4 => \txAXIS_tdata_reg[6]_1\,
      I5 => \txAXIS_tdata_reg[0]_0\,
      O => \stateOp_reg[1]_9\(4)
    );
\txAXIS_tdata[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0002AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_6\,
      I1 => \txAXIS_tdata_reg[7]_0\,
      I2 => Q(0),
      I3 => Q(2),
      I4 => \txAXIS_tdata_reg[7]_1\,
      I5 => \txAXIS_tdata_reg[5]_3\,
      O => \stateOp_reg[1]_9\(5)
    );
\txlen[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08A00800"
    )
        port map (
      I0 => \wordcntLast[2]_i_3_n_0\,
      I1 => \txlen_reg[0]\,
      I2 => Q(4),
      I3 => Q(3),
      I4 => plusOp(0),
      O => \stateOp_reg[4]_14\(0)
    );
validCrc_sig_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0010FFFF"
    )
        port map (
      I0 => stateOp_reg,
      I1 => stateRecv(0),
      I2 => stateRecv(2),
      I3 => stateRecv(1),
      I4 => \crc_imd_reg[4]\,
      O => AXIS_tvalid
    );
validCrc_sig_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAABAAAAAAAAA"
    )
        port map (
      I0 => crcAXIS_tlast_sig_reg_3,
      I1 => stateRecv(1),
      I2 => stateRecv(2),
      I3 => stateRecv(0),
      I4 => stateOp_reg,
      I5 => \^recvaxis_tlast\,
      O => AXIS_tlast
    );
\wdone_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"777F777F777F0000"
    )
        port map (
      I0 => \^axil_bvalid_sig_reg_0\,
      I1 => apuAXIL_bready,
      I2 => \^axil_awready_sig_reg_0\,
      I3 => awdone_reg_n_0,
      I4 => \^axil_wready_sig_reg_0\,
      I5 => wdone_reg_n_0,
      O => \wdone_i_1__0_n_0\
    );
wdone_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \wdone_i_1__0_n_0\,
      Q => wdone_reg_n_0,
      R => AXIL_rvalid_sig_reg_0(0)
    );
\wordcntCrcLast[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0C44"
    )
        port map (
      I0 => plusOp(0),
      I1 => \^stateop_reg[4]_3\,
      I2 => \wordcntCrcLast_reg[0]\,
      I3 => \lastAXIS_tkeep_reg[1]\,
      O => \stateOp_reg[4]_13\(0)
    );
\wordcntCrcLast[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[16]\(1),
      O => \stateOp_reg[4]_13\(10)
    );
\wordcntCrcLast[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[16]\(2),
      O => \stateOp_reg[4]_13\(11)
    );
\wordcntCrcLast[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[16]\(3),
      O => \stateOp_reg[4]_13\(12)
    );
\wordcntCrcLast[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[16]\(4),
      O => \stateOp_reg[4]_13\(13)
    );
\wordcntCrcLast[14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[16]\(5),
      O => \stateOp_reg[4]_13\(14)
    );
\wordcntCrcLast[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[16]\(6),
      O => \stateOp_reg[4]_13\(15)
    );
\wordcntCrcLast[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[16]\(7),
      O => \stateOp_reg[4]_13\(16)
    );
\wordcntCrcLast[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[24]_0\(0),
      O => \stateOp_reg[4]_13\(17)
    );
\wordcntCrcLast[18]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[24]_0\(1),
      O => \stateOp_reg[4]_13\(18)
    );
\wordcntCrcLast[19]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[24]_0\(2),
      O => \stateOp_reg[4]_13\(19)
    );
\wordcntCrcLast[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => O(0),
      O => \stateOp_reg[4]_13\(1)
    );
\wordcntCrcLast[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[24]_0\(3),
      O => \stateOp_reg[4]_13\(20)
    );
\wordcntCrcLast[21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[24]_0\(4),
      O => \stateOp_reg[4]_13\(21)
    );
\wordcntCrcLast[22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[24]_0\(5),
      O => \stateOp_reg[4]_13\(22)
    );
\wordcntCrcLast[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[24]_0\(6),
      O => \stateOp_reg[4]_13\(23)
    );
\wordcntCrcLast[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1410FFFF"
    )
        port map (
      I0 => \wordcntCrcLast_reg[24]\,
      I1 => Q(4),
      I2 => Q(3),
      I3 => \wordcntLast_reg[28]\,
      I4 => \^stateop_reg[4]_3\,
      O => \stateOp_reg[4]_2\(0)
    );
\wordcntCrcLast[24]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[24]_0\(7),
      O => \stateOp_reg[4]_13\(24)
    );
\wordcntCrcLast[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA88A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => O(1),
      I4 => \wordcntCrcLast_reg[2]\,
      O => \stateOp_reg[4]_13\(2)
    );
\wordcntCrcLast[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => O(2),
      O => \stateOp_reg[4]_13\(3)
    );
\wordcntCrcLast[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => O(3),
      O => \stateOp_reg[4]_13\(4)
    );
\wordcntCrcLast[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => O(4),
      O => \stateOp_reg[4]_13\(5)
    );
\wordcntCrcLast[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => O(5),
      O => \stateOp_reg[4]_13\(6)
    );
\wordcntCrcLast[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => O(6),
      O => \stateOp_reg[4]_13\(7)
    );
\wordcntCrcLast[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => O(7),
      O => \stateOp_reg[4]_13\(8)
    );
\wordcntCrcLast[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[4]_3\,
      I1 => \wordcntCrcLast_reg[1]\,
      I2 => \lastAXIS_tkeep_reg[1]\,
      I3 => \wordcntCrcLast_reg[16]\(0),
      O => \stateOp_reg[4]_13\(9)
    );
\wordcntLast[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00470000004700"
    )
        port map (
      I0 => \wordcntLast_reg[0]\,
      I1 => \wordcntLast_reg[0]_0\,
      I2 => \wordcntLast_reg[0]_1\,
      I3 => \^stateop_reg[4]_0\,
      I4 => Q(5),
      I5 => \wordcntLast_reg[0]_2\,
      O => \stateOp_reg[4]_7\(0)
    );
\wordcntLast[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(10),
      O => \stateOp_reg[4]_7\(10)
    );
\wordcntLast[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(11),
      O => \stateOp_reg[4]_7\(11)
    );
\wordcntLast[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(12),
      O => \stateOp_reg[4]_7\(12)
    );
\wordcntLast[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(13),
      O => \stateOp_reg[4]_7\(13)
    );
\wordcntLast[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(14),
      O => \stateOp_reg[4]_7\(14)
    );
\wordcntLast[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(15),
      O => \stateOp_reg[4]_7\(15)
    );
\wordcntLast[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(16),
      O => \stateOp_reg[4]_7\(16)
    );
\wordcntLast[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(17),
      O => \stateOp_reg[4]_7\(17)
    );
\wordcntLast[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(18),
      O => \stateOp_reg[4]_7\(18)
    );
\wordcntLast[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(19),
      O => \stateOp_reg[4]_7\(19)
    );
\wordcntLast[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08A00800"
    )
        port map (
      I0 => \wordcntLast[2]_i_3_n_0\,
      I1 => \retbuf_reg[7][7]_0\,
      I2 => Q(4),
      I3 => Q(3),
      I4 => plusOp(1),
      O => \stateOp_reg[4]_7\(1)
    );
\wordcntLast[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(20),
      O => \stateOp_reg[4]_7\(20)
    );
\wordcntLast[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(21),
      O => \stateOp_reg[4]_7\(21)
    );
\wordcntLast[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(22),
      O => \stateOp_reg[4]_7\(22)
    );
\wordcntLast[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(23),
      O => \stateOp_reg[4]_7\(23)
    );
\wordcntLast[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(24),
      O => \stateOp_reg[4]_7\(24)
    );
\wordcntLast[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(25),
      O => \stateOp_reg[4]_7\(25)
    );
\wordcntLast[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(26),
      O => \stateOp_reg[4]_7\(26)
    );
\wordcntLast[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(27),
      O => \stateOp_reg[4]_7\(27)
    );
\wordcntLast[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0075FFFF"
    )
        port map (
      I0 => \wordcntLast_reg[28]_0\,
      I1 => \wordcntLast_reg[28]_1\,
      I2 => \wordcntLast_reg[28]\,
      I3 => Q(5),
      I4 => \^stateop_reg[4]_0\,
      O => \stateOp_reg[5]_2\(0)
    );
\wordcntLast[28]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(28),
      O => \stateOp_reg[4]_7\(28)
    );
\wordcntLast[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2C200000"
    )
        port map (
      I0 => \wordcntCrcLast_reg[2]\,
      I1 => Q(4),
      I2 => Q(3),
      I3 => plusOp(2),
      I4 => \wordcntLast[2]_i_3_n_0\,
      O => \stateOp_reg[4]_7\(2)
    );
\wordcntLast[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000000000800"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => Q(2),
      I2 => Q(5),
      I3 => Q(0),
      I4 => Q(1),
      I5 => Q(3),
      O => \wordcntLast[2]_i_3_n_0\
    );
\wordcntLast[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(3),
      O => \stateOp_reg[4]_7\(3)
    );
\wordcntLast[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(4),
      O => \stateOp_reg[4]_7\(4)
    );
\wordcntLast[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(5),
      O => \stateOp_reg[4]_7\(5)
    );
\wordcntLast[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(6),
      O => \stateOp_reg[4]_7\(6)
    );
\wordcntLast[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(7),
      O => \stateOp_reg[4]_7\(7)
    );
\wordcntLast[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(8),
      O => \stateOp_reg[4]_7\(8)
    );
\wordcntLast[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg[4]_0\,
      I1 => \wordcntLast_reg[3]\,
      I2 => plusOp(9),
      O => \stateOp_reg[4]_7\(9)
    );
\wordcnt[0]__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000004000000"
    )
        port map (
      I0 => stateRecv(0),
      I1 => stateRecv(1),
      I2 => stateRecv(2),
      I3 => \recvAXIL_rdata[63]_i_2_n_0\,
      I4 => p_1_in0,
      I5 => AXIL_rvalid_sig_reg_0(0),
      O => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt[0]__0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000001000000"
    )
        port map (
      I0 => \^recvaxis_tlast\,
      I1 => stateRecv(1),
      I2 => stateRecv(0),
      I3 => \wordcnt[0]__0_i_4_n_0\,
      I4 => p_1_in0,
      I5 => AXIL_rvalid_sig_reg_0(0),
      O => wordcnt0
    );
\wordcnt[0]__0_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_33_in,
      I1 => stateRecv(2),
      O => \wordcnt[0]__0_i_4_n_0\
    );
\wordcnt[0]__0_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wordcnt_reg[0]__0_n_0\,
      O => \wordcnt[0]__0_i_5_n_0\
    );
\wordcnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008000000"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => \wordcnt[0]_i_4_n_0\,
      I2 => AXIL_rvalid_sig_reg_0(0),
      I3 => AXIL_araddr_sig(5),
      I4 => strbRead,
      I5 => AXIL_araddr_sig(4),
      O => \wordcnt[0]_i_1_n_0\
    );
\wordcnt[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => \wordcnt_reg[0]_0\(0),
      O => \stateOp_reg[4]_6\(0)
    );
\wordcnt[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => \sendAXIL_rdata[63]_i_5_n_0\,
      I1 => AXIL_rvalid_sig_reg_0(0),
      I2 => \stateSend[2]_i_6_n_0\,
      I3 => stateSend(0),
      I4 => sendStrbToStart0,
      I5 => \stateSend[2]_i_3_n_0\,
      O => \wordcnt[0]_i_2_n_0\
    );
\wordcnt[0]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      I2 => stateSend(0),
      O => \wordcnt[0]_i_4_n_0\
    );
\wordcnt[0]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => apuAXIL_arvalid,
      I1 => \^axil_arready\,
      O => strbRead
    );
\wordcnt[0]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcnt_reg(0),
      O => \wordcnt[0]_i_6_n_0\
    );
\wordcnt[10]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(9),
      O => \stateOp_reg[4]_6\(10)
    );
\wordcnt[11]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(10),
      O => \stateOp_reg[4]_6\(11)
    );
\wordcnt[12]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(11),
      O => \stateOp_reg[4]_6\(12)
    );
\wordcnt[13]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(12),
      O => \stateOp_reg[4]_6\(13)
    );
\wordcnt[14]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(13),
      O => \stateOp_reg[4]_6\(14)
    );
\wordcnt[15]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(14),
      O => \stateOp_reg[4]_6\(15)
    );
\wordcnt[16]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(15),
      O => \stateOp_reg[4]_6\(16)
    );
\wordcnt[17]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(16),
      O => \stateOp_reg[4]_6\(17)
    );
\wordcnt[18]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(17),
      O => \stateOp_reg[4]_6\(18)
    );
\wordcnt[19]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(18),
      O => \stateOp_reg[4]_6\(19)
    );
\wordcnt[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(0),
      O => \stateOp_reg[4]_6\(1)
    );
\wordcnt[20]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(19),
      O => \stateOp_reg[4]_6\(20)
    );
\wordcnt[21]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(20),
      O => \stateOp_reg[4]_6\(21)
    );
\wordcnt[22]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(21),
      O => \stateOp_reg[4]_6\(22)
    );
\wordcnt[23]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(22),
      O => \stateOp_reg[4]_6\(23)
    );
\wordcnt[24]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(23),
      O => \stateOp_reg[4]_6\(24)
    );
\wordcnt[25]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(24),
      O => \stateOp_reg[4]_6\(25)
    );
\wordcnt[26]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(25),
      O => \stateOp_reg[4]_6\(26)
    );
\wordcnt[27]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(26),
      O => \stateOp_reg[4]_6\(27)
    );
\wordcnt[28]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(27),
      O => \stateOp_reg[4]_6\(28)
    );
\wordcnt[29]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(28),
      O => \stateOp_reg[4]_6\(29)
    );
\wordcnt[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(1),
      O => \stateOp_reg[4]_6\(2)
    );
\wordcnt[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0055F033FFFFFFFF"
    )
        port map (
      I0 => \wordcnt[30]_i_3_n_0\,
      I1 => \wordcnt[30]_i_4__0_n_0\,
      I2 => \wordcnt[30]_i_5_n_0\,
      I3 => \wordcnt_reg[0]_1\,
      I4 => \wordcnt_reg[0]_2\,
      I5 => \^stateop_reg[4]_3\,
      O => \stateSend_reg[2]_0\(0)
    );
\wordcnt[30]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(29),
      O => \stateOp_reg[4]_6\(30)
    );
\wordcnt[30]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFFFFFF55555555"
    )
        port map (
      I0 => \wordcntLast_reg[28]\,
      I1 => crcAXIS_tlast_sig_reg_0(0),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      I5 => \wordcnt_reg[0]_3\,
      O => \wordcnt[30]_i_3_n_0\
    );
\wordcnt[30]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF4FF"
    )
        port map (
      I0 => CO(0),
      I1 => crcAXIS_tlast_sig_reg_0(0),
      I2 => stateRecv(1),
      I3 => stateRecv(2),
      I4 => stateRecv(0),
      O => \wordcnt[30]_i_4__0_n_0\
    );
\wordcnt[30]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAABAA"
    )
        port map (
      I0 => \wordcnt_reg[0]_3\,
      I1 => crcAXIS_tlast_sig_reg_0(0),
      I2 => stateRecv(0),
      I3 => stateRecv(2),
      I4 => stateRecv(1),
      O => \wordcnt[30]_i_5_n_0\
    );
\wordcnt[30]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAA8A"
    )
        port map (
      I0 => \stateOp[0]_i_2_n_0\,
      I1 => Q(4),
      I2 => commok_sig_reg_1,
      I3 => Q(2),
      I4 => Q(5),
      I5 => Q(0),
      O => \^stateop_reg[4]_3\
    );
\wordcnt[3]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(2),
      O => \stateOp_reg[4]_6\(3)
    );
\wordcnt[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(3),
      O => \stateOp_reg[4]_6\(4)
    );
\wordcnt[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(4),
      O => \stateOp_reg[4]_6\(5)
    );
\wordcnt[6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(5),
      O => \stateOp_reg[4]_6\(6)
    );
\wordcnt[7]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(6),
      O => \stateOp_reg[4]_6\(7)
    );
\wordcnt[8]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(7),
      O => \stateOp_reg[4]_6\(8)
    );
\wordcnt[9]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \wordcnt_reg[1]_0\,
      I1 => \^stateop_reg[4]_3\,
      I2 => txlast1(8),
      O => \stateOp_reg[4]_6\(9)
    );
\wordcnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[0]_i_3_n_15\,
      Q => wordcnt_reg(0),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[0]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3_n_15\,
      Q => \wordcnt_reg[0]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[0]__0_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[0]__0_i_3_n_0\,
      CO(6) => \wordcnt_reg[0]__0_i_3_n_1\,
      CO(5) => \wordcnt_reg[0]__0_i_3_n_2\,
      CO(4) => \wordcnt_reg[0]__0_i_3_n_3\,
      CO(3) => \wordcnt_reg[0]__0_i_3_n_4\,
      CO(2) => \wordcnt_reg[0]__0_i_3_n_5\,
      CO(1) => \wordcnt_reg[0]__0_i_3_n_6\,
      CO(0) => \wordcnt_reg[0]__0_i_3_n_7\,
      DI(7 downto 0) => B"00000001",
      O(7) => \wordcnt_reg[0]__0_i_3_n_8\,
      O(6) => \wordcnt_reg[0]__0_i_3_n_9\,
      O(5) => \wordcnt_reg[0]__0_i_3_n_10\,
      O(4) => \wordcnt_reg[0]__0_i_3_n_11\,
      O(3) => \wordcnt_reg[0]__0_i_3_n_12\,
      O(2) => \wordcnt_reg[0]__0_i_3_n_13\,
      O(1) => \wordcnt_reg[0]__0_i_3_n_14\,
      O(0) => \wordcnt_reg[0]__0_i_3_n_15\,
      S(7) => \wordcnt_reg[7]__0_n_0\,
      S(6) => \wordcnt_reg[6]__0_n_0\,
      S(5) => \wordcnt_reg[5]__0_n_0\,
      S(4) => \wordcnt_reg[4]__0_n_0\,
      S(3) => \wordcnt_reg[3]__0_n_0\,
      S(2) => \wordcnt_reg[2]__0_n_0\,
      S(1) => \wordcnt_reg[1]__0_n_0\,
      S(0) => \wordcnt[0]__0_i_5_n_0\
    );
\wordcnt_reg[0]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[0]_i_3_n_0\,
      CO(6) => \wordcnt_reg[0]_i_3_n_1\,
      CO(5) => \wordcnt_reg[0]_i_3_n_2\,
      CO(4) => \wordcnt_reg[0]_i_3_n_3\,
      CO(3) => \wordcnt_reg[0]_i_3_n_4\,
      CO(2) => \wordcnt_reg[0]_i_3_n_5\,
      CO(1) => \wordcnt_reg[0]_i_3_n_6\,
      CO(0) => \wordcnt_reg[0]_i_3_n_7\,
      DI(7 downto 0) => B"00000001",
      O(7) => \wordcnt_reg[0]_i_3_n_8\,
      O(6) => \wordcnt_reg[0]_i_3_n_9\,
      O(5) => \wordcnt_reg[0]_i_3_n_10\,
      O(4) => \wordcnt_reg[0]_i_3_n_11\,
      O(3) => \wordcnt_reg[0]_i_3_n_12\,
      O(2) => \wordcnt_reg[0]_i_3_n_13\,
      O(1) => \wordcnt_reg[0]_i_3_n_14\,
      O(0) => \wordcnt_reg[0]_i_3_n_15\,
      S(7 downto 1) => wordcnt_reg(7 downto 1),
      S(0) => \wordcnt[0]_i_6_n_0\
    );
\wordcnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[8]_i_1_n_13\,
      Q => wordcnt_reg(10),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[10]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1_n_13\,
      Q => \wordcnt_reg[10]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[8]_i_1_n_12\,
      Q => wordcnt_reg(11),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[11]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1_n_12\,
      Q => \wordcnt_reg[11]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[8]_i_1_n_11\,
      Q => wordcnt_reg(12),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[12]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1_n_11\,
      Q => \wordcnt_reg[12]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[8]_i_1_n_10\,
      Q => wordcnt_reg(13),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[13]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1_n_10\,
      Q => \wordcnt_reg[13]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[8]_i_1_n_9\,
      Q => wordcnt_reg(14),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[14]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1_n_9\,
      Q => \wordcnt_reg[14]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[8]_i_1_n_8\,
      Q => wordcnt_reg(15),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[15]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1_n_8\,
      Q => \wordcnt_reg[15]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[16]_i_1_n_15\,
      Q => wordcnt_reg(16),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[16]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1_n_15\,
      Q => \wordcnt_reg[16]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[16]__0_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[8]__0_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[16]__0_i_1_n_0\,
      CO(6) => \wordcnt_reg[16]__0_i_1_n_1\,
      CO(5) => \wordcnt_reg[16]__0_i_1_n_2\,
      CO(4) => \wordcnt_reg[16]__0_i_1_n_3\,
      CO(3) => \wordcnt_reg[16]__0_i_1_n_4\,
      CO(2) => \wordcnt_reg[16]__0_i_1_n_5\,
      CO(1) => \wordcnt_reg[16]__0_i_1_n_6\,
      CO(0) => \wordcnt_reg[16]__0_i_1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \wordcnt_reg[16]__0_i_1_n_8\,
      O(6) => \wordcnt_reg[16]__0_i_1_n_9\,
      O(5) => \wordcnt_reg[16]__0_i_1_n_10\,
      O(4) => \wordcnt_reg[16]__0_i_1_n_11\,
      O(3) => \wordcnt_reg[16]__0_i_1_n_12\,
      O(2) => \wordcnt_reg[16]__0_i_1_n_13\,
      O(1) => \wordcnt_reg[16]__0_i_1_n_14\,
      O(0) => \wordcnt_reg[16]__0_i_1_n_15\,
      S(7) => \wordcnt_reg[23]__0_n_0\,
      S(6) => \wordcnt_reg[22]__0_n_0\,
      S(5) => \wordcnt_reg[21]__0_n_0\,
      S(4) => \wordcnt_reg[20]__0_n_0\,
      S(3) => \wordcnt_reg[19]__0_n_0\,
      S(2) => \wordcnt_reg[18]__0_n_0\,
      S(1) => \wordcnt_reg[17]__0_n_0\,
      S(0) => \wordcnt_reg[16]__0_n_0\
    );
\wordcnt_reg[16]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[8]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[16]_i_1_n_0\,
      CO(6) => \wordcnt_reg[16]_i_1_n_1\,
      CO(5) => \wordcnt_reg[16]_i_1_n_2\,
      CO(4) => \wordcnt_reg[16]_i_1_n_3\,
      CO(3) => \wordcnt_reg[16]_i_1_n_4\,
      CO(2) => \wordcnt_reg[16]_i_1_n_5\,
      CO(1) => \wordcnt_reg[16]_i_1_n_6\,
      CO(0) => \wordcnt_reg[16]_i_1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \wordcnt_reg[16]_i_1_n_8\,
      O(6) => \wordcnt_reg[16]_i_1_n_9\,
      O(5) => \wordcnt_reg[16]_i_1_n_10\,
      O(4) => \wordcnt_reg[16]_i_1_n_11\,
      O(3) => \wordcnt_reg[16]_i_1_n_12\,
      O(2) => \wordcnt_reg[16]_i_1_n_13\,
      O(1) => \wordcnt_reg[16]_i_1_n_14\,
      O(0) => \wordcnt_reg[16]_i_1_n_15\,
      S(7 downto 0) => wordcnt_reg(23 downto 16)
    );
\wordcnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[16]_i_1_n_14\,
      Q => wordcnt_reg(17),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[17]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1_n_14\,
      Q => \wordcnt_reg[17]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[16]_i_1_n_13\,
      Q => wordcnt_reg(18),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[18]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1_n_13\,
      Q => \wordcnt_reg[18]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[16]_i_1_n_12\,
      Q => wordcnt_reg(19),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[19]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1_n_12\,
      Q => \wordcnt_reg[19]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[0]_i_3_n_14\,
      Q => wordcnt_reg(1),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[1]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3_n_14\,
      Q => \wordcnt_reg[1]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[16]_i_1_n_11\,
      Q => wordcnt_reg(20),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[20]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1_n_11\,
      Q => \wordcnt_reg[20]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[16]_i_1_n_10\,
      Q => wordcnt_reg(21),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[21]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1_n_10\,
      Q => \wordcnt_reg[21]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[16]_i_1_n_9\,
      Q => wordcnt_reg(22),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[22]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1_n_9\,
      Q => \wordcnt_reg[22]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[16]_i_1_n_8\,
      Q => wordcnt_reg(23),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[23]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1_n_8\,
      Q => \wordcnt_reg[23]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[24]_i_1_n_15\,
      Q => wordcnt_reg(24),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[24]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[24]__0_i_1_n_15\,
      Q => \wordcnt_reg[24]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[24]__0_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[16]__0_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_wordcnt_reg[24]__0_i_1_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \wordcnt_reg[24]__0_i_1_n_2\,
      CO(4) => \wordcnt_reg[24]__0_i_1_n_3\,
      CO(3) => \wordcnt_reg[24]__0_i_1_n_4\,
      CO(2) => \wordcnt_reg[24]__0_i_1_n_5\,
      CO(1) => \wordcnt_reg[24]__0_i_1_n_6\,
      CO(0) => \wordcnt_reg[24]__0_i_1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NLW_wordcnt_reg[24]__0_i_1_O_UNCONNECTED\(7),
      O(6) => \wordcnt_reg[24]__0_i_1_n_9\,
      O(5) => \wordcnt_reg[24]__0_i_1_n_10\,
      O(4) => \wordcnt_reg[24]__0_i_1_n_11\,
      O(3) => \wordcnt_reg[24]__0_i_1_n_12\,
      O(2) => \wordcnt_reg[24]__0_i_1_n_13\,
      O(1) => \wordcnt_reg[24]__0_i_1_n_14\,
      O(0) => \wordcnt_reg[24]__0_i_1_n_15\,
      S(7) => '0',
      S(6) => \wordcnt_reg[30]__0_n_0\,
      S(5) => \wordcnt_reg[29]__0_n_0\,
      S(4) => \wordcnt_reg[28]__0_n_0\,
      S(3) => \wordcnt_reg[27]__0_n_0\,
      S(2) => \wordcnt_reg[26]__0_n_0\,
      S(1) => \wordcnt_reg[25]__0_n_0\,
      S(0) => \wordcnt_reg[24]__0_n_0\
    );
\wordcnt_reg[24]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[16]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_wordcnt_reg[24]_i_1_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \wordcnt_reg[24]_i_1_n_2\,
      CO(4) => \wordcnt_reg[24]_i_1_n_3\,
      CO(3) => \wordcnt_reg[24]_i_1_n_4\,
      CO(2) => \wordcnt_reg[24]_i_1_n_5\,
      CO(1) => \wordcnt_reg[24]_i_1_n_6\,
      CO(0) => \wordcnt_reg[24]_i_1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NLW_wordcnt_reg[24]_i_1_O_UNCONNECTED\(7),
      O(6) => \wordcnt_reg[24]_i_1_n_9\,
      O(5) => \wordcnt_reg[24]_i_1_n_10\,
      O(4) => \wordcnt_reg[24]_i_1_n_11\,
      O(3) => \wordcnt_reg[24]_i_1_n_12\,
      O(2) => \wordcnt_reg[24]_i_1_n_13\,
      O(1) => \wordcnt_reg[24]_i_1_n_14\,
      O(0) => \wordcnt_reg[24]_i_1_n_15\,
      S(7) => '0',
      S(6 downto 0) => wordcnt_reg(30 downto 24)
    );
\wordcnt_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[24]_i_1_n_14\,
      Q => wordcnt_reg(25),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[25]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[24]__0_i_1_n_14\,
      Q => \wordcnt_reg[25]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[24]_i_1_n_13\,
      Q => wordcnt_reg(26),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[26]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[24]__0_i_1_n_13\,
      Q => \wordcnt_reg[26]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[24]_i_1_n_12\,
      Q => wordcnt_reg(27),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[27]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[24]__0_i_1_n_12\,
      Q => \wordcnt_reg[27]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[24]_i_1_n_11\,
      Q => wordcnt_reg(28),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[28]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[24]__0_i_1_n_11\,
      Q => \wordcnt_reg[28]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[24]_i_1_n_10\,
      Q => wordcnt_reg(29),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[29]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[24]__0_i_1_n_10\,
      Q => \wordcnt_reg[29]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[0]_i_3_n_13\,
      Q => wordcnt_reg(2),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[2]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3_n_13\,
      Q => \wordcnt_reg[2]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[24]_i_1_n_9\,
      Q => wordcnt_reg(30),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[30]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[24]__0_i_1_n_9\,
      Q => \wordcnt_reg[30]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[0]_i_3_n_12\,
      Q => wordcnt_reg(3),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[3]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3_n_12\,
      Q => \wordcnt_reg[3]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[0]_i_3_n_11\,
      Q => wordcnt_reg(4),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[4]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3_n_11\,
      Q => \wordcnt_reg[4]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[0]_i_3_n_10\,
      Q => wordcnt_reg(5),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[5]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3_n_10\,
      Q => \wordcnt_reg[5]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[0]_i_3_n_9\,
      Q => wordcnt_reg(6),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[6]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3_n_9\,
      Q => \wordcnt_reg[6]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[0]_i_3_n_8\,
      Q => wordcnt_reg(7),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[7]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3_n_8\,
      Q => \wordcnt_reg[7]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[8]_i_1_n_15\,
      Q => wordcnt_reg(8),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[8]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1_n_15\,
      Q => \wordcnt_reg[8]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
\wordcnt_reg[8]__0_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[0]__0_i_3_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[8]__0_i_1_n_0\,
      CO(6) => \wordcnt_reg[8]__0_i_1_n_1\,
      CO(5) => \wordcnt_reg[8]__0_i_1_n_2\,
      CO(4) => \wordcnt_reg[8]__0_i_1_n_3\,
      CO(3) => \wordcnt_reg[8]__0_i_1_n_4\,
      CO(2) => \wordcnt_reg[8]__0_i_1_n_5\,
      CO(1) => \wordcnt_reg[8]__0_i_1_n_6\,
      CO(0) => \wordcnt_reg[8]__0_i_1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \wordcnt_reg[8]__0_i_1_n_8\,
      O(6) => \wordcnt_reg[8]__0_i_1_n_9\,
      O(5) => \wordcnt_reg[8]__0_i_1_n_10\,
      O(4) => \wordcnt_reg[8]__0_i_1_n_11\,
      O(3) => \wordcnt_reg[8]__0_i_1_n_12\,
      O(2) => \wordcnt_reg[8]__0_i_1_n_13\,
      O(1) => \wordcnt_reg[8]__0_i_1_n_14\,
      O(0) => \wordcnt_reg[8]__0_i_1_n_15\,
      S(7) => \wordcnt_reg[15]__0_n_0\,
      S(6) => \wordcnt_reg[14]__0_n_0\,
      S(5) => \wordcnt_reg[13]__0_n_0\,
      S(4) => \wordcnt_reg[12]__0_n_0\,
      S(3) => \wordcnt_reg[11]__0_n_0\,
      S(2) => \wordcnt_reg[10]__0_n_0\,
      S(1) => \wordcnt_reg[9]__0_n_0\,
      S(0) => \wordcnt_reg[8]__0_n_0\
    );
\wordcnt_reg[8]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[0]_i_3_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[8]_i_1_n_0\,
      CO(6) => \wordcnt_reg[8]_i_1_n_1\,
      CO(5) => \wordcnt_reg[8]_i_1_n_2\,
      CO(4) => \wordcnt_reg[8]_i_1_n_3\,
      CO(3) => \wordcnt_reg[8]_i_1_n_4\,
      CO(2) => \wordcnt_reg[8]_i_1_n_5\,
      CO(1) => \wordcnt_reg[8]_i_1_n_6\,
      CO(0) => \wordcnt_reg[8]_i_1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \wordcnt_reg[8]_i_1_n_8\,
      O(6) => \wordcnt_reg[8]_i_1_n_9\,
      O(5) => \wordcnt_reg[8]_i_1_n_10\,
      O(4) => \wordcnt_reg[8]_i_1_n_11\,
      O(3) => \wordcnt_reg[8]_i_1_n_12\,
      O(2) => \wordcnt_reg[8]_i_1_n_13\,
      O(1) => \wordcnt_reg[8]_i_1_n_14\,
      O(0) => \wordcnt_reg[8]_i_1_n_15\,
      S(7 downto 0) => wordcnt_reg(15 downto 8)
    );
\wordcnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2_n_0\,
      D => \wordcnt_reg[8]_i_1_n_14\,
      Q => wordcnt_reg(9),
      R => \wordcnt[0]_i_1_n_0\
    );
\wordcnt_reg[9]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1_n_14\,
      Q => \wordcnt_reg[9]__0_n_0\,
      R => \wordcnt[0]__0_i_1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Axislave_v1_0__parameterized1\ is
  port (
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \stateOp_reg[1]\ : out STD_LOGIC;
    recvAXIS_tdata : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \crc_imd_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[15]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \tixVController_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \resid_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[0]\ : out STD_LOGIC;
    \tixVController_reg[0]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \stateOp_reg[0]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \stateOp_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \stateOp_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    rxAXIS_tvalid : out STD_LOGIC;
    \stateOp_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \tixVController_reg[0]_0\ : out STD_LOGIC;
    \tixVController_reg[1]\ : out STD_LOGIC;
    \wordcnt_reg[30]_0\ : out STD_LOGIC_VECTOR ( 30 downto 0 );
    \stateOp_reg[2]_1\ : out STD_LOGIC;
    rpuAXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    recvAXIS_tlast : out STD_LOGIC;
    \stateOp_reg[1]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \stateOp_reg[0]_2\ : out STD_LOGIC;
    \rxlen_reg[1]\ : out STD_LOGIC;
    \crc_imd_reg[1]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    recvAXIS_tlast_sig_reg_0 : out STD_LOGIC;
    crc_imd032_out : out STD_LOGIC;
    crc_imd017_out : out STD_LOGIC;
    \recvAXIS_tdata_sig_reg[7]_0\ : out STD_LOGIC;
    stateOp_reg : out STD_LOGIC;
    \recvAXIS_tdata_sig_reg[21]_0\ : out STD_LOGIC;
    \txAXIS_tdata_reg[14]\ : out STD_LOGIC;
    stateOp_reg_0 : out STD_LOGIC;
    \txAXIS_tdata_reg[30]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \crc_imd_reg[14]\ : out STD_LOGIC;
    crc_imd059_out : out STD_LOGIC;
    crc_imd060_out : out STD_LOGIC;
    \txAXIS_tdata_reg[11]\ : out STD_LOGIC;
    \recvAXIS_tdata_sig_reg[12]_0\ : out STD_LOGIC;
    \txAXIS_tdata_reg[31]\ : out STD_LOGIC;
    \recvAXIS_tdata_sig_reg[13]_0\ : out STD_LOGIC;
    stateOp_reg_1 : out STD_LOGIC;
    stateOp_reg_2 : out STD_LOGIC;
    stateOp_reg_3 : out STD_LOGIC;
    \recvAXIS_tdata_sig_reg[5]_0\ : out STD_LOGIC;
    \txAXIS_tdata_reg[14]_0\ : out STD_LOGIC;
    \recvAXIS_tdata_sig_reg[23]_0\ : out STD_LOGIC;
    \recvAXIS_tdata_sig_reg[2]_0\ : out STD_LOGIC;
    \recvAXIS_tdata_sig_reg[13]_1\ : out STD_LOGIC;
    \txAXIS_tdata_reg[11]_0\ : out STD_LOGIC;
    \recvAXIS_tdata_sig_reg[21]_1\ : out STD_LOGIC;
    \txAXIS_tdata_reg[7]\ : out STD_LOGIC;
    p_24_in : out STD_LOGIC;
    crcAXIS_tlast_sig_reg : out STD_LOGIC;
    \stateOp_reg[2]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_2\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \tixVCommand_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \tixVCommand_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \scoreMin_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \tkst_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \tkst_reg[31]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \stateOp_reg[0]_3\ : out STD_LOGIC;
    \resid_reg[0]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \ixRetbufCrc_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ixRetbufCrc_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ixRetbufCrc_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ixRetbufCrc_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ixRetbufCrc_reg[2]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ixRetbufCrc_reg[2]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ixRetbufCrc_reg[2]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resid_reg[0]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_3\ : out STD_LOGIC_VECTOR ( 29 downto 0 );
    \tixVCommand_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \ixRetbufCrc_reg[5]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \opbuf_reg[0][7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \opbuf_reg[5][7]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \recvAXIS_tdata_sig_reg[15]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \recvAXIS_tdata_sig_reg[23]_1\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \recvAXIS_tdata_sig_reg[23]_2\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \opbuf_reg[1][7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \stateOp_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ixRetbufCrc_reg[5]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \opbuf_reg[2][7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \recvAXIS_tdata_sig_reg[15]_1\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \stateOp_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_4\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_5\ : out STD_LOGIC;
    \stateSend_reg[0]_0\ : out STD_LOGIC;
    AXIS_tlast : out STD_LOGIC;
    AXIS_tvalid : out STD_LOGIC;
    \out\ : out STD_LOGIC_VECTOR ( 24 downto 0 );
    AXIL_wready_sig_reg_0 : out STD_LOGIC;
    AXIL_awready_sig_reg_0 : out STD_LOGIC;
    AXIL_arready : out STD_LOGIC;
    AXIL_bvalid_sig_reg_0 : out STD_LOGIC;
    rpuAXIL_rvalid : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    crcAXIS_tlast_sig_reg_0 : in STD_LOGIC;
    \pollbuf_reg[4][7]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pollbuf_reg[0][7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \txAXIS_tdata_reg[15]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \retbuf_reg[36][7]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \retbuf_reg[36][7]_0\ : in STD_LOGIC;
    \retbuf_reg[5][5]\ : in STD_LOGIC;
    \lastAXIS_tkeep_reg[3]\ : in STD_LOGIC;
    lenRet1 : in STD_LOGIC;
    \crcAXIS_tkeep_reg[0]\ : in STD_LOGIC;
    \opbuf_reg[6][0]\ : in STD_LOGIC;
    \opbuf_reg[6][0]_0\ : in STD_LOGIC;
    \opbuf_reg[1][0]\ : in STD_LOGIC;
    \opbuf_reg[1][0]_0\ : in STD_LOGIC;
    \retbuf_reg[14][4]\ : in STD_LOGIC;
    \retbuf_reg[14][4]_0\ : in STD_LOGIC;
    \retbuf_reg[2][7]\ : in STD_LOGIC;
    \wordcnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_next_reg[4]\ : in STD_LOGIC;
    \lastAXIS_tkeep_reg[3]_0\ : in STD_LOGIC;
    \stateOp_next_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_next_reg[2]_0\ : in STD_LOGIC;
    \stateOp_next_reg[1]\ : in STD_LOGIC;
    crcAXIS_tlast_sig_reg_1 : in STD_LOGIC;
    crcAXIS_tlast_sig_reg_2 : in STD_LOGIC;
    \rxlen_reg[1]_0\ : in STD_LOGIC;
    rxlen : in STD_LOGIC_VECTOR ( 0 to 0 );
    \crc_imd_reg[2]\ : in STD_LOGIC;
    \crc_imd_reg[2]_0\ : in STD_LOGIC;
    crc_imd013_out : in STD_LOGIC;
    crc_imd015_out : in STD_LOGIC;
    crc_imd033_out : in STD_LOGIC;
    crc_imd019_out : in STD_LOGIC;
    crc_imd020_out : in STD_LOGIC;
    \crc_imd_reg[9]\ : in STD_LOGIC;
    stateOp_reg_4 : in STD_LOGIC;
    \crc_imd_reg[2]_1\ : in STD_LOGIC;
    \crc_imd_reg[0]\ : in STD_LOGIC;
    \crc_imd_reg[0]_0\ : in STD_LOGIC;
    \crc_imd_reg[2]_2\ : in STD_LOGIC;
    \crc_imd_reg[2]_3\ : in STD_LOGIC;
    \crc_imd_reg[4]\ : in STD_LOGIC;
    \crc_imd_reg[6]\ : in STD_LOGIC;
    \crc_imd_reg[8]\ : in STD_LOGIC;
    \crc_imd_reg[8]_0\ : in STD_LOGIC;
    \crc_imd_reg[9]_0\ : in STD_LOGIC;
    \crc_imd_reg[10]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \crc_imd_reg[13]\ : in STD_LOGIC;
    \crc_imd_reg[15]_0\ : in STD_LOGIC;
    \crc_imd_reg[15]_1\ : in STD_LOGIC;
    p_10_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    \sendAXIL_rdata_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \crc_imd_reg[11]\ : in STD_LOGIC;
    \crc_imd[6]_i_3__0_0\ : in STD_LOGIC;
    \crc_imd[2]_i_3__0_0\ : in STD_LOGIC;
    \stateOp_reg[0]_4\ : in STD_LOGIC;
    \stateOp_reg[0]_5\ : in STD_LOGIC;
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[0]_6\ : in STD_LOGIC;
    \stateOp_reg[0]_7\ : in STD_LOGIC;
    \crcAXIS_tlast_sig_i_4__0_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \wordcnt_reg[0]_1\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[0]_0\ : in STD_LOGIC;
    \stateOp_reg[0]_8\ : in STD_LOGIC;
    \stateOp_reg[0]_9\ : in STD_LOGIC;
    \lastAXIS_tkeep_reg[3]_1\ : in STD_LOGIC;
    \retbuf_reg[5][7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \retbuf_reg[5][5]_0\ : in STD_LOGIC;
    \retbuf_reg[5][5]_1\ : in STD_LOGIC;
    \retbuf_reg[1][7]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \retbuf_reg[4][4]\ : in STD_LOGIC;
    \retbuf_reg[4][5]\ : in STD_LOGIC;
    \retbuf_reg[4][6]\ : in STD_LOGIC;
    \retbuf_reg[1][0]\ : in STD_LOGIC;
    \retbuf_reg[1][2]\ : in STD_LOGIC;
    \retbuf_reg[1][4]\ : in STD_LOGIC;
    \retbuf_reg[1][5]\ : in STD_LOGIC;
    \retbuf_reg[1][6]\ : in STD_LOGIC;
    \retbuf_reg[1][7]_0\ : in STD_LOGIC;
    \retbuf_reg[4][7]\ : in STD_LOGIC;
    \retbuf_reg[5][7]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]_1\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \crcAXIS_tkeep_reg[3]_0\ : in STD_LOGIC;
    \stateOp_reg[3]_3\ : in STD_LOGIC;
    \stateOp_reg[3]_4\ : in STD_LOGIC;
    crcAXIS_tlast_sig_reg_3 : in STD_LOGIC;
    crcAXIS_tlast_sig_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
    crcAXIS_tlast_sig_reg_5 : in STD_LOGIC;
    \txAXIS_tdata_reg[0]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[0]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[0]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[0]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[1]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[1]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[1]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[1]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[2]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[2]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[3]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[3]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[3]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[4]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[4]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[5]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[5]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[5]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[6]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[6]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]_3\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]_4\ : in STD_LOGIC;
    \txAXIS_tdata_reg[8]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[8]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[8]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[9]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[9]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[9]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[10]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[10]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[10]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[11]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[11]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[11]_3\ : in STD_LOGIC;
    \txAXIS_tdata_reg[12]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[12]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[12]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[13]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[13]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[13]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[14]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[14]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[14]_3\ : in STD_LOGIC;
    \txAXIS_tdata_reg[15]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[15]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[15]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[17]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[17]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[17]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[17]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[17]_3\ : in STD_LOGIC;
    \txAXIS_tdata_reg[19]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[19]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[19]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[19]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[20]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[20]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[20]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[20]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[21]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[21]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[21]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[22]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[22]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[22]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[23]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[23]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[23]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[24]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[24]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[24]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[25]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[25]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[26]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[26]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[26]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[26]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[27]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[27]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[27]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[28]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[28]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[28]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[29]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[29]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[30]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[30]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[30]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[31]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[31]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[31]_2\ : in STD_LOGIC;
    \pollbuf_reg[1][7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \txAXIS_tdata_reg[15]_3\ : in STD_LOGIC;
    \tixVBuffer_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \len_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \len_reg[15]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \tixVController_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \crcAXIS_tkeep_reg[1]\ : in STD_LOGIC;
    \retbuf_reg[39][0]\ : in STD_LOGIC;
    \stateOp_reg[1]_6\ : in STD_LOGIC;
    \stateOp_reg[1]_7\ : in STD_LOGIC;
    \stateOp_reg[2]_3\ : in STD_LOGIC;
    \stateOp_reg[2]_4\ : in STD_LOGIC;
    \stateOp_reg[4]_1\ : in STD_LOGIC;
    \stateOp_reg[4]_2\ : in STD_LOGIC;
    \stateOp_next_reg[0]\ : in STD_LOGIC;
    \tixVBufxfop_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    txlast1 : in STD_LOGIC_VECTOR ( 29 downto 0 );
    \txlen_reg[0]\ : in STD_LOGIC;
    \wordcntLast_reg[1]\ : in STD_LOGIC;
    crcAXIS_tlast_sig_reg_6 : in STD_LOGIC;
    \stateOp_reg[0]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateOp_reg[0]_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateOp_reg[0]_12\ : in STD_LOGIC;
    \crcAXIS_tkeep_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[3]_5\ : in STD_LOGIC;
    \stateOp_reg[3]_6\ : in STD_LOGIC;
    \recvAXIS_tlast_sig_reg_i_3__0_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \stateOp_reg[0]_13\ : in STD_LOGIC;
    \crcAXIS_tlast_sig_i_9__0_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \crcAXIS_tlast_sig_i_9__0_1\ : in STD_LOGIC;
    rpuAXIL_wvalid : in STD_LOGIC;
    \sendAXIL_rdata_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    aclk_sig : in STD_LOGIC;
    rpuAXIL_awvalid : in STD_LOGIC;
    rpuAXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    rpuAXIL_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rpuAXIL_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rpuAXIL_bready : in STD_LOGIC;
    rpuAXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rpuAXIL_arvalid : in STD_LOGIC;
    rpuAXIL_rready : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Axislave_v1_0__parameterized1\ : entity is "Axislave_v1_0";
end \design_1_Vsp_core_0_0_Axislave_v1_0__parameterized1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Axislave_v1_0__parameterized1\ is
  signal AXIL_araddr_sig : STD_LOGIC_VECTOR ( 5 downto 4 );
  signal \^axil_arready\ : STD_LOGIC;
  signal AXIL_arready_sig0 : STD_LOGIC;
  signal AXIL_awready_sig0 : STD_LOGIC;
  signal \AXIL_awready_sig_i_1__0_n_0\ : STD_LOGIC;
  signal \^axil_awready_sig_reg_0\ : STD_LOGIC;
  signal \AXIL_bvalid_sig_i_1__0_n_0\ : STD_LOGIC;
  signal \^axil_bvalid_sig_reg_0\ : STD_LOGIC;
  signal \AXIL_rvalid_sig_i_1__0_n_0\ : STD_LOGIC;
  signal \AXIL_wdata_sig[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \AXIL_wdata_sig[23]_i_1__0_n_0\ : STD_LOGIC;
  signal \AXIL_wdata_sig[31]_i_1__0_n_0\ : STD_LOGIC;
  signal \AXIL_wdata_sig[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[0]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[10]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[11]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[12]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[13]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[14]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[15]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[16]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[17]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[18]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[19]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[1]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[20]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[21]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[22]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[23]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[24]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[25]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[26]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[27]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[28]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[29]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[30]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[31]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[4]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[5]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[6]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[7]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[8]\ : STD_LOGIC;
  signal \AXIL_wdata_sig_reg_n_0_[9]\ : STD_LOGIC;
  signal \AXIL_wready_sig_i_1__0_n_0\ : STD_LOGIC;
  signal \^axil_wready_sig_reg_0\ : STD_LOGIC;
  signal AXIS_tdata : STD_LOGIC_VECTOR ( 31 downto 2 );
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ackRxtx : STD_LOGIC;
  signal \awdone_i_1__1_n_0\ : STD_LOGIC;
  signal awdone_reg_n_0 : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_4_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_5_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_6_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_8_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_9_n_0\ : STD_LOGIC;
  signal \crcAXIS_tlast_sig_i_2__0_n_0\ : STD_LOGIC;
  signal \crcAXIS_tlast_sig_i_4__0_n_0\ : STD_LOGIC;
  signal \crcAXIS_tlast_sig_i_5__0_n_0\ : STD_LOGIC;
  signal \crcAXIS_tlast_sig_i_8__0_n_0\ : STD_LOGIC;
  signal \crcAXIS_tlast_sig_i_9__0_n_0\ : STD_LOGIC;
  signal \^crc_imd017_out\ : STD_LOGIC;
  signal \^crc_imd032_out\ : STD_LOGIC;
  signal \^crc_imd059_out\ : STD_LOGIC;
  signal \^crc_imd060_out\ : STD_LOGIC;
  signal \crc_imd[0]_i_10__0_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_7__0_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_17__0_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_18__0_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_19__0_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_26__0_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_27__0_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_11__0_n_0\ : STD_LOGIC;
  signal \crc_imd[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \crc_imd[2]_i_5__0_n_0\ : STD_LOGIC;
  signal \crc_imd[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \crc_imd[3]_i_6__0_n_0\ : STD_LOGIC;
  signal \crc_imd[3]_i_7__0_n_0\ : STD_LOGIC;
  signal \crc_imd[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \crc_imd[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \crc_imd[5]_i_3__0_n_0\ : STD_LOGIC;
  signal \crc_imd[5]_i_4__0_n_0\ : STD_LOGIC;
  signal \crc_imd[6]_i_3__0_n_0\ : STD_LOGIC;
  signal \crc_imd[6]_i_4__0_n_0\ : STD_LOGIC;
  signal \crc_imd[9]_i_4__0_n_0\ : STD_LOGIC;
  signal \crc_imd[9]_i_7__0_n_0\ : STD_LOGIC;
  signal \^crc_imd_reg[14]\ : STD_LOGIC;
  signal i : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \i[0]_i_1__14_n_0\ : STD_LOGIC;
  signal \i[10]_i_1__3_n_0\ : STD_LOGIC;
  signal \i[11]_i_1__2_n_0\ : STD_LOGIC;
  signal \i[12]_i_1__2_n_0\ : STD_LOGIC;
  signal \i[12]_i_2__0_n_0\ : STD_LOGIC;
  signal \i[13]_i_1__2_n_0\ : STD_LOGIC;
  signal \i[13]_i_2__2_n_0\ : STD_LOGIC;
  signal \i[14]_i_1__0_n_0\ : STD_LOGIC;
  signal \i[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \i[15]_i_2__0_n_0\ : STD_LOGIC;
  signal \i[15]_i_3__0_n_0\ : STD_LOGIC;
  signal \i[15]_i_4__0_n_0\ : STD_LOGIC;
  signal \i[15]_i_5__0_n_0\ : STD_LOGIC;
  signal \i[1]_i_1__13_n_0\ : STD_LOGIC;
  signal \i[2]_i_1__9_n_0\ : STD_LOGIC;
  signal \i[3]_i_1__9_n_0\ : STD_LOGIC;
  signal \i[4]_i_1__9_n_0\ : STD_LOGIC;
  signal \i[5]_i_1__8_n_0\ : STD_LOGIC;
  signal \i[5]_i_2__5_n_0\ : STD_LOGIC;
  signal \i[6]_i_1__7_n_0\ : STD_LOGIC;
  signal \i[7]_i_1__7_n_0\ : STD_LOGIC;
  signal \i[8]_i_1__6_n_0\ : STD_LOGIC;
  signal \i[9]_i_1__4_n_0\ : STD_LOGIC;
  signal \i[9]_i_2__4_n_0\ : STD_LOGIC;
  signal ixBlkWrite : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal len : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \myCrc/crc_imd031_out\ : STD_LOGIC;
  signal \myCrc/crc_imd034_out\ : STD_LOGIC;
  signal \myCrc/crc_imd035_out\ : STD_LOGIC;
  signal \myCrc/crc_imd058_out\ : STD_LOGIC;
  signal \myCrc/crc_imd061_out\ : STD_LOGIC;
  signal \myCrc/crc_imd062_out\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal p_1_in0 : STD_LOGIC;
  signal \recvAXIL_rdata[31]_i_1_n_0\ : STD_LOGIC;
  signal \recvAXIL_rdata[31]_i_2_n_0\ : STD_LOGIC;
  signal \recvAXIL_rdata_reg_n_0_[31]\ : STD_LOGIC;
  signal \^recvaxis_tdata\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \recvAXIS_tdata_sig[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[13]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[14]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[16]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[17]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[18]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[19]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[20]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[21]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[22]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[23]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[24]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[25]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[26]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[27]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[28]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[29]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[30]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[31]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[31]_i_2_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tdata_sig[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \^recvaxis_tdata_sig_reg[12]_0\ : STD_LOGIC;
  signal \^recvaxis_tdata_sig_reg[13]_0\ : STD_LOGIC;
  signal \^recvaxis_tdata_sig_reg[21]_0\ : STD_LOGIC;
  signal \^recvaxis_tdata_sig_reg[23]_0\ : STD_LOGIC;
  signal \^recvaxis_tdata_sig_reg[7]_0\ : STD_LOGIC;
  signal \^recvaxis_tlast\ : STD_LOGIC;
  signal recvAXIS_tlast_sig0 : STD_LOGIC;
  signal \recvAXIS_tlast_sig_i_10__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_i_11__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_i_12__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_i_13__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_i_14__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_i_1__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_i_4__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_i_5__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_i_6__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_i_7__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_i_8__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_i_9__0_n_0\ : STD_LOGIC;
  signal \^recvaxis_tlast_sig_reg_0\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_reg_i_2__0_n_6\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_reg_i_2__0_n_7\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_reg_i_3__0_n_0\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_reg_i_3__0_n_1\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_reg_i_3__0_n_2\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_reg_i_3__0_n_3\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_reg_i_3__0_n_4\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_reg_i_3__0_n_5\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_reg_i_3__0_n_6\ : STD_LOGIC;
  signal \recvAXIS_tlast_sig_reg_i_3__0_n_7\ : STD_LOGIC;
  signal recvAXIS_tready : STD_LOGIC;
  signal \recvStrbToStart_i_1__0_n_0\ : STD_LOGIC;
  signal \recvStrbToStart_i_2__0_n_0\ : STD_LOGIC;
  signal recvStrbToStart_reg_n_0 : STD_LOGIC;
  signal \recvStrbToStop_i_1__0_n_0\ : STD_LOGIC;
  signal \recvStrbToStop_i_2__0_n_0\ : STD_LOGIC;
  signal \recvStrbToStop_i_3__0_n_0\ : STD_LOGIC;
  signal recvStrbToStop_reg_n_0 : STD_LOGIC;
  signal req : STD_LOGIC;
  signal \rpuAXIL_rdata[31]_INST_0_i_1_n_0\ : STD_LOGIC;
  signal \^rpuaxil_rvalid\ : STD_LOGIC;
  signal rxAXIS_tdata : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal \^rxaxis_tvalid\ : STD_LOGIC;
  signal \rxlen[1]_i_2_n_0\ : STD_LOGIC;
  signal \rxlen[1]_i_4_n_0\ : STD_LOGIC;
  signal \rxlen[1]_i_5_n_0\ : STD_LOGIC;
  signal sendAXIL_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \sendAXIL_rdata[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[13]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[14]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[16]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[17]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[18]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[19]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[20]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[21]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[22]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[23]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[24]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[25]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[26]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[27]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[28]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[29]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[30]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[31]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[31]_i_2_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[31]_i_3_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[31]_i_4_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[31]_i_5_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \sendAXIL_rdata[9]_i_1__0_n_0\ : STD_LOGIC;
  signal sendStrbToStart0 : STD_LOGIC;
  signal \sendStrbToStart_i_10__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStart_i_11__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStart_i_12__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStart_i_13__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStart_i_1__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStart_i_2__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStart_i_3__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStart_i_4__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStart_i_5__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStart_i_6__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStart_i_7__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStart_i_8__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStart_i_9__0_n_0\ : STD_LOGIC;
  signal sendStrbToStart_reg_n_0 : STD_LOGIC;
  signal \sendStrbToStop_i_1__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStop_i_2__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStop_i_3__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStop_i_4__0_n_0\ : STD_LOGIC;
  signal \sendStrbToStop_i_5__0_n_0\ : STD_LOGIC;
  signal sendStrbToStop_reg_n_0 : STD_LOGIC;
  signal \stateOp[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \stateOp[0]_i_3_n_0\ : STD_LOGIC;
  signal \stateOp[0]_i_6__0_n_0\ : STD_LOGIC;
  signal \stateOp[0]_i_8__0_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_10__0_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_2__5_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_9__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_3__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_5__2_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_8_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_19_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_7__0_n_0\ : STD_LOGIC;
  signal \^stateop_reg[0]\ : STD_LOGIC;
  signal \^stateop_reg[0]_3\ : STD_LOGIC;
  signal \^stateop_reg[1]\ : STD_LOGIC;
  signal \^stateop_reg[1]_5\ : STD_LOGIC;
  signal \^stateop_reg[2]_1\ : STD_LOGIC;
  signal stateRecv : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \stateRecv[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \stateRecv[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_10__0_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_4__0_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_5__0_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_6_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_7__0_n_0\ : STD_LOGIC;
  signal \stateRecv[2]_i_9_n_0\ : STD_LOGIC;
  signal stateSend : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \stateSend[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \stateSend[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_10__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_11__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_13__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_14__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_15__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_16__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_17__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_18__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_19__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_20__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_21__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_22__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_23__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_24__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_25__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_26__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_27__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_28__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_29__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_30__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_31__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_4__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_5__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_6__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_7__0_n_0\ : STD_LOGIC;
  signal \stateSend[2]_i_9__0_n_0\ : STD_LOGIC;
  signal \^statesend_reg[0]_0\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12__0_n_0\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12__0_n_1\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12__0_n_2\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12__0_n_3\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12__0_n_4\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12__0_n_5\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12__0_n_6\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_12__0_n_7\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_8__0_n_6\ : STD_LOGIC;
  signal \stateSend_reg[2]_i_8__0_n_7\ : STD_LOGIC;
  signal stateTo : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \stateTo[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \stateTo[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \stateTo[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \stateTo[1]_i_4__0_n_0\ : STD_LOGIC;
  signal \stateTo[1]_i_5__0_n_0\ : STD_LOGIC;
  signal \stateTo[1]_i_6__0_n_0\ : STD_LOGIC;
  signal strbRead : STD_LOGIC;
  signal \^tixvcontroller_reg[0]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^tixvcontroller_reg[0]_0\ : STD_LOGIC;
  signal \^tixvcontroller_reg[1]\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_3__0_n_0\ : STD_LOGIC;
  signal \^txaxis_tdata_reg[11]\ : STD_LOGIC;
  signal \^txaxis_tdata_reg[11]_0\ : STD_LOGIC;
  signal \^txaxis_tdata_reg[14]\ : STD_LOGIC;
  signal \^txaxis_tdata_reg[30]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal txAXIS_tready : STD_LOGIC;
  signal \wdone_i_1__1_n_0\ : STD_LOGIC;
  signal wdone_reg_n_0 : STD_LOGIC;
  signal wordcnt0 : STD_LOGIC;
  signal \wordcntCrcLast[15]_i_2_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[15]_i_3_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[15]_i_4_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[15]_i_5_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[15]_i_6_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[15]_i_7_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[15]_i_8_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[15]_i_9_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[23]_i_2_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[23]_i_3_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[23]_i_4_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[23]_i_5_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[23]_i_6_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[23]_i_7_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[23]_i_8_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[23]_i_9_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[24]_i_2__0_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[7]_i_10_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[7]_i_11_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[7]_i_12_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[7]_i_2_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[7]_i_3_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[7]_i_4_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[7]_i_5_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[7]_i_6_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[7]_i_7_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[7]_i_8_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[7]_i_9_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[23]_i_1_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[23]_i_1_n_1\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[23]_i_1_n_2\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[23]_i_1_n_3\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[23]_i_1_n_4\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[23]_i_1_n_5\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[23]_i_1_n_6\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[23]_i_1_n_7\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \wordcnt[0]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \wordcnt[0]__0_i_4__0_n_0\ : STD_LOGIC;
  signal \wordcnt[0]__0_i_5__0_n_0\ : STD_LOGIC;
  signal \wordcnt[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \wordcnt[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \wordcnt[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \wordcnt[0]_i_6__0_n_0\ : STD_LOGIC;
  signal \wordcnt[30]_i_3__0_n_0\ : STD_LOGIC;
  signal \wordcnt[30]_i_5__0_n_0\ : STD_LOGIC;
  signal \wordcnt[30]_i_8__0_n_0\ : STD_LOGIC;
  signal wordcnt_reg : STD_LOGIC_VECTOR ( 30 downto 0 );
  signal \wordcnt_reg[0]__0_i_3__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_8\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_i_3__0_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[0]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_8\ : STD_LOGIC;
  signal \wordcnt_reg[0]_i_3__0_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[10]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[11]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[12]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[13]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[14]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[15]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_8\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_i_1__0_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[16]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_8\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_1__0_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[17]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[18]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[19]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[1]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[20]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[21]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[22]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[23]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1__0_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1__0_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1__0_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1__0_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1__0_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1__0_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1__0_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1__0_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1__0_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1__0_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1__0_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1__0_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_i_1__0_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[24]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1__0_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1__0_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1__0_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1__0_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1__0_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1__0_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1__0_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1__0_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1__0_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1__0_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1__0_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1__0_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_1__0_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[25]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[26]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[27]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[28]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[29]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[2]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[30]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[3]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[4]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[5]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[6]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[7]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_8\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_i_1__0_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[8]__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_10\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_11\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_12\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_13\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_14\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_15\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_8\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_1__0_n_9\ : STD_LOGIC;
  signal \wordcnt_reg[9]__0_n_0\ : STD_LOGIC;
  signal \NLW_recvAXIS_tlast_sig_reg_i_2__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_recvAXIS_tlast_sig_reg_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_recvAXIS_tlast_sig_reg_i_3__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateSend_reg[2]_i_12__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateSend_reg[2]_i_8__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_stateSend_reg[2]_i_8__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_wordcntCrcLast_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_wordcntCrcLast_reg[24]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_wordcnt_reg[24]__0_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_wordcnt_reg[24]__0_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_wordcnt_reg[24]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_wordcnt_reg[24]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \crcAXIS_tkeep[0]_i_1__0\ : label is "soft_lutpair2760";
  attribute SOFT_HLUTNM of \crcAXIS_tkeep[2]_i_1__0\ : label is "soft_lutpair2702";
  attribute SOFT_HLUTNM of \crcAXIS_tkeep[3]_i_2__0\ : label is "soft_lutpair2702";
  attribute SOFT_HLUTNM of \crcAXIS_tkeep[3]_i_8\ : label is "soft_lutpair2677";
  attribute SOFT_HLUTNM of \crc_imd[10]_i_4__0\ : label is "soft_lutpair2721";
  attribute SOFT_HLUTNM of \crc_imd[12]_i_2__0\ : label is "soft_lutpair2700";
  attribute SOFT_HLUTNM of \crc_imd[12]_i_4__0\ : label is "soft_lutpair2723";
  attribute SOFT_HLUTNM of \crc_imd[12]_i_5__0\ : label is "soft_lutpair2722";
  attribute SOFT_HLUTNM of \crc_imd[14]_i_10__0\ : label is "soft_lutpair2675";
  attribute SOFT_HLUTNM of \crc_imd[14]_i_2__0\ : label is "soft_lutpair2671";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_23__0\ : label is "soft_lutpair2673";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_27__0\ : label is "soft_lutpair2674";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_4\ : label is "soft_lutpair2682";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_9__0\ : label is "soft_lutpair2698";
  attribute SOFT_HLUTNM of \crc_imd[1]_i_5__0\ : label is "soft_lutpair2675";
  attribute SOFT_HLUTNM of \crc_imd[1]_i_6__0\ : label is "soft_lutpair2698";
  attribute SOFT_HLUTNM of \crc_imd[2]_i_6__0\ : label is "soft_lutpair2674";
  attribute SOFT_HLUTNM of \crc_imd[3]_i_2__0\ : label is "soft_lutpair2699";
  attribute SOFT_HLUTNM of \crc_imd[3]_i_5__0\ : label is "soft_lutpair2672";
  attribute SOFT_HLUTNM of \crc_imd[7]_i_2__0\ : label is "soft_lutpair2676";
  attribute SOFT_HLUTNM of \crc_imd[7]_i_9__0\ : label is "soft_lutpair2676";
  attribute SOFT_HLUTNM of \crc_imd[8]_i_7__0\ : label is "soft_lutpair2724";
  attribute SOFT_HLUTNM of \crc_imd[9]_i_3__0\ : label is "soft_lutpair2672";
  attribute SOFT_HLUTNM of \crc_imd[9]_i_8__0\ : label is "soft_lutpair2673";
  attribute SOFT_HLUTNM of \i[0]_i_1__14\ : label is "soft_lutpair2736";
  attribute SOFT_HLUTNM of \i[10]_i_1__3\ : label is "soft_lutpair2696";
  attribute SOFT_HLUTNM of \i[11]_i_1__2\ : label is "soft_lutpair2696";
  attribute SOFT_HLUTNM of \i[12]_i_2__0\ : label is "soft_lutpair2739";
  attribute SOFT_HLUTNM of \i[13]_i_1__2\ : label is "soft_lutpair2736";
  attribute SOFT_HLUTNM of \i[14]_i_1__0\ : label is "soft_lutpair2737";
  attribute SOFT_HLUTNM of \i[15]_i_2__0\ : label is "soft_lutpair2737";
  attribute SOFT_HLUTNM of \i[15]_i_3__0\ : label is "soft_lutpair2738";
  attribute SOFT_HLUTNM of \i[15]_i_5__0\ : label is "soft_lutpair2738";
  attribute SOFT_HLUTNM of \i[1]_i_1__13\ : label is "soft_lutpair2745";
  attribute SOFT_HLUTNM of \i[2]_i_1__9\ : label is "soft_lutpair2694";
  attribute SOFT_HLUTNM of \i[3]_i_1__9\ : label is "soft_lutpair2694";
  attribute SOFT_HLUTNM of \i[5]_i_1__8\ : label is "soft_lutpair2745";
  attribute SOFT_HLUTNM of \i[6]_i_1__7\ : label is "soft_lutpair2739";
  attribute SOFT_HLUTNM of \i[7]_i_1__7\ : label is "soft_lutpair2695";
  attribute SOFT_HLUTNM of \i[8]_i_1__6\ : label is "soft_lutpair2695";
  attribute SOFT_HLUTNM of \ixRetbufCrc[1]_i_1__0\ : label is "soft_lutpair2761";
  attribute SOFT_HLUTNM of \ixRetbufCrc[2]_i_1__0\ : label is "soft_lutpair2720";
  attribute SOFT_HLUTNM of \ixRetbufCrc[5]_i_2__0\ : label is "soft_lutpair2761";
  attribute SOFT_HLUTNM of \lastAXIS_tkeep[2]_i_1\ : label is "soft_lutpair2763";
  attribute SOFT_HLUTNM of \lastAXIS_tkeep[3]_i_1\ : label is "soft_lutpair2701";
  attribute SOFT_HLUTNM of \len[0]_i_1__0\ : label is "soft_lutpair2775";
  attribute SOFT_HLUTNM of \len[10]_i_1__0\ : label is "soft_lutpair2780";
  attribute SOFT_HLUTNM of \len[11]_i_1__0\ : label is "soft_lutpair2781";
  attribute SOFT_HLUTNM of \len[12]_i_1__0\ : label is "soft_lutpair2781";
  attribute SOFT_HLUTNM of \len[13]_i_1__0\ : label is "soft_lutpair2782";
  attribute SOFT_HLUTNM of \len[14]_i_1__0\ : label is "soft_lutpair2782";
  attribute SOFT_HLUTNM of \len[15]_i_2\ : label is "soft_lutpair2783";
  attribute SOFT_HLUTNM of \len[1]_i_1__0\ : label is "soft_lutpair2776";
  attribute SOFT_HLUTNM of \len[2]_i_1__0\ : label is "soft_lutpair2776";
  attribute SOFT_HLUTNM of \len[3]_i_1__0\ : label is "soft_lutpair2777";
  attribute SOFT_HLUTNM of \len[4]_i_1__0\ : label is "soft_lutpair2777";
  attribute SOFT_HLUTNM of \len[5]_i_1__0\ : label is "soft_lutpair2778";
  attribute SOFT_HLUTNM of \len[6]_i_1__0\ : label is "soft_lutpair2778";
  attribute SOFT_HLUTNM of \len[7]_i_1__0\ : label is "soft_lutpair2779";
  attribute SOFT_HLUTNM of \len[8]_i_1__0\ : label is "soft_lutpair2779";
  attribute SOFT_HLUTNM of \len[9]_i_1__0\ : label is "soft_lutpair2780";
  attribute SOFT_HLUTNM of \opbuf[0][0]_i_1__0\ : label is "soft_lutpair2703";
  attribute SOFT_HLUTNM of \opbuf[0][1]_i_1__0\ : label is "soft_lutpair2721";
  attribute SOFT_HLUTNM of \opbuf[0][2]_i_1__0\ : label is "soft_lutpair2722";
  attribute SOFT_HLUTNM of \opbuf[0][3]_i_1__0\ : label is "soft_lutpair2723";
  attribute SOFT_HLUTNM of \opbuf[0][4]_i_1__0\ : label is "soft_lutpair2725";
  attribute SOFT_HLUTNM of \opbuf[0][5]_i_1__0\ : label is "soft_lutpair2740";
  attribute SOFT_HLUTNM of \opbuf[0][6]_i_1__0\ : label is "soft_lutpair2724";
  attribute SOFT_HLUTNM of \opbuf[0][7]_i_1__0\ : label is "soft_lutpair2742";
  attribute SOFT_HLUTNM of \opbuf[1][0]_i_1__0\ : label is "soft_lutpair2712";
  attribute SOFT_HLUTNM of \opbuf[1][1]_i_1__0\ : label is "soft_lutpair2713";
  attribute SOFT_HLUTNM of \opbuf[1][2]_i_1__0\ : label is "soft_lutpair2714";
  attribute SOFT_HLUTNM of \opbuf[1][3]_i_1__0\ : label is "soft_lutpair2715";
  attribute SOFT_HLUTNM of \opbuf[1][4]_i_1__0\ : label is "soft_lutpair2716";
  attribute SOFT_HLUTNM of \opbuf[1][5]_i_1__0\ : label is "soft_lutpair2717";
  attribute SOFT_HLUTNM of \opbuf[1][6]_i_1__0\ : label is "soft_lutpair2718";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_2\ : label is "soft_lutpair2719";
  attribute SOFT_HLUTNM of \opbuf[2][0]_i_1__0\ : label is "soft_lutpair2712";
  attribute SOFT_HLUTNM of \opbuf[2][1]_i_1__0\ : label is "soft_lutpair2713";
  attribute SOFT_HLUTNM of \opbuf[2][2]_i_1__0\ : label is "soft_lutpair2714";
  attribute SOFT_HLUTNM of \opbuf[2][3]_i_1__0\ : label is "soft_lutpair2715";
  attribute SOFT_HLUTNM of \opbuf[2][4]_i_1__0\ : label is "soft_lutpair2716";
  attribute SOFT_HLUTNM of \opbuf[2][5]_i_1__0\ : label is "soft_lutpair2717";
  attribute SOFT_HLUTNM of \opbuf[2][6]_i_1__0\ : label is "soft_lutpair2718";
  attribute SOFT_HLUTNM of \opbuf[2][7]_i_1__0\ : label is "soft_lutpair2719";
  attribute SOFT_HLUTNM of \opbuf[5][0]_i_1__0\ : label is "soft_lutpair2704";
  attribute SOFT_HLUTNM of \opbuf[5][1]_i_1__0\ : label is "soft_lutpair2705";
  attribute SOFT_HLUTNM of \opbuf[5][2]_i_1__0\ : label is "soft_lutpair2706";
  attribute SOFT_HLUTNM of \opbuf[5][3]_i_1__0\ : label is "soft_lutpair2707";
  attribute SOFT_HLUTNM of \opbuf[5][4]_i_1__0\ : label is "soft_lutpair2708";
  attribute SOFT_HLUTNM of \opbuf[5][5]_i_1__0\ : label is "soft_lutpair2709";
  attribute SOFT_HLUTNM of \opbuf[5][6]_i_1__0\ : label is "soft_lutpair2710";
  attribute SOFT_HLUTNM of \opbuf[5][7]_i_1__0\ : label is "soft_lutpair2711";
  attribute SOFT_HLUTNM of \opbuf[6][0]_i_1__0\ : label is "soft_lutpair2704";
  attribute SOFT_HLUTNM of \opbuf[6][1]_i_1__0\ : label is "soft_lutpair2705";
  attribute SOFT_HLUTNM of \opbuf[6][2]_i_1__0\ : label is "soft_lutpair2706";
  attribute SOFT_HLUTNM of \opbuf[6][3]_i_1__0\ : label is "soft_lutpair2707";
  attribute SOFT_HLUTNM of \opbuf[6][4]_i_1__0\ : label is "soft_lutpair2708";
  attribute SOFT_HLUTNM of \opbuf[6][5]_i_1__0\ : label is "soft_lutpair2709";
  attribute SOFT_HLUTNM of \opbuf[6][6]_i_1__0\ : label is "soft_lutpair2710";
  attribute SOFT_HLUTNM of \opbuf[6][7]_i_2\ : label is "soft_lutpair2711";
  attribute SOFT_HLUTNM of \pollbuf[0][0]_i_1__0\ : label is "soft_lutpair2760";
  attribute SOFT_HLUTNM of \pollbuf[0][1]_i_1__0\ : label is "soft_lutpair2768";
  attribute SOFT_HLUTNM of \pollbuf[0][2]_i_1__0\ : label is "soft_lutpair2768";
  attribute SOFT_HLUTNM of \pollbuf[0][3]_i_1__0\ : label is "soft_lutpair2769";
  attribute SOFT_HLUTNM of \pollbuf[0][4]_i_1__0\ : label is "soft_lutpair2769";
  attribute SOFT_HLUTNM of \pollbuf[0][5]_i_1__0\ : label is "soft_lutpair2770";
  attribute SOFT_HLUTNM of \pollbuf[0][6]_i_1__0\ : label is "soft_lutpair2770";
  attribute SOFT_HLUTNM of \pollbuf[0][7]_i_2__0\ : label is "soft_lutpair2771";
  attribute SOFT_HLUTNM of \pollbuf[1][0]_i_1__0\ : label is "soft_lutpair2764";
  attribute SOFT_HLUTNM of \pollbuf[1][1]_i_1__0\ : label is "soft_lutpair2764";
  attribute SOFT_HLUTNM of \pollbuf[1][2]_i_1__0\ : label is "soft_lutpair2765";
  attribute SOFT_HLUTNM of \pollbuf[1][3]_i_1__0\ : label is "soft_lutpair2765";
  attribute SOFT_HLUTNM of \pollbuf[1][4]_i_1__0\ : label is "soft_lutpair2766";
  attribute SOFT_HLUTNM of \pollbuf[1][5]_i_1__0\ : label is "soft_lutpair2766";
  attribute SOFT_HLUTNM of \pollbuf[1][6]_i_1__0\ : label is "soft_lutpair2767";
  attribute SOFT_HLUTNM of \pollbuf[1][7]_i_1__0\ : label is "soft_lutpair2767";
  attribute SOFT_HLUTNM of \pollbuf[4][0]_i_1\ : label is "soft_lutpair2753";
  attribute SOFT_HLUTNM of \pollbuf[4][1]_i_1\ : label is "soft_lutpair2754";
  attribute SOFT_HLUTNM of \pollbuf[4][2]_i_1\ : label is "soft_lutpair2755";
  attribute SOFT_HLUTNM of \pollbuf[4][3]_i_1\ : label is "soft_lutpair2700";
  attribute SOFT_HLUTNM of \pollbuf[4][4]_i_1\ : label is "soft_lutpair2757";
  attribute SOFT_HLUTNM of \pollbuf[4][5]_i_1\ : label is "soft_lutpair2758";
  attribute SOFT_HLUTNM of \pollbuf[4][6]_i_1\ : label is "soft_lutpair2759";
  attribute SOFT_HLUTNM of \pollbuf[4][7]_i_2\ : label is "soft_lutpair2699";
  attribute SOFT_HLUTNM of \pollbuf[5][0]_i_1\ : label is "soft_lutpair2753";
  attribute SOFT_HLUTNM of \pollbuf[5][1]_i_1\ : label is "soft_lutpair2754";
  attribute SOFT_HLUTNM of \pollbuf[5][2]_i_1\ : label is "soft_lutpair2755";
  attribute SOFT_HLUTNM of \pollbuf[5][3]_i_1\ : label is "soft_lutpair2756";
  attribute SOFT_HLUTNM of \pollbuf[5][4]_i_1\ : label is "soft_lutpair2756";
  attribute SOFT_HLUTNM of \pollbuf[5][5]_i_1\ : label is "soft_lutpair2757";
  attribute SOFT_HLUTNM of \pollbuf[5][6]_i_1\ : label is "soft_lutpair2758";
  attribute SOFT_HLUTNM of \pollbuf[5][7]_i_1\ : label is "soft_lutpair2759";
  attribute SOFT_HLUTNM of \recvAXIL_rdata[31]_i_1\ : label is "soft_lutpair2744";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[10]_i_1__0\ : label is "soft_lutpair2728";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[11]_i_1__0\ : label is "soft_lutpair2813";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[12]_i_1__0\ : label is "soft_lutpair2812";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[13]_i_1__0\ : label is "soft_lutpair2733";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[14]_i_1__0\ : label is "soft_lutpair2812";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[15]_i_1__0\ : label is "soft_lutpair2811";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[16]_i_1__0\ : label is "soft_lutpair2811";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[17]_i_1__0\ : label is "soft_lutpair2810";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[18]_i_1__0\ : label is "soft_lutpair2810";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[19]_i_1__0\ : label is "soft_lutpair2809";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[1]_i_1__0\ : label is "soft_lutpair2735";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[20]_i_1__0\ : label is "soft_lutpair2809";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[21]_i_1__0\ : label is "soft_lutpair2732";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[22]_i_1__0\ : label is "soft_lutpair2727";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[23]_i_1__0\ : label is "soft_lutpair2808";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[24]_i_1__0\ : label is "soft_lutpair2808";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[25]_i_1__0\ : label is "soft_lutpair2734";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[26]_i_1__0\ : label is "soft_lutpair2730";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[27]_i_1__0\ : label is "soft_lutpair2807";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[28]_i_1__0\ : label is "soft_lutpair2807";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[29]_i_1__0\ : label is "soft_lutpair2806";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[2]_i_1__0\ : label is "soft_lutpair2816";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[30]_i_1__0\ : label is "soft_lutpair2806";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[31]_i_2\ : label is "soft_lutpair2697";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[3]_i_1__0\ : label is "soft_lutpair2816";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[4]_i_1__0\ : label is "soft_lutpair2815";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[5]_i_1__0\ : label is "soft_lutpair2815";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[6]_i_1__0\ : label is "soft_lutpair2814";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[7]_i_1__0\ : label is "soft_lutpair2814";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[8]_i_1__0\ : label is "soft_lutpair2729";
  attribute SOFT_HLUTNM of \recvAXIS_tdata_sig[9]_i_1__0\ : label is "soft_lutpair2813";
  attribute SOFT_HLUTNM of \recvStrbToStop_i_3__0\ : label is "soft_lutpair2697";
  attribute SOFT_HLUTNM of \resid[0]_i_1__0\ : label is "soft_lutpair2701";
  attribute SOFT_HLUTNM of \resid[1]_i_2__0\ : label is "soft_lutpair2763";
  attribute SOFT_HLUTNM of \retbuf[0][0]_i_2__0\ : label is "soft_lutpair2678";
  attribute SOFT_HLUTNM of \retbuf[1][7]_i_1__0\ : label is "soft_lutpair2681";
  attribute SOFT_HLUTNM of \retbuf[31][0]_i_1__0\ : label is "soft_lutpair2740";
  attribute SOFT_HLUTNM of \retbuf[33][7]_i_1__0\ : label is "soft_lutpair2680";
  attribute SOFT_HLUTNM of \retbuf[38][7]_i_1\ : label is "soft_lutpair2679";
  attribute SOFT_HLUTNM of \retbuf[4][4]_i_1__0\ : label is "soft_lutpair2679";
  attribute SOFT_HLUTNM of \retbuf[5][5]_i_1\ : label is "soft_lutpair2678";
  attribute SOFT_HLUTNM of \retbuf[5][7]_i_1__0\ : label is "soft_lutpair2681";
  attribute SOFT_HLUTNM of \retbuf[8][7]_i_1__0\ : label is "soft_lutpair2680";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[11]_INST_0\ : label is "soft_lutpair2750";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[13]_INST_0\ : label is "soft_lutpair2749";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[15]_INST_0\ : label is "soft_lutpair2749";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[17]_INST_0\ : label is "soft_lutpair2748";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[19]_INST_0\ : label is "soft_lutpair2748";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[1]_INST_0\ : label is "soft_lutpair2752";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[21]_INST_0\ : label is "soft_lutpair2747";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[23]_INST_0\ : label is "soft_lutpair2747";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[25]_INST_0\ : label is "soft_lutpair2746";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[27]_INST_0\ : label is "soft_lutpair2746";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[29]_INST_0\ : label is "soft_lutpair2744";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[31]_INST_0\ : label is "soft_lutpair2743";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[31]_INST_0_i_1\ : label is "soft_lutpair2684";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[3]_INST_0\ : label is "soft_lutpair2752";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[5]_INST_0\ : label is "soft_lutpair2751";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[7]_INST_0\ : label is "soft_lutpair2751";
  attribute SOFT_HLUTNM of \rpuAXIL_rdata[9]_INST_0\ : label is "soft_lutpair2750";
  attribute SOFT_HLUTNM of \rxlen[1]_i_4\ : label is "soft_lutpair2726";
  attribute SOFT_HLUTNM of \sendAXIL_rdata[0]_i_1__0\ : label is "soft_lutpair2687";
  attribute SOFT_HLUTNM of \sendAXIL_rdata[1]_i_1__0\ : label is "soft_lutpair2688";
  attribute SOFT_HLUTNM of \sendAXIL_rdata[2]_i_1__0\ : label is "soft_lutpair2689";
  attribute SOFT_HLUTNM of \sendAXIL_rdata[31]_i_4\ : label is "soft_lutpair2685";
  attribute SOFT_HLUTNM of \sendAXIL_rdata[3]_i_1__0\ : label is "soft_lutpair2690";
  attribute SOFT_HLUTNM of \sendAXIL_rdata[4]_i_1__0\ : label is "soft_lutpair2691";
  attribute SOFT_HLUTNM of \sendAXIL_rdata[5]_i_1__0\ : label is "soft_lutpair2692";
  attribute SOFT_HLUTNM of \sendStrbToStart_i_10__0\ : label is "soft_lutpair2734";
  attribute SOFT_HLUTNM of \sendStrbToStart_i_11__0\ : label is "soft_lutpair2735";
  attribute SOFT_HLUTNM of \sendStrbToStart_i_12__0\ : label is "soft_lutpair2732";
  attribute SOFT_HLUTNM of \sendStrbToStart_i_13__0\ : label is "soft_lutpair2733";
  attribute SOFT_HLUTNM of \sendStrbToStart_i_3__0\ : label is "soft_lutpair2726";
  attribute SOFT_HLUTNM of \sendStrbToStop_i_4__0\ : label is "soft_lutpair2690";
  attribute SOFT_HLUTNM of \stateOp[0]_i_8__0\ : label is "soft_lutpair2725";
  attribute SOFT_HLUTNM of \stateOp[1]_i_10__0\ : label is "soft_lutpair2691";
  attribute SOFT_HLUTNM of \stateOp[1]_i_5__2\ : label is "soft_lutpair2688";
  attribute SOFT_HLUTNM of \stateOp[1]_i_9__1\ : label is "soft_lutpair2689";
  attribute SOFT_HLUTNM of \stateOp[2]_i_3__2\ : label is "soft_lutpair2683";
  attribute SOFT_HLUTNM of \stateOp[3]_i_8\ : label is "soft_lutpair2683";
  attribute SOFT_HLUTNM of \stateOp[4]_i_2__0\ : label is "soft_lutpair2742";
  attribute SOFT_HLUTNM of \stateOp_i_1__3\ : label is "soft_lutpair2671";
  attribute SOFT_HLUTNM of \stateOp_next[0]_i_1\ : label is "soft_lutpair2787";
  attribute SOFT_HLUTNM of \stateOp_next[1]_i_1__0\ : label is "soft_lutpair2670";
  attribute SOFT_HLUTNM of \stateOp_next[2]_i_1\ : label is "soft_lutpair2670";
  attribute SOFT_HLUTNM of \stateOp_next[3]_i_1__0\ : label is "soft_lutpair2741";
  attribute SOFT_HLUTNM of \stateOp_next[4]_i_2__0\ : label is "soft_lutpair2741";
  attribute SOFT_HLUTNM of \stateRecv[2]_i_10__0\ : label is "soft_lutpair2686";
  attribute SOFT_HLUTNM of \stateRecv[2]_i_7__0\ : label is "soft_lutpair2669";
  attribute SOFT_HLUTNM of \stateRecv[2]_i_8__0\ : label is "soft_lutpair2685";
  attribute SOFT_HLUTNM of \stateSend[2]_i_28__0\ : label is "soft_lutpair2729";
  attribute SOFT_HLUTNM of \stateSend[2]_i_29__0\ : label is "soft_lutpair2730";
  attribute SOFT_HLUTNM of \stateSend[2]_i_30__0\ : label is "soft_lutpair2727";
  attribute SOFT_HLUTNM of \stateSend[2]_i_31__0\ : label is "soft_lutpair2728";
  attribute SOFT_HLUTNM of \stateSend[2]_i_32__0\ : label is "soft_lutpair2743";
  attribute SOFT_HLUTNM of \stateSend[2]_i_3__0\ : label is "soft_lutpair2731";
  attribute SOFT_HLUTNM of \stateSend[2]_i_4__0\ : label is "soft_lutpair2687";
  attribute SOFT_HLUTNM of \stateSend[2]_i_5__0\ : label is "soft_lutpair2686";
  attribute SOFT_HLUTNM of \stateSend[2]_i_6__0\ : label is "soft_lutpair2692";
  attribute SOFT_HLUTNM of \stateSend[2]_i_9__0\ : label is "soft_lutpair2669";
  attribute SOFT_HLUTNM of \stateTo[0]_i_1__0\ : label is "soft_lutpair2693";
  attribute SOFT_HLUTNM of \stateTo[1]_i_2__0\ : label is "soft_lutpair2693";
  attribute SOFT_HLUTNM of \stateTo[1]_i_3__0\ : label is "soft_lutpair2684";
  attribute SOFT_HLUTNM of \tixVBuffer[0]_i_1__0\ : label is "soft_lutpair2771";
  attribute SOFT_HLUTNM of \tixVBuffer[1]_i_1__0\ : label is "soft_lutpair2772";
  attribute SOFT_HLUTNM of \tixVBuffer[2]_i_1__0\ : label is "soft_lutpair2772";
  attribute SOFT_HLUTNM of \tixVBuffer[3]_i_1__0\ : label is "soft_lutpair2773";
  attribute SOFT_HLUTNM of \tixVBuffer[4]_i_1__0\ : label is "soft_lutpair2773";
  attribute SOFT_HLUTNM of \tixVBuffer[5]_i_1__0\ : label is "soft_lutpair2774";
  attribute SOFT_HLUTNM of \tixVBuffer[6]_i_1__0\ : label is "soft_lutpair2774";
  attribute SOFT_HLUTNM of \tixVBuffer[7]_i_1\ : label is "soft_lutpair2775";
  attribute SOFT_HLUTNM of \tixVCommand[0]_i_1__0\ : label is "soft_lutpair2791";
  attribute SOFT_HLUTNM of \tixVCommand[1]_i_1__0\ : label is "soft_lutpair2788";
  attribute SOFT_HLUTNM of \tixVCommand[2]_i_1__0\ : label is "soft_lutpair2788";
  attribute SOFT_HLUTNM of \tixVCommand[3]_i_1__0\ : label is "soft_lutpair2789";
  attribute SOFT_HLUTNM of \tixVCommand[4]_i_1__0\ : label is "soft_lutpair2789";
  attribute SOFT_HLUTNM of \tixVCommand[5]_i_1__0\ : label is "soft_lutpair2790";
  attribute SOFT_HLUTNM of \tixVCommand[6]_i_1__0\ : label is "soft_lutpair2790";
  attribute SOFT_HLUTNM of \tixVCommand[7]_i_1__0\ : label is "soft_lutpair2791";
  attribute SOFT_HLUTNM of \tixVController[0]_i_1__0\ : label is "soft_lutpair2783";
  attribute SOFT_HLUTNM of \tixVController[1]_i_1__0\ : label is "soft_lutpair2784";
  attribute SOFT_HLUTNM of \tixVController[2]_i_1__0\ : label is "soft_lutpair2784";
  attribute SOFT_HLUTNM of \tixVController[3]_i_1__0\ : label is "soft_lutpair2785";
  attribute SOFT_HLUTNM of \tixVController[4]_i_1__0\ : label is "soft_lutpair2785";
  attribute SOFT_HLUTNM of \tixVController[5]_i_1__0\ : label is "soft_lutpair2786";
  attribute SOFT_HLUTNM of \tixVController[6]_i_1__0\ : label is "soft_lutpair2786";
  attribute SOFT_HLUTNM of \tixVController[7]_i_2__0\ : label is "soft_lutpair2787";
  attribute SOFT_HLUTNM of \txAXIS_tdata[29]_i_1__0\ : label is "soft_lutpair2703";
  attribute SOFT_HLUTNM of \validCrc_sig_i_2__0\ : label is "soft_lutpair2682";
  attribute SOFT_HLUTNM of \wordcntLast[0]_i_1__0\ : label is "soft_lutpair2720";
  attribute SOFT_HLUTNM of \wordcnt[0]_i_1__1\ : label is "soft_lutpair2762";
  attribute SOFT_HLUTNM of \wordcnt[0]_i_4__0\ : label is "soft_lutpair2677";
  attribute SOFT_HLUTNM of \wordcnt[0]_i_5__0\ : label is "soft_lutpair2731";
  attribute SOFT_HLUTNM of \wordcnt[10]_i_1\ : label is "soft_lutpair2801";
  attribute SOFT_HLUTNM of \wordcnt[11]_i_1\ : label is "soft_lutpair2801";
  attribute SOFT_HLUTNM of \wordcnt[12]_i_1\ : label is "soft_lutpair2800";
  attribute SOFT_HLUTNM of \wordcnt[13]_i_1\ : label is "soft_lutpair2800";
  attribute SOFT_HLUTNM of \wordcnt[14]_i_1\ : label is "soft_lutpair2799";
  attribute SOFT_HLUTNM of \wordcnt[15]_i_1\ : label is "soft_lutpair2799";
  attribute SOFT_HLUTNM of \wordcnt[16]_i_1\ : label is "soft_lutpair2798";
  attribute SOFT_HLUTNM of \wordcnt[17]_i_1\ : label is "soft_lutpair2798";
  attribute SOFT_HLUTNM of \wordcnt[18]_i_1\ : label is "soft_lutpair2797";
  attribute SOFT_HLUTNM of \wordcnt[19]_i_1\ : label is "soft_lutpair2797";
  attribute SOFT_HLUTNM of \wordcnt[20]_i_1\ : label is "soft_lutpair2796";
  attribute SOFT_HLUTNM of \wordcnt[21]_i_1\ : label is "soft_lutpair2796";
  attribute SOFT_HLUTNM of \wordcnt[22]_i_1\ : label is "soft_lutpair2795";
  attribute SOFT_HLUTNM of \wordcnt[23]_i_1\ : label is "soft_lutpair2795";
  attribute SOFT_HLUTNM of \wordcnt[24]_i_1\ : label is "soft_lutpair2794";
  attribute SOFT_HLUTNM of \wordcnt[25]_i_1\ : label is "soft_lutpair2794";
  attribute SOFT_HLUTNM of \wordcnt[26]_i_1\ : label is "soft_lutpair2793";
  attribute SOFT_HLUTNM of \wordcnt[27]_i_1\ : label is "soft_lutpair2793";
  attribute SOFT_HLUTNM of \wordcnt[28]_i_1\ : label is "soft_lutpair2792";
  attribute SOFT_HLUTNM of \wordcnt[29]_i_1\ : label is "soft_lutpair2792";
  attribute SOFT_HLUTNM of \wordcnt[2]_i_1\ : label is "soft_lutpair2805";
  attribute SOFT_HLUTNM of \wordcnt[30]_i_2\ : label is "soft_lutpair2762";
  attribute SOFT_HLUTNM of \wordcnt[3]_i_1\ : label is "soft_lutpair2805";
  attribute SOFT_HLUTNM of \wordcnt[4]_i_1\ : label is "soft_lutpair2804";
  attribute SOFT_HLUTNM of \wordcnt[5]_i_1\ : label is "soft_lutpair2804";
  attribute SOFT_HLUTNM of \wordcnt[6]_i_1\ : label is "soft_lutpair2803";
  attribute SOFT_HLUTNM of \wordcnt[7]_i_1\ : label is "soft_lutpair2803";
  attribute SOFT_HLUTNM of \wordcnt[8]_i_1\ : label is "soft_lutpair2802";
  attribute SOFT_HLUTNM of \wordcnt[9]_i_1\ : label is "soft_lutpair2802";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \wordcnt_reg[0]__0_i_3__0\ : label is 16;
  attribute ADDER_THRESHOLD of \wordcnt_reg[0]_i_3__0\ : label is 16;
  attribute ADDER_THRESHOLD of \wordcnt_reg[16]__0_i_1__0\ : label is 16;
  attribute ADDER_THRESHOLD of \wordcnt_reg[16]_i_1__0\ : label is 16;
  attribute ADDER_THRESHOLD of \wordcnt_reg[24]__0_i_1__0\ : label is 16;
  attribute ADDER_THRESHOLD of \wordcnt_reg[24]_i_1__0\ : label is 16;
  attribute ADDER_THRESHOLD of \wordcnt_reg[8]__0_i_1__0\ : label is 16;
  attribute ADDER_THRESHOLD of \wordcnt_reg[8]_i_1__0\ : label is 16;
begin
  AXIL_arready <= \^axil_arready\;
  AXIL_awready_sig_reg_0 <= \^axil_awready_sig_reg_0\;
  AXIL_bvalid_sig_reg_0 <= \^axil_bvalid_sig_reg_0\;
  AXIL_wready_sig_reg_0 <= \^axil_wready_sig_reg_0\;
  E(0) <= \^e\(0);
  crc_imd017_out <= \^crc_imd017_out\;
  crc_imd032_out <= \^crc_imd032_out\;
  crc_imd059_out <= \^crc_imd059_out\;
  crc_imd060_out <= \^crc_imd060_out\;
  \crc_imd_reg[14]\ <= \^crc_imd_reg[14]\;
  recvAXIS_tdata(8 downto 0) <= \^recvaxis_tdata\(8 downto 0);
  \recvAXIS_tdata_sig_reg[12]_0\ <= \^recvaxis_tdata_sig_reg[12]_0\;
  \recvAXIS_tdata_sig_reg[13]_0\ <= \^recvaxis_tdata_sig_reg[13]_0\;
  \recvAXIS_tdata_sig_reg[21]_0\ <= \^recvaxis_tdata_sig_reg[21]_0\;
  \recvAXIS_tdata_sig_reg[23]_0\ <= \^recvaxis_tdata_sig_reg[23]_0\;
  \recvAXIS_tdata_sig_reg[7]_0\ <= \^recvaxis_tdata_sig_reg[7]_0\;
  recvAXIS_tlast <= \^recvaxis_tlast\;
  recvAXIS_tlast_sig_reg_0 <= \^recvaxis_tlast_sig_reg_0\;
  rpuAXIL_rvalid <= \^rpuaxil_rvalid\;
  rxAXIS_tvalid <= \^rxaxis_tvalid\;
  \stateOp_reg[0]\ <= \^stateop_reg[0]\;
  \stateOp_reg[0]_3\ <= \^stateop_reg[0]_3\;
  \stateOp_reg[1]\ <= \^stateop_reg[1]\;
  \stateOp_reg[1]_5\ <= \^stateop_reg[1]_5\;
  \stateOp_reg[2]_1\ <= \^stateop_reg[2]_1\;
  \stateSend_reg[0]_0\ <= \^statesend_reg[0]_0\;
  \tixVController_reg[0]\(2 downto 0) <= \^tixvcontroller_reg[0]\(2 downto 0);
  \tixVController_reg[0]_0\ <= \^tixvcontroller_reg[0]_0\;
  \tixVController_reg[1]\ <= \^tixvcontroller_reg[1]\;
  \txAXIS_tdata_reg[11]\ <= \^txaxis_tdata_reg[11]\;
  \txAXIS_tdata_reg[11]_0\ <= \^txaxis_tdata_reg[11]_0\;
  \txAXIS_tdata_reg[14]\ <= \^txaxis_tdata_reg[14]\;
  \txAXIS_tdata_reg[30]\(11 downto 0) <= \^txaxis_tdata_reg[30]\(11 downto 0);
\AXIL_araddr_sig_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => AXIL_arready_sig0,
      D => rpuAXIL_araddr(0),
      Q => AXIL_araddr_sig(4),
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_araddr_sig_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => AXIL_arready_sig0,
      D => rpuAXIL_araddr(1),
      Q => AXIL_araddr_sig(5),
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_arready_sig_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^rpuaxil_rvalid\,
      I1 => rpuAXIL_arvalid,
      I2 => \^axil_arready\,
      O => AXIL_arready_sig0
    );
AXIL_arready_sig_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => AXIL_arready_sig0,
      Q => \^axil_arready\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_awaddr_sig[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => rpuAXIL_awvalid,
      I1 => awdone_reg_n_0,
      I2 => \^axil_awready_sig_reg_0\,
      O => AXIL_awready_sig0
    );
\AXIL_awaddr_sig_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => AXIL_awready_sig0,
      D => rpuAXIL_awaddr(0),
      Q => ixBlkWrite(0),
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_awaddr_sig_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => AXIL_awready_sig0,
      D => rpuAXIL_awaddr(1),
      Q => ixBlkWrite(1),
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_awready_sig_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^axil_awready_sig_reg_0\,
      I1 => awdone_reg_n_0,
      I2 => rpuAXIL_awvalid,
      O => \AXIL_awready_sig_i_1__0_n_0\
    );
AXIL_awready_sig_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \AXIL_awready_sig_i_1__0_n_0\,
      Q => \^axil_awready_sig_reg_0\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_bvalid_sig_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"111FFFFFEEE0EEE0"
    )
        port map (
      I0 => \^axil_wready_sig_reg_0\,
      I1 => wdone_reg_n_0,
      I2 => awdone_reg_n_0,
      I3 => \^axil_awready_sig_reg_0\,
      I4 => rpuAXIL_bready,
      I5 => \^axil_bvalid_sig_reg_0\,
      O => \AXIL_bvalid_sig_i_1__0_n_0\
    );
AXIL_bvalid_sig_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \AXIL_bvalid_sig_i_1__0_n_0\,
      Q => \^axil_bvalid_sig_reg_0\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_rvalid_sig_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88F8"
    )
        port map (
      I0 => \^axil_arready\,
      I1 => rpuAXIL_arvalid,
      I2 => \^rpuaxil_rvalid\,
      I3 => rpuAXIL_rready,
      O => \AXIL_rvalid_sig_i_1__0_n_0\
    );
AXIL_rvalid_sig_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \AXIL_rvalid_sig_i_1__0_n_0\,
      Q => \^rpuaxil_rvalid\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig[15]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => rpuAXIL_wstrb(1),
      I1 => wdone_reg_n_0,
      I2 => \^axil_wready_sig_reg_0\,
      I3 => rpuAXIL_wvalid,
      O => \AXIL_wdata_sig[15]_i_1__0_n_0\
    );
\AXIL_wdata_sig[23]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => rpuAXIL_wstrb(2),
      I1 => wdone_reg_n_0,
      I2 => \^axil_wready_sig_reg_0\,
      I3 => rpuAXIL_wvalid,
      O => \AXIL_wdata_sig[23]_i_1__0_n_0\
    );
\AXIL_wdata_sig[31]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => rpuAXIL_wstrb(3),
      I1 => wdone_reg_n_0,
      I2 => \^axil_wready_sig_reg_0\,
      I3 => rpuAXIL_wvalid,
      O => \AXIL_wdata_sig[31]_i_1__0_n_0\
    );
\AXIL_wdata_sig[7]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => rpuAXIL_wstrb(0),
      I1 => wdone_reg_n_0,
      I2 => \^axil_wready_sig_reg_0\,
      I3 => rpuAXIL_wvalid,
      O => \AXIL_wdata_sig[7]_i_1__0_n_0\
    );
\AXIL_wdata_sig_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1__0_n_0\,
      D => rpuAXIL_wdata(0),
      Q => \AXIL_wdata_sig_reg_n_0_[0]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1__0_n_0\,
      D => rpuAXIL_wdata(10),
      Q => \AXIL_wdata_sig_reg_n_0_[10]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1__0_n_0\,
      D => rpuAXIL_wdata(11),
      Q => \AXIL_wdata_sig_reg_n_0_[11]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1__0_n_0\,
      D => rpuAXIL_wdata(12),
      Q => \AXIL_wdata_sig_reg_n_0_[12]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1__0_n_0\,
      D => rpuAXIL_wdata(13),
      Q => \AXIL_wdata_sig_reg_n_0_[13]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1__0_n_0\,
      D => rpuAXIL_wdata(14),
      Q => \AXIL_wdata_sig_reg_n_0_[14]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1__0_n_0\,
      D => rpuAXIL_wdata(15),
      Q => \AXIL_wdata_sig_reg_n_0_[15]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1__0_n_0\,
      D => rpuAXIL_wdata(16),
      Q => \AXIL_wdata_sig_reg_n_0_[16]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1__0_n_0\,
      D => rpuAXIL_wdata(17),
      Q => \AXIL_wdata_sig_reg_n_0_[17]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1__0_n_0\,
      D => rpuAXIL_wdata(18),
      Q => \AXIL_wdata_sig_reg_n_0_[18]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1__0_n_0\,
      D => rpuAXIL_wdata(19),
      Q => \AXIL_wdata_sig_reg_n_0_[19]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1__0_n_0\,
      D => rpuAXIL_wdata(1),
      Q => \AXIL_wdata_sig_reg_n_0_[1]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1__0_n_0\,
      D => rpuAXIL_wdata(20),
      Q => \AXIL_wdata_sig_reg_n_0_[20]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1__0_n_0\,
      D => rpuAXIL_wdata(21),
      Q => \AXIL_wdata_sig_reg_n_0_[21]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1__0_n_0\,
      D => rpuAXIL_wdata(22),
      Q => \AXIL_wdata_sig_reg_n_0_[22]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[23]_i_1__0_n_0\,
      D => rpuAXIL_wdata(23),
      Q => \AXIL_wdata_sig_reg_n_0_[23]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1__0_n_0\,
      D => rpuAXIL_wdata(24),
      Q => \AXIL_wdata_sig_reg_n_0_[24]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1__0_n_0\,
      D => rpuAXIL_wdata(25),
      Q => \AXIL_wdata_sig_reg_n_0_[25]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1__0_n_0\,
      D => rpuAXIL_wdata(26),
      Q => \AXIL_wdata_sig_reg_n_0_[26]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1__0_n_0\,
      D => rpuAXIL_wdata(27),
      Q => \AXIL_wdata_sig_reg_n_0_[27]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1__0_n_0\,
      D => rpuAXIL_wdata(28),
      Q => \AXIL_wdata_sig_reg_n_0_[28]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1__0_n_0\,
      D => rpuAXIL_wdata(29),
      Q => \AXIL_wdata_sig_reg_n_0_[29]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1__0_n_0\,
      D => rpuAXIL_wdata(2),
      Q => p_0_in(0),
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1__0_n_0\,
      D => rpuAXIL_wdata(30),
      Q => \AXIL_wdata_sig_reg_n_0_[30]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[31]_i_1__0_n_0\,
      D => rpuAXIL_wdata(31),
      Q => \AXIL_wdata_sig_reg_n_0_[31]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1__0_n_0\,
      D => rpuAXIL_wdata(3),
      Q => p_0_in(1),
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1__0_n_0\,
      D => rpuAXIL_wdata(4),
      Q => \AXIL_wdata_sig_reg_n_0_[4]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1__0_n_0\,
      D => rpuAXIL_wdata(5),
      Q => \AXIL_wdata_sig_reg_n_0_[5]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1__0_n_0\,
      D => rpuAXIL_wdata(6),
      Q => \AXIL_wdata_sig_reg_n_0_[6]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[7]_i_1__0_n_0\,
      D => rpuAXIL_wdata(7),
      Q => \AXIL_wdata_sig_reg_n_0_[7]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1__0_n_0\,
      D => rpuAXIL_wdata(8),
      Q => \AXIL_wdata_sig_reg_n_0_[8]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wdata_sig_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \AXIL_wdata_sig[15]_i_1__0_n_0\,
      D => rpuAXIL_wdata(9),
      Q => \AXIL_wdata_sig_reg_n_0_[9]\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\AXIL_wready_sig_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => wdone_reg_n_0,
      I1 => \^axil_wready_sig_reg_0\,
      I2 => rpuAXIL_wvalid,
      O => \AXIL_wready_sig_i_1__0_n_0\
    );
AXIL_wready_sig_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \AXIL_wready_sig_i_1__0_n_0\,
      Q => \^axil_wready_sig_reg_0\,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\awdone_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"777F777F777F0000"
    )
        port map (
      I0 => \^axil_bvalid_sig_reg_0\,
      I1 => rpuAXIL_bready,
      I2 => wdone_reg_n_0,
      I3 => \^axil_wready_sig_reg_0\,
      I4 => awdone_reg_n_0,
      I5 => \^axil_awready_sig_reg_0\,
      O => \awdone_i_1__1_n_0\
    );
awdone_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \awdone_i_1__1_n_0\,
      Q => awdone_reg_n_0,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\crcAXIS_tkeep[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[0]\,
      I1 => \^stateop_reg[1]\,
      O => \stateOp_reg[0]_0\(0)
    );
\crcAXIS_tkeep[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF36FFFF"
    )
        port map (
      I0 => Q(2),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \crcAXIS_tkeep_reg[1]\,
      I4 => \^stateop_reg[1]\,
      O => \stateOp_reg[0]_0\(1)
    );
\crcAXIS_tkeep[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BAAA"
    )
        port map (
      I0 => \crcAXIS_tkeep[3]_i_6_n_0\,
      I1 => Q(0),
      I2 => Q(4),
      I3 => \crcAXIS_tkeep_reg[3]\(0),
      O => \stateOp_reg[0]_0\(2)
    );
\crcAXIS_tkeep[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F3F7F3F7F3F7FFF"
    )
        port map (
      I0 => \crcAXIS_tkeep[3]_i_3__0_n_0\,
      I1 => \^stateop_reg[1]\,
      I2 => \crcAXIS_tkeep[3]_i_4_n_0\,
      I3 => Q(3),
      I4 => Q(2),
      I5 => \crcAXIS_tkeep[3]_i_5_n_0\,
      O => \stateOp_reg[3]\(0)
    );
\crcAXIS_tkeep[3]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF40"
    )
        port map (
      I0 => Q(0),
      I1 => Q(4),
      I2 => \crcAXIS_tkeep_reg[3]\(1),
      I3 => \crcAXIS_tkeep[3]_i_6_n_0\,
      O => \stateOp_reg[0]_0\(3)
    );
\crcAXIS_tkeep[3]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF00FEFE"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[0]_0\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => \crcAXIS_tkeep[3]_i_8_n_0\,
      I4 => Q(0),
      I5 => Q(4),
      O => \crcAXIS_tkeep[3]_i_3__0_n_0\
    );
\crcAXIS_tkeep[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F3F3F3FFFBFFFBFB"
    )
        port map (
      I0 => Q(1),
      I1 => Q(2),
      I2 => Q(3),
      I3 => \crcAXIS_tkeep[3]_i_9_n_0\,
      I4 => Q(0),
      I5 => Q(4),
      O => \crcAXIS_tkeep[3]_i_4_n_0\
    );
\crcAXIS_tkeep[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF553FFFFFFF"
    )
        port map (
      I0 => crcAXIS_tlast_sig_reg_4(0),
      I1 => \wordcnt[30]_i_5__0_n_0\,
      I2 => \crcAXIS_tkeep_reg[0]_1\(0),
      I3 => Q(1),
      I4 => Q(0),
      I5 => Q(4),
      O => \crcAXIS_tkeep[3]_i_5_n_0\
    );
\crcAXIS_tkeep[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFA282FFFF"
    )
        port map (
      I0 => Q(0),
      I1 => Q(1),
      I2 => Q(4),
      I3 => \lastAXIS_tkeep_reg[3]_0\,
      I4 => \^stateop_reg[1]\,
      I5 => \crcAXIS_tkeep_reg[3]_0\,
      O => \crcAXIS_tkeep[3]_i_6_n_0\
    );
\crcAXIS_tkeep[3]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFFFFFF"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      I2 => stateSend(0),
      I3 => Q(1),
      I4 => CO(0),
      O => \crcAXIS_tkeep[3]_i_8_n_0\
    );
\crcAXIS_tkeep[3]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000000000000"
    )
        port map (
      I0 => CO(0),
      I1 => stateRecv(2),
      I2 => stateRecv(1),
      I3 => stateRecv(0),
      I4 => \crcAXIS_tkeep_reg[0]_1\(0),
      I5 => Q(1),
      O => \crcAXIS_tkeep[3]_i_9_n_0\
    );
\crcAXIS_tlast_sig_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAFFAEAAAA00A2"
    )
        port map (
      I0 => \crcAXIS_tlast_sig_i_2__0_n_0\,
      I1 => crcAXIS_tlast_sig_reg_1,
      I2 => \crcAXIS_tlast_sig_i_4__0_n_0\,
      I3 => Q(0),
      I4 => \crcAXIS_tlast_sig_i_5__0_n_0\,
      I5 => crcAXIS_tlast_sig_reg_2,
      O => \stateOp_reg[0]_2\
    );
\crcAXIS_tlast_sig_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBFF333"
    )
        port map (
      I0 => CO(0),
      I1 => \^stateop_reg[1]\,
      I2 => crcAXIS_tlast_sig_reg_3,
      I3 => crcAXIS_tlast_sig_reg_4(0),
      I4 => crcAXIS_tlast_sig_reg_5,
      O => \crcAXIS_tlast_sig_i_2__0_n_0\
    );
\crcAXIS_tlast_sig_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000E2220000"
    )
        port map (
      I0 => \crcAXIS_tlast_sig_i_8__0_n_0\,
      I1 => Q(4),
      I2 => CO(0),
      I3 => \^rxaxis_tvalid\,
      I4 => Q(2),
      I5 => crcAXIS_tlast_sig_reg_0,
      O => \crcAXIS_tlast_sig_i_4__0_n_0\
    );
\crcAXIS_tlast_sig_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF04FF"
    )
        port map (
      I0 => \crcAXIS_tlast_sig_i_9__0_n_0\,
      I1 => Q(0),
      I2 => Q(4),
      I3 => \^stateop_reg[1]\,
      I4 => crcAXIS_tlast_sig_reg_6,
      O => \crcAXIS_tlast_sig_i_5__0_n_0\
    );
\crcAXIS_tlast_sig_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \rxlen[1]_i_4_n_0\,
      I1 => \crcAXIS_tlast_sig_i_4__0_0\(4),
      I2 => \crcAXIS_tlast_sig_i_4__0_0\(2),
      I3 => \crcAXIS_tlast_sig_i_4__0_0\(0),
      I4 => \crcAXIS_tlast_sig_i_4__0_0\(1),
      I5 => \crcAXIS_tlast_sig_i_4__0_0\(3),
      O => \crcAXIS_tlast_sig_i_8__0_n_0\
    );
\crcAXIS_tlast_sig_i_9__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0FFFFF2AFFFFFF2A"
    )
        port map (
      I0 => Q(1),
      I1 => CO(0),
      I2 => \^rxaxis_tvalid\,
      I3 => Q(3),
      I4 => Q(2),
      I5 => \stateOp[2]_i_5__2_n_0\,
      O => \crcAXIS_tlast_sig_i_9__0_n_0\
    );
\crc_imd[0]_i_10__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => AXIS_tdata(20),
      I1 => AXIS_tdata(18),
      I2 => AXIS_tdata(17),
      I3 => AXIS_tdata(19),
      O => \crc_imd[0]_i_10__0_n_0\
    );
\crc_imd[0]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \crc_imd_reg[0]\,
      I1 => \^recvaxis_tdata_sig_reg[21]_0\,
      I2 => \crc_imd_reg[0]_0\,
      I3 => \^txaxis_tdata_reg[14]\,
      I4 => \crc_imd[0]_i_7__0_n_0\,
      I5 => \crc_imd[15]_i_17__0_n_0\,
      O => stateOp_reg
    );
\crc_imd[0]_i_7__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^crc_imd_reg[14]\,
      I1 => \crc_imd[0]_i_10__0_n_0\,
      I2 => \^txaxis_tdata_reg[30]\(9),
      I3 => AXIS_tdata(24),
      O => \crc_imd[0]_i_7__0_n_0\
    );
\crc_imd[0]_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^txaxis_tdata_reg[11]\,
      I1 => \^recvaxis_tdata_sig_reg[12]_0\,
      I2 => \crc_imd_reg[2]_2\,
      I3 => \crc_imd_reg[6]\,
      O => \^txaxis_tdata_reg[11]_0\
    );
\crc_imd[10]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A000C000"
    )
        port map (
      I0 => \myCrc/crc_imd058_out\,
      I1 => \myCrc/crc_imd031_out\,
      I2 => \crc_imd_reg[2]_1\,
      I3 => \crc_imd_reg[10]\(0),
      I4 => \crc_imd_reg[10]\(1),
      O => stateOp_reg_1
    );
\crc_imd[10]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(1),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(1),
      O => \^txaxis_tdata_reg[30]\(1)
    );
\crc_imd[10]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(0),
      I2 => stateOp_reg_4,
      I3 => \^recvaxis_tdata\(0),
      O => \^txaxis_tdata_reg[30]\(0)
    );
\crc_imd[10]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => AXIS_tdata(16),
      I1 => \crc_imd_reg[8]\,
      I2 => \pollbuf_reg[4][7]\(8),
      I3 => AXIS_tdata(17),
      I4 => \^txaxis_tdata_reg[30]\(0),
      O => \myCrc/crc_imd058_out\
    );
\crc_imd[11]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3311CC1E005A005A"
    )
        port map (
      I0 => rxAXIS_tdata(2),
      I1 => \sendAXIL_rdata_reg[31]_0\(2),
      I2 => rxAXIS_tdata(1),
      I3 => stateOp_reg_4,
      I4 => \sendAXIL_rdata_reg[31]_0\(1),
      I5 => \crc_imd_reg[11]\,
      O => \recvAXIS_tdata_sig_reg[2]_0\
    );
\crc_imd[11]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \pollbuf_reg[4][7]\(7),
      I1 => AXIS_tdata(18),
      I2 => \^txaxis_tdata_reg[30]\(1),
      I3 => \pollbuf_reg[4][7]\(9),
      I4 => \^txaxis_tdata_reg[30]\(6),
      I5 => AXIS_tdata(17),
      O => \^crc_imd059_out\
    );
\crc_imd[11]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(17),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(17),
      O => AXIS_tdata(17)
    );
\crc_imd[12]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^txaxis_tdata_reg[30]\(2),
      I1 => AXIS_tdata(2),
      I2 => \pollbuf_reg[4][7]\(11),
      I3 => \pollbuf_reg[4][7]\(10),
      O => \^crc_imd017_out\
    );
\crc_imd[12]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(3),
      I2 => stateOp_reg_4,
      I3 => \^recvaxis_tdata\(1),
      O => \^txaxis_tdata_reg[30]\(2)
    );
\crc_imd[12]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(2),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(2),
      O => AXIS_tdata(2)
    );
\crc_imd[12]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \^txaxis_tdata_reg[30]\(0),
      I1 => \pollbuf_reg[4][7]\(8),
      I2 => AXIS_tdata(18),
      I3 => \pollbuf_reg[4][7]\(10),
      I4 => AXIS_tdata(2),
      I5 => AXIS_tdata(19),
      O => \^crc_imd060_out\
    );
\crc_imd[12]_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(18),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(18),
      O => AXIS_tdata(18)
    );
\crc_imd[13]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA0000003C000000"
    )
        port map (
      I0 => \myCrc/crc_imd061_out\,
      I1 => \crc_imd_reg[13]\,
      I2 => \^recvaxis_tdata_sig_reg[12]_0\,
      I3 => \crc_imd_reg[2]_1\,
      I4 => \crc_imd_reg[10]\(0),
      I5 => \crc_imd_reg[10]\(1),
      O => stateOp_reg_2
    );
\crc_imd[13]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => AXIS_tdata(19),
      I1 => \^txaxis_tdata_reg[30]\(1),
      I2 => \pollbuf_reg[4][7]\(9),
      I3 => \pollbuf_reg[4][7]\(11),
      I4 => AXIS_tdata(20),
      I5 => \^txaxis_tdata_reg[30]\(2),
      O => \myCrc/crc_imd061_out\
    );
\crc_imd[13]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0DDDF222"
    )
        port map (
      I0 => rxAXIS_tdata(12),
      I1 => stateOp_reg_4,
      I2 => \sendAXIL_rdata_reg[31]_0\(12),
      I3 => \crc_imd_reg[11]\,
      I4 => \pollbuf_reg[4][7]\(4),
      O => \^recvaxis_tdata_sig_reg[12]_0\
    );
\crc_imd[13]_i_7__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(19),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(19),
      O => AXIS_tdata(19)
    );
\crc_imd[14]_i_10__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(21),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(21),
      O => \^txaxis_tdata_reg[30]\(7)
    );
\crc_imd[14]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FF20"
    )
        port map (
      I0 => \^recvaxis_tlast\,
      I1 => stateOp_reg_4,
      I2 => \^rxaxis_tvalid\,
      I3 => crcAXIS_tlast_sig_reg_2,
      I4 => \crc_imd_reg[2]_1\,
      O => \^recvaxis_tlast_sig_reg_0\
    );
\crc_imd[14]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A000C000"
    )
        port map (
      I0 => \myCrc/crc_imd062_out\,
      I1 => \myCrc/crc_imd035_out\,
      I2 => \crc_imd_reg[2]_1\,
      I3 => \crc_imd_reg[10]\(0),
      I4 => \crc_imd_reg[10]\(1),
      O => stateOp_reg_3
    );
\crc_imd[14]_i_8__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => AXIS_tdata(20),
      I1 => AXIS_tdata(2),
      I2 => \^txaxis_tdata_reg[30]\(7),
      I3 => \pollbuf_reg[4][7]\(10),
      I4 => \crc_imd[6]_i_3__0_0\,
      O => \myCrc/crc_imd062_out\
    );
\crc_imd[14]_i_9__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(20),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(20),
      O => AXIS_tdata(20)
    );
\crc_imd[15]_i_14__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"95AA95956A556A6A"
    )
        port map (
      I0 => \pollbuf_reg[4][7]\(14),
      I1 => \crc_imd_reg[11]\,
      I2 => \sendAXIL_rdata_reg[31]_0\(6),
      I3 => stateOp_reg_4,
      I4 => rxAXIS_tdata(6),
      I5 => \^recvaxis_tdata_sig_reg[7]_0\,
      O => \^crc_imd_reg[14]\
    );
\crc_imd[15]_i_15__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"95AA95956A556A6A"
    )
        port map (
      I0 => \^txaxis_tdata_reg[11]_0\,
      I1 => \crc_imd_reg[11]\,
      I2 => \sendAXIL_rdata_reg[31]_0\(14),
      I3 => stateOp_reg_4,
      I4 => \^recvaxis_tdata\(7),
      I5 => \pollbuf_reg[4][7]\(6),
      O => \^txaxis_tdata_reg[14]\
    );
\crc_imd[15]_i_17__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => AXIS_tdata(31),
      I1 => \^txaxis_tdata_reg[30]\(11),
      I2 => \^txaxis_tdata_reg[30]\(10),
      I3 => \crc_imd[15]_i_26__0_n_0\,
      I4 => \crc_imd[5]_i_4__0_n_0\,
      O => \crc_imd[15]_i_17__0_n_0\
    );
\crc_imd[15]_i_18__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0DDDF222"
    )
        port map (
      I0 => \^recvaxis_tdata\(3),
      I1 => stateOp_reg_4,
      I2 => \sendAXIL_rdata_reg[31]_0\(5),
      I3 => \crc_imd_reg[11]\,
      I4 => \pollbuf_reg[4][7]\(13),
      O => \crc_imd[15]_i_18__0_n_0\
    );
\crc_imd[15]_i_19__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3311CC1E005A005A"
    )
        port map (
      I0 => rxAXIS_tdata(16),
      I1 => \sendAXIL_rdata_reg[31]_0\(16),
      I2 => rxAXIS_tdata(24),
      I3 => stateOp_reg_4,
      I4 => \sendAXIL_rdata_reg[31]_0\(24),
      I5 => \crc_imd_reg[11]\,
      O => \crc_imd[15]_i_19__0_n_0\
    );
\crc_imd[15]_i_23__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \crc_imd[15]_i_27__0_n_0\,
      I1 => rxAXIS_tdata(23),
      I2 => stateOp_reg_4,
      I3 => \sendAXIL_rdata_reg[31]_0\(23),
      I4 => \crc_imd_reg[11]\,
      O => \^recvaxis_tdata_sig_reg[23]_0\
    );
\crc_imd[15]_i_24__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3311CC1E005A005A"
    )
        port map (
      I0 => rxAXIS_tdata(21),
      I1 => \sendAXIL_rdata_reg[31]_0\(21),
      I2 => rxAXIS_tdata(16),
      I3 => stateOp_reg_4,
      I4 => \sendAXIL_rdata_reg[31]_0\(16),
      I5 => \crc_imd_reg[11]\,
      O => \^recvaxis_tdata_sig_reg[21]_0\
    );
\crc_imd[15]_i_25__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(29),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(29),
      O => \^txaxis_tdata_reg[30]\(10)
    );
\crc_imd[15]_i_26__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3311CC1E005A005A"
    )
        port map (
      I0 => rxAXIS_tdata(25),
      I1 => \sendAXIL_rdata_reg[31]_0\(25),
      I2 => rxAXIS_tdata(26),
      I3 => stateOp_reg_4,
      I4 => \sendAXIL_rdata_reg[31]_0\(26),
      I5 => \crc_imd_reg[11]\,
      O => \crc_imd[15]_i_26__0_n_0\
    );
\crc_imd[15]_i_27__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \crc_imd[0]_i_10__0_n_0\,
      I1 => rxAXIS_tdata(22),
      I2 => stateOp_reg_4,
      I3 => \sendAXIL_rdata_reg[31]_0\(22),
      I4 => \crc_imd_reg[11]\,
      O => \crc_imd[15]_i_27__0_n_0\
    );
\crc_imd[15]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => stateRecv(2),
      I1 => stateRecv(1),
      I2 => stateRecv(0),
      O => \^rxaxis_tvalid\
    );
\crc_imd[15]_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[15]_i_17__0_n_0\,
      I1 => \crc_imd[15]_i_18__0_n_0\,
      I2 => \^crc_imd_reg[14]\,
      I3 => \crc_imd[15]_i_19__0_n_0\,
      I4 => \crc_imd_reg[15]_0\,
      I5 => \crc_imd_reg[15]_1\,
      O => \recvAXIS_tdata_sig_reg[5]_0\
    );
\crc_imd[15]_i_9__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[13]_0\,
      I1 => \crc_imd_reg[9]_0\,
      I2 => \^txaxis_tdata_reg[14]\,
      I3 => \^recvaxis_tdata_sig_reg[23]_0\,
      O => \recvAXIS_tdata_sig_reg[13]_1\
    );
\crc_imd[1]_i_11__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \crc_imd[15]_i_27__0_n_0\,
      I1 => \^recvaxis_tdata_sig_reg[21]_0\,
      I2 => \^recvaxis_tdata_sig_reg[7]_0\,
      I3 => \crc_imd[6]_i_3__0_0\,
      O => \crc_imd[1]_i_11__0_n_0\
    );
\crc_imd[1]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28828228"
    )
        port map (
      I0 => \crc_imd_reg[0]\,
      I1 => \crc_imd[1]_i_11__0_n_0\,
      I2 => \crc_imd[15]_i_17__0_n_0\,
      I3 => \^txaxis_tdata_reg[14]\,
      I4 => \crc_imd_reg[0]_0\,
      O => stateOp_reg_0
    );
\crc_imd[1]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[13]_0\,
      I1 => rxAXIS_tdata(21),
      I2 => stateOp_reg_4,
      I3 => \sendAXIL_rdata_reg[31]_0\(21),
      I4 => \crc_imd_reg[11]\,
      O => \recvAXIS_tdata_sig_reg[21]_1\
    );
\crc_imd[1]_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \^txaxis_tdata_reg[14]\,
      I1 => \^recvaxis_tdata_sig_reg[23]_0\,
      I2 => p_10_out(0),
      O => \txAXIS_tdata_reg[14]_0\
    );
\crc_imd[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \^recvaxis_tlast_sig_reg_0\,
      I1 => \crc_imd_reg[2]\,
      I2 => \myCrc/crc_imd031_out\,
      I3 => \crc_imd_reg[2]_0\,
      I4 => crc_imd013_out,
      I5 => \crc_imd[2]_i_3__0_n_0\,
      O => \crc_imd_reg[1]\(0)
    );
\crc_imd[2]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => AXIS_tdata(8),
      I1 => \pollbuf_reg[4][7]\(0),
      I2 => \crc_imd[3]_i_6__0_n_0\,
      I3 => \^txaxis_tdata_reg[30]\(3),
      I4 => \pollbuf_reg[4][7]\(14),
      O => \myCrc/crc_imd031_out\
    );
\crc_imd[2]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF960096009600"
    )
        port map (
      I0 => \crc_imd[2]_i_5__0_n_0\,
      I1 => \^txaxis_tdata_reg[30]\(8),
      I2 => \crc_imd_reg[2]_2\,
      I3 => \crc_imd_reg[0]\,
      I4 => \myCrc/crc_imd058_out\,
      I5 => \crc_imd_reg[2]_3\,
      O => \crc_imd[2]_i_3__0_n_0\
    );
\crc_imd[2]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(8),
      I2 => stateOp_reg_4,
      I3 => \^recvaxis_tdata\(4),
      O => AXIS_tdata(8)
    );
\crc_imd[2]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9666999996669666"
    )
        port map (
      I0 => \crc_imd[2]_i_3__0_0\,
      I1 => AXIS_tdata(24),
      I2 => \crc_imd_reg[11]\,
      I3 => \sendAXIL_rdata_reg[31]_0\(25),
      I4 => stateOp_reg_4,
      I5 => rxAXIS_tdata(25),
      O => \crc_imd[2]_i_5__0_n_0\
    );
\crc_imd[2]_i_6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(22),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(22),
      O => \^txaxis_tdata_reg[30]\(8)
    );
\crc_imd[2]_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(24),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(24),
      O => AXIS_tdata(24)
    );
\crc_imd[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \^recvaxis_tlast_sig_reg_0\,
      I1 => \crc_imd_reg[2]\,
      I2 => \^crc_imd032_out\,
      I3 => \crc_imd_reg[2]_0\,
      I4 => crc_imd015_out,
      I5 => \crc_imd[3]_i_4__0_n_0\,
      O => \crc_imd_reg[1]\(1)
    );
\crc_imd[3]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => AXIS_tdata(7),
      I1 => \pollbuf_reg[4][7]\(15),
      I2 => \crc_imd[3]_i_6__0_n_0\,
      I3 => \crc_imd_reg[6]\,
      O => \^crc_imd032_out\
    );
\crc_imd[3]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF960096009600"
    )
        port map (
      I0 => \crc_imd[3]_i_7__0_n_0\,
      I1 => \^crc_imd_reg[14]\,
      I2 => \crc_imd[3]_i_6__0_n_0\,
      I3 => \crc_imd_reg[0]\,
      I4 => \^crc_imd059_out\,
      I5 => \crc_imd_reg[2]_3\,
      O => \crc_imd[3]_i_4__0_n_0\
    );
\crc_imd[3]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(7),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(7),
      O => AXIS_tdata(7)
    );
\crc_imd[3]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0DDDF222"
    )
        port map (
      I0 => rxAXIS_tdata(9),
      I1 => stateOp_reg_4,
      I2 => \sendAXIL_rdata_reg[31]_0\(9),
      I3 => \crc_imd_reg[11]\,
      I4 => \pollbuf_reg[4][7]\(1),
      O => \crc_imd[3]_i_6__0_n_0\
    );
\crc_imd[3]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"95AA95956A556A6A"
    )
        port map (
      I0 => \crc_imd[15]_i_26__0_n_0\,
      I1 => \crc_imd_reg[11]\,
      I2 => \sendAXIL_rdata_reg[31]_0\(23),
      I3 => stateOp_reg_4,
      I4 => rxAXIS_tdata(23),
      I5 => \crc_imd[15]_i_18__0_n_0\,
      O => \crc_imd[3]_i_7__0_n_0\
    );
\crc_imd[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \^recvaxis_tlast_sig_reg_0\,
      I1 => \crc_imd_reg[2]\,
      I2 => crc_imd033_out,
      I3 => \crc_imd_reg[2]_0\,
      I4 => \^crc_imd017_out\,
      I5 => \crc_imd[4]_i_3__0_n_0\,
      O => \crc_imd_reg[1]\(2)
    );
\crc_imd[4]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF960096009600"
    )
        port map (
      I0 => \crc_imd[4]_i_4__0_n_0\,
      I1 => \^crc_imd_reg[14]\,
      I2 => \crc_imd_reg[4]\,
      I3 => \crc_imd_reg[0]\,
      I4 => \^crc_imd060_out\,
      I5 => \crc_imd_reg[2]_3\,
      O => \crc_imd[4]_i_3__0_n_0\
    );
\crc_imd[4]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3311CC1E005A005A"
    )
        port map (
      I0 => rxAXIS_tdata(26),
      I1 => \sendAXIL_rdata_reg[31]_0\(26),
      I2 => rxAXIS_tdata(27),
      I3 => stateOp_reg_4,
      I4 => \sendAXIL_rdata_reg[31]_0\(27),
      I5 => \crc_imd_reg[11]\,
      O => \crc_imd[4]_i_4__0_n_0\
    );
\crc_imd[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \^recvaxis_tlast_sig_reg_0\,
      I1 => \crc_imd_reg[2]\,
      I2 => \myCrc/crc_imd034_out\,
      I3 => \crc_imd_reg[2]_0\,
      I4 => crc_imd019_out,
      I5 => \crc_imd[5]_i_3__0_n_0\,
      O => \crc_imd_reg[1]\(3)
    );
\crc_imd[5]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8F88707770778F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(11),
      I2 => stateOp_reg_4,
      I3 => \^recvaxis_tdata\(6),
      I4 => \pollbuf_reg[4][7]\(3),
      I5 => \^recvaxis_tdata_sig_reg[12]_0\,
      O => \myCrc/crc_imd034_out\
    );
\crc_imd[5]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF960096009600"
    )
        port map (
      I0 => \^recvaxis_tdata_sig_reg[7]_0\,
      I1 => \crc_imd[5]_i_4__0_n_0\,
      I2 => \^txaxis_tdata_reg[11]\,
      I3 => \crc_imd_reg[0]\,
      I4 => \myCrc/crc_imd061_out\,
      I5 => \crc_imd_reg[2]_3\,
      O => \crc_imd[5]_i_3__0_n_0\
    );
\crc_imd[5]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3311CC1E005A005A"
    )
        port map (
      I0 => rxAXIS_tdata(27),
      I1 => \sendAXIL_rdata_reg[31]_0\(27),
      I2 => rxAXIS_tdata(28),
      I3 => stateOp_reg_4,
      I4 => \sendAXIL_rdata_reg[31]_0\(28),
      I5 => \crc_imd_reg[11]\,
      O => \crc_imd[5]_i_4__0_n_0\
    );
\crc_imd[5]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8F88707770778F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(11),
      I2 => stateOp_reg_4,
      I3 => \^recvaxis_tdata\(6),
      I4 => \pollbuf_reg[4][7]\(3),
      I5 => \crc_imd[3]_i_6__0_n_0\,
      O => \^txaxis_tdata_reg[11]\
    );
\crc_imd[6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \^recvaxis_tlast_sig_reg_0\,
      I1 => \crc_imd_reg[2]\,
      I2 => \myCrc/crc_imd035_out\,
      I3 => \crc_imd_reg[2]_0\,
      I4 => crc_imd020_out,
      I5 => \crc_imd[6]_i_3__0_n_0\,
      O => \crc_imd_reg[1]\(4)
    );
\crc_imd[6]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9666999996669666"
    )
        port map (
      I0 => \pollbuf_reg[4][7]\(5),
      I1 => \^recvaxis_tdata_sig_reg[12]_0\,
      I2 => \crc_imd_reg[11]\,
      I3 => \sendAXIL_rdata_reg[31]_0\(13),
      I4 => stateOp_reg_4,
      I5 => rxAXIS_tdata(13),
      O => \myCrc/crc_imd035_out\
    );
\crc_imd[6]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF960096009600"
    )
        port map (
      I0 => \crc_imd[6]_i_4__0_n_0\,
      I1 => \^recvaxis_tdata_sig_reg[12]_0\,
      I2 => \crc_imd_reg[6]\,
      I3 => \crc_imd_reg[0]\,
      I4 => \myCrc/crc_imd062_out\,
      I5 => \crc_imd_reg[2]_3\,
      O => \crc_imd[6]_i_3__0_n_0\
    );
\crc_imd[6]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3311CC1E005A005A"
    )
        port map (
      I0 => rxAXIS_tdata(29),
      I1 => \sendAXIL_rdata_reg[31]_0\(29),
      I2 => rxAXIS_tdata(28),
      I3 => stateOp_reg_4,
      I4 => \sendAXIL_rdata_reg[31]_0\(28),
      I5 => \crc_imd_reg[11]\,
      O => \crc_imd[6]_i_4__0_n_0\
    );
\crc_imd[7]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0DDDF222"
    )
        port map (
      I0 => rxAXIS_tdata(13),
      I1 => stateOp_reg_4,
      I2 => \sendAXIL_rdata_reg[31]_0\(13),
      I3 => \crc_imd_reg[11]\,
      I4 => \pollbuf_reg[4][7]\(5),
      O => \^recvaxis_tdata_sig_reg[13]_0\
    );
\crc_imd[7]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3311CC1E005A005A"
    )
        port map (
      I0 => rxAXIS_tdata(6),
      I1 => \sendAXIL_rdata_reg[31]_0\(6),
      I2 => \^recvaxis_tdata\(3),
      I3 => stateOp_reg_4,
      I4 => \sendAXIL_rdata_reg[31]_0\(5),
      I5 => \crc_imd_reg[11]\,
      O => p_24_in
    );
\crc_imd[7]_i_9__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(13),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(13),
      O => \^txaxis_tdata_reg[30]\(4)
    );
\crc_imd[8]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"95AA95956A556A6A"
    )
        port map (
      I0 => \^txaxis_tdata_reg[30]\(3),
      I1 => \crc_imd_reg[11]\,
      I2 => \sendAXIL_rdata_reg[31]_0\(7),
      I3 => stateOp_reg_4,
      I4 => rxAXIS_tdata(7),
      I5 => \pollbuf_reg[4][7]\(14),
      O => \txAXIS_tdata_reg[7]\
    );
\crc_imd[8]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF69960000"
    )
        port map (
      I0 => AXIS_tdata(31),
      I1 => \^txaxis_tdata_reg[30]\(11),
      I2 => \^recvaxis_tdata_sig_reg[12]_0\,
      I3 => \crc_imd_reg[8]\,
      I4 => \crc_imd_reg[0]\,
      I5 => \crc_imd_reg[8]_0\,
      O => \txAXIS_tdata_reg[31]\
    );
\crc_imd[8]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(14),
      I2 => stateOp_reg_4,
      I3 => \^recvaxis_tdata\(7),
      O => \^txaxis_tdata_reg[30]\(5)
    );
\crc_imd[8]_i_6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(15),
      I2 => stateOp_reg_4,
      I3 => \^recvaxis_tdata\(8),
      O => \^txaxis_tdata_reg[30]\(6)
    );
\crc_imd[8]_i_7__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(6),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(6),
      O => \^txaxis_tdata_reg[30]\(3)
    );
\crc_imd[8]_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(30),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(30),
      O => \^txaxis_tdata_reg[30]\(11)
    );
\crc_imd[9]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEEFEFEEE"
    )
        port map (
      I0 => \^recvaxis_tlast_sig_reg_0\,
      I1 => \crc_imd_reg[9]\,
      I2 => \crc_imd_reg[2]_0\,
      I3 => \^recvaxis_tdata_sig_reg[7]_0\,
      I4 => \pollbuf_reg[4][7]\(1),
      I5 => \crc_imd[9]_i_4__0_n_0\,
      O => \crc_imd_reg[1]\(5)
    );
\crc_imd[9]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0DDDF222"
    )
        port map (
      I0 => rxAXIS_tdata(7),
      I1 => stateOp_reg_4,
      I2 => \sendAXIL_rdata_reg[31]_0\(7),
      I3 => \crc_imd_reg[11]\,
      I4 => \pollbuf_reg[4][7]\(15),
      O => \^recvaxis_tdata_sig_reg[7]_0\
    );
\crc_imd[9]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF69960000"
    )
        port map (
      I0 => AXIS_tdata(16),
      I1 => \^recvaxis_tdata_sig_reg[13]_0\,
      I2 => AXIS_tdata(31),
      I3 => \crc_imd_reg[9]_0\,
      I4 => \crc_imd_reg[0]\,
      I5 => \crc_imd[9]_i_7__0_n_0\,
      O => \crc_imd[9]_i_4__0_n_0\
    );
\crc_imd[9]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(16),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(16),
      O => AXIS_tdata(16)
    );
\crc_imd[9]_i_6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(31),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(31),
      O => AXIS_tdata(31)
    );
\crc_imd[9]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28828228"
    )
        port map (
      I0 => \crc_imd_reg[2]_3\,
      I1 => \crc_imd_reg[2]_2\,
      I2 => \crc_imd[15]_i_18__0_n_0\,
      I3 => \^recvaxis_tdata_sig_reg[7]_0\,
      I4 => \^txaxis_tdata_reg[30]\(9),
      O => \crc_imd[9]_i_7__0_n_0\
    );
\crc_imd[9]_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => \sendAXIL_rdata_reg[31]_0\(23),
      I2 => stateOp_reg_4,
      I3 => rxAXIS_tdata(23),
      O => \^txaxis_tdata_reg[30]\(9)
    );
\i[0]_i_1__14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => i(0),
      I1 => \i[15]_i_5__0_n_0\,
      O => \i[0]_i_1__14_n_0\
    );
\i[10]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => i(9),
      I1 => \i[12]_i_2__0_n_0\,
      I2 => i(10),
      I3 => \i[15]_i_5__0_n_0\,
      O => \i[10]_i_1__3_n_0\
    );
\i[11]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"14444444"
    )
        port map (
      I0 => \i[15]_i_5__0_n_0\,
      I1 => i(11),
      I2 => i(10),
      I3 => i(9),
      I4 => \i[12]_i_2__0_n_0\,
      O => \i[11]_i_1__2_n_0\
    );
\i[12]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => i(11),
      I1 => i(10),
      I2 => i(9),
      I3 => \i[12]_i_2__0_n_0\,
      I4 => i(12),
      I5 => \i[15]_i_5__0_n_0\,
      O => \i[12]_i_1__2_n_0\
    );
\i[12]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => i(8),
      I1 => i(7),
      I2 => \i[9]_i_2__4_n_0\,
      I3 => i(6),
      O => \i[12]_i_2__0_n_0\
    );
\i[13]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1444"
    )
        port map (
      I0 => \i[15]_i_5__0_n_0\,
      I1 => i(13),
      I2 => \i[13]_i_2__2_n_0\,
      I3 => i(12),
      O => \i[13]_i_1__2_n_0\
    );
\i[13]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => i(11),
      I1 => i(10),
      I2 => i(9),
      I3 => \i[12]_i_2__0_n_0\,
      O => \i[13]_i_2__2_n_0\
    );
\i[14]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \i[15]_i_4__0_n_0\,
      I1 => i(14),
      I2 => \i[15]_i_5__0_n_0\,
      O => \i[14]_i_1__0_n_0\
    );
\i[15]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F0F1FFFFFFFFFF"
    )
        port map (
      I0 => sendStrbToStop_reg_n_0,
      I1 => recvStrbToStop_reg_n_0,
      I2 => \i[15]_i_3__0_n_0\,
      I3 => stateTo(1),
      I4 => stateTo(0),
      I5 => req,
      O => \i[15]_i_1__0_n_0\
    );
\i[15]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => i(14),
      I1 => \i[15]_i_4__0_n_0\,
      I2 => i(15),
      I3 => \i[15]_i_5__0_n_0\,
      O => \i[15]_i_2__0_n_0\
    );
\i[15]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => recvStrbToStart_reg_n_0,
      I1 => sendStrbToStart_reg_n_0,
      O => \i[15]_i_3__0_n_0\
    );
\i[15]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => i(13),
      I1 => i(11),
      I2 => i(10),
      I3 => i(9),
      I4 => \i[12]_i_2__0_n_0\,
      I5 => i(12),
      O => \i[15]_i_4__0_n_0\
    );
\i[15]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => sendStrbToStart_reg_n_0,
      I1 => recvStrbToStart_reg_n_0,
      I2 => stateTo(1),
      I3 => req,
      O => \i[15]_i_5__0_n_0\
    );
\i[1]_i_1__13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => i(1),
      I1 => i(0),
      I2 => \i[15]_i_5__0_n_0\,
      O => \i[1]_i_1__13_n_0\
    );
\i[2]_i_1__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => i(1),
      I1 => i(0),
      I2 => i(2),
      I3 => \i[15]_i_5__0_n_0\,
      O => \i[2]_i_1__9_n_0\
    );
\i[3]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => i(2),
      I1 => i(0),
      I2 => i(1),
      I3 => i(3),
      I4 => \i[15]_i_5__0_n_0\,
      O => \i[3]_i_1__9_n_0\
    );
\i[4]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => i(3),
      I1 => i(1),
      I2 => i(0),
      I3 => i(2),
      I4 => i(4),
      I5 => \i[15]_i_5__0_n_0\,
      O => \i[4]_i_1__9_n_0\
    );
\i[5]_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"09"
    )
        port map (
      I0 => \i[5]_i_2__5_n_0\,
      I1 => i(5),
      I2 => \i[15]_i_5__0_n_0\,
      O => \i[5]_i_1__8_n_0\
    );
\i[5]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => i(3),
      I1 => i(1),
      I2 => i(0),
      I3 => i(2),
      I4 => i(4),
      O => \i[5]_i_2__5_n_0\
    );
\i[6]_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"09"
    )
        port map (
      I0 => \i[9]_i_2__4_n_0\,
      I1 => i(6),
      I2 => \i[15]_i_5__0_n_0\,
      O => \i[6]_i_1__7_n_0\
    );
\i[7]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00D2"
    )
        port map (
      I0 => i(6),
      I1 => \i[9]_i_2__4_n_0\,
      I2 => i(7),
      I3 => \i[15]_i_5__0_n_0\,
      O => \i[7]_i_1__7_n_0\
    );
\i[8]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44144444"
    )
        port map (
      I0 => \i[15]_i_5__0_n_0\,
      I1 => i(8),
      I2 => i(7),
      I3 => \i[9]_i_2__4_n_0\,
      I4 => i(6),
      O => \i[8]_i_1__6_n_0\
    );
\i[9]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F7FF0800"
    )
        port map (
      I0 => i(8),
      I1 => i(7),
      I2 => \i[9]_i_2__4_n_0\,
      I3 => i(6),
      I4 => i(9),
      I5 => \i[15]_i_5__0_n_0\,
      O => \i[9]_i_1__4_n_0\
    );
\i[9]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => i(4),
      I1 => i(2),
      I2 => i(0),
      I3 => i(1),
      I4 => i(3),
      I5 => i(5),
      O => \i[9]_i_2__4_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[0]_i_1__14_n_0\,
      Q => i(0)
    );
\i_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[10]_i_1__3_n_0\,
      Q => i(10)
    );
\i_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[11]_i_1__2_n_0\,
      Q => i(11)
    );
\i_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[12]_i_1__2_n_0\,
      Q => i(12)
    );
\i_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[13]_i_1__2_n_0\,
      Q => i(13)
    );
\i_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[14]_i_1__0_n_0\,
      Q => i(14)
    );
\i_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[15]_i_2__0_n_0\,
      Q => i(15)
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[1]_i_1__13_n_0\,
      Q => i(1)
    );
\i_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[2]_i_1__9_n_0\,
      Q => i(2)
    );
\i_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[3]_i_1__9_n_0\,
      Q => i(3)
    );
\i_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[4]_i_1__9_n_0\,
      Q => i(4)
    );
\i_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[5]_i_1__8_n_0\,
      Q => i(5)
    );
\i_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[6]_i_1__7_n_0\,
      Q => i(6)
    );
\i_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[7]_i_1__7_n_0\,
      Q => i(7)
    );
\i_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[8]_i_1__6_n_0\,
      Q => i(8)
    );
\i_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[15]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \i[9]_i_1__4_n_0\,
      Q => i(9)
    );
\ixRetbufCrc[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \lastAXIS_tkeep_reg[3]\,
      I1 => \^stateop_reg[1]\,
      O => \^tixvcontroller_reg[0]\(0)
    );
\ixRetbufCrc[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => \lastAXIS_tkeep_reg[3]\,
      I1 => lenRet1,
      I2 => \^stateop_reg[1]\,
      O => \^tixvcontroller_reg[0]\(1)
    );
\ixRetbufCrc[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000080FFFFFFFF"
    )
        port map (
      I0 => Q(2),
      I1 => Q(1),
      I2 => Q(3),
      I3 => Q(0),
      I4 => Q(4),
      I5 => \^stateop_reg[1]\,
      O => \^e\(0)
    );
\ixRetbufCrc[5]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => lenRet1,
      I1 => \^stateop_reg[1]\,
      O => \^tixvcontroller_reg[0]\(2)
    );
\lastAXIS_tkeep[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \lastAXIS_tkeep_reg[3]_0\,
      I1 => \^e\(0),
      O => \tixVCommand_reg[1]\(0)
    );
\lastAXIS_tkeep[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2EFF"
    )
        port map (
      I0 => \lastAXIS_tkeep_reg[3]_0\,
      I1 => \lastAXIS_tkeep_reg[3]_1\,
      I2 => \lastAXIS_tkeep_reg[3]\,
      I3 => \^stateop_reg[1]\,
      O => \tixVCommand_reg[1]\(1)
    );
\len[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(0),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(0)
    );
\len[10]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(2),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(10)
    );
\len[11]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(3),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(11)
    );
\len[12]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(4),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(12)
    );
\len[13]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(5),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(13)
    );
\len[14]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(6),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(14)
    );
\len[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(7),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(15)
    );
\len[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(1),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(1)
    );
\len[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(2),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(2)
    );
\len[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(3),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(3)
    );
\len[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(4),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(4)
    );
\len[5]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(5),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(5)
    );
\len[6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(6),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(6)
    );
\len[7]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[7]\(7),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(7)
    );
\len[8]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(0),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(8)
    );
\len[9]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \len_reg[15]\(1),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[5][7]\(9)
    );
\opbuf[0][0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \^recvaxis_tdata\(0),
      O => D(0)
    );
\opbuf[0][1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(1),
      O => D(1)
    );
\opbuf[0][2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(2),
      O => D(2)
    );
\opbuf[0][3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \^recvaxis_tdata\(1),
      O => D(3)
    );
\opbuf[0][4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \^recvaxis_tdata\(2),
      O => D(4)
    );
\opbuf[0][5]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \^recvaxis_tdata\(3),
      O => D(5)
    );
\opbuf[0][6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(6),
      O => D(6)
    );
\opbuf[0][7]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(7),
      O => D(7)
    );
\opbuf[1][0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \^recvaxis_tdata\(4),
      I2 => \opbuf_reg[1][0]\,
      I3 => \^recvaxis_tdata\(0),
      O => \recvAXIS_tdata_sig_reg[15]_1\(0)
    );
\opbuf[1][1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(9),
      I2 => \opbuf_reg[1][0]\,
      I3 => rxAXIS_tdata(1),
      O => \recvAXIS_tdata_sig_reg[15]_1\(1)
    );
\opbuf[1][2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \^recvaxis_tdata\(5),
      I2 => \opbuf_reg[1][0]\,
      I3 => rxAXIS_tdata(2),
      O => \recvAXIS_tdata_sig_reg[15]_1\(2)
    );
\opbuf[1][3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \^recvaxis_tdata\(6),
      I2 => \opbuf_reg[1][0]\,
      I3 => \^recvaxis_tdata\(1),
      O => \recvAXIS_tdata_sig_reg[15]_1\(3)
    );
\opbuf[1][4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(12),
      I2 => \opbuf_reg[1][0]\,
      I3 => \^recvaxis_tdata\(2),
      O => \recvAXIS_tdata_sig_reg[15]_1\(4)
    );
\opbuf[1][5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(13),
      I2 => \opbuf_reg[1][0]\,
      I3 => \^recvaxis_tdata\(3),
      O => \recvAXIS_tdata_sig_reg[15]_1\(5)
    );
\opbuf[1][6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \^recvaxis_tdata\(7),
      I2 => \opbuf_reg[1][0]\,
      I3 => rxAXIS_tdata(6),
      O => \recvAXIS_tdata_sig_reg[15]_1\(6)
    );
\opbuf[1][7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20000000FFFFFFFF"
    )
        port map (
      I0 => Q(0),
      I1 => \opbuf_reg[1][0]\,
      I2 => \^rxaxis_tvalid\,
      I3 => Q(1),
      I4 => \opbuf_reg[1][0]_0\,
      I5 => \^stateop_reg[1]\,
      O => \stateOp_reg[0]_1\(0)
    );
\opbuf[1][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \^recvaxis_tdata\(8),
      I2 => \opbuf_reg[1][0]\,
      I3 => rxAXIS_tdata(7),
      O => \recvAXIS_tdata_sig_reg[15]_1\(7)
    );
\opbuf[2][0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(16),
      I2 => \opbuf_reg[1][0]\,
      I3 => \^recvaxis_tdata\(0),
      O => \recvAXIS_tdata_sig_reg[23]_2\(0)
    );
\opbuf[2][1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(17),
      I2 => \opbuf_reg[1][0]\,
      I3 => rxAXIS_tdata(1),
      O => \recvAXIS_tdata_sig_reg[23]_2\(1)
    );
\opbuf[2][2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(18),
      I2 => \opbuf_reg[1][0]\,
      I3 => rxAXIS_tdata(2),
      O => \recvAXIS_tdata_sig_reg[23]_2\(2)
    );
\opbuf[2][3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(19),
      I2 => \opbuf_reg[1][0]\,
      I3 => \^recvaxis_tdata\(1),
      O => \recvAXIS_tdata_sig_reg[23]_2\(3)
    );
\opbuf[2][4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(20),
      I2 => \opbuf_reg[1][0]\,
      I3 => \^recvaxis_tdata\(2),
      O => \recvAXIS_tdata_sig_reg[23]_2\(4)
    );
\opbuf[2][5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(21),
      I2 => \opbuf_reg[1][0]\,
      I3 => \^recvaxis_tdata\(3),
      O => \recvAXIS_tdata_sig_reg[23]_2\(5)
    );
\opbuf[2][6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(22),
      I2 => \opbuf_reg[1][0]\,
      I3 => rxAXIS_tdata(6),
      O => \recvAXIS_tdata_sig_reg[23]_2\(6)
    );
\opbuf[2][7]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(23),
      I2 => \opbuf_reg[1][0]\,
      I3 => rxAXIS_tdata(7),
      O => \recvAXIS_tdata_sig_reg[23]_2\(7)
    );
\opbuf[5][0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \^recvaxis_tdata\(4),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => \^recvaxis_tdata\(0),
      O => \recvAXIS_tdata_sig_reg[15]_0\(0)
    );
\opbuf[5][1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(9),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => rxAXIS_tdata(1),
      O => \recvAXIS_tdata_sig_reg[15]_0\(1)
    );
\opbuf[5][2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \^recvaxis_tdata\(5),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => rxAXIS_tdata(2),
      O => \recvAXIS_tdata_sig_reg[15]_0\(2)
    );
\opbuf[5][3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \^recvaxis_tdata\(6),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => \^recvaxis_tdata\(1),
      O => \recvAXIS_tdata_sig_reg[15]_0\(3)
    );
\opbuf[5][4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(12),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => \^recvaxis_tdata\(2),
      O => \recvAXIS_tdata_sig_reg[15]_0\(4)
    );
\opbuf[5][5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(13),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => \^recvaxis_tdata\(3),
      O => \recvAXIS_tdata_sig_reg[15]_0\(5)
    );
\opbuf[5][6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \^recvaxis_tdata\(7),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => rxAXIS_tdata(6),
      O => \recvAXIS_tdata_sig_reg[15]_0\(6)
    );
\opbuf[5][7]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \^recvaxis_tdata\(8),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => rxAXIS_tdata(7),
      O => \recvAXIS_tdata_sig_reg[15]_0\(7)
    );
\opbuf[6][0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(16),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => \^recvaxis_tdata\(0),
      O => \recvAXIS_tdata_sig_reg[23]_1\(0)
    );
\opbuf[6][1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(17),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => rxAXIS_tdata(1),
      O => \recvAXIS_tdata_sig_reg[23]_1\(1)
    );
\opbuf[6][2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(18),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => rxAXIS_tdata(2),
      O => \recvAXIS_tdata_sig_reg[23]_1\(2)
    );
\opbuf[6][3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(19),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => \^recvaxis_tdata\(1),
      O => \recvAXIS_tdata_sig_reg[23]_1\(3)
    );
\opbuf[6][4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(20),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => \^recvaxis_tdata\(2),
      O => \recvAXIS_tdata_sig_reg[23]_1\(4)
    );
\opbuf[6][5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(21),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => \^recvaxis_tdata\(3),
      O => \recvAXIS_tdata_sig_reg[23]_1\(5)
    );
\opbuf[6][6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(22),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => rxAXIS_tdata(6),
      O => \recvAXIS_tdata_sig_reg[23]_1\(6)
    );
\opbuf[6][7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000200FFFFFFFF"
    )
        port map (
      I0 => \^rxaxis_tvalid\,
      I1 => \opbuf_reg[6][0]\,
      I2 => Q(2),
      I3 => Q(0),
      I4 => \opbuf_reg[6][0]_0\,
      I5 => \^stateop_reg[1]\,
      O => \stateOp_reg[2]_0\(0)
    );
\opbuf[6][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => rxAXIS_tdata(23),
      I2 => \opbuf_reg[6][0]_0\,
      I3 => rxAXIS_tdata(7),
      O => \recvAXIS_tdata_sig_reg[23]_1\(7)
    );
\pollbuf[0][0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[0][7]\(0),
      O => \tixVController_reg[7]\(0)
    );
\pollbuf[0][1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\(1),
      I1 => \^stateop_reg[1]\,
      O => \tixVController_reg[7]\(1)
    );
\pollbuf[0][2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\(2),
      I1 => \^stateop_reg[1]\,
      O => \tixVController_reg[7]\(2)
    );
\pollbuf[0][3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\(3),
      I1 => \^stateop_reg[1]\,
      O => \tixVController_reg[7]\(3)
    );
\pollbuf[0][4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\(4),
      I1 => \^stateop_reg[1]\,
      O => \tixVController_reg[7]\(4)
    );
\pollbuf[0][5]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\(5),
      I1 => \^stateop_reg[1]\,
      O => \tixVController_reg[7]\(5)
    );
\pollbuf[0][6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\(6),
      I1 => \^stateop_reg[1]\,
      O => \tixVController_reg[7]\(6)
    );
\pollbuf[0][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10000000FFFFFFFF"
    )
        port map (
      I0 => Q(3),
      I1 => Q(4),
      I2 => Q(2),
      I3 => Q(0),
      I4 => Q(1),
      I5 => \^stateop_reg[1]\,
      O => \stateOp_reg[3]_1\(0)
    );
\pollbuf[0][7]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[0][7]\(7),
      I1 => \^stateop_reg[1]\,
      O => \tixVController_reg[7]\(7)
    );
\pollbuf[1][0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[1][7]\(0),
      I1 => \^stateop_reg[1]\,
      O => \tixVCommand_reg[7]\(0)
    );
\pollbuf[1][1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[1][7]\(1),
      I1 => \^stateop_reg[1]\,
      O => \tixVCommand_reg[7]\(1)
    );
\pollbuf[1][2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[1][7]\(2),
      I1 => \^stateop_reg[1]\,
      O => \tixVCommand_reg[7]\(2)
    );
\pollbuf[1][3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[1][7]\(3),
      I1 => \^stateop_reg[1]\,
      O => \tixVCommand_reg[7]\(3)
    );
\pollbuf[1][4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[1][7]\(4),
      I1 => \^stateop_reg[1]\,
      O => \tixVCommand_reg[7]\(4)
    );
\pollbuf[1][5]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[1][7]\(5),
      I1 => \^stateop_reg[1]\,
      O => \tixVCommand_reg[7]\(5)
    );
\pollbuf[1][6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[1][7]\(6),
      I1 => \^stateop_reg[1]\,
      O => \tixVCommand_reg[7]\(6)
    );
\pollbuf[1][7]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pollbuf_reg[1][7]\(7),
      I1 => \^stateop_reg[1]\,
      O => \tixVCommand_reg[7]\(7)
    );
\pollbuf[4][0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(8),
      O => \crc_imd_reg[15]\(0)
    );
\pollbuf[4][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(9),
      O => \crc_imd_reg[15]\(1)
    );
\pollbuf[4][2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(10),
      O => \crc_imd_reg[15]\(2)
    );
\pollbuf[4][3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(11),
      O => \crc_imd_reg[15]\(3)
    );
\pollbuf[4][4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(12),
      O => \crc_imd_reg[15]\(4)
    );
\pollbuf[4][5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(13),
      O => \crc_imd_reg[15]\(5)
    );
\pollbuf[4][6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(14),
      O => \crc_imd_reg[15]\(6)
    );
\pollbuf[4][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000008FFFFFFFF"
    )
        port map (
      I0 => Q(3),
      I1 => Q(1),
      I2 => Q(4),
      I3 => Q(0),
      I4 => Q(2),
      I5 => \^stateop_reg[1]\,
      O => \stateOp_reg[3]_0\(0)
    );
\pollbuf[4][7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(15),
      O => \crc_imd_reg[15]\(7)
    );
\pollbuf[5][0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(0),
      O => \crc_imd_reg[7]\(0)
    );
\pollbuf[5][1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(1),
      O => \crc_imd_reg[7]\(1)
    );
\pollbuf[5][2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(2),
      O => \crc_imd_reg[7]\(2)
    );
\pollbuf[5][3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(3),
      O => \crc_imd_reg[7]\(3)
    );
\pollbuf[5][4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(4),
      O => \crc_imd_reg[7]\(4)
    );
\pollbuf[5][5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(5),
      O => \crc_imd_reg[7]\(5)
    );
\pollbuf[5][6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(6),
      O => \crc_imd_reg[7]\(6)
    );
\pollbuf[5][7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \pollbuf_reg[4][7]\(7),
      O => \crc_imd_reg[7]\(7)
    );
\recvAXIL_rdata[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => \recvAXIL_rdata[31]_i_2_n_0\,
      I1 => p_1_in0,
      I2 => \recvAXIL_rdata_reg_n_0_[31]\,
      O => \recvAXIL_rdata[31]_i_1_n_0\
    );
\recvAXIL_rdata[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400000000"
    )
        port map (
      I0 => AXIL_araddr_sig(4),
      I1 => strbRead,
      I2 => stateRecv(0),
      I3 => AXIL_araddr_sig(5),
      I4 => stateRecv(2),
      I5 => stateRecv(1),
      O => \recvAXIL_rdata[31]_i_2_n_0\
    );
\recvAXIL_rdata_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIL_rdata[31]_i_1_n_0\,
      Q => \recvAXIL_rdata_reg_n_0_[31]\
    );
\recvAXIS_tdata_sig[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[0]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[0]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[10]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[10]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[10]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[11]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[11]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[11]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[12]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[12]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[12]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[13]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[13]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[13]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[14]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[14]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[14]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[15]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[15]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[15]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[16]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[16]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[16]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[17]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[17]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[17]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[18]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[18]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[18]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[19]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[19]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[19]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[1]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[1]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[20]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[20]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[20]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[21]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[21]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[21]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[22]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[22]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[22]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[23]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[23]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[23]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[24]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[24]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[24]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[25]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[25]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[25]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[26]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[26]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[26]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[27]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[27]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[27]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[28]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[28]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[28]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[29]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[29]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[29]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in(0),
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[2]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[30]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[30]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[30]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[31]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D5"
    )
        port map (
      I0 => p_1_in0,
      I1 => \stateRecv[2]_i_4__0_n_0\,
      I2 => stateRecv(0),
      O => \recvAXIS_tdata_sig[31]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[31]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[31]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[31]_i_2_n_0\
    );
\recvAXIS_tdata_sig[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in(1),
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[3]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[4]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[4]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[5]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[5]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[5]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[6]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[6]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[7]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[7]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[7]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[8]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[8]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[8]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig[9]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[9]\,
      I1 => p_1_in0,
      O => \recvAXIS_tdata_sig[9]_i_1__0_n_0\
    );
\recvAXIS_tdata_sig_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[0]_i_1__0_n_0\,
      Q => \^recvaxis_tdata\(0)
    );
\recvAXIS_tdata_sig_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[10]_i_1__0_n_0\,
      Q => \^recvaxis_tdata\(5)
    );
\recvAXIS_tdata_sig_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[11]_i_1__0_n_0\,
      Q => \^recvaxis_tdata\(6)
    );
\recvAXIS_tdata_sig_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[12]_i_1__0_n_0\,
      Q => rxAXIS_tdata(12)
    );
\recvAXIS_tdata_sig_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[13]_i_1__0_n_0\,
      Q => rxAXIS_tdata(13)
    );
\recvAXIS_tdata_sig_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[14]_i_1__0_n_0\,
      Q => \^recvaxis_tdata\(7)
    );
\recvAXIS_tdata_sig_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[15]_i_1__0_n_0\,
      Q => \^recvaxis_tdata\(8)
    );
\recvAXIS_tdata_sig_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[16]_i_1__0_n_0\,
      Q => rxAXIS_tdata(16)
    );
\recvAXIS_tdata_sig_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[17]_i_1__0_n_0\,
      Q => rxAXIS_tdata(17)
    );
\recvAXIS_tdata_sig_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[18]_i_1__0_n_0\,
      Q => rxAXIS_tdata(18)
    );
\recvAXIS_tdata_sig_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[19]_i_1__0_n_0\,
      Q => rxAXIS_tdata(19)
    );
\recvAXIS_tdata_sig_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[1]_i_1__0_n_0\,
      Q => rxAXIS_tdata(1)
    );
\recvAXIS_tdata_sig_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[20]_i_1__0_n_0\,
      Q => rxAXIS_tdata(20)
    );
\recvAXIS_tdata_sig_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[21]_i_1__0_n_0\,
      Q => rxAXIS_tdata(21)
    );
\recvAXIS_tdata_sig_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[22]_i_1__0_n_0\,
      Q => rxAXIS_tdata(22)
    );
\recvAXIS_tdata_sig_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[23]_i_1__0_n_0\,
      Q => rxAXIS_tdata(23)
    );
\recvAXIS_tdata_sig_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[24]_i_1__0_n_0\,
      Q => rxAXIS_tdata(24)
    );
\recvAXIS_tdata_sig_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[25]_i_1__0_n_0\,
      Q => rxAXIS_tdata(25)
    );
\recvAXIS_tdata_sig_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[26]_i_1__0_n_0\,
      Q => rxAXIS_tdata(26)
    );
\recvAXIS_tdata_sig_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[27]_i_1__0_n_0\,
      Q => rxAXIS_tdata(27)
    );
\recvAXIS_tdata_sig_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[28]_i_1__0_n_0\,
      Q => rxAXIS_tdata(28)
    );
\recvAXIS_tdata_sig_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[29]_i_1__0_n_0\,
      Q => rxAXIS_tdata(29)
    );
\recvAXIS_tdata_sig_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[2]_i_1__0_n_0\,
      Q => rxAXIS_tdata(2)
    );
\recvAXIS_tdata_sig_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[30]_i_1__0_n_0\,
      Q => rxAXIS_tdata(30)
    );
\recvAXIS_tdata_sig_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[31]_i_2_n_0\,
      Q => rxAXIS_tdata(31)
    );
\recvAXIS_tdata_sig_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[3]_i_1__0_n_0\,
      Q => \^recvaxis_tdata\(1)
    );
\recvAXIS_tdata_sig_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[4]_i_1__0_n_0\,
      Q => \^recvaxis_tdata\(2)
    );
\recvAXIS_tdata_sig_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[5]_i_1__0_n_0\,
      Q => \^recvaxis_tdata\(3)
    );
\recvAXIS_tdata_sig_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[6]_i_1__0_n_0\,
      Q => rxAXIS_tdata(6)
    );
\recvAXIS_tdata_sig_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[7]_i_1__0_n_0\,
      Q => rxAXIS_tdata(7)
    );
\recvAXIS_tdata_sig_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[8]_i_1__0_n_0\,
      Q => \^recvaxis_tdata\(4)
    );
\recvAXIS_tdata_sig_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recvAXIS_tdata_sig[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tdata_sig[9]_i_1__0_n_0\,
      Q => rxAXIS_tdata(9)
    );
\recvAXIS_tlast_sig_i_10__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \wordcnt_reg[13]__0_n_0\,
      I1 => \wordcnt_reg[14]__0_n_0\,
      I2 => \wordcnt_reg[12]__0_n_0\,
      O => \recvAXIS_tlast_sig_i_10__0_n_0\
    );
\recvAXIS_tlast_sig_i_11__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \wordcnt_reg[10]__0_n_0\,
      I1 => \wordcnt_reg[11]__0_n_0\,
      I2 => \wordcnt_reg[9]__0_n_0\,
      O => \recvAXIS_tlast_sig_i_11__0_n_0\
    );
\recvAXIS_tlast_sig_i_12__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \wordcnt_reg[7]__0_n_0\,
      I1 => \wordcnt_reg[8]__0_n_0\,
      I2 => \wordcnt_reg[6]__0_n_0\,
      O => \recvAXIS_tlast_sig_i_12__0_n_0\
    );
\recvAXIS_tlast_sig_i_13__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00101101"
    )
        port map (
      I0 => \wordcnt_reg[4]__0_n_0\,
      I1 => \wordcnt_reg[5]__0_n_0\,
      I2 => \recvAXIS_tlast_sig_reg_i_3__0_0\(2),
      I3 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I4 => \wordcnt_reg[3]__0_n_0\,
      O => \recvAXIS_tlast_sig_i_13__0_n_0\
    );
\recvAXIS_tlast_sig_i_14__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000002D00002D"
    )
        port map (
      I0 => \recvAXIS_tlast_sig_reg_i_3__0_0\(0),
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => \wordcnt_reg[0]__0_n_0\,
      I3 => \wordcnt_reg[1]__0_n_0\,
      I4 => len(1),
      I5 => \wordcnt_reg[2]__0_n_0\,
      O => \recvAXIS_tlast_sig_i_14__0_n_0\
    );
\recvAXIS_tlast_sig_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => p_1_in0,
      I1 => \stateRecv[2]_i_4__0_n_0\,
      I2 => stateRecv(0),
      I3 => recvAXIS_tlast_sig0,
      I4 => \^recvaxis_tlast\,
      O => \recvAXIS_tlast_sig_i_1__0_n_0\
    );
\recvAXIS_tlast_sig_i_4__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wordcnt_reg[30]__0_n_0\,
      O => \recvAXIS_tlast_sig_i_4__0_n_0\
    );
\recvAXIS_tlast_sig_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \wordcnt_reg[28]__0_n_0\,
      I1 => \wordcnt_reg[29]__0_n_0\,
      I2 => \wordcnt_reg[27]__0_n_0\,
      O => \recvAXIS_tlast_sig_i_5__0_n_0\
    );
\recvAXIS_tlast_sig_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \wordcnt_reg[25]__0_n_0\,
      I1 => \wordcnt_reg[26]__0_n_0\,
      I2 => \wordcnt_reg[24]__0_n_0\,
      O => \recvAXIS_tlast_sig_i_6__0_n_0\
    );
\recvAXIS_tlast_sig_i_7__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \wordcnt_reg[22]__0_n_0\,
      I1 => \wordcnt_reg[23]__0_n_0\,
      I2 => \wordcnt_reg[21]__0_n_0\,
      O => \recvAXIS_tlast_sig_i_7__0_n_0\
    );
\recvAXIS_tlast_sig_i_8__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \wordcnt_reg[19]__0_n_0\,
      I1 => \wordcnt_reg[20]__0_n_0\,
      I2 => \wordcnt_reg[18]__0_n_0\,
      O => \recvAXIS_tlast_sig_i_8__0_n_0\
    );
\recvAXIS_tlast_sig_i_9__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \wordcnt_reg[16]__0_n_0\,
      I1 => \wordcnt_reg[17]__0_n_0\,
      I2 => \wordcnt_reg[15]__0_n_0\,
      O => \recvAXIS_tlast_sig_i_9__0_n_0\
    );
recvAXIS_tlast_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvAXIS_tlast_sig_i_1__0_n_0\,
      Q => \^recvaxis_tlast\
    );
\recvAXIS_tlast_sig_reg_i_2__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \recvAXIS_tlast_sig_reg_i_3__0_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_recvAXIS_tlast_sig_reg_i_2__0_CO_UNCONNECTED\(7 downto 3),
      CO(2) => recvAXIS_tlast_sig0,
      CO(1) => \recvAXIS_tlast_sig_reg_i_2__0_n_6\,
      CO(0) => \recvAXIS_tlast_sig_reg_i_2__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_recvAXIS_tlast_sig_reg_i_2__0_O_UNCONNECTED\(7 downto 0),
      S(7 downto 3) => B"00000",
      S(2) => \recvAXIS_tlast_sig_i_4__0_n_0\,
      S(1) => \recvAXIS_tlast_sig_i_5__0_n_0\,
      S(0) => \recvAXIS_tlast_sig_i_6__0_n_0\
    );
\recvAXIS_tlast_sig_reg_i_3__0\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \recvAXIS_tlast_sig_reg_i_3__0_n_0\,
      CO(6) => \recvAXIS_tlast_sig_reg_i_3__0_n_1\,
      CO(5) => \recvAXIS_tlast_sig_reg_i_3__0_n_2\,
      CO(4) => \recvAXIS_tlast_sig_reg_i_3__0_n_3\,
      CO(3) => \recvAXIS_tlast_sig_reg_i_3__0_n_4\,
      CO(2) => \recvAXIS_tlast_sig_reg_i_3__0_n_5\,
      CO(1) => \recvAXIS_tlast_sig_reg_i_3__0_n_6\,
      CO(0) => \recvAXIS_tlast_sig_reg_i_3__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_recvAXIS_tlast_sig_reg_i_3__0_O_UNCONNECTED\(7 downto 0),
      S(7) => \recvAXIS_tlast_sig_i_7__0_n_0\,
      S(6) => \recvAXIS_tlast_sig_i_8__0_n_0\,
      S(5) => \recvAXIS_tlast_sig_i_9__0_n_0\,
      S(4) => \recvAXIS_tlast_sig_i_10__0_n_0\,
      S(3) => \recvAXIS_tlast_sig_i_11__0_n_0\,
      S(2) => \recvAXIS_tlast_sig_i_12__0_n_0\,
      S(1) => \recvAXIS_tlast_sig_i_13__0_n_0\,
      S(0) => \recvAXIS_tlast_sig_i_14__0_n_0\
    );
\recvStrbToStart_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B080"
    )
        port map (
      I0 => \stateRecv[2]_i_5__0_n_0\,
      I1 => \recvStrbToStart_i_2__0_n_0\,
      I2 => p_1_in0,
      I3 => recvStrbToStart_reg_n_0,
      O => \recvStrbToStart_i_1__0_n_0\
    );
\recvStrbToStart_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3E2E3F3F"
    )
        port map (
      I0 => \wordcnt[0]__0_i_4__0_n_0\,
      I1 => stateRecv(1),
      I2 => stateRecv(2),
      I3 => stateRecv(0),
      I4 => \stateRecv[2]_i_9_n_0\,
      O => \recvStrbToStart_i_2__0_n_0\
    );
recvStrbToStart_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvStrbToStart_i_1__0_n_0\,
      Q => recvStrbToStart_reg_n_0
    );
\recvStrbToStop_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C080CFF0C080C00"
    )
        port map (
      I0 => \stateRecv[2]_i_4__0_n_0\,
      I1 => stateRecv(0),
      I2 => \recvStrbToStop_i_2__0_n_0\,
      I3 => \stateRecv[2]_i_6_n_0\,
      I4 => \recvStrbToStop_i_3__0_n_0\,
      I5 => recvStrbToStop_reg_n_0,
      O => \recvStrbToStop_i_1__0_n_0\
    );
\recvStrbToStop_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F000000FFFFFFFF"
    )
        port map (
      I0 => stateRecv(0),
      I1 => stateRecv(2),
      I2 => stateRecv(1),
      I3 => stateTo(1),
      I4 => stateTo(0),
      I5 => \stateRecv[2]_i_7__0_n_0\,
      O => \recvStrbToStop_i_2__0_n_0\
    );
\recvStrbToStop_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFD5"
    )
        port map (
      I0 => p_1_in0,
      I1 => \stateRecv[2]_i_4__0_n_0\,
      I2 => stateRecv(0),
      I3 => stateRecv(2),
      O => \recvStrbToStop_i_3__0_n_0\
    );
recvStrbToStop_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \recvStrbToStop_i_1__0_n_0\,
      Q => recvStrbToStop_reg_n_0
    );
\resid[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \lastAXIS_tkeep_reg[3]_1\,
      I2 => \lastAXIS_tkeep_reg[3]\,
      O => \tixVCommand_reg[1]_0\(0)
    );
\resid[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10080000FFFFFFFF"
    )
        port map (
      I0 => Q(4),
      I1 => Q(0),
      I2 => Q(3),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^stateop_reg[1]\,
      O => \stateOp_reg[4]\(0)
    );
\resid[1]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \lastAXIS_tkeep_reg[3]_0\,
      I1 => \^e\(0),
      O => \tixVCommand_reg[1]_0\(1)
    );
\retbuf[0][0]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \retbuf_reg[5][5]\,
      I1 => \^stateop_reg[1]\,
      O => \^stateop_reg[0]\
    );
\retbuf[0][2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002000"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => Q(0),
      I2 => Q(1),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \^stateop_reg[0]_3\
    );
\retbuf[0][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000008"
    )
        port map (
      I0 => \retbuf_reg[36][7]_0\,
      I1 => \txAXIS_tdata_reg[15]\(0),
      I2 => \retbuf_reg[36][7]\(1),
      I3 => \retbuf_reg[36][7]\(2),
      I4 => \retbuf_reg[36][7]\(0),
      I5 => \^tixvcontroller_reg[1]\,
      O => \resid_reg[0]_3\(0)
    );
\retbuf[1][0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0E0E0"
    )
        port map (
      I0 => \retbuf_reg[5][5]\,
      I1 => \retbuf_reg[1][7]\(8),
      I2 => \^stateop_reg[1]\,
      I3 => \retbuf_reg[5][5]_0\,
      I4 => \retbuf_reg[1][0]\,
      O => \tkst_reg[31]\(0)
    );
\retbuf[1][1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[1][7]\(9),
      I2 => \pollbuf_reg[4][7]\(1),
      I3 => \retbuf_reg[1][7]_0\,
      I4 => \pollbuf_reg[4][7]\(9),
      I5 => \^stateop_reg[0]_3\,
      O => \tkst_reg[31]\(1)
    );
\retbuf[1][2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0E0E0"
    )
        port map (
      I0 => \retbuf_reg[5][5]\,
      I1 => \retbuf_reg[1][7]\(10),
      I2 => \^stateop_reg[1]\,
      I3 => \retbuf_reg[5][5]_0\,
      I4 => \retbuf_reg[1][2]\,
      O => \tkst_reg[31]\(2)
    );
\retbuf[1][3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[1][7]\(11),
      I2 => \pollbuf_reg[4][7]\(3),
      I3 => \retbuf_reg[1][7]_0\,
      I4 => \pollbuf_reg[4][7]\(11),
      I5 => \^stateop_reg[0]_3\,
      O => \tkst_reg[31]\(3)
    );
\retbuf[1][4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0E0E0"
    )
        port map (
      I0 => \retbuf_reg[5][5]\,
      I1 => \retbuf_reg[1][7]\(12),
      I2 => \^stateop_reg[1]\,
      I3 => \retbuf_reg[5][5]_0\,
      I4 => \retbuf_reg[1][4]\,
      O => \tkst_reg[31]\(4)
    );
\retbuf[1][5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0E0E0"
    )
        port map (
      I0 => \retbuf_reg[5][5]\,
      I1 => \retbuf_reg[1][7]\(13),
      I2 => \^stateop_reg[1]\,
      I3 => \retbuf_reg[5][5]_0\,
      I4 => \retbuf_reg[1][5]\,
      O => \tkst_reg[31]\(5)
    );
\retbuf[1][6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0E0E0"
    )
        port map (
      I0 => \retbuf_reg[5][5]\,
      I1 => \retbuf_reg[1][7]\(14),
      I2 => \^stateop_reg[1]\,
      I3 => \retbuf_reg[5][5]_0\,
      I4 => \retbuf_reg[1][6]\,
      O => \tkst_reg[31]\(6)
    );
\retbuf[1][7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAAE"
    )
        port map (
      I0 => \^tixvcontroller_reg[1]\,
      I1 => \retbuf_reg[36][7]_0\,
      I2 => \retbuf_reg[36][7]\(1),
      I3 => \retbuf_reg[36][7]\(2),
      I4 => \retbuf_reg[36][7]\(0),
      O => \ixRetbufCrc_reg[2]_3\(0)
    );
\retbuf[1][7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[1][7]\(15),
      I2 => \pollbuf_reg[4][7]\(7),
      I3 => \retbuf_reg[1][7]_0\,
      I4 => \pollbuf_reg[4][7]\(15),
      I5 => \^stateop_reg[0]_3\,
      O => \tkst_reg[31]\(7)
    );
\retbuf[2][7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"11151111FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg[14][4]\,
      I1 => \retbuf_reg[14][4]_0\,
      I2 => \retbuf_reg[2][7]\,
      I3 => \pollbuf_reg[0][7]\(1),
      I4 => \pollbuf_reg[0][7]\(2),
      I5 => \^stateop_reg[1]\,
      O => \^tixvcontroller_reg[1]\
    );
\retbuf[31][0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1F"
    )
        port map (
      I0 => \retbuf_reg[14][4]\,
      I1 => \retbuf_reg[14][4]_0\,
      I2 => \^stateop_reg[1]\,
      O => \^tixvcontroller_reg[0]_0\
    );
\retbuf[32][7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000800"
    )
        port map (
      I0 => \txAXIS_tdata_reg[15]\(0),
      I1 => \retbuf_reg[36][7]_0\,
      I2 => \retbuf_reg[36][7]\(1),
      I3 => \retbuf_reg[36][7]\(2),
      I4 => \retbuf_reg[36][7]\(0),
      I5 => \^tixvcontroller_reg[0]_0\,
      O => \resid_reg[0]_1\(0)
    );
\retbuf[33][7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0020"
    )
        port map (
      I0 => \retbuf_reg[36][7]_0\,
      I1 => \retbuf_reg[36][7]\(1),
      I2 => \retbuf_reg[36][7]\(2),
      I3 => \retbuf_reg[36][7]\(0),
      I4 => \^tixvcontroller_reg[0]_0\,
      O => \ixRetbufCrc_reg[2]\(0)
    );
\retbuf[35][7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAEAAAAAAAAAAAAA"
    )
        port map (
      I0 => \^tixvcontroller_reg[0]_0\,
      I1 => \retbuf_reg[36][7]\(0),
      I2 => \retbuf_reg[36][7]\(2),
      I3 => \retbuf_reg[36][7]\(1),
      I4 => \retbuf_reg[36][7]_0\,
      I5 => \txAXIS_tdata_reg[15]\(0),
      O => \ixRetbufCrc_reg[1]\(0)
    );
\retbuf[36][7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C800000FFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata_reg[15]\(0),
      I1 => \retbuf_reg[36][7]\(2),
      I2 => \retbuf_reg[36][7]\(1),
      I3 => \retbuf_reg[36][7]\(0),
      I4 => \retbuf_reg[36][7]_0\,
      I5 => \^stateop_reg[1]\,
      O => \resid_reg[0]\(0)
    );
\retbuf[37][7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55D55555"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \retbuf_reg[36][7]\(2),
      I2 => \retbuf_reg[36][7]\(1),
      I3 => \retbuf_reg[36][7]\(0),
      I4 => \retbuf_reg[36][7]_0\,
      O => \ixRetbufCrc_reg[5]_0\(0)
    );
\retbuf[38][7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      O => \stateOp_reg[1]_4\(0)
    );
\retbuf[39][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555555D5555555"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \retbuf_reg[36][7]\(2),
      I2 => \retbuf_reg[36][7]\(1),
      I3 => \retbuf_reg[36][7]\(0),
      I4 => Q(1),
      I5 => \retbuf_reg[39][0]\,
      O => \ixRetbufCrc_reg[5]_1\(0)
    );
\retbuf[3][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAEAAAAA"
    )
        port map (
      I0 => \^tixvcontroller_reg[1]\,
      I1 => \txAXIS_tdata_reg[15]\(0),
      I2 => \retbuf_reg[36][7]_0\,
      I3 => \retbuf_reg[36][7]\(2),
      I4 => \retbuf_reg[36][7]\(0),
      I5 => \retbuf_reg[36][7]\(1),
      O => \resid_reg[0]_2\(0)
    );
\retbuf[4][0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[1][7]\(0),
      I2 => \pollbuf_reg[4][7]\(0),
      I3 => \retbuf_reg[4][7]\,
      I4 => \pollbuf_reg[4][7]\(8),
      I5 => \^stateop_reg[0]_3\,
      O => \tkst_reg[7]\(0)
    );
\retbuf[4][1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[1][7]\(1),
      I2 => \pollbuf_reg[4][7]\(1),
      I3 => \retbuf_reg[4][7]\,
      I4 => \pollbuf_reg[4][7]\(9),
      I5 => \^stateop_reg[0]_3\,
      O => \tkst_reg[7]\(1)
    );
\retbuf[4][2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[1][7]\(2),
      I2 => \pollbuf_reg[4][7]\(2),
      I3 => \retbuf_reg[4][7]\,
      I4 => \pollbuf_reg[4][7]\(10),
      I5 => \^stateop_reg[0]_3\,
      O => \tkst_reg[7]\(2)
    );
\retbuf[4][3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[1][7]\(3),
      I2 => \pollbuf_reg[4][7]\(3),
      I3 => \retbuf_reg[4][7]\,
      I4 => \pollbuf_reg[4][7]\(11),
      I5 => \^stateop_reg[0]_3\,
      O => \tkst_reg[7]\(3)
    );
\retbuf[4][4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0E0E0"
    )
        port map (
      I0 => \retbuf_reg[5][5]\,
      I1 => \retbuf_reg[1][7]\(4),
      I2 => \^stateop_reg[1]\,
      I3 => \retbuf_reg[5][5]_0\,
      I4 => \retbuf_reg[4][4]\,
      O => \tkst_reg[7]\(4)
    );
\retbuf[4][5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0E0E0"
    )
        port map (
      I0 => \retbuf_reg[5][5]\,
      I1 => \retbuf_reg[1][7]\(5),
      I2 => \^stateop_reg[1]\,
      I3 => \retbuf_reg[5][5]_0\,
      I4 => \retbuf_reg[4][5]\,
      O => \tkst_reg[7]\(5)
    );
\retbuf[4][6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0E0E0"
    )
        port map (
      I0 => \retbuf_reg[5][5]\,
      I1 => \retbuf_reg[1][7]\(6),
      I2 => \^stateop_reg[1]\,
      I3 => \retbuf_reg[5][5]_0\,
      I4 => \retbuf_reg[4][6]\,
      O => \tkst_reg[7]\(6)
    );
\retbuf[4][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABAEAAAAABAAAAAA"
    )
        port map (
      I0 => \^tixvcontroller_reg[1]\,
      I1 => \retbuf_reg[36][7]\(1),
      I2 => \retbuf_reg[36][7]\(2),
      I3 => \retbuf_reg[36][7]\(0),
      I4 => \retbuf_reg[36][7]_0\,
      I5 => \txAXIS_tdata_reg[15]\(0),
      O => \ixRetbufCrc_reg[2]_2\(0)
    );
\retbuf[4][7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[1][7]\(7),
      I2 => \pollbuf_reg[4][7]\(7),
      I3 => \retbuf_reg[4][7]\,
      I4 => \pollbuf_reg[4][7]\(15),
      I5 => \^stateop_reg[0]_3\,
      O => \tkst_reg[7]\(7)
    );
\retbuf[5][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[5][7]\(0),
      I2 => \pollbuf_reg[4][7]\(0),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \pollbuf_reg[4][7]\(8),
      I5 => \^stateop_reg[0]_3\,
      O => \scoreMin_reg[7]\(0)
    );
\retbuf[5][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[5][7]\(1),
      I2 => \pollbuf_reg[4][7]\(1),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \pollbuf_reg[4][7]\(9),
      I5 => \^stateop_reg[0]_3\,
      O => \scoreMin_reg[7]\(1)
    );
\retbuf[5][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[5][7]\(2),
      I2 => \pollbuf_reg[4][7]\(2),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \pollbuf_reg[4][7]\(10),
      I5 => \^stateop_reg[0]_3\,
      O => \scoreMin_reg[7]\(2)
    );
\retbuf[5][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[5][7]\(3),
      I2 => \pollbuf_reg[4][7]\(3),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \pollbuf_reg[4][7]\(11),
      I5 => \^stateop_reg[0]_3\,
      O => \scoreMin_reg[7]\(3)
    );
\retbuf[5][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[5][7]\(4),
      I2 => \pollbuf_reg[4][7]\(4),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \pollbuf_reg[4][7]\(12),
      I5 => \^stateop_reg[0]_3\,
      O => \scoreMin_reg[7]\(4)
    );
\retbuf[5][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0E0E0"
    )
        port map (
      I0 => \retbuf_reg[5][5]\,
      I1 => \retbuf_reg[5][7]\(5),
      I2 => \^stateop_reg[1]\,
      I3 => \retbuf_reg[5][5]_0\,
      I4 => \retbuf_reg[5][5]_1\,
      O => \scoreMin_reg[7]\(5)
    );
\retbuf[5][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[5][7]\(6),
      I2 => \pollbuf_reg[4][7]\(6),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \pollbuf_reg[4][7]\(14),
      I5 => \^stateop_reg[0]_3\,
      O => \scoreMin_reg[7]\(6)
    );
\retbuf[5][7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAEAAAA"
    )
        port map (
      I0 => \^tixvcontroller_reg[1]\,
      I1 => \retbuf_reg[36][7]\(1),
      I2 => \retbuf_reg[36][7]\(2),
      I3 => \retbuf_reg[36][7]\(0),
      I4 => \retbuf_reg[36][7]_0\,
      O => \ixRetbufCrc_reg[2]_1\(0)
    );
\retbuf[5][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFF44444444444"
    )
        port map (
      I0 => \^stateop_reg[0]\,
      I1 => \retbuf_reg[5][7]\(7),
      I2 => \pollbuf_reg[4][7]\(7),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \pollbuf_reg[4][7]\(15),
      I5 => \^stateop_reg[0]_3\,
      O => \scoreMin_reg[7]\(7)
    );
\retbuf[7][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF2000FFFF0000"
    )
        port map (
      I0 => \retbuf_reg[36][7]_0\,
      I1 => \retbuf_reg[36][7]\(2),
      I2 => \retbuf_reg[36][7]\(0),
      I3 => \retbuf_reg[36][7]\(1),
      I4 => \^tixvcontroller_reg[0]_0\,
      I5 => \txAXIS_tdata_reg[15]\(0),
      O => \ixRetbufCrc_reg[5]\(0)
    );
\retbuf[8][7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEAAAAA"
    )
        port map (
      I0 => \^tixvcontroller_reg[0]_0\,
      I1 => \retbuf_reg[36][7]\(1),
      I2 => \retbuf_reg[36][7]\(0),
      I3 => \retbuf_reg[36][7]\(2),
      I4 => \retbuf_reg[36][7]_0\,
      O => \ixRetbufCrc_reg[2]_0\(0)
    );
\rpuAXIL_rdata[0]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(0),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(0)
    );
\rpuAXIL_rdata[10]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(10),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(10)
    );
\rpuAXIL_rdata[11]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(11),
      O => rpuAXIL_rdata(11)
    );
\rpuAXIL_rdata[12]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(12),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(12)
    );
\rpuAXIL_rdata[13]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(13),
      O => rpuAXIL_rdata(13)
    );
\rpuAXIL_rdata[14]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(14),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(14)
    );
\rpuAXIL_rdata[15]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(15),
      O => rpuAXIL_rdata(15)
    );
\rpuAXIL_rdata[16]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(16),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(16)
    );
\rpuAXIL_rdata[17]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(17),
      O => rpuAXIL_rdata(17)
    );
\rpuAXIL_rdata[18]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(18),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(18)
    );
\rpuAXIL_rdata[19]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(19),
      O => rpuAXIL_rdata(19)
    );
\rpuAXIL_rdata[1]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(1),
      O => rpuAXIL_rdata(1)
    );
\rpuAXIL_rdata[20]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(20),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(20)
    );
\rpuAXIL_rdata[21]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(21),
      O => rpuAXIL_rdata(21)
    );
\rpuAXIL_rdata[22]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(22),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(22)
    );
\rpuAXIL_rdata[23]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(23),
      O => rpuAXIL_rdata(23)
    );
\rpuAXIL_rdata[24]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(24),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(24)
    );
\rpuAXIL_rdata[25]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(25),
      O => rpuAXIL_rdata(25)
    );
\rpuAXIL_rdata[26]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(26),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(26)
    );
\rpuAXIL_rdata[27]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(27),
      O => rpuAXIL_rdata(27)
    );
\rpuAXIL_rdata[28]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(28),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(28)
    );
\rpuAXIL_rdata[29]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(29),
      O => rpuAXIL_rdata(29)
    );
\rpuAXIL_rdata[2]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(2),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(2)
    );
\rpuAXIL_rdata[30]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(30),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(30)
    );
\rpuAXIL_rdata[31]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(31),
      O => rpuAXIL_rdata(31)
    );
\rpuAXIL_rdata[31]_INST_0_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FE40F05F"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => Q(2),
      I3 => Q(4),
      I4 => Q(3),
      O => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\
    );
\rpuAXIL_rdata[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(3),
      O => rpuAXIL_rdata(3)
    );
\rpuAXIL_rdata[4]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(4),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(4)
    );
\rpuAXIL_rdata[5]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(5),
      O => rpuAXIL_rdata(5)
    );
\rpuAXIL_rdata[6]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(6),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(6)
    );
\rpuAXIL_rdata[7]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(7),
      O => rpuAXIL_rdata(7)
    );
\rpuAXIL_rdata[8]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A280A28002808A8"
    )
        port map (
      I0 => sendAXIL_rdata(8),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => Q(1),
      O => rpuAXIL_rdata(8)
    );
\rpuAXIL_rdata[9]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \recvAXIL_rdata_reg_n_0_[31]\,
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => sendAXIL_rdata(9),
      O => rpuAXIL_rdata(9)
    );
\rxlen[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AABFAA80"
    )
        port map (
      I0 => \rxlen[1]_i_2_n_0\,
      I1 => \rxlen_reg[1]_0\,
      I2 => \rxlen[1]_i_4_n_0\,
      I3 => \rxlen[1]_i_5_n_0\,
      I4 => rxlen(0),
      O => \rxlen_reg[1]\
    );
\rxlen[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000000"
    )
        port map (
      I0 => Q(3),
      I1 => Q(2),
      I2 => Q(0),
      I3 => Q(1),
      I4 => Q(4),
      I5 => \^stateop_reg[1]\,
      O => \rxlen[1]_i_2_n_0\
    );
\rxlen[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => stateSend(0),
      I1 => stateSend(1),
      I2 => stateSend(2),
      I3 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      O => \rxlen[1]_i_4_n_0\
    );
\rxlen[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00010800FFFFFFFF"
    )
        port map (
      I0 => Q(2),
      I1 => Q(0),
      I2 => Q(3),
      I3 => Q(4),
      I4 => Q(1),
      I5 => \^stateop_reg[1]\,
      O => \rxlen[1]_i_5_n_0\
    );
\sendAXIL_rdata[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(0),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[0]_i_1__0_n_0\
    );
\sendAXIL_rdata[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(10),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[10]_i_1__0_n_0\
    );
\sendAXIL_rdata[11]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(11),
      O => \sendAXIL_rdata[11]_i_1__0_n_0\
    );
\sendAXIL_rdata[12]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(12),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[12]_i_1__0_n_0\
    );
\sendAXIL_rdata[13]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(13),
      O => \sendAXIL_rdata[13]_i_1__0_n_0\
    );
\sendAXIL_rdata[14]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(14),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[14]_i_1__0_n_0\
    );
\sendAXIL_rdata[15]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(15),
      O => \sendAXIL_rdata[15]_i_1__0_n_0\
    );
\sendAXIL_rdata[16]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(16),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[16]_i_1__0_n_0\
    );
\sendAXIL_rdata[17]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(17),
      O => \sendAXIL_rdata[17]_i_1__0_n_0\
    );
\sendAXIL_rdata[18]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(18),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[18]_i_1__0_n_0\
    );
\sendAXIL_rdata[19]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(19),
      O => \sendAXIL_rdata[19]_i_1__0_n_0\
    );
\sendAXIL_rdata[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(1),
      O => \sendAXIL_rdata[1]_i_1__0_n_0\
    );
\sendAXIL_rdata[20]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(20),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[20]_i_1__0_n_0\
    );
\sendAXIL_rdata[21]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(21),
      O => \sendAXIL_rdata[21]_i_1__0_n_0\
    );
\sendAXIL_rdata[22]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(22),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[22]_i_1__0_n_0\
    );
\sendAXIL_rdata[23]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(23),
      O => \sendAXIL_rdata[23]_i_1__0_n_0\
    );
\sendAXIL_rdata[24]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(24),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[24]_i_1__0_n_0\
    );
\sendAXIL_rdata[25]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(25),
      O => \sendAXIL_rdata[25]_i_1__0_n_0\
    );
\sendAXIL_rdata[26]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(26),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[26]_i_1__0_n_0\
    );
\sendAXIL_rdata[27]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(27),
      O => \sendAXIL_rdata[27]_i_1__0_n_0\
    );
\sendAXIL_rdata[28]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(28),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[28]_i_1__0_n_0\
    );
\sendAXIL_rdata[29]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(29),
      O => \sendAXIL_rdata[29]_i_1__0_n_0\
    );
\sendAXIL_rdata[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(2),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[2]_i_1__0_n_0\
    );
\sendAXIL_rdata[30]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(30),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[30]_i_1__0_n_0\
    );
\sendAXIL_rdata[31]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F00FF40FFFFFFFF"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      I2 => stateSend(0),
      I3 => \sendAXIL_rdata[31]_i_3_n_0\,
      I4 => \sendAXIL_rdata[31]_i_4_n_0\,
      I5 => \sendAXIL_rdata[31]_i_5_n_0\,
      O => \sendAXIL_rdata[31]_i_1__0_n_0\
    );
\sendAXIL_rdata[31]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(31),
      O => \sendAXIL_rdata[31]_i_2_n_0\
    );
\sendAXIL_rdata[31]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008000000"
    )
        port map (
      I0 => \^axil_arready\,
      I1 => rpuAXIL_arvalid,
      I2 => AXIL_araddr_sig(4),
      I3 => AXIL_araddr_sig(5),
      I4 => stateSend(1),
      I5 => stateSend(2),
      O => \sendAXIL_rdata[31]_i_3_n_0\
    );
\sendAXIL_rdata[31]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7F7FBDF"
    )
        port map (
      I0 => Q(3),
      I1 => Q(1),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      O => \sendAXIL_rdata[31]_i_4_n_0\
    );
\sendAXIL_rdata[31]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000AAA8AAA8AAA8"
    )
        port map (
      I0 => \stateSend[2]_i_9__0_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => stateTo(0),
      I5 => stateTo(1),
      O => \sendAXIL_rdata[31]_i_5_n_0\
    );
\sendAXIL_rdata[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(3),
      O => \sendAXIL_rdata[3]_i_1__0_n_0\
    );
\sendAXIL_rdata[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(4),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[4]_i_1__0_n_0\
    );
\sendAXIL_rdata[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(5),
      O => \sendAXIL_rdata[5]_i_1__0_n_0\
    );
\sendAXIL_rdata[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(6),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[6]_i_1__0_n_0\
    );
\sendAXIL_rdata[7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(7),
      O => \sendAXIL_rdata[7]_i_1__0_n_0\
    );
\sendAXIL_rdata[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[31]_0\(8),
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      O => \sendAXIL_rdata[8]_i_1__0_n_0\
    );
\sendAXIL_rdata[9]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0020"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => \sendAXIL_rdata_reg[31]_0\(9),
      O => \sendAXIL_rdata[9]_i_1__0_n_0\
    );
\sendAXIL_rdata_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[0]_i_1__0_n_0\,
      Q => sendAXIL_rdata(0)
    );
\sendAXIL_rdata_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[10]_i_1__0_n_0\,
      Q => sendAXIL_rdata(10)
    );
\sendAXIL_rdata_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[11]_i_1__0_n_0\,
      Q => sendAXIL_rdata(11)
    );
\sendAXIL_rdata_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[12]_i_1__0_n_0\,
      Q => sendAXIL_rdata(12)
    );
\sendAXIL_rdata_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[13]_i_1__0_n_0\,
      Q => sendAXIL_rdata(13)
    );
\sendAXIL_rdata_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[14]_i_1__0_n_0\,
      Q => sendAXIL_rdata(14)
    );
\sendAXIL_rdata_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[15]_i_1__0_n_0\,
      Q => sendAXIL_rdata(15)
    );
\sendAXIL_rdata_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[16]_i_1__0_n_0\,
      Q => sendAXIL_rdata(16)
    );
\sendAXIL_rdata_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[17]_i_1__0_n_0\,
      Q => sendAXIL_rdata(17)
    );
\sendAXIL_rdata_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[18]_i_1__0_n_0\,
      Q => sendAXIL_rdata(18)
    );
\sendAXIL_rdata_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[19]_i_1__0_n_0\,
      Q => sendAXIL_rdata(19)
    );
\sendAXIL_rdata_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[1]_i_1__0_n_0\,
      Q => sendAXIL_rdata(1)
    );
\sendAXIL_rdata_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[20]_i_1__0_n_0\,
      Q => sendAXIL_rdata(20)
    );
\sendAXIL_rdata_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[21]_i_1__0_n_0\,
      Q => sendAXIL_rdata(21)
    );
\sendAXIL_rdata_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[22]_i_1__0_n_0\,
      Q => sendAXIL_rdata(22)
    );
\sendAXIL_rdata_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[23]_i_1__0_n_0\,
      Q => sendAXIL_rdata(23)
    );
\sendAXIL_rdata_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[24]_i_1__0_n_0\,
      Q => sendAXIL_rdata(24)
    );
\sendAXIL_rdata_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[25]_i_1__0_n_0\,
      Q => sendAXIL_rdata(25)
    );
\sendAXIL_rdata_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[26]_i_1__0_n_0\,
      Q => sendAXIL_rdata(26)
    );
\sendAXIL_rdata_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[27]_i_1__0_n_0\,
      Q => sendAXIL_rdata(27)
    );
\sendAXIL_rdata_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[28]_i_1__0_n_0\,
      Q => sendAXIL_rdata(28)
    );
\sendAXIL_rdata_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[29]_i_1__0_n_0\,
      Q => sendAXIL_rdata(29)
    );
\sendAXIL_rdata_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[2]_i_1__0_n_0\,
      Q => sendAXIL_rdata(2)
    );
\sendAXIL_rdata_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[30]_i_1__0_n_0\,
      Q => sendAXIL_rdata(30)
    );
\sendAXIL_rdata_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[31]_i_2_n_0\,
      Q => sendAXIL_rdata(31)
    );
\sendAXIL_rdata_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[3]_i_1__0_n_0\,
      Q => sendAXIL_rdata(3)
    );
\sendAXIL_rdata_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[4]_i_1__0_n_0\,
      Q => sendAXIL_rdata(4)
    );
\sendAXIL_rdata_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[5]_i_1__0_n_0\,
      Q => sendAXIL_rdata(5)
    );
\sendAXIL_rdata_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[6]_i_1__0_n_0\,
      Q => sendAXIL_rdata(6)
    );
\sendAXIL_rdata_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[7]_i_1__0_n_0\,
      Q => sendAXIL_rdata(7)
    );
\sendAXIL_rdata_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[8]_i_1__0_n_0\,
      Q => sendAXIL_rdata(8)
    );
\sendAXIL_rdata_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \sendAXIL_rdata[31]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendAXIL_rdata[9]_i_1__0_n_0\,
      Q => sendAXIL_rdata(9)
    );
\sendStrbToStart_i_10__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[25]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[23]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[28]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[24]\,
      O => \sendStrbToStart_i_10__0_n_0\
    );
\sendStrbToStart_i_11__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[1]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[30]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[20]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[8]\,
      O => \sendStrbToStart_i_11__0_n_0\
    );
\sendStrbToStart_i_12__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[21]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[5]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[27]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[9]\,
      O => \sendStrbToStart_i_12__0_n_0\
    );
\sendStrbToStart_i_13__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[13]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[10]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[11]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[12]\,
      O => \sendStrbToStart_i_13__0_n_0\
    );
\sendStrbToStart_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F300770003007700"
    )
        port map (
      I0 => stateSend(2),
      I1 => \sendStrbToStart_i_2__0_n_0\,
      I2 => \sendStrbToStart_i_3__0_n_0\,
      I3 => \sendAXIL_rdata[31]_i_5_n_0\,
      I4 => \sendStrbToStart_i_4__0_n_0\,
      I5 => sendStrbToStart_reg_n_0,
      O => \sendStrbToStart_i_1__0_n_0\
    );
\sendStrbToStart_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAAFFFFFFFF3FFF"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_4_n_0\,
      I1 => \stateSend[2]_i_3__0_n_0\,
      I2 => sendStrbToStart0,
      I3 => stateSend(2),
      I4 => stateSend(1),
      I5 => stateSend(0),
      O => \sendStrbToStart_i_2__0_n_0\
    );
\sendStrbToStart_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D999"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      I2 => \sendAXIL_rdata[31]_i_4_n_0\,
      I3 => stateSend(0),
      O => \sendStrbToStart_i_3__0_n_0\
    );
\sendStrbToStart_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFBFFFF"
    )
        port map (
      I0 => \sendStrbToStart_i_5__0_n_0\,
      I1 => stateSend(0),
      I2 => stateSend(1),
      I3 => \stateRecv[2]_i_10__0_n_0\,
      I4 => ixBlkWrite(1),
      I5 => ixBlkWrite(0),
      O => \sendStrbToStart_i_4__0_n_0\
    );
\sendStrbToStart_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \sendStrbToStart_i_6__0_n_0\,
      I1 => \sendStrbToStart_i_7__0_n_0\,
      I2 => \sendStrbToStart_i_8__0_n_0\,
      I3 => \sendStrbToStart_i_9__0_n_0\,
      O => \sendStrbToStart_i_5__0_n_0\
    );
\sendStrbToStart_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEFF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[4]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[14]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[18]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[15]\,
      I4 => \sendStrbToStart_i_10__0_n_0\,
      O => \sendStrbToStart_i_6__0_n_0\
    );
\sendStrbToStart_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFF7"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[17]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[29]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[16]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[22]\,
      I4 => \sendStrbToStart_i_11__0_n_0\,
      O => \sendStrbToStart_i_7__0_n_0\
    );
\sendStrbToStart_i_8__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF7FF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[7]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[19]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[26]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[31]\,
      I4 => \sendStrbToStart_i_12__0_n_0\,
      O => \sendStrbToStart_i_8__0_n_0\
    );
\sendStrbToStart_i_9__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[0]\,
      I1 => p_0_in(1),
      I2 => p_0_in(0),
      I3 => \AXIL_wdata_sig_reg_n_0_[6]\,
      I4 => \sendStrbToStart_i_13__0_n_0\,
      O => \sendStrbToStart_i_9__0_n_0\
    );
sendStrbToStart_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendStrbToStart_i_1__0_n_0\,
      Q => sendStrbToStart_reg_n_0
    );
\sendStrbToStop_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAAAAA8AAAAA"
    )
        port map (
      I0 => \sendStrbToStop_i_2__0_n_0\,
      I1 => \sendStrbToStop_i_3__0_n_0\,
      I2 => \sendAXIL_rdata[31]_i_5_n_0\,
      I3 => \sendStrbToStop_i_4__0_n_0\,
      I4 => \sendStrbToStop_i_5__0_n_0\,
      I5 => sendStrbToStop_reg_n_0,
      O => \sendStrbToStop_i_1__0_n_0\
    );
\sendStrbToStop_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5F5C0C0C00000000"
    )
        port map (
      I0 => \stateSend[2]_i_5__0_n_0\,
      I1 => \sendAXIL_rdata[31]_i_3_n_0\,
      I2 => stateSend(0),
      I3 => \stateSend[2]_i_3__0_n_0\,
      I4 => \stateSend[2]_i_6__0_n_0\,
      I5 => \sendAXIL_rdata[31]_i_5_n_0\,
      O => \sendStrbToStop_i_2__0_n_0\
    );
\sendStrbToStop_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400040007000400"
    )
        port map (
      I0 => \stateSend[2]_i_5__0_n_0\,
      I1 => stateSend(0),
      I2 => stateSend(1),
      I3 => stateSend(2),
      I4 => \stateSend[2]_i_3__0_n_0\,
      I5 => sendStrbToStart0,
      O => \sendStrbToStop_i_3__0_n_0\
    );
\sendStrbToStop_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      I2 => stateSend(0),
      O => \sendStrbToStop_i_4__0_n_0\
    );
\sendStrbToStop_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFDFCFDFDFDFDFDF"
    )
        port map (
      I0 => stateSend(0),
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => AXIL_araddr_sig(5),
      I4 => AXIL_araddr_sig(4),
      I5 => strbRead,
      O => \sendStrbToStop_i_5__0_n_0\
    );
sendStrbToStop_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \sendStrbToStop_i_1__0_n_0\,
      Q => sendStrbToStop_reg_n_0
    );
\stateOp[0]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2222222200022202"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => \stateOp[0]_i_3_n_0\,
      I2 => \stateOp_reg[0]_8\,
      I3 => Q(3),
      I4 => \stateOp_reg[0]_9\,
      I5 => Q(4),
      O => \stateOp_reg[1]_2\(0)
    );
\stateOp[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BF00BFBFBFBFBFBF"
    )
        port map (
      I0 => \^stateop_reg[1]_5\,
      I1 => \stateOp_reg[0]_10\(0),
      I2 => \stateOp_reg[0]_10\(1),
      I3 => \^statesend_reg[0]_0\,
      I4 => \stateOp_reg[0]_11\(0),
      I5 => \stateOp_reg[0]_11\(1),
      O => \stateOp[0]_i_2__0_n_0\
    );
\stateOp[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B000F000B00000"
    )
        port map (
      I0 => Q(0),
      I1 => \stateOp[0]_i_6__0_n_0\,
      I2 => Q(4),
      I3 => Q(3),
      I4 => Q(2),
      I5 => \stateOp_reg[0]_13\,
      O => \stateOp[0]_i_3_n_0\
    );
\stateOp[0]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => Q(1),
      I1 => \stateOp[0]_i_8__0_n_0\,
      I2 => rxAXIS_tdata(1),
      I3 => \^recvaxis_tdata\(1),
      I4 => \^recvaxis_tdata\(3),
      I5 => rxAXIS_tdata(7),
      O => \stateOp[0]_i_6__0_n_0\
    );
\stateOp[0]_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^recvaxis_tdata\(2),
      I1 => rxAXIS_tdata(6),
      I2 => \^recvaxis_tdata\(0),
      I3 => rxAXIS_tdata(2),
      O => \stateOp[0]_i_8__0_n_0\
    );
\stateOp[1]_i_10__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      O => \stateOp[1]_i_10__0_n_0\
    );
\stateOp[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08AAAA0808080808"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \stateOp[1]_i_2__5_n_0\,
      I2 => \stateOp_reg[1]_6\,
      I3 => Q(0),
      I4 => Q(1),
      I5 => \stateOp_reg[1]_7\,
      O => \stateOp_reg[1]_2\(1)
    );
\stateOp[1]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBF3F3FBFBF3F3F"
    )
        port map (
      I0 => \stateOp[2]_i_5__2_n_0\,
      I1 => Q(2),
      I2 => Q(3),
      I3 => CO(0),
      I4 => Q(0),
      I5 => Q(1),
      O => \stateOp[1]_i_2__5_n_0\
    );
\stateOp[1]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF0FFFFEEEEFFFF"
    )
        port map (
      I0 => txAXIS_tready,
      I1 => \stateOp_reg[0]_12\,
      I2 => \^rxaxis_tvalid\,
      I3 => stateOp_reg_4,
      I4 => ackRxtx,
      I5 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      O => \^statesend_reg[0]_0\
    );
\stateOp[1]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEBFEFDFFE37CFDF"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => Q(2),
      I3 => Q(4),
      I4 => Q(3),
      I5 => ackRxtx,
      O => \^stateop_reg[1]_5\
    );
\stateOp[1]_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => stateSend(0),
      I1 => stateSend(1),
      I2 => stateSend(2),
      O => txAXIS_tready
    );
\stateOp[1]_i_7__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7C007C007CFF7C00"
    )
        port map (
      I0 => stateRecv(0),
      I1 => stateRecv(2),
      I2 => stateRecv(1),
      I3 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I4 => \stateOp[1]_i_9__1_n_0\,
      I5 => \stateOp[1]_i_10__0_n_0\,
      O => ackRxtx
    );
\stateOp[1]_i_9__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => stateSend(1),
      I1 => stateSend(2),
      I2 => stateSend(0),
      O => \stateOp[1]_i_9__1_n_0\
    );
\stateOp[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00022202AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => Q(4),
      I2 => \stateOp_reg[2]_3\,
      I3 => Q(3),
      I4 => \stateOp[2]_i_3__2_n_0\,
      I5 => \stateOp_reg[2]_4\,
      O => \stateOp_reg[1]_2\(2)
    );
\stateOp[2]_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FC7F7F"
    )
        port map (
      I0 => CO(0),
      I1 => Q(0),
      I2 => Q(1),
      I3 => \stateOp[2]_i_5__2_n_0\,
      I4 => Q(2),
      O => \stateOp[2]_i_3__2_n_0\
    );
\stateOp[2]_i_5__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \crcAXIS_tlast_sig_i_9__0_0\(3),
      I1 => \crcAXIS_tlast_sig_i_9__0_0\(2),
      I2 => \crcAXIS_tlast_sig_i_9__0_0\(1),
      I3 => \crcAXIS_tlast_sig_i_9__0_0\(0),
      I4 => \crcAXIS_tlast_sig_i_9__0_1\,
      I5 => \stateOp[0]_i_6__0_n_0\,
      O => \stateOp[2]_i_5__2_n_0\
    );
\stateOp[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080808080888"
    )
        port map (
      I0 => \stateOp[3]_i_2__0_n_0\,
      I1 => \^stateop_reg[1]\,
      I2 => \stateOp_reg[3]_3\,
      I3 => \txAXIS_tdata_reg[7]_0\,
      I4 => \txAXIS_tdata_reg[7]_1\,
      I5 => \stateOp_reg[3]_4\,
      O => \stateOp_reg[1]_2\(3)
    );
\stateOp[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"15FF15FFFFFF55FF"
    )
        port map (
      I0 => \stateOp_reg[3]_5\,
      I1 => Q(2),
      I2 => \stateOp[3]_i_8_n_0\,
      I3 => \stateOp_reg[3]_6\,
      I4 => Q(4),
      I5 => Q(3),
      O => \stateOp[3]_i_2__0_n_0\
    );
\stateOp[3]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => Q(0),
      I1 => Q(1),
      I2 => \stateOp[2]_i_5__2_n_0\,
      O => \stateOp[3]_i_8_n_0\
    );
\stateOp[4]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"03F202F3038F3BFC"
    )
        port map (
      I0 => \rxlen[1]_i_4_n_0\,
      I1 => Q(4),
      I2 => Q(0),
      I3 => Q(3),
      I4 => Q(1),
      I5 => Q(2),
      O => \stateOp[4]_i_19_n_0\
    );
\stateOp[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFA2228000"
    )
        port map (
      I0 => \stateOp_reg[0]_4\,
      I1 => \stateOp_reg[0]_5\,
      I2 => \^rxaxis_tvalid\,
      I3 => CO(0),
      I4 => \stateOp_reg[0]_6\,
      I5 => \stateOp[4]_i_7__0_n_0\,
      O => \stateOp_reg[2]_2\(0)
    );
\stateOp[4]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \stateOp_reg[4]_1\,
      I2 => \stateOp_reg[4]_2\,
      O => \stateOp_reg[1]_2\(4)
    );
\stateOp[4]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFBFBBBBBBBFBBB"
    )
        port map (
      I0 => \stateOp[4]_i_19_n_0\,
      I1 => \^stateop_reg[1]\,
      I2 => \stateOp_reg[0]_7\,
      I3 => \^rxaxis_tvalid\,
      I4 => \stateOp_reg[0]_4\,
      I5 => txAXIS_tready,
      O => \stateOp[4]_i_7__0_n_0\
    );
\stateOp[4]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \^stateop_reg[1]\
    );
\stateOp_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5155"
    )
        port map (
      I0 => crcAXIS_tlast_sig_reg_2,
      I1 => \^rxaxis_tvalid\,
      I2 => stateOp_reg_4,
      I3 => \^recvaxis_tlast\,
      O => crcAXIS_tlast_sig_reg
    );
\stateOp_next[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \stateOp_next_reg[0]\,
      O => \stateOp_reg[1]_0\(0)
    );
\stateOp_next[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \stateOp_next_reg[1]\,
      O => \stateOp_reg[1]_0\(1)
    );
\stateOp_next[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF002000"
    )
        port map (
      I0 => \stateOp_next_reg[2]\(0),
      I1 => \stateOp_next_reg[2]_0\,
      I2 => \lastAXIS_tkeep_reg[3]_0\,
      I3 => \^stateop_reg[1]\,
      I4 => \stateOp_next_reg[1]\,
      O => \stateOp_reg[1]_0\(2)
    );
\stateOp_next[3]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \stateOp_next_reg[4]\,
      I2 => \lastAXIS_tkeep_reg[3]_0\,
      O => \stateOp_reg[1]_0\(3)
    );
\stateOp_next[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00001000FFFFFFFF"
    )
        port map (
      I0 => Q(3),
      I1 => Q(4),
      I2 => Q(0),
      I3 => Q(2),
      I4 => Q(1),
      I5 => \^stateop_reg[1]\,
      O => \stateOp_reg[3]_2\(0)
    );
\stateOp_next[4]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \stateOp_next_reg[4]\,
      O => \stateOp_reg[1]_0\(4)
    );
\stateRecv[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"06FF060006000600"
    )
        port map (
      I0 => stateRecv(2),
      I1 => stateRecv(1),
      I2 => stateRecv(0),
      I3 => p_1_in0,
      I4 => req,
      I5 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      O => \stateRecv[0]_i_1__0_n_0\
    );
\stateRecv[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCC0CCCCC4CCC0"
    )
        port map (
      I0 => \^recvaxis_tlast\,
      I1 => \stateRecv[2]_i_7__0_n_0\,
      I2 => \stateSend[2]_i_10__0_n_0\,
      I3 => stateRecv(1),
      I4 => stateRecv(2),
      I5 => stateRecv(0),
      O => \stateRecv[1]_i_1__0_n_0\
    );
\stateRecv[2]_i_10__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^axil_bvalid_sig_reg_0\,
      I1 => rpuAXIL_bready,
      O => \stateRecv[2]_i_10__0_n_0\
    );
\stateRecv[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF5FFD5FFFFFFD5"
    )
        port map (
      I0 => p_1_in0,
      I1 => \stateRecv[2]_i_4__0_n_0\,
      I2 => stateRecv(0),
      I3 => \stateRecv[2]_i_5__0_n_0\,
      I4 => \stateRecv[2]_i_6_n_0\,
      I5 => stateRecv(2),
      O => \stateRecv[2]_i_1__0_n_0\
    );
\stateRecv[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCC0CCC8C0C0"
    )
        port map (
      I0 => \^recvaxis_tlast\,
      I1 => \stateRecv[2]_i_7__0_n_0\,
      I2 => \stateSend[2]_i_10__0_n_0\,
      I3 => stateRecv(1),
      I4 => stateRecv(2),
      I5 => stateRecv(0),
      O => \stateRecv[2]_i_2__0_n_0\
    );
\stateRecv[2]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA2A2A2A2A2A2A00"
    )
        port map (
      I0 => \stateRecv[2]_i_7__0_n_0\,
      I1 => stateTo(0),
      I2 => stateTo(1),
      I3 => stateRecv(1),
      I4 => stateRecv(2),
      I5 => stateRecv(0),
      O => p_1_in0
    );
\stateRecv[2]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000000000"
    )
        port map (
      I0 => \^axil_bvalid_sig_reg_0\,
      I1 => rpuAXIL_bready,
      I2 => ixBlkWrite(1),
      I3 => ixBlkWrite(0),
      I4 => stateRecv(2),
      I5 => stateRecv(1),
      O => \stateRecv[2]_i_4__0_n_0\
    );
\stateRecv[2]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0F2F2F0F0F0FF"
    )
        port map (
      I0 => recvAXIS_tready,
      I1 => stateRecv(0),
      I2 => \recvAXIL_rdata[31]_i_2_n_0\,
      I3 => \stateRecv[2]_i_9_n_0\,
      I4 => stateRecv(1),
      I5 => stateRecv(2),
      O => \stateRecv[2]_i_5__0_n_0\
    );
\stateRecv[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \stateSend[2]_i_11__0_n_0\,
      I1 => stateRecv(2),
      I2 => stateRecv(1),
      I3 => ixBlkWrite(0),
      I4 => \stateRecv[2]_i_10__0_n_0\,
      I5 => ixBlkWrite(1),
      O => \stateRecv[2]_i_6_n_0\
    );
\stateRecv[2]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01400000"
    )
        port map (
      I0 => Q(3),
      I1 => Q(4),
      I2 => Q(2),
      I3 => Q(0),
      I4 => Q(1),
      O => \stateRecv[2]_i_7__0_n_0\
    );
\stateRecv[2]_i_8__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00084240"
    )
        port map (
      I0 => Q(0),
      I1 => Q(2),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(3),
      O => recvAXIS_tready
    );
\stateRecv[2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFBFFFFFF"
    )
        port map (
      I0 => \sendStrbToStart_i_5__0_n_0\,
      I1 => stateRecv(0),
      I2 => ixBlkWrite(0),
      I3 => \^axil_bvalid_sig_reg_0\,
      I4 => rpuAXIL_bready,
      I5 => ixBlkWrite(1),
      O => \stateRecv[2]_i_9_n_0\
    );
\stateRecv_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateRecv[2]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \stateRecv[0]_i_1__0_n_0\,
      Q => stateRecv(0)
    );
\stateRecv_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateRecv[2]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \stateRecv[1]_i_1__0_n_0\,
      Q => stateRecv(1)
    );
\stateRecv_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateRecv[2]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \stateRecv[2]_i_2__0_n_0\,
      Q => stateRecv(2)
    );
\stateSend[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAA002A002A002A"
    )
        port map (
      I0 => \stateSend[2]_i_9__0_n_0\,
      I1 => stateSend(2),
      I2 => stateSend(1),
      I3 => stateSend(0),
      I4 => stateTo(1),
      I5 => stateTo(0),
      O => \stateSend[0]_i_1__0_n_0\
    );
\stateSend[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCCCC0CCCC40"
    )
        port map (
      I0 => sendStrbToStart0,
      I1 => \stateSend[2]_i_9__0_n_0\,
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      I5 => \stateSend[2]_i_10__0_n_0\,
      O => \stateSend[1]_i_1__0_n_0\
    );
\stateSend[2]_i_10__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateTo(1),
      I1 => stateTo(0),
      O => \stateSend[2]_i_10__0_n_0\
    );
\stateSend[2]_i_11__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \stateSend[2]_i_16__0_n_0\,
      I1 => \stateSend[2]_i_17__0_n_0\,
      I2 => \stateSend[2]_i_18__0_n_0\,
      I3 => \stateSend[2]_i_19__0_n_0\,
      O => \stateSend[2]_i_11__0_n_0\
    );
\stateSend[2]_i_13__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcnt_reg(30),
      O => \stateSend[2]_i_13__0_n_0\
    );
\stateSend[2]_i_14__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => wordcnt_reg(28),
      I1 => wordcnt_reg(29),
      I2 => wordcnt_reg(27),
      O => \stateSend[2]_i_14__0_n_0\
    );
\stateSend[2]_i_15__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => wordcnt_reg(25),
      I1 => wordcnt_reg(26),
      I2 => wordcnt_reg(24),
      O => \stateSend[2]_i_15__0_n_0\
    );
\stateSend[2]_i_16__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFBFF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[5]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[6]\,
      I2 => p_0_in(1),
      I3 => p_0_in(0),
      I4 => \stateSend[2]_i_28__0_n_0\,
      O => \stateSend[2]_i_16__0_n_0\
    );
\stateSend[2]_i_17__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[13]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[4]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[14]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[15]\,
      I4 => \stateSend[2]_i_29__0_n_0\,
      O => \stateSend[2]_i_17__0_n_0\
    );
\stateSend[2]_i_18__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[25]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[30]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[19]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[21]\,
      I4 => \stateSend[2]_i_30__0_n_0\,
      O => \stateSend[2]_i_18__0_n_0\
    );
\stateSend[2]_i_19__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFBFFF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[7]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[0]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[16]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[18]\,
      I4 => \stateSend[2]_i_31__0_n_0\,
      O => \stateSend[2]_i_19__0_n_0\
    );
\stateSend[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF8B00"
    )
        port map (
      I0 => \stateSend[2]_i_3__0_n_0\,
      I1 => \stateSend[2]_i_4__0_n_0\,
      I2 => \stateSend[2]_i_5__0_n_0\,
      I3 => \stateSend[2]_i_6__0_n_0\,
      I4 => \stateSend[2]_i_7__0_n_0\,
      I5 => \sendAXIL_rdata[31]_i_1__0_n_0\,
      O => \stateSend[2]_i_1__0_n_0\
    );
\stateSend[2]_i_20__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => wordcnt_reg(22),
      I1 => wordcnt_reg(23),
      I2 => wordcnt_reg(21),
      O => \stateSend[2]_i_20__0_n_0\
    );
\stateSend[2]_i_21__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => wordcnt_reg(19),
      I1 => wordcnt_reg(20),
      I2 => wordcnt_reg(18),
      O => \stateSend[2]_i_21__0_n_0\
    );
\stateSend[2]_i_22__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => wordcnt_reg(16),
      I1 => wordcnt_reg(17),
      I2 => wordcnt_reg(15),
      O => \stateSend[2]_i_22__0_n_0\
    );
\stateSend[2]_i_23__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => wordcnt_reg(13),
      I1 => wordcnt_reg(14),
      I2 => wordcnt_reg(12),
      O => \stateSend[2]_i_23__0_n_0\
    );
\stateSend[2]_i_24__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => wordcnt_reg(10),
      I1 => wordcnt_reg(11),
      I2 => wordcnt_reg(9),
      O => \stateSend[2]_i_24__0_n_0\
    );
\stateSend[2]_i_25__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => wordcnt_reg(7),
      I1 => wordcnt_reg(8),
      I2 => wordcnt_reg(6),
      O => \stateSend[2]_i_25__0_n_0\
    );
\stateSend[2]_i_26__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00101101"
    )
        port map (
      I0 => wordcnt_reg(4),
      I1 => wordcnt_reg(5),
      I2 => \recvAXIS_tlast_sig_reg_i_3__0_0\(2),
      I3 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I4 => wordcnt_reg(3),
      O => \stateSend[2]_i_26__0_n_0\
    );
\stateSend[2]_i_27__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000002D00002D"
    )
        port map (
      I0 => \recvAXIS_tlast_sig_reg_i_3__0_0\(0),
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => wordcnt_reg(0),
      I3 => wordcnt_reg(1),
      I4 => len(1),
      I5 => wordcnt_reg(2),
      O => \stateSend[2]_i_27__0_n_0\
    );
\stateSend[2]_i_28__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[8]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[11]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[12]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[1]\,
      O => \stateSend[2]_i_28__0_n_0\
    );
\stateSend[2]_i_29__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[26]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[24]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[31]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[29]\,
      O => \stateSend[2]_i_29__0_n_0\
    );
\stateSend[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCCCCCCCC0C080"
    )
        port map (
      I0 => sendStrbToStart0,
      I1 => \stateSend[2]_i_9__0_n_0\,
      I2 => stateSend(2),
      I3 => stateSend(1),
      I4 => stateSend(0),
      I5 => \stateSend[2]_i_10__0_n_0\,
      O => \stateSend[2]_i_2__0_n_0\
    );
\stateSend[2]_i_30__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[22]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[20]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[17]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[9]\,
      O => \stateSend[2]_i_30__0_n_0\
    );
\stateSend[2]_i_31__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => \AXIL_wdata_sig_reg_n_0_[10]\,
      I1 => \AXIL_wdata_sig_reg_n_0_[23]\,
      I2 => \AXIL_wdata_sig_reg_n_0_[28]\,
      I3 => \AXIL_wdata_sig_reg_n_0_[27]\,
      O => \stateSend[2]_i_31__0_n_0\
    );
\stateSend[2]_i_32__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rxlen(0),
      I1 => \rpuAXIL_rdata[31]_INST_0_i_1_n_0\,
      I2 => \recvAXIS_tlast_sig_reg_i_3__0_0\(1),
      O => len(1)
    );
\stateSend[2]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^axil_arready\,
      I1 => rpuAXIL_arvalid,
      I2 => AXIL_araddr_sig(5),
      I3 => AXIL_araddr_sig(4),
      O => \stateSend[2]_i_3__0_n_0\
    );
\stateSend[2]_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      I2 => stateSend(0),
      O => \stateSend[2]_i_4__0_n_0\
    );
\stateSend[2]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFFFFFF"
    )
        port map (
      I0 => ixBlkWrite(0),
      I1 => ixBlkWrite(1),
      I2 => \^axil_bvalid_sig_reg_0\,
      I3 => rpuAXIL_bready,
      I4 => \stateSend[2]_i_11__0_n_0\,
      O => \stateSend[2]_i_5__0_n_0\
    );
\stateSend[2]_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      O => \stateSend[2]_i_6__0_n_0\
    );
\stateSend[2]_i_7__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => stateSend(2),
      I1 => \sendStrbToStart_i_4__0_n_0\,
      O => \stateSend[2]_i_7__0_n_0\
    );
\stateSend[2]_i_9__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2616062E"
    )
        port map (
      I0 => Q(3),
      I1 => Q(4),
      I2 => Q(2),
      I3 => Q(0),
      I4 => Q(1),
      O => \stateSend[2]_i_9__0_n_0\
    );
\stateSend_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSend[2]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \stateSend[0]_i_1__0_n_0\,
      Q => stateSend(0)
    );
\stateSend_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSend[2]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \stateSend[1]_i_1__0_n_0\,
      Q => stateSend(1)
    );
\stateSend_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSend[2]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \stateSend[2]_i_2__0_n_0\,
      Q => stateSend(2)
    );
\stateSend_reg[2]_i_12__0\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \stateSend_reg[2]_i_12__0_n_0\,
      CO(6) => \stateSend_reg[2]_i_12__0_n_1\,
      CO(5) => \stateSend_reg[2]_i_12__0_n_2\,
      CO(4) => \stateSend_reg[2]_i_12__0_n_3\,
      CO(3) => \stateSend_reg[2]_i_12__0_n_4\,
      CO(2) => \stateSend_reg[2]_i_12__0_n_5\,
      CO(1) => \stateSend_reg[2]_i_12__0_n_6\,
      CO(0) => \stateSend_reg[2]_i_12__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_stateSend_reg[2]_i_12__0_O_UNCONNECTED\(7 downto 0),
      S(7) => \stateSend[2]_i_20__0_n_0\,
      S(6) => \stateSend[2]_i_21__0_n_0\,
      S(5) => \stateSend[2]_i_22__0_n_0\,
      S(4) => \stateSend[2]_i_23__0_n_0\,
      S(3) => \stateSend[2]_i_24__0_n_0\,
      S(2) => \stateSend[2]_i_25__0_n_0\,
      S(1) => \stateSend[2]_i_26__0_n_0\,
      S(0) => \stateSend[2]_i_27__0_n_0\
    );
\stateSend_reg[2]_i_8__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \stateSend_reg[2]_i_12__0_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_stateSend_reg[2]_i_8__0_CO_UNCONNECTED\(7 downto 3),
      CO(2) => sendStrbToStart0,
      CO(1) => \stateSend_reg[2]_i_8__0_n_6\,
      CO(0) => \stateSend_reg[2]_i_8__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_stateSend_reg[2]_i_8__0_O_UNCONNECTED\(7 downto 0),
      S(7 downto 3) => B"00000",
      S(2) => \stateSend[2]_i_13__0_n_0\,
      S(1) => \stateSend[2]_i_14__0_n_0\,
      S(0) => \stateSend[2]_i_15__0_n_0\
    );
\stateTo[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => req,
      I1 => stateTo(1),
      I2 => stateTo(0),
      O => \stateTo[0]_i_1__0_n_0\
    );
\stateTo[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55FD57FF55FD55FF"
    )
        port map (
      I0 => req,
      I1 => sendStrbToStart_reg_n_0,
      I2 => recvStrbToStart_reg_n_0,
      I3 => stateTo(1),
      I4 => stateTo(0),
      I5 => \stateTo[1]_i_4__0_n_0\,
      O => \stateTo[1]_i_1__0_n_0\
    );
\stateTo[1]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"080808A8"
    )
        port map (
      I0 => req,
      I1 => stateTo(0),
      I2 => stateTo(1),
      I3 => recvStrbToStop_reg_n_0,
      I4 => sendStrbToStop_reg_n_0,
      O => \stateTo[1]_i_2__0_n_0\
    );
\stateTo[1]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0B177630"
    )
        port map (
      I0 => Q(0),
      I1 => Q(2),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(3),
      O => req
    );
\stateTo[1]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEFEEEEFE"
    )
        port map (
      I0 => sendStrbToStop_reg_n_0,
      I1 => recvStrbToStop_reg_n_0,
      I2 => i(15),
      I3 => \i[15]_i_4__0_n_0\,
      I4 => i(14),
      I5 => \stateTo[1]_i_5__0_n_0\,
      O => \stateTo[1]_i_4__0_n_0\
    );
\stateTo[1]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFDFF7F"
    )
        port map (
      I0 => i(12),
      I1 => \i[12]_i_2__0_n_0\,
      I2 => i(9),
      I3 => \stateTo[1]_i_6__0_n_0\,
      I4 => i(10),
      O => \stateTo[1]_i_5__0_n_0\
    );
\stateTo[1]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFEF"
    )
        port map (
      I0 => \i[9]_i_2__4_n_0\,
      I1 => i(7),
      I2 => i(11),
      I3 => i(8),
      I4 => i(6),
      I5 => i(13),
      O => \stateTo[1]_i_6__0_n_0\
    );
\stateTo_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateTo[1]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \stateTo[0]_i_1__0_n_0\,
      Q => stateTo(0)
    );
\stateTo_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateTo[1]_i_1__0_n_0\,
      CLR => \sendAXIL_rdata_reg[0]_0\(0),
      D => \stateTo[1]_i_2__0_n_0\,
      Q => stateTo(1)
    );
\tixVBuffer[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(0),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[0][7]\(0)
    );
\tixVBuffer[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(1),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[0][7]\(1)
    );
\tixVBuffer[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(2),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[0][7]\(2)
    );
\tixVBuffer[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(3),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[0][7]\(3)
    );
\tixVBuffer[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(4),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[0][7]\(4)
    );
\tixVBuffer[5]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(5),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[0][7]\(5)
    );
\tixVBuffer[6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(6),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[0][7]\(6)
    );
\tixVBuffer[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBuffer_reg[7]\(7),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[0][7]\(7)
    );
\tixVCommand[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(0),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[2][7]\(0)
    );
\tixVCommand[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(1),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[2][7]\(1)
    );
\tixVCommand[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(2),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[2][7]\(2)
    );
\tixVCommand[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(3),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[2][7]\(3)
    );
\tixVCommand[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(4),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[2][7]\(4)
    );
\tixVCommand[5]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(5),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[2][7]\(5)
    );
\tixVCommand[6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(6),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[2][7]\(6)
    );
\tixVCommand[7]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVBufxfop_reg[7]\(7),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[2][7]\(7)
    );
\tixVController[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_0\(0),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[1][7]\(0)
    );
\tixVController[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_0\(1),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[1][7]\(1)
    );
\tixVController[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_0\(2),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[1][7]\(2)
    );
\tixVController[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_0\(3),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[1][7]\(3)
    );
\tixVController[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_0\(4),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[1][7]\(4)
    );
\tixVController[5]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_0\(5),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[1][7]\(5)
    );
\tixVController[6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_0\(6),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[1][7]\(6)
    );
\tixVController[7]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \tixVController_reg[7]_0\(7),
      I1 => \^stateop_reg[1]\,
      O => \opbuf_reg[1][7]\(7)
    );
\txAXIS_tdata[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0020AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[0]\,
      I2 => \txAXIS_tdata_reg[0]_0\,
      I3 => Q(3),
      I4 => \txAXIS_tdata_reg[0]_1\,
      I5 => \txAXIS_tdata_reg[0]_2\,
      O => \stateOp_reg[1]_3\(0)
    );
\txAXIS_tdata[10]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888A88888888"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[10]\,
      I2 => \txAXIS_tdata_reg[10]_0\,
      I3 => \txAXIS_tdata_reg[10]_1\,
      I4 => Q(1),
      I5 => Q(4),
      O => \stateOp_reg[1]_3\(10)
    );
\txAXIS_tdata[11]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000A808AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[11]_1\,
      I2 => Q(4),
      I3 => \txAXIS_tdata_reg[11]_2\,
      I4 => Q(1),
      I5 => \txAXIS_tdata_reg[11]_3\,
      O => \stateOp_reg[1]_3\(11)
    );
\txAXIS_tdata[12]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000002A2AAAA02A2"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[12]\,
      I2 => Q(4),
      I3 => \txAXIS_tdata_reg[12]_0\,
      I4 => Q(1),
      I5 => \txAXIS_tdata_reg[12]_1\,
      O => \stateOp_reg[1]_3\(12)
    );
\txAXIS_tdata[13]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8A8A8888888A88"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[13]\,
      I2 => Q(1),
      I3 => \txAXIS_tdata_reg[13]_0\,
      I4 => Q(4),
      I5 => \txAXIS_tdata_reg[13]_1\,
      O => \stateOp_reg[1]_3\(13)
    );
\txAXIS_tdata[14]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000002A2AAAA02A2"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[14]_1\,
      I2 => Q(4),
      I3 => \txAXIS_tdata_reg[14]_2\,
      I4 => Q(1),
      I5 => \txAXIS_tdata_reg[14]_3\,
      O => \stateOp_reg[1]_3\(14)
    );
\txAXIS_tdata[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"57FF575757575757"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => Q(1),
      I2 => \txAXIS_tdata_reg[15]_3\,
      I3 => \txAXIS_tdata_reg[15]\(0),
      I4 => \txAXIS_tdata_reg[15]\(1),
      I5 => \retbuf_reg[5][5]_0\,
      O => \resid_reg[0]_0\(1)
    );
\txAXIS_tdata[15]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8A8A8888888A88"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[15]_0\,
      I2 => Q(1),
      I3 => \txAXIS_tdata_reg[15]_1\,
      I4 => Q(4),
      I5 => \txAXIS_tdata_reg[15]_2\,
      O => \stateOp_reg[1]_3\(15)
    );
\txAXIS_tdata[17]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000800080008AAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[17]\,
      I2 => \txAXIS_tdata_reg[17]_0\,
      I3 => \txAXIS_tdata_reg[17]_1\,
      I4 => \txAXIS_tdata_reg[17]_2\,
      I5 => \txAXIS_tdata_reg[17]_3\,
      O => \stateOp_reg[1]_3\(16)
    );
\txAXIS_tdata[19]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000A8AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[19]\,
      I2 => \txAXIS_tdata_reg[19]_0\,
      I3 => \txAXIS_tdata_reg[19]_1\,
      I4 => \txAXIS_tdata_reg[17]_1\,
      I5 => \txAXIS_tdata_reg[19]_2\,
      O => \stateOp_reg[1]_3\(17)
    );
\txAXIS_tdata[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00A8AAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[1]\,
      I2 => \txAXIS_tdata_reg[1]_0\,
      I3 => \txAXIS_tdata_reg[1]_1\,
      I4 => \txAXIS_tdata_reg[1]_2\,
      O => \stateOp_reg[1]_3\(1)
    );
\txAXIS_tdata[20]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888A8A8A888A"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[20]\,
      I2 => \txAXIS_tdata_reg[17]_1\,
      I3 => \txAXIS_tdata_reg[20]_0\,
      I4 => \txAXIS_tdata_reg[20]_1\,
      I5 => \txAXIS_tdata_reg[20]_2\,
      O => \stateOp_reg[1]_3\(18)
    );
\txAXIS_tdata[21]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000800080008AAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[21]\,
      I2 => \txAXIS_tdata_reg[21]_0\,
      I3 => \txAXIS_tdata_reg[17]_1\,
      I4 => \txAXIS_tdata_reg[17]_2\,
      I5 => \txAXIS_tdata_reg[21]_1\,
      O => \stateOp_reg[1]_3\(19)
    );
\txAXIS_tdata[22]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00080000AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[22]\,
      I2 => \txAXIS_tdata_reg[22]_0\,
      I3 => Q(1),
      I4 => Q(4),
      I5 => \txAXIS_tdata_reg[22]_1\,
      O => \stateOp_reg[1]_3\(20)
    );
\txAXIS_tdata[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF575757"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => Q(1),
      I2 => \txAXIS_tdata_reg[15]_3\,
      I3 => \txAXIS_tdata_reg[15]\(1),
      I4 => \retbuf_reg[5][5]_0\,
      O => \resid_reg[0]_0\(2)
    );
\txAXIS_tdata[23]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000800080008AAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[23]\,
      I2 => \txAXIS_tdata_reg[23]_0\,
      I3 => \txAXIS_tdata_reg[17]_1\,
      I4 => \txAXIS_tdata_reg[17]_2\,
      I5 => \txAXIS_tdata_reg[23]_1\,
      O => \stateOp_reg[1]_3\(21)
    );
\txAXIS_tdata[24]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000002A2AAAA02A2"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[24]\,
      I2 => Q(4),
      I3 => \txAXIS_tdata_reg[24]_0\,
      I4 => Q(1),
      I5 => \txAXIS_tdata_reg[24]_1\,
      O => \stateOp_reg[1]_3\(22)
    );
\txAXIS_tdata[25]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000002A2AAAA02A2"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[24]\,
      I2 => Q(4),
      I3 => \txAXIS_tdata_reg[25]\,
      I4 => Q(1),
      I5 => \txAXIS_tdata_reg[25]_0\,
      O => \stateOp_reg[1]_3\(23)
    );
\txAXIS_tdata[26]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"888888888888A8AA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[26]\,
      I2 => \txAXIS_tdata_reg[26]_0\,
      I3 => \txAXIS_tdata_reg[26]_1\,
      I4 => \txAXIS_tdata_reg[26]_2\,
      I5 => \txAXIS_tdata_reg[17]_1\,
      O => \stateOp_reg[1]_3\(24)
    );
\txAXIS_tdata[27]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000A8AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[27]\,
      I2 => \txAXIS_tdata_reg[19]_0\,
      I3 => \txAXIS_tdata_reg[27]_0\,
      I4 => \txAXIS_tdata_reg[17]_1\,
      I5 => \txAXIS_tdata_reg[27]_1\,
      O => \stateOp_reg[1]_3\(25)
    );
\txAXIS_tdata[28]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00080000AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[28]\,
      I2 => \txAXIS_tdata_reg[28]_0\,
      I3 => Q(1),
      I4 => Q(4),
      I5 => \txAXIS_tdata_reg[28]_1\,
      O => \stateOp_reg[1]_3\(26)
    );
\txAXIS_tdata[29]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[29]\,
      I2 => Q(1),
      I3 => \txAXIS_tdata_reg[29]_0\,
      O => \stateOp_reg[1]_3\(27)
    );
\txAXIS_tdata[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0020AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[2]\,
      I2 => \txAXIS_tdata_reg[0]_0\,
      I3 => Q(3),
      I4 => \txAXIS_tdata_reg[2]_0\,
      I5 => \txAXIS_tdata_reg[0]_2\,
      O => \stateOp_reg[1]_3\(2)
    );
\txAXIS_tdata[30]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00080000AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[30]_0\,
      I2 => \txAXIS_tdata_reg[30]_1\,
      I3 => Q(1),
      I4 => Q(4),
      I5 => \txAXIS_tdata_reg[30]_2\,
      O => \stateOp_reg[1]_3\(28)
    );
\txAXIS_tdata[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"90FF90FF90FFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata_reg[15]\(0),
      I1 => \txAXIS_tdata_reg[15]\(1),
      I2 => \retbuf_reg[5][5]_0\,
      I3 => \^stateop_reg[1]\,
      I4 => Q(1),
      I5 => \txAXIS_tdata_reg[15]_3\,
      O => \resid_reg[0]_0\(3)
    );
\txAXIS_tdata[31]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000A808AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[31]_0\,
      I2 => \txAXIS_tdata_reg[20]_1\,
      I3 => \txAXIS_tdata_reg[31]_1\,
      I4 => \txAXIS_tdata_reg[17]_1\,
      I5 => \txAXIS_tdata_reg[31]_2\,
      O => \stateOp_reg[1]_3\(29)
    );
\txAXIS_tdata[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000888AAAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[3]\,
      I2 => Q(1),
      I3 => \txAXIS_tdata_reg[3]_0\,
      I4 => \txAXIS_tdata_reg[3]_1\,
      I5 => \txAXIS_tdata_reg[1]_2\,
      O => \stateOp_reg[1]_3\(3)
    );
\txAXIS_tdata[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0020AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[4]\,
      I2 => \txAXIS_tdata_reg[0]_0\,
      I3 => Q(3),
      I4 => \txAXIS_tdata_reg[4]_0\,
      I5 => \txAXIS_tdata_reg[0]_2\,
      O => \stateOp_reg[1]_3\(4)
    );
\txAXIS_tdata[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000888AAAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[5]\,
      I2 => Q(1),
      I3 => \txAXIS_tdata_reg[5]_0\,
      I4 => \txAXIS_tdata_reg[5]_1\,
      I5 => \txAXIS_tdata_reg[1]_2\,
      O => \stateOp_reg[1]_3\(5)
    );
\txAXIS_tdata[6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0800AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[0]_0\,
      I2 => Q(3),
      I3 => \txAXIS_tdata_reg[6]\,
      I4 => \txAXIS_tdata_reg[6]_0\,
      I5 => \txAXIS_tdata_reg[0]_2\,
      O => \stateOp_reg[1]_3\(6)
    );
\txAXIS_tdata[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABAAAAAAAAAAAA"
    )
        port map (
      I0 => \txAXIS_tdata[7]_i_3__0_n_0\,
      I1 => \txAXIS_tdata_reg[7]_0\,
      I2 => \txAXIS_tdata_reg[7]_1\,
      I3 => Q(3),
      I4 => Q(4),
      I5 => Q(2),
      O => \resid_reg[0]_0\(0)
    );
\txAXIS_tdata[7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000888AAAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[7]_2\,
      I2 => Q(1),
      I3 => \txAXIS_tdata_reg[7]_3\,
      I4 => \txAXIS_tdata_reg[7]_4\,
      I5 => \txAXIS_tdata_reg[1]_2\,
      O => \stateOp_reg[1]_3\(7)
    );
\txAXIS_tdata[7]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01000014FFFFFFFF"
    )
        port map (
      I0 => Q(1),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => \^stateop_reg[1]\,
      O => \txAXIS_tdata[7]_i_3__0_n_0\
    );
\txAXIS_tdata[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000A808AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[8]\,
      I2 => Q(4),
      I3 => \txAXIS_tdata_reg[8]_0\,
      I4 => Q(1),
      I5 => \txAXIS_tdata_reg[8]_1\,
      O => \stateOp_reg[1]_3\(8)
    );
\txAXIS_tdata[9]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000A808AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => \txAXIS_tdata_reg[9]\,
      I2 => Q(4),
      I3 => \txAXIS_tdata_reg[9]_0\,
      I4 => Q(1),
      I5 => \txAXIS_tdata_reg[9]_1\,
      O => \stateOp_reg[1]_3\(9)
    );
\txlen[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => \^tixvcontroller_reg[0]\(0),
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(3),
      I4 => Q(0),
      I5 => Q(4),
      O => \stateOp_reg[2]\(1)
    );
\validCrc_sig_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAABA"
    )
        port map (
      I0 => \crc_imd_reg[11]\,
      I1 => stateOp_reg_4,
      I2 => stateRecv(2),
      I3 => stateRecv(1),
      I4 => stateRecv(0),
      O => AXIS_tvalid
    );
\validCrc_sig_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAABAAAAAAAAAA"
    )
        port map (
      I0 => crcAXIS_tlast_sig_reg_2,
      I1 => stateRecv(0),
      I2 => stateRecv(1),
      I3 => stateRecv(2),
      I4 => stateOp_reg_4,
      I5 => \^recvaxis_tlast\,
      O => AXIS_tlast
    );
\wdone_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"777F777F777F0000"
    )
        port map (
      I0 => \^axil_bvalid_sig_reg_0\,
      I1 => rpuAXIL_bready,
      I2 => \^axil_awready_sig_reg_0\,
      I3 => awdone_reg_n_0,
      I4 => \^axil_wready_sig_reg_0\,
      I5 => wdone_reg_n_0,
      O => \wdone_i_1__1_n_0\
    );
wdone_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \wdone_i_1__1_n_0\,
      Q => wdone_reg_n_0,
      R => \sendAXIL_rdata_reg[0]_0\(0)
    );
\wordcntCrcLast[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[15]_i_2_n_0\
    );
\wordcntCrcLast[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[15]_i_3_n_0\
    );
\wordcntCrcLast[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[15]_i_4_n_0\
    );
\wordcntCrcLast[15]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[15]_i_5_n_0\
    );
\wordcntCrcLast[15]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[15]_i_6_n_0\
    );
\wordcntCrcLast[15]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[15]_i_7_n_0\
    );
\wordcntCrcLast[15]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[15]_i_8_n_0\
    );
\wordcntCrcLast[15]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[15]_i_9_n_0\
    );
\wordcntCrcLast[23]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[23]_i_2_n_0\
    );
\wordcntCrcLast[23]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[23]_i_3_n_0\
    );
\wordcntCrcLast[23]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[23]_i_4_n_0\
    );
\wordcntCrcLast[23]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[23]_i_5_n_0\
    );
\wordcntCrcLast[23]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[23]_i_6_n_0\
    );
\wordcntCrcLast[23]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[23]_i_7_n_0\
    );
\wordcntCrcLast[23]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[23]_i_8_n_0\
    );
\wordcntCrcLast[23]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[23]_i_9_n_0\
    );
\wordcntCrcLast[24]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[24]_i_2__0_n_0\
    );
\wordcntCrcLast[7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[7]_i_10_n_0\
    );
\wordcntCrcLast[7]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \lastAXIS_tkeep_reg[3]\,
      I1 => \^stateop_reg[1]\,
      O => \wordcntCrcLast[7]_i_11_n_0\
    );
\wordcntCrcLast[7]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => lenRet1,
      I1 => \^stateop_reg[1]\,
      O => \wordcntCrcLast[7]_i_12_n_0\
    );
\wordcntCrcLast[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => lenRet1,
      I1 => \^stateop_reg[1]\,
      O => \wordcntCrcLast[7]_i_2_n_0\
    );
\wordcntCrcLast[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \lastAXIS_tkeep_reg[3]\,
      I1 => \^stateop_reg[1]\,
      O => \wordcntCrcLast[7]_i_3_n_0\
    );
\wordcntCrcLast[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => lenRet1,
      I1 => \^stateop_reg[1]\,
      O => \wordcntCrcLast[7]_i_4_n_0\
    );
\wordcntCrcLast[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[7]_i_5_n_0\
    );
\wordcntCrcLast[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[7]_i_6_n_0\
    );
\wordcntCrcLast[7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[7]_i_7_n_0\
    );
\wordcntCrcLast[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp[0]_i_2__0_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(2),
      O => \wordcntCrcLast[7]_i_8_n_0\
    );
\wordcntCrcLast[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => lenRet1,
      I1 => \^stateop_reg[1]\,
      O => \wordcntCrcLast[7]_i_9_n_0\
    );
\wordcntCrcLast_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcntCrcLast_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcntCrcLast_reg[15]_i_1_n_0\,
      CO(6) => \wordcntCrcLast_reg[15]_i_1_n_1\,
      CO(5) => \wordcntCrcLast_reg[15]_i_1_n_2\,
      CO(4) => \wordcntCrcLast_reg[15]_i_1_n_3\,
      CO(3) => \wordcntCrcLast_reg[15]_i_1_n_4\,
      CO(2) => \wordcntCrcLast_reg[15]_i_1_n_5\,
      CO(1) => \wordcntCrcLast_reg[15]_i_1_n_6\,
      CO(0) => \wordcntCrcLast_reg[15]_i_1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \out\(15 downto 8),
      S(7) => \wordcntCrcLast[15]_i_2_n_0\,
      S(6) => \wordcntCrcLast[15]_i_3_n_0\,
      S(5) => \wordcntCrcLast[15]_i_4_n_0\,
      S(4) => \wordcntCrcLast[15]_i_5_n_0\,
      S(3) => \wordcntCrcLast[15]_i_6_n_0\,
      S(2) => \wordcntCrcLast[15]_i_7_n_0\,
      S(1) => \wordcntCrcLast[15]_i_8_n_0\,
      S(0) => \wordcntCrcLast[15]_i_9_n_0\
    );
\wordcntCrcLast_reg[23]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcntCrcLast_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcntCrcLast_reg[23]_i_1_n_0\,
      CO(6) => \wordcntCrcLast_reg[23]_i_1_n_1\,
      CO(5) => \wordcntCrcLast_reg[23]_i_1_n_2\,
      CO(4) => \wordcntCrcLast_reg[23]_i_1_n_3\,
      CO(3) => \wordcntCrcLast_reg[23]_i_1_n_4\,
      CO(2) => \wordcntCrcLast_reg[23]_i_1_n_5\,
      CO(1) => \wordcntCrcLast_reg[23]_i_1_n_6\,
      CO(0) => \wordcntCrcLast_reg[23]_i_1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \out\(23 downto 16),
      S(7) => \wordcntCrcLast[23]_i_2_n_0\,
      S(6) => \wordcntCrcLast[23]_i_3_n_0\,
      S(5) => \wordcntCrcLast[23]_i_4_n_0\,
      S(4) => \wordcntCrcLast[23]_i_5_n_0\,
      S(3) => \wordcntCrcLast[23]_i_6_n_0\,
      S(2) => \wordcntCrcLast[23]_i_7_n_0\,
      S(1) => \wordcntCrcLast[23]_i_8_n_0\,
      S(0) => \wordcntCrcLast[23]_i_9_n_0\
    );
\wordcntCrcLast_reg[24]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcntCrcLast_reg[23]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 0) => \NLW_wordcntCrcLast_reg[24]_i_1_CO_UNCONNECTED\(7 downto 0),
      DI(7 downto 0) => B"00000000",
      O(7 downto 1) => \NLW_wordcntCrcLast_reg[24]_i_1_O_UNCONNECTED\(7 downto 1),
      O(0) => \out\(24),
      S(7 downto 1) => B"0000000",
      S(0) => \wordcntCrcLast[24]_i_2__0_n_0\
    );
\wordcntCrcLast_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \wordcntCrcLast_reg[7]_i_1_n_0\,
      CO(6) => \wordcntCrcLast_reg[7]_i_1_n_1\,
      CO(5) => \wordcntCrcLast_reg[7]_i_1_n_2\,
      CO(4) => \wordcntCrcLast_reg[7]_i_1_n_3\,
      CO(3) => \wordcntCrcLast_reg[7]_i_1_n_4\,
      CO(2) => \wordcntCrcLast_reg[7]_i_1_n_5\,
      CO(1) => \wordcntCrcLast_reg[7]_i_1_n_6\,
      CO(0) => \wordcntCrcLast_reg[7]_i_1_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3) => \wordcntCrcLast[7]_i_2_n_0\,
      DI(2) => '0',
      DI(1) => \wordcntCrcLast[7]_i_3_n_0\,
      DI(0) => \wordcntCrcLast[7]_i_4_n_0\,
      O(7 downto 0) => \out\(7 downto 0),
      S(7) => \wordcntCrcLast[7]_i_5_n_0\,
      S(6) => \wordcntCrcLast[7]_i_6_n_0\,
      S(5) => \wordcntCrcLast[7]_i_7_n_0\,
      S(4) => \wordcntCrcLast[7]_i_8_n_0\,
      S(3) => \wordcntCrcLast[7]_i_9_n_0\,
      S(2) => \wordcntCrcLast[7]_i_10_n_0\,
      S(1) => \wordcntCrcLast[7]_i_11_n_0\,
      S(0) => \wordcntCrcLast[7]_i_12_n_0\
    );
\wordcntLast[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E000"
    )
        port map (
      I0 => lenRet1,
      I1 => Q(0),
      I2 => \txlen_reg[0]\,
      I3 => \^stateop_reg[1]\,
      O => \stateOp_reg[2]\(0)
    );
\wordcntLast[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000002000000020"
    )
        port map (
      I0 => \wordcntLast_reg[1]\,
      I1 => Q(4),
      I2 => \^stateop_reg[1]\,
      I3 => Q(3),
      I4 => Q(2),
      I5 => \lastAXIS_tkeep_reg[3]\,
      O => \stateOp_reg[4]_0\(0)
    );
\wordcntLast[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555D555555D5D575"
    )
        port map (
      I0 => \^stateop_reg[1]\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(3),
      I4 => Q(0),
      I5 => Q(4),
      O => \^stateop_reg[2]_1\
    );
\wordcntLast[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => \^tixvcontroller_reg[0]\(2),
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(3),
      I4 => Q(0),
      I5 => Q(4),
      O => \stateOp_reg[2]\(2)
    );
\wordcnt[0]__0_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \recvAXIL_rdata[31]_i_2_n_0\,
      I1 => \sendAXIL_rdata_reg[0]_0\(0),
      I2 => p_1_in0,
      O => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt[0]__0_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000400"
    )
        port map (
      I0 => \sendAXIL_rdata_reg[0]_0\(0),
      I1 => p_1_in0,
      I2 => \^recvaxis_tlast\,
      I3 => \wordcnt[0]__0_i_4__0_n_0\,
      I4 => stateRecv(0),
      I5 => stateRecv(1),
      O => wordcnt0
    );
\wordcnt[0]__0_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0204500000000000"
    )
        port map (
      I0 => Q(3),
      I1 => Q(1),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      I5 => stateRecv(2),
      O => \wordcnt[0]__0_i_4__0_n_0\
    );
\wordcnt[0]__0_i_5__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wordcnt_reg[0]__0_n_0\,
      O => \wordcnt[0]__0_i_5__0_n_0\
    );
\wordcnt[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[0]_0\(0),
      I2 => \wordcnt[0]_i_4__0_n_0\,
      I3 => AXIL_araddr_sig(5),
      I4 => AXIL_araddr_sig(4),
      I5 => strbRead,
      O => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt[0]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wordcnt_reg[0]_0\(0),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(0)
    );
\wordcnt[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => \sendAXIL_rdata[31]_i_5_n_0\,
      I1 => \sendAXIL_rdata_reg[0]_0\(0),
      I2 => \stateSend[2]_i_6__0_n_0\,
      I3 => stateSend(0),
      I4 => sendStrbToStart0,
      I5 => \stateSend[2]_i_3__0_n_0\,
      O => \wordcnt[0]_i_2__0_n_0\
    );
\wordcnt[0]_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => stateSend(2),
      I1 => stateSend(1),
      I2 => stateSend(0),
      O => \wordcnt[0]_i_4__0_n_0\
    );
\wordcnt[0]_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => rpuAXIL_arvalid,
      I1 => \^axil_arready\,
      O => strbRead
    );
\wordcnt[0]_i_6__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcnt_reg(0),
      O => \wordcnt[0]_i_6__0_n_0\
    );
\wordcnt[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(9),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(10)
    );
\wordcnt[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(10),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(11)
    );
\wordcnt[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(11),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(12)
    );
\wordcnt[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(12),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(13)
    );
\wordcnt[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(13),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(14)
    );
\wordcnt[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(14),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(15)
    );
\wordcnt[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(15),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(16)
    );
\wordcnt[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(16),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(17)
    );
\wordcnt[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(17),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(18)
    );
\wordcnt[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(18),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(19)
    );
\wordcnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(0),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(1)
    );
\wordcnt[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(19),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(20)
    );
\wordcnt[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(20),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(21)
    );
\wordcnt[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(21),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(22)
    );
\wordcnt[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(22),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(23)
    );
\wordcnt[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(23),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(24)
    );
\wordcnt[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(24),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(25)
    );
\wordcnt[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(25),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(26)
    );
\wordcnt[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(26),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(27)
    );
\wordcnt[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(27),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(28)
    );
\wordcnt[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(28),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(29)
    );
\wordcnt[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(1),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(2)
    );
\wordcnt[30]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABBAABAAFFFFFFFF"
    )
        port map (
      I0 => \wordcnt[30]_i_3__0_n_0\,
      I1 => \wordcnt_reg[0]_1\,
      I2 => Q(1),
      I3 => Q(0),
      I4 => \wordcnt[30]_i_5__0_n_0\,
      I5 => \^stateop_reg[1]\,
      O => \stateOp_reg[1]_1\(0)
    );
\wordcnt[30]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(29),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(30)
    );
\wordcnt[30]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000540555555555"
    )
        port map (
      I0 => Q(4),
      I1 => \wordcnt[30]_i_5__0_n_0\,
      I2 => Q(2),
      I3 => Q(0),
      I4 => crcAXIS_tlast_sig_reg_0,
      I5 => \wordcnt[30]_i_8__0_n_0\,
      O => \wordcnt[30]_i_3__0_n_0\
    );
\wordcnt[30]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => stateRecv(0),
      I1 => stateRecv(1),
      I2 => stateRecv(2),
      I3 => CO(0),
      O => \wordcnt[30]_i_5__0_n_0\
    );
\wordcnt[30]_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DD0FFFFFFFFFFFFF"
    )
        port map (
      I0 => txAXIS_tready,
      I1 => CO(0),
      I2 => Q(2),
      I3 => Q(0),
      I4 => Q(1),
      I5 => Q(3),
      O => \wordcnt[30]_i_8__0_n_0\
    );
\wordcnt[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(2),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(3)
    );
\wordcnt[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(3),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(4)
    );
\wordcnt[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(4),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(5)
    );
\wordcnt[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(5),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(6)
    );
\wordcnt[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(6),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(7)
    );
\wordcnt[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(7),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(8)
    );
\wordcnt[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txlast1(8),
      I1 => \^stateop_reg[2]_1\,
      O => \wordcnt_reg[30]_0\(9)
    );
\wordcnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[0]_i_3__0_n_15\,
      Q => wordcnt_reg(0),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[0]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3__0_n_15\,
      Q => \wordcnt_reg[0]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[0]__0_i_3__0\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[0]__0_i_3__0_n_0\,
      CO(6) => \wordcnt_reg[0]__0_i_3__0_n_1\,
      CO(5) => \wordcnt_reg[0]__0_i_3__0_n_2\,
      CO(4) => \wordcnt_reg[0]__0_i_3__0_n_3\,
      CO(3) => \wordcnt_reg[0]__0_i_3__0_n_4\,
      CO(2) => \wordcnt_reg[0]__0_i_3__0_n_5\,
      CO(1) => \wordcnt_reg[0]__0_i_3__0_n_6\,
      CO(0) => \wordcnt_reg[0]__0_i_3__0_n_7\,
      DI(7 downto 0) => B"00000001",
      O(7) => \wordcnt_reg[0]__0_i_3__0_n_8\,
      O(6) => \wordcnt_reg[0]__0_i_3__0_n_9\,
      O(5) => \wordcnt_reg[0]__0_i_3__0_n_10\,
      O(4) => \wordcnt_reg[0]__0_i_3__0_n_11\,
      O(3) => \wordcnt_reg[0]__0_i_3__0_n_12\,
      O(2) => \wordcnt_reg[0]__0_i_3__0_n_13\,
      O(1) => \wordcnt_reg[0]__0_i_3__0_n_14\,
      O(0) => \wordcnt_reg[0]__0_i_3__0_n_15\,
      S(7) => \wordcnt_reg[7]__0_n_0\,
      S(6) => \wordcnt_reg[6]__0_n_0\,
      S(5) => \wordcnt_reg[5]__0_n_0\,
      S(4) => \wordcnt_reg[4]__0_n_0\,
      S(3) => \wordcnt_reg[3]__0_n_0\,
      S(2) => \wordcnt_reg[2]__0_n_0\,
      S(1) => \wordcnt_reg[1]__0_n_0\,
      S(0) => \wordcnt[0]__0_i_5__0_n_0\
    );
\wordcnt_reg[0]_i_3__0\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[0]_i_3__0_n_0\,
      CO(6) => \wordcnt_reg[0]_i_3__0_n_1\,
      CO(5) => \wordcnt_reg[0]_i_3__0_n_2\,
      CO(4) => \wordcnt_reg[0]_i_3__0_n_3\,
      CO(3) => \wordcnt_reg[0]_i_3__0_n_4\,
      CO(2) => \wordcnt_reg[0]_i_3__0_n_5\,
      CO(1) => \wordcnt_reg[0]_i_3__0_n_6\,
      CO(0) => \wordcnt_reg[0]_i_3__0_n_7\,
      DI(7 downto 0) => B"00000001",
      O(7) => \wordcnt_reg[0]_i_3__0_n_8\,
      O(6) => \wordcnt_reg[0]_i_3__0_n_9\,
      O(5) => \wordcnt_reg[0]_i_3__0_n_10\,
      O(4) => \wordcnt_reg[0]_i_3__0_n_11\,
      O(3) => \wordcnt_reg[0]_i_3__0_n_12\,
      O(2) => \wordcnt_reg[0]_i_3__0_n_13\,
      O(1) => \wordcnt_reg[0]_i_3__0_n_14\,
      O(0) => \wordcnt_reg[0]_i_3__0_n_15\,
      S(7 downto 1) => wordcnt_reg(7 downto 1),
      S(0) => \wordcnt[0]_i_6__0_n_0\
    );
\wordcnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[8]_i_1__0_n_13\,
      Q => wordcnt_reg(10),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[10]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1__0_n_13\,
      Q => \wordcnt_reg[10]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[8]_i_1__0_n_12\,
      Q => wordcnt_reg(11),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[11]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1__0_n_12\,
      Q => \wordcnt_reg[11]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[8]_i_1__0_n_11\,
      Q => wordcnt_reg(12),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[12]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1__0_n_11\,
      Q => \wordcnt_reg[12]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[8]_i_1__0_n_10\,
      Q => wordcnt_reg(13),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[13]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1__0_n_10\,
      Q => \wordcnt_reg[13]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[8]_i_1__0_n_9\,
      Q => wordcnt_reg(14),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[14]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1__0_n_9\,
      Q => \wordcnt_reg[14]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[8]_i_1__0_n_8\,
      Q => wordcnt_reg(15),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[15]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1__0_n_8\,
      Q => \wordcnt_reg[15]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[16]_i_1__0_n_15\,
      Q => wordcnt_reg(16),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[16]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1__0_n_15\,
      Q => \wordcnt_reg[16]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[16]__0_i_1__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[8]__0_i_1__0_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[16]__0_i_1__0_n_0\,
      CO(6) => \wordcnt_reg[16]__0_i_1__0_n_1\,
      CO(5) => \wordcnt_reg[16]__0_i_1__0_n_2\,
      CO(4) => \wordcnt_reg[16]__0_i_1__0_n_3\,
      CO(3) => \wordcnt_reg[16]__0_i_1__0_n_4\,
      CO(2) => \wordcnt_reg[16]__0_i_1__0_n_5\,
      CO(1) => \wordcnt_reg[16]__0_i_1__0_n_6\,
      CO(0) => \wordcnt_reg[16]__0_i_1__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \wordcnt_reg[16]__0_i_1__0_n_8\,
      O(6) => \wordcnt_reg[16]__0_i_1__0_n_9\,
      O(5) => \wordcnt_reg[16]__0_i_1__0_n_10\,
      O(4) => \wordcnt_reg[16]__0_i_1__0_n_11\,
      O(3) => \wordcnt_reg[16]__0_i_1__0_n_12\,
      O(2) => \wordcnt_reg[16]__0_i_1__0_n_13\,
      O(1) => \wordcnt_reg[16]__0_i_1__0_n_14\,
      O(0) => \wordcnt_reg[16]__0_i_1__0_n_15\,
      S(7) => \wordcnt_reg[23]__0_n_0\,
      S(6) => \wordcnt_reg[22]__0_n_0\,
      S(5) => \wordcnt_reg[21]__0_n_0\,
      S(4) => \wordcnt_reg[20]__0_n_0\,
      S(3) => \wordcnt_reg[19]__0_n_0\,
      S(2) => \wordcnt_reg[18]__0_n_0\,
      S(1) => \wordcnt_reg[17]__0_n_0\,
      S(0) => \wordcnt_reg[16]__0_n_0\
    );
\wordcnt_reg[16]_i_1__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[8]_i_1__0_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[16]_i_1__0_n_0\,
      CO(6) => \wordcnt_reg[16]_i_1__0_n_1\,
      CO(5) => \wordcnt_reg[16]_i_1__0_n_2\,
      CO(4) => \wordcnt_reg[16]_i_1__0_n_3\,
      CO(3) => \wordcnt_reg[16]_i_1__0_n_4\,
      CO(2) => \wordcnt_reg[16]_i_1__0_n_5\,
      CO(1) => \wordcnt_reg[16]_i_1__0_n_6\,
      CO(0) => \wordcnt_reg[16]_i_1__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \wordcnt_reg[16]_i_1__0_n_8\,
      O(6) => \wordcnt_reg[16]_i_1__0_n_9\,
      O(5) => \wordcnt_reg[16]_i_1__0_n_10\,
      O(4) => \wordcnt_reg[16]_i_1__0_n_11\,
      O(3) => \wordcnt_reg[16]_i_1__0_n_12\,
      O(2) => \wordcnt_reg[16]_i_1__0_n_13\,
      O(1) => \wordcnt_reg[16]_i_1__0_n_14\,
      O(0) => \wordcnt_reg[16]_i_1__0_n_15\,
      S(7 downto 0) => wordcnt_reg(23 downto 16)
    );
\wordcnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[16]_i_1__0_n_14\,
      Q => wordcnt_reg(17),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[17]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1__0_n_14\,
      Q => \wordcnt_reg[17]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[16]_i_1__0_n_13\,
      Q => wordcnt_reg(18),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[18]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1__0_n_13\,
      Q => \wordcnt_reg[18]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[16]_i_1__0_n_12\,
      Q => wordcnt_reg(19),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[19]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1__0_n_12\,
      Q => \wordcnt_reg[19]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[0]_i_3__0_n_14\,
      Q => wordcnt_reg(1),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[1]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3__0_n_14\,
      Q => \wordcnt_reg[1]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[16]_i_1__0_n_11\,
      Q => wordcnt_reg(20),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[20]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1__0_n_11\,
      Q => \wordcnt_reg[20]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[16]_i_1__0_n_10\,
      Q => wordcnt_reg(21),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[21]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1__0_n_10\,
      Q => \wordcnt_reg[21]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[16]_i_1__0_n_9\,
      Q => wordcnt_reg(22),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[22]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1__0_n_9\,
      Q => \wordcnt_reg[22]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[16]_i_1__0_n_8\,
      Q => wordcnt_reg(23),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[23]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[16]__0_i_1__0_n_8\,
      Q => \wordcnt_reg[23]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[24]_i_1__0_n_15\,
      Q => wordcnt_reg(24),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[24]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[24]__0_i_1__0_n_15\,
      Q => \wordcnt_reg[24]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[24]__0_i_1__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[16]__0_i_1__0_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_wordcnt_reg[24]__0_i_1__0_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \wordcnt_reg[24]__0_i_1__0_n_2\,
      CO(4) => \wordcnt_reg[24]__0_i_1__0_n_3\,
      CO(3) => \wordcnt_reg[24]__0_i_1__0_n_4\,
      CO(2) => \wordcnt_reg[24]__0_i_1__0_n_5\,
      CO(1) => \wordcnt_reg[24]__0_i_1__0_n_6\,
      CO(0) => \wordcnt_reg[24]__0_i_1__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NLW_wordcnt_reg[24]__0_i_1__0_O_UNCONNECTED\(7),
      O(6) => \wordcnt_reg[24]__0_i_1__0_n_9\,
      O(5) => \wordcnt_reg[24]__0_i_1__0_n_10\,
      O(4) => \wordcnt_reg[24]__0_i_1__0_n_11\,
      O(3) => \wordcnt_reg[24]__0_i_1__0_n_12\,
      O(2) => \wordcnt_reg[24]__0_i_1__0_n_13\,
      O(1) => \wordcnt_reg[24]__0_i_1__0_n_14\,
      O(0) => \wordcnt_reg[24]__0_i_1__0_n_15\,
      S(7) => '0',
      S(6) => \wordcnt_reg[30]__0_n_0\,
      S(5) => \wordcnt_reg[29]__0_n_0\,
      S(4) => \wordcnt_reg[28]__0_n_0\,
      S(3) => \wordcnt_reg[27]__0_n_0\,
      S(2) => \wordcnt_reg[26]__0_n_0\,
      S(1) => \wordcnt_reg[25]__0_n_0\,
      S(0) => \wordcnt_reg[24]__0_n_0\
    );
\wordcnt_reg[24]_i_1__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[16]_i_1__0_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_wordcnt_reg[24]_i_1__0_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \wordcnt_reg[24]_i_1__0_n_2\,
      CO(4) => \wordcnt_reg[24]_i_1__0_n_3\,
      CO(3) => \wordcnt_reg[24]_i_1__0_n_4\,
      CO(2) => \wordcnt_reg[24]_i_1__0_n_5\,
      CO(1) => \wordcnt_reg[24]_i_1__0_n_6\,
      CO(0) => \wordcnt_reg[24]_i_1__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NLW_wordcnt_reg[24]_i_1__0_O_UNCONNECTED\(7),
      O(6) => \wordcnt_reg[24]_i_1__0_n_9\,
      O(5) => \wordcnt_reg[24]_i_1__0_n_10\,
      O(4) => \wordcnt_reg[24]_i_1__0_n_11\,
      O(3) => \wordcnt_reg[24]_i_1__0_n_12\,
      O(2) => \wordcnt_reg[24]_i_1__0_n_13\,
      O(1) => \wordcnt_reg[24]_i_1__0_n_14\,
      O(0) => \wordcnt_reg[24]_i_1__0_n_15\,
      S(7) => '0',
      S(6 downto 0) => wordcnt_reg(30 downto 24)
    );
\wordcnt_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[24]_i_1__0_n_14\,
      Q => wordcnt_reg(25),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[25]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[24]__0_i_1__0_n_14\,
      Q => \wordcnt_reg[25]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[24]_i_1__0_n_13\,
      Q => wordcnt_reg(26),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[26]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[24]__0_i_1__0_n_13\,
      Q => \wordcnt_reg[26]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[24]_i_1__0_n_12\,
      Q => wordcnt_reg(27),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[27]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[24]__0_i_1__0_n_12\,
      Q => \wordcnt_reg[27]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[24]_i_1__0_n_11\,
      Q => wordcnt_reg(28),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[28]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[24]__0_i_1__0_n_11\,
      Q => \wordcnt_reg[28]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[24]_i_1__0_n_10\,
      Q => wordcnt_reg(29),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[29]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[24]__0_i_1__0_n_10\,
      Q => \wordcnt_reg[29]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[0]_i_3__0_n_13\,
      Q => wordcnt_reg(2),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[2]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3__0_n_13\,
      Q => \wordcnt_reg[2]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[24]_i_1__0_n_9\,
      Q => wordcnt_reg(30),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[30]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[24]__0_i_1__0_n_9\,
      Q => \wordcnt_reg[30]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[0]_i_3__0_n_12\,
      Q => wordcnt_reg(3),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[3]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3__0_n_12\,
      Q => \wordcnt_reg[3]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[0]_i_3__0_n_11\,
      Q => wordcnt_reg(4),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[4]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3__0_n_11\,
      Q => \wordcnt_reg[4]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[0]_i_3__0_n_10\,
      Q => wordcnt_reg(5),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[5]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3__0_n_10\,
      Q => \wordcnt_reg[5]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[0]_i_3__0_n_9\,
      Q => wordcnt_reg(6),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[6]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3__0_n_9\,
      Q => \wordcnt_reg[6]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[0]_i_3__0_n_8\,
      Q => wordcnt_reg(7),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[7]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[0]__0_i_3__0_n_8\,
      Q => \wordcnt_reg[7]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[8]_i_1__0_n_15\,
      Q => wordcnt_reg(8),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[8]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1__0_n_15\,
      Q => \wordcnt_reg[8]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
\wordcnt_reg[8]__0_i_1__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[0]__0_i_3__0_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[8]__0_i_1__0_n_0\,
      CO(6) => \wordcnt_reg[8]__0_i_1__0_n_1\,
      CO(5) => \wordcnt_reg[8]__0_i_1__0_n_2\,
      CO(4) => \wordcnt_reg[8]__0_i_1__0_n_3\,
      CO(3) => \wordcnt_reg[8]__0_i_1__0_n_4\,
      CO(2) => \wordcnt_reg[8]__0_i_1__0_n_5\,
      CO(1) => \wordcnt_reg[8]__0_i_1__0_n_6\,
      CO(0) => \wordcnt_reg[8]__0_i_1__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \wordcnt_reg[8]__0_i_1__0_n_8\,
      O(6) => \wordcnt_reg[8]__0_i_1__0_n_9\,
      O(5) => \wordcnt_reg[8]__0_i_1__0_n_10\,
      O(4) => \wordcnt_reg[8]__0_i_1__0_n_11\,
      O(3) => \wordcnt_reg[8]__0_i_1__0_n_12\,
      O(2) => \wordcnt_reg[8]__0_i_1__0_n_13\,
      O(1) => \wordcnt_reg[8]__0_i_1__0_n_14\,
      O(0) => \wordcnt_reg[8]__0_i_1__0_n_15\,
      S(7) => \wordcnt_reg[15]__0_n_0\,
      S(6) => \wordcnt_reg[14]__0_n_0\,
      S(5) => \wordcnt_reg[13]__0_n_0\,
      S(4) => \wordcnt_reg[12]__0_n_0\,
      S(3) => \wordcnt_reg[11]__0_n_0\,
      S(2) => \wordcnt_reg[10]__0_n_0\,
      S(1) => \wordcnt_reg[9]__0_n_0\,
      S(0) => \wordcnt_reg[8]__0_n_0\
    );
\wordcnt_reg[8]_i_1__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[0]_i_3__0_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[8]_i_1__0_n_0\,
      CO(6) => \wordcnt_reg[8]_i_1__0_n_1\,
      CO(5) => \wordcnt_reg[8]_i_1__0_n_2\,
      CO(4) => \wordcnt_reg[8]_i_1__0_n_3\,
      CO(3) => \wordcnt_reg[8]_i_1__0_n_4\,
      CO(2) => \wordcnt_reg[8]_i_1__0_n_5\,
      CO(1) => \wordcnt_reg[8]_i_1__0_n_6\,
      CO(0) => \wordcnt_reg[8]_i_1__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \wordcnt_reg[8]_i_1__0_n_8\,
      O(6) => \wordcnt_reg[8]_i_1__0_n_9\,
      O(5) => \wordcnt_reg[8]_i_1__0_n_10\,
      O(4) => \wordcnt_reg[8]_i_1__0_n_11\,
      O(3) => \wordcnt_reg[8]_i_1__0_n_12\,
      O(2) => \wordcnt_reg[8]_i_1__0_n_13\,
      O(1) => \wordcnt_reg[8]_i_1__0_n_14\,
      O(0) => \wordcnt_reg[8]_i_1__0_n_15\,
      S(7 downto 0) => wordcnt_reg(15 downto 8)
    );
\wordcnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \wordcnt[0]_i_2__0_n_0\,
      D => \wordcnt_reg[8]_i_1__0_n_14\,
      Q => wordcnt_reg(9),
      R => \wordcnt[0]_i_1__0_n_0\
    );
\wordcnt_reg[9]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => wordcnt0,
      D => \wordcnt_reg[8]__0_i_1__0_n_14\,
      Q => \wordcnt_reg[9]__0_n_0\,
      R => \wordcnt[0]__0_i_1__0_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Crc8005_32 is
  port (
    stateOp_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \crc_imd_reg[3]_0\ : out STD_LOGIC;
    \resid_reg[1]\ : out STD_LOGIC;
    \resid_reg[1]_0\ : out STD_LOGIC;
    \resid_reg[1]_1\ : out STD_LOGIC;
    \stateOp_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \crcAXIS_tkeep_reg[2]\ : out STD_LOGIC;
    p_10_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    stateOp_reg_1 : out STD_LOGIC;
    \crc_imd_reg[6]_0\ : out STD_LOGIC;
    \recvAXIS_tdata_sig_reg[13]\ : out STD_LOGIC;
    \crcAXIS_tkeep_reg[2]_0\ : out STD_LOGIC;
    crc_imd013_out : out STD_LOGIC;
    crc_imd019_out : out STD_LOGIC;
    crc_imd020_out : out STD_LOGIC;
    stateOp_reg_2 : out STD_LOGIC;
    \crc_imd_reg[12]_0\ : out STD_LOGIC;
    \crcAXIS_tkeep_reg[1]\ : out STD_LOGIC;
    \crc_imd_reg[7]_0\ : out STD_LOGIC;
    \stateOp_reg[3]_1\ : out STD_LOGIC;
    \crc_imd_reg[3]_1\ : out STD_LOGIC;
    \crc_imd_reg[2]_0\ : out STD_LOGIC;
    \crc_imd_reg[13]_0\ : out STD_LOGIC;
    \crc_imd_reg[14]_0\ : out STD_LOGIC;
    \stateOp_reg[2]\ : out STD_LOGIC;
    \crc_imd_reg[8]_0\ : out STD_LOGIC;
    crc_imd015_out : out STD_LOGIC;
    \crc_imd_reg[9]_0\ : out STD_LOGIC;
    \txAXIS_tdata_reg[8]\ : out STD_LOGIC;
    \crc_imd_reg[0]_0\ : out STD_LOGIC;
    crc_imd033_out : out STD_LOGIC;
    \tkst_reg[23]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \tkst_reg[15]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \scoreMax_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[2]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \crc_imd_reg[15]_1\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[15]_2\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[15]_3\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[15]_4\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[0]_1\ : out STD_LOGIC;
    \crc_imd_reg[15]_5\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[1]_0\ : out STD_LOGIC;
    \crc_imd_reg[2]_2\ : out STD_LOGIC;
    \crc_imd_reg[6]_1\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \crc_imd_reg[3]_2\ : out STD_LOGIC;
    \crc_imd_reg[14]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateOp_next_reg[2]\ : out STD_LOGIC;
    \crc_imd_reg[3]_3\ : out STD_LOGIC;
    \stateOp_reg[1]\ : out STD_LOGIC;
    \stateOp_next_reg[0]\ : out STD_LOGIC;
    \crc_imd_reg[15]_6\ : out STD_LOGIC;
    \crc_imd_reg[13]_1\ : out STD_LOGIC;
    \crc_imd_reg[11]_0\ : out STD_LOGIC;
    \crc_imd_reg[9]_1\ : out STD_LOGIC;
    \stateOp_reg[4]\ : out STD_LOGIC;
    \stateOp_reg[4]_0\ : out STD_LOGIC;
    \crc_imd_reg[0]_2\ : out STD_LOGIC;
    \crc_imd_reg[2]_3\ : out STD_LOGIC;
    \crc_imd_reg[4]_0\ : out STD_LOGIC;
    \crc_imd_reg[5]_0\ : out STD_LOGIC;
    \crc_imd_reg[6]_2\ : out STD_LOGIC;
    \crc_imd_reg[5]_1\ : out STD_LOGIC;
    \crc_imd_reg[4]_1\ : out STD_LOGIC;
    \crc_imd_reg[5]_2\ : out STD_LOGIC;
    \crc_imd_reg[6]_3\ : out STD_LOGIC;
    \stateOp_reg[3]_2\ : out STD_LOGIC;
    \stateOp_reg[3]_3\ : out STD_LOGIC;
    \stateOp_reg[3]_4\ : out STD_LOGIC;
    \stateOp_reg[3]_5\ : out STD_LOGIC;
    \crc_imd_reg[0]_3\ : out STD_LOGIC;
    \crc_imd_reg[1]_1\ : out STD_LOGIC;
    \crc_imd_reg[15]_7\ : out STD_LOGIC;
    \crc_imd_reg[13]_2\ : out STD_LOGIC;
    \resid_reg[1]_2\ : out STD_LOGIC;
    \crc_imd_reg[9]_2\ : out STD_LOGIC;
    \stateOp_reg[1]_0\ : out STD_LOGIC;
    \stateOp_reg[1]_1\ : out STD_LOGIC;
    \stateOp_reg[1]_2\ : out STD_LOGIC;
    \stateOp_reg[1]_3\ : out STD_LOGIC;
    \crc_imd_reg[7]_1\ : out STD_LOGIC;
    \crc_imd_reg[12]_1\ : out STD_LOGIC;
    \stateOp_reg[1]_4\ : out STD_LOGIC;
    \crc_imd_reg[14]_2\ : out STD_LOGIC;
    \stateOp_reg[1]_5\ : out STD_LOGIC;
    \crc_imd_reg[4]_2\ : out STD_LOGIC;
    \crc_imd_reg[6]_4\ : out STD_LOGIC;
    stateOp_reg_3 : in STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    first_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \txlen_reg[3]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \retbuf_reg[0][0]\ : in STD_LOGIC;
    \retbuf_reg[33][0]\ : in STD_LOGIC;
    \retbuf_reg[0][6]\ : in STD_LOGIC;
    \retbuf_reg[31][0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \tixVCommand_reg[0]\ : in STD_LOGIC;
    \tixVCommand_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \crc_imd_reg[0]_4\ : in STD_LOGIC;
    \crc_imd_reg[0]_5\ : in STD_LOGIC;
    \crc_imd_reg[1]_2\ : in STD_LOGIC;
    \crc_imd_reg[1]_3\ : in STD_LOGIC;
    \crc_imd_reg[1]_4\ : in STD_LOGIC;
    \crc_imd_reg[7]_2\ : in STD_LOGIC;
    \crc_imd_reg[8]_1\ : in STD_LOGIC;
    \crc_imd_reg[8]_2\ : in STD_LOGIC;
    AXIS_tdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
    \crc_imd_reg[10]_0\ : in STD_LOGIC;
    \crc_imd_reg[11]_1\ : in STD_LOGIC;
    crc_imd017_out : in STD_LOGIC;
    \crc_imd_reg[13]_3\ : in STD_LOGIC;
    \crc_imd_reg[14]_3\ : in STD_LOGIC;
    \crc_imd_reg[15]_8\ : in STD_LOGIC;
    \crc_imd_reg[15]_9\ : in STD_LOGIC;
    \crc_imd_reg[15]_10\ : in STD_LOGIC;
    \crc_imd_reg[15]_11\ : in STD_LOGIC;
    \crc_imd_reg[0]_6\ : in STD_LOGIC;
    \crc_imd_reg[0]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    p_24_in : in STD_LOGIC;
    crc_imd032_out : in STD_LOGIC;
    crc_imd059_out : in STD_LOGIC;
    \crc_imd_reg[0]_8\ : in STD_LOGIC;
    rxAXIS_tvalid : in STD_LOGIC;
    recvAXIS_tlast : in STD_LOGIC;
    crc_imd060_out : in STD_LOGIC;
    \crc_imd_reg[0]_9\ : in STD_LOGIC;
    \crc_imd_reg[0]_10\ : in STD_LOGIC;
    \crc_imd_reg[0]_11\ : in STD_LOGIC;
    \crc_imd[15]_i_9__0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \crc_imd[15]_i_9__0_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \crc_imd[1]_i_2__0_0\ : in STD_LOGIC;
    \crc_imd[1]_i_2__0_1\ : in STD_LOGIC;
    AXIS_tvalid : in STD_LOGIC;
    AXIS_tlast : in STD_LOGIC;
    \retbuf_reg[0][0]_0\ : in STD_LOGIC;
    \retbuf_reg[0][0]_1\ : in STD_LOGIC;
    \retbuf_reg[0][1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \retbuf_reg[2][7]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \retbuf_reg[6][7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \txAXIS_tdata_reg[16]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[16]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[18]\ : in STD_LOGIC;
    \retbuf_reg[37][0]\ : in STD_LOGIC;
    \retbuf_reg[36][0]\ : in STD_LOGIC;
    \retbuf_reg[33][0]_0\ : in STD_LOGIC;
    \retbuf_reg[8][5]\ : in STD_LOGIC;
    \retbuf_reg[0][3]\ : in STD_LOGIC;
    \retbuf_reg[8][0]\ : in STD_LOGIC;
    \stateOp_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateOp_reg[4]_1\ : in STD_LOGIC;
    \stateOp_reg[4]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[10]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[10]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \txAXIS_tdata_reg[10]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \txAXIS_tdata_reg[26]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \retbuf_reg[1][0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \txAXIS_tdata_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \txAXIS_tdata_reg[6]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \crc_imd_reg[9]_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Crc8005_32 : entity is "Crc8005_32";
end design_1_Vsp_core_0_0_Crc8005_32;

architecture STRUCTURE of design_1_Vsp_core_0_0_Crc8005_32 is
  signal \^d\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^crcaxis_tkeep_reg[2]\ : STD_LOGIC;
  signal \^crcaxis_tkeep_reg[2]_0\ : STD_LOGIC;
  signal \^crc_imd013_out\ : STD_LOGIC;
  signal \^crc_imd019_out\ : STD_LOGIC;
  signal \^crc_imd020_out\ : STD_LOGIC;
  signal \crc_imd[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_5__0_n_0\ : STD_LOGIC;
  signal \crc_imd[0]_i_6__0_n_0\ : STD_LOGIC;
  signal \crc_imd[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \crc_imd[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \crc_imd[11]_i_3__0_n_0\ : STD_LOGIC;
  signal \crc_imd[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \crc_imd[12]_i_3__0_n_0\ : STD_LOGIC;
  signal \crc_imd[13]_i_1__0_n_0\ : STD_LOGIC;
  signal \crc_imd[14]_i_1__0_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_11__0_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_12__0_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_2__0_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_3_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_6__0_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_7__0_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_10__0_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_3__0_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_8__0_n_0\ : STD_LOGIC;
  signal \crc_imd[1]_i_9__0_n_0\ : STD_LOGIC;
  signal \crc_imd[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \crc_imd[7]_i_4__0_n_0\ : STD_LOGIC;
  signal \crc_imd[7]_i_5__0_n_0\ : STD_LOGIC;
  signal \crc_imd[7]_i_6__0_n_0\ : STD_LOGIC;
  signal \crc_imd[7]_i_8__0_n_0\ : STD_LOGIC;
  signal \crc_imd[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \crc_imd[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \^crc_imd_reg[12]_0\ : STD_LOGIC;
  signal \^crc_imd_reg[13]_0\ : STD_LOGIC;
  signal \^crc_imd_reg[15]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^crc_imd_reg[2]_0\ : STD_LOGIC;
  signal \^crc_imd_reg[3]_0\ : STD_LOGIC;
  signal \^crc_imd_reg[3]_1\ : STD_LOGIC;
  signal \^crc_imd_reg[3]_3\ : STD_LOGIC;
  signal \^crc_imd_reg[6]_0\ : STD_LOGIC;
  signal \^crc_imd_reg[6]_1\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^crc_imd_reg[7]_0\ : STD_LOGIC;
  signal first : STD_LOGIC;
  signal \first_i_1__0_n_0\ : STD_LOGIC;
  signal \^p_10_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^recvaxis_tdata_sig_reg[13]\ : STD_LOGIC;
  signal \retbuf[0][1]_i_2__0_n_0\ : STD_LOGIC;
  signal \retbuf[2][2]_i_2__0_n_0\ : STD_LOGIC;
  signal \retbuf[2][4]_i_2__0_n_0\ : STD_LOGIC;
  signal \retbuf[3][0]_i_2__0_n_0\ : STD_LOGIC;
  signal \retbuf[6][6]_i_2__0_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_10_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_11_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_12_n_0\ : STD_LOGIC;
  signal \^stateop_reg[2]\ : STD_LOGIC;
  signal \^stateop_reg[3]_1\ : STD_LOGIC;
  signal \^stateop_reg_0\ : STD_LOGIC;
  signal \^stateop_reg_1\ : STD_LOGIC;
  signal \^stateop_reg_2\ : STD_LOGIC;
  signal \tixVController[7]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[0]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[10]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[26]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[2]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[4]_i_7__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_9__0_n_0\ : STD_LOGIC;
  signal \txlen[3]_i_2_n_0\ : STD_LOGIC;
  signal \validCrc_sig_i_1__0_n_0\ : STD_LOGIC;
  signal validCrc_sig_reg_n_0 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \crc_imd[0]_i_3__0\ : label is "soft_lutpair2663";
  attribute SOFT_HLUTNM of \crc_imd[14]_i_3__0\ : label is "soft_lutpair2633";
  attribute SOFT_HLUTNM of \crc_imd[14]_i_5__0\ : label is "soft_lutpair2662";
  attribute SOFT_HLUTNM of \crc_imd[14]_i_7__0\ : label is "soft_lutpair2647";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_10__0\ : label is "soft_lutpair2634";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_16__0\ : label is "soft_lutpair2663";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_3\ : label is "soft_lutpair2634";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_5__0\ : label is "soft_lutpair2647";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_7__0\ : label is "soft_lutpair2633";
  attribute SOFT_HLUTNM of \crc_imd[1]_i_7__0\ : label is "soft_lutpair2662";
  attribute SOFT_HLUTNM of \crc_imd[1]_i_9__0\ : label is "soft_lutpair2635";
  attribute SOFT_HLUTNM of \crc_imd[3]_i_3__0\ : label is "soft_lutpair2635";
  attribute SOFT_HLUTNM of \len[15]_i_1__0\ : label is "soft_lutpair2653";
  attribute SOFT_HLUTNM of \retbuf[0][1]_i_2__0\ : label is "soft_lutpair2637";
  attribute SOFT_HLUTNM of \retbuf[2][2]_i_2__0\ : label is "soft_lutpair2638";
  attribute SOFT_HLUTNM of \retbuf[2][3]_i_1__0\ : label is "soft_lutpair2665";
  attribute SOFT_HLUTNM of \retbuf[2][4]_i_2__0\ : label is "soft_lutpair2639";
  attribute SOFT_HLUTNM of \retbuf[2][5]_i_1__0\ : label is "soft_lutpair2668";
  attribute SOFT_HLUTNM of \retbuf[2][6]_i_1__0\ : label is "soft_lutpair2667";
  attribute SOFT_HLUTNM of \retbuf[2][7]_i_2__0\ : label is "soft_lutpair2664";
  attribute SOFT_HLUTNM of \retbuf[36][0]_i_1__0\ : label is "soft_lutpair2654";
  attribute SOFT_HLUTNM of \retbuf[36][1]_i_1__0\ : label is "soft_lutpair2655";
  attribute SOFT_HLUTNM of \retbuf[36][2]_i_1__0\ : label is "soft_lutpair2656";
  attribute SOFT_HLUTNM of \retbuf[36][3]_i_1__0\ : label is "soft_lutpair2657";
  attribute SOFT_HLUTNM of \retbuf[36][4]_i_1__0\ : label is "soft_lutpair2658";
  attribute SOFT_HLUTNM of \retbuf[36][5]_i_1__0\ : label is "soft_lutpair2659";
  attribute SOFT_HLUTNM of \retbuf[36][6]_i_1__0\ : label is "soft_lutpair2660";
  attribute SOFT_HLUTNM of \retbuf[36][7]_i_2__0\ : label is "soft_lutpair2661";
  attribute SOFT_HLUTNM of \retbuf[37][0]_i_1__0\ : label is "soft_lutpair2654";
  attribute SOFT_HLUTNM of \retbuf[37][1]_i_1__0\ : label is "soft_lutpair2655";
  attribute SOFT_HLUTNM of \retbuf[37][2]_i_1__0\ : label is "soft_lutpair2656";
  attribute SOFT_HLUTNM of \retbuf[37][3]_i_1__0\ : label is "soft_lutpair2657";
  attribute SOFT_HLUTNM of \retbuf[37][4]_i_1__0\ : label is "soft_lutpair2658";
  attribute SOFT_HLUTNM of \retbuf[37][5]_i_1__0\ : label is "soft_lutpair2659";
  attribute SOFT_HLUTNM of \retbuf[37][6]_i_1__0\ : label is "soft_lutpair2660";
  attribute SOFT_HLUTNM of \retbuf[37][7]_i_2__0\ : label is "soft_lutpair2661";
  attribute SOFT_HLUTNM of \retbuf[38][0]_i_1__0\ : label is "soft_lutpair2636";
  attribute SOFT_HLUTNM of \retbuf[38][1]_i_1__0\ : label is "soft_lutpair2637";
  attribute SOFT_HLUTNM of \retbuf[38][2]_i_1__0\ : label is "soft_lutpair2638";
  attribute SOFT_HLUTNM of \retbuf[38][4]_i_1__0\ : label is "soft_lutpair2639";
  attribute SOFT_HLUTNM of \retbuf[38][5]_i_1__0\ : label is "soft_lutpair2641";
  attribute SOFT_HLUTNM of \retbuf[38][6]_i_1__0\ : label is "soft_lutpair2640";
  attribute SOFT_HLUTNM of \retbuf[38][7]_i_2__0\ : label is "soft_lutpair2645";
  attribute SOFT_HLUTNM of \retbuf[3][0]_i_2__0\ : label is "soft_lutpair2636";
  attribute SOFT_HLUTNM of \retbuf[3][3]_i_1__0\ : label is "soft_lutpair2665";
  attribute SOFT_HLUTNM of \retbuf[3][5]_i_1__0\ : label is "soft_lutpair2668";
  attribute SOFT_HLUTNM of \retbuf[3][6]_i_1__0\ : label is "soft_lutpair2667";
  attribute SOFT_HLUTNM of \retbuf[3][7]_i_2__0\ : label is "soft_lutpair2664";
  attribute SOFT_HLUTNM of \retbuf[6][3]_i_1\ : label is "soft_lutpair2666";
  attribute SOFT_HLUTNM of \retbuf[6][6]_i_2__0\ : label is "soft_lutpair2640";
  attribute SOFT_HLUTNM of \retbuf[6][7]_i_1__0\ : label is "soft_lutpair2666";
  attribute SOFT_HLUTNM of \retbuf[7][1]_i_1__0\ : label is "soft_lutpair2643";
  attribute SOFT_HLUTNM of \retbuf[7][4]_i_1__0\ : label is "soft_lutpair2644";
  attribute SOFT_HLUTNM of \retbuf[7][6]_i_1__0\ : label is "soft_lutpair2642";
  attribute SOFT_HLUTNM of \stateOp[2]_i_2__2\ : label is "soft_lutpair2646";
  attribute SOFT_HLUTNM of \tixVController[7]_i_3__0\ : label is "soft_lutpair2646";
  attribute SOFT_HLUTNM of \txAXIS_tdata[10]_i_5__0\ : label is "soft_lutpair2648";
  attribute SOFT_HLUTNM of \txAXIS_tdata[11]_i_4__0\ : label is "soft_lutpair2632";
  attribute SOFT_HLUTNM of \txAXIS_tdata[12]_i_4__0\ : label is "soft_lutpair2644";
  attribute SOFT_HLUTNM of \txAXIS_tdata[13]_i_2__0\ : label is "soft_lutpair2650";
  attribute SOFT_HLUTNM of \txAXIS_tdata[14]_i_4__0\ : label is "soft_lutpair2642";
  attribute SOFT_HLUTNM of \txAXIS_tdata[15]_i_3__0\ : label is "soft_lutpair2652";
  attribute SOFT_HLUTNM of \txAXIS_tdata[17]_i_4__0\ : label is "soft_lutpair2643";
  attribute SOFT_HLUTNM of \txAXIS_tdata[19]_i_4__0\ : label is "soft_lutpair2632";
  attribute SOFT_HLUTNM of \txAXIS_tdata[20]_i_2__0\ : label is "soft_lutpair2649";
  attribute SOFT_HLUTNM of \txAXIS_tdata[21]_i_4__0\ : label is "soft_lutpair2641";
  attribute SOFT_HLUTNM of \txAXIS_tdata[22]_i_4__0\ : label is "soft_lutpair2651";
  attribute SOFT_HLUTNM of \txAXIS_tdata[23]_i_6__0\ : label is "soft_lutpair2645";
  attribute SOFT_HLUTNM of \txAXIS_tdata[24]_i_3__0\ : label is "soft_lutpair2630";
  attribute SOFT_HLUTNM of \txAXIS_tdata[25]_i_4__0\ : label is "soft_lutpair2631";
  attribute SOFT_HLUTNM of \txAXIS_tdata[26]_i_6__0\ : label is "soft_lutpair2648";
  attribute SOFT_HLUTNM of \txAXIS_tdata[28]_i_4__0\ : label is "soft_lutpair2649";
  attribute SOFT_HLUTNM of \txAXIS_tdata[29]_i_2__0\ : label is "soft_lutpair2650";
  attribute SOFT_HLUTNM of \txAXIS_tdata[30]_i_4__0\ : label is "soft_lutpair2651";
  attribute SOFT_HLUTNM of \txAXIS_tdata[31]_i_8__0\ : label is "soft_lutpair2652";
  attribute SOFT_HLUTNM of \txAXIS_tdata[8]_i_4__0\ : label is "soft_lutpair2630";
  attribute SOFT_HLUTNM of \txAXIS_tdata[9]_i_4__0\ : label is "soft_lutpair2631";
  attribute SOFT_HLUTNM of \txlen[3]_i_1\ : label is "soft_lutpair2653";
begin
  D(7 downto 0) <= \^d\(7 downto 0);
  \crcAXIS_tkeep_reg[2]\ <= \^crcaxis_tkeep_reg[2]\;
  \crcAXIS_tkeep_reg[2]_0\ <= \^crcaxis_tkeep_reg[2]_0\;
  crc_imd013_out <= \^crc_imd013_out\;
  crc_imd019_out <= \^crc_imd019_out\;
  crc_imd020_out <= \^crc_imd020_out\;
  \crc_imd_reg[12]_0\ <= \^crc_imd_reg[12]_0\;
  \crc_imd_reg[13]_0\ <= \^crc_imd_reg[13]_0\;
  \crc_imd_reg[15]_0\(15 downto 0) <= \^crc_imd_reg[15]_0\(15 downto 0);
  \crc_imd_reg[2]_0\ <= \^crc_imd_reg[2]_0\;
  \crc_imd_reg[3]_0\ <= \^crc_imd_reg[3]_0\;
  \crc_imd_reg[3]_1\ <= \^crc_imd_reg[3]_1\;
  \crc_imd_reg[3]_3\ <= \^crc_imd_reg[3]_3\;
  \crc_imd_reg[6]_0\ <= \^crc_imd_reg[6]_0\;
  \crc_imd_reg[6]_1\(4 downto 0) <= \^crc_imd_reg[6]_1\(4 downto 0);
  \crc_imd_reg[7]_0\ <= \^crc_imd_reg[7]_0\;
  p_10_out(0) <= \^p_10_out\(0);
  \recvAXIS_tdata_sig_reg[13]\ <= \^recvaxis_tdata_sig_reg[13]\;
  \stateOp_reg[2]\ <= \^stateop_reg[2]\;
  \stateOp_reg[3]_1\ <= \^stateop_reg[3]_1\;
  stateOp_reg_0 <= \^stateop_reg_0\;
  stateOp_reg_1 <= \^stateop_reg_1\;
  stateOp_reg_2 <= \^stateop_reg_2\;
\crc_imd[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEEE"
    )
        port map (
      I0 => \crc_imd_reg[0]_4\,
      I1 => \crc_imd[0]_i_2__0_n_0\,
      I2 => \^crcaxis_tkeep_reg[2]\,
      I3 => \^p_10_out\(0),
      I4 => \crc_imd_reg[0]_5\,
      I5 => \crc_imd[0]_i_5__0_n_0\,
      O => \crc_imd[0]_i_1__0_n_0\
    );
\crc_imd[0]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28828228"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[2]_0\,
      I1 => \^recvaxis_tdata_sig_reg[13]\,
      I2 => \crc_imd_reg[15]_11\,
      I3 => \crc_imd[1]_i_10__0_n_0\,
      I4 => \crc_imd_reg[0]_6\,
      O => \crc_imd[0]_i_2__0_n_0\
    );
\crc_imd[0]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \crc_imd_reg[15]_10\,
      I1 => \crc_imd[1]_i_10__0_n_0\,
      I2 => \crc_imd[0]_i_6__0_n_0\,
      O => \^p_10_out\(0)
    );
\crc_imd[0]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \^stateop_reg_1\,
      I1 => \crc_imd_reg[0]_9\,
      I2 => \^recvaxis_tdata_sig_reg[13]\,
      I3 => \crc_imd_reg[0]_10\,
      I4 => \crc_imd_reg[0]_11\,
      I5 => \^crc_imd_reg[13]_0\,
      O => \crc_imd[0]_i_5__0_n_0\
    );
\crc_imd[0]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"95AA95956A556A6A"
    )
        port map (
      I0 => \crc_imd[1]_i_9__0_n_0\,
      I1 => \^stateop_reg[2]\,
      I2 => \crc_imd[15]_i_9__0\(0),
      I3 => \^stateop_reg[3]_1\,
      I4 => \crc_imd[15]_i_9__0_0\(0),
      I5 => \^crc_imd_reg[15]_0\(8),
      O => \crc_imd[0]_i_6__0_n_0\
    );
\crc_imd[0]_i_9__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \crc_imd[1]_i_10__0_n_0\,
      I1 => \crc_imd_reg[15]_10\,
      O => \^crc_imd_reg[13]_0\
    );
\crc_imd[10]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \crc_imd_reg[0]_4\,
      I1 => \^crcaxis_tkeep_reg[2]_0\,
      I2 => \^crc_imd013_out\,
      I3 => \^crcaxis_tkeep_reg[2]\,
      I4 => \^crc_imd_reg[15]_0\(2),
      I5 => \crc_imd_reg[10]_0\,
      O => \crc_imd[10]_i_1__0_n_0\
    );
\crc_imd[10]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(8),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => AXIS_tdata(1),
      I3 => AXIS_tdata(0),
      O => \^crc_imd013_out\
    );
\crc_imd[11]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEAAEAEEA"
    )
        port map (
      I0 => \crc_imd_reg[0]_4\,
      I1 => \^crcaxis_tkeep_reg[2]_0\,
      I2 => \^crc_imd_reg[15]_0\(10),
      I3 => \^crc_imd_reg[15]_0\(9),
      I4 => \crc_imd_reg[11]_1\,
      I5 => \crc_imd[11]_i_3__0_n_0\,
      O => \crc_imd[11]_i_1__0_n_0\
    );
\crc_imd[11]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^stateop_reg_1\,
      I1 => crc_imd032_out,
      I2 => \^stateop_reg_2\,
      I3 => crc_imd059_out,
      I4 => \^crc_imd_reg[15]_0\(3),
      I5 => \^crcaxis_tkeep_reg[2]\,
      O => \crc_imd[11]_i_3__0_n_0\
    );
\crc_imd[12]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \crc_imd_reg[0]_4\,
      I1 => \^crcaxis_tkeep_reg[2]_0\,
      I2 => crc_imd017_out,
      I3 => \^crcaxis_tkeep_reg[2]\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \crc_imd[12]_i_3__0_n_0\,
      O => \crc_imd[12]_i_1__0_n_0\
    );
\crc_imd[12]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA0000003C000000"
    )
        port map (
      I0 => crc_imd060_out,
      I1 => \^crc_imd_reg[2]_0\,
      I2 => \^crc_imd_reg[3]_1\,
      I3 => \^stateop_reg_0\,
      I4 => \crc_imd_reg[0]_7\(2),
      I5 => \crc_imd_reg[0]_7\(3),
      O => \crc_imd[12]_i_3__0_n_0\
    );
\crc_imd[12]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \crc_imd[15]_i_9__0_0\(5),
      I2 => \^stateop_reg[3]_1\,
      I3 => \crc_imd[15]_i_9__0\(5),
      I4 => \^stateop_reg[2]\,
      O => \^crc_imd_reg[2]_0\
    );
\crc_imd[13]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \crc_imd_reg[0]_4\,
      I1 => \^crcaxis_tkeep_reg[2]_0\,
      I2 => \^crc_imd019_out\,
      I3 => \^crcaxis_tkeep_reg[2]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \crc_imd_reg[13]_3\,
      O => \crc_imd[13]_i_1__0_n_0\
    );
\crc_imd[13]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9666999996669666"
    )
        port map (
      I0 => \^crc_imd_reg[12]_0\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \^stateop_reg[2]\,
      I3 => \crc_imd[15]_i_9__0\(1),
      I4 => \^stateop_reg[3]_1\,
      I5 => \crc_imd[15]_i_9__0_0\(1),
      O => \^crc_imd019_out\
    );
\crc_imd[13]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \crc_imd[15]_i_9__0_0\(6),
      I2 => \^stateop_reg[3]_1\,
      I3 => \crc_imd[15]_i_9__0\(6),
      I4 => \^stateop_reg[2]\,
      O => \^crc_imd_reg[3]_1\
    );
\crc_imd[14]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \crc_imd_reg[0]_4\,
      I1 => \^crcaxis_tkeep_reg[2]_0\,
      I2 => \^crc_imd020_out\,
      I3 => \^crcaxis_tkeep_reg[2]\,
      I4 => \^crc_imd_reg[15]_0\(6),
      I5 => \crc_imd_reg[14]_3\,
      O => \crc_imd[14]_i_1__0_n_0\
    );
\crc_imd[14]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \crc_imd_reg[0]_7\(2),
      I1 => \^stateop_reg_0\,
      I2 => \crc_imd_reg[0]_7\(1),
      O => \^crcaxis_tkeep_reg[2]_0\
    );
\crc_imd[14]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8F88707770778F88"
    )
        port map (
      I0 => \^stateop_reg[2]\,
      I1 => \crc_imd[15]_i_9__0\(3),
      I2 => \^stateop_reg[3]_1\,
      I3 => \crc_imd[15]_i_9__0_0\(3),
      I4 => \^crc_imd_reg[15]_0\(13),
      I5 => \^crc_imd_reg[12]_0\,
      O => \^crc_imd020_out\
    );
\crc_imd[14]_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \crc_imd_reg[0]_7\(2),
      I1 => \^stateop_reg_0\,
      I2 => \crc_imd_reg[0]_7\(1),
      O => \^crcaxis_tkeep_reg[2]\
    );
\crc_imd[14]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00040400"
    )
        port map (
      I0 => Q(2),
      I1 => Q(0),
      I2 => Q(1),
      I3 => Q(4),
      I4 => Q(3),
      O => \^stateop_reg[2]\
    );
\crc_imd[15]_i_10__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg_0\,
      I1 => \crc_imd_reg[0]_7\(2),
      I2 => \crc_imd_reg[0]_7\(3),
      O => \^stateop_reg_2\
    );
\crc_imd[15]_i_11__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \^stateop_reg_1\,
      I1 => \crc_imd_reg[15]_11\,
      I2 => \crc_imd_reg[0]_10\,
      I3 => \^p_10_out\(0),
      I4 => \crc_imd_reg[0]_9\,
      I5 => \^crc_imd_reg[7]_0\,
      O => \crc_imd[15]_i_11__0_n_0\
    );
\crc_imd[15]_i_12__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A888A888A880000"
    )
        port map (
      I0 => \crc_imd_reg[0]_7\(0),
      I1 => \^stateop_reg[2]\,
      I2 => \^stateop_reg[3]_1\,
      I3 => rxAXIS_tvalid,
      I4 => validCrc_sig_reg_n_0,
      I5 => first,
      O => \crc_imd[15]_i_12__0_n_0\
    );
\crc_imd[15]_i_13__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(12),
      I1 => \crc_imd[15]_i_9__0_0\(2),
      I2 => \^stateop_reg[3]_1\,
      I3 => \crc_imd[15]_i_9__0\(2),
      I4 => \^stateop_reg[2]\,
      O => \^crc_imd_reg[12]_0\
    );
\crc_imd[15]_i_16__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \crc_imd_reg[7]_2\,
      I1 => \^crc_imd_reg[7]_0\,
      I2 => \crc_imd[0]_i_6__0_n_0\,
      O => \^recvaxis_tdata_sig_reg[13]\
    );
\crc_imd[15]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABABAAABABABABAB"
    )
        port map (
      I0 => \crc_imd[15]_i_3_n_0\,
      I1 => \^stateop_reg_0\,
      I2 => \crc_imd_reg[0]_8\,
      I3 => rxAXIS_tvalid,
      I4 => \^stateop_reg[3]_1\,
      I5 => recvAXIS_tlast,
      O => \crc_imd[15]_i_1__0_n_0\
    );
\crc_imd[15]_i_20__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(8),
      I1 => \crc_imd[15]_i_9__0_0\(0),
      I2 => \^stateop_reg[3]_1\,
      I3 => \crc_imd[15]_i_9__0\(0),
      I4 => \^stateop_reg[2]\,
      O => \crc_imd_reg[8]_0\
    );
\crc_imd[15]_i_21__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(9),
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \crc_imd_reg[11]_1\,
      O => \crc_imd_reg[9]_0\
    );
\crc_imd[15]_i_22__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \crc_imd[15]_i_9__0_0\(8),
      I2 => \^stateop_reg[3]_1\,
      I3 => \crc_imd[15]_i_9__0\(8),
      I4 => \^stateop_reg[2]\,
      O => \^crc_imd_reg[7]_0\
    );
\crc_imd[15]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEFFEEEEE"
    )
        port map (
      I0 => \crc_imd[15]_i_6__0_n_0\,
      I1 => \crc_imd[15]_i_7__0_n_0\,
      I2 => \crc_imd_reg[15]_8\,
      I3 => \crc_imd_reg[15]_9\,
      I4 => \^stateop_reg_2\,
      I5 => \crc_imd[15]_i_11__0_n_0\,
      O => \crc_imd[15]_i_2__0_n_0\
    );
\crc_imd[15]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80A00020"
    )
        port map (
      I0 => \crc_imd[15]_i_12__0_n_0\,
      I1 => \crc_imd_reg[0]_7\(2),
      I2 => \^stateop_reg_0\,
      I3 => \crc_imd_reg[0]_7\(3),
      I4 => \crc_imd_reg[0]_7\(1),
      O => \crc_imd[15]_i_3_n_0\
    );
\crc_imd[15]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFBBFFF"
    )
        port map (
      I0 => Q(3),
      I1 => Q(1),
      I2 => Q(4),
      I3 => Q(2),
      I4 => Q(0),
      O => \^stateop_reg[3]_1\
    );
\crc_imd[15]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF69960000"
    )
        port map (
      I0 => \^crc_imd_reg[12]_0\,
      I1 => \crc_imd_reg[15]_10\,
      I2 => \crc_imd_reg[15]_11\,
      I3 => \^recvaxis_tdata_sig_reg[13]\,
      I4 => \^crcaxis_tkeep_reg[2]_0\,
      I5 => \crc_imd_reg[0]_4\,
      O => \crc_imd[15]_i_6__0_n_0\
    );
\crc_imd[15]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00040400"
    )
        port map (
      I0 => \crc_imd_reg[0]_7\(1),
      I1 => \^stateop_reg_0\,
      I2 => \crc_imd_reg[0]_7\(2),
      I3 => \^crc_imd_reg[15]_0\(7),
      I4 => \^p_10_out\(0),
      O => \crc_imd[15]_i_7__0_n_0\
    );
\crc_imd[1]_i_10__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9666999996669666"
    )
        port map (
      I0 => \^crc_imd_reg[12]_0\,
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \^stateop_reg[2]\,
      I3 => \crc_imd[15]_i_9__0\(3),
      I4 => \^stateop_reg[3]_1\,
      I5 => \crc_imd[15]_i_9__0_0\(3),
      O => \crc_imd[1]_i_10__0_n_0\
    );
\crc_imd[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFFFEFEFEFEFE"
    )
        port map (
      I0 => \crc_imd[1]_i_2__0_n_0\,
      I1 => \crc_imd[1]_i_3__0_n_0\,
      I2 => \crc_imd_reg[1]_2\,
      I3 => \crc_imd_reg[1]_3\,
      I4 => \crc_imd_reg[1]_4\,
      I5 => \^stateop_reg_1\,
      O => \crc_imd[1]_i_1__0_n_0\
    );
\crc_imd[1]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF9600"
    )
        port map (
      I0 => \^crc_imd_reg[6]_0\,
      I1 => \^recvaxis_tdata_sig_reg[13]\,
      I2 => \crc_imd[1]_i_8__0_n_0\,
      I3 => \^crcaxis_tkeep_reg[2]_0\,
      I4 => \crc_imd_reg[0]_4\,
      O => \crc_imd[1]_i_2__0_n_0\
    );
\crc_imd[1]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400000400040400"
    )
        port map (
      I0 => \crc_imd_reg[0]_7\(1),
      I1 => \^stateop_reg_0\,
      I2 => \crc_imd_reg[0]_7\(2),
      I3 => \crc_imd[1]_i_9__0_n_0\,
      I4 => \crc_imd[1]_i_10__0_n_0\,
      I5 => \crc_imd_reg[15]_10\,
      O => \crc_imd[1]_i_3__0_n_0\
    );
\crc_imd[1]_i_7__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^stateop_reg_0\,
      I1 => \crc_imd_reg[0]_7\(2),
      I2 => \crc_imd_reg[0]_7\(3),
      O => \^stateop_reg_1\
    );
\crc_imd[1]_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \crc_imd[1]_i_10__0_n_0\,
      I1 => \crc_imd[1]_i_2__0_0\,
      I2 => \crc_imd[1]_i_2__0_1\,
      I3 => AXIS_tdata(3),
      I4 => \^crc_imd_reg[15]_0\(14),
      I5 => \^crc_imd_reg[2]_0\,
      O => \crc_imd[1]_i_8__0_n_0\
    );
\crc_imd[1]_i_9__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(11),
      I1 => AXIS_tdata(2),
      I2 => \crc_imd_reg[11]_1\,
      I3 => \^crc_imd_reg[15]_0\(10),
      I4 => \^crc_imd_reg[15]_0\(9),
      O => \crc_imd[1]_i_9__0_n_0\
    );
\crc_imd[2]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \crc_imd[15]_i_9__0_0\(4),
      I2 => \^stateop_reg[3]_1\,
      I3 => \crc_imd[15]_i_9__0\(4),
      I4 => \^stateop_reg[2]\,
      O => \crc_imd_reg[0]_0\
    );
\crc_imd[3]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \crc_imd_reg[11]_1\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \^crc_imd_reg[15]_0\(10),
      O => crc_imd015_out
    );
\crc_imd[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"95AA95956A556A6A"
    )
        port map (
      I0 => \^crc_imd_reg[2]_0\,
      I1 => \^stateop_reg[2]\,
      I2 => \crc_imd[15]_i_9__0\(6),
      I3 => \^stateop_reg[3]_1\,
      I4 => \crc_imd[15]_i_9__0_0\(6),
      I5 => \^crc_imd_reg[15]_0\(3),
      O => crc_imd033_out
    );
\crc_imd[4]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"95AA95956A556A6A"
    )
        port map (
      I0 => \^crc_imd_reg[2]_0\,
      I1 => \^stateop_reg[2]\,
      I2 => \crc_imd[15]_i_9__0\(4),
      I3 => \^stateop_reg[3]_1\,
      I4 => \crc_imd[15]_i_9__0_0\(4),
      I5 => \^crc_imd_reg[15]_0\(0),
      O => \txAXIS_tdata_reg[8]\
    );
\crc_imd[7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFAEEA"
    )
        port map (
      I0 => \crc_imd_reg[0]_4\,
      I1 => \^crcaxis_tkeep_reg[2]_0\,
      I2 => \crc_imd_reg[7]_2\,
      I3 => \^crc_imd_reg[6]_0\,
      I4 => \crc_imd[7]_i_4__0_n_0\,
      O => \crc_imd[7]_i_1__0_n_0\
    );
\crc_imd[7]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \crc_imd[15]_i_9__0_0\(7),
      I2 => \^stateop_reg[3]_1\,
      I3 => \crc_imd[15]_i_9__0\(7),
      I4 => \^stateop_reg[2]\,
      O => \^crc_imd_reg[6]_0\
    );
\crc_imd[7]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEFEFFEEEEEEEEE"
    )
        port map (
      I0 => \crc_imd[7]_i_5__0_n_0\,
      I1 => \crc_imd[7]_i_6__0_n_0\,
      I2 => p_24_in,
      I3 => \^crc_imd_reg[15]_0\(13),
      I4 => \^crc_imd_reg[15]_0\(14),
      I5 => \^crcaxis_tkeep_reg[2]\,
      O => \crc_imd[7]_i_4__0_n_0\
    );
\crc_imd[7]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \^stateop_reg_1\,
      I1 => \crc_imd[7]_i_8__0_n_0\,
      I2 => \^crc_imd_reg[15]_0\(11),
      I3 => AXIS_tdata(8),
      I4 => AXIS_tdata(2),
      I5 => AXIS_tdata(7),
      O => \crc_imd[7]_i_5__0_n_0\
    );
\crc_imd[7]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \^stateop_reg_2\,
      I1 => \^crc_imd_reg[15]_0\(5),
      I2 => AXIS_tdata(10),
      I3 => \^crc_imd_reg[3]_1\,
      I4 => AXIS_tdata(4),
      I5 => AXIS_tdata(11),
      O => \crc_imd[7]_i_6__0_n_0\
    );
\crc_imd[7]_i_8__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(13),
      I1 => \crc_imd[15]_i_9__0_0\(3),
      I2 => \^stateop_reg[3]_1\,
      I3 => \crc_imd[15]_i_9__0\(3),
      I4 => \^stateop_reg[2]\,
      O => \crc_imd[7]_i_8__0_n_0\
    );
\crc_imd[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEAAEAEEA"
    )
        port map (
      I0 => \crc_imd[8]_i_2__0_n_0\,
      I1 => \^crcaxis_tkeep_reg[2]\,
      I2 => \^crc_imd_reg[15]_0\(0),
      I3 => \^crc_imd_reg[15]_0\(15),
      I4 => \crc_imd_reg[8]_1\,
      I5 => \crc_imd_reg[8]_2\,
      O => \crc_imd[8]_i_1__0_n_0\
    );
\crc_imd[8]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF69960000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => AXIS_tdata(5),
      I2 => \^crc_imd_reg[15]_0\(6),
      I3 => AXIS_tdata(6),
      I4 => \^crcaxis_tkeep_reg[2]_0\,
      I5 => \crc_imd_reg[0]_4\,
      O => \crc_imd[8]_i_2__0_n_0\
    );
\crc_imd[8]_i_9__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \^stateop_reg_1\,
      I1 => AXIS_tdata(9),
      I2 => \^crc_imd_reg[15]_0\(14),
      I3 => AXIS_tdata(8),
      I4 => \^crc_imd_reg[12]_0\,
      I5 => AXIS_tdata(3),
      O => \crc_imd_reg[14]_0\
    );
\crc_imd[9]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800000800080800"
    )
        port map (
      I0 => \crc_imd_reg[0]_7\(1),
      I1 => \^stateop_reg_0\,
      I2 => \crc_imd_reg[0]_7\(2),
      I3 => AXIS_tdata(0),
      I4 => \^crc_imd_reg[15]_0\(8),
      I5 => \^crc_imd_reg[7]_0\,
      O => \crcAXIS_tkeep_reg[1]\
    );
\crc_imd_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd[0]_i_1__0_n_0\,
      Q => \^crc_imd_reg[15]_0\(0)
    );
\crc_imd_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd[10]_i_1__0_n_0\,
      Q => \^crc_imd_reg[15]_0\(10)
    );
\crc_imd_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd[11]_i_1__0_n_0\,
      Q => \^crc_imd_reg[15]_0\(11)
    );
\crc_imd_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd[12]_i_1__0_n_0\,
      Q => \^crc_imd_reg[15]_0\(12)
    );
\crc_imd_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd[13]_i_1__0_n_0\,
      Q => \^crc_imd_reg[15]_0\(13)
    );
\crc_imd_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd[14]_i_1__0_n_0\,
      Q => \^crc_imd_reg[15]_0\(14)
    );
\crc_imd_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd[15]_i_2__0_n_0\,
      Q => \^crc_imd_reg[15]_0\(15)
    );
\crc_imd_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd[1]_i_1__0_n_0\,
      Q => \^crc_imd_reg[15]_0\(1)
    );
\crc_imd_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd_reg[9]_3\(0),
      Q => \^crc_imd_reg[15]_0\(2)
    );
\crc_imd_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd_reg[9]_3\(1),
      Q => \^crc_imd_reg[15]_0\(3)
    );
\crc_imd_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd_reg[9]_3\(2),
      Q => \^crc_imd_reg[15]_0\(4)
    );
\crc_imd_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd_reg[9]_3\(3),
      Q => \^crc_imd_reg[15]_0\(5)
    );
\crc_imd_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd_reg[9]_3\(4),
      Q => \^crc_imd_reg[15]_0\(6)
    );
\crc_imd_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd[7]_i_1__0_n_0\,
      Q => \^crc_imd_reg[15]_0\(7)
    );
\crc_imd_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd[8]_i_1__0_n_0\,
      Q => \^crc_imd_reg[15]_0\(8)
    );
\crc_imd_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1__0_n_0\,
      CLR => first_reg_0(0),
      D => \crc_imd_reg[9]_3\(5),
      Q => \^crc_imd_reg[15]_0\(9)
    );
\first_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A2F"
    )
        port map (
      I0 => first,
      I1 => AXIS_tvalid,
      I2 => \^stateop_reg_0\,
      I3 => AXIS_tlast,
      O => \first_i_1__0_n_0\
    );
first_reg: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \first_i_1__0_n_0\,
      PRE => first_reg_0(0),
      Q => first
    );
\len[15]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"01FF"
    )
        port map (
      I0 => \tixVController[7]_i_3__0_n_0\,
      I1 => Q(3),
      I2 => Q(4),
      I3 => \txlen_reg[3]\,
      O => \stateOp_reg[3]\(0)
    );
\retbuf[0][0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800FFFFB800B800"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \retbuf_reg[0][0]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[0][0]_0\,
      I4 => \retbuf_reg[0][0]_1\,
      I5 => \retbuf_reg[0][1]\(0),
      O => \^d\(0)
    );
\retbuf[0][1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5500FC00"
    )
        port map (
      I0 => \retbuf[0][1]_i_2__0_n_0\,
      I1 => \retbuf_reg[0][1]\(1),
      I2 => \retbuf_reg[0][3]\,
      I3 => \txlen_reg[3]\,
      I4 => \retbuf_reg[33][0]\,
      O => \^d\(1)
    );
\retbuf[0][1]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"01FD"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(9),
      O => \retbuf[0][1]_i_2__0_n_0\
    );
\retbuf[0][2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8880"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(2),
      O => \^d\(2)
    );
\retbuf[0][3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E2E20000FF000000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(11),
      I1 => \retbuf_reg[0][0]\,
      I2 => \^crc_imd_reg[15]_0\(3),
      I3 => \retbuf_reg[0][3]\,
      I4 => \txlen_reg[3]\,
      I5 => \retbuf_reg[33][0]\,
      O => \^d\(3)
    );
\retbuf[0][4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8B80000FF000000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \retbuf_reg[0][0]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[0][3]\,
      I4 => \txlen_reg[3]\,
      I5 => \retbuf_reg[33][0]\,
      O => \^d\(4)
    );
\retbuf[0][5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A808AAAA00000000"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \retbuf_reg[0][0]\,
      I3 => \^crc_imd_reg[15]_0\(5),
      I4 => \retbuf_reg[33][0]\,
      I5 => \retbuf_reg[0][6]\,
      O => \^d\(5)
    );
\retbuf[0][6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A808AAAA00000000"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[0][0]\,
      I3 => \^crc_imd_reg[15]_0\(6),
      I4 => \retbuf_reg[33][0]\,
      I5 => \retbuf_reg[0][6]\,
      O => \^d\(6)
    );
\retbuf[0][7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE02000000000000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(15),
      I4 => \txlen_reg[3]\,
      I5 => \retbuf_reg[33][0]\,
      O => \^d\(7)
    );
\retbuf[15][1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFD555D00000000"
    )
        port map (
      I0 => \retbuf_reg[33][0]\,
      I1 => \^crc_imd_reg[15]_0\(1),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => \^crc_imd_reg[15]_0\(9),
      I5 => \txlen_reg[3]\,
      O => \crc_imd_reg[1]_0\
    );
\retbuf[15][2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFD555D00000000"
    )
        port map (
      I0 => \retbuf_reg[33][0]\,
      I1 => \^crc_imd_reg[15]_0\(2),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => \^crc_imd_reg[15]_0\(10),
      I5 => \txlen_reg[3]\,
      O => \crc_imd_reg[2]_2\
    );
\retbuf[15][3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFD555D00000000"
    )
        port map (
      I0 => \retbuf_reg[33][0]\,
      I1 => \^crc_imd_reg[15]_0\(3),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => \^crc_imd_reg[15]_0\(11),
      I5 => \txlen_reg[3]\,
      O => \crc_imd_reg[3]_2\
    );
\retbuf[1][0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555500015555FFFD"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \retbuf_reg[1][0]\(0),
      I2 => \retbuf_reg[1][0]\(2),
      I3 => \retbuf_reg[1][0]\(1),
      I4 => \retbuf_reg[0][0]\,
      I5 => \^crc_imd_reg[15]_0\(8),
      O => \crc_imd_reg[0]_2\
    );
\retbuf[1][2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555500015555FFFD"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \retbuf_reg[1][0]\(0),
      I2 => \retbuf_reg[1][0]\(2),
      I3 => \retbuf_reg[1][0]\(1),
      I4 => \retbuf_reg[0][0]\,
      I5 => \^crc_imd_reg[15]_0\(10),
      O => \crc_imd_reg[2]_3\
    );
\retbuf[1][4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555500015555FFFD"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \retbuf_reg[1][0]\(0),
      I2 => \retbuf_reg[1][0]\(2),
      I3 => \retbuf_reg[1][0]\(1),
      I4 => \retbuf_reg[0][0]\,
      I5 => \^crc_imd_reg[15]_0\(12),
      O => \crc_imd_reg[4]_0\
    );
\retbuf[1][5]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555500015555FFFD"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(5),
      I1 => \retbuf_reg[1][0]\(0),
      I2 => \retbuf_reg[1][0]\(2),
      I3 => \retbuf_reg[1][0]\(1),
      I4 => \retbuf_reg[0][0]\,
      I5 => \^crc_imd_reg[15]_0\(13),
      O => \crc_imd_reg[5]_0\
    );
\retbuf[1][6]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555500015555FFFD"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \retbuf_reg[1][0]\(0),
      I2 => \retbuf_reg[1][0]\(2),
      I3 => \retbuf_reg[1][0]\(1),
      I4 => \retbuf_reg[0][0]\,
      I5 => \^crc_imd_reg[15]_0\(14),
      O => \crc_imd_reg[6]_2\
    );
\retbuf[2][0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800FFFFB800B800"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \retbuf_reg[0][0]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[0][0]_0\,
      I4 => \retbuf_reg[0][0]_1\,
      I5 => \retbuf_reg[2][7]\(8),
      O => \tkst_reg[23]\(0)
    );
\retbuf[2][1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5500FC00"
    )
        port map (
      I0 => \retbuf[0][1]_i_2__0_n_0\,
      I1 => \retbuf_reg[2][7]\(9),
      I2 => \retbuf_reg[0][3]\,
      I3 => \txlen_reg[3]\,
      I4 => \retbuf_reg[33][0]\,
      O => \tkst_reg[23]\(1)
    );
\retbuf[2][2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5500FC00"
    )
        port map (
      I0 => \retbuf[2][2]_i_2__0_n_0\,
      I1 => \retbuf_reg[2][7]\(10),
      I2 => \retbuf_reg[0][3]\,
      I3 => \txlen_reg[3]\,
      I4 => \retbuf_reg[33][0]\,
      O => \tkst_reg[23]\(2)
    );
\retbuf[2][2]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"01FD"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(10),
      O => \retbuf[2][2]_i_2__0_n_0\
    );
\retbuf[2][3]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^crc_imd_reg[3]_0\,
      I1 => \retbuf_reg[0][0]_1\,
      I2 => \retbuf_reg[2][7]\(11),
      O => \tkst_reg[23]\(3)
    );
\retbuf[2][4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5500FC00"
    )
        port map (
      I0 => \retbuf[2][4]_i_2__0_n_0\,
      I1 => \retbuf_reg[2][7]\(12),
      I2 => \retbuf_reg[0][3]\,
      I3 => \txlen_reg[3]\,
      I4 => \retbuf_reg[33][0]\,
      O => \tkst_reg[23]\(4)
    );
\retbuf[2][4]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"01FD"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(12),
      O => \retbuf[2][4]_i_2__0_n_0\
    );
\retbuf[2][5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^crc_imd_reg[6]_1\(3),
      I1 => \retbuf_reg[0][6]\,
      I2 => \retbuf_reg[2][7]\(13),
      O => \tkst_reg[23]\(5)
    );
\retbuf[2][6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^crc_imd_reg[6]_1\(4),
      I1 => \retbuf_reg[0][6]\,
      I2 => \retbuf_reg[2][7]\(14),
      O => \tkst_reg[23]\(6)
    );
\retbuf[2][7]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^d\(7),
      I1 => \retbuf_reg[0][0]_1\,
      I2 => \retbuf_reg[2][7]\(15),
      O => \tkst_reg[23]\(7)
    );
\retbuf[31][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFD555D00000000"
    )
        port map (
      I0 => \retbuf_reg[33][0]\,
      I1 => \^crc_imd_reg[15]_0\(0),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => \^crc_imd_reg[15]_0\(8),
      I5 => \txlen_reg[3]\,
      O => \crc_imd_reg[0]_1\
    );
\retbuf[32][4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFD555D00000000"
    )
        port map (
      I0 => \retbuf_reg[33][0]\,
      I1 => \^crc_imd_reg[15]_0\(4),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => \^crc_imd_reg[15]_0\(12),
      I5 => \txlen_reg[3]\,
      O => \^crc_imd_reg[6]_1\(2)
    );
\retbuf[32][6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFD555D00000000"
    )
        port map (
      I0 => \retbuf_reg[33][0]\,
      I1 => \^crc_imd_reg[15]_0\(6),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => \^crc_imd_reg[15]_0\(14),
      I5 => \txlen_reg[3]\,
      O => \^crc_imd_reg[6]_1\(4)
    );
\retbuf[33][0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88AA88AA8AAA80AA"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(0),
      I2 => \retbuf_reg[0][0]\,
      I3 => \retbuf_reg[33][0]\,
      I4 => \^crc_imd_reg[15]_0\(8),
      I5 => \retbuf_reg[33][0]_0\,
      O => \crc_imd_reg[15]_3\(0)
    );
\retbuf[33][1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88AA88AA8AAA80AA"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(1),
      I2 => \retbuf_reg[0][0]\,
      I3 => \retbuf_reg[33][0]\,
      I4 => \^crc_imd_reg[15]_0\(9),
      I5 => \retbuf_reg[33][0]_0\,
      O => \crc_imd_reg[15]_3\(1)
    );
\retbuf[33][2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA888A00008880"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => \retbuf_reg[33][0]_0\,
      I5 => \^crc_imd_reg[15]_0\(2),
      O => \crc_imd_reg[15]_3\(2)
    );
\retbuf[33][3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA888A00008880"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => \retbuf_reg[33][0]_0\,
      I5 => \^crc_imd_reg[15]_0\(3),
      O => \crc_imd_reg[15]_3\(3)
    );
\retbuf[33][4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88AA88AA8AAA80AA"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(4),
      I2 => \retbuf_reg[0][0]\,
      I3 => \retbuf_reg[33][0]\,
      I4 => \^crc_imd_reg[15]_0\(12),
      I5 => \retbuf_reg[33][0]_0\,
      O => \crc_imd_reg[15]_3\(4)
    );
\retbuf[33][5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \retbuf_reg[0][0]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[33][0]_0\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[33][0]\,
      O => \crc_imd_reg[15]_3\(5)
    );
\retbuf[33][6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88AA88AA8AAA80AA"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(6),
      I2 => \retbuf_reg[0][0]\,
      I3 => \retbuf_reg[33][0]\,
      I4 => \^crc_imd_reg[15]_0\(14),
      I5 => \retbuf_reg[33][0]_0\,
      O => \crc_imd_reg[15]_3\(6)
    );
\retbuf[33][7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA888A00008880"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => \retbuf_reg[33][0]_0\,
      I5 => \^crc_imd_reg[15]_0\(7),
      O => \crc_imd_reg[15]_3\(7)
    );
\retbuf[36][0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(0),
      O => \crc_imd_reg[15]_2\(0)
    );
\retbuf[36][1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(1),
      O => \crc_imd_reg[15]_2\(1)
    );
\retbuf[36][2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(2),
      O => \crc_imd_reg[15]_2\(2)
    );
\retbuf[36][3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(3),
      O => \crc_imd_reg[15]_2\(3)
    );
\retbuf[36][4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(4),
      O => \crc_imd_reg[15]_2\(4)
    );
\retbuf[36][5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(5),
      O => \crc_imd_reg[15]_2\(5)
    );
\retbuf[36][6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(6),
      O => \crc_imd_reg[15]_2\(6)
    );
\retbuf[36][7]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(7),
      O => \crc_imd_reg[15]_2\(7)
    );
\retbuf[37][0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(0),
      O => \crc_imd_reg[15]_1\(0)
    );
\retbuf[37][1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(1),
      O => \crc_imd_reg[15]_1\(1)
    );
\retbuf[37][2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(2),
      O => \crc_imd_reg[15]_1\(2)
    );
\retbuf[37][3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(3),
      O => \crc_imd_reg[15]_1\(3)
    );
\retbuf[37][4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(4),
      O => \crc_imd_reg[15]_1\(4)
    );
\retbuf[37][5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(5),
      O => \crc_imd_reg[15]_1\(5)
    );
\retbuf[37][6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(6),
      O => \crc_imd_reg[15]_1\(6)
    );
\retbuf[37][7]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(7),
      O => \crc_imd_reg[15]_1\(7)
    );
\retbuf[38][0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8880"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(0),
      O => \crc_imd_reg[15]_5\(0)
    );
\retbuf[38][1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8880"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(1),
      O => \crc_imd_reg[15]_5\(1)
    );
\retbuf[38][2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8880"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(2),
      O => \crc_imd_reg[15]_5\(2)
    );
\retbuf[38][3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8880"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(3),
      O => \crc_imd_reg[15]_5\(3)
    );
\retbuf[38][4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8880"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(4),
      O => \crc_imd_reg[15]_5\(4)
    );
\retbuf[38][5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8880"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(5),
      O => \crc_imd_reg[15]_5\(5)
    );
\retbuf[38][6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8880"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(6),
      O => \crc_imd_reg[15]_5\(6)
    );
\retbuf[38][7]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8880"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(7),
      O => \crc_imd_reg[15]_5\(7)
    );
\retbuf[3][0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5500FC00"
    )
        port map (
      I0 => \retbuf[3][0]_i_2__0_n_0\,
      I1 => \retbuf_reg[2][7]\(0),
      I2 => \retbuf_reg[0][3]\,
      I3 => \txlen_reg[3]\,
      I4 => \retbuf_reg[33][0]\,
      O => \tkst_reg[15]\(0)
    );
\retbuf[3][0]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"01FD"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(8),
      O => \retbuf[3][0]_i_2__0_n_0\
    );
\retbuf[3][1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5500FC00"
    )
        port map (
      I0 => \retbuf[0][1]_i_2__0_n_0\,
      I1 => \retbuf_reg[2][7]\(1),
      I2 => \retbuf_reg[0][3]\,
      I3 => \txlen_reg[3]\,
      I4 => \retbuf_reg[33][0]\,
      O => \tkst_reg[15]\(1)
    );
\retbuf[3][2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800FFFFB800B800"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \retbuf_reg[0][0]\,
      I2 => \^crc_imd_reg[15]_0\(10),
      I3 => \retbuf_reg[0][0]_0\,
      I4 => \retbuf_reg[0][0]_1\,
      I5 => \retbuf_reg[2][7]\(2),
      O => \tkst_reg[15]\(2)
    );
\retbuf[3][3]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^crc_imd_reg[3]_0\,
      I1 => \retbuf_reg[0][0]_1\,
      I2 => \retbuf_reg[2][7]\(3),
      O => \tkst_reg[15]\(3)
    );
\retbuf[3][4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5500FC00"
    )
        port map (
      I0 => \retbuf[2][4]_i_2__0_n_0\,
      I1 => \retbuf_reg[2][7]\(4),
      I2 => \retbuf_reg[0][3]\,
      I3 => \txlen_reg[3]\,
      I4 => \retbuf_reg[33][0]\,
      O => \tkst_reg[15]\(4)
    );
\retbuf[3][5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^crc_imd_reg[6]_1\(3),
      I1 => \retbuf_reg[0][6]\,
      I2 => \retbuf_reg[2][7]\(5),
      O => \tkst_reg[15]\(5)
    );
\retbuf[3][6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^crc_imd_reg[6]_1\(4),
      I1 => \retbuf_reg[0][6]\,
      I2 => \retbuf_reg[2][7]\(6),
      O => \tkst_reg[15]\(6)
    );
\retbuf[3][7]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^d\(7),
      I1 => \retbuf_reg[0][0]_1\,
      I2 => \retbuf_reg[2][7]\(7),
      O => \tkst_reg[15]\(7)
    );
\retbuf[4][4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555500105555FFDF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \retbuf_reg[1][0]\(2),
      I2 => \retbuf_reg[1][0]\(0),
      I3 => \retbuf_reg[1][0]\(1),
      I4 => \retbuf_reg[0][0]\,
      I5 => \^crc_imd_reg[15]_0\(12),
      O => \crc_imd_reg[4]_1\
    );
\retbuf[4][5]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555500105555FFDF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(5),
      I1 => \retbuf_reg[1][0]\(2),
      I2 => \retbuf_reg[1][0]\(0),
      I3 => \retbuf_reg[1][0]\(1),
      I4 => \retbuf_reg[0][0]\,
      I5 => \^crc_imd_reg[15]_0\(13),
      O => \crc_imd_reg[5]_2\
    );
\retbuf[4][6]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555500105555FFDF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \retbuf_reg[1][0]\(2),
      I2 => \retbuf_reg[1][0]\(0),
      I3 => \retbuf_reg[1][0]\(1),
      I4 => \retbuf_reg[0][0]\,
      I5 => \^crc_imd_reg[15]_0\(14),
      O => \crc_imd_reg[6]_3\
    );
\retbuf[5][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555501005555FDFF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(5),
      I1 => \retbuf_reg[1][0]\(0),
      I2 => \retbuf_reg[1][0]\(2),
      I3 => \retbuf_reg[1][0]\(1),
      I4 => \retbuf_reg[0][0]\,
      I5 => \^crc_imd_reg[15]_0\(13),
      O => \crc_imd_reg[5]_1\
    );
\retbuf[6][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800FFFFB800B800"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \retbuf_reg[0][0]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[0][0]_0\,
      I4 => \retbuf_reg[0][0]_1\,
      I5 => \retbuf_reg[6][7]\(0),
      O => \scoreMax_reg[7]\(0)
    );
\retbuf[6][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800FFFFB800B800"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \retbuf_reg[0][0]\,
      I2 => \^crc_imd_reg[15]_0\(9),
      I3 => \retbuf_reg[0][0]_0\,
      I4 => \retbuf_reg[0][0]_1\,
      I5 => \retbuf_reg[6][7]\(1),
      O => \scoreMax_reg[7]\(1)
    );
\retbuf[6][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800FFFFB800B800"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \retbuf_reg[0][0]\,
      I2 => \^crc_imd_reg[15]_0\(10),
      I3 => \retbuf_reg[0][0]_0\,
      I4 => \retbuf_reg[0][0]_1\,
      I5 => \retbuf_reg[6][7]\(2),
      O => \scoreMax_reg[7]\(2)
    );
\retbuf[6][3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^crc_imd_reg[3]_0\,
      I1 => \retbuf_reg[0][0]_1\,
      I2 => \retbuf_reg[6][7]\(3),
      O => \scoreMax_reg[7]\(3)
    );
\retbuf[6][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800FFFFB800B800"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \retbuf_reg[0][0]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[0][0]_0\,
      I4 => \retbuf_reg[0][0]_1\,
      I5 => \retbuf_reg[6][7]\(4),
      O => \scoreMax_reg[7]\(4)
    );
\retbuf[6][5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^crc_imd_reg[6]_1\(3),
      I1 => \retbuf_reg[0][6]\,
      I2 => \retbuf_reg[6][7]\(5),
      O => \scoreMax_reg[7]\(5)
    );
\retbuf[6][6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55003000"
    )
        port map (
      I0 => \retbuf[6][6]_i_2__0_n_0\,
      I1 => \retbuf_reg[0][3]\,
      I2 => \retbuf_reg[6][7]\(6),
      I3 => \txlen_reg[3]\,
      I4 => \retbuf_reg[33][0]\,
      O => \scoreMax_reg[7]\(6)
    );
\retbuf[6][6]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"01FD"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(14),
      O => \retbuf[6][6]_i_2__0_n_0\
    );
\retbuf[6][7]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^d\(7),
      I1 => \retbuf_reg[0][0]_1\,
      I2 => \retbuf_reg[6][7]\(7),
      O => \scoreMax_reg[7]\(7)
    );
\retbuf[7][0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8880"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(0),
      O => \^crc_imd_reg[6]_1\(0)
    );
\retbuf[7][1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8880"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(1),
      O => \^crc_imd_reg[6]_1\(1)
    );
\retbuf[7][3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE02000000000000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(11),
      I4 => \txlen_reg[3]\,
      I5 => \retbuf_reg[33][0]\,
      O => \^crc_imd_reg[3]_0\
    );
\retbuf[7][4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8880"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(4),
      O => \crc_imd_reg[14]_1\(0)
    );
\retbuf[7][5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFD555D00000000"
    )
        port map (
      I0 => \retbuf_reg[33][0]\,
      I1 => \^crc_imd_reg[15]_0\(5),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => \^crc_imd_reg[15]_0\(13),
      I5 => \txlen_reg[3]\,
      O => \^crc_imd_reg[6]_1\(3)
    );
\retbuf[7][6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8880"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(6),
      O => \crc_imd_reg[14]_1\(1)
    );
\retbuf[8][0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[8][0]\,
      I3 => \^crc_imd_reg[15]_0\(0),
      O => \crc_imd_reg[15]_4\(0)
    );
\retbuf[8][1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[8][0]\,
      I3 => \^crc_imd_reg[15]_0\(1),
      O => \crc_imd_reg[15]_4\(1)
    );
\retbuf[8][2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[8][0]\,
      I3 => \^crc_imd_reg[15]_0\(2),
      O => \crc_imd_reg[15]_4\(2)
    );
\retbuf[8][3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[8][0]\,
      I3 => \^crc_imd_reg[15]_0\(3),
      O => \crc_imd_reg[15]_4\(3)
    );
\retbuf[8][4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[8][0]\,
      I3 => \^crc_imd_reg[15]_0\(4),
      O => \crc_imd_reg[15]_4\(4)
    );
\retbuf[8][5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \retbuf_reg[0][0]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[8][5]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[33][0]\,
      O => \crc_imd_reg[15]_4\(5)
    );
\retbuf[8][6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[8][0]\,
      I3 => \^crc_imd_reg[15]_0\(6),
      O => \crc_imd_reg[15]_4\(6)
    );
\retbuf[8][7]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][0]_0\,
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[8][0]\,
      I3 => \^crc_imd_reg[15]_0\(7),
      O => \crc_imd_reg[15]_4\(7)
    );
\stateOp[0]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F3FAF0F0"
    )
        port map (
      I0 => \^crc_imd_reg[3]_3\,
      I1 => \stateOp_reg[2]_0\(0),
      I2 => Q(0),
      I3 => Q(1),
      I4 => Q(2),
      O => \stateOp_next_reg[0]\
    );
\stateOp[2]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F00F3FAF"
    )
        port map (
      I0 => \^crc_imd_reg[3]_3\,
      I1 => \stateOp_reg[2]_0\(1),
      I2 => Q(2),
      I3 => Q(1),
      I4 => Q(0),
      O => \stateOp_next_reg[2]\
    );
\stateOp[3]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(5),
      I1 => \^crc_imd_reg[15]_0\(4),
      I2 => \^crc_imd_reg[15]_0\(7),
      I3 => \^crc_imd_reg[15]_0\(6),
      O => \stateOp[3]_i_10_n_0\
    );
\stateOp[3]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(8),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \^crc_imd_reg[15]_0\(10),
      I3 => \^crc_imd_reg[15]_0\(11),
      I4 => \stateOp[3]_i_12_n_0\,
      O => \stateOp[3]_i_11_n_0\
    );
\stateOp[3]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(13),
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \^crc_imd_reg[15]_0\(14),
      I3 => \^crc_imd_reg[15]_0\(15),
      O => \stateOp[3]_i_12_n_0\
    );
\stateOp[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \stateOp[3]_i_10_n_0\,
      I1 => \^crc_imd_reg[15]_0\(3),
      I2 => \^crc_imd_reg[15]_0\(2),
      I3 => \^crc_imd_reg[15]_0\(1),
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \stateOp[3]_i_11_n_0\,
      O => \^crc_imd_reg[3]_3\
    );
\stateOp[4]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20C32CC3FFFFFFFF"
    )
        port map (
      I0 => \^crc_imd_reg[3]_3\,
      I1 => \stateOp_reg[4]_1\,
      I2 => Q(1),
      I3 => Q(0),
      I4 => \crc_imd_reg[0]_8\,
      I5 => \stateOp_reg[4]_2\,
      O => \stateOp_reg[1]\
    );
stateOp_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => first_reg_0(0),
      D => stateOp_reg_3,
      Q => \^stateop_reg_0\
    );
\tixVController[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01FF00FF01FF01FF"
    )
        port map (
      I0 => \tixVController[7]_i_3__0_n_0\,
      I1 => Q(3),
      I2 => Q(4),
      I3 => \txlen_reg[3]\,
      I4 => \tixVCommand_reg[0]\,
      I5 => \tixVCommand_reg[0]_0\(0),
      O => \stateOp_reg[3]_0\(0)
    );
\tixVController[7]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => \^crc_imd_reg[3]_3\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(2),
      O => \tixVController[7]_i_3__0_n_0\
    );
\txAXIS_tdata[0]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80FFFF8A808A80"
    )
        port map (
      I0 => Q(3),
      I1 => \txAXIS_tdata_reg[6]\(0),
      I2 => \txAXIS_tdata_reg[10]\,
      I3 => \txAXIS_tdata_reg[6]_0\(0),
      I4 => \txAXIS_tdata[0]_i_6__0_n_0\,
      I5 => Q(1),
      O => \stateOp_reg[3]_2\
    );
\txAXIS_tdata[0]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0301030003010303"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(8),
      I1 => Q(0),
      I2 => Q(3),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => \retbuf_reg[31][0]\(0),
      I5 => \^crc_imd_reg[15]_0\(0),
      O => \txAXIS_tdata[0]_i_6__0_n_0\
    );
\txAXIS_tdata[10]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABABABAAAAABAAAA"
    )
        port map (
      I0 => \txAXIS_tdata[10]_i_5__0_n_0\,
      I1 => Q(4),
      I2 => Q(1),
      I3 => \txAXIS_tdata_reg[10]\,
      I4 => \txAXIS_tdata_reg[10]_0\(0),
      I5 => \txAXIS_tdata_reg[10]_1\(0),
      O => \stateOp_reg[4]\
    );
\txAXIS_tdata[10]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28082000"
    )
        port map (
      I0 => Q(1),
      I1 => \retbuf_reg[31][0]\(1),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(2),
      I4 => \^crc_imd_reg[15]_0\(10),
      O => \txAXIS_tdata[10]_i_5__0_n_0\
    );
\txAXIS_tdata[11]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"9DBFFFFF"
    )
        port map (
      I0 => \retbuf_reg[31][0]\(1),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(3),
      I3 => \^crc_imd_reg[15]_0\(11),
      I4 => Q(1),
      O => \resid_reg[1]_1\
    );
\txAXIS_tdata[12]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F53F"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(12),
      I1 => \^crc_imd_reg[15]_0\(4),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      O => \crc_imd_reg[12]_1\
    );
\txAXIS_tdata[13]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28082000"
    )
        port map (
      I0 => Q(1),
      I1 => \retbuf_reg[31][0]\(1),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(5),
      I4 => \^crc_imd_reg[15]_0\(13),
      O => \stateOp_reg[1]_4\
    );
\txAXIS_tdata[14]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F53F"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(14),
      I1 => \^crc_imd_reg[15]_0\(6),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      O => \crc_imd_reg[14]_2\
    );
\txAXIS_tdata[15]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28082000"
    )
        port map (
      I0 => Q(1),
      I1 => \retbuf_reg[31][0]\(1),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(7),
      I4 => \^crc_imd_reg[15]_0\(15),
      O => \stateOp_reg[1]_5\
    );
\txAXIS_tdata[16]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888AAA888A8"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \txAXIS_tdata_reg[16]\,
      I2 => \^crc_imd_reg[15]_0\(0),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(8),
      I5 => \txAXIS_tdata_reg[16]_0\,
      O => \crc_imd_reg[2]_1\(0)
    );
\txAXIS_tdata[17]_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(9),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(1),
      O => \crc_imd_reg[9]_2\
    );
\txAXIS_tdata[18]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888AAA888A8"
    )
        port map (
      I0 => \txlen_reg[3]\,
      I1 => \txAXIS_tdata_reg[18]\,
      I2 => \^crc_imd_reg[15]_0\(2),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(10),
      I5 => \txAXIS_tdata_reg[16]_0\,
      O => \crc_imd_reg[2]_1\(1)
    );
\txAXIS_tdata[19]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"777FFF7F"
    )
        port map (
      I0 => \retbuf_reg[31][0]\(1),
      I1 => Q(1),
      I2 => \^crc_imd_reg[15]_0\(3),
      I3 => \retbuf_reg[31][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(11),
      O => \resid_reg[1]_2\
    );
\txAXIS_tdata[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF00B80000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(9),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(1),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => Q(1),
      I5 => Q(3),
      O => \crc_imd_reg[9]_1\
    );
\txAXIS_tdata[20]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2000000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => Q(1),
      I4 => \retbuf_reg[31][0]\(1),
      O => \crc_imd_reg[4]_2\
    );
\txAXIS_tdata[21]_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(13),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(5),
      O => \crc_imd_reg[13]_2\
    );
\txAXIS_tdata[22]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1DFFFFFF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(14),
      I3 => Q(1),
      I4 => \retbuf_reg[31][0]\(1),
      O => \crc_imd_reg[6]_4\
    );
\txAXIS_tdata[23]_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(15),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(7),
      O => \crc_imd_reg[15]_7\
    );
\txAXIS_tdata[24]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5FF3"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      O => \crc_imd_reg[0]_3\
    );
\txAXIS_tdata[25]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5FF3"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      O => \crc_imd_reg[1]_1\
    );
\txAXIS_tdata[26]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAABAA"
    )
        port map (
      I0 => \txAXIS_tdata[26]_i_6__0_n_0\,
      I1 => Q(4),
      I2 => Q(1),
      I3 => \txAXIS_tdata_reg[26]\(0),
      I4 => \txAXIS_tdata_reg[10]\,
      O => \stateOp_reg[4]_0\
    );
\txAXIS_tdata[26]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A0000808"
    )
        port map (
      I0 => Q(1),
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(2),
      I4 => \retbuf_reg[31][0]\(0),
      O => \txAXIS_tdata[26]_i_6__0_n_0\
    );
\txAXIS_tdata[27]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F7FF5FF"
    )
        port map (
      I0 => Q(1),
      I1 => \^crc_imd_reg[15]_0\(3),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(11),
      I4 => \retbuf_reg[31][0]\(1),
      O => \stateOp_reg[1]_0\
    );
\txAXIS_tdata[28]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F7FF5FF"
    )
        port map (
      I0 => Q(1),
      I1 => \^crc_imd_reg[15]_0\(4),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(12),
      I4 => \retbuf_reg[31][0]\(1),
      O => \stateOp_reg[1]_1\
    );
\txAXIS_tdata[29]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A0000808"
    )
        port map (
      I0 => Q(1),
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \retbuf_reg[31][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(5),
      I4 => \retbuf_reg[31][0]\(0),
      O => \stateOp_reg[1]_2\
    );
\txAXIS_tdata[2]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80FFFF8A808A80"
    )
        port map (
      I0 => Q(3),
      I1 => \txAXIS_tdata_reg[6]\(1),
      I2 => \txAXIS_tdata_reg[10]\,
      I3 => \txAXIS_tdata_reg[6]_0\(1),
      I4 => \txAXIS_tdata[2]_i_6__0_n_0\,
      I5 => Q(1),
      O => \stateOp_reg[3]_3\
    );
\txAXIS_tdata[2]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0301030003010303"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(10),
      I1 => Q(0),
      I2 => Q(3),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => \retbuf_reg[31][0]\(0),
      I5 => \^crc_imd_reg[15]_0\(2),
      O => \txAXIS_tdata[2]_i_6__0_n_0\
    );
\txAXIS_tdata[30]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F7FF5FF"
    )
        port map (
      I0 => Q(1),
      I1 => \^crc_imd_reg[15]_0\(6),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(14),
      I4 => \retbuf_reg[31][0]\(1),
      O => \stateOp_reg[1]_3\
    );
\txAXIS_tdata[31]_i_8__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5FF3FFFF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[31][0]\(0),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => Q(1),
      O => \crc_imd_reg[7]_1\
    );
\txAXIS_tdata[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF00B80000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(11),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(3),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => Q(1),
      I5 => Q(3),
      O => \crc_imd_reg[11]_0\
    );
\txAXIS_tdata[4]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80FFFF8A808A80"
    )
        port map (
      I0 => Q(3),
      I1 => \txAXIS_tdata_reg[6]\(2),
      I2 => \txAXIS_tdata_reg[10]\,
      I3 => \txAXIS_tdata_reg[6]_0\(2),
      I4 => \txAXIS_tdata[4]_i_7__0_n_0\,
      I5 => Q(1),
      O => \stateOp_reg[3]_4\
    );
\txAXIS_tdata[4]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0301030003010303"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(12),
      I1 => Q(0),
      I2 => Q(3),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => \retbuf_reg[31][0]\(0),
      I5 => \^crc_imd_reg[15]_0\(4),
      O => \txAXIS_tdata[4]_i_7__0_n_0\
    );
\txAXIS_tdata[5]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF00B80000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(13),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(5),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => Q(1),
      I5 => Q(3),
      O => \crc_imd_reg[13]_1\
    );
\txAXIS_tdata[6]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80FFFF8A808A80"
    )
        port map (
      I0 => Q(3),
      I1 => \txAXIS_tdata_reg[6]\(3),
      I2 => \txAXIS_tdata_reg[10]\,
      I3 => \txAXIS_tdata_reg[6]_0\(3),
      I4 => \txAXIS_tdata[6]_i_9__0_n_0\,
      I5 => Q(1),
      O => \stateOp_reg[3]_5\
    );
\txAXIS_tdata[6]_i_9__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0301030003010303"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(14),
      I1 => Q(0),
      I2 => Q(3),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => \retbuf_reg[31][0]\(0),
      I5 => \^crc_imd_reg[15]_0\(6),
      O => \txAXIS_tdata[6]_i_9__0_n_0\
    );
\txAXIS_tdata[7]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF00B80000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(15),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(7),
      I3 => \retbuf_reg[31][0]\(1),
      I4 => Q(1),
      I5 => Q(3),
      O => \crc_imd_reg[15]_6\
    );
\txAXIS_tdata[8]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"9DBFFFFF"
    )
        port map (
      I0 => \retbuf_reg[31][0]\(1),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(0),
      I3 => \^crc_imd_reg[15]_0\(8),
      I4 => Q(1),
      O => \resid_reg[1]\
    );
\txAXIS_tdata[9]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"9DBFFFFF"
    )
        port map (
      I0 => \retbuf_reg[31][0]\(1),
      I1 => \retbuf_reg[31][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(1),
      I3 => \^crc_imd_reg[15]_0\(9),
      I4 => Q(1),
      O => \resid_reg[1]_0\
    );
\txlen[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \txlen[3]_i_2_n_0\,
      I1 => \txlen_reg[3]\,
      O => E(0)
    );
\txlen[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"040000000CC00C00"
    )
        port map (
      I0 => \^crc_imd_reg[3]_3\,
      I1 => Q(2),
      I2 => Q(3),
      I3 => Q(0),
      I4 => Q(1),
      I5 => Q(4),
      O => \txlen[3]_i_2_n_0\
    );
\validCrc_sig_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAF0F0A8F0AAAA"
    )
        port map (
      I0 => \crc_imd[15]_i_3_n_0\,
      I1 => first,
      I2 => validCrc_sig_reg_n_0,
      I3 => AXIS_tvalid,
      I4 => \^stateop_reg_0\,
      I5 => AXIS_tlast,
      O => \validCrc_sig_i_1__0_n_0\
    );
validCrc_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => first_reg_0(0),
      D => \validCrc_sig_i_1__0_n_0\,
      Q => validCrc_sig_reg_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Crc8005_64 is
  port (
    stateOp_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \crc_imd_reg[15]_1\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
    \stateOp_reg[0]\ : out STD_LOGIC;
    \opbuf_reg[2][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \crc_imd_reg[14]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \crc_imd_reg[15]_2\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[15]_3\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[15]_4\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[15]_5\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[15]_6\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[15]_7\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_1\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_2\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_3\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_4\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_5\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_6\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_7\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_8\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_9\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_10\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_11\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_12\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_13\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_14\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[15]_8\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[15]_9\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_15\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \crc_imd_reg[13]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \crc_imd_reg[14]_1\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
    \crc_imd_reg[7]_16\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \crc_imd_reg[7]_17\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \crc_imd_reg[8]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \crc_imd_reg[11]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \stateOp_reg[1]\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    \stateOp_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[5]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[3]\ : out STD_LOGIC;
    \stateOp_reg[2]\ : out STD_LOGIC;
    \stateOp_reg[1]_0\ : out STD_LOGIC;
    \stateOp_reg[1]_1\ : out STD_LOGIC;
    \stateOp_reg[3]_0\ : out STD_LOGIC;
    \stateOp_reg[3]_1\ : out STD_LOGIC;
    \stateOp_reg[4]_0\ : out STD_LOGIC;
    \stateOp_reg[4]_1\ : out STD_LOGIC;
    \stateOp_reg[1]_2\ : out STD_LOGIC;
    \crc_imd_reg[7]_18\ : out STD_LOGIC;
    \crc_imd_reg[6]_0\ : out STD_LOGIC;
    \stateOp_reg[3]_2\ : out STD_LOGIC;
    \crc_imd_reg[4]_0\ : out STD_LOGIC;
    \crc_imd_reg[3]_0\ : out STD_LOGIC;
    \crc_imd_reg[2]_0\ : out STD_LOGIC;
    \stateOp_reg[3]_3\ : out STD_LOGIC;
    \crc_imd_reg[0]_0\ : out STD_LOGIC;
    \crc_imd_reg[9]_0\ : out STD_LOGIC;
    \tixVBuffer_reg[7]\ : out STD_LOGIC;
    \tixVBuffer_reg[7]_0\ : out STD_LOGIC;
    \tixVBuffer_reg[7]_1\ : out STD_LOGIC;
    \tixVBuffer_reg[7]_2\ : out STD_LOGIC;
    \tixVBuffer_reg[7]_3\ : out STD_LOGIC;
    \crc_imd_reg[14]_2\ : out STD_LOGIC;
    \tixVBuffer_reg[7]_4\ : out STD_LOGIC;
    \crc_imd_reg[13]_1\ : out STD_LOGIC;
    \tixVBuffer_reg[7]_5\ : out STD_LOGIC;
    \tixVBuffer_reg[7]_6\ : out STD_LOGIC;
    \tixVBuffer_reg[7]_7\ : out STD_LOGIC;
    \crc_imd_reg[10]_0\ : out STD_LOGIC;
    \tixVBuffer_reg[7]_8\ : out STD_LOGIC;
    \tixVBuffer_reg[7]_9\ : out STD_LOGIC;
    \crc_imd_reg[8]_1\ : out STD_LOGIC;
    \crc_imd_reg[10]_1\ : out STD_LOGIC;
    \pollbuf_reg[0][4]\ : out STD_LOGIC;
    \pollbuf_reg[0][6]\ : out STD_LOGIC;
    \crc_imd_reg[15]_10\ : out STD_LOGIC;
    \resid_reg[0]\ : out STD_LOGIC;
    \resid_reg[0]_0\ : out STD_LOGIC;
    \resid_reg[0]_1\ : out STD_LOGIC;
    \resid_reg[0]_2\ : out STD_LOGIC;
    \resid_reg[0]_3\ : out STD_LOGIC;
    \resid_reg[0]_4\ : out STD_LOGIC;
    \resid_reg[0]_5\ : out STD_LOGIC;
    \crc_imd_reg[15]_11\ : out STD_LOGIC;
    \crc_imd_reg[13]_2\ : out STD_LOGIC;
    \crc_imd_reg[12]_0\ : out STD_LOGIC;
    \crc_imd_reg[9]_1\ : out STD_LOGIC;
    \crc_imd_reg[8]_2\ : out STD_LOGIC;
    \resid_reg[1]\ : out STD_LOGIC;
    \resid_reg[1]_0\ : out STD_LOGIC;
    \resid_reg[1]_1\ : out STD_LOGIC;
    \resid_reg[2]\ : out STD_LOGIC;
    \resid_reg[2]_0\ : out STD_LOGIC;
    \resid_reg[2]_1\ : out STD_LOGIC;
    \resid_reg[2]_2\ : out STD_LOGIC;
    \resid_reg[2]_3\ : out STD_LOGIC;
    \resid_reg[2]_4\ : out STD_LOGIC;
    \crc_imd_reg[14]_3\ : out STD_LOGIC;
    \crc_imd_reg[15]_12\ : out STD_LOGIC;
    \crcAXIS_tkeep_reg[2]\ : out STD_LOGIC;
    \crcAXIS_tkeep_reg[2]_0\ : out STD_LOGIC;
    \recvAXIS_tdata_sig_reg[11]\ : out STD_LOGIC;
    \crcAXIS_tkeep_reg[6]\ : out STD_LOGIC;
    \crcAXIS_tkeep_reg[6]_0\ : out STD_LOGIC;
    \crcAXIS_tkeep_reg[4]\ : out STD_LOGIC;
    \crcAXIS_tkeep_reg[4]_0\ : out STD_LOGIC;
    \crcAXIS_tkeep_reg[6]_1\ : out STD_LOGIC;
    \crcAXIS_tkeep_reg[6]_2\ : out STD_LOGIC;
    \crcAXIS_tkeep_reg[6]_3\ : out STD_LOGIC;
    \crcAXIS_tkeep_reg[6]_4\ : out STD_LOGIC;
    \crc_imd_reg[6]_1\ : out STD_LOGIC;
    \crc_imd_reg[15]_13\ : out STD_LOGIC;
    \crc_imd_reg[8]_3\ : out STD_LOGIC;
    \crc_imd_reg[3]_1\ : out STD_LOGIC;
    \crc_imd_reg[3]_2\ : out STD_LOGIC;
    \crc_imd_reg[4]_1\ : out STD_LOGIC;
    \crc_imd_reg[7]_19\ : out STD_LOGIC;
    \crc_imd_reg[2]_1\ : out STD_LOGIC;
    p_10_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    stateOp_reg_1 : in STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    \crc_imd_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \txlen_reg[28]\ : in STD_LOGIC;
    \txlen_reg[28]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \retbuf_reg[0][6]\ : in STD_LOGIC;
    \len_reg[0]\ : in STD_LOGIC;
    \len_reg[0]_0\ : in STD_LOGIC;
    \retbuf_reg[6][0]\ : in STD_LOGIC;
    \retbuf_reg[5][7]\ : in STD_LOGIC;
    \retbuf_reg[4][6]\ : in STD_LOGIC;
    \retbuf_reg[5][7]_0\ : in STD_LOGIC;
    \retbuf_reg[5][6]\ : in STD_LOGIC;
    \retbuf_reg[5][5]\ : in STD_LOGIC;
    \retbuf_reg[5][4]\ : in STD_LOGIC;
    \retbuf_reg[5][3]\ : in STD_LOGIC;
    \retbuf_reg[5][2]\ : in STD_LOGIC;
    \retbuf_reg[5][1]\ : in STD_LOGIC;
    \retbuf_reg[5][0]\ : in STD_LOGIC;
    \retbuf_reg[6][7]\ : in STD_LOGIC;
    \retbuf_reg[6][7]_0\ : in STD_LOGIC;
    \retbuf_reg[6][6]\ : in STD_LOGIC;
    \retbuf_reg[6][4]\ : in STD_LOGIC;
    \retbuf_reg[6][3]\ : in STD_LOGIC;
    \retbuf_reg[6][2]\ : in STD_LOGIC;
    \retbuf_reg[6][1]\ : in STD_LOGIC;
    \retbuf_reg[6][0]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \txAXIS_tdata_reg[0]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[3]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[8]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[1]\ : in STD_LOGIC;
    \tixVCommand_reg[0]\ : in STD_LOGIC;
    \tixVCommand_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \retbuf_reg[4][6]_0\ : in STD_LOGIC;
    \retbuf_reg[4][6]_1\ : in STD_LOGIC;
    \retbuf_reg[4][5]\ : in STD_LOGIC;
    \retbuf_reg[4][4]\ : in STD_LOGIC;
    \retbuf_reg[39][0]\ : in STD_LOGIC;
    \retbuf_reg[38][0]\ : in STD_LOGIC;
    \retbuf_reg[37][0]\ : in STD_LOGIC;
    \retbuf_reg[36][0]\ : in STD_LOGIC;
    \retbuf_reg[35][5]\ : in STD_LOGIC;
    \retbuf_reg[35][5]_0\ : in STD_LOGIC;
    \retbuf_reg[34][0]\ : in STD_LOGIC;
    \retbuf_reg[33][0]\ : in STD_LOGIC;
    \retbuf_reg[3][5]\ : in STD_LOGIC;
    \retbuf_reg[32][4]\ : in STD_LOGIC;
    \retbuf_reg[32][6]\ : in STD_LOGIC;
    \retbuf_reg[31][0]\ : in STD_LOGIC;
    \retbuf_reg[30][1]\ : in STD_LOGIC;
    \retbuf_reg[30][1]_0\ : in STD_LOGIC;
    \retbuf_reg[29][0]\ : in STD_LOGIC;
    \retbuf_reg[28][0]\ : in STD_LOGIC;
    \retbuf_reg[27][5]\ : in STD_LOGIC;
    \retbuf_reg[26][1]\ : in STD_LOGIC;
    \retbuf_reg[25][0]\ : in STD_LOGIC;
    \retbuf_reg[24][0]\ : in STD_LOGIC;
    \retbuf_reg[23][1]\ : in STD_LOGIC;
    \retbuf_reg[22][0]\ : in STD_LOGIC;
    \retbuf_reg[21][3]\ : in STD_LOGIC;
    \retbuf_reg[20][0]\ : in STD_LOGIC;
    \retbuf_reg[19][5]\ : in STD_LOGIC;
    \retbuf_reg[18][5]\ : in STD_LOGIC;
    \retbuf_reg[17][0]\ : in STD_LOGIC;
    \retbuf_reg[16][0]\ : in STD_LOGIC;
    \retbuf_reg[7][3]\ : in STD_LOGIC;
    \retbuf_reg[7][3]_0\ : in STD_LOGIC;
    \retbuf_reg[3][0]\ : in STD_LOGIC;
    \retbuf_reg[3][0]_0\ : in STD_LOGIC;
    \retbuf_reg[3][1]\ : in STD_LOGIC;
    \retbuf_reg[3][4]\ : in STD_LOGIC;
    \retbuf_reg[3][5]_0\ : in STD_LOGIC;
    \retbuf_reg[2][0]\ : in STD_LOGIC;
    \retbuf_reg[2][0]_0\ : in STD_LOGIC;
    \retbuf_reg[2][1]\ : in STD_LOGIC;
    \retbuf_reg[2][2]\ : in STD_LOGIC;
    \retbuf_reg[2][3]\ : in STD_LOGIC;
    \retbuf_reg[2][4]\ : in STD_LOGIC;
    \retbuf_reg[2][5]\ : in STD_LOGIC;
    \retbuf_reg[2][6]\ : in STD_LOGIC;
    \retbuf_reg[1][0]\ : in STD_LOGIC;
    \retbuf_reg[1][0]_0\ : in STD_LOGIC;
    \retbuf_reg[1][1]\ : in STD_LOGIC;
    \retbuf_reg[1][2]\ : in STD_LOGIC;
    \retbuf_reg[1][4]\ : in STD_LOGIC;
    \retbuf_reg[1][5]\ : in STD_LOGIC;
    \retbuf_reg[1][6]\ : in STD_LOGIC;
    \retbuf_reg[0][1]\ : in STD_LOGIC;
    \retbuf_reg[0][1]_0\ : in STD_LOGIC;
    \retbuf_reg[0][3]\ : in STD_LOGIC;
    \retbuf_reg[0][4]\ : in STD_LOGIC;
    \retbuf_reg[0][5]\ : in STD_LOGIC;
    \retbuf_reg[0][6]_0\ : in STD_LOGIC;
    \retbuf_reg[1][7]\ : in STD_LOGIC;
    \retbuf_reg[1][7]_0\ : in STD_LOGIC;
    \retbuf_reg[1][7]_1\ : in STD_LOGIC;
    \retbuf_reg[1][3]\ : in STD_LOGIC;
    \retbuf_reg[34][7]\ : in STD_LOGIC;
    \retbuf_reg[35][0]\ : in STD_LOGIC;
    \retbuf_reg[32][0]\ : in STD_LOGIC;
    \retbuf_reg[30][0]\ : in STD_LOGIC;
    \retbuf_reg[28][1]\ : in STD_LOGIC;
    \retbuf_reg[27][0]\ : in STD_LOGIC;
    \retbuf_reg[26][0]\ : in STD_LOGIC;
    \retbuf_reg[25][1]\ : in STD_LOGIC;
    \retbuf_reg[24][1]\ : in STD_LOGIC;
    \retbuf_reg[23][0]\ : in STD_LOGIC;
    \retbuf_reg[22][1]\ : in STD_LOGIC;
    \retbuf_reg[21][0]\ : in STD_LOGIC;
    \retbuf_reg[20][1]\ : in STD_LOGIC;
    \retbuf_reg[19][0]\ : in STD_LOGIC;
    \retbuf_reg[18][0]\ : in STD_LOGIC;
    \retbuf_reg[17][1]\ : in STD_LOGIC;
    \retbuf_reg[16][1]\ : in STD_LOGIC;
    \retbuf_reg[15][0]\ : in STD_LOGIC;
    \retbuf_reg[11][0]\ : in STD_LOGIC;
    \retbuf_reg[4][1]\ : in STD_LOGIC;
    \retbuf_reg[4][2]\ : in STD_LOGIC;
    \retbuf_reg[0][7]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[1]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[1]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[1]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[1]_3\ : in STD_LOGIC;
    \txAXIS_tdata_reg[3]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[8]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[9]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[10]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[11]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[12]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[13]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[14]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[15]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[40]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[41]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[42]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[43]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[44]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[45]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[46]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[47]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \crc_imd_reg[0]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]_3\ : in STD_LOGIC;
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[0]_0\ : in STD_LOGIC;
    \stateOp_reg[2]_1\ : in STD_LOGIC;
    \stateOp_reg[5]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateOp_reg[0]_1\ : in STD_LOGIC;
    \stateOp_reg[5]_2\ : in STD_LOGIC;
    \stateOp_reg[5]_3\ : in STD_LOGIC;
    \stateOp_reg[5]_4\ : in STD_LOGIC;
    \stateOp_reg[5]_5\ : in STD_LOGIC;
    \txAXIS_tdata_reg[0]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[0]_1\ : in STD_LOGIC;
    \txAXIS_tdata[0]_i_2_0\ : in STD_LOGIC;
    \txAXIS_tdata[0]_i_2_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[62]\ : in STD_LOGIC;
    \txAXIS_tdata[0]_i_2_2\ : in STD_LOGIC;
    \txAXIS_tdata[2]_i_3_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]_4\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]_5\ : in STD_LOGIC;
    \txAXIS_tdata_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \txAXIS_tdata_reg[5]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[39]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[39]_0\ : in STD_LOGIC;
    \retbuf_reg[0][0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \txAXIS_tdata_reg[38]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[37]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[36]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[35]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[34]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[33]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[32]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[1]_4\ : in STD_LOGIC;
    \txAXIS_tdata_reg[62]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[62]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[62]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[59]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[59]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[58]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[58]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[55]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[55]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[55]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[54]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[54]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[53]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[53]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[52]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[52]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[51]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[51]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[50]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[50]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[49]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[49]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[48]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[48]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[15]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[15]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[14]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[14]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[13]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[13]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[12]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[12]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[11]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[11]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[10]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[10]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[9]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[9]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[8]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[8]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[47]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[47]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[47]_2\ : in STD_LOGIC;
    \txAXIS_tdata_reg[46]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[46]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[45]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[45]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[44]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[44]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[43]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[43]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[42]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[42]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[41]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[41]_1\ : in STD_LOGIC;
    \txAXIS_tdata_reg[40]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[40]_1\ : in STD_LOGIC;
    \txAXIS_tdata[15]_i_6_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \txAXIS_tdata_reg[4]\ : in STD_LOGIC;
    \txAXIS_tdata_reg[4]_0\ : in STD_LOGIC;
    \txAXIS_tdata_reg[2]\ : in STD_LOGIC;
    \retbuf_reg[0][0]_0\ : in STD_LOGIC;
    \retbuf_reg[3][7]\ : in STD_LOGIC;
    \retbuf_reg[6][5]\ : in STD_LOGIC;
    \retbuf_reg[7][5]\ : in STD_LOGIC;
    \crc_imd_reg[3]_3\ : in STD_LOGIC;
    \crc_imd_reg[3]_4\ : in STD_LOGIC;
    \crc_imd_reg[5]_0\ : in STD_LOGIC;
    \crc_imd_reg[6]_2\ : in STD_LOGIC;
    \crc_imd_reg[7]_20\ : in STD_LOGIC;
    \crc_imd_reg[7]_21\ : in STD_LOGIC;
    \crc_imd_reg[7]_22\ : in STD_LOGIC;
    p_136_in : in STD_LOGIC;
    \crc_imd_reg[7]_23\ : in STD_LOGIC;
    crc_imd0148_out : in STD_LOGIC;
    crc_imd065_out : in STD_LOGIC;
    crc_imd081_out : in STD_LOGIC;
    crc_imd0149_out : in STD_LOGIC;
    crc_imd066_out : in STD_LOGIC;
    crc_imd083_out : in STD_LOGIC;
    crc_imd0150_out : in STD_LOGIC;
    crc_imd067_out : in STD_LOGIC;
    crc_imd085_out : in STD_LOGIC;
    crc_imd0151_out : in STD_LOGIC;
    crc_imd068_out : in STD_LOGIC;
    crc_imd086_out : in STD_LOGIC;
    crc_imd0152_out : in STD_LOGIC;
    crc_imd069_out : in STD_LOGIC;
    crc_imd087_out : in STD_LOGIC;
    crc_imd0112_out : in STD_LOGIC;
    crc_imd041_out : in STD_LOGIC;
    crc_imd0115_out : in STD_LOGIC;
    crc_imd042_out : in STD_LOGIC;
    crc_imd0118_out : in STD_LOGIC;
    crc_imd043_out : in STD_LOGIC;
    crc_imd0121_out : in STD_LOGIC;
    crc_imd0124_out : in STD_LOGIC;
    \crc_imd_reg[0]_3\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
    \crc_imd_reg[0]_4\ : in STD_LOGIC;
    recvAXIS_tlast : in STD_LOGIC;
    \crc_imd_reg[0]_5\ : in STD_LOGIC;
    crc_imd0175_out : in STD_LOGIC;
    crc_imd0198_out : in STD_LOGIC;
    crc_imd0176_out : in STD_LOGIC;
    crc_imd0200_out : in STD_LOGIC;
    crc_imd0165_out : in STD_LOGIC;
    crc_imd0202_out : in STD_LOGIC;
    crc_imd0100_out : in STD_LOGIC;
    crc_imd0172_out : in STD_LOGIC;
    crc_imd0173_out : in STD_LOGIC;
    crc_imd0174_out : in STD_LOGIC;
    AXIS_tdata : in STD_LOGIC_VECTOR ( 12 downto 0 );
    \crc_imd[15]_i_21\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \crc_imd[15]_i_21_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \crc_imd[15]_i_18\ : in STD_LOGIC;
    AXIS_tvalid : in STD_LOGIC;
    AXIS_tlast : in STD_LOGIC;
    \crc_imd_reg[15]_14\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Crc8005_64 : entity is "Crc8005_64";
end design_1_Vsp_core_0_0_Crc8005_64;

architecture STRUCTURE of design_1_Vsp_core_0_0_Crc8005_64 is
  signal commok_sig_i_3_n_0 : STD_LOGIC;
  signal \^crcaxis_tkeep_reg[2]\ : STD_LOGIC;
  signal \^crcaxis_tkeep_reg[2]_0\ : STD_LOGIC;
  signal \^crcaxis_tkeep_reg[4]\ : STD_LOGIC;
  signal \^crcaxis_tkeep_reg[4]_0\ : STD_LOGIC;
  signal \^crcaxis_tkeep_reg[6]\ : STD_LOGIC;
  signal \^crcaxis_tkeep_reg[6]_2\ : STD_LOGIC;
  signal \^crcaxis_tkeep_reg[6]_3\ : STD_LOGIC;
  signal \^crcaxis_tkeep_reg[6]_4\ : STD_LOGIC;
  signal crc_imd013_out : STD_LOGIC;
  signal crc_imd044_out : STD_LOGIC;
  signal crc_imd046_out : STD_LOGIC;
  signal \crc_imd[10]_i_1_n_0\ : STD_LOGIC;
  signal \crc_imd[10]_i_2_n_0\ : STD_LOGIC;
  signal \crc_imd[10]_i_3_n_0\ : STD_LOGIC;
  signal \crc_imd[10]_i_4_n_0\ : STD_LOGIC;
  signal \crc_imd[11]_i_1_n_0\ : STD_LOGIC;
  signal \crc_imd[11]_i_2_n_0\ : STD_LOGIC;
  signal \crc_imd[11]_i_3_n_0\ : STD_LOGIC;
  signal \crc_imd[11]_i_4_n_0\ : STD_LOGIC;
  signal \crc_imd[12]_i_1_n_0\ : STD_LOGIC;
  signal \crc_imd[12]_i_2_n_0\ : STD_LOGIC;
  signal \crc_imd[12]_i_3_n_0\ : STD_LOGIC;
  signal \crc_imd[12]_i_4_n_0\ : STD_LOGIC;
  signal \crc_imd[13]_i_1_n_0\ : STD_LOGIC;
  signal \crc_imd[13]_i_2_n_0\ : STD_LOGIC;
  signal \crc_imd[13]_i_3_n_0\ : STD_LOGIC;
  signal \crc_imd[13]_i_4_n_0\ : STD_LOGIC;
  signal \crc_imd[14]_i_1_n_0\ : STD_LOGIC;
  signal \crc_imd[14]_i_4_n_0\ : STD_LOGIC;
  signal \crc_imd[14]_i_5_n_0\ : STD_LOGIC;
  signal \crc_imd[14]_i_6_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_12_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_13_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_14_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_1_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_43_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_44_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_45_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_46_n_0\ : STD_LOGIC;
  signal \crc_imd[15]_i_5_n_0\ : STD_LOGIC;
  signal \crc_imd[3]_i_1_n_0\ : STD_LOGIC;
  signal \crc_imd[3]_i_4_n_0\ : STD_LOGIC;
  signal \crc_imd[5]_i_1_n_0\ : STD_LOGIC;
  signal \crc_imd[5]_i_4_n_0\ : STD_LOGIC;
  signal \crc_imd[5]_i_5_n_0\ : STD_LOGIC;
  signal \crc_imd[6]_i_1_n_0\ : STD_LOGIC;
  signal \crc_imd[6]_i_5_n_0\ : STD_LOGIC;
  signal \crc_imd[6]_i_6_n_0\ : STD_LOGIC;
  signal \crc_imd[7]_i_1_n_0\ : STD_LOGIC;
  signal \crc_imd[7]_i_2_n_0\ : STD_LOGIC;
  signal \crc_imd[7]_i_8_n_0\ : STD_LOGIC;
  signal \^crc_imd_reg[10]_0\ : STD_LOGIC;
  signal \^crc_imd_reg[13]_1\ : STD_LOGIC;
  signal \^crc_imd_reg[14]_2\ : STD_LOGIC;
  signal \^crc_imd_reg[15]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^crc_imd_reg[3]_2\ : STD_LOGIC;
  signal \^crc_imd_reg[4]_1\ : STD_LOGIC;
  signal \^crc_imd_reg[8]_1\ : STD_LOGIC;
  signal \^crc_imd_reg[9]_0\ : STD_LOGIC;
  signal first : STD_LOGIC;
  signal first_i_1_n_0 : STD_LOGIC;
  signal \^recvaxis_tdata_sig_reg[11]\ : STD_LOGIC;
  signal \stateOp[0]_i_6_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_7__1_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_10_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_11_n_0\ : STD_LOGIC;
  signal \^stateop_reg[0]\ : STD_LOGIC;
  signal \^stateop_reg[2]\ : STD_LOGIC;
  signal \^stateop_reg[4]\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^stateop_reg_0\ : STD_LOGIC;
  signal \tixVBuffer[7]_i_5_n_0\ : STD_LOGIC;
  signal \tixVBuffer[7]_i_6_n_0\ : STD_LOGIC;
  signal \tixVBuffer[7]_i_7_n_0\ : STD_LOGIC;
  signal \tixVBuffer[7]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[0]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[0]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[10]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[10]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[10]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[11]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[11]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[11]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[12]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[12]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[12]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[13]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[13]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[13]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[14]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[14]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[14]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_16_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_21_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[1]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[2]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[3]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[40]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[40]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[41]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[41]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[42]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[42]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[43]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[43]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[44]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[44]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[45]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[45]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[46]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[46]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[47]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[47]_i_9_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[51]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[52]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[55]_i_12_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[58]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[59]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[5]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[62]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_12_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[8]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[8]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[8]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[9]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[9]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[9]_i_8_n_0\ : STD_LOGIC;
  signal \txlen[28]_i_2_n_0\ : STD_LOGIC;
  signal \txlen[28]_i_3_n_0\ : STD_LOGIC;
  signal validCrc_sig_i_1_n_0 : STD_LOGIC;
  signal validCrc_sig_reg_n_0 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \crc_imd[11]_i_2\ : label is "soft_lutpair1929";
  attribute SOFT_HLUTNM of \crc_imd[14]_i_13\ : label is "soft_lutpair1995";
  attribute SOFT_HLUTNM of \crc_imd[14]_i_15\ : label is "soft_lutpair1995";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_14\ : label is "soft_lutpair1997";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_20\ : label is "soft_lutpair1927";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_26\ : label is "soft_lutpair1928";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_32\ : label is "soft_lutpair1928";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_43\ : label is "soft_lutpair1996";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_44\ : label is "soft_lutpair1996";
  attribute SOFT_HLUTNM of \crc_imd[15]_i_46\ : label is "soft_lutpair1999";
  attribute SOFT_HLUTNM of \crc_imd[3]_i_2\ : label is "soft_lutpair1929";
  attribute SOFT_HLUTNM of \crc_imd[6]_i_4\ : label is "soft_lutpair1999";
  attribute SOFT_HLUTNM of \crc_imd[7]_i_7\ : label is "soft_lutpair1927";
  attribute SOFT_HLUTNM of first_i_1 : label is "soft_lutpair1997";
  attribute SOFT_HLUTNM of \retbuf[11][0]_i_1\ : label is "soft_lutpair1991";
  attribute SOFT_HLUTNM of \retbuf[11][1]_i_1\ : label is "soft_lutpair1992";
  attribute SOFT_HLUTNM of \retbuf[11][2]_i_1\ : label is "soft_lutpair1993";
  attribute SOFT_HLUTNM of \retbuf[11][3]_i_1\ : label is "soft_lutpair1994";
  attribute SOFT_HLUTNM of \retbuf[15][0]_i_1\ : label is "soft_lutpair1984";
  attribute SOFT_HLUTNM of \retbuf[16][1]_i_1\ : label is "soft_lutpair1988";
  attribute SOFT_HLUTNM of \retbuf[16][2]_i_1\ : label is "soft_lutpair1985";
  attribute SOFT_HLUTNM of \retbuf[16][3]_i_1\ : label is "soft_lutpair1989";
  attribute SOFT_HLUTNM of \retbuf[16][7]_i_2\ : label is "soft_lutpair1990";
  attribute SOFT_HLUTNM of \retbuf[17][1]_i_1\ : label is "soft_lutpair1988";
  attribute SOFT_HLUTNM of \retbuf[17][3]_i_1\ : label is "soft_lutpair1989";
  attribute SOFT_HLUTNM of \retbuf[17][6]_i_1\ : label is "soft_lutpair1986";
  attribute SOFT_HLUTNM of \retbuf[17][7]_i_2\ : label is "soft_lutpair1987";
  attribute SOFT_HLUTNM of \retbuf[18][0]_i_1\ : label is "soft_lutpair1984";
  attribute SOFT_HLUTNM of \retbuf[18][1]_i_1\ : label is "soft_lutpair1981";
  attribute SOFT_HLUTNM of \retbuf[18][2]_i_1\ : label is "soft_lutpair1985";
  attribute SOFT_HLUTNM of \retbuf[18][3]_i_1\ : label is "soft_lutpair1982";
  attribute SOFT_HLUTNM of \retbuf[18][4]_i_1\ : label is "soft_lutpair1983";
  attribute SOFT_HLUTNM of \retbuf[18][6]_i_1\ : label is "soft_lutpair1986";
  attribute SOFT_HLUTNM of \retbuf[18][7]_i_2\ : label is "soft_lutpair1987";
  attribute SOFT_HLUTNM of \retbuf[19][0]_i_1\ : label is "soft_lutpair1976";
  attribute SOFT_HLUTNM of \retbuf[19][1]_i_1\ : label is "soft_lutpair1981";
  attribute SOFT_HLUTNM of \retbuf[19][2]_i_1\ : label is "soft_lutpair1978";
  attribute SOFT_HLUTNM of \retbuf[19][3]_i_1\ : label is "soft_lutpair1982";
  attribute SOFT_HLUTNM of \retbuf[19][4]_i_1\ : label is "soft_lutpair1983";
  attribute SOFT_HLUTNM of \retbuf[19][6]_i_1\ : label is "soft_lutpair1979";
  attribute SOFT_HLUTNM of \retbuf[19][7]_i_2\ : label is "soft_lutpair1980";
  attribute SOFT_HLUTNM of \retbuf[20][1]_i_1\ : label is "soft_lutpair1977";
  attribute SOFT_HLUTNM of \retbuf[20][2]_i_1\ : label is "soft_lutpair1978";
  attribute SOFT_HLUTNM of \retbuf[20][3]_i_1\ : label is "soft_lutpair1973";
  attribute SOFT_HLUTNM of \retbuf[20][6]_i_1\ : label is "soft_lutpair1979";
  attribute SOFT_HLUTNM of \retbuf[20][7]_i_2\ : label is "soft_lutpair1980";
  attribute SOFT_HLUTNM of \retbuf[21][0]_i_1\ : label is "soft_lutpair1976";
  attribute SOFT_HLUTNM of \retbuf[21][1]_i_1\ : label is "soft_lutpair1977";
  attribute SOFT_HLUTNM of \retbuf[21][2]_i_1\ : label is "soft_lutpair1972";
  attribute SOFT_HLUTNM of \retbuf[21][6]_i_1\ : label is "soft_lutpair1974";
  attribute SOFT_HLUTNM of \retbuf[21][7]_i_2\ : label is "soft_lutpair1975";
  attribute SOFT_HLUTNM of \retbuf[22][1]_i_1\ : label is "soft_lutpair1969";
  attribute SOFT_HLUTNM of \retbuf[22][3]_i_1\ : label is "soft_lutpair1973";
  attribute SOFT_HLUTNM of \retbuf[22][6]_i_1\ : label is "soft_lutpair1974";
  attribute SOFT_HLUTNM of \retbuf[22][7]_i_2\ : label is "soft_lutpair1975";
  attribute SOFT_HLUTNM of \retbuf[23][0]_i_1\ : label is "soft_lutpair1964";
  attribute SOFT_HLUTNM of \retbuf[23][2]_i_1\ : label is "soft_lutpair1972";
  attribute SOFT_HLUTNM of \retbuf[23][3]_i_1\ : label is "soft_lutpair1970";
  attribute SOFT_HLUTNM of \retbuf[23][4]_i_1\ : label is "soft_lutpair1962";
  attribute SOFT_HLUTNM of \retbuf[23][7]_i_2\ : label is "soft_lutpair1971";
  attribute SOFT_HLUTNM of \retbuf[24][1]_i_1\ : label is "soft_lutpair1969";
  attribute SOFT_HLUTNM of \retbuf[24][2]_i_1\ : label is "soft_lutpair1967";
  attribute SOFT_HLUTNM of \retbuf[24][3]_i_1\ : label is "soft_lutpair1970";
  attribute SOFT_HLUTNM of \retbuf[24][6]_i_1\ : label is "soft_lutpair1968";
  attribute SOFT_HLUTNM of \retbuf[24][7]_i_2\ : label is "soft_lutpair1971";
  attribute SOFT_HLUTNM of \retbuf[25][1]_i_1\ : label is "soft_lutpair1960";
  attribute SOFT_HLUTNM of \retbuf[25][2]_i_1\ : label is "soft_lutpair1967";
  attribute SOFT_HLUTNM of \retbuf[25][3]_i_1\ : label is "soft_lutpair1965";
  attribute SOFT_HLUTNM of \retbuf[25][6]_i_1\ : label is "soft_lutpair1968";
  attribute SOFT_HLUTNM of \retbuf[25][7]_i_2\ : label is "soft_lutpair1966";
  attribute SOFT_HLUTNM of \retbuf[26][0]_i_1\ : label is "soft_lutpair1964";
  attribute SOFT_HLUTNM of \retbuf[26][2]_i_1\ : label is "soft_lutpair1961";
  attribute SOFT_HLUTNM of \retbuf[26][3]_i_1\ : label is "soft_lutpair1965";
  attribute SOFT_HLUTNM of \retbuf[26][6]_i_1\ : label is "soft_lutpair1963";
  attribute SOFT_HLUTNM of \retbuf[26][7]_i_2\ : label is "soft_lutpair1966";
  attribute SOFT_HLUTNM of \retbuf[27][0]_i_1\ : label is "soft_lutpair1956";
  attribute SOFT_HLUTNM of \retbuf[27][1]_i_1\ : label is "soft_lutpair1960";
  attribute SOFT_HLUTNM of \retbuf[27][2]_i_1\ : label is "soft_lutpair1961";
  attribute SOFT_HLUTNM of \retbuf[27][3]_i_1\ : label is "soft_lutpair1958";
  attribute SOFT_HLUTNM of \retbuf[27][4]_i_1\ : label is "soft_lutpair1962";
  attribute SOFT_HLUTNM of \retbuf[27][6]_i_1\ : label is "soft_lutpair1963";
  attribute SOFT_HLUTNM of \retbuf[27][7]_i_2\ : label is "soft_lutpair1959";
  attribute SOFT_HLUTNM of \retbuf[28][1]_i_1\ : label is "soft_lutpair1953";
  attribute SOFT_HLUTNM of \retbuf[28][2]_i_1\ : label is "soft_lutpair1954";
  attribute SOFT_HLUTNM of \retbuf[28][3]_i_1\ : label is "soft_lutpair1958";
  attribute SOFT_HLUTNM of \retbuf[28][4]_i_1\ : label is "soft_lutpair1957";
  attribute SOFT_HLUTNM of \retbuf[28][7]_i_2\ : label is "soft_lutpair1959";
  attribute SOFT_HLUTNM of \retbuf[30][0]_i_1\ : label is "soft_lutpair1956";
  attribute SOFT_HLUTNM of \retbuf[30][4]_i_1\ : label is "soft_lutpair1957";
  attribute SOFT_HLUTNM of \retbuf[30][6]_i_1\ : label is "soft_lutpair1952";
  attribute SOFT_HLUTNM of \retbuf[30][7]_i_2\ : label is "soft_lutpair1955";
  attribute SOFT_HLUTNM of \retbuf[32][0]_i_1\ : label is "soft_lutpair1950";
  attribute SOFT_HLUTNM of \retbuf[32][1]_i_1\ : label is "soft_lutpair1953";
  attribute SOFT_HLUTNM of \retbuf[32][2]_i_1\ : label is "soft_lutpair1954";
  attribute SOFT_HLUTNM of \retbuf[32][3]_i_1\ : label is "soft_lutpair1951";
  attribute SOFT_HLUTNM of \retbuf[32][7]_i_2\ : label is "soft_lutpair1955";
  attribute SOFT_HLUTNM of \retbuf[34][1]_i_1\ : label is "soft_lutpair1949";
  attribute SOFT_HLUTNM of \retbuf[34][2]_i_1\ : label is "soft_lutpair1948";
  attribute SOFT_HLUTNM of \retbuf[34][4]_i_1\ : label is "soft_lutpair1947";
  attribute SOFT_HLUTNM of \retbuf[34][7]_i_2\ : label is "soft_lutpair1946";
  attribute SOFT_HLUTNM of \retbuf[35][0]_i_1\ : label is "soft_lutpair1950";
  attribute SOFT_HLUTNM of \retbuf[35][1]_i_1\ : label is "soft_lutpair1949";
  attribute SOFT_HLUTNM of \retbuf[35][2]_i_1\ : label is "soft_lutpair1948";
  attribute SOFT_HLUTNM of \retbuf[35][3]_i_1\ : label is "soft_lutpair1951";
  attribute SOFT_HLUTNM of \retbuf[35][4]_i_1\ : label is "soft_lutpair1947";
  attribute SOFT_HLUTNM of \retbuf[35][6]_i_1\ : label is "soft_lutpair1952";
  attribute SOFT_HLUTNM of \retbuf[35][7]_i_2\ : label is "soft_lutpair1946";
  attribute SOFT_HLUTNM of \retbuf[36][0]_i_1\ : label is "soft_lutpair1938";
  attribute SOFT_HLUTNM of \retbuf[36][1]_i_1\ : label is "soft_lutpair1939";
  attribute SOFT_HLUTNM of \retbuf[36][2]_i_1\ : label is "soft_lutpair1940";
  attribute SOFT_HLUTNM of \retbuf[36][3]_i_1\ : label is "soft_lutpair1941";
  attribute SOFT_HLUTNM of \retbuf[36][4]_i_1\ : label is "soft_lutpair1942";
  attribute SOFT_HLUTNM of \retbuf[36][5]_i_1\ : label is "soft_lutpair1943";
  attribute SOFT_HLUTNM of \retbuf[36][6]_i_1\ : label is "soft_lutpair1944";
  attribute SOFT_HLUTNM of \retbuf[36][7]_i_2\ : label is "soft_lutpair1945";
  attribute SOFT_HLUTNM of \retbuf[37][0]_i_1\ : label is "soft_lutpair1938";
  attribute SOFT_HLUTNM of \retbuf[37][1]_i_1\ : label is "soft_lutpair1939";
  attribute SOFT_HLUTNM of \retbuf[37][2]_i_1\ : label is "soft_lutpair1940";
  attribute SOFT_HLUTNM of \retbuf[37][3]_i_1\ : label is "soft_lutpair1941";
  attribute SOFT_HLUTNM of \retbuf[37][4]_i_1\ : label is "soft_lutpair1942";
  attribute SOFT_HLUTNM of \retbuf[37][5]_i_1\ : label is "soft_lutpair1943";
  attribute SOFT_HLUTNM of \retbuf[37][6]_i_1\ : label is "soft_lutpair1944";
  attribute SOFT_HLUTNM of \retbuf[37][7]_i_2\ : label is "soft_lutpair1945";
  attribute SOFT_HLUTNM of \retbuf[38][0]_i_1\ : label is "soft_lutpair1930";
  attribute SOFT_HLUTNM of \retbuf[38][1]_i_1\ : label is "soft_lutpair1931";
  attribute SOFT_HLUTNM of \retbuf[38][2]_i_1\ : label is "soft_lutpair1932";
  attribute SOFT_HLUTNM of \retbuf[38][3]_i_1\ : label is "soft_lutpair1933";
  attribute SOFT_HLUTNM of \retbuf[38][4]_i_1\ : label is "soft_lutpair1934";
  attribute SOFT_HLUTNM of \retbuf[38][5]_i_1\ : label is "soft_lutpair1935";
  attribute SOFT_HLUTNM of \retbuf[38][6]_i_1\ : label is "soft_lutpair1936";
  attribute SOFT_HLUTNM of \retbuf[38][7]_i_2\ : label is "soft_lutpair1937";
  attribute SOFT_HLUTNM of \retbuf[39][0]_i_1\ : label is "soft_lutpair1930";
  attribute SOFT_HLUTNM of \retbuf[39][1]_i_1\ : label is "soft_lutpair1931";
  attribute SOFT_HLUTNM of \retbuf[39][2]_i_1\ : label is "soft_lutpair1932";
  attribute SOFT_HLUTNM of \retbuf[39][3]_i_1\ : label is "soft_lutpair1933";
  attribute SOFT_HLUTNM of \retbuf[39][4]_i_1\ : label is "soft_lutpair1934";
  attribute SOFT_HLUTNM of \retbuf[39][5]_i_1\ : label is "soft_lutpair1935";
  attribute SOFT_HLUTNM of \retbuf[39][6]_i_1\ : label is "soft_lutpair1936";
  attribute SOFT_HLUTNM of \retbuf[39][7]_i_2\ : label is "soft_lutpair1937";
  attribute SOFT_HLUTNM of \retbuf[4][7]_i_8\ : label is "soft_lutpair1990";
  attribute SOFT_HLUTNM of \retbuf[7][0]_i_1\ : label is "soft_lutpair1991";
  attribute SOFT_HLUTNM of \retbuf[7][1]_i_1\ : label is "soft_lutpair1992";
  attribute SOFT_HLUTNM of \retbuf[7][2]_i_1\ : label is "soft_lutpair1993";
  attribute SOFT_HLUTNM of \txAXIS_tdata[10]_i_8\ : label is "soft_lutpair1921";
  attribute SOFT_HLUTNM of \txAXIS_tdata[11]_i_8\ : label is "soft_lutpair1920";
  attribute SOFT_HLUTNM of \txAXIS_tdata[12]_i_8\ : label is "soft_lutpair1924";
  attribute SOFT_HLUTNM of \txAXIS_tdata[13]_i_8\ : label is "soft_lutpair1925";
  attribute SOFT_HLUTNM of \txAXIS_tdata[14]_i_8\ : label is "soft_lutpair1926";
  attribute SOFT_HLUTNM of \txAXIS_tdata[15]_i_21\ : label is "soft_lutpair1919";
  attribute SOFT_HLUTNM of \txAXIS_tdata[16]_i_3\ : label is "soft_lutpair1922";
  attribute SOFT_HLUTNM of \txAXIS_tdata[17]_i_3\ : label is "soft_lutpair1923";
  attribute SOFT_HLUTNM of \txAXIS_tdata[18]_i_3\ : label is "soft_lutpair1998";
  attribute SOFT_HLUTNM of \txAXIS_tdata[21]_i_3\ : label is "soft_lutpair1925";
  attribute SOFT_HLUTNM of \txAXIS_tdata[22]_i_3\ : label is "soft_lutpair1926";
  attribute SOFT_HLUTNM of \txAXIS_tdata[30]_i_3\ : label is "soft_lutpair1918";
  attribute SOFT_HLUTNM of \txAXIS_tdata[31]_i_5\ : label is "soft_lutpair1913";
  attribute SOFT_HLUTNM of \txAXIS_tdata[40]_i_7\ : label is "soft_lutpair1917";
  attribute SOFT_HLUTNM of \txAXIS_tdata[41]_i_7\ : label is "soft_lutpair1916";
  attribute SOFT_HLUTNM of \txAXIS_tdata[42]_i_7\ : label is "soft_lutpair1921";
  attribute SOFT_HLUTNM of \txAXIS_tdata[43]_i_7\ : label is "soft_lutpair1920";
  attribute SOFT_HLUTNM of \txAXIS_tdata[44]_i_7\ : label is "soft_lutpair1915";
  attribute SOFT_HLUTNM of \txAXIS_tdata[45]_i_7\ : label is "soft_lutpair1914";
  attribute SOFT_HLUTNM of \txAXIS_tdata[46]_i_7\ : label is "soft_lutpair1918";
  attribute SOFT_HLUTNM of \txAXIS_tdata[47]_i_9\ : label is "soft_lutpair1919";
  attribute SOFT_HLUTNM of \txAXIS_tdata[51]_i_7\ : label is "soft_lutpair1994";
  attribute SOFT_HLUTNM of \txAXIS_tdata[52]_i_7\ : label is "soft_lutpair1924";
  attribute SOFT_HLUTNM of \txAXIS_tdata[55]_i_12\ : label is "soft_lutpair1998";
  attribute SOFT_HLUTNM of \txAXIS_tdata[56]_i_2\ : label is "soft_lutpair1917";
  attribute SOFT_HLUTNM of \txAXIS_tdata[57]_i_2\ : label is "soft_lutpair1916";
  attribute SOFT_HLUTNM of \txAXIS_tdata[60]_i_2\ : label is "soft_lutpair1915";
  attribute SOFT_HLUTNM of \txAXIS_tdata[61]_i_2\ : label is "soft_lutpair1914";
  attribute SOFT_HLUTNM of \txAXIS_tdata[63]_i_6\ : label is "soft_lutpair1913";
  attribute SOFT_HLUTNM of \txAXIS_tdata[8]_i_8\ : label is "soft_lutpair1922";
  attribute SOFT_HLUTNM of \txAXIS_tdata[9]_i_8\ : label is "soft_lutpair1923";
begin
  \crcAXIS_tkeep_reg[2]\ <= \^crcaxis_tkeep_reg[2]\;
  \crcAXIS_tkeep_reg[2]_0\ <= \^crcaxis_tkeep_reg[2]_0\;
  \crcAXIS_tkeep_reg[4]\ <= \^crcaxis_tkeep_reg[4]\;
  \crcAXIS_tkeep_reg[4]_0\ <= \^crcaxis_tkeep_reg[4]_0\;
  \crcAXIS_tkeep_reg[6]\ <= \^crcaxis_tkeep_reg[6]\;
  \crcAXIS_tkeep_reg[6]_2\ <= \^crcaxis_tkeep_reg[6]_2\;
  \crcAXIS_tkeep_reg[6]_3\ <= \^crcaxis_tkeep_reg[6]_3\;
  \crcAXIS_tkeep_reg[6]_4\ <= \^crcaxis_tkeep_reg[6]_4\;
  \crc_imd_reg[10]_0\ <= \^crc_imd_reg[10]_0\;
  \crc_imd_reg[13]_1\ <= \^crc_imd_reg[13]_1\;
  \crc_imd_reg[14]_2\ <= \^crc_imd_reg[14]_2\;
  \crc_imd_reg[15]_0\(15 downto 0) <= \^crc_imd_reg[15]_0\(15 downto 0);
  \crc_imd_reg[3]_2\ <= \^crc_imd_reg[3]_2\;
  \crc_imd_reg[4]_1\ <= \^crc_imd_reg[4]_1\;
  \crc_imd_reg[8]_1\ <= \^crc_imd_reg[8]_1\;
  \crc_imd_reg[9]_0\ <= \^crc_imd_reg[9]_0\;
  \recvAXIS_tdata_sig_reg[11]\ <= \^recvaxis_tdata_sig_reg[11]\;
  \stateOp_reg[0]\ <= \^stateop_reg[0]\;
  \stateOp_reg[2]\ <= \^stateop_reg[2]\;
  \stateOp_reg[4]\(0) <= \^stateop_reg[4]\(0);
  stateOp_reg_0 <= \^stateop_reg_0\;
commok_sig_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7E3F"
    )
        port map (
      I0 => Q(3),
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(2),
      I4 => commok_sig_i_3_n_0,
      O => \stateOp_reg[3]\
    );
commok_sig_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFBBFF8FFFBBFFB"
    )
        port map (
      I0 => \tixVBuffer[7]_i_5_n_0\,
      I1 => Q(2),
      I2 => Q(3),
      I3 => Q(4),
      I4 => Q(5),
      I5 => \crc_imd_reg[0]_2\,
      O => commok_sig_i_3_n_0
    );
\crc_imd[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF8"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \^crcaxis_tkeep_reg[2]\,
      I2 => \crc_imd_reg[3]_3\,
      I3 => \crc_imd[10]_i_2_n_0\,
      I4 => \crc_imd[10]_i_3_n_0\,
      I5 => \crc_imd[10]_i_4_n_0\,
      O => \crc_imd[10]_i_1_n_0\
    );
\crc_imd[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28828228"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[2]_0\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \^crc_imd_reg[15]_0\(9),
      I3 => AXIS_tdata(0),
      I4 => AXIS_tdata(1),
      O => \crc_imd[10]_i_2_n_0\
    );
\crc_imd[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]_2\,
      I1 => crc_imd0148_out,
      I2 => \^crcaxis_tkeep_reg[6]_3\,
      I3 => crc_imd0172_out,
      I4 => crc_imd081_out,
      I5 => \^crcaxis_tkeep_reg[6]_4\,
      O => \crc_imd[10]_i_3_n_0\
    );
\crc_imd[10]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]\,
      I1 => crc_imd0112_out,
      I2 => \^crcaxis_tkeep_reg[4]\,
      I3 => crc_imd041_out,
      I4 => crc_imd065_out,
      I5 => \^crcaxis_tkeep_reg[4]_0\,
      O => \crc_imd[10]_i_4_n_0\
    );
\crc_imd[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF8"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \^crcaxis_tkeep_reg[2]\,
      I2 => \crc_imd_reg[3]_3\,
      I3 => \crc_imd[11]_i_2_n_0\,
      I4 => \crc_imd[11]_i_3_n_0\,
      I5 => \crc_imd[11]_i_4_n_0\,
      O => \crc_imd[11]_i_1_n_0\
    );
\crc_imd[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28828228"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[2]_0\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => AXIS_tdata(2),
      I3 => AXIS_tdata(1),
      I4 => \^crc_imd_reg[15]_0\(9),
      O => \crc_imd[11]_i_2_n_0\
    );
\crc_imd[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]_2\,
      I1 => crc_imd0149_out,
      I2 => \^crcaxis_tkeep_reg[6]_3\,
      I3 => crc_imd0173_out,
      I4 => crc_imd083_out,
      I5 => \^crcaxis_tkeep_reg[6]_4\,
      O => \crc_imd[11]_i_3_n_0\
    );
\crc_imd[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]\,
      I1 => crc_imd0115_out,
      I2 => \^crcaxis_tkeep_reg[4]\,
      I3 => crc_imd042_out,
      I4 => crc_imd066_out,
      I5 => \^crcaxis_tkeep_reg[4]_0\,
      O => \crc_imd[11]_i_4_n_0\
    );
\crc_imd[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF8"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \^crcaxis_tkeep_reg[2]\,
      I2 => \crc_imd_reg[3]_3\,
      I3 => \crc_imd[12]_i_2_n_0\,
      I4 => \crc_imd[12]_i_3_n_0\,
      I5 => \crc_imd[12]_i_4_n_0\,
      O => \crc_imd[12]_i_1_n_0\
    );
\crc_imd[12]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28828228"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[2]_0\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \^crc_imd_reg[15]_0\(10),
      I3 => AXIS_tdata(3),
      I4 => AXIS_tdata(2),
      O => \crc_imd[12]_i_2_n_0\
    );
\crc_imd[12]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]_2\,
      I1 => crc_imd0150_out,
      I2 => \^crcaxis_tkeep_reg[6]_3\,
      I3 => crc_imd0174_out,
      I4 => crc_imd085_out,
      I5 => \^crcaxis_tkeep_reg[6]_4\,
      O => \crc_imd[12]_i_3_n_0\
    );
\crc_imd[12]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]\,
      I1 => crc_imd0118_out,
      I2 => \^crcaxis_tkeep_reg[4]\,
      I3 => crc_imd043_out,
      I4 => crc_imd067_out,
      I5 => \^crcaxis_tkeep_reg[4]_0\,
      O => \crc_imd[12]_i_4_n_0\
    );
\crc_imd[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF8"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(5),
      I1 => \^crcaxis_tkeep_reg[2]\,
      I2 => \crc_imd_reg[3]_3\,
      I3 => \crc_imd[13]_i_2_n_0\,
      I4 => \crc_imd[13]_i_3_n_0\,
      I5 => \crc_imd[13]_i_4_n_0\,
      O => \crc_imd[13]_i_1_n_0\
    );
\crc_imd[13]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28828228"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[2]_0\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => AXIS_tdata(3),
      I4 => AXIS_tdata(4),
      O => \crc_imd[13]_i_2_n_0\
    );
\crc_imd[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]_2\,
      I1 => crc_imd0151_out,
      I2 => \^crcaxis_tkeep_reg[6]_3\,
      I3 => crc_imd0175_out,
      I4 => crc_imd086_out,
      I5 => \^crcaxis_tkeep_reg[6]_4\,
      O => \crc_imd[13]_i_3_n_0\
    );
\crc_imd[13]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]\,
      I1 => crc_imd0121_out,
      I2 => \^crcaxis_tkeep_reg[4]\,
      I3 => crc_imd044_out,
      I4 => crc_imd068_out,
      I5 => \^crcaxis_tkeep_reg[4]_0\,
      O => \crc_imd[13]_i_4_n_0\
    );
\crc_imd[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF8"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \^crcaxis_tkeep_reg[2]\,
      I2 => \crc_imd_reg[3]_3\,
      I3 => \crc_imd[14]_i_4_n_0\,
      I4 => \crc_imd[14]_i_5_n_0\,
      I5 => \crc_imd[14]_i_6_n_0\,
      O => \crc_imd[14]_i_1_n_0\
    );
\crc_imd[14]_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \crc_imd_reg[0]_3\(3),
      I1 => \crc_imd_reg[0]_3\(1),
      I2 => \^stateop_reg_0\,
      I3 => \crc_imd_reg[0]_3\(2),
      O => \^crcaxis_tkeep_reg[4]\
    );
\crc_imd[14]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \crc_imd_reg[0]_3\(3),
      I1 => \crc_imd_reg[0]_3\(1),
      I2 => \^stateop_reg_0\,
      I3 => \crc_imd_reg[0]_3\(2),
      O => \^crcaxis_tkeep_reg[4]_0\
    );
\crc_imd[14]_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A6A655A6"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \crc_imd[15]_i_21\(3),
      I2 => \^stateop_reg[2]\,
      I3 => \crc_imd[15]_i_21_0\(3),
      I4 => \^stateop_reg[0]\,
      O => \^crc_imd_reg[3]_2\
    );
\crc_imd[14]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \crc_imd_reg[0]_3\(1),
      I1 => \^stateop_reg_0\,
      I2 => \crc_imd_reg[0]_3\(0),
      O => \^crcaxis_tkeep_reg[2]\
    );
\crc_imd[14]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28828228"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[2]_0\,
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => AXIS_tdata(4),
      I4 => AXIS_tdata(5),
      O => \crc_imd[14]_i_4_n_0\
    );
\crc_imd[14]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]_2\,
      I1 => crc_imd0152_out,
      I2 => \^crcaxis_tkeep_reg[6]_3\,
      I3 => crc_imd0176_out,
      I4 => crc_imd087_out,
      I5 => \^crcaxis_tkeep_reg[6]_4\,
      O => \crc_imd[14]_i_5_n_0\
    );
\crc_imd[14]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]\,
      I1 => crc_imd0124_out,
      I2 => \^crcaxis_tkeep_reg[4]\,
      I3 => crc_imd046_out,
      I4 => crc_imd069_out,
      I5 => \^crcaxis_tkeep_reg[4]_0\,
      O => \crc_imd[14]_i_6_n_0\
    );
\crc_imd[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF11011111"
    )
        port map (
      I0 => \^stateop_reg_0\,
      I1 => \crc_imd_reg[0]_4\,
      I2 => \crc_imd_reg[0]_2\,
      I3 => \^stateop_reg[0]\,
      I4 => recvAXIS_tlast,
      I5 => \crc_imd[15]_i_5_n_0\,
      O => \crc_imd[15]_i_1_n_0\
    );
\crc_imd[15]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00020200000202"
    )
        port map (
      I0 => \crc_imd[15]_i_43_n_0\,
      I1 => \crc_imd_reg[0]_3\(6),
      I2 => \crc_imd_reg[0]_3\(5),
      I3 => \crc_imd[15]_i_44_n_0\,
      I4 => \crc_imd_reg[0]_3\(4),
      I5 => \crc_imd_reg[0]_3\(2),
      O => \crc_imd[15]_i_12_n_0\
    );
\crc_imd[15]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAAAAAA"
    )
        port map (
      I0 => \crc_imd[15]_i_45_n_0\,
      I1 => \crc_imd[15]_i_46_n_0\,
      I2 => \crc_imd_reg[0]_3\(0),
      I3 => \crc_imd_reg[0]_3\(4),
      I4 => \crc_imd_reg[0]_3\(2),
      O => \crc_imd[15]_i_13_n_0\
    );
\crc_imd[15]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => first,
      I1 => validCrc_sig_reg_n_0,
      O => \crc_imd[15]_i_14_n_0\
    );
\crc_imd[15]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \crc_imd_reg[0]_3\(5),
      I1 => \^stateop_reg_0\,
      I2 => \crc_imd_reg[0]_3\(1),
      I3 => \crc_imd_reg[0]_3\(3),
      I4 => \crc_imd_reg[0]_3\(4),
      O => \^crcaxis_tkeep_reg[6]_4\
    );
\crc_imd[15]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \crc_imd_reg[0]_3\(5),
      I1 => \^stateop_reg_0\,
      I2 => \crc_imd_reg[0]_3\(1),
      I3 => \crc_imd_reg[0]_3\(3),
      I4 => \crc_imd_reg[0]_3\(6),
      O => \^crcaxis_tkeep_reg[6]_3\
    );
\crc_imd[15]_i_32\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \crc_imd_reg[0]_3\(5),
      I1 => \^stateop_reg_0\,
      I2 => \crc_imd_reg[0]_3\(1),
      I3 => \crc_imd_reg[0]_3\(3),
      I4 => \crc_imd_reg[0]_3\(6),
      O => \^crcaxis_tkeep_reg[6]_2\
    );
\crc_imd[15]_i_43\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D100"
    )
        port map (
      I0 => \crc_imd_reg[0]_3\(3),
      I1 => \crc_imd_reg[0]_3\(2),
      I2 => \crc_imd_reg[0]_3\(1),
      I3 => \^stateop_reg_0\,
      O => \crc_imd[15]_i_43_n_0\
    );
\crc_imd[15]_i_44\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \crc_imd_reg[0]_3\(3),
      I1 => \crc_imd_reg[0]_3\(1),
      I2 => \^stateop_reg_0\,
      I3 => \crc_imd_reg[0]_3\(5),
      O => \crc_imd[15]_i_44_n_0\
    );
\crc_imd[15]_i_45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \crc_imd_reg[0]_3\(3),
      I1 => \crc_imd_reg[0]_3\(5),
      I2 => \crc_imd_reg[0]_3\(2),
      I3 => \crc_imd_reg[0]_3\(4),
      I4 => \crc_imd_reg[0]_3\(1),
      I5 => \^stateop_reg_0\,
      O => \crc_imd[15]_i_45_n_0\
    );
\crc_imd[15]_i_46\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^stateop_reg_0\,
      I1 => \crc_imd_reg[0]_3\(1),
      I2 => \crc_imd_reg[0]_3\(3),
      O => \crc_imd[15]_i_46_n_0\
    );
\crc_imd[15]_i_49\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A6A655A6"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \crc_imd[15]_i_21\(2),
      I2 => \^stateop_reg[2]\,
      I3 => \crc_imd[15]_i_21_0\(2),
      I4 => \^stateop_reg[0]\,
      O => \crc_imd_reg[2]_1\
    );
\crc_imd[15]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFFFFFFEFDFFFF"
    )
        port map (
      I0 => Q(0),
      I1 => Q(2),
      I2 => Q(4),
      I3 => Q(5),
      I4 => Q(1),
      I5 => Q(3),
      O => \^stateop_reg[0]\
    );
\crc_imd[15]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88F8000000000000"
    )
        port map (
      I0 => \crc_imd[15]_i_12_n_0\,
      I1 => \crc_imd_reg[0]_3\(0),
      I2 => \crc_imd[15]_i_13_n_0\,
      I3 => \crc_imd_reg[0]_3\(6),
      I4 => \crc_imd[15]_i_14_n_0\,
      I5 => \crc_imd_reg[0]_5\,
      O => \crc_imd[15]_i_5_n_0\
    );
\crc_imd[15]_i_50\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A6A655A6"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \crc_imd[15]_i_21\(5),
      I2 => \^stateop_reg[2]\,
      I3 => \crc_imd[15]_i_21_0\(5),
      I4 => \^stateop_reg[0]\,
      O => \crc_imd_reg[7]_19\
    );
\crc_imd[15]_i_76\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A6A655A6"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(8),
      I1 => \crc_imd[15]_i_21\(0),
      I2 => \^stateop_reg[2]\,
      I3 => \crc_imd[15]_i_21_0\(0),
      I4 => \^stateop_reg[0]\,
      O => \crc_imd_reg[8]_3\
    );
\crc_imd[1]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \^crc_imd_reg[3]_2\,
      I1 => \^crc_imd_reg[4]_1\,
      I2 => \crc_imd[15]_i_18\,
      O => \crc_imd_reg[3]_1\
    );
\crc_imd[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]\,
      I1 => crc_imd0148_out,
      I2 => \^crcaxis_tkeep_reg[4]\,
      I3 => crc_imd065_out,
      I4 => crc_imd081_out,
      I5 => \^crcaxis_tkeep_reg[4]_0\,
      O => \crcAXIS_tkeep_reg[6]_0\
    );
\crc_imd[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFF8"
    )
        port map (
      I0 => crc_imd013_out,
      I1 => \^crcaxis_tkeep_reg[2]\,
      I2 => \crc_imd_reg[3]_3\,
      I3 => \crc_imd_reg[3]_4\,
      I4 => \crc_imd[3]_i_4_n_0\,
      O => \crc_imd[3]_i_1_n_0\
    );
\crc_imd[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(9),
      I1 => AXIS_tdata(1),
      I2 => AXIS_tdata(2),
      I3 => \^crc_imd_reg[15]_0\(10),
      O => crc_imd013_out
    );
\crc_imd[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]\,
      I1 => crc_imd0149_out,
      I2 => \^crcaxis_tkeep_reg[4]\,
      I3 => crc_imd066_out,
      I4 => crc_imd083_out,
      I5 => \^crcaxis_tkeep_reg[4]_0\,
      O => \crc_imd[3]_i_4_n_0\
    );
\crc_imd[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]\,
      I1 => crc_imd0150_out,
      I2 => \^crcaxis_tkeep_reg[4]\,
      I3 => crc_imd067_out,
      I4 => crc_imd085_out,
      I5 => \^crcaxis_tkeep_reg[4]_0\,
      O => \crcAXIS_tkeep_reg[6]_1\
    );
\crc_imd[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFEA"
    )
        port map (
      I0 => \crc_imd_reg[5]_0\,
      I1 => crc_imd044_out,
      I2 => \^crcaxis_tkeep_reg[2]_0\,
      I3 => \crc_imd[5]_i_4_n_0\,
      I4 => \crc_imd[5]_i_5_n_0\,
      O => \crc_imd[5]_i_1_n_0\
    );
\crc_imd[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => AXIS_tdata(9),
      I2 => AXIS_tdata(8),
      I3 => \^crc_imd_reg[15]_0\(4),
      O => crc_imd044_out
    );
\crc_imd[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]_2\,
      I1 => crc_imd0175_out,
      I2 => \^crcaxis_tkeep_reg[6]_3\,
      I3 => crc_imd0198_out,
      I4 => crc_imd0121_out,
      I5 => \^crcaxis_tkeep_reg[6]_4\,
      O => \crc_imd[5]_i_4_n_0\
    );
\crc_imd[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]\,
      I1 => crc_imd0151_out,
      I2 => \^crcaxis_tkeep_reg[4]\,
      I3 => crc_imd068_out,
      I4 => crc_imd086_out,
      I5 => \^crcaxis_tkeep_reg[4]_0\,
      O => \crc_imd[5]_i_5_n_0\
    );
\crc_imd[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFEA"
    )
        port map (
      I0 => \crc_imd_reg[6]_2\,
      I1 => crc_imd046_out,
      I2 => \^crcaxis_tkeep_reg[2]_0\,
      I3 => \crc_imd[6]_i_5_n_0\,
      I4 => \crc_imd[6]_i_6_n_0\,
      O => \crc_imd[6]_i_1_n_0\
    );
\crc_imd[6]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => AXIS_tdata(10),
      I2 => AXIS_tdata(9),
      I3 => \^crc_imd_reg[15]_0\(5),
      O => crc_imd046_out
    );
\crc_imd[6]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \crc_imd_reg[0]_3\(1),
      I1 => \^stateop_reg_0\,
      I2 => \crc_imd_reg[0]_3\(0),
      O => \^crcaxis_tkeep_reg[2]_0\
    );
\crc_imd[6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]_2\,
      I1 => crc_imd0176_out,
      I2 => \^crcaxis_tkeep_reg[6]_3\,
      I3 => crc_imd0200_out,
      I4 => crc_imd0124_out,
      I5 => \^crcaxis_tkeep_reg[6]_4\,
      O => \crc_imd[6]_i_5_n_0\
    );
\crc_imd[6]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]\,
      I1 => crc_imd0152_out,
      I2 => \^crcaxis_tkeep_reg[4]\,
      I3 => crc_imd069_out,
      I4 => crc_imd087_out,
      I5 => \^crcaxis_tkeep_reg[4]_0\,
      O => \crc_imd[6]_i_6_n_0\
    );
\crc_imd[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFFFEFEFEFEFE"
    )
        port map (
      I0 => \crc_imd[7]_i_2_n_0\,
      I1 => \crc_imd_reg[7]_20\,
      I2 => \crc_imd_reg[7]_21\,
      I3 => \^recvaxis_tdata_sig_reg[11]\,
      I4 => \crc_imd_reg[7]_22\,
      I5 => \^crcaxis_tkeep_reg[6]\,
      O => \crc_imd[7]_i_1_n_0\
    );
\crc_imd[7]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A6A655A6"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \crc_imd[15]_i_21\(4),
      I2 => \^stateop_reg[2]\,
      I3 => \crc_imd[15]_i_21_0\(4),
      I4 => \^stateop_reg[0]\,
      O => \^crc_imd_reg[4]_1\
    );
\crc_imd[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEAAEAEEA"
    )
        port map (
      I0 => \crc_imd[7]_i_8_n_0\,
      I1 => \^crcaxis_tkeep_reg[2]_0\,
      I2 => \^crc_imd_reg[15]_0\(5),
      I3 => \^crc_imd_reg[15]_0\(6),
      I4 => p_136_in,
      I5 => \crc_imd_reg[7]_23\,
      O => \crc_imd[7]_i_2_n_0\
    );
\crc_imd[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"65AA65659A559A9A"
    )
        port map (
      I0 => \^crc_imd_reg[4]_1\,
      I1 => \^stateop_reg[0]\,
      I2 => \crc_imd[15]_i_21_0\(3),
      I3 => \^stateop_reg[2]\,
      I4 => \crc_imd[15]_i_21\(3),
      I5 => \^crc_imd_reg[15]_0\(3),
      O => \^recvaxis_tdata_sig_reg[11]\
    );
\crc_imd[7]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => \crc_imd_reg[0]_3\(5),
      I1 => \^stateop_reg_0\,
      I2 => \crc_imd_reg[0]_3\(1),
      I3 => \crc_imd_reg[0]_3\(3),
      I4 => \crc_imd_reg[0]_3\(4),
      O => \^crcaxis_tkeep_reg[6]\
    );
\crc_imd[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[6]_2\,
      I1 => crc_imd0165_out,
      I2 => \^crcaxis_tkeep_reg[6]_3\,
      I3 => crc_imd0202_out,
      I4 => crc_imd0100_out,
      I5 => \^crcaxis_tkeep_reg[6]_4\,
      O => \crc_imd[7]_i_8_n_0\
    );
\crc_imd[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228288228828228"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[2]\,
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \^crc_imd_reg[15]_0\(14),
      I3 => AXIS_tdata(7),
      I4 => AXIS_tdata(6),
      I5 => \^crc_imd_reg[15]_0\(0),
      O => \crc_imd_reg[15]_13\
    );
\crc_imd[8]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28828228"
    )
        port map (
      I0 => \^crcaxis_tkeep_reg[2]_0\,
      I1 => \^crc_imd_reg[15]_0\(6),
      I2 => \^crc_imd_reg[15]_0\(7),
      I3 => AXIS_tdata(11),
      I4 => AXIS_tdata(12),
      O => \crc_imd_reg[6]_1\
    );
\crc_imd[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22F2DD0DDD0D22F2"
    )
        port map (
      I0 => \crc_imd[15]_i_21\(1),
      I1 => \^stateop_reg[2]\,
      I2 => \crc_imd[15]_i_21_0\(1),
      I3 => \^stateop_reg[0]\,
      I4 => \^crc_imd_reg[15]_0\(1),
      I5 => \^crc_imd_reg[15]_0\(15),
      O => p_10_out(0)
    );
\crc_imd[9]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEF6FFFFFFFFFF"
    )
        port map (
      I0 => Q(2),
      I1 => Q(1),
      I2 => Q(5),
      I3 => Q(4),
      I4 => Q(3),
      I5 => Q(0),
      O => \^stateop_reg[2]\
    );
\crc_imd_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd_reg[15]_14\(0),
      Q => \^crc_imd_reg[15]_0\(0)
    );
\crc_imd_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd[10]_i_1_n_0\,
      Q => \^crc_imd_reg[15]_0\(10)
    );
\crc_imd_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd[11]_i_1_n_0\,
      Q => \^crc_imd_reg[15]_0\(11)
    );
\crc_imd_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd[12]_i_1_n_0\,
      Q => \^crc_imd_reg[15]_0\(12)
    );
\crc_imd_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd[13]_i_1_n_0\,
      Q => \^crc_imd_reg[15]_0\(13)
    );
\crc_imd_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd[14]_i_1_n_0\,
      Q => \^crc_imd_reg[15]_0\(14)
    );
\crc_imd_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd_reg[15]_14\(6),
      Q => \^crc_imd_reg[15]_0\(15)
    );
\crc_imd_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd_reg[15]_14\(1),
      Q => \^crc_imd_reg[15]_0\(1)
    );
\crc_imd_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd_reg[15]_14\(2),
      Q => \^crc_imd_reg[15]_0\(2)
    );
\crc_imd_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd[3]_i_1_n_0\,
      Q => \^crc_imd_reg[15]_0\(3)
    );
\crc_imd_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd_reg[15]_14\(3),
      Q => \^crc_imd_reg[15]_0\(4)
    );
\crc_imd_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd[5]_i_1_n_0\,
      Q => \^crc_imd_reg[15]_0\(5)
    );
\crc_imd_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd[6]_i_1_n_0\,
      Q => \^crc_imd_reg[15]_0\(6)
    );
\crc_imd_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd[7]_i_1_n_0\,
      Q => \^crc_imd_reg[15]_0\(7)
    );
\crc_imd_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd_reg[15]_14\(4),
      Q => \^crc_imd_reg[15]_0\(8)
    );
\crc_imd_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \crc_imd[15]_i_1_n_0\,
      CLR => \crc_imd_reg[0]_1\(0),
      D => \crc_imd_reg[15]_14\(5),
      Q => \^crc_imd_reg[15]_0\(9)
    );
first_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A2F"
    )
        port map (
      I0 => first,
      I1 => AXIS_tvalid,
      I2 => \^stateop_reg_0\,
      I3 => AXIS_tlast,
      O => first_i_1_n_0
    );
first_reg: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => first_i_1_n_0,
      PRE => \crc_imd_reg[0]_1\(0),
      Q => first
    );
\retbuf[0][0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000100FFFEFF"
    )
        port map (
      I0 => \retbuf_reg[0][0]\(0),
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(0),
      I4 => \retbuf_reg[0][0]_0\,
      I5 => \^crc_imd_reg[15]_0\(8),
      O => \resid_reg[0]\
    );
\retbuf[0][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(1),
      I4 => \retbuf_reg[0][1]\,
      I5 => \retbuf_reg[0][1]_0\,
      O => \crc_imd_reg[7]_17\(0)
    );
\retbuf[0][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(3),
      I4 => \retbuf_reg[0][1]\,
      I5 => \retbuf_reg[0][3]\,
      O => \crc_imd_reg[7]_17\(1)
    );
\retbuf[0][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(4),
      I4 => \retbuf_reg[0][1]\,
      I5 => \retbuf_reg[0][4]\,
      O => \crc_imd_reg[7]_17\(2)
    );
\retbuf[0][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(5),
      I4 => \retbuf_reg[0][1]\,
      I5 => \retbuf_reg[0][5]\,
      O => \crc_imd_reg[7]_17\(3)
    );
\retbuf[0][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(6),
      I4 => \retbuf_reg[0][1]\,
      I5 => \retbuf_reg[0][6]_0\,
      O => \crc_imd_reg[7]_17\(4)
    );
\retbuf[0][7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFE040"
    )
        port map (
      I0 => \retbuf_reg[0][1]\,
      I1 => \^crc_imd_reg[15]_0\(7),
      I2 => \retbuf_reg[1][7]\,
      I3 => \^crc_imd_reg[15]_0\(15),
      I4 => \retbuf_reg[0][7]\,
      O => \crc_imd_reg[7]_17\(5)
    );
\retbuf[11][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[1][7]\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[11][0]\,
      I3 => \^crc_imd_reg[15]_0\(0),
      O => \crc_imd_reg[11]_1\(0)
    );
\retbuf[11][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[1][7]\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[11][0]\,
      I3 => \^crc_imd_reg[15]_0\(1),
      O => \crc_imd_reg[11]_1\(1)
    );
\retbuf[11][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[1][7]\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[11][0]\,
      I3 => \^crc_imd_reg[15]_0\(2),
      O => \crc_imd_reg[11]_1\(2)
    );
\retbuf[11][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[1][7]\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[11][0]\,
      I3 => \^crc_imd_reg[15]_0\(3),
      O => \crc_imd_reg[11]_1\(3)
    );
\retbuf[15][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[1][7]\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[15][0]\,
      I3 => \^crc_imd_reg[15]_0\(0),
      O => \crc_imd_reg[8]_0\(0)
    );
\retbuf[16][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[16][0]\,
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_15\(0)
    );
\retbuf[16][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[16][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_15\(1)
    );
\retbuf[16][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[16][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_15\(2)
    );
\retbuf[16][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[16][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_15\(3)
    );
\retbuf[16][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[16][0]\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_15\(4)
    );
\retbuf[16][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[16][0]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_15\(5)
    );
\retbuf[16][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[16][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_15\(6)
    );
\retbuf[16][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[16][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_15\(7)
    );
\retbuf[17][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[17][0]\,
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[15]_9\(0)
    );
\retbuf[17][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AC00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(9),
      I1 => \^crc_imd_reg[15]_0\(1),
      I2 => \retbuf_reg[17][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[15]_9\(1)
    );
\retbuf[17][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(10),
      I3 => \retbuf_reg[17][0]\,
      I4 => \^crc_imd_reg[15]_0\(2),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[15]_9\(2)
    );
\retbuf[17][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AC00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(11),
      I1 => \^crc_imd_reg[15]_0\(3),
      I2 => \retbuf_reg[17][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[15]_9\(3)
    );
\retbuf[17][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[17][0]\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[15]_9\(4)
    );
\retbuf[17][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[17][0]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[15]_9\(5)
    );
\retbuf[17][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AC00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(14),
      I1 => \^crc_imd_reg[15]_0\(6),
      I2 => \retbuf_reg[17][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[15]_9\(6)
    );
\retbuf[17][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AC00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(15),
      I1 => \^crc_imd_reg[15]_0\(7),
      I2 => \retbuf_reg[17][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[15]_9\(7)
    );
\retbuf[18][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AC00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(8),
      I1 => \^crc_imd_reg[15]_0\(0),
      I2 => \retbuf_reg[18][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[15]_8\(0)
    );
\retbuf[18][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AC00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(9),
      I1 => \^crc_imd_reg[15]_0\(1),
      I2 => \retbuf_reg[18][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[15]_8\(1)
    );
\retbuf[18][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AC00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(10),
      I1 => \^crc_imd_reg[15]_0\(2),
      I2 => \retbuf_reg[18][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[15]_8\(2)
    );
\retbuf[18][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AC00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(11),
      I1 => \^crc_imd_reg[15]_0\(3),
      I2 => \retbuf_reg[18][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[15]_8\(3)
    );
\retbuf[18][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AC00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(12),
      I1 => \^crc_imd_reg[15]_0\(4),
      I2 => \retbuf_reg[18][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[15]_8\(4)
    );
\retbuf[18][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[18][5]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[15]_8\(5)
    );
\retbuf[18][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AC00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(14),
      I1 => \^crc_imd_reg[15]_0\(6),
      I2 => \retbuf_reg[18][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[15]_8\(6)
    );
\retbuf[18][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AC00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(15),
      I1 => \^crc_imd_reg[15]_0\(7),
      I2 => \retbuf_reg[18][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[15]_8\(7)
    );
\retbuf[19][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[19][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_14\(0)
    );
\retbuf[19][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[19][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_14\(1)
    );
\retbuf[19][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[19][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_14\(2)
    );
\retbuf[19][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[19][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_14\(3)
    );
\retbuf[19][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[19][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_14\(4)
    );
\retbuf[19][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[19][5]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_14\(5)
    );
\retbuf[19][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[19][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_14\(6)
    );
\retbuf[19][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[19][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_14\(7)
    );
\retbuf[1][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(0),
      I4 => \retbuf_reg[1][0]\,
      I5 => \retbuf_reg[1][0]_0\,
      O => \crc_imd_reg[7]_16\(0)
    );
\retbuf[1][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(1),
      I4 => \retbuf_reg[1][0]\,
      I5 => \retbuf_reg[1][1]\,
      O => \crc_imd_reg[7]_16\(1)
    );
\retbuf[1][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(2),
      I4 => \retbuf_reg[1][0]\,
      I5 => \retbuf_reg[1][2]\,
      O => \crc_imd_reg[7]_16\(2)
    );
\retbuf[1][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E040FFFFE040E040"
    )
        port map (
      I0 => \retbuf_reg[1][0]\,
      I1 => \^crc_imd_reg[15]_0\(3),
      I2 => \retbuf_reg[1][7]\,
      I3 => \^crc_imd_reg[15]_0\(11),
      I4 => \retbuf_reg[1][3]\,
      I5 => \retbuf_reg[1][7]_1\,
      O => \crc_imd_reg[7]_16\(3)
    );
\retbuf[1][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(4),
      I4 => \retbuf_reg[1][0]\,
      I5 => \retbuf_reg[1][4]\,
      O => \crc_imd_reg[7]_16\(4)
    );
\retbuf[1][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(5),
      I4 => \retbuf_reg[1][0]\,
      I5 => \retbuf_reg[1][5]\,
      O => \crc_imd_reg[7]_16\(5)
    );
\retbuf[1][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(6),
      I4 => \retbuf_reg[1][0]\,
      I5 => \retbuf_reg[1][6]\,
      O => \crc_imd_reg[7]_16\(6)
    );
\retbuf[1][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E040FFFFE040E040"
    )
        port map (
      I0 => \retbuf_reg[1][0]\,
      I1 => \^crc_imd_reg[15]_0\(7),
      I2 => \retbuf_reg[1][7]\,
      I3 => \^crc_imd_reg[15]_0\(15),
      I4 => \retbuf_reg[1][7]_0\,
      I5 => \retbuf_reg[1][7]_1\,
      O => \crc_imd_reg[7]_16\(7)
    );
\retbuf[20][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[20][0]\,
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_13\(0)
    );
\retbuf[20][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[20][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_13\(1)
    );
\retbuf[20][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[20][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_13\(2)
    );
\retbuf[20][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[20][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_13\(3)
    );
\retbuf[20][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[20][0]\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_13\(4)
    );
\retbuf[20][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[20][0]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_13\(5)
    );
\retbuf[20][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[20][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_13\(6)
    );
\retbuf[20][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[20][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_13\(7)
    );
\retbuf[21][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[21][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_12\(0)
    );
\retbuf[21][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[21][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_12\(1)
    );
\retbuf[21][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[21][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_12\(2)
    );
\retbuf[21][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(11),
      I3 => \retbuf_reg[21][3]\,
      I4 => \^crc_imd_reg[15]_0\(3),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_12\(3)
    );
\retbuf[21][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[21][3]\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_12\(4)
    );
\retbuf[21][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[21][3]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_12\(5)
    );
\retbuf[21][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[21][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_12\(6)
    );
\retbuf[21][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[21][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_12\(7)
    );
\retbuf[22][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[22][0]\,
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_11\(0)
    );
\retbuf[22][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[22][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_11\(1)
    );
\retbuf[22][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(10),
      I3 => \retbuf_reg[22][0]\,
      I4 => \^crc_imd_reg[15]_0\(2),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_11\(2)
    );
\retbuf[22][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[22][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_11\(3)
    );
\retbuf[22][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[22][0]\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_11\(4)
    );
\retbuf[22][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[22][0]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_11\(5)
    );
\retbuf[22][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[22][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_11\(6)
    );
\retbuf[22][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[22][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_11\(7)
    );
\retbuf[23][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[23][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_10\(0)
    );
\retbuf[23][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(9),
      I3 => \retbuf_reg[23][1]\,
      I4 => \^crc_imd_reg[15]_0\(1),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_10\(1)
    );
\retbuf[23][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[23][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_10\(2)
    );
\retbuf[23][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[23][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_10\(3)
    );
\retbuf[23][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[23][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_10\(4)
    );
\retbuf[23][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[23][1]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_10\(5)
    );
\retbuf[23][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(14),
      I3 => \retbuf_reg[23][1]\,
      I4 => \^crc_imd_reg[15]_0\(6),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_10\(6)
    );
\retbuf[23][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[23][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_10\(7)
    );
\retbuf[24][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[24][0]\,
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_9\(0)
    );
\retbuf[24][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[24][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_9\(1)
    );
\retbuf[24][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[24][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_9\(2)
    );
\retbuf[24][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[24][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_9\(3)
    );
\retbuf[24][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[24][0]\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_9\(4)
    );
\retbuf[24][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[24][0]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_9\(5)
    );
\retbuf[24][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[24][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_9\(6)
    );
\retbuf[24][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[24][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_9\(7)
    );
\retbuf[25][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[25][0]\,
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_8\(0)
    );
\retbuf[25][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[25][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_8\(1)
    );
\retbuf[25][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[25][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_8\(2)
    );
\retbuf[25][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[25][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_8\(3)
    );
\retbuf[25][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[25][0]\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_8\(4)
    );
\retbuf[25][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[25][0]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_8\(5)
    );
\retbuf[25][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[25][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_8\(6)
    );
\retbuf[25][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[25][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_8\(7)
    );
\retbuf[26][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[26][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_7\(0)
    );
\retbuf[26][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(9),
      I3 => \retbuf_reg[26][1]\,
      I4 => \^crc_imd_reg[15]_0\(1),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_7\(1)
    );
\retbuf[26][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[26][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_7\(2)
    );
\retbuf[26][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[26][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_7\(3)
    );
\retbuf[26][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[26][1]\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_7\(4)
    );
\retbuf[26][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[26][1]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_7\(5)
    );
\retbuf[26][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[26][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_7\(6)
    );
\retbuf[26][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[26][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_7\(7)
    );
\retbuf[27][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[27][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_6\(0)
    );
\retbuf[27][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[27][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_6\(1)
    );
\retbuf[27][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[27][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_6\(2)
    );
\retbuf[27][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[27][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_6\(3)
    );
\retbuf[27][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[27][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_6\(4)
    );
\retbuf[27][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[27][5]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_6\(5)
    );
\retbuf[27][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[27][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_6\(6)
    );
\retbuf[27][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[27][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_6\(7)
    );
\retbuf[28][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[28][0]\,
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_5\(0)
    );
\retbuf[28][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[28][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_5\(1)
    );
\retbuf[28][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[28][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_5\(2)
    );
\retbuf[28][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[28][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_5\(3)
    );
\retbuf[28][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[28][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_5\(4)
    );
\retbuf[28][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[28][0]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_5\(5)
    );
\retbuf[28][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(14),
      I3 => \retbuf_reg[28][0]\,
      I4 => \^crc_imd_reg[15]_0\(6),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_5\(6)
    );
\retbuf[28][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[28][1]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_5\(7)
    );
\retbuf[29][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[29][0]\,
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_4\(0)
    );
\retbuf[29][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(9),
      I3 => \retbuf_reg[29][0]\,
      I4 => \^crc_imd_reg[15]_0\(1),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_4\(1)
    );
\retbuf[29][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(10),
      I3 => \retbuf_reg[29][0]\,
      I4 => \^crc_imd_reg[15]_0\(2),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_4\(2)
    );
\retbuf[29][3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAC0000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[29][0]\,
      I3 => \retbuf_reg[35][5]\,
      I4 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_4\(3)
    );
\retbuf[29][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[29][0]\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_4\(4)
    );
\retbuf[29][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[29][0]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_4\(5)
    );
\retbuf[29][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(14),
      I3 => \retbuf_reg[29][0]\,
      I4 => \^crc_imd_reg[15]_0\(6),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_4\(6)
    );
\retbuf[29][7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAC0000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[29][0]\,
      I3 => \retbuf_reg[35][5]\,
      I4 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_4\(7)
    );
\retbuf[2][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(0),
      I4 => \retbuf_reg[2][0]\,
      I5 => \retbuf_reg[2][0]_0\,
      O => \crc_imd_reg[14]_1\(0)
    );
\retbuf[2][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(1),
      I4 => \retbuf_reg[2][0]\,
      I5 => \retbuf_reg[2][1]\,
      O => \crc_imd_reg[14]_1\(1)
    );
\retbuf[2][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(2),
      I4 => \retbuf_reg[2][0]\,
      I5 => \retbuf_reg[2][2]\,
      O => \crc_imd_reg[14]_1\(2)
    );
\retbuf[2][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(3),
      I4 => \retbuf_reg[2][0]\,
      I5 => \retbuf_reg[2][3]\,
      O => \crc_imd_reg[14]_1\(3)
    );
\retbuf[2][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(4),
      I4 => \retbuf_reg[2][0]\,
      I5 => \retbuf_reg[2][4]\,
      O => \crc_imd_reg[14]_1\(4)
    );
\retbuf[2][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(5),
      I4 => \retbuf_reg[2][0]\,
      I5 => \retbuf_reg[2][5]\,
      O => \crc_imd_reg[14]_1\(5)
    );
\retbuf[2][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(6),
      I4 => \retbuf_reg[2][0]\,
      I5 => \retbuf_reg[2][6]\,
      O => \crc_imd_reg[14]_1\(6)
    );
\retbuf[30][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[30][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_3\(0)
    );
\retbuf[30][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(9),
      I3 => \retbuf_reg[30][1]_0\,
      I4 => \^crc_imd_reg[15]_0\(1),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_3\(1)
    );
\retbuf[30][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(10),
      I3 => \retbuf_reg[30][1]_0\,
      I4 => \^crc_imd_reg[15]_0\(2),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_3\(2)
    );
\retbuf[30][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(11),
      I3 => \retbuf_reg[30][1]_0\,
      I4 => \^crc_imd_reg[15]_0\(3),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_3\(3)
    );
\retbuf[30][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[30][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_3\(4)
    );
\retbuf[30][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[30][1]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[30][1]_0\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_3\(5)
    );
\retbuf[30][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[30][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_3\(6)
    );
\retbuf[30][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[30][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_3\(7)
    );
\retbuf[31][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[31][0]\,
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_2\(0)
    );
\retbuf[31][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAC0000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[31][0]\,
      I3 => \retbuf_reg[35][5]\,
      I4 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_2\(1)
    );
\retbuf[31][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(10),
      I3 => \retbuf_reg[31][0]\,
      I4 => \^crc_imd_reg[15]_0\(2),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_2\(2)
    );
\retbuf[31][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(11),
      I3 => \retbuf_reg[31][0]\,
      I4 => \^crc_imd_reg[15]_0\(3),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_2\(3)
    );
\retbuf[31][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAC0000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[31][0]\,
      I3 => \retbuf_reg[35][5]\,
      I4 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_2\(4)
    );
\retbuf[31][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[31][0]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_2\(5)
    );
\retbuf[31][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(14),
      I3 => \retbuf_reg[31][0]\,
      I4 => \^crc_imd_reg[15]_0\(6),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_2\(6)
    );
\retbuf[31][7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAC0000"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[31][0]\,
      I3 => \retbuf_reg[35][5]\,
      I4 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_2\(7)
    );
\retbuf[32][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[32][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_1\(0)
    );
\retbuf[32][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[32][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_1\(1)
    );
\retbuf[32][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[32][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_1\(2)
    );
\retbuf[32][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[32][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_1\(3)
    );
\retbuf[32][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[32][4]\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_1\(4)
    );
\retbuf[32][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[32][4]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_1\(5)
    );
\retbuf[32][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[32][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(14),
      I3 => \retbuf_reg[32][4]\,
      I4 => \^crc_imd_reg[15]_0\(6),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_1\(6)
    );
\retbuf[32][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[32][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_1\(7)
    );
\retbuf[33][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[33][0]\,
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[15]_7\(0)
    );
\retbuf[33][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(9),
      I3 => \retbuf_reg[33][0]\,
      I4 => \^crc_imd_reg[15]_0\(1),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[15]_7\(1)
    );
\retbuf[33][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C0C0C088"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(10),
      I1 => \retbuf_reg[1][7]\,
      I2 => \^crc_imd_reg[15]_0\(2),
      I3 => \retbuf_reg[33][0]\,
      I4 => \retbuf_reg[35][5]\,
      O => \crc_imd_reg[15]_7\(2)
    );
\retbuf[33][3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C0C0C088"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(11),
      I1 => \retbuf_reg[1][7]\,
      I2 => \^crc_imd_reg[15]_0\(3),
      I3 => \retbuf_reg[33][0]\,
      I4 => \retbuf_reg[35][5]\,
      O => \crc_imd_reg[15]_7\(3)
    );
\retbuf[33][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[33][0]\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[15]_7\(4)
    );
\retbuf[33][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[33][0]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[15]_7\(5)
    );
\retbuf[33][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(14),
      I3 => \retbuf_reg[33][0]\,
      I4 => \^crc_imd_reg[15]_0\(6),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[15]_7\(6)
    );
\retbuf[33][7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C0C0C088"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(15),
      I1 => \retbuf_reg[1][7]\,
      I2 => \^crc_imd_reg[15]_0\(7),
      I3 => \retbuf_reg[33][0]\,
      I4 => \retbuf_reg[35][5]\,
      O => \crc_imd_reg[15]_7\(7)
    );
\retbuf[34][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[34][0]\,
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[15]_6\(0)
    );
\retbuf[34][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88C0"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(9),
      I1 => \retbuf_reg[1][7]\,
      I2 => \^crc_imd_reg[15]_0\(1),
      I3 => \retbuf_reg[34][7]\,
      O => \crc_imd_reg[15]_6\(1)
    );
\retbuf[34][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88C0"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(10),
      I1 => \retbuf_reg[1][7]\,
      I2 => \^crc_imd_reg[15]_0\(2),
      I3 => \retbuf_reg[34][7]\,
      O => \crc_imd_reg[15]_6\(2)
    );
\retbuf[34][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(11),
      I3 => \retbuf_reg[34][0]\,
      I4 => \^crc_imd_reg[15]_0\(3),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[15]_6\(3)
    );
\retbuf[34][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88C0"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(12),
      I1 => \retbuf_reg[1][7]\,
      I2 => \^crc_imd_reg[15]_0\(4),
      I3 => \retbuf_reg[34][7]\,
      O => \crc_imd_reg[15]_6\(4)
    );
\retbuf[34][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[34][0]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[15]_6\(5)
    );
\retbuf[34][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(14),
      I3 => \retbuf_reg[34][0]\,
      I4 => \^crc_imd_reg[15]_0\(6),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[15]_6\(6)
    );
\retbuf[34][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88C0"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(15),
      I1 => \retbuf_reg[1][7]\,
      I2 => \^crc_imd_reg[15]_0\(7),
      I3 => \retbuf_reg[34][7]\,
      O => \crc_imd_reg[15]_6\(7)
    );
\retbuf[35][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(0),
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[35][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_0\(0)
    );
\retbuf[35][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(1),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[35][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_0\(1)
    );
\retbuf[35][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(2),
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[35][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_0\(2)
    );
\retbuf[35][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(3),
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[35][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_0\(3)
    );
\retbuf[35][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(4),
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[35][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_0\(4)
    );
\retbuf[35][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA80020AAAAAAAA"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \retbuf_reg[35][5]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[35][5]_0\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]\,
      O => \crc_imd_reg[7]_0\(5)
    );
\retbuf[35][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(6),
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[35][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_0\(6)
    );
\retbuf[35][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA00"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(7),
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[35][0]\,
      I3 => \retbuf_reg[1][7]\,
      O => \crc_imd_reg[7]_0\(7)
    );
\retbuf[36][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(0),
      O => \crc_imd_reg[15]_5\(0)
    );
\retbuf[36][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(1),
      O => \crc_imd_reg[15]_5\(1)
    );
\retbuf[36][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(2),
      O => \crc_imd_reg[15]_5\(2)
    );
\retbuf[36][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(3),
      O => \crc_imd_reg[15]_5\(3)
    );
\retbuf[36][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(4),
      O => \crc_imd_reg[15]_5\(4)
    );
\retbuf[36][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(5),
      O => \crc_imd_reg[15]_5\(5)
    );
\retbuf[36][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(6),
      O => \crc_imd_reg[15]_5\(6)
    );
\retbuf[36][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[36][0]\,
      I3 => \^crc_imd_reg[15]_0\(7),
      O => \crc_imd_reg[15]_5\(7)
    );
\retbuf[37][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(0),
      O => \crc_imd_reg[15]_4\(0)
    );
\retbuf[37][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(1),
      O => \crc_imd_reg[15]_4\(1)
    );
\retbuf[37][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(2),
      O => \crc_imd_reg[15]_4\(2)
    );
\retbuf[37][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(3),
      O => \crc_imd_reg[15]_4\(3)
    );
\retbuf[37][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(4),
      O => \crc_imd_reg[15]_4\(4)
    );
\retbuf[37][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(5),
      O => \crc_imd_reg[15]_4\(5)
    );
\retbuf[37][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(6),
      O => \crc_imd_reg[15]_4\(6)
    );
\retbuf[37][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[37][0]\,
      I3 => \^crc_imd_reg[15]_0\(7),
      O => \crc_imd_reg[15]_4\(7)
    );
\retbuf[38][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[38][0]\,
      I3 => \^crc_imd_reg[15]_0\(0),
      O => \crc_imd_reg[15]_3\(0)
    );
\retbuf[38][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[38][0]\,
      I3 => \^crc_imd_reg[15]_0\(1),
      O => \crc_imd_reg[15]_3\(1)
    );
\retbuf[38][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[38][0]\,
      I3 => \^crc_imd_reg[15]_0\(2),
      O => \crc_imd_reg[15]_3\(2)
    );
\retbuf[38][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[38][0]\,
      I3 => \^crc_imd_reg[15]_0\(3),
      O => \crc_imd_reg[15]_3\(3)
    );
\retbuf[38][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[38][0]\,
      I3 => \^crc_imd_reg[15]_0\(4),
      O => \crc_imd_reg[15]_3\(4)
    );
\retbuf[38][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \retbuf_reg[38][0]\,
      I3 => \^crc_imd_reg[15]_0\(5),
      O => \crc_imd_reg[15]_3\(5)
    );
\retbuf[38][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[38][0]\,
      I3 => \^crc_imd_reg[15]_0\(6),
      O => \crc_imd_reg[15]_3\(6)
    );
\retbuf[38][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[38][0]\,
      I3 => \^crc_imd_reg[15]_0\(7),
      O => \crc_imd_reg[15]_3\(7)
    );
\retbuf[39][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[39][0]\,
      I3 => \^crc_imd_reg[15]_0\(0),
      O => \crc_imd_reg[15]_2\(0)
    );
\retbuf[39][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[39][0]\,
      I3 => \^crc_imd_reg[15]_0\(1),
      O => \crc_imd_reg[15]_2\(1)
    );
\retbuf[39][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[39][0]\,
      I3 => \^crc_imd_reg[15]_0\(2),
      O => \crc_imd_reg[15]_2\(2)
    );
\retbuf[39][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \retbuf_reg[39][0]\,
      I3 => \^crc_imd_reg[15]_0\(3),
      O => \crc_imd_reg[15]_2\(3)
    );
\retbuf[39][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[39][0]\,
      I3 => \^crc_imd_reg[15]_0\(4),
      O => \crc_imd_reg[15]_2\(4)
    );
\retbuf[39][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \retbuf_reg[39][0]\,
      I3 => \^crc_imd_reg[15]_0\(5),
      O => \crc_imd_reg[15]_2\(5)
    );
\retbuf[39][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \retbuf_reg[39][0]\,
      I3 => \^crc_imd_reg[15]_0\(6),
      O => \crc_imd_reg[15]_2\(6)
    );
\retbuf[39][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \^crc_imd_reg[15]_0\(15),
      I2 => \retbuf_reg[39][0]\,
      I3 => \^crc_imd_reg[15]_0\(7),
      O => \crc_imd_reg[15]_2\(7)
    );
\retbuf[3][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(0),
      I4 => \retbuf_reg[3][0]\,
      I5 => \retbuf_reg[3][0]_0\,
      O => \crc_imd_reg[13]_0\(0)
    );
\retbuf[3][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(1),
      I4 => \retbuf_reg[3][0]\,
      I5 => \retbuf_reg[3][1]\,
      O => \crc_imd_reg[13]_0\(1)
    );
\retbuf[3][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000100FFFEFF"
    )
        port map (
      I0 => \retbuf_reg[0][0]\(0),
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(2),
      I4 => \retbuf_reg[3][7]\,
      I5 => \^crc_imd_reg[15]_0\(10),
      O => \resid_reg[0]_3\
    );
\retbuf[3][3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000100FFFEFF"
    )
        port map (
      I0 => \retbuf_reg[0][0]\(0),
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(3),
      I4 => \retbuf_reg[3][7]\,
      I5 => \^crc_imd_reg[15]_0\(11),
      O => \resid_reg[0]_2\
    );
\retbuf[3][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(12),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(4),
      I4 => \retbuf_reg[3][0]\,
      I5 => \retbuf_reg[3][4]\,
      O => \crc_imd_reg[13]_0\(2)
    );
\retbuf[3][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA0A8080A000"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(5),
      I4 => \retbuf_reg[3][0]\,
      I5 => \retbuf_reg[3][5]_0\,
      O => \crc_imd_reg[13]_0\(3)
    );
\retbuf[3][6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000100FFFEFF"
    )
        port map (
      I0 => \retbuf_reg[0][0]\(0),
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(6),
      I4 => \retbuf_reg[3][7]\,
      I5 => \^crc_imd_reg[15]_0\(14),
      O => \resid_reg[0]_1\
    );
\retbuf[3][7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000100FFFEFF"
    )
        port map (
      I0 => \retbuf_reg[0][0]\(0),
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(7),
      I4 => \retbuf_reg[3][7]\,
      I5 => \^crc_imd_reg[15]_0\(15),
      O => \resid_reg[0]_0\
    );
\retbuf[4][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFB800"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(9),
      I1 => \retbuf_reg[4][6]_1\,
      I2 => \^crc_imd_reg[15]_0\(1),
      I3 => \retbuf_reg[1][7]\,
      I4 => \retbuf_reg[4][1]\,
      O => \crc_imd_reg[14]_0\(0)
    );
\retbuf[4][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFB800"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(10),
      I1 => \retbuf_reg[4][6]_1\,
      I2 => \^crc_imd_reg[15]_0\(2),
      I3 => \retbuf_reg[1][7]\,
      I4 => \retbuf_reg[4][2]\,
      O => \crc_imd_reg[14]_0\(1)
    );
\retbuf[4][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8088808888880088"
    )
        port map (
      I0 => \retbuf_reg[4][4]\,
      I1 => \retbuf_reg[6][0]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[4][6]\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \retbuf_reg[4][6]_1\,
      O => \crc_imd_reg[14]_0\(2)
    );
\retbuf[4][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8088808888880088"
    )
        port map (
      I0 => \retbuf_reg[4][5]\,
      I1 => \retbuf_reg[6][0]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[4][6]\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[4][6]_1\,
      O => \crc_imd_reg[14]_0\(3)
    );
\retbuf[4][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8088808888880088"
    )
        port map (
      I0 => \retbuf_reg[4][6]_0\,
      I1 => \retbuf_reg[6][0]\,
      I2 => \^crc_imd_reg[15]_0\(14),
      I3 => \retbuf_reg[4][6]\,
      I4 => \^crc_imd_reg[15]_0\(6),
      I5 => \retbuf_reg[4][6]_1\,
      O => \crc_imd_reg[14]_0\(4)
    );
\retbuf[4][7]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(15),
      I1 => \retbuf_reg[4][6]_1\,
      I2 => \^crc_imd_reg[15]_0\(7),
      O => \crc_imd_reg[15]_10\
    );
\retbuf[5][0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[5][0]\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \retbuf_reg[6][0]\,
      O => D(0)
    );
\retbuf[5][1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[5][1]\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(9),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(1),
      I5 => \retbuf_reg[6][0]\,
      O => D(1)
    );
\retbuf[5][2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[5][2]\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(10),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(2),
      I5 => \retbuf_reg[6][0]\,
      O => D(2)
    );
\retbuf[5][3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[5][3]\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(11),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(3),
      I5 => \retbuf_reg[6][0]\,
      O => D(3)
    );
\retbuf[5][4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[5][4]\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \retbuf_reg[6][0]\,
      O => D(4)
    );
\retbuf[5][5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[5][5]\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(13),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \retbuf_reg[6][0]\,
      O => D(5)
    );
\retbuf[5][6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[5][6]\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(14),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(6),
      I5 => \retbuf_reg[6][0]\,
      O => D(6)
    );
\retbuf[5][7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[5][7]\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(15),
      I3 => \retbuf_reg[5][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(7),
      I5 => \retbuf_reg[6][0]\,
      O => D(7)
    );
\retbuf[6][0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[6][0]_0\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(8),
      I3 => \retbuf_reg[6][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \retbuf_reg[6][0]\,
      O => \crc_imd_reg[15]_1\(0)
    );
\retbuf[6][1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[6][1]\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(9),
      I3 => \retbuf_reg[6][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(1),
      I5 => \retbuf_reg[6][0]\,
      O => \crc_imd_reg[15]_1\(1)
    );
\retbuf[6][2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[6][2]\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(10),
      I3 => \retbuf_reg[6][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(2),
      I5 => \retbuf_reg[6][0]\,
      O => \crc_imd_reg[15]_1\(2)
    );
\retbuf[6][3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[6][3]\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(11),
      I3 => \retbuf_reg[6][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(3),
      I5 => \retbuf_reg[6][0]\,
      O => \crc_imd_reg[15]_1\(3)
    );
\retbuf[6][4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[6][4]\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \retbuf_reg[6][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \retbuf_reg[6][0]\,
      O => \crc_imd_reg[15]_1\(4)
    );
\retbuf[6][5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000100FFFEFF"
    )
        port map (
      I0 => \retbuf_reg[0][0]\(0),
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(5),
      I4 => \retbuf_reg[6][5]\,
      I5 => \^crc_imd_reg[15]_0\(13),
      O => \resid_reg[0]_4\
    );
\retbuf[6][6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[6][6]\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(14),
      I3 => \retbuf_reg[6][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(6),
      I5 => \retbuf_reg[6][0]\,
      O => \crc_imd_reg[15]_1\(5)
    );
\retbuf[6][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \retbuf_reg[6][7]\,
      I1 => \retbuf_reg[4][6]\,
      I2 => \^crc_imd_reg[15]_0\(15),
      I3 => \retbuf_reg[6][7]_0\,
      I4 => \^crc_imd_reg[15]_0\(7),
      I5 => \retbuf_reg[6][0]\,
      O => \crc_imd_reg[15]_1\(6)
    );
\retbuf[7][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[1][7]\,
      I1 => \^crc_imd_reg[15]_0\(8),
      I2 => \retbuf_reg[7][3]_0\,
      I3 => \^crc_imd_reg[15]_0\(0),
      O => \crc_imd_reg[11]_0\(0)
    );
\retbuf[7][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[1][7]\,
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \retbuf_reg[7][3]_0\,
      I3 => \^crc_imd_reg[15]_0\(1),
      O => \crc_imd_reg[11]_0\(1)
    );
\retbuf[7][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A808"
    )
        port map (
      I0 => \retbuf_reg[1][7]\,
      I1 => \^crc_imd_reg[15]_0\(10),
      I2 => \retbuf_reg[7][3]_0\,
      I3 => \^crc_imd_reg[15]_0\(2),
      O => \crc_imd_reg[11]_0\(2)
    );
\retbuf[7][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2A2A2020202A202"
    )
        port map (
      I0 => \retbuf_reg[3][5]\,
      I1 => \retbuf_reg[7][3]\,
      I2 => \retbuf_reg[4][6]\,
      I3 => \^crc_imd_reg[15]_0\(11),
      I4 => \retbuf_reg[7][3]_0\,
      I5 => \^crc_imd_reg[15]_0\(3),
      O => \crc_imd_reg[11]_0\(3)
    );
\retbuf[7][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000100FFFEFF"
    )
        port map (
      I0 => \retbuf_reg[0][0]\(0),
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \^crc_imd_reg[15]_0\(5),
      I4 => \retbuf_reg[7][5]\,
      I5 => \^crc_imd_reg[15]_0\(13),
      O => \resid_reg[0]_5\
    );
\stateOp[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0044440400004444"
    )
        port map (
      I0 => \stateOp_reg[0]_0\,
      I1 => \txAXIS_tdata_reg[7]_0\,
      I2 => \tixVBuffer[7]_i_5_n_0\,
      I3 => Q(1),
      I4 => Q(0),
      I5 => Q(2),
      O => \stateOp_reg[1]_1\
    );
\stateOp[0]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4700"
    )
        port map (
      I0 => \stateOp_reg[5]_1\(0),
      I1 => Q(1),
      I2 => \tixVBuffer[7]_i_5_n_0\,
      I3 => Q(2),
      I4 => Q(0),
      O => \stateOp[0]_i_6_n_0\
    );
\stateOp[2]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA2AAAAAAA2AAA2"
    )
        port map (
      I0 => \stateOp[5]_i_10_n_0\,
      I1 => Q(1),
      I2 => Q(2),
      I3 => Q(0),
      I4 => CO(0),
      I5 => \stateOp_reg[2]_0\(0),
      O => \stateOp_reg[1]_0\
    );
\stateOp[2]_i_7__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0530FFF"
    )
        port map (
      I0 => \stateOp_reg[5]_1\(0),
      I1 => \tixVBuffer[7]_i_5_n_0\,
      I2 => Q(1),
      I3 => Q(0),
      I4 => Q(2),
      O => \stateOp[2]_i_7__1_n_0\
    );
\stateOp[5]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800080008880088"
    )
        port map (
      I0 => Q(5),
      I1 => \txAXIS_tdata_reg[7]_0\,
      I2 => Q(1),
      I3 => Q(2),
      I4 => \tixVBuffer[7]_i_5_n_0\,
      I5 => Q(0),
      O => \stateOp[5]_i_10_n_0\
    );
\stateOp[5]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F007F7F7F7F7F7F"
    )
        port map (
      I0 => \stateOp_reg[5]_1\(1),
      I1 => \stateOp_reg[5]_2\,
      I2 => \stateOp_reg[5]_3\,
      I3 => \stateOp_reg[5]_4\,
      I4 => \stateOp_reg[5]_5\,
      I5 => \tixVBuffer[7]_i_5_n_0\,
      O => \stateOp[5]_i_11_n_0\
    );
\stateOp[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"888A"
    )
        port map (
      I0 => \retbuf_reg[0][6]\,
      I1 => \stateOp[5]_i_10_n_0\,
      I2 => Q(5),
      I3 => \stateOp[5]_i_11_n_0\,
      O => \stateOp_reg[5]\(0)
    );
stateOp_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \crc_imd_reg[0]_1\(0),
      D => stateOp_reg_1,
      Q => \^stateop_reg_0\
    );
\stateOp_reg[0]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \stateOp[0]_i_6_n_0\,
      I1 => \stateOp_reg[0]_1\,
      O => \stateOp_reg[3]_1\,
      S => Q(3)
    );
\stateOp_reg[2]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \stateOp[2]_i_7__1_n_0\,
      I1 => \stateOp_reg[2]_1\,
      O => \stateOp_reg[3]_0\,
      S => Q(3)
    );
\tixVBuffer[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00080000FFFFFFFF"
    )
        port map (
      I0 => \len_reg[0]\,
      I1 => \len_reg[0]_0\,
      I2 => Q(4),
      I3 => Q(5),
      I4 => \tixVBuffer[7]_i_5_n_0\,
      I5 => \retbuf_reg[6][0]\,
      O => \^stateop_reg[4]\(0)
    );
\tixVBuffer[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \tixVBuffer[7]_i_6_n_0\,
      I1 => \^crc_imd_reg[15]_0\(0),
      I2 => \^crc_imd_reg[15]_0\(1),
      I3 => \^crc_imd_reg[15]_0\(3),
      I4 => \^crc_imd_reg[15]_0\(2),
      I5 => \tixVBuffer[7]_i_7_n_0\,
      O => \tixVBuffer[7]_i_5_n_0\
    );
\tixVBuffer[7]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(5),
      I1 => \^crc_imd_reg[15]_0\(4),
      I2 => \^crc_imd_reg[15]_0\(6),
      I3 => \^crc_imd_reg[15]_0\(7),
      O => \tixVBuffer[7]_i_6_n_0\
    );
\tixVBuffer[7]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(8),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \^crc_imd_reg[15]_0\(10),
      I3 => \^crc_imd_reg[15]_0\(11),
      I4 => \tixVBuffer[7]_i_8_n_0\,
      O => \tixVBuffer[7]_i_7_n_0\
    );
\tixVBuffer[7]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(15),
      I1 => \^crc_imd_reg[15]_0\(14),
      I2 => \^crc_imd_reg[15]_0\(12),
      I3 => \^crc_imd_reg[15]_0\(13),
      O => \tixVBuffer[7]_i_8_n_0\
    );
\tixVController[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8AAA"
    )
        port map (
      I0 => \^stateop_reg[4]\(0),
      I1 => \tixVCommand_reg[0]\,
      I2 => \tixVCommand_reg[0]_0\(0),
      I3 => \retbuf_reg[6][0]\,
      O => \opbuf_reg[2][0]\(0)
    );
\txAXIS_tdata[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF77F30000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[0]_0\,
      I1 => Q(4),
      I2 => \txAXIS_tdata_reg[3]\(0),
      I3 => \txAXIS_tdata_reg[0]\,
      I4 => \txAXIS_tdata_reg[0]_1\,
      I5 => \txAXIS_tdata[0]_i_4_n_0\,
      O => \stateOp_reg[4]_0\
    );
\txAXIS_tdata[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF4540"
    )
        port map (
      I0 => \txAXIS_tdata[0]_i_2_0\,
      I1 => \txAXIS_tdata[0]_i_2_1\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata[0]_i_2_2\,
      I4 => \txAXIS_tdata[0]_i_8_n_0\,
      I5 => \txAXIS_tdata[2]_i_3_0\,
      O => \txAXIS_tdata[0]_i_4_n_0\
    );
\txAXIS_tdata[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF44F444F444F4"
    )
        port map (
      I0 => \^crc_imd_reg[8]_1\,
      I1 => \txAXIS_tdata_reg[4]\,
      I2 => \txAXIS_tdata_reg[7]_6\(0),
      I3 => \txAXIS_tdata_reg[4]_0\,
      I4 => \stateOp_reg[5]_5\,
      I5 => \^crc_imd_reg[15]_0\(8),
      O => \txAXIS_tdata[0]_i_8_n_0\
    );
\txAXIS_tdata[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8A888A88888888"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata[10]_i_2_n_0\,
      I2 => \txAXIS_tdata_reg[10]\,
      I3 => Q(3),
      I4 => \^crc_imd_reg[15]_0\(2),
      I5 => \txAXIS_tdata_reg[8]\,
      O => \stateOp_reg[1]\(4)
    );
\txAXIS_tdata[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4540"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[10]_0\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[10]_1\,
      I4 => \txAXIS_tdata[10]_i_6_n_0\,
      O => \txAXIS_tdata[10]_i_2_n_0\
    );
\txAXIS_tdata[10]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"101F1010"
    )
        port map (
      I0 => \txAXIS_tdata[10]_i_8_n_0\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(4),
      I4 => \txAXIS_tdata[15]_i_6_0\(2),
      O => \txAXIS_tdata[10]_i_6_n_0\
    );
\txAXIS_tdata[10]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFC7F7"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(10),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(2),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[10]_i_8_n_0\
    );
\txAXIS_tdata[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8A888A88888888"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata[11]_i_2_n_0\,
      I2 => \txAXIS_tdata_reg[11]\,
      I3 => Q(3),
      I4 => \^crc_imd_reg[15]_0\(3),
      I5 => \txAXIS_tdata_reg[8]\,
      O => \stateOp_reg[1]\(5)
    );
\txAXIS_tdata[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4540"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[11]_0\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[11]_1\,
      I4 => \txAXIS_tdata[11]_i_6_n_0\,
      O => \txAXIS_tdata[11]_i_2_n_0\
    );
\txAXIS_tdata[11]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"101F1010"
    )
        port map (
      I0 => \txAXIS_tdata[11]_i_8_n_0\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(4),
      I4 => \txAXIS_tdata[15]_i_6_0\(3),
      O => \txAXIS_tdata[11]_i_6_n_0\
    );
\txAXIS_tdata[11]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFC7F7"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(11),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(3),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[11]_i_8_n_0\
    );
\txAXIS_tdata[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8A888A88888888"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata[12]_i_2_n_0\,
      I2 => \txAXIS_tdata_reg[12]\,
      I3 => Q(3),
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \txAXIS_tdata_reg[8]\,
      O => \stateOp_reg[1]\(6)
    );
\txAXIS_tdata[12]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4540"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[12]_0\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[12]_1\,
      I4 => \txAXIS_tdata[12]_i_6_n_0\,
      O => \txAXIS_tdata[12]_i_2_n_0\
    );
\txAXIS_tdata[12]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"101F1010"
    )
        port map (
      I0 => \txAXIS_tdata[12]_i_8_n_0\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(4),
      I4 => \txAXIS_tdata[15]_i_6_0\(4),
      O => \txAXIS_tdata[12]_i_6_n_0\
    );
\txAXIS_tdata[12]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFC7F7"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(12),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(4),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[12]_i_8_n_0\
    );
\txAXIS_tdata[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8A888A88888888"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata[13]_i_2_n_0\,
      I2 => \txAXIS_tdata_reg[13]\,
      I3 => Q(3),
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \txAXIS_tdata_reg[8]\,
      O => \stateOp_reg[1]\(7)
    );
\txAXIS_tdata[13]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4540"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[13]_0\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[13]_1\,
      I4 => \txAXIS_tdata[13]_i_6_n_0\,
      O => \txAXIS_tdata[13]_i_2_n_0\
    );
\txAXIS_tdata[13]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"101F1010"
    )
        port map (
      I0 => \txAXIS_tdata[13]_i_8_n_0\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(4),
      I4 => \txAXIS_tdata[15]_i_6_0\(5),
      O => \txAXIS_tdata[13]_i_6_n_0\
    );
\txAXIS_tdata[13]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFC7F7"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(13),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(5),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[13]_i_8_n_0\
    );
\txAXIS_tdata[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8A888A88888888"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata[14]_i_2_n_0\,
      I2 => \txAXIS_tdata_reg[14]\,
      I3 => Q(3),
      I4 => \^crc_imd_reg[15]_0\(6),
      I5 => \txAXIS_tdata_reg[8]\,
      O => \stateOp_reg[1]\(8)
    );
\txAXIS_tdata[14]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4540"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[14]_0\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[14]_1\,
      I4 => \txAXIS_tdata[14]_i_6_n_0\,
      O => \txAXIS_tdata[14]_i_2_n_0\
    );
\txAXIS_tdata[14]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"101F1010"
    )
        port map (
      I0 => \txAXIS_tdata[14]_i_8_n_0\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(4),
      I4 => \txAXIS_tdata[15]_i_6_0\(6),
      O => \txAXIS_tdata[14]_i_6_n_0\
    );
\txAXIS_tdata[14]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFC7F7"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(14),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(6),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[14]_i_8_n_0\
    );
\txAXIS_tdata[15]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"101F1010"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_21_n_0\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(4),
      I4 => \txAXIS_tdata[15]_i_6_0\(7),
      O => \txAXIS_tdata[15]_i_16_n_0\
    );
\txAXIS_tdata[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8A888A88888888"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata[15]_i_6_n_0\,
      I2 => \txAXIS_tdata_reg[15]\,
      I3 => Q(3),
      I4 => \^crc_imd_reg[15]_0\(7),
      I5 => \txAXIS_tdata_reg[8]\,
      O => \stateOp_reg[1]\(9)
    );
\txAXIS_tdata[15]_i_21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFC7F7"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(15),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(7),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[15]_i_21_n_0\
    );
\txAXIS_tdata[15]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4540"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[15]_0\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[15]_1\,
      I4 => \txAXIS_tdata[15]_i_16_n_0\,
      O => \txAXIS_tdata[15]_i_6_n_0\
    );
\txAXIS_tdata[16]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(8),
      I1 => \retbuf_reg[0][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(0),
      O => \^crc_imd_reg[8]_1\
    );
\txAXIS_tdata[17]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(9),
      I1 => \retbuf_reg[0][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(1),
      O => \^crc_imd_reg[9]_0\
    );
\txAXIS_tdata[18]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(10),
      I1 => \retbuf_reg[0][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(2),
      O => \^crc_imd_reg[10]_0\
    );
\txAXIS_tdata[19]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020200000002000"
    )
        port map (
      I0 => \retbuf_reg[0][0]\(1),
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \txAXIS_tdata_reg[2]\,
      I3 => \^crc_imd_reg[15]_0\(3),
      I4 => \retbuf_reg[0][0]\(0),
      I5 => \^crc_imd_reg[15]_0\(11),
      O => \resid_reg[1]\
    );
\txAXIS_tdata[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA200AAAAAAAA"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata[1]_i_2__0_n_0\,
      I2 => \txAXIS_tdata[1]_i_3_n_0\,
      I3 => \txAXIS_tdata_reg[1]_1\,
      I4 => \txAXIS_tdata_reg[1]_2\,
      I5 => \txAXIS_tdata_reg[1]_3\,
      O => \stateOp_reg[1]\(0)
    );
\txAXIS_tdata[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22277727FFFFFFFF"
    )
        port map (
      I0 => Q(3),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \txAXIS_tdata_reg[3]\(1),
      I3 => \txAXIS_tdata_reg[0]\,
      I4 => \txAXIS_tdata_reg[1]\,
      I5 => \txAXIS_tdata_reg[8]\,
      O => \txAXIS_tdata[1]_i_2__0_n_0\
    );
\txAXIS_tdata[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF040000000400"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_4\,
      I1 => Q(1),
      I2 => \^crc_imd_reg[9]_0\,
      I3 => Q(4),
      I4 => Q(3),
      I5 => \txAXIS_tdata_reg[7]_6\(1),
      O => \txAXIS_tdata[1]_i_3_n_0\
    );
\txAXIS_tdata[20]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020200000002000"
    )
        port map (
      I0 => \retbuf_reg[0][0]\(1),
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \txAXIS_tdata_reg[2]\,
      I3 => \^crc_imd_reg[15]_0\(4),
      I4 => \retbuf_reg[0][0]\(0),
      I5 => \^crc_imd_reg[15]_0\(12),
      O => \resid_reg[1]_0\
    );
\txAXIS_tdata[21]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(13),
      I1 => \retbuf_reg[0][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(5),
      O => \^crc_imd_reg[13]_1\
    );
\txAXIS_tdata[22]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(14),
      I1 => \retbuf_reg[0][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(6),
      O => \^crc_imd_reg[14]_2\
    );
\txAXIS_tdata[23]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020200000002000"
    )
        port map (
      I0 => \retbuf_reg[0][0]\(1),
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \txAXIS_tdata_reg[2]\,
      I3 => \^crc_imd_reg[15]_0\(7),
      I4 => \retbuf_reg[0][0]\(0),
      I5 => \^crc_imd_reg[15]_0\(15),
      O => \resid_reg[1]_1\
    );
\txAXIS_tdata[24]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2008000820000000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[2]\,
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \retbuf_reg[0][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \^crc_imd_reg[15]_0\(8),
      O => \resid_reg[2]\
    );
\txAXIS_tdata[25]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2008000820000000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[2]\,
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \retbuf_reg[0][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(1),
      I5 => \^crc_imd_reg[15]_0\(9),
      O => \resid_reg[2]_0\
    );
\txAXIS_tdata[26]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2008000820000000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[2]\,
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \retbuf_reg[0][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(2),
      I5 => \^crc_imd_reg[15]_0\(10),
      O => \resid_reg[2]_1\
    );
\txAXIS_tdata[27]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2008000820000000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[2]\,
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \retbuf_reg[0][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(3),
      I5 => \^crc_imd_reg[15]_0\(11),
      O => \resid_reg[2]_2\
    );
\txAXIS_tdata[28]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2008000820000000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[2]\,
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \retbuf_reg[0][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(4),
      I5 => \^crc_imd_reg[15]_0\(12),
      O => \resid_reg[2]_3\
    );
\txAXIS_tdata[29]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2008000820000000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[2]\,
      I1 => \retbuf_reg[0][0]\(2),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \retbuf_reg[0][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(5),
      I5 => \^crc_imd_reg[15]_0\(13),
      O => \resid_reg[2]_4\
    );
\txAXIS_tdata[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000B800"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(10),
      I1 => \retbuf_reg[0][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(2),
      I3 => \txAXIS_tdata_reg[2]\,
      I4 => \txAXIS_tdata_reg[1]_4\,
      I5 => \txAXIS_tdata[2]_i_7_n_0\,
      O => \crc_imd_reg[10]_1\
    );
\txAXIS_tdata[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAEAAAFBBBEAAA"
    )
        port map (
      I0 => \txAXIS_tdata[2]_i_3_0\,
      I1 => Q(4),
      I2 => Q(3),
      I3 => \^crc_imd_reg[15]_0\(10),
      I4 => \txAXIS_tdata_reg[7]_6\(2),
      I5 => Q(0),
      O => \txAXIS_tdata[2]_i_7_n_0\
    );
\txAXIS_tdata[30]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF53FFF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(14),
      I1 => \^crc_imd_reg[15]_0\(6),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \retbuf_reg[0][0]\(1),
      I4 => \retbuf_reg[0][0]\(2),
      O => \crc_imd_reg[14]_3\
    );
\txAXIS_tdata[31]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF53FFF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(15),
      I1 => \^crc_imd_reg[15]_0\(7),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \retbuf_reg[0][0]\(1),
      I4 => \retbuf_reg[0][0]\(2),
      O => \crc_imd_reg[15]_12\
    );
\txAXIS_tdata[32]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AA2A222AAA2A"
    )
        port map (
      I0 => \txAXIS_tdata_reg[32]\,
      I1 => \txAXIS_tdata_reg[39]_0\,
      I2 => \^crc_imd_reg[15]_0\(0),
      I3 => \retbuf_reg[0][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(8),
      I5 => Q(3),
      O => \crc_imd_reg[0]_0\
    );
\txAXIS_tdata[33]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000033077777"
    )
        port map (
      I0 => Q(3),
      I1 => \^crc_imd_reg[15]_0\(9),
      I2 => \^crc_imd_reg[15]_0\(1),
      I3 => \retbuf_reg[0][0]\(0),
      I4 => \txAXIS_tdata_reg[39]_0\,
      I5 => \txAXIS_tdata_reg[33]\,
      O => \stateOp_reg[3]_3\
    );
\txAXIS_tdata[34]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AA2A222AAA2A"
    )
        port map (
      I0 => \txAXIS_tdata_reg[34]\,
      I1 => \txAXIS_tdata_reg[39]_0\,
      I2 => \^crc_imd_reg[15]_0\(2),
      I3 => \retbuf_reg[0][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(10),
      I5 => Q(3),
      O => \crc_imd_reg[2]_0\
    );
\txAXIS_tdata[35]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AA2A222AAA2A"
    )
        port map (
      I0 => \txAXIS_tdata_reg[35]\,
      I1 => \txAXIS_tdata_reg[39]_0\,
      I2 => \^crc_imd_reg[15]_0\(3),
      I3 => \retbuf_reg[0][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(11),
      I5 => Q(3),
      O => \crc_imd_reg[3]_0\
    );
\txAXIS_tdata[36]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AA2A222AAA2A"
    )
        port map (
      I0 => \txAXIS_tdata_reg[36]\,
      I1 => \txAXIS_tdata_reg[39]_0\,
      I2 => \^crc_imd_reg[15]_0\(4),
      I3 => \retbuf_reg[0][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(12),
      I5 => Q(3),
      O => \crc_imd_reg[4]_0\
    );
\txAXIS_tdata[37]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000033077777"
    )
        port map (
      I0 => Q(3),
      I1 => \^crc_imd_reg[15]_0\(13),
      I2 => \^crc_imd_reg[15]_0\(5),
      I3 => \retbuf_reg[0][0]\(0),
      I4 => \txAXIS_tdata_reg[39]_0\,
      I5 => \txAXIS_tdata_reg[37]\,
      O => \stateOp_reg[3]_2\
    );
\txAXIS_tdata[38]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000F757F7"
    )
        port map (
      I0 => \txAXIS_tdata_reg[39]_0\,
      I1 => \^crc_imd_reg[15]_0\(6),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(14),
      I4 => Q(3),
      I5 => \txAXIS_tdata_reg[38]\,
      O => \crc_imd_reg[6]_0\
    );
\txAXIS_tdata[39]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AA2A222AAA2A"
    )
        port map (
      I0 => \txAXIS_tdata_reg[39]\,
      I1 => \txAXIS_tdata_reg[39]_0\,
      I2 => \^crc_imd_reg[15]_0\(7),
      I3 => \retbuf_reg[0][0]\(0),
      I4 => \^crc_imd_reg[15]_0\(15),
      I5 => Q(3),
      O => \crc_imd_reg[7]_18\
    );
\txAXIS_tdata[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA200AAAAAAAA"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata[3]_i_2__0_n_0\,
      I2 => \txAXIS_tdata[3]_i_3_n_0\,
      I3 => \txAXIS_tdata_reg[1]_1\,
      I4 => \txAXIS_tdata_reg[3]_1\,
      I5 => \txAXIS_tdata_reg[1]_3\,
      O => \stateOp_reg[1]\(1)
    );
\txAXIS_tdata[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22277727FFFFFFFF"
    )
        port map (
      I0 => Q(3),
      I1 => \^crc_imd_reg[15]_0\(11),
      I2 => \txAXIS_tdata_reg[3]\(2),
      I3 => \txAXIS_tdata_reg[0]\,
      I4 => \txAXIS_tdata_reg[3]_0\,
      I5 => \txAXIS_tdata_reg[8]\,
      O => \txAXIS_tdata[3]_i_2__0_n_0\
    );
\txAXIS_tdata[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF040000000400"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_4\,
      I1 => Q(1),
      I2 => \txAXIS_tdata[51]_i_7_n_0\,
      I3 => Q(4),
      I4 => Q(3),
      I5 => \txAXIS_tdata_reg[7]_6\(3),
      O => \txAXIS_tdata[3]_i_3_n_0\
    );
\txAXIS_tdata[40]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2A202A2020202A2"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata_reg[40]\,
      I2 => Q(1),
      I3 => \txAXIS_tdata[40]_i_3_n_0\,
      I4 => Q(3),
      I5 => \^crc_imd_reg[15]_0\(0),
      O => \stateOp_reg[1]\(10)
    );
\txAXIS_tdata[40]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFBFFFFABFB0000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[47]_0\,
      I1 => \txAXIS_tdata_reg[40]_0\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[40]_1\,
      I4 => Q(2),
      I5 => \txAXIS_tdata[40]_i_7_n_0\,
      O => \txAXIS_tdata[40]_i_3_n_0\
    );
\txAXIS_tdata[40]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C7F7FFFF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(8),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(0),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[40]_i_7_n_0\
    );
\txAXIS_tdata[41]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2A202A2020202A2"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata_reg[41]\,
      I2 => Q(1),
      I3 => \txAXIS_tdata[41]_i_3_n_0\,
      I4 => Q(3),
      I5 => \^crc_imd_reg[15]_0\(1),
      O => \stateOp_reg[1]\(11)
    );
\txAXIS_tdata[41]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFBFFFFABFB0000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[47]_0\,
      I1 => \txAXIS_tdata_reg[41]_0\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[41]_1\,
      I4 => Q(2),
      I5 => \txAXIS_tdata[41]_i_7_n_0\,
      O => \txAXIS_tdata[41]_i_3_n_0\
    );
\txAXIS_tdata[41]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C7F7FFFF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(9),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(1),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[41]_i_7_n_0\
    );
\txAXIS_tdata[42]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2A202A2020202A2"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata_reg[42]\,
      I2 => Q(1),
      I3 => \txAXIS_tdata[42]_i_3_n_0\,
      I4 => Q(3),
      I5 => \^crc_imd_reg[15]_0\(2),
      O => \stateOp_reg[1]\(12)
    );
\txAXIS_tdata[42]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFBFFFFABFB0000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[47]_0\,
      I1 => \txAXIS_tdata_reg[42]_0\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[42]_1\,
      I4 => Q(2),
      I5 => \txAXIS_tdata[42]_i_7_n_0\,
      O => \txAXIS_tdata[42]_i_3_n_0\
    );
\txAXIS_tdata[42]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C7F7FFFF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(10),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(2),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[42]_i_7_n_0\
    );
\txAXIS_tdata[43]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2A202A2020202A2"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata_reg[43]\,
      I2 => Q(1),
      I3 => \txAXIS_tdata[43]_i_3_n_0\,
      I4 => Q(3),
      I5 => \^crc_imd_reg[15]_0\(3),
      O => \stateOp_reg[1]\(13)
    );
\txAXIS_tdata[43]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFBFFFFABFB0000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[47]_0\,
      I1 => \txAXIS_tdata_reg[43]_0\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[43]_1\,
      I4 => Q(2),
      I5 => \txAXIS_tdata[43]_i_7_n_0\,
      O => \txAXIS_tdata[43]_i_3_n_0\
    );
\txAXIS_tdata[43]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C7F7FFFF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(11),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(3),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[43]_i_7_n_0\
    );
\txAXIS_tdata[44]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2A202A2020202A2"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata_reg[44]\,
      I2 => Q(1),
      I3 => \txAXIS_tdata[44]_i_3_n_0\,
      I4 => Q(3),
      I5 => \^crc_imd_reg[15]_0\(4),
      O => \stateOp_reg[1]\(14)
    );
\txAXIS_tdata[44]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFBFFFFABFB0000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[47]_0\,
      I1 => \txAXIS_tdata_reg[44]_0\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[44]_1\,
      I4 => Q(2),
      I5 => \txAXIS_tdata[44]_i_7_n_0\,
      O => \txAXIS_tdata[44]_i_3_n_0\
    );
\txAXIS_tdata[44]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C7F7FFFF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(12),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(4),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[44]_i_7_n_0\
    );
\txAXIS_tdata[45]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2A202A2020202A2"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata_reg[45]\,
      I2 => Q(1),
      I3 => \txAXIS_tdata[45]_i_3_n_0\,
      I4 => Q(3),
      I5 => \^crc_imd_reg[15]_0\(5),
      O => \stateOp_reg[1]\(15)
    );
\txAXIS_tdata[45]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFBFFFFABFB0000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[47]_0\,
      I1 => \txAXIS_tdata_reg[45]_0\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[45]_1\,
      I4 => Q(2),
      I5 => \txAXIS_tdata[45]_i_7_n_0\,
      O => \txAXIS_tdata[45]_i_3_n_0\
    );
\txAXIS_tdata[45]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C7F7FFFF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(13),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(5),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[45]_i_7_n_0\
    );
\txAXIS_tdata[46]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2A202A2020202A2"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata_reg[46]\,
      I2 => Q(1),
      I3 => \txAXIS_tdata[46]_i_3_n_0\,
      I4 => Q(3),
      I5 => \^crc_imd_reg[15]_0\(6),
      O => \stateOp_reg[1]\(16)
    );
\txAXIS_tdata[46]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFBFFFFABFB0000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[47]_0\,
      I1 => \txAXIS_tdata_reg[46]_0\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[46]_1\,
      I4 => Q(2),
      I5 => \txAXIS_tdata[46]_i_7_n_0\,
      O => \txAXIS_tdata[46]_i_3_n_0\
    );
\txAXIS_tdata[46]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C7F7FFFF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(14),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(6),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[46]_i_7_n_0\
    );
\txAXIS_tdata[47]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2A202A2020202A2"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata_reg[47]\,
      I2 => Q(1),
      I3 => \txAXIS_tdata[47]_i_5_n_0\,
      I4 => Q(3),
      I5 => \^crc_imd_reg[15]_0\(7),
      O => \stateOp_reg[1]\(17)
    );
\txAXIS_tdata[47]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFBFFFFABFB0000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[47]_0\,
      I1 => \txAXIS_tdata_reg[47]_1\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[47]_2\,
      I4 => Q(2),
      I5 => \txAXIS_tdata[47]_i_9_n_0\,
      O => \txAXIS_tdata[47]_i_5_n_0\
    );
\txAXIS_tdata[47]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C7F7FFFF"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(15),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(7),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[47]_i_9_n_0\
    );
\txAXIS_tdata[48]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFB0000ABFBABFB"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[48]\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[48]_0\,
      I4 => \^crc_imd_reg[8]_1\,
      I5 => \txAXIS_tdata_reg[55]_1\,
      O => \tixVBuffer_reg[7]_9\
    );
\txAXIS_tdata[49]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFB0000ABFBABFB"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[49]\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[49]_0\,
      I4 => \^crc_imd_reg[9]_0\,
      I5 => \txAXIS_tdata_reg[55]_1\,
      O => \tixVBuffer_reg[7]_8\
    );
\txAXIS_tdata[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF44F444F444F4"
    )
        port map (
      I0 => \txAXIS_tdata[52]_i_7_n_0\,
      I1 => \txAXIS_tdata_reg[4]\,
      I2 => \txAXIS_tdata_reg[7]_6\(4),
      I3 => \txAXIS_tdata_reg[4]_0\,
      I4 => \stateOp_reg[5]_5\,
      I5 => \^crc_imd_reg[15]_0\(12),
      O => \pollbuf_reg[0][4]\
    );
\txAXIS_tdata[50]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFB0000ABFBABFB"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[50]\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[50]_0\,
      I4 => \^crc_imd_reg[10]_0\,
      I5 => \txAXIS_tdata_reg[55]_1\,
      O => \tixVBuffer_reg[7]_7\
    );
\txAXIS_tdata[51]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFB0000ABFBABFB"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[51]\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[51]_0\,
      I4 => \txAXIS_tdata[51]_i_7_n_0\,
      I5 => \txAXIS_tdata_reg[55]_1\,
      O => \tixVBuffer_reg[7]_6\
    );
\txAXIS_tdata[51]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(11),
      I1 => \retbuf_reg[0][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(3),
      O => \txAXIS_tdata[51]_i_7_n_0\
    );
\txAXIS_tdata[52]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFB0000ABFBABFB"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[52]\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[52]_0\,
      I4 => \txAXIS_tdata[52]_i_7_n_0\,
      I5 => \txAXIS_tdata_reg[55]_1\,
      O => \tixVBuffer_reg[7]_5\
    );
\txAXIS_tdata[52]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(12),
      I1 => \retbuf_reg[0][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(4),
      O => \txAXIS_tdata[52]_i_7_n_0\
    );
\txAXIS_tdata[53]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFB0000ABFBABFB"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[53]\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[53]_0\,
      I4 => \^crc_imd_reg[13]_1\,
      I5 => \txAXIS_tdata_reg[55]_1\,
      O => \tixVBuffer_reg[7]_4\
    );
\txAXIS_tdata[54]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFB0000ABFBABFB"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[54]\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[54]_0\,
      I4 => \^crc_imd_reg[14]_2\,
      I5 => \txAXIS_tdata_reg[55]_1\,
      O => \tixVBuffer_reg[7]_3\
    );
\txAXIS_tdata[55]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(15),
      I1 => \retbuf_reg[0][0]\(0),
      I2 => \^crc_imd_reg[15]_0\(7),
      O => \txAXIS_tdata[55]_i_12_n_0\
    );
\txAXIS_tdata[55]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABFB0000ABFBABFB"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[55]\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[55]_0\,
      I4 => \txAXIS_tdata[55]_i_12_n_0\,
      I5 => \txAXIS_tdata_reg[55]_1\,
      O => \tixVBuffer_reg[7]_2\
    );
\txAXIS_tdata[56]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3FFFFFF5"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(8),
      I1 => \^crc_imd_reg[15]_0\(0),
      I2 => \retbuf_reg[0][0]\(2),
      I3 => \retbuf_reg[0][0]\(1),
      I4 => \retbuf_reg[0][0]\(0),
      O => \crc_imd_reg[8]_2\
    );
\txAXIS_tdata[57]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3FFFFFF5"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(9),
      I1 => \^crc_imd_reg[15]_0\(1),
      I2 => \retbuf_reg[0][0]\(2),
      I3 => \retbuf_reg[0][0]\(1),
      I4 => \retbuf_reg[0][0]\(0),
      O => \crc_imd_reg[9]_1\
    );
\txAXIS_tdata[58]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABFB"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[58]\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[58]_0\,
      I4 => \txAXIS_tdata[58]_i_7_n_0\,
      O => \tixVBuffer_reg[7]_1\
    );
\txAXIS_tdata[58]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8002000280000000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[2]\,
      I1 => \retbuf_reg[0][0]\(0),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \retbuf_reg[0][0]\(2),
      I4 => \^crc_imd_reg[15]_0\(2),
      I5 => \^crc_imd_reg[15]_0\(10),
      O => \txAXIS_tdata[58]_i_7_n_0\
    );
\txAXIS_tdata[59]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABFB"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[59]\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[59]_0\,
      I4 => \txAXIS_tdata[59]_i_7_n_0\,
      O => \tixVBuffer_reg[7]_0\
    );
\txAXIS_tdata[59]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8002000280000000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[2]\,
      I1 => \retbuf_reg[0][0]\(0),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \retbuf_reg[0][0]\(2),
      I4 => \^crc_imd_reg[15]_0\(3),
      I5 => \^crc_imd_reg[15]_0\(11),
      O => \txAXIS_tdata[59]_i_7_n_0\
    );
\txAXIS_tdata[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F000DFF0FFF0DFF"
    )
        port map (
      I0 => \txAXIS_tdata_reg[5]\,
      I1 => Q(1),
      I2 => \txAXIS_tdata[5]_i_7_n_0\,
      I3 => Q(4),
      I4 => Q(3),
      I5 => \txAXIS_tdata_reg[7]_6\(5),
      O => \stateOp_reg[1]_2\
    );
\txAXIS_tdata[5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF0E0000000400"
    )
        port map (
      I0 => \retbuf_reg[0][0]\(0),
      I1 => \^crc_imd_reg[15]_0\(5),
      I2 => \txAXIS_tdata_reg[1]_4\,
      I3 => Q(1),
      I4 => Q(3),
      I5 => \^crc_imd_reg[15]_0\(13),
      O => \txAXIS_tdata[5]_i_7_n_0\
    );
\txAXIS_tdata[60]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3FFFFFF5"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(12),
      I1 => \^crc_imd_reg[15]_0\(4),
      I2 => \retbuf_reg[0][0]\(2),
      I3 => \retbuf_reg[0][0]\(1),
      I4 => \retbuf_reg[0][0]\(0),
      O => \crc_imd_reg[12]_0\
    );
\txAXIS_tdata[61]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3FFFFFF5"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(13),
      I1 => \^crc_imd_reg[15]_0\(5),
      I2 => \retbuf_reg[0][0]\(2),
      I3 => \retbuf_reg[0][0]\(1),
      I4 => \retbuf_reg[0][0]\(0),
      O => \crc_imd_reg[13]_2\
    );
\txAXIS_tdata[62]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABFB"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[62]_1\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[62]_2\,
      I4 => \txAXIS_tdata[62]_i_7_n_0\,
      O => \tixVBuffer_reg[7]\
    );
\txAXIS_tdata[62]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8002000280000000"
    )
        port map (
      I0 => \txAXIS_tdata_reg[2]\,
      I1 => \retbuf_reg[0][0]\(0),
      I2 => \retbuf_reg[0][0]\(1),
      I3 => \retbuf_reg[0][0]\(2),
      I4 => \^crc_imd_reg[15]_0\(6),
      I5 => \^crc_imd_reg[15]_0\(14),
      O => \txAXIS_tdata[62]_i_7_n_0\
    );
\txAXIS_tdata[63]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3FFFFFF5"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(15),
      I1 => \^crc_imd_reg[15]_0\(7),
      I2 => \retbuf_reg[0][0]\(2),
      I3 => \retbuf_reg[0][0]\(1),
      I4 => \retbuf_reg[0][0]\(0),
      O => \crc_imd_reg[15]_11\
    );
\txAXIS_tdata[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF44F444F444F4"
    )
        port map (
      I0 => \^crc_imd_reg[14]_2\,
      I1 => \txAXIS_tdata_reg[4]\,
      I2 => \txAXIS_tdata_reg[7]_6\(6),
      I3 => \txAXIS_tdata_reg[4]_0\,
      I4 => \stateOp_reg[5]_5\,
      I5 => \^crc_imd_reg[15]_0\(14),
      O => \pollbuf_reg[0][6]\
    );
\txAXIS_tdata[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0075"
    )
        port map (
      I0 => \txAXIS_tdata_reg[7]\,
      I1 => \txAXIS_tdata_reg[7]_0\,
      I2 => \txAXIS_tdata_reg[7]_1\,
      I3 => Q(5),
      I4 => \txAXIS_tdata[7]_i_5_n_0\,
      I5 => \txAXIS_tdata_reg[7]_2\(0),
      O => \stateOp_reg[5]_0\(0)
    );
\txAXIS_tdata[7]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF0E0000000400"
    )
        port map (
      I0 => \retbuf_reg[0][0]\(0),
      I1 => \^crc_imd_reg[15]_0\(7),
      I2 => \txAXIS_tdata_reg[1]_4\,
      I3 => Q(1),
      I4 => Q(3),
      I5 => \^crc_imd_reg[15]_0\(15),
      O => \txAXIS_tdata[7]_i_12_n_0\
    );
\txAXIS_tdata[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tixVBuffer[7]_i_5_n_0\,
      I1 => \txAXIS_tdata_reg[7]_3\,
      O => \txAXIS_tdata[7]_i_5_n_0\
    );
\txAXIS_tdata[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0E000EFF0EFF0EFF"
    )
        port map (
      I0 => \txAXIS_tdata_reg[7]_4\,
      I1 => \txAXIS_tdata_reg[7]_5\,
      I2 => \txAXIS_tdata[7]_i_12_n_0\,
      I3 => Q(4),
      I4 => Q(3),
      I5 => \txAXIS_tdata_reg[7]_6\(7),
      O => \stateOp_reg[4]_1\
    );
\txAXIS_tdata[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8A888A88888888"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata[8]_i_2_n_0\,
      I2 => \txAXIS_tdata_reg[8]_0\,
      I3 => Q(3),
      I4 => \^crc_imd_reg[15]_0\(0),
      I5 => \txAXIS_tdata_reg[8]\,
      O => \stateOp_reg[1]\(2)
    );
\txAXIS_tdata[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4540"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[8]_1\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[8]_2\,
      I4 => \txAXIS_tdata[8]_i_6_n_0\,
      O => \txAXIS_tdata[8]_i_2_n_0\
    );
\txAXIS_tdata[8]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"101F1010"
    )
        port map (
      I0 => \txAXIS_tdata[8]_i_8_n_0\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(4),
      I4 => \txAXIS_tdata[15]_i_6_0\(0),
      O => \txAXIS_tdata[8]_i_6_n_0\
    );
\txAXIS_tdata[8]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFC7F7"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(8),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(0),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[8]_i_8_n_0\
    );
\txAXIS_tdata[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8A888A88888888"
    )
        port map (
      I0 => \txAXIS_tdata_reg[1]_0\,
      I1 => \txAXIS_tdata[9]_i_2_n_0\,
      I2 => \txAXIS_tdata_reg[9]\,
      I3 => Q(3),
      I4 => \^crc_imd_reg[15]_0\(1),
      I5 => \txAXIS_tdata_reg[8]\,
      O => \stateOp_reg[1]\(3)
    );
\txAXIS_tdata[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4540"
    )
        port map (
      I0 => \txAXIS_tdata_reg[62]_0\,
      I1 => \txAXIS_tdata_reg[9]_0\,
      I2 => \txAXIS_tdata_reg[62]\,
      I3 => \txAXIS_tdata_reg[9]_1\,
      I4 => \txAXIS_tdata[9]_i_6_n_0\,
      O => \txAXIS_tdata[9]_i_2_n_0\
    );
\txAXIS_tdata[9]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"101F1010"
    )
        port map (
      I0 => \txAXIS_tdata[9]_i_8_n_0\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(4),
      I4 => \txAXIS_tdata[15]_i_6_0\(1),
      O => \txAXIS_tdata[9]_i_6_n_0\
    );
\txAXIS_tdata[9]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFC7F7"
    )
        port map (
      I0 => \^crc_imd_reg[15]_0\(9),
      I1 => \retbuf_reg[0][0]\(1),
      I2 => \retbuf_reg[0][0]\(0),
      I3 => \^crc_imd_reg[15]_0\(1),
      I4 => \retbuf_reg[0][0]\(2),
      O => \txAXIS_tdata[9]_i_8_n_0\
    );
\txlen[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"75770000FFFFFFFF"
    )
        port map (
      I0 => \txlen[28]_i_2_n_0\,
      I1 => \txlen[28]_i_3_n_0\,
      I2 => \txlen_reg[28]\,
      I3 => \txlen_reg[28]_0\,
      I4 => Q(2),
      I5 => \retbuf_reg[0][6]\,
      O => E(0)
    );
\txlen[28]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEFEEFFFFFF"
    )
        port map (
      I0 => Q(4),
      I1 => Q(0),
      I2 => \tixVBuffer[7]_i_5_n_0\,
      I3 => Q(1),
      I4 => Q(3),
      I5 => Q(5),
      O => \txlen[28]_i_2_n_0\
    );
\txlen[28]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFF3F3F3"
    )
        port map (
      I0 => \tixVBuffer[7]_i_5_n_0\,
      I1 => Q(0),
      I2 => Q(5),
      I3 => Q(4),
      I4 => Q(1),
      I5 => Q(3),
      O => \txlen[28]_i_3_n_0\
    );
validCrc_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAF0F0A8F0AAAA"
    )
        port map (
      I0 => \crc_imd[15]_i_5_n_0\,
      I1 => first,
      I2 => validCrc_sig_reg_n_0,
      I3 => AXIS_tvalid,
      I4 => \^stateop_reg_0\,
      I5 => AXIS_tlast,
      O => validCrc_sig_i_1_n_0
    );
validCrc_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \crc_imd_reg[0]_1\(0),
      D => validCrc_sig_i_1_n_0,
      Q => validCrc_sig_reg_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Ddrif is
  port (
    stateStats : out STD_LOGIC;
    ddrAXI_bready_sig_reg_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddrAXI_rvalid_0 : out STD_LOGIC;
    \ixRdidEgr_reg[4]_0\ : out STD_LOGIC;
    ddrAXI_wlast : out STD_LOGIC;
    \rdmutex_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \wrmutex_reg[1]_0\ : out STD_LOGIC;
    hdrmemAXI_rlast : out STD_LOGIC;
    ddrAXI_araddr : out STD_LOGIC_VECTOR ( 20 downto 0 );
    probe : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \FSM_onehot_stateRead_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rdmutex_reg[1]_1\ : out STD_LOGIC;
    ddrAXI_awaddr : out STD_LOGIC_VECTOR ( 0 to 0 );
    \wrmutex_reg[1]_1\ : out STD_LOGIC;
    stateStats_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddrAXI_wready_0 : out STD_LOGIC;
    \NRdA_reg[31]_0\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
    \NRdB_reg[31]_0\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
    \NWrA_reg[31]_0\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
    \NWrB_reg[31]_0\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
    tkclk : in STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    AR : in STD_LOGIC_VECTOR ( 0 to 0 );
    memclk : in STD_LOGIC;
    \strbWrlock_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    wrAAXI_awvalid : in STD_LOGIC;
    ddrAXI_rvalid : in STD_LOGIC;
    \burstIgrstr_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    ddrAXI_bvalid : in STD_LOGIC;
    wrAAXI_wlast : in STD_LOGIC;
    ddrAXI_wready : in STD_LOGIC;
    ddrAXI_wvalid : in STD_LOGIC;
    ddrAXI_rlast : in STD_LOGIC;
    \rdid_reg[1][0]_0\ : in STD_LOGIC;
    rdAAXI_araddr : in STD_LOGIC_VECTOR ( 19 downto 0 );
    \ixRdid_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    ddrAXI_arready : in STD_LOGIC;
    \rdmutex_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    ddrAXI_awready : in STD_LOGIC;
    ddrAXI_awvalid : in STD_LOGIC;
    \i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    egrAXIS_tlast : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Ddrif : entity is "Ddrif";
end design_1_Vsp_core_0_0_Ddrif;

architecture STRUCTURE of design_1_Vsp_core_0_0_Ddrif is
  signal \FSM_onehot_stateRead[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateRead[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateRead[2]_i_2_n_0\ : STD_LOGIC;
  signal \^fsm_onehot_stateread_reg[2]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \FSM_onehot_stateRead_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_stateRead_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_stateWrite[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateWrite[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateWrite[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateWrite[2]_i_3_n_0\ : STD_LOGIC;
  signal NRdA : STD_LOGIC;
  signal \NRdA[10]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[11]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[12]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[13]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[14]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[15]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[16]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[17]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[18]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[19]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[20]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[21]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[22]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[23]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[24]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[25]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[26]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[27]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[28]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[29]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[30]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[31]_i_2_n_0\ : STD_LOGIC;
  signal \NRdA[31]_i_3_n_0\ : STD_LOGIC;
  signal \NRdA[31]_i_4_n_0\ : STD_LOGIC;
  signal \NRdA[31]_i_5_n_0\ : STD_LOGIC;
  signal \NRdA[4]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[5]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[6]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[7]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[8]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA[9]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[10]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[10]_i_3_n_0\ : STD_LOGIC;
  signal \NRdA_collect[11]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[12]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[13]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[14]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[15]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[16]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[17]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[18]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[19]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[20]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[21]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[22]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[23]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[24]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[25]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[26]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[27]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[28]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[29]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[30]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[31]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[4]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[5]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[6]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[7]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[8]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect[9]_i_1_n_0\ : STD_LOGIC;
  signal \NRdA_collect_reg[10]_i_2_n_0\ : STD_LOGIC;
  signal \NRdA_collect_reg[10]_i_2_n_1\ : STD_LOGIC;
  signal \NRdA_collect_reg[10]_i_2_n_2\ : STD_LOGIC;
  signal \NRdA_collect_reg[10]_i_2_n_3\ : STD_LOGIC;
  signal \NRdA_collect_reg[10]_i_2_n_4\ : STD_LOGIC;
  signal \NRdA_collect_reg[10]_i_2_n_5\ : STD_LOGIC;
  signal \NRdA_collect_reg[10]_i_2_n_6\ : STD_LOGIC;
  signal \NRdA_collect_reg[10]_i_2_n_7\ : STD_LOGIC;
  signal \NRdA_collect_reg[18]_i_2_n_0\ : STD_LOGIC;
  signal \NRdA_collect_reg[18]_i_2_n_1\ : STD_LOGIC;
  signal \NRdA_collect_reg[18]_i_2_n_2\ : STD_LOGIC;
  signal \NRdA_collect_reg[18]_i_2_n_3\ : STD_LOGIC;
  signal \NRdA_collect_reg[18]_i_2_n_4\ : STD_LOGIC;
  signal \NRdA_collect_reg[18]_i_2_n_5\ : STD_LOGIC;
  signal \NRdA_collect_reg[18]_i_2_n_6\ : STD_LOGIC;
  signal \NRdA_collect_reg[18]_i_2_n_7\ : STD_LOGIC;
  signal \NRdA_collect_reg[26]_i_2_n_0\ : STD_LOGIC;
  signal \NRdA_collect_reg[26]_i_2_n_1\ : STD_LOGIC;
  signal \NRdA_collect_reg[26]_i_2_n_2\ : STD_LOGIC;
  signal \NRdA_collect_reg[26]_i_2_n_3\ : STD_LOGIC;
  signal \NRdA_collect_reg[26]_i_2_n_4\ : STD_LOGIC;
  signal \NRdA_collect_reg[26]_i_2_n_5\ : STD_LOGIC;
  signal \NRdA_collect_reg[26]_i_2_n_6\ : STD_LOGIC;
  signal \NRdA_collect_reg[26]_i_2_n_7\ : STD_LOGIC;
  signal \NRdA_collect_reg[31]_i_2_n_4\ : STD_LOGIC;
  signal \NRdA_collect_reg[31]_i_2_n_5\ : STD_LOGIC;
  signal \NRdA_collect_reg[31]_i_2_n_6\ : STD_LOGIC;
  signal \NRdA_collect_reg[31]_i_2_n_7\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[10]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[11]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[12]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[13]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[14]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[15]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[16]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[17]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[18]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[19]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[20]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[21]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[22]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[23]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[24]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[25]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[26]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[27]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[28]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[29]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[30]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[31]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[4]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[5]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[6]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[7]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[8]\ : STD_LOGIC;
  signal \NRdA_collect_reg_n_0_[9]\ : STD_LOGIC;
  signal \NRdB[10]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[11]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[12]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[13]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[14]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[15]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[16]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[17]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[18]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[19]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[20]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[21]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[22]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[23]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[24]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[25]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[26]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[27]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[28]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[29]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[30]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[31]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[4]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[5]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[6]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[7]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[8]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB[9]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[10]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[10]_i_3_n_0\ : STD_LOGIC;
  signal \NRdB_collect[11]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[12]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[13]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[14]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[15]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[16]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[17]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[18]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[19]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[20]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[21]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[22]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[23]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[24]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[25]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[26]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[27]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[28]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[29]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[30]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[31]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[4]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[5]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[6]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[7]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[8]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect[9]_i_1_n_0\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_0\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_1\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_10\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_11\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_12\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_13\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_14\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_2\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_3\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_4\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_5\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_6\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_7\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_8\ : STD_LOGIC;
  signal \NRdB_collect_reg[10]_i_2_n_9\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_0\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_1\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_10\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_11\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_12\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_13\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_14\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_15\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_2\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_3\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_4\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_5\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_6\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_7\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_8\ : STD_LOGIC;
  signal \NRdB_collect_reg[18]_i_2_n_9\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_0\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_1\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_10\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_11\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_12\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_13\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_14\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_15\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_2\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_3\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_4\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_5\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_6\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_7\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_8\ : STD_LOGIC;
  signal \NRdB_collect_reg[26]_i_2_n_9\ : STD_LOGIC;
  signal \NRdB_collect_reg[31]_i_2_n_11\ : STD_LOGIC;
  signal \NRdB_collect_reg[31]_i_2_n_12\ : STD_LOGIC;
  signal \NRdB_collect_reg[31]_i_2_n_13\ : STD_LOGIC;
  signal \NRdB_collect_reg[31]_i_2_n_14\ : STD_LOGIC;
  signal \NRdB_collect_reg[31]_i_2_n_15\ : STD_LOGIC;
  signal \NRdB_collect_reg[31]_i_2_n_4\ : STD_LOGIC;
  signal \NRdB_collect_reg[31]_i_2_n_5\ : STD_LOGIC;
  signal \NRdB_collect_reg[31]_i_2_n_6\ : STD_LOGIC;
  signal \NRdB_collect_reg[31]_i_2_n_7\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[10]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[11]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[12]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[13]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[14]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[15]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[16]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[17]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[18]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[19]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[20]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[21]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[22]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[23]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[24]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[25]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[26]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[27]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[28]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[29]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[30]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[31]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[4]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[5]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[6]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[7]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[8]\ : STD_LOGIC;
  signal \NRdB_collect_reg_n_0_[9]\ : STD_LOGIC;
  signal \NWrA[10]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[11]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[12]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[13]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[14]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[15]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[16]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[17]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[18]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[19]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[20]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[21]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[22]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[23]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[24]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[25]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[26]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[27]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[28]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[29]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[30]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[31]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[4]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[5]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[6]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[7]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[8]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA[9]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[10]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[10]_i_3_n_0\ : STD_LOGIC;
  signal \NWrA_collect[11]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[12]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[13]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[14]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[15]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[16]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[17]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[18]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[19]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[20]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[21]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[22]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[23]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[24]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[25]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[26]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[27]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[28]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[29]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[30]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[31]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[4]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[5]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[6]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[7]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[8]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect[9]_i_1_n_0\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_0\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_1\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_10\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_11\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_12\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_13\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_14\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_2\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_3\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_4\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_5\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_6\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_7\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_8\ : STD_LOGIC;
  signal \NWrA_collect_reg[10]_i_2_n_9\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_0\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_1\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_10\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_11\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_12\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_13\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_14\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_15\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_2\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_3\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_4\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_5\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_6\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_7\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_8\ : STD_LOGIC;
  signal \NWrA_collect_reg[18]_i_2_n_9\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_0\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_1\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_10\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_11\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_12\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_13\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_14\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_15\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_2\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_3\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_4\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_5\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_6\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_7\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_8\ : STD_LOGIC;
  signal \NWrA_collect_reg[26]_i_2_n_9\ : STD_LOGIC;
  signal \NWrA_collect_reg[31]_i_2_n_11\ : STD_LOGIC;
  signal \NWrA_collect_reg[31]_i_2_n_12\ : STD_LOGIC;
  signal \NWrA_collect_reg[31]_i_2_n_13\ : STD_LOGIC;
  signal \NWrA_collect_reg[31]_i_2_n_14\ : STD_LOGIC;
  signal \NWrA_collect_reg[31]_i_2_n_15\ : STD_LOGIC;
  signal \NWrA_collect_reg[31]_i_2_n_4\ : STD_LOGIC;
  signal \NWrA_collect_reg[31]_i_2_n_5\ : STD_LOGIC;
  signal \NWrA_collect_reg[31]_i_2_n_6\ : STD_LOGIC;
  signal \NWrA_collect_reg[31]_i_2_n_7\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[10]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[11]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[12]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[13]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[14]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[15]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[16]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[17]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[18]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[19]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[20]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[21]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[22]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[23]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[24]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[25]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[26]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[27]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[28]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[29]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[30]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[31]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[4]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[5]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[6]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[7]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[8]\ : STD_LOGIC;
  signal \NWrA_collect_reg_n_0_[9]\ : STD_LOGIC;
  signal \NWrB[10]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[11]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[12]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[13]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[14]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[15]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[16]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[17]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[18]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[19]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[20]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[21]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[22]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[23]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[24]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[25]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[26]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[27]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[28]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[29]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[30]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[31]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[4]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[5]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[6]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[7]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[8]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB[9]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[10]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[10]_i_3_n_0\ : STD_LOGIC;
  signal \NWrB_collect[11]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[12]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[13]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[14]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[15]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[16]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[17]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[18]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[19]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[20]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[21]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[22]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[23]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[24]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[25]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[26]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[27]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[28]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[29]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[30]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[31]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[4]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[5]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[6]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[7]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[8]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect[9]_i_1_n_0\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_0\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_1\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_10\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_11\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_12\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_13\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_14\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_2\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_3\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_4\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_5\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_6\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_7\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_8\ : STD_LOGIC;
  signal \NWrB_collect_reg[10]_i_2_n_9\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_0\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_1\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_10\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_11\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_12\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_13\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_14\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_15\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_2\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_3\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_4\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_5\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_6\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_7\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_8\ : STD_LOGIC;
  signal \NWrB_collect_reg[18]_i_2_n_9\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_0\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_1\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_10\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_11\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_12\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_13\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_14\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_15\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_2\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_3\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_4\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_5\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_6\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_7\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_8\ : STD_LOGIC;
  signal \NWrB_collect_reg[26]_i_2_n_9\ : STD_LOGIC;
  signal \NWrB_collect_reg[31]_i_2_n_11\ : STD_LOGIC;
  signal \NWrB_collect_reg[31]_i_2_n_12\ : STD_LOGIC;
  signal \NWrB_collect_reg[31]_i_2_n_13\ : STD_LOGIC;
  signal \NWrB_collect_reg[31]_i_2_n_14\ : STD_LOGIC;
  signal \NWrB_collect_reg[31]_i_2_n_15\ : STD_LOGIC;
  signal \NWrB_collect_reg[31]_i_2_n_4\ : STD_LOGIC;
  signal \NWrB_collect_reg[31]_i_2_n_5\ : STD_LOGIC;
  signal \NWrB_collect_reg[31]_i_2_n_6\ : STD_LOGIC;
  signal \NWrB_collect_reg[31]_i_2_n_7\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[10]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[11]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[12]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[13]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[14]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[15]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[16]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[17]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[18]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[19]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[20]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[21]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[22]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[23]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[24]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[25]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[26]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[27]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[28]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[29]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[30]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[31]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[4]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[5]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[6]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[7]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[8]\ : STD_LOGIC;
  signal \NWrB_collect_reg_n_0_[9]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal awdone_i_1_n_0 : STD_LOGIC;
  signal awdone_reg_n_0 : STD_LOGIC;
  signal ddrAXI_bready_sig : STD_LOGIC;
  signal ddrAXI_bready_sig0 : STD_LOGIC;
  signal ddrAXI_bready_sig_i_1_n_0 : STD_LOGIC;
  signal ddrAXI_bready_sig_i_2_n_0 : STD_LOGIC;
  signal ddrAXI_bready_sig_i_3_n_0 : STD_LOGIC;
  signal ddrAXI_bready_sig_i_4_n_0 : STD_LOGIC;
  signal \^ddraxi_bready_sig_reg_0\ : STD_LOGIC;
  signal ddrAXI_rready_INST_0_i_10_n_0 : STD_LOGIC;
  signal ddrAXI_rready_INST_0_i_11_n_0 : STD_LOGIC;
  signal ddrAXI_rready_INST_0_i_12_n_0 : STD_LOGIC;
  signal ddrAXI_rready_INST_0_i_13_n_0 : STD_LOGIC;
  signal ddrAXI_rready_INST_0_i_2_n_0 : STD_LOGIC;
  signal ddrAXI_rready_INST_0_i_3_n_0 : STD_LOGIC;
  signal ddrAXI_rready_INST_0_i_4_n_0 : STD_LOGIC;
  signal ddrAXI_rready_INST_0_i_5_n_0 : STD_LOGIC;
  signal ddrAXI_rready_INST_0_i_6_n_0 : STD_LOGIC;
  signal ddrAXI_rready_INST_0_i_7_n_0 : STD_LOGIC;
  signal ddrAXI_rready_INST_0_i_8_n_0 : STD_LOGIC;
  signal ddrAXI_rready_INST_0_i_9_n_0 : STD_LOGIC;
  signal \i[10]_i_2_n_0\ : STD_LOGIC;
  signal \i[13]_i_1_n_0\ : STD_LOGIC;
  signal \i[13]_i_2_n_0\ : STD_LOGIC;
  signal \i[13]_i_3_n_0\ : STD_LOGIC;
  signal \i[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \i[5]_i_2__1_n_0\ : STD_LOGIC;
  signal \i[9]_i_2__0_n_0\ : STD_LOGIC;
  signal i_reg : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal ixRdid : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ixRdidEgr : STD_LOGIC;
  signal \ixRdidEgr[0]_i_1_n_0\ : STD_LOGIC;
  signal \ixRdidEgr[1]_i_1_n_0\ : STD_LOGIC;
  signal \ixRdidEgr[2]_i_1_n_0\ : STD_LOGIC;
  signal \ixRdidEgr[3]_i_1_n_0\ : STD_LOGIC;
  signal \ixRdidEgr[4]_i_2_n_0\ : STD_LOGIC;
  signal \ixRdidEgr__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^ixrdidegr_reg[4]_0\ : STD_LOGIC;
  signal \ixRdid[2]_i_1_n_0\ : STD_LOGIC;
  signal \ixRdid[3]_i_1_n_0\ : STD_LOGIC;
  signal \ixRdid[4]_i_1_n_0\ : STD_LOGIC;
  signal \ixRdid[4]_i_2_n_0\ : STD_LOGIC;
  signal \ixRdid__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal p_0_in : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal plusOp : STD_LOGIC_VECTOR ( 31 downto 4 );
  signal \rdid[0][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[0][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[0][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[10][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[10][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[11][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[11][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[12][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[12][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[12][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[13][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[13][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[13][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[14][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[14][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[14][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[15][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[15][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[15][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[16][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[16][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[16][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[16][0]_i_4_n_0\ : STD_LOGIC;
  signal \rdid[17][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[17][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[17][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[18][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[18][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[18][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[18][0]_i_4_n_0\ : STD_LOGIC;
  signal \rdid[18][0]_i_5_n_0\ : STD_LOGIC;
  signal \rdid[19][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[19][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[19][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[1][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[1][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[1][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[1][0]_i_5_n_0\ : STD_LOGIC;
  signal \rdid[20][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[20][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[20][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[21][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[21][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[22][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[22][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[22][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[23][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[23][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[23][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[24][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[24][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[25][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[25][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[25][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[26][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[26][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[27][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[27][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[27][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[27][0]_i_4_n_0\ : STD_LOGIC;
  signal \rdid[28][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[28][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[29][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[29][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[2][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[2][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[2][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[2][0]_i_4_n_0\ : STD_LOGIC;
  signal \rdid[30][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[30][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[31][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[31][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[3][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[3][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[3][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[3][0]_i_4_n_0\ : STD_LOGIC;
  signal \rdid[3][0]_i_5_n_0\ : STD_LOGIC;
  signal \rdid[4][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[4][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[4][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[5][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[5][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[5][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[5][0]_i_4_n_0\ : STD_LOGIC;
  signal \rdid[5][0]_i_5_n_0\ : STD_LOGIC;
  signal \rdid[5][0]_i_6_n_0\ : STD_LOGIC;
  signal \rdid[6][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[6][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[6][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[7][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[7][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[8][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[8][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[8][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[9][0]_i_1_n_0\ : STD_LOGIC;
  signal \rdid[9][0]_i_2_n_0\ : STD_LOGIC;
  signal \rdid[9][0]_i_3_n_0\ : STD_LOGIC;
  signal \rdid[9][0]_i_4_n_0\ : STD_LOGIC;
  signal \rdid_reg[0]_3\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[10]_13\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[11]_14\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[12]_15\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[13]_16\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[14]_17\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[15]_18\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[16]_19\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[17]_20\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[18]_21\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[19]_22\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[1]_4\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[20]_23\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[21]_24\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[22]_25\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[23]_26\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[24]_27\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[25]_28\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[26]_29\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[27]_30\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[28]_31\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[29]_32\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[2]_5\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[30]_33\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[31]_34\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[3]_6\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[4]_7\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[5]_8\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[6]_9\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[7]_10\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[8]_11\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdid_reg[9]_12\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rdmutex[0]_i_1_n_0\ : STD_LOGIC;
  signal \rdmutex[1]_i_10_n_0\ : STD_LOGIC;
  signal \rdmutex[1]_i_11_n_0\ : STD_LOGIC;
  signal \rdmutex[1]_i_12_n_0\ : STD_LOGIC;
  signal \rdmutex[1]_i_13_n_0\ : STD_LOGIC;
  signal \rdmutex[1]_i_14_n_0\ : STD_LOGIC;
  signal \rdmutex[1]_i_15_n_0\ : STD_LOGIC;
  signal \rdmutex[1]_i_16_n_0\ : STD_LOGIC;
  signal \rdmutex[1]_i_1_n_0\ : STD_LOGIC;
  signal \rdmutex[1]_i_2_n_0\ : STD_LOGIC;
  signal \rdmutex[1]_i_9_n_0\ : STD_LOGIC;
  signal \^rdmutex_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^rdmutex_reg[1]_1\ : STD_LOGIC;
  signal \rdmutex_reg[1]_i_3_n_0\ : STD_LOGIC;
  signal \rdmutex_reg[1]_i_4_n_0\ : STD_LOGIC;
  signal \rdmutex_reg[1]_i_5_n_0\ : STD_LOGIC;
  signal \rdmutex_reg[1]_i_6_n_0\ : STD_LOGIC;
  signal \rdmutex_reg[1]_i_7_n_0\ : STD_LOGIC;
  signal \rdmutex_reg[1]_i_8_n_0\ : STD_LOGIC;
  signal \^statestats\ : STD_LOGIC;
  signal \strbRdlock_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \strbRdlock_i[1]_i_1_n_0\ : STD_LOGIC;
  signal \strbRdlock_i[2]_i_1_n_0\ : STD_LOGIC;
  signal \strbRdlock_i[3]_i_1_n_0\ : STD_LOGIC;
  signal \strbRdlock_i[3]_i_2_n_0\ : STD_LOGIC;
  signal strbRdlock_i_1_n_0 : STD_LOGIC;
  signal strbRdlock_i_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal strbRdlock_mclk_i_1_n_0 : STD_LOGIC;
  signal strbRdlock_mclk_reg_n_0 : STD_LOGIC;
  signal strbRdlock_reg_n_0 : STD_LOGIC;
  signal strbRdlock_to_mclk_i_1_n_0 : STD_LOGIC;
  signal strbRdlock_to_mclk_reg_n_0 : STD_LOGIC;
  signal strbRdlock_to_mclkm1 : STD_LOGIC;
  signal strbRdlock_to_mclkm2 : STD_LOGIC;
  signal strbRdlock_wait9_out : STD_LOGIC;
  signal strbRdlock_wait_reg_n_0 : STD_LOGIC;
  signal strbWrlock : STD_LOGIC;
  signal \strbWrlock_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \strbWrlock_i[1]_i_1_n_0\ : STD_LOGIC;
  signal \strbWrlock_i[2]_i_1_n_0\ : STD_LOGIC;
  signal \strbWrlock_i[3]_i_1_n_0\ : STD_LOGIC;
  signal \strbWrlock_i[3]_i_2_n_0\ : STD_LOGIC;
  signal strbWrlock_i_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal strbWrlock_mclk_i_1_n_0 : STD_LOGIC;
  signal strbWrlock_mclk_reg_n_0 : STD_LOGIC;
  signal strbWrlock_to_mclk_i_1_n_0 : STD_LOGIC;
  signal strbWrlock_to_mclk_reg_n_0 : STD_LOGIC;
  signal strbWrlock_to_mclkm1 : STD_LOGIC;
  signal strbWrlock_to_mclkm2 : STD_LOGIC;
  signal strbWrlock_wait3_out : STD_LOGIC;
  signal strbWrlock_wait_reg_n_0 : STD_LOGIC;
  signal wdone_i_1_n_0 : STD_LOGIC;
  signal wdone_i_2_n_0 : STD_LOGIC;
  signal wdone_reg_n_0 : STD_LOGIC;
  signal \^wrmutex_reg[1]_0\ : STD_LOGIC;
  signal \^wrmutex_reg[1]_1\ : STD_LOGIC;
  signal \wrmutex_reg_n_0_[0]\ : STD_LOGIC;
  signal \wrmutex_reg_n_0_[1]\ : STD_LOGIC;
  signal wtr : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \wtr[0]_i_1_n_0\ : STD_LOGIC;
  signal \wtr[1]_i_1_n_0\ : STD_LOGIC;
  signal \wtr[2]_i_1_n_0\ : STD_LOGIC;
  signal \wtr[3]_i_1_n_0\ : STD_LOGIC;
  signal \wtr[4]_i_1_n_0\ : STD_LOGIC;
  signal \wtr[4]_i_2_n_0\ : STD_LOGIC;
  signal \wtr[4]_i_3_n_0\ : STD_LOGIC;
  signal \wtr[4]_i_4_n_0\ : STD_LOGIC;
  signal \wtr[4]_i_5_n_0\ : STD_LOGIC;
  signal \NLW_NRdA_collect_reg[10]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_NRdA_collect_reg[31]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_NRdA_collect_reg[31]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_NRdB_collect_reg[10]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_NRdB_collect_reg[31]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_NRdB_collect_reg[31]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_NWrA_collect_reg[10]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_NWrA_collect_reg[31]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_NWrA_collect_reg[31]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_NWrB_collect_reg[10]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_NWrB_collect_reg[31]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_NWrB_collect_reg[31]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_stateRead[1]_i_1\ : label is "soft_lutpair1625";
  attribute SOFT_HLUTNM of \FSM_onehot_stateRead[2]_i_2\ : label is "soft_lutpair1587";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateRead_reg[0]\ : label is "iSTATE:100,iSTATE0:001,iSTATE1:010,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateRead_reg[1]\ : label is "iSTATE:100,iSTATE0:001,iSTATE1:010,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateRead_reg[2]\ : label is "iSTATE:100,iSTATE0:001,iSTATE1:010,";
  attribute SOFT_HLUTNM of \FSM_onehot_stateWrite[1]_i_1\ : label is "soft_lutpair1618";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateWrite_reg[0]\ : label is "iSTATE:100,iSTATE0:001,iSTATE1:010,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateWrite_reg[1]\ : label is "iSTATE:100,iSTATE0:001,iSTATE1:010,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateWrite_reg[2]\ : label is "iSTATE:100,iSTATE0:001,iSTATE1:010,";
  attribute SOFT_HLUTNM of \FSM_sequential_stateIgrstr[0]_i_3\ : label is "soft_lutpair1598";
  attribute SOFT_HLUTNM of \FSM_sequential_stateIgrstr[1]_i_4\ : label is "soft_lutpair1598";
  attribute SOFT_HLUTNM of \NRdA[30]_i_1\ : label is "soft_lutpair1572";
  attribute SOFT_HLUTNM of \NRdA[31]_i_2\ : label is "soft_lutpair1571";
  attribute SOFT_HLUTNM of \NRdA[31]_i_3\ : label is "soft_lutpair1588";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \NRdA_collect_reg[10]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \NRdA_collect_reg[18]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \NRdA_collect_reg[26]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \NRdA_collect_reg[31]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \NRdB_collect_reg[10]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \NRdB_collect_reg[18]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \NRdB_collect_reg[26]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \NRdB_collect_reg[31]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \NWrA_collect_reg[10]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \NWrA_collect_reg[18]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \NWrA_collect_reg[26]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \NWrA_collect_reg[31]_i_2\ : label is 35;
  attribute SOFT_HLUTNM of \NWrB[30]_i_1\ : label is "soft_lutpair1586";
  attribute SOFT_HLUTNM of \NWrB[31]_i_1\ : label is "soft_lutpair1585";
  attribute ADDER_THRESHOLD of \NWrB_collect_reg[10]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \NWrB_collect_reg[18]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \NWrB_collect_reg[26]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \NWrB_collect_reg[31]_i_2\ : label is 35;
  attribute SOFT_HLUTNM of \aRowbufBEgrstr[8]_i_3\ : label is "soft_lutpair1624";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[10]_INST_0\ : label is "soft_lutpair1602";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[11]_INST_0\ : label is "soft_lutpair1602";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[12]_INST_0\ : label is "soft_lutpair1603";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[13]_INST_0\ : label is "soft_lutpair1603";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[14]_INST_0\ : label is "soft_lutpair1604";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[15]_INST_0\ : label is "soft_lutpair1604";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[16]_INST_0\ : label is "soft_lutpair1605";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[17]_INST_0\ : label is "soft_lutpair1605";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[18]_INST_0\ : label is "soft_lutpair1606";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[19]_INST_0\ : label is "soft_lutpair1606";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[20]_INST_0\ : label is "soft_lutpair1607";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[21]_INST_0\ : label is "soft_lutpair1607";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[22]_INST_0\ : label is "soft_lutpair1608";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[23]_INST_0\ : label is "soft_lutpair1608";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[24]_INST_0\ : label is "soft_lutpair1609";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[25]_INST_0\ : label is "soft_lutpair1609";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[26]_INST_0\ : label is "soft_lutpair1610";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[27]_INST_0\ : label is "soft_lutpair1610";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[28]_INST_0\ : label is "soft_lutpair1572";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[8]_INST_0\ : label is "soft_lutpair1601";
  attribute SOFT_HLUTNM of \ddrAXI_araddr[9]_INST_0\ : label is "soft_lutpair1601";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[28]_INST_0\ : label is "soft_lutpair1585";
  attribute SOFT_HLUTNM of ddrAXI_bready_sig_i_4 : label is "soft_lutpair1584";
  attribute SOFT_HLUTNM of ddrAXI_wvalid_INST_0_i_1 : label is "soft_lutpair1586";
  attribute SOFT_HLUTNM of \i[0]_i_1__3\ : label is "soft_lutpair1626";
  attribute SOFT_HLUTNM of \i[0]_i_1__8\ : label is "soft_lutpair1626";
  attribute SOFT_HLUTNM of \i[10]_i_1\ : label is "soft_lutpair1617";
  attribute SOFT_HLUTNM of \i[11]_i_1\ : label is "soft_lutpair1617";
  attribute SOFT_HLUTNM of \i[12]_i_1\ : label is "soft_lutpair1566";
  attribute SOFT_HLUTNM of \i[13]_i_2\ : label is "soft_lutpair1566";
  attribute SOFT_HLUTNM of \i[1]_i_1__5\ : label is "soft_lutpair1588";
  attribute SOFT_HLUTNM of \i[2]_i_1__1\ : label is "soft_lutpair1580";
  attribute SOFT_HLUTNM of \i[3]_i_1__1\ : label is "soft_lutpair1580";
  attribute SOFT_HLUTNM of \i[5]_i_1__1\ : label is "soft_lutpair1616";
  attribute SOFT_HLUTNM of \i[6]_i_1__1\ : label is "soft_lutpair1616";
  attribute SOFT_HLUTNM of \i[7]_i_1__1\ : label is "soft_lutpair1581";
  attribute SOFT_HLUTNM of \i[8]_i_1__0\ : label is "soft_lutpair1581";
  attribute SOFT_HLUTNM of \ixRdidEgr[0]_i_1\ : label is "soft_lutpair1623";
  attribute SOFT_HLUTNM of \ixRdidEgr[1]_i_1\ : label is "soft_lutpair1621";
  attribute SOFT_HLUTNM of \ixRdidEgr[2]_i_1\ : label is "soft_lutpair1567";
  attribute SOFT_HLUTNM of \ixRdidEgr[3]_i_1\ : label is "soft_lutpair1567";
  attribute SOFT_HLUTNM of \ixRdid[0]_i_1\ : label is "soft_lutpair1619";
  attribute SOFT_HLUTNM of \ixRdid[1]_i_1\ : label is "soft_lutpair1619";
  attribute SOFT_HLUTNM of \ixRdid[2]_i_1\ : label is "soft_lutpair1565";
  attribute SOFT_HLUTNM of \ixRdid[3]_i_1\ : label is "soft_lutpair1565";
  attribute SOFT_HLUTNM of \ixRdid[4]_i_3\ : label is "soft_lutpair1571";
  attribute SOFT_HLUTNM of \probe[5]_INST_0\ : label is "soft_lutpair1624";
  attribute SOFT_HLUTNM of \rdid[0][0]_i_3\ : label is "soft_lutpair1589";
  attribute SOFT_HLUTNM of \rdid[10][0]_i_2\ : label is "soft_lutpair1578";
  attribute SOFT_HLUTNM of \rdid[12][0]_i_3\ : label is "soft_lutpair1574";
  attribute SOFT_HLUTNM of \rdid[13][0]_i_2\ : label is "soft_lutpair1600";
  attribute SOFT_HLUTNM of \rdid[13][0]_i_3\ : label is "soft_lutpair1613";
  attribute SOFT_HLUTNM of \rdid[14][0]_i_2\ : label is "soft_lutpair1578";
  attribute SOFT_HLUTNM of \rdid[14][0]_i_3\ : label is "soft_lutpair1583";
  attribute SOFT_HLUTNM of \rdid[15][0]_i_3\ : label is "soft_lutpair1583";
  attribute SOFT_HLUTNM of \rdid[16][0]_i_2\ : label is "soft_lutpair1612";
  attribute SOFT_HLUTNM of \rdid[16][0]_i_3\ : label is "soft_lutpair1570";
  attribute SOFT_HLUTNM of \rdid[16][0]_i_4\ : label is "soft_lutpair1575";
  attribute SOFT_HLUTNM of \rdid[17][0]_i_3\ : label is "soft_lutpair1591";
  attribute SOFT_HLUTNM of \rdid[18][0]_i_2\ : label is "soft_lutpair1614";
  attribute SOFT_HLUTNM of \rdid[18][0]_i_3\ : label is "soft_lutpair1599";
  attribute SOFT_HLUTNM of \rdid[18][0]_i_5\ : label is "soft_lutpair1574";
  attribute SOFT_HLUTNM of \rdid[19][0]_i_2\ : label is "soft_lutpair1611";
  attribute SOFT_HLUTNM of \rdid[19][0]_i_3\ : label is "soft_lutpair1599";
  attribute SOFT_HLUTNM of \rdid[1][0]_i_3\ : label is "soft_lutpair1622";
  attribute SOFT_HLUTNM of \rdid[20][0]_i_2\ : label is "soft_lutpair1575";
  attribute SOFT_HLUTNM of \rdid[20][0]_i_3\ : label is "soft_lutpair1614";
  attribute SOFT_HLUTNM of \rdid[21][0]_i_2\ : label is "soft_lutpair1576";
  attribute SOFT_HLUTNM of \rdid[22][0]_i_3\ : label is "soft_lutpair1612";
  attribute SOFT_HLUTNM of \rdid[23][0]_i_3\ : label is "soft_lutpair1591";
  attribute SOFT_HLUTNM of \rdid[25][0]_i_2\ : label is "soft_lutpair1622";
  attribute SOFT_HLUTNM of \rdid[27][0]_i_2\ : label is "soft_lutpair1570";
  attribute SOFT_HLUTNM of \rdid[27][0]_i_3\ : label is "soft_lutpair1620";
  attribute SOFT_HLUTNM of \rdid[27][0]_i_4\ : label is "soft_lutpair1615";
  attribute SOFT_HLUTNM of \rdid[29][0]_i_2\ : label is "soft_lutpair1615";
  attribute SOFT_HLUTNM of \rdid[2][0]_i_2\ : label is "soft_lutpair1573";
  attribute SOFT_HLUTNM of \rdid[2][0]_i_3\ : label is "soft_lutpair1589";
  attribute SOFT_HLUTNM of \rdid[2][0]_i_4\ : label is "soft_lutpair1613";
  attribute SOFT_HLUTNM of \rdid[30][0]_i_2\ : label is "soft_lutpair1579";
  attribute SOFT_HLUTNM of \rdid[3][0]_i_2\ : label is "soft_lutpair1611";
  attribute SOFT_HLUTNM of \rdid[3][0]_i_3\ : label is "soft_lutpair1621";
  attribute SOFT_HLUTNM of \rdid[3][0]_i_4\ : label is "soft_lutpair1590";
  attribute SOFT_HLUTNM of \rdid[3][0]_i_5\ : label is "soft_lutpair1577";
  attribute SOFT_HLUTNM of \rdid[4][0]_i_3\ : label is "soft_lutpair1623";
  attribute SOFT_HLUTNM of \rdid[5][0]_i_2\ : label is "soft_lutpair1579";
  attribute SOFT_HLUTNM of \rdid[5][0]_i_3\ : label is "soft_lutpair1577";
  attribute SOFT_HLUTNM of \rdid[5][0]_i_6\ : label is "soft_lutpair1576";
  attribute SOFT_HLUTNM of \rdid[6][0]_i_3\ : label is "soft_lutpair1620";
  attribute SOFT_HLUTNM of \rdid[8][0]_i_2\ : label is "soft_lutpair1590";
  attribute SOFT_HLUTNM of \rdid[8][0]_i_3\ : label is "soft_lutpair1573";
  attribute SOFT_HLUTNM of \rdid[9][0]_i_3\ : label is "soft_lutpair1600";
  attribute SOFT_HLUTNM of \rdmutex[1]_i_1\ : label is "soft_lutpair1625";
  attribute SOFT_HLUTNM of \strbRdlock_i[0]_i_1\ : label is "soft_lutpair1596";
  attribute SOFT_HLUTNM of \strbRdlock_i[1]_i_1\ : label is "soft_lutpair1596";
  attribute SOFT_HLUTNM of \strbRdlock_i[2]_i_1\ : label is "soft_lutpair1568";
  attribute SOFT_HLUTNM of \strbRdlock_i[3]_i_2\ : label is "soft_lutpair1568";
  attribute SOFT_HLUTNM of strbRdlock_i_1 : label is "soft_lutpair1587";
  attribute SOFT_HLUTNM of strbRdlock_mclk_i_1 : label is "soft_lutpair1592";
  attribute SOFT_HLUTNM of strbRdlock_wait_i_1 : label is "soft_lutpair1592";
  attribute SOFT_HLUTNM of \strbWrlock_i[0]_i_1\ : label is "soft_lutpair1597";
  attribute SOFT_HLUTNM of \strbWrlock_i[1]_i_1\ : label is "soft_lutpair1597";
  attribute SOFT_HLUTNM of \strbWrlock_i[2]_i_1\ : label is "soft_lutpair1569";
  attribute SOFT_HLUTNM of \strbWrlock_i[3]_i_2\ : label is "soft_lutpair1569";
  attribute SOFT_HLUTNM of strbWrlock_mclk_i_1 : label is "soft_lutpair1593";
  attribute SOFT_HLUTNM of strbWrlock_wait_i_1 : label is "soft_lutpair1593";
  attribute SOFT_HLUTNM of wdone_i_2 : label is "soft_lutpair1618";
  attribute SOFT_HLUTNM of \wtr[0]_i_1\ : label is "soft_lutpair1595";
  attribute SOFT_HLUTNM of \wtr[1]_i_1\ : label is "soft_lutpair1582";
  attribute SOFT_HLUTNM of \wtr[2]_i_1\ : label is "soft_lutpair1582";
  attribute SOFT_HLUTNM of \wtr[4]_i_3\ : label is "soft_lutpair1594";
  attribute SOFT_HLUTNM of \wtr[4]_i_4\ : label is "soft_lutpair1595";
  attribute SOFT_HLUTNM of \wtr[4]_i_5\ : label is "soft_lutpair1584";
  attribute SOFT_HLUTNM of \wtr[4]_i_6\ : label is "soft_lutpair1594";
begin
  \FSM_onehot_stateRead_reg[2]_0\(0) <= \^fsm_onehot_stateread_reg[2]_0\(0);
  Q(1 downto 0) <= \^q\(1 downto 0);
  ddrAXI_bready_sig_reg_0 <= \^ddraxi_bready_sig_reg_0\;
  \ixRdidEgr_reg[4]_0\ <= \^ixrdidegr_reg[4]_0\;
  \rdmutex_reg[1]_0\(1 downto 0) <= \^rdmutex_reg[1]_0\(1 downto 0);
  \rdmutex_reg[1]_1\ <= \^rdmutex_reg[1]_1\;
  stateStats <= \^statestats\;
  \wrmutex_reg[1]_0\ <= \^wrmutex_reg[1]_0\;
  \wrmutex_reg[1]_1\ <= \^wrmutex_reg[1]_1\;
\FSM_onehot_stateRead[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I1 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      O => \FSM_onehot_stateRead[1]_i_1_n_0\
    );
\FSM_onehot_stateRead[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \ixRdid[4]_i_1_n_0\,
      I1 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      O => \FSM_onehot_stateRead[2]_i_1_n_0\
    );
\FSM_onehot_stateRead[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \rdmutex[1]_i_2_n_0\,
      I1 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      O => \FSM_onehot_stateRead[2]_i_2_n_0\
    );
\FSM_onehot_stateRead_reg[0]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '1'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateRead[2]_i_1_n_0\,
      D => '0',
      PRE => \strbWrlock_i_reg[0]_0\(0),
      Q => \FSM_onehot_stateRead_reg_n_0_[0]\
    );
\FSM_onehot_stateRead_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateRead[2]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \FSM_onehot_stateRead[1]_i_1_n_0\,
      Q => \FSM_onehot_stateRead_reg_n_0_[1]\
    );
\FSM_onehot_stateRead_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateRead[2]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \FSM_onehot_stateRead_reg_n_0_[1]\,
      Q => \^fsm_onehot_stateread_reg[2]_0\(0)
    );
\FSM_onehot_stateWrite[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => ddrAXI_bready_sig,
      I1 => \^q\(0),
      O => \FSM_onehot_stateWrite[1]_i_1_n_0\
    );
\FSM_onehot_stateWrite[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEAAAAAAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_stateWrite[2]_i_2_n_0\,
      I1 => ddrAXI_awready,
      I2 => ddrAXI_awvalid,
      I3 => awdone_reg_n_0,
      I4 => \^q\(1),
      I5 => \FSM_onehot_stateWrite[2]_i_3_n_0\,
      O => \FSM_onehot_stateWrite[2]_i_1_n_0\
    );
\FSM_onehot_stateWrite[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAEAEAEAEAEAAAEA"
    )
        port map (
      I0 => ddrAXI_bready_sig,
      I1 => wrAAXI_awvalid,
      I2 => \^q\(0),
      I3 => wtr(4),
      I4 => \wtr[4]_i_4_n_0\,
      I5 => wtr(3),
      O => \FSM_onehot_stateWrite[2]_i_2_n_0\
    );
\FSM_onehot_stateWrite[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEF0F0F0FFF0F0F0"
    )
        port map (
      I0 => \wrmutex_reg_n_0_[1]\,
      I1 => wrAAXI_wlast,
      I2 => wdone_reg_n_0,
      I3 => ddrAXI_wready,
      I4 => ddrAXI_wvalid,
      I5 => \wrmutex_reg_n_0_[0]\,
      O => \FSM_onehot_stateWrite[2]_i_3_n_0\
    );
\FSM_onehot_stateWrite_reg[0]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '1'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateWrite[2]_i_1_n_0\,
      D => '0',
      PRE => \strbWrlock_i_reg[0]_0\(0),
      Q => ddrAXI_bready_sig
    );
\FSM_onehot_stateWrite_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateWrite[2]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \FSM_onehot_stateWrite[1]_i_1_n_0\,
      Q => \^q\(0)
    );
\FSM_onehot_stateWrite_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateWrite[2]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \^q\(0),
      Q => \^q\(1)
    );
\FSM_sequential_stateIgrstr[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => ddrAXI_rlast,
      I1 => \^ixrdidegr_reg[4]_0\,
      O => hdrmemAXI_rlast
    );
\FSM_sequential_stateIgrstr[1]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => ddrAXI_rvalid,
      I1 => \^ixrdidegr_reg[4]_0\,
      I2 => \burstIgrstr_reg[0]\(0),
      O => ddrAXI_rvalid_0
    );
\NRdA[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(10),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[10]\,
      O => \NRdA[10]_i_1_n_0\
    );
\NRdA[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(11),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[11]\,
      O => \NRdA[11]_i_1_n_0\
    );
\NRdA[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(12),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[12]\,
      O => \NRdA[12]_i_1_n_0\
    );
\NRdA[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(13),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[13]\,
      O => \NRdA[13]_i_1_n_0\
    );
\NRdA[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(14),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[14]\,
      O => \NRdA[14]_i_1_n_0\
    );
\NRdA[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(15),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[15]\,
      O => \NRdA[15]_i_1_n_0\
    );
\NRdA[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(16),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[16]\,
      O => \NRdA[16]_i_1_n_0\
    );
\NRdA[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(17),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[17]\,
      O => \NRdA[17]_i_1_n_0\
    );
\NRdA[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(18),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[18]\,
      O => \NRdA[18]_i_1_n_0\
    );
\NRdA[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(19),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[19]\,
      O => \NRdA[19]_i_1_n_0\
    );
\NRdA[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(20),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[20]\,
      O => \NRdA[20]_i_1_n_0\
    );
\NRdA[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(21),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[21]\,
      O => \NRdA[21]_i_1_n_0\
    );
\NRdA[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(22),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[22]\,
      O => \NRdA[22]_i_1_n_0\
    );
\NRdA[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(23),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[23]\,
      O => \NRdA[23]_i_1_n_0\
    );
\NRdA[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(24),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[24]\,
      O => \NRdA[24]_i_1_n_0\
    );
\NRdA[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(25),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[25]\,
      O => \NRdA[25]_i_1_n_0\
    );
\NRdA[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(26),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[26]\,
      O => \NRdA[26]_i_1_n_0\
    );
\NRdA[27]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(27),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[27]\,
      O => \NRdA[27]_i_1_n_0\
    );
\NRdA[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(28),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[28]\,
      O => \NRdA[28]_i_1_n_0\
    );
\NRdA[29]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(29),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[29]\,
      O => \NRdA[29]_i_1_n_0\
    );
\NRdA[30]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(30),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[30]\,
      O => \NRdA[30]_i_1_n_0\
    );
\NRdA[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \NRdA[31]_i_3_n_0\,
      I1 => i_reg(10),
      I2 => i_reg(9),
      I3 => i_reg(7),
      I4 => i_reg(3),
      I5 => \NRdA[31]_i_4_n_0\,
      O => NRdA
    );
\NRdA[31]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(31),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[31]\,
      O => \NRdA[31]_i_2_n_0\
    );
\NRdA[31]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => tkclk,
      I1 => \^statestats\,
      I2 => i_reg(1),
      I3 => i_reg(0),
      O => \NRdA[31]_i_3_n_0\
    );
\NRdA[31]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
        port map (
      I0 => i_reg(12),
      I1 => i_reg(4),
      I2 => i_reg(2),
      I3 => i_reg(6),
      I4 => \NRdA[31]_i_5_n_0\,
      O => \NRdA[31]_i_4_n_0\
    );
\NRdA[31]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => i_reg(8),
      I1 => i_reg(5),
      I2 => i_reg(13),
      I3 => i_reg(11),
      O => \NRdA[31]_i_5_n_0\
    );
\NRdA[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(4),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[4]\,
      O => \NRdA[4]_i_1_n_0\
    );
\NRdA[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(5),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[5]\,
      O => \NRdA[5]_i_1_n_0\
    );
\NRdA[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(6),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[6]\,
      O => \NRdA[6]_i_1_n_0\
    );
\NRdA[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(7),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[7]\,
      O => \NRdA[7]_i_1_n_0\
    );
\NRdA[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(8),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[8]\,
      O => \NRdA[8]_i_1_n_0\
    );
\NRdA[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF0080"
    )
        port map (
      I0 => plusOp(9),
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdA_collect_reg_n_0_[9]\,
      O => \NRdA[9]_i_1_n_0\
    );
\NRdA_collect[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[10]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(10),
      I5 => NRdA,
      O => \NRdA_collect[10]_i_1_n_0\
    );
\NRdA_collect[10]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[4]\,
      O => \NRdA_collect[10]_i_3_n_0\
    );
\NRdA_collect[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[11]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(11),
      I5 => NRdA,
      O => \NRdA_collect[11]_i_1_n_0\
    );
\NRdA_collect[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[12]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(12),
      I5 => NRdA,
      O => \NRdA_collect[12]_i_1_n_0\
    );
\NRdA_collect[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[13]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(13),
      I5 => NRdA,
      O => \NRdA_collect[13]_i_1_n_0\
    );
\NRdA_collect[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[14]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(14),
      I5 => NRdA,
      O => \NRdA_collect[14]_i_1_n_0\
    );
\NRdA_collect[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[15]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(15),
      I5 => NRdA,
      O => \NRdA_collect[15]_i_1_n_0\
    );
\NRdA_collect[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[16]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(16),
      I5 => NRdA,
      O => \NRdA_collect[16]_i_1_n_0\
    );
\NRdA_collect[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[17]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(17),
      I5 => NRdA,
      O => \NRdA_collect[17]_i_1_n_0\
    );
\NRdA_collect[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[18]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(18),
      I5 => NRdA,
      O => \NRdA_collect[18]_i_1_n_0\
    );
\NRdA_collect[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[19]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(19),
      I5 => NRdA,
      O => \NRdA_collect[19]_i_1_n_0\
    );
\NRdA_collect[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[20]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(20),
      I5 => NRdA,
      O => \NRdA_collect[20]_i_1_n_0\
    );
\NRdA_collect[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[21]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(21),
      I5 => NRdA,
      O => \NRdA_collect[21]_i_1_n_0\
    );
\NRdA_collect[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[22]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(22),
      I5 => NRdA,
      O => \NRdA_collect[22]_i_1_n_0\
    );
\NRdA_collect[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[23]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(23),
      I5 => NRdA,
      O => \NRdA_collect[23]_i_1_n_0\
    );
\NRdA_collect[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[24]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(24),
      I5 => NRdA,
      O => \NRdA_collect[24]_i_1_n_0\
    );
\NRdA_collect[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[25]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(25),
      I5 => NRdA,
      O => \NRdA_collect[25]_i_1_n_0\
    );
\NRdA_collect[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[26]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(26),
      I5 => NRdA,
      O => \NRdA_collect[26]_i_1_n_0\
    );
\NRdA_collect[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[27]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(27),
      I5 => NRdA,
      O => \NRdA_collect[27]_i_1_n_0\
    );
\NRdA_collect[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[28]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(28),
      I5 => NRdA,
      O => \NRdA_collect[28]_i_1_n_0\
    );
\NRdA_collect[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[29]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(29),
      I5 => NRdA,
      O => \NRdA_collect[29]_i_1_n_0\
    );
\NRdA_collect[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[30]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(30),
      I5 => NRdA,
      O => \NRdA_collect[30]_i_1_n_0\
    );
\NRdA_collect[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[31]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(31),
      I5 => NRdA,
      O => \NRdA_collect[31]_i_1_n_0\
    );
\NRdA_collect[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[4]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(4),
      I5 => NRdA,
      O => \NRdA_collect[4]_i_1_n_0\
    );
\NRdA_collect[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[5]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(5),
      I5 => NRdA,
      O => \NRdA_collect[5]_i_1_n_0\
    );
\NRdA_collect[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[6]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(6),
      I5 => NRdA,
      O => \NRdA_collect[6]_i_1_n_0\
    );
\NRdA_collect[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[7]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(7),
      I5 => NRdA,
      O => \NRdA_collect[7]_i_1_n_0\
    );
\NRdA_collect[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[8]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(8),
      I5 => NRdA,
      O => \NRdA_collect[8]_i_1_n_0\
    );
\NRdA_collect[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BAAA8AAA"
    )
        port map (
      I0 => \NRdA_collect_reg_n_0_[9]\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => plusOp(9),
      I5 => NRdA,
      O => \NRdA_collect[9]_i_1_n_0\
    );
\NRdA_collect_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[10]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[10]\
    );
\NRdA_collect_reg[10]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \NRdA_collect_reg[10]_i_2_n_0\,
      CO(6) => \NRdA_collect_reg[10]_i_2_n_1\,
      CO(5) => \NRdA_collect_reg[10]_i_2_n_2\,
      CO(4) => \NRdA_collect_reg[10]_i_2_n_3\,
      CO(3) => \NRdA_collect_reg[10]_i_2_n_4\,
      CO(2) => \NRdA_collect_reg[10]_i_2_n_5\,
      CO(1) => \NRdA_collect_reg[10]_i_2_n_6\,
      CO(0) => \NRdA_collect_reg[10]_i_2_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \NRdA_collect_reg_n_0_[4]\,
      DI(0) => '0',
      O(7 downto 1) => plusOp(10 downto 4),
      O(0) => \NLW_NRdA_collect_reg[10]_i_2_O_UNCONNECTED\(0),
      S(7) => \NRdA_collect_reg_n_0_[10]\,
      S(6) => \NRdA_collect_reg_n_0_[9]\,
      S(5) => \NRdA_collect_reg_n_0_[8]\,
      S(4) => \NRdA_collect_reg_n_0_[7]\,
      S(3) => \NRdA_collect_reg_n_0_[6]\,
      S(2) => \NRdA_collect_reg_n_0_[5]\,
      S(1) => \NRdA_collect[10]_i_3_n_0\,
      S(0) => '0'
    );
\NRdA_collect_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[11]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[11]\
    );
\NRdA_collect_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[12]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[12]\
    );
\NRdA_collect_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[13]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[13]\
    );
\NRdA_collect_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[14]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[14]\
    );
\NRdA_collect_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[15]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[15]\
    );
\NRdA_collect_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[16]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[16]\
    );
\NRdA_collect_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[17]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[17]\
    );
\NRdA_collect_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[18]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[18]\
    );
\NRdA_collect_reg[18]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \NRdA_collect_reg[10]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \NRdA_collect_reg[18]_i_2_n_0\,
      CO(6) => \NRdA_collect_reg[18]_i_2_n_1\,
      CO(5) => \NRdA_collect_reg[18]_i_2_n_2\,
      CO(4) => \NRdA_collect_reg[18]_i_2_n_3\,
      CO(3) => \NRdA_collect_reg[18]_i_2_n_4\,
      CO(2) => \NRdA_collect_reg[18]_i_2_n_5\,
      CO(1) => \NRdA_collect_reg[18]_i_2_n_6\,
      CO(0) => \NRdA_collect_reg[18]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => plusOp(18 downto 11),
      S(7) => \NRdA_collect_reg_n_0_[18]\,
      S(6) => \NRdA_collect_reg_n_0_[17]\,
      S(5) => \NRdA_collect_reg_n_0_[16]\,
      S(4) => \NRdA_collect_reg_n_0_[15]\,
      S(3) => \NRdA_collect_reg_n_0_[14]\,
      S(2) => \NRdA_collect_reg_n_0_[13]\,
      S(1) => \NRdA_collect_reg_n_0_[12]\,
      S(0) => \NRdA_collect_reg_n_0_[11]\
    );
\NRdA_collect_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[19]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[19]\
    );
\NRdA_collect_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[20]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[20]\
    );
\NRdA_collect_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[21]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[21]\
    );
\NRdA_collect_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[22]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[22]\
    );
\NRdA_collect_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[23]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[23]\
    );
\NRdA_collect_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[24]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[24]\
    );
\NRdA_collect_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[25]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[25]\
    );
\NRdA_collect_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[26]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[26]\
    );
\NRdA_collect_reg[26]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \NRdA_collect_reg[18]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \NRdA_collect_reg[26]_i_2_n_0\,
      CO(6) => \NRdA_collect_reg[26]_i_2_n_1\,
      CO(5) => \NRdA_collect_reg[26]_i_2_n_2\,
      CO(4) => \NRdA_collect_reg[26]_i_2_n_3\,
      CO(3) => \NRdA_collect_reg[26]_i_2_n_4\,
      CO(2) => \NRdA_collect_reg[26]_i_2_n_5\,
      CO(1) => \NRdA_collect_reg[26]_i_2_n_6\,
      CO(0) => \NRdA_collect_reg[26]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => plusOp(26 downto 19),
      S(7) => \NRdA_collect_reg_n_0_[26]\,
      S(6) => \NRdA_collect_reg_n_0_[25]\,
      S(5) => \NRdA_collect_reg_n_0_[24]\,
      S(4) => \NRdA_collect_reg_n_0_[23]\,
      S(3) => \NRdA_collect_reg_n_0_[22]\,
      S(2) => \NRdA_collect_reg_n_0_[21]\,
      S(1) => \NRdA_collect_reg_n_0_[20]\,
      S(0) => \NRdA_collect_reg_n_0_[19]\
    );
\NRdA_collect_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[27]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[27]\
    );
\NRdA_collect_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[28]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[28]\
    );
\NRdA_collect_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[29]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[29]\
    );
\NRdA_collect_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[30]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[30]\
    );
\NRdA_collect_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[31]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[31]\
    );
\NRdA_collect_reg[31]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \NRdA_collect_reg[26]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_NRdA_collect_reg[31]_i_2_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \NRdA_collect_reg[31]_i_2_n_4\,
      CO(2) => \NRdA_collect_reg[31]_i_2_n_5\,
      CO(1) => \NRdA_collect_reg[31]_i_2_n_6\,
      CO(0) => \NRdA_collect_reg[31]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 5) => \NLW_NRdA_collect_reg[31]_i_2_O_UNCONNECTED\(7 downto 5),
      O(4 downto 0) => plusOp(31 downto 27),
      S(7 downto 5) => B"000",
      S(4) => \NRdA_collect_reg_n_0_[31]\,
      S(3) => \NRdA_collect_reg_n_0_[30]\,
      S(2) => \NRdA_collect_reg_n_0_[29]\,
      S(1) => \NRdA_collect_reg_n_0_[28]\,
      S(0) => \NRdA_collect_reg_n_0_[27]\
    );
\NRdA_collect_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[4]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[4]\
    );
\NRdA_collect_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[5]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[5]\
    );
\NRdA_collect_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[6]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[6]\
    );
\NRdA_collect_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[7]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[7]\
    );
\NRdA_collect_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[8]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[8]\
    );
\NRdA_collect_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdA_collect[9]_i_1_n_0\,
      Q => \NRdA_collect_reg_n_0_[9]\
    );
\NRdA_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[10]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(6)
    );
\NRdA_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[11]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(7)
    );
\NRdA_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[12]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(8)
    );
\NRdA_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[13]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(9)
    );
\NRdA_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[14]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(10)
    );
\NRdA_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[15]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(11)
    );
\NRdA_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[16]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(12)
    );
\NRdA_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[17]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(13)
    );
\NRdA_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[18]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(14)
    );
\NRdA_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[19]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(15)
    );
\NRdA_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[20]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(16)
    );
\NRdA_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[21]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(17)
    );
\NRdA_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[22]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(18)
    );
\NRdA_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[23]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(19)
    );
\NRdA_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[24]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(20)
    );
\NRdA_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[25]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(21)
    );
\NRdA_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[26]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(22)
    );
\NRdA_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[27]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(23)
    );
\NRdA_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[28]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(24)
    );
\NRdA_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[29]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(25)
    );
\NRdA_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[30]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(26)
    );
\NRdA_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[31]_i_2_n_0\,
      Q => \NRdA_reg[31]_0\(27)
    );
\NRdA_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[4]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(0)
    );
\NRdA_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[5]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(1)
    );
\NRdA_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[6]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(2)
    );
\NRdA_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[7]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(3)
    );
\NRdA_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[8]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(4)
    );
\NRdA_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdA[9]_i_1_n_0\,
      Q => \NRdA_reg[31]_0\(5)
    );
\NRdB[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[10]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[10]_i_2_n_8\,
      O => \NRdB[10]_i_1_n_0\
    );
\NRdB[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[11]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[18]_i_2_n_15\,
      O => \NRdB[11]_i_1_n_0\
    );
\NRdB[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[12]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[18]_i_2_n_14\,
      O => \NRdB[12]_i_1_n_0\
    );
\NRdB[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[13]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[18]_i_2_n_13\,
      O => \NRdB[13]_i_1_n_0\
    );
\NRdB[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[14]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[18]_i_2_n_12\,
      O => \NRdB[14]_i_1_n_0\
    );
\NRdB[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[15]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[18]_i_2_n_11\,
      O => \NRdB[15]_i_1_n_0\
    );
\NRdB[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[16]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[18]_i_2_n_10\,
      O => \NRdB[16]_i_1_n_0\
    );
\NRdB[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[17]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[18]_i_2_n_9\,
      O => \NRdB[17]_i_1_n_0\
    );
\NRdB[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[18]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[18]_i_2_n_8\,
      O => \NRdB[18]_i_1_n_0\
    );
\NRdB[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[19]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[26]_i_2_n_15\,
      O => \NRdB[19]_i_1_n_0\
    );
\NRdB[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[20]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[26]_i_2_n_14\,
      O => \NRdB[20]_i_1_n_0\
    );
\NRdB[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[21]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[26]_i_2_n_13\,
      O => \NRdB[21]_i_1_n_0\
    );
\NRdB[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[22]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[26]_i_2_n_12\,
      O => \NRdB[22]_i_1_n_0\
    );
\NRdB[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[23]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[26]_i_2_n_11\,
      O => \NRdB[23]_i_1_n_0\
    );
\NRdB[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[24]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[26]_i_2_n_10\,
      O => \NRdB[24]_i_1_n_0\
    );
\NRdB[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[25]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[26]_i_2_n_9\,
      O => \NRdB[25]_i_1_n_0\
    );
\NRdB[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[26]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[26]_i_2_n_8\,
      O => \NRdB[26]_i_1_n_0\
    );
\NRdB[27]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[27]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[31]_i_2_n_15\,
      O => \NRdB[27]_i_1_n_0\
    );
\NRdB[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[28]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[31]_i_2_n_14\,
      O => \NRdB[28]_i_1_n_0\
    );
\NRdB[29]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[29]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[31]_i_2_n_13\,
      O => \NRdB[29]_i_1_n_0\
    );
\NRdB[30]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[30]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[31]_i_2_n_12\,
      O => \NRdB[30]_i_1_n_0\
    );
\NRdB[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[31]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[31]_i_2_n_11\,
      O => \NRdB[31]_i_1_n_0\
    );
\NRdB[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[4]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[10]_i_2_n_14\,
      O => \NRdB[4]_i_1_n_0\
    );
\NRdB[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[5]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[10]_i_2_n_13\,
      O => \NRdB[5]_i_1_n_0\
    );
\NRdB[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[6]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[10]_i_2_n_12\,
      O => \NRdB[6]_i_1_n_0\
    );
\NRdB[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[7]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[10]_i_2_n_11\,
      O => \NRdB[7]_i_1_n_0\
    );
\NRdB[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[8]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[10]_i_2_n_10\,
      O => \NRdB[8]_i_1_n_0\
    );
\NRdB[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[9]\,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => \^rdmutex_reg[1]_0\(1),
      I4 => \NRdB_collect_reg[10]_i_2_n_9\,
      O => \NRdB[9]_i_1_n_0\
    );
\NRdB_collect[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[10]_i_2_n_8\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[10]\,
      I5 => NRdA,
      O => \NRdB_collect[10]_i_1_n_0\
    );
\NRdB_collect[10]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \NRdB_collect_reg_n_0_[4]\,
      O => \NRdB_collect[10]_i_3_n_0\
    );
\NRdB_collect[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[18]_i_2_n_15\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[11]\,
      I5 => NRdA,
      O => \NRdB_collect[11]_i_1_n_0\
    );
\NRdB_collect[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[18]_i_2_n_14\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[12]\,
      I5 => NRdA,
      O => \NRdB_collect[12]_i_1_n_0\
    );
\NRdB_collect[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[18]_i_2_n_13\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[13]\,
      I5 => NRdA,
      O => \NRdB_collect[13]_i_1_n_0\
    );
\NRdB_collect[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[18]_i_2_n_12\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[14]\,
      I5 => NRdA,
      O => \NRdB_collect[14]_i_1_n_0\
    );
\NRdB_collect[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[18]_i_2_n_11\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[15]\,
      I5 => NRdA,
      O => \NRdB_collect[15]_i_1_n_0\
    );
\NRdB_collect[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[18]_i_2_n_10\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[16]\,
      I5 => NRdA,
      O => \NRdB_collect[16]_i_1_n_0\
    );
\NRdB_collect[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[18]_i_2_n_9\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[17]\,
      I5 => NRdA,
      O => \NRdB_collect[17]_i_1_n_0\
    );
\NRdB_collect[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[18]_i_2_n_8\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[18]\,
      I5 => NRdA,
      O => \NRdB_collect[18]_i_1_n_0\
    );
\NRdB_collect[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[26]_i_2_n_15\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[19]\,
      I5 => NRdA,
      O => \NRdB_collect[19]_i_1_n_0\
    );
\NRdB_collect[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[26]_i_2_n_14\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[20]\,
      I5 => NRdA,
      O => \NRdB_collect[20]_i_1_n_0\
    );
\NRdB_collect[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[26]_i_2_n_13\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[21]\,
      I5 => NRdA,
      O => \NRdB_collect[21]_i_1_n_0\
    );
\NRdB_collect[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[26]_i_2_n_12\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[22]\,
      I5 => NRdA,
      O => \NRdB_collect[22]_i_1_n_0\
    );
\NRdB_collect[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[26]_i_2_n_11\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[23]\,
      I5 => NRdA,
      O => \NRdB_collect[23]_i_1_n_0\
    );
\NRdB_collect[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[26]_i_2_n_10\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[24]\,
      I5 => NRdA,
      O => \NRdB_collect[24]_i_1_n_0\
    );
\NRdB_collect[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[26]_i_2_n_9\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[25]\,
      I5 => NRdA,
      O => \NRdB_collect[25]_i_1_n_0\
    );
\NRdB_collect[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[26]_i_2_n_8\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[26]\,
      I5 => NRdA,
      O => \NRdB_collect[26]_i_1_n_0\
    );
\NRdB_collect[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[31]_i_2_n_15\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[27]\,
      I5 => NRdA,
      O => \NRdB_collect[27]_i_1_n_0\
    );
\NRdB_collect[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[31]_i_2_n_14\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[28]\,
      I5 => NRdA,
      O => \NRdB_collect[28]_i_1_n_0\
    );
\NRdB_collect[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[31]_i_2_n_13\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[29]\,
      I5 => NRdA,
      O => \NRdB_collect[29]_i_1_n_0\
    );
\NRdB_collect[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[31]_i_2_n_12\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[30]\,
      I5 => NRdA,
      O => \NRdB_collect[30]_i_1_n_0\
    );
\NRdB_collect[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[31]_i_2_n_11\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[31]\,
      I5 => NRdA,
      O => \NRdB_collect[31]_i_1_n_0\
    );
\NRdB_collect[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[10]_i_2_n_14\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[4]\,
      I5 => NRdA,
      O => \NRdB_collect[4]_i_1_n_0\
    );
\NRdB_collect[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[10]_i_2_n_13\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[5]\,
      I5 => NRdA,
      O => \NRdB_collect[5]_i_1_n_0\
    );
\NRdB_collect[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[10]_i_2_n_12\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[6]\,
      I5 => NRdA,
      O => \NRdB_collect[6]_i_1_n_0\
    );
\NRdB_collect[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[10]_i_2_n_11\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[7]\,
      I5 => NRdA,
      O => \NRdB_collect[7]_i_1_n_0\
    );
\NRdB_collect[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[10]_i_2_n_10\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[8]\,
      I5 => NRdA,
      O => \NRdB_collect[8]_i_1_n_0\
    );
\NRdB_collect[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NRdB_collect_reg[10]_i_2_n_9\,
      I1 => \^rdmutex_reg[1]_0\(1),
      I2 => \^rdmutex_reg[1]_0\(0),
      I3 => strbRdlock_mclk_reg_n_0,
      I4 => \NRdB_collect_reg_n_0_[9]\,
      I5 => NRdA,
      O => \NRdB_collect[9]_i_1_n_0\
    );
\NRdB_collect_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[10]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[10]\
    );
\NRdB_collect_reg[10]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \NRdB_collect_reg[10]_i_2_n_0\,
      CO(6) => \NRdB_collect_reg[10]_i_2_n_1\,
      CO(5) => \NRdB_collect_reg[10]_i_2_n_2\,
      CO(4) => \NRdB_collect_reg[10]_i_2_n_3\,
      CO(3) => \NRdB_collect_reg[10]_i_2_n_4\,
      CO(2) => \NRdB_collect_reg[10]_i_2_n_5\,
      CO(1) => \NRdB_collect_reg[10]_i_2_n_6\,
      CO(0) => \NRdB_collect_reg[10]_i_2_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \NRdB_collect_reg_n_0_[4]\,
      DI(0) => '0',
      O(7) => \NRdB_collect_reg[10]_i_2_n_8\,
      O(6) => \NRdB_collect_reg[10]_i_2_n_9\,
      O(5) => \NRdB_collect_reg[10]_i_2_n_10\,
      O(4) => \NRdB_collect_reg[10]_i_2_n_11\,
      O(3) => \NRdB_collect_reg[10]_i_2_n_12\,
      O(2) => \NRdB_collect_reg[10]_i_2_n_13\,
      O(1) => \NRdB_collect_reg[10]_i_2_n_14\,
      O(0) => \NLW_NRdB_collect_reg[10]_i_2_O_UNCONNECTED\(0),
      S(7) => \NRdB_collect_reg_n_0_[10]\,
      S(6) => \NRdB_collect_reg_n_0_[9]\,
      S(5) => \NRdB_collect_reg_n_0_[8]\,
      S(4) => \NRdB_collect_reg_n_0_[7]\,
      S(3) => \NRdB_collect_reg_n_0_[6]\,
      S(2) => \NRdB_collect_reg_n_0_[5]\,
      S(1) => \NRdB_collect[10]_i_3_n_0\,
      S(0) => '0'
    );
\NRdB_collect_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[11]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[11]\
    );
\NRdB_collect_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[12]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[12]\
    );
\NRdB_collect_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[13]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[13]\
    );
\NRdB_collect_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[14]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[14]\
    );
\NRdB_collect_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[15]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[15]\
    );
\NRdB_collect_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[16]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[16]\
    );
\NRdB_collect_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[17]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[17]\
    );
\NRdB_collect_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[18]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[18]\
    );
\NRdB_collect_reg[18]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \NRdB_collect_reg[10]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \NRdB_collect_reg[18]_i_2_n_0\,
      CO(6) => \NRdB_collect_reg[18]_i_2_n_1\,
      CO(5) => \NRdB_collect_reg[18]_i_2_n_2\,
      CO(4) => \NRdB_collect_reg[18]_i_2_n_3\,
      CO(3) => \NRdB_collect_reg[18]_i_2_n_4\,
      CO(2) => \NRdB_collect_reg[18]_i_2_n_5\,
      CO(1) => \NRdB_collect_reg[18]_i_2_n_6\,
      CO(0) => \NRdB_collect_reg[18]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NRdB_collect_reg[18]_i_2_n_8\,
      O(6) => \NRdB_collect_reg[18]_i_2_n_9\,
      O(5) => \NRdB_collect_reg[18]_i_2_n_10\,
      O(4) => \NRdB_collect_reg[18]_i_2_n_11\,
      O(3) => \NRdB_collect_reg[18]_i_2_n_12\,
      O(2) => \NRdB_collect_reg[18]_i_2_n_13\,
      O(1) => \NRdB_collect_reg[18]_i_2_n_14\,
      O(0) => \NRdB_collect_reg[18]_i_2_n_15\,
      S(7) => \NRdB_collect_reg_n_0_[18]\,
      S(6) => \NRdB_collect_reg_n_0_[17]\,
      S(5) => \NRdB_collect_reg_n_0_[16]\,
      S(4) => \NRdB_collect_reg_n_0_[15]\,
      S(3) => \NRdB_collect_reg_n_0_[14]\,
      S(2) => \NRdB_collect_reg_n_0_[13]\,
      S(1) => \NRdB_collect_reg_n_0_[12]\,
      S(0) => \NRdB_collect_reg_n_0_[11]\
    );
\NRdB_collect_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[19]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[19]\
    );
\NRdB_collect_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[20]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[20]\
    );
\NRdB_collect_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[21]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[21]\
    );
\NRdB_collect_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[22]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[22]\
    );
\NRdB_collect_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[23]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[23]\
    );
\NRdB_collect_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[24]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[24]\
    );
\NRdB_collect_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[25]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[25]\
    );
\NRdB_collect_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[26]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[26]\
    );
\NRdB_collect_reg[26]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \NRdB_collect_reg[18]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \NRdB_collect_reg[26]_i_2_n_0\,
      CO(6) => \NRdB_collect_reg[26]_i_2_n_1\,
      CO(5) => \NRdB_collect_reg[26]_i_2_n_2\,
      CO(4) => \NRdB_collect_reg[26]_i_2_n_3\,
      CO(3) => \NRdB_collect_reg[26]_i_2_n_4\,
      CO(2) => \NRdB_collect_reg[26]_i_2_n_5\,
      CO(1) => \NRdB_collect_reg[26]_i_2_n_6\,
      CO(0) => \NRdB_collect_reg[26]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NRdB_collect_reg[26]_i_2_n_8\,
      O(6) => \NRdB_collect_reg[26]_i_2_n_9\,
      O(5) => \NRdB_collect_reg[26]_i_2_n_10\,
      O(4) => \NRdB_collect_reg[26]_i_2_n_11\,
      O(3) => \NRdB_collect_reg[26]_i_2_n_12\,
      O(2) => \NRdB_collect_reg[26]_i_2_n_13\,
      O(1) => \NRdB_collect_reg[26]_i_2_n_14\,
      O(0) => \NRdB_collect_reg[26]_i_2_n_15\,
      S(7) => \NRdB_collect_reg_n_0_[26]\,
      S(6) => \NRdB_collect_reg_n_0_[25]\,
      S(5) => \NRdB_collect_reg_n_0_[24]\,
      S(4) => \NRdB_collect_reg_n_0_[23]\,
      S(3) => \NRdB_collect_reg_n_0_[22]\,
      S(2) => \NRdB_collect_reg_n_0_[21]\,
      S(1) => \NRdB_collect_reg_n_0_[20]\,
      S(0) => \NRdB_collect_reg_n_0_[19]\
    );
\NRdB_collect_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[27]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[27]\
    );
\NRdB_collect_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[28]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[28]\
    );
\NRdB_collect_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[29]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[29]\
    );
\NRdB_collect_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[30]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[30]\
    );
\NRdB_collect_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[31]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[31]\
    );
\NRdB_collect_reg[31]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \NRdB_collect_reg[26]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_NRdB_collect_reg[31]_i_2_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \NRdB_collect_reg[31]_i_2_n_4\,
      CO(2) => \NRdB_collect_reg[31]_i_2_n_5\,
      CO(1) => \NRdB_collect_reg[31]_i_2_n_6\,
      CO(0) => \NRdB_collect_reg[31]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 5) => \NLW_NRdB_collect_reg[31]_i_2_O_UNCONNECTED\(7 downto 5),
      O(4) => \NRdB_collect_reg[31]_i_2_n_11\,
      O(3) => \NRdB_collect_reg[31]_i_2_n_12\,
      O(2) => \NRdB_collect_reg[31]_i_2_n_13\,
      O(1) => \NRdB_collect_reg[31]_i_2_n_14\,
      O(0) => \NRdB_collect_reg[31]_i_2_n_15\,
      S(7 downto 5) => B"000",
      S(4) => \NRdB_collect_reg_n_0_[31]\,
      S(3) => \NRdB_collect_reg_n_0_[30]\,
      S(2) => \NRdB_collect_reg_n_0_[29]\,
      S(1) => \NRdB_collect_reg_n_0_[28]\,
      S(0) => \NRdB_collect_reg_n_0_[27]\
    );
\NRdB_collect_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[4]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[4]\
    );
\NRdB_collect_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[5]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[5]\
    );
\NRdB_collect_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[6]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[6]\
    );
\NRdB_collect_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[7]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[7]\
    );
\NRdB_collect_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[8]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[8]\
    );
\NRdB_collect_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NRdB_collect[9]_i_1_n_0\,
      Q => \NRdB_collect_reg_n_0_[9]\
    );
\NRdB_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[10]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(6)
    );
\NRdB_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[11]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(7)
    );
\NRdB_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[12]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(8)
    );
\NRdB_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[13]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(9)
    );
\NRdB_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[14]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(10)
    );
\NRdB_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[15]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(11)
    );
\NRdB_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[16]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(12)
    );
\NRdB_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[17]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(13)
    );
\NRdB_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[18]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(14)
    );
\NRdB_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[19]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(15)
    );
\NRdB_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[20]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(16)
    );
\NRdB_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[21]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(17)
    );
\NRdB_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[22]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(18)
    );
\NRdB_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[23]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(19)
    );
\NRdB_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[24]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(20)
    );
\NRdB_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[25]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(21)
    );
\NRdB_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[26]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(22)
    );
\NRdB_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[27]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(23)
    );
\NRdB_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[28]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(24)
    );
\NRdB_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[29]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(25)
    );
\NRdB_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[30]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(26)
    );
\NRdB_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[31]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(27)
    );
\NRdB_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[4]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(0)
    );
\NRdB_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[5]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(1)
    );
\NRdB_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[6]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(2)
    );
\NRdB_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[7]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(3)
    );
\NRdB_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[8]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(4)
    );
\NRdB_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NRdB[9]_i_1_n_0\,
      Q => \NRdB_reg[31]_0\(5)
    );
\NWrA[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[10]_i_2_n_8\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[10]\,
      O => \NWrA[10]_i_1_n_0\
    );
\NWrA[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[18]_i_2_n_15\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[11]\,
      O => \NWrA[11]_i_1_n_0\
    );
\NWrA[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[18]_i_2_n_14\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[12]\,
      O => \NWrA[12]_i_1_n_0\
    );
\NWrA[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[18]_i_2_n_13\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[13]\,
      O => \NWrA[13]_i_1_n_0\
    );
\NWrA[14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[18]_i_2_n_12\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[14]\,
      O => \NWrA[14]_i_1_n_0\
    );
\NWrA[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[18]_i_2_n_11\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[15]\,
      O => \NWrA[15]_i_1_n_0\
    );
\NWrA[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[18]_i_2_n_10\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[16]\,
      O => \NWrA[16]_i_1_n_0\
    );
\NWrA[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[18]_i_2_n_9\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[17]\,
      O => \NWrA[17]_i_1_n_0\
    );
\NWrA[18]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[18]_i_2_n_8\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[18]\,
      O => \NWrA[18]_i_1_n_0\
    );
\NWrA[19]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[26]_i_2_n_15\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[19]\,
      O => \NWrA[19]_i_1_n_0\
    );
\NWrA[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[26]_i_2_n_14\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[20]\,
      O => \NWrA[20]_i_1_n_0\
    );
\NWrA[21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[26]_i_2_n_13\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[21]\,
      O => \NWrA[21]_i_1_n_0\
    );
\NWrA[22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[26]_i_2_n_12\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[22]\,
      O => \NWrA[22]_i_1_n_0\
    );
\NWrA[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[26]_i_2_n_11\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[23]\,
      O => \NWrA[23]_i_1_n_0\
    );
\NWrA[24]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[26]_i_2_n_10\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[24]\,
      O => \NWrA[24]_i_1_n_0\
    );
\NWrA[25]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[26]_i_2_n_9\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[25]\,
      O => \NWrA[25]_i_1_n_0\
    );
\NWrA[26]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[26]_i_2_n_8\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[26]\,
      O => \NWrA[26]_i_1_n_0\
    );
\NWrA[27]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[31]_i_2_n_15\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[27]\,
      O => \NWrA[27]_i_1_n_0\
    );
\NWrA[28]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[31]_i_2_n_14\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[28]\,
      O => \NWrA[28]_i_1_n_0\
    );
\NWrA[29]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[31]_i_2_n_13\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[29]\,
      O => \NWrA[29]_i_1_n_0\
    );
\NWrA[30]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[31]_i_2_n_12\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[30]\,
      O => \NWrA[30]_i_1_n_0\
    );
\NWrA[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[31]_i_2_n_11\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[31]\,
      O => \NWrA[31]_i_1_n_0\
    );
\NWrA[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[10]_i_2_n_14\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[4]\,
      O => \NWrA[4]_i_1_n_0\
    );
\NWrA[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[10]_i_2_n_13\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[5]\,
      O => \NWrA[5]_i_1_n_0\
    );
\NWrA[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[10]_i_2_n_12\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[6]\,
      O => \NWrA[6]_i_1_n_0\
    );
\NWrA[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[10]_i_2_n_11\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[7]\,
      O => \NWrA[7]_i_1_n_0\
    );
\NWrA[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[10]_i_2_n_10\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[8]\,
      O => \NWrA[8]_i_1_n_0\
    );
\NWrA[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \NWrA_collect_reg[10]_i_2_n_9\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \^wrmutex_reg[1]_0\,
      I3 => \NWrA_collect_reg_n_0_[9]\,
      O => \NWrA[9]_i_1_n_0\
    );
\NWrA_collect[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[10]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[10]_i_2_n_8\,
      I4 => NRdA,
      O => \NWrA_collect[10]_i_1_n_0\
    );
\NWrA_collect[10]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[4]\,
      O => \NWrA_collect[10]_i_3_n_0\
    );
\NWrA_collect[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[11]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[18]_i_2_n_15\,
      I4 => NRdA,
      O => \NWrA_collect[11]_i_1_n_0\
    );
\NWrA_collect[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[12]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[18]_i_2_n_14\,
      I4 => NRdA,
      O => \NWrA_collect[12]_i_1_n_0\
    );
\NWrA_collect[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[13]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[18]_i_2_n_13\,
      I4 => NRdA,
      O => \NWrA_collect[13]_i_1_n_0\
    );
\NWrA_collect[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[14]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[18]_i_2_n_12\,
      I4 => NRdA,
      O => \NWrA_collect[14]_i_1_n_0\
    );
\NWrA_collect[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[15]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[18]_i_2_n_11\,
      I4 => NRdA,
      O => \NWrA_collect[15]_i_1_n_0\
    );
\NWrA_collect[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[16]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[18]_i_2_n_10\,
      I4 => NRdA,
      O => \NWrA_collect[16]_i_1_n_0\
    );
\NWrA_collect[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[17]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[18]_i_2_n_9\,
      I4 => NRdA,
      O => \NWrA_collect[17]_i_1_n_0\
    );
\NWrA_collect[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[18]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[18]_i_2_n_8\,
      I4 => NRdA,
      O => \NWrA_collect[18]_i_1_n_0\
    );
\NWrA_collect[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[19]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[26]_i_2_n_15\,
      I4 => NRdA,
      O => \NWrA_collect[19]_i_1_n_0\
    );
\NWrA_collect[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[20]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[26]_i_2_n_14\,
      I4 => NRdA,
      O => \NWrA_collect[20]_i_1_n_0\
    );
\NWrA_collect[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[21]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[26]_i_2_n_13\,
      I4 => NRdA,
      O => \NWrA_collect[21]_i_1_n_0\
    );
\NWrA_collect[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[22]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[26]_i_2_n_12\,
      I4 => NRdA,
      O => \NWrA_collect[22]_i_1_n_0\
    );
\NWrA_collect[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[23]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[26]_i_2_n_11\,
      I4 => NRdA,
      O => \NWrA_collect[23]_i_1_n_0\
    );
\NWrA_collect[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[24]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[26]_i_2_n_10\,
      I4 => NRdA,
      O => \NWrA_collect[24]_i_1_n_0\
    );
\NWrA_collect[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[25]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[26]_i_2_n_9\,
      I4 => NRdA,
      O => \NWrA_collect[25]_i_1_n_0\
    );
\NWrA_collect[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[26]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[26]_i_2_n_8\,
      I4 => NRdA,
      O => \NWrA_collect[26]_i_1_n_0\
    );
\NWrA_collect[27]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[27]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[31]_i_2_n_15\,
      I4 => NRdA,
      O => \NWrA_collect[27]_i_1_n_0\
    );
\NWrA_collect[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[28]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[31]_i_2_n_14\,
      I4 => NRdA,
      O => \NWrA_collect[28]_i_1_n_0\
    );
\NWrA_collect[29]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[29]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[31]_i_2_n_13\,
      I4 => NRdA,
      O => \NWrA_collect[29]_i_1_n_0\
    );
\NWrA_collect[30]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[30]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[31]_i_2_n_12\,
      I4 => NRdA,
      O => \NWrA_collect[30]_i_1_n_0\
    );
\NWrA_collect[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[31]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[31]_i_2_n_11\,
      I4 => NRdA,
      O => \NWrA_collect[31]_i_1_n_0\
    );
\NWrA_collect[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[4]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[10]_i_2_n_14\,
      I4 => NRdA,
      O => \NWrA_collect[4]_i_1_n_0\
    );
\NWrA_collect[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[5]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[10]_i_2_n_13\,
      I4 => NRdA,
      O => \NWrA_collect[5]_i_1_n_0\
    );
\NWrA_collect[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[6]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[10]_i_2_n_12\,
      I4 => NRdA,
      O => \NWrA_collect[6]_i_1_n_0\
    );
\NWrA_collect[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[7]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[10]_i_2_n_11\,
      I4 => NRdA,
      O => \NWrA_collect[7]_i_1_n_0\
    );
\NWrA_collect[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[8]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[10]_i_2_n_10\,
      I4 => NRdA,
      O => \NWrA_collect[8]_i_1_n_0\
    );
\NWrA_collect[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \NWrA_collect_reg_n_0_[9]\,
      I1 => \^wrmutex_reg[1]_0\,
      I2 => strbWrlock_mclk_reg_n_0,
      I3 => \NWrA_collect_reg[10]_i_2_n_9\,
      I4 => NRdA,
      O => \NWrA_collect[9]_i_1_n_0\
    );
\NWrA_collect_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[10]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[10]\
    );
\NWrA_collect_reg[10]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \NWrA_collect_reg[10]_i_2_n_0\,
      CO(6) => \NWrA_collect_reg[10]_i_2_n_1\,
      CO(5) => \NWrA_collect_reg[10]_i_2_n_2\,
      CO(4) => \NWrA_collect_reg[10]_i_2_n_3\,
      CO(3) => \NWrA_collect_reg[10]_i_2_n_4\,
      CO(2) => \NWrA_collect_reg[10]_i_2_n_5\,
      CO(1) => \NWrA_collect_reg[10]_i_2_n_6\,
      CO(0) => \NWrA_collect_reg[10]_i_2_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \NWrA_collect_reg_n_0_[4]\,
      DI(0) => '0',
      O(7) => \NWrA_collect_reg[10]_i_2_n_8\,
      O(6) => \NWrA_collect_reg[10]_i_2_n_9\,
      O(5) => \NWrA_collect_reg[10]_i_2_n_10\,
      O(4) => \NWrA_collect_reg[10]_i_2_n_11\,
      O(3) => \NWrA_collect_reg[10]_i_2_n_12\,
      O(2) => \NWrA_collect_reg[10]_i_2_n_13\,
      O(1) => \NWrA_collect_reg[10]_i_2_n_14\,
      O(0) => \NLW_NWrA_collect_reg[10]_i_2_O_UNCONNECTED\(0),
      S(7) => \NWrA_collect_reg_n_0_[10]\,
      S(6) => \NWrA_collect_reg_n_0_[9]\,
      S(5) => \NWrA_collect_reg_n_0_[8]\,
      S(4) => \NWrA_collect_reg_n_0_[7]\,
      S(3) => \NWrA_collect_reg_n_0_[6]\,
      S(2) => \NWrA_collect_reg_n_0_[5]\,
      S(1) => \NWrA_collect[10]_i_3_n_0\,
      S(0) => '0'
    );
\NWrA_collect_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[11]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[11]\
    );
\NWrA_collect_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[12]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[12]\
    );
\NWrA_collect_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[13]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[13]\
    );
\NWrA_collect_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[14]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[14]\
    );
\NWrA_collect_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[15]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[15]\
    );
\NWrA_collect_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[16]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[16]\
    );
\NWrA_collect_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[17]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[17]\
    );
\NWrA_collect_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[18]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[18]\
    );
\NWrA_collect_reg[18]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \NWrA_collect_reg[10]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \NWrA_collect_reg[18]_i_2_n_0\,
      CO(6) => \NWrA_collect_reg[18]_i_2_n_1\,
      CO(5) => \NWrA_collect_reg[18]_i_2_n_2\,
      CO(4) => \NWrA_collect_reg[18]_i_2_n_3\,
      CO(3) => \NWrA_collect_reg[18]_i_2_n_4\,
      CO(2) => \NWrA_collect_reg[18]_i_2_n_5\,
      CO(1) => \NWrA_collect_reg[18]_i_2_n_6\,
      CO(0) => \NWrA_collect_reg[18]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NWrA_collect_reg[18]_i_2_n_8\,
      O(6) => \NWrA_collect_reg[18]_i_2_n_9\,
      O(5) => \NWrA_collect_reg[18]_i_2_n_10\,
      O(4) => \NWrA_collect_reg[18]_i_2_n_11\,
      O(3) => \NWrA_collect_reg[18]_i_2_n_12\,
      O(2) => \NWrA_collect_reg[18]_i_2_n_13\,
      O(1) => \NWrA_collect_reg[18]_i_2_n_14\,
      O(0) => \NWrA_collect_reg[18]_i_2_n_15\,
      S(7) => \NWrA_collect_reg_n_0_[18]\,
      S(6) => \NWrA_collect_reg_n_0_[17]\,
      S(5) => \NWrA_collect_reg_n_0_[16]\,
      S(4) => \NWrA_collect_reg_n_0_[15]\,
      S(3) => \NWrA_collect_reg_n_0_[14]\,
      S(2) => \NWrA_collect_reg_n_0_[13]\,
      S(1) => \NWrA_collect_reg_n_0_[12]\,
      S(0) => \NWrA_collect_reg_n_0_[11]\
    );
\NWrA_collect_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[19]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[19]\
    );
\NWrA_collect_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[20]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[20]\
    );
\NWrA_collect_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[21]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[21]\
    );
\NWrA_collect_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[22]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[22]\
    );
\NWrA_collect_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[23]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[23]\
    );
\NWrA_collect_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[24]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[24]\
    );
\NWrA_collect_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[25]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[25]\
    );
\NWrA_collect_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[26]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[26]\
    );
\NWrA_collect_reg[26]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \NWrA_collect_reg[18]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \NWrA_collect_reg[26]_i_2_n_0\,
      CO(6) => \NWrA_collect_reg[26]_i_2_n_1\,
      CO(5) => \NWrA_collect_reg[26]_i_2_n_2\,
      CO(4) => \NWrA_collect_reg[26]_i_2_n_3\,
      CO(3) => \NWrA_collect_reg[26]_i_2_n_4\,
      CO(2) => \NWrA_collect_reg[26]_i_2_n_5\,
      CO(1) => \NWrA_collect_reg[26]_i_2_n_6\,
      CO(0) => \NWrA_collect_reg[26]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NWrA_collect_reg[26]_i_2_n_8\,
      O(6) => \NWrA_collect_reg[26]_i_2_n_9\,
      O(5) => \NWrA_collect_reg[26]_i_2_n_10\,
      O(4) => \NWrA_collect_reg[26]_i_2_n_11\,
      O(3) => \NWrA_collect_reg[26]_i_2_n_12\,
      O(2) => \NWrA_collect_reg[26]_i_2_n_13\,
      O(1) => \NWrA_collect_reg[26]_i_2_n_14\,
      O(0) => \NWrA_collect_reg[26]_i_2_n_15\,
      S(7) => \NWrA_collect_reg_n_0_[26]\,
      S(6) => \NWrA_collect_reg_n_0_[25]\,
      S(5) => \NWrA_collect_reg_n_0_[24]\,
      S(4) => \NWrA_collect_reg_n_0_[23]\,
      S(3) => \NWrA_collect_reg_n_0_[22]\,
      S(2) => \NWrA_collect_reg_n_0_[21]\,
      S(1) => \NWrA_collect_reg_n_0_[20]\,
      S(0) => \NWrA_collect_reg_n_0_[19]\
    );
\NWrA_collect_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[27]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[27]\
    );
\NWrA_collect_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[28]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[28]\
    );
\NWrA_collect_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[29]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[29]\
    );
\NWrA_collect_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[30]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[30]\
    );
\NWrA_collect_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[31]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[31]\
    );
\NWrA_collect_reg[31]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \NWrA_collect_reg[26]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_NWrA_collect_reg[31]_i_2_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \NWrA_collect_reg[31]_i_2_n_4\,
      CO(2) => \NWrA_collect_reg[31]_i_2_n_5\,
      CO(1) => \NWrA_collect_reg[31]_i_2_n_6\,
      CO(0) => \NWrA_collect_reg[31]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 5) => \NLW_NWrA_collect_reg[31]_i_2_O_UNCONNECTED\(7 downto 5),
      O(4) => \NWrA_collect_reg[31]_i_2_n_11\,
      O(3) => \NWrA_collect_reg[31]_i_2_n_12\,
      O(2) => \NWrA_collect_reg[31]_i_2_n_13\,
      O(1) => \NWrA_collect_reg[31]_i_2_n_14\,
      O(0) => \NWrA_collect_reg[31]_i_2_n_15\,
      S(7 downto 5) => B"000",
      S(4) => \NWrA_collect_reg_n_0_[31]\,
      S(3) => \NWrA_collect_reg_n_0_[30]\,
      S(2) => \NWrA_collect_reg_n_0_[29]\,
      S(1) => \NWrA_collect_reg_n_0_[28]\,
      S(0) => \NWrA_collect_reg_n_0_[27]\
    );
\NWrA_collect_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[4]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[4]\
    );
\NWrA_collect_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[5]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[5]\
    );
\NWrA_collect_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[6]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[6]\
    );
\NWrA_collect_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[7]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[7]\
    );
\NWrA_collect_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[8]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[8]\
    );
\NWrA_collect_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrA_collect[9]_i_1_n_0\,
      Q => \NWrA_collect_reg_n_0_[9]\
    );
\NWrA_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[10]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(6)
    );
\NWrA_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[11]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(7)
    );
\NWrA_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[12]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(8)
    );
\NWrA_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[13]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(9)
    );
\NWrA_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[14]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(10)
    );
\NWrA_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[15]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(11)
    );
\NWrA_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[16]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(12)
    );
\NWrA_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[17]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(13)
    );
\NWrA_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[18]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(14)
    );
\NWrA_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[19]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(15)
    );
\NWrA_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[20]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(16)
    );
\NWrA_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[21]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(17)
    );
\NWrA_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[22]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(18)
    );
\NWrA_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[23]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(19)
    );
\NWrA_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[24]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(20)
    );
\NWrA_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[25]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(21)
    );
\NWrA_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[26]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(22)
    );
\NWrA_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[27]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(23)
    );
\NWrA_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[28]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(24)
    );
\NWrA_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[29]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(25)
    );
\NWrA_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[30]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(26)
    );
\NWrA_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[31]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(27)
    );
\NWrA_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[4]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(0)
    );
\NWrA_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[5]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(1)
    );
\NWrA_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[6]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(2)
    );
\NWrA_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[7]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(3)
    );
\NWrA_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[8]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(4)
    );
\NWrA_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrA[9]_i_1_n_0\,
      Q => \NWrA_reg[31]_0\(5)
    );
\NWrB[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[10]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[10]_i_2_n_8\,
      O => \NWrB[10]_i_1_n_0\
    );
\NWrB[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[11]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[18]_i_2_n_15\,
      O => \NWrB[11]_i_1_n_0\
    );
\NWrB[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[12]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[18]_i_2_n_14\,
      O => \NWrB[12]_i_1_n_0\
    );
\NWrB[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[13]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[18]_i_2_n_13\,
      O => \NWrB[13]_i_1_n_0\
    );
\NWrB[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[14]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[18]_i_2_n_12\,
      O => \NWrB[14]_i_1_n_0\
    );
\NWrB[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[15]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[18]_i_2_n_11\,
      O => \NWrB[15]_i_1_n_0\
    );
\NWrB[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[16]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[18]_i_2_n_10\,
      O => \NWrB[16]_i_1_n_0\
    );
\NWrB[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[17]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[18]_i_2_n_9\,
      O => \NWrB[17]_i_1_n_0\
    );
\NWrB[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[18]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[18]_i_2_n_8\,
      O => \NWrB[18]_i_1_n_0\
    );
\NWrB[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[19]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[26]_i_2_n_15\,
      O => \NWrB[19]_i_1_n_0\
    );
\NWrB[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[20]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[26]_i_2_n_14\,
      O => \NWrB[20]_i_1_n_0\
    );
\NWrB[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[21]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[26]_i_2_n_13\,
      O => \NWrB[21]_i_1_n_0\
    );
\NWrB[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[22]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[26]_i_2_n_12\,
      O => \NWrB[22]_i_1_n_0\
    );
\NWrB[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[23]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[26]_i_2_n_11\,
      O => \NWrB[23]_i_1_n_0\
    );
\NWrB[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[24]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[26]_i_2_n_10\,
      O => \NWrB[24]_i_1_n_0\
    );
\NWrB[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[25]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[26]_i_2_n_9\,
      O => \NWrB[25]_i_1_n_0\
    );
\NWrB[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[26]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[26]_i_2_n_8\,
      O => \NWrB[26]_i_1_n_0\
    );
\NWrB[27]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[27]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[31]_i_2_n_15\,
      O => \NWrB[27]_i_1_n_0\
    );
\NWrB[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[28]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[31]_i_2_n_14\,
      O => \NWrB[28]_i_1_n_0\
    );
\NWrB[29]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[29]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[31]_i_2_n_13\,
      O => \NWrB[29]_i_1_n_0\
    );
\NWrB[30]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[30]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[31]_i_2_n_12\,
      O => \NWrB[30]_i_1_n_0\
    );
\NWrB[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[31]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[31]_i_2_n_11\,
      O => \NWrB[31]_i_1_n_0\
    );
\NWrB[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[4]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[10]_i_2_n_14\,
      O => \NWrB[4]_i_1_n_0\
    );
\NWrB[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[5]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[10]_i_2_n_13\,
      O => \NWrB[5]_i_1_n_0\
    );
\NWrB[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[6]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[10]_i_2_n_12\,
      O => \NWrB[6]_i_1_n_0\
    );
\NWrB[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[7]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[10]_i_2_n_11\,
      O => \NWrB[7]_i_1_n_0\
    );
\NWrB[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[8]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[10]_i_2_n_10\,
      O => \NWrB[8]_i_1_n_0\
    );
\NWrB[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAAA2AA"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[9]\,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => \wrmutex_reg_n_0_[1]\,
      I4 => \NWrB_collect_reg[10]_i_2_n_9\,
      O => \NWrB[9]_i_1_n_0\
    );
\NWrB_collect[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[10]_i_2_n_8\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[10]\,
      I5 => NRdA,
      O => \NWrB_collect[10]_i_1_n_0\
    );
\NWrB_collect[10]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \NWrB_collect_reg_n_0_[4]\,
      O => \NWrB_collect[10]_i_3_n_0\
    );
\NWrB_collect[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[18]_i_2_n_15\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[11]\,
      I5 => NRdA,
      O => \NWrB_collect[11]_i_1_n_0\
    );
\NWrB_collect[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[18]_i_2_n_14\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[12]\,
      I5 => NRdA,
      O => \NWrB_collect[12]_i_1_n_0\
    );
\NWrB_collect[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[18]_i_2_n_13\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[13]\,
      I5 => NRdA,
      O => \NWrB_collect[13]_i_1_n_0\
    );
\NWrB_collect[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[18]_i_2_n_12\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[14]\,
      I5 => NRdA,
      O => \NWrB_collect[14]_i_1_n_0\
    );
\NWrB_collect[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[18]_i_2_n_11\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[15]\,
      I5 => NRdA,
      O => \NWrB_collect[15]_i_1_n_0\
    );
\NWrB_collect[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[18]_i_2_n_10\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[16]\,
      I5 => NRdA,
      O => \NWrB_collect[16]_i_1_n_0\
    );
\NWrB_collect[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[18]_i_2_n_9\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[17]\,
      I5 => NRdA,
      O => \NWrB_collect[17]_i_1_n_0\
    );
\NWrB_collect[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[18]_i_2_n_8\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[18]\,
      I5 => NRdA,
      O => \NWrB_collect[18]_i_1_n_0\
    );
\NWrB_collect[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[26]_i_2_n_15\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[19]\,
      I5 => NRdA,
      O => \NWrB_collect[19]_i_1_n_0\
    );
\NWrB_collect[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[26]_i_2_n_14\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[20]\,
      I5 => NRdA,
      O => \NWrB_collect[20]_i_1_n_0\
    );
\NWrB_collect[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[26]_i_2_n_13\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[21]\,
      I5 => NRdA,
      O => \NWrB_collect[21]_i_1_n_0\
    );
\NWrB_collect[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[26]_i_2_n_12\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[22]\,
      I5 => NRdA,
      O => \NWrB_collect[22]_i_1_n_0\
    );
\NWrB_collect[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[26]_i_2_n_11\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[23]\,
      I5 => NRdA,
      O => \NWrB_collect[23]_i_1_n_0\
    );
\NWrB_collect[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[26]_i_2_n_10\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[24]\,
      I5 => NRdA,
      O => \NWrB_collect[24]_i_1_n_0\
    );
\NWrB_collect[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[26]_i_2_n_9\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[25]\,
      I5 => NRdA,
      O => \NWrB_collect[25]_i_1_n_0\
    );
\NWrB_collect[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[26]_i_2_n_8\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[26]\,
      I5 => NRdA,
      O => \NWrB_collect[26]_i_1_n_0\
    );
\NWrB_collect[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[31]_i_2_n_15\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[27]\,
      I5 => NRdA,
      O => \NWrB_collect[27]_i_1_n_0\
    );
\NWrB_collect[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[31]_i_2_n_14\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[28]\,
      I5 => NRdA,
      O => \NWrB_collect[28]_i_1_n_0\
    );
\NWrB_collect[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[31]_i_2_n_13\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[29]\,
      I5 => NRdA,
      O => \NWrB_collect[29]_i_1_n_0\
    );
\NWrB_collect[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[31]_i_2_n_12\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[30]\,
      I5 => NRdA,
      O => \NWrB_collect[30]_i_1_n_0\
    );
\NWrB_collect[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[31]_i_2_n_11\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[31]\,
      I5 => NRdA,
      O => \NWrB_collect[31]_i_1_n_0\
    );
\NWrB_collect[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[10]_i_2_n_14\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[4]\,
      I5 => NRdA,
      O => \NWrB_collect[4]_i_1_n_0\
    );
\NWrB_collect[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[10]_i_2_n_13\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[5]\,
      I5 => NRdA,
      O => \NWrB_collect[5]_i_1_n_0\
    );
\NWrB_collect[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[10]_i_2_n_12\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[6]\,
      I5 => NRdA,
      O => \NWrB_collect[6]_i_1_n_0\
    );
\NWrB_collect[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[10]_i_2_n_11\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[7]\,
      I5 => NRdA,
      O => \NWrB_collect[7]_i_1_n_0\
    );
\NWrB_collect[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[10]_i_2_n_10\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[8]\,
      I5 => NRdA,
      O => \NWrB_collect[8]_i_1_n_0\
    );
\NWrB_collect[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FBFF0800"
    )
        port map (
      I0 => \NWrB_collect_reg[10]_i_2_n_9\,
      I1 => \wrmutex_reg_n_0_[1]\,
      I2 => \wrmutex_reg_n_0_[0]\,
      I3 => strbWrlock_mclk_reg_n_0,
      I4 => \NWrB_collect_reg_n_0_[9]\,
      I5 => NRdA,
      O => \NWrB_collect[9]_i_1_n_0\
    );
\NWrB_collect_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[10]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[10]\
    );
\NWrB_collect_reg[10]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \NWrB_collect_reg[10]_i_2_n_0\,
      CO(6) => \NWrB_collect_reg[10]_i_2_n_1\,
      CO(5) => \NWrB_collect_reg[10]_i_2_n_2\,
      CO(4) => \NWrB_collect_reg[10]_i_2_n_3\,
      CO(3) => \NWrB_collect_reg[10]_i_2_n_4\,
      CO(2) => \NWrB_collect_reg[10]_i_2_n_5\,
      CO(1) => \NWrB_collect_reg[10]_i_2_n_6\,
      CO(0) => \NWrB_collect_reg[10]_i_2_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \NWrB_collect_reg_n_0_[4]\,
      DI(0) => '0',
      O(7) => \NWrB_collect_reg[10]_i_2_n_8\,
      O(6) => \NWrB_collect_reg[10]_i_2_n_9\,
      O(5) => \NWrB_collect_reg[10]_i_2_n_10\,
      O(4) => \NWrB_collect_reg[10]_i_2_n_11\,
      O(3) => \NWrB_collect_reg[10]_i_2_n_12\,
      O(2) => \NWrB_collect_reg[10]_i_2_n_13\,
      O(1) => \NWrB_collect_reg[10]_i_2_n_14\,
      O(0) => \NLW_NWrB_collect_reg[10]_i_2_O_UNCONNECTED\(0),
      S(7) => \NWrB_collect_reg_n_0_[10]\,
      S(6) => \NWrB_collect_reg_n_0_[9]\,
      S(5) => \NWrB_collect_reg_n_0_[8]\,
      S(4) => \NWrB_collect_reg_n_0_[7]\,
      S(3) => \NWrB_collect_reg_n_0_[6]\,
      S(2) => \NWrB_collect_reg_n_0_[5]\,
      S(1) => \NWrB_collect[10]_i_3_n_0\,
      S(0) => '0'
    );
\NWrB_collect_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[11]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[11]\
    );
\NWrB_collect_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[12]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[12]\
    );
\NWrB_collect_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[13]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[13]\
    );
\NWrB_collect_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[14]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[14]\
    );
\NWrB_collect_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[15]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[15]\
    );
\NWrB_collect_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[16]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[16]\
    );
\NWrB_collect_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[17]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[17]\
    );
\NWrB_collect_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[18]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[18]\
    );
\NWrB_collect_reg[18]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \NWrB_collect_reg[10]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \NWrB_collect_reg[18]_i_2_n_0\,
      CO(6) => \NWrB_collect_reg[18]_i_2_n_1\,
      CO(5) => \NWrB_collect_reg[18]_i_2_n_2\,
      CO(4) => \NWrB_collect_reg[18]_i_2_n_3\,
      CO(3) => \NWrB_collect_reg[18]_i_2_n_4\,
      CO(2) => \NWrB_collect_reg[18]_i_2_n_5\,
      CO(1) => \NWrB_collect_reg[18]_i_2_n_6\,
      CO(0) => \NWrB_collect_reg[18]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NWrB_collect_reg[18]_i_2_n_8\,
      O(6) => \NWrB_collect_reg[18]_i_2_n_9\,
      O(5) => \NWrB_collect_reg[18]_i_2_n_10\,
      O(4) => \NWrB_collect_reg[18]_i_2_n_11\,
      O(3) => \NWrB_collect_reg[18]_i_2_n_12\,
      O(2) => \NWrB_collect_reg[18]_i_2_n_13\,
      O(1) => \NWrB_collect_reg[18]_i_2_n_14\,
      O(0) => \NWrB_collect_reg[18]_i_2_n_15\,
      S(7) => \NWrB_collect_reg_n_0_[18]\,
      S(6) => \NWrB_collect_reg_n_0_[17]\,
      S(5) => \NWrB_collect_reg_n_0_[16]\,
      S(4) => \NWrB_collect_reg_n_0_[15]\,
      S(3) => \NWrB_collect_reg_n_0_[14]\,
      S(2) => \NWrB_collect_reg_n_0_[13]\,
      S(1) => \NWrB_collect_reg_n_0_[12]\,
      S(0) => \NWrB_collect_reg_n_0_[11]\
    );
\NWrB_collect_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[19]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[19]\
    );
\NWrB_collect_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[20]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[20]\
    );
\NWrB_collect_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[21]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[21]\
    );
\NWrB_collect_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[22]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[22]\
    );
\NWrB_collect_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[23]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[23]\
    );
\NWrB_collect_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[24]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[24]\
    );
\NWrB_collect_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[25]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[25]\
    );
\NWrB_collect_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[26]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[26]\
    );
\NWrB_collect_reg[26]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \NWrB_collect_reg[18]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \NWrB_collect_reg[26]_i_2_n_0\,
      CO(6) => \NWrB_collect_reg[26]_i_2_n_1\,
      CO(5) => \NWrB_collect_reg[26]_i_2_n_2\,
      CO(4) => \NWrB_collect_reg[26]_i_2_n_3\,
      CO(3) => \NWrB_collect_reg[26]_i_2_n_4\,
      CO(2) => \NWrB_collect_reg[26]_i_2_n_5\,
      CO(1) => \NWrB_collect_reg[26]_i_2_n_6\,
      CO(0) => \NWrB_collect_reg[26]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NWrB_collect_reg[26]_i_2_n_8\,
      O(6) => \NWrB_collect_reg[26]_i_2_n_9\,
      O(5) => \NWrB_collect_reg[26]_i_2_n_10\,
      O(4) => \NWrB_collect_reg[26]_i_2_n_11\,
      O(3) => \NWrB_collect_reg[26]_i_2_n_12\,
      O(2) => \NWrB_collect_reg[26]_i_2_n_13\,
      O(1) => \NWrB_collect_reg[26]_i_2_n_14\,
      O(0) => \NWrB_collect_reg[26]_i_2_n_15\,
      S(7) => \NWrB_collect_reg_n_0_[26]\,
      S(6) => \NWrB_collect_reg_n_0_[25]\,
      S(5) => \NWrB_collect_reg_n_0_[24]\,
      S(4) => \NWrB_collect_reg_n_0_[23]\,
      S(3) => \NWrB_collect_reg_n_0_[22]\,
      S(2) => \NWrB_collect_reg_n_0_[21]\,
      S(1) => \NWrB_collect_reg_n_0_[20]\,
      S(0) => \NWrB_collect_reg_n_0_[19]\
    );
\NWrB_collect_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[27]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[27]\
    );
\NWrB_collect_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[28]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[28]\
    );
\NWrB_collect_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[29]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[29]\
    );
\NWrB_collect_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[30]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[30]\
    );
\NWrB_collect_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[31]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[31]\
    );
\NWrB_collect_reg[31]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \NWrB_collect_reg[26]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_NWrB_collect_reg[31]_i_2_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \NWrB_collect_reg[31]_i_2_n_4\,
      CO(2) => \NWrB_collect_reg[31]_i_2_n_5\,
      CO(1) => \NWrB_collect_reg[31]_i_2_n_6\,
      CO(0) => \NWrB_collect_reg[31]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 5) => \NLW_NWrB_collect_reg[31]_i_2_O_UNCONNECTED\(7 downto 5),
      O(4) => \NWrB_collect_reg[31]_i_2_n_11\,
      O(3) => \NWrB_collect_reg[31]_i_2_n_12\,
      O(2) => \NWrB_collect_reg[31]_i_2_n_13\,
      O(1) => \NWrB_collect_reg[31]_i_2_n_14\,
      O(0) => \NWrB_collect_reg[31]_i_2_n_15\,
      S(7 downto 5) => B"000",
      S(4) => \NWrB_collect_reg_n_0_[31]\,
      S(3) => \NWrB_collect_reg_n_0_[30]\,
      S(2) => \NWrB_collect_reg_n_0_[29]\,
      S(1) => \NWrB_collect_reg_n_0_[28]\,
      S(0) => \NWrB_collect_reg_n_0_[27]\
    );
\NWrB_collect_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[4]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[4]\
    );
\NWrB_collect_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[5]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[5]\
    );
\NWrB_collect_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[6]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[6]\
    );
\NWrB_collect_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[7]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[7]\
    );
\NWrB_collect_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[8]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[8]\
    );
\NWrB_collect_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \NWrB_collect[9]_i_1_n_0\,
      Q => \NWrB_collect_reg_n_0_[9]\
    );
\NWrB_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[10]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(6)
    );
\NWrB_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[11]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(7)
    );
\NWrB_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[12]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(8)
    );
\NWrB_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[13]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(9)
    );
\NWrB_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[14]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(10)
    );
\NWrB_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[15]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(11)
    );
\NWrB_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[16]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(12)
    );
\NWrB_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[17]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(13)
    );
\NWrB_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[18]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(14)
    );
\NWrB_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[19]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(15)
    );
\NWrB_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[20]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(16)
    );
\NWrB_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[21]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(17)
    );
\NWrB_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[22]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(18)
    );
\NWrB_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[23]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(19)
    );
\NWrB_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[24]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(20)
    );
\NWrB_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[25]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(21)
    );
\NWrB_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[26]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(22)
    );
\NWrB_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[27]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(23)
    );
\NWrB_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[28]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(24)
    );
\NWrB_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[29]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(25)
    );
\NWrB_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[30]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(26)
    );
\NWrB_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[31]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(27)
    );
\NWrB_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[4]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(0)
    );
\NWrB_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[5]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(1)
    );
\NWrB_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[6]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(2)
    );
\NWrB_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[7]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(3)
    );
\NWrB_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[8]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(4)
    );
\NWrB_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => NRdA,
      CLR => AR(0),
      D => \NWrB[9]_i_1_n_0\,
      Q => \NWrB_reg[31]_0\(5)
    );
\aRowbufBEgrstr[8]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^wrmutex_reg[1]_1\,
      I1 => ddrAXI_wready,
      I2 => egrAXIS_tlast,
      O => ddrAXI_wready_0
    );
awdone_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FF20"
    )
        port map (
      I0 => ddrAXI_awready,
      I1 => \^wrmutex_reg[1]_1\,
      I2 => wrAAXI_awvalid,
      I3 => awdone_reg_n_0,
      I4 => ddrAXI_bready_sig,
      I5 => \^q\(0),
      O => awdone_i_1_n_0
    );
awdone_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => wdone_i_1_n_0,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => awdone_i_1_n_0,
      Q => awdone_reg_n_0
    );
\ddrAXI_araddr[10]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(2),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(2)
    );
\ddrAXI_araddr[11]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(3),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(3)
    );
\ddrAXI_araddr[12]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(4),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(4)
    );
\ddrAXI_araddr[13]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(5),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(5)
    );
\ddrAXI_araddr[14]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(6),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(6)
    );
\ddrAXI_araddr[15]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(7),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(7)
    );
\ddrAXI_araddr[16]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(8),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(8)
    );
\ddrAXI_araddr[17]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(9),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(9)
    );
\ddrAXI_araddr[18]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(10),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(10)
    );
\ddrAXI_araddr[19]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(11),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(11)
    );
\ddrAXI_araddr[20]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(12),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(12)
    );
\ddrAXI_araddr[21]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(13),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(13)
    );
\ddrAXI_araddr[22]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(14),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(14)
    );
\ddrAXI_araddr[23]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(15),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(15)
    );
\ddrAXI_araddr[24]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(16),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(16)
    );
\ddrAXI_araddr[25]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(17),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(17)
    );
\ddrAXI_araddr[26]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(18),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(18)
    );
\ddrAXI_araddr[27]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(19),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(19)
    );
\ddrAXI_araddr[28]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^rdmutex_reg[1]_0\(1),
      I1 => \^rdmutex_reg[1]_0\(0),
      O => ddrAXI_araddr(20)
    );
\ddrAXI_araddr[8]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(0),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(0)
    );
\ddrAXI_araddr[9]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rdAAXI_araddr(1),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => ddrAXI_araddr(1)
    );
\ddrAXI_awaddr[27]_INST_0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \wrmutex_reg_n_0_[1]\,
      I1 => \wrmutex_reg_n_0_[0]\,
      O => \^wrmutex_reg[1]_0\
    );
\ddrAXI_awaddr[28]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \wrmutex_reg_n_0_[1]\,
      I1 => \wrmutex_reg_n_0_[0]\,
      O => ddrAXI_awaddr(0)
    );
ddrAXI_bready_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000447F0000CCFF"
    )
        port map (
      I0 => ddrAXI_bready_sig_i_2_n_0,
      I1 => \^ddraxi_bready_sig_reg_0\,
      I2 => ddrAXI_bvalid,
      I3 => ddrAXI_bready_sig_i_3_n_0,
      I4 => ddrAXI_bready_sig,
      I5 => ddrAXI_bready_sig_i_4_n_0,
      O => ddrAXI_bready_sig_i_1_n_0
    );
ddrAXI_bready_sig_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFFFE"
    )
        port map (
      I0 => wtr(4),
      I1 => wtr(3),
      I2 => wtr(2),
      I3 => wtr(0),
      I4 => wtr(1),
      I5 => \wtr[4]_i_3_n_0\,
      O => ddrAXI_bready_sig_i_2_n_0
    );
ddrAXI_bready_sig_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00010000FFFFFFFF"
    )
        port map (
      I0 => wtr(3),
      I1 => wtr(1),
      I2 => wtr(0),
      I3 => wtr(2),
      I4 => wtr(4),
      I5 => D(0),
      O => ddrAXI_bready_sig_i_3_n_0
    );
ddrAXI_bready_sig_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => wtr(3),
      I1 => wtr(4),
      I2 => wtr(0),
      I3 => wtr(1),
      I4 => wtr(2),
      O => ddrAXI_bready_sig_i_4_n_0
    );
ddrAXI_bready_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => ddrAXI_bready_sig_i_1_n_0,
      Q => \^ddraxi_bready_sig_reg_0\
    );
ddrAXI_rready_INST_0_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => ddrAXI_rready_INST_0_i_2_n_0,
      I1 => ddrAXI_rready_INST_0_i_3_n_0,
      I2 => \ixRdidEgr__0\(4),
      I3 => ddrAXI_rready_INST_0_i_4_n_0,
      I4 => \ixRdidEgr__0\(3),
      I5 => ddrAXI_rready_INST_0_i_5_n_0,
      O => \^ixrdidegr_reg[4]_0\
    );
ddrAXI_rready_INST_0_i_10: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[11]_14\(0),
      I1 => \rdid_reg[10]_13\(0),
      I2 => \ixRdidEgr__0\(1),
      I3 => \rdid_reg[9]_12\(0),
      I4 => \ixRdidEgr__0\(0),
      I5 => \rdid_reg[8]_11\(0),
      O => ddrAXI_rready_INST_0_i_10_n_0
    );
ddrAXI_rready_INST_0_i_11: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[15]_18\(0),
      I1 => \rdid_reg[14]_17\(0),
      I2 => \ixRdidEgr__0\(1),
      I3 => \rdid_reg[13]_16\(0),
      I4 => \ixRdidEgr__0\(0),
      I5 => \rdid_reg[12]_15\(0),
      O => ddrAXI_rready_INST_0_i_11_n_0
    );
ddrAXI_rready_INST_0_i_12: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[3]_6\(0),
      I1 => \rdid_reg[2]_5\(0),
      I2 => \ixRdidEgr__0\(1),
      I3 => \rdid_reg[1]_4\(0),
      I4 => \ixRdidEgr__0\(0),
      I5 => \rdid_reg[0]_3\(0),
      O => ddrAXI_rready_INST_0_i_12_n_0
    );
ddrAXI_rready_INST_0_i_13: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[7]_10\(0),
      I1 => \rdid_reg[6]_9\(0),
      I2 => \ixRdidEgr__0\(1),
      I3 => \rdid_reg[5]_8\(0),
      I4 => \ixRdidEgr__0\(0),
      I5 => \rdid_reg[4]_7\(0),
      O => ddrAXI_rready_INST_0_i_13_n_0
    );
ddrAXI_rready_INST_0_i_2: unisim.vcomponents.MUXF7
     port map (
      I0 => ddrAXI_rready_INST_0_i_6_n_0,
      I1 => ddrAXI_rready_INST_0_i_7_n_0,
      O => ddrAXI_rready_INST_0_i_2_n_0,
      S => \ixRdidEgr__0\(2)
    );
ddrAXI_rready_INST_0_i_3: unisim.vcomponents.MUXF7
     port map (
      I0 => ddrAXI_rready_INST_0_i_8_n_0,
      I1 => ddrAXI_rready_INST_0_i_9_n_0,
      O => ddrAXI_rready_INST_0_i_3_n_0,
      S => \ixRdidEgr__0\(2)
    );
ddrAXI_rready_INST_0_i_4: unisim.vcomponents.MUXF7
     port map (
      I0 => ddrAXI_rready_INST_0_i_10_n_0,
      I1 => ddrAXI_rready_INST_0_i_11_n_0,
      O => ddrAXI_rready_INST_0_i_4_n_0,
      S => \ixRdidEgr__0\(2)
    );
ddrAXI_rready_INST_0_i_5: unisim.vcomponents.MUXF7
     port map (
      I0 => ddrAXI_rready_INST_0_i_12_n_0,
      I1 => ddrAXI_rready_INST_0_i_13_n_0,
      O => ddrAXI_rready_INST_0_i_5_n_0,
      S => \ixRdidEgr__0\(2)
    );
ddrAXI_rready_INST_0_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[27]_30\(0),
      I1 => \rdid_reg[26]_29\(0),
      I2 => \ixRdidEgr__0\(1),
      I3 => \rdid_reg[25]_28\(0),
      I4 => \ixRdidEgr__0\(0),
      I5 => \rdid_reg[24]_27\(0),
      O => ddrAXI_rready_INST_0_i_6_n_0
    );
ddrAXI_rready_INST_0_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[31]_34\(0),
      I1 => \rdid_reg[30]_33\(0),
      I2 => \ixRdidEgr__0\(1),
      I3 => \rdid_reg[29]_32\(0),
      I4 => \ixRdidEgr__0\(0),
      I5 => \rdid_reg[28]_31\(0),
      O => ddrAXI_rready_INST_0_i_7_n_0
    );
ddrAXI_rready_INST_0_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[19]_22\(0),
      I1 => \rdid_reg[18]_21\(0),
      I2 => \ixRdidEgr__0\(1),
      I3 => \rdid_reg[17]_20\(0),
      I4 => \ixRdidEgr__0\(0),
      I5 => \rdid_reg[16]_19\(0),
      O => ddrAXI_rready_INST_0_i_8_n_0
    );
ddrAXI_rready_INST_0_i_9: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[23]_26\(0),
      I1 => \rdid_reg[22]_25\(0),
      I2 => \ixRdidEgr__0\(1),
      I3 => \rdid_reg[21]_24\(0),
      I4 => \ixRdidEgr__0\(0),
      I5 => \rdid_reg[20]_23\(0),
      O => ddrAXI_rready_INST_0_i_9_n_0
    );
ddrAXI_wlast_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \wrmutex_reg_n_0_[1]\,
      I1 => wrAAXI_wlast,
      I2 => \wrmutex_reg_n_0_[0]\,
      O => ddrAXI_wlast
    );
ddrAXI_wvalid_INST_0_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \wrmutex_reg_n_0_[1]\,
      I1 => \wrmutex_reg_n_0_[0]\,
      O => \^wrmutex_reg[1]_1\
    );
\i[0]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^statestats\,
      I1 => i_reg(0),
      O => p_0_in(0)
    );
\i[0]_i_1__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^statestats\,
      I1 => \i_reg[0]_0\(0),
      O => stateStats_reg_0(0)
    );
\i[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \^statestats\,
      I1 => \i[10]_i_2_n_0\,
      I2 => i_reg(10),
      O => p_0_in(10)
    );
\i[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7FFFFFF"
    )
        port map (
      I0 => i_reg(8),
      I1 => i_reg(6),
      I2 => \i[9]_i_2__0_n_0\,
      I3 => i_reg(7),
      I4 => i_reg(9),
      O => \i[10]_i_2_n_0\
    );
\i[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \^statestats\,
      I1 => \i[13]_i_3_n_0\,
      I2 => i_reg(11),
      O => p_0_in(11)
    );
\i[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A208"
    )
        port map (
      I0 => \^statestats\,
      I1 => i_reg(11),
      I2 => \i[13]_i_3_n_0\,
      I3 => i_reg(12),
      O => p_0_in(12)
    );
\i[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => tkclk,
      I1 => \^statestats\,
      I2 => NRdA,
      O => \i[13]_i_1_n_0\
    );
\i[13]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BF400000"
    )
        port map (
      I0 => \i[13]_i_3_n_0\,
      I1 => i_reg(11),
      I2 => i_reg(12),
      I3 => i_reg(13),
      I4 => \^statestats\,
      O => \i[13]_i_2_n_0\
    );
\i[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFFFFFFF"
    )
        port map (
      I0 => i_reg(9),
      I1 => i_reg(7),
      I2 => \i[9]_i_2__0_n_0\,
      I3 => i_reg(6),
      I4 => i_reg(8),
      I5 => i_reg(10),
      O => \i[13]_i_3_n_0\
    );
\i[1]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => i_reg(1),
      I1 => i_reg(0),
      I2 => \^statestats\,
      O => \i[1]_i_1__5_n_0\
    );
\i[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \^statestats\,
      I1 => i_reg(0),
      I2 => i_reg(1),
      I3 => i_reg(2),
      O => p_0_in(2)
    );
\i[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \^statestats\,
      I1 => i_reg(1),
      I2 => i_reg(0),
      I3 => i_reg(2),
      I4 => i_reg(3),
      O => p_0_in(3)
    );
\i[4]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \^statestats\,
      I1 => i_reg(2),
      I2 => i_reg(0),
      I3 => i_reg(1),
      I4 => i_reg(3),
      I5 => i_reg(4),
      O => p_0_in(4)
    );
\i[5]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \^statestats\,
      I1 => \i[5]_i_2__1_n_0\,
      I2 => i_reg(5),
      O => p_0_in(5)
    );
\i[5]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => i_reg(3),
      I1 => i_reg(1),
      I2 => i_reg(0),
      I3 => i_reg(2),
      I4 => i_reg(4),
      O => \i[5]_i_2__1_n_0\
    );
\i[6]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \^statestats\,
      I1 => \i[9]_i_2__0_n_0\,
      I2 => i_reg(6),
      O => p_0_in(6)
    );
\i[7]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A20"
    )
        port map (
      I0 => \^statestats\,
      I1 => \i[9]_i_2__0_n_0\,
      I2 => i_reg(6),
      I3 => i_reg(7),
      O => p_0_in(7)
    );
\i[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A2AA0800"
    )
        port map (
      I0 => \^statestats\,
      I1 => i_reg(6),
      I2 => \i[9]_i_2__0_n_0\,
      I3 => i_reg(7),
      I4 => i_reg(8),
      O => p_0_in(8)
    );
\i[9]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2AAAAAA08000000"
    )
        port map (
      I0 => \^statestats\,
      I1 => i_reg(7),
      I2 => \i[9]_i_2__0_n_0\,
      I3 => i_reg(6),
      I4 => i_reg(8),
      I5 => i_reg(9),
      O => p_0_in(9)
    );
\i[9]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => i_reg(4),
      I1 => i_reg(2),
      I2 => i_reg(0),
      I3 => i_reg(1),
      I4 => i_reg(3),
      I5 => i_reg(5),
      O => \i[9]_i_2__0_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[13]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(0),
      Q => i_reg(0)
    );
\i_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[13]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(10),
      Q => i_reg(10)
    );
\i_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[13]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(11),
      Q => i_reg(11)
    );
\i_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[13]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(12),
      Q => i_reg(12)
    );
\i_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[13]_i_1_n_0\,
      CLR => AR(0),
      D => \i[13]_i_2_n_0\,
      Q => i_reg(13)
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[13]_i_1_n_0\,
      CLR => AR(0),
      D => \i[1]_i_1__5_n_0\,
      Q => i_reg(1)
    );
\i_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[13]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(2),
      Q => i_reg(2)
    );
\i_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[13]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(3),
      Q => i_reg(3)
    );
\i_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[13]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(4),
      Q => i_reg(4)
    );
\i_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[13]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(5),
      Q => i_reg(5)
    );
\i_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[13]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(6),
      Q => i_reg(6)
    );
\i_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[13]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(7),
      Q => i_reg(7)
    );
\i_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[13]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(8),
      Q => i_reg(8)
    );
\i_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[13]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(9),
      Q => i_reg(9)
    );
\ixRdidEgr[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I1 => \ixRdidEgr__0\(0),
      O => \ixRdidEgr[0]_i_1_n_0\
    );
\ixRdidEgr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \ixRdidEgr__0\(0),
      I1 => \ixRdidEgr__0\(1),
      I2 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      O => \ixRdidEgr[1]_i_1_n_0\
    );
\ixRdidEgr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1540"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I1 => \ixRdidEgr__0\(1),
      I2 => \ixRdidEgr__0\(0),
      I3 => \ixRdidEgr__0\(2),
      O => \ixRdidEgr[2]_i_1_n_0\
    );
\ixRdidEgr[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15554000"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I1 => \ixRdidEgr__0\(0),
      I2 => \ixRdidEgr__0\(1),
      I3 => \ixRdidEgr__0\(2),
      I4 => \ixRdidEgr__0\(3),
      O => \ixRdidEgr[3]_i_1_n_0\
    );
\ixRdidEgr[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I1 => \rdid_reg[1][0]_0\,
      O => ixRdidEgr
    );
\ixRdidEgr[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I1 => \ixRdidEgr__0\(2),
      I2 => \ixRdidEgr__0\(3),
      I3 => \ixRdidEgr__0\(0),
      I4 => \ixRdidEgr__0\(1),
      I5 => \ixRdidEgr__0\(4),
      O => \ixRdidEgr[4]_i_2_n_0\
    );
\ixRdidEgr_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => ixRdidEgr,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \ixRdidEgr[0]_i_1_n_0\,
      Q => \ixRdidEgr__0\(0)
    );
\ixRdidEgr_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => ixRdidEgr,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \ixRdidEgr[1]_i_1_n_0\,
      Q => \ixRdidEgr__0\(1)
    );
\ixRdidEgr_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => ixRdidEgr,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \ixRdidEgr[2]_i_1_n_0\,
      Q => \ixRdidEgr__0\(2)
    );
\ixRdidEgr_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => ixRdidEgr,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \ixRdidEgr[3]_i_1_n_0\,
      Q => \ixRdidEgr__0\(3)
    );
\ixRdidEgr_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => ixRdidEgr,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \ixRdidEgr[4]_i_2_n_0\,
      Q => \ixRdidEgr__0\(4)
    );
\ixRdid[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I1 => \ixRdid__0\(0),
      O => ixRdid(0)
    );
\ixRdid[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \ixRdid__0\(0),
      I1 => \ixRdid__0\(1),
      I2 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      O => ixRdid(1)
    );
\ixRdid[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1540"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I1 => \ixRdid__0\(1),
      I2 => \ixRdid__0\(0),
      I3 => \ixRdid__0\(2),
      O => \ixRdid[2]_i_1_n_0\
    );
\ixRdid[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15554000"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I1 => \ixRdid__0\(0),
      I2 => \ixRdid__0\(1),
      I3 => \ixRdid__0\(2),
      I4 => \ixRdid__0\(3),
      O => \ixRdid[3]_i_1_n_0\
    );
\ixRdid[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAEAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I1 => \ixRdid_reg[0]_0\(0),
      I2 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I3 => \^fsm_onehot_stateread_reg[2]_0\(0),
      I4 => ddrAXI_arready,
      I5 => \^rdmutex_reg[1]_1\,
      O => \ixRdid[4]_i_1_n_0\
    );
\ixRdid[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I1 => \ixRdid__0\(0),
      I2 => \ixRdid__0\(1),
      I3 => \ixRdid__0\(2),
      I4 => \ixRdid__0\(3),
      I5 => \ixRdid__0\(4),
      O => \ixRdid[4]_i_2_n_0\
    );
\ixRdid[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^rdmutex_reg[1]_0\(1),
      I1 => \^rdmutex_reg[1]_0\(0),
      O => \^rdmutex_reg[1]_1\
    );
\ixRdid_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ixRdid[4]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => ixRdid(0),
      Q => \ixRdid__0\(0)
    );
\ixRdid_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ixRdid[4]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => ixRdid(1),
      Q => \ixRdid__0\(1)
    );
\ixRdid_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ixRdid[4]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \ixRdid[2]_i_1_n_0\,
      Q => \ixRdid__0\(2)
    );
\ixRdid_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ixRdid[4]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \ixRdid[3]_i_1_n_0\,
      Q => \ixRdid__0\(3)
    );
\ixRdid_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ixRdid[4]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \ixRdid[4]_i_2_n_0\,
      Q => \ixRdid__0\(4)
    );
\probe[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^fsm_onehot_stateread_reg[2]_0\(0),
      I1 => \^rdmutex_reg[1]_0\(0),
      I2 => \^rdmutex_reg[1]_0\(1),
      O => probe(0)
    );
\probe[5]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^wrmutex_reg[1]_1\,
      O => probe(1)
    );
\rdid[0][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAFFFBAAAAAAAA"
    )
        port map (
      I0 => \rdid[0][0]_i_2_n_0\,
      I1 => \rdid[0][0]_i_3_n_0\,
      I2 => \ixRdidEgr__0\(4),
      I3 => \ixRdidEgr__0\(3),
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[0]_3\(0),
      O => \rdid[0][0]_i_1_n_0\
    );
\rdid[0][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \ixRdid__0\(1),
      I1 => \ixRdid__0\(0),
      I2 => \ixRdid__0\(2),
      I3 => \ixRdid__0\(3),
      I4 => \ixRdid__0\(4),
      I5 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      O => \rdid[0][0]_i_2_n_0\
    );
\rdid[0][0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \rdid_reg[1][0]_0\,
      I1 => \ixRdidEgr__0\(1),
      I2 => \ixRdidEgr__0\(0),
      I3 => \ixRdidEgr__0\(2),
      O => \rdid[0][0]_i_3_n_0\
    );
\rdid[10][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FFEFFF00FF00"
    )
        port map (
      I0 => \rdid[8][0]_i_2_n_0\,
      I1 => \ixRdidEgr__0\(0),
      I2 => \ixRdidEgr__0\(1),
      I3 => \rdid[10][0]_i_2_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[10]_13\(0),
      O => \rdid[10][0]_i_1_n_0\
    );
\rdid[10][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080000"
    )
        port map (
      I0 => \rdid[2][0]_i_4_n_0\,
      I1 => \ixRdid__0\(3),
      I2 => \ixRdid__0\(2),
      I3 => \ixRdid__0\(4),
      I4 => \ixRdid__0\(1),
      O => \rdid[10][0]_i_2_n_0\
    );
\rdid[11][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FFBFFF00FF00"
    )
        port map (
      I0 => \rdid[8][0]_i_2_n_0\,
      I1 => \ixRdidEgr__0\(1),
      I2 => \ixRdidEgr__0\(0),
      I3 => \rdid[11][0]_i_2_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[11]_14\(0),
      O => \rdid[11][0]_i_1_n_0\
    );
\rdid[11][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000004000000"
    )
        port map (
      I0 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      I1 => \ixRdid__0\(3),
      I2 => \ixRdid__0\(2),
      I3 => \ixRdid__0\(1),
      I4 => \ixRdid__0\(0),
      I5 => \ixRdid__0\(4),
      O => \rdid[11][0]_i_2_n_0\
    );
\rdid[12][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0030557500300030"
    )
        port map (
      I0 => \rdid[12][0]_i_2_n_0\,
      I1 => \ixRdid__0\(0),
      I2 => \ixRdid__0\(3),
      I3 => \rdid[12][0]_i_3_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[12]_15\(0),
      O => \rdid[12][0]_i_1_n_0\
    );
\rdid[12][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => \rdid_reg[1][0]_0\,
      I1 => \ixRdidEgr__0\(0),
      I2 => \ixRdidEgr__0\(3),
      I3 => \ixRdidEgr__0\(4),
      I4 => \ixRdidEgr__0\(1),
      I5 => \ixRdidEgr__0\(2),
      O => \rdid[12][0]_i_2_n_0\
    );
\rdid[12][0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFFFF"
    )
        port map (
      I0 => \rdmutex[1]_i_2_n_0\,
      I1 => \ixRdid__0\(4),
      I2 => \ixRdid__0\(1),
      I3 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I4 => \ixRdid__0\(2),
      O => \rdid[12][0]_i_3_n_0\
    );
\rdid[13][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FFBFFF00FF00"
    )
        port map (
      I0 => \rdid[1][0]_i_3_n_0\,
      I1 => \rdid[13][0]_i_2_n_0\,
      I2 => \rdid_reg[1][0]_0\,
      I3 => \rdid[13][0]_i_3_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[13]_16\(0),
      O => \rdid[13][0]_i_1_n_0\
    );
\rdid[13][0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ixRdidEgr__0\(3),
      I1 => \ixRdidEgr__0\(2),
      O => \rdid[13][0]_i_2_n_0\
    );
\rdid[13][0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \ixRdid__0\(0),
      I1 => \ixRdid__0\(3),
      I2 => \rdid[12][0]_i_3_n_0\,
      O => \rdid[13][0]_i_3_n_0\
    );
\rdid[14][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAFBAAAA"
    )
        port map (
      I0 => \rdid[14][0]_i_2_n_0\,
      I1 => \rdid_reg[1][0]_0\,
      I2 => \rdid[14][0]_i_3_n_0\,
      I3 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I4 => \rdid_reg[14]_17\(0),
      O => \rdid[14][0]_i_1_n_0\
    );
\rdid[14][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => \rdid[2][0]_i_4_n_0\,
      I1 => \ixRdid__0\(3),
      I2 => \ixRdid__0\(2),
      I3 => \ixRdid__0\(4),
      I4 => \ixRdid__0\(1),
      O => \rdid[14][0]_i_2_n_0\
    );
\rdid[14][0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF7FF"
    )
        port map (
      I0 => \ixRdidEgr__0\(2),
      I1 => \ixRdidEgr__0\(1),
      I2 => \ixRdidEgr__0\(4),
      I3 => \ixRdidEgr__0\(3),
      I4 => \ixRdidEgr__0\(0),
      O => \rdid[14][0]_i_3_n_0\
    );
\rdid[15][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAFFBFAAAAAAAA"
    )
        port map (
      I0 => \rdid[15][0]_i_2_n_0\,
      I1 => \rdid_reg[1][0]_0\,
      I2 => \rdid[15][0]_i_3_n_0\,
      I3 => \ixRdidEgr__0\(4),
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[15]_18\(0),
      O => \rdid[15][0]_i_1_n_0\
    );
\rdid[15][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040000000"
    )
        port map (
      I0 => \ixRdid__0\(4),
      I1 => \ixRdid__0\(0),
      I2 => \ixRdid__0\(1),
      I3 => \ixRdid__0\(2),
      I4 => \ixRdid__0\(3),
      I5 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      O => \rdid[15][0]_i_2_n_0\
    );
\rdid[15][0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \ixRdidEgr__0\(2),
      I1 => \ixRdidEgr__0\(3),
      I2 => \ixRdidEgr__0\(0),
      I3 => \ixRdidEgr__0\(1),
      O => \rdid[15][0]_i_3_n_0\
    );
\rdid[16][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010FFFF00100000"
    )
        port map (
      I0 => \ixRdid__0\(1),
      I1 => \ixRdid__0\(0),
      I2 => \ixRdid__0\(4),
      I3 => \rdid[16][0]_i_2_n_0\,
      I4 => \rdid[16][0]_i_3_n_0\,
      I5 => \rdid_reg[16]_19\(0),
      O => \rdid[16][0]_i_1_n_0\
    );
\rdid[16][0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \ixRdid__0\(2),
      I1 => \ixRdid__0\(3),
      I2 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      O => \rdid[16][0]_i_2_n_0\
    );
\rdid[16][0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFAAEA"
    )
        port map (
      I0 => \rdid[16][0]_i_4_n_0\,
      I1 => \rdid[0][0]_i_3_n_0\,
      I2 => \ixRdidEgr__0\(4),
      I3 => \ixRdidEgr__0\(3),
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      O => \rdid[16][0]_i_3_n_0\
    );
\rdid[16][0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \ixRdid__0\(0),
      I1 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I2 => \rdid[20][0]_i_3_n_0\,
      I3 => \ixRdid__0\(4),
      I4 => \ixRdid__0\(2),
      O => \rdid[16][0]_i_4_n_0\
    );
\rdid[17][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAFFFEAAAAAAAA"
    )
        port map (
      I0 => \rdid[17][0]_i_2_n_0\,
      I1 => \ixRdidEgr__0\(2),
      I2 => \ixRdidEgr__0\(3),
      I3 => \rdid[17][0]_i_3_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[17]_20\(0),
      O => \rdid[17][0]_i_1_n_0\
    );
\rdid[17][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \ixRdid__0\(4),
      I1 => \ixRdid__0\(0),
      I2 => \ixRdid__0\(1),
      I3 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      I4 => \ixRdid__0\(3),
      I5 => \ixRdid__0\(2),
      O => \rdid[17][0]_i_2_n_0\
    );
\rdid[17][0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => \rdid_reg[1][0]_0\,
      I1 => \ixRdidEgr__0\(1),
      I2 => \ixRdidEgr__0\(0),
      I3 => \ixRdidEgr__0\(4),
      O => \rdid[17][0]_i_3_n_0\
    );
\rdid[18][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2222F2FF22220200"
    )
        port map (
      I0 => \rdid[18][0]_i_2_n_0\,
      I1 => \rdid[16][0]_i_2_n_0\,
      I2 => \rdid[18][0]_i_3_n_0\,
      I3 => \rdid[2][0]_i_3_n_0\,
      I4 => \rdid[18][0]_i_4_n_0\,
      I5 => \rdid_reg[18]_21\(0),
      O => \rdid[18][0]_i_1_n_0\
    );
\rdid[18][0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \ixRdid__0\(4),
      I1 => \ixRdid__0\(1),
      I2 => \ixRdid__0\(0),
      O => \rdid[18][0]_i_2_n_0\
    );
\rdid[18][0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \ixRdidEgr__0\(3),
      I1 => \ixRdidEgr__0\(4),
      O => \rdid[18][0]_i_3_n_0\
    );
\rdid[18][0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAEAAAAAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I1 => \ixRdid__0\(4),
      I2 => \ixRdid__0\(3),
      I3 => \ixRdid__0\(0),
      I4 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I5 => \rdid[18][0]_i_5_n_0\,
      O => \rdid[18][0]_i_4_n_0\
    );
\rdid[18][0]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \rdmutex[1]_i_2_n_0\,
      I1 => \ixRdid__0\(1),
      I2 => \ixRdid__0\(2),
      O => \rdid[18][0]_i_5_n_0\
    );
\rdid[19][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAFFEFAAAAAAAA"
    )
        port map (
      I0 => \rdid[19][0]_i_2_n_0\,
      I1 => \ixRdidEgr__0\(2),
      I2 => \rdid[3][0]_i_3_n_0\,
      I3 => \rdid[19][0]_i_3_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[19]_22\(0),
      O => \rdid[19][0]_i_1_n_0\
    );
\rdid[19][0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \rdid[3][0]_i_5_n_0\,
      I1 => \ixRdid__0\(4),
      I2 => \ixRdid__0\(3),
      O => \rdid[19][0]_i_2_n_0\
    );
\rdid[19][0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \ixRdidEgr__0\(4),
      I1 => \ixRdidEgr__0\(3),
      I2 => \rdid_reg[1][0]_0\,
      O => \rdid[19][0]_i_3_n_0\
    );
\rdid[1][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FFEFFF00FF00"
    )
        port map (
      I0 => \rdid[1][0]_i_2_n_0\,
      I1 => \rdid[1][0]_i_3_n_0\,
      I2 => \rdid_reg[1][0]_0\,
      I3 => \rdid[1][0]_i_5_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[1]_4\(0),
      O => \rdid[1][0]_i_1_n_0\
    );
\rdid[1][0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \ixRdidEgr__0\(3),
      I1 => \ixRdidEgr__0\(2),
      O => \rdid[1][0]_i_2_n_0\
    );
\rdid[1][0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \ixRdidEgr__0\(4),
      I1 => \ixRdidEgr__0\(0),
      I2 => \ixRdidEgr__0\(1),
      O => \rdid[1][0]_i_3_n_0\
    );
\rdid[1][0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \ixRdid__0\(2),
      I1 => \ixRdid__0\(4),
      I2 => \ixRdid__0\(3),
      I3 => \ixRdid__0\(1),
      I4 => \ixRdid__0\(0),
      I5 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      O => \rdid[1][0]_i_5_n_0\
    );
\rdid[20][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0FBF0F0"
    )
        port map (
      I0 => \rdid[19][0]_i_3_n_0\,
      I1 => \rdid[4][0]_i_3_n_0\,
      I2 => \rdid[20][0]_i_2_n_0\,
      I3 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I4 => \rdid_reg[20]_23\(0),
      O => \rdid[20][0]_i_1_n_0\
    );
\rdid[20][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08000000"
    )
        port map (
      I0 => \rdid[20][0]_i_3_n_0\,
      I1 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I2 => \ixRdid__0\(0),
      I3 => \ixRdid__0\(2),
      I4 => \ixRdid__0\(4),
      O => \rdid[20][0]_i_2_n_0\
    );
\rdid[20][0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \ixRdid__0\(1),
      I1 => \ixRdid__0\(3),
      I2 => \rdmutex[1]_i_2_n_0\,
      O => \rdid[20][0]_i_3_n_0\
    );
\rdid[21][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FFEFFF00FF00"
    )
        port map (
      I0 => \rdid[17][0]_i_3_n_0\,
      I1 => \ixRdidEgr__0\(3),
      I2 => \ixRdidEgr__0\(2),
      I3 => \rdid[21][0]_i_2_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[21]_24\(0),
      O => \rdid[21][0]_i_1_n_0\
    );
\rdid[21][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \rdid[20][0]_i_3_n_0\,
      I1 => \ixRdid__0\(4),
      I2 => \ixRdid__0\(0),
      I3 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I4 => \ixRdid__0\(2),
      O => \rdid[21][0]_i_2_n_0\
    );
\rdid[22][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BABBAAAA"
    )
        port map (
      I0 => \rdid[22][0]_i_2_n_0\,
      I1 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I2 => \rdid[19][0]_i_3_n_0\,
      I3 => \rdid[6][0]_i_3_n_0\,
      I4 => \rdid_reg[22]_25\(0),
      O => \rdid[22][0]_i_1_n_0\
    );
\rdid[22][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \ixRdid__0\(3),
      I1 => \ixRdid__0\(4),
      I2 => \ixRdid__0\(1),
      I3 => \ixRdid__0\(0),
      I4 => \rdid[22][0]_i_3_n_0\,
      I5 => \rdmutex[1]_i_2_n_0\,
      O => \rdid[22][0]_i_2_n_0\
    );
\rdid[22][0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I1 => \ixRdid__0\(2),
      O => \rdid[22][0]_i_3_n_0\
    );
\rdid[23][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABBBBBBAAAAAAAA"
    )
        port map (
      I0 => \rdid[23][0]_i_2_n_0\,
      I1 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I2 => \ixRdidEgr__0\(3),
      I3 => \ixRdidEgr__0\(4),
      I4 => \rdid[23][0]_i_3_n_0\,
      I5 => \rdid_reg[23]_26\(0),
      O => \rdid[23][0]_i_1_n_0\
    );
\rdid[23][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => \ixRdid__0\(2),
      I1 => \ixRdid__0\(4),
      I2 => \ixRdid__0\(0),
      I3 => \ixRdid__0\(1),
      I4 => \ixRdid__0\(3),
      I5 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      O => \rdid[23][0]_i_2_n_0\
    );
\rdid[23][0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \rdid_reg[1][0]_0\,
      I1 => \ixRdidEgr__0\(2),
      I2 => \ixRdidEgr__0\(1),
      I3 => \ixRdidEgr__0\(0),
      O => \rdid[23][0]_i_3_n_0\
    );
\rdid[24][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FF7FFF00FF00"
    )
        port map (
      I0 => \ixRdidEgr__0\(3),
      I1 => \ixRdidEgr__0\(4),
      I2 => \rdid[0][0]_i_3_n_0\,
      I3 => \rdid[24][0]_i_2_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[24]_27\(0),
      O => \rdid[24][0]_i_1_n_0\
    );
\rdid[24][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \ixRdid__0\(3),
      I1 => \ixRdid__0\(4),
      I2 => \ixRdid__0\(2),
      I3 => \ixRdid__0\(0),
      I4 => \ixRdid__0\(1),
      I5 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      O => \rdid[24][0]_i_2_n_0\
    );
\rdid[25][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FFFBFF00FF00"
    )
        port map (
      I0 => \rdid[9][0]_i_3_n_0\,
      I1 => \ixRdidEgr__0\(4),
      I2 => \rdid[25][0]_i_2_n_0\,
      I3 => \rdid[25][0]_i_3_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[25]_28\(0),
      O => \rdid[25][0]_i_1_n_0\
    );
\rdid[25][0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \ixRdidEgr__0\(1),
      I1 => \ixRdidEgr__0\(0),
      O => \rdid[25][0]_i_2_n_0\
    );
\rdid[25][0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000080000"
    )
        port map (
      I0 => \ixRdid__0\(4),
      I1 => \ixRdid__0\(0),
      I2 => \ixRdid__0\(1),
      I3 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      I4 => \ixRdid__0\(3),
      I5 => \ixRdid__0\(2),
      O => \rdid[25][0]_i_3_n_0\
    );
\rdid[26][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABBBBBBBAAAAAAAA"
    )
        port map (
      I0 => \rdid[26][0]_i_2_n_0\,
      I1 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I2 => \ixRdidEgr__0\(3),
      I3 => \ixRdidEgr__0\(4),
      I4 => \rdid[2][0]_i_3_n_0\,
      I5 => \rdid_reg[26]_29\(0),
      O => \rdid[26][0]_i_1_n_0\
    );
\rdid[26][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \ixRdid__0\(0),
      I1 => \ixRdid__0\(1),
      I2 => \ixRdid__0\(4),
      I3 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      I4 => \ixRdid__0\(3),
      I5 => \ixRdid__0\(2),
      O => \rdid[26][0]_i_2_n_0\
    );
\rdid[27][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FF7FFF00FF00"
    )
        port map (
      I0 => \rdid[27][0]_i_2_n_0\,
      I1 => \rdid_reg[1][0]_0\,
      I2 => \rdid[27][0]_i_3_n_0\,
      I3 => \rdid[27][0]_i_4_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[27]_30\(0),
      O => \rdid[27][0]_i_1_n_0\
    );
\rdid[27][0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ixRdidEgr__0\(3),
      I1 => \ixRdidEgr__0\(4),
      O => \rdid[27][0]_i_2_n_0\
    );
\rdid[27][0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \ixRdidEgr__0\(0),
      I1 => \ixRdidEgr__0\(1),
      I2 => \ixRdidEgr__0\(2),
      O => \rdid[27][0]_i_3_n_0\
    );
\rdid[27][0]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \ixRdid__0\(4),
      I1 => \ixRdid__0\(3),
      I2 => \rdid[3][0]_i_5_n_0\,
      O => \rdid[27][0]_i_4_n_0\
    );
\rdid[28][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FF7FFF00FF00"
    )
        port map (
      I0 => \rdid[27][0]_i_2_n_0\,
      I1 => \rdid_reg[1][0]_0\,
      I2 => \rdid[4][0]_i_3_n_0\,
      I3 => \rdid[28][0]_i_2_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[28]_31\(0),
      O => \rdid[28][0]_i_1_n_0\
    );
\rdid[28][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \ixRdid__0\(0),
      I1 => \ixRdid__0\(2),
      I2 => \ixRdid__0\(4),
      I3 => \ixRdid__0\(1),
      I4 => \ixRdid__0\(3),
      I5 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      O => \rdid[28][0]_i_2_n_0\
    );
\rdid[29][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FFBFFF00FF00"
    )
        port map (
      I0 => \rdid[17][0]_i_3_n_0\,
      I1 => \ixRdidEgr__0\(3),
      I2 => \ixRdidEgr__0\(2),
      I3 => \rdid[29][0]_i_2_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[29]_32\(0),
      O => \rdid[29][0]_i_1_n_0\
    );
\rdid[29][0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \ixRdid__0\(4),
      I1 => \ixRdid__0\(3),
      I2 => \rdid[5][0]_i_3_n_0\,
      O => \rdid[29][0]_i_2_n_0\
    );
\rdid[2][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBABBBBAAAAAAAA"
    )
        port map (
      I0 => \rdid[2][0]_i_2_n_0\,
      I1 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I2 => \ixRdidEgr__0\(3),
      I3 => \ixRdidEgr__0\(4),
      I4 => \rdid[2][0]_i_3_n_0\,
      I5 => \rdid_reg[2]_5\(0),
      O => \rdid[2][0]_i_1_n_0\
    );
\rdid[2][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => \rdid[2][0]_i_4_n_0\,
      I1 => \ixRdid__0\(1),
      I2 => \ixRdid__0\(2),
      I3 => \ixRdid__0\(4),
      I4 => \ixRdid__0\(3),
      O => \rdid[2][0]_i_2_n_0\
    );
\rdid[2][0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \rdid_reg[1][0]_0\,
      I1 => \ixRdidEgr__0\(0),
      I2 => \ixRdidEgr__0\(1),
      I3 => \ixRdidEgr__0\(2),
      O => \rdid[2][0]_i_3_n_0\
    );
\rdid[2][0]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \ixRdid__0\(0),
      I1 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I2 => \rdmutex[1]_i_2_n_0\,
      O => \rdid[2][0]_i_4_n_0\
    );
\rdid[30][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FF7FFF00FF00"
    )
        port map (
      I0 => \rdid[27][0]_i_2_n_0\,
      I1 => \rdid[6][0]_i_3_n_0\,
      I2 => \rdid_reg[1][0]_0\,
      I3 => \rdid[30][0]_i_2_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[30]_33\(0),
      O => \rdid[30][0]_i_1_n_0\
    );
\rdid[30][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \rdid[2][0]_i_4_n_0\,
      I1 => \ixRdid__0\(3),
      I2 => \ixRdid__0\(2),
      I3 => \ixRdid__0\(4),
      I4 => \ixRdid__0\(1),
      O => \rdid[30][0]_i_2_n_0\
    );
\rdid[31][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FF7FFF00FF00"
    )
        port map (
      I0 => \ixRdidEgr__0\(3),
      I1 => \ixRdidEgr__0\(4),
      I2 => \rdid[23][0]_i_3_n_0\,
      I3 => \rdid[31][0]_i_2_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[31]_34\(0),
      O => \rdid[31][0]_i_1_n_0\
    );
\rdid[31][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080000000"
    )
        port map (
      I0 => \ixRdid__0\(2),
      I1 => \ixRdid__0\(4),
      I2 => \ixRdid__0\(1),
      I3 => \ixRdid__0\(3),
      I4 => \ixRdid__0\(0),
      I5 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      O => \rdid[31][0]_i_2_n_0\
    );
\rdid[3][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAFFEFAAAAAAAA"
    )
        port map (
      I0 => \rdid[3][0]_i_2_n_0\,
      I1 => \ixRdidEgr__0\(2),
      I2 => \rdid[3][0]_i_3_n_0\,
      I3 => \rdid[3][0]_i_4_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[3]_6\(0),
      O => \rdid[3][0]_i_1_n_0\
    );
\rdid[3][0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \ixRdid__0\(4),
      I1 => \ixRdid__0\(3),
      I2 => \rdid[3][0]_i_5_n_0\,
      O => \rdid[3][0]_i_2_n_0\
    );
\rdid[3][0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ixRdidEgr__0\(1),
      I1 => \ixRdidEgr__0\(0),
      O => \rdid[3][0]_i_3_n_0\
    );
\rdid[3][0]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \ixRdidEgr__0\(4),
      I1 => \ixRdidEgr__0\(3),
      I2 => \rdid_reg[1][0]_0\,
      O => \rdid[3][0]_i_4_n_0\
    );
\rdid[3][0]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF7FF"
    )
        port map (
      I0 => \ixRdid__0\(0),
      I1 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I2 => \ixRdid__0\(2),
      I3 => \ixRdid__0\(1),
      I4 => \rdmutex[1]_i_2_n_0\,
      O => \rdid[3][0]_i_5_n_0\
    );
\rdid[4][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BABBAAAA"
    )
        port map (
      I0 => \rdid[4][0]_i_2_n_0\,
      I1 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I2 => \rdid[3][0]_i_4_n_0\,
      I3 => \rdid[4][0]_i_3_n_0\,
      I4 => \rdid_reg[4]_7\(0),
      O => \rdid[4][0]_i_1_n_0\
    );
\rdid[4][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000080000"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I1 => \ixRdid__0\(2),
      I2 => \ixRdid__0\(0),
      I3 => \ixRdid__0\(1),
      I4 => \rdid[5][0]_i_2_n_0\,
      I5 => \rdmutex[1]_i_2_n_0\,
      O => \rdid[4][0]_i_2_n_0\
    );
\rdid[4][0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \ixRdidEgr__0\(0),
      I1 => \ixRdidEgr__0\(2),
      I2 => \ixRdidEgr__0\(1),
      O => \rdid[4][0]_i_3_n_0\
    );
\rdid[5][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2222222F22222220"
    )
        port map (
      I0 => \rdid[5][0]_i_2_n_0\,
      I1 => \rdid[5][0]_i_3_n_0\,
      I2 => \rdid[5][0]_i_4_n_0\,
      I3 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I4 => \rdid[5][0]_i_5_n_0\,
      I5 => \rdid_reg[5]_8\(0),
      O => \rdid[5][0]_i_1_n_0\
    );
\rdid[5][0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \ixRdid__0\(3),
      I1 => \ixRdid__0\(4),
      O => \rdid[5][0]_i_2_n_0\
    );
\rdid[5][0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBFFFFF"
    )
        port map (
      I0 => \rdmutex[1]_i_2_n_0\,
      I1 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I2 => \ixRdid__0\(2),
      I3 => \ixRdid__0\(1),
      I4 => \ixRdid__0\(0),
      O => \rdid[5][0]_i_3_n_0\
    );
\rdid[5][0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000800"
    )
        port map (
      I0 => \rdid_reg[1][0]_0\,
      I1 => \ixRdidEgr__0\(0),
      I2 => \ixRdidEgr__0\(1),
      I3 => \ixRdidEgr__0\(2),
      I4 => \ixRdidEgr__0\(3),
      I5 => \ixRdidEgr__0\(4),
      O => \rdid[5][0]_i_4_n_0\
    );
\rdid[5][0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \ixRdid__0\(1),
      I1 => \ixRdid__0\(4),
      I2 => \rdid[5][0]_i_6_n_0\,
      I3 => \ixRdid__0\(3),
      I4 => \ixRdid__0\(2),
      I5 => \rdmutex[1]_i_2_n_0\,
      O => \rdid[5][0]_i_5_n_0\
    );
\rdid[5][0]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I1 => \ixRdid__0\(0),
      O => \rdid[5][0]_i_6_n_0\
    );
\rdid[6][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BABBAAAA"
    )
        port map (
      I0 => \rdid[6][0]_i_2_n_0\,
      I1 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I2 => \rdid[3][0]_i_4_n_0\,
      I3 => \rdid[6][0]_i_3_n_0\,
      I4 => \rdid_reg[6]_9\(0),
      O => \rdid[6][0]_i_1_n_0\
    );
\rdid[6][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008000000"
    )
        port map (
      I0 => \rdid[5][0]_i_2_n_0\,
      I1 => \ixRdid__0\(1),
      I2 => \ixRdid__0\(0),
      I3 => \ixRdid__0\(2),
      I4 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I5 => \rdmutex[1]_i_2_n_0\,
      O => \rdid[6][0]_i_2_n_0\
    );
\rdid[6][0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \ixRdidEgr__0\(2),
      I1 => \ixRdidEgr__0\(1),
      I2 => \ixRdidEgr__0\(0),
      O => \rdid[6][0]_i_3_n_0\
    );
\rdid[7][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABBBBBBAAAAAAAA"
    )
        port map (
      I0 => \rdid[7][0]_i_2_n_0\,
      I1 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I2 => \rdid[3][0]_i_4_n_0\,
      I3 => \rdid[3][0]_i_3_n_0\,
      I4 => \ixRdidEgr__0\(2),
      I5 => \rdid_reg[7]_10\(0),
      O => \rdid[7][0]_i_1_n_0\
    );
\rdid[7][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => \ixRdid__0\(2),
      I1 => \ixRdid__0\(1),
      I2 => \ixRdid__0\(0),
      I3 => \ixRdid__0\(3),
      I4 => \ixRdid__0\(4),
      I5 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      O => \rdid[7][0]_i_2_n_0\
    );
\rdid[8][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FFFEFF00FF00"
    )
        port map (
      I0 => \rdid[8][0]_i_2_n_0\,
      I1 => \ixRdidEgr__0\(1),
      I2 => \ixRdidEgr__0\(0),
      I3 => \rdid[8][0]_i_3_n_0\,
      I4 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I5 => \rdid_reg[8]_11\(0),
      O => \rdid[8][0]_i_1_n_0\
    );
\rdid[8][0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFBF"
    )
        port map (
      I0 => \ixRdidEgr__0\(4),
      I1 => \rdid_reg[1][0]_0\,
      I2 => \ixRdidEgr__0\(3),
      I3 => \ixRdidEgr__0\(2),
      O => \rdid[8][0]_i_2_n_0\
    );
\rdid[8][0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \rdid[2][0]_i_4_n_0\,
      I1 => \ixRdid__0\(4),
      I2 => \ixRdid__0\(1),
      I3 => \ixRdid__0\(3),
      I4 => \ixRdid__0\(2),
      O => \rdid[8][0]_i_3_n_0\
    );
\rdid[9][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBAAAAA"
    )
        port map (
      I0 => \rdid[9][0]_i_2_n_0\,
      I1 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I2 => \rdid[1][0]_i_3_n_0\,
      I3 => \rdid[9][0]_i_3_n_0\,
      I4 => \rdid_reg[9]_12\(0),
      O => \rdid[9][0]_i_1_n_0\
    );
\rdid[9][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040000000"
    )
        port map (
      I0 => \ixRdid__0\(2),
      I1 => \ixRdid__0\(3),
      I2 => \rdid[9][0]_i_4_n_0\,
      I3 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I4 => \ixRdid__0\(0),
      I5 => \rdmutex[1]_i_2_n_0\,
      O => \rdid[9][0]_i_2_n_0\
    );
\rdid[9][0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \ixRdidEgr__0\(2),
      I1 => \ixRdidEgr__0\(3),
      I2 => \rdid_reg[1][0]_0\,
      O => \rdid[9][0]_i_3_n_0\
    );
\rdid[9][0]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \ixRdid__0\(4),
      I1 => \ixRdid__0\(1),
      O => \rdid[9][0]_i_4_n_0\
    );
\rdid_reg[0][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[0][0]_i_1_n_0\,
      Q => \rdid_reg[0]_3\(0)
    );
\rdid_reg[10][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[10][0]_i_1_n_0\,
      Q => \rdid_reg[10]_13\(0)
    );
\rdid_reg[11][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[11][0]_i_1_n_0\,
      Q => \rdid_reg[11]_14\(0)
    );
\rdid_reg[12][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[12][0]_i_1_n_0\,
      Q => \rdid_reg[12]_15\(0)
    );
\rdid_reg[13][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[13][0]_i_1_n_0\,
      Q => \rdid_reg[13]_16\(0)
    );
\rdid_reg[14][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[14][0]_i_1_n_0\,
      Q => \rdid_reg[14]_17\(0)
    );
\rdid_reg[15][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[15][0]_i_1_n_0\,
      Q => \rdid_reg[15]_18\(0)
    );
\rdid_reg[16][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[16][0]_i_1_n_0\,
      Q => \rdid_reg[16]_19\(0)
    );
\rdid_reg[17][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[17][0]_i_1_n_0\,
      Q => \rdid_reg[17]_20\(0)
    );
\rdid_reg[18][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[18][0]_i_1_n_0\,
      Q => \rdid_reg[18]_21\(0)
    );
\rdid_reg[19][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[19][0]_i_1_n_0\,
      Q => \rdid_reg[19]_22\(0)
    );
\rdid_reg[1][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[1][0]_i_1_n_0\,
      Q => \rdid_reg[1]_4\(0)
    );
\rdid_reg[20][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[20][0]_i_1_n_0\,
      Q => \rdid_reg[20]_23\(0)
    );
\rdid_reg[21][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[21][0]_i_1_n_0\,
      Q => \rdid_reg[21]_24\(0)
    );
\rdid_reg[22][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[22][0]_i_1_n_0\,
      Q => \rdid_reg[22]_25\(0)
    );
\rdid_reg[23][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[23][0]_i_1_n_0\,
      Q => \rdid_reg[23]_26\(0)
    );
\rdid_reg[24][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[24][0]_i_1_n_0\,
      Q => \rdid_reg[24]_27\(0)
    );
\rdid_reg[25][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[25][0]_i_1_n_0\,
      Q => \rdid_reg[25]_28\(0)
    );
\rdid_reg[26][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[26][0]_i_1_n_0\,
      Q => \rdid_reg[26]_29\(0)
    );
\rdid_reg[27][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[27][0]_i_1_n_0\,
      Q => \rdid_reg[27]_30\(0)
    );
\rdid_reg[28][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[28][0]_i_1_n_0\,
      Q => \rdid_reg[28]_31\(0)
    );
\rdid_reg[29][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[29][0]_i_1_n_0\,
      Q => \rdid_reg[29]_32\(0)
    );
\rdid_reg[2][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[2][0]_i_1_n_0\,
      Q => \rdid_reg[2]_5\(0)
    );
\rdid_reg[30][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[30][0]_i_1_n_0\,
      Q => \rdid_reg[30]_33\(0)
    );
\rdid_reg[31][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[31][0]_i_1_n_0\,
      Q => \rdid_reg[31]_34\(0)
    );
\rdid_reg[3][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[3][0]_i_1_n_0\,
      Q => \rdid_reg[3]_6\(0)
    );
\rdid_reg[4][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[4][0]_i_1_n_0\,
      Q => \rdid_reg[4]_7\(0)
    );
\rdid_reg[5][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[5][0]_i_1_n_0\,
      Q => \rdid_reg[5]_8\(0)
    );
\rdid_reg[6][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[6][0]_i_1_n_0\,
      Q => \rdid_reg[6]_9\(0)
    );
\rdid_reg[7][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[7][0]_i_1_n_0\,
      Q => \rdid_reg[7]_10\(0)
    );
\rdid_reg[8][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[8][0]_i_1_n_0\,
      Q => \rdid_reg[8]_11\(0)
    );
\rdid_reg[9][0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdid[9][0]_i_1_n_0\,
      Q => \rdid_reg[9]_12\(0)
    );
\rdmutex[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \FSM_onehot_stateRead[2]_i_2_n_0\,
      O => \rdmutex[0]_i_1_n_0\
    );
\rdmutex[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \rdmutex[1]_i_2_n_0\,
      I1 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      O => \rdmutex[1]_i_1_n_0\
    );
\rdmutex[1]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[7]_10\(0),
      I1 => \rdid_reg[6]_9\(0),
      I2 => \ixRdid__0\(1),
      I3 => \rdid_reg[5]_8\(0),
      I4 => \ixRdid__0\(0),
      I5 => \rdid_reg[4]_7\(0),
      O => \rdmutex[1]_i_10_n_0\
    );
\rdmutex[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[11]_14\(0),
      I1 => \rdid_reg[10]_13\(0),
      I2 => \ixRdid__0\(1),
      I3 => \rdid_reg[9]_12\(0),
      I4 => \ixRdid__0\(0),
      I5 => \rdid_reg[8]_11\(0),
      O => \rdmutex[1]_i_11_n_0\
    );
\rdmutex[1]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[15]_18\(0),
      I1 => \rdid_reg[14]_17\(0),
      I2 => \ixRdid__0\(1),
      I3 => \rdid_reg[13]_16\(0),
      I4 => \ixRdid__0\(0),
      I5 => \rdid_reg[12]_15\(0),
      O => \rdmutex[1]_i_12_n_0\
    );
\rdmutex[1]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[19]_22\(0),
      I1 => \rdid_reg[18]_21\(0),
      I2 => \ixRdid__0\(1),
      I3 => \rdid_reg[17]_20\(0),
      I4 => \ixRdid__0\(0),
      I5 => \rdid_reg[16]_19\(0),
      O => \rdmutex[1]_i_13_n_0\
    );
\rdmutex[1]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[23]_26\(0),
      I1 => \rdid_reg[22]_25\(0),
      I2 => \ixRdid__0\(1),
      I3 => \rdid_reg[21]_24\(0),
      I4 => \ixRdid__0\(0),
      I5 => \rdid_reg[20]_23\(0),
      O => \rdmutex[1]_i_14_n_0\
    );
\rdmutex[1]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[27]_30\(0),
      I1 => \rdid_reg[26]_29\(0),
      I2 => \ixRdid__0\(1),
      I3 => \rdid_reg[25]_28\(0),
      I4 => \ixRdid__0\(0),
      I5 => \rdid_reg[24]_27\(0),
      O => \rdmutex[1]_i_15_n_0\
    );
\rdmutex[1]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[31]_34\(0),
      I1 => \rdid_reg[30]_33\(0),
      I2 => \ixRdid__0\(1),
      I3 => \rdid_reg[29]_32\(0),
      I4 => \ixRdid__0\(0),
      I5 => \rdid_reg[28]_31\(0),
      O => \rdmutex[1]_i_16_n_0\
    );
\rdmutex[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE2FFFF"
    )
        port map (
      I0 => \rdmutex_reg[1]_i_3_n_0\,
      I1 => \ixRdid__0\(4),
      I2 => \rdmutex_reg[1]_i_4_n_0\,
      I3 => \rdmutex_reg[1]_2\(0),
      I4 => web(0),
      O => \rdmutex[1]_i_2_n_0\
    );
\rdmutex[1]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rdid_reg[3]_6\(0),
      I1 => \rdid_reg[2]_5\(0),
      I2 => \ixRdid__0\(1),
      I3 => \rdid_reg[1]_4\(0),
      I4 => \ixRdid__0\(0),
      I5 => \rdid_reg[0]_3\(0),
      O => \rdmutex[1]_i_9_n_0\
    );
\rdmutex_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateRead[2]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdmutex[0]_i_1_n_0\,
      Q => \^rdmutex_reg[1]_0\(0)
    );
\rdmutex_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateRead[2]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \rdmutex[1]_i_1_n_0\,
      Q => \^rdmutex_reg[1]_0\(1)
    );
\rdmutex_reg[1]_i_3\: unisim.vcomponents.MUXF8
     port map (
      I0 => \rdmutex_reg[1]_i_5_n_0\,
      I1 => \rdmutex_reg[1]_i_6_n_0\,
      O => \rdmutex_reg[1]_i_3_n_0\,
      S => \ixRdid__0\(3)
    );
\rdmutex_reg[1]_i_4\: unisim.vcomponents.MUXF8
     port map (
      I0 => \rdmutex_reg[1]_i_7_n_0\,
      I1 => \rdmutex_reg[1]_i_8_n_0\,
      O => \rdmutex_reg[1]_i_4_n_0\,
      S => \ixRdid__0\(3)
    );
\rdmutex_reg[1]_i_5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rdmutex[1]_i_9_n_0\,
      I1 => \rdmutex[1]_i_10_n_0\,
      O => \rdmutex_reg[1]_i_5_n_0\,
      S => \ixRdid__0\(2)
    );
\rdmutex_reg[1]_i_6\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rdmutex[1]_i_11_n_0\,
      I1 => \rdmutex[1]_i_12_n_0\,
      O => \rdmutex_reg[1]_i_6_n_0\,
      S => \ixRdid__0\(2)
    );
\rdmutex_reg[1]_i_7\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rdmutex[1]_i_13_n_0\,
      I1 => \rdmutex[1]_i_14_n_0\,
      O => \rdmutex_reg[1]_i_7_n_0\,
      S => \ixRdid__0\(2)
    );
\rdmutex_reg[1]_i_8\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rdmutex[1]_i_15_n_0\,
      I1 => \rdmutex[1]_i_16_n_0\,
      O => \rdmutex_reg[1]_i_8_n_0\,
      S => \ixRdid__0\(2)
    );
stateStats_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => tkclk,
      Q => \^statestats\
    );
\strbRdlock_i[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => strbRdlock_i_reg(0),
      I1 => strbRdlock_reg_n_0,
      O => \strbRdlock_i[0]_i_1_n_0\
    );
\strbRdlock_i[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => strbRdlock_i_reg(1),
      I1 => strbRdlock_i_reg(0),
      I2 => strbRdlock_reg_n_0,
      O => \strbRdlock_i[1]_i_1_n_0\
    );
\strbRdlock_i[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => strbRdlock_i_reg(2),
      I1 => strbRdlock_i_reg(1),
      I2 => strbRdlock_i_reg(0),
      I3 => strbRdlock_reg_n_0,
      O => \strbRdlock_i[2]_i_1_n_0\
    );
\strbRdlock_i[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFFFF"
    )
        port map (
      I0 => strbRdlock_reg_n_0,
      I1 => strbRdlock_i_reg(2),
      I2 => strbRdlock_i_reg(0),
      I3 => strbRdlock_i_reg(1),
      I4 => strbRdlock_i_reg(3),
      O => \strbRdlock_i[3]_i_1_n_0\
    );
\strbRdlock_i[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => strbRdlock_i_reg(3),
      I1 => strbRdlock_i_reg(2),
      I2 => strbRdlock_i_reg(0),
      I3 => strbRdlock_i_reg(1),
      I4 => strbRdlock_reg_n_0,
      O => \strbRdlock_i[3]_i_2_n_0\
    );
strbRdlock_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00F30050"
    )
        port map (
      I0 => \rdmutex[1]_i_2_n_0\,
      I1 => \^fsm_onehot_stateread_reg[2]_0\(0),
      I2 => \FSM_onehot_stateRead_reg_n_0_[1]\,
      I3 => \FSM_onehot_stateRead_reg_n_0_[0]\,
      I4 => strbRdlock_reg_n_0,
      O => strbRdlock_i_1_n_0
    );
\strbRdlock_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \strbRdlock_i[3]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \strbRdlock_i[0]_i_1_n_0\,
      Q => strbRdlock_i_reg(0)
    );
\strbRdlock_i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \strbRdlock_i[3]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \strbRdlock_i[1]_i_1_n_0\,
      Q => strbRdlock_i_reg(1)
    );
\strbRdlock_i_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \strbRdlock_i[3]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \strbRdlock_i[2]_i_1_n_0\,
      Q => strbRdlock_i_reg(2)
    );
\strbRdlock_i_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \strbRdlock_i[3]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \strbRdlock_i[3]_i_2_n_0\,
      Q => strbRdlock_i_reg(3)
    );
strbRdlock_mclk_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => strbRdlock_mclk_reg_n_0,
      I1 => strbRdlock_wait_reg_n_0,
      I2 => strbRdlock_to_mclkm2,
      I3 => strbRdlock_to_mclkm1,
      O => strbRdlock_mclk_i_1_n_0
    );
strbRdlock_mclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => strbRdlock_mclk_i_1_n_0,
      Q => strbRdlock_mclk_reg_n_0
    );
strbRdlock_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => strbRdlock_i_1_n_0,
      Q => strbRdlock_reg_n_0
    );
strbRdlock_to_mclk_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFBFAAAAAAAA"
    )
        port map (
      I0 => strbRdlock_reg_n_0,
      I1 => strbRdlock_i_reg(3),
      I2 => strbRdlock_i_reg(1),
      I3 => strbRdlock_i_reg(2),
      I4 => strbRdlock_i_reg(0),
      I5 => strbRdlock_to_mclk_reg_n_0,
      O => strbRdlock_to_mclk_i_1_n_0
    );
strbRdlock_to_mclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => strbRdlock_to_mclk_i_1_n_0,
      Q => strbRdlock_to_mclk_reg_n_0
    );
strbRdlock_to_mclkm1_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => strbRdlock_to_mclk_reg_n_0,
      Q => strbRdlock_to_mclkm1
    );
strbRdlock_to_mclkm2_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => strbRdlock_to_mclkm1,
      Q => strbRdlock_to_mclkm2
    );
strbRdlock_wait_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BAA0"
    )
        port map (
      I0 => strbRdlock_wait_reg_n_0,
      I1 => strbRdlock_mclk_reg_n_0,
      I2 => strbRdlock_to_mclkm1,
      I3 => strbRdlock_to_mclkm2,
      O => strbRdlock_wait9_out
    );
strbRdlock_wait_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => strbRdlock_wait9_out,
      Q => strbRdlock_wait_reg_n_0
    );
\strbWrlock_i[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => strbWrlock_i_reg(0),
      I1 => strbWrlock,
      O => \strbWrlock_i[0]_i_1_n_0\
    );
\strbWrlock_i[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => strbWrlock_i_reg(1),
      I1 => strbWrlock_i_reg(0),
      I2 => strbWrlock,
      O => \strbWrlock_i[1]_i_1_n_0\
    );
\strbWrlock_i[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => strbWrlock_i_reg(2),
      I1 => strbWrlock_i_reg(1),
      I2 => strbWrlock_i_reg(0),
      I3 => strbWrlock,
      O => \strbWrlock_i[2]_i_1_n_0\
    );
\strbWrlock_i[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFFFF"
    )
        port map (
      I0 => strbWrlock,
      I1 => strbWrlock_i_reg(2),
      I2 => strbWrlock_i_reg(0),
      I3 => strbWrlock_i_reg(1),
      I4 => strbWrlock_i_reg(3),
      O => \strbWrlock_i[3]_i_1_n_0\
    );
\strbWrlock_i[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => strbWrlock_i_reg(3),
      I1 => strbWrlock_i_reg(2),
      I2 => strbWrlock_i_reg(0),
      I3 => strbWrlock_i_reg(1),
      I4 => strbWrlock,
      O => \strbWrlock_i[3]_i_2_n_0\
    );
\strbWrlock_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \strbWrlock_i[3]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \strbWrlock_i[0]_i_1_n_0\,
      Q => strbWrlock_i_reg(0)
    );
\strbWrlock_i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \strbWrlock_i[3]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \strbWrlock_i[1]_i_1_n_0\,
      Q => strbWrlock_i_reg(1)
    );
\strbWrlock_i_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \strbWrlock_i[3]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \strbWrlock_i[2]_i_1_n_0\,
      Q => strbWrlock_i_reg(2)
    );
\strbWrlock_i_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \strbWrlock_i[3]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \strbWrlock_i[3]_i_2_n_0\,
      Q => strbWrlock_i_reg(3)
    );
strbWrlock_mclk_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => strbWrlock_mclk_reg_n_0,
      I1 => strbWrlock_wait_reg_n_0,
      I2 => strbWrlock_to_mclkm2,
      I3 => strbWrlock_to_mclkm1,
      O => strbWrlock_mclk_i_1_n_0
    );
strbWrlock_mclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => strbWrlock_mclk_i_1_n_0,
      Q => strbWrlock_mclk_reg_n_0
    );
strbWrlock_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => wdone_i_1_n_0,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => D(0),
      Q => strbWrlock
    );
strbWrlock_to_mclk_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFBFAAAAAAAA"
    )
        port map (
      I0 => strbWrlock,
      I1 => strbWrlock_i_reg(3),
      I2 => strbWrlock_i_reg(1),
      I3 => strbWrlock_i_reg(2),
      I4 => strbWrlock_i_reg(0),
      I5 => strbWrlock_to_mclk_reg_n_0,
      O => strbWrlock_to_mclk_i_1_n_0
    );
strbWrlock_to_mclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => strbWrlock_to_mclk_i_1_n_0,
      Q => strbWrlock_to_mclk_reg_n_0
    );
strbWrlock_to_mclkm1_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => strbWrlock_to_mclk_reg_n_0,
      Q => strbWrlock_to_mclkm1
    );
strbWrlock_to_mclkm2_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => strbWrlock_to_mclkm1,
      Q => strbWrlock_to_mclkm2
    );
strbWrlock_wait_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BAA0"
    )
        port map (
      I0 => strbWrlock_wait_reg_n_0,
      I1 => strbWrlock_mclk_reg_n_0,
      I2 => strbWrlock_to_mclkm1,
      I3 => strbWrlock_to_mclkm2,
      O => strbWrlock_wait3_out
    );
strbWrlock_wait_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => strbWrlock_wait3_out,
      Q => strbWrlock_wait_reg_n_0
    );
wdone_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \FSM_onehot_stateWrite[2]_i_2_n_0\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => wdone_i_1_n_0
    );
wdone_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \FSM_onehot_stateWrite[2]_i_3_n_0\,
      I1 => ddrAXI_bready_sig,
      I2 => \^q\(0),
      O => wdone_i_2_n_0
    );
wdone_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => wdone_i_1_n_0,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => wdone_i_2_n_0,
      Q => wdone_reg_n_0
    );
\wrmutex_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateWrite[2]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => D(0),
      Q => \wrmutex_reg_n_0_[0]\
    );
\wrmutex_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateWrite[2]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => D(1),
      Q => \wrmutex_reg_n_0_[1]\
    );
\wtr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => wtr(0),
      I1 => ddrAXI_bready_sig_i_2_n_0,
      I2 => ddrAXI_bready_sig0,
      O => \wtr[0]_i_1_n_0\
    );
\wtr[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EB28"
    )
        port map (
      I0 => ddrAXI_bready_sig0,
      I1 => wtr(1),
      I2 => wtr(0),
      I3 => ddrAXI_bready_sig_i_2_n_0,
      O => \wtr[1]_i_1_n_0\
    );
\wtr[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BCCE8882"
    )
        port map (
      I0 => ddrAXI_bready_sig_i_2_n_0,
      I1 => wtr(2),
      I2 => wtr(0),
      I3 => wtr(1),
      I4 => ddrAXI_bready_sig0,
      O => \wtr[2]_i_1_n_0\
    );
\wtr[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BCCCCCCE88888882"
    )
        port map (
      I0 => ddrAXI_bready_sig_i_2_n_0,
      I1 => wtr(3),
      I2 => wtr(2),
      I3 => wtr(1),
      I4 => wtr(0),
      I5 => ddrAXI_bready_sig0,
      O => \wtr[3]_i_1_n_0\
    );
\wtr[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFAABF"
    )
        port map (
      I0 => ddrAXI_bready_sig_i_2_n_0,
      I1 => \^ddraxi_bready_sig_reg_0\,
      I2 => ddrAXI_bvalid,
      I3 => ddrAXI_bready_sig_i_3_n_0,
      I4 => ddrAXI_bready_sig,
      O => \wtr[4]_i_1_n_0\
    );
\wtr[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5FF0F0F050405040"
    )
        port map (
      I0 => \wtr[4]_i_3_n_0\,
      I1 => \wtr[4]_i_4_n_0\,
      I2 => wtr(4),
      I3 => wtr(3),
      I4 => \wtr[4]_i_5_n_0\,
      I5 => ddrAXI_bready_sig0,
      O => \wtr[4]_i_2_n_0\
    );
\wtr[4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F7"
    )
        port map (
      I0 => \^ddraxi_bready_sig_reg_0\,
      I1 => ddrAXI_bvalid,
      I2 => \FSM_onehot_stateWrite[2]_i_2_n_0\,
      O => \wtr[4]_i_3_n_0\
    );
\wtr[4]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => wtr(2),
      I1 => wtr(0),
      I2 => wtr(1),
      O => \wtr[4]_i_4_n_0\
    );
\wtr[4]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => wtr(0),
      I1 => wtr(1),
      I2 => wtr(2),
      O => \wtr[4]_i_5_n_0\
    );
\wtr[4]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0015"
    )
        port map (
      I0 => ddrAXI_bready_sig_i_3_n_0,
      I1 => ddrAXI_bvalid,
      I2 => \^ddraxi_bready_sig_reg_0\,
      I3 => ddrAXI_bready_sig,
      O => ddrAXI_bready_sig0
    );
\wtr_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \wtr[4]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \wtr[0]_i_1_n_0\,
      Q => wtr(0)
    );
\wtr_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \wtr[4]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \wtr[1]_i_1_n_0\,
      Q => wtr(1)
    );
\wtr_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \wtr[4]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \wtr[2]_i_1_n_0\,
      Q => wtr(2)
    );
\wtr_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \wtr[4]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \wtr[3]_i_1_n_0\,
      Q => wtr(3)
    );
\wtr_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \wtr[4]_i_1_n_0\,
      CLR => \strbWrlock_i_reg[0]_0\(0),
      D => \wtr[4]_i_2_n_0\,
      Q => wtr(4)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Director is
  port (
    ackInvDirectorSet : out STD_LOGIC;
    ackInvDirectorConfig : out STD_LOGIC;
    stateOp_reg_0 : out STD_LOGIC;
    rng : out STD_LOGIC;
    \NRowRaw_sig_reg[7]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
    rng_sig_reg_0 : out STD_LOGIC;
    \rowRaw_lcl_reg[10]\ : out STD_LOGIC;
    \NRowRaw_sig_reg[10]_0\ : out STD_LOGIC;
    \NRowRaw_sig_reg[11]_0\ : out STD_LOGIC;
    \row_reg[11]\ : out STD_LOGIC;
    \row_reg[9]\ : out STD_LOGIC;
    \col_reg[8]\ : out STD_LOGIC;
    \NColRaw_sig_reg[11]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    rng_sig_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \NColRaw_sig_reg[11]_1\ : out STD_LOGIC;
    \NColRaw_sig_reg[8]_0\ : out STD_LOGIC;
    \NColRaw_sig_reg[2]_0\ : out STD_LOGIC;
    \NColRaw_sig_reg[9]_0\ : out STD_LOGIC;
    \NColRaw_sig_reg[5]_0\ : out STD_LOGIC;
    \NColRaw_sig_reg[3]_0\ : out STD_LOGIC;
    \row_lcl_reg[0]\ : out STD_LOGIC;
    \NColRaw_sig_reg[7]_0\ : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    AR : in STD_LOGIC_VECTOR ( 0 to 0 );
    stateOp0_out : in STD_LOGIC;
    rng_sig_reg_2 : in STD_LOGIC;
    reqInvDirectorConfig : in STD_LOGIC;
    reqInvDirectorSet : in STD_LOGIC;
    enCoobuf_reg : in STD_LOGIC;
    \stateMaxsel[0]_i_2_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    commok : in STD_LOGIC;
    \i_reg[0]__1\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \stateLive[1]_i_11_0\ : in STD_LOGIC;
    \row_reg[0]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \stateSynth[2]_i_12_0\ : in STD_LOGIC;
    \i[7]_i_3_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \i[7]_i_6_0\ : in STD_LOGIC;
    \toVideoinAXIS_tdata_sig_reg[23]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \aImdbufB_reg[0]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \stateMaxsel[0]_i_6_0\ : in STD_LOGIC;
    \stateSwap[2]_i_5_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    rgbToManyAXIS_tlast_sig_i_2 : in STD_LOGIC_VECTOR ( 4 downto 0 );
    rgbToManyAXIS_tlast_sig_i_2_0 : in STD_LOGIC;
    rgbToManyAXIS_tlast_sig_i_4_0 : in STD_LOGIC;
    rgbToManyAXIS_tlast_sig_i_4_1 : in STD_LOGIC;
    rgbToManyAXIS_tlast_sig_i_4_2 : in STD_LOGIC;
    \NRowRaw_sig_reg[11]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D : in STD_LOGIC_VECTOR ( 18 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Director : entity is "Director";
end design_1_Vsp_core_0_0_Director;

architecture STRUCTURE of design_1_Vsp_core_0_0_Director is
  signal \^ncolraw_sig_reg[11]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \^ncolraw_sig_reg[2]_0\ : STD_LOGIC;
  signal \^ncolraw_sig_reg[8]_0\ : STD_LOGIC;
  signal NRowRaw_sig : STD_LOGIC;
  signal \^nrowraw_sig_reg[10]_0\ : STD_LOGIC;
  signal \^nrowraw_sig_reg[11]_0\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \^ackinvdirectorconfig\ : STD_LOGIC;
  signal \^ackinvdirectorset\ : STD_LOGIC;
  signal ackInvSet_sig : STD_LOGIC;
  signal \i[7]_i_12_n_0\ : STD_LOGIC;
  signal \i[7]_i_13_n_0\ : STD_LOGIC;
  signal \i[7]_i_14_n_0\ : STD_LOGIC;
  signal \i[7]_i_15_n_0\ : STD_LOGIC;
  signal \i[7]_i_16_n_0\ : STD_LOGIC;
  signal \i[7]_i_6_n_0\ : STD_LOGIC;
  signal \i[7]_i_7_n_0\ : STD_LOGIC;
  signal \i[7]_i_8_n_0\ : STD_LOGIC;
  signal \i[7]_i_9_n_0\ : STD_LOGIC;
  signal rgbToManyAXIS_tlast_sig_i_6_n_0 : STD_LOGIC;
  signal rgbToManyAXIS_tlast_sig_i_7_n_0 : STD_LOGIC;
  signal \^rng\ : STD_LOGIC;
  signal \row[11]_i_10_n_0\ : STD_LOGIC;
  signal \row[11]_i_11_n_0\ : STD_LOGIC;
  signal \row[11]_i_8_n_0\ : STD_LOGIC;
  signal \row[11]_i_9_n_0\ : STD_LOGIC;
  signal \stateImdstream[2]_i_10_n_0\ : STD_LOGIC;
  signal \stateImdstream[2]_i_4_n_0\ : STD_LOGIC;
  signal \stateImdstream[2]_i_6_n_0\ : STD_LOGIC;
  signal \stateImdstream[2]_i_7_n_0\ : STD_LOGIC;
  signal \stateImdstream[2]_i_8_n_0\ : STD_LOGIC;
  signal \stateImdstream[2]_i_9_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_11_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_12_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_13_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_14_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_17_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_18_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_19_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_6_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_7_n_0\ : STD_LOGIC;
  signal \stateMaxsel[0]_i_3_n_0\ : STD_LOGIC;
  signal \stateMaxsel[0]_i_4_n_0\ : STD_LOGIC;
  signal \stateMaxsel[0]_i_5_n_0\ : STD_LOGIC;
  signal \stateMaxsel[0]_i_6_n_0\ : STD_LOGIC;
  signal \stateMaxsel[0]_i_7_n_0\ : STD_LOGIC;
  signal \stateMaxsel[0]_i_8_n_0\ : STD_LOGIC;
  signal \stateMaxsel[0]_i_9_n_0\ : STD_LOGIC;
  signal stateOp : STD_LOGIC;
  signal \^stateop_reg_0\ : STD_LOGIC;
  signal \stateSwap[2]_i_10_n_0\ : STD_LOGIC;
  signal \stateSwap[2]_i_11_n_0\ : STD_LOGIC;
  signal \stateSwap[2]_i_12_n_0\ : STD_LOGIC;
  signal \stateSwap[2]_i_13_n_0\ : STD_LOGIC;
  signal \stateSwap[2]_i_14_n_0\ : STD_LOGIC;
  signal \stateSwap[2]_i_15_n_0\ : STD_LOGIC;
  signal \stateSwap[2]_i_7_n_0\ : STD_LOGIC;
  signal \stateSwap[2]_i_8_n_0\ : STD_LOGIC;
  signal \stateSwap[2]_i_9_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_13_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_14_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_15_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_16_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_17_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_18_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_20_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_21_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \col_lcl[10]__0_i_18\ : label is "soft_lutpair1680";
  attribute SOFT_HLUTNM of \col_lcl[10]__0_i_7\ : label is "soft_lutpair1675";
  attribute SOFT_HLUTNM of \i[7]_i_13\ : label is "soft_lutpair1672";
  attribute SOFT_HLUTNM of \i[7]_i_15\ : label is "soft_lutpair1678";
  attribute SOFT_HLUTNM of \i[7]_i_16\ : label is "soft_lutpair1680";
  attribute SOFT_HLUTNM of \i[7]_i_8\ : label is "soft_lutpair1678";
  attribute SOFT_HLUTNM of \row[11]_i_10\ : label is "soft_lutpair1674";
  attribute SOFT_HLUTNM of \row[11]_i_11\ : label is "soft_lutpair1679";
  attribute SOFT_HLUTNM of \seq[1][5]_i_1\ : label is "soft_lutpair1683";
  attribute SOFT_HLUTNM of \stateImdstream[2]_i_5\ : label is "soft_lutpair1675";
  attribute SOFT_HLUTNM of \stateImdstream[2]_i_8\ : label is "soft_lutpair1672";
  attribute SOFT_HLUTNM of \stateLive[1]_i_12\ : label is "soft_lutpair1682";
  attribute SOFT_HLUTNM of \stateLive[1]_i_14\ : label is "soft_lutpair1671";
  attribute SOFT_HLUTNM of \stateLive[1]_i_18\ : label is "soft_lutpair1670";
  attribute SOFT_HLUTNM of \stateLive[1]_i_19\ : label is "soft_lutpair1673";
  attribute SOFT_HLUTNM of \stateMaxsel[0]_i_7\ : label is "soft_lutpair1681";
  attribute SOFT_HLUTNM of \stateMaxsel[0]_i_9\ : label is "soft_lutpair1676";
  attribute SOFT_HLUTNM of \stateSwap[2]_i_10\ : label is "soft_lutpair1681";
  attribute SOFT_HLUTNM of \stateSwap[2]_i_11\ : label is "soft_lutpair1676";
  attribute SOFT_HLUTNM of \stateSwap[2]_i_13\ : label is "soft_lutpair1677";
  attribute SOFT_HLUTNM of \stateSwap[2]_i_14\ : label is "soft_lutpair1677";
  attribute SOFT_HLUTNM of \stateSynth[2]_i_13\ : label is "soft_lutpair1671";
  attribute SOFT_HLUTNM of \stateSynth[2]_i_14\ : label is "soft_lutpair1679";
  attribute SOFT_HLUTNM of \stateSynth[2]_i_15\ : label is "soft_lutpair1682";
  attribute SOFT_HLUTNM of \stateSynth[2]_i_17\ : label is "soft_lutpair1674";
  attribute SOFT_HLUTNM of \stateSynth[2]_i_20\ : label is "soft_lutpair1673";
  attribute SOFT_HLUTNM of \stateSynth[2]_i_21\ : label is "soft_lutpair1670";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[23]_i_1\ : label is "soft_lutpair1683";
begin
  \NColRaw_sig_reg[11]_0\(10 downto 0) <= \^ncolraw_sig_reg[11]_0\(10 downto 0);
  \NColRaw_sig_reg[2]_0\ <= \^ncolraw_sig_reg[2]_0\;
  \NColRaw_sig_reg[8]_0\ <= \^ncolraw_sig_reg[8]_0\;
  \NRowRaw_sig_reg[10]_0\ <= \^nrowraw_sig_reg[10]_0\;
  \NRowRaw_sig_reg[11]_0\ <= \^nrowraw_sig_reg[11]_0\;
  Q(11 downto 0) <= \^q\(11 downto 0);
  ackInvDirectorConfig <= \^ackinvdirectorconfig\;
  ackInvDirectorSet <= \^ackinvdirectorset\;
  rng <= \^rng\;
  stateOp_reg_0 <= \^stateop_reg_0\;
\/i_\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^stateop_reg_0\,
      I1 => reqInvDirectorConfig,
      I2 => reqInvDirectorSet,
      O => ackInvSet_sig
    );
\NColRaw_sig_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      CLR => AR(0),
      D => D(9),
      Q => \^ncolraw_sig_reg[11]_0\(9)
    );
\NColRaw_sig_reg[11]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      D => D(10),
      PRE => AR(0),
      Q => \^ncolraw_sig_reg[11]_0\(10)
    );
\NColRaw_sig_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      CLR => AR(0),
      D => D(0),
      Q => \^ncolraw_sig_reg[11]_0\(0)
    );
\NColRaw_sig_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      CLR => AR(0),
      D => D(1),
      Q => \^ncolraw_sig_reg[11]_0\(1)
    );
\NColRaw_sig_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      CLR => AR(0),
      D => D(2),
      Q => \^ncolraw_sig_reg[11]_0\(2)
    );
\NColRaw_sig_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      CLR => AR(0),
      D => D(3),
      Q => \^ncolraw_sig_reg[11]_0\(3)
    );
\NColRaw_sig_reg[5]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      D => D(4),
      PRE => AR(0),
      Q => \^ncolraw_sig_reg[11]_0\(4)
    );
\NColRaw_sig_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      CLR => AR(0),
      D => D(5),
      Q => \^ncolraw_sig_reg[11]_0\(5)
    );
\NColRaw_sig_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      CLR => AR(0),
      D => D(6),
      Q => \^ncolraw_sig_reg[11]_0\(6)
    );
\NColRaw_sig_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      CLR => AR(0),
      D => D(7),
      Q => \^ncolraw_sig_reg[11]_0\(7)
    );
\NColRaw_sig_reg[9]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      D => D(8),
      PRE => AR(0),
      Q => \^ncolraw_sig_reg[11]_0\(8)
    );
\NRowRaw_sig_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      CLR => AR(0),
      D => D(11),
      Q => \^q\(0)
    );
\NRowRaw_sig_reg[10]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      D => \NRowRaw_sig_reg[11]_1\(2),
      PRE => AR(0),
      Q => \^q\(10)
    );
\NRowRaw_sig_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      CLR => AR(0),
      D => \NRowRaw_sig_reg[11]_1\(3),
      Q => \^q\(11)
    );
\NRowRaw_sig_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      CLR => AR(0),
      D => D(12),
      Q => \^q\(1)
    );
\NRowRaw_sig_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      CLR => AR(0),
      D => D(13),
      Q => \^q\(2)
    );
\NRowRaw_sig_reg[3]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      D => D(14),
      PRE => AR(0),
      Q => \^q\(3)
    );
\NRowRaw_sig_reg[4]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      D => D(15),
      PRE => AR(0),
      Q => \^q\(4)
    );
\NRowRaw_sig_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      CLR => AR(0),
      D => D(16),
      Q => \^q\(5)
    );
\NRowRaw_sig_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      CLR => AR(0),
      D => D(17),
      Q => \^q\(6)
    );
\NRowRaw_sig_reg[7]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      D => D(18),
      PRE => AR(0),
      Q => \^q\(7)
    );
\NRowRaw_sig_reg[8]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      D => \NRowRaw_sig_reg[11]_1\(0),
      PRE => AR(0),
      Q => \^q\(8)
    );
\NRowRaw_sig_reg[9]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => NRowRaw_sig,
      D => \NRowRaw_sig_reg[11]_1\(1),
      PRE => AR(0),
      Q => \^q\(9)
    );
\ackInvConfig_sig_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \^stateop_reg_0\,
      I1 => reqInvDirectorConfig,
      O => NRowRaw_sig
    );
ackInvConfig_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stateOp,
      CLR => AR(0),
      D => NRowRaw_sig,
      Q => \^ackinvdirectorconfig\
    );
\ackInvSet_sig_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5D5DFF5D"
    )
        port map (
      I0 => \^stateop_reg_0\,
      I1 => \^ackinvdirectorset\,
      I2 => reqInvDirectorSet,
      I3 => \^ackinvdirectorconfig\,
      I4 => reqInvDirectorConfig,
      O => stateOp
    );
ackInvSet_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stateOp,
      CLR => AR(0),
      D => ackInvSet_sig,
      Q => \^ackinvdirectorset\
    );
\col_lcl[10]__0_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(1),
      I1 => \^ncolraw_sig_reg[11]_0\(0),
      I2 => \^ncolraw_sig_reg[11]_0\(2),
      O => \^ncolraw_sig_reg[2]_0\
    );
\col_lcl[10]__0_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(4),
      I1 => \^ncolraw_sig_reg[11]_0\(2),
      I2 => \^ncolraw_sig_reg[11]_0\(0),
      I3 => \^ncolraw_sig_reg[11]_0\(1),
      I4 => \^ncolraw_sig_reg[11]_0\(3),
      I5 => \^ncolraw_sig_reg[11]_0\(5),
      O => \NColRaw_sig_reg[5]_0\
    );
\col_lcl[10]__0_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(2),
      I1 => \^ncolraw_sig_reg[11]_0\(0),
      I2 => \^ncolraw_sig_reg[11]_0\(1),
      I3 => \^ncolraw_sig_reg[11]_0\(3),
      O => \NColRaw_sig_reg[3]_0\
    );
\col_lcl[10]__0_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAA9AA"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(8),
      I1 => \^ncolraw_sig_reg[11]_0\(7),
      I2 => \^ncolraw_sig_reg[11]_0\(5),
      I3 => \stateImdstream[2]_i_8_n_0\,
      I4 => \^ncolraw_sig_reg[11]_0\(6),
      O => \NColRaw_sig_reg[9]_0\
    );
\i[7]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF6FF6F69F"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(4),
      I1 => \i[7]_i_3_0\(1),
      I2 => \i[7]_i_3_0\(0),
      I3 => \i[7]_i_16_n_0\,
      I4 => \^ncolraw_sig_reg[11]_0\(3),
      I5 => \i[7]_i_6_0\,
      O => \i[7]_i_12_n_0\
    );
\i[7]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(4),
      I1 => \^ncolraw_sig_reg[11]_0\(2),
      I2 => \^ncolraw_sig_reg[11]_0\(1),
      I3 => \^ncolraw_sig_reg[11]_0\(0),
      I4 => \^ncolraw_sig_reg[11]_0\(3),
      O => \i[7]_i_13_n_0\
    );
\i[7]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(5),
      I1 => \^ncolraw_sig_reg[11]_0\(3),
      I2 => \^ncolraw_sig_reg[11]_0\(0),
      I3 => \^ncolraw_sig_reg[11]_0\(1),
      I4 => \^ncolraw_sig_reg[11]_0\(2),
      I5 => \^ncolraw_sig_reg[11]_0\(4),
      O => \i[7]_i_14_n_0\
    );
\i[7]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(8),
      I1 => \^ncolraw_sig_reg[11]_0\(6),
      I2 => \i[7]_i_14_n_0\,
      I3 => \^ncolraw_sig_reg[11]_0\(7),
      O => \i[7]_i_15_n_0\
    );
\i[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(2),
      I1 => \^ncolraw_sig_reg[11]_0\(1),
      I2 => \^ncolraw_sig_reg[11]_0\(0),
      O => \i[7]_i_16_n_0\
    );
\i[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010010110"
    )
        port map (
      I0 => \i[7]_i_6_n_0\,
      I1 => \i[7]_i_7_n_0\,
      I2 => \i[7]_i_3_0\(5),
      I3 => \i[7]_i_8_n_0\,
      I4 => \^ncolraw_sig_reg[11]_0\(8),
      I5 => \i[7]_i_9_n_0\,
      O => \col_reg[8]\
    );
\i[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFEFEFFBFBFEFEBF"
    )
        port map (
      I0 => \i[7]_i_12_n_0\,
      I1 => \i[7]_i_3_0\(2),
      I2 => \^ncolraw_sig_reg[11]_0\(6),
      I3 => \i[7]_i_13_n_0\,
      I4 => \^ncolraw_sig_reg[11]_0\(5),
      I5 => \i[7]_i_3_0\(3),
      O => \i[7]_i_6_n_0\
    );
\i[7]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A9"
    )
        port map (
      I0 => \i[7]_i_3_0\(4),
      I1 => \^ncolraw_sig_reg[11]_0\(6),
      I2 => \i[7]_i_14_n_0\,
      I3 => \^ncolraw_sig_reg[11]_0\(7),
      O => \i[7]_i_7_n_0\
    );
\i[7]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(7),
      I1 => \i[7]_i_14_n_0\,
      I2 => \^ncolraw_sig_reg[11]_0\(6),
      O => \i[7]_i_8_n_0\
    );
\i[7]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"9EF7F79E"
    )
        port map (
      I0 => \i[7]_i_3_0\(6),
      I1 => \i[7]_i_15_n_0\,
      I2 => \^ncolraw_sig_reg[11]_0\(9),
      I3 => \^ncolraw_sig_reg[11]_0\(10),
      I4 => \i[7]_i_3_0\(7),
      O => \i[7]_i_9_n_0\
    );
rgbToManyAXIS_tlast_sig_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0480804040080804"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(6),
      I1 => rgbToManyAXIS_tlast_sig_i_6_n_0,
      I2 => rgbToManyAXIS_tlast_sig_i_2(4),
      I3 => rgbToManyAXIS_tlast_sig_i_2_0,
      I4 => rgbToManyAXIS_tlast_sig_i_2(3),
      I5 => \^ncolraw_sig_reg[11]_0\(7),
      O => \NColRaw_sig_reg[7]_0\
    );
rgbToManyAXIS_tlast_sig_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1001000000001001"
    )
        port map (
      I0 => rgbToManyAXIS_tlast_sig_i_7_n_0,
      I1 => rgbToManyAXIS_tlast_sig_i_4_0,
      I2 => \^ncolraw_sig_reg[11]_0\(4),
      I3 => rgbToManyAXIS_tlast_sig_i_4_1,
      I4 => rgbToManyAXIS_tlast_sig_i_4_2,
      I5 => \^ncolraw_sig_reg[11]_0\(5),
      O => rgbToManyAXIS_tlast_sig_i_6_n_0
    );
rgbToManyAXIS_tlast_sig_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7BFFDEFEFF7BFFD"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(0),
      I1 => \^ncolraw_sig_reg[11]_0\(2),
      I2 => rgbToManyAXIS_tlast_sig_i_2(0),
      I3 => rgbToManyAXIS_tlast_sig_i_2(1),
      I4 => rgbToManyAXIS_tlast_sig_i_2(2),
      I5 => \^ncolraw_sig_reg[11]_0\(1),
      O => rgbToManyAXIS_tlast_sig_i_7_n_0
    );
rng_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => rng_sig_reg_2,
      Q => \^rng\
    );
\row[11]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5556"
    )
        port map (
      I0 => \^q\(8),
      I1 => \^q\(6),
      I2 => \stateLive[1]_i_13_n_0\,
      I3 => \^q\(7),
      O => \row[11]_i_10_n_0\
    );
\row[11]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"56"
    )
        port map (
      I0 => \^q\(7),
      I1 => \stateLive[1]_i_13_n_0\,
      I2 => \^q\(6),
      O => \row[11]_i_11_n_0\
    );
\row[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000900090000"
    )
        port map (
      I0 => \^nrowraw_sig_reg[11]_0\,
      I1 => \row_reg[0]\(8),
      I2 => \row[11]_i_8_n_0\,
      I3 => \row[11]_i_9_n_0\,
      I4 => \row_reg[0]\(7),
      I5 => \^nrowraw_sig_reg[10]_0\,
      O => \row_reg[11]\
    );
\row[11]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555556AAAAAAA9"
    )
        port map (
      I0 => \row_reg[0]\(6),
      I1 => \^q\(8),
      I2 => \^q\(6),
      I3 => \stateLive[1]_i_13_n_0\,
      I4 => \^q\(7),
      I5 => \^q\(9),
      O => \row[11]_i_8_n_0\
    );
\row[11]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF9FFF9FFFF"
    )
        port map (
      I0 => \row[11]_i_10_n_0\,
      I1 => \row_reg[0]\(5),
      I2 => \stateSynth[2]_i_16_n_0\,
      I3 => \stateSynth[2]_i_15_n_0\,
      I4 => \row_reg[0]\(4),
      I5 => \row[11]_i_11_n_0\,
      O => \row[11]_i_9_n_0\
    );
\seq[1][5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng\,
      I1 => commok,
      O => rng_sig_reg_0
    );
\stateImdstream[2]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF69F6FF6FFFF"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(2),
      I1 => \aImdbufB_reg[0]\(2),
      I2 => \aImdbufB_reg[0]\(1),
      I3 => \^ncolraw_sig_reg[11]_0\(1),
      I4 => \^ncolraw_sig_reg[11]_0\(0),
      I5 => \aImdbufB_reg[0]\(0),
      O => \stateImdstream[2]_i_10_n_0\
    );
\stateImdstream[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF6F6FFF9FFFFF6"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(10),
      I1 => \aImdbufB_reg[0]\(10),
      I2 => \stateImdstream[2]_i_4_n_0\,
      I3 => \aImdbufB_reg[0]\(9),
      I4 => \^ncolraw_sig_reg[8]_0\,
      I5 => \^ncolraw_sig_reg[11]_0\(9),
      O => \NColRaw_sig_reg[11]_1\
    );
\stateImdstream[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF6F6FFF9FFFFF6"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(8),
      I1 => \aImdbufB_reg[0]\(8),
      I2 => \stateImdstream[2]_i_6_n_0\,
      I3 => \aImdbufB_reg[0]\(7),
      I4 => \stateImdstream[2]_i_7_n_0\,
      I5 => \^ncolraw_sig_reg[11]_0\(7),
      O => \stateImdstream[2]_i_4_n_0\
    );
\stateImdstream[2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(7),
      I1 => \^ncolraw_sig_reg[11]_0\(5),
      I2 => \stateImdstream[2]_i_8_n_0\,
      I3 => \^ncolraw_sig_reg[11]_0\(6),
      I4 => \^ncolraw_sig_reg[11]_0\(8),
      O => \^ncolraw_sig_reg[8]_0\
    );
\stateImdstream[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EBFEFFBFFFBFEBFE"
    )
        port map (
      I0 => \stateImdstream[2]_i_9_n_0\,
      I1 => \aImdbufB_reg[0]\(5),
      I2 => \stateImdstream[2]_i_8_n_0\,
      I3 => \^ncolraw_sig_reg[11]_0\(5),
      I4 => \^ncolraw_sig_reg[11]_0\(6),
      I5 => \aImdbufB_reg[0]\(6),
      O => \stateImdstream[2]_i_6_n_0\
    );
\stateImdstream[2]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(5),
      I1 => \stateImdstream[2]_i_8_n_0\,
      I2 => \^ncolraw_sig_reg[11]_0\(6),
      O => \stateImdstream[2]_i_7_n_0\
    );
\stateImdstream[2]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(3),
      I1 => \^ncolraw_sig_reg[11]_0\(1),
      I2 => \^ncolraw_sig_reg[11]_0\(0),
      I3 => \^ncolraw_sig_reg[11]_0\(2),
      I4 => \^ncolraw_sig_reg[11]_0\(4),
      O => \stateImdstream[2]_i_8_n_0\
    );
\stateImdstream[2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF66F9FF6"
    )
        port map (
      I0 => \^ncolraw_sig_reg[11]_0\(4),
      I1 => \aImdbufB_reg[0]\(4),
      I2 => \aImdbufB_reg[0]\(3),
      I3 => \^ncolraw_sig_reg[2]_0\,
      I4 => \^ncolraw_sig_reg[11]_0\(3),
      I5 => \stateImdstream[2]_i_10_n_0\,
      O => \stateImdstream[2]_i_9_n_0\
    );
\stateLive[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFEFEFFBFBFEFEBF"
    )
        port map (
      I0 => \stateLive[1]_i_17_n_0\,
      I1 => \i_reg[0]__1\(2),
      I2 => \^q\(6),
      I3 => \stateLive[1]_i_18_n_0\,
      I4 => \^q\(5),
      I5 => \i_reg[0]__1\(3),
      O => \stateLive[1]_i_11_n_0\
    );
\stateLive[1]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^q\(6),
      I1 => \stateLive[1]_i_13_n_0\,
      O => \stateLive[1]_i_12_n_0\
    );
\stateLive[1]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^q\(5),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(4),
      O => \stateLive[1]_i_13_n_0\
    );
\stateLive[1]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^q\(9),
      I1 => \^q\(7),
      I2 => \stateLive[1]_i_13_n_0\,
      I3 => \^q\(6),
      I4 => \^q\(8),
      O => \stateLive[1]_i_14_n_0\
    );
\stateLive[1]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF6FF6F69F"
    )
        port map (
      I0 => \^q\(4),
      I1 => \i_reg[0]__1\(1),
      I2 => \i_reg[0]__1\(0),
      I3 => \stateLive[1]_i_19_n_0\,
      I4 => \^q\(3),
      I5 => \stateLive[1]_i_11_0\,
      O => \stateLive[1]_i_17_n_0\
    );
\stateLive[1]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(3),
      O => \stateLive[1]_i_18_n_0\
    );
\stateLive[1]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \stateLive[1]_i_19_n_0\
    );
\stateLive[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEFFFFFFFFFFEEF"
    )
        port map (
      I0 => \stateLive[1]_i_6_n_0\,
      I1 => \stateLive[1]_i_7_n_0\,
      I2 => \i_reg[0]__1\(7),
      I3 => \^nrowraw_sig_reg[10]_0\,
      I4 => \i_reg[0]__1\(8),
      I5 => \^nrowraw_sig_reg[11]_0\,
      O => \rowRaw_lcl_reg[10]\
    );
\stateLive[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFEFEFFDFDFEFEDF"
    )
        port map (
      I0 => \i_reg[0]__1\(4),
      I1 => \stateLive[1]_i_11_n_0\,
      I2 => \^q\(8),
      I3 => \stateLive[1]_i_12_n_0\,
      I4 => \^q\(7),
      I5 => \i_reg[0]__1\(5),
      O => \stateLive[1]_i_6_n_0\
    );
\stateLive[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555556AAAAAAA9"
    )
        port map (
      I0 => \i_reg[0]__1\(6),
      I1 => \^q\(8),
      I2 => \^q\(6),
      I3 => \stateLive[1]_i_13_n_0\,
      I4 => \^q\(7),
      I5 => \^q\(9),
      O => \stateLive[1]_i_7_n_0\
    );
\stateLive[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555556"
    )
        port map (
      I0 => \^q\(10),
      I1 => \^q\(8),
      I2 => \^q\(6),
      I3 => \stateLive[1]_i_13_n_0\,
      I4 => \^q\(7),
      I5 => \^q\(9),
      O => \^nrowraw_sig_reg[10]_0\
    );
\stateLive[1]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \^q\(11),
      I1 => \stateLive[1]_i_14_n_0\,
      I2 => \^q\(10),
      O => \^nrowraw_sig_reg[11]_0\
    );
\stateMaxsel[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555411455555555"
    )
        port map (
      I0 => enCoobuf_reg,
      I1 => \^q\(7),
      I2 => \stateMaxsel[0]_i_3_n_0\,
      I3 => \stateMaxsel[0]_i_2_0\(3),
      I4 => \stateMaxsel[0]_i_4_n_0\,
      I5 => \stateMaxsel[0]_i_5_n_0\,
      O => \NRowRaw_sig_reg[7]_0\
    );
\stateMaxsel[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \^q\(5),
      I1 => \^q\(3),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(4),
      I5 => \^q\(6),
      O => \stateMaxsel[0]_i_3_n_0\
    );
\stateMaxsel[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF96F6FF66FF6F6"
    )
        port map (
      I0 => \^q\(9),
      I1 => \stateMaxsel[0]_i_2_0\(5),
      I2 => \^q\(8),
      I3 => \^q\(7),
      I4 => \stateMaxsel[0]_i_3_n_0\,
      I5 => \stateMaxsel[0]_i_2_0\(4),
      O => \stateMaxsel[0]_i_4_n_0\
    );
\stateMaxsel[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2802008000802802"
    )
        port map (
      I0 => \stateMaxsel[0]_i_6_n_0\,
      I1 => \stateMaxsel[0]_i_2_0\(6),
      I2 => \stateMaxsel[0]_i_7_n_0\,
      I3 => \^q\(10),
      I4 => \^q\(11),
      I5 => \stateMaxsel[0]_i_2_0\(7),
      O => \stateMaxsel[0]_i_5_n_0\
    );
\stateMaxsel[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0009090006000009"
    )
        port map (
      I0 => \^q\(6),
      I1 => \stateMaxsel[0]_i_2_0\(2),
      I2 => \stateMaxsel[0]_i_8_n_0\,
      I3 => \stateMaxsel[0]_i_2_0\(1),
      I4 => \stateMaxsel[0]_i_9_n_0\,
      I5 => \^q\(5),
      O => \stateMaxsel[0]_i_6_n_0\
    );
\stateMaxsel[0]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^q\(8),
      I1 => \stateMaxsel[0]_i_3_n_0\,
      I2 => \^q\(7),
      I3 => \^q\(9),
      O => \stateMaxsel[0]_i_7_n_0\
    );
\stateMaxsel[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBEEEEEEEEB"
    )
        port map (
      I0 => \stateMaxsel[0]_i_6_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \stateMaxsel[0]_i_2_0\(0),
      O => \stateMaxsel[0]_i_8_n_0\
    );
\stateMaxsel[0]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(4),
      O => \stateMaxsel[0]_i_9_n_0\
    );
stateOp_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stateOp,
      CLR => AR(0),
      D => stateOp0_out,
      Q => \^stateop_reg_0\
    );
\stateSwap[2]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^q\(7),
      I1 => \stateSwap[2]_i_15_n_0\,
      I2 => \^q\(8),
      O => \stateSwap[2]_i_10_n_0\
    );
\stateSwap[2]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(5),
      O => \stateSwap[2]_i_11_n_0\
    );
\stateSwap[2]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7B7B7BBDDEDEDEE7"
    )
        port map (
      I0 => \stateSwap[2]_i_5_0\(7),
      I1 => \stateSwap[2]_i_5_0\(8),
      I2 => \^q\(8),
      I3 => \stateSwap[2]_i_15_n_0\,
      I4 => \^q\(7),
      I5 => \^q\(9),
      O => \stateSwap[2]_i_12_n_0\
    );
\stateSwap[2]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7BBDDEE7"
    )
        port map (
      I0 => \stateSwap[2]_i_5_0\(1),
      I1 => \stateSwap[2]_i_5_0\(2),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => \stateSwap[2]_i_13_n_0\
    );
\stateSwap[2]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(3),
      O => \stateSwap[2]_i_14_n_0\
    );
\stateSwap[2]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^q\(5),
      I1 => \^q\(3),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(4),
      I5 => \^q\(6),
      O => \stateSwap[2]_i_15_n_0\
    );
\stateSwap[2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFEB"
    )
        port map (
      I0 => \stateSwap[2]_i_7_n_0\,
      I1 => \stateSwap[2]_i_5_0\(0),
      I2 => \^q\(1),
      I3 => \stateSwap[2]_i_8_n_0\,
      I4 => \stateSwap[2]_i_9_n_0\,
      O => \row_lcl_reg[0]\
    );
\stateSwap[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"777BBBBDDDDEEEE7"
    )
        port map (
      I0 => \stateSwap[2]_i_5_0\(9),
      I1 => \stateSwap[2]_i_5_0\(10),
      I2 => \stateSwap[2]_i_10_n_0\,
      I3 => \^q\(9),
      I4 => \^q\(10),
      I5 => \^q\(11),
      O => \stateSwap[2]_i_7_n_0\
    );
\stateSwap[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF7EBDD7EB"
    )
        port map (
      I0 => \^q\(7),
      I1 => \stateSwap[2]_i_11_n_0\,
      I2 => \^q\(6),
      I3 => \stateSwap[2]_i_5_0\(6),
      I4 => \stateSwap[2]_i_5_0\(5),
      I5 => \stateSwap[2]_i_12_n_0\,
      O => \stateSwap[2]_i_8_n_0\
    );
\stateSwap[2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFEEFFBFBBFFEEF"
    )
        port map (
      I0 => \stateSwap[2]_i_13_n_0\,
      I1 => \^q\(5),
      I2 => \stateSwap[2]_i_14_n_0\,
      I3 => \^q\(4),
      I4 => \stateSwap[2]_i_5_0\(4),
      I5 => \stateSwap[2]_i_5_0\(3),
      O => \stateSwap[2]_i_9_n_0\
    );
\stateSynth[2]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF9"
    )
        port map (
      I0 => \stateSynth[2]_i_13_n_0\,
      I1 => \row_reg[0]\(6),
      I2 => \stateSynth[2]_i_14_n_0\,
      I3 => \stateSynth[2]_i_15_n_0\,
      I4 => \stateSynth[2]_i_16_n_0\,
      I5 => \stateSynth[2]_i_17_n_0\,
      O => \row_reg[9]\
    );
\stateSynth[2]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55555556"
    )
        port map (
      I0 => \^q\(9),
      I1 => \^q\(7),
      I2 => \stateLive[1]_i_13_n_0\,
      I3 => \^q\(6),
      I4 => \^q\(8),
      O => \stateSynth[2]_i_13_n_0\
    );
\stateSynth[2]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A9"
    )
        port map (
      I0 => \row_reg[0]\(4),
      I1 => \^q\(6),
      I2 => \stateLive[1]_i_13_n_0\,
      I3 => \^q\(7),
      O => \stateSynth[2]_i_14_n_0\
    );
\stateSynth[2]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \row_reg[0]\(3),
      I1 => \stateLive[1]_i_13_n_0\,
      I2 => \^q\(6),
      O => \stateSynth[2]_i_15_n_0\
    );
\stateSynth[2]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF9FFF9FFFF"
    )
        port map (
      I0 => \stateSynth[2]_i_18_n_0\,
      I1 => \row_reg[0]\(2),
      I2 => \stateSynth[2]_i_12_0\,
      I3 => \stateSynth[2]_i_20_n_0\,
      I4 => \row_reg[0]\(1),
      I5 => \stateSynth[2]_i_21_n_0\,
      O => \stateSynth[2]_i_16_n_0\
    );
\stateSynth[2]_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5556AAA9"
    )
        port map (
      I0 => \row_reg[0]\(5),
      I1 => \^q\(7),
      I2 => \stateLive[1]_i_13_n_0\,
      I3 => \^q\(6),
      I4 => \^q\(8),
      O => \stateSynth[2]_i_17_n_0\
    );
\stateSynth[2]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555556"
    )
        port map (
      I0 => \^q\(5),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(4),
      O => \stateSynth[2]_i_18_n_0\
    );
\stateSynth[2]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5556AAA9"
    )
        port map (
      I0 => \row_reg[0]\(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(3),
      O => \stateSynth[2]_i_20_n_0\
    );
\stateSynth[2]_i_21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55555556"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(3),
      O => \stateSynth[2]_i_21_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^rng\,
      I1 => \toVideoinAXIS_tdata_sig_reg[23]\(0),
      O => rng_sig_reg_1(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_I2cmaster_v1_0 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \recv_sig_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    scl : inout STD_LOGIC;
    sda : inout STD_LOGIC;
    \stateConfig_reg[0]\ : in STD_LOGIC;
    \stateConfig_reg[0]_0\ : in STD_LOGIC;
    \stateConfig_reg[0]_1\ : in STD_LOGIC;
    \stateConfig_reg[0]_2\ : in STD_LOGIC;
    \stateConfig_reg[0]_3\ : in STD_LOGIC;
    \i2cSend_reg[0]\ : in STD_LOGIC;
    \i2cSend_reg[7]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \i2cSend_reg[0]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \i2cSend_reg[1]\ : in STD_LOGIC;
    \i2cSend_reg[2]\ : in STD_LOGIC;
    \i2cSend_reg[3]\ : in STD_LOGIC;
    \i2cSend_reg[4]\ : in STD_LOGIC;
    \i2cSend_reg[5]\ : in STD_LOGIC;
    \i2cSend_reg[6]\ : in STD_LOGIC;
    \i2cSend_reg[7]_0\ : in STD_LOGIC;
    \stateConfig_reg[0]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    tkclk : in STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    sda_sig_reg_0 : in STD_LOGIC;
    i2cReadNotWrite : in STD_LOGIC;
    sda_sig_i_16_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    sda_sig_i_12_0 : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_I2cmaster_v1_0 : entity is "I2cmaster_v1_0";
end design_1_Vsp_core_0_0_I2cmaster_v1_0;

architecture STRUCTURE of design_1_Vsp_core_0_0_I2cmaster_v1_0 is
  signal \FSM_sequential_elem[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_elem[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_elem[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_elem[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_elem[2]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_elem[2]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_elem[2]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_elem[2]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_elem[2]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_elem[2]_i_9_n_0\ : STD_LOGIC;
  signal T : STD_LOGIC;
  signal bitcnt : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \bitcnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \bitcnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \bitcnt[1]_i_2_n_0\ : STD_LOGIC;
  signal \bitcnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \bitcnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \bitcnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \bitcnt[3]_i_3_n_0\ : STD_LOGIC;
  signal dne : STD_LOGIC;
  signal \elem__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal i : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal i2cRecv : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \i[3]_i_2_n_0\ : STD_LOGIC;
  signal \i[4]_i_2_n_0\ : STD_LOGIC;
  signal \i[4]_i_3_n_0\ : STD_LOGIC;
  signal \i[5]_i_2_n_0\ : STD_LOGIC;
  signal \i[6]_i_2_n_0\ : STD_LOGIC;
  signal \i[7]_i_2_n_0\ : STD_LOGIC;
  signal \i[8]_i_2_n_0\ : STD_LOGIC;
  signal \i[9]_i_1_n_0\ : STD_LOGIC;
  signal \i[9]_i_3_n_0\ : STD_LOGIC;
  signal \i[9]_i_4_n_0\ : STD_LOGIC;
  signal imax : STD_LOGIC_VECTOR ( 8 downto 4 );
  signal p_1_in : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal recv_sig1 : STD_LOGIC;
  signal \recv_sig[0]_i_1_n_0\ : STD_LOGIC;
  signal \recv_sig[1]_i_1_n_0\ : STD_LOGIC;
  signal \recv_sig[2]_i_1_n_0\ : STD_LOGIC;
  signal \recv_sig[3]_i_1_n_0\ : STD_LOGIC;
  signal \recv_sig[4]_i_1_n_0\ : STD_LOGIC;
  signal \recv_sig[5]_i_1_n_0\ : STD_LOGIC;
  signal \recv_sig[6]_i_1_n_0\ : STD_LOGIC;
  signal \recv_sig[7]_i_1_n_0\ : STD_LOGIC;
  signal \recv_sig[7]_i_2_n_0\ : STD_LOGIC;
  signal \recv_sig[7]_i_3_n_0\ : STD_LOGIC;
  signal recvraw : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \recvraw[0]_i_1_n_0\ : STD_LOGIC;
  signal \recvraw[1]_i_1_n_0\ : STD_LOGIC;
  signal \recvraw[2]_i_1_n_0\ : STD_LOGIC;
  signal \recvraw[3]_i_1_n_0\ : STD_LOGIC;
  signal \recvraw[3]_i_2_n_0\ : STD_LOGIC;
  signal \recvraw[3]_i_3_n_0\ : STD_LOGIC;
  signal \recvraw[4]_i_1_n_0\ : STD_LOGIC;
  signal \recvraw[4]_i_2_n_0\ : STD_LOGIC;
  signal \recvraw[5]_i_1_n_0\ : STD_LOGIC;
  signal \recvraw[5]_i_2_n_0\ : STD_LOGIC;
  signal \recvraw[6]_i_1_n_0\ : STD_LOGIC;
  signal \recvraw[6]_i_2_n_0\ : STD_LOGIC;
  signal \recvraw[7]_i_1_n_0\ : STD_LOGIC;
  signal \recvraw[7]_i_2_n_0\ : STD_LOGIC;
  signal \recvraw[7]_i_3_n_0\ : STD_LOGIC;
  signal \recvraw[7]_i_4_n_0\ : STD_LOGIC;
  signal req : STD_LOGIC;
  signal sda_in : STD_LOGIC;
  signal sda_sig_i_10_n_0 : STD_LOGIC;
  signal sda_sig_i_11_n_0 : STD_LOGIC;
  signal sda_sig_i_12_n_0 : STD_LOGIC;
  signal sda_sig_i_13_n_0 : STD_LOGIC;
  signal sda_sig_i_14_n_0 : STD_LOGIC;
  signal sda_sig_i_15_n_0 : STD_LOGIC;
  signal sda_sig_i_16_n_0 : STD_LOGIC;
  signal sda_sig_i_17_n_0 : STD_LOGIC;
  signal sda_sig_i_18_n_0 : STD_LOGIC;
  signal sda_sig_i_19_n_0 : STD_LOGIC;
  signal sda_sig_i_1_n_0 : STD_LOGIC;
  signal sda_sig_i_20_n_0 : STD_LOGIC;
  signal sda_sig_i_21_n_0 : STD_LOGIC;
  signal sda_sig_i_22_n_0 : STD_LOGIC;
  signal sda_sig_i_23_n_0 : STD_LOGIC;
  signal sda_sig_i_24_n_0 : STD_LOGIC;
  signal sda_sig_i_25_n_0 : STD_LOGIC;
  signal sda_sig_i_26_n_0 : STD_LOGIC;
  signal sda_sig_i_27_n_0 : STD_LOGIC;
  signal sda_sig_i_28_n_0 : STD_LOGIC;
  signal sda_sig_i_29_n_0 : STD_LOGIC;
  signal sda_sig_i_2_n_0 : STD_LOGIC;
  signal sda_sig_i_30_n_0 : STD_LOGIC;
  signal sda_sig_i_31_n_0 : STD_LOGIC;
  signal sda_sig_i_34_n_0 : STD_LOGIC;
  signal sda_sig_i_35_n_0 : STD_LOGIC;
  signal sda_sig_i_36_n_0 : STD_LOGIC;
  signal sda_sig_i_37_n_0 : STD_LOGIC;
  signal sda_sig_i_38_n_0 : STD_LOGIC;
  signal sda_sig_i_39_n_0 : STD_LOGIC;
  signal sda_sig_i_3_n_0 : STD_LOGIC;
  signal sda_sig_i_40_n_0 : STD_LOGIC;
  signal sda_sig_i_41_n_0 : STD_LOGIC;
  signal sda_sig_i_42_n_0 : STD_LOGIC;
  signal sda_sig_i_43_n_0 : STD_LOGIC;
  signal sda_sig_i_44_n_0 : STD_LOGIC;
  signal sda_sig_i_45_n_0 : STD_LOGIC;
  signal sda_sig_i_46_n_0 : STD_LOGIC;
  signal sda_sig_i_47_n_0 : STD_LOGIC;
  signal sda_sig_i_4_n_0 : STD_LOGIC;
  signal sda_sig_i_5_n_0 : STD_LOGIC;
  signal sda_sig_i_6_n_0 : STD_LOGIC;
  signal sda_sig_i_7_n_0 : STD_LOGIC;
  signal sda_sig_i_8_n_0 : STD_LOGIC;
  signal sda_sig_i_9_n_0 : STD_LOGIC;
  signal sda_sig_reg_i_32_n_0 : STD_LOGIC;
  signal sda_sig_reg_i_33_n_0 : STD_LOGIC;
  signal sda_sig_reg_n_0 : STD_LOGIC;
  signal \stateConfig[3]_i_4_n_0\ : STD_LOGIC;
  signal \stateXfer[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateXfer[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateXfer[1]_i_2_n_0\ : STD_LOGIC;
  signal \stateXfer[2]_i_1_n_0\ : STD_LOGIC;
  signal \stateXfer[2]_i_2_n_0\ : STD_LOGIC;
  signal \stateXfer[2]_i_3_n_0\ : STD_LOGIC;
  signal \stateXfer[2]_i_4_n_0\ : STD_LOGIC;
  signal \stateXfer[3]_i_1_n_0\ : STD_LOGIC;
  signal \stateXfer[3]_i_2_n_0\ : STD_LOGIC;
  signal \stateXfer[3]_i_3_n_0\ : STD_LOGIC;
  signal \stateXfer_reg_n_0_[0]\ : STD_LOGIC;
  signal \stateXfer_reg_n_0_[1]\ : STD_LOGIC;
  signal \stateXfer_reg_n_0_[2]\ : STD_LOGIC;
  signal \stateXfer_reg_n_0_[3]\ : STD_LOGIC;
  signal NLW_myIobufScl_O_UNCONNECTED : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_elem[0]_i_1\ : label is "soft_lutpair594";
  attribute SOFT_HLUTNM of \FSM_sequential_elem[1]_i_1\ : label is "soft_lutpair602";
  attribute SOFT_HLUTNM of \FSM_sequential_elem[2]_i_2\ : label is "soft_lutpair594";
  attribute SOFT_HLUTNM of \FSM_sequential_elem[2]_i_4\ : label is "soft_lutpair603";
  attribute SOFT_HLUTNM of \FSM_sequential_elem[2]_i_5\ : label is "soft_lutpair595";
  attribute SOFT_HLUTNM of \FSM_sequential_elem[2]_i_9\ : label is "soft_lutpair597";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_elem_reg[0]\ : label is "iSTATE:110,iSTATE0:000,iSTATE1:100,iSTATE2:011,iSTATE3:101,iSTATE4:010,iSTATE5:001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_elem_reg[1]\ : label is "iSTATE:110,iSTATE0:000,iSTATE1:100,iSTATE2:011,iSTATE3:101,iSTATE4:010,iSTATE5:001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_elem_reg[2]\ : label is "iSTATE:110,iSTATE0:000,iSTATE1:100,iSTATE2:011,iSTATE3:101,iSTATE4:010,iSTATE5:001";
  attribute SOFT_HLUTNM of \bitcnt[1]_i_2\ : label is "soft_lutpair600";
  attribute SOFT_HLUTNM of \bitcnt[2]_i_1\ : label is "soft_lutpair599";
  attribute SOFT_HLUTNM of \bitcnt[3]_i_3\ : label is "soft_lutpair606";
  attribute SOFT_HLUTNM of \i[2]_i_1\ : label is "soft_lutpair604";
  attribute SOFT_HLUTNM of \i[3]_i_2\ : label is "soft_lutpair597";
  attribute SOFT_HLUTNM of \i[4]_i_2\ : label is "soft_lutpair598";
  attribute SOFT_HLUTNM of \i[4]_i_3\ : label is "soft_lutpair616";
  attribute SOFT_HLUTNM of \i[6]_i_2\ : label is "soft_lutpair596";
  attribute SOFT_HLUTNM of \i[7]_i_2\ : label is "soft_lutpair596";
  attribute box_type : string;
  attribute box_type of myIobufScl : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of myIobufScl_i_1 : label is "soft_lutpair595";
  attribute box_type of myIobufSda : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \recv_sig[7]_i_3\ : label is "soft_lutpair616";
  attribute SOFT_HLUTNM of \regVal[1]_i_1\ : label is "soft_lutpair615";
  attribute SOFT_HLUTNM of \regVal[2]_i_1\ : label is "soft_lutpair615";
  attribute SOFT_HLUTNM of \regVal[3]_i_1\ : label is "soft_lutpair614";
  attribute SOFT_HLUTNM of \regVal[4]_i_1\ : label is "soft_lutpair614";
  attribute SOFT_HLUTNM of \regVal[5]_i_1\ : label is "soft_lutpair613";
  attribute SOFT_HLUTNM of \regVal[6]_i_1\ : label is "soft_lutpair613";
  attribute SOFT_HLUTNM of \regVal[7]_i_2\ : label is "soft_lutpair603";
  attribute SOFT_HLUTNM of sda_sig_i_10 : label is "soft_lutpair610";
  attribute SOFT_HLUTNM of sda_sig_i_11 : label is "soft_lutpair602";
  attribute SOFT_HLUTNM of sda_sig_i_15 : label is "soft_lutpair611";
  attribute SOFT_HLUTNM of sda_sig_i_18 : label is "soft_lutpair605";
  attribute SOFT_HLUTNM of sda_sig_i_20 : label is "soft_lutpair610";
  attribute SOFT_HLUTNM of sda_sig_i_21 : label is "soft_lutpair604";
  attribute SOFT_HLUTNM of sda_sig_i_22 : label is "soft_lutpair608";
  attribute SOFT_HLUTNM of sda_sig_i_24 : label is "soft_lutpair608";
  attribute SOFT_HLUTNM of sda_sig_i_26 : label is "soft_lutpair609";
  attribute SOFT_HLUTNM of sda_sig_i_29 : label is "soft_lutpair600";
  attribute SOFT_HLUTNM of sda_sig_i_30 : label is "soft_lutpair601";
  attribute SOFT_HLUTNM of sda_sig_i_31 : label is "soft_lutpair607";
  attribute SOFT_HLUTNM of sda_sig_i_38 : label is "soft_lutpair605";
  attribute SOFT_HLUTNM of sda_sig_i_39 : label is "soft_lutpair612";
  attribute SOFT_HLUTNM of sda_sig_i_40 : label is "soft_lutpair607";
  attribute SOFT_HLUTNM of sda_sig_i_41 : label is "soft_lutpair609";
  attribute SOFT_HLUTNM of sda_sig_i_42 : label is "soft_lutpair599";
  attribute SOFT_HLUTNM of sda_sig_i_43 : label is "soft_lutpair598";
  attribute SOFT_HLUTNM of \stateConfig[3]_i_8\ : label is "soft_lutpair606";
  attribute SOFT_HLUTNM of \stateXfer[2]_i_3\ : label is "soft_lutpair601";
  attribute SOFT_HLUTNM of \stateXfer[2]_i_4\ : label is "soft_lutpair611";
  attribute SOFT_HLUTNM of \stateXfer[3]_i_3\ : label is "soft_lutpair612";
begin
\FSM_sequential_elem[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82028002"
    )
        port map (
      I0 => \FSM_sequential_elem[2]_i_5_n_0\,
      I1 => \elem__0\(1),
      I2 => \elem__0\(0),
      I3 => \elem__0\(2),
      I4 => i2cReadNotWrite,
      O => \FSM_sequential_elem[0]_i_1_n_0\
    );
\FSM_sequential_elem[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A82AAA2A"
    )
        port map (
      I0 => \FSM_sequential_elem[2]_i_5_n_0\,
      I1 => \elem__0\(1),
      I2 => \elem__0\(0),
      I3 => \elem__0\(2),
      I4 => i2cReadNotWrite,
      O => \FSM_sequential_elem[1]_i_1_n_0\
    );
\FSM_sequential_elem[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000043FFFFFFFF"
    )
        port map (
      I0 => \FSM_sequential_elem[2]_i_3_n_0\,
      I1 => \stateXfer_reg_n_0_[1]\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => req,
      O => \FSM_sequential_elem[2]_i_1_n_0\
    );
\FSM_sequential_elem[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA0080"
    )
        port map (
      I0 => \FSM_sequential_elem[2]_i_5_n_0\,
      I1 => \elem__0\(2),
      I2 => i2cReadNotWrite,
      I3 => \elem__0\(0),
      I4 => \elem__0\(1),
      O => \FSM_sequential_elem[2]_i_2_n_0\
    );
\FSM_sequential_elem[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFE7"
    )
        port map (
      I0 => \i[8]_i_2_n_0\,
      I1 => imax(8),
      I2 => \i[9]_i_3_n_0\,
      I3 => \FSM_sequential_elem[2]_i_6_n_0\,
      I4 => \FSM_sequential_elem[2]_i_7_n_0\,
      I5 => \FSM_sequential_elem[2]_i_8_n_0\,
      O => \FSM_sequential_elem[2]_i_3_n_0\
    );
\FSM_sequential_elem[2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => Q(3),
      I1 => Q(2),
      I2 => Q(0),
      I3 => Q(1),
      O => req
    );
\FSM_sequential_elem[2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => req,
      I1 => \stateXfer_reg_n_0_[3]\,
      I2 => \stateXfer_reg_n_0_[0]\,
      I3 => \stateXfer_reg_n_0_[2]\,
      I4 => \stateXfer_reg_n_0_[1]\,
      O => \FSM_sequential_elem[2]_i_5_n_0\
    );
\FSM_sequential_elem[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"426A6A6AAAAAAAAA"
    )
        port map (
      I0 => i(7),
      I1 => \FSM_sequential_elem[2]_i_9_n_0\,
      I2 => i(5),
      I3 => \i[3]_i_2_n_0\,
      I4 => imax(7),
      I5 => i(6),
      O => \FSM_sequential_elem[2]_i_6_n_0\
    );
\FSM_sequential_elem[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF6FFFFFFFFF5FFF"
    )
        port map (
      I0 => i(4),
      I1 => i(3),
      I2 => i(0),
      I3 => imax(4),
      I4 => i(1),
      I5 => i(2),
      O => \FSM_sequential_elem[2]_i_7_n_0\
    );
\FSM_sequential_elem[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E00000000FFFFFFE"
    )
        port map (
      I0 => \i[3]_i_2_n_0\,
      I1 => imax(7),
      I2 => i(6),
      I3 => \FSM_sequential_elem[2]_i_9_n_0\,
      I4 => i(5),
      I5 => i(7),
      O => \FSM_sequential_elem[2]_i_8_n_0\
    );
\FSM_sequential_elem[2]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => i(4),
      I1 => i(1),
      I2 => i(0),
      I3 => i(2),
      I4 => i(3),
      O => \FSM_sequential_elem[2]_i_9_n_0\
    );
\FSM_sequential_elem_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_sequential_elem[2]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \FSM_sequential_elem[0]_i_1_n_0\,
      Q => \elem__0\(0)
    );
\FSM_sequential_elem_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_sequential_elem[2]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \FSM_sequential_elem[1]_i_1_n_0\,
      Q => \elem__0\(1)
    );
\FSM_sequential_elem_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_sequential_elem[2]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \FSM_sequential_elem[2]_i_2_n_0\,
      Q => \elem__0\(2)
    );
\bitcnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000001000000"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[1]\,
      I1 => \stateXfer_reg_n_0_[0]\,
      I2 => \stateXfer_reg_n_0_[3]\,
      I3 => \stateXfer_reg_n_0_[2]\,
      I4 => req,
      I5 => bitcnt(0),
      O => \bitcnt[0]_i_1_n_0\
    );
\bitcnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[1]\,
      I1 => \stateXfer_reg_n_0_[0]\,
      I2 => \stateXfer_reg_n_0_[3]\,
      I3 => \stateXfer_reg_n_0_[2]\,
      I4 => req,
      I5 => \bitcnt[1]_i_2_n_0\,
      O => \bitcnt[1]_i_1_n_0\
    );
\bitcnt[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => bitcnt(0),
      I1 => bitcnt(1),
      O => \bitcnt[1]_i_2_n_0\
    );
\bitcnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04444000"
    )
        port map (
      I0 => \bitcnt[3]_i_3_n_0\,
      I1 => req,
      I2 => bitcnt(0),
      I3 => bitcnt(1),
      I4 => bitcnt(2),
      O => \bitcnt[2]_i_1_n_0\
    );
\bitcnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000057FFFFFFFF"
    )
        port map (
      I0 => \FSM_sequential_elem[2]_i_3_n_0\,
      I1 => \stateXfer_reg_n_0_[1]\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => req,
      O => \bitcnt[3]_i_1_n_0\
    );
\bitcnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0444444440000000"
    )
        port map (
      I0 => \bitcnt[3]_i_3_n_0\,
      I1 => req,
      I2 => bitcnt(1),
      I3 => bitcnt(0),
      I4 => bitcnt(2),
      I5 => bitcnt(3),
      O => \bitcnt[3]_i_2_n_0\
    );
\bitcnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[1]\,
      I1 => \stateXfer_reg_n_0_[0]\,
      I2 => \stateXfer_reg_n_0_[3]\,
      I3 => \stateXfer_reg_n_0_[2]\,
      O => \bitcnt[3]_i_3_n_0\
    );
\bitcnt_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bitcnt[3]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \bitcnt[0]_i_1_n_0\,
      Q => bitcnt(0)
    );
\bitcnt_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bitcnt[3]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \bitcnt[1]_i_1_n_0\,
      Q => bitcnt(1)
    );
\bitcnt_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bitcnt[3]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \bitcnt[2]_i_1_n_0\,
      Q => bitcnt(2)
    );
\bitcnt_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bitcnt[3]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \bitcnt[3]_i_2_n_0\,
      Q => bitcnt(3)
    );
\i2cSend[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"454045404540FFFF"
    )
        port map (
      I0 => \i2cSend_reg[0]\,
      I1 => \i2cSend_reg[7]\(0),
      I2 => \i2cSend_reg[7]\(8),
      I3 => i2cRecv(0),
      I4 => \i2cSend_reg[0]_0\,
      I5 => Q(3),
      O => D(0)
    );
\i2cSend[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"454045404540FFFF"
    )
        port map (
      I0 => \i2cSend_reg[0]\,
      I1 => \i2cSend_reg[7]\(1),
      I2 => \i2cSend_reg[7]\(9),
      I3 => i2cRecv(1),
      I4 => \i2cSend_reg[1]\,
      I5 => Q(3),
      O => D(1)
    );
\i2cSend[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"454045404540FFFF"
    )
        port map (
      I0 => \i2cSend_reg[0]\,
      I1 => \i2cSend_reg[7]\(2),
      I2 => \i2cSend_reg[7]\(10),
      I3 => i2cRecv(2),
      I4 => \i2cSend_reg[2]\,
      I5 => Q(3),
      O => D(2)
    );
\i2cSend[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"454045404540FFFF"
    )
        port map (
      I0 => \i2cSend_reg[0]\,
      I1 => \i2cSend_reg[7]\(3),
      I2 => \i2cSend_reg[7]\(11),
      I3 => i2cRecv(3),
      I4 => \i2cSend_reg[3]\,
      I5 => Q(3),
      O => D(3)
    );
\i2cSend[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"454045404540FFFF"
    )
        port map (
      I0 => \i2cSend_reg[0]\,
      I1 => \i2cSend_reg[7]\(4),
      I2 => \i2cSend_reg[7]\(12),
      I3 => i2cRecv(4),
      I4 => \i2cSend_reg[4]\,
      I5 => Q(3),
      O => D(4)
    );
\i2cSend[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"454045404540FFFF"
    )
        port map (
      I0 => \i2cSend_reg[0]\,
      I1 => \i2cSend_reg[7]\(5),
      I2 => \i2cSend_reg[7]\(13),
      I3 => i2cRecv(5),
      I4 => \i2cSend_reg[5]\,
      I5 => Q(3),
      O => D(5)
    );
\i2cSend[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"454045404540FFFF"
    )
        port map (
      I0 => \i2cSend_reg[0]\,
      I1 => \i2cSend_reg[7]\(6),
      I2 => \i2cSend_reg[7]\(14),
      I3 => i2cRecv(6),
      I4 => \i2cSend_reg[6]\,
      I5 => Q(3),
      O => D(6)
    );
\i2cSend[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"454045404540FFFF"
    )
        port map (
      I0 => \i2cSend_reg[0]\,
      I1 => \i2cSend_reg[7]\(7),
      I2 => \i2cSend_reg[7]\(15),
      I3 => i2cRecv(7),
      I4 => \i2cSend_reg[7]_0\,
      I5 => Q(3),
      O => D(7)
    );
\i[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFE0000"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[1]\,
      I1 => \stateXfer_reg_n_0_[2]\,
      I2 => \stateXfer_reg_n_0_[0]\,
      I3 => \stateXfer_reg_n_0_[3]\,
      I4 => req,
      I5 => i(0),
      O => p_1_in(0)
    );
\i[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6060606000600000"
    )
        port map (
      I0 => i(1),
      I1 => i(0),
      I2 => \FSM_sequential_elem[2]_i_5_n_0\,
      I3 => \i[4]_i_3_n_0\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => \FSM_sequential_elem[2]_i_3_n_0\,
      O => p_1_in(1)
    );
\i[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \FSM_sequential_elem[2]_i_5_n_0\,
      I1 => i(0),
      I2 => i(1),
      I3 => i(2),
      O => p_1_in(2)
    );
\i[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888888800000"
    )
        port map (
      I0 => \i[3]_i_2_n_0\,
      I1 => \FSM_sequential_elem[2]_i_5_n_0\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[1]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => \FSM_sequential_elem[2]_i_3_n_0\,
      O => p_1_in(3)
    );
\i[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => i(1),
      I1 => i(0),
      I2 => i(2),
      I3 => i(3),
      O => \i[3]_i_2_n_0\
    );
\i[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6060606000600000"
    )
        port map (
      I0 => \i[4]_i_2_n_0\,
      I1 => i(4),
      I2 => \FSM_sequential_elem[2]_i_5_n_0\,
      I3 => \i[4]_i_3_n_0\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => \FSM_sequential_elem[2]_i_3_n_0\,
      O => p_1_in(4)
    );
\i[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => i(3),
      I1 => i(2),
      I2 => i(0),
      I3 => i(1),
      O => \i[4]_i_2_n_0\
    );
\i[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[2]\,
      I1 => \stateXfer_reg_n_0_[1]\,
      O => \i[4]_i_3_n_0\
    );
\i[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888888800000"
    )
        port map (
      I0 => \i[5]_i_2_n_0\,
      I1 => \FSM_sequential_elem[2]_i_5_n_0\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[1]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => \FSM_sequential_elem[2]_i_3_n_0\,
      O => p_1_in(5)
    );
\i[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => i(5),
      I1 => i(3),
      I2 => i(2),
      I3 => i(0),
      I4 => i(1),
      I5 => i(4),
      O => \i[5]_i_2_n_0\
    );
\i[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888888800000"
    )
        port map (
      I0 => \i[6]_i_2_n_0\,
      I1 => \FSM_sequential_elem[2]_i_5_n_0\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[1]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => \FSM_sequential_elem[2]_i_3_n_0\,
      O => p_1_in(6)
    );
\i[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => i(6),
      I1 => i(4),
      I2 => \i[4]_i_2_n_0\,
      I3 => i(5),
      O => \i[6]_i_2_n_0\
    );
\i[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888888800000"
    )
        port map (
      I0 => \i[7]_i_2_n_0\,
      I1 => \FSM_sequential_elem[2]_i_5_n_0\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[1]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => \FSM_sequential_elem[2]_i_3_n_0\,
      O => p_1_in(7)
    );
\i[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => i(7),
      I1 => i(5),
      I2 => \i[4]_i_2_n_0\,
      I3 => i(4),
      I4 => i(6),
      O => \i[7]_i_2_n_0\
    );
\i[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888888800000"
    )
        port map (
      I0 => \i[8]_i_2_n_0\,
      I1 => \FSM_sequential_elem[2]_i_5_n_0\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[1]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => \FSM_sequential_elem[2]_i_3_n_0\,
      O => p_1_in(8)
    );
\i[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => i(8),
      I1 => i(6),
      I2 => i(4),
      I3 => \i[4]_i_2_n_0\,
      I4 => i(5),
      I5 => i(7),
      O => \i[8]_i_2_n_0\
    );
\i[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5777FFFF"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[3]\,
      I1 => \stateXfer_reg_n_0_[2]\,
      I2 => \stateXfer_reg_n_0_[1]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => req,
      O => \i[9]_i_1_n_0\
    );
\i[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444400000"
    )
        port map (
      I0 => \i[9]_i_3_n_0\,
      I1 => \FSM_sequential_elem[2]_i_5_n_0\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[1]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => \FSM_sequential_elem[2]_i_3_n_0\,
      O => p_1_in(9)
    );
\i[9]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"95555555"
    )
        port map (
      I0 => i(9),
      I1 => i(7),
      I2 => \i[9]_i_4_n_0\,
      I3 => i(6),
      I4 => i(8),
      O => \i[9]_i_3_n_0\
    );
\i[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => i(5),
      I1 => i(3),
      I2 => i(2),
      I3 => i(0),
      I4 => i(1),
      I5 => i(4),
      O => \i[9]_i_4_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => p_1_in(0),
      Q => i(0)
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => p_1_in(1),
      Q => i(1)
    );
\i_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => p_1_in(2),
      Q => i(2)
    );
\i_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => p_1_in(3),
      Q => i(3)
    );
\i_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => p_1_in(4),
      Q => i(4)
    );
\i_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => p_1_in(5),
      Q => i(5)
    );
\i_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => p_1_in(6),
      Q => i(6)
    );
\i_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => p_1_in(7),
      Q => i(7)
    );
\i_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => p_1_in(8),
      Q => i(8)
    );
\i_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => p_1_in(9),
      Q => i(9)
    );
\imax[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0001FFFF"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[1]\,
      I1 => \stateXfer_reg_n_0_[2]\,
      I2 => \stateXfer_reg_n_0_[0]\,
      I3 => \stateXfer_reg_n_0_[3]\,
      I4 => req,
      O => recv_sig1
    );
\imax_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => recv_sig1,
      CLR => sda_sig_reg_0,
      D => '1',
      Q => imax(4)
    );
\imax_reg[7]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => recv_sig1,
      D => '1',
      PRE => sda_sig_reg_0,
      Q => imax(7)
    );
\imax_reg[8]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => recv_sig1,
      D => '0',
      PRE => sda_sig_reg_0,
      Q => imax(8)
    );
myIobufScl: unisim.vcomponents.IOBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => '0',
      IO => scl,
      O => NLW_myIobufScl_O_UNCONNECTED,
      T => T
    );
myIobufScl_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBBD"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[3]\,
      I1 => \stateXfer_reg_n_0_[0]\,
      I2 => \stateXfer_reg_n_0_[1]\,
      I3 => \stateXfer_reg_n_0_[2]\,
      O => T
    );
myIobufSda: unisim.vcomponents.IOBUF
    generic map(
      IOSTANDARD => "DEFAULT"
    )
        port map (
      I => '0',
      IO => sda,
      O => sda_in,
      T => sda_sig_reg_n_0
    );
\recv_sig[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA800000000"
    )
        port map (
      I0 => recvraw(0),
      I1 => \stateXfer_reg_n_0_[1]\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => req,
      O => \recv_sig[0]_i_1_n_0\
    );
\recv_sig[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA800000000"
    )
        port map (
      I0 => recvraw(1),
      I1 => \stateXfer_reg_n_0_[1]\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => req,
      O => \recv_sig[1]_i_1_n_0\
    );
\recv_sig[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA800000000"
    )
        port map (
      I0 => recvraw(2),
      I1 => \stateXfer_reg_n_0_[1]\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => req,
      O => \recv_sig[2]_i_1_n_0\
    );
\recv_sig[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA800000000"
    )
        port map (
      I0 => recvraw(3),
      I1 => \stateXfer_reg_n_0_[1]\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => req,
      O => \recv_sig[3]_i_1_n_0\
    );
\recv_sig[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA800000000"
    )
        port map (
      I0 => recvraw(4),
      I1 => \stateXfer_reg_n_0_[1]\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => req,
      O => \recv_sig[4]_i_1_n_0\
    );
\recv_sig[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA800000000"
    )
        port map (
      I0 => recvraw(5),
      I1 => \stateXfer_reg_n_0_[1]\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => req,
      O => \recv_sig[5]_i_1_n_0\
    );
\recv_sig[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA800000000"
    )
        port map (
      I0 => recvraw(6),
      I1 => \stateXfer_reg_n_0_[1]\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => req,
      O => \recv_sig[6]_i_1_n_0\
    );
\recv_sig[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000040FFFFFFFF"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[2]\,
      I1 => \stateXfer_reg_n_0_[3]\,
      I2 => i2cReadNotWrite,
      I3 => \recv_sig[7]_i_3_n_0\,
      I4 => \FSM_sequential_elem[2]_i_3_n_0\,
      I5 => \FSM_sequential_elem[2]_i_5_n_0\,
      O => \recv_sig[7]_i_1_n_0\
    );
\recv_sig[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA800000000"
    )
        port map (
      I0 => recvraw(7),
      I1 => \stateXfer_reg_n_0_[1]\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => req,
      O => \recv_sig[7]_i_2_n_0\
    );
\recv_sig[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[0]\,
      I1 => \stateXfer_reg_n_0_[1]\,
      O => \recv_sig[7]_i_3_n_0\
    );
\recv_sig_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recv_sig[7]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \recv_sig[0]_i_1_n_0\,
      Q => i2cRecv(0)
    );
\recv_sig_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recv_sig[7]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \recv_sig[1]_i_1_n_0\,
      Q => i2cRecv(1)
    );
\recv_sig_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recv_sig[7]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \recv_sig[2]_i_1_n_0\,
      Q => i2cRecv(2)
    );
\recv_sig_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recv_sig[7]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \recv_sig[3]_i_1_n_0\,
      Q => i2cRecv(3)
    );
\recv_sig_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recv_sig[7]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \recv_sig[4]_i_1_n_0\,
      Q => i2cRecv(4)
    );
\recv_sig_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recv_sig[7]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \recv_sig[5]_i_1_n_0\,
      Q => i2cRecv(5)
    );
\recv_sig_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recv_sig[7]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \recv_sig[6]_i_1_n_0\,
      Q => i2cRecv(6)
    );
\recv_sig_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \recv_sig[7]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \recv_sig[7]_i_2_n_0\,
      Q => i2cRecv(7)
    );
\recvraw[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFF000002000000"
    )
        port map (
      I0 => sda_in,
      I1 => \recvraw[4]_i_2_n_0\,
      I2 => \recvraw[3]_i_2_n_0\,
      I3 => \recvraw[3]_i_3_n_0\,
      I4 => \FSM_sequential_elem[2]_i_5_n_0\,
      I5 => recvraw(0),
      O => \recvraw[0]_i_1_n_0\
    );
\recvraw[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFF000002000000"
    )
        port map (
      I0 => sda_in,
      I1 => \recvraw[5]_i_2_n_0\,
      I2 => \recvraw[3]_i_2_n_0\,
      I3 => \recvraw[3]_i_3_n_0\,
      I4 => \FSM_sequential_elem[2]_i_5_n_0\,
      I5 => recvraw(1),
      O => \recvraw[1]_i_1_n_0\
    );
\recvraw[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFF000002000000"
    )
        port map (
      I0 => sda_in,
      I1 => \recvraw[6]_i_2_n_0\,
      I2 => \recvraw[3]_i_2_n_0\,
      I3 => \recvraw[3]_i_3_n_0\,
      I4 => \FSM_sequential_elem[2]_i_5_n_0\,
      I5 => recvraw(2),
      O => \recvraw[2]_i_1_n_0\
    );
\recvraw[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFF000002000000"
    )
        port map (
      I0 => sda_in,
      I1 => \recvraw[7]_i_3_n_0\,
      I2 => \recvraw[3]_i_2_n_0\,
      I3 => \recvraw[3]_i_3_n_0\,
      I4 => \FSM_sequential_elem[2]_i_5_n_0\,
      I5 => recvraw(3),
      O => \recvraw[3]_i_1_n_0\
    );
\recvraw[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000100010001000"
    )
        port map (
      I0 => \elem__0\(1),
      I1 => \elem__0\(2),
      I2 => \elem__0\(0),
      I3 => i2cReadNotWrite,
      I4 => bitcnt(2),
      I5 => bitcnt(3),
      O => \recvraw[3]_i_2_n_0\
    );
\recvraw[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000100012001000"
    )
        port map (
      I0 => \elem__0\(1),
      I1 => \elem__0\(2),
      I2 => \elem__0\(0),
      I3 => i2cReadNotWrite,
      I4 => bitcnt(2),
      I5 => bitcnt(3),
      O => \recvraw[3]_i_3_n_0\
    );
\recvraw[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFF000002000000"
    )
        port map (
      I0 => sda_in,
      I1 => \recvraw[7]_i_2_n_0\,
      I2 => \recvraw[4]_i_2_n_0\,
      I3 => \recvraw[7]_i_4_n_0\,
      I4 => \FSM_sequential_elem[2]_i_5_n_0\,
      I5 => recvraw(4),
      O => \recvraw[4]_i_1_n_0\
    );
\recvraw[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDFFFFFFFFFFFF"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[2]\,
      I1 => \stateXfer_reg_n_0_[3]\,
      I2 => \stateXfer_reg_n_0_[0]\,
      I3 => \stateXfer_reg_n_0_[1]\,
      I4 => bitcnt(1),
      I5 => bitcnt(0),
      O => \recvraw[4]_i_2_n_0\
    );
\recvraw[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFF000002000000"
    )
        port map (
      I0 => sda_in,
      I1 => \recvraw[7]_i_2_n_0\,
      I2 => \recvraw[5]_i_2_n_0\,
      I3 => \recvraw[7]_i_4_n_0\,
      I4 => \FSM_sequential_elem[2]_i_5_n_0\,
      I5 => recvraw(5),
      O => \recvraw[5]_i_1_n_0\
    );
\recvraw[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFBFFFFFFFF"
    )
        port map (
      I0 => bitcnt(0),
      I1 => bitcnt(1),
      I2 => \stateXfer_reg_n_0_[1]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => \stateXfer_reg_n_0_[2]\,
      O => \recvraw[5]_i_2_n_0\
    );
\recvraw[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFF000002000000"
    )
        port map (
      I0 => sda_in,
      I1 => \recvraw[7]_i_2_n_0\,
      I2 => \recvraw[6]_i_2_n_0\,
      I3 => \recvraw[7]_i_4_n_0\,
      I4 => \FSM_sequential_elem[2]_i_5_n_0\,
      I5 => recvraw(6),
      O => \recvraw[6]_i_1_n_0\
    );
\recvraw[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFDFFFFFFFF"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[2]\,
      I1 => \stateXfer_reg_n_0_[3]\,
      I2 => \stateXfer_reg_n_0_[0]\,
      I3 => \stateXfer_reg_n_0_[1]\,
      I4 => bitcnt(1),
      I5 => bitcnt(0),
      O => \recvraw[6]_i_2_n_0\
    );
\recvraw[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFF000002000000"
    )
        port map (
      I0 => sda_in,
      I1 => \recvraw[7]_i_2_n_0\,
      I2 => \recvraw[7]_i_3_n_0\,
      I3 => \recvraw[7]_i_4_n_0\,
      I4 => \FSM_sequential_elem[2]_i_5_n_0\,
      I5 => recvraw(7),
      O => \recvraw[7]_i_1_n_0\
    );
\recvraw[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000D000000000000"
    )
        port map (
      I0 => bitcnt(3),
      I1 => bitcnt(2),
      I2 => \elem__0\(1),
      I3 => \elem__0\(2),
      I4 => \elem__0\(0),
      I5 => i2cReadNotWrite,
      O => \recvraw[7]_i_2_n_0\
    );
\recvraw[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFD"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[2]\,
      I1 => \stateXfer_reg_n_0_[3]\,
      I2 => \stateXfer_reg_n_0_[0]\,
      I3 => \stateXfer_reg_n_0_[1]\,
      I4 => bitcnt(1),
      I5 => bitcnt(0),
      O => \recvraw[7]_i_3_n_0\
    );
\recvraw[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000100010001200"
    )
        port map (
      I0 => \elem__0\(1),
      I1 => \elem__0\(2),
      I2 => \elem__0\(0),
      I3 => i2cReadNotWrite,
      I4 => bitcnt(3),
      I5 => bitcnt(2),
      O => \recvraw[7]_i_4_n_0\
    );
\recvraw_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg_0,
      D => \recvraw[0]_i_1_n_0\,
      Q => recvraw(0)
    );
\recvraw_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg_0,
      D => \recvraw[1]_i_1_n_0\,
      Q => recvraw(1)
    );
\recvraw_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg_0,
      D => \recvraw[2]_i_1_n_0\,
      Q => recvraw(2)
    );
\recvraw_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg_0,
      D => \recvraw[3]_i_1_n_0\,
      Q => recvraw(3)
    );
\recvraw_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg_0,
      D => \recvraw[4]_i_1_n_0\,
      Q => recvraw(4)
    );
\recvraw_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg_0,
      D => \recvraw[5]_i_1_n_0\,
      Q => recvraw(5)
    );
\recvraw_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg_0,
      D => \recvraw[6]_i_1_n_0\,
      Q => recvraw(6)
    );
\recvraw_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg_0,
      D => \recvraw[7]_i_1_n_0\,
      Q => recvraw(7)
    );
\regVal[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => i2cRecv(0),
      I1 => Q(3),
      O => \recv_sig_reg[7]_0\(0)
    );
\regVal[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => i2cRecv(1),
      I1 => Q(3),
      O => \recv_sig_reg[7]_0\(1)
    );
\regVal[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => i2cRecv(2),
      I1 => Q(3),
      O => \recv_sig_reg[7]_0\(2)
    );
\regVal[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => i2cRecv(3),
      I1 => Q(3),
      O => \recv_sig_reg[7]_0\(3)
    );
\regVal[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => i2cRecv(4),
      I1 => Q(3),
      O => \recv_sig_reg[7]_0\(4)
    );
\regVal[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => i2cRecv(5),
      I1 => Q(3),
      O => \recv_sig_reg[7]_0\(5)
    );
\regVal[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => i2cRecv(6),
      I1 => Q(3),
      O => \recv_sig_reg[7]_0\(6)
    );
\regVal[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => i2cRecv(7),
      I1 => Q(3),
      O => \recv_sig_reg[7]_0\(7)
    );
sda_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFFFEFEFE00"
    )
        port map (
      I0 => sda_sig_i_2_n_0,
      I1 => sda_sig_i_3_n_0,
      I2 => sda_sig_i_4_n_0,
      I3 => sda_sig_i_5_n_0,
      I4 => sda_sig_i_6_n_0,
      I5 => sda_sig_reg_n_0,
      O => sda_sig_i_1_n_0
    );
sda_sig_i_10: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1540"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[3]\,
      I1 => \stateXfer_reg_n_0_[2]\,
      I2 => \stateXfer_reg_n_0_[1]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      O => sda_sig_i_10_n_0
    );
sda_sig_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => i2cReadNotWrite,
      I1 => \elem__0\(0),
      I2 => \elem__0\(2),
      I3 => \elem__0\(1),
      O => sda_sig_i_11_n_0
    );
sda_sig_i_12: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555DDFD5555DFFF"
    )
        port map (
      I0 => sda_sig_i_22_n_0,
      I1 => bitcnt(3),
      I2 => bitcnt(2),
      I3 => sda_sig_i_23_n_0,
      I4 => sda_sig_i_24_n_0,
      I5 => sda_sig_i_25_n_0,
      O => sda_sig_i_12_n_0
    );
sda_sig_i_13: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF8A80"
    )
        port map (
      I0 => sda_sig_i_26_n_0,
      I1 => sda_sig_i_27_n_0,
      I2 => sda_sig_i_28_n_0,
      I3 => sda_sig_i_29_n_0,
      I4 => sda_sig_i_30_n_0,
      I5 => sda_sig_i_31_n_0,
      O => sda_sig_i_13_n_0
    );
sda_sig_i_14: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010100000001000"
    )
        port map (
      I0 => \elem__0\(1),
      I1 => \elem__0\(0),
      I2 => \elem__0\(2),
      I3 => sda_sig_reg_i_32_n_0,
      I4 => bitcnt(3),
      I5 => sda_sig_reg_i_33_n_0,
      O => sda_sig_i_14_n_0
    );
sda_sig_i_15: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \elem__0\(0),
      I1 => \elem__0\(1),
      I2 => \elem__0\(2),
      O => sda_sig_i_15_n_0
    );
sda_sig_i_16: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => sda_sig_i_34_n_0,
      I1 => sda_sig_i_35_n_0,
      I2 => sda_sig_i_26_n_0,
      I3 => sda_sig_i_36_n_0,
      I4 => sda_sig_i_28_n_0,
      I5 => sda_sig_i_37_n_0,
      O => sda_sig_i_16_n_0
    );
sda_sig_i_17: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5D5D5D555D5D5DDD"
    )
        port map (
      I0 => sda_sig_i_38_n_0,
      I1 => sda_sig_i_39_n_0,
      I2 => sda_sig_i_40_n_0,
      I3 => bitcnt(3),
      I4 => sda_sig_i_41_n_0,
      I5 => sda_sig_i_42_n_0,
      O => sda_sig_i_17_n_0
    );
sda_sig_i_18: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBB3"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[3]\,
      I1 => \stateXfer_reg_n_0_[0]\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[1]\,
      O => sda_sig_i_18_n_0
    );
sda_sig_i_19: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF577FA000"
    )
        port map (
      I0 => i(6),
      I1 => sda_sig_i_43_n_0,
      I2 => i(5),
      I3 => \FSM_sequential_elem[2]_i_9_n_0\,
      I4 => i(7),
      I5 => \FSM_sequential_elem[2]_i_7_n_0\,
      O => sda_sig_i_19_n_0
    );
sda_sig_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000003101"
    )
        port map (
      I0 => sda_sig_i_7_n_0,
      I1 => \FSM_sequential_elem[2]_i_7_n_0\,
      I2 => \i[7]_i_2_n_0\,
      I3 => sda_sig_i_8_n_0,
      I4 => sda_sig_i_9_n_0,
      I5 => sda_sig_i_10_n_0,
      O => sda_sig_i_2_n_0
    );
sda_sig_i_20: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[2]\,
      I1 => \stateXfer_reg_n_0_[3]\,
      O => sda_sig_i_20_n_0
    );
sda_sig_i_21: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => i(1),
      I1 => i(0),
      I2 => i(2),
      O => sda_sig_i_21_n_0
    );
sda_sig_i_22: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E7"
    )
        port map (
      I0 => \elem__0\(1),
      I1 => \elem__0\(0),
      I2 => \elem__0\(2),
      O => sda_sig_i_22_n_0
    );
sda_sig_i_23: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => sda_sig_i_12_0(0),
      I1 => sda_sig_i_12_0(1),
      I2 => bitcnt(1),
      I3 => sda_sig_i_12_0(2),
      I4 => bitcnt(0),
      I5 => sda_sig_i_12_0(3),
      O => sda_sig_i_23_n_0
    );
sda_sig_i_24: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFB"
    )
        port map (
      I0 => i2cReadNotWrite,
      I1 => \elem__0\(1),
      I2 => \elem__0\(2),
      I3 => \elem__0\(0),
      O => sda_sig_i_24_n_0
    );
sda_sig_i_25: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => sda_sig_i_12_0(4),
      I1 => sda_sig_i_12_0(5),
      I2 => bitcnt(1),
      I3 => sda_sig_i_12_0(6),
      I4 => bitcnt(0),
      I5 => sda_sig_i_12_0(7),
      O => sda_sig_i_25_n_0
    );
sda_sig_i_26: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => bitcnt(3),
      I1 => bitcnt(2),
      I2 => bitcnt(0),
      I3 => bitcnt(1),
      O => sda_sig_i_26_n_0
    );
sda_sig_i_27: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCAF0CAFFCA00CA0"
    )
        port map (
      I0 => sda_sig_i_12_0(6),
      I1 => sda_sig_i_12_0(5),
      I2 => bitcnt(0),
      I3 => bitcnt(1),
      I4 => sda_sig_i_12_0(4),
      I5 => sda_sig_i_12_0(3),
      O => sda_sig_i_27_n_0
    );
sda_sig_i_28: unisim.vcomponents.LUT3
    generic map(
      INIT => X"56"
    )
        port map (
      I0 => bitcnt(2),
      I1 => bitcnt(1),
      I2 => bitcnt(0),
      O => sda_sig_i_28_n_0
    );
sda_sig_i_29: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FCA00CA0"
    )
        port map (
      I0 => sda_sig_i_12_0(2),
      I1 => sda_sig_i_12_0(1),
      I2 => bitcnt(0),
      I3 => bitcnt(1),
      I4 => sda_sig_i_12_0(0),
      O => sda_sig_i_29_n_0
    );
sda_sig_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00001003FFFFFFFF"
    )
        port map (
      I0 => sda_sig_i_11_n_0,
      I1 => \stateXfer_reg_n_0_[1]\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => req,
      O => sda_sig_i_3_n_0
    );
sda_sig_i_30: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => bitcnt(0),
      I1 => bitcnt(1),
      I2 => sda_sig_i_12_0(7),
      I3 => bitcnt(3),
      I4 => bitcnt(2),
      O => sda_sig_i_30_n_0
    );
sda_sig_i_31: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFB"
    )
        port map (
      I0 => i2cReadNotWrite,
      I1 => \elem__0\(0),
      I2 => \elem__0\(2),
      I3 => \elem__0\(1),
      O => sda_sig_i_31_n_0
    );
sda_sig_i_34: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCAF0CAFFCA00CA0"
    )
        port map (
      I0 => sda_sig_i_16_0(6),
      I1 => sda_sig_i_16_0(5),
      I2 => bitcnt(0),
      I3 => bitcnt(1),
      I4 => sda_sig_i_16_0(4),
      I5 => sda_sig_i_16_0(3),
      O => sda_sig_i_34_n_0
    );
sda_sig_i_35: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCAF0CAFFCA00CA0"
    )
        port map (
      I0 => sda_sig_i_16_0(2),
      I1 => sda_sig_i_16_0(1),
      I2 => bitcnt(0),
      I3 => bitcnt(1),
      I4 => sda_sig_i_16_0(0),
      I5 => sda_sig_i_16_0(15),
      O => sda_sig_i_35_n_0
    );
sda_sig_i_36: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FACF0ACFFAC00AC0"
    )
        port map (
      I0 => sda_sig_i_16_0(13),
      I1 => sda_sig_i_16_0(14),
      I2 => bitcnt(0),
      I3 => bitcnt(1),
      I4 => sda_sig_i_16_0(12),
      I5 => sda_sig_i_16_0(11),
      O => sda_sig_i_36_n_0
    );
sda_sig_i_37: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCAF0CAFFCA00CA0"
    )
        port map (
      I0 => sda_sig_i_16_0(10),
      I1 => sda_sig_i_16_0(9),
      I2 => bitcnt(0),
      I3 => bitcnt(1),
      I4 => sda_sig_i_16_0(8),
      I5 => sda_sig_i_16_0(7),
      O => sda_sig_i_37_n_0
    );
sda_sig_i_38: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[2]\,
      I1 => \stateXfer_reg_n_0_[3]\,
      I2 => \stateXfer_reg_n_0_[1]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      O => sda_sig_i_38_n_0
    );
sda_sig_i_39: unisim.vcomponents.LUT3
    generic map(
      INIT => X"41"
    )
        port map (
      I0 => \elem__0\(1),
      I1 => \elem__0\(0),
      I2 => \elem__0\(2),
      O => sda_sig_i_39_n_0
    );
sda_sig_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFF4F4F4"
    )
        port map (
      I0 => sda_sig_i_12_n_0,
      I1 => sda_sig_i_13_n_0,
      I2 => sda_sig_i_14_n_0,
      I3 => sda_sig_i_15_n_0,
      I4 => sda_sig_i_16_n_0,
      I5 => sda_sig_i_17_n_0,
      O => sda_sig_i_4_n_0
    );
sda_sig_i_40: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => i2cReadNotWrite,
      I1 => \elem__0\(2),
      I2 => \elem__0\(1),
      I3 => \elem__0\(0),
      O => sda_sig_i_40_n_0
    );
sda_sig_i_41: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => bitcnt(1),
      I1 => bitcnt(0),
      I2 => bitcnt(2),
      O => sda_sig_i_41_n_0
    );
sda_sig_i_42: unisim.vcomponents.LUT3
    generic map(
      INIT => X"38"
    )
        port map (
      I0 => bitcnt(0),
      I1 => bitcnt(2),
      I2 => bitcnt(1),
      O => sda_sig_i_42_n_0
    );
sda_sig_i_43: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => imax(7),
      I1 => i(3),
      I2 => i(2),
      I3 => i(0),
      I4 => i(1),
      O => sda_sig_i_43_n_0
    );
sda_sig_i_44: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => sda_sig_i_16_0(4),
      I1 => sda_sig_i_16_0(5),
      I2 => bitcnt(1),
      I3 => sda_sig_i_16_0(6),
      I4 => bitcnt(0),
      I5 => sda_sig_i_16_0(7),
      O => sda_sig_i_44_n_0
    );
sda_sig_i_45: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => sda_sig_i_16_0(0),
      I1 => sda_sig_i_16_0(1),
      I2 => bitcnt(1),
      I3 => sda_sig_i_16_0(2),
      I4 => bitcnt(0),
      I5 => sda_sig_i_16_0(3),
      O => sda_sig_i_45_n_0
    );
sda_sig_i_46: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFCFC0C0AFA0AFA0"
    )
        port map (
      I0 => sda_sig_i_16_0(13),
      I1 => sda_sig_i_16_0(12),
      I2 => bitcnt(1),
      I3 => sda_sig_i_16_0(15),
      I4 => sda_sig_i_16_0(14),
      I5 => bitcnt(0),
      O => sda_sig_i_46_n_0
    );
sda_sig_i_47: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => sda_sig_i_16_0(8),
      I1 => sda_sig_i_16_0(9),
      I2 => bitcnt(1),
      I3 => sda_sig_i_16_0(10),
      I4 => bitcnt(0),
      I5 => sda_sig_i_16_0(11),
      O => sda_sig_i_47_n_0
    );
sda_sig_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"11111115FFFFFFFF"
    )
        port map (
      I0 => sda_sig_i_18_n_0,
      I1 => \i[4]_i_3_n_0\,
      I2 => \FSM_sequential_elem[2]_i_8_n_0\,
      I3 => sda_sig_i_19_n_0,
      I4 => sda_sig_i_9_n_0,
      I5 => \FSM_sequential_elem[2]_i_5_n_0\,
      O => sda_sig_i_5_n_0
    );
sda_sig_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => \recv_sig[7]_i_3_n_0\,
      I1 => \FSM_sequential_elem[2]_i_8_n_0\,
      I2 => sda_sig_i_19_n_0,
      I3 => sda_sig_i_9_n_0,
      I4 => sda_sig_i_20_n_0,
      I5 => \stateXfer[3]_i_3_n_0\,
      O => sda_sig_i_6_n_0
    );
sda_sig_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFFEFFFFFFFEEF"
    )
        port map (
      I0 => i(6),
      I1 => imax(7),
      I2 => i(3),
      I3 => sda_sig_i_21_n_0,
      I4 => i(5),
      I5 => i(4),
      O => sda_sig_i_7_n_0
    );
sda_sig_i_8: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80080000"
    )
        port map (
      I0 => i(6),
      I1 => imax(7),
      I2 => i(3),
      I3 => sda_sig_i_21_n_0,
      I4 => i(5),
      O => sda_sig_i_8_n_0
    );
sda_sig_i_9: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D5557FFF7FFFEAAA"
    )
        port map (
      I0 => i(9),
      I1 => i(7),
      I2 => \i[9]_i_4_n_0\,
      I3 => i(6),
      I4 => i(8),
      I5 => imax(8),
      O => sda_sig_i_9_n_0
    );
sda_sig_reg: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => sda_sig_i_1_n_0,
      PRE => sda_sig_reg_0,
      Q => sda_sig_reg_n_0
    );
sda_sig_reg_i_32: unisim.vcomponents.MUXF7
     port map (
      I0 => sda_sig_i_44_n_0,
      I1 => sda_sig_i_45_n_0,
      O => sda_sig_reg_i_32_n_0,
      S => bitcnt(2)
    );
sda_sig_reg_i_33: unisim.vcomponents.MUXF7
     port map (
      I0 => sda_sig_i_46_n_0,
      I1 => sda_sig_i_47_n_0,
      O => sda_sig_reg_i_33_n_0,
      S => bitcnt(2)
    );
\stateConfig[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEAEEEAEA"
    )
        port map (
      I0 => \stateConfig_reg[0]\,
      I1 => \stateConfig_reg[0]_0\,
      I2 => \stateConfig[3]_i_4_n_0\,
      I3 => \stateConfig_reg[0]_1\,
      I4 => \stateConfig_reg[0]_2\,
      I5 => \stateConfig_reg[0]_3\,
      O => E(0)
    );
\stateConfig[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080B0808383B383"
    )
        port map (
      I0 => dne,
      I1 => Q(1),
      I2 => Q(0),
      I3 => \stateConfig_reg[0]_4\(0),
      I4 => \stateConfig_reg[0]_4\(1),
      I5 => tkclk,
      O => \stateConfig[3]_i_4_n_0\
    );
\stateConfig[3]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \stateXfer_reg_n_0_[1]\,
      I1 => \stateXfer_reg_n_0_[0]\,
      I2 => \stateXfer_reg_n_0_[3]\,
      I3 => \stateXfer_reg_n_0_[2]\,
      O => dne
    );
\stateXfer[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A88A8A0AAA8A8A0A"
    )
        port map (
      I0 => req,
      I1 => \stateXfer_reg_n_0_[3]\,
      I2 => \stateXfer_reg_n_0_[0]\,
      I3 => \stateXfer_reg_n_0_[2]\,
      I4 => \stateXfer_reg_n_0_[1]\,
      I5 => \stateXfer[3]_i_3_n_0\,
      O => \stateXfer[0]_i_1_n_0\
    );
\stateXfer[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8A8A8A8A8AAAA00"
    )
        port map (
      I0 => req,
      I1 => \stateXfer[1]_i_2_n_0\,
      I2 => \stateXfer_reg_n_0_[3]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[1]\,
      I5 => \stateXfer_reg_n_0_[2]\,
      O => \stateXfer[1]_i_1_n_0\
    );
\stateXfer[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3D0031003D003D00"
    )
        port map (
      I0 => \stateXfer[2]_i_3_n_0\,
      I1 => \stateXfer_reg_n_0_[1]\,
      I2 => \stateXfer_reg_n_0_[0]\,
      I3 => \stateXfer_reg_n_0_[2]\,
      I4 => \elem__0\(0),
      I5 => \elem__0\(1),
      O => \stateXfer[1]_i_2_n_0\
    );
\stateXfer[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000088808800"
    )
        port map (
      I0 => \stateXfer[2]_i_2_n_0\,
      I1 => req,
      I2 => \stateXfer_reg_n_0_[0]\,
      I3 => \stateXfer_reg_n_0_[2]\,
      I4 => \stateXfer_reg_n_0_[1]\,
      I5 => \stateXfer_reg_n_0_[3]\,
      O => \stateXfer[2]_i_1_n_0\
    );
\stateXfer[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3333F333FFFFBBBB"
    )
        port map (
      I0 => \stateXfer[2]_i_3_n_0\,
      I1 => \stateXfer_reg_n_0_[2]\,
      I2 => \stateXfer[2]_i_4_n_0\,
      I3 => i2cReadNotWrite,
      I4 => \stateXfer_reg_n_0_[0]\,
      I5 => \stateXfer_reg_n_0_[1]\,
      O => \stateXfer[2]_i_2_n_0\
    );
\stateXfer[2]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => bitcnt(1),
      I1 => bitcnt(0),
      I2 => bitcnt(3),
      I3 => bitcnt(2),
      O => \stateXfer[2]_i_3_n_0\
    );
\stateXfer[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \elem__0\(2),
      I1 => \elem__0\(0),
      I2 => \elem__0\(1),
      O => \stateXfer[2]_i_4_n_0\
    );
\stateXfer[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01055557FFFFFFFF"
    )
        port map (
      I0 => \FSM_sequential_elem[2]_i_3_n_0\,
      I1 => \stateXfer_reg_n_0_[1]\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[3]\,
      I5 => req,
      O => \stateXfer[3]_i_1_n_0\
    );
\stateXfer[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00800000"
    )
        port map (
      I0 => req,
      I1 => \stateXfer[3]_i_3_n_0\,
      I2 => \stateXfer_reg_n_0_[2]\,
      I3 => \stateXfer_reg_n_0_[0]\,
      I4 => \stateXfer_reg_n_0_[1]\,
      I5 => \stateXfer_reg_n_0_[3]\,
      O => \stateXfer[3]_i_2_n_0\
    );
\stateXfer[3]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \elem__0\(1),
      I1 => \elem__0\(0),
      O => \stateXfer[3]_i_3_n_0\
    );
\stateXfer_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateXfer[3]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \stateXfer[0]_i_1_n_0\,
      Q => \stateXfer_reg_n_0_[0]\
    );
\stateXfer_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateXfer[3]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \stateXfer[1]_i_1_n_0\,
      Q => \stateXfer_reg_n_0_[1]\
    );
\stateXfer_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateXfer[3]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \stateXfer[2]_i_1_n_0\,
      Q => \stateXfer_reg_n_0_[2]\
    );
\stateXfer_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateXfer[3]_i_1_n_0\,
      CLR => sda_sig_reg_0,
      D => \stateXfer[3]_i_2_n_0\,
      Q => \stateXfer_reg_n_0_[3]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Parrom is
  port (
    DO : out STD_LOGIC_VECTOR ( 6 downto 0 );
    \stateConfig_reg[3]\ : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \invbuf_reg[2][0]\ : out STD_LOGIC;
    \invbuf_reg[2][1]\ : out STD_LOGIC;
    \invbuf_reg[2][2]\ : out STD_LOGIC;
    \invbuf_reg[2][3]\ : out STD_LOGIC;
    \invbuf_reg[2][4]\ : out STD_LOGIC;
    \invbuf_reg[2][5]\ : out STD_LOGIC;
    \invbuf_reg[2][6]\ : out STD_LOGIC;
    \invbuf_reg[2][7]\ : out STD_LOGIC;
    \stateConfig_reg[3]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \stateConfig_reg[0]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \stateConfig_reg[1]\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    prepdone_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    specNotGnr_reg : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateConfig_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_reg : out STD_LOGIC;
    specNotGnr_reg_0 : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
    specNotGnr_reg_1 : in STD_LOGIC;
    \j_reg[1]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \j_reg[7]\ : in STD_LOGIC;
    specNotGnr : in STD_LOGIC;
    specNotGnr_reg_2 : in STD_LOGIC;
    \i2cRegaddr_reg[15]\ : in STD_LOGIC;
    prepdone_reg_0 : in STD_LOGIC;
    \i2cRegaddr_reg[15]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 7 downto 0 );
    reqInvSetReg : in STD_LOGIC;
    \i2cSend_reg[7]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
    \aParrom_reg[10]\ : in STD_LOGIC;
    \i2cRegaddr_reg[13]\ : in STD_LOGIC;
    \i2cRegaddr_reg[12]\ : in STD_LOGIC;
    \i2cRegaddr_reg[6]\ : in STD_LOGIC;
    \i2cRegaddr_reg[4]\ : in STD_LOGIC;
    \i2cRegaddr_reg[3]\ : in STD_LOGIC;
    \i2cRegaddr_reg[0]\ : in STD_LOGIC;
    \stateConfig_reg[0]_0\ : in STD_LOGIC;
    \aParrom_reg[5]\ : in STD_LOGIC;
    \aParrom_reg[6]\ : in STD_LOGIC;
    \aParrom_reg[9]\ : in STD_LOGIC;
    \aParrom_reg[9]_0\ : in STD_LOGIC;
    \stateConfig_reg[2]\ : in STD_LOGIC;
    \stateConfig_reg[2]_0\ : in STD_LOGIC;
    \stateConfig_reg[2]_1\ : in STD_LOGIC;
    \bytecnt_reg[0]\ : in STD_LOGIC;
    prepdone : in STD_LOGIC;
    \bytecnt_reg[0]_0\ : in STD_LOGIC;
    \k[1]_i_4_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \stateConfig_reg[1]_0\ : in STD_LOGIC;
    \stateConfig_reg[1]_1\ : in STD_LOGIC;
    \stateConfig_reg[1]_2\ : in STD_LOGIC;
    i2cReadNotWrite : in STD_LOGIC;
    ackLiveToConfigSetReg : in STD_LOGIC;
    \aParrom_reg[10]_0\ : in STD_LOGIC;
    \j_reg[7]_0\ : in STD_LOGIC;
    \j_reg[7]_1\ : in STD_LOGIC;
    \j_reg[7]_2\ : in STD_LOGIC;
    \aParrom_reg[10]_1\ : in STD_LOGIC;
    \k_reg[1]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Parrom : entity is "Parrom";
end design_1_Vsp_core_0_0_Parrom;

architecture STRUCTURE of design_1_Vsp_core_0_0_Parrom is
  signal \^do\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal aParrom1 : STD_LOGIC;
  signal \aParrom[8]_i_2_n_0\ : STD_LOGIC;
  signal drdParrom : STD_LOGIC_VECTOR ( 4 to 4 );
  signal en : STD_LOGIC;
  signal \j[7]_i_6_n_0\ : STD_LOGIC;
  signal \k[1]_i_4_n_0\ : STD_LOGIC;
  signal \k[1]_i_7_n_0\ : STD_LOGIC;
  signal \^reset_reg\ : STD_LOGIC;
  signal \stateConfig[1]_i_2_n_0\ : STD_LOGIC;
  signal \stateConfig[2]_i_4_n_0\ : STD_LOGIC;
  signal NLW_myBram_CASDINA_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_myBram_CASDINB_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_myBram_CASDINPA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_myBram_CASDINPB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_myBram_CASDOUTA_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_myBram_CASDOUTB_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_myBram_CASDOUTPA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_myBram_CASDOUTPB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_myBram_DINADIN_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 8 );
  signal NLW_myBram_DINBDIN_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_myBram_DINPADINP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
  signal NLW_myBram_DINPBDINP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_myBram_DOUTADOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 8 );
  signal NLW_myBram_DOUTBDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_myBram_DOUTPADOUTP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_myBram_DOUTPBDOUTP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \aParrom[0]_i_1\ : label is "soft_lutpair620";
  attribute SOFT_HLUTNM of \aParrom[1]_i_1\ : label is "soft_lutpair620";
  attribute SOFT_HLUTNM of \aParrom[2]_i_1\ : label is "soft_lutpair617";
  attribute SOFT_HLUTNM of \aParrom[3]_i_1\ : label is "soft_lutpair617";
  attribute SOFT_HLUTNM of \aParrom[5]_i_1\ : label is "soft_lutpair621";
  attribute SOFT_HLUTNM of \aParrom[6]_i_1\ : label is "soft_lutpair621";
  attribute SOFT_HLUTNM of \aParrom[7]_i_1\ : label is "soft_lutpair618";
  attribute SOFT_HLUTNM of \aParrom[8]_i_1\ : label is "soft_lutpair618";
  attribute SOFT_HLUTNM of \aParrom[8]_i_2\ : label is "soft_lutpair619";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of myBram : label is "RAMB16_S9";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of myBram : label is "ADDR[0]:ADDRARDADDR[3] ADDR[10]:ADDRARDADDR[13] ADDR[1]:ADDRARDADDR[4] ADDR[2]:ADDRARDADDR[5] ADDR[3]:ADDRARDADDR[6] ADDR[4]:ADDRARDADDR[7] ADDR[5]:ADDRARDADDR[8] ADDR[6]:ADDRARDADDR[9] ADDR[7]:ADDRARDADDR[10] ADDR[8]:ADDRARDADDR[11] ADDR[9]:ADDRARDADDR[12] CLK:CLKARDCLK DI[0]:DINADIN[0] DI[1]:DINADIN[1] DI[2]:DINADIN[2] DI[3]:DINADIN[3] DI[4]:DINADIN[4] DI[5]:DINADIN[5] DI[6]:DINADIN[6] DI[7]:DINADIN[7] DIP[0]:DINPADINP[0] DO[0]:DOUTADOUT[0] DO[1]:DOUTADOUT[1] DO[2]:DOUTADOUT[2] DO[3]:DOUTADOUT[3] DO[4]:DOUTADOUT[4] DO[5]:DOUTADOUT[5] DO[6]:DOUTADOUT[6] DO[7]:DOUTADOUT[7] DOP[0]:DOUTPADOUTP[0] EN:ENARDEN SSR:RSTRAMARSTRAM WE:WEA[0] GND:SLEEP,CASOREGIMUXB,CASOREGIMUXA,CASDOMUXB,CASDOMUXA,CASDIMUXB,CASDIMUXA,WEBWE[3],WEBWE[2],WEBWE[1],WEBWE[0],RSTREGB,RSTREGARSTREG,RSTRAMB,ENBWREN,CLKBWRCLK VCC:CASOREGIMUXEN_B,CASOREGIMUXEN_A,CASDOMUXEN_B,CASDOMUXEN_A,ADDRENB,ADDRENA,ADDRBWRADDR[9],ADDRBWRADDR[8],ADDRBWRADDR[7],ADDRBWRADDR[6],ADDRBWRADDR[5],ADDRBWRADDR[4],ADDRBWRADDR[3],ADDRBWRADDR[2],ADDRBWRADDR[1],ADDRBWRADDR[13],ADDRBWRADDR[12],ADDRBWRADDR[11],ADDRBWRADDR[10],ADDRBWRADDR[0],ADDRARDADDR[2],ADDRARDADDR[1],ADDRARDADDR[0] DIADI[10]:DINADIN[10] DIADI[11]:DINADIN[11] DIADI[12]:DINADIN[12] DIADI[13]:DINADIN[13] DIADI[14]:DINADIN[14] DIADI[15]:DINADIN[15] DIADI[8]:DINADIN[8] DIADI[9]:DINADIN[9] DIBDI[0]:DINBDIN[0] DIBDI[10]:DINBDIN[10] DIBDI[11]:DINBDIN[11] DIBDI[12]:DINBDIN[12] DIBDI[13]:DINBDIN[13] DIBDI[14]:DINBDIN[14] DIBDI[15]:DINBDIN[15] DIBDI[1]:DINBDIN[1] DIBDI[2]:DINBDIN[2] DIBDI[3]:DINBDIN[3] DIBDI[4]:DINBDIN[4] DIBDI[5]:DINBDIN[5] DIBDI[6]:DINBDIN[6] DIBDI[7]:DINBDIN[7] DIBDI[8]:DINBDIN[8] DIBDI[9]:DINBDIN[9] DIPADIP[1]:DINPADINP[1] DIPBDIP[0]:DINPBDINP[0] DIPBDIP[1]:DINPBDINP[1] DOADO[10]:DOUTADOUT[10] DOADO[11]:DOUTADOUT[11] DOADO[12]:DOUTADOUT[12] DOADO[13]:DOUTADOUT[13] DOADO[14]:DOUTADOUT[14] DOADO[15]:DOUTADOUT[15] DOADO[8]:DOUTADOUT[8] DOADO[9]:DOUTADOUT[9] DOBDO[0]:DOUTBDOUT[0] DOBDO[10]:DOUTBDOUT[10] DOBDO[11]:DOUTBDOUT[11] DOBDO[12]:DOUTBDOUT[12] DOBDO[13]:DOUTBDOUT[13] DOBDO[14]:DOUTBDOUT[14] DOBDO[15]:DOUTBDOUT[15] DOBDO[1]:DOUTBDOUT[1] DOBDO[2]:DOUTBDOUT[2] DOBDO[3]:DOUTBDOUT[3] DOBDO[4]:DOUTBDOUT[4] DOBDO[5]:DOUTBDOUT[5] DOBDO[6]:DOUTBDOUT[6] DOBDO[7]:DOUTBDOUT[7] DOBDO[8]:DOUTBDOUT[8] DOBDO[9]:DOUTBDOUT[9] DOPADOP[1]:DOUTPADOUTP[1] DOPBDOP[0]:DOUTPBDOUTP[0] DOPBDOP[1]:DOUTPBDOUTP[1]";
  attribute box_type : string;
  attribute box_type of myBram : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of myBram_i_1 : label is "soft_lutpair619";
begin
  DO(6 downto 0) <= \^do\(6 downto 0);
  reset_reg <= \^reset_reg\;
\aParrom[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \aParrom[8]_i_2_n_0\,
      I1 => Q(0),
      O => \stateConfig_reg[1]\(0)
    );
\aParrom[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5454545554555455"
    )
        port map (
      I0 => \j_reg[1]\(3),
      I1 => \aParrom_reg[10]\,
      I2 => \aParrom_reg[10]_0\,
      I3 => specNotGnr_reg_1,
      I4 => aParrom1,
      I5 => specNotGnr,
      O => \stateConfig_reg[3]_1\(0)
    );
\aParrom[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAE8FFFC"
    )
        port map (
      I0 => aParrom1,
      I1 => \j_reg[1]\(1),
      I2 => \j_reg[1]\(0),
      I3 => \j_reg[1]\(2),
      I4 => \aParrom_reg[10]_1\,
      O => \stateConfig_reg[1]\(10)
    );
\aParrom[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \aParrom[8]_i_2_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      O => \stateConfig_reg[1]\(1)
    );
\aParrom[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \aParrom[8]_i_2_n_0\,
      I1 => Q(0),
      I2 => Q(1),
      I3 => Q(2),
      O => \stateConfig_reg[1]\(2)
    );
\aParrom[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \aParrom[8]_i_2_n_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(2),
      I4 => Q(3),
      O => \stateConfig_reg[1]\(3)
    );
\aParrom[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \aParrom[8]_i_2_n_0\,
      I1 => Q(2),
      I2 => Q(0),
      I3 => Q(1),
      I4 => Q(3),
      I5 => Q(4),
      O => \stateConfig_reg[1]\(4)
    );
\aParrom[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \aParrom[8]_i_2_n_0\,
      I1 => Q(5),
      I2 => \aParrom_reg[5]\,
      O => \stateConfig_reg[1]\(5)
    );
\aParrom[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \aParrom[8]_i_2_n_0\,
      I1 => Q(6),
      I2 => \aParrom_reg[6]\,
      O => \stateConfig_reg[1]\(6)
    );
\aParrom[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2888"
    )
        port map (
      I0 => \aParrom[8]_i_2_n_0\,
      I1 => Q(7),
      I2 => Q(6),
      I3 => \aParrom_reg[6]\,
      O => \stateConfig_reg[1]\(7)
    );
\aParrom[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \aParrom[8]_i_2_n_0\,
      I1 => Q(8),
      I2 => \aParrom_reg[6]\,
      I3 => Q(6),
      I4 => Q(7),
      O => \stateConfig_reg[1]\(8)
    );
\aParrom[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55555514"
    )
        port map (
      I0 => aParrom1,
      I1 => \j_reg[1]\(0),
      I2 => \j_reg[1]\(1),
      I3 => \j_reg[1]\(3),
      I4 => \j_reg[1]\(2),
      O => \aParrom[8]_i_2_n_0\
    );
\aParrom[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F6F600F6F6F6F6"
    )
        port map (
      I0 => Q(9),
      I1 => \aParrom_reg[9]\,
      I2 => aParrom1,
      I3 => \j_reg[1]\(0),
      I4 => \j_reg[1]\(1),
      I5 => \aParrom_reg[9]_0\,
      O => \stateConfig_reg[1]\(9)
    );
\bytecnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAEEAFEEAAAAAAAA"
    )
        port map (
      I0 => \bytecnt_reg[0]\,
      I1 => prepdone,
      I2 => \j[7]_i_6_n_0\,
      I3 => \bytecnt_reg[0]_0\,
      I4 => \k[1]_i_4_0\(0),
      I5 => prepdone_reg_0,
      O => prepdone_reg(0)
    );
\i2cRegaddr[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000002"
    )
        port map (
      I0 => \i2cRegaddr_reg[0]\,
      I1 => \j_reg[1]\(3),
      I2 => \j_reg[1]\(2),
      I3 => \j_reg[1]\(0),
      I4 => \j_reg[1]\(1),
      I5 => \^do\(0),
      O => \stateConfig_reg[3]_0\(0)
    );
\i2cRegaddr[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000002"
    )
        port map (
      I0 => \i2cRegaddr_reg[12]\,
      I1 => \j_reg[1]\(3),
      I2 => \j_reg[1]\(2),
      I3 => \j_reg[1]\(0),
      I4 => \j_reg[1]\(1),
      I5 => drdParrom(4),
      O => \stateConfig_reg[3]_0\(4)
    );
\i2cRegaddr[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000002"
    )
        port map (
      I0 => \i2cRegaddr_reg[13]\,
      I1 => \j_reg[1]\(3),
      I2 => \j_reg[1]\(2),
      I3 => \j_reg[1]\(0),
      I4 => \j_reg[1]\(1),
      I5 => \^do\(4),
      O => \stateConfig_reg[3]_0\(5)
    );
\i2cRegaddr[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00C0040400000404"
    )
        port map (
      I0 => \i2cRegaddr_reg[15]\,
      I1 => prepdone_reg_0,
      I2 => \j_reg[1]\(1),
      I3 => aParrom1,
      I4 => \j_reg[1]\(2),
      I5 => \i2cRegaddr_reg[15]_0\,
      O => E(0)
    );
\i2cRegaddr[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000002"
    )
        port map (
      I0 => \i2cRegaddr_reg[3]\,
      I1 => \j_reg[1]\(3),
      I2 => \j_reg[1]\(2),
      I3 => \j_reg[1]\(0),
      I4 => \j_reg[1]\(1),
      I5 => \^do\(3),
      O => \stateConfig_reg[3]_0\(1)
    );
\i2cRegaddr[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000002"
    )
        port map (
      I0 => \i2cRegaddr_reg[4]\,
      I1 => \j_reg[1]\(3),
      I2 => \j_reg[1]\(2),
      I3 => \j_reg[1]\(0),
      I4 => \j_reg[1]\(1),
      I5 => drdParrom(4),
      O => \stateConfig_reg[3]_0\(2)
    );
\i2cRegaddr[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000002"
    )
        port map (
      I0 => \i2cRegaddr_reg[6]\,
      I1 => \j_reg[1]\(3),
      I2 => \j_reg[1]\(2),
      I3 => \j_reg[1]\(0),
      I4 => \j_reg[1]\(1),
      I5 => \^do\(5),
      O => \stateConfig_reg[3]_0\(3)
    );
\i2cSend[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FF000047FF47FF"
    )
        port map (
      I0 => D(0),
      I1 => reqInvSetReg,
      I2 => \i2cSend_reg[7]\(0),
      I3 => \aParrom_reg[10]\,
      I4 => specNotGnr_reg_1,
      I5 => \^do\(0),
      O => \invbuf_reg[2][0]\
    );
\i2cSend[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FF000047FF47FF"
    )
        port map (
      I0 => D(1),
      I1 => reqInvSetReg,
      I2 => \i2cSend_reg[7]\(1),
      I3 => \aParrom_reg[10]\,
      I4 => specNotGnr_reg_1,
      I5 => \^do\(1),
      O => \invbuf_reg[2][1]\
    );
\i2cSend[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FF000047FF47FF"
    )
        port map (
      I0 => D(2),
      I1 => reqInvSetReg,
      I2 => \i2cSend_reg[7]\(2),
      I3 => \aParrom_reg[10]\,
      I4 => specNotGnr_reg_1,
      I5 => \^do\(2),
      O => \invbuf_reg[2][2]\
    );
\i2cSend[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FF000047FF47FF"
    )
        port map (
      I0 => D(3),
      I1 => reqInvSetReg,
      I2 => \i2cSend_reg[7]\(3),
      I3 => \aParrom_reg[10]\,
      I4 => specNotGnr_reg_1,
      I5 => \^do\(3),
      O => \invbuf_reg[2][3]\
    );
\i2cSend[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FF000047FF47FF"
    )
        port map (
      I0 => D(4),
      I1 => reqInvSetReg,
      I2 => \i2cSend_reg[7]\(4),
      I3 => \aParrom_reg[10]\,
      I4 => specNotGnr_reg_1,
      I5 => drdParrom(4),
      O => \invbuf_reg[2][4]\
    );
\i2cSend[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0FFFF7FFFFFFF7"
    )
        port map (
      I0 => reqInvSetReg,
      I1 => D(5),
      I2 => \j_reg[1]\(2),
      I3 => \j_reg[1]\(0),
      I4 => \j_reg[1]\(1),
      I5 => \^do\(4),
      O => \invbuf_reg[2][5]\
    );
\i2cSend[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FF000047FF47FF"
    )
        port map (
      I0 => D(6),
      I1 => reqInvSetReg,
      I2 => \i2cSend_reg[7]\(5),
      I3 => \aParrom_reg[10]\,
      I4 => specNotGnr_reg_1,
      I5 => \^do\(5),
      O => \invbuf_reg[2][6]\
    );
\i2cSend[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FF000047FF47FF"
    )
        port map (
      I0 => D(7),
      I1 => reqInvSetReg,
      I2 => \i2cSend_reg[7]\(6),
      I3 => \aParrom_reg[10]\,
      I4 => specNotGnr_reg_1,
      I5 => \^do\(6),
      O => \invbuf_reg[2][7]\
    );
\j[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000008000000000"
    )
        port map (
      I0 => specNotGnr,
      I1 => \j_reg[1]\(1),
      I2 => \j_reg[1]\(2),
      I3 => \j_reg[1]\(3),
      I4 => \j_reg[1]\(0),
      I5 => \^reset_reg\,
      O => specNotGnr_reg_0
    );
\j[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5554545444444444"
    )
        port map (
      I0 => \j_reg[7]\,
      I1 => \j_reg[7]_0\,
      I2 => \j_reg[7]_1\,
      I3 => \j[7]_i_6_n_0\,
      I4 => \stateConfig_reg[2]_1\,
      I5 => \j_reg[7]_2\,
      O => \^reset_reg\
    );
\j[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => aParrom1,
      I1 => specNotGnr,
      O => \j[7]_i_6_n_0\
    );
\k[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44454444"
    )
        port map (
      I0 => \j_reg[7]\,
      I1 => \k[1]_i_4_n_0\,
      I2 => i2cReadNotWrite,
      I3 => prepdone,
      I4 => ackLiveToConfigSetReg,
      O => SR(0)
    );
\k[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0022302000000000"
    )
        port map (
      I0 => \k_reg[1]\,
      I1 => \j_reg[1]\(3),
      I2 => \k[1]_i_7_n_0\,
      I3 => \j_reg[1]\(2),
      I4 => \j_reg[1]\(0),
      I5 => \j_reg[1]\(1),
      O => \k[1]_i_4_n_0\
    );
\k[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000044404440444"
    )
        port map (
      I0 => \k[1]_i_4_0\(2),
      I1 => \j_reg[1]\(2),
      I2 => \k[1]_i_4_0\(0),
      I3 => \k[1]_i_4_0\(1),
      I4 => aParrom1,
      I5 => specNotGnr,
      O => \k[1]_i_7_n_0\
    );
myBram: unisim.vcomponents.RAMB18E2
    generic map(
      DOA_REG => 0,
      DOB_REG => 0,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"000114010009EB300005EB3000FF0B3000FF0A30000CEB300005EB3000000001",
      INIT_01 => X"0001640100786301000D6201005961010004600100002B0100182A0100002801",
      INIT_02 => X"00076C0100906B0100086A01000F69010001680100776701000B660100586501",
      INIT_03 => X"000A8C010000750100007401000171010001700100386F0100046E0100806D01",
      INIT_04 => X"000A0903006007030000060300030503000304030001030300050103000A8D01",
      INIT_05 => X"0040570100720D0300000C0300010B03000A090300720D0300000C0300010B03",
      INIT_06 => X"00545B0100045A0100786301000D620100E36101000660010000590100025801",
      INIT_07 => X"00F09A0100F09901000098010000950100009401000193010000910100019001",
      INIT_08 => X"000CA2010000A1010008A00100009F0100089E0100009D01000A9C0100009B01",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"008F183A0003013A00019D3100001D3400471C34000150300001023000010030",
      INIT_21 => X"007F263A004F243A0087223A004F203A00011F3A00371E3A00471C3A004F1A3A",
      INIT_22 => X"00302C30000235300026343000003230001131300094303000001830003F283A",
      INIT_23 => X"005876300000753000B074300097573000AC5630000A2F3000382E3000002D30",
      INIT_24 => X"00840C300010D930004CD8300000CF300000CE300000C7300000C630000F7730",
      INIT_25 => X"002188320000A13100019E31007F6A31008F683100035A3100B04C31005D0D30",
      INIT_26 => X"00317C360001783600044C3600044A3600014836001816340005143400028A32",
      INIT_27 => X"003D1C3700031737000116370002153700021437000308370010063700317E36",
      INIT_28 => X"00083237000031370089303700002F3700462E3700002D3700002C37003F1D37",
      INIT_29 => X"0001603700115F3700005E3700005D37000240370005353700FE343700013337",
      INIT_2A => X"00007637000F6E3700176D37001A6C37001B6B37001B6A37001B6937001B6837",
      INIT_2B => X"00237E3700017D3700087C3700007B3700897A37000079370046783700007737",
      INIT_2C => X"00D98A37000F883700A584370006833700F582370003813700D9803700027F37",
      INIT_2D => X"007A94370043923700F5903700068F3700878E3700058D3700EB8C3700038B37",
      INIT_2E => X"00000000000000000000000000000000000000300001003A0036B03700A19637",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000230",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => B"00" & X"0000",
      INIT_B => B"00" & X"0000",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 0,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SRVAL_A => B"00" & X"0000",
      SRVAL_B => B"00" & X"0000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 0
    )
        port map (
      ADDRARDADDR(13 downto 3) => Q(10 downto 0),
      ADDRARDADDR(2 downto 0) => B"111",
      ADDRBWRADDR(13 downto 0) => B"11111111111111",
      ADDRENA => '1',
      ADDRENB => '1',
      CASDIMUXA => '0',
      CASDIMUXB => '0',
      CASDINA(15 downto 0) => NLW_myBram_CASDINA_UNCONNECTED(15 downto 0),
      CASDINB(15 downto 0) => NLW_myBram_CASDINB_UNCONNECTED(15 downto 0),
      CASDINPA(1 downto 0) => NLW_myBram_CASDINPA_UNCONNECTED(1 downto 0),
      CASDINPB(1 downto 0) => NLW_myBram_CASDINPB_UNCONNECTED(1 downto 0),
      CASDOMUXA => '0',
      CASDOMUXB => '0',
      CASDOMUXEN_A => '1',
      CASDOMUXEN_B => '1',
      CASDOUTA(15 downto 0) => NLW_myBram_CASDOUTA_UNCONNECTED(15 downto 0),
      CASDOUTB(15 downto 0) => NLW_myBram_CASDOUTB_UNCONNECTED(15 downto 0),
      CASDOUTPA(1 downto 0) => NLW_myBram_CASDOUTPA_UNCONNECTED(1 downto 0),
      CASDOUTPB(1 downto 0) => NLW_myBram_CASDOUTPB_UNCONNECTED(1 downto 0),
      CASOREGIMUXA => '0',
      CASOREGIMUXB => '0',
      CASOREGIMUXEN_A => '1',
      CASOREGIMUXEN_B => '1',
      CLKARDCLK => aclk_sig,
      CLKBWRCLK => '0',
      DINADIN(15 downto 8) => NLW_myBram_DINADIN_UNCONNECTED(15 downto 8),
      DINADIN(7 downto 0) => B"00000000",
      DINBDIN(15 downto 0) => NLW_myBram_DINBDIN_UNCONNECTED(15 downto 0),
      DINPADINP(1) => NLW_myBram_DINPADINP_UNCONNECTED(1),
      DINPADINP(0) => '0',
      DINPBDINP(1 downto 0) => NLW_myBram_DINPBDINP_UNCONNECTED(1 downto 0),
      DOUTADOUT(15 downto 8) => NLW_myBram_DOUTADOUT_UNCONNECTED(15 downto 8),
      DOUTADOUT(7 downto 5) => \^do\(6 downto 4),
      DOUTADOUT(4) => drdParrom(4),
      DOUTADOUT(3 downto 0) => \^do\(3 downto 0),
      DOUTBDOUT(15 downto 0) => NLW_myBram_DOUTBDOUT_UNCONNECTED(15 downto 0),
      DOUTPADOUTP(1 downto 0) => NLW_myBram_DOUTPADOUTP_UNCONNECTED(1 downto 0),
      DOUTPBDOUTP(1 downto 0) => NLW_myBram_DOUTPBDOUTP_UNCONNECTED(1 downto 0),
      ENARDEN => en,
      ENBWREN => '0',
      REGCEAREGCE => '0',
      REGCEB => '0',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SLEEP => '0',
      WEA(1 downto 0) => B"00",
      WEBWE(3 downto 0) => B"0000"
    );
myBram_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \j_reg[1]\(3),
      I1 => \j_reg[1]\(2),
      I2 => \j_reg[1]\(1),
      I3 => \j_reg[1]\(0),
      O => en
    );
prepdone_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
        port map (
      I0 => aParrom1,
      I1 => specNotGnr,
      I2 => \j_reg[1]\(1),
      I3 => \j_reg[1]\(2),
      I4 => prepdone_reg_0,
      I5 => prepdone,
      O => specNotGnr_reg
    );
specNotGnr_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF0100"
    )
        port map (
      I0 => specNotGnr_reg_1,
      I1 => \j_reg[1]\(3),
      I2 => \j_reg[7]\,
      I3 => aParrom1,
      I4 => specNotGnr,
      I5 => specNotGnr_reg_2,
      O => \stateConfig_reg[3]\
    );
\stateConfig[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAABAAABAAABAA"
    )
        port map (
      I0 => \stateConfig_reg[0]_0\,
      I1 => \j_reg[1]\(0),
      I2 => \j_reg[1]\(3),
      I3 => \j_reg[1]\(2),
      I4 => \j_reg[1]\(1),
      I5 => aParrom1,
      O => \stateConfig_reg[0]\(0)
    );
\stateConfig[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F053F053F050F05"
    )
        port map (
      I0 => \stateConfig_reg[1]_1\,
      I1 => \j_reg[1]\(0),
      I2 => \j_reg[1]\(1),
      I3 => \j_reg[1]\(2),
      I4 => \j[7]_i_6_n_0\,
      I5 => \stateConfig_reg[1]_2\,
      O => \stateConfig[1]_i_2_n_0\
    );
\stateConfig[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CDCCCDCCCDFCCDCC"
    )
        port map (
      I0 => \stateConfig_reg[2]\,
      I1 => \stateConfig_reg[2]_0\,
      I2 => \j_reg[1]\(2),
      I3 => \j_reg[1]\(3),
      I4 => \stateConfig_reg[2]_1\,
      I5 => aParrom1,
      O => \stateConfig_reg[0]\(2)
    );
\stateConfig[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \i2cRegaddr_reg[15]_0\,
      I1 => \stateConfig[2]_i_4_n_0\,
      I2 => \^do\(3),
      I3 => \^do\(2),
      I4 => \^do\(1),
      I5 => \^do\(0),
      O => aParrom1
    );
\stateConfig[2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^do\(4),
      I1 => drdParrom(4),
      I2 => \^do\(5),
      I3 => \^do\(6),
      O => \stateConfig[2]_i_4_n_0\
    );
\stateConfig[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FC22000000AA00"
    )
        port map (
      I0 => \stateConfig_reg[2]\,
      I1 => \j_reg[1]\(0),
      I2 => \j[7]_i_6_n_0\,
      I3 => \j_reg[1]\(3),
      I4 => \j_reg[1]\(2),
      I5 => \j_reg[1]\(1),
      O => \stateConfig_reg[0]\(3)
    );
\stateConfig_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \stateConfig[1]_i_2_n_0\,
      I1 => \stateConfig_reg[1]_0\,
      O => \stateConfig_reg[0]\(1),
      S => \j_reg[1]\(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Rgbled_v1_0 is
  port (
    rgb0_r : out STD_LOGIC;
    rgb0_g : out STD_LOGIC;
    rgb0_b : out STD_LOGIC;
    \i_reg[6]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \i_reg[7]_0\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \i_reg[7]__1_0\ : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    \i_reg[0]__1_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    DI : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S : in STD_LOGIC_VECTOR ( 1 downto 0 );
    stateGreen_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    stateGreen_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    stateBlue_i_2_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    rgb0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \seq_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateGreen0_inferred__0/i__carry_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Rgbled_v1_0 : entity is "Rgbled_v1_0";
end design_1_Vsp_core_0_0_Rgbled_v1_0;

architecture STRUCTURE of design_1_Vsp_core_0_0_Rgbled_v1_0 is
  signal \^d\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal data0 : STD_LOGIC;
  signal \i[0]__0_i_1__1_n_0\ : STD_LOGIC;
  signal \i[0]__1_i_1__0_n_0\ : STD_LOGIC;
  signal \i[1]__0_i_1__1_n_0\ : STD_LOGIC;
  signal \i[1]__1_i_1_n_0\ : STD_LOGIC;
  signal \i[2]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \i[2]__1_i_1_n_0\ : STD_LOGIC;
  signal \i[3]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \i[3]__1_i_1_n_0\ : STD_LOGIC;
  signal \i[4]__1_i_1_n_0\ : STD_LOGIC;
  signal \i[5]__1_i_1_n_0\ : STD_LOGIC;
  signal \i[6]__1_i_1_n_0\ : STD_LOGIC;
  signal \i[7]__0_i_2_n_0\ : STD_LOGIC;
  signal \i[7]__1_i_1_n_0\ : STD_LOGIC;
  signal \i[7]__1_i_2_n_0\ : STD_LOGIC;
  signal \i[7]_i_2__1_n_0\ : STD_LOGIC;
  signal \i[8]__0_i_1_n_0\ : STD_LOGIC;
  signal \i[8]__0_i_2_n_0\ : STD_LOGIC;
  signal \i[8]__1_i_1_n_0\ : STD_LOGIC;
  signal \i__carry_i_11__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_2_n_0\ : STD_LOGIC;
  signal \i__carry_i_3__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_3__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_3_n_0\ : STD_LOGIC;
  signal \i__carry_i_4__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_4__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_4_n_0\ : STD_LOGIC;
  signal \i__carry_i_5__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_5__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_5_n_0\ : STD_LOGIC;
  signal \i__carry_i_6__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_7_n_0\ : STD_LOGIC;
  signal \i__carry_i_8__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_8__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_8_n_0\ : STD_LOGIC;
  signal \i__carry_i_9__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_9__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_9_n_0\ : STD_LOGIC;
  signal \i_reg[0]__0_n_0\ : STD_LOGIC;
  signal \i_reg[0]__1_n_0\ : STD_LOGIC;
  signal \i_reg[1]__0_n_0\ : STD_LOGIC;
  signal \i_reg[1]__1_n_0\ : STD_LOGIC;
  signal \i_reg[2]__0_n_0\ : STD_LOGIC;
  signal \i_reg[2]__1_n_0\ : STD_LOGIC;
  signal \i_reg[3]__0_n_0\ : STD_LOGIC;
  signal \i_reg[3]__1_n_0\ : STD_LOGIC;
  signal \i_reg[4]__0_n_0\ : STD_LOGIC;
  signal \i_reg[4]__1_n_0\ : STD_LOGIC;
  signal \i_reg[5]__0_n_0\ : STD_LOGIC;
  signal \i_reg[5]__1_n_0\ : STD_LOGIC;
  signal \^i_reg[6]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \i_reg[6]__0_n_0\ : STD_LOGIC;
  signal \i_reg[6]__1_n_0\ : STD_LOGIC;
  signal \i_reg[7]__0_n_0\ : STD_LOGIC;
  signal \i_reg[7]__1_n_0\ : STD_LOGIC;
  signal \i_reg[8]__0_n_0\ : STD_LOGIC;
  signal \i_reg[8]__1_n_0\ : STD_LOGIC;
  signal \i_reg_n_0_[0]\ : STD_LOGIC;
  signal \i_reg_n_0_[1]\ : STD_LOGIC;
  signal \i_reg_n_0_[2]\ : STD_LOGIC;
  signal \i_reg_n_0_[3]\ : STD_LOGIC;
  signal \i_reg_n_0_[4]\ : STD_LOGIC;
  signal \i_reg_n_0_[5]\ : STD_LOGIC;
  signal \i_reg_n_0_[6]\ : STD_LOGIC;
  signal \i_reg_n_0_[7]\ : STD_LOGIC;
  signal \i_reg_n_0_[8]\ : STD_LOGIC;
  signal j : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \j[0]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \j[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \j[1]__0_i_1_n_0\ : STD_LOGIC;
  signal \j[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \j[2]__0_i_1_n_0\ : STD_LOGIC;
  signal \j[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \j[3]__0_i_1_n_0\ : STD_LOGIC;
  signal \j[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \j[4]__0_i_1_n_0\ : STD_LOGIC;
  signal \j[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \j[5]__0_i_1_n_0\ : STD_LOGIC;
  signal \j[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \j[6]__0_i_1_n_0\ : STD_LOGIC;
  signal \j[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \j[7]__0_i_1_n_0\ : STD_LOGIC;
  signal \j[7]__0_i_2_n_0\ : STD_LOGIC;
  signal \j[7]__1_i_2_n_0\ : STD_LOGIC;
  signal \j[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \j[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \j[8]__0_i_1_n_0\ : STD_LOGIC;
  signal \j[8]__0_i_2_n_0\ : STD_LOGIC;
  signal \j[8]__1_i_2_n_0\ : STD_LOGIC;
  signal \j[8]_i_1_n_0\ : STD_LOGIC;
  signal \j[8]_i_2_n_0\ : STD_LOGIC;
  signal \j[9]__0_i_1_n_0\ : STD_LOGIC;
  signal \j[9]__0_i_2_n_0\ : STD_LOGIC;
  signal \j[9]__0_i_3_n_0\ : STD_LOGIC;
  signal \j[9]__0_i_4_n_0\ : STD_LOGIC;
  signal \j[9]__1_i_2_n_0\ : STD_LOGIC;
  signal \j[9]__1_i_3_n_0\ : STD_LOGIC;
  signal \j[9]__1_i_4_n_0\ : STD_LOGIC;
  signal \j[9]_i_1_n_0\ : STD_LOGIC;
  signal \j[9]_i_2_n_0\ : STD_LOGIC;
  signal \j[9]_i_3_n_0\ : STD_LOGIC;
  signal \j[9]_i_4_n_0\ : STD_LOGIC;
  signal \j_reg[0]__0_n_0\ : STD_LOGIC;
  signal \j_reg[0]__1_n_0\ : STD_LOGIC;
  signal \j_reg[1]__0_n_0\ : STD_LOGIC;
  signal \j_reg[1]__1_n_0\ : STD_LOGIC;
  signal \j_reg[2]__0_n_0\ : STD_LOGIC;
  signal \j_reg[2]__1_n_0\ : STD_LOGIC;
  signal \j_reg[3]__0_n_0\ : STD_LOGIC;
  signal \j_reg[3]__1_n_0\ : STD_LOGIC;
  signal \j_reg[4]__0_n_0\ : STD_LOGIC;
  signal \j_reg[4]__1_n_0\ : STD_LOGIC;
  signal \j_reg[5]__0_n_0\ : STD_LOGIC;
  signal \j_reg[5]__1_n_0\ : STD_LOGIC;
  signal \j_reg[6]__0_n_0\ : STD_LOGIC;
  signal \j_reg[6]__1_n_0\ : STD_LOGIC;
  signal \j_reg[7]__0_n_0\ : STD_LOGIC;
  signal \j_reg[7]__1_n_0\ : STD_LOGIC;
  signal \j_reg[8]__0_n_0\ : STD_LOGIC;
  signal \j_reg[8]__1_n_0\ : STD_LOGIC;
  signal \j_reg[9]__0_n_0\ : STD_LOGIC;
  signal \j_reg[9]__1_n_0\ : STD_LOGIC;
  signal \j_reg_n_0_[0]\ : STD_LOGIC;
  signal \j_reg_n_0_[1]\ : STD_LOGIC;
  signal \j_reg_n_0_[2]\ : STD_LOGIC;
  signal \j_reg_n_0_[3]\ : STD_LOGIC;
  signal \j_reg_n_0_[4]\ : STD_LOGIC;
  signal \j_reg_n_0_[5]\ : STD_LOGIC;
  signal \j_reg_n_0_[6]\ : STD_LOGIC;
  signal \j_reg_n_0_[7]\ : STD_LOGIC;
  signal \j_reg_n_0_[8]\ : STD_LOGIC;
  signal \j_reg_n_0_[9]\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 8 downto 6 );
  signal p_2_in : STD_LOGIC;
  signal \^rgb0_b\ : STD_LOGIC;
  signal \^rgb0_g\ : STD_LOGIC;
  signal \^rgb0_r\ : STD_LOGIC;
  signal sel0 : STD_LOGIC_VECTOR ( 8 to 8 );
  signal \sel0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \stateBlue0_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal \stateBlue0_inferred__0/i__carry_n_4\ : STD_LOGIC;
  signal \stateBlue0_inferred__0/i__carry_n_5\ : STD_LOGIC;
  signal \stateBlue0_inferred__0/i__carry_n_6\ : STD_LOGIC;
  signal \stateBlue0_inferred__0/i__carry_n_7\ : STD_LOGIC;
  signal stateBlue_i_1_n_0 : STD_LOGIC;
  signal stateBlue_i_2_n_0 : STD_LOGIC;
  signal stateBlue_i_3_n_0 : STD_LOGIC;
  signal stateBlue_i_4_n_0 : STD_LOGIC;
  signal stateBlue_i_5_n_0 : STD_LOGIC;
  signal stateBlue_i_7_n_0 : STD_LOGIC;
  signal stateBlue_i_8_n_0 : STD_LOGIC;
  signal stateBlue_i_9_n_0 : STD_LOGIC;
  signal \stateGreen0_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal \stateGreen0_inferred__0/i__carry_n_4\ : STD_LOGIC;
  signal \stateGreen0_inferred__0/i__carry_n_5\ : STD_LOGIC;
  signal \stateGreen0_inferred__0/i__carry_n_6\ : STD_LOGIC;
  signal \stateGreen0_inferred__0/i__carry_n_7\ : STD_LOGIC;
  signal stateGreen_i_1_n_0 : STD_LOGIC;
  signal stateGreen_i_2_n_0 : STD_LOGIC;
  signal stateGreen_i_3_n_0 : STD_LOGIC;
  signal stateGreen_i_4_n_0 : STD_LOGIC;
  signal stateGreen_i_5_n_0 : STD_LOGIC;
  signal stateGreen_i_6_n_0 : STD_LOGIC;
  signal \stateRed0_inferred__0/i__carry_n_4\ : STD_LOGIC;
  signal \stateRed0_inferred__0/i__carry_n_5\ : STD_LOGIC;
  signal \stateRed0_inferred__0/i__carry_n_6\ : STD_LOGIC;
  signal \stateRed0_inferred__0/i__carry_n_7\ : STD_LOGIC;
  signal stateRed_i_1_n_0 : STD_LOGIC;
  signal stateRed_i_2_n_0 : STD_LOGIC;
  signal stateRed_i_3_n_0 : STD_LOGIC;
  signal stateRed_i_4_n_0 : STD_LOGIC;
  signal stateRed_i_7_n_0 : STD_LOGIC;
  signal stateRed_i_8_n_0 : STD_LOGIC;
  signal \NLW_stateBlue0_inferred__0/i__carry_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_stateBlue0_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateGreen0_inferred__0/i__carry_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_stateGreen0_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateRed0_inferred__0/i__carry_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_stateRed0_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \i[0]__0_i_1__1\ : label is "soft_lutpair2616";
  attribute SOFT_HLUTNM of \i[0]__1_i_1__0\ : label is "soft_lutpair2617";
  attribute SOFT_HLUTNM of \i[0]_i_1__7\ : label is "soft_lutpair2615";
  attribute SOFT_HLUTNM of \i[1]__0_i_1__1\ : label is "soft_lutpair2616";
  attribute SOFT_HLUTNM of \i[1]__1_i_1\ : label is "soft_lutpair2612";
  attribute SOFT_HLUTNM of \i[1]_i_1__6\ : label is "soft_lutpair2615";
  attribute SOFT_HLUTNM of \i[2]__0_i_1__0\ : label is "soft_lutpair2601";
  attribute SOFT_HLUTNM of \i[2]__1_i_1\ : label is "soft_lutpair2612";
  attribute SOFT_HLUTNM of \i[2]_i_1__3\ : label is "soft_lutpair2597";
  attribute SOFT_HLUTNM of \i[3]__0_i_1__0\ : label is "soft_lutpair2601";
  attribute SOFT_HLUTNM of \i[3]__1_i_1\ : label is "soft_lutpair2604";
  attribute SOFT_HLUTNM of \i[3]_i_1__3\ : label is "soft_lutpair2597";
  attribute SOFT_HLUTNM of \i[6]__0_i_1\ : label is "soft_lutpair2606";
  attribute SOFT_HLUTNM of \i[6]__1_i_1\ : label is "soft_lutpair2613";
  attribute SOFT_HLUTNM of \i[6]_i_1__4\ : label is "soft_lutpair2614";
  attribute SOFT_HLUTNM of \i[7]__0_i_1\ : label is "soft_lutpair2600";
  attribute SOFT_HLUTNM of \i[7]__1_i_1\ : label is "soft_lutpair2607";
  attribute SOFT_HLUTNM of \i[7]_i_1__4\ : label is "soft_lutpair2605";
  attribute SOFT_HLUTNM of \i__carry_i_10__0\ : label is "soft_lutpair2609";
  attribute SOFT_HLUTNM of \i__carry_i_10__1\ : label is "soft_lutpair2613";
  attribute SOFT_HLUTNM of \i__carry_i_11\ : label is "soft_lutpair2614";
  attribute SOFT_HLUTNM of \i__carry_i_11__0\ : label is "soft_lutpair2604";
  attribute SOFT_HLUTNM of \i__carry_i_12\ : label is "soft_lutpair2609";
  attribute SOFT_HLUTNM of \j[0]__1_i_1\ : label is "soft_lutpair2617";
  attribute SOFT_HLUTNM of \j[1]__0_i_1\ : label is "soft_lutpair2610";
  attribute SOFT_HLUTNM of \j[1]__1_i_1\ : label is "soft_lutpair2611";
  attribute SOFT_HLUTNM of \j[1]_i_1__0\ : label is "soft_lutpair2608";
  attribute SOFT_HLUTNM of \j[2]__0_i_1\ : label is "soft_lutpair2610";
  attribute SOFT_HLUTNM of \j[2]__1_i_1\ : label is "soft_lutpair2611";
  attribute SOFT_HLUTNM of \j[2]_i_1__0\ : label is "soft_lutpair2608";
  attribute SOFT_HLUTNM of \j[3]__0_i_1\ : label is "soft_lutpair2598";
  attribute SOFT_HLUTNM of \j[3]__1_i_1\ : label is "soft_lutpair2602";
  attribute SOFT_HLUTNM of \j[3]_i_1__0\ : label is "soft_lutpair2595";
  attribute SOFT_HLUTNM of \j[5]__0_i_1\ : label is "soft_lutpair2599";
  attribute SOFT_HLUTNM of \j[5]__1_i_1\ : label is "soft_lutpair2603";
  attribute SOFT_HLUTNM of \j[5]_i_1__0\ : label is "soft_lutpair2596";
  attribute SOFT_HLUTNM of \j[6]__0_i_1\ : label is "soft_lutpair2599";
  attribute SOFT_HLUTNM of \j[6]__1_i_1\ : label is "soft_lutpair2603";
  attribute SOFT_HLUTNM of \j[6]_i_1__0\ : label is "soft_lutpair2596";
  attribute SOFT_HLUTNM of \j[7]__0_i_2\ : label is "soft_lutpair2598";
  attribute SOFT_HLUTNM of \j[7]__1_i_2\ : label is "soft_lutpair2602";
  attribute SOFT_HLUTNM of \j[7]_i_2__0\ : label is "soft_lutpair2595";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of \stateBlue0_inferred__0/i__carry\ : label is 11;
  attribute SOFT_HLUTNM of stateBlue_i_5 : label is "soft_lutpair2607";
  attribute COMPARATOR_THRESHOLD of \stateGreen0_inferred__0/i__carry\ : label is 11;
  attribute SOFT_HLUTNM of stateGreen_i_2 : label is "soft_lutpair2600";
  attribute SOFT_HLUTNM of stateGreen_i_4 : label is "soft_lutpair2606";
  attribute COMPARATOR_THRESHOLD of \stateRed0_inferred__0/i__carry\ : label is 11;
  attribute SOFT_HLUTNM of stateRed_i_5 : label is "soft_lutpair2605";
begin
  D(3 downto 0) <= \^d\(3 downto 0);
  \i_reg[6]_0\(3 downto 0) <= \^i_reg[6]_0\(3 downto 0);
  rgb0_b <= \^rgb0_b\;
  rgb0_g <= \^rgb0_g\;
  rgb0_r <= \^rgb0_r\;
\i[0]__0_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \i_reg[0]__0_n_0\,
      I1 => \j[9]__0_i_3_n_0\,
      O => \i[0]__0_i_1__1_n_0\
    );
\i[0]__1_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \i_reg[0]__1_n_0\,
      I1 => \j[9]__1_i_3_n_0\,
      O => \i[0]__1_i_1__0_n_0\
    );
\i[0]_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \j[9]_i_3_n_0\,
      O => \sel0__0\(0)
    );
\i[1]__0_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \i_reg[0]__0_n_0\,
      I1 => \j[9]__0_i_3_n_0\,
      I2 => \i_reg[1]__0_n_0\,
      O => \i[1]__0_i_1__1_n_0\
    );
\i[1]__1_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \i_reg[0]__1_n_0\,
      I1 => \j[9]__1_i_3_n_0\,
      I2 => \i_reg[1]__1_n_0\,
      O => \i[1]__1_i_1_n_0\
    );
\i[1]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \j[9]_i_3_n_0\,
      I2 => \i_reg_n_0_[1]\,
      O => \sel0__0\(1)
    );
\i[2]__0_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \i_reg[1]__0_n_0\,
      I1 => \j[9]__0_i_3_n_0\,
      I2 => \i_reg[0]__0_n_0\,
      I3 => \i_reg[2]__0_n_0\,
      O => \i[2]__0_i_1__0_n_0\
    );
\i[2]__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \i_reg[1]__1_n_0\,
      I1 => \j[9]__1_i_3_n_0\,
      I2 => \i_reg[0]__1_n_0\,
      I3 => \i_reg[2]__1_n_0\,
      O => \i[2]__1_i_1_n_0\
    );
\i[2]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \j[9]_i_3_n_0\,
      I2 => \i_reg_n_0_[0]\,
      I3 => \i_reg_n_0_[2]\,
      O => \sel0__0\(2)
    );
\i[3]__0_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \i_reg[2]__0_n_0\,
      I1 => \i_reg[0]__0_n_0\,
      I2 => \j[9]__0_i_3_n_0\,
      I3 => \i_reg[1]__0_n_0\,
      I4 => \i_reg[3]__0_n_0\,
      O => \i[3]__0_i_1__0_n_0\
    );
\i[3]__1_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \i_reg[2]__1_n_0\,
      I1 => \i_reg[0]__1_n_0\,
      I2 => \j[9]__1_i_3_n_0\,
      I3 => \i_reg[1]__1_n_0\,
      I4 => \i_reg[3]__1_n_0\,
      O => \i[3]__1_i_1_n_0\
    );
\i[3]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \i_reg_n_0_[2]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \j[9]_i_3_n_0\,
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[3]\,
      O => \sel0__0\(3)
    );
\i[4]__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \i_reg[1]__0_n_0\,
      I1 => \j[9]__0_i_3_n_0\,
      I2 => \i_reg[0]__0_n_0\,
      I3 => \i_reg[2]__0_n_0\,
      I4 => \i_reg[3]__0_n_0\,
      I5 => \i_reg[4]__0_n_0\,
      O => \^d\(0)
    );
\i[4]__1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \i_reg[1]__1_n_0\,
      I1 => \j[9]__1_i_3_n_0\,
      I2 => \i_reg[0]__1_n_0\,
      I3 => \i_reg[2]__1_n_0\,
      I4 => \i_reg[3]__1_n_0\,
      I5 => \i_reg[4]__1_n_0\,
      O => \i[4]__1_i_1_n_0\
    );
\i[4]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \j[9]_i_3_n_0\,
      I2 => \i_reg_n_0_[0]\,
      I3 => \i_reg_n_0_[2]\,
      I4 => \i_reg_n_0_[3]\,
      I5 => \i_reg_n_0_[4]\,
      O => \^i_reg[6]_0\(0)
    );
\i[5]__0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \i[7]__0_i_2_n_0\,
      I1 => \i_reg[5]__0_n_0\,
      O => \^d\(1)
    );
\i[5]__1_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \i[7]__1_i_2_n_0\,
      I1 => \i_reg[5]__1_n_0\,
      O => \i[5]__1_i_1_n_0\
    );
\i[5]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \i[7]_i_2__1_n_0\,
      I1 => \i_reg_n_0_[5]\,
      O => \^i_reg[6]_0\(1)
    );
\i[6]__0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \i_reg[5]__0_n_0\,
      I1 => \i[7]__0_i_2_n_0\,
      I2 => \i_reg[6]__0_n_0\,
      O => \^d\(2)
    );
\i[6]__1_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \i[7]__1_i_2_n_0\,
      I1 => \i_reg[5]__1_n_0\,
      I2 => \i_reg[6]__1_n_0\,
      O => \i[6]__1_i_1_n_0\
    );
\i[6]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \i[7]_i_2__1_n_0\,
      I1 => \i_reg_n_0_[5]\,
      I2 => \i_reg_n_0_[6]\,
      O => p_0_in(6)
    );
\i[7]__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => \i_reg[6]__0_n_0\,
      I1 => \i[7]__0_i_2_n_0\,
      I2 => \i_reg[5]__0_n_0\,
      I3 => \i_reg[7]__0_n_0\,
      O => \^d\(3)
    );
\i[7]__0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \i_reg[4]__0_n_0\,
      I1 => \i_reg[1]__0_n_0\,
      I2 => \j[9]__0_i_3_n_0\,
      I3 => \i_reg[0]__0_n_0\,
      I4 => \i_reg[2]__0_n_0\,
      I5 => \i_reg[3]__0_n_0\,
      O => \i[7]__0_i_2_n_0\
    );
\i[7]__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B4F0"
    )
        port map (
      I0 => \i[7]__1_i_2_n_0\,
      I1 => \i_reg[5]__1_n_0\,
      I2 => \i_reg[7]__1_n_0\,
      I3 => \i_reg[6]__1_n_0\,
      O => \i[7]__1_i_1_n_0\
    );
\i[7]__1_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \i_reg[4]__1_n_0\,
      I1 => \i_reg[1]__1_n_0\,
      I2 => \j[9]__1_i_3_n_0\,
      I3 => \i_reg[0]__1_n_0\,
      I4 => \i_reg[2]__1_n_0\,
      I5 => \i_reg[3]__1_n_0\,
      O => \i[7]__1_i_2_n_0\
    );
\i[7]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B4F0"
    )
        port map (
      I0 => \i[7]_i_2__1_n_0\,
      I1 => \i_reg_n_0_[5]\,
      I2 => \i_reg_n_0_[7]\,
      I3 => \i_reg_n_0_[6]\,
      O => p_0_in(7)
    );
\i[7]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \i_reg_n_0_[4]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \j[9]_i_3_n_0\,
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[2]\,
      I5 => \i_reg_n_0_[3]\,
      O => \i[7]_i_2__1_n_0\
    );
\i[8]__0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \i[8]__0_i_2_n_0\,
      I1 => stateGreen_i_4_n_0,
      O => \i[8]__0_i_1_n_0\
    );
\i[8]__0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFBFFEFF"
    )
        port map (
      I0 => stateGreen_i_5_n_0,
      I1 => \i_reg[7]__0_n_0\,
      I2 => \i_reg[6]__0_n_0\,
      I3 => \i[7]__0_i_2_n_0\,
      I4 => \i_reg[5]__0_n_0\,
      I5 => stateGreen_i_3_n_0,
      O => \i[8]__0_i_2_n_0\
    );
\i[8]__1_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateBlue_i_4_n_0,
      I1 => stateBlue_i_5_n_0,
      O => \i[8]__1_i_1_n_0\
    );
\i[8]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateRed_i_4_n_0,
      I1 => sel0(8),
      O => p_0_in(8)
    );
\i__carry_i_10__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7AE"
    )
        port map (
      I0 => \i_reg_n_0_[7]\,
      I1 => \i_reg_n_0_[5]\,
      I2 => \i[7]_i_2__1_n_0\,
      I3 => \i_reg_n_0_[6]\,
      O => \i_reg[7]_0\
    );
\i__carry_i_10__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7AE"
    )
        port map (
      I0 => \i_reg[7]__1_n_0\,
      I1 => \i_reg[5]__1_n_0\,
      I2 => \i[7]__1_i_2_n_0\,
      I3 => \i_reg[6]__1_n_0\,
      O => \i_reg[7]__1_0\
    );
\i__carry_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \i_reg_n_0_[5]\,
      I1 => \i[7]_i_2__1_n_0\,
      I2 => \i_reg_n_0_[6]\,
      O => \^i_reg[6]_0\(2)
    );
\i__carry_i_11__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \i_reg[3]__1_n_0\,
      I1 => \i_reg[2]__1_n_0\,
      I2 => \i_reg[0]__1_n_0\,
      I3 => \j[9]__1_i_3_n_0\,
      I4 => \i_reg[1]__1_n_0\,
      O => \i__carry_i_11__0_n_0\
    );
\i__carry_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => \i_reg_n_0_[6]\,
      I1 => \i[7]_i_2__1_n_0\,
      I2 => \i_reg_n_0_[5]\,
      I3 => \i_reg_n_0_[7]\,
      O => \^i_reg[6]_0\(3)
    );
\i__carry_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"007E"
    )
        port map (
      I0 => \i__carry_i_11__0_n_0\,
      I1 => \i_reg[4]__1_n_0\,
      I2 => \i_reg[5]__1_n_0\,
      I3 => rgb0(0),
      O => \i__carry_i_2_n_0\
    );
\i__carry_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFFEAAA"
    )
        port map (
      I0 => \i_reg[2]__1_n_0\,
      I1 => \i_reg[0]__1_n_0\,
      I2 => \j[9]__1_i_3_n_0\,
      I3 => \i_reg[1]__1_n_0\,
      I4 => \i_reg[3]__1_n_0\,
      I5 => rgb0(0),
      O => \i__carry_i_3_n_0\
    );
\i__carry_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFFEAAA"
    )
        port map (
      I0 => \i_reg_n_0_[2]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \j[9]_i_3_n_0\,
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[3]\,
      I5 => rgb0(1),
      O => \i__carry_i_3__0_n_0\
    );
\i__carry_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFEAAA00000000"
    )
        port map (
      I0 => \i_reg[2]__0_n_0\,
      I1 => \i_reg[0]__0_n_0\,
      I2 => \j[9]__0_i_3_n_0\,
      I3 => \i_reg[1]__0_n_0\,
      I4 => \i_reg[3]__0_n_0\,
      I5 => \stateGreen0_inferred__0/i__carry_0\,
      O => \i__carry_i_3__1_n_0\
    );
\i__carry_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"007E"
    )
        port map (
      I0 => \i_reg[0]__1_n_0\,
      I1 => \j[9]__1_i_3_n_0\,
      I2 => \i_reg[1]__1_n_0\,
      I3 => rgb0(0),
      O => \i__carry_i_4_n_0\
    );
\i__carry_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"007E"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \j[9]_i_3_n_0\,
      I2 => \i_reg_n_0_[1]\,
      I3 => rgb0(1),
      O => \i__carry_i_4__0_n_0\
    );
\i__carry_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"007E7E7E"
    )
        port map (
      I0 => \i_reg[0]__0_n_0\,
      I1 => \j[9]__0_i_3_n_0\,
      I2 => \i_reg[1]__0_n_0\,
      I3 => Q(0),
      I4 => \seq_reg[1]_0\(0),
      O => \i__carry_i_4__1_n_0\
    );
\i__carry_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sel0(8),
      O => \i__carry_i_5_n_0\
    );
\i__carry_i_5__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => stateGreen_i_4_n_0,
      O => \i__carry_i_5__0_n_0\
    );
\i__carry_i_5__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => stateBlue_i_5_n_0,
      O => \i__carry_i_5__1_n_0\
    );
\i__carry_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88481181"
    )
        port map (
      I0 => rgb0(0),
      I1 => \i_reg[7]__1_n_0\,
      I2 => \i_reg[5]__1_n_0\,
      I3 => \i[7]__1_i_2_n_0\,
      I4 => \i_reg[6]__1_n_0\,
      O => \i__carry_i_6__0_n_0\
    );
\i__carry_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4881"
    )
        port map (
      I0 => rgb0(0),
      I1 => \i_reg[5]__1_n_0\,
      I2 => \i_reg[4]__1_n_0\,
      I3 => \i__carry_i_11__0_n_0\,
      O => \i__carry_i_7_n_0\
    );
\i__carry_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4888888881111111"
    )
        port map (
      I0 => rgb0(0),
      I1 => \i_reg[3]__1_n_0\,
      I2 => \i_reg[1]__1_n_0\,
      I3 => \j[9]__1_i_3_n_0\,
      I4 => \i_reg[0]__1_n_0\,
      I5 => \i_reg[2]__1_n_0\,
      O => \i__carry_i_8_n_0\
    );
\i__carry_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4888888881111111"
    )
        port map (
      I0 => rgb0(1),
      I1 => \i_reg_n_0_[3]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \j[9]_i_3_n_0\,
      I4 => \i_reg_n_0_[0]\,
      I5 => \i_reg_n_0_[2]\,
      O => \i__carry_i_8__0_n_0\
    );
\i__carry_i_8__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"800015552AAA8000"
    )
        port map (
      I0 => \i_reg[3]__0_n_0\,
      I1 => \i_reg[1]__0_n_0\,
      I2 => \j[9]__0_i_3_n_0\,
      I3 => \i_reg[0]__0_n_0\,
      I4 => \i_reg[2]__0_n_0\,
      I5 => \stateGreen0_inferred__0/i__carry_0\,
      O => \i__carry_i_8__1_n_0\
    );
\i__carry_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4881"
    )
        port map (
      I0 => rgb0(0),
      I1 => \i_reg[1]__1_n_0\,
      I2 => \j[9]__1_i_3_n_0\,
      I3 => \i_reg[0]__1_n_0\,
      O => \i__carry_i_9_n_0\
    );
\i__carry_i_9__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4881"
    )
        port map (
      I0 => rgb0(1),
      I1 => \i_reg_n_0_[1]\,
      I2 => \j[9]_i_3_n_0\,
      I3 => \i_reg_n_0_[0]\,
      O => \i__carry_i_9__0_n_0\
    );
\i__carry_i_9__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28818181"
    )
        port map (
      I0 => \i_reg[1]__0_n_0\,
      I1 => \j[9]__0_i_3_n_0\,
      I2 => \i_reg[0]__0_n_0\,
      I3 => \seq_reg[1]_0\(0),
      I4 => Q(0),
      O => \i__carry_i_9__1_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \sel0__0\(0),
      Q => \i_reg_n_0_[0]\
    );
\i_reg[0]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \i[0]__0_i_1__1_n_0\,
      Q => \i_reg[0]__0_n_0\
    );
\i_reg[0]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \i[0]__1_i_1__0_n_0\,
      Q => \i_reg[0]__1_n_0\
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \sel0__0\(1),
      Q => \i_reg_n_0_[1]\
    );
\i_reg[1]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \i[1]__0_i_1__1_n_0\,
      Q => \i_reg[1]__0_n_0\
    );
\i_reg[1]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \i[1]__1_i_1_n_0\,
      Q => \i_reg[1]__1_n_0\
    );
\i_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \sel0__0\(2),
      Q => \i_reg_n_0_[2]\
    );
\i_reg[2]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \i[2]__0_i_1__0_n_0\,
      Q => \i_reg[2]__0_n_0\
    );
\i_reg[2]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \i[2]__1_i_1_n_0\,
      Q => \i_reg[2]__1_n_0\
    );
\i_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \sel0__0\(3),
      Q => \i_reg_n_0_[3]\
    );
\i_reg[3]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \i[3]__0_i_1__0_n_0\,
      Q => \i_reg[3]__0_n_0\
    );
\i_reg[3]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \i[3]__1_i_1_n_0\,
      Q => \i_reg[3]__1_n_0\
    );
\i_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \^i_reg[6]_0\(0),
      Q => \i_reg_n_0_[4]\
    );
\i_reg[4]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \^d\(0),
      Q => \i_reg[4]__0_n_0\
    );
\i_reg[4]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \i[4]__1_i_1_n_0\,
      Q => \i_reg[4]__1_n_0\
    );
\i_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \^i_reg[6]_0\(1),
      Q => \i_reg_n_0_[5]\
    );
\i_reg[5]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \^d\(1),
      Q => \i_reg[5]__0_n_0\
    );
\i_reg[5]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \i[5]__1_i_1_n_0\,
      Q => \i_reg[5]__1_n_0\
    );
\i_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => p_0_in(6),
      Q => \i_reg_n_0_[6]\
    );
\i_reg[6]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \^d\(2),
      Q => \i_reg[6]__0_n_0\
    );
\i_reg[6]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \i[6]__1_i_1_n_0\,
      Q => \i_reg[6]__1_n_0\
    );
\i_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => p_0_in(7),
      Q => \i_reg_n_0_[7]\
    );
\i_reg[7]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \^d\(3),
      Q => \i_reg[7]__0_n_0\
    );
\i_reg[7]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \i[7]__1_i_1_n_0\,
      Q => \i_reg[7]__1_n_0\
    );
\i_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => p_0_in(8),
      Q => \i_reg_n_0_[8]\
    );
\i_reg[8]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \i[8]__0_i_1_n_0\,
      Q => \i_reg[8]__0_n_0\
    );
\i_reg[8]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \i[8]__1_i_1_n_0\,
      Q => \i_reg[8]__1_n_0\
    );
\j[0]__0_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \j[9]__0_i_3_n_0\,
      I1 => \j_reg[0]__0_n_0\,
      O => \j[0]__0_i_1__0_n_0\
    );
\j[0]__1_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \j[9]__1_i_3_n_0\,
      I1 => \j_reg[0]__1_n_0\,
      O => j(0)
    );
\j[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \j[9]_i_3_n_0\,
      I1 => \j_reg_n_0_[0]\,
      O => \j[0]_i_1__0_n_0\
    );
\j[1]__0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \j_reg[1]__0_n_0\,
      I1 => \j_reg[0]__0_n_0\,
      I2 => \j[9]__0_i_3_n_0\,
      O => \j[1]__0_i_1_n_0\
    );
\j[1]__1_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \j_reg[1]__1_n_0\,
      I1 => \j_reg[0]__1_n_0\,
      I2 => \j[9]__1_i_3_n_0\,
      O => j(1)
    );
\j[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \j_reg_n_0_[1]\,
      I1 => \j_reg_n_0_[0]\,
      I2 => \j[9]_i_3_n_0\,
      O => \j[1]_i_1__0_n_0\
    );
\j[2]__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => \j_reg[2]__0_n_0\,
      I1 => \j_reg[1]__0_n_0\,
      I2 => \j_reg[0]__0_n_0\,
      I3 => \j[9]__0_i_3_n_0\,
      O => \j[2]__0_i_1_n_0\
    );
\j[2]__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => \j_reg[2]__1_n_0\,
      I1 => \j_reg[1]__1_n_0\,
      I2 => \j_reg[0]__1_n_0\,
      I3 => \j[9]__1_i_3_n_0\,
      O => j(2)
    );
\j[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => \j_reg_n_0_[2]\,
      I1 => \j_reg_n_0_[1]\,
      I2 => \j_reg_n_0_[0]\,
      I3 => \j[9]_i_3_n_0\,
      O => \j[2]_i_1__0_n_0\
    );
\j[3]__0_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => \j_reg[3]__0_n_0\,
      I1 => \j_reg[0]__0_n_0\,
      I2 => \j_reg[1]__0_n_0\,
      I3 => \j_reg[2]__0_n_0\,
      I4 => \j[9]__0_i_3_n_0\,
      O => \j[3]__0_i_1_n_0\
    );
\j[3]__1_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => \j_reg[3]__1_n_0\,
      I1 => \j_reg[0]__1_n_0\,
      I2 => \j_reg[1]__1_n_0\,
      I3 => \j_reg[2]__1_n_0\,
      I4 => \j[9]__1_i_3_n_0\,
      O => j(3)
    );
\j[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => \j_reg_n_0_[3]\,
      I1 => \j_reg_n_0_[0]\,
      I2 => \j_reg_n_0_[1]\,
      I3 => \j_reg_n_0_[2]\,
      I4 => \j[9]_i_3_n_0\,
      O => \j[3]_i_1__0_n_0\
    );
\j[4]__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => \j[9]__0_i_3_n_0\,
      I1 => \j_reg[0]__0_n_0\,
      I2 => \j_reg[1]__0_n_0\,
      I3 => \j_reg[2]__0_n_0\,
      I4 => \j_reg[3]__0_n_0\,
      I5 => \j_reg[4]__0_n_0\,
      O => \j[4]__0_i_1_n_0\
    );
\j[4]__1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => \j[9]__1_i_3_n_0\,
      I1 => \j_reg[0]__1_n_0\,
      I2 => \j_reg[1]__1_n_0\,
      I3 => \j_reg[2]__1_n_0\,
      I4 => \j_reg[3]__1_n_0\,
      I5 => \j_reg[4]__1_n_0\,
      O => j(4)
    );
\j[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => \j[9]_i_3_n_0\,
      I1 => \j_reg_n_0_[0]\,
      I2 => \j_reg_n_0_[1]\,
      I3 => \j_reg_n_0_[2]\,
      I4 => \j_reg_n_0_[3]\,
      I5 => \j_reg_n_0_[4]\,
      O => \j[4]_i_1__0_n_0\
    );
\j[5]__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => \j_reg[5]__0_n_0\,
      I1 => \j_reg[4]__0_n_0\,
      I2 => \j[7]__0_i_2_n_0\,
      I3 => \j[9]__0_i_3_n_0\,
      O => \j[5]__0_i_1_n_0\
    );
\j[5]__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => \j_reg[5]__1_n_0\,
      I1 => \j_reg[4]__1_n_0\,
      I2 => \j[7]__1_i_2_n_0\,
      I3 => \j[9]__1_i_3_n_0\,
      O => j(5)
    );
\j[5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => \j_reg_n_0_[5]\,
      I1 => \j_reg_n_0_[4]\,
      I2 => \j[7]_i_2__0_n_0\,
      I3 => \j[9]_i_3_n_0\,
      O => \j[5]_i_1__0_n_0\
    );
\j[6]__0_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => \j_reg[6]__0_n_0\,
      I1 => \j[7]__0_i_2_n_0\,
      I2 => \j_reg[4]__0_n_0\,
      I3 => \j_reg[5]__0_n_0\,
      I4 => \j[9]__0_i_3_n_0\,
      O => \j[6]__0_i_1_n_0\
    );
\j[6]__1_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => \j_reg[6]__1_n_0\,
      I1 => \j[7]__1_i_2_n_0\,
      I2 => \j_reg[4]__1_n_0\,
      I3 => \j_reg[5]__1_n_0\,
      I4 => \j[9]__1_i_3_n_0\,
      O => j(6)
    );
\j[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => \j_reg_n_0_[6]\,
      I1 => \j[7]_i_2__0_n_0\,
      I2 => \j_reg_n_0_[4]\,
      I3 => \j_reg_n_0_[5]\,
      I4 => \j[9]_i_3_n_0\,
      O => \j[6]_i_1__0_n_0\
    );
\j[7]__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000006AAAAAAA"
    )
        port map (
      I0 => \j_reg[7]__0_n_0\,
      I1 => \j_reg[5]__0_n_0\,
      I2 => \j_reg[4]__0_n_0\,
      I3 => \j[7]__0_i_2_n_0\,
      I4 => \j_reg[6]__0_n_0\,
      I5 => \j[9]__0_i_3_n_0\,
      O => \j[7]__0_i_1_n_0\
    );
\j[7]__0_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \j_reg[3]__0_n_0\,
      I1 => \j_reg[2]__0_n_0\,
      I2 => \j_reg[1]__0_n_0\,
      I3 => \j_reg[0]__0_n_0\,
      O => \j[7]__0_i_2_n_0\
    );
\j[7]__1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000006AAAAAAA"
    )
        port map (
      I0 => \j_reg[7]__1_n_0\,
      I1 => \j_reg[5]__1_n_0\,
      I2 => \j_reg[4]__1_n_0\,
      I3 => \j[7]__1_i_2_n_0\,
      I4 => \j_reg[6]__1_n_0\,
      I5 => \j[9]__1_i_3_n_0\,
      O => j(7)
    );
\j[7]__1_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \j_reg[3]__1_n_0\,
      I1 => \j_reg[2]__1_n_0\,
      I2 => \j_reg[1]__1_n_0\,
      I3 => \j_reg[0]__1_n_0\,
      O => \j[7]__1_i_2_n_0\
    );
\j[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000006AAAAAAA"
    )
        port map (
      I0 => \j_reg_n_0_[7]\,
      I1 => \j_reg_n_0_[5]\,
      I2 => \j_reg_n_0_[4]\,
      I3 => \j[7]_i_2__0_n_0\,
      I4 => \j_reg_n_0_[6]\,
      I5 => \j[9]_i_3_n_0\,
      O => \j[7]_i_1__0_n_0\
    );
\j[7]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \j_reg_n_0_[3]\,
      I1 => \j_reg_n_0_[2]\,
      I2 => \j_reg_n_0_[1]\,
      I3 => \j_reg_n_0_[0]\,
      O => \j[7]_i_2__0_n_0\
    );
\j[8]__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000A6AAAAAA"
    )
        port map (
      I0 => \j_reg[8]__0_n_0\,
      I1 => \j_reg[6]__0_n_0\,
      I2 => \j[8]__0_i_2_n_0\,
      I3 => \j_reg[5]__0_n_0\,
      I4 => \j_reg[7]__0_n_0\,
      I5 => \j[9]__0_i_3_n_0\,
      O => \j[8]__0_i_1_n_0\
    );
\j[8]__0_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \j_reg[4]__0_n_0\,
      I1 => \j_reg[0]__0_n_0\,
      I2 => \j_reg[1]__0_n_0\,
      I3 => \j_reg[2]__0_n_0\,
      I4 => \j_reg[3]__0_n_0\,
      O => \j[8]__0_i_2_n_0\
    );
\j[8]__1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000A6AAAAAA"
    )
        port map (
      I0 => \j_reg[8]__1_n_0\,
      I1 => \j_reg[6]__1_n_0\,
      I2 => \j[8]__1_i_2_n_0\,
      I3 => \j_reg[5]__1_n_0\,
      I4 => \j_reg[7]__1_n_0\,
      I5 => \j[9]__1_i_3_n_0\,
      O => j(8)
    );
\j[8]__1_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \j_reg[4]__1_n_0\,
      I1 => \j_reg[0]__1_n_0\,
      I2 => \j_reg[1]__1_n_0\,
      I3 => \j_reg[2]__1_n_0\,
      I4 => \j_reg[3]__1_n_0\,
      O => \j[8]__1_i_2_n_0\
    );
\j[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000A6AAAAAA"
    )
        port map (
      I0 => \j_reg_n_0_[8]\,
      I1 => \j_reg_n_0_[6]\,
      I2 => \j[8]_i_2_n_0\,
      I3 => \j_reg_n_0_[5]\,
      I4 => \j_reg_n_0_[7]\,
      I5 => \j[9]_i_3_n_0\,
      O => \j[8]_i_1_n_0\
    );
\j[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \j_reg_n_0_[4]\,
      I1 => \j_reg_n_0_[0]\,
      I2 => \j_reg_n_0_[1]\,
      I3 => \j_reg_n_0_[2]\,
      I4 => \j_reg_n_0_[3]\,
      O => \j[8]_i_2_n_0\
    );
\j[9]__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000A6AAAAAA"
    )
        port map (
      I0 => \j_reg[9]__0_n_0\,
      I1 => \j_reg[7]__0_n_0\,
      I2 => \j[9]__0_i_2_n_0\,
      I3 => \j_reg[6]__0_n_0\,
      I4 => \j_reg[8]__0_n_0\,
      I5 => \j[9]__0_i_3_n_0\,
      O => \j[9]__0_i_1_n_0\
    );
\j[9]__0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \j_reg[3]__0_n_0\,
      I1 => \j_reg[2]__0_n_0\,
      I2 => \j_reg[1]__0_n_0\,
      I3 => \j_reg[0]__0_n_0\,
      I4 => \j_reg[4]__0_n_0\,
      I5 => \j_reg[5]__0_n_0\,
      O => \j[9]__0_i_2_n_0\
    );
\j[9]__0_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000008000000000"
    )
        port map (
      I0 => \j[9]__0_i_4_n_0\,
      I1 => \j_reg[9]__0_n_0\,
      I2 => \j_reg[7]__0_n_0\,
      I3 => \j[9]__0_i_2_n_0\,
      I4 => \j_reg[6]__0_n_0\,
      I5 => \j_reg[8]__0_n_0\,
      O => \j[9]__0_i_3_n_0\
    );
\j[9]__0_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000020000000"
    )
        port map (
      I0 => \j_reg[5]__0_n_0\,
      I1 => \j_reg[4]__0_n_0\,
      I2 => \j_reg[0]__0_n_0\,
      I3 => \j_reg[1]__0_n_0\,
      I4 => \j_reg[2]__0_n_0\,
      I5 => \j_reg[3]__0_n_0\,
      O => \j[9]__0_i_4_n_0\
    );
\j[9]__1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000A6AAAAAA"
    )
        port map (
      I0 => \j_reg[9]__1_n_0\,
      I1 => \j_reg[7]__1_n_0\,
      I2 => \j[9]__1_i_2_n_0\,
      I3 => \j_reg[6]__1_n_0\,
      I4 => \j_reg[8]__1_n_0\,
      I5 => \j[9]__1_i_3_n_0\,
      O => j(9)
    );
\j[9]__1_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \j_reg[3]__1_n_0\,
      I1 => \j_reg[2]__1_n_0\,
      I2 => \j_reg[1]__1_n_0\,
      I3 => \j_reg[0]__1_n_0\,
      I4 => \j_reg[4]__1_n_0\,
      I5 => \j_reg[5]__1_n_0\,
      O => \j[9]__1_i_2_n_0\
    );
\j[9]__1_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000008000000000"
    )
        port map (
      I0 => \j[9]__1_i_4_n_0\,
      I1 => \j_reg[9]__1_n_0\,
      I2 => \j_reg[7]__1_n_0\,
      I3 => \j[9]__1_i_2_n_0\,
      I4 => \j_reg[6]__1_n_0\,
      I5 => \j_reg[8]__1_n_0\,
      O => \j[9]__1_i_3_n_0\
    );
\j[9]__1_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000020000000"
    )
        port map (
      I0 => \j_reg[5]__1_n_0\,
      I1 => \j_reg[4]__1_n_0\,
      I2 => \j_reg[0]__1_n_0\,
      I3 => \j_reg[1]__1_n_0\,
      I4 => \j_reg[2]__1_n_0\,
      I5 => \j_reg[3]__1_n_0\,
      O => \j[9]__1_i_4_n_0\
    );
\j[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000A6AAAAAA"
    )
        port map (
      I0 => \j_reg_n_0_[9]\,
      I1 => \j_reg_n_0_[7]\,
      I2 => \j[9]_i_2_n_0\,
      I3 => \j_reg_n_0_[6]\,
      I4 => \j_reg_n_0_[8]\,
      I5 => \j[9]_i_3_n_0\,
      O => \j[9]_i_1_n_0\
    );
\j[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \j_reg_n_0_[3]\,
      I1 => \j_reg_n_0_[2]\,
      I2 => \j_reg_n_0_[1]\,
      I3 => \j_reg_n_0_[0]\,
      I4 => \j_reg_n_0_[4]\,
      I5 => \j_reg_n_0_[5]\,
      O => \j[9]_i_2_n_0\
    );
\j[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000008000000000"
    )
        port map (
      I0 => \j[9]_i_4_n_0\,
      I1 => \j_reg_n_0_[9]\,
      I2 => \j_reg_n_0_[7]\,
      I3 => \j[9]_i_2_n_0\,
      I4 => \j_reg_n_0_[6]\,
      I5 => \j_reg_n_0_[8]\,
      O => \j[9]_i_3_n_0\
    );
\j[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000020000000"
    )
        port map (
      I0 => \j_reg_n_0_[5]\,
      I1 => \j_reg_n_0_[4]\,
      I2 => \j_reg_n_0_[0]\,
      I3 => \j_reg_n_0_[1]\,
      I4 => \j_reg_n_0_[2]\,
      I5 => \j_reg_n_0_[3]\,
      O => \j[9]_i_4_n_0\
    );
\j_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[0]_i_1__0_n_0\,
      Q => \j_reg_n_0_[0]\
    );
\j_reg[0]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[0]__0_i_1__0_n_0\,
      Q => \j_reg[0]__0_n_0\
    );
\j_reg[0]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => j(0),
      Q => \j_reg[0]__1_n_0\
    );
\j_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[1]_i_1__0_n_0\,
      Q => \j_reg_n_0_[1]\
    );
\j_reg[1]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[1]__0_i_1_n_0\,
      Q => \j_reg[1]__0_n_0\
    );
\j_reg[1]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => j(1),
      Q => \j_reg[1]__1_n_0\
    );
\j_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[2]_i_1__0_n_0\,
      Q => \j_reg_n_0_[2]\
    );
\j_reg[2]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[2]__0_i_1_n_0\,
      Q => \j_reg[2]__0_n_0\
    );
\j_reg[2]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => j(2),
      Q => \j_reg[2]__1_n_0\
    );
\j_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[3]_i_1__0_n_0\,
      Q => \j_reg_n_0_[3]\
    );
\j_reg[3]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[3]__0_i_1_n_0\,
      Q => \j_reg[3]__0_n_0\
    );
\j_reg[3]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => j(3),
      Q => \j_reg[3]__1_n_0\
    );
\j_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[4]_i_1__0_n_0\,
      Q => \j_reg_n_0_[4]\
    );
\j_reg[4]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[4]__0_i_1_n_0\,
      Q => \j_reg[4]__0_n_0\
    );
\j_reg[4]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => j(4),
      Q => \j_reg[4]__1_n_0\
    );
\j_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[5]_i_1__0_n_0\,
      Q => \j_reg_n_0_[5]\
    );
\j_reg[5]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[5]__0_i_1_n_0\,
      Q => \j_reg[5]__0_n_0\
    );
\j_reg[5]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => j(5),
      Q => \j_reg[5]__1_n_0\
    );
\j_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[6]_i_1__0_n_0\,
      Q => \j_reg_n_0_[6]\
    );
\j_reg[6]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[6]__0_i_1_n_0\,
      Q => \j_reg[6]__0_n_0\
    );
\j_reg[6]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => j(6),
      Q => \j_reg[6]__1_n_0\
    );
\j_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[7]_i_1__0_n_0\,
      Q => \j_reg_n_0_[7]\
    );
\j_reg[7]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[7]__0_i_1_n_0\,
      Q => \j_reg[7]__0_n_0\
    );
\j_reg[7]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => j(7),
      Q => \j_reg[7]__1_n_0\
    );
\j_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[8]_i_1_n_0\,
      Q => \j_reg_n_0_[8]\
    );
\j_reg[8]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[8]__0_i_1_n_0\,
      Q => \j_reg[8]__0_n_0\
    );
\j_reg[8]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => j(8),
      Q => \j_reg[8]__1_n_0\
    );
\j_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[9]_i_1_n_0\,
      Q => \j_reg_n_0_[9]\
    );
\j_reg[9]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => \j[9]__0_i_1_n_0\,
      Q => \j_reg[9]__0_n_0\
    );
\j_reg[9]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => j(9),
      Q => \j_reg[9]__1_n_0\
    );
\stateBlue0_inferred__0/i__carry\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_stateBlue0_inferred__0/i__carry_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \stateBlue0_inferred__0/i__carry_n_3\,
      CO(3) => \stateBlue0_inferred__0/i__carry_n_4\,
      CO(2) => \stateBlue0_inferred__0/i__carry_n_5\,
      CO(1) => \stateBlue0_inferred__0/i__carry_n_6\,
      CO(0) => \stateBlue0_inferred__0/i__carry_n_7\,
      DI(7 downto 4) => B"0001",
      DI(3) => stateBlue_i_2_0(0),
      DI(2) => \i__carry_i_2_n_0\,
      DI(1) => \i__carry_i_3_n_0\,
      DI(0) => \i__carry_i_4_n_0\,
      O(7 downto 0) => \NLW_stateBlue0_inferred__0/i__carry_O_UNCONNECTED\(7 downto 0),
      S(7 downto 5) => B"000",
      S(4) => \i__carry_i_5__1_n_0\,
      S(3) => \i__carry_i_6__0_n_0\,
      S(2) => \i__carry_i_7_n_0\,
      S(1) => \i__carry_i_8_n_0\,
      S(0) => \i__carry_i_9_n_0\
    );
stateBlue_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"770F770077007700"
    )
        port map (
      I0 => stateBlue_i_2_n_0,
      I1 => stateBlue_i_3_n_0,
      I2 => stateBlue_i_4_n_0,
      I3 => \^rgb0_b\,
      I4 => stateBlue_i_5_n_0,
      I5 => rgb0(0),
      O => stateBlue_i_1_n_0
    );
stateBlue_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateBlue0_inferred__0/i__carry_n_3\,
      I1 => stateBlue_i_7_n_0,
      O => stateBlue_i_2_n_0
    );
stateBlue_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFDFFFF"
    )
        port map (
      I0 => \i_reg[8]__1_n_0\,
      I1 => stateBlue_i_8_n_0,
      I2 => \i_reg[7]__1_n_0\,
      I3 => \i_reg[5]__1_n_0\,
      I4 => \i[7]__1_i_2_n_0\,
      I5 => \i_reg[6]__1_n_0\,
      O => stateBlue_i_3_n_0
    );
stateBlue_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFBFFEFF"
    )
        port map (
      I0 => stateBlue_i_8_n_0,
      I1 => \i_reg[7]__1_n_0\,
      I2 => \i_reg[6]__1_n_0\,
      I3 => \i[7]__1_i_2_n_0\,
      I4 => \i_reg[5]__1_n_0\,
      I5 => stateBlue_i_7_n_0,
      O => stateBlue_i_4_n_0
    );
stateBlue_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFF2000"
    )
        port map (
      I0 => \i_reg[5]__1_n_0\,
      I1 => \i[7]__1_i_2_n_0\,
      I2 => \i_reg[6]__1_n_0\,
      I3 => \i_reg[7]__1_n_0\,
      I4 => \i_reg[8]__1_n_0\,
      O => stateBlue_i_5_n_0
    );
stateBlue_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F6FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \j_reg[3]__1_n_0\,
      I1 => \j_reg[4]__1_n_0\,
      I2 => stateBlue_i_9_n_0,
      I3 => \j_reg[2]__1_n_0\,
      I4 => \j_reg[1]__1_n_0\,
      I5 => \j_reg[0]__1_n_0\,
      O => stateBlue_i_7_n_0
    );
stateBlue_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \i_reg[4]__1_n_0\,
      I1 => \i_reg[2]__1_n_0\,
      I2 => \i_reg[0]__1_n_0\,
      I3 => \j[9]__1_i_3_n_0\,
      I4 => \i_reg[1]__1_n_0\,
      I5 => \i_reg[3]__1_n_0\,
      O => stateBlue_i_8_n_0
    );
stateBlue_i_9: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \j_reg[5]__1_n_0\,
      I1 => \j_reg[8]__1_n_0\,
      I2 => \j_reg[9]__1_n_0\,
      I3 => \j_reg[7]__1_n_0\,
      I4 => \j_reg[6]__1_n_0\,
      O => stateBlue_i_9_n_0
    );
stateBlue_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => stateBlue_i_1_n_0,
      Q => \^rgb0_b\
    );
\stateGreen0_inferred__0/i__carry\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_stateGreen0_inferred__0/i__carry_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \stateGreen0_inferred__0/i__carry_n_3\,
      CO(3) => \stateGreen0_inferred__0/i__carry_n_4\,
      CO(2) => \stateGreen0_inferred__0/i__carry_n_5\,
      CO(1) => \stateGreen0_inferred__0/i__carry_n_6\,
      CO(0) => \stateGreen0_inferred__0/i__carry_n_7\,
      DI(7 downto 4) => B"0001",
      DI(3 downto 2) => stateGreen_reg_0(1 downto 0),
      DI(1) => \i__carry_i_3__1_n_0\,
      DI(0) => \i__carry_i_4__1_n_0\,
      O(7 downto 0) => \NLW_stateGreen0_inferred__0/i__carry_O_UNCONNECTED\(7 downto 0),
      S(7 downto 5) => B"000",
      S(4) => \i__carry_i_5__0_n_0\,
      S(3 downto 2) => stateGreen_reg_1(1 downto 0),
      S(1) => \i__carry_i_8__1_n_0\,
      S(0) => \i__carry_i_9__1_n_0\
    );
stateGreen_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF3F000AFF330000"
    )
        port map (
      I0 => \seq_reg[1]_0\(0),
      I1 => \stateGreen0_inferred__0/i__carry_n_3\,
      I2 => stateGreen_i_2_n_0,
      I3 => stateGreen_i_3_n_0,
      I4 => \^rgb0_g\,
      I5 => stateGreen_i_4_n_0,
      O => stateGreen_i_1_n_0
    );
stateGreen_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDFFB"
    )
        port map (
      I0 => \i_reg[5]__0_n_0\,
      I1 => \i[7]__0_i_2_n_0\,
      I2 => \i_reg[6]__0_n_0\,
      I3 => \i_reg[7]__0_n_0\,
      I4 => stateGreen_i_5_n_0,
      O => stateGreen_i_2_n_0
    );
stateGreen_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F6FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \j_reg[3]__0_n_0\,
      I1 => \j_reg[4]__0_n_0\,
      I2 => stateGreen_i_6_n_0,
      I3 => \j_reg[2]__0_n_0\,
      I4 => \j_reg[1]__0_n_0\,
      I5 => \j_reg[0]__0_n_0\,
      O => stateGreen_i_3_n_0
    );
stateGreen_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFF2000"
    )
        port map (
      I0 => \i_reg[5]__0_n_0\,
      I1 => \i[7]__0_i_2_n_0\,
      I2 => \i_reg[6]__0_n_0\,
      I3 => \i_reg[7]__0_n_0\,
      I4 => \i_reg[8]__0_n_0\,
      O => stateGreen_i_4_n_0
    );
stateGreen_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \i_reg[4]__0_n_0\,
      I1 => \i_reg[2]__0_n_0\,
      I2 => \i_reg[0]__0_n_0\,
      I3 => \j[9]__0_i_3_n_0\,
      I4 => \i_reg[1]__0_n_0\,
      I5 => \i_reg[3]__0_n_0\,
      O => stateGreen_i_5_n_0
    );
stateGreen_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \j_reg[5]__0_n_0\,
      I1 => \j_reg[8]__0_n_0\,
      I2 => \j_reg[9]__0_n_0\,
      I3 => \j_reg[7]__0_n_0\,
      I4 => \j_reg[6]__0_n_0\,
      O => stateGreen_i_6_n_0
    );
stateGreen_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => stateGreen_i_1_n_0,
      Q => \^rgb0_g\
    );
\stateRed0_inferred__0/i__carry\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_stateRed0_inferred__0/i__carry_CO_UNCONNECTED\(7 downto 5),
      CO(4) => data0,
      CO(3) => \stateRed0_inferred__0/i__carry_n_4\,
      CO(2) => \stateRed0_inferred__0/i__carry_n_5\,
      CO(1) => \stateRed0_inferred__0/i__carry_n_6\,
      CO(0) => \stateRed0_inferred__0/i__carry_n_7\,
      DI(7 downto 4) => B"0001",
      DI(3 downto 2) => DI(1 downto 0),
      DI(1) => \i__carry_i_3__0_n_0\,
      DI(0) => \i__carry_i_4__0_n_0\,
      O(7 downto 0) => \NLW_stateRed0_inferred__0/i__carry_O_UNCONNECTED\(7 downto 0),
      S(7 downto 5) => B"000",
      S(4) => \i__carry_i_5_n_0\,
      S(3 downto 2) => S(1 downto 0),
      S(1) => \i__carry_i_8__0_n_0\,
      S(0) => \i__carry_i_9__0_n_0\
    );
stateRed_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"770F770077007700"
    )
        port map (
      I0 => stateRed_i_2_n_0,
      I1 => stateRed_i_3_n_0,
      I2 => stateRed_i_4_n_0,
      I3 => \^rgb0_r\,
      I4 => sel0(8),
      I5 => rgb0(1),
      O => stateRed_i_1_n_0
    );
stateRed_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => data0,
      I1 => stateRed_i_7_n_0,
      O => stateRed_i_2_n_0
    );
stateRed_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFDFFFF"
    )
        port map (
      I0 => \i_reg_n_0_[8]\,
      I1 => stateRed_i_8_n_0,
      I2 => \i_reg_n_0_[7]\,
      I3 => \i_reg_n_0_[5]\,
      I4 => \i[7]_i_2__1_n_0\,
      I5 => \i_reg_n_0_[6]\,
      O => stateRed_i_3_n_0
    );
stateRed_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFBFFEFF"
    )
        port map (
      I0 => stateRed_i_8_n_0,
      I1 => \i_reg_n_0_[7]\,
      I2 => \i_reg_n_0_[6]\,
      I3 => \i[7]_i_2__1_n_0\,
      I4 => \i_reg_n_0_[5]\,
      I5 => stateRed_i_7_n_0,
      O => stateRed_i_4_n_0
    );
stateRed_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFF2000"
    )
        port map (
      I0 => \i_reg_n_0_[5]\,
      I1 => \i[7]_i_2__1_n_0\,
      I2 => \i_reg_n_0_[6]\,
      I3 => \i_reg_n_0_[7]\,
      I4 => \i_reg_n_0_[8]\,
      O => sel0(8)
    );
stateRed_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F6FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \j_reg_n_0_[3]\,
      I1 => \j_reg_n_0_[4]\,
      I2 => p_2_in,
      I3 => \j_reg_n_0_[2]\,
      I4 => \j_reg_n_0_[1]\,
      I5 => \j_reg_n_0_[0]\,
      O => stateRed_i_7_n_0
    );
stateRed_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \i_reg_n_0_[4]\,
      I1 => \i_reg_n_0_[2]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => \j[9]_i_3_n_0\,
      I4 => \i_reg_n_0_[1]\,
      I5 => \i_reg_n_0_[3]\,
      O => stateRed_i_8_n_0
    );
stateRed_i_9: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \j_reg_n_0_[5]\,
      I1 => \j_reg_n_0_[8]\,
      I2 => \j_reg_n_0_[9]\,
      I3 => \j_reg_n_0_[7]\,
      I4 => \j_reg_n_0_[6]\,
      O => p_2_in
    );
stateRed_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \i_reg[0]__1_0\(0),
      D => stateRed_i_1_n_0,
      Q => \^rgb0_r\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Rotary is
  port (
    ackInvRotaryMoveto : out STD_LOGIC;
    ackInvRotarySet : out STD_LOGIC;
    ackInvRotaryZero : out STD_LOGIC;
    ackInvRotaryConfig : out STD_LOGIC;
    rng_reg_0 : out STD_LOGIC;
    O : out STD_LOGIC_VECTOR ( 5 downto 0 );
    CO : out STD_LOGIC_VECTOR ( 0 to 0 );
    \invbuf_reg[0][5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \i__carry_i_11__1_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \invbuf_reg[0][5]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    dir : out STD_LOGIC;
    step : out STD_LOGIC;
    m0z : out STD_LOGIC;
    m0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \stateOp_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rng_reg_1 : out STD_LOGIC;
    step_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    aclk_sig : in STD_LOGIC;
    \tixVStepmode_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    ackInvSet_sig : in STD_LOGIC;
    ackInvZero_sig_reg_0 : in STD_LOGIC;
    targetNotSteady : in STD_LOGIC;
    reqInvRotaryMoveto : in STD_LOGIC;
    ccwNotCw0 : in STD_LOGIC;
    rng_reg_2 : in STD_LOGIC;
    ccwNotCw_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \i__carry_i_11__1_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \tixVStepmode_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ccwNotCw_reg_1 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    ccwNotCw_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    DI : in STD_LOGIC_VECTOR ( 2 downto 0 );
    ccwNotCw_reg_3 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    dir_0 : in STD_LOGIC;
    tkclk : in STD_LOGIC;
    \step1__6\ : in STD_LOGIC;
    \i_reg[3]_0\ : in STD_LOGIC;
    \stateOp_reg[1]_1\ : in STD_LOGIC;
    ccwNotCw5_in : in STD_LOGIC;
    reqInvRotaryConfig : in STD_LOGIC;
    reqInvRotaryZero : in STD_LOGIC;
    \ackInvConfig_sig0__6\ : in STD_LOGIC;
    \capt_reg[5]\ : in STD_LOGIC;
    \lsb_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateOp_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Rotary : entity is "Rotary";
end design_1_Vsp_core_0_0_Rotary;

architecture STRUCTURE of design_1_Vsp_core_0_0_Rotary is
  signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^o\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal TStep : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal ackInvZero_sig : STD_LOGIC;
  signal \angle1__15\ : STD_LOGIC;
  signal \angle[0]_i_1_n_0\ : STD_LOGIC;
  signal \angle[10]_i_1_n_0\ : STD_LOGIC;
  signal \angle[10]_i_2_n_0\ : STD_LOGIC;
  signal \angle[10]_i_3_n_0\ : STD_LOGIC;
  signal \angle[11]_i_1_n_0\ : STD_LOGIC;
  signal \angle[11]_i_3_n_0\ : STD_LOGIC;
  signal \angle[12]_i_1_n_0\ : STD_LOGIC;
  signal \angle[12]_i_2_n_0\ : STD_LOGIC;
  signal \angle[12]_i_3_n_0\ : STD_LOGIC;
  signal \angle[12]_i_4_n_0\ : STD_LOGIC;
  signal \angle[12]_i_5_n_0\ : STD_LOGIC;
  signal \angle[12]_i_7_n_0\ : STD_LOGIC;
  signal \angle[13]_i_1_n_0\ : STD_LOGIC;
  signal \angle[13]_i_2_n_0\ : STD_LOGIC;
  signal \angle[13]_i_3_n_0\ : STD_LOGIC;
  signal \angle[13]_i_4_n_0\ : STD_LOGIC;
  signal \angle[13]_i_5_n_0\ : STD_LOGIC;
  signal \angle[13]_i_7_n_0\ : STD_LOGIC;
  signal \angle[13]_i_8_n_0\ : STD_LOGIC;
  signal \angle[13]_i_9_n_0\ : STD_LOGIC;
  signal \angle[1]_i_1_n_0\ : STD_LOGIC;
  signal \angle[1]_i_2_n_0\ : STD_LOGIC;
  signal \angle[2]_i_1_n_0\ : STD_LOGIC;
  signal \angle[2]_i_3_n_0\ : STD_LOGIC;
  signal \angle[3]_i_1_n_0\ : STD_LOGIC;
  signal \angle[3]_i_3_n_0\ : STD_LOGIC;
  signal \angle[4]_i_1_n_0\ : STD_LOGIC;
  signal \angle[5]_i_1_n_0\ : STD_LOGIC;
  signal \angle[5]_i_2_n_0\ : STD_LOGIC;
  signal \angle[5]_i_3_n_0\ : STD_LOGIC;
  signal \angle[6]_i_1_n_0\ : STD_LOGIC;
  signal \angle[6]_i_2_n_0\ : STD_LOGIC;
  signal \angle[6]_i_3_n_0\ : STD_LOGIC;
  signal \angle[6]_i_4_n_0\ : STD_LOGIC;
  signal \angle[7]_i_1_n_0\ : STD_LOGIC;
  signal \angle[7]_i_2_n_0\ : STD_LOGIC;
  signal \angle[7]_i_3_n_0\ : STD_LOGIC;
  signal \angle[7]_i_4_n_0\ : STD_LOGIC;
  signal \angle[8]_i_1_n_0\ : STD_LOGIC;
  signal \angle[8]_i_2_n_0\ : STD_LOGIC;
  signal \angle[8]_i_3_n_0\ : STD_LOGIC;
  signal \angle[8]_i_4_n_0\ : STD_LOGIC;
  signal \angle[9]_i_1_n_0\ : STD_LOGIC;
  signal \angle[9]_i_2_n_0\ : STD_LOGIC;
  signal \angle__2\ : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal ccwNotCw1_carry_i_1_n_0 : STD_LOGIC;
  signal ccwNotCw1_carry_n_5 : STD_LOGIC;
  signal ccwNotCw1_carry_n_6 : STD_LOGIC;
  signal ccwNotCw1_carry_n_7 : STD_LOGIC;
  signal \ccwNotCw1_inferred__0/i__carry_n_1\ : STD_LOGIC;
  signal \ccwNotCw1_inferred__0/i__carry_n_2\ : STD_LOGIC;
  signal \ccwNotCw1_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal \ccwNotCw1_inferred__0/i__carry_n_4\ : STD_LOGIC;
  signal \ccwNotCw1_inferred__0/i__carry_n_5\ : STD_LOGIC;
  signal \ccwNotCw1_inferred__0/i__carry_n_6\ : STD_LOGIC;
  signal \ccwNotCw1_inferred__0/i__carry_n_7\ : STD_LOGIC;
  signal \ccwNotCw1_inferred__1/i__carry_n_2\ : STD_LOGIC;
  signal \ccwNotCw1_inferred__1/i__carry_n_3\ : STD_LOGIC;
  signal \ccwNotCw1_inferred__1/i__carry_n_4\ : STD_LOGIC;
  signal \ccwNotCw1_inferred__1/i__carry_n_5\ : STD_LOGIC;
  signal \ccwNotCw1_inferred__1/i__carry_n_6\ : STD_LOGIC;
  signal \ccwNotCw1_inferred__1/i__carry_n_7\ : STD_LOGIC;
  signal ccwNotCw2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \ccwNotCw2_carry__0_n_3\ : STD_LOGIC;
  signal \ccwNotCw2_carry__0_n_4\ : STD_LOGIC;
  signal \ccwNotCw2_carry__0_n_5\ : STD_LOGIC;
  signal \ccwNotCw2_carry__0_n_6\ : STD_LOGIC;
  signal \ccwNotCw2_carry__0_n_7\ : STD_LOGIC;
  signal ccwNotCw2_carry_n_0 : STD_LOGIC;
  signal ccwNotCw2_carry_n_1 : STD_LOGIC;
  signal ccwNotCw2_carry_n_2 : STD_LOGIC;
  signal ccwNotCw2_carry_n_3 : STD_LOGIC;
  signal ccwNotCw2_carry_n_4 : STD_LOGIC;
  signal ccwNotCw2_carry_n_5 : STD_LOGIC;
  signal ccwNotCw2_carry_n_6 : STD_LOGIC;
  signal ccwNotCw2_carry_n_7 : STD_LOGIC;
  signal i : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \i[5]_i_2__6_n_0\ : STD_LOGIC;
  signal \i[7]_i_1__10_n_0\ : STD_LOGIC;
  signal \i[7]_i_4__0_n_0\ : STD_LOGIC;
  signal \i__3\ : STD_LOGIC;
  signal \i__carry_i_10__3_n_0\ : STD_LOGIC;
  signal \i__carry_i_11__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_11__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_12__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_13_n_0\ : STD_LOGIC;
  signal \i__carry_i_1__4_n_0\ : STD_LOGIC;
  signal \i__carry_i_2__3_n_0\ : STD_LOGIC;
  signal \i__carry_i_3__3_n_0\ : STD_LOGIC;
  signal \i__carry_i_5__4_n_0\ : STD_LOGIC;
  signal \i__carry_i_6__3_n_0\ : STD_LOGIC;
  signal \i__carry_i_7__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_8__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_9__3_n_0\ : STD_LOGIC;
  signal lsb : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m0_INST_0_i_1_n_0 : STD_LOGIC;
  signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^rng_reg_0\ : STD_LOGIC;
  signal rotaryToStepmuxDir : STD_LOGIC;
  signal rotaryToStepmuxStep : STD_LOGIC;
  signal stateOp121_in : STD_LOGIC;
  signal \stateOp4__26\ : STD_LOGIC;
  signal stateOp50_out : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \stateOp6__2\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \stateOp[0]_i_5__1_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_10__2_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_2__10_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_5__4_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_6__3_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_7__2_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_8__3_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_9__2_n_0\ : STD_LOGIC;
  signal \^stateop_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal step_i_1_n_0 : STD_LOGIC;
  signal step_i_2_n_0 : STD_LOGIC;
  signal step_i_3_n_0 : STD_LOGIC;
  signal step_i_4_n_0 : STD_LOGIC;
  signal step_i_5_n_0 : STD_LOGIC;
  signal step_i_6_n_0 : STD_LOGIC;
  signal targetNotSteady_reg_n_0 : STD_LOGIC;
  signal \target_reg_n_0_[0]\ : STD_LOGIC;
  signal \target_reg_n_0_[10]\ : STD_LOGIC;
  signal \target_reg_n_0_[11]\ : STD_LOGIC;
  signal \target_reg_n_0_[12]\ : STD_LOGIC;
  signal \target_reg_n_0_[13]\ : STD_LOGIC;
  signal \target_reg_n_0_[1]\ : STD_LOGIC;
  signal \target_reg_n_0_[2]\ : STD_LOGIC;
  signal \target_reg_n_0_[3]\ : STD_LOGIC;
  signal \target_reg_n_0_[4]\ : STD_LOGIC;
  signal \target_reg_n_0_[5]\ : STD_LOGIC;
  signal \target_reg_n_0_[6]\ : STD_LOGIC;
  signal \target_reg_n_0_[7]\ : STD_LOGIC;
  signal \target_reg_n_0_[8]\ : STD_LOGIC;
  signal \target_reg_n_0_[9]\ : STD_LOGIC;
  signal tixVStepmode : STD_LOGIC;
  signal \tixVStepmode_reg_n_0_[0]\ : STD_LOGIC;
  signal \tixVStepmode_reg_n_0_[1]\ : STD_LOGIC;
  signal \tixVStepmode_reg_n_0_[2]\ : STD_LOGIC;
  signal \tixVStepmode_reg_n_0_[3]\ : STD_LOGIC;
  signal \tixVStepmode_reg_n_0_[4]\ : STD_LOGIC;
  signal \tixVStepmode_reg_n_0_[5]\ : STD_LOGIC;
  signal \tixVStepmode_reg_n_0_[6]\ : STD_LOGIC;
  signal \tixVStepmode_reg_n_0_[7]\ : STD_LOGIC;
  signal NLW_ccwNotCw1_carry_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_ccwNotCw1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ccwNotCw1_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ccwNotCw1_inferred__1/i__carry_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_ccwNotCw1_inferred__1/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ccwNotCw2_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_ccwNotCw2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \angle[0]_i_2\ : label is "soft_lutpair2627";
  attribute SOFT_HLUTNM of \angle[11]_i_3\ : label is "soft_lutpair2625";
  attribute SOFT_HLUTNM of \angle[12]_i_7\ : label is "soft_lutpair2626";
  attribute SOFT_HLUTNM of \angle[13]_i_4\ : label is "soft_lutpair2625";
  attribute SOFT_HLUTNM of \angle[13]_i_5\ : label is "soft_lutpair2628";
  attribute SOFT_HLUTNM of \angle[13]_i_7\ : label is "soft_lutpair2626";
  attribute SOFT_HLUTNM of \angle[13]_i_8\ : label is "soft_lutpair2620";
  attribute SOFT_HLUTNM of \angle[1]_i_1\ : label is "soft_lutpair2624";
  attribute SOFT_HLUTNM of \angle[2]_i_1\ : label is "soft_lutpair2624";
  attribute SOFT_HLUTNM of \angle[3]_i_3\ : label is "soft_lutpair2622";
  attribute SOFT_HLUTNM of \angle[5]_i_2\ : label is "soft_lutpair2623";
  attribute SOFT_HLUTNM of \angle[6]_i_5\ : label is "soft_lutpair2627";
  attribute SOFT_HLUTNM of \angle[7]_i_3\ : label is "soft_lutpair2621";
  attribute SOFT_HLUTNM of \angle[7]_i_4\ : label is "soft_lutpair2620";
  attribute SOFT_HLUTNM of \angle[7]_i_5\ : label is "soft_lutpair2622";
  attribute SOFT_HLUTNM of \angle[8]_i_3\ : label is "soft_lutpair2623";
  attribute SOFT_HLUTNM of \angle[8]_i_4\ : label is "soft_lutpair2621";
  attribute SOFT_HLUTNM of \capt[5]_i_1__0\ : label is "soft_lutpair2629";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of ccwNotCw1_carry : label is 11;
  attribute COMPARATOR_THRESHOLD of \ccwNotCw1_inferred__0/i__carry\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \ccwNotCw1_inferred__1/i__carry\ : label is 11;
  attribute SOFT_HLUTNM of dir_INST_0 : label is "soft_lutpair2628";
  attribute SOFT_HLUTNM of \i[0]_i_1__18\ : label is "soft_lutpair2618";
  attribute SOFT_HLUTNM of \i[1]_i_1__18\ : label is "soft_lutpair2618";
  attribute SOFT_HLUTNM of \i[5]_i_1__13\ : label is "soft_lutpair2619";
  attribute SOFT_HLUTNM of step_INST_0 : label is "soft_lutpair2629";
  attribute SOFT_HLUTNM of step_i_3 : label is "soft_lutpair2619";
begin
  CO(0) <= \^co\(0);
  O(5 downto 0) <= \^o\(5 downto 0);
  Q(13 downto 0) <= \^q\(13 downto 0);
  rng_reg_0 <= \^rng_reg_0\;
  \stateOp_reg[1]_0\(1 downto 0) <= \^stateop_reg[1]_0\(1 downto 0);
\TStep_reg[0]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => tixVStepmode,
      D => D(0),
      PRE => \tixVStepmode_reg[0]_0\(0),
      Q => TStep(0)
    );
\TStep_reg[1]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => tixVStepmode,
      D => D(1),
      PRE => \tixVStepmode_reg[0]_0\(0),
      Q => TStep(1)
    );
\TStep_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => tixVStepmode,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => D(2),
      Q => TStep(2)
    );
\TStep_reg[3]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => tixVStepmode,
      D => D(3),
      PRE => \tixVStepmode_reg[0]_0\(0),
      Q => TStep(3)
    );
\TStep_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => tixVStepmode,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => D(4),
      Q => TStep(4)
    );
\TStep_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => tixVStepmode,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => D(5),
      Q => TStep(5)
    );
\TStep_reg[6]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => tixVStepmode,
      D => D(6),
      PRE => \tixVStepmode_reg[0]_0\(0),
      Q => TStep(6)
    );
\TStep_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => tixVStepmode,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => D(7),
      Q => TStep(7)
    );
\ackInvConfig_sig_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => \^stateop_reg[1]_0\(0),
      I1 => \^stateop_reg[1]_0\(1),
      I2 => reqInvRotaryConfig,
      O => tixVStepmode
    );
ackInvConfig_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvZero_sig,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => tixVStepmode,
      Q => ackInvRotaryConfig
    );
ackInvMoveto_sig_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF40"
    )
        port map (
      I0 => \^stateop_reg[1]_0\(1),
      I1 => \^stateop_reg[1]_0\(0),
      I2 => \ackInvConfig_sig0__6\,
      I3 => \step1__6\,
      O => ackInvZero_sig
    );
ackInvMoveto_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvZero_sig,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => E(0),
      Q => ackInvRotaryMoveto
    );
ackInvSet_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvZero_sig,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => ackInvSet_sig,
      Q => ackInvRotarySet
    );
ackInvZero_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvZero_sig,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => ackInvZero_sig_reg_0,
      Q => ackInvRotaryZero
    );
\angle[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BC3CBC30"
    )
        port map (
      I0 => \angle[12]_i_2_n_0\,
      I1 => \stateOp6__2\(0),
      I2 => \^q\(0),
      I3 => rotaryToStepmuxDir,
      I4 => \angle[13]_i_5_n_0\,
      I5 => \step1__6\,
      O => \angle[0]_i_1_n_0\
    );
\angle[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => lsb(1),
      I1 => lsb(0),
      O => \stateOp6__2\(0)
    );
\angle[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BFAAEAAA"
    )
        port map (
      I0 => \angle[10]_i_2_n_0\,
      I1 => \^q\(9),
      I2 => \angle[10]_i_3_n_0\,
      I3 => \angle[13]_i_5_n_0\,
      I4 => \^q\(10),
      I5 => \step1__6\,
      O => \angle[10]_i_1_n_0\
    );
\angle[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEAAAB00000000"
    )
        port map (
      I0 => \angle[12]_i_2_n_0\,
      I1 => \^q\(9),
      I2 => \angle[8]_i_2_n_0\,
      I3 => \^q\(8),
      I4 => \^q\(10),
      I5 => rotaryToStepmuxDir,
      O => \angle[10]_i_2_n_0\
    );
\angle[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(8),
      I1 => \^q\(6),
      I2 => \^q\(4),
      I3 => \angle[5]_i_3_n_0\,
      I4 => \^q\(5),
      I5 => \^q\(7),
      O => \angle[10]_i_3_n_0\
    );
\angle[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000008F88F888"
    )
        port map (
      I0 => \angle__2\(11),
      I1 => rotaryToStepmuxDir,
      I2 => \angle[11]_i_3_n_0\,
      I3 => \angle[13]_i_5_n_0\,
      I4 => \^q\(11),
      I5 => \step1__6\,
      O => \angle[11]_i_1_n_0\
    );
\angle[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAAA9"
    )
        port map (
      I0 => \^q\(11),
      I1 => \^q\(9),
      I2 => \angle[8]_i_2_n_0\,
      I3 => \^q\(8),
      I4 => \^q\(10),
      I5 => \angle[12]_i_2_n_0\,
      O => \angle__2\(11)
    );
\angle[11]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^q\(10),
      I1 => \angle[10]_i_3_n_0\,
      I2 => \^q\(9),
      O => \angle[11]_i_3_n_0\
    );
\angle[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFEB00"
    )
        port map (
      I0 => \angle[12]_i_2_n_0\,
      I1 => \angle[12]_i_3_n_0\,
      I2 => \^q\(12),
      I3 => rotaryToStepmuxDir,
      I4 => \angle[12]_i_4_n_0\,
      I5 => \step1__6\,
      O => \angle[12]_i_1_n_0\
    );
\angle[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \angle[12]_i_5_n_0\,
      I1 => stateOp50_out(1),
      I2 => \^q\(13),
      I3 => \^q\(12),
      I4 => \^q\(11),
      I5 => \^q\(10),
      O => \angle[12]_i_2_n_0\
    );
\angle[12]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^q\(10),
      I1 => \^q\(8),
      I2 => \angle[7]_i_2_n_0\,
      I3 => \^q\(7),
      I4 => \^q\(9),
      I5 => \^q\(11),
      O => \angle[12]_i_3_n_0\
    );
\angle[12]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF000080000000"
    )
        port map (
      I0 => \^q\(11),
      I1 => \^q\(9),
      I2 => \angle[10]_i_3_n_0\,
      I3 => \^q\(10),
      I4 => \angle[13]_i_5_n_0\,
      I5 => \^q\(12),
      O => \angle[12]_i_4_n_0\
    );
\angle[12]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => stateOp50_out(0),
      I1 => stateOp50_out(2),
      I2 => \angle[12]_i_7_n_0\,
      I3 => \^q\(5),
      I4 => \^q\(4),
      I5 => \^q\(3),
      O => \angle[12]_i_5_n_0\
    );
\angle[12]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^q\(1),
      I1 => lsb(1),
      O => stateOp50_out(1)
    );
\angle[12]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^q\(9),
      I1 => \^q\(8),
      I2 => \^q\(7),
      I3 => \^q\(6),
      O => \angle[12]_i_7_n_0\
    );
\angle[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000F300000020"
    )
        port map (
      I0 => \i__3\,
      I1 => \^stateop_reg[1]_0\(0),
      I2 => \^stateop_reg[1]_0\(1),
      I3 => ccwNotCw5_in,
      I4 => reqInvRotaryConfig,
      I5 => reqInvRotaryZero,
      O => \angle[13]_i_1_n_0\
    );
\angle[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BFAAEAAA"
    )
        port map (
      I0 => \angle[13]_i_3_n_0\,
      I1 => \^q\(12),
      I2 => \angle[13]_i_4_n_0\,
      I3 => \angle[13]_i_5_n_0\,
      I4 => \^q\(13),
      I5 => \step1__6\,
      O => \angle[13]_i_2_n_0\
    );
\angle[13]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEAB0000"
    )
        port map (
      I0 => \angle[12]_i_2_n_0\,
      I1 => \^q\(12),
      I2 => \angle[12]_i_3_n_0\,
      I3 => \^q\(13),
      I4 => rotaryToStepmuxDir,
      O => \angle[13]_i_3_n_0\
    );
\angle[13]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^q\(11),
      I1 => \^q\(9),
      I2 => \angle[10]_i_3_n_0\,
      I3 => \^q\(10),
      O => \angle[13]_i_4_n_0\
    );
\angle[13]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rotaryToStepmuxDir,
      I1 => \angle1__15\,
      O => \angle[13]_i_5_n_0\
    );
\angle[13]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080000000"
    )
        port map (
      I0 => \angle[13]_i_7_n_0\,
      I1 => \^q\(13),
      I2 => \^q\(12),
      I3 => \^q\(11),
      I4 => \^q\(10),
      I5 => \angle[13]_i_8_n_0\,
      O => \angle1__15\
    );
\angle[13]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \^q\(7),
      I1 => \^q\(6),
      I2 => \^q\(8),
      I3 => \^q\(9),
      O => \angle[13]_i_7_n_0\
    );
\angle[13]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABBBBB"
    )
        port map (
      I0 => \angle[13]_i_9_n_0\,
      I1 => lsb(1),
      I2 => lsb(0),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => \angle[13]_i_8_n_0\
    );
\angle[13]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F7F7FFF7FFF7FFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(4),
      I2 => \^q\(5),
      I3 => \^q\(2),
      I4 => lsb(0),
      I5 => lsb(1),
      O => \angle[13]_i_9_n_0\
    );
\angle[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \angle[1]_i_2_n_0\,
      I1 => \step1__6\,
      O => \angle[1]_i_1_n_0\
    );
\angle[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0CEECF0F0CAAC"
    )
        port map (
      I0 => \angle[13]_i_5_n_0\,
      I1 => rotaryToStepmuxDir,
      I2 => \^q\(1),
      I3 => stateOp50_out(0),
      I4 => lsb(1),
      I5 => \angle[12]_i_2_n_0\,
      O => \angle[1]_i_2_n_0\
    );
\angle[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0A0C"
    )
        port map (
      I0 => \angle__2\(2),
      I1 => \angle[2]_i_3_n_0\,
      I2 => \step1__6\,
      I3 => rotaryToStepmuxDir,
      O => \angle[2]_i_1_n_0\
    );
\angle[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFFFFFFAA9955A9"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => lsb(1),
      I4 => lsb(0),
      I5 => \angle[12]_i_2_n_0\,
      O => \angle__2\(2)
    );
\angle[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF55551500000040"
    )
        port map (
      I0 => \angle1__15\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => lsb(1),
      I4 => lsb(0),
      I5 => \^q\(2),
      O => \angle[2]_i_3_n_0\
    );
\angle[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000088F8F888"
    )
        port map (
      I0 => \angle__2\(3),
      I1 => rotaryToStepmuxDir,
      I2 => \angle[13]_i_5_n_0\,
      I3 => \angle[3]_i_3_n_0\,
      I4 => \^q\(3),
      I5 => \step1__6\,
      O => \angle[3]_i_1_n_0\
    );
\angle[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAA59"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => lsb(1),
      I3 => stateOp50_out(0),
      I4 => stateOp50_out(2),
      I5 => \angle[12]_i_2_n_0\,
      O => \angle__2\(3)
    );
\angle[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => lsb(0),
      I3 => lsb(1),
      I4 => \^q\(1),
      O => \angle[3]_i_3_n_0\
    );
\angle[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000088F8F888"
    )
        port map (
      I0 => \angle__2\(4),
      I1 => rotaryToStepmuxDir,
      I2 => \angle[13]_i_5_n_0\,
      I3 => \angle[5]_i_3_n_0\,
      I4 => \^q\(4),
      I5 => \step1__6\,
      O => \angle[4]_i_1_n_0\
    );
\angle[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAAA9"
    )
        port map (
      I0 => \^q\(4),
      I1 => stateOp50_out(2),
      I2 => stateOp50_out(0),
      I3 => stateOp50_out(1),
      I4 => \^q\(3),
      I5 => \angle[12]_i_2_n_0\,
      O => \angle__2\(4)
    );
\angle[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BFAAEAAA"
    )
        port map (
      I0 => \angle[5]_i_2_n_0\,
      I1 => \^q\(4),
      I2 => \angle[5]_i_3_n_0\,
      I3 => \angle[13]_i_5_n_0\,
      I4 => \^q\(5),
      I5 => \step1__6\,
      O => \angle[5]_i_1_n_0\
    );
\angle[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEAB0000"
    )
        port map (
      I0 => \angle[12]_i_2_n_0\,
      I1 => \^q\(4),
      I2 => \angle[6]_i_4_n_0\,
      I3 => \^q\(5),
      I4 => rotaryToStepmuxDir,
      O => \angle[5]_i_2_n_0\
    );
\angle[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000000000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => lsb(1),
      I3 => lsb(0),
      I4 => \^q\(0),
      I5 => \^q\(2),
      O => \angle[5]_i_3_n_0\
    );
\angle[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000BFAAEAAA"
    )
        port map (
      I0 => \angle[6]_i_2_n_0\,
      I1 => \^q\(5),
      I2 => \angle[6]_i_3_n_0\,
      I3 => \angle[13]_i_5_n_0\,
      I4 => \^q\(6),
      I5 => \step1__6\,
      O => \angle[6]_i_1_n_0\
    );
\angle[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEAAAB00000000"
    )
        port map (
      I0 => \angle[12]_i_2_n_0\,
      I1 => \^q\(5),
      I2 => \angle[6]_i_4_n_0\,
      I3 => \^q\(4),
      I4 => \^q\(6),
      I5 => rotaryToStepmuxDir,
      O => \angle[6]_i_2_n_0\
    );
\angle[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000800000000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => stateOp50_out(2),
      I2 => stateOp50_out(0),
      I3 => \^q\(1),
      I4 => lsb(1),
      I5 => \^q\(3),
      O => \angle[6]_i_3_n_0\
    );
\angle[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF2F2F2B2A"
    )
        port map (
      I0 => \^q\(2),
      I1 => lsb(0),
      I2 => lsb(1),
      I3 => \^q\(0),
      I4 => \^q\(1),
      I5 => \^q\(3),
      O => \angle[6]_i_4_n_0\
    );
\angle[6]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \^q\(0),
      I1 => lsb(0),
      I2 => lsb(1),
      O => stateOp50_out(0)
    );
\angle[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000008F88F444"
    )
        port map (
      I0 => \angle[7]_i_2_n_0\,
      I1 => \angle[8]_i_3_n_0\,
      I2 => \angle[7]_i_3_n_0\,
      I3 => \angle[13]_i_5_n_0\,
      I4 => \^q\(7),
      I5 => \step1__6\,
      O => \angle[7]_i_1_n_0\
    );
\angle[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^q\(5),
      I1 => \^q\(3),
      I2 => \angle[7]_i_4_n_0\,
      I3 => stateOp50_out(2),
      I4 => \^q\(4),
      I5 => \^q\(6),
      O => \angle[7]_i_2_n_0\
    );
\angle[7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^q\(6),
      I1 => \^q\(4),
      I2 => \angle[5]_i_3_n_0\,
      I3 => \^q\(5),
      O => \angle[7]_i_3_n_0\
    );
\angle[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F04"
    )
        port map (
      I0 => lsb(0),
      I1 => \^q\(0),
      I2 => lsb(1),
      I3 => \^q\(1),
      O => \angle[7]_i_4_n_0\
    );
\angle[7]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => \^q\(2),
      I1 => lsb(0),
      I2 => lsb(1),
      O => stateOp50_out(2)
    );
\angle[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000008F88F444"
    )
        port map (
      I0 => \angle[8]_i_2_n_0\,
      I1 => \angle[8]_i_3_n_0\,
      I2 => \angle[8]_i_4_n_0\,
      I3 => \angle[13]_i_5_n_0\,
      I4 => \^q\(8),
      I5 => \step1__6\,
      O => \angle[8]_i_1_n_0\
    );
\angle[8]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \angle[7]_i_2_n_0\,
      I1 => \^q\(7),
      O => \angle[8]_i_2_n_0\
    );
\angle[8]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rotaryToStepmuxDir,
      I1 => \angle[12]_i_2_n_0\,
      O => \angle[8]_i_3_n_0\
    );
\angle[8]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^q\(7),
      I1 => \^q\(5),
      I2 => \angle[5]_i_3_n_0\,
      I3 => \^q\(4),
      I4 => \^q\(6),
      O => \angle[8]_i_4_n_0\
    );
\angle[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BAEA"
    )
        port map (
      I0 => \angle[9]_i_2_n_0\,
      I1 => \angle[10]_i_3_n_0\,
      I2 => \angle[13]_i_5_n_0\,
      I3 => \^q\(9),
      I4 => \step1__6\,
      O => \angle[9]_i_1_n_0\
    );
\angle[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEAAAB00000000"
    )
        port map (
      I0 => \angle[12]_i_2_n_0\,
      I1 => \^q\(8),
      I2 => \angle[7]_i_2_n_0\,
      I3 => \^q\(7),
      I4 => \^q\(9),
      I5 => rotaryToStepmuxDir,
      O => \angle[9]_i_2_n_0\
    );
\angle_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \angle[13]_i_1_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \angle[0]_i_1_n_0\,
      Q => \^q\(0)
    );
\angle_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \angle[13]_i_1_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \angle[10]_i_1_n_0\,
      Q => \^q\(10)
    );
\angle_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \angle[13]_i_1_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \angle[11]_i_1_n_0\,
      Q => \^q\(11)
    );
\angle_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \angle[13]_i_1_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \angle[12]_i_1_n_0\,
      Q => \^q\(12)
    );
\angle_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \angle[13]_i_1_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \angle[13]_i_2_n_0\,
      Q => \^q\(13)
    );
\angle_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \angle[13]_i_1_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \angle[1]_i_1_n_0\,
      Q => \^q\(1)
    );
\angle_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \angle[13]_i_1_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \angle[2]_i_1_n_0\,
      Q => \^q\(2)
    );
\angle_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \angle[13]_i_1_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \angle[3]_i_1_n_0\,
      Q => \^q\(3)
    );
\angle_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \angle[13]_i_1_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \angle[4]_i_1_n_0\,
      Q => \^q\(4)
    );
\angle_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \angle[13]_i_1_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \angle[5]_i_1_n_0\,
      Q => \^q\(5)
    );
\angle_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \angle[13]_i_1_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \angle[6]_i_1_n_0\,
      Q => \^q\(6)
    );
\angle_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \angle[13]_i_1_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \angle[7]_i_1_n_0\,
      Q => \^q\(7)
    );
\angle_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \angle[13]_i_1_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \angle[8]_i_1_n_0\,
      Q => \^q\(8)
    );
\angle_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \angle[13]_i_1_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \angle[9]_i_1_n_0\,
      Q => \^q\(9)
    );
\capt[5]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rotaryToStepmuxStep,
      I1 => \capt_reg[5]\,
      O => step_reg_0(0)
    );
ccwNotCw1_carry: unisim.vcomponents.CARRY8
     port map (
      CI => ccwNotCw1_carry_i_1_n_0,
      CI_TOP => '0',
      CO(7 downto 4) => NLW_ccwNotCw1_carry_CO_UNCONNECTED(7 downto 4),
      CO(3) => \invbuf_reg[0][5]\(0),
      CO(2) => ccwNotCw1_carry_n_5,
      CO(1) => ccwNotCw1_carry_n_6,
      CO(0) => ccwNotCw1_carry_n_7,
      DI(7 downto 3) => B"00000",
      DI(2) => \^o\(5),
      DI(1 downto 0) => B"00",
      O(7 downto 0) => NLW_ccwNotCw1_carry_O_UNCONNECTED(7 downto 0),
      S(7 downto 4) => B"0000",
      S(3) => \^co\(0),
      S(2 downto 0) => ccwNotCw_reg_1(2 downto 0)
    );
ccwNotCw1_carry_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => ccwNotCw2(6),
      I1 => ccwNotCw2(7),
      O => ccwNotCw1_carry_i_1_n_0
    );
\ccwNotCw1_inferred__0/i__carry\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \i__carry_i_11__1_0\(0),
      CO(6) => \ccwNotCw1_inferred__0/i__carry_n_1\,
      CO(5) => \ccwNotCw1_inferred__0/i__carry_n_2\,
      CO(4) => \ccwNotCw1_inferred__0/i__carry_n_3\,
      CO(3) => \ccwNotCw1_inferred__0/i__carry_n_4\,
      CO(2) => \ccwNotCw1_inferred__0/i__carry_n_5\,
      CO(1) => \ccwNotCw1_inferred__0/i__carry_n_6\,
      CO(0) => \ccwNotCw1_inferred__0/i__carry_n_7\,
      DI(7) => '0',
      DI(6) => ccwNotCw_reg_2(0),
      DI(5 downto 4) => B"00",
      DI(3) => \i__carry_i_2__3_n_0\,
      DI(2 downto 1) => B"00",
      DI(0) => \i__carry_i_3__3_n_0\,
      O(7 downto 0) => \NLW_ccwNotCw1_inferred__0/i__carry_O_UNCONNECTED\(7 downto 0),
      S(7 downto 4) => ccwNotCw_reg_0(3 downto 0),
      S(3) => \i__carry_i_8__2_n_0\,
      S(2) => \i__carry_i_9__3_n_0\,
      S(1) => \i__carry_i_10__3_n_0\,
      S(0) => \i__carry_i_11__1_n_0\
    );
\ccwNotCw1_inferred__1/i__carry\: unisim.vcomponents.CARRY8
     port map (
      CI => \i__carry_i_1__4_n_0\,
      CI_TOP => '0',
      CO(7) => \NLW_ccwNotCw1_inferred__1/i__carry_CO_UNCONNECTED\(7),
      CO(6) => \invbuf_reg[0][5]_0\(0),
      CO(5) => \ccwNotCw1_inferred__1/i__carry_n_2\,
      CO(4) => \ccwNotCw1_inferred__1/i__carry_n_3\,
      CO(3) => \ccwNotCw1_inferred__1/i__carry_n_4\,
      CO(2) => \ccwNotCw1_inferred__1/i__carry_n_5\,
      CO(1) => \ccwNotCw1_inferred__1/i__carry_n_6\,
      CO(0) => \ccwNotCw1_inferred__1/i__carry_n_7\,
      DI(7 downto 6) => B"00",
      DI(5 downto 3) => DI(2 downto 0),
      DI(2) => \i__carry_i_5__4_n_0\,
      DI(1) => \i__carry_i_6__3_n_0\,
      DI(0) => \i__carry_i_7__2_n_0\,
      O(7 downto 0) => \NLW_ccwNotCw1_inferred__1/i__carry_O_UNCONNECTED\(7 downto 0),
      S(7) => '0',
      S(6) => \^co\(0),
      S(5 downto 3) => ccwNotCw_reg_3(2 downto 0),
      S(2) => \i__carry_i_11__2_n_0\,
      S(1) => \i__carry_i_12__0_n_0\,
      S(0) => \i__carry_i_13_n_0\
    );
ccwNotCw2_carry: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => ccwNotCw2_carry_n_0,
      CO(6) => ccwNotCw2_carry_n_1,
      CO(5) => ccwNotCw2_carry_n_2,
      CO(4) => ccwNotCw2_carry_n_3,
      CO(3) => ccwNotCw2_carry_n_4,
      CO(2) => ccwNotCw2_carry_n_5,
      CO(1) => ccwNotCw2_carry_n_6,
      CO(0) => ccwNotCw2_carry_n_7,
      DI(7 downto 0) => D(7 downto 0),
      O(7 downto 0) => ccwNotCw2(7 downto 0),
      S(7 downto 0) => \i__carry_i_11__1_1\(7 downto 0)
    );
\ccwNotCw2_carry__0\: unisim.vcomponents.CARRY8
     port map (
      CI => ccwNotCw2_carry_n_0,
      CI_TOP => '0',
      CO(7) => \NLW_ccwNotCw2_carry__0_CO_UNCONNECTED\(7),
      CO(6) => \^co\(0),
      CO(5) => \NLW_ccwNotCw2_carry__0_CO_UNCONNECTED\(5),
      CO(4) => \ccwNotCw2_carry__0_n_3\,
      CO(3) => \ccwNotCw2_carry__0_n_4\,
      CO(2) => \ccwNotCw2_carry__0_n_5\,
      CO(1) => \ccwNotCw2_carry__0_n_6\,
      CO(0) => \ccwNotCw2_carry__0_n_7\,
      DI(7 downto 6) => B"00",
      DI(5 downto 0) => \tixVStepmode_reg[7]_0\(5 downto 0),
      O(7 downto 6) => \NLW_ccwNotCw2_carry__0_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => \^o\(5 downto 0),
      S(7 downto 6) => B"01",
      S(5 downto 0) => S(5 downto 0)
    );
ccwNotCw_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => targetNotSteady,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => ccwNotCw0,
      Q => rotaryToStepmuxDir
    );
dir_INST_0: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rotaryToStepmuxDir,
      I1 => dir_0,
      O => dir
    );
\i[0]_i_1__18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0051"
    )
        port map (
      I0 => \step1__6\,
      I1 => \^stateop_reg[1]_0\(1),
      I2 => \^stateop_reg[1]_0\(0),
      I3 => i(0),
      O => p_1_in(0)
    );
\i[1]_i_1__18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000B0B00"
    )
        port map (
      I0 => \^stateop_reg[1]_0\(0),
      I1 => \^stateop_reg[1]_0\(1),
      I2 => \step1__6\,
      I3 => i(0),
      I4 => i(1),
      O => p_1_in(1)
    );
\i[2]_i_1__14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000B0B0B0B000000"
    )
        port map (
      I0 => \^stateop_reg[1]_0\(0),
      I1 => \^stateop_reg[1]_0\(1),
      I2 => \step1__6\,
      I3 => i(0),
      I4 => i(1),
      I5 => i(2),
      O => p_1_in(2)
    );
\i[3]_i_1__14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15554000"
    )
        port map (
      I0 => \i_reg[3]_0\,
      I1 => i(1),
      I2 => i(0),
      I3 => i(2),
      I4 => i(3),
      O => p_1_in(3)
    );
\i[4]_i_1__14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => \i_reg[3]_0\,
      I1 => i(2),
      I2 => i(0),
      I3 => i(1),
      I4 => i(3),
      I5 => i(4),
      O => p_1_in(4)
    );
\i[5]_i_1__13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11012202"
    )
        port map (
      I0 => \i[5]_i_2__6_n_0\,
      I1 => \step1__6\,
      I2 => \^stateop_reg[1]_0\(1),
      I3 => \^stateop_reg[1]_0\(0),
      I4 => i(5),
      O => p_1_in(5)
    );
\i[5]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => i(4),
      I1 => i(2),
      I2 => i(0),
      I3 => i(1),
      I4 => i(3),
      O => \i[5]_i_2__6_n_0\
    );
\i[6]_i_1__12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11012202"
    )
        port map (
      I0 => \i[7]_i_4__0_n_0\,
      I1 => \step1__6\,
      I2 => \^stateop_reg[1]_0\(1),
      I3 => \^stateop_reg[1]_0\(0),
      I4 => i(6),
      O => p_1_in(6)
    );
\i[7]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CECCFECC"
    )
        port map (
      I0 => \i__3\,
      I1 => \step1__6\,
      I2 => \^stateop_reg[1]_0\(0),
      I3 => \^stateop_reg[1]_0\(1),
      I4 => tkclk,
      O => \i[7]_i_1__10_n_0\
    );
\i[7]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0707000708080008"
    )
        port map (
      I0 => i(6),
      I1 => \i[7]_i_4__0_n_0\,
      I2 => \step1__6\,
      I3 => \^stateop_reg[1]_0\(1),
      I4 => \^stateop_reg[1]_0\(0),
      I5 => i(7),
      O => p_1_in(7)
    );
\i[7]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000090090000"
    )
        port map (
      I0 => i(7),
      I1 => TStep(7),
      I2 => i(6),
      I3 => TStep(6),
      I4 => tkclk,
      I5 => step_i_2_n_0,
      O => \i__3\
    );
\i[7]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => i(5),
      I1 => i(3),
      I2 => i(1),
      I3 => i(0),
      I4 => i(2),
      I5 => i(4),
      O => \i[7]_i_4__0_n_0\
    );
\i__carry_i_10__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ccwNotCw2(3),
      I1 => ccwNotCw2(2),
      O => \i__carry_i_10__3_n_0\
    );
\i__carry_i_11__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => ccwNotCw2(0),
      I1 => ccwNotCw2(1),
      O => \i__carry_i_11__1_n_0\
    );
\i__carry_i_11__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ccwNotCw2(7),
      I1 => ccwNotCw2(6),
      O => \i__carry_i_11__2_n_0\
    );
\i__carry_i_12__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ccwNotCw2(5),
      I1 => ccwNotCw2(4),
      O => \i__carry_i_12__0_n_0\
    );
\i__carry_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ccwNotCw2(3),
      I1 => ccwNotCw2(2),
      O => \i__carry_i_13_n_0\
    );
\i__carry_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => ccwNotCw2(0),
      I1 => ccwNotCw2(1),
      O => \i__carry_i_1__4_n_0\
    );
\i__carry_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => ccwNotCw2(7),
      I1 => ccwNotCw2(6),
      O => \i__carry_i_2__3_n_0\
    );
\i__carry_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ccwNotCw2(1),
      I1 => ccwNotCw2(0),
      O => \i__carry_i_3__3_n_0\
    );
\i__carry_i_5__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => ccwNotCw2(6),
      I1 => ccwNotCw2(7),
      O => \i__carry_i_5__4_n_0\
    );
\i__carry_i_6__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => ccwNotCw2(4),
      I1 => ccwNotCw2(5),
      O => \i__carry_i_6__3_n_0\
    );
\i__carry_i_7__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => ccwNotCw2(2),
      I1 => ccwNotCw2(3),
      O => \i__carry_i_7__2_n_0\
    );
\i__carry_i_8__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ccwNotCw2(6),
      I1 => ccwNotCw2(7),
      O => \i__carry_i_8__2_n_0\
    );
\i__carry_i_9__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ccwNotCw2(5),
      I1 => ccwNotCw2(4),
      O => \i__carry_i_9__3_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__10_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => p_1_in(0),
      Q => i(0)
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__10_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => p_1_in(1),
      Q => i(1)
    );
\i_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__10_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => p_1_in(2),
      Q => i(2)
    );
\i_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__10_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => p_1_in(3),
      Q => i(3)
    );
\i_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__10_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => p_1_in(4),
      Q => i(4)
    );
\i_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__10_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => p_1_in(5),
      Q => i(5)
    );
\i_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__10_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => p_1_in(6),
      Q => i(6)
    );
\i_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__10_n_0\,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => p_1_in(7),
      Q => i(7)
    );
\lsb_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => tixVStepmode,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \lsb_reg[1]_0\(0),
      Q => lsb(0)
    );
\lsb_reg[1]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => tixVStepmode,
      D => \lsb_reg[1]_0\(1),
      PRE => \tixVStepmode_reg[0]_0\(0),
      Q => lsb(1)
    );
m0_INST_0: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => m0_INST_0_i_1_n_0,
      I1 => \tixVStepmode_reg_n_0_[1]\,
      I2 => \tixVStepmode_reg_n_0_[0]\,
      I3 => \tixVStepmode_reg_n_0_[3]\,
      I4 => \tixVStepmode_reg_n_0_[2]\,
      I5 => dir_0,
      O => m0
    );
m0_INST_0_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \tixVStepmode_reg_n_0_[7]\,
      I1 => \tixVStepmode_reg_n_0_[6]\,
      I2 => \tixVStepmode_reg_n_0_[4]\,
      I3 => \tixVStepmode_reg_n_0_[5]\,
      O => m0_INST_0_i_1_n_0
    );
m0z_INST_0: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => m0_INST_0_i_1_n_0,
      I1 => \tixVStepmode_reg_n_0_[0]\,
      I2 => \tixVStepmode_reg_n_0_[1]\,
      I3 => \tixVStepmode_reg_n_0_[3]\,
      I4 => \tixVStepmode_reg_n_0_[2]\,
      I5 => dir_0,
      O => m0z
    );
rng_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => rng_reg_2,
      Q => \^rng_reg_0\
    );
\stateOp[0]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44C0"
    )
        port map (
      I0 => \stateOp4__26\,
      I1 => stateOp121_in,
      I2 => \^rng_reg_0\,
      I3 => targetNotSteady_reg_n_0,
      O => rng_reg_1
    );
\stateOp[0]_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => TStep(3),
      I1 => TStep(2),
      I2 => TStep(1),
      I3 => TStep(0),
      I4 => \stateOp[0]_i_5__1_n_0\,
      O => stateOp121_in
    );
\stateOp[0]_i_5__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => TStep(4),
      I1 => TStep(5),
      I2 => TStep(7),
      I3 => TStep(6),
      O => \stateOp[0]_i_5__1_n_0\
    );
\stateOp[1]_i_10__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => \^q\(4),
      I1 => \target_reg_n_0_[4]\,
      I2 => \^q\(3),
      I3 => \target_reg_n_0_[3]\,
      O => \stateOp[1]_i_10__2_n_0\
    );
\stateOp[1]_i_2__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABBBBBBBAAAAABBB"
    )
        port map (
      I0 => \stateOp_reg[1]_1\,
      I1 => \step1__6\,
      I2 => \stateOp4__26\,
      I3 => targetNotSteady_reg_n_0,
      I4 => \^stateop_reg[1]_0\(0),
      I5 => \^stateop_reg[1]_0\(1),
      O => \stateOp[1]_i_2__10_n_0\
    );
\stateOp[1]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \stateOp[1]_i_5__4_n_0\,
      I1 => \stateOp[1]_i_6__3_n_0\,
      I2 => \stateOp[1]_i_7__2_n_0\,
      I3 => \stateOp[1]_i_8__3_n_0\,
      I4 => \stateOp[1]_i_9__2_n_0\,
      I5 => \stateOp[1]_i_10__2_n_0\,
      O => \stateOp4__26\
    );
\stateOp[1]_i_5__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \target_reg_n_0_[7]\,
      I1 => \^q\(7),
      I2 => \target_reg_n_0_[6]\,
      I3 => \^q\(6),
      I4 => \^q\(8),
      I5 => \target_reg_n_0_[8]\,
      O => \stateOp[1]_i_5__4_n_0\
    );
\stateOp[1]_i_6__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \target_reg_n_0_[10]\,
      I1 => \^q\(10),
      I2 => \target_reg_n_0_[9]\,
      I3 => \^q\(9),
      I4 => \^q\(11),
      I5 => \target_reg_n_0_[11]\,
      O => \stateOp[1]_i_6__3_n_0\
    );
\stateOp[1]_i_7__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => \^q\(13),
      I1 => \target_reg_n_0_[13]\,
      I2 => \^q\(12),
      I3 => \target_reg_n_0_[12]\,
      O => \stateOp[1]_i_7__2_n_0\
    );
\stateOp[1]_i_8__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"666F6F6F66F6F6F6"
    )
        port map (
      I0 => \^q\(5),
      I1 => \target_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => lsb(0),
      I4 => lsb(1),
      I5 => \target_reg_n_0_[2]\,
      O => \stateOp[1]_i_8__3_n_0\
    );
\stateOp[1]_i_9__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000666F000066F6"
    )
        port map (
      I0 => \^q\(1),
      I1 => \target_reg_n_0_[1]\,
      I2 => \^q\(0),
      I3 => lsb(0),
      I4 => lsb(1),
      I5 => \target_reg_n_0_[0]\,
      O => \stateOp[1]_i_9__2_n_0\
    );
\stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp_reg[1]_2\(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \stateOp_reg[0]_0\(0),
      Q => \^stateop_reg[1]_0\(0)
    );
\stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp_reg[1]_2\(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \stateOp[1]_i_2__10_n_0\,
      Q => \^stateop_reg[1]_0\(1)
    );
step_INST_0: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rotaryToStepmuxStep,
      I1 => dir_0,
      O => step
    );
step_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFBF00000040"
    )
        port map (
      I0 => step_i_2_n_0,
      I1 => tkclk,
      I2 => step_i_3_n_0,
      I3 => step_i_4_n_0,
      I4 => \step1__6\,
      I5 => rotaryToStepmuxStep,
      O => step_i_1_n_0
    );
step_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBEFFFFBE"
    )
        port map (
      I0 => step_i_5_n_0,
      I1 => i(1),
      I2 => TStep(1),
      I3 => i(0),
      I4 => TStep(0),
      I5 => step_i_6_n_0,
      O => step_i_2_n_0
    );
step_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[1]_0\(1),
      I1 => \^stateop_reg[1]_0\(0),
      O => step_i_3_n_0
    );
step_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => i(7),
      I1 => TStep(7),
      I2 => i(6),
      I3 => TStep(6),
      O => step_i_4_n_0
    );
step_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => i(4),
      I1 => TStep(4),
      I2 => i(3),
      I3 => TStep(3),
      O => step_i_5_n_0
    );
step_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => i(5),
      I1 => TStep(5),
      I2 => i(2),
      I3 => TStep(2),
      O => step_i_6_n_0
    );
step_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => step_i_1_n_0,
      Q => rotaryToStepmuxStep
    );
targetNotSteady_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => targetNotSteady,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => reqInvRotaryMoveto,
      Q => targetNotSteady_reg_n_0
    );
\target_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => D(0),
      Q => \target_reg_n_0_[0]\
    );
\target_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \tixVStepmode_reg[7]_0\(2),
      Q => \target_reg_n_0_[10]\
    );
\target_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \tixVStepmode_reg[7]_0\(3),
      Q => \target_reg_n_0_[11]\
    );
\target_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \tixVStepmode_reg[7]_0\(4),
      Q => \target_reg_n_0_[12]\
    );
\target_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \tixVStepmode_reg[7]_0\(5),
      Q => \target_reg_n_0_[13]\
    );
\target_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => D(1),
      Q => \target_reg_n_0_[1]\
    );
\target_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => D(2),
      Q => \target_reg_n_0_[2]\
    );
\target_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => D(3),
      Q => \target_reg_n_0_[3]\
    );
\target_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => D(4),
      Q => \target_reg_n_0_[4]\
    );
\target_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => D(5),
      Q => \target_reg_n_0_[5]\
    );
\target_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => D(6),
      Q => \target_reg_n_0_[6]\
    );
\target_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => D(7),
      Q => \target_reg_n_0_[7]\
    );
\target_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \tixVStepmode_reg[7]_0\(0),
      Q => \target_reg_n_0_[8]\
    );
\target_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \tixVStepmode_reg[7]_0\(1),
      Q => \target_reg_n_0_[9]\
    );
\tixVStepmode_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVStepmode,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \tixVStepmode_reg[7]_0\(0),
      Q => \tixVStepmode_reg_n_0_[0]\
    );
\tixVStepmode_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVStepmode,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \tixVStepmode_reg[7]_0\(1),
      Q => \tixVStepmode_reg_n_0_[1]\
    );
\tixVStepmode_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVStepmode,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \tixVStepmode_reg[7]_0\(2),
      Q => \tixVStepmode_reg_n_0_[2]\
    );
\tixVStepmode_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVStepmode,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \tixVStepmode_reg[7]_0\(3),
      Q => \tixVStepmode_reg_n_0_[3]\
    );
\tixVStepmode_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVStepmode,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \tixVStepmode_reg[7]_0\(4),
      Q => \tixVStepmode_reg_n_0_[4]\
    );
\tixVStepmode_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVStepmode,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \tixVStepmode_reg[7]_0\(5),
      Q => \tixVStepmode_reg_n_0_[5]\
    );
\tixVStepmode_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVStepmode,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \tixVStepmode_reg[7]_0\(6),
      Q => \tixVStepmode_reg_n_0_[6]\
    );
\tixVStepmode_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVStepmode,
      CLR => \tixVStepmode_reg[0]_0\(0),
      D => \tixVStepmode_reg[7]_0\(7),
      Q => \tixVStepmode_reg_n_0_[7]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Spimaster_v1_0 is
  port (
    mosi : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_stateOp_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_stateOp_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_stateOp_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_stateOp_reg[1]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    cs : out STD_LOGIC;
    sclk : out STD_LOGIC;
    \FSM_sequential_stateOp_reg[0]\ : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    \FSM_sequential_stateXfer_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_stateOp_reg[0]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \i_reg[0]_0\ : in STD_LOGIC;
    reqInvLaserSet : in STD_LOGIC;
    \FSM_sequential_stateOp_reg[0]_1\ : in STD_LOGIC;
    \i_reg[0]_1\ : in STD_LOGIC;
    rNotL_reg : in STD_LOGIC;
    len : in STD_LOGIC_VECTOR ( 0 to 0 );
    \send_var_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Spimaster_v1_0 : entity is "Spimaster_v1_0";
end design_1_Vsp_core_0_0_Spimaster_v1_0;

architecture STRUCTURE of design_1_Vsp_core_0_0_Spimaster_v1_0 is
  signal \FSM_sequential_stateOp[2]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateOp[2]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateOp[2]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateOp[2]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateXfer[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateXfer[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateXfer[2]_i_3_n_0\ : STD_LOGIC;
  signal bitcnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal bitcnt0 : STD_LOGIC;
  signal \bitcnt[2]_i_4_n_0\ : STD_LOGIC;
  signal \bytecnt[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \bytecnt[0]_i_2_n_0\ : STD_LOGIC;
  signal \bytecnt[0]_i_3_n_0\ : STD_LOGIC;
  signal \bytecnt[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \bytecnt[0]_i_4_n_0\ : STD_LOGIC;
  signal \bytecnt[0]_i_5_n_0\ : STD_LOGIC;
  signal bytecnt_reg : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal \bytecnt_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_1\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_10\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_11\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_12\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_13\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_14\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_15\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_2\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_3\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_4\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_5\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_6\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_7\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_8\ : STD_LOGIC;
  signal \bytecnt_reg[0]_i_3_n_9\ : STD_LOGIC;
  signal \bytecnt_reg[16]_i_1_n_15\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_10\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_11\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_12\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_13\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_14\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_15\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_8\ : STD_LOGIC;
  signal \bytecnt_reg[8]_i_1_n_9\ : STD_LOGIC;
  signal data0 : STD_LOGIC;
  signal data2 : STD_LOGIC;
  signal data3 : STD_LOGIC;
  signal data4 : STD_LOGIC;
  signal data5 : STD_LOGIC;
  signal data6 : STD_LOGIC;
  signal data7 : STD_LOGIC;
  signal dneSpi : STD_LOGIC;
  signal i0 : STD_LOGIC;
  signal \i[0]_i_1__21_n_0\ : STD_LOGIC;
  signal \i[10]_i_3__0_n_0\ : STD_LOGIC;
  signal \i[1]_i_1__16_n_0\ : STD_LOGIC;
  signal \i[2]_i_1__12_n_0\ : STD_LOGIC;
  signal \i[3]_i_1__12_n_0\ : STD_LOGIC;
  signal \i[4]_i_1__12_n_0\ : STD_LOGIC;
  signal \i[5]_i_1__11_n_0\ : STD_LOGIC;
  signal \i[6]_i_1__13_n_0\ : STD_LOGIC;
  signal \i[6]_i_3__1_n_0\ : STD_LOGIC;
  signal \i[6]_i_4__1_n_0\ : STD_LOGIC;
  signal \i[6]_i_5_n_0\ : STD_LOGIC;
  signal \i[6]_i_6_n_0\ : STD_LOGIC;
  signal \i__carry_i_1__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_2__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_3__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_4__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_5__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_6__2_n_0\ : STD_LOGIC;
  signal \i_reg_n_0_[0]\ : STD_LOGIC;
  signal \i_reg_n_0_[1]\ : STD_LOGIC;
  signal \i_reg_n_0_[2]\ : STD_LOGIC;
  signal \i_reg_n_0_[3]\ : STD_LOGIC;
  signal \i_reg_n_0_[4]\ : STD_LOGIC;
  signal \i_reg_n_0_[5]\ : STD_LOGIC;
  signal \i_reg_n_0_[6]\ : STD_LOGIC;
  signal in5 : STD_LOGIC;
  signal \j[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \j[0]_i_2_n_0\ : STD_LOGIC;
  signal \j_reg_n_0_[0]\ : STD_LOGIC;
  signal \^mosi\ : STD_LOGIC;
  signal mosi_sig : STD_LOGIC;
  signal \mosi_sig0__4\ : STD_LOGIC;
  signal mosi_sig_i_1_n_0 : STD_LOGIC;
  signal mosi_sig_i_4_n_0 : STD_LOGIC;
  signal mosi_sig_i_5_n_0 : STD_LOGIC;
  signal mosi_sig_i_6_n_0 : STD_LOGIC;
  signal mosi_sig_i_7_n_0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal req : STD_LOGIC;
  signal send_var0 : STD_LOGIC;
  signal \send_var_reg_n_0_[0]\ : STD_LOGIC;
  signal \stateXfer1_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal \stateXfer1_inferred__0/i__carry_n_4\ : STD_LOGIC;
  signal \stateXfer1_inferred__0/i__carry_n_5\ : STD_LOGIC;
  signal \stateXfer1_inferred__0/i__carry_n_6\ : STD_LOGIC;
  signal \stateXfer1_inferred__0/i__carry_n_7\ : STD_LOGIC;
  signal \stateXfer__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_bytecnt_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_bytecnt_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_stateXfer1_inferred__0/i__carry_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_stateXfer1_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_stateOp[0]_i_2\ : label is "soft_lutpair2497";
  attribute SOFT_HLUTNM of \FSM_sequential_stateOp[2]_i_4\ : label is "soft_lutpair2492";
  attribute SOFT_HLUTNM of \FSM_sequential_stateOp[2]_i_9\ : label is "soft_lutpair2488";
  attribute SOFT_HLUTNM of \FSM_sequential_stateXfer[0]_i_1\ : label is "soft_lutpair2488";
  attribute SOFT_HLUTNM of \FSM_sequential_stateXfer[1]_i_1\ : label is "soft_lutpair2486";
  attribute SOFT_HLUTNM of \FSM_sequential_stateXfer[1]_i_2\ : label is "soft_lutpair2489";
  attribute SOFT_HLUTNM of \FSM_sequential_stateXfer[2]_i_3\ : label is "soft_lutpair2493";
  attribute SOFT_HLUTNM of \FSM_sequential_stateXfer[2]_i_4\ : label is "soft_lutpair2487";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateXfer_reg[0]\ : label is "iSTATE:111,iSTATE0:101,iSTATE1:001,iSTATE2:110,iSTATE3:100,iSTATE4:011,iSTATE5:010,iSTATE6:000";
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateXfer_reg[1]\ : label is "iSTATE:111,iSTATE0:101,iSTATE1:001,iSTATE2:110,iSTATE3:100,iSTATE4:011,iSTATE5:010,iSTATE6:000";
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateXfer_reg[2]\ : label is "iSTATE:111,iSTATE0:101,iSTATE1:001,iSTATE2:110,iSTATE3:100,iSTATE4:011,iSTATE5:010,iSTATE6:000";
  attribute SOFT_HLUTNM of \bitcnt[1]_i_1__0\ : label is "soft_lutpair2496";
  attribute SOFT_HLUTNM of \bitcnt[2]_i_3\ : label is "soft_lutpair2496";
  attribute SOFT_HLUTNM of \bitcnt[2]_i_4\ : label is "soft_lutpair2490";
  attribute SOFT_HLUTNM of \bytecnt[0]_i_4\ : label is "soft_lutpair2492";
  attribute SOFT_HLUTNM of \bytecnt[0]_i_4__0\ : label is "soft_lutpair2497";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \bytecnt_reg[0]_i_3\ : label is 16;
  attribute ADDER_THRESHOLD of \bytecnt_reg[16]_i_1\ : label is 16;
  attribute ADDER_THRESHOLD of \bytecnt_reg[8]_i_1\ : label is 16;
  attribute SOFT_HLUTNM of cs_INST_0 : label is "soft_lutpair2486";
  attribute SOFT_HLUTNM of \i[2]_i_1__12\ : label is "soft_lutpair2495";
  attribute SOFT_HLUTNM of \i[3]_i_1__12\ : label is "soft_lutpair2495";
  attribute SOFT_HLUTNM of \i[4]_i_1__12\ : label is "soft_lutpair2491";
  attribute SOFT_HLUTNM of \i[6]_i_4__1\ : label is "soft_lutpair2494";
  attribute SOFT_HLUTNM of \i[6]_i_5\ : label is "soft_lutpair2491";
  attribute SOFT_HLUTNM of \j[0]_i_1__1\ : label is "soft_lutpair2489";
  attribute SOFT_HLUTNM of mosi_sig_i_3 : label is "soft_lutpair2494";
  attribute SOFT_HLUTNM of mosi_sig_i_5 : label is "soft_lutpair2490";
  attribute SOFT_HLUTNM of sclk_INST_0 : label is "soft_lutpair2493";
  attribute SOFT_HLUTNM of \txbuf[1][7]_i_1\ : label is "soft_lutpair2487";
begin
  mosi <= \^mosi\;
\FSM_sequential_stateOp[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0033FFF055FF"
    )
        port map (
      I0 => \FSM_sequential_stateOp_reg[0]_0\,
      I1 => dneSpi,
      I2 => \FSM_sequential_stateOp_reg[0]_1\,
      I3 => Q(2),
      I4 => Q(1),
      I5 => Q(0),
      O => D(0)
    );
\FSM_sequential_stateOp[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \stateXfer__0\(1),
      I1 => \stateXfer__0\(2),
      I2 => \stateXfer__0\(0),
      O => dneSpi
    );
\FSM_sequential_stateOp[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAEAEAFFEAEAEAEA"
    )
        port map (
      I0 => \FSM_sequential_stateOp[2]_i_3_n_0\,
      I1 => \FSM_sequential_stateOp[2]_i_4_n_0\,
      I2 => Q(1),
      I3 => Q(0),
      I4 => reqInvLaserSet,
      I5 => Q(2),
      O => \FSM_sequential_stateOp_reg[1]\(0)
    );
\FSM_sequential_stateOp[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F3B0C083F3B3C08"
    )
        port map (
      I0 => \FSM_sequential_stateOp_reg[0]_0\,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(0),
      I4 => \FSM_sequential_stateOp[2]_i_7_n_0\,
      I5 => \i_reg[0]_0\,
      O => D(1)
    );
\FSM_sequential_stateOp[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0AAADDFF0AAADDF5"
    )
        port map (
      I0 => Q(0),
      I1 => reqInvLaserSet,
      I2 => \FSM_sequential_stateOp[2]_i_9_n_0\,
      I3 => Q(2),
      I4 => Q(1),
      I5 => dneSpi,
      O => \FSM_sequential_stateOp[2]_i_3_n_0\
    );
\FSM_sequential_stateOp[2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0081"
    )
        port map (
      I0 => \stateXfer__0\(2),
      I1 => \stateXfer__0\(1),
      I2 => \stateXfer__0\(0),
      I3 => Q(2),
      O => \FSM_sequential_stateOp[2]_i_4_n_0\
    );
\FSM_sequential_stateOp[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FDFDFF000000"
    )
        port map (
      I0 => \stateXfer__0\(1),
      I1 => \stateXfer__0\(2),
      I2 => \stateXfer__0\(0),
      I3 => \i_reg[0]_1\,
      I4 => Q(1),
      I5 => Q(0),
      O => \FSM_sequential_stateOp[2]_i_7_n_0\
    );
\FSM_sequential_stateOp[2]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2E"
    )
        port map (
      I0 => \stateXfer__0\(2),
      I1 => \stateXfer__0\(0),
      I2 => \stateXfer__0\(1),
      O => \FSM_sequential_stateOp[2]_i_9_n_0\
    );
\FSM_sequential_stateXfer[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F5075507"
    )
        port map (
      I0 => \stateXfer__0\(0),
      I1 => in5,
      I2 => \stateXfer__0\(1),
      I3 => \stateXfer__0\(2),
      I4 => len(0),
      O => p_3_out(0)
    );
\FSM_sequential_stateXfer[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FCAF000F"
    )
        port map (
      I0 => req,
      I1 => \FSM_sequential_stateXfer[1]_i_2_n_0\,
      I2 => \stateXfer__0\(1),
      I3 => \stateXfer__0\(2),
      I4 => \stateXfer__0\(0),
      O => p_3_out(1)
    );
\FSM_sequential_stateXfer[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => bitcnt(0),
      I1 => bitcnt(1),
      I2 => bitcnt(2),
      O => \FSM_sequential_stateXfer[1]_i_2_n_0\
    );
\FSM_sequential_stateXfer[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEFFAAFBFEFBBAF"
    )
        port map (
      I0 => \FSM_sequential_stateXfer[2]_i_3_n_0\,
      I1 => \stateXfer__0\(2),
      I2 => \stateXfer__0\(0),
      I3 => \stateXfer__0\(1),
      I4 => \mosi_sig0__4\,
      I5 => req,
      O => \FSM_sequential_stateXfer[2]_i_1_n_0\
    );
\FSM_sequential_stateXfer[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6961616161616961"
    )
        port map (
      I0 => \stateXfer__0\(1),
      I1 => \stateXfer__0\(0),
      I2 => \stateXfer__0\(2),
      I3 => Q(0),
      I4 => Q(1),
      I5 => Q(2),
      O => p_3_out(2)
    );
\FSM_sequential_stateXfer[2]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \j_reg_n_0_[0]\,
      I1 => \stateXfer__0\(1),
      I2 => \stateXfer__0\(2),
      I3 => \i[6]_i_4__1_n_0\,
      O => \FSM_sequential_stateXfer[2]_i_3_n_0\
    );
\FSM_sequential_stateXfer[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => Q(0),
      I1 => Q(1),
      I2 => Q(2),
      O => req
    );
\FSM_sequential_stateXfer_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_sequential_stateXfer[2]_i_1_n_0\,
      CLR => \FSM_sequential_stateXfer_reg[2]_0\(0),
      D => p_3_out(0),
      Q => \stateXfer__0\(0)
    );
\FSM_sequential_stateXfer_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_sequential_stateXfer[2]_i_1_n_0\,
      CLR => \FSM_sequential_stateXfer_reg[2]_0\(0),
      D => p_3_out(1),
      Q => \stateXfer__0\(1)
    );
\FSM_sequential_stateXfer_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_sequential_stateXfer[2]_i_1_n_0\,
      CLR => \FSM_sequential_stateXfer_reg[2]_0\(0),
      D => p_3_out(2),
      Q => \stateXfer__0\(2)
    );
\bitcnt[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => bitcnt(0),
      O => p_0_in(0)
    );
\bitcnt[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => bitcnt(1),
      I1 => bitcnt(0),
      O => p_0_in(1)
    );
\bitcnt[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080000"
    )
        port map (
      I0 => \stateXfer__0\(1),
      I1 => \stateXfer__0\(0),
      I2 => \stateXfer__0\(2),
      I3 => \FSM_sequential_stateXfer_reg[2]_0\(0),
      I4 => req,
      O => send_var0
    );
\bitcnt[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1555"
    )
        port map (
      I0 => \bitcnt[2]_i_4_n_0\,
      I1 => bitcnt(0),
      I2 => bitcnt(1),
      I3 => bitcnt(2),
      I4 => \bytecnt[0]_i_2_n_0\,
      O => bitcnt0
    );
\bitcnt[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => bitcnt(0),
      I1 => bitcnt(1),
      I2 => bitcnt(2),
      O => p_0_in(2)
    );
\bitcnt[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FDFFFFFF"
    )
        port map (
      I0 => \mosi_sig0__4\,
      I1 => \FSM_sequential_stateXfer_reg[2]_0\(0),
      I2 => \stateXfer__0\(1),
      I3 => \stateXfer__0\(0),
      I4 => \stateXfer__0\(2),
      O => \bitcnt[2]_i_4_n_0\
    );
\bitcnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => bitcnt0,
      D => p_0_in(0),
      Q => bitcnt(0),
      R => send_var0
    );
\bitcnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => bitcnt0,
      D => p_0_in(1),
      Q => bitcnt(1),
      R => send_var0
    );
\bitcnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => bitcnt0,
      D => p_0_in(2),
      Q => bitcnt(2),
      R => send_var0
    );
\bytecnt[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFB3F33F8083F03"
    )
        port map (
      I0 => reqInvLaserSet,
      I1 => Q(2),
      I2 => Q(1),
      I3 => \bytecnt[0]_i_3_n_0\,
      I4 => Q(0),
      I5 => \bytecnt[0]_i_4_n_0\,
      O => \FSM_sequential_stateOp_reg[2]\(0)
    );
\bytecnt[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \FSM_sequential_stateXfer_reg[2]_0\(0),
      I1 => \stateXfer__0\(0),
      I2 => \stateXfer__0\(1),
      I3 => \stateXfer__0\(2),
      O => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000004004"
    )
        port map (
      I0 => \FSM_sequential_stateXfer_reg[2]_0\(0),
      I1 => Q(0),
      I2 => Q(1),
      I3 => Q(2),
      I4 => \stateXfer__0\(2),
      I5 => \bytecnt[0]_i_4__0_n_0\,
      O => \bytecnt[0]_i_2_n_0\
    );
\bytecnt[0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \i[10]_i_3__0_n_0\,
      I1 => \i_reg[0]_1\,
      I2 => rNotL_reg,
      O => \bytecnt[0]_i_3_n_0\
    );
\bytecnt[0]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1510"
    )
        port map (
      I0 => Q(1),
      I1 => \stateXfer__0\(1),
      I2 => \stateXfer__0\(0),
      I3 => \stateXfer__0\(2),
      O => \bytecnt[0]_i_4_n_0\
    );
\bytecnt[0]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \stateXfer__0\(0),
      I1 => \stateXfer__0\(1),
      O => \bytecnt[0]_i_4__0_n_0\
    );
\bytecnt[0]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => bytecnt_reg(0),
      O => \bytecnt[0]_i_5_n_0\
    );
\bytecnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[0]_i_3_n_15\,
      Q => bytecnt_reg(0),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[0]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \bytecnt_reg[0]_i_3_n_0\,
      CO(6) => \bytecnt_reg[0]_i_3_n_1\,
      CO(5) => \bytecnt_reg[0]_i_3_n_2\,
      CO(4) => \bytecnt_reg[0]_i_3_n_3\,
      CO(3) => \bytecnt_reg[0]_i_3_n_4\,
      CO(2) => \bytecnt_reg[0]_i_3_n_5\,
      CO(1) => \bytecnt_reg[0]_i_3_n_6\,
      CO(0) => \bytecnt_reg[0]_i_3_n_7\,
      DI(7 downto 0) => B"00000001",
      O(7) => \bytecnt_reg[0]_i_3_n_8\,
      O(6) => \bytecnt_reg[0]_i_3_n_9\,
      O(5) => \bytecnt_reg[0]_i_3_n_10\,
      O(4) => \bytecnt_reg[0]_i_3_n_11\,
      O(3) => \bytecnt_reg[0]_i_3_n_12\,
      O(2) => \bytecnt_reg[0]_i_3_n_13\,
      O(1) => \bytecnt_reg[0]_i_3_n_14\,
      O(0) => \bytecnt_reg[0]_i_3_n_15\,
      S(7 downto 1) => bytecnt_reg(7 downto 1),
      S(0) => \bytecnt[0]_i_5_n_0\
    );
\bytecnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[8]_i_1_n_13\,
      Q => bytecnt_reg(10),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[8]_i_1_n_12\,
      Q => bytecnt_reg(11),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[8]_i_1_n_11\,
      Q => bytecnt_reg(12),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[8]_i_1_n_10\,
      Q => bytecnt_reg(13),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[8]_i_1_n_9\,
      Q => bytecnt_reg(14),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[8]_i_1_n_8\,
      Q => bytecnt_reg(15),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[16]_i_1_n_15\,
      Q => bytecnt_reg(16),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[16]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \bytecnt_reg[8]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 0) => \NLW_bytecnt_reg[16]_i_1_CO_UNCONNECTED\(7 downto 0),
      DI(7 downto 0) => B"00000000",
      O(7 downto 1) => \NLW_bytecnt_reg[16]_i_1_O_UNCONNECTED\(7 downto 1),
      O(0) => \bytecnt_reg[16]_i_1_n_15\,
      S(7 downto 1) => B"0000000",
      S(0) => bytecnt_reg(16)
    );
\bytecnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[0]_i_3_n_14\,
      Q => bytecnt_reg(1),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[0]_i_3_n_13\,
      Q => bytecnt_reg(2),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[0]_i_3_n_12\,
      Q => bytecnt_reg(3),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[0]_i_3_n_11\,
      Q => bytecnt_reg(4),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[0]_i_3_n_10\,
      Q => bytecnt_reg(5),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[0]_i_3_n_9\,
      Q => bytecnt_reg(6),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[0]_i_3_n_8\,
      Q => bytecnt_reg(7),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[8]_i_1_n_15\,
      Q => bytecnt_reg(8),
      R => \bytecnt[0]_i_1__1_n_0\
    );
\bytecnt_reg[8]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \bytecnt_reg[0]_i_3_n_0\,
      CI_TOP => '0',
      CO(7) => \bytecnt_reg[8]_i_1_n_0\,
      CO(6) => \bytecnt_reg[8]_i_1_n_1\,
      CO(5) => \bytecnt_reg[8]_i_1_n_2\,
      CO(4) => \bytecnt_reg[8]_i_1_n_3\,
      CO(3) => \bytecnt_reg[8]_i_1_n_4\,
      CO(2) => \bytecnt_reg[8]_i_1_n_5\,
      CO(1) => \bytecnt_reg[8]_i_1_n_6\,
      CO(0) => \bytecnt_reg[8]_i_1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \bytecnt_reg[8]_i_1_n_8\,
      O(6) => \bytecnt_reg[8]_i_1_n_9\,
      O(5) => \bytecnt_reg[8]_i_1_n_10\,
      O(4) => \bytecnt_reg[8]_i_1_n_11\,
      O(3) => \bytecnt_reg[8]_i_1_n_12\,
      O(2) => \bytecnt_reg[8]_i_1_n_13\,
      O(1) => \bytecnt_reg[8]_i_1_n_14\,
      O(0) => \bytecnt_reg[8]_i_1_n_15\,
      S(7 downto 0) => bytecnt_reg(15 downto 8)
    );
\bytecnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \bytecnt[0]_i_2_n_0\,
      D => \bytecnt_reg[8]_i_1_n_14\,
      Q => bytecnt_reg(9),
      R => \bytecnt[0]_i_1__1_n_0\
    );
cs_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"83"
    )
        port map (
      I0 => \stateXfer__0\(1),
      I1 => \stateXfer__0\(0),
      I2 => \stateXfer__0\(2),
      O => cs
    );
\i[0]_i_1__21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000043157F15"
    )
        port map (
      I0 => \i[6]_i_4__1_n_0\,
      I1 => \stateXfer__0\(1),
      I2 => \stateXfer__0\(0),
      I3 => \stateXfer__0\(2),
      I4 => \mosi_sig0__4\,
      I5 => \i_reg_n_0_[0]\,
      O => \i[0]_i_1__21_n_0\
    );
\i[10]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800080"
    )
        port map (
      I0 => \i_reg[0]_0\,
      I1 => Q(1),
      I2 => Q(0),
      I3 => Q(2),
      I4 => \i_reg[0]_1\,
      I5 => \i[10]_i_3__0_n_0\,
      O => \FSM_sequential_stateOp_reg[1]_0\(0)
    );
\i[10]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000400100000000"
    )
        port map (
      I0 => Q(2),
      I1 => \stateXfer__0\(0),
      I2 => \stateXfer__0\(1),
      I3 => \stateXfer__0\(2),
      I4 => Q(0),
      I5 => Q(1),
      O => \i[10]_i_3__0_n_0\
    );
\i[1]_i_1__16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \i_reg_n_0_[1]\,
      O => \i[1]_i_1__16_n_0\
    );
\i[2]_i_1__12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[2]\,
      O => \i[2]_i_1__12_n_0\
    );
\i[3]_i_1__12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \i_reg_n_0_[2]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => \i_reg_n_0_[3]\,
      O => \i[3]_i_1__12_n_0\
    );
\i[4]_i_1__12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \i_reg_n_0_[3]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \i_reg_n_0_[2]\,
      I4 => \i_reg_n_0_[4]\,
      O => \i[4]_i_1__12_n_0\
    );
\i[5]_i_1__11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \i_reg_n_0_[4]\,
      I1 => \i_reg_n_0_[2]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[3]\,
      I5 => \i_reg_n_0_[5]\,
      O => \i[5]_i_1__11_n_0\
    );
\i[6]_i_1__13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA0A8888000A888"
    )
        port map (
      I0 => i0,
      I1 => \i[6]_i_4__1_n_0\,
      I2 => \stateXfer__0\(1),
      I3 => \stateXfer__0\(0),
      I4 => \stateXfer__0\(2),
      I5 => \mosi_sig0__4\,
      O => \i[6]_i_1__13_n_0\
    );
\i[6]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"050F0D00"
    )
        port map (
      I0 => \stateXfer__0\(1),
      I1 => req,
      I2 => \FSM_sequential_stateXfer_reg[2]_0\(0),
      I3 => \stateXfer__0\(0),
      I4 => \stateXfer__0\(2),
      O => i0
    );
\i[6]_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \i_reg_n_0_[5]\,
      I1 => \i[6]_i_5_n_0\,
      I2 => \i_reg_n_0_[6]\,
      O => \i[6]_i_3__1_n_0\
    );
\i[6]_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8288"
    )
        port map (
      I0 => \i[6]_i_6_n_0\,
      I1 => \i_reg_n_0_[6]\,
      I2 => \i[6]_i_5_n_0\,
      I3 => \i_reg_n_0_[5]\,
      O => \i[6]_i_4__1_n_0\
    );
\i[6]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \i_reg_n_0_[3]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \i_reg_n_0_[2]\,
      I4 => \i_reg_n_0_[4]\,
      O => \i[6]_i_5_n_0\
    );
\i[6]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002000"
    )
        port map (
      I0 => \i_reg_n_0_[5]\,
      I1 => \i_reg_n_0_[3]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[2]\,
      I5 => \i_reg_n_0_[4]\,
      O => \i[6]_i_6_n_0\
    );
\i__carry_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => bytecnt_reg(16),
      I1 => bytecnt_reg(15),
      O => \i__carry_i_1__2_n_0\
    );
\i__carry_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => bytecnt_reg(14),
      I1 => bytecnt_reg(13),
      I2 => bytecnt_reg(12),
      O => \i__carry_i_2__2_n_0\
    );
\i__carry_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => bytecnt_reg(11),
      I1 => bytecnt_reg(10),
      I2 => bytecnt_reg(9),
      O => \i__carry_i_3__2_n_0\
    );
\i__carry_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => bytecnt_reg(8),
      I1 => bytecnt_reg(7),
      I2 => bytecnt_reg(6),
      O => \i__carry_i_4__2_n_0\
    );
\i__carry_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => bytecnt_reg(5),
      I1 => bytecnt_reg(4),
      I2 => bytecnt_reg(3),
      O => \i__carry_i_5__2_n_0\
    );
\i__carry_i_6__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1001"
    )
        port map (
      I0 => bytecnt_reg(2),
      I1 => bytecnt_reg(0),
      I2 => len(0),
      I3 => bytecnt_reg(1),
      O => \i__carry_i_6__2_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i0,
      D => \i[0]_i_1__21_n_0\,
      Q => \i_reg_n_0_[0]\,
      R => '0'
    );
\i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i0,
      D => \i[1]_i_1__16_n_0\,
      Q => \i_reg_n_0_[1]\,
      R => \i[6]_i_1__13_n_0\
    );
\i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i0,
      D => \i[2]_i_1__12_n_0\,
      Q => \i_reg_n_0_[2]\,
      R => \i[6]_i_1__13_n_0\
    );
\i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i0,
      D => \i[3]_i_1__12_n_0\,
      Q => \i_reg_n_0_[3]\,
      R => \i[6]_i_1__13_n_0\
    );
\i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i0,
      D => \i[4]_i_1__12_n_0\,
      Q => \i_reg_n_0_[4]\,
      R => \i[6]_i_1__13_n_0\
    );
\i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i0,
      D => \i[5]_i_1__11_n_0\,
      Q => \i_reg_n_0_[5]\,
      R => \i[6]_i_1__13_n_0\
    );
\i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i0,
      D => \i[6]_i_3__1_n_0\,
      Q => \i_reg_n_0_[6]\,
      R => \i[6]_i_1__13_n_0\
    );
\j[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8CCCCCCC"
    )
        port map (
      I0 => \bitcnt[2]_i_4_n_0\,
      I1 => \j[0]_i_2_n_0\,
      I2 => bitcnt(0),
      I3 => bitcnt(1),
      I4 => bitcnt(2),
      O => \j[0]_i_1__1_n_0\
    );
\j[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFDF00000020"
    )
        port map (
      I0 => \i[6]_i_4__1_n_0\,
      I1 => \FSM_sequential_stateXfer_reg[2]_0\(0),
      I2 => \stateXfer__0\(0),
      I3 => \stateXfer__0\(2),
      I4 => \stateXfer__0\(1),
      I5 => \j_reg_n_0_[0]\,
      O => \j[0]_i_2_n_0\
    );
\j[7]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1000"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => Q(2),
      I3 => \FSM_sequential_stateOp_reg[0]_0\,
      I4 => \bytecnt[0]_i_3_n_0\,
      O => \FSM_sequential_stateOp_reg[1]_1\(0)
    );
\j_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      D => \j[0]_i_1__1_n_0\,
      Q => \j_reg_n_0_[0]\,
      R => '0'
    );
mosi_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFFFFFA0800000A"
    )
        port map (
      I0 => mosi_sig,
      I1 => \mosi_sig0__4\,
      I2 => \stateXfer__0\(0),
      I3 => \stateXfer__0\(1),
      I4 => \stateXfer__0\(2),
      I5 => \^mosi\,
      O => mosi_sig_i_1_n_0
    );
mosi_sig_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C088C088C08888C0"
    )
        port map (
      I0 => mosi_sig_i_4_n_0,
      I1 => mosi_sig_i_5_n_0,
      I2 => mosi_sig_i_6_n_0,
      I3 => bitcnt(2),
      I4 => bitcnt(1),
      I5 => bitcnt(0),
      O => mosi_sig
    );
mosi_sig_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2822"
    )
        port map (
      I0 => mosi_sig_i_7_n_0,
      I1 => \i_reg_n_0_[6]\,
      I2 => \i[6]_i_5_n_0\,
      I3 => \i_reg_n_0_[5]\,
      O => \mosi_sig0__4\
    );
mosi_sig_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FACF0ACFFAC00AC0"
    )
        port map (
      I0 => data7,
      I1 => data6,
      I2 => bitcnt(1),
      I3 => bitcnt(0),
      I4 => data5,
      I5 => data4,
      O => mosi_sig_i_4_n_0
    );
mosi_sig_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \stateXfer__0\(2),
      I1 => \stateXfer__0\(1),
      I2 => \stateXfer__0\(0),
      O => mosi_sig_i_5_n_0
    );
mosi_sig_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FACF0ACFFAC00AC0"
    )
        port map (
      I0 => data3,
      I1 => data2,
      I2 => bitcnt(1),
      I3 => bitcnt(0),
      I4 => \send_var_reg_n_0_[0]\,
      I5 => data0,
      O => mosi_sig_i_6_n_0
    );
mosi_sig_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => \i_reg_n_0_[5]\,
      I1 => \i_reg_n_0_[3]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[2]\,
      I5 => \i_reg_n_0_[4]\,
      O => mosi_sig_i_7_n_0
    );
mosi_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \FSM_sequential_stateXfer_reg[2]_0\(0),
      D => mosi_sig_i_1_n_0,
      Q => \^mosi\
    );
rNotL_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F3FFF7FFA2AAA2AA"
    )
        port map (
      I0 => \bytecnt[0]_i_3_n_0\,
      I1 => Q(0),
      I2 => Q(1),
      I3 => Q(2),
      I4 => reqInvLaserSet,
      I5 => rNotL_reg,
      O => \FSM_sequential_stateOp_reg[0]\
    );
sclk_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \stateXfer__0\(1),
      I1 => \stateXfer__0\(0),
      I2 => \stateXfer__0\(2),
      O => sclk
    );
\send_var_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => send_var0,
      D => \send_var_reg[7]_0\(0),
      Q => \send_var_reg_n_0_[0]\,
      R => '0'
    );
\send_var_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => send_var0,
      D => \send_var_reg[7]_0\(1),
      Q => data2,
      R => '0'
    );
\send_var_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => send_var0,
      D => \send_var_reg[7]_0\(2),
      Q => data3,
      R => '0'
    );
\send_var_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => send_var0,
      D => \send_var_reg[7]_0\(3),
      Q => data4,
      R => '0'
    );
\send_var_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => send_var0,
      D => \send_var_reg[7]_0\(4),
      Q => data5,
      R => '0'
    );
\send_var_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => send_var0,
      D => \send_var_reg[7]_0\(5),
      Q => data6,
      R => '0'
    );
\send_var_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => send_var0,
      D => \send_var_reg[7]_0\(6),
      Q => data7,
      R => '0'
    );
\send_var_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => send_var0,
      D => \send_var_reg[7]_0\(7),
      Q => data0,
      R => '0'
    );
\stateXfer1_inferred__0/i__carry\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_stateXfer1_inferred__0/i__carry_CO_UNCONNECTED\(7 downto 6),
      CO(5) => in5,
      CO(4) => \stateXfer1_inferred__0/i__carry_n_3\,
      CO(3) => \stateXfer1_inferred__0/i__carry_n_4\,
      CO(2) => \stateXfer1_inferred__0/i__carry_n_5\,
      CO(1) => \stateXfer1_inferred__0/i__carry_n_6\,
      CO(0) => \stateXfer1_inferred__0/i__carry_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_stateXfer1_inferred__0/i__carry_O_UNCONNECTED\(7 downto 0),
      S(7 downto 6) => B"00",
      S(5) => \i__carry_i_1__2_n_0\,
      S(4) => \i__carry_i_2__2_n_0\,
      S(3) => \i__carry_i_3__2_n_0\,
      S(2) => \i__carry_i_4__2_n_0\,
      S(1) => \i__carry_i_5__2_n_0\,
      S(0) => \i__carry_i_6__2_n_0\
    );
\txbuf[1][7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F83F0803"
    )
        port map (
      I0 => reqInvLaserSet,
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(0),
      I4 => \bytecnt[0]_i_3_n_0\,
      O => E(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_State is
  port (
    \seq_reg[1][13]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ixSeq_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ixSeq_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \seq_reg[0][5]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    rgb0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S : out STD_LOGIC_VECTOR ( 1 downto 0 );
    DI : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \seq_reg[1][13]_1\ : out STD_LOGIC;
    \i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \seq_reg[1][5]_0\ : in STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    \i_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \seq[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \stateBlue0_inferred__0/i__carry\ : in STD_LOGIC;
    \stateRed0_inferred__0/i__carry\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \stateRed0_inferred__0/i__carry_0\ : in STD_LOGIC;
    tkclk : in STD_LOGIC;
    stateStats : in STD_LOGIC;
    \i_reg[0]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \seq_reg[0][21]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_State : entity is "State";
end design_1_Vsp_core_0_0_State;

architecture STRUCTURE of design_1_Vsp_core_0_0_State is
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \i[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \i[10]_i_3_n_0\ : STD_LOGIC;
  signal \i[5]_i_2__2_n_0\ : STD_LOGIC;
  signal \i[9]_i_2__1_n_0\ : STD_LOGIC;
  signal i_reg : STD_LOGIC_VECTOR ( 10 downto 1 );
  signal \^i_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ixSeq : STD_LOGIC;
  signal \ixSeq[0]_i_1_n_0\ : STD_LOGIC;
  signal \ixSeq[1]_i_1_n_0\ : STD_LOGIC;
  signal \ixSeq[2]_i_2_n_0\ : STD_LOGIC;
  signal \ixSeq[2]_i_3_n_0\ : STD_LOGIC;
  signal \ixSeq[2]_i_4_n_0\ : STD_LOGIC;
  signal \ixSeq[2]_i_5_n_0\ : STD_LOGIC;
  signal \ixSeq_reg_n_0_[0]\ : STD_LOGIC;
  signal \ixSeq_reg_n_0_[1]\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 10 downto 1 );
  signal \seq[0][21]_i_1_n_0\ : STD_LOGIC;
  signal \seq[0][21]_i_3_n_0\ : STD_LOGIC;
  signal \seq[0][21]_i_4_n_0\ : STD_LOGIC;
  signal \seq[0][21]_i_5_n_0\ : STD_LOGIC;
  signal \seq_reg[0]_1\ : STD_LOGIC_VECTOR ( 21 downto 5 );
  signal \^seq_reg[1][13]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \seq_reg[1]_0\ : STD_LOGIC_VECTOR ( 5 to 5 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \i[10]_i_3\ : label is "soft_lutpair2878";
  attribute SOFT_HLUTNM of \i[1]_i_1__7\ : label is "soft_lutpair2879";
  attribute SOFT_HLUTNM of \i[2]_i_1__4\ : label is "soft_lutpair2875";
  attribute SOFT_HLUTNM of \i[3]_i_1__4\ : label is "soft_lutpair2875";
  attribute SOFT_HLUTNM of \i[5]_i_1__3\ : label is "soft_lutpair2879";
  attribute SOFT_HLUTNM of \i[6]_i_1__2\ : label is "soft_lutpair2878";
  attribute SOFT_HLUTNM of \i[7]_i_1__2\ : label is "soft_lutpair2876";
  attribute SOFT_HLUTNM of \i[8]_i_1__2\ : label is "soft_lutpair2876";
  attribute SOFT_HLUTNM of \ixSeq[0]_i_1\ : label is "soft_lutpair2873";
  attribute SOFT_HLUTNM of \ixSeq[2]_i_2\ : label is "soft_lutpair2877";
  attribute SOFT_HLUTNM of \ixSeq[2]_i_3\ : label is "soft_lutpair2874";
  attribute SOFT_HLUTNM of \seq[0][21]_i_5\ : label is "soft_lutpair2874";
  attribute SOFT_HLUTNM of stateBlue_i_6 : label is "soft_lutpair2873";
  attribute SOFT_HLUTNM of stateRed_i_6 : label is "soft_lutpair2877";
begin
  Q(0) <= \^q\(0);
  \i_reg[0]_0\(0) <= \^i_reg[0]_0\(0);
  \seq_reg[1][13]_0\(0) <= \^seq_reg[1][13]_0\(0);
\i[10]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => ixSeq,
      I1 => tkclk,
      I2 => stateStats,
      O => \i[10]_i_1__0_n_0\
    );
\i[10]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B040"
    )
        port map (
      I0 => \i[10]_i_3_n_0\,
      I1 => i_reg(9),
      I2 => stateStats,
      I3 => i_reg(10),
      O => p_0_in(10)
    );
\i[10]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7FF"
    )
        port map (
      I0 => i_reg(7),
      I1 => i_reg(6),
      I2 => \i[9]_i_2__1_n_0\,
      I3 => i_reg(8),
      O => \i[10]_i_3_n_0\
    );
\i[1]_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => i_reg(1),
      I1 => \^i_reg[0]_0\(0),
      I2 => stateStats,
      O => p_0_in(1)
    );
\i[2]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7080"
    )
        port map (
      I0 => \^i_reg[0]_0\(0),
      I1 => i_reg(1),
      I2 => stateStats,
      I3 => i_reg(2),
      O => p_0_in(2)
    );
\i[3]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F008000"
    )
        port map (
      I0 => i_reg(1),
      I1 => \^i_reg[0]_0\(0),
      I2 => i_reg(2),
      I3 => stateStats,
      I4 => i_reg(3),
      O => p_0_in(3)
    );
\i[4]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF000080000000"
    )
        port map (
      I0 => i_reg(2),
      I1 => \^i_reg[0]_0\(0),
      I2 => i_reg(1),
      I3 => i_reg(3),
      I4 => stateStats,
      I5 => i_reg(4),
      O => p_0_in(4)
    );
\i[5]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"48"
    )
        port map (
      I0 => \i[5]_i_2__2_n_0\,
      I1 => stateStats,
      I2 => i_reg(5),
      O => p_0_in(5)
    );
\i[5]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => i_reg(4),
      I1 => i_reg(3),
      I2 => i_reg(1),
      I3 => \^i_reg[0]_0\(0),
      I4 => i_reg(2),
      O => \i[5]_i_2__2_n_0\
    );
\i[6]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"84"
    )
        port map (
      I0 => \i[9]_i_2__1_n_0\,
      I1 => stateStats,
      I2 => i_reg(6),
      O => p_0_in(6)
    );
\i[7]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D020"
    )
        port map (
      I0 => i_reg(6),
      I1 => \i[9]_i_2__1_n_0\,
      I2 => stateStats,
      I3 => i_reg(7),
      O => p_0_in(7)
    );
\i[8]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BF004000"
    )
        port map (
      I0 => \i[9]_i_2__1_n_0\,
      I1 => i_reg(6),
      I2 => i_reg(7),
      I3 => stateStats,
      I4 => i_reg(8),
      O => p_0_in(8)
    );
\i[9]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FF000008000000"
    )
        port map (
      I0 => i_reg(7),
      I1 => i_reg(6),
      I2 => \i[9]_i_2__1_n_0\,
      I3 => i_reg(8),
      I4 => stateStats,
      I5 => i_reg(9),
      O => p_0_in(9)
    );
\i[9]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => i_reg(2),
      I1 => \^i_reg[0]_0\(0),
      I2 => i_reg(1),
      I3 => i_reg(3),
      I4 => i_reg(4),
      I5 => i_reg(5),
      O => \i[9]_i_2__1_n_0\
    );
\i__carry_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"002000F0FAFAFAFA"
    )
        port map (
      I0 => D(2),
      I1 => \ixSeq_reg_n_0_[0]\,
      I2 => D(3),
      I3 => \^q\(0),
      I4 => \ixSeq_reg_n_0_[1]\,
      I5 => \^seq_reg[1][13]_0\(0),
      O => \ixSeq_reg[0]_0\(1)
    );
\i__carry_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^seq_reg[1][13]_0\(0),
      I1 => \^q\(0),
      O => \seq_reg[1][13]_1\
    );
\i__carry_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000002AAAAAAA2"
    )
        port map (
      I0 => \stateBlue0_inferred__0/i__carry\,
      I1 => \seq_reg[0]_1\(5),
      I2 => \ixSeq_reg_n_0_[0]\,
      I3 => \ixSeq_reg_n_0_[1]\,
      I4 => \^q\(0),
      I5 => \seq_reg[1]_0\(5),
      O => \seq_reg[0][5]_0\(0)
    );
\i__carry_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA8AAAA"
    )
        port map (
      I0 => \stateRed0_inferred__0/i__carry_0\,
      I1 => \^q\(0),
      I2 => \ixSeq_reg_n_0_[1]\,
      I3 => \ixSeq_reg_n_0_[0]\,
      I4 => \seq_reg[0]_1\(21),
      O => DI(1)
    );
\i__carry_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEE0EEEEEEEE"
    )
        port map (
      I0 => \stateRed0_inferred__0/i__carry\(1),
      I1 => \stateRed0_inferred__0/i__carry\(0),
      I2 => \^q\(0),
      I3 => \ixSeq_reg_n_0_[1]\,
      I4 => \ixSeq_reg_n_0_[0]\,
      I5 => \seq_reg[0]_1\(21),
      O => DI(0)
    );
\i__carry_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3B3B333F2A22222A"
    )
        port map (
      I0 => D(1),
      I1 => \^seq_reg[1][13]_0\(0),
      I2 => \^q\(0),
      I3 => \ixSeq_reg_n_0_[0]\,
      I4 => \ixSeq_reg_n_0_[1]\,
      I5 => D(0),
      O => \ixSeq_reg[0]_0\(0)
    );
\i__carry_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C804C00400330833"
    )
        port map (
      I0 => \ixSeq_reg_n_0_[1]\,
      I1 => \^seq_reg[1][13]_0\(0),
      I2 => \^q\(0),
      I3 => D(3),
      I4 => \ixSeq_reg_n_0_[0]\,
      I5 => D(2),
      O => \ixSeq_reg[1]_0\(1)
    );
\i__carry_i_6__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000200000000FFFD"
    )
        port map (
      I0 => \seq_reg[0]_1\(21),
      I1 => \ixSeq_reg_n_0_[0]\,
      I2 => \ixSeq_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => \stateRed0_inferred__0/i__carry\(2),
      I5 => \stateRed0_inferred__0/i__carry\(3),
      O => S(1)
    );
\i__carry_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000200000000FFFD"
    )
        port map (
      I0 => \seq_reg[0]_1\(21),
      I1 => \ixSeq_reg_n_0_[0]\,
      I2 => \ixSeq_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => \stateRed0_inferred__0/i__carry\(0),
      I5 => \stateRed0_inferred__0/i__carry\(1),
      O => S(0)
    );
\i__carry_i_7__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8480888011191115"
    )
        port map (
      I0 => D(1),
      I1 => \^seq_reg[1][13]_0\(0),
      I2 => \^q\(0),
      I3 => \ixSeq_reg_n_0_[0]\,
      I4 => \ixSeq_reg_n_0_[1]\,
      I5 => D(0),
      O => \ixSeq_reg[1]_0\(0)
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[10]_i_1__0_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => \i_reg[0]_2\(0),
      Q => \^i_reg[0]_0\(0)
    );
\i_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[10]_i_1__0_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => p_0_in(10),
      Q => i_reg(10)
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[10]_i_1__0_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => p_0_in(1),
      Q => i_reg(1)
    );
\i_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[10]_i_1__0_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => p_0_in(2),
      Q => i_reg(2)
    );
\i_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[10]_i_1__0_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => p_0_in(3),
      Q => i_reg(3)
    );
\i_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[10]_i_1__0_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => p_0_in(4),
      Q => i_reg(4)
    );
\i_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[10]_i_1__0_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => p_0_in(5),
      Q => i_reg(5)
    );
\i_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[10]_i_1__0_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => p_0_in(6),
      Q => i_reg(6)
    );
\i_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[10]_i_1__0_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => p_0_in(7),
      Q => i_reg(7)
    );
\i_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[10]_i_1__0_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => p_0_in(8),
      Q => i_reg(8)
    );
\i_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[10]_i_1__0_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => p_0_in(9),
      Q => i_reg(9)
    );
\ixSeq[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \^q\(0),
      I1 => \ixSeq_reg_n_0_[1]\,
      I2 => \ixSeq_reg_n_0_[0]\,
      O => \ixSeq[0]_i_1_n_0\
    );
\ixSeq[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ixSeq_reg_n_0_[1]\,
      I1 => \ixSeq_reg_n_0_[0]\,
      O => \ixSeq[1]_i_1_n_0\
    );
\ixSeq[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A222000000000000"
    )
        port map (
      I0 => \ixSeq[2]_i_3_n_0\,
      I1 => i_reg(8),
      I2 => i_reg(6),
      I3 => i_reg(7),
      I4 => \ixSeq[2]_i_4_n_0\,
      I5 => \ixSeq[2]_i_5_n_0\,
      O => ixSeq
    );
\ixSeq[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"68"
    )
        port map (
      I0 => \ixSeq_reg_n_0_[0]\,
      I1 => \ixSeq_reg_n_0_[1]\,
      I2 => \^q\(0),
      O => \ixSeq[2]_i_2_n_0\
    );
\ixSeq[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => \^i_reg[0]_0\(0),
      I1 => i_reg(4),
      I2 => i_reg(5),
      I3 => i_reg(1),
      I4 => i_reg(2),
      O => \ixSeq[2]_i_3_n_0\
    );
\ixSeq[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"07"
    )
        port map (
      I0 => i_reg(3),
      I1 => i_reg(4),
      I2 => i_reg(5),
      O => \ixSeq[2]_i_4_n_0\
    );
\ixSeq[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000800000000000"
    )
        port map (
      I0 => i_reg(7),
      I1 => i_reg(8),
      I2 => i_reg(9),
      I3 => i_reg(10),
      I4 => stateStats,
      I5 => tkclk,
      O => \ixSeq[2]_i_5_n_0\
    );
\ixSeq_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ixSeq,
      CLR => \i_reg[0]_1\(0),
      D => \ixSeq[0]_i_1_n_0\,
      Q => \ixSeq_reg_n_0_[0]\
    );
\ixSeq_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ixSeq,
      CLR => \i_reg[0]_1\(0),
      D => \ixSeq[1]_i_1_n_0\,
      Q => \ixSeq_reg_n_0_[1]\
    );
\ixSeq_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ixSeq,
      CLR => \i_reg[0]_1\(0),
      D => \ixSeq[2]_i_2_n_0\,
      Q => \^q\(0)
    );
\seq[0][21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000888800000000"
    )
        port map (
      I0 => \seq[0][21]_i_3_n_0\,
      I1 => \ixSeq[2]_i_5_n_0\,
      I2 => i_reg(7),
      I3 => i_reg(6),
      I4 => i_reg(8),
      I5 => \seq[0][21]_i_4_n_0\,
      O => \seq[0][21]_i_1_n_0\
    );
\seq[0][21]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000004000000"
    )
        port map (
      I0 => \ixSeq_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => \ixSeq_reg_n_0_[1]\,
      I3 => \seq[0][21]_i_5_n_0\,
      I4 => i_reg(4),
      I5 => i_reg(5),
      O => \seq[0][21]_i_3_n_0\
    );
\seq[0][21]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0015000000150015"
    )
        port map (
      I0 => i_reg(5),
      I1 => i_reg(4),
      I2 => i_reg(3),
      I3 => i_reg(2),
      I4 => i_reg(1),
      I5 => \^i_reg[0]_0\(0),
      O => \seq[0][21]_i_4_n_0\
    );
\seq[0][21]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => i_reg(1),
      I1 => i_reg(2),
      O => \seq[0][21]_i_5_n_0\
    );
\seq_reg[0][21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \seq[0][21]_i_1_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => \seq_reg[0][21]_0\(1),
      Q => \seq_reg[0]_1\(21)
    );
\seq_reg[0][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \seq[0][21]_i_1_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => \seq_reg[0][21]_0\(0),
      Q => \seq_reg[0]_1\(5)
    );
\seq_reg[1][13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \seq[0][21]_i_1_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => \seq[1]_2\(0),
      Q => \^seq_reg[1][13]_0\(0)
    );
\seq_reg[1][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \seq[0][21]_i_1_n_0\,
      CLR => \i_reg[0]_1\(0),
      D => \seq_reg[1][5]_0\,
      Q => \seq_reg[1]_0\(5)
    );
stateBlue_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABAAA8"
    )
        port map (
      I0 => \seq_reg[1]_0\(5),
      I1 => \^q\(0),
      I2 => \ixSeq_reg_n_0_[1]\,
      I3 => \ixSeq_reg_n_0_[0]\,
      I4 => \seq_reg[0]_1\(5),
      O => rgb0(0)
    );
stateRed_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \seq_reg[0]_1\(21),
      I1 => \ixSeq_reg_n_0_[0]\,
      I2 => \ixSeq_reg_n_0_[1]\,
      I3 => \^q\(0),
      O => rgb0(1)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Stepmux is
  port (
    ackInvStepmuxSet : out STD_LOGIC;
    linNotRot_reg_0 : out STD_LOGIC;
    nslp : out STD_LOGIC;
    reqInvStepmuxSet : in STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    stateOp_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    linNotRot_reg_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Stepmux : entity is "Stepmux";
end design_1_Vsp_core_0_0_Stepmux;

architecture STRUCTURE of design_1_Vsp_core_0_0_Stepmux is
  signal \^linnotrot_reg_0\ : STD_LOGIC;
begin
  linNotRot_reg_0 <= \^linnotrot_reg_0\;
linNotRot_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => stateOp_reg_0(0),
      D => linNotRot_reg_1,
      Q => \^linnotrot_reg_0\
    );
nslp_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^linnotrot_reg_0\,
      O => nslp
    );
stateOp_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => stateOp_reg_0(0),
      D => reqInvStepmuxSet,
      Q => ackInvStepmuxSet
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Timeout_v1_0 is
  port (
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateOp_reg[1]_0\ : out STD_LOGIC;
    tkclk : in STD_LOGIC;
    \stateOp_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[0]_0\ : in STD_LOGIC;
    \stateOp[1]_i_3__1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    aclk_sig : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Timeout_v1_0 : entity is "Timeout_v1_0";
end design_1_Vsp_core_0_0_Timeout_v1_0;

architecture STRUCTURE of design_1_Vsp_core_0_0_Timeout_v1_0 is
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \i[6]_i_1__10_n_0\ : STD_LOGIC;
  signal \i[6]_i_2__1_n_0\ : STD_LOGIC;
  signal \i[6]_i_4__0_n_0\ : STD_LOGIC;
  signal i_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal stateOp : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \stateOp[1]_i_1__8_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_4__2_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_8__2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \i[1]_i_1__14\ : label is "soft_lutpair2820";
  attribute SOFT_HLUTNM of \i[2]_i_1__10\ : label is "soft_lutpair2819";
  attribute SOFT_HLUTNM of \i[3]_i_1__10\ : label is "soft_lutpair2819";
  attribute SOFT_HLUTNM of \i[4]_i_1__10\ : label is "soft_lutpair2817";
  attribute SOFT_HLUTNM of \i[6]_i_3__0\ : label is "soft_lutpair2821";
  attribute SOFT_HLUTNM of \i[6]_i_4__0\ : label is "soft_lutpair2817";
  attribute SOFT_HLUTNM of \stateOp[0]_i_1__7\ : label is "soft_lutpair2818";
  attribute SOFT_HLUTNM of \stateOp[1]_i_2__8\ : label is "soft_lutpair2818";
  attribute SOFT_HLUTNM of \stateOp[1]_i_4__2\ : label is "soft_lutpair2820";
  attribute SOFT_HLUTNM of \stateOp[1]_i_8__2\ : label is "soft_lutpair2821";
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
\i[0]_i_1__15\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => i_reg(0),
      O => p_0_in(0)
    );
\i[1]_i_1__14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => i_reg(0),
      I1 => i_reg(1),
      O => p_0_in(1)
    );
\i[2]_i_1__10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => i_reg(0),
      I1 => i_reg(1),
      I2 => i_reg(2),
      O => p_0_in(2)
    );
\i[3]_i_1__10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => i_reg(1),
      I1 => i_reg(0),
      I2 => i_reg(2),
      I3 => i_reg(3),
      O => p_0_in(3)
    );
\i[4]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => i_reg(2),
      I1 => i_reg(0),
      I2 => i_reg(1),
      I3 => i_reg(3),
      I4 => i_reg(4),
      O => p_0_in(4)
    );
\i[5]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => i_reg(3),
      I1 => i_reg(1),
      I2 => i_reg(0),
      I3 => i_reg(2),
      I4 => i_reg(4),
      I5 => i_reg(5),
      O => p_0_in(5)
    );
\i[6]_i_1__10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AB"
    )
        port map (
      I0 => \stateOp_reg[0]_0\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \stateOp_reg[1]_1\(0),
      O => \i[6]_i_1__10_n_0\
    );
\i[6]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => tkclk,
      I3 => \stateOp_reg[1]_1\(0),
      O => \i[6]_i_2__1_n_0\
    );
\i[6]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \i[6]_i_4__0_n_0\,
      I1 => i_reg(5),
      I2 => i_reg(6),
      O => p_0_in(6)
    );
\i[6]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => i_reg(4),
      I1 => i_reg(2),
      I2 => i_reg(0),
      I3 => i_reg(1),
      I4 => i_reg(3),
      O => \i[6]_i_4__0_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[6]_i_2__1_n_0\,
      D => p_0_in(0),
      Q => i_reg(0),
      R => \i[6]_i_1__10_n_0\
    );
\i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[6]_i_2__1_n_0\,
      D => p_0_in(1),
      Q => i_reg(1),
      R => \i[6]_i_1__10_n_0\
    );
\i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[6]_i_2__1_n_0\,
      D => p_0_in(2),
      Q => i_reg(2),
      R => \i[6]_i_1__10_n_0\
    );
\i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[6]_i_2__1_n_0\,
      D => p_0_in(3),
      Q => i_reg(3),
      R => \i[6]_i_1__10_n_0\
    );
\i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[6]_i_2__1_n_0\,
      D => p_0_in(4),
      Q => i_reg(4),
      R => \i[6]_i_1__10_n_0\
    );
\i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[6]_i_2__1_n_0\,
      D => p_0_in(5),
      Q => i_reg(5),
      R => \i[6]_i_1__10_n_0\
    );
\i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[6]_i_2__1_n_0\,
      D => p_0_in(6),
      Q => i_reg(6),
      R => \i[6]_i_1__10_n_0\
    );
\stateOp[0]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F0D"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \stateOp_reg[0]_0\,
      I3 => \stateOp[1]_i_4__2_n_0\,
      O => stateOp(0)
    );
\stateOp[1]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBFBBAF"
    )
        port map (
      I0 => \stateOp_reg[0]_0\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => tkclk,
      I4 => \stateOp[1]_i_4__2_n_0\,
      O => \stateOp[1]_i_1__8_n_0\
    );
\stateOp[1]_i_2__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \stateOp_reg[0]_0\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => stateOp(1)
    );
\stateOp[1]_i_4__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => i_reg(4),
      I1 => i_reg(1),
      I2 => i_reg(3),
      I3 => \stateOp[1]_i_8__2_n_0\,
      O => \stateOp[1]_i_4__2_n_0\
    );
\stateOp[1]_i_6__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => \stateOp[1]_i_3__1\(1),
      I1 => \stateOp[1]_i_3__1\(3),
      I2 => \stateOp[1]_i_3__1\(2),
      I3 => \stateOp[1]_i_3__1\(0),
      O => \stateOp_reg[1]_0\
    );
\stateOp[1]_i_8__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7FF"
    )
        port map (
      I0 => i_reg(6),
      I1 => i_reg(2),
      I2 => i_reg(0),
      I3 => i_reg(5),
      O => \stateOp[1]_i_8__2_n_0\
    );
\stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[1]_i_1__8_n_0\,
      CLR => \stateOp_reg[1]_1\(0),
      D => stateOp(0),
      Q => \^q\(0)
    );
\stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[1]_i_1__8_n_0\,
      CLR => \stateOp_reg[1]_1\(0),
      D => stateOp(1),
      Q => \^q\(1)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Timeout_v1_0_56 is
  port (
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateOp_reg[2]\ : out STD_LOGIC;
    tkclk : in STD_LOGIC;
    \stateOp_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[0]_1\ : in STD_LOGIC;
    \stateOp[1]_i_3\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    aclk_sig : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Timeout_v1_0_56 : entity is "Timeout_v1_0";
end design_1_Vsp_core_0_0_Timeout_v1_0_56;

architecture STRUCTURE of design_1_Vsp_core_0_0_Timeout_v1_0_56 is
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \i[6]_i_1__9_n_0\ : STD_LOGIC;
  signal \i[6]_i_2__0_n_0\ : STD_LOGIC;
  signal \i[6]_i_4_n_0\ : STD_LOGIC;
  signal i_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal stateOp : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \stateOp[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_4_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_8_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \i[1]_i_1__11\ : label is "soft_lutpair2255";
  attribute SOFT_HLUTNM of \i[2]_i_1__7\ : label is "soft_lutpair2254";
  attribute SOFT_HLUTNM of \i[3]_i_1__7\ : label is "soft_lutpair2254";
  attribute SOFT_HLUTNM of \i[4]_i_1__7\ : label is "soft_lutpair2252";
  attribute SOFT_HLUTNM of \i[6]_i_3\ : label is "soft_lutpair2256";
  attribute SOFT_HLUTNM of \i[6]_i_4\ : label is "soft_lutpair2252";
  attribute SOFT_HLUTNM of \stateOp[0]_i_1__4\ : label is "soft_lutpair2253";
  attribute SOFT_HLUTNM of \stateOp[1]_i_2__6\ : label is "soft_lutpair2253";
  attribute SOFT_HLUTNM of \stateOp[1]_i_4\ : label is "soft_lutpair2255";
  attribute SOFT_HLUTNM of \stateOp[1]_i_8\ : label is "soft_lutpair2256";
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
\i[0]_i_1__12\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => i_reg(0),
      O => p_0_in(0)
    );
\i[1]_i_1__11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => i_reg(0),
      I1 => i_reg(1),
      O => p_0_in(1)
    );
\i[2]_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => i_reg(0),
      I1 => i_reg(1),
      I2 => i_reg(2),
      O => p_0_in(2)
    );
\i[3]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => i_reg(1),
      I1 => i_reg(0),
      I2 => i_reg(2),
      I3 => i_reg(3),
      O => p_0_in(3)
    );
\i[4]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => i_reg(2),
      I1 => i_reg(0),
      I2 => i_reg(1),
      I3 => i_reg(3),
      I4 => i_reg(4),
      O => p_0_in(4)
    );
\i[5]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => i_reg(3),
      I1 => i_reg(1),
      I2 => i_reg(0),
      I3 => i_reg(2),
      I4 => i_reg(4),
      I5 => i_reg(5),
      O => p_0_in(5)
    );
\i[6]_i_1__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AB"
    )
        port map (
      I0 => \stateOp_reg[0]_1\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \stateOp_reg[0]_0\(0),
      O => \i[6]_i_1__9_n_0\
    );
\i[6]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => tkclk,
      I3 => \stateOp_reg[0]_0\(0),
      O => \i[6]_i_2__0_n_0\
    );
\i[6]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \i[6]_i_4_n_0\,
      I1 => i_reg(5),
      I2 => i_reg(6),
      O => p_0_in(6)
    );
\i[6]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => i_reg(4),
      I1 => i_reg(2),
      I2 => i_reg(0),
      I3 => i_reg(1),
      I4 => i_reg(3),
      O => \i[6]_i_4_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[6]_i_2__0_n_0\,
      D => p_0_in(0),
      Q => i_reg(0),
      R => \i[6]_i_1__9_n_0\
    );
\i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[6]_i_2__0_n_0\,
      D => p_0_in(1),
      Q => i_reg(1),
      R => \i[6]_i_1__9_n_0\
    );
\i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[6]_i_2__0_n_0\,
      D => p_0_in(2),
      Q => i_reg(2),
      R => \i[6]_i_1__9_n_0\
    );
\i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[6]_i_2__0_n_0\,
      D => p_0_in(3),
      Q => i_reg(3),
      R => \i[6]_i_1__9_n_0\
    );
\i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[6]_i_2__0_n_0\,
      D => p_0_in(4),
      Q => i_reg(4),
      R => \i[6]_i_1__9_n_0\
    );
\i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[6]_i_2__0_n_0\,
      D => p_0_in(5),
      Q => i_reg(5),
      R => \i[6]_i_1__9_n_0\
    );
\i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[6]_i_2__0_n_0\,
      D => p_0_in(6),
      Q => i_reg(6),
      R => \i[6]_i_1__9_n_0\
    );
\stateOp[0]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F0D"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \stateOp_reg[0]_1\,
      I3 => \stateOp[1]_i_4_n_0\,
      O => stateOp(0)
    );
\stateOp[1]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBFBBAF"
    )
        port map (
      I0 => \stateOp_reg[0]_1\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => tkclk,
      I4 => \stateOp[1]_i_4_n_0\,
      O => \stateOp[1]_i_1__6_n_0\
    );
\stateOp[1]_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \stateOp_reg[0]_1\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => stateOp(1)
    );
\stateOp[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => i_reg(4),
      I1 => i_reg(1),
      I2 => i_reg(3),
      I3 => \stateOp[1]_i_8_n_0\,
      O => \stateOp[1]_i_4_n_0\
    );
\stateOp[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFB3FFFFFFFFF"
    )
        port map (
      I0 => \stateOp[1]_i_3\(2),
      I1 => \stateOp[1]_i_3\(3),
      I2 => \stateOp[1]_i_3\(1),
      I3 => \stateOp[1]_i_3\(4),
      I4 => \stateOp[1]_i_3\(5),
      I5 => \stateOp[1]_i_3\(0),
      O => \stateOp_reg[2]\
    );
\stateOp[1]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7FF"
    )
        port map (
      I0 => i_reg(6),
      I1 => i_reg(2),
      I2 => i_reg(0),
      I3 => i_reg(5),
      O => \stateOp[1]_i_8_n_0\
    );
\stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[1]_i_1__6_n_0\,
      CLR => \stateOp_reg[0]_0\(0),
      D => stateOp(0),
      Q => \^q\(0)
    );
\stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[1]_i_1__6_n_0\,
      CLR => \stateOp_reg[0]_0\(0),
      D => stateOp(1),
      Q => \^q\(1)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Timeout_v1_0__parameterized1\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    tkclk : in STD_LOGIC;
    \stateOp_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[0]_1\ : in STD_LOGIC;
    aclk_sig : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Timeout_v1_0__parameterized1\ : entity is "Timeout_v1_0";
end \design_1_Vsp_core_0_0_Timeout_v1_0__parameterized1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Timeout_v1_0__parameterized1\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \i[9]_i_1__6_n_0\ : STD_LOGIC;
  signal \i[9]_i_2__6_n_0\ : STD_LOGIC;
  signal \i[9]_i_4__1_n_0\ : STD_LOGIC;
  signal i_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal stateOp : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \stateOp[1]_i_1__9_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_4__3_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_5__3_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \i[1]_i_1__15\ : label is "soft_lutpair2826";
  attribute SOFT_HLUTNM of \i[2]_i_1__11\ : label is "soft_lutpair2826";
  attribute SOFT_HLUTNM of \i[3]_i_1__11\ : label is "soft_lutpair2823";
  attribute SOFT_HLUTNM of \i[4]_i_1__11\ : label is "soft_lutpair2823";
  attribute SOFT_HLUTNM of \i[6]_i_1__8\ : label is "soft_lutpair2825";
  attribute SOFT_HLUTNM of \i[7]_i_1__8\ : label is "soft_lutpair2825";
  attribute SOFT_HLUTNM of \i[8]_i_1__7\ : label is "soft_lutpair2822";
  attribute SOFT_HLUTNM of \i[9]_i_3__1\ : label is "soft_lutpair2822";
  attribute SOFT_HLUTNM of \stateOp[0]_i_1__8\ : label is "soft_lutpair2824";
  attribute SOFT_HLUTNM of \stateOp[1]_i_2__9\ : label is "soft_lutpair2824";
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
\i[0]_i_1__16\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => i_reg(0),
      O => p_0_in(0)
    );
\i[1]_i_1__15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => i_reg(0),
      I1 => i_reg(1),
      O => p_0_in(1)
    );
\i[2]_i_1__11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => i_reg(0),
      I1 => i_reg(1),
      I2 => i_reg(2),
      O => p_0_in(2)
    );
\i[3]_i_1__11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => i_reg(1),
      I1 => i_reg(0),
      I2 => i_reg(2),
      I3 => i_reg(3),
      O => p_0_in(3)
    );
\i[4]_i_1__11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => i_reg(2),
      I1 => i_reg(0),
      I2 => i_reg(1),
      I3 => i_reg(3),
      I4 => i_reg(4),
      O => p_0_in(4)
    );
\i[5]_i_1__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => i_reg(3),
      I1 => i_reg(1),
      I2 => i_reg(0),
      I3 => i_reg(2),
      I4 => i_reg(4),
      I5 => i_reg(5),
      O => p_0_in(5)
    );
\i[6]_i_1__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \i[9]_i_4__1_n_0\,
      I1 => i_reg(6),
      O => p_0_in(6)
    );
\i[7]_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \i[9]_i_4__1_n_0\,
      I1 => i_reg(6),
      I2 => i_reg(7),
      O => p_0_in(7)
    );
\i[8]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => i_reg(6),
      I1 => \i[9]_i_4__1_n_0\,
      I2 => i_reg(7),
      I3 => i_reg(8),
      O => p_0_in(8)
    );
\i[9]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AB"
    )
        port map (
      I0 => \stateOp_reg[0]_1\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \stateOp_reg[0]_0\(0),
      O => \i[9]_i_1__6_n_0\
    );
\i[9]_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => tkclk,
      I3 => \stateOp_reg[0]_0\(0),
      O => \i[9]_i_2__6_n_0\
    );
\i[9]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => i_reg(7),
      I1 => \i[9]_i_4__1_n_0\,
      I2 => i_reg(6),
      I3 => i_reg(8),
      I4 => i_reg(9),
      O => p_0_in(9)
    );
\i[9]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => i_reg(5),
      I1 => i_reg(3),
      I2 => i_reg(1),
      I3 => i_reg(0),
      I4 => i_reg(2),
      I5 => i_reg(4),
      O => \i[9]_i_4__1_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__6_n_0\,
      D => p_0_in(0),
      Q => i_reg(0),
      R => \i[9]_i_1__6_n_0\
    );
\i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__6_n_0\,
      D => p_0_in(1),
      Q => i_reg(1),
      R => \i[9]_i_1__6_n_0\
    );
\i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__6_n_0\,
      D => p_0_in(2),
      Q => i_reg(2),
      R => \i[9]_i_1__6_n_0\
    );
\i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__6_n_0\,
      D => p_0_in(3),
      Q => i_reg(3),
      R => \i[9]_i_1__6_n_0\
    );
\i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__6_n_0\,
      D => p_0_in(4),
      Q => i_reg(4),
      R => \i[9]_i_1__6_n_0\
    );
\i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__6_n_0\,
      D => p_0_in(5),
      Q => i_reg(5),
      R => \i[9]_i_1__6_n_0\
    );
\i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__6_n_0\,
      D => p_0_in(6),
      Q => i_reg(6),
      R => \i[9]_i_1__6_n_0\
    );
\i_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__6_n_0\,
      D => p_0_in(7),
      Q => i_reg(7),
      R => \i[9]_i_1__6_n_0\
    );
\i_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__6_n_0\,
      D => p_0_in(8),
      Q => i_reg(8),
      R => \i[9]_i_1__6_n_0\
    );
\i_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__6_n_0\,
      D => p_0_in(9),
      Q => i_reg(9),
      R => \i[9]_i_1__6_n_0\
    );
\stateOp[0]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F0D"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \stateOp_reg[0]_1\,
      I3 => \stateOp[1]_i_4__3_n_0\,
      O => stateOp(0)
    );
\stateOp[1]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBFBBAF"
    )
        port map (
      I0 => \stateOp_reg[0]_1\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => tkclk,
      I4 => \stateOp[1]_i_4__3_n_0\,
      O => \stateOp[1]_i_1__9_n_0\
    );
\stateOp[1]_i_2__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \stateOp_reg[0]_1\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => stateOp(1)
    );
\stateOp[1]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => i_reg(1),
      I1 => i_reg(0),
      I2 => i_reg(8),
      I3 => i_reg(2),
      I4 => i_reg(4),
      I5 => \stateOp[1]_i_5__3_n_0\,
      O => \stateOp[1]_i_4__3_n_0\
    );
\stateOp[1]_i_5__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => i_reg(9),
      I1 => i_reg(7),
      I2 => i_reg(3),
      I3 => i_reg(5),
      I4 => i_reg(6),
      O => \stateOp[1]_i_5__3_n_0\
    );
\stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[1]_i_1__9_n_0\,
      CLR => \stateOp_reg[0]_0\(0),
      D => stateOp(0),
      Q => \^q\(0)
    );
\stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[1]_i_1__9_n_0\,
      CLR => \stateOp_reg[0]_0\(0),
      D => stateOp(1),
      Q => \^q\(1)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Timeout_v1_0__parameterized1_57\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateOp_reg[0]_0\ : out STD_LOGIC;
    \stateOp_reg[2]\ : out STD_LOGIC;
    \stateOp_reg[3]\ : out STD_LOGIC;
    tkclk : in STD_LOGIC;
    \stateOp_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[0]_1\ : in STD_LOGIC;
    \stateOp[1]_i_3__0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    aclk_sig : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Timeout_v1_0__parameterized1_57\ : entity is "Timeout_v1_0";
end \design_1_Vsp_core_0_0_Timeout_v1_0__parameterized1_57\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Timeout_v1_0__parameterized1_57\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \i[9]_i_1__5_n_0\ : STD_LOGIC;
  signal \i[9]_i_2__5_n_0\ : STD_LOGIC;
  signal \i[9]_i_4__0_n_0\ : STD_LOGIC;
  signal i_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal stateOp : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \stateOp[1]_i_1__7_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_4__0_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_8__0_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \i[1]_i_1__12\ : label is "soft_lutpair2261";
  attribute SOFT_HLUTNM of \i[2]_i_1__8\ : label is "soft_lutpair2261";
  attribute SOFT_HLUTNM of \i[3]_i_1__8\ : label is "soft_lutpair2258";
  attribute SOFT_HLUTNM of \i[4]_i_1__8\ : label is "soft_lutpair2258";
  attribute SOFT_HLUTNM of \i[6]_i_1__6\ : label is "soft_lutpair2260";
  attribute SOFT_HLUTNM of \i[7]_i_1__6\ : label is "soft_lutpair2260";
  attribute SOFT_HLUTNM of \i[8]_i_1__5\ : label is "soft_lutpair2257";
  attribute SOFT_HLUTNM of \i[9]_i_3__0\ : label is "soft_lutpair2257";
  attribute SOFT_HLUTNM of \stateOp[0]_i_1__5\ : label is "soft_lutpair2259";
  attribute SOFT_HLUTNM of \stateOp[1]_i_2__7\ : label is "soft_lutpair2259";
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
\i[0]_i_1__13\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => i_reg(0),
      O => p_0_in(0)
    );
\i[1]_i_1__12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => i_reg(0),
      I1 => i_reg(1),
      O => p_0_in(1)
    );
\i[2]_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => i_reg(0),
      I1 => i_reg(1),
      I2 => i_reg(2),
      O => p_0_in(2)
    );
\i[3]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => i_reg(1),
      I1 => i_reg(0),
      I2 => i_reg(2),
      I3 => i_reg(3),
      O => p_0_in(3)
    );
\i[4]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => i_reg(2),
      I1 => i_reg(0),
      I2 => i_reg(1),
      I3 => i_reg(3),
      I4 => i_reg(4),
      O => p_0_in(4)
    );
\i[5]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => i_reg(3),
      I1 => i_reg(1),
      I2 => i_reg(0),
      I3 => i_reg(2),
      I4 => i_reg(4),
      I5 => i_reg(5),
      O => p_0_in(5)
    );
\i[6]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \i[9]_i_4__0_n_0\,
      I1 => i_reg(6),
      O => p_0_in(6)
    );
\i[7]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \i[9]_i_4__0_n_0\,
      I1 => i_reg(6),
      I2 => i_reg(7),
      O => p_0_in(7)
    );
\i[8]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => i_reg(6),
      I1 => \i[9]_i_4__0_n_0\,
      I2 => i_reg(7),
      I3 => i_reg(8),
      O => p_0_in(8)
    );
\i[9]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AB"
    )
        port map (
      I0 => \stateOp_reg[0]_1\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \stateOp_reg[1]_0\(0),
      O => \i[9]_i_1__5_n_0\
    );
\i[9]_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => tkclk,
      I3 => \stateOp_reg[1]_0\(0),
      O => \i[9]_i_2__5_n_0\
    );
\i[9]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => i_reg(7),
      I1 => \i[9]_i_4__0_n_0\,
      I2 => i_reg(6),
      I3 => i_reg(8),
      I4 => i_reg(9),
      O => p_0_in(9)
    );
\i[9]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => i_reg(5),
      I1 => i_reg(3),
      I2 => i_reg(1),
      I3 => i_reg(0),
      I4 => i_reg(2),
      I5 => i_reg(4),
      O => \i[9]_i_4__0_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__5_n_0\,
      D => p_0_in(0),
      Q => i_reg(0),
      R => \i[9]_i_1__5_n_0\
    );
\i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__5_n_0\,
      D => p_0_in(1),
      Q => i_reg(1),
      R => \i[9]_i_1__5_n_0\
    );
\i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__5_n_0\,
      D => p_0_in(2),
      Q => i_reg(2),
      R => \i[9]_i_1__5_n_0\
    );
\i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__5_n_0\,
      D => p_0_in(3),
      Q => i_reg(3),
      R => \i[9]_i_1__5_n_0\
    );
\i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__5_n_0\,
      D => p_0_in(4),
      Q => i_reg(4),
      R => \i[9]_i_1__5_n_0\
    );
\i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__5_n_0\,
      D => p_0_in(5),
      Q => i_reg(5),
      R => \i[9]_i_1__5_n_0\
    );
\i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__5_n_0\,
      D => p_0_in(6),
      Q => i_reg(6),
      R => \i[9]_i_1__5_n_0\
    );
\i_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__5_n_0\,
      D => p_0_in(7),
      Q => i_reg(7),
      R => \i[9]_i_1__5_n_0\
    );
\i_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__5_n_0\,
      D => p_0_in(8),
      Q => i_reg(8),
      R => \i[9]_i_1__5_n_0\
    );
\i_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[9]_i_2__5_n_0\,
      D => p_0_in(9),
      Q => i_reg(9),
      R => \i[9]_i_1__5_n_0\
    );
\stateOp[0]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F0D"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \stateOp_reg[0]_1\,
      I3 => \stateOp[1]_i_4__0_n_0\,
      O => stateOp(0)
    );
\stateOp[1]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBFBBAF"
    )
        port map (
      I0 => \stateOp_reg[0]_1\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => tkclk,
      I4 => \stateOp[1]_i_4__0_n_0\,
      O => \stateOp[1]_i_1__7_n_0\
    );
\stateOp[1]_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \stateOp_reg[0]_1\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => stateOp(1)
    );
\stateOp[1]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => i_reg(1),
      I1 => i_reg(0),
      I2 => i_reg(8),
      I3 => i_reg(2),
      I4 => i_reg(4),
      I5 => \stateOp[1]_i_8__0_n_0\,
      O => \stateOp[1]_i_4__0_n_0\
    );
\stateOp[1]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF6FFFFFBFF"
    )
        port map (
      I0 => \stateOp[1]_i_3__0\(0),
      I1 => \stateOp[1]_i_3__0\(2),
      I2 => \stateOp[1]_i_3__0\(3),
      I3 => \stateOp[1]_i_3__0\(1),
      I4 => \stateOp[1]_i_3__0\(4),
      I5 => \stateOp[1]_i_3__0\(5),
      O => \stateOp_reg[0]_0\
    );
\stateOp[1]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008000040"
    )
        port map (
      I0 => \stateOp[1]_i_3__0\(3),
      I1 => \stateOp[1]_i_3__0\(1),
      I2 => \stateOp[1]_i_3__0\(5),
      I3 => \stateOp[1]_i_3__0\(4),
      I4 => \stateOp[1]_i_3__0\(2),
      I5 => \stateOp[1]_i_3__0\(0),
      O => \stateOp_reg[3]\
    );
\stateOp[1]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040000800000020"
    )
        port map (
      I0 => \stateOp[1]_i_3__0\(2),
      I1 => \stateOp[1]_i_3__0\(0),
      I2 => \stateOp[1]_i_3__0\(4),
      I3 => \stateOp[1]_i_3__0\(5),
      I4 => \stateOp[1]_i_3__0\(1),
      I5 => \stateOp[1]_i_3__0\(3),
      O => \stateOp_reg[2]\
    );
\stateOp[1]_i_8__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => i_reg(9),
      I1 => i_reg(7),
      I2 => i_reg(3),
      I3 => i_reg(5),
      I4 => i_reg(6),
      O => \stateOp[1]_i_8__0_n_0\
    );
\stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[1]_i_1__7_n_0\,
      CLR => \stateOp_reg[1]_0\(0),
      D => stateOp(0),
      Q => \^q\(0)
    );
\stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[1]_i_1__7_n_0\,
      CLR => \stateOp_reg[1]_0\(0),
      D => stateOp(1),
      Q => \^q\(1)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Tkclksrc_Easy_v1_0 is
  port (
    tkclk : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ackInvTkclksrcSetTkst : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    tkclk_sig_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    reqInvTkclksrcSetTkst : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 23 downto 0 );
    \tkst_reg[31]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \stateOp_reg[1]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Tkclksrc_Easy_v1_0 : entity is "Tkclksrc_Easy_v1_0";
end design_1_Vsp_core_0_0_Tkclksrc_Easy_v1_0;

architecture STRUCTURE of design_1_Vsp_core_0_0_Tkclksrc_Easy_v1_0 is
  signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal i : STD_LOGIC;
  signal \i[0]_i_1__9_n_0\ : STD_LOGIC;
  signal \i[10]_i_1__1_n_0\ : STD_LOGIC;
  signal \i[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \i[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \i[13]_i_2__0_n_0\ : STD_LOGIC;
  signal \i[13]_i_3__0_n_0\ : STD_LOGIC;
  signal \i[13]_i_4_n_0\ : STD_LOGIC;
  signal \i[1]_i_1__8_n_0\ : STD_LOGIC;
  signal \i[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \i[3]_i_1__5_n_0\ : STD_LOGIC;
  signal \i[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \i[5]_i_1__4_n_0\ : STD_LOGIC;
  signal \i[5]_i_2__3_n_0\ : STD_LOGIC;
  signal \i[6]_i_1__3_n_0\ : STD_LOGIC;
  signal \i[7]_i_1__3_n_0\ : STD_LOGIC;
  signal \i[8]_i_1__3_n_0\ : STD_LOGIC;
  signal \i[9]_i_1__2_n_0\ : STD_LOGIC;
  signal \i[9]_i_2__2_n_0\ : STD_LOGIC;
  signal \i_reg_n_0_[0]\ : STD_LOGIC;
  signal \i_reg_n_0_[10]\ : STD_LOGIC;
  signal \i_reg_n_0_[11]\ : STD_LOGIC;
  signal \i_reg_n_0_[12]\ : STD_LOGIC;
  signal \i_reg_n_0_[13]\ : STD_LOGIC;
  signal \i_reg_n_0_[1]\ : STD_LOGIC;
  signal \i_reg_n_0_[2]\ : STD_LOGIC;
  signal \i_reg_n_0_[3]\ : STD_LOGIC;
  signal \i_reg_n_0_[4]\ : STD_LOGIC;
  signal \i_reg_n_0_[5]\ : STD_LOGIC;
  signal \i_reg_n_0_[6]\ : STD_LOGIC;
  signal \i_reg_n_0_[7]\ : STD_LOGIC;
  signal \i_reg_n_0_[8]\ : STD_LOGIC;
  signal \i_reg_n_0_[9]\ : STD_LOGIC;
  signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \plusOp__60\ : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal \plusOp_carry__0_n_0\ : STD_LOGIC;
  signal \plusOp_carry__0_n_1\ : STD_LOGIC;
  signal \plusOp_carry__0_n_2\ : STD_LOGIC;
  signal \plusOp_carry__0_n_3\ : STD_LOGIC;
  signal \plusOp_carry__0_n_4\ : STD_LOGIC;
  signal \plusOp_carry__0_n_5\ : STD_LOGIC;
  signal \plusOp_carry__0_n_6\ : STD_LOGIC;
  signal \plusOp_carry__0_n_7\ : STD_LOGIC;
  signal \plusOp_carry__1_n_0\ : STD_LOGIC;
  signal \plusOp_carry__1_n_1\ : STD_LOGIC;
  signal \plusOp_carry__1_n_2\ : STD_LOGIC;
  signal \plusOp_carry__1_n_3\ : STD_LOGIC;
  signal \plusOp_carry__1_n_4\ : STD_LOGIC;
  signal \plusOp_carry__1_n_5\ : STD_LOGIC;
  signal \plusOp_carry__1_n_6\ : STD_LOGIC;
  signal \plusOp_carry__1_n_7\ : STD_LOGIC;
  signal \plusOp_carry__2_n_2\ : STD_LOGIC;
  signal \plusOp_carry__2_n_3\ : STD_LOGIC;
  signal \plusOp_carry__2_n_4\ : STD_LOGIC;
  signal \plusOp_carry__2_n_5\ : STD_LOGIC;
  signal \plusOp_carry__2_n_6\ : STD_LOGIC;
  signal \plusOp_carry__2_n_7\ : STD_LOGIC;
  signal plusOp_carry_n_0 : STD_LOGIC;
  signal plusOp_carry_n_1 : STD_LOGIC;
  signal plusOp_carry_n_2 : STD_LOGIC;
  signal plusOp_carry_n_3 : STD_LOGIC;
  signal plusOp_carry_n_4 : STD_LOGIC;
  signal plusOp_carry_n_5 : STD_LOGIC;
  signal plusOp_carry_n_6 : STD_LOGIC;
  signal plusOp_carry_n_7 : STD_LOGIC;
  signal \stateOp[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \stateOp_reg_n_0_[0]\ : STD_LOGIC;
  signal \stateOp_reg_n_0_[1]\ : STD_LOGIC;
  signal \^tkclk\ : STD_LOGIC;
  signal \tkclk_sig1__3\ : STD_LOGIC_VECTOR ( 10 to 10 );
  signal tkclk_sig_i_1_n_0 : STD_LOGIC;
  signal \tkst[31]_i_1__1_n_0\ : STD_LOGIC;
  signal \tkst[31]_i_3_n_0\ : STD_LOGIC;
  signal \tkst[31]_i_4_n_0\ : STD_LOGIC;
  signal \tkst[31]_i_5_n_0\ : STD_LOGIC;
  signal \tkst[31]_i_6_n_0\ : STD_LOGIC;
  signal \NLW_plusOp_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_plusOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \i[0]_i_1__9\ : label is "soft_lutpair2885";
  attribute SOFT_HLUTNM of \i[10]_i_1__1\ : label is "soft_lutpair2887";
  attribute SOFT_HLUTNM of \i[11]_i_1__0\ : label is "soft_lutpair2887";
  attribute SOFT_HLUTNM of \i[12]_i_1__0\ : label is "soft_lutpair2884";
  attribute SOFT_HLUTNM of \i[13]_i_2__0\ : label is "soft_lutpair2884";
  attribute SOFT_HLUTNM of \i[13]_i_3__0\ : label is "soft_lutpair2880";
  attribute SOFT_HLUTNM of \i[1]_i_1__8\ : label is "soft_lutpair2885";
  attribute SOFT_HLUTNM of \i[2]_i_1__5\ : label is "soft_lutpair2882";
  attribute SOFT_HLUTNM of \i[3]_i_1__5\ : label is "soft_lutpair2882";
  attribute SOFT_HLUTNM of \i[5]_i_1__4\ : label is "soft_lutpair2886";
  attribute SOFT_HLUTNM of \i[6]_i_1__3\ : label is "soft_lutpair2886";
  attribute SOFT_HLUTNM of \i[7]_i_1__3\ : label is "soft_lutpair2883";
  attribute SOFT_HLUTNM of \i[8]_i_1__3\ : label is "soft_lutpair2883";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of plusOp_carry : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_carry__0\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_carry__1\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_carry__2\ : label is 35;
  attribute SOFT_HLUTNM of \stateOp[5]_i_67\ : label is "soft_lutpair2881";
  attribute SOFT_HLUTNM of tkclk_sig_i_1 : label is "soft_lutpair2880";
  attribute SOFT_HLUTNM of \tkst[0]_i_1__0\ : label is "soft_lutpair2881";
begin
  Q(31 downto 0) <= \^q\(31 downto 0);
  tkclk <= \^tkclk\;
\i[0]_i_1__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \i[13]_i_3__0_n_0\,
      I1 => \i_reg_n_0_[0]\,
      O => \i[0]_i_1__9_n_0\
    );
\i[10]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \i[13]_i_3__0_n_0\,
      I1 => \tkclk_sig1__3\(10),
      O => \i[10]_i_1__1_n_0\
    );
\i[10]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFF08000000"
    )
        port map (
      I0 => \i_reg_n_0_[8]\,
      I1 => \i_reg_n_0_[7]\,
      I2 => \i[9]_i_2__2_n_0\,
      I3 => \i_reg_n_0_[6]\,
      I4 => \i_reg_n_0_[9]\,
      I5 => \i_reg_n_0_[10]\,
      O => \tkclk_sig1__3\(10)
    );
\i[11]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \i[13]_i_3__0_n_0\,
      I1 => \i_reg_n_0_[11]\,
      I2 => \i[13]_i_4_n_0\,
      O => \i[11]_i_1__0_n_0\
    );
\i[12]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8288"
    )
        port map (
      I0 => \i[13]_i_3__0_n_0\,
      I1 => \i_reg_n_0_[12]\,
      I2 => \i[13]_i_4_n_0\,
      I3 => \i_reg_n_0_[11]\,
      O => \i[12]_i_1__0_n_0\
    );
\i[13]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D5"
    )
        port map (
      I0 => \stateOp_reg_n_0_[0]\,
      I1 => \stateOp_reg_n_0_[1]\,
      I2 => reqInvTkclksrcSetTkst,
      O => i
    );
\i[13]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88288888"
    )
        port map (
      I0 => \i[13]_i_3__0_n_0\,
      I1 => \i_reg_n_0_[13]\,
      I2 => \i_reg_n_0_[11]\,
      I3 => \i[13]_i_4_n_0\,
      I4 => \i_reg_n_0_[12]\,
      O => \i[13]_i_2__0_n_0\
    );
\i[13]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0454"
    )
        port map (
      I0 => \tkst[31]_i_3_n_0\,
      I1 => \stateOp_reg_n_0_[0]\,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => reqInvTkclksrcSetTkst,
      O => \i[13]_i_3__0_n_0\
    );
\i[13]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \i_reg_n_0_[8]\,
      I1 => \i_reg_n_0_[7]\,
      I2 => \i[9]_i_2__2_n_0\,
      I3 => \i_reg_n_0_[6]\,
      I4 => \i_reg_n_0_[9]\,
      I5 => \i_reg_n_0_[10]\,
      O => \i[13]_i_4_n_0\
    );
\i[1]_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \i[13]_i_3__0_n_0\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      O => \i[1]_i_1__8_n_0\
    );
\i[2]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2888"
    )
        port map (
      I0 => \i[13]_i_3__0_n_0\,
      I1 => \i_reg_n_0_[2]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \i_reg_n_0_[0]\,
      O => \i[2]_i_1__5_n_0\
    );
\i[3]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \i[13]_i_3__0_n_0\,
      I1 => \i_reg_n_0_[3]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[2]\,
      O => \i[3]_i_1__5_n_0\
    );
\i[4]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \i[13]_i_3__0_n_0\,
      I1 => \i_reg_n_0_[4]\,
      I2 => \i_reg_n_0_[2]\,
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[0]\,
      I5 => \i_reg_n_0_[3]\,
      O => \i[4]_i_1__5_n_0\
    );
\i[5]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \i[13]_i_3__0_n_0\,
      I1 => \i[5]_i_2__3_n_0\,
      O => \i[5]_i_1__4_n_0\
    );
\i[5]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555555"
    )
        port map (
      I0 => \i_reg_n_0_[5]\,
      I1 => \i_reg_n_0_[2]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[3]\,
      I5 => \i_reg_n_0_[4]\,
      O => \i[5]_i_2__3_n_0\
    );
\i[6]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \i[13]_i_3__0_n_0\,
      I1 => \i_reg_n_0_[6]\,
      I2 => \i[9]_i_2__2_n_0\,
      O => \i[6]_i_1__3_n_0\
    );
\i[7]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8288"
    )
        port map (
      I0 => \i[13]_i_3__0_n_0\,
      I1 => \i_reg_n_0_[7]\,
      I2 => \i[9]_i_2__2_n_0\,
      I3 => \i_reg_n_0_[6]\,
      O => \i[7]_i_1__3_n_0\
    );
\i[8]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88288888"
    )
        port map (
      I0 => \i[13]_i_3__0_n_0\,
      I1 => \i_reg_n_0_[8]\,
      I2 => \i_reg_n_0_[6]\,
      I3 => \i[9]_i_2__2_n_0\,
      I4 => \i_reg_n_0_[7]\,
      O => \i[8]_i_1__3_n_0\
    );
\i[9]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888288888888888"
    )
        port map (
      I0 => \i[13]_i_3__0_n_0\,
      I1 => \i_reg_n_0_[9]\,
      I2 => \i_reg_n_0_[8]\,
      I3 => \i_reg_n_0_[7]\,
      I4 => \i[9]_i_2__2_n_0\,
      I5 => \i_reg_n_0_[6]\,
      O => \i[9]_i_1__2_n_0\
    );
\i[9]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \i_reg_n_0_[5]\,
      I1 => \i_reg_n_0_[2]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[3]\,
      I5 => \i_reg_n_0_[4]\,
      O => \i[9]_i_2__2_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => tkclk_sig_reg_0(0),
      D => \i[0]_i_1__9_n_0\,
      Q => \i_reg_n_0_[0]\
    );
\i_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => tkclk_sig_reg_0(0),
      D => \i[10]_i_1__1_n_0\,
      Q => \i_reg_n_0_[10]\
    );
\i_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => tkclk_sig_reg_0(0),
      D => \i[11]_i_1__0_n_0\,
      Q => \i_reg_n_0_[11]\
    );
\i_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => tkclk_sig_reg_0(0),
      D => \i[12]_i_1__0_n_0\,
      Q => \i_reg_n_0_[12]\
    );
\i_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => tkclk_sig_reg_0(0),
      D => \i[13]_i_2__0_n_0\,
      Q => \i_reg_n_0_[13]\
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => tkclk_sig_reg_0(0),
      D => \i[1]_i_1__8_n_0\,
      Q => \i_reg_n_0_[1]\
    );
\i_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => tkclk_sig_reg_0(0),
      D => \i[2]_i_1__5_n_0\,
      Q => \i_reg_n_0_[2]\
    );
\i_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => tkclk_sig_reg_0(0),
      D => \i[3]_i_1__5_n_0\,
      Q => \i_reg_n_0_[3]\
    );
\i_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => tkclk_sig_reg_0(0),
      D => \i[4]_i_1__5_n_0\,
      Q => \i_reg_n_0_[4]\
    );
\i_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => tkclk_sig_reg_0(0),
      D => \i[5]_i_1__4_n_0\,
      Q => \i_reg_n_0_[5]\
    );
\i_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => tkclk_sig_reg_0(0),
      D => \i[6]_i_1__3_n_0\,
      Q => \i_reg_n_0_[6]\
    );
\i_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => tkclk_sig_reg_0(0),
      D => \i[7]_i_1__3_n_0\,
      Q => \i_reg_n_0_[7]\
    );
\i_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => tkclk_sig_reg_0(0),
      D => \i[8]_i_1__3_n_0\,
      Q => \i_reg_n_0_[8]\
    );
\i_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => tkclk_sig_reg_0(0),
      D => \i[9]_i_1__2_n_0\,
      Q => \i_reg_n_0_[9]\
    );
plusOp_carry: unisim.vcomponents.CARRY8
     port map (
      CI => \^q\(0),
      CI_TOP => '0',
      CO(7) => plusOp_carry_n_0,
      CO(6) => plusOp_carry_n_1,
      CO(5) => plusOp_carry_n_2,
      CO(4) => plusOp_carry_n_3,
      CO(3) => plusOp_carry_n_4,
      CO(2) => plusOp_carry_n_5,
      CO(1) => plusOp_carry_n_6,
      CO(0) => plusOp_carry_n_7,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \plusOp__60\(8 downto 1),
      S(7 downto 0) => \^q\(8 downto 1)
    );
\plusOp_carry__0\: unisim.vcomponents.CARRY8
     port map (
      CI => plusOp_carry_n_0,
      CI_TOP => '0',
      CO(7) => \plusOp_carry__0_n_0\,
      CO(6) => \plusOp_carry__0_n_1\,
      CO(5) => \plusOp_carry__0_n_2\,
      CO(4) => \plusOp_carry__0_n_3\,
      CO(3) => \plusOp_carry__0_n_4\,
      CO(2) => \plusOp_carry__0_n_5\,
      CO(1) => \plusOp_carry__0_n_6\,
      CO(0) => \plusOp_carry__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \plusOp__60\(16 downto 9),
      S(7 downto 0) => \^q\(16 downto 9)
    );
\plusOp_carry__1\: unisim.vcomponents.CARRY8
     port map (
      CI => \plusOp_carry__0_n_0\,
      CI_TOP => '0',
      CO(7) => \plusOp_carry__1_n_0\,
      CO(6) => \plusOp_carry__1_n_1\,
      CO(5) => \plusOp_carry__1_n_2\,
      CO(4) => \plusOp_carry__1_n_3\,
      CO(3) => \plusOp_carry__1_n_4\,
      CO(2) => \plusOp_carry__1_n_5\,
      CO(1) => \plusOp_carry__1_n_6\,
      CO(0) => \plusOp_carry__1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \plusOp__60\(24 downto 17),
      S(7 downto 0) => \^q\(24 downto 17)
    );
\plusOp_carry__2\: unisim.vcomponents.CARRY8
     port map (
      CI => \plusOp_carry__1_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_plusOp_carry__2_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \plusOp_carry__2_n_2\,
      CO(4) => \plusOp_carry__2_n_3\,
      CO(3) => \plusOp_carry__2_n_4\,
      CO(2) => \plusOp_carry__2_n_5\,
      CO(1) => \plusOp_carry__2_n_6\,
      CO(0) => \plusOp_carry__2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NLW_plusOp_carry__2_O_UNCONNECTED\(7),
      O(6 downto 0) => \plusOp__60\(31 downto 25),
      S(7) => '0',
      S(6 downto 0) => \^q\(31 downto 25)
    );
\stateOp[0]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \stateOp_reg_n_0_[0]\,
      I1 => \stateOp_reg_n_0_[1]\,
      I2 => reqInvTkclksrcSetTkst,
      O => \stateOp[0]_i_1__3_n_0\
    );
\stateOp[5]_i_67\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateOp_reg_n_0_[0]\,
      I1 => \stateOp_reg_n_0_[1]\,
      O => ackInvTkclksrcSetTkst
    );
\stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => tkclk_sig_reg_0(0),
      D => \stateOp[0]_i_1__3_n_0\,
      Q => \stateOp_reg_n_0_[0]\
    );
\stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => tkclk_sig_reg_0(0),
      D => \stateOp_reg[1]_0\,
      Q => \stateOp_reg_n_0_[1]\
    );
tkclk_sig_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0CDC0020"
    )
        port map (
      I0 => \tkst[31]_i_3_n_0\,
      I1 => \stateOp_reg_n_0_[0]\,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => reqInvTkclksrcSetTkst,
      I4 => \^tkclk\,
      O => tkclk_sig_i_1_n_0
    );
tkclk_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => tkclk_sig_reg_0(0),
      D => tkclk_sig_i_1_n_0,
      Q => \^tkclk\
    );
\tkst[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"808ABFBA"
    )
        port map (
      I0 => D(0),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \^q\(0),
      O => p_1_in(0)
    );
\tkst[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(10),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(10),
      O => p_1_in(10)
    );
\tkst[11]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(11),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(11),
      O => p_1_in(11)
    );
\tkst[12]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(12),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(12),
      O => p_1_in(12)
    );
\tkst[13]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(13),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(13),
      O => p_1_in(13)
    );
\tkst[14]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(14),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(14),
      O => p_1_in(14)
    );
\tkst[15]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(15),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(15),
      O => p_1_in(15)
    );
\tkst[16]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(16),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(16),
      O => p_1_in(16)
    );
\tkst[17]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(17),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(17),
      O => p_1_in(17)
    );
\tkst[18]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(18),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(18),
      O => p_1_in(18)
    );
\tkst[19]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(19),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(19),
      O => p_1_in(19)
    );
\tkst[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(1),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(1),
      O => p_1_in(1)
    );
\tkst[20]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(20),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(20),
      O => p_1_in(20)
    );
\tkst[21]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(21),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(21),
      O => p_1_in(21)
    );
\tkst[22]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(22),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(22),
      O => p_1_in(22)
    );
\tkst[23]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(23),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(23),
      O => p_1_in(23)
    );
\tkst[24]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => \tkst_reg[31]_0\(0),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(24),
      O => p_1_in(24)
    );
\tkst[25]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => \tkst_reg[31]_0\(1),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(25),
      O => p_1_in(25)
    );
\tkst[26]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => \tkst_reg[31]_0\(2),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(26),
      O => p_1_in(26)
    );
\tkst[27]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => \tkst_reg[31]_0\(3),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(27),
      O => p_1_in(27)
    );
\tkst[28]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => \tkst_reg[31]_0\(4),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(28),
      O => p_1_in(28)
    );
\tkst[29]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => \tkst_reg[31]_0\(5),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(29),
      O => p_1_in(29)
    );
\tkst[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(2),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(2),
      O => p_1_in(2)
    );
\tkst[30]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => \tkst_reg[31]_0\(6),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(30),
      O => p_1_in(30)
    );
\tkst[31]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F000F8F0"
    )
        port map (
      I0 => \tkst[31]_i_3_n_0\,
      I1 => \^tkclk\,
      I2 => reqInvTkclksrcSetTkst,
      I3 => \stateOp_reg_n_0_[1]\,
      I4 => \stateOp_reg_n_0_[0]\,
      O => \tkst[31]_i_1__1_n_0\
    );
\tkst[31]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => \tkst_reg[31]_0\(7),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(31),
      O => p_1_in(31)
    );
\tkst[31]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008000008"
    )
        port map (
      I0 => \tkst[31]_i_4_n_0\,
      I1 => \i_reg_n_0_[13]\,
      I2 => \i_reg_n_0_[11]\,
      I3 => \tkst[31]_i_5_n_0\,
      I4 => \i_reg_n_0_[10]\,
      I5 => \i_reg_n_0_[12]\,
      O => \tkst[31]_i_3_n_0\
    );
\tkst[31]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000800000"
    )
        port map (
      I0 => \tkst[31]_i_6_n_0\,
      I1 => \i_reg_n_0_[9]\,
      I2 => \i_reg_n_0_[8]\,
      I3 => \i_reg_n_0_[7]\,
      I4 => \i[9]_i_2__2_n_0\,
      I5 => \i_reg_n_0_[6]\,
      O => \tkst[31]_i_4_n_0\
    );
\tkst[31]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7FFFFFF"
    )
        port map (
      I0 => \i_reg_n_0_[9]\,
      I1 => \i_reg_n_0_[6]\,
      I2 => \i[9]_i_2__2_n_0\,
      I3 => \i_reg_n_0_[7]\,
      I4 => \i_reg_n_0_[8]\,
      O => \tkst[31]_i_5_n_0\
    );
\tkst[31]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040000000"
    )
        port map (
      I0 => \i_reg_n_0_[4]\,
      I1 => \i_reg_n_0_[3]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[2]\,
      I5 => \i_reg_n_0_[5]\,
      O => \tkst[31]_i_6_n_0\
    );
\tkst[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(3),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(3),
      O => p_1_in(3)
    );
\tkst[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(4),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(4),
      O => p_1_in(4)
    );
\tkst[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(5),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(5),
      O => p_1_in(5)
    );
\tkst[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(6),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(6),
      O => p_1_in(6)
    );
\tkst[7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(7),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(7),
      O => p_1_in(7)
    );
\tkst[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(8),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(8),
      O => p_1_in(8)
    );
\tkst[9]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBA808A"
    )
        port map (
      I0 => D(9),
      I1 => reqInvTkclksrcSetTkst,
      I2 => \stateOp_reg_n_0_[1]\,
      I3 => \stateOp_reg_n_0_[0]\,
      I4 => \plusOp__60\(9),
      O => p_1_in(9)
    );
\tkst_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(0),
      Q => \^q\(0)
    );
\tkst_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(10),
      Q => \^q\(10)
    );
\tkst_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(11),
      Q => \^q\(11)
    );
\tkst_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(12),
      Q => \^q\(12)
    );
\tkst_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(13),
      Q => \^q\(13)
    );
\tkst_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(14),
      Q => \^q\(14)
    );
\tkst_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(15),
      Q => \^q\(15)
    );
\tkst_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(16),
      Q => \^q\(16)
    );
\tkst_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(17),
      Q => \^q\(17)
    );
\tkst_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(18),
      Q => \^q\(18)
    );
\tkst_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(19),
      Q => \^q\(19)
    );
\tkst_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(1),
      Q => \^q\(1)
    );
\tkst_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(20),
      Q => \^q\(20)
    );
\tkst_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(21),
      Q => \^q\(21)
    );
\tkst_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(22),
      Q => \^q\(22)
    );
\tkst_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(23),
      Q => \^q\(23)
    );
\tkst_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(24),
      Q => \^q\(24)
    );
\tkst_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(25),
      Q => \^q\(25)
    );
\tkst_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(26),
      Q => \^q\(26)
    );
\tkst_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(27),
      Q => \^q\(27)
    );
\tkst_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(28),
      Q => \^q\(28)
    );
\tkst_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(29),
      Q => \^q\(29)
    );
\tkst_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(2),
      Q => \^q\(2)
    );
\tkst_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(30),
      Q => \^q\(30)
    );
\tkst_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(31),
      Q => \^q\(31)
    );
\tkst_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(3),
      Q => \^q\(3)
    );
\tkst_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(4),
      Q => \^q\(4)
    );
\tkst_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(5),
      Q => \^q\(5)
    );
\tkst_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(6),
      Q => \^q\(6)
    );
\tkst_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(7),
      Q => \^q\(7)
    );
\tkst_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(8),
      Q => \^q\(8)
    );
\tkst_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tkst[31]_i_1__1_n_0\,
      CLR => tkclk_sig_reg_0(0),
      D => p_1_in(9),
      Q => \^q\(9)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_addr_arbiter_sasd is
  port (
    m_valid_i : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    aa_grant_rnw : out STD_LOGIC;
    aresetn_d_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_ready_d0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_no_arbiter.grant_rnw_reg_0\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_no_arbiter.grant_rnw_reg_1\ : out STD_LOGIC;
    aresetn_d_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_no_arbiter.m_amesg_i_reg[13]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
    aclk : in STD_LOGIC;
    aresetn_d : in STD_LOGIC;
    s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \m_ready_d_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_atarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
    \m_ready_d_reg[0]\ : in STD_LOGIC;
    s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    sr_rvalid : in STD_LOGIC;
    \m_ready_d_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \m_ready_d_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_addr_arbiter_sasd : entity is "axi_crossbar_v2_1_34_addr_arbiter_sasd";
end design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_addr_arbiter_sasd;

architecture STRUCTURE of design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_addr_arbiter_sasd is
  signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^aa_grant_rnw\ : STD_LOGIC;
  signal \gen_no_arbiter.grant_rnw_i_1_n_0\ : STD_LOGIC;
  signal \^gen_no_arbiter.grant_rnw_reg_0\ : STD_LOGIC;
  signal \^gen_no_arbiter.grant_rnw_reg_1\ : STD_LOGIC;
  signal \^gen_no_arbiter.m_amesg_i_reg[13]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0\ : STD_LOGIC;
  signal \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0\ : STD_LOGIC;
  signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
  signal \gen_no_arbiter.s_ready_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \^m_ready_d0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \m_ready_d[1]_i_3_n_0\ : STD_LOGIC;
  signal \m_ready_d[2]_i_3_n_0\ : STD_LOGIC;
  signal \m_ready_d[2]_i_4_n_0\ : STD_LOGIC;
  signal \^m_valid_i\ : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC;
  signal p_0_in6_out : STD_LOGIC;
  signal s_amesg : STD_LOGIC_VECTOR ( 13 downto 3 );
  signal s_arvalid_reg : STD_LOGIC;
  signal \s_arvalid_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal s_awvalid_reg : STD_LOGIC;
  signal s_awvalid_reg0 : STD_LOGIC;
  signal s_ready_i : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3\ : label is "soft_lutpair553";
  attribute inverted : string;
  attribute inverted of \gen_no_arbiter.m_grant_hot_i_reg[0]_inv\ : label is "yes";
  attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair553";
  attribute SOFT_HLUTNM of \m_atarget_hot[1]_i_1\ : label is "soft_lutpair560";
  attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair556";
  attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair557";
  attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair556";
  attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair557";
  attribute SOFT_HLUTNM of \m_axi_bready[0]_INST_0\ : label is "soft_lutpair555";
  attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair554";
  attribute SOFT_HLUTNM of m_valid_i_i_2 : label is "soft_lutpair554";
  attribute SOFT_HLUTNM of \s_arvalid_reg[0]_i_2\ : label is "soft_lutpair558";
  attribute SOFT_HLUTNM of \s_awvalid_reg[0]_i_1\ : label is "soft_lutpair558";
  attribute SOFT_HLUTNM of \s_axi_arready[0]_INST_0\ : label is "soft_lutpair559";
  attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair559";
  attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0\ : label is "soft_lutpair560";
  attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_1\ : label is "soft_lutpair555";
begin
  SR(0) <= \^sr\(0);
  aa_grant_rnw <= \^aa_grant_rnw\;
  \gen_no_arbiter.grant_rnw_reg_0\ <= \^gen_no_arbiter.grant_rnw_reg_0\;
  \gen_no_arbiter.grant_rnw_reg_1\ <= \^gen_no_arbiter.grant_rnw_reg_1\;
  \gen_no_arbiter.m_amesg_i_reg[13]_0\(6 downto 0) <= \^gen_no_arbiter.m_amesg_i_reg[13]_0\(6 downto 0);
  m_ready_d0(1 downto 0) <= \^m_ready_d0\(1 downto 0);
  m_valid_i <= \^m_valid_i\;
\gen_no_arbiter.grant_rnw_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF53FF00005000"
    )
        port map (
      I0 => s_awvalid_reg,
      I1 => s_axi_awvalid(0),
      I2 => s_axi_arvalid(0),
      I3 => p_0_in1_in,
      I4 => \^m_valid_i\,
      I5 => \^aa_grant_rnw\,
      O => \gen_no_arbiter.grant_rnw_i_1_n_0\
    );
\gen_no_arbiter.grant_rnw_reg\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => \gen_no_arbiter.grant_rnw_i_1_n_0\,
      Q => \^aa_grant_rnw\,
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(6),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(6),
      O => s_amesg(13)
    );
\gen_no_arbiter.m_amesg_i[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(0),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(0),
      O => s_amesg(3)
    );
\gen_no_arbiter.m_amesg_i[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(1),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(1),
      O => s_amesg(4)
    );
\gen_no_arbiter.m_amesg_i[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(2),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(2),
      O => s_amesg(5)
    );
\gen_no_arbiter.m_amesg_i[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(3),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(3),
      O => s_amesg(6)
    );
\gen_no_arbiter.m_amesg_i[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => aresetn_d,
      O => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(4),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(4),
      O => s_amesg(7)
    );
\gen_no_arbiter.m_amesg_i[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => s_axi_araddr(5),
      I1 => s_axi_arvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_awaddr(5),
      O => s_amesg(8)
    );
\gen_no_arbiter.m_amesg_i_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => p_0_in1_in,
      D => s_amesg(13),
      Q => \^gen_no_arbiter.m_amesg_i_reg[13]_0\(6),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => p_0_in1_in,
      D => s_amesg(3),
      Q => \^gen_no_arbiter.m_amesg_i_reg[13]_0\(0),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => p_0_in1_in,
      D => s_amesg(4),
      Q => \^gen_no_arbiter.m_amesg_i_reg[13]_0\(1),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => p_0_in1_in,
      D => s_amesg(5),
      Q => \^gen_no_arbiter.m_amesg_i_reg[13]_0\(2),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => p_0_in1_in,
      D => s_amesg(6),
      Q => \^gen_no_arbiter.m_amesg_i_reg[13]_0\(3),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => p_0_in1_in,
      D => s_amesg(7),
      Q => \^gen_no_arbiter.m_amesg_i_reg[13]_0\(4),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_amesg_i_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => p_0_in1_in,
      D => s_amesg(8),
      Q => \^gen_no_arbiter.m_amesg_i_reg[13]_0\(5),
      R => \^sr\(0)
    );
\gen_no_arbiter.m_grant_hot_i[0]_inv_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80808C80"
    )
        port map (
      I0 => \m_ready_d[1]_i_3_n_0\,
      I1 => \^m_valid_i\,
      I2 => \^aa_grant_rnw\,
      I3 => \^m_ready_d0\(0),
      I4 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0\,
      I5 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0\,
      O => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0\
    );
\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF0D"
    )
        port map (
      I0 => s_axi_bready(0),
      I1 => \m_ready_d[2]_i_3_n_0\,
      I2 => \m_ready_d_reg[2]\(0),
      I3 => \m_ready_d[2]_i_4_n_0\,
      O => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0\
    );
\gen_no_arbiter.m_grant_hot_i[0]_inv_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D5D5D5F5"
    )
        port map (
      I0 => aresetn_d,
      I1 => \^m_valid_i\,
      I2 => p_0_in1_in,
      I3 => s_axi_arvalid(0),
      I4 => s_axi_awvalid(0),
      O => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0\
    );
\gen_no_arbiter.m_grant_hot_i_reg[0]_inv\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0\,
      Q => p_0_in1_in,
      R => '0'
    );
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"35F535F5350535F5"
    )
        port map (
      I0 => p_0_in1_in,
      I1 => \m_ready_d[1]_i_3_n_0\,
      I2 => \^m_valid_i\,
      I3 => \^aa_grant_rnw\,
      I4 => \^m_ready_d0\(0),
      I5 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0\,
      O => \gen_no_arbiter.m_valid_i_i_1_n_0\
    );
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
      Q => \^m_valid_i\,
      R => \^sr\(0)
    );
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^m_valid_i\,
      I1 => p_0_in1_in,
      I2 => aresetn_d,
      O => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\
    );
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\,
      Q => s_ready_i,
      R => '0'
    );
\m_atarget_hot[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in1_in,
      I1 => \^gen_no_arbiter.m_amesg_i_reg[13]_0\(6),
      O => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\(0)
    );
\m_atarget_hot[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => p_0_in1_in,
      I1 => \^gen_no_arbiter.m_amesg_i_reg[13]_0\(6),
      O => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\(1)
    );
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => Q(0),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      I3 => \m_ready_d_reg[1]\(1),
      O => m_axi_arvalid(0)
    );
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => Q(1),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      I3 => \m_ready_d_reg[1]\(1),
      O => m_axi_arvalid(1)
    );
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => Q(0),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      I3 => \m_ready_d_reg[2]\(2),
      O => m_axi_awvalid(0)
    );
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => Q(1),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      I3 => \m_ready_d_reg[2]\(2),
      O => m_axi_awvalid(1)
    );
\m_axi_bready[0]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200000"
    )
        port map (
      I0 => Q(0),
      I1 => \m_ready_d_reg[2]\(0),
      I2 => \^m_valid_i\,
      I3 => \^aa_grant_rnw\,
      I4 => s_axi_bready(0),
      O => m_axi_bready(0)
    );
\m_axi_bready[1]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200000"
    )
        port map (
      I0 => Q(1),
      I1 => \m_ready_d_reg[2]\(0),
      I2 => \^m_valid_i\,
      I3 => \^aa_grant_rnw\,
      I4 => s_axi_bready(0),
      O => m_axi_bready(1)
    );
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => Q(0),
      I1 => s_axi_wvalid(0),
      I2 => \m_ready_d_reg[2]\(1),
      I3 => \^m_valid_i\,
      I4 => \^aa_grant_rnw\,
      O => m_axi_wvalid(0)
    );
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => Q(1),
      I1 => s_axi_wvalid(0),
      I2 => \m_ready_d_reg[2]\(1),
      I3 => \^m_valid_i\,
      I4 => \^aa_grant_rnw\,
      O => m_axi_wvalid(1)
    );
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0080FFFF"
    )
        port map (
      I0 => s_axi_rready(0),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      I3 => \m_ready_d_reg[1]\(0),
      I4 => sr_rvalid,
      O => E(0)
    );
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \m_ready_d_reg[1]\(0),
      I1 => \^m_valid_i\,
      I2 => \^aa_grant_rnw\,
      I3 => s_axi_rready(0),
      I4 => \m_ready_d_reg[0]_0\(0),
      I5 => sr_rvalid,
      O => D(0)
    );
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DCCCDCDCDCCCCCCC"
    )
        port map (
      I0 => \^gen_no_arbiter.grant_rnw_reg_1\,
      I1 => \m_ready_d_reg[2]\(1),
      I2 => s_axi_wvalid(0),
      I3 => m_axi_wready(1),
      I4 => m_atarget_enc(0),
      I5 => m_axi_wready(0),
      O => \^m_ready_d0\(0)
    );
\m_ready_d[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \m_ready_d[1]_i_3_n_0\,
      I1 => aresetn_d,
      O => aresetn_d_reg(0)
    );
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAEAEAEAAAAAAA"
    )
        port map (
      I0 => \m_ready_d_reg[1]\(1),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      I3 => m_axi_arready(1),
      I4 => m_atarget_enc(0),
      I5 => m_axi_arready(0),
      O => D(1)
    );
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF00E2"
    )
        port map (
      I0 => m_axi_arready(0),
      I1 => m_atarget_enc(0),
      I2 => m_axi_arready(1),
      I3 => \^gen_no_arbiter.grant_rnw_reg_0\,
      I4 => \m_ready_d_reg[1]\(1),
      I5 => \m_ready_d_reg[0]\,
      O => \m_ready_d[1]_i_3_n_0\
    );
\m_ready_d[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555555DDDD55D5"
    )
        port map (
      I0 => aresetn_d,
      I1 => \^m_ready_d0\(0),
      I2 => s_axi_bready(0),
      I3 => \m_ready_d[2]_i_3_n_0\,
      I4 => \m_ready_d_reg[2]\(0),
      I5 => \m_ready_d[2]_i_4_n_0\,
      O => aresetn_d_reg_0(0)
    );
\m_ready_d[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000E200"
    )
        port map (
      I0 => m_axi_awready(0),
      I1 => m_atarget_enc(0),
      I2 => m_axi_awready(1),
      I3 => \^m_valid_i\,
      I4 => \^aa_grant_rnw\,
      I5 => \m_ready_d_reg[2]\(2),
      O => \^m_ready_d0\(1)
    );
\m_ready_d[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFBFBFFFFFFFBFF"
    )
        port map (
      I0 => \^aa_grant_rnw\,
      I1 => \^m_valid_i\,
      I2 => \m_ready_d_reg[2]\(0),
      I3 => m_axi_bvalid(0),
      I4 => m_atarget_enc(0),
      I5 => m_axi_bvalid(1),
      O => \m_ready_d[2]_i_3_n_0\
    );
\m_ready_d[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4555454545555555"
    )
        port map (
      I0 => \m_ready_d_reg[2]\(2),
      I1 => \^aa_grant_rnw\,
      I2 => \^m_valid_i\,
      I3 => m_axi_awready(1),
      I4 => m_atarget_enc(0),
      I5 => m_axi_awready(0),
      O => \m_ready_d[2]_i_4_n_0\
    );
m_valid_i_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^aa_grant_rnw\,
      I1 => \^m_valid_i\,
      O => \^gen_no_arbiter.grant_rnw_reg_0\
    );
\s_arvalid_reg[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => s_ready_i,
      I1 => aresetn_d,
      O => s_arvalid_reg
    );
\s_arvalid_reg[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => s_axi_arvalid(0),
      I1 => s_awvalid_reg,
      O => p_0_in6_out
    );
\s_arvalid_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => p_0_in6_out,
      Q => \s_arvalid_reg_reg_n_0_[0]\,
      R => s_arvalid_reg
    );
\s_awvalid_reg[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4044"
    )
        port map (
      I0 => \s_arvalid_reg_reg_n_0_[0]\,
      I1 => s_axi_awvalid(0),
      I2 => s_awvalid_reg,
      I3 => s_axi_arvalid(0),
      O => s_awvalid_reg0
    );
\s_awvalid_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => s_awvalid_reg0,
      Q => s_awvalid_reg,
      R => s_arvalid_reg
    );
\s_axi_arready[0]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^aa_grant_rnw\,
      I1 => s_ready_i,
      O => s_axi_arready(0)
    );
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => s_ready_i,
      I1 => \^aa_grant_rnw\,
      O => s_axi_awready(0)
    );
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000004540"
    )
        port map (
      I0 => p_0_in1_in,
      I1 => m_axi_bvalid(1),
      I2 => m_atarget_enc(0),
      I3 => m_axi_bvalid(0),
      I4 => \m_ready_d_reg[2]\(0),
      I5 => \^gen_no_arbiter.grant_rnw_reg_1\,
      O => s_axi_bvalid(0)
    );
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => p_0_in1_in,
      I1 => sr_rvalid,
      O => s_axi_rvalid(0)
    );
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000004540"
    )
        port map (
      I0 => p_0_in1_in,
      I1 => m_axi_wready(1),
      I2 => m_atarget_enc(0),
      I3 => m_axi_wready(0),
      I4 => \^gen_no_arbiter.grant_rnw_reg_1\,
      I5 => \m_ready_d_reg[2]\(1),
      O => s_axi_wready(0)
    );
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^aa_grant_rnw\,
      I1 => \^m_valid_i\,
      O => \^gen_no_arbiter.grant_rnw_reg_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_splitter is
  port (
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_atarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
    \m_ready_d_reg[0]_0\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    aclk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_splitter : entity is "axi_crossbar_v2_1_34_splitter";
end design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_splitter;

architecture STRUCTURE of design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_splitter is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal m_ready_d0 : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
\m_ready_d[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000FFFF8A80"
    )
        port map (
      I0 => s_axi_bready(0),
      I1 => m_axi_bvalid(1),
      I2 => m_atarget_enc(0),
      I3 => m_axi_bvalid(0),
      I4 => \^q\(0),
      I5 => \m_ready_d_reg[0]_0\,
      O => m_ready_d0(0)
    );
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => m_ready_d0(0),
      Q => \^q\(0),
      R => SR(0)
    );
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => D(0),
      Q => \^q\(1),
      R => SR(0)
    );
\m_ready_d_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => D(1),
      Q => \^q\(2),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_splitter__parameterized0\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    aclk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_splitter__parameterized0\ : entity is "axi_crossbar_v2_1_34_splitter";
end \design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_splitter__parameterized0\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_splitter__parameterized0\ is
begin
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => D(0),
      Q => Q(0),
      R => SR(0)
    );
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => D(1),
      Q => Q(1),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_axi_register_slice_v2_1_33_axic_register_slice is
  port (
    sr_rvalid : out STD_LOGIC;
    m_valid_i_reg_0 : out STD_LOGIC;
    \m_payload_i_reg[34]_0\ : out STD_LOGIC_VECTOR ( 32 downto 0 );
    m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 );
    aclk : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_ready_i_reg_0 : in STD_LOGIC;
    s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_atarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
    aa_grant_rnw : in STD_LOGIC;
    m_valid_i : in STD_LOGIC;
    rd_req_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_axi_register_slice_v2_1_33_axic_register_slice : entity is "axi_register_slice_v2_1_33_axic_register_slice";
end design_1_Vsp_core_0_0_axi_register_slice_v2_1_33_axic_register_slice;

architecture STRUCTURE of design_1_Vsp_core_0_0_axi_register_slice_v2_1_33_axic_register_slice is
  signal aa_rready : STD_LOGIC;
  signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
  signal \aresetn_d_reg_n_0_[1]\ : STD_LOGIC;
  signal \^m_payload_i_reg[34]_0\ : STD_LOGIC_VECTOR ( 32 downto 0 );
  signal m_valid_i_i_1_n_0 : STD_LOGIC;
  signal m_valid_i_i_3_n_0 : STD_LOGIC;
  signal s_ready_i_i_1_n_0 : STD_LOGIC;
  signal skid_buffer : STD_LOGIC_VECTOR ( 34 downto 0 );
  signal \skid_buffer[10]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[11]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[12]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[13]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[14]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[15]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[16]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[17]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[18]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[19]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[20]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[21]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[22]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[23]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[24]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[25]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[26]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[27]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[28]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[29]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[30]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[31]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[32]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[33]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[34]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[3]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[4]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[5]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[6]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[7]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[8]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer[9]_i_1_n_0\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
  signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
  signal \^sr_rvalid\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \m_axi_rready[0]_INST_0\ : label is "soft_lutpair593";
  attribute SOFT_HLUTNM of \m_axi_rready[1]_INST_0\ : label is "soft_lutpair593";
  attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair585";
  attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair584";
  attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair583";
  attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair582";
  attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair581";
  attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair580";
  attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair579";
  attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair578";
  attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair577";
  attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair576";
  attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair575";
  attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair574";
  attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair573";
  attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair572";
  attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair571";
  attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair570";
  attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair569";
  attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair568";
  attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair567";
  attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair566";
  attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair565";
  attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair564";
  attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair563";
  attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair562";
  attribute SOFT_HLUTNM of \m_payload_i[34]_i_2\ : label is "soft_lutpair561";
  attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair592";
  attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair591";
  attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair590";
  attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair589";
  attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair588";
  attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair587";
  attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair586";
  attribute SOFT_HLUTNM of \skid_buffer[10]_i_1\ : label is "soft_lutpair585";
  attribute SOFT_HLUTNM of \skid_buffer[11]_i_1\ : label is "soft_lutpair584";
  attribute SOFT_HLUTNM of \skid_buffer[12]_i_1\ : label is "soft_lutpair583";
  attribute SOFT_HLUTNM of \skid_buffer[13]_i_1\ : label is "soft_lutpair582";
  attribute SOFT_HLUTNM of \skid_buffer[14]_i_1\ : label is "soft_lutpair581";
  attribute SOFT_HLUTNM of \skid_buffer[15]_i_1\ : label is "soft_lutpair580";
  attribute SOFT_HLUTNM of \skid_buffer[16]_i_1\ : label is "soft_lutpair579";
  attribute SOFT_HLUTNM of \skid_buffer[17]_i_1\ : label is "soft_lutpair578";
  attribute SOFT_HLUTNM of \skid_buffer[18]_i_1\ : label is "soft_lutpair577";
  attribute SOFT_HLUTNM of \skid_buffer[19]_i_1\ : label is "soft_lutpair576";
  attribute SOFT_HLUTNM of \skid_buffer[20]_i_1\ : label is "soft_lutpair575";
  attribute SOFT_HLUTNM of \skid_buffer[21]_i_1\ : label is "soft_lutpair574";
  attribute SOFT_HLUTNM of \skid_buffer[22]_i_1\ : label is "soft_lutpair573";
  attribute SOFT_HLUTNM of \skid_buffer[23]_i_1\ : label is "soft_lutpair572";
  attribute SOFT_HLUTNM of \skid_buffer[24]_i_1\ : label is "soft_lutpair571";
  attribute SOFT_HLUTNM of \skid_buffer[25]_i_1\ : label is "soft_lutpair570";
  attribute SOFT_HLUTNM of \skid_buffer[26]_i_1\ : label is "soft_lutpair569";
  attribute SOFT_HLUTNM of \skid_buffer[27]_i_1\ : label is "soft_lutpair568";
  attribute SOFT_HLUTNM of \skid_buffer[28]_i_1\ : label is "soft_lutpair567";
  attribute SOFT_HLUTNM of \skid_buffer[29]_i_1\ : label is "soft_lutpair566";
  attribute SOFT_HLUTNM of \skid_buffer[30]_i_1\ : label is "soft_lutpair565";
  attribute SOFT_HLUTNM of \skid_buffer[31]_i_1\ : label is "soft_lutpair564";
  attribute SOFT_HLUTNM of \skid_buffer[32]_i_1\ : label is "soft_lutpair563";
  attribute SOFT_HLUTNM of \skid_buffer[33]_i_1\ : label is "soft_lutpair562";
  attribute SOFT_HLUTNM of \skid_buffer[34]_i_1\ : label is "soft_lutpair561";
  attribute SOFT_HLUTNM of \skid_buffer[3]_i_1\ : label is "soft_lutpair592";
  attribute SOFT_HLUTNM of \skid_buffer[4]_i_1\ : label is "soft_lutpair591";
  attribute SOFT_HLUTNM of \skid_buffer[5]_i_1\ : label is "soft_lutpair590";
  attribute SOFT_HLUTNM of \skid_buffer[6]_i_1\ : label is "soft_lutpair589";
  attribute SOFT_HLUTNM of \skid_buffer[7]_i_1\ : label is "soft_lutpair588";
  attribute SOFT_HLUTNM of \skid_buffer[8]_i_1\ : label is "soft_lutpair587";
  attribute SOFT_HLUTNM of \skid_buffer[9]_i_1\ : label is "soft_lutpair586";
begin
  \m_payload_i_reg[34]_0\(32 downto 0) <= \^m_payload_i_reg[34]_0\(32 downto 0);
  sr_rvalid <= \^sr_rvalid\;
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => '1',
      Q => \aresetn_d_reg_n_0_[0]\,
      R => SR(0)
    );
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \aresetn_d_reg_n_0_[0]\,
      Q => \aresetn_d_reg_n_0_[1]\,
      R => SR(0)
    );
\m_axi_rready[0]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => aa_rready,
      I1 => rd_req_reg(0),
      O => m_axi_rready(0)
    );
\m_axi_rready[1]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => aa_rready,
      I1 => rd_req_reg(1),
      O => m_axi_rready(1)
    );
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(39),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(7),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[10]\,
      O => skid_buffer(10)
    );
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(40),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(8),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[11]\,
      O => skid_buffer(11)
    );
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(41),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(9),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[12]\,
      O => skid_buffer(12)
    );
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(42),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(10),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[13]\,
      O => skid_buffer(13)
    );
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(43),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(11),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[14]\,
      O => skid_buffer(14)
    );
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(44),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(12),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[15]\,
      O => skid_buffer(15)
    );
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(45),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(13),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[16]\,
      O => skid_buffer(16)
    );
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(46),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(14),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[17]\,
      O => skid_buffer(17)
    );
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(47),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(15),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[18]\,
      O => skid_buffer(18)
    );
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(48),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(16),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[19]\,
      O => skid_buffer(19)
    );
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(49),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(17),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[20]\,
      O => skid_buffer(20)
    );
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(50),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(18),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[21]\,
      O => skid_buffer(21)
    );
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(51),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(19),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[22]\,
      O => skid_buffer(22)
    );
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(52),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(20),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[23]\,
      O => skid_buffer(23)
    );
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(53),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(21),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[24]\,
      O => skid_buffer(24)
    );
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(54),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(22),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[25]\,
      O => skid_buffer(25)
    );
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(55),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(23),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[26]\,
      O => skid_buffer(26)
    );
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(56),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(24),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[27]\,
      O => skid_buffer(27)
    );
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(57),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(25),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[28]\,
      O => skid_buffer(28)
    );
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(58),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(26),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[29]\,
      O => skid_buffer(29)
    );
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(59),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(27),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[30]\,
      O => skid_buffer(30)
    );
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(60),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(28),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[31]\,
      O => skid_buffer(31)
    );
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(61),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(29),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[32]\,
      O => skid_buffer(32)
    );
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(62),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(30),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[33]\,
      O => skid_buffer(33)
    );
\m_payload_i[34]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(63),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(31),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[34]\,
      O => skid_buffer(34)
    );
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(32),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(0),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[3]\,
      O => skid_buffer(3)
    );
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(33),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(1),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[4]\,
      O => skid_buffer(4)
    );
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(34),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(2),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[5]\,
      O => skid_buffer(5)
    );
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(35),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(3),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[6]\,
      O => skid_buffer(6)
    );
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(36),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(4),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[7]\,
      O => skid_buffer(7)
    );
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(37),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(5),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[8]\,
      O => skid_buffer(8)
    );
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => m_axi_rdata(38),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(6),
      I3 => aa_rready,
      I4 => \skid_buffer_reg_n_0_[9]\,
      O => skid_buffer(9)
    );
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(0),
      Q => \^m_payload_i_reg[34]_0\(0),
      R => '0'
    );
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(10),
      Q => \^m_payload_i_reg[34]_0\(8),
      R => '0'
    );
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(11),
      Q => \^m_payload_i_reg[34]_0\(9),
      R => '0'
    );
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(12),
      Q => \^m_payload_i_reg[34]_0\(10),
      R => '0'
    );
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(13),
      Q => \^m_payload_i_reg[34]_0\(11),
      R => '0'
    );
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(14),
      Q => \^m_payload_i_reg[34]_0\(12),
      R => '0'
    );
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(15),
      Q => \^m_payload_i_reg[34]_0\(13),
      R => '0'
    );
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(16),
      Q => \^m_payload_i_reg[34]_0\(14),
      R => '0'
    );
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(17),
      Q => \^m_payload_i_reg[34]_0\(15),
      R => '0'
    );
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(18),
      Q => \^m_payload_i_reg[34]_0\(16),
      R => '0'
    );
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(19),
      Q => \^m_payload_i_reg[34]_0\(17),
      R => '0'
    );
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(20),
      Q => \^m_payload_i_reg[34]_0\(18),
      R => '0'
    );
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(21),
      Q => \^m_payload_i_reg[34]_0\(19),
      R => '0'
    );
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(22),
      Q => \^m_payload_i_reg[34]_0\(20),
      R => '0'
    );
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(23),
      Q => \^m_payload_i_reg[34]_0\(21),
      R => '0'
    );
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(24),
      Q => \^m_payload_i_reg[34]_0\(22),
      R => '0'
    );
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(25),
      Q => \^m_payload_i_reg[34]_0\(23),
      R => '0'
    );
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(26),
      Q => \^m_payload_i_reg[34]_0\(24),
      R => '0'
    );
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(27),
      Q => \^m_payload_i_reg[34]_0\(25),
      R => '0'
    );
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(28),
      Q => \^m_payload_i_reg[34]_0\(26),
      R => '0'
    );
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(29),
      Q => \^m_payload_i_reg[34]_0\(27),
      R => '0'
    );
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(30),
      Q => \^m_payload_i_reg[34]_0\(28),
      R => '0'
    );
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(31),
      Q => \^m_payload_i_reg[34]_0\(29),
      R => '0'
    );
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(32),
      Q => \^m_payload_i_reg[34]_0\(30),
      R => '0'
    );
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(33),
      Q => \^m_payload_i_reg[34]_0\(31),
      R => '0'
    );
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(34),
      Q => \^m_payload_i_reg[34]_0\(32),
      R => '0'
    );
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(3),
      Q => \^m_payload_i_reg[34]_0\(1),
      R => '0'
    );
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(4),
      Q => \^m_payload_i_reg[34]_0\(2),
      R => '0'
    );
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(5),
      Q => \^m_payload_i_reg[34]_0\(3),
      R => '0'
    );
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(6),
      Q => \^m_payload_i_reg[34]_0\(4),
      R => '0'
    );
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(7),
      Q => \^m_payload_i_reg[34]_0\(5),
      R => '0'
    );
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(8),
      Q => \^m_payload_i_reg[34]_0\(6),
      R => '0'
    );
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => E(0),
      D => skid_buffer(9),
      Q => \^m_payload_i_reg[34]_0\(7),
      R => '0'
    );
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFFFFFF"
    )
        port map (
      I0 => \^sr_rvalid\,
      I1 => \^m_payload_i_reg[34]_0\(0),
      I2 => s_axi_rready(0),
      I3 => aa_grant_rnw,
      I4 => m_valid_i,
      I5 => Q(0),
      O => m_valid_i_reg_0
    );
m_valid_i_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88808888AAAAAAAA"
    )
        port map (
      I0 => \aresetn_d_reg_n_0_[1]\,
      I1 => \^sr_rvalid\,
      I2 => Q(0),
      I3 => s_ready_i_reg_0,
      I4 => s_axi_rready(0),
      I5 => m_valid_i_i_3_n_0,
      O => m_valid_i_i_1_n_0
    );
m_valid_i_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8AAA8A8A8AAAAAA"
    )
        port map (
      I0 => aa_rready,
      I1 => Q(0),
      I2 => s_ready_i_reg_0,
      I3 => m_axi_rvalid(1),
      I4 => m_atarget_enc(0),
      I5 => m_axi_rvalid(0),
      O => m_valid_i_i_3_n_0
    );
m_valid_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => m_valid_i_i_1_n_0,
      Q => \^sr_rvalid\,
      R => '0'
    );
s_ready_i_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8A8AAA8A8A8A8A"
    )
        port map (
      I0 => \aresetn_d_reg_n_0_[0]\,
      I1 => m_valid_i_i_3_n_0,
      I2 => \^sr_rvalid\,
      I3 => Q(0),
      I4 => s_ready_i_reg_0,
      I5 => s_axi_rready(0),
      O => s_ready_i_i_1_n_0
    );
s_ready_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => s_ready_i_i_1_n_0,
      Q => aa_rready,
      R => '0'
    );
\skid_buffer[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => aa_rready,
      I1 => \skid_buffer_reg_n_0_[0]\,
      O => skid_buffer(0)
    );
\skid_buffer[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(39),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(7),
      O => \skid_buffer[10]_i_1_n_0\
    );
\skid_buffer[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(40),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(8),
      O => \skid_buffer[11]_i_1_n_0\
    );
\skid_buffer[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(41),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(9),
      O => \skid_buffer[12]_i_1_n_0\
    );
\skid_buffer[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(42),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(10),
      O => \skid_buffer[13]_i_1_n_0\
    );
\skid_buffer[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(43),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(11),
      O => \skid_buffer[14]_i_1_n_0\
    );
\skid_buffer[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(44),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(12),
      O => \skid_buffer[15]_i_1_n_0\
    );
\skid_buffer[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(45),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(13),
      O => \skid_buffer[16]_i_1_n_0\
    );
\skid_buffer[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(46),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(14),
      O => \skid_buffer[17]_i_1_n_0\
    );
\skid_buffer[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(47),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(15),
      O => \skid_buffer[18]_i_1_n_0\
    );
\skid_buffer[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(48),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(16),
      O => \skid_buffer[19]_i_1_n_0\
    );
\skid_buffer[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(49),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(17),
      O => \skid_buffer[20]_i_1_n_0\
    );
\skid_buffer[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(50),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(18),
      O => \skid_buffer[21]_i_1_n_0\
    );
\skid_buffer[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(51),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(19),
      O => \skid_buffer[22]_i_1_n_0\
    );
\skid_buffer[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(52),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(20),
      O => \skid_buffer[23]_i_1_n_0\
    );
\skid_buffer[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(53),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(21),
      O => \skid_buffer[24]_i_1_n_0\
    );
\skid_buffer[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(54),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(22),
      O => \skid_buffer[25]_i_1_n_0\
    );
\skid_buffer[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(55),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(23),
      O => \skid_buffer[26]_i_1_n_0\
    );
\skid_buffer[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(56),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(24),
      O => \skid_buffer[27]_i_1_n_0\
    );
\skid_buffer[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(57),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(25),
      O => \skid_buffer[28]_i_1_n_0\
    );
\skid_buffer[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(58),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(26),
      O => \skid_buffer[29]_i_1_n_0\
    );
\skid_buffer[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(59),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(27),
      O => \skid_buffer[30]_i_1_n_0\
    );
\skid_buffer[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(60),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(28),
      O => \skid_buffer[31]_i_1_n_0\
    );
\skid_buffer[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(61),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(29),
      O => \skid_buffer[32]_i_1_n_0\
    );
\skid_buffer[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(62),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(30),
      O => \skid_buffer[33]_i_1_n_0\
    );
\skid_buffer[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(63),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(31),
      O => \skid_buffer[34]_i_1_n_0\
    );
\skid_buffer[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(32),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(0),
      O => \skid_buffer[3]_i_1_n_0\
    );
\skid_buffer[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(33),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(1),
      O => \skid_buffer[4]_i_1_n_0\
    );
\skid_buffer[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(34),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(2),
      O => \skid_buffer[5]_i_1_n_0\
    );
\skid_buffer[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(35),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(3),
      O => \skid_buffer[6]_i_1_n_0\
    );
\skid_buffer[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(36),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(4),
      O => \skid_buffer[7]_i_1_n_0\
    );
\skid_buffer[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(37),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(5),
      O => \skid_buffer[8]_i_1_n_0\
    );
\skid_buffer[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axi_rdata(38),
      I1 => m_atarget_enc(0),
      I2 => m_axi_rdata(6),
      O => \skid_buffer[9]_i_1_n_0\
    );
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => '1',
      D => skid_buffer(0),
      Q => \skid_buffer_reg_n_0_[0]\,
      R => '0'
    );
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[10]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[10]\,
      R => '0'
    );
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[11]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[11]\,
      R => '0'
    );
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[12]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[12]\,
      R => '0'
    );
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[13]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[13]\,
      R => '0'
    );
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[14]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[14]\,
      R => '0'
    );
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[15]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[15]\,
      R => '0'
    );
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[16]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[16]\,
      R => '0'
    );
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[17]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[17]\,
      R => '0'
    );
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[18]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[18]\,
      R => '0'
    );
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[19]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[19]\,
      R => '0'
    );
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[20]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[20]\,
      R => '0'
    );
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[21]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[21]\,
      R => '0'
    );
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[22]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[22]\,
      R => '0'
    );
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[23]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[23]\,
      R => '0'
    );
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[24]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[24]\,
      R => '0'
    );
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[25]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[25]\,
      R => '0'
    );
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[26]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[26]\,
      R => '0'
    );
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[27]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[27]\,
      R => '0'
    );
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[28]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[28]\,
      R => '0'
    );
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[29]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[29]\,
      R => '0'
    );
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[30]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[30]\,
      R => '0'
    );
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[31]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[31]\,
      R => '0'
    );
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[32]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[32]\,
      R => '0'
    );
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[33]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[33]\,
      R => '0'
    );
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[34]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[34]\,
      R => '0'
    );
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[3]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[3]\,
      R => '0'
    );
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[4]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[4]\,
      R => '0'
    );
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[5]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[5]\,
      R => '0'
    );
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[6]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[6]\,
      R => '0'
    );
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[7]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[7]\,
      R => '0'
    );
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[8]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[8]\,
      R => '0'
    );
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => aa_rready,
      D => \skid_buffer[9]_i_1_n_0\,
      Q => \skid_buffer_reg_n_0_[9]\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_axis_dwidth_converter_v1_1_32_axisc_downsizer is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \state_reg[1]_0\ : out STD_LOGIC;
    m_axis_tlast : out STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 );
    m_axis_tid : out STD_LOGIC_VECTOR ( 5 downto 0 );
    m_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axis_tvalid : in STD_LOGIC;
    areset_r : in STD_LOGIC;
    s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    aclk : in STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
    s_axis_tlast : in STD_LOGIC;
    s_axis_tid : in STD_LOGIC_VECTOR ( 5 downto 0 );
    s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_axis_dwidth_converter_v1_1_32_axisc_downsizer : entity is "axis_dwidth_converter_v1_1_32_axisc_downsizer";
end design_1_Vsp_core_0_0_axis_dwidth_converter_v1_1_32_axisc_downsizer;

architecture STRUCTURE of design_1_Vsp_core_0_0_axis_dwidth_converter_v1_1_32_axisc_downsizer is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal p_0_in1_in : STD_LOGIC_VECTOR ( 59 downto 0 );
  signal \r0_data_reg_n_0_[32]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[33]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[34]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[35]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[36]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[37]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[38]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[39]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[40]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[41]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[42]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[43]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[48]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[49]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[50]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[51]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[52]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[53]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[54]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[55]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[56]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[57]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[58]\ : STD_LOGIC;
  signal \r0_data_reg_n_0_[59]\ : STD_LOGIC;
  signal r0_id : STD_LOGIC_VECTOR ( 9 downto 4 );
  signal r0_is_end : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \r0_is_null_r[1]_i_1_n_0\ : STD_LOGIC;
  signal r0_last_reg_n_0 : STD_LOGIC;
  signal \r0_out_sel_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \r0_out_sel_r_reg_n_0_[0]\ : STD_LOGIC;
  signal r0_user : STD_LOGIC_VECTOR ( 19 to 19 );
  signal r1_id : STD_LOGIC_VECTOR ( 9 downto 4 );
  signal r1_last_reg_n_0 : STD_LOGIC;
  signal r1_load : STD_LOGIC;
  signal r1_user : STD_LOGIC_VECTOR ( 0 to 0 );
  signal state : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \state[0]_i_1_n_0\ : STD_LOGIC;
  signal \^state_reg[1]_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \m_axis_tdata[0]_INST_0\ : label is "soft_lutpair543";
  attribute SOFT_HLUTNM of \m_axis_tdata[10]_INST_0\ : label is "soft_lutpair538";
  attribute SOFT_HLUTNM of \m_axis_tdata[11]_INST_0\ : label is "soft_lutpair538";
  attribute SOFT_HLUTNM of \m_axis_tdata[16]_INST_0\ : label is "soft_lutpair537";
  attribute SOFT_HLUTNM of \m_axis_tdata[17]_INST_0\ : label is "soft_lutpair537";
  attribute SOFT_HLUTNM of \m_axis_tdata[18]_INST_0\ : label is "soft_lutpair536";
  attribute SOFT_HLUTNM of \m_axis_tdata[19]_INST_0\ : label is "soft_lutpair536";
  attribute SOFT_HLUTNM of \m_axis_tdata[1]_INST_0\ : label is "soft_lutpair543";
  attribute SOFT_HLUTNM of \m_axis_tdata[20]_INST_0\ : label is "soft_lutpair535";
  attribute SOFT_HLUTNM of \m_axis_tdata[21]_INST_0\ : label is "soft_lutpair535";
  attribute SOFT_HLUTNM of \m_axis_tdata[22]_INST_0\ : label is "soft_lutpair534";
  attribute SOFT_HLUTNM of \m_axis_tdata[23]_INST_0\ : label is "soft_lutpair534";
  attribute SOFT_HLUTNM of \m_axis_tdata[24]_INST_0\ : label is "soft_lutpair533";
  attribute SOFT_HLUTNM of \m_axis_tdata[25]_INST_0\ : label is "soft_lutpair533";
  attribute SOFT_HLUTNM of \m_axis_tdata[26]_INST_0\ : label is "soft_lutpair532";
  attribute SOFT_HLUTNM of \m_axis_tdata[27]_INST_0\ : label is "soft_lutpair532";
  attribute SOFT_HLUTNM of \m_axis_tdata[2]_INST_0\ : label is "soft_lutpair542";
  attribute SOFT_HLUTNM of \m_axis_tdata[3]_INST_0\ : label is "soft_lutpair542";
  attribute SOFT_HLUTNM of \m_axis_tdata[4]_INST_0\ : label is "soft_lutpair541";
  attribute SOFT_HLUTNM of \m_axis_tdata[5]_INST_0\ : label is "soft_lutpair541";
  attribute SOFT_HLUTNM of \m_axis_tdata[6]_INST_0\ : label is "soft_lutpair540";
  attribute SOFT_HLUTNM of \m_axis_tdata[7]_INST_0\ : label is "soft_lutpair540";
  attribute SOFT_HLUTNM of \m_axis_tdata[8]_INST_0\ : label is "soft_lutpair539";
  attribute SOFT_HLUTNM of \m_axis_tdata[9]_INST_0\ : label is "soft_lutpair539";
  attribute SOFT_HLUTNM of \m_axis_tid[9]_INST_0\ : label is "soft_lutpair531";
  attribute SOFT_HLUTNM of \r0_is_null_r[1]_i_1\ : label is "soft_lutpair530";
  attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair531";
  attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair530";
  attribute FSM_ENCODING : string;
  attribute FSM_ENCODING of \state_reg[0]\ : label is "none";
  attribute FSM_ENCODING of \state_reg[1]\ : label is "none";
begin
  E(0) <= \^e\(0);
  \state_reg[1]_0\ <= \^state_reg[1]_0\;
\m_axis_tdata[0]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(32),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(0),
      O => m_axis_tdata(0)
    );
\m_axis_tdata[10]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(42),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(10),
      O => m_axis_tdata(10)
    );
\m_axis_tdata[11]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(43),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(11),
      O => m_axis_tdata(11)
    );
\m_axis_tdata[16]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(48),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(16),
      O => m_axis_tdata(12)
    );
\m_axis_tdata[17]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(49),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(17),
      O => m_axis_tdata(13)
    );
\m_axis_tdata[18]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(50),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(18),
      O => m_axis_tdata(14)
    );
\m_axis_tdata[19]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(51),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(19),
      O => m_axis_tdata(15)
    );
\m_axis_tdata[1]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(33),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(1),
      O => m_axis_tdata(1)
    );
\m_axis_tdata[20]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(52),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(20),
      O => m_axis_tdata(16)
    );
\m_axis_tdata[21]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(53),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(21),
      O => m_axis_tdata(17)
    );
\m_axis_tdata[22]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(54),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(22),
      O => m_axis_tdata(18)
    );
\m_axis_tdata[23]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(55),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(23),
      O => m_axis_tdata(19)
    );
\m_axis_tdata[24]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(56),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(24),
      O => m_axis_tdata(20)
    );
\m_axis_tdata[25]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(57),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(25),
      O => m_axis_tdata(21)
    );
\m_axis_tdata[26]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(58),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(26),
      O => m_axis_tdata(22)
    );
\m_axis_tdata[27]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(59),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(27),
      O => m_axis_tdata(23)
    );
\m_axis_tdata[2]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(34),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(2),
      O => m_axis_tdata(2)
    );
\m_axis_tdata[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(35),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(3),
      O => m_axis_tdata(3)
    );
\m_axis_tdata[4]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(36),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(4),
      O => m_axis_tdata(4)
    );
\m_axis_tdata[5]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(37),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(5),
      O => m_axis_tdata(5)
    );
\m_axis_tdata[6]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(38),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(6),
      O => m_axis_tdata(6)
    );
\m_axis_tdata[7]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(39),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(7),
      O => m_axis_tdata(7)
    );
\m_axis_tdata[8]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(40),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(8),
      O => m_axis_tdata(8)
    );
\m_axis_tdata[9]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in1_in(41),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => p_0_in1_in(9),
      O => m_axis_tdata(9)
    );
\m_axis_tid[4]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BF80"
    )
        port map (
      I0 => r1_id(4),
      I1 => \^state_reg[1]_0\,
      I2 => \^e\(0),
      I3 => r0_id(4),
      O => m_axis_tid(0)
    );
\m_axis_tid[5]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BF80"
    )
        port map (
      I0 => r1_id(5),
      I1 => \^state_reg[1]_0\,
      I2 => \^e\(0),
      I3 => r0_id(5),
      O => m_axis_tid(1)
    );
\m_axis_tid[6]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BF80"
    )
        port map (
      I0 => r1_id(6),
      I1 => \^state_reg[1]_0\,
      I2 => \^e\(0),
      I3 => r0_id(6),
      O => m_axis_tid(2)
    );
\m_axis_tid[7]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BF80"
    )
        port map (
      I0 => r1_id(7),
      I1 => \^state_reg[1]_0\,
      I2 => \^e\(0),
      I3 => r0_id(7),
      O => m_axis_tid(3)
    );
\m_axis_tid[8]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BF80"
    )
        port map (
      I0 => r1_id(8),
      I1 => \^state_reg[1]_0\,
      I2 => \^e\(0),
      I3 => r0_id(8),
      O => m_axis_tid(4)
    );
\m_axis_tid[9]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BF80"
    )
        port map (
      I0 => r1_id(9),
      I1 => \^state_reg[1]_0\,
      I2 => \^e\(0),
      I3 => r0_id(9),
      O => m_axis_tid(5)
    );
m_axis_tlast_INST_0: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8880888"
    )
        port map (
      I0 => r0_last_reg_n_0,
      I1 => r0_is_end(0),
      I2 => \^state_reg[1]_0\,
      I3 => \^e\(0),
      I4 => r1_last_reg_n_0,
      O => m_axis_tlast
    );
\m_axis_tuser[0]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => r1_user(0),
      I1 => \r0_out_sel_r_reg_n_0_[0]\,
      I2 => r0_user(19),
      O => m_axis_tuser(0)
    );
\r0_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(0),
      Q => p_0_in1_in(0),
      R => '0'
    );
\r0_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(10),
      Q => p_0_in1_in(10),
      R => '0'
    );
\r0_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(11),
      Q => p_0_in1_in(11),
      R => '0'
    );
\r0_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(12),
      Q => p_0_in1_in(16),
      R => '0'
    );
\r0_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(13),
      Q => p_0_in1_in(17),
      R => '0'
    );
\r0_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(14),
      Q => p_0_in1_in(18),
      R => '0'
    );
\r0_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(15),
      Q => p_0_in1_in(19),
      R => '0'
    );
\r0_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(1),
      Q => p_0_in1_in(1),
      R => '0'
    );
\r0_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(16),
      Q => p_0_in1_in(20),
      R => '0'
    );
\r0_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(17),
      Q => p_0_in1_in(21),
      R => '0'
    );
\r0_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(18),
      Q => p_0_in1_in(22),
      R => '0'
    );
\r0_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(19),
      Q => p_0_in1_in(23),
      R => '0'
    );
\r0_data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(20),
      Q => p_0_in1_in(24),
      R => '0'
    );
\r0_data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(21),
      Q => p_0_in1_in(25),
      R => '0'
    );
\r0_data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(22),
      Q => p_0_in1_in(26),
      R => '0'
    );
\r0_data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(23),
      Q => p_0_in1_in(27),
      R => '0'
    );
\r0_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(2),
      Q => p_0_in1_in(2),
      R => '0'
    );
\r0_data_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(24),
      Q => \r0_data_reg_n_0_[32]\,
      R => '0'
    );
\r0_data_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(25),
      Q => \r0_data_reg_n_0_[33]\,
      R => '0'
    );
\r0_data_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(26),
      Q => \r0_data_reg_n_0_[34]\,
      R => '0'
    );
\r0_data_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(27),
      Q => \r0_data_reg_n_0_[35]\,
      R => '0'
    );
\r0_data_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(28),
      Q => \r0_data_reg_n_0_[36]\,
      R => '0'
    );
\r0_data_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(29),
      Q => \r0_data_reg_n_0_[37]\,
      R => '0'
    );
\r0_data_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(30),
      Q => \r0_data_reg_n_0_[38]\,
      R => '0'
    );
\r0_data_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(31),
      Q => \r0_data_reg_n_0_[39]\,
      R => '0'
    );
\r0_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(3),
      Q => p_0_in1_in(3),
      R => '0'
    );
\r0_data_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(32),
      Q => \r0_data_reg_n_0_[40]\,
      R => '0'
    );
\r0_data_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(33),
      Q => \r0_data_reg_n_0_[41]\,
      R => '0'
    );
\r0_data_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(34),
      Q => \r0_data_reg_n_0_[42]\,
      R => '0'
    );
\r0_data_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(35),
      Q => \r0_data_reg_n_0_[43]\,
      R => '0'
    );
\r0_data_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(36),
      Q => \r0_data_reg_n_0_[48]\,
      R => '0'
    );
\r0_data_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(37),
      Q => \r0_data_reg_n_0_[49]\,
      R => '0'
    );
\r0_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(4),
      Q => p_0_in1_in(4),
      R => '0'
    );
\r0_data_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(38),
      Q => \r0_data_reg_n_0_[50]\,
      R => '0'
    );
\r0_data_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(39),
      Q => \r0_data_reg_n_0_[51]\,
      R => '0'
    );
\r0_data_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(40),
      Q => \r0_data_reg_n_0_[52]\,
      R => '0'
    );
\r0_data_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(41),
      Q => \r0_data_reg_n_0_[53]\,
      R => '0'
    );
\r0_data_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(42),
      Q => \r0_data_reg_n_0_[54]\,
      R => '0'
    );
\r0_data_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(43),
      Q => \r0_data_reg_n_0_[55]\,
      R => '0'
    );
\r0_data_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(44),
      Q => \r0_data_reg_n_0_[56]\,
      R => '0'
    );
\r0_data_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(45),
      Q => \r0_data_reg_n_0_[57]\,
      R => '0'
    );
\r0_data_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(46),
      Q => \r0_data_reg_n_0_[58]\,
      R => '0'
    );
\r0_data_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(47),
      Q => \r0_data_reg_n_0_[59]\,
      R => '0'
    );
\r0_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(5),
      Q => p_0_in1_in(5),
      R => '0'
    );
\r0_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(6),
      Q => p_0_in1_in(6),
      R => '0'
    );
\r0_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(7),
      Q => p_0_in1_in(7),
      R => '0'
    );
\r0_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(8),
      Q => p_0_in1_in(8),
      R => '0'
    );
\r0_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tdata(9),
      Q => p_0_in1_in(9),
      R => '0'
    );
\r0_id_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tid(0),
      Q => r0_id(4),
      R => '0'
    );
\r0_id_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tid(1),
      Q => r0_id(5),
      R => '0'
    );
\r0_id_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tid(2),
      Q => r0_id(6),
      R => '0'
    );
\r0_id_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tid(3),
      Q => r0_id(7),
      R => '0'
    );
\r0_id_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tid(4),
      Q => r0_id(8),
      R => '0'
    );
\r0_id_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tid(5),
      Q => r0_id(9),
      R => '0'
    );
\r0_is_null_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F40"
    )
        port map (
      I0 => s_axis_tkeep(0),
      I1 => s_axis_tvalid,
      I2 => \^e\(0),
      I3 => r0_is_end(0),
      O => \r0_is_null_r[1]_i_1_n_0\
    );
\r0_is_null_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \r0_is_null_r[1]_i_1_n_0\,
      Q => r0_is_end(0),
      R => areset_r
    );
r0_last_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tlast,
      Q => r0_last_reg_n_0,
      R => '0'
    );
\r0_out_sel_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000045"
    )
        port map (
      I0 => r0_is_end(0),
      I1 => \^state_reg[1]_0\,
      I2 => \^e\(0),
      I3 => \r0_out_sel_r_reg_n_0_[0]\,
      I4 => areset_r,
      O => \r0_out_sel_r[0]_i_1_n_0\
    );
\r0_out_sel_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \r0_out_sel_r[0]_i_1_n_0\,
      Q => \r0_out_sel_r_reg_n_0_[0]\,
      R => '0'
    );
\r0_user_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => \^e\(0),
      D => s_axis_tuser(0),
      Q => r0_user(19),
      R => '0'
    );
\r1_data[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^state_reg[1]_0\,
      I1 => \^e\(0),
      O => r1_load
    );
\r1_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[32]\,
      Q => p_0_in1_in(32),
      R => '0'
    );
\r1_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[42]\,
      Q => p_0_in1_in(42),
      R => '0'
    );
\r1_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[43]\,
      Q => p_0_in1_in(43),
      R => '0'
    );
\r1_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[48]\,
      Q => p_0_in1_in(48),
      R => '0'
    );
\r1_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[49]\,
      Q => p_0_in1_in(49),
      R => '0'
    );
\r1_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[50]\,
      Q => p_0_in1_in(50),
      R => '0'
    );
\r1_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[51]\,
      Q => p_0_in1_in(51),
      R => '0'
    );
\r1_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[33]\,
      Q => p_0_in1_in(33),
      R => '0'
    );
\r1_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[52]\,
      Q => p_0_in1_in(52),
      R => '0'
    );
\r1_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[53]\,
      Q => p_0_in1_in(53),
      R => '0'
    );
\r1_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[54]\,
      Q => p_0_in1_in(54),
      R => '0'
    );
\r1_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[55]\,
      Q => p_0_in1_in(55),
      R => '0'
    );
\r1_data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[56]\,
      Q => p_0_in1_in(56),
      R => '0'
    );
\r1_data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[57]\,
      Q => p_0_in1_in(57),
      R => '0'
    );
\r1_data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[58]\,
      Q => p_0_in1_in(58),
      R => '0'
    );
\r1_data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[59]\,
      Q => p_0_in1_in(59),
      R => '0'
    );
\r1_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[34]\,
      Q => p_0_in1_in(34),
      R => '0'
    );
\r1_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[35]\,
      Q => p_0_in1_in(35),
      R => '0'
    );
\r1_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[36]\,
      Q => p_0_in1_in(36),
      R => '0'
    );
\r1_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[37]\,
      Q => p_0_in1_in(37),
      R => '0'
    );
\r1_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[38]\,
      Q => p_0_in1_in(38),
      R => '0'
    );
\r1_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[39]\,
      Q => p_0_in1_in(39),
      R => '0'
    );
\r1_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[40]\,
      Q => p_0_in1_in(40),
      R => '0'
    );
\r1_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => \r0_data_reg_n_0_[41]\,
      Q => p_0_in1_in(41),
      R => '0'
    );
\r1_id_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => r0_id(4),
      Q => r1_id(4),
      R => '0'
    );
\r1_id_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => r0_id(5),
      Q => r1_id(5),
      R => '0'
    );
\r1_id_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => r0_id(6),
      Q => r1_id(6),
      R => '0'
    );
\r1_id_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => r0_id(7),
      Q => r1_id(7),
      R => '0'
    );
\r1_id_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => r0_id(8),
      Q => r1_id(8),
      R => '0'
    );
\r1_id_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => r0_id(9),
      Q => r1_id(9),
      R => '0'
    );
r1_last_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => r0_last_reg_n_0,
      Q => r1_last_reg_n_0,
      R => '0'
    );
\r1_user_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk,
      CE => r1_load,
      D => r0_user(19),
      Q => r1_user(0),
      R => '0'
    );
\state[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^e\(0),
      I1 => s_axis_tvalid,
      O => \state[0]_i_1_n_0\
    );
\state[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C5C0"
    )
        port map (
      I0 => r0_is_end(0),
      I1 => s_axis_tvalid,
      I2 => \^e\(0),
      I3 => \^state_reg[1]_0\,
      O => state(1)
    );
\state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => \state[0]_i_1_n_0\,
      Q => \^e\(0),
      R => areset_r
    );
\state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => state(1),
      Q => \^state_reg[1]_0\,
      R => areset_r
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_mipi_iobuf_rx is
  port (
    data_to_bs_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
    lp_rx_o_n : out STD_LOGIC_VECTOR ( 4 downto 0 );
    lp_rx_o_p : out STD_LOGIC_VECTOR ( 4 downto 0 );
    hs_rx_disable : in STD_LOGIC_VECTOR ( 4 downto 0 );
    data_from_pins : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_mipi_iobuf_rx : entity is "bd_7289_phy_0_hssio_rx_mipi_iobuf_rx";
end design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_mipi_iobuf_rx;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_mipi_iobuf_rx is
  attribute box_type : string;
  attribute box_type of \io_gen[0].ibufds_dphy\ : label is "PRIMITIVE";
  attribute box_type of \io_gen[2].ibufds_dphy\ : label is "PRIMITIVE";
  attribute box_type of \io_gen[4].ibufds_dphy\ : label is "PRIMITIVE";
  attribute box_type of \io_gen[6].ibufds_dphy\ : label is "PRIMITIVE";
  attribute box_type of \io_gen[8].ibufds_dphy\ : label is "PRIMITIVE";
begin
\io_gen[0].ibufds_dphy\: unisim.vcomponents.IBUFDS_DPHY
    generic map(
      SIM_DEVICE => "ULTRASCALE_PLUS"
    )
        port map (
      HSRX_DISABLE => hs_rx_disable(0),
      HSRX_O => data_to_bs_out(0),
      I => data_from_pins(0),
      IB => data_from_pins(1),
      LPRX_DISABLE => '0',
      LPRX_O_N => lp_rx_o_n(0),
      LPRX_O_P => lp_rx_o_p(0)
    );
\io_gen[2].ibufds_dphy\: unisim.vcomponents.IBUFDS_DPHY
    generic map(
      SIM_DEVICE => "ULTRASCALE_PLUS"
    )
        port map (
      HSRX_DISABLE => hs_rx_disable(1),
      HSRX_O => data_to_bs_out(1),
      I => data_from_pins(2),
      IB => data_from_pins(3),
      LPRX_DISABLE => '0',
      LPRX_O_N => lp_rx_o_n(1),
      LPRX_O_P => lp_rx_o_p(1)
    );
\io_gen[4].ibufds_dphy\: unisim.vcomponents.IBUFDS_DPHY
    generic map(
      SIM_DEVICE => "ULTRASCALE_PLUS"
    )
        port map (
      HSRX_DISABLE => hs_rx_disable(2),
      HSRX_O => data_to_bs_out(2),
      I => data_from_pins(4),
      IB => data_from_pins(5),
      LPRX_DISABLE => '0',
      LPRX_O_N => lp_rx_o_n(2),
      LPRX_O_P => lp_rx_o_p(2)
    );
\io_gen[6].ibufds_dphy\: unisim.vcomponents.IBUFDS_DPHY
    generic map(
      SIM_DEVICE => "ULTRASCALE_PLUS"
    )
        port map (
      HSRX_DISABLE => hs_rx_disable(3),
      HSRX_O => data_to_bs_out(3),
      I => data_from_pins(6),
      IB => data_from_pins(7),
      LPRX_DISABLE => '0',
      LPRX_O_N => lp_rx_o_n(3),
      LPRX_O_P => lp_rx_o_p(3)
    );
\io_gen[8].ibufds_dphy\: unisim.vcomponents.IBUFDS_DPHY
    generic map(
      SIM_DEVICE => "ULTRASCALE_PLUS"
    )
        port map (
      HSRX_DISABLE => hs_rx_disable(4),
      HSRX_O => data_to_bs_out(4),
      I => data_from_pins(8),
      IB => data_from_pins(9),
      LPRX_DISABLE => '0',
      LPRX_O_N => lp_rx_o_n(4),
      LPRX_O_P => lp_rx_o_p(4)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_cdc_sync is
  port (
    lpf_exr_reg : out STD_LOGIC;
    scndry_out : out STD_LOGIC;
    lpf_exr : in STD_LOGIC;
    p_1_in4_in : in STD_LOGIC;
    p_2_in3_in : in STD_LOGIC;
    exr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_reset_in : in STD_LOGIC;
    slowest_sync_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_cdc_sync : entity is "cdc_sync";
end design_1_Vsp_core_0_0_cdc_sync;

architecture STRUCTURE of design_1_Vsp_core_0_0_cdc_sync is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  signal Q : STD_LOGIC;
  signal exr_d1 : STD_LOGIC;
  signal \^scndry_out\ : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
  attribute box_type : string;
  attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
  attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
  attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
  attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "VCC:CE";
  attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
  attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
  attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
  attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "VCC:CE";
  attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
  attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
  attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
  attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "VCC:CE";
  attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
  scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => exr_d1,
      Q => Q,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ext_reset_in,
      O => exr_d1
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => Q,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \^scndry_out\,
      R => '0'
    );
lpf_exr_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAAAAA8"
    )
        port map (
      I0 => lpf_exr,
      I1 => p_1_in4_in,
      I2 => p_2_in3_in,
      I3 => \^scndry_out\,
      I4 => exr_lpf(0),
      O => lpf_exr_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_bs_ctrl_top is
  port (
    \BITSLICE_CTRL[1].bs_ctrl_inst_0\ : out STD_LOGIC;
    n1_vtc_rdy_out : out STD_LOGIC;
    n0_vtc_rdy_out : out STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[7]\ : out STD_LOGIC;
    core_rdy : out STD_LOGIC;
    in0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    n0_rx_bit_ctrl_out0 : out STD_LOGIC_VECTOR ( 39 downto 0 );
    n0_rx_bit_ctrl_out2 : out STD_LOGIC_VECTOR ( 39 downto 0 );
    n0_rx_bit_ctrl_out4 : out STD_LOGIC_VECTOR ( 39 downto 0 );
    n0_tx_bit_ctrl_out0 : out STD_LOGIC_VECTOR ( 39 downto 0 );
    n0_tx_bit_ctrl_out2 : out STD_LOGIC_VECTOR ( 39 downto 0 );
    n0_tx_bit_ctrl_out4 : out STD_LOGIC_VECTOR ( 39 downto 0 );
    n1_rx_bit_ctrl_out0 : out STD_LOGIC_VECTOR ( 39 downto 0 );
    n1_rx_bit_ctrl_out2 : out STD_LOGIC_VECTOR ( 39 downto 0 );
    n1_tx_bit_ctrl_out0 : out STD_LOGIC_VECTOR ( 39 downto 0 );
    n1_tx_bit_ctrl_out2 : out STD_LOGIC_VECTOR ( 39 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    n1_en_vtc_in : in STD_LOGIC;
    pll0_clkoutphy_out : in STD_LOGIC;
    riu_clk : in STD_LOGIC;
    bsctrl_rst : in STD_LOGIC;
    rx_bs0_rx_bit_ctrl_out : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs2_rx_bit_ctrl_out : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs4_rx_bit_ctrl_out : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs0_tx_bit_ctrl_out : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs2_tx_bit_ctrl_out : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs4_tx_bit_ctrl_out : in STD_LOGIC_VECTOR ( 39 downto 0 );
    n0_tbyte_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rx_bs6_rx_bit_ctrl_out : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs8_rx_bit_ctrl_out : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs6_tx_bit_ctrl_out : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs8_tx_bit_ctrl_out : in STD_LOGIC_VECTOR ( 39 downto 0 );
    n1_tbyte_in : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_bs_ctrl_top : entity is "high_speed_selectio_wiz_v3_6_10_bs_ctrl_top";
end design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_bs_ctrl_top;

architecture STRUCTURE of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_bs_ctrl_top is
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_10\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_11\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_12\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_13\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_14\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_15\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_16\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_17\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_18\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_19\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_2\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_20\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_21\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_22\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_263\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_264\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_265\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_266\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_267\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_268\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_269\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_270\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_271\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_272\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_273\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_274\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_275\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_276\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_277\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_278\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_279\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_280\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_281\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_282\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_283\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_284\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_285\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_286\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_287\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_288\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_289\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_290\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_291\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_292\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_293\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_294\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_295\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_296\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_297\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_298\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_299\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_300\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_301\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_302\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_5\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_543\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_544\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_545\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_546\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_547\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_548\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_549\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_550\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_551\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_552\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_553\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_554\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_555\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_556\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_557\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_558\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_559\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_560\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_561\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_562\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_563\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_564\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_565\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_566\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_567\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_568\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_569\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_570\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_571\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_572\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_573\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_574\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_575\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_576\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_577\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_578\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_579\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_580\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_581\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_582\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_7\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_8\ : STD_LOGIC;
  signal \BITSLICE_CTRL[0].bs_ctrl_inst_n_9\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_10\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_11\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_12\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_13\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_14\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_15\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_16\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_17\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_18\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_19\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_2\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_20\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_21\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_22\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_5\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_7\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_8\ : STD_LOGIC;
  signal \BITSLICE_CTRL[1].bs_ctrl_inst_n_9\ : STD_LOGIC;
  signal n0_rx_bit_ctrl_out1 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_rx_bit_ctrl_out3 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_rx_bit_ctrl_out5 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_tx_bit_ctrl_out1 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_tx_bit_ctrl_out3 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_tx_bit_ctrl_out5 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_tx_bit_ctrl_out_tri : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \^n0_vtc_rdy_out\ : STD_LOGIC;
  signal n1_rx_bit_ctrl_out1 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_rx_bit_ctrl_out3 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_rx_bit_ctrl_out4 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_rx_bit_ctrl_out5 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_rx_bit_ctrl_out6 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_tx_bit_ctrl_out1 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_tx_bit_ctrl_out3 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_tx_bit_ctrl_out4 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_tx_bit_ctrl_out5 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_tx_bit_ctrl_out6 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_tx_bit_ctrl_out_tri : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \^n1_vtc_rdy_out\ : STD_LOGIC;
  signal nclk_nibble_out : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pclk_nibble_out : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_BITSLICE_CTRL[0].bs_ctrl_inst_CLK_TO_EXT_NORTH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_BITSLICE_CTRL[0].bs_ctrl_inst_CLK_TO_EXT_SOUTH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_BITSLICE_CTRL[0].bs_ctrl_inst_DYN_DCI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_BITSLICE_CTRL[1].bs_ctrl_inst_CLK_TO_EXT_NORTH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_BITSLICE_CTRL[1].bs_ctrl_inst_CLK_TO_EXT_SOUTH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_BITSLICE_CTRL[1].bs_ctrl_inst_DYN_DCI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  attribute box_type : string;
  attribute box_type of \BITSLICE_CTRL[0].bs_ctrl_inst\ : label is "PRIMITIVE";
  attribute box_type of \BITSLICE_CTRL[1].bs_ctrl_inst\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \CORE_RDY_GEN[0].core_rdy_r[0]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_7\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_9\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of src_data_inferred_i_1 : label is "soft_lutpair0";
begin
  n0_vtc_rdy_out <= \^n0_vtc_rdy_out\;
  n1_vtc_rdy_out <= \^n1_vtc_rdy_out\;
\BITSLICE_CTRL[0].bs_ctrl_inst\: unisim.vcomponents.BITSLICE_CONTROL
    generic map(
      CTRL_CLK => "EXTERNAL",
      DIV_MODE => "DIV4",
      EN_CLK_TO_EXT_NORTH => "DISABLE",
      EN_CLK_TO_EXT_SOUTH => "DISABLE",
      EN_DYN_ODLY_MODE => "FALSE",
      EN_OTHER_NCLK => "FALSE",
      EN_OTHER_PCLK => "FALSE",
      IDLY_VT_TRACK => "TRUE",
      INV_RXCLK => "FALSE",
      ODLY_VT_TRACK => "TRUE",
      QDLY_VT_TRACK => "TRUE",
      READ_IDLE_COUNT => B"00" & X"0",
      REFCLK_SRC => "PLLCLK",
      ROUNDING_FACTOR => 16,
      RXGATE_EXTEND => "FALSE",
      RX_CLK_PHASE_N => "SHIFT_0",
      RX_CLK_PHASE_P => "SHIFT_0",
      RX_GATING => "DISABLE",
      SELF_CALIBRATE => "ENABLE",
      SERIAL_MODE => "FALSE",
      SIM_DEVICE => "ULTRASCALE_PLUS_ES1",
      SIM_SPEEDUP => "FAST",
      SIM_VERSION => 2.000000,
      TX_GATING => "DISABLE"
    )
        port map (
      CLK_FROM_EXT => '1',
      CLK_TO_EXT_NORTH => \NLW_BITSLICE_CTRL[0].bs_ctrl_inst_CLK_TO_EXT_NORTH_UNCONNECTED\,
      CLK_TO_EXT_SOUTH => \NLW_BITSLICE_CTRL[0].bs_ctrl_inst_CLK_TO_EXT_SOUTH_UNCONNECTED\,
      DLY_RDY => \BITSLICE_CTRL[0].bs_ctrl_inst_n_2\,
      DYN_DCI(6 downto 0) => \NLW_BITSLICE_CTRL[0].bs_ctrl_inst_DYN_DCI_UNCONNECTED\(6 downto 0),
      EN_VTC => n1_en_vtc_in,
      NCLK_NIBBLE_IN => nclk_nibble_out(1),
      NCLK_NIBBLE_OUT => nclk_nibble_out(0),
      PCLK_NIBBLE_IN => pclk_nibble_out(1),
      PCLK_NIBBLE_OUT => pclk_nibble_out(0),
      PHY_RDCS0(3 downto 0) => B"0000",
      PHY_RDCS1(3 downto 0) => B"0000",
      PHY_RDEN(3 downto 0) => B"1111",
      PHY_WRCS0(3 downto 0) => B"0000",
      PHY_WRCS1(3 downto 0) => B"0000",
      PLL_CLK => pll0_clkoutphy_out,
      REFCLK => '0',
      RIU_ADDR(5 downto 0) => B"000000",
      RIU_CLK => riu_clk,
      RIU_NIBBLE_SEL => '0',
      RIU_RD_DATA(15) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_7\,
      RIU_RD_DATA(14) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_8\,
      RIU_RD_DATA(13) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_9\,
      RIU_RD_DATA(12) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_10\,
      RIU_RD_DATA(11) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_11\,
      RIU_RD_DATA(10) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_12\,
      RIU_RD_DATA(9) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_13\,
      RIU_RD_DATA(8) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_14\,
      RIU_RD_DATA(7) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_15\,
      RIU_RD_DATA(6) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_16\,
      RIU_RD_DATA(5) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_17\,
      RIU_RD_DATA(4) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_18\,
      RIU_RD_DATA(3) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_19\,
      RIU_RD_DATA(2) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_20\,
      RIU_RD_DATA(1) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_21\,
      RIU_RD_DATA(0) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_22\,
      RIU_VALID => \BITSLICE_CTRL[0].bs_ctrl_inst_n_5\,
      RIU_WR_DATA(15 downto 0) => B"0000000000000000",
      RIU_WR_EN => '0',
      RST => bsctrl_rst,
      RX_BIT_CTRL_IN0(39 downto 0) => rx_bs0_rx_bit_ctrl_out(39 downto 0),
      RX_BIT_CTRL_IN1(39 downto 0) => B"0000000000000000000000000000000000000000",
      RX_BIT_CTRL_IN2(39 downto 0) => rx_bs2_rx_bit_ctrl_out(39 downto 0),
      RX_BIT_CTRL_IN3(39 downto 0) => B"0000000000000000000000000000000000000000",
      RX_BIT_CTRL_IN4(39 downto 0) => rx_bs4_rx_bit_ctrl_out(39 downto 0),
      RX_BIT_CTRL_IN5(39 downto 0) => B"0000000000000000000000000000000000000000",
      RX_BIT_CTRL_IN6(39 downto 0) => B"0000000000000000000000000000000000000000",
      RX_BIT_CTRL_OUT0(39 downto 0) => n0_rx_bit_ctrl_out0(39 downto 0),
      RX_BIT_CTRL_OUT1(39 downto 0) => n0_rx_bit_ctrl_out1(39 downto 0),
      RX_BIT_CTRL_OUT2(39 downto 0) => n0_rx_bit_ctrl_out2(39 downto 0),
      RX_BIT_CTRL_OUT3(39 downto 0) => n0_rx_bit_ctrl_out3(39 downto 0),
      RX_BIT_CTRL_OUT4(39 downto 0) => n0_rx_bit_ctrl_out4(39 downto 0),
      RX_BIT_CTRL_OUT5(39 downto 0) => n0_rx_bit_ctrl_out5(39 downto 0),
      RX_BIT_CTRL_OUT6(39) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_263\,
      RX_BIT_CTRL_OUT6(38) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_264\,
      RX_BIT_CTRL_OUT6(37) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_265\,
      RX_BIT_CTRL_OUT6(36) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_266\,
      RX_BIT_CTRL_OUT6(35) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_267\,
      RX_BIT_CTRL_OUT6(34) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_268\,
      RX_BIT_CTRL_OUT6(33) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_269\,
      RX_BIT_CTRL_OUT6(32) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_270\,
      RX_BIT_CTRL_OUT6(31) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_271\,
      RX_BIT_CTRL_OUT6(30) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_272\,
      RX_BIT_CTRL_OUT6(29) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_273\,
      RX_BIT_CTRL_OUT6(28) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_274\,
      RX_BIT_CTRL_OUT6(27) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_275\,
      RX_BIT_CTRL_OUT6(26) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_276\,
      RX_BIT_CTRL_OUT6(25) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_277\,
      RX_BIT_CTRL_OUT6(24) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_278\,
      RX_BIT_CTRL_OUT6(23) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_279\,
      RX_BIT_CTRL_OUT6(22) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_280\,
      RX_BIT_CTRL_OUT6(21) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_281\,
      RX_BIT_CTRL_OUT6(20) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_282\,
      RX_BIT_CTRL_OUT6(19) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_283\,
      RX_BIT_CTRL_OUT6(18) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_284\,
      RX_BIT_CTRL_OUT6(17) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_285\,
      RX_BIT_CTRL_OUT6(16) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_286\,
      RX_BIT_CTRL_OUT6(15) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_287\,
      RX_BIT_CTRL_OUT6(14) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_288\,
      RX_BIT_CTRL_OUT6(13) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_289\,
      RX_BIT_CTRL_OUT6(12) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_290\,
      RX_BIT_CTRL_OUT6(11) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_291\,
      RX_BIT_CTRL_OUT6(10) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_292\,
      RX_BIT_CTRL_OUT6(9) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_293\,
      RX_BIT_CTRL_OUT6(8) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_294\,
      RX_BIT_CTRL_OUT6(7) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_295\,
      RX_BIT_CTRL_OUT6(6) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_296\,
      RX_BIT_CTRL_OUT6(5) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_297\,
      RX_BIT_CTRL_OUT6(4) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_298\,
      RX_BIT_CTRL_OUT6(3) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_299\,
      RX_BIT_CTRL_OUT6(2) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_300\,
      RX_BIT_CTRL_OUT6(1) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_301\,
      RX_BIT_CTRL_OUT6(0) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_302\,
      TBYTE_IN(3 downto 0) => n0_tbyte_in(3 downto 0),
      TX_BIT_CTRL_IN0(39 downto 0) => rx_bs0_tx_bit_ctrl_out(39 downto 0),
      TX_BIT_CTRL_IN1(39 downto 0) => B"0000000000000000000000000000000000000000",
      TX_BIT_CTRL_IN2(39 downto 0) => rx_bs2_tx_bit_ctrl_out(39 downto 0),
      TX_BIT_CTRL_IN3(39 downto 0) => B"0000000000000000000000000000000000000000",
      TX_BIT_CTRL_IN4(39 downto 0) => rx_bs4_tx_bit_ctrl_out(39 downto 0),
      TX_BIT_CTRL_IN5(39 downto 0) => B"0000000000000000000000000000000000000000",
      TX_BIT_CTRL_IN6(39 downto 0) => B"0000000000000000000000000000000000000000",
      TX_BIT_CTRL_IN_TRI(39 downto 0) => B"0000000000000000000000000000000000000000",
      TX_BIT_CTRL_OUT0(39 downto 0) => n0_tx_bit_ctrl_out0(39 downto 0),
      TX_BIT_CTRL_OUT1(39 downto 0) => n0_tx_bit_ctrl_out1(39 downto 0),
      TX_BIT_CTRL_OUT2(39 downto 0) => n0_tx_bit_ctrl_out2(39 downto 0),
      TX_BIT_CTRL_OUT3(39 downto 0) => n0_tx_bit_ctrl_out3(39 downto 0),
      TX_BIT_CTRL_OUT4(39 downto 0) => n0_tx_bit_ctrl_out4(39 downto 0),
      TX_BIT_CTRL_OUT5(39 downto 0) => n0_tx_bit_ctrl_out5(39 downto 0),
      TX_BIT_CTRL_OUT6(39) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_543\,
      TX_BIT_CTRL_OUT6(38) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_544\,
      TX_BIT_CTRL_OUT6(37) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_545\,
      TX_BIT_CTRL_OUT6(36) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_546\,
      TX_BIT_CTRL_OUT6(35) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_547\,
      TX_BIT_CTRL_OUT6(34) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_548\,
      TX_BIT_CTRL_OUT6(33) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_549\,
      TX_BIT_CTRL_OUT6(32) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_550\,
      TX_BIT_CTRL_OUT6(31) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_551\,
      TX_BIT_CTRL_OUT6(30) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_552\,
      TX_BIT_CTRL_OUT6(29) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_553\,
      TX_BIT_CTRL_OUT6(28) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_554\,
      TX_BIT_CTRL_OUT6(27) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_555\,
      TX_BIT_CTRL_OUT6(26) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_556\,
      TX_BIT_CTRL_OUT6(25) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_557\,
      TX_BIT_CTRL_OUT6(24) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_558\,
      TX_BIT_CTRL_OUT6(23) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_559\,
      TX_BIT_CTRL_OUT6(22) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_560\,
      TX_BIT_CTRL_OUT6(21) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_561\,
      TX_BIT_CTRL_OUT6(20) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_562\,
      TX_BIT_CTRL_OUT6(19) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_563\,
      TX_BIT_CTRL_OUT6(18) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_564\,
      TX_BIT_CTRL_OUT6(17) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_565\,
      TX_BIT_CTRL_OUT6(16) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_566\,
      TX_BIT_CTRL_OUT6(15) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_567\,
      TX_BIT_CTRL_OUT6(14) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_568\,
      TX_BIT_CTRL_OUT6(13) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_569\,
      TX_BIT_CTRL_OUT6(12) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_570\,
      TX_BIT_CTRL_OUT6(11) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_571\,
      TX_BIT_CTRL_OUT6(10) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_572\,
      TX_BIT_CTRL_OUT6(9) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_573\,
      TX_BIT_CTRL_OUT6(8) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_574\,
      TX_BIT_CTRL_OUT6(7) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_575\,
      TX_BIT_CTRL_OUT6(6) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_576\,
      TX_BIT_CTRL_OUT6(5) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_577\,
      TX_BIT_CTRL_OUT6(4) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_578\,
      TX_BIT_CTRL_OUT6(3) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_579\,
      TX_BIT_CTRL_OUT6(2) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_580\,
      TX_BIT_CTRL_OUT6(1) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_581\,
      TX_BIT_CTRL_OUT6(0) => \BITSLICE_CTRL[0].bs_ctrl_inst_n_582\,
      TX_BIT_CTRL_OUT_TRI(39 downto 0) => n0_tx_bit_ctrl_out_tri(39 downto 0),
      VTC_RDY => \^n0_vtc_rdy_out\
    );
\BITSLICE_CTRL[1].bs_ctrl_inst\: unisim.vcomponents.BITSLICE_CONTROL
    generic map(
      CTRL_CLK => "EXTERNAL",
      DIV_MODE => "DIV4",
      EN_CLK_TO_EXT_NORTH => "DISABLE",
      EN_CLK_TO_EXT_SOUTH => "DISABLE",
      EN_DYN_ODLY_MODE => "FALSE",
      EN_OTHER_NCLK => "TRUE",
      EN_OTHER_PCLK => "TRUE",
      IDLY_VT_TRACK => "TRUE",
      INV_RXCLK => "FALSE",
      ODLY_VT_TRACK => "TRUE",
      QDLY_VT_TRACK => "TRUE",
      READ_IDLE_COUNT => B"00" & X"0",
      REFCLK_SRC => "PLLCLK",
      ROUNDING_FACTOR => 16,
      RXGATE_EXTEND => "FALSE",
      RX_CLK_PHASE_N => "SHIFT_0",
      RX_CLK_PHASE_P => "SHIFT_0",
      RX_GATING => "DISABLE",
      SELF_CALIBRATE => "ENABLE",
      SERIAL_MODE => "FALSE",
      SIM_DEVICE => "ULTRASCALE_PLUS_ES1",
      SIM_SPEEDUP => "FAST",
      SIM_VERSION => 2.000000,
      TX_GATING => "DISABLE"
    )
        port map (
      CLK_FROM_EXT => '1',
      CLK_TO_EXT_NORTH => \NLW_BITSLICE_CTRL[1].bs_ctrl_inst_CLK_TO_EXT_NORTH_UNCONNECTED\,
      CLK_TO_EXT_SOUTH => \NLW_BITSLICE_CTRL[1].bs_ctrl_inst_CLK_TO_EXT_SOUTH_UNCONNECTED\,
      DLY_RDY => \BITSLICE_CTRL[1].bs_ctrl_inst_n_2\,
      DYN_DCI(6 downto 0) => \NLW_BITSLICE_CTRL[1].bs_ctrl_inst_DYN_DCI_UNCONNECTED\(6 downto 0),
      EN_VTC => n1_en_vtc_in,
      NCLK_NIBBLE_IN => nclk_nibble_out(0),
      NCLK_NIBBLE_OUT => nclk_nibble_out(1),
      PCLK_NIBBLE_IN => pclk_nibble_out(0),
      PCLK_NIBBLE_OUT => pclk_nibble_out(1),
      PHY_RDCS0(3 downto 0) => B"0000",
      PHY_RDCS1(3 downto 0) => B"0000",
      PHY_RDEN(3 downto 0) => B"1111",
      PHY_WRCS0(3 downto 0) => B"0000",
      PHY_WRCS1(3 downto 0) => B"0000",
      PLL_CLK => pll0_clkoutphy_out,
      REFCLK => '0',
      RIU_ADDR(5 downto 0) => B"000000",
      RIU_CLK => riu_clk,
      RIU_NIBBLE_SEL => '0',
      RIU_RD_DATA(15) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_7\,
      RIU_RD_DATA(14) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_8\,
      RIU_RD_DATA(13) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_9\,
      RIU_RD_DATA(12) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_10\,
      RIU_RD_DATA(11) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_11\,
      RIU_RD_DATA(10) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_12\,
      RIU_RD_DATA(9) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_13\,
      RIU_RD_DATA(8) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_14\,
      RIU_RD_DATA(7) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_15\,
      RIU_RD_DATA(6) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_16\,
      RIU_RD_DATA(5) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_17\,
      RIU_RD_DATA(4) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_18\,
      RIU_RD_DATA(3) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_19\,
      RIU_RD_DATA(2) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_20\,
      RIU_RD_DATA(1) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_21\,
      RIU_RD_DATA(0) => \BITSLICE_CTRL[1].bs_ctrl_inst_n_22\,
      RIU_VALID => \BITSLICE_CTRL[1].bs_ctrl_inst_n_5\,
      RIU_WR_DATA(15 downto 0) => B"0000000000000000",
      RIU_WR_EN => '0',
      RST => bsctrl_rst,
      RX_BIT_CTRL_IN0(39 downto 0) => rx_bs6_rx_bit_ctrl_out(39 downto 0),
      RX_BIT_CTRL_IN1(39 downto 0) => B"0000000000000000000000000000000000000000",
      RX_BIT_CTRL_IN2(39 downto 0) => rx_bs8_rx_bit_ctrl_out(39 downto 0),
      RX_BIT_CTRL_IN3(39 downto 0) => B"0000000000000000000000000000000000000000",
      RX_BIT_CTRL_IN4(39 downto 0) => B"0000000000000000000000000000000000000000",
      RX_BIT_CTRL_IN5(39 downto 0) => B"0000000000000000000000000000000000000000",
      RX_BIT_CTRL_IN6(39 downto 0) => B"0000000000000000000000000000000000000000",
      RX_BIT_CTRL_OUT0(39 downto 0) => n1_rx_bit_ctrl_out0(39 downto 0),
      RX_BIT_CTRL_OUT1(39 downto 0) => n1_rx_bit_ctrl_out1(39 downto 0),
      RX_BIT_CTRL_OUT2(39 downto 0) => n1_rx_bit_ctrl_out2(39 downto 0),
      RX_BIT_CTRL_OUT3(39 downto 0) => n1_rx_bit_ctrl_out3(39 downto 0),
      RX_BIT_CTRL_OUT4(39 downto 0) => n1_rx_bit_ctrl_out4(39 downto 0),
      RX_BIT_CTRL_OUT5(39 downto 0) => n1_rx_bit_ctrl_out5(39 downto 0),
      RX_BIT_CTRL_OUT6(39 downto 0) => n1_rx_bit_ctrl_out6(39 downto 0),
      TBYTE_IN(3 downto 0) => n1_tbyte_in(3 downto 0),
      TX_BIT_CTRL_IN0(39 downto 0) => rx_bs6_tx_bit_ctrl_out(39 downto 0),
      TX_BIT_CTRL_IN1(39 downto 0) => B"0000000000000000000000000000000000000000",
      TX_BIT_CTRL_IN2(39 downto 0) => rx_bs8_tx_bit_ctrl_out(39 downto 0),
      TX_BIT_CTRL_IN3(39 downto 0) => B"0000000000000000000000000000000000000000",
      TX_BIT_CTRL_IN4(39 downto 0) => B"0000000000000000000000000000000000000000",
      TX_BIT_CTRL_IN5(39 downto 0) => B"0000000000000000000000000000000000000000",
      TX_BIT_CTRL_IN6(39 downto 0) => B"0000000000000000000000000000000000000000",
      TX_BIT_CTRL_IN_TRI(39 downto 0) => B"0000000000000000000000000000000000000000",
      TX_BIT_CTRL_OUT0(39 downto 0) => n1_tx_bit_ctrl_out0(39 downto 0),
      TX_BIT_CTRL_OUT1(39 downto 0) => n1_tx_bit_ctrl_out1(39 downto 0),
      TX_BIT_CTRL_OUT2(39 downto 0) => n1_tx_bit_ctrl_out2(39 downto 0),
      TX_BIT_CTRL_OUT3(39 downto 0) => n1_tx_bit_ctrl_out3(39 downto 0),
      TX_BIT_CTRL_OUT4(39 downto 0) => n1_tx_bit_ctrl_out4(39 downto 0),
      TX_BIT_CTRL_OUT5(39 downto 0) => n1_tx_bit_ctrl_out5(39 downto 0),
      TX_BIT_CTRL_OUT6(39 downto 0) => n1_tx_bit_ctrl_out6(39 downto 0),
      TX_BIT_CTRL_OUT_TRI(39 downto 0) => n1_tx_bit_ctrl_out_tri(39 downto 0),
      VTC_RDY => \^n1_vtc_rdy_out\
    );
\CORE_RDY_GEN[0].core_rdy_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \BITSLICE_CTRL[1].bs_ctrl_inst_n_2\,
      I1 => \BITSLICE_CTRL[0].bs_ctrl_inst_n_2\,
      I2 => \^n1_vtc_rdy_out\,
      I3 => \^n0_vtc_rdy_out\,
      O => core_rdy
    );
\GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => Q(0),
      I1 => \^n1_vtc_rdy_out\,
      I2 => \^n0_vtc_rdy_out\,
      O => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[7]\
    );
\GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => \^n1_vtc_rdy_out\,
      I1 => \^n0_vtc_rdy_out\,
      I2 => Q(0),
      O => \BITSLICE_CTRL[1].bs_ctrl_inst_0\
    );
src_data_inferred_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \BITSLICE_CTRL[0].bs_ctrl_inst_n_2\,
      I1 => \BITSLICE_CTRL[1].bs_ctrl_inst_n_2\,
      O => in0(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_clk_scheme is
  port (
    pll0_clkoutphy_out : out STD_LOGIC;
    pll0_locked_out : out STD_LOGIC;
    pll0_clkout0_out : out STD_LOGIC;
    riu_clk : in STD_LOGIC;
    pll0_clkoutphy_en_in : in STD_LOGIC;
    pll0_rst_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_clk_scheme : entity is "high_speed_selectio_wiz_v3_6_10_clk_scheme";
end design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_clk_scheme;

architecture STRUCTURE of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_clk_scheme is
  signal \GEN_PLL_IN_IP_USP.pll0_clkout0\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.pll0_clkout1_buf_n_0\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_10\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_11\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_12\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_13\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_14\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_15\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_16\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_17\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_18\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_19\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_20\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_21\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_22\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_23\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_6\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_8\ : STD_LOGIC;
  signal \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_9\ : STD_LOGIC;
  signal pll0_clkout1 : STD_LOGIC;
  signal \^pll0_locked_out\ : STD_LOGIC;
  signal \NLW_GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_CLKFBIN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_CLKFBOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_CLKOUT0B_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_CLKOUT1B_UNCONNECTED\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \GEN_PLL_IN_IP_USP.pll0_clkout0_buf\ : label is "PRIMITIVE";
  attribute box_type of \GEN_PLL_IN_IP_USP.pll0_clkout1_buf\ : label is "PRIMITIVE";
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst\ : label is "MLO";
  attribute box_type of \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst\ : label is "PRIMITIVE";
begin
  pll0_locked_out <= \^pll0_locked_out\;
\GEN_PLL_IN_IP_USP.pll0_clkout0_buf\: unisim.vcomponents.BUFGCE
    generic map(
      CE_TYPE => "SYNC",
      IS_CE_INVERTED => '0',
      IS_I_INVERTED => '0',
      SIM_DEVICE => "ULTRASCALE",
      STARTUP_SYNC => "FALSE"
    )
        port map (
      CE => \^pll0_locked_out\,
      I => \GEN_PLL_IN_IP_USP.pll0_clkout0\,
      O => pll0_clkout0_out
    );
\GEN_PLL_IN_IP_USP.pll0_clkout1_buf\: unisim.vcomponents.BUFGCE
    generic map(
      CE_TYPE => "SYNC",
      IS_CE_INVERTED => '0',
      IS_I_INVERTED => '0',
      SIM_DEVICE => "ULTRASCALE",
      STARTUP_SYNC => "FALSE"
    )
        port map (
      CE => \^pll0_locked_out\,
      I => pll0_clkout1,
      O => \GEN_PLL_IN_IP_USP.pll0_clkout1_buf_n_0\
    );
\GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst\: unisim.vcomponents.PLLE4_ADV
    generic map(
      CLKFBOUT_MULT => 15,
      CLKFBOUT_PHASE => 0.000000,
      CLKIN_PERIOD => 5.000000,
      CLKOUT0_DIVIDE => 8,
      CLKOUT0_DUTY_CYCLE => 0.500000,
      CLKOUT0_PHASE => 0.000000,
      CLKOUT1_DIVIDE => 1,
      CLKOUT1_DUTY_CYCLE => 0.500000,
      CLKOUT1_PHASE => 0.000000,
      CLKOUTPHY_MODE => "VCO",
      COMPENSATION => "INTERNAL",
      DIVCLK_DIVIDE => 2,
      IS_CLKFBIN_INVERTED => '0',
      IS_CLKIN_INVERTED => '0',
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REF_JITTER => 0.010000,
      STARTUP_WAIT => "FALSE"
    )
        port map (
      CLKFBIN => \NLW_GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_CLKFBIN_UNCONNECTED\,
      CLKFBOUT => \NLW_GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_CLKFBOUT_UNCONNECTED\,
      CLKIN => riu_clk,
      CLKOUT0 => \GEN_PLL_IN_IP_USP.pll0_clkout0\,
      CLKOUT0B => \NLW_GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_CLKOUT0B_UNCONNECTED\,
      CLKOUT1 => pll0_clkout1,
      CLKOUT1B => \NLW_GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_CLKOUT1B_UNCONNECTED\,
      CLKOUTPHY => pll0_clkoutphy_out,
      CLKOUTPHYEN => pll0_clkoutphy_en_in,
      DADDR(6 downto 0) => B"0000000",
      DCLK => '0',
      DEN => '0',
      DI(15 downto 0) => B"0000000000000000",
      DO(15) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_8\,
      DO(14) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_9\,
      DO(13) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_10\,
      DO(12) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_11\,
      DO(11) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_12\,
      DO(10) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_13\,
      DO(9) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_14\,
      DO(8) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_15\,
      DO(7) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_16\,
      DO(6) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_17\,
      DO(5) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_18\,
      DO(4) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_19\,
      DO(3) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_20\,
      DO(2) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_21\,
      DO(1) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_22\,
      DO(0) => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_23\,
      DRDY => \GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst_n_6\,
      DWE => '0',
      LOCKED => \^pll0_locked_out\,
      PWRDWN => '0',
      RST => pll0_rst_in
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_rx_bs is
  port (
    fifo_wr_clk_0 : out STD_LOGIC;
    rx_bs0_rx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs0_tx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    fifo_empty_2 : out STD_LOGIC;
    rx_bs2_rx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs2_tx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    data_to_fabric_data_rxp0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fifo_empty_4 : out STD_LOGIC;
    rx_bs4_rx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs4_tx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    data_to_fabric_data_rxp1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fifo_empty_6 : out STD_LOGIC;
    rx_bs6_rx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs6_tx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    data_to_fabric_data_rxp2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fifo_empty_8 : out STD_LOGIC;
    rx_bs8_rx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs8_tx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    data_to_fabric_data_rxp3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    data_to_bs_out : in STD_LOGIC_VECTOR ( 4 downto 0 );
    fifo_rd_clk_0 : in STD_LOGIC;
    rx_bs_rst_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    rx_bs_rst_dly_ext_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    rx_bs0_rx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs0_tx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    fifo_rd_en_2 : in STD_LOGIC;
    rx_bs2_rx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs2_tx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    fifo_rd_en_4 : in STD_LOGIC;
    rx_bs4_rx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs4_tx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    fifo_rd_en_6 : in STD_LOGIC;
    rx_bs6_rx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs6_tx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    fifo_rd_en_8 : in STD_LOGIC;
    rx_bs8_rx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs8_tx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_rx_bs : entity is "high_speed_selectio_wiz_v3_6_10_rx_bs";
end design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_rx_bs;

architecture STRUCTURE of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_rx_bs is
  signal \RX_BS[0].rx_bitslice_if_bs_n_0\ : STD_LOGIC;
  signal \RX_BS[0].rx_bitslice_if_bs_n_82\ : STD_LOGIC;
  signal \RX_BS[0].rx_bitslice_if_bs_n_83\ : STD_LOGIC;
  signal \RX_BS[0].rx_bitslice_if_bs_n_84\ : STD_LOGIC;
  signal \RX_BS[0].rx_bitslice_if_bs_n_85\ : STD_LOGIC;
  signal \RX_BS[0].rx_bitslice_if_bs_n_86\ : STD_LOGIC;
  signal \RX_BS[0].rx_bitslice_if_bs_n_87\ : STD_LOGIC;
  signal \RX_BS[0].rx_bitslice_if_bs_n_88\ : STD_LOGIC;
  signal \RX_BS[0].rx_bitslice_if_bs_n_89\ : STD_LOGIC;
  signal \NLW_RX_BS[0].rx_bitslice_if_bs_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_RX_BS[0].rx_bitslice_if_bs_CNTVALUEOUT_EXT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_RX_BS[2].rx_bitslice_if_bs_FIFO_WRCLK_OUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_RX_BS[2].rx_bitslice_if_bs_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_RX_BS[2].rx_bitslice_if_bs_CNTVALUEOUT_EXT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_RX_BS[4].rx_bitslice_if_bs_FIFO_WRCLK_OUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_RX_BS[4].rx_bitslice_if_bs_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_RX_BS[4].rx_bitslice_if_bs_CNTVALUEOUT_EXT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_RX_BS[6].rx_bitslice_if_bs_FIFO_WRCLK_OUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_RX_BS[6].rx_bitslice_if_bs_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_RX_BS[6].rx_bitslice_if_bs_CNTVALUEOUT_EXT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_RX_BS[8].rx_bitslice_if_bs_FIFO_WRCLK_OUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_RX_BS[8].rx_bitslice_if_bs_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_RX_BS[8].rx_bitslice_if_bs_CNTVALUEOUT_EXT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \RX_BS[0].rx_bitslice_if_bs\ : label is "PRIMITIVE";
  attribute box_type of \RX_BS[2].rx_bitslice_if_bs\ : label is "PRIMITIVE";
  attribute box_type of \RX_BS[4].rx_bitslice_if_bs\ : label is "PRIMITIVE";
  attribute box_type of \RX_BS[6].rx_bitslice_if_bs\ : label is "PRIMITIVE";
  attribute box_type of \RX_BS[8].rx_bitslice_if_bs\ : label is "PRIMITIVE";
begin
\RX_BS[0].rx_bitslice_if_bs\: unisim.vcomponents.RX_BITSLICE
    generic map(
      CASCADE => "FALSE",
      DATA_TYPE => "DATA_AND_CLOCK",
      DATA_WIDTH => 8,
      DELAY_FORMAT => "TIME",
      DELAY_TYPE => "FIXED",
      DELAY_VALUE => 0,
      DELAY_VALUE_EXT => 0,
      FIFO_SYNC_MODE => "FALSE",
      IS_CLK_EXT_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_RST_DLY_EXT_INVERTED => '0',
      IS_RST_DLY_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REFCLK_FREQUENCY => 1500.000000,
      SIM_DEVICE => "ULTRASCALE_PLUS_ES1",
      SIM_VERSION => 2.000000,
      UPDATE_MODE => "ASYNC",
      UPDATE_MODE_EXT => "ASYNC"
    )
        port map (
      CE => '0',
      CE_EXT => '0',
      CLK => '0',
      CLK_EXT => '0',
      CNTVALUEIN(8 downto 0) => B"000000000",
      CNTVALUEIN_EXT(8 downto 0) => B"000000000",
      CNTVALUEOUT(8 downto 0) => \NLW_RX_BS[0].rx_bitslice_if_bs_CNTVALUEOUT_UNCONNECTED\(8 downto 0),
      CNTVALUEOUT_EXT(8 downto 0) => \NLW_RX_BS[0].rx_bitslice_if_bs_CNTVALUEOUT_EXT_UNCONNECTED\(8 downto 0),
      DATAIN => data_to_bs_out(0),
      EN_VTC => '1',
      EN_VTC_EXT => '1',
      FIFO_EMPTY => \RX_BS[0].rx_bitslice_if_bs_n_0\,
      FIFO_RD_CLK => fifo_rd_clk_0,
      FIFO_RD_EN => '1',
      FIFO_WRCLK_OUT => fifo_wr_clk_0,
      INC => '0',
      INC_EXT => '0',
      LOAD => '0',
      LOAD_EXT => '0',
      Q(7) => \RX_BS[0].rx_bitslice_if_bs_n_82\,
      Q(6) => \RX_BS[0].rx_bitslice_if_bs_n_83\,
      Q(5) => \RX_BS[0].rx_bitslice_if_bs_n_84\,
      Q(4) => \RX_BS[0].rx_bitslice_if_bs_n_85\,
      Q(3) => \RX_BS[0].rx_bitslice_if_bs_n_86\,
      Q(2) => \RX_BS[0].rx_bitslice_if_bs_n_87\,
      Q(1) => \RX_BS[0].rx_bitslice_if_bs_n_88\,
      Q(0) => \RX_BS[0].rx_bitslice_if_bs_n_89\,
      RST => rx_bs_rst_in(0),
      RST_DLY => rx_bs_rst_dly_ext_in(0),
      RST_DLY_EXT => rx_bs_rst_dly_ext_in(0),
      RX_BIT_CTRL_IN(39 downto 0) => rx_bs0_rx_bit_ctrl_in(39 downto 0),
      RX_BIT_CTRL_OUT(39 downto 0) => rx_bs0_rx_bit_ctrl_out(39 downto 0),
      TX_BIT_CTRL_IN(39 downto 0) => rx_bs0_tx_bit_ctrl_in(39 downto 0),
      TX_BIT_CTRL_OUT(39 downto 0) => rx_bs0_tx_bit_ctrl_out(39 downto 0)
    );
\RX_BS[2].rx_bitslice_if_bs\: unisim.vcomponents.RX_BITSLICE
    generic map(
      CASCADE => "FALSE",
      DATA_TYPE => "DATA",
      DATA_WIDTH => 8,
      DELAY_FORMAT => "TIME",
      DELAY_TYPE => "FIXED",
      DELAY_VALUE => 0,
      DELAY_VALUE_EXT => 0,
      FIFO_SYNC_MODE => "FALSE",
      IS_CLK_EXT_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_RST_DLY_EXT_INVERTED => '0',
      IS_RST_DLY_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REFCLK_FREQUENCY => 1500.000000,
      SIM_DEVICE => "ULTRASCALE_PLUS_ES1",
      SIM_VERSION => 2.000000,
      UPDATE_MODE => "ASYNC",
      UPDATE_MODE_EXT => "ASYNC"
    )
        port map (
      CE => '0',
      CE_EXT => '0',
      CLK => '0',
      CLK_EXT => '0',
      CNTVALUEIN(8 downto 0) => B"000000000",
      CNTVALUEIN_EXT(8 downto 0) => B"000000000",
      CNTVALUEOUT(8 downto 0) => \NLW_RX_BS[2].rx_bitslice_if_bs_CNTVALUEOUT_UNCONNECTED\(8 downto 0),
      CNTVALUEOUT_EXT(8 downto 0) => \NLW_RX_BS[2].rx_bitslice_if_bs_CNTVALUEOUT_EXT_UNCONNECTED\(8 downto 0),
      DATAIN => data_to_bs_out(1),
      EN_VTC => '1',
      EN_VTC_EXT => '1',
      FIFO_EMPTY => fifo_empty_2,
      FIFO_RD_CLK => fifo_rd_clk_0,
      FIFO_RD_EN => fifo_rd_en_2,
      FIFO_WRCLK_OUT => \NLW_RX_BS[2].rx_bitslice_if_bs_FIFO_WRCLK_OUT_UNCONNECTED\,
      INC => '0',
      INC_EXT => '0',
      LOAD => '0',
      LOAD_EXT => '0',
      Q(7 downto 0) => data_to_fabric_data_rxp0(7 downto 0),
      RST => rx_bs_rst_in(1),
      RST_DLY => rx_bs_rst_dly_ext_in(1),
      RST_DLY_EXT => rx_bs_rst_dly_ext_in(1),
      RX_BIT_CTRL_IN(39 downto 0) => rx_bs2_rx_bit_ctrl_in(39 downto 0),
      RX_BIT_CTRL_OUT(39 downto 0) => rx_bs2_rx_bit_ctrl_out(39 downto 0),
      TX_BIT_CTRL_IN(39 downto 0) => rx_bs2_tx_bit_ctrl_in(39 downto 0),
      TX_BIT_CTRL_OUT(39 downto 0) => rx_bs2_tx_bit_ctrl_out(39 downto 0)
    );
\RX_BS[4].rx_bitslice_if_bs\: unisim.vcomponents.RX_BITSLICE
    generic map(
      CASCADE => "FALSE",
      DATA_TYPE => "DATA",
      DATA_WIDTH => 8,
      DELAY_FORMAT => "TIME",
      DELAY_TYPE => "FIXED",
      DELAY_VALUE => 0,
      DELAY_VALUE_EXT => 0,
      FIFO_SYNC_MODE => "FALSE",
      IS_CLK_EXT_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_RST_DLY_EXT_INVERTED => '0',
      IS_RST_DLY_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REFCLK_FREQUENCY => 1500.000000,
      SIM_DEVICE => "ULTRASCALE_PLUS_ES1",
      SIM_VERSION => 2.000000,
      UPDATE_MODE => "ASYNC",
      UPDATE_MODE_EXT => "ASYNC"
    )
        port map (
      CE => '0',
      CE_EXT => '0',
      CLK => '0',
      CLK_EXT => '0',
      CNTVALUEIN(8 downto 0) => B"000000000",
      CNTVALUEIN_EXT(8 downto 0) => B"000000000",
      CNTVALUEOUT(8 downto 0) => \NLW_RX_BS[4].rx_bitslice_if_bs_CNTVALUEOUT_UNCONNECTED\(8 downto 0),
      CNTVALUEOUT_EXT(8 downto 0) => \NLW_RX_BS[4].rx_bitslice_if_bs_CNTVALUEOUT_EXT_UNCONNECTED\(8 downto 0),
      DATAIN => data_to_bs_out(2),
      EN_VTC => '1',
      EN_VTC_EXT => '1',
      FIFO_EMPTY => fifo_empty_4,
      FIFO_RD_CLK => fifo_rd_clk_0,
      FIFO_RD_EN => fifo_rd_en_4,
      FIFO_WRCLK_OUT => \NLW_RX_BS[4].rx_bitslice_if_bs_FIFO_WRCLK_OUT_UNCONNECTED\,
      INC => '0',
      INC_EXT => '0',
      LOAD => '0',
      LOAD_EXT => '0',
      Q(7 downto 0) => data_to_fabric_data_rxp1(7 downto 0),
      RST => rx_bs_rst_in(2),
      RST_DLY => rx_bs_rst_dly_ext_in(2),
      RST_DLY_EXT => rx_bs_rst_dly_ext_in(2),
      RX_BIT_CTRL_IN(39 downto 0) => rx_bs4_rx_bit_ctrl_in(39 downto 0),
      RX_BIT_CTRL_OUT(39 downto 0) => rx_bs4_rx_bit_ctrl_out(39 downto 0),
      TX_BIT_CTRL_IN(39 downto 0) => rx_bs4_tx_bit_ctrl_in(39 downto 0),
      TX_BIT_CTRL_OUT(39 downto 0) => rx_bs4_tx_bit_ctrl_out(39 downto 0)
    );
\RX_BS[6].rx_bitslice_if_bs\: unisim.vcomponents.RX_BITSLICE
    generic map(
      CASCADE => "FALSE",
      DATA_TYPE => "DATA",
      DATA_WIDTH => 8,
      DELAY_FORMAT => "TIME",
      DELAY_TYPE => "FIXED",
      DELAY_VALUE => 0,
      DELAY_VALUE_EXT => 0,
      FIFO_SYNC_MODE => "FALSE",
      IS_CLK_EXT_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_RST_DLY_EXT_INVERTED => '0',
      IS_RST_DLY_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REFCLK_FREQUENCY => 1500.000000,
      SIM_DEVICE => "ULTRASCALE_PLUS_ES1",
      SIM_VERSION => 2.000000,
      UPDATE_MODE => "ASYNC",
      UPDATE_MODE_EXT => "ASYNC"
    )
        port map (
      CE => '0',
      CE_EXT => '0',
      CLK => '0',
      CLK_EXT => '0',
      CNTVALUEIN(8 downto 0) => B"000000000",
      CNTVALUEIN_EXT(8 downto 0) => B"000000000",
      CNTVALUEOUT(8 downto 0) => \NLW_RX_BS[6].rx_bitslice_if_bs_CNTVALUEOUT_UNCONNECTED\(8 downto 0),
      CNTVALUEOUT_EXT(8 downto 0) => \NLW_RX_BS[6].rx_bitslice_if_bs_CNTVALUEOUT_EXT_UNCONNECTED\(8 downto 0),
      DATAIN => data_to_bs_out(3),
      EN_VTC => '1',
      EN_VTC_EXT => '1',
      FIFO_EMPTY => fifo_empty_6,
      FIFO_RD_CLK => fifo_rd_clk_0,
      FIFO_RD_EN => fifo_rd_en_6,
      FIFO_WRCLK_OUT => \NLW_RX_BS[6].rx_bitslice_if_bs_FIFO_WRCLK_OUT_UNCONNECTED\,
      INC => '0',
      INC_EXT => '0',
      LOAD => '0',
      LOAD_EXT => '0',
      Q(7 downto 0) => data_to_fabric_data_rxp2(7 downto 0),
      RST => rx_bs_rst_in(3),
      RST_DLY => rx_bs_rst_dly_ext_in(3),
      RST_DLY_EXT => rx_bs_rst_dly_ext_in(3),
      RX_BIT_CTRL_IN(39 downto 0) => rx_bs6_rx_bit_ctrl_in(39 downto 0),
      RX_BIT_CTRL_OUT(39 downto 0) => rx_bs6_rx_bit_ctrl_out(39 downto 0),
      TX_BIT_CTRL_IN(39 downto 0) => rx_bs6_tx_bit_ctrl_in(39 downto 0),
      TX_BIT_CTRL_OUT(39 downto 0) => rx_bs6_tx_bit_ctrl_out(39 downto 0)
    );
\RX_BS[8].rx_bitslice_if_bs\: unisim.vcomponents.RX_BITSLICE
    generic map(
      CASCADE => "FALSE",
      DATA_TYPE => "DATA",
      DATA_WIDTH => 8,
      DELAY_FORMAT => "TIME",
      DELAY_TYPE => "FIXED",
      DELAY_VALUE => 0,
      DELAY_VALUE_EXT => 0,
      FIFO_SYNC_MODE => "FALSE",
      IS_CLK_EXT_INVERTED => '0',
      IS_CLK_INVERTED => '0',
      IS_RST_DLY_EXT_INVERTED => '0',
      IS_RST_DLY_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REFCLK_FREQUENCY => 1500.000000,
      SIM_DEVICE => "ULTRASCALE_PLUS_ES1",
      SIM_VERSION => 2.000000,
      UPDATE_MODE => "ASYNC",
      UPDATE_MODE_EXT => "ASYNC"
    )
        port map (
      CE => '0',
      CE_EXT => '0',
      CLK => '0',
      CLK_EXT => '0',
      CNTVALUEIN(8 downto 0) => B"000000000",
      CNTVALUEIN_EXT(8 downto 0) => B"000000000",
      CNTVALUEOUT(8 downto 0) => \NLW_RX_BS[8].rx_bitslice_if_bs_CNTVALUEOUT_UNCONNECTED\(8 downto 0),
      CNTVALUEOUT_EXT(8 downto 0) => \NLW_RX_BS[8].rx_bitslice_if_bs_CNTVALUEOUT_EXT_UNCONNECTED\(8 downto 0),
      DATAIN => data_to_bs_out(4),
      EN_VTC => '1',
      EN_VTC_EXT => '1',
      FIFO_EMPTY => fifo_empty_8,
      FIFO_RD_CLK => fifo_rd_clk_0,
      FIFO_RD_EN => fifo_rd_en_8,
      FIFO_WRCLK_OUT => \NLW_RX_BS[8].rx_bitslice_if_bs_FIFO_WRCLK_OUT_UNCONNECTED\,
      INC => '0',
      INC_EXT => '0',
      LOAD => '0',
      LOAD_EXT => '0',
      Q(7 downto 0) => data_to_fabric_data_rxp3(7 downto 0),
      RST => rx_bs_rst_in(4),
      RST_DLY => rx_bs_rst_dly_ext_in(4),
      RST_DLY_EXT => rx_bs_rst_dly_ext_in(4),
      RX_BIT_CTRL_IN(39 downto 0) => rx_bs8_rx_bit_ctrl_in(39 downto 0),
      RX_BIT_CTRL_OUT(39 downto 0) => rx_bs8_rx_bit_ctrl_out(39 downto 0),
      TX_BIT_CTRL_IN(39 downto 0) => rx_bs8_tx_bit_ctrl_in(39 downto 0),
      TX_BIT_CTRL_OUT(39 downto 0) => rx_bs8_tx_bit_ctrl_out(39 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell is
  port (
    \out\ : in STD_LOGIC;
    CLK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell : entity is "high_speed_selectio_wiz_v3_6_10_sync_cell";
end design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell;

architecture STRUCTURE of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell is
  signal sync_flop_0 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of sync_flop_0 : signal is "true";
  signal sync_flop_1 : STD_LOGIC;
  attribute async_reg of sync_flop_1 : signal is "true";
  signal sync_flop_2 : STD_LOGIC;
  attribute async_reg of sync_flop_2 : signal is "true";
  signal sync_flop_3 : STD_LOGIC;
  attribute async_reg of sync_flop_3 : signal is "true";
  signal sync_flop_4 : STD_LOGIC;
  attribute async_reg of sync_flop_4 : signal is "true";
  signal sync_flop_5 : STD_LOGIC;
  attribute async_reg of sync_flop_5 : signal is "true";
  signal sync_flop_6 : STD_LOGIC;
  attribute async_reg of sync_flop_6 : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \sync_flop_0_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \sync_flop_0_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_3_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_3_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_4_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_4_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_5_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_5_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_6_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_6_reg[0]\ : label is "yes";
begin
\sync_flop_0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \out\,
      Q => sync_flop_0,
      R => '0'
    );
\sync_flop_1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sync_flop_0,
      Q => sync_flop_1,
      R => '0'
    );
\sync_flop_2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sync_flop_1,
      Q => sync_flop_2,
      R => '0'
    );
\sync_flop_3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sync_flop_2,
      Q => sync_flop_3,
      R => '0'
    );
\sync_flop_4_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sync_flop_3,
      Q => sync_flop_4,
      R => '0'
    );
\sync_flop_5_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sync_flop_4,
      Q => sync_flop_5,
      R => '0'
    );
\sync_flop_6_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sync_flop_5,
      Q => sync_flop_6,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_217 is
  port (
    SS : out STD_LOGIC_VECTOR ( 0 to 0 );
    bs_rst_dphy_in : in STD_LOGIC;
    riu_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_217 : entity is "high_speed_selectio_wiz_v3_6_10_sync_cell";
end design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_217;

architecture STRUCTURE of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_217 is
  signal sync_flop_0 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of sync_flop_0 : signal is "true";
  signal sync_flop_1 : STD_LOGIC;
  attribute async_reg of sync_flop_1 : signal is "true";
  signal sync_flop_2 : STD_LOGIC;
  attribute async_reg of sync_flop_2 : signal is "true";
  signal sync_flop_3 : STD_LOGIC;
  attribute async_reg of sync_flop_3 : signal is "true";
  signal sync_flop_4 : STD_LOGIC;
  attribute async_reg of sync_flop_4 : signal is "true";
  signal sync_flop_5 : STD_LOGIC;
  attribute async_reg of sync_flop_5 : signal is "true";
  signal sync_flop_6 : STD_LOGIC;
  attribute async_reg of sync_flop_6 : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \sync_flop_0_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \sync_flop_0_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_3_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_3_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_4_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_4_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_5_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_5_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_6_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_6_reg[0]\ : label is "yes";
begin
  SS(0) <= sync_flop_1;
\sync_flop_0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_dphy_in,
      Q => sync_flop_0,
      R => '0'
    );
\sync_flop_1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_0,
      Q => sync_flop_1,
      R => '0'
    );
\sync_flop_2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_1,
      Q => sync_flop_2,
      R => '0'
    );
\sync_flop_3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_2,
      Q => sync_flop_3,
      R => '0'
    );
\sync_flop_4_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_3,
      Q => sync_flop_4,
      R => '0'
    );
\sync_flop_5_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_4,
      Q => sync_flop_5,
      R => '0'
    );
\sync_flop_6_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_5,
      Q => sync_flop_6,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_218 is
  port (
    \out\ : out STD_LOGIC;
    \sync_flop_1_reg[0]_0\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    riu_clk : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[6]\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[6]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_218 : entity is "high_speed_selectio_wiz_v3_6_10_sync_cell";
end design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_218;

architecture STRUCTURE of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_218 is
  signal sync_flop_0 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of sync_flop_0 : signal is "true";
  signal sync_flop_1 : STD_LOGIC;
  attribute async_reg of sync_flop_1 : signal is "true";
  signal sync_flop_2 : STD_LOGIC;
  attribute async_reg of sync_flop_2 : signal is "true";
  signal sync_flop_3 : STD_LOGIC;
  attribute async_reg of sync_flop_3 : signal is "true";
  signal sync_flop_4 : STD_LOGIC;
  attribute async_reg of sync_flop_4 : signal is "true";
  signal sync_flop_5 : STD_LOGIC;
  attribute async_reg of sync_flop_5 : signal is "true";
  signal sync_flop_6 : STD_LOGIC;
  attribute async_reg of sync_flop_6 : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \sync_flop_0_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \sync_flop_0_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_3_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_3_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_4_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_4_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_5_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_5_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_6_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_6_reg[0]\ : label is "yes";
begin
  \out\ <= sync_flop_1;
\GEN_RIU_NOT_FROM_PLL.hssio_state[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => sync_flop_1,
      I1 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[6]_0\,
      I2 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[6]\,
      I3 => Q(1),
      O => D(0)
    );
\GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF80CC808080CC"
    )
        port map (
      I0 => sync_flop_1,
      I1 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[6]\,
      I2 => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg\,
      I3 => Q(2),
      I4 => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\,
      I5 => Q(0),
      O => \sync_flop_1_reg[0]_0\
    );
\sync_flop_0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => in0(0),
      Q => sync_flop_0,
      R => '0'
    );
\sync_flop_1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_0,
      Q => sync_flop_1,
      R => '0'
    );
\sync_flop_2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_1,
      Q => sync_flop_2,
      R => '0'
    );
\sync_flop_3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_2,
      Q => sync_flop_3,
      R => '0'
    );
\sync_flop_4_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_3,
      Q => sync_flop_4,
      R => '0'
    );
\sync_flop_5_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_4,
      Q => sync_flop_5,
      R => '0'
    );
\sync_flop_6_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_5,
      Q => sync_flop_6,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_219 is
  port (
    riu_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_219 : entity is "high_speed_selectio_wiz_v3_6_10_sync_cell";
end design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_219;

architecture STRUCTURE of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_219 is
  signal n_0_0 : STD_LOGIC;
  signal sync_flop_0 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of sync_flop_0 : signal is "true";
  signal sync_flop_1 : STD_LOGIC;
  attribute async_reg of sync_flop_1 : signal is "true";
  signal sync_flop_2 : STD_LOGIC;
  attribute async_reg of sync_flop_2 : signal is "true";
  signal sync_flop_3 : STD_LOGIC;
  attribute async_reg of sync_flop_3 : signal is "true";
  signal sync_flop_4 : STD_LOGIC;
  attribute async_reg of sync_flop_4 : signal is "true";
  signal sync_flop_5 : STD_LOGIC;
  attribute async_reg of sync_flop_5 : signal is "true";
  signal sync_flop_6 : STD_LOGIC;
  attribute async_reg of sync_flop_6 : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \sync_flop_0_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \sync_flop_0_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_3_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_3_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_4_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_4_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_5_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_5_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_6_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_6_reg[0]\ : label is "yes";
begin
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_0
    );
\sync_flop_0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => n_0_0,
      Q => sync_flop_0,
      R => '0'
    );
\sync_flop_1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_0,
      Q => sync_flop_1,
      R => '0'
    );
\sync_flop_2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_1,
      Q => sync_flop_2,
      R => '0'
    );
\sync_flop_3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_2,
      Q => sync_flop_3,
      R => '0'
    );
\sync_flop_4_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_3,
      Q => sync_flop_4,
      R => '0'
    );
\sync_flop_5_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_4,
      Q => sync_flop_5,
      R => '0'
    );
\sync_flop_6_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_5,
      Q => sync_flop_6,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_220 is
  port (
    \out\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sync_flop_1_reg[0]_0\ : out STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg\ : out STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[6]\ : out STD_LOGIC;
    \sync_flop_1_reg[0]_1\ : out STD_LOGIC;
    \sync_flop_1_reg[0]_2\ : out STD_LOGIC;
    pll0_locked_out : in STD_LOGIC;
    riu_clk : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
    n1_vtc_rdy_out : in STD_LOGIC;
    n0_vtc_rdy_out : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[7]\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_1\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[3]\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[4]\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[2]\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[0]\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_2\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_3\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_4\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_5\ : in STD_LOGIC;
    timeout_cntr_rst : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_reg\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_reg_0\ : in STD_LOGIC;
    bsc_en_vtc : in STD_LOGIC;
    rst_seq_done : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.rst_seq_done_reg\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.rst_seq_done_reg_0\ : in STD_LOGIC;
    bs_dly_rst : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.bs_dly_rst_reg\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.bs_dly_rst_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_220 : entity is "high_speed_selectio_wiz_v3_6_10_sync_cell";
end design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_220;

architecture STRUCTURE of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_220 is
  signal \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_4_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.hssio_state[0]_i_2_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.hssio_state[8]_i_2_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_3_n_0\ : STD_LOGIC;
  signal sync_flop_0 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of sync_flop_0 : signal is "true";
  signal sync_flop_1 : STD_LOGIC;
  attribute async_reg of sync_flop_1 : signal is "true";
  signal sync_flop_2 : STD_LOGIC;
  attribute async_reg of sync_flop_2 : signal is "true";
  signal sync_flop_3 : STD_LOGIC;
  attribute async_reg of sync_flop_3 : signal is "true";
  signal sync_flop_4 : STD_LOGIC;
  attribute async_reg of sync_flop_4 : signal is "true";
  signal sync_flop_5 : STD_LOGIC;
  attribute async_reg of sync_flop_5 : signal is "true";
  signal sync_flop_6 : STD_LOGIC;
  attribute async_reg of sync_flop_6 : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \sync_flop_0_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \sync_flop_0_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_3_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_3_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_4_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_4_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_5_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_5_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_6_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_6_reg[0]\ : label is "yes";
begin
  \out\ <= sync_flop_1;
\GEN_RIU_NOT_FROM_PLL.bs_dly_rst_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAFFEFAAAA0020"
    )
        port map (
      I0 => bs_dly_rst,
      I1 => \GEN_RIU_NOT_FROM_PLL.bs_dly_rst_reg\,
      I2 => sync_flop_1,
      I3 => Q(8),
      I4 => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_reg\,
      I5 => \GEN_RIU_NOT_FROM_PLL.bs_dly_rst_reg_0\,
      O => \sync_flop_1_reg[0]_2\
    );
\GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAFFEFAAAA0020"
    )
        port map (
      I0 => Q(6),
      I1 => \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_reg\,
      I2 => Q(0),
      I3 => \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_reg_0\,
      I4 => \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_4_n_0\,
      I5 => bsc_en_vtc,
      O => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[6]\
    );
\GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000000000"
    )
        port map (
      I0 => sync_flop_1,
      I1 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[7]\,
      I2 => Q(4),
      I3 => Q(6),
      I4 => Q(2),
      I5 => \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg\,
      O => \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_4_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFAFAFAFFFFFFFEF"
    )
        port map (
      I0 => \GEN_RIU_NOT_FROM_PLL.hssio_state[0]_i_2_n_0\,
      I1 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[0]\,
      I2 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[3]\,
      I3 => Q(6),
      I4 => Q(4),
      I5 => sync_flop_1,
      O => D(0)
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4040FFFF4040FF40"
    )
        port map (
      I0 => sync_flop_1,
      I1 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[2]\,
      I2 => Q(2),
      I3 => Q(7),
      I4 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[7]\,
      I5 => Q(6),
      O => \GEN_RIU_NOT_FROM_PLL.hssio_state[0]_i_2_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AB00AA00"
    )
        port map (
      I0 => Q(1),
      I1 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[2]\,
      I2 => sync_flop_1,
      I3 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[3]\,
      I4 => Q(2),
      O => D(1)
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => sync_flop_1,
      I1 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[3]\,
      I2 => Q(2),
      O => D(2)
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080C080"
    )
        port map (
      I0 => Q(3),
      I1 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[3]\,
      I2 => sync_flop_1,
      I3 => Q(4),
      I4 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[4]\,
      O => D(3)
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFAA000000000000"
    )
        port map (
      I0 => Q(6),
      I1 => n1_vtc_rdy_out,
      I2 => n0_vtc_rdy_out,
      I3 => Q(7),
      I4 => \GEN_RIU_NOT_FROM_PLL.hssio_state[8]_i_2_n_0\,
      I5 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[7]\,
      O => D(4)
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C888888888888888"
    )
        port map (
      I0 => Q(8),
      I1 => \GEN_RIU_NOT_FROM_PLL.hssio_state[8]_i_2_n_0\,
      I2 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[7]\,
      I3 => Q(7),
      I4 => n1_vtc_rdy_out,
      I5 => n0_vtc_rdy_out,
      O => D(5)
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state[8]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[3]\,
      I1 => sync_flop_1,
      O => \GEN_RIU_NOT_FROM_PLL.hssio_state[8]_i_2_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AABFAA80"
    )
        port map (
      I0 => rst_seq_done,
      I1 => sync_flop_1,
      I2 => Q(8),
      I3 => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_reg\,
      I4 => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_reg_0\,
      O => \sync_flop_1_reg[0]_1\
    );
\GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200000"
    )
        port map (
      I0 => sync_flop_1,
      I1 => Q(6),
      I2 => Q(4),
      I3 => Q(2),
      I4 => \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg\,
      O => \sync_flop_1_reg[0]_0\
    );
\GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFFFEFEFE00"
    )
        port map (
      I0 => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_2\,
      I1 => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_3_n_0\,
      I2 => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_3\,
      I3 => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_4\,
      I4 => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_5\,
      I5 => timeout_cntr_rst,
      O => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg\
    );
\GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\,
      I1 => sync_flop_1,
      I2 => Q(2),
      I3 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[7]\,
      I4 => Q(5),
      I5 => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_1\,
      O => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_3_n_0\
    );
\sync_flop_0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => pll0_locked_out,
      Q => sync_flop_0,
      R => '0'
    );
\sync_flop_1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_0,
      Q => sync_flop_1,
      R => '0'
    );
\sync_flop_2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_1,
      Q => sync_flop_2,
      R => '0'
    );
\sync_flop_3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_2,
      Q => sync_flop_3,
      R => '0'
    );
\sync_flop_4_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_3,
      Q => sync_flop_4,
      R => '0'
    );
\sync_flop_5_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_4,
      Q => sync_flop_5,
      R => '0'
    );
\sync_flop_6_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_5,
      Q => sync_flop_6,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_221 is
  port (
    \out\ : out STD_LOGIC;
    rst : in STD_LOGIC;
    riu_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_221 : entity is "high_speed_selectio_wiz_v3_6_10_sync_cell";
end design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_221;

architecture STRUCTURE of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_221 is
  signal sync_flop_0 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of sync_flop_0 : signal is "true";
  signal sync_flop_1 : STD_LOGIC;
  attribute async_reg of sync_flop_1 : signal is "true";
  signal sync_flop_2 : STD_LOGIC;
  attribute async_reg of sync_flop_2 : signal is "true";
  signal sync_flop_3 : STD_LOGIC;
  attribute async_reg of sync_flop_3 : signal is "true";
  signal sync_flop_4 : STD_LOGIC;
  attribute async_reg of sync_flop_4 : signal is "true";
  signal sync_flop_5 : STD_LOGIC;
  attribute async_reg of sync_flop_5 : signal is "true";
  signal sync_flop_6 : STD_LOGIC;
  attribute async_reg of sync_flop_6 : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \sync_flop_0_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \sync_flop_0_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_3_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_3_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_4_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_4_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_5_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_5_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_6_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_6_reg[0]\ : label is "yes";
begin
  \out\ <= sync_flop_1;
\sync_flop_0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => rst,
      Q => sync_flop_0,
      R => '0'
    );
\sync_flop_1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_0,
      Q => sync_flop_1,
      R => '0'
    );
\sync_flop_2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_1,
      Q => sync_flop_2,
      R => '0'
    );
\sync_flop_3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_2,
      Q => sync_flop_3,
      R => '0'
    );
\sync_flop_4_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_3,
      Q => sync_flop_4,
      R => '0'
    );
\sync_flop_5_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_4,
      Q => sync_flop_5,
      R => '0'
    );
\sync_flop_6_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_5,
      Q => sync_flop_6,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_222 is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pll0_fab_clk_cntr_reg[0]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_222 : entity is "high_speed_selectio_wiz_v3_6_10_sync_cell";
end design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_222;

architecture STRUCTURE of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_222 is
  signal sync_flop_0 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of sync_flop_0 : signal is "true";
  signal sync_flop_1 : STD_LOGIC;
  attribute async_reg of sync_flop_1 : signal is "true";
  signal sync_flop_2 : STD_LOGIC;
  attribute async_reg of sync_flop_2 : signal is "true";
  signal sync_flop_3 : STD_LOGIC;
  attribute async_reg of sync_flop_3 : signal is "true";
  signal sync_flop_4 : STD_LOGIC;
  attribute async_reg of sync_flop_4 : signal is "true";
  signal sync_flop_5 : STD_LOGIC;
  attribute async_reg of sync_flop_5 : signal is "true";
  signal sync_flop_6 : STD_LOGIC;
  attribute async_reg of sync_flop_6 : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \sync_flop_0_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \sync_flop_0_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_3_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_3_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_4_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_4_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_5_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_5_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_6_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_6_reg[0]\ : label is "yes";
begin
\pll0_fab_clk_cntr[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"5D"
    )
        port map (
      I0 => sync_flop_1,
      I1 => Q(0),
      I2 => \pll0_fab_clk_cntr_reg[0]\,
      O => SR(0)
    );
\sync_flop_0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => in0(0),
      Q => sync_flop_0,
      R => '0'
    );
\sync_flop_1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sync_flop_0,
      Q => sync_flop_1,
      R => '0'
    );
\sync_flop_2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sync_flop_1,
      Q => sync_flop_2,
      R => '0'
    );
\sync_flop_3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sync_flop_2,
      Q => sync_flop_3,
      R => '0'
    );
\sync_flop_4_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sync_flop_3,
      Q => sync_flop_4,
      R => '0'
    );
\sync_flop_5_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sync_flop_4,
      Q => sync_flop_5,
      R => '0'
    );
\sync_flop_6_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sync_flop_5,
      Q => sync_flop_6,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_223 is
  port (
    \out\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[3]\ : out STD_LOGIC;
    \sync_flop_1_reg[0]_0\ : out STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[4]\ : out STD_LOGIC;
    in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    riu_clk : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[5]\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.pll0_clkoutphy_en_reg\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[5]_0\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.pll0_clkoutphy_en_reg_0\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.pll0_clkoutphy_en_reg_1\ : in STD_LOGIC;
    pll0_clkoutphy_en_in : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg_0\ : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_223 : entity is "high_speed_selectio_wiz_v3_6_10_sync_cell";
end design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_223;

architecture STRUCTURE of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_223 is
  signal pll0_clkoutphy_en : STD_LOGIC;
  signal sync_flop_0 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of sync_flop_0 : signal is "true";
  signal sync_flop_1 : STD_LOGIC;
  attribute async_reg of sync_flop_1 : signal is "true";
  signal sync_flop_2 : STD_LOGIC;
  attribute async_reg of sync_flop_2 : signal is "true";
  signal sync_flop_3 : STD_LOGIC;
  attribute async_reg of sync_flop_3 : signal is "true";
  signal sync_flop_4 : STD_LOGIC;
  attribute async_reg of sync_flop_4 : signal is "true";
  signal sync_flop_5 : STD_LOGIC;
  attribute async_reg of sync_flop_5 : signal is "true";
  signal sync_flop_6 : STD_LOGIC;
  attribute async_reg of sync_flop_6 : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \sync_flop_0_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \sync_flop_0_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_3_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_3_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_4_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_4_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_5_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_5_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \sync_flop_6_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_flop_6_reg[0]\ : label is "yes";
begin
  \out\ <= sync_flop_1;
\GEN_RIU_NOT_FROM_PLL.hssio_state[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80008000F0008000"
    )
        port map (
      I0 => sync_flop_1,
      I1 => Q(2),
      I2 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[5]\,
      I3 => \GEN_RIU_NOT_FROM_PLL.pll0_clkoutphy_en_reg\,
      I4 => Q(3),
      I5 => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[5]_0\,
      O => D(0)
    );
\GEN_RIU_NOT_FROM_PLL.pll0_clkoutphy_en_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AABFAA80"
    )
        port map (
      I0 => pll0_clkoutphy_en,
      I1 => \GEN_RIU_NOT_FROM_PLL.pll0_clkoutphy_en_reg\,
      I2 => Q(2),
      I3 => \GEN_RIU_NOT_FROM_PLL.pll0_clkoutphy_en_reg_1\,
      I4 => pll0_clkoutphy_en_in,
      O => \sync_flop_1_reg[0]_0\
    );
\GEN_RIU_NOT_FROM_PLL.pll0_clkoutphy_en_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200000"
    )
        port map (
      I0 => Q(2),
      I1 => Q(4),
      I2 => sync_flop_1,
      I3 => Q(0),
      I4 => \GEN_RIU_NOT_FROM_PLL.pll0_clkoutphy_en_reg_0\,
      O => pll0_clkoutphy_en
    );
\GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"222F2220"
    )
        port map (
      I0 => Q(2),
      I1 => sync_flop_1,
      I2 => \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg\,
      I3 => \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg_0\,
      I4 => \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg_1\(0),
      O => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[4]\
    );
\GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF9FFF9FFFFFFF9"
    )
        port map (
      I0 => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg\,
      I1 => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\,
      I2 => Q(1),
      I3 => Q(5),
      I4 => Q(2),
      I5 => sync_flop_1,
      O => \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[3]\
    );
\sync_flop_0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => in0(0),
      Q => sync_flop_0,
      R => '0'
    );
\sync_flop_1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_0,
      Q => sync_flop_1,
      R => '0'
    );
\sync_flop_2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_1,
      Q => sync_flop_2,
      R => '0'
    );
\sync_flop_3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_2,
      Q => sync_flop_3,
      R => '0'
    );
\sync_flop_4_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_3,
      Q => sync_flop_4,
      R => '0'
    );
\sync_flop_5_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_4,
      Q => sync_flop_5,
      R => '0'
    );
\sync_flop_6_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_flop_5,
      Q => sync_flop_6,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_upcnt_n is
  port (
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    seq_clr : in STD_LOGIC;
    seq_cnt_en : in STD_LOGIC;
    slowest_sync_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_upcnt_n : entity is "upcnt_n";
end design_1_Vsp_core_0_0_upcnt_n;

architecture STRUCTURE of design_1_Vsp_core_0_0_upcnt_n is
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal clear : STD_LOGIC;
  signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair181";
  attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair181";
  attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair180";
  attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair180";
begin
  Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => q_int0(0)
    );
\q_int[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => q_int0(1)
    );
\q_int[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => q_int0(2)
    );
\q_int[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => q_int0(3)
    );
\q_int[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => q_int0(4)
    );
\q_int[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => seq_clr,
      O => clear
    );
\q_int[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => \^q\(4),
      I5 => \^q\(5),
      O => q_int0(5)
    );
\q_int_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => slowest_sync_clk,
      CE => seq_cnt_en,
      D => q_int0(0),
      Q => \^q\(0),
      R => clear
    );
\q_int_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => slowest_sync_clk,
      CE => seq_cnt_en,
      D => q_int0(1),
      Q => \^q\(1),
      R => clear
    );
\q_int_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => slowest_sync_clk,
      CE => seq_cnt_en,
      D => q_int0(2),
      Q => \^q\(2),
      R => clear
    );
\q_int_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => slowest_sync_clk,
      CE => seq_cnt_en,
      D => q_int0(3),
      Q => \^q\(3),
      R => clear
    );
\q_int_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => slowest_sync_clk,
      CE => seq_cnt_en,
      D => q_int0(4),
      Q => \^q\(4),
      R => clear
    );
\q_int_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => slowest_sync_clk,
      CE => seq_cnt_en,
      D => q_int0(5),
      Q => \^q\(5),
      R => clear
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_vfb_v1_0_27_op_inf is
  port (
    sband_tu_r : out STD_LOGIC_VECTOR ( 0 to 0 );
    vfb_eol_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \vfb_sof_reg[0]_0\ : out STD_LOGIC;
    vfb_valid_reg_0 : out STD_LOGIC;
    vfb_sof015_out : out STD_LOGIC;
    \vfb_cnt_reg[3]_0\ : out STD_LOGIC;
    \sband_tk_r_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    vfb_sof : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sband_td_r_reg[47]_0\ : out STD_LOGIC_VECTOR ( 47 downto 0 );
    vfb_data : out STD_LOGIC_VECTOR ( 23 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    vfb_sof119_out : in STD_LOGIC;
    sband_tl : in STD_LOGIC;
    vfb_clk : in STD_LOGIC;
    sband_tu : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 6 downto 0 );
    m_axis_tvalid : in STD_LOGIC;
    vfb_arstn : in STD_LOGIC;
    \vfb_sof_reg[0]_1\ : in STD_LOGIC;
    \vfb_sof_reg[0]_2\ : in STD_LOGIC;
    m_axis_tlast : in STD_LOGIC;
    m_axis_tid : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \TUSR0.vfb_sof_reg[64]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \sband_td_r_reg[47]_1\ : in STD_LOGIC_VECTOR ( 47 downto 0 );
    \vfb_data_reg[23]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \vfb_data_reg[15]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_vfb_v1_0_27_op_inf : entity is "vfb_v1_0_27_op_inf";
end design_1_Vsp_core_0_0_vfb_v1_0_27_op_inf;

architecture STRUCTURE of design_1_Vsp_core_0_0_vfb_v1_0_27_op_inf is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \TUSR0.vfb_sof[69]_i_1_n_0\ : STD_LOGIC;
  signal \TUSR0.vfb_sof[69]_i_3_n_0\ : STD_LOGIC;
  signal \TUSR0.vfb_sof[69]_i_4_n_0\ : STD_LOGIC;
  signal cnt_done0 : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal p_1_in : STD_LOGIC_VECTOR ( 68 downto 63 );
  signal sband_tact : STD_LOGIC;
  signal sband_tact_i_1_n_0 : STD_LOGIC;
  signal sband_tact_i_2_n_0 : STD_LOGIC;
  signal \sband_tk_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \sband_tk_r_reg_n_0_[2]\ : STD_LOGIC;
  signal sband_tl_r : STD_LOGIC;
  signal sband_ts_r : STD_LOGIC_VECTOR ( 9 downto 4 );
  signal \vfb_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal vfb_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \vfb_data[15]_i_1_n_0\ : STD_LOGIC;
  signal \vfb_data[23]_i_1_n_0\ : STD_LOGIC;
  signal vfb_eol_i_1_n_0 : STD_LOGIC;
  signal vfb_eol_i_2_n_0 : STD_LOGIC;
  signal vfb_eol_i_3_n_0 : STD_LOGIC;
  signal \^vfb_eol_reg_0\ : STD_LOGIC;
  signal \^vfb_sof015_out\ : STD_LOGIC;
  signal vfb_sof4_out : STD_LOGIC;
  signal \vfb_sof[0]_i_1_n_0\ : STD_LOGIC;
  signal \vfb_sof[0]_i_5_n_0\ : STD_LOGIC;
  signal \^vfb_sof_reg[0]_0\ : STD_LOGIC;
  signal vfb_tu0 : STD_LOGIC;
  signal vfb_tu0_i_1_n_0 : STD_LOGIC;
  signal vfb_valid_i_2_n_0 : STD_LOGIC;
  signal \^vfb_valid_reg_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \TUSR0.vfb_sof[69]_i_3\ : label is "soft_lutpair547";
  attribute SOFT_HLUTNM of \TUSR0.vfb_sof[69]_i_4\ : label is "soft_lutpair547";
  attribute SOFT_HLUTNM of sband_tact_i_1 : label is "soft_lutpair548";
  attribute SOFT_HLUTNM of sband_tact_i_2 : label is "soft_lutpair549";
  attribute SOFT_HLUTNM of sband_tl_r_i_3 : label is "soft_lutpair549";
  attribute SOFT_HLUTNM of \vfb_cnt[1]_i_1\ : label is "soft_lutpair552";
  attribute SOFT_HLUTNM of \vfb_cnt[2]_i_1\ : label is "soft_lutpair552";
  attribute SOFT_HLUTNM of \vfb_cnt[3]_i_2\ : label is "soft_lutpair550";
  attribute SOFT_HLUTNM of vfb_eol_i_4 : label is "soft_lutpair548";
  attribute SOFT_HLUTNM of \vfb_sof[0]_i_4\ : label is "soft_lutpair546";
  attribute SOFT_HLUTNM of \vfb_sof[0]_i_5\ : label is "soft_lutpair551";
  attribute SOFT_HLUTNM of vfb_tu0_i_1 : label is "soft_lutpair551";
  attribute SOFT_HLUTNM of vfb_valid_i_2 : label is "soft_lutpair546";
  attribute SOFT_HLUTNM of vfb_valid_i_3 : label is "soft_lutpair550";
begin
  E(0) <= \^e\(0);
  vfb_eol_reg_0 <= \^vfb_eol_reg_0\;
  vfb_sof015_out <= \^vfb_sof015_out\;
  \vfb_sof_reg[0]_0\ <= \^vfb_sof_reg[0]_0\;
  vfb_valid_reg_0 <= \^vfb_valid_reg_0\;
\TUSR0.vfb_sof[64]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \TUSR0.vfb_sof[69]_i_3_n_0\,
      I1 => sband_ts_r(4),
      I2 => \TUSR0.vfb_sof[69]_i_4_n_0\,
      I3 => Q(0),
      I4 => m_axis_tid(0),
      I5 => \TUSR0.vfb_sof_reg[64]_0\,
      O => p_1_in(63)
    );
\TUSR0.vfb_sof[65]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \TUSR0.vfb_sof[69]_i_3_n_0\,
      I1 => sband_ts_r(5),
      I2 => \TUSR0.vfb_sof[69]_i_4_n_0\,
      I3 => Q(1),
      I4 => m_axis_tid(1),
      I5 => \TUSR0.vfb_sof_reg[64]_0\,
      O => p_1_in(64)
    );
\TUSR0.vfb_sof[66]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \TUSR0.vfb_sof[69]_i_3_n_0\,
      I1 => sband_ts_r(6),
      I2 => \TUSR0.vfb_sof[69]_i_4_n_0\,
      I3 => Q(2),
      I4 => m_axis_tid(2),
      I5 => \TUSR0.vfb_sof_reg[64]_0\,
      O => p_1_in(65)
    );
\TUSR0.vfb_sof[67]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \TUSR0.vfb_sof[69]_i_3_n_0\,
      I1 => sband_ts_r(7),
      I2 => \TUSR0.vfb_sof[69]_i_4_n_0\,
      I3 => Q(3),
      I4 => m_axis_tid(3),
      I5 => \TUSR0.vfb_sof_reg[64]_0\,
      O => p_1_in(66)
    );
\TUSR0.vfb_sof[68]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \TUSR0.vfb_sof[69]_i_3_n_0\,
      I1 => sband_ts_r(8),
      I2 => \TUSR0.vfb_sof[69]_i_4_n_0\,
      I3 => Q(4),
      I4 => m_axis_tid(4),
      I5 => \TUSR0.vfb_sof_reg[64]_0\,
      O => p_1_in(67)
    );
\TUSR0.vfb_sof[69]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFEFEFFFFFFFF"
    )
        port map (
      I0 => \^vfb_sof015_out\,
      I1 => m_axis_tvalid,
      I2 => vfb_sof119_out,
      I3 => \^vfb_eol_reg_0\,
      I4 => \^e\(0),
      I5 => vfb_arstn,
      O => \TUSR0.vfb_sof[69]_i_1_n_0\
    );
\TUSR0.vfb_sof[69]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \TUSR0.vfb_sof[69]_i_3_n_0\,
      I1 => sband_ts_r(9),
      I2 => \TUSR0.vfb_sof[69]_i_4_n_0\,
      I3 => Q(5),
      I4 => m_axis_tid(5),
      I5 => \TUSR0.vfb_sof_reg[64]_0\,
      O => p_1_in(68)
    );
\TUSR0.vfb_sof[69]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000070"
    )
        port map (
      I0 => \^e\(0),
      I1 => \^vfb_eol_reg_0\,
      I2 => vfb_arstn,
      I3 => m_axis_tvalid,
      I4 => vfb_sof119_out,
      O => \TUSR0.vfb_sof[69]_i_3_n_0\
    );
\TUSR0.vfb_sof[69]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00700000"
    )
        port map (
      I0 => \^e\(0),
      I1 => \^vfb_eol_reg_0\,
      I2 => vfb_arstn,
      I3 => m_axis_tvalid,
      I4 => vfb_sof119_out,
      O => \TUSR0.vfb_sof[69]_i_4_n_0\
    );
\TUSR0.vfb_sof_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \TUSR0.vfb_sof[69]_i_1_n_0\,
      D => p_1_in(63),
      Q => vfb_sof(0),
      R => '0'
    );
\TUSR0.vfb_sof_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \TUSR0.vfb_sof[69]_i_1_n_0\,
      D => p_1_in(64),
      Q => vfb_sof(1),
      R => '0'
    );
\TUSR0.vfb_sof_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \TUSR0.vfb_sof[69]_i_1_n_0\,
      D => p_1_in(65),
      Q => vfb_sof(2),
      R => '0'
    );
\TUSR0.vfb_sof_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \TUSR0.vfb_sof[69]_i_1_n_0\,
      D => p_1_in(66),
      Q => vfb_sof(3),
      R => '0'
    );
\TUSR0.vfb_sof_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \TUSR0.vfb_sof[69]_i_1_n_0\,
      D => p_1_in(67),
      Q => vfb_sof(4),
      R => '0'
    );
\TUSR0.vfb_sof_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \TUSR0.vfb_sof[69]_i_1_n_0\,
      D => p_1_in(68),
      Q => vfb_sof(5),
      R => '0'
    );
sband_tact_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF75FF00"
    )
        port map (
      I0 => \^e\(0),
      I1 => \^vfb_eol_reg_0\,
      I2 => sband_tact_i_2_n_0,
      I3 => vfb_sof119_out,
      I4 => sband_tact,
      O => sband_tact_i_1_n_0
    );
sband_tact_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => vfb_cnt_reg(3),
      I1 => vfb_cnt_reg(2),
      I2 => vfb_cnt_reg(1),
      O => sband_tact_i_2_n_0
    );
sband_tact_reg: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => sband_tact_i_1_n_0,
      Q => sband_tact,
      R => SR(0)
    );
\sband_td_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(0),
      Q => \sband_td_r_reg[47]_0\(0),
      R => SR(0)
    );
\sband_td_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(10),
      Q => \sband_td_r_reg[47]_0\(10),
      R => SR(0)
    );
\sband_td_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(11),
      Q => \sband_td_r_reg[47]_0\(11),
      R => SR(0)
    );
\sband_td_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(12),
      Q => \sband_td_r_reg[47]_0\(12),
      R => SR(0)
    );
\sband_td_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(13),
      Q => \sband_td_r_reg[47]_0\(13),
      R => SR(0)
    );
\sband_td_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(14),
      Q => \sband_td_r_reg[47]_0\(14),
      R => SR(0)
    );
\sband_td_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(15),
      Q => \sband_td_r_reg[47]_0\(15),
      R => SR(0)
    );
\sband_td_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(16),
      Q => \sband_td_r_reg[47]_0\(16),
      R => SR(0)
    );
\sband_td_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(17),
      Q => \sband_td_r_reg[47]_0\(17),
      R => SR(0)
    );
\sband_td_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(18),
      Q => \sband_td_r_reg[47]_0\(18),
      R => SR(0)
    );
\sband_td_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(19),
      Q => \sband_td_r_reg[47]_0\(19),
      R => SR(0)
    );
\sband_td_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(1),
      Q => \sband_td_r_reg[47]_0\(1),
      R => SR(0)
    );
\sband_td_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(20),
      Q => \sband_td_r_reg[47]_0\(20),
      R => SR(0)
    );
\sband_td_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(21),
      Q => \sband_td_r_reg[47]_0\(21),
      R => SR(0)
    );
\sband_td_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(22),
      Q => \sband_td_r_reg[47]_0\(22),
      R => SR(0)
    );
\sband_td_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(23),
      Q => \sband_td_r_reg[47]_0\(23),
      R => SR(0)
    );
\sband_td_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(24),
      Q => \sband_td_r_reg[47]_0\(24),
      R => SR(0)
    );
\sband_td_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(25),
      Q => \sband_td_r_reg[47]_0\(25),
      R => SR(0)
    );
\sband_td_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(26),
      Q => \sband_td_r_reg[47]_0\(26),
      R => SR(0)
    );
\sband_td_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(27),
      Q => \sband_td_r_reg[47]_0\(27),
      R => SR(0)
    );
\sband_td_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(28),
      Q => \sband_td_r_reg[47]_0\(28),
      R => SR(0)
    );
\sband_td_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(29),
      Q => \sband_td_r_reg[47]_0\(29),
      R => SR(0)
    );
\sband_td_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(2),
      Q => \sband_td_r_reg[47]_0\(2),
      R => SR(0)
    );
\sband_td_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(30),
      Q => \sband_td_r_reg[47]_0\(30),
      R => SR(0)
    );
\sband_td_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(31),
      Q => \sband_td_r_reg[47]_0\(31),
      R => SR(0)
    );
\sband_td_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(32),
      Q => \sband_td_r_reg[47]_0\(32),
      R => SR(0)
    );
\sband_td_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(33),
      Q => \sband_td_r_reg[47]_0\(33),
      R => SR(0)
    );
\sband_td_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(34),
      Q => \sband_td_r_reg[47]_0\(34),
      R => SR(0)
    );
\sband_td_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(35),
      Q => \sband_td_r_reg[47]_0\(35),
      R => SR(0)
    );
\sband_td_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(36),
      Q => \sband_td_r_reg[47]_0\(36),
      R => SR(0)
    );
\sband_td_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(37),
      Q => \sband_td_r_reg[47]_0\(37),
      R => SR(0)
    );
\sband_td_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(38),
      Q => \sband_td_r_reg[47]_0\(38),
      R => SR(0)
    );
\sband_td_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(39),
      Q => \sband_td_r_reg[47]_0\(39),
      R => SR(0)
    );
\sband_td_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(3),
      Q => \sband_td_r_reg[47]_0\(3),
      R => SR(0)
    );
\sband_td_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(40),
      Q => \sband_td_r_reg[47]_0\(40),
      R => SR(0)
    );
\sband_td_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(41),
      Q => \sband_td_r_reg[47]_0\(41),
      R => SR(0)
    );
\sband_td_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(42),
      Q => \sband_td_r_reg[47]_0\(42),
      R => SR(0)
    );
\sband_td_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(43),
      Q => \sband_td_r_reg[47]_0\(43),
      R => SR(0)
    );
\sband_td_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(44),
      Q => \sband_td_r_reg[47]_0\(44),
      R => SR(0)
    );
\sband_td_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(45),
      Q => \sband_td_r_reg[47]_0\(45),
      R => SR(0)
    );
\sband_td_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(46),
      Q => \sband_td_r_reg[47]_0\(46),
      R => SR(0)
    );
\sband_td_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(47),
      Q => \sband_td_r_reg[47]_0\(47),
      R => SR(0)
    );
\sband_td_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(4),
      Q => \sband_td_r_reg[47]_0\(4),
      R => SR(0)
    );
\sband_td_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(5),
      Q => \sband_td_r_reg[47]_0\(5),
      R => SR(0)
    );
\sband_td_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(6),
      Q => \sband_td_r_reg[47]_0\(6),
      R => SR(0)
    );
\sband_td_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(7),
      Q => \sband_td_r_reg[47]_0\(7),
      R => SR(0)
    );
\sband_td_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(8),
      Q => \sband_td_r_reg[47]_0\(8),
      R => SR(0)
    );
\sband_td_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => \sband_td_r_reg[47]_1\(9),
      Q => \sband_td_r_reg[47]_0\(9),
      R => SR(0)
    );
\sband_tk_r[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^e\(0),
      I1 => vfb_sof119_out,
      O => \sband_tk_r[4]_i_1_n_0\
    );
\sband_tk_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => D(0),
      Q => \sband_tk_r_reg_n_0_[2]\,
      R => SR(0)
    );
\sband_tk_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \sband_tk_r[4]_i_1_n_0\,
      D => D(1),
      Q => \sband_tk_r_reg[4]_0\(0),
      R => SR(0)
    );
sband_tl_r_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"40FF"
    )
        port map (
      I0 => vfb_cnt_reg(3),
      I1 => vfb_cnt_reg(1),
      I2 => vfb_cnt_reg(2),
      I3 => \^e\(0),
      O => \vfb_cnt_reg[3]_0\
    );
sband_tl_r_reg: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => vfb_sof119_out,
      D => sband_tl,
      Q => sband_tl_r,
      R => SR(0)
    );
\sband_ts_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => vfb_sof119_out,
      D => Q(0),
      Q => sband_ts_r(4),
      R => SR(0)
    );
\sband_ts_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => vfb_sof119_out,
      D => Q(1),
      Q => sband_ts_r(5),
      R => SR(0)
    );
\sband_ts_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => vfb_sof119_out,
      D => Q(2),
      Q => sband_ts_r(6),
      R => SR(0)
    );
\sband_ts_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => vfb_sof119_out,
      D => Q(3),
      Q => sband_ts_r(7),
      R => SR(0)
    );
\sband_ts_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => vfb_sof119_out,
      D => Q(4),
      Q => sband_ts_r(8),
      R => SR(0)
    );
\sband_ts_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => vfb_sof119_out,
      D => Q(5),
      Q => sband_ts_r(9),
      R => SR(0)
    );
\sband_tu_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => vfb_sof119_out,
      D => sband_tu(0),
      Q => sband_tu_r(0),
      R => SR(0)
    );
\vfb_cnt[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => vfb_cnt_reg(1),
      O => cnt_done0(1)
    );
\vfb_cnt[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => vfb_cnt_reg(1),
      I1 => vfb_cnt_reg(2),
      O => cnt_done0(2)
    );
\vfb_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888A888FFFFFFFF"
    )
        port map (
      I0 => \^e\(0),
      I1 => \^vfb_eol_reg_0\,
      I2 => vfb_cnt_reg(1),
      I3 => vfb_cnt_reg(2),
      I4 => vfb_cnt_reg(3),
      I5 => vfb_arstn,
      O => \vfb_cnt[3]_i_1_n_0\
    );
\vfb_cnt[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => vfb_cnt_reg(1),
      I1 => vfb_cnt_reg(2),
      I2 => vfb_cnt_reg(3),
      O => cnt_done0(3)
    );
\vfb_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \^e\(0),
      D => cnt_done0(1),
      Q => vfb_cnt_reg(1),
      R => \vfb_cnt[3]_i_1_n_0\
    );
\vfb_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \^e\(0),
      D => cnt_done0(2),
      Q => vfb_cnt_reg(2),
      R => \vfb_cnt[3]_i_1_n_0\
    );
\vfb_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \^e\(0),
      D => cnt_done0(3),
      Q => vfb_cnt_reg(3),
      R => \vfb_cnt[3]_i_1_n_0\
    );
\vfb_data[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"07FF"
    )
        port map (
      I0 => \^e\(0),
      I1 => \^vfb_eol_reg_0\,
      I2 => m_axis_tvalid,
      I3 => vfb_arstn,
      O => \vfb_data[15]_i_1_n_0\
    );
\vfb_data[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFF"
    )
        port map (
      I0 => m_axis_tvalid,
      I1 => vfb_arstn,
      I2 => \^vfb_eol_reg_0\,
      I3 => \^e\(0),
      O => \vfb_data[23]_i_1_n_0\
    );
\vfb_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[15]_0\(0),
      Q => vfb_data(0),
      R => \vfb_data[15]_i_1_n_0\
    );
\vfb_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(6),
      Q => vfb_data(10),
      R => '0'
    );
\vfb_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(7),
      Q => vfb_data(11),
      R => '0'
    );
\vfb_data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[15]_0\(4),
      Q => vfb_data(12),
      R => \vfb_data[15]_i_1_n_0\
    );
\vfb_data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[15]_0\(5),
      Q => vfb_data(13),
      R => \vfb_data[15]_i_1_n_0\
    );
\vfb_data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[15]_0\(6),
      Q => vfb_data(14),
      R => \vfb_data[15]_i_1_n_0\
    );
\vfb_data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[15]_0\(7),
      Q => vfb_data(15),
      R => \vfb_data[15]_i_1_n_0\
    );
\vfb_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(8),
      Q => vfb_data(16),
      R => '0'
    );
\vfb_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(9),
      Q => vfb_data(17),
      R => '0'
    );
\vfb_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(10),
      Q => vfb_data(18),
      R => '0'
    );
\vfb_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(11),
      Q => vfb_data(19),
      R => '0'
    );
\vfb_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[15]_0\(1),
      Q => vfb_data(1),
      R => \vfb_data[15]_i_1_n_0\
    );
\vfb_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(12),
      Q => vfb_data(20),
      R => '0'
    );
\vfb_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(13),
      Q => vfb_data(21),
      R => '0'
    );
\vfb_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(14),
      Q => vfb_data(22),
      R => '0'
    );
\vfb_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(15),
      Q => vfb_data(23),
      R => '0'
    );
\vfb_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[15]_0\(2),
      Q => vfb_data(2),
      R => \vfb_data[15]_i_1_n_0\
    );
\vfb_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[15]_0\(3),
      Q => vfb_data(3),
      R => \vfb_data[15]_i_1_n_0\
    );
\vfb_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(0),
      Q => vfb_data(4),
      R => '0'
    );
\vfb_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(1),
      Q => vfb_data(5),
      R => '0'
    );
\vfb_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(2),
      Q => vfb_data(6),
      R => '0'
    );
\vfb_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(3),
      Q => vfb_data(7),
      R => '0'
    );
\vfb_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(4),
      Q => vfb_data(8),
      R => '0'
    );
\vfb_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \vfb_data[23]_i_1_n_0\,
      D => \vfb_data_reg[23]_0\(5),
      Q => vfb_data(9),
      R => '0'
    );
vfb_eol_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEAAAAAAAEAAA"
    )
        port map (
      I0 => vfb_eol_i_2_n_0,
      I1 => sband_tl,
      I2 => vfb_eol_i_3_n_0,
      I3 => vfb_sof119_out,
      I4 => m_axis_tvalid,
      I5 => m_axis_tlast,
      O => vfb_eol_i_1_n_0
    );
vfb_eol_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \^vfb_sof015_out\,
      I1 => sband_tl_r,
      I2 => \sband_tk_r_reg_n_0_[2]\,
      I3 => \^vfb_valid_reg_0\,
      I4 => vfb_sof119_out,
      I5 => m_axis_tvalid,
      O => vfb_eol_i_2_n_0
    );
vfb_eol_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"07"
    )
        port map (
      I0 => \^vfb_eol_reg_0\,
      I1 => \^e\(0),
      I2 => Q(6),
      O => vfb_eol_i_3_n_0
    );
vfb_eol_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^e\(0),
      I1 => \^vfb_eol_reg_0\,
      O => \^vfb_valid_reg_0\
    );
vfb_eol_reg: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => vfb_eol_i_1_n_0,
      Q => \^vfb_eol_reg_0\,
      R => SR(0)
    );
\vfb_sof[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8AAA80000000000"
    )
        port map (
      I0 => vfb_arstn,
      I1 => \vfb_sof_reg[0]_1\,
      I2 => \vfb_sof_reg[0]_2\,
      I3 => vfb_sof4_out,
      I4 => \^vfb_sof_reg[0]_0\,
      I5 => \vfb_sof[0]_i_5_n_0\,
      O => \vfb_sof[0]_i_1_n_0\
    );
\vfb_sof[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFF8"
    )
        port map (
      I0 => \^e\(0),
      I1 => \^vfb_eol_reg_0\,
      I2 => vfb_sof119_out,
      I3 => m_axis_tvalid,
      I4 => \^vfb_sof015_out\,
      O => vfb_sof4_out
    );
\vfb_sof[0]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0DDD"
    )
        port map (
      I0 => vfb_tu0,
      I1 => \^vfb_eol_reg_0\,
      I2 => \^vfb_sof_reg[0]_0\,
      I3 => \^e\(0),
      O => \vfb_sof[0]_i_5_n_0\
    );
\vfb_sof_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => \vfb_sof[0]_i_1_n_0\,
      Q => \^vfb_sof_reg[0]_0\,
      R => '0'
    );
vfb_tu0_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3F20"
    )
        port map (
      I0 => \^vfb_sof_reg[0]_0\,
      I1 => \^vfb_eol_reg_0\,
      I2 => \^e\(0),
      I3 => vfb_tu0,
      O => vfb_tu0_i_1_n_0
    );
vfb_tu0_reg: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => vfb_tu0_i_1_n_0,
      Q => vfb_tu0,
      R => SR(0)
    );
vfb_valid_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFFFAEEE"
    )
        port map (
      I0 => m_axis_tvalid,
      I1 => \^vfb_sof015_out\,
      I2 => \^e\(0),
      I3 => \^vfb_eol_reg_0\,
      I4 => vfb_sof119_out,
      O => vfb_valid_i_2_n_0
    );
vfb_valid_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F700"
    )
        port map (
      I0 => vfb_cnt_reg(1),
      I1 => vfb_cnt_reg(2),
      I2 => vfb_cnt_reg(3),
      I3 => sband_tact,
      O => \^vfb_sof015_out\
    );
vfb_valid_reg: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => vfb_valid_i_2_n_0,
      Q => \^e\(0),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_vfb_v1_0_27_reorder is
  port (
    cur_dtype_udef : out STD_LOGIC;
    s_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_fifo_tv : out STD_LOGIC;
    s_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axis_tlast : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
    sband_tu : out STD_LOGIC_VECTOR ( 0 to 0 );
    \buf_valid_reg[1]_0\ : out STD_LOGIC;
    \state_reg[1]\ : out STD_LOGIC;
    vfb_sof119_out : out STD_LOGIC;
    sband_tl : out STD_LOGIC;
    \buf_data_reg[0][106]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \buf_data_reg[0][171]_0\ : out STD_LOGIC_VECTOR ( 47 downto 0 );
    \state_reg[1]_0\ : out STD_LOGIC;
    \s_fifo_td_reg[59]_0\ : out STD_LOGIC_VECTOR ( 47 downto 0 );
    \s_fifo_tid_reg[9]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    vfb_clk : in STD_LOGIC;
    s_axis_tready : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 80 downto 0 );
    s_axis_tvalid : in STD_LOGIC;
    vfb_arstn : in STD_LOGIC;
    m_axis_tvalid : in STD_LOGIC;
    \vfb_sof_reg[0]\ : in STD_LOGIC;
    sband_tu_r : in STD_LOGIC_VECTOR ( 0 to 0 );
    \buf_valid_reg[1]_1\ : in STD_LOGIC;
    sband_tl_r_reg : in STD_LOGIC;
    \sband_tk_r_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \sband_td_r_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    vfb_sof015_out : in STD_LOGIC;
    sband_tl_r_reg_0 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \REQ_BUFFER_RAW12.buff_tv_i_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_vfb_v1_0_27_reorder : entity is "vfb_v1_0_27_reorder";
end design_1_Vsp_core_0_0_vfb_v1_0_27_reorder;

architecture STRUCTURE of design_1_Vsp_core_0_0_vfb_v1_0_27_reorder is
  signal \^q\ : STD_LOGIC_VECTOR ( 22 downto 0 );
  signal \REQ_BUFFER_RAW12.buff_tk_i\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \REQ_BUFFER_RAW12.buff_tk_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tk_i[1]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tk_i[2]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tk_i[3]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tk_i[4]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tk_i[5]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tk_i[6]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tk_i[7]_i_2_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tl_i\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tl_i0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tl_i7_out\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tl_i_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tl_i_i_5_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tl_i_i_6_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tl_i_i_7_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tl_i_i_8_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tl_i_reg_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_ts_i[4]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_ts_i[5]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_ts_i[6]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_ts_i[7]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_ts_i[8]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_ts_i[9]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[4]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[5]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[6]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[7]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[8]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[9]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tu_i\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tu_i_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tu_i_i_2_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tv_i2__2\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tv_i8_out\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tv_i_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tv_i_i_5_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[0]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[10]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[11]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[12]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[13]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[14]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[15]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[16]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[17]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[18]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[19]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[1]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[20]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[21]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[22]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[23]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[24]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[25]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[26]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[27]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[28]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[29]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[2]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[30]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[31]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[32]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[33]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[34]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[35]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[36]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[37]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[38]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[39]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[3]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[40]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[41]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[42]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[43]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[44]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[45]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[46]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[47]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[48]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[49]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[4]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[50]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[51]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[52]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[53]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[54]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[55]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[56]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[57]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[58]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[59]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[5]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[60]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[61]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[62]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[63]_i_2_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[6]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[7]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[8]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data[9]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[0]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[10]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[11]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[12]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[13]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[14]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[15]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[16]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[17]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[18]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[19]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[1]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[20]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[21]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[22]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[23]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[24]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[25]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[26]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[27]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[28]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[29]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[2]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[30]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[31]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[32]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[33]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[34]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[35]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[36]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[37]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[38]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[39]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[3]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[40]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[41]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[42]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[43]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[44]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[45]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[46]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[47]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[48]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[49]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[4]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[50]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[51]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[52]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[53]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[54]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[55]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[56]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[57]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[58]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[59]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[5]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[60]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[61]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[62]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[63]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[6]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[7]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[8]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.cur_data_reg_n_0_[9]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.filt_tl_on\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.filt_tl_on_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.indx_cntr\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \REQ_BUFFER_RAW12.indx_cntr0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.indx_cntr[0]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.indx_cntr[1]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.liv_data\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \REQ_BUFFER_RAW12.liv_data[63]_i_3_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.liv_tk\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \REQ_BUFFER_RAW12.liv_ts\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[4]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[5]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[6]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[7]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[8]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[9]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.res_data\ : STD_LOGIC_VECTOR ( 63 downto 16 );
  signal \REQ_BUFFER_RAW12.resi_wdth\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth133_out\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[3]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[3]_i_2_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[4]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[4]_i_2_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[4]_i_3_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[4]_i_4_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[4]_i_5_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[4]_i_6_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[5]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[5]_i_2_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[5]_i_3_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[5]_i_4_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[5]_i_5_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[6]_i_1_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[6]_i_2_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[6]_i_3_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[6]_i_4_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[7]_i_10_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[7]_i_11_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[7]_i_12_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[7]_i_13_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[7]_i_2_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[7]_i_3_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[7]_i_4_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[7]_i_5_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[7]_i_6_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[7]_i_7_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[7]_i_8_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth[7]_i_9_n_0\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[5]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[6]\ : STD_LOGIC;
  signal \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[7]\ : STD_LOGIC;
  signal \REQ_REORDER_RAW12.tk_partial_i1__2\ : STD_LOGIC;
  signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \buf_data[0][172]_i_1_n_0\ : STD_LOGIC;
  signal \buf_data[1][172]_i_1_n_0\ : STD_LOGIC;
  signal \buf_data_reg[1]_0\ : STD_LOGIC_VECTOR ( 172 downto 4 );
  signal \buf_data_reg_n_0_[0][4]\ : STD_LOGIC;
  signal \buf_valid[0]_i_1_n_0\ : STD_LOGIC;
  signal \buf_valid[1]_i_1_n_0\ : STD_LOGIC;
  signal \buf_valid[1]_i_4_n_0\ : STD_LOGIC;
  signal \buf_valid_reg_n_0_[0]\ : STD_LOGIC;
  signal buff_td : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal buff_tr141_in : STD_LOGIC;
  signal cur_dtype_pxls : STD_LOGIC;
  signal cur_dtype_pxls0 : STD_LOGIC;
  signal cur_dtype_pxls1 : STD_LOGIC;
  signal cur_dtype_pxls_i_2_n_0 : STD_LOGIC;
  signal cur_dtype_pxls_i_4_n_0 : STD_LOGIC;
  signal cur_dtype_sink : STD_LOGIC;
  signal cur_dtype_sink_i_1_n_0 : STD_LOGIC;
  signal cur_dtype_sink_reg_n_0 : STD_LOGIC;
  signal \^cur_dtype_udef\ : STD_LOGIC;
  signal cur_dtype_udef_i_1_n_0 : STD_LOGIC;
  signal \main_dtvc__4\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_0_in39_in : STD_LOGIC;
  signal \p_2_in__0\ : STD_LOGIC_VECTOR ( 172 downto 4 );
  signal p_3_in : STD_LOGIC;
  signal \^s_axis_tkeep\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^s_axis_tlast\ : STD_LOGIC;
  signal s_axis_tlast_0 : STD_LOGIC;
  signal \s_axis_tready__3\ : STD_LOGIC;
  signal \s_fifo_tk[7]_i_1_n_0\ : STD_LOGIC;
  signal \s_fifo_tk[7]_i_2_n_0\ : STD_LOGIC;
  signal \s_fifo_tk[7]_i_4_n_0\ : STD_LOGIC;
  signal \s_fifo_tk[7]_i_5_n_0\ : STD_LOGIC;
  signal s_fifo_tl_i_1_n_0 : STD_LOGIC;
  signal \^s_fifo_tv\ : STD_LOGIC;
  signal s_fifo_tv_i_1_n_0 : STD_LOGIC;
  signal sban_dtvc : STD_LOGIC;
  signal sband_td : STD_LOGIC_VECTOR ( 63 downto 16 );
  signal sband_tk : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^sband_tl\ : STD_LOGIC;
  signal \sband_tu_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \^vfb_sof119_out\ : STD_LOGIC;
  signal \vfb_sof[0]_i_6_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.buff_tl_i_i_5\ : label is "soft_lutpair498";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.buff_tl_i_i_6\ : label is "soft_lutpair528";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.buff_tl_i_i_7\ : label is "soft_lutpair491";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.buff_tl_i_i_9\ : label is "soft_lutpair527";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.buff_tu_i_i_2\ : label is "soft_lutpair526";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.buff_tv_i_i_2\ : label is "soft_lutpair488";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.indx_cntr[0]_i_1\ : label is "soft_lutpair529";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.indx_cntr[1]_i_1\ : label is "soft_lutpair529";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.liv_data[63]_i_2\ : label is "soft_lutpair488";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.resi_wdth[4]_i_3\ : label is "soft_lutpair490";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.resi_wdth[4]_i_4\ : label is "soft_lutpair492";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.resi_wdth[4]_i_5\ : label is "soft_lutpair500";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.resi_wdth[4]_i_6\ : label is "soft_lutpair528";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.resi_wdth[5]_i_1\ : label is "soft_lutpair489";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.resi_wdth[5]_i_2\ : label is "soft_lutpair490";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.resi_wdth[5]_i_5\ : label is "soft_lutpair491";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.resi_wdth[7]_i_13\ : label is "soft_lutpair492";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.resi_wdth[7]_i_4\ : label is "soft_lutpair527";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.resi_wdth[7]_i_7\ : label is "soft_lutpair489";
  attribute SOFT_HLUTNM of \REQ_BUFFER_RAW12.resi_wdth[7]_i_9\ : label is "soft_lutpair498";
  attribute SOFT_HLUTNM of \buf_data[0][171]_i_1\ : label is "soft_lutpair494";
  attribute SOFT_HLUTNM of \buf_data[0][172]_i_2\ : label is "soft_lutpair493";
  attribute SOFT_HLUTNM of \buf_valid[0]_i_1\ : label is "soft_lutpair495";
  attribute SOFT_HLUTNM of \buf_valid[1]_i_1\ : label is "soft_lutpair495";
  attribute SOFT_HLUTNM of \buf_valid[1]_i_4\ : label is "soft_lutpair525";
  attribute SOFT_HLUTNM of cur_dtype_pxls_i_2 : label is "soft_lutpair526";
  attribute SOFT_HLUTNM of cur_dtype_udef_i_1 : label is "soft_lutpair496";
  attribute SOFT_HLUTNM of s_axis_tready_INST_0 : label is "soft_lutpair494";
  attribute SOFT_HLUTNM of \s_fifo_tk[7]_i_4\ : label is "soft_lutpair499";
  attribute SOFT_HLUTNM of \s_fifo_tk[7]_i_5\ : label is "soft_lutpair499";
  attribute SOFT_HLUTNM of \sband_td_r[0]_i_1\ : label is "soft_lutpair524";
  attribute SOFT_HLUTNM of \sband_td_r[10]_i_1\ : label is "soft_lutpair519";
  attribute SOFT_HLUTNM of \sband_td_r[11]_i_1\ : label is "soft_lutpair519";
  attribute SOFT_HLUTNM of \sband_td_r[12]_i_1\ : label is "soft_lutpair518";
  attribute SOFT_HLUTNM of \sband_td_r[13]_i_1\ : label is "soft_lutpair518";
  attribute SOFT_HLUTNM of \sband_td_r[14]_i_1\ : label is "soft_lutpair517";
  attribute SOFT_HLUTNM of \sband_td_r[15]_i_1\ : label is "soft_lutpair517";
  attribute SOFT_HLUTNM of \sband_td_r[16]_i_1\ : label is "soft_lutpair516";
  attribute SOFT_HLUTNM of \sband_td_r[17]_i_1\ : label is "soft_lutpair515";
  attribute SOFT_HLUTNM of \sband_td_r[18]_i_1\ : label is "soft_lutpair514";
  attribute SOFT_HLUTNM of \sband_td_r[19]_i_1\ : label is "soft_lutpair513";
  attribute SOFT_HLUTNM of \sband_td_r[1]_i_1\ : label is "soft_lutpair524";
  attribute SOFT_HLUTNM of \sband_td_r[20]_i_1\ : label is "soft_lutpair512";
  attribute SOFT_HLUTNM of \sband_td_r[21]_i_1\ : label is "soft_lutpair511";
  attribute SOFT_HLUTNM of \sband_td_r[22]_i_1\ : label is "soft_lutpair510";
  attribute SOFT_HLUTNM of \sband_td_r[23]_i_1\ : label is "soft_lutpair509";
  attribute SOFT_HLUTNM of \sband_td_r[24]_i_1\ : label is "soft_lutpair508";
  attribute SOFT_HLUTNM of \sband_td_r[25]_i_1\ : label is "soft_lutpair507";
  attribute SOFT_HLUTNM of \sband_td_r[26]_i_1\ : label is "soft_lutpair506";
  attribute SOFT_HLUTNM of \sband_td_r[27]_i_1\ : label is "soft_lutpair505";
  attribute SOFT_HLUTNM of \sband_td_r[28]_i_1\ : label is "soft_lutpair504";
  attribute SOFT_HLUTNM of \sband_td_r[29]_i_1\ : label is "soft_lutpair503";
  attribute SOFT_HLUTNM of \sband_td_r[2]_i_1\ : label is "soft_lutpair523";
  attribute SOFT_HLUTNM of \sband_td_r[30]_i_1\ : label is "soft_lutpair502";
  attribute SOFT_HLUTNM of \sband_td_r[31]_i_1\ : label is "soft_lutpair501";
  attribute SOFT_HLUTNM of \sband_td_r[32]_i_1\ : label is "soft_lutpair516";
  attribute SOFT_HLUTNM of \sband_td_r[33]_i_1\ : label is "soft_lutpair515";
  attribute SOFT_HLUTNM of \sband_td_r[34]_i_1\ : label is "soft_lutpair514";
  attribute SOFT_HLUTNM of \sband_td_r[35]_i_1\ : label is "soft_lutpair513";
  attribute SOFT_HLUTNM of \sband_td_r[36]_i_1\ : label is "soft_lutpair512";
  attribute SOFT_HLUTNM of \sband_td_r[37]_i_1\ : label is "soft_lutpair511";
  attribute SOFT_HLUTNM of \sband_td_r[38]_i_1\ : label is "soft_lutpair510";
  attribute SOFT_HLUTNM of \sband_td_r[39]_i_1\ : label is "soft_lutpair509";
  attribute SOFT_HLUTNM of \sband_td_r[3]_i_1\ : label is "soft_lutpair523";
  attribute SOFT_HLUTNM of \sband_td_r[40]_i_1\ : label is "soft_lutpair508";
  attribute SOFT_HLUTNM of \sband_td_r[41]_i_1\ : label is "soft_lutpair507";
  attribute SOFT_HLUTNM of \sband_td_r[42]_i_1\ : label is "soft_lutpair506";
  attribute SOFT_HLUTNM of \sband_td_r[43]_i_1\ : label is "soft_lutpair505";
  attribute SOFT_HLUTNM of \sband_td_r[44]_i_1\ : label is "soft_lutpair504";
  attribute SOFT_HLUTNM of \sband_td_r[45]_i_1\ : label is "soft_lutpair503";
  attribute SOFT_HLUTNM of \sband_td_r[46]_i_1\ : label is "soft_lutpair502";
  attribute SOFT_HLUTNM of \sband_td_r[47]_i_1\ : label is "soft_lutpair501";
  attribute SOFT_HLUTNM of \sband_td_r[4]_i_1\ : label is "soft_lutpair522";
  attribute SOFT_HLUTNM of \sband_td_r[5]_i_1\ : label is "soft_lutpair522";
  attribute SOFT_HLUTNM of \sband_td_r[6]_i_1\ : label is "soft_lutpair521";
  attribute SOFT_HLUTNM of \sband_td_r[7]_i_1\ : label is "soft_lutpair521";
  attribute SOFT_HLUTNM of \sband_td_r[8]_i_1\ : label is "soft_lutpair520";
  attribute SOFT_HLUTNM of \sband_td_r[9]_i_1\ : label is "soft_lutpair520";
  attribute SOFT_HLUTNM of \sband_tk_r[2]_i_1\ : label is "soft_lutpair500";
  attribute SOFT_HLUTNM of \sband_tk_r[4]_i_2\ : label is "soft_lutpair497";
  attribute SOFT_HLUTNM of sband_tl_r_i_2 : label is "soft_lutpair493";
  attribute SOFT_HLUTNM of \sband_tu_r[0]_i_1\ : label is "soft_lutpair496";
  attribute SOFT_HLUTNM of \sband_tu_r[0]_i_3\ : label is "soft_lutpair525";
  attribute SOFT_HLUTNM of \vfb_data[23]_i_3\ : label is "soft_lutpair497";
begin
  Q(22 downto 0) <= \^q\(22 downto 0);
  SR(0) <= \^sr\(0);
  cur_dtype_udef <= \^cur_dtype_udef\;
  s_axis_tkeep(0) <= \^s_axis_tkeep\(0);
  s_axis_tlast <= \^s_axis_tlast\;
  s_fifo_tv <= \^s_fifo_tv\;
  sband_tl <= \^sband_tl\;
  vfb_sof119_out <= \^vfb_sof119_out\;
\REQ_BUFFER_RAW12.buff_tk_i[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAFFFFA2AA0000"
    )
        port map (
      I0 => sband_tk(0),
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I5 => \REQ_BUFFER_RAW12.liv_tk\(0),
      O => \REQ_BUFFER_RAW12.buff_tk_i[0]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_tk_i[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAFFFFA2AA0000"
    )
        port map (
      I0 => sband_tk(1),
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I5 => \REQ_BUFFER_RAW12.liv_tk\(1),
      O => \REQ_BUFFER_RAW12.buff_tk_i[1]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_tk_i[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAFFFFA2AA0000"
    )
        port map (
      I0 => \^q\(6),
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I5 => \REQ_BUFFER_RAW12.liv_tk\(2),
      O => \REQ_BUFFER_RAW12.buff_tk_i[2]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_tk_i[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAFFFFA2AA0000"
    )
        port map (
      I0 => sband_tk(3),
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I5 => \REQ_BUFFER_RAW12.liv_tk\(3),
      O => \REQ_BUFFER_RAW12.buff_tk_i[3]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_tk_i[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAFFFFA2AA0000"
    )
        port map (
      I0 => sband_tk(4),
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I5 => \REQ_BUFFER_RAW12.liv_tk\(4),
      O => \REQ_BUFFER_RAW12.buff_tk_i[4]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_tk_i[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAFFFFA2AA0000"
    )
        port map (
      I0 => sband_tk(5),
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I5 => \REQ_BUFFER_RAW12.liv_tk\(5),
      O => \REQ_BUFFER_RAW12.buff_tk_i[5]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_tk_i[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAFFFFA2AA0000"
    )
        port map (
      I0 => sband_tk(6),
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I5 => \REQ_BUFFER_RAW12.liv_tk\(6),
      O => \REQ_BUFFER_RAW12.buff_tk_i[6]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_tk_i[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E2EE"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I2 => s_axis_tready,
      I3 => \^s_fifo_tv\,
      O => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_tk_i[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAFFFFA2AA0000"
    )
        port map (
      I0 => sband_tk(7),
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I5 => \REQ_BUFFER_RAW12.liv_tk\(7),
      O => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_2_n_0\
    );
\REQ_BUFFER_RAW12.buff_tk_i_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.buff_tk_i[0]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_tk_i\(0),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.buff_tk_i_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.buff_tk_i[1]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_tk_i\(1),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.buff_tk_i_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.buff_tk_i[2]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_tk_i\(2),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.buff_tk_i_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.buff_tk_i[3]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_tk_i\(3),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.buff_tk_i_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.buff_tk_i[4]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_tk_i\(4),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.buff_tk_i_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.buff_tk_i[5]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_tk_i\(5),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.buff_tk_i_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.buff_tk_i[6]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_tk_i\(6),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.buff_tk_i_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_2_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_tk_i\(7),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.buff_tl_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBF8000000000000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tl_i0\,
      I1 => \REQ_BUFFER_RAW12.buff_tl_i\,
      I2 => \REQ_BUFFER_RAW12.buff_tl_i7_out\,
      I3 => \REQ_BUFFER_RAW12.buff_tl_i_reg_n_0\,
      I4 => vfb_arstn,
      I5 => \REQ_BUFFER_RAW12.buff_tl_i_i_5_n_0\,
      O => \REQ_BUFFER_RAW12.buff_tl_i_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_tl_i_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF80000000000000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tu_i_i_2_n_0\,
      I1 => \REQ_BUFFER_RAW12.buff_tl_i_i_6_n_0\,
      I2 => \REQ_BUFFER_RAW12.buff_tl_i_i_7_n_0\,
      I3 => p_0_in39_in,
      I4 => cur_dtype_pxls1,
      I5 => s_axis_tlast_0,
      O => \REQ_BUFFER_RAW12.buff_tl_i0\
    );
\REQ_BUFFER_RAW12.buff_tl_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000808080808080"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tlast_0,
      I2 => cur_dtype_pxls1,
      I3 => s_axis_tready,
      I4 => \^s_fifo_tv\,
      I5 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      O => \REQ_BUFFER_RAW12.buff_tl_i\
    );
\REQ_BUFFER_RAW12.buff_tl_i_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA2AAA2AAA2AAA"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tl_i_i_8_n_0\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I2 => s_axis_tlast_0,
      I3 => cur_dtype_pxls1,
      I4 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_4_n_0\,
      I5 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      O => \REQ_BUFFER_RAW12.buff_tl_i7_out\
    );
\REQ_BUFFER_RAW12.buff_tl_i_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F77"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tl_i_reg_n_0\,
      I1 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I2 => s_axis_tready,
      I3 => \^s_fifo_tv\,
      O => \REQ_BUFFER_RAW12.buff_tl_i_i_5_n_0\
    );
\REQ_BUFFER_RAW12.buff_tl_i_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => sband_tk(0),
      I1 => sband_tk(7),
      I2 => sband_tk(6),
      O => \REQ_BUFFER_RAW12.buff_tl_i_i_6_n_0\
    );
\REQ_BUFFER_RAW12.buff_tl_i_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8000008B"
    )
        port map (
      I0 => sband_tk(1),
      I1 => \^q\(6),
      I2 => sband_tk(3),
      I3 => sband_tk(4),
      I4 => sband_tk(5),
      O => \REQ_BUFFER_RAW12.buff_tl_i_i_7_n_0\
    );
\REQ_BUFFER_RAW12.buff_tl_i_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080808080808088"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.filt_tl_on\,
      I1 => p_3_in,
      I2 => buff_tr141_in,
      I3 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[7]\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[6]\,
      I5 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      O => \REQ_BUFFER_RAW12.buff_tl_i_i_8_n_0\
    );
\REQ_BUFFER_RAW12.buff_tl_i_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \^s_fifo_tv\,
      I1 => s_axis_tready,
      I2 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      O => p_3_in
    );
\REQ_BUFFER_RAW12.buff_tl_i_reg\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => \REQ_BUFFER_RAW12.buff_tl_i_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_tl_i_reg_n_0\,
      R => '0'
    );
\REQ_BUFFER_RAW12.buff_ts_i[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAFFFFA2AA0000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I5 => \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[4]\,
      O => \REQ_BUFFER_RAW12.buff_ts_i[4]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_ts_i[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAFFFFA2AA0000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I5 => \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[5]\,
      O => \REQ_BUFFER_RAW12.buff_ts_i[5]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_ts_i[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAFFFFA2AA0000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I5 => \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[6]\,
      O => \REQ_BUFFER_RAW12.buff_ts_i[6]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_ts_i[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAFFFFA2AA0000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I5 => \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[7]\,
      O => \REQ_BUFFER_RAW12.buff_ts_i[7]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_ts_i[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAFFFFA2AA0000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I5 => \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[8]\,
      O => \REQ_BUFFER_RAW12.buff_ts_i[8]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_ts_i[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAAFFFFA2AA0000"
    )
        port map (
      I0 => \^q\(5),
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I5 => \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[9]\,
      O => \REQ_BUFFER_RAW12.buff_ts_i[9]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_ts_i_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.buff_ts_i[4]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[4]\,
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.buff_ts_i_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.buff_ts_i[5]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[5]\,
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.buff_ts_i_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.buff_ts_i[6]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[6]\,
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.buff_ts_i_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.buff_ts_i[7]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[7]\,
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.buff_ts_i_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.buff_ts_i[8]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[8]\,
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.buff_ts_i_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.buff_tk_i[7]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.buff_ts_i[9]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[9]\,
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.buff_tu_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00800000008000"
    )
        port map (
      I0 => \s_axis_tready__3\,
      I1 => \REQ_BUFFER_RAW12.buff_tu_i_i_2_n_0\,
      I2 => \buf_data_reg_n_0_[0][4]\,
      I3 => vfb_arstn,
      I4 => \REQ_BUFFER_RAW12.buff_tu_i\,
      I5 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_4_n_0\,
      O => \REQ_BUFFER_RAW12.buff_tu_i_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_tu_i_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \buf_valid_reg_n_0_[0]\,
      I1 => \REQ_BUFFER_RAW12.liv_data[63]_i_3_n_0\,
      I2 => cur_dtype_pxls,
      O => \REQ_BUFFER_RAW12.buff_tu_i_i_2_n_0\
    );
\REQ_BUFFER_RAW12.buff_tu_i_reg\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => \REQ_BUFFER_RAW12.buff_tu_i_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_tu_i\,
      R => '0'
    );
\REQ_BUFFER_RAW12.buff_tv_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0808FF08"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tv_i2__2\,
      I1 => \REQ_BUFFER_RAW12.filt_tl_on\,
      I2 => \REQ_BUFFER_RAW12.buff_tl_i_reg_n_0\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.buff_tv_i_reg_0\,
      I5 => \REQ_BUFFER_RAW12.buff_tv_i8_out\,
      O => \REQ_BUFFER_RAW12.buff_tv_i_i_1_n_0\
    );
\REQ_BUFFER_RAW12.buff_tv_i_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01030303"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[6]\,
      I2 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[7]\,
      I3 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[5]\,
      O => \REQ_BUFFER_RAW12.buff_tv_i2__2\
    );
\REQ_BUFFER_RAW12.buff_tv_i_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0FFFFF22022222"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tv_i_i_5_n_0\,
      I1 => \REQ_BUFFER_RAW12.buff_tl_i_reg_n_0\,
      I2 => \^s_fifo_tv\,
      I3 => s_axis_tready,
      I4 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I5 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      O => \REQ_BUFFER_RAW12.buff_tv_i8_out\
    );
\REQ_BUFFER_RAW12.buff_tv_i_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFAFFF8FFF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.filt_tl_on\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      I2 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[6]\,
      I3 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[7]\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      I5 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[5]\,
      O => \REQ_BUFFER_RAW12.buff_tv_i_i_5_n_0\
    );
\REQ_BUFFER_RAW12.buff_tv_i_reg\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => \REQ_BUFFER_RAW12.buff_tv_i_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(7),
      I5 => \REQ_BUFFER_RAW12.liv_data\(0),
      O => \REQ_BUFFER_RAW12.cur_data[0]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(17),
      I5 => \REQ_BUFFER_RAW12.liv_data\(10),
      O => \REQ_BUFFER_RAW12.cur_data[10]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(18),
      I5 => \REQ_BUFFER_RAW12.liv_data\(11),
      O => \REQ_BUFFER_RAW12.cur_data[11]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(19),
      I5 => \REQ_BUFFER_RAW12.liv_data\(12),
      O => \REQ_BUFFER_RAW12.cur_data[12]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(20),
      I5 => \REQ_BUFFER_RAW12.liv_data\(13),
      O => \REQ_BUFFER_RAW12.cur_data[13]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(21),
      I5 => \REQ_BUFFER_RAW12.liv_data\(14),
      O => \REQ_BUFFER_RAW12.cur_data[14]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(22),
      I5 => \REQ_BUFFER_RAW12.liv_data\(15),
      O => \REQ_BUFFER_RAW12.cur_data[15]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(16),
      I5 => \REQ_BUFFER_RAW12.liv_data\(16),
      O => \REQ_BUFFER_RAW12.cur_data[16]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(17),
      I5 => \REQ_BUFFER_RAW12.liv_data\(17),
      O => \REQ_BUFFER_RAW12.cur_data[17]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(18),
      I5 => \REQ_BUFFER_RAW12.liv_data\(18),
      O => \REQ_BUFFER_RAW12.cur_data[18]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(19),
      I5 => \REQ_BUFFER_RAW12.liv_data\(19),
      O => \REQ_BUFFER_RAW12.cur_data[19]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(8),
      I5 => \REQ_BUFFER_RAW12.liv_data\(1),
      O => \REQ_BUFFER_RAW12.cur_data[1]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(20),
      I5 => \REQ_BUFFER_RAW12.liv_data\(20),
      O => \REQ_BUFFER_RAW12.cur_data[20]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(21),
      I5 => \REQ_BUFFER_RAW12.liv_data\(21),
      O => \REQ_BUFFER_RAW12.cur_data[21]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(22),
      I5 => \REQ_BUFFER_RAW12.liv_data\(22),
      O => \REQ_BUFFER_RAW12.cur_data[22]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(23),
      I5 => \REQ_BUFFER_RAW12.liv_data\(23),
      O => \REQ_BUFFER_RAW12.cur_data[23]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(24),
      I5 => \REQ_BUFFER_RAW12.liv_data\(24),
      O => \REQ_BUFFER_RAW12.cur_data[24]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(25),
      I5 => \REQ_BUFFER_RAW12.liv_data\(25),
      O => \REQ_BUFFER_RAW12.cur_data[25]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(26),
      I5 => \REQ_BUFFER_RAW12.liv_data\(26),
      O => \REQ_BUFFER_RAW12.cur_data[26]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(27),
      I5 => \REQ_BUFFER_RAW12.liv_data\(27),
      O => \REQ_BUFFER_RAW12.cur_data[27]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(28),
      I5 => \REQ_BUFFER_RAW12.liv_data\(28),
      O => \REQ_BUFFER_RAW12.cur_data[28]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(29),
      I5 => \REQ_BUFFER_RAW12.liv_data\(29),
      O => \REQ_BUFFER_RAW12.cur_data[29]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(9),
      I5 => \REQ_BUFFER_RAW12.liv_data\(2),
      O => \REQ_BUFFER_RAW12.cur_data[2]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(30),
      I5 => \REQ_BUFFER_RAW12.liv_data\(30),
      O => \REQ_BUFFER_RAW12.cur_data[30]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(31),
      I5 => \REQ_BUFFER_RAW12.liv_data\(31),
      O => \REQ_BUFFER_RAW12.cur_data[31]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[32]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(32),
      I5 => \REQ_BUFFER_RAW12.liv_data\(32),
      O => \REQ_BUFFER_RAW12.cur_data[32]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[33]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(33),
      I5 => \REQ_BUFFER_RAW12.liv_data\(33),
      O => \REQ_BUFFER_RAW12.cur_data[33]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[34]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(34),
      I5 => \REQ_BUFFER_RAW12.liv_data\(34),
      O => \REQ_BUFFER_RAW12.cur_data[34]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[35]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(35),
      I5 => \REQ_BUFFER_RAW12.liv_data\(35),
      O => \REQ_BUFFER_RAW12.cur_data[35]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[36]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(36),
      I5 => \REQ_BUFFER_RAW12.liv_data\(36),
      O => \REQ_BUFFER_RAW12.cur_data[36]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[37]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(37),
      I5 => \REQ_BUFFER_RAW12.liv_data\(37),
      O => \REQ_BUFFER_RAW12.cur_data[37]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[38]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(38),
      I5 => \REQ_BUFFER_RAW12.liv_data\(38),
      O => \REQ_BUFFER_RAW12.cur_data[38]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[39]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(39),
      I5 => \REQ_BUFFER_RAW12.liv_data\(39),
      O => \REQ_BUFFER_RAW12.cur_data[39]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(10),
      I5 => \REQ_BUFFER_RAW12.liv_data\(3),
      O => \REQ_BUFFER_RAW12.cur_data[3]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[40]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(40),
      I5 => \REQ_BUFFER_RAW12.liv_data\(40),
      O => \REQ_BUFFER_RAW12.cur_data[40]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[41]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(41),
      I5 => \REQ_BUFFER_RAW12.liv_data\(41),
      O => \REQ_BUFFER_RAW12.cur_data[41]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[42]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(42),
      I5 => \REQ_BUFFER_RAW12.liv_data\(42),
      O => \REQ_BUFFER_RAW12.cur_data[42]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[43]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(43),
      I5 => \REQ_BUFFER_RAW12.liv_data\(43),
      O => \REQ_BUFFER_RAW12.cur_data[43]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[44]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(44),
      I5 => \REQ_BUFFER_RAW12.liv_data\(44),
      O => \REQ_BUFFER_RAW12.cur_data[44]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[45]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(45),
      I5 => \REQ_BUFFER_RAW12.liv_data\(45),
      O => \REQ_BUFFER_RAW12.cur_data[45]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[46]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(46),
      I5 => \REQ_BUFFER_RAW12.liv_data\(46),
      O => \REQ_BUFFER_RAW12.cur_data[46]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[47]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(47),
      I5 => \REQ_BUFFER_RAW12.liv_data\(47),
      O => \REQ_BUFFER_RAW12.cur_data[47]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[48]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(48),
      I5 => \REQ_BUFFER_RAW12.liv_data\(48),
      O => \REQ_BUFFER_RAW12.cur_data[48]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[49]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(49),
      I5 => \REQ_BUFFER_RAW12.liv_data\(49),
      O => \REQ_BUFFER_RAW12.cur_data[49]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(11),
      I5 => \REQ_BUFFER_RAW12.liv_data\(4),
      O => \REQ_BUFFER_RAW12.cur_data[4]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[50]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(50),
      I5 => \REQ_BUFFER_RAW12.liv_data\(50),
      O => \REQ_BUFFER_RAW12.cur_data[50]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[51]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(51),
      I5 => \REQ_BUFFER_RAW12.liv_data\(51),
      O => \REQ_BUFFER_RAW12.cur_data[51]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[52]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(52),
      I5 => \REQ_BUFFER_RAW12.liv_data\(52),
      O => \REQ_BUFFER_RAW12.cur_data[52]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[53]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(53),
      I5 => \REQ_BUFFER_RAW12.liv_data\(53),
      O => \REQ_BUFFER_RAW12.cur_data[53]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[54]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(54),
      I5 => \REQ_BUFFER_RAW12.liv_data\(54),
      O => \REQ_BUFFER_RAW12.cur_data[54]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[55]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(55),
      I5 => \REQ_BUFFER_RAW12.liv_data\(55),
      O => \REQ_BUFFER_RAW12.cur_data[55]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[56]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(56),
      I5 => \REQ_BUFFER_RAW12.liv_data\(56),
      O => \REQ_BUFFER_RAW12.cur_data[56]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[57]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(57),
      I5 => \REQ_BUFFER_RAW12.liv_data\(57),
      O => \REQ_BUFFER_RAW12.cur_data[57]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[58]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(58),
      I5 => \REQ_BUFFER_RAW12.liv_data\(58),
      O => \REQ_BUFFER_RAW12.cur_data[58]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[59]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(59),
      I5 => \REQ_BUFFER_RAW12.liv_data\(59),
      O => \REQ_BUFFER_RAW12.cur_data[59]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(12),
      I5 => \REQ_BUFFER_RAW12.liv_data\(5),
      O => \REQ_BUFFER_RAW12.cur_data[5]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[60]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(60),
      I5 => \REQ_BUFFER_RAW12.liv_data\(60),
      O => \REQ_BUFFER_RAW12.cur_data[60]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[61]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(61),
      I5 => \REQ_BUFFER_RAW12.liv_data\(61),
      O => \REQ_BUFFER_RAW12.cur_data[61]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[62]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(62),
      I5 => \REQ_BUFFER_RAW12.liv_data\(62),
      O => \REQ_BUFFER_RAW12.cur_data[62]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[63]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => s_axis_tready,
      I1 => \^s_fifo_tv\,
      I2 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      O => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[63]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => sband_td(63),
      I5 => \REQ_BUFFER_RAW12.liv_data\(63),
      O => \REQ_BUFFER_RAW12.cur_data[63]_i_2_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(13),
      I5 => \REQ_BUFFER_RAW12.liv_data\(6),
      O => \REQ_BUFFER_RAW12.cur_data[6]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(14),
      I5 => \REQ_BUFFER_RAW12.liv_data\(7),
      O => \REQ_BUFFER_RAW12.cur_data[7]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(15),
      I5 => \REQ_BUFFER_RAW12.liv_data\(8),
      O => \REQ_BUFFER_RAW12.cur_data[8]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF75008AFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \^q\(16),
      I5 => \REQ_BUFFER_RAW12.liv_data\(9),
      O => \REQ_BUFFER_RAW12.cur_data[9]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.cur_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[0]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[0]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[10]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[10]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[11]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[11]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[12]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[12]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[13]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[13]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[14]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[14]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[15]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[15]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[16]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[16]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[17]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[17]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[18]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[18]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[19]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[19]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[1]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[1]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[20]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[20]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[21]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[21]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[22]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[22]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[23]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[23]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[24]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[24]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[25]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[25]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[26]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[26]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[27]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[27]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[28]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[28]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[29]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[29]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[2]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[2]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[30]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[30]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[31]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[31]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[32]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[32]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[33]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[33]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[34]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[34]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[35]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[35]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[36]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[36]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[37]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[37]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[38]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[38]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[39]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[39]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[3]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[3]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[40]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[40]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[41]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[41]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[42]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[42]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[43]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[43]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[44]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[44]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[45]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[45]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[46]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[46]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[47]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[47]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[48]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[48]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[49]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[49]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[4]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[4]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[50]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[50]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[51]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[51]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[52]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[52]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[53]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[53]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[54]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[54]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[55]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[55]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[56]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[56]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[57]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[57]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[58]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[58]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[59]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[59]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[5]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[5]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[60]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[60]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[61]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[61]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[62]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[62]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[63]_i_2_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[63]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[6]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[6]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[7]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[7]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[8]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[8]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.cur_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.cur_data[63]_i_1_n_0\,
      D => \REQ_BUFFER_RAW12.cur_data[9]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[9]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.filt_tl_on_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F08080F0F08080"
    )
        port map (
      I0 => \^sband_tl\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I2 => vfb_arstn,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.filt_tl_on\,
      I5 => \REQ_BUFFER_RAW12.buff_tl_i_reg_n_0\,
      O => \REQ_BUFFER_RAW12.filt_tl_on_i_1_n_0\
    );
\REQ_BUFFER_RAW12.filt_tl_on_reg\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => \REQ_BUFFER_RAW12.filt_tl_on_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.filt_tl_on\,
      R => '0'
    );
\REQ_BUFFER_RAW12.indx_cntr[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      O => \REQ_BUFFER_RAW12.indx_cntr[0]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.indx_cntr[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I1 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      O => \REQ_BUFFER_RAW12.indx_cntr[1]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.indx_cntr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.indx_cntr[0]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.indx_cntr\(0),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.indx_cntr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.indx_cntr[1]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.indx_cntr\(1),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.liv_data[63]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000000000000"
    )
        port map (
      I0 => buff_tr141_in,
      I1 => \REQ_BUFFER_RAW12.filt_tl_on\,
      I2 => \REQ_BUFFER_RAW12.buff_tl_i_reg_n_0\,
      I3 => cur_dtype_pxls,
      I4 => \REQ_BUFFER_RAW12.liv_data[63]_i_3_n_0\,
      I5 => \buf_valid_reg_n_0_[0]\,
      O => \REQ_BUFFER_RAW12.resi_wdth133_out\
    );
\REQ_BUFFER_RAW12.liv_data[63]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0007"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[5]\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      I2 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[7]\,
      I3 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[6]\,
      O => buff_tr141_in
    );
\REQ_BUFFER_RAW12.liv_data[63]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000000000000"
    )
        port map (
      I0 => \^q\(5),
      I1 => \^q\(4),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \REQ_BUFFER_RAW12.liv_data[63]_i_3_n_0\
    );
\REQ_BUFFER_RAW12.liv_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(7),
      Q => \REQ_BUFFER_RAW12.liv_data\(0),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(17),
      Q => \REQ_BUFFER_RAW12.liv_data\(10),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(18),
      Q => \REQ_BUFFER_RAW12.liv_data\(11),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(19),
      Q => \REQ_BUFFER_RAW12.liv_data\(12),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(20),
      Q => \REQ_BUFFER_RAW12.liv_data\(13),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(21),
      Q => \REQ_BUFFER_RAW12.liv_data\(14),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(22),
      Q => \REQ_BUFFER_RAW12.liv_data\(15),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(16),
      Q => \REQ_BUFFER_RAW12.liv_data\(16),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(17),
      Q => \REQ_BUFFER_RAW12.liv_data\(17),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(18),
      Q => \REQ_BUFFER_RAW12.liv_data\(18),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(19),
      Q => \REQ_BUFFER_RAW12.liv_data\(19),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(8),
      Q => \REQ_BUFFER_RAW12.liv_data\(1),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(20),
      Q => \REQ_BUFFER_RAW12.liv_data\(20),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(21),
      Q => \REQ_BUFFER_RAW12.liv_data\(21),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(22),
      Q => \REQ_BUFFER_RAW12.liv_data\(22),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(23),
      Q => \REQ_BUFFER_RAW12.liv_data\(23),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(24),
      Q => \REQ_BUFFER_RAW12.liv_data\(24),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(25),
      Q => \REQ_BUFFER_RAW12.liv_data\(25),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(26),
      Q => \REQ_BUFFER_RAW12.liv_data\(26),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(27),
      Q => \REQ_BUFFER_RAW12.liv_data\(27),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(28),
      Q => \REQ_BUFFER_RAW12.liv_data\(28),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(29),
      Q => \REQ_BUFFER_RAW12.liv_data\(29),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(9),
      Q => \REQ_BUFFER_RAW12.liv_data\(2),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(30),
      Q => \REQ_BUFFER_RAW12.liv_data\(30),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(31),
      Q => \REQ_BUFFER_RAW12.liv_data\(31),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(32),
      Q => \REQ_BUFFER_RAW12.liv_data\(32),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(33),
      Q => \REQ_BUFFER_RAW12.liv_data\(33),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(34),
      Q => \REQ_BUFFER_RAW12.liv_data\(34),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(35),
      Q => \REQ_BUFFER_RAW12.liv_data\(35),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(36),
      Q => \REQ_BUFFER_RAW12.liv_data\(36),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(37),
      Q => \REQ_BUFFER_RAW12.liv_data\(37),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(38),
      Q => \REQ_BUFFER_RAW12.liv_data\(38),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(39),
      Q => \REQ_BUFFER_RAW12.liv_data\(39),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(10),
      Q => \REQ_BUFFER_RAW12.liv_data\(3),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(40),
      Q => \REQ_BUFFER_RAW12.liv_data\(40),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(41),
      Q => \REQ_BUFFER_RAW12.liv_data\(41),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(42),
      Q => \REQ_BUFFER_RAW12.liv_data\(42),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(43),
      Q => \REQ_BUFFER_RAW12.liv_data\(43),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(44),
      Q => \REQ_BUFFER_RAW12.liv_data\(44),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(45),
      Q => \REQ_BUFFER_RAW12.liv_data\(45),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(46),
      Q => \REQ_BUFFER_RAW12.liv_data\(46),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(47),
      Q => \REQ_BUFFER_RAW12.liv_data\(47),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(48),
      Q => \REQ_BUFFER_RAW12.liv_data\(48),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(49),
      Q => \REQ_BUFFER_RAW12.liv_data\(49),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(11),
      Q => \REQ_BUFFER_RAW12.liv_data\(4),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(50),
      Q => \REQ_BUFFER_RAW12.liv_data\(50),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(51),
      Q => \REQ_BUFFER_RAW12.liv_data\(51),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(52),
      Q => \REQ_BUFFER_RAW12.liv_data\(52),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(53),
      Q => \REQ_BUFFER_RAW12.liv_data\(53),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(54),
      Q => \REQ_BUFFER_RAW12.liv_data\(54),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(55),
      Q => \REQ_BUFFER_RAW12.liv_data\(55),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(56),
      Q => \REQ_BUFFER_RAW12.liv_data\(56),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(57),
      Q => \REQ_BUFFER_RAW12.liv_data\(57),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(58),
      Q => \REQ_BUFFER_RAW12.liv_data\(58),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(59),
      Q => \REQ_BUFFER_RAW12.liv_data\(59),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(12),
      Q => \REQ_BUFFER_RAW12.liv_data\(5),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(60),
      Q => \REQ_BUFFER_RAW12.liv_data\(60),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(61),
      Q => \REQ_BUFFER_RAW12.liv_data\(61),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(62),
      Q => \REQ_BUFFER_RAW12.liv_data\(62),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_td(63),
      Q => \REQ_BUFFER_RAW12.liv_data\(63),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(13),
      Q => \REQ_BUFFER_RAW12.liv_data\(6),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(14),
      Q => \REQ_BUFFER_RAW12.liv_data\(7),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(15),
      Q => \REQ_BUFFER_RAW12.liv_data\(8),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(16),
      Q => \REQ_BUFFER_RAW12.liv_data\(9),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_tk_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_tk(0),
      Q => \REQ_BUFFER_RAW12.liv_tk\(0),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.liv_tk_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_tk(1),
      Q => \REQ_BUFFER_RAW12.liv_tk\(1),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.liv_tk_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => \^q\(6),
      Q => \REQ_BUFFER_RAW12.liv_tk\(2),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.liv_tk_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_tk(3),
      Q => \REQ_BUFFER_RAW12.liv_tk\(3),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.liv_tk_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_tk(4),
      Q => \REQ_BUFFER_RAW12.liv_tk\(4),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.liv_tk_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_tk(5),
      Q => \REQ_BUFFER_RAW12.liv_tk\(5),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.liv_tk_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_tk(6),
      Q => \REQ_BUFFER_RAW12.liv_tk\(6),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.liv_tk_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      D => sband_tk(7),
      Q => \REQ_BUFFER_RAW12.liv_tk\(7),
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.liv_ts[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5DFF0000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tl_i_reg_n_0\,
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      O => \REQ_BUFFER_RAW12.liv_ts\
    );
\REQ_BUFFER_RAW12.liv_ts_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.liv_ts\,
      D => \^q\(0),
      Q => \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[4]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_ts_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.liv_ts\,
      D => \^q\(1),
      Q => \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[5]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_ts_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.liv_ts\,
      D => \^q\(2),
      Q => \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[6]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_ts_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.liv_ts\,
      D => \^q\(3),
      Q => \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[7]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_ts_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.liv_ts\,
      D => \^q\(4),
      Q => \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[8]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.liv_ts_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.liv_ts\,
      D => \^q\(5),
      Q => \REQ_BUFFER_RAW12.liv_ts_reg_n_0_[9]\,
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data[63]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      O => \REQ_BUFFER_RAW12.indx_cntr0\
    );
\REQ_BUFFER_RAW12.res_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[16]\,
      Q => \REQ_BUFFER_RAW12.res_data\(16),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[17]\,
      Q => \REQ_BUFFER_RAW12.res_data\(17),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[18]\,
      Q => \REQ_BUFFER_RAW12.res_data\(18),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[19]\,
      Q => \REQ_BUFFER_RAW12.res_data\(19),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[20]\,
      Q => \REQ_BUFFER_RAW12.res_data\(20),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[21]\,
      Q => \REQ_BUFFER_RAW12.res_data\(21),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[22]\,
      Q => \REQ_BUFFER_RAW12.res_data\(22),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[23]\,
      Q => \REQ_BUFFER_RAW12.res_data\(23),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[24]\,
      Q => \REQ_BUFFER_RAW12.res_data\(24),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[25]\,
      Q => \REQ_BUFFER_RAW12.res_data\(25),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[26]\,
      Q => \REQ_BUFFER_RAW12.res_data\(26),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[27]\,
      Q => \REQ_BUFFER_RAW12.res_data\(27),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[28]\,
      Q => \REQ_BUFFER_RAW12.res_data\(28),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[29]\,
      Q => \REQ_BUFFER_RAW12.res_data\(29),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[30]\,
      Q => \REQ_BUFFER_RAW12.res_data\(30),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[31]\,
      Q => \REQ_BUFFER_RAW12.res_data\(31),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[32]\,
      Q => \REQ_BUFFER_RAW12.res_data\(32),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[33]\,
      Q => \REQ_BUFFER_RAW12.res_data\(33),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[34]\,
      Q => \REQ_BUFFER_RAW12.res_data\(34),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[35]\,
      Q => \REQ_BUFFER_RAW12.res_data\(35),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[36]\,
      Q => \REQ_BUFFER_RAW12.res_data\(36),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[37]\,
      Q => \REQ_BUFFER_RAW12.res_data\(37),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[38]\,
      Q => \REQ_BUFFER_RAW12.res_data\(38),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[39]\,
      Q => \REQ_BUFFER_RAW12.res_data\(39),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[40]\,
      Q => \REQ_BUFFER_RAW12.res_data\(40),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[41]\,
      Q => \REQ_BUFFER_RAW12.res_data\(41),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[42]\,
      Q => \REQ_BUFFER_RAW12.res_data\(42),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[43]\,
      Q => \REQ_BUFFER_RAW12.res_data\(43),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[44]\,
      Q => \REQ_BUFFER_RAW12.res_data\(44),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[45]\,
      Q => \REQ_BUFFER_RAW12.res_data\(45),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[46]\,
      Q => \REQ_BUFFER_RAW12.res_data\(46),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[47]\,
      Q => \REQ_BUFFER_RAW12.res_data\(47),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[48]\,
      Q => \REQ_BUFFER_RAW12.res_data\(48),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[49]\,
      Q => \REQ_BUFFER_RAW12.res_data\(49),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[50]\,
      Q => \REQ_BUFFER_RAW12.res_data\(50),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[51]\,
      Q => \REQ_BUFFER_RAW12.res_data\(51),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[52]\,
      Q => \REQ_BUFFER_RAW12.res_data\(52),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[53]\,
      Q => \REQ_BUFFER_RAW12.res_data\(53),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[54]\,
      Q => \REQ_BUFFER_RAW12.res_data\(54),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[55]\,
      Q => \REQ_BUFFER_RAW12.res_data\(55),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[56]\,
      Q => \REQ_BUFFER_RAW12.res_data\(56),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[57]\,
      Q => \REQ_BUFFER_RAW12.res_data\(57),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[58]\,
      Q => \REQ_BUFFER_RAW12.res_data\(58),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[59]\,
      Q => \REQ_BUFFER_RAW12.res_data\(59),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[60]\,
      Q => \REQ_BUFFER_RAW12.res_data\(60),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[61]\,
      Q => \REQ_BUFFER_RAW12.res_data\(61),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[62]\,
      Q => \REQ_BUFFER_RAW12.res_data\(62),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.res_data_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[63]\,
      Q => \REQ_BUFFER_RAW12.res_data\(63),
      R => \^sr\(0)
    );
\REQ_BUFFER_RAW12.resi_wdth[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2EE2"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I2 => sband_tk(1),
      I3 => \REQ_BUFFER_RAW12.resi_wdth[3]_i_2_n_0\,
      O => \REQ_BUFFER_RAW12.resi_wdth[3]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth[4]_i_5_n_0\,
      I1 => sband_tk(7),
      I2 => sband_tk(6),
      I3 => sband_tk(5),
      I4 => sband_tk(0),
      I5 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      O => \REQ_BUFFER_RAW12.resi_wdth[3]_i_2_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3C55C355"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth[4]_i_2_n_0\,
      I2 => \REQ_BUFFER_RAW12.resi_wdth[4]_i_3_n_0\,
      I3 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth[4]_i_4_n_0\,
      O => \REQ_BUFFER_RAW12.resi_wdth[4]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F66060F660F6F660"
    )
        port map (
      I0 => sband_tk(0),
      I1 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      I2 => \REQ_BUFFER_RAW12.resi_wdth[4]_i_5_n_0\,
      I3 => sband_tk(7),
      I4 => sband_tk(6),
      I5 => sband_tk(5),
      O => \REQ_BUFFER_RAW12.resi_wdth[4]_i_2_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A995566A"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth[5]_i_5_n_0\,
      I1 => sband_tk(5),
      I2 => sband_tk(6),
      I3 => sband_tk(7),
      I4 => \REQ_BUFFER_RAW12.resi_wdth[5]_i_4_n_0\,
      O => \REQ_BUFFER_RAW12.resi_wdth[4]_i_3_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"9669FFFF"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      I1 => sband_tk(0),
      I2 => \REQ_BUFFER_RAW12.resi_wdth[4]_i_6_n_0\,
      I3 => \REQ_BUFFER_RAW12.resi_wdth[4]_i_5_n_0\,
      I4 => sband_tk(1),
      O => \REQ_BUFFER_RAW12.resi_wdth[4]_i_4_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[4]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \^q\(6),
      I1 => sband_tk(4),
      I2 => sband_tk(3),
      O => \REQ_BUFFER_RAW12.resi_wdth[4]_i_5_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[4]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => sband_tk(7),
      I1 => sband_tk(6),
      I2 => sband_tk(5),
      O => \REQ_BUFFER_RAW12.resi_wdth[4]_i_6_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66660FF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth[5]_i_2_n_0\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth[5]_i_3_n_0\,
      I2 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[5]\,
      I3 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      O => \REQ_BUFFER_RAW12.resi_wdth[5]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEE8E888"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth[5]_i_4_n_0\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth[5]_i_5_n_0\,
      I2 => sband_tk(5),
      I3 => sband_tk(6),
      I4 => sband_tk(7),
      O => \REQ_BUFFER_RAW12.resi_wdth[5]_i_2_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A999955556666AAA"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[5]\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_9_n_0\,
      I2 => sband_tk(0),
      I3 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      I5 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_11_n_0\,
      O => \REQ_BUFFER_RAW12.resi_wdth[5]_i_3_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8778878787878787"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      I1 => sband_tk(0),
      I2 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      I3 => s_axis_tready,
      I4 => \^s_fifo_tv\,
      I5 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      O => \REQ_BUFFER_RAW12.resi_wdth[5]_i_4_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[5]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => sband_tk(4),
      I1 => \^q\(6),
      I2 => sband_tk(3),
      O => \REQ_BUFFER_RAW12.resi_wdth[5]_i_5_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"66666666F0000FFF"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth[6]_i_2_n_0\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth[6]_i_3_n_0\,
      I2 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      I3 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[5]\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[6]\,
      I5 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      O => \REQ_BUFFER_RAW12.resi_wdth[6]_i_1_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA80557F7FFF8000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[5]\,
      I1 => sband_tk(0),
      I2 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      I3 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[6]\,
      I5 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_9_n_0\,
      O => \REQ_BUFFER_RAW12.resi_wdth[6]_i_2_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[6]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_11_n_0\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth[6]_i_4_n_0\,
      I2 => \REQ_BUFFER_RAW12.resi_wdth[5]_i_2_n_0\,
      O => \REQ_BUFFER_RAW12.resi_wdth[6]_i_3_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F15151580EAEAEA"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      I2 => sband_tk(0),
      I3 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_4_n_0\,
      I4 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I5 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[5]\,
      O => \REQ_BUFFER_RAW12.resi_wdth[6]_i_4_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A200FFFF"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tl_i_reg_n_0\,
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I4 => vfb_arstn,
      O => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.resi_wdth[7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF7F7F7F7000000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I1 => \^s_fifo_tv\,
      I2 => s_axis_tready,
      I3 => sband_tk(0),
      I4 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      I5 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      O => \REQ_BUFFER_RAW12.resi_wdth[7]_i_10_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F999999099909000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth[5]_i_4_n_0\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_12_n_0\,
      I2 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_13_n_0\,
      I3 => \REQ_BUFFER_RAW12.resi_wdth[4]_i_6_n_0\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth[4]_i_5_n_0\,
      I5 => sband_tk(1),
      O => \REQ_BUFFER_RAW12.resi_wdth[7]_i_11_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[7]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E8E8E817E8171717"
    )
        port map (
      I0 => sband_tk(7),
      I1 => sband_tk(6),
      I2 => sband_tk(5),
      I3 => sband_tk(3),
      I4 => \^q\(6),
      I5 => sband_tk(4),
      O => \REQ_BUFFER_RAW12.resi_wdth[7]_i_12_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[7]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      I1 => sband_tk(0),
      O => \REQ_BUFFER_RAW12.resi_wdth[7]_i_13_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000FFF8"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[5]\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      I2 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[7]\,
      I3 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[6]\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_4_n_0\,
      I5 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      O => \REQ_BUFFER_RAW12.resi_wdth[7]_i_2_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"99999999F00FFF00"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_5_n_0\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_6_n_0\,
      I2 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[6]\,
      I3 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[7]\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_7_n_0\,
      I5 => \REQ_BUFFER_RAW12.resi_wdth133_out\,
      O => \REQ_BUFFER_RAW12.resi_wdth[7]_i_3_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[7]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2F"
    )
        port map (
      I0 => \^s_fifo_tv\,
      I1 => s_axis_tready,
      I2 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      O => \REQ_BUFFER_RAW12.resi_wdth[7]_i_4_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAA6A5595AAAA"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[7]\,
      I1 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I2 => \^s_fifo_tv\,
      I3 => s_axis_tready,
      I4 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_8_n_0\,
      I5 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[6]\,
      O => \REQ_BUFFER_RAW12.resi_wdth[7]_i_5_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6F99999FFF9F9FFF"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_9_n_0\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[6]\,
      I2 => \REQ_BUFFER_RAW12.resi_wdth[5]_i_2_n_0\,
      I3 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[5]\,
      I4 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_10_n_0\,
      I5 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_11_n_0\,
      O => \REQ_BUFFER_RAW12.resi_wdth[7]_i_6_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[5]\,
      O => \REQ_BUFFER_RAW12.resi_wdth[7]_i_7_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F151515FFFFFFFF"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      I1 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      I2 => sband_tk(0),
      I3 => \REQ_BUFFER_RAW12.resi_wdth[7]_i_4_n_0\,
      I4 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I5 => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[5]\,
      O => \REQ_BUFFER_RAW12.resi_wdth[7]_i_8_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth[7]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => s_axis_tready,
      I1 => \^s_fifo_tv\,
      I2 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      O => \REQ_BUFFER_RAW12.resi_wdth[7]_i_9_n_0\
    );
\REQ_BUFFER_RAW12.resi_wdth_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth[7]_i_2_n_0\,
      D => \REQ_BUFFER_RAW12.resi_wdth[3]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[3]\,
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.resi_wdth_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth[7]_i_2_n_0\,
      D => \REQ_BUFFER_RAW12.resi_wdth[4]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[4]\,
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.resi_wdth_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth[7]_i_2_n_0\,
      D => \REQ_BUFFER_RAW12.resi_wdth[5]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[5]\,
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.resi_wdth_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth[7]_i_2_n_0\,
      D => \REQ_BUFFER_RAW12.resi_wdth[6]_i_1_n_0\,
      Q => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[6]\,
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\REQ_BUFFER_RAW12.resi_wdth_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.resi_wdth[7]_i_2_n_0\,
      D => \REQ_BUFFER_RAW12.resi_wdth[7]_i_3_n_0\,
      Q => \REQ_BUFFER_RAW12.resi_wdth_reg_n_0_[7]\,
      R => \REQ_BUFFER_RAW12.resi_wdth\
    );
\buf_data[0][100]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(8),
      I3 => \buf_data_reg[1]_0\(100),
      O => \p_2_in__0\(100)
    );
\buf_data[0][101]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(9),
      I3 => \buf_data_reg[1]_0\(101),
      O => \p_2_in__0\(101)
    );
\buf_data[0][102]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(10),
      I3 => \buf_data_reg[1]_0\(102),
      O => \p_2_in__0\(102)
    );
\buf_data[0][103]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(11),
      I3 => \buf_data_reg[1]_0\(103),
      O => \p_2_in__0\(103)
    );
\buf_data[0][104]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(12),
      I3 => \buf_data_reg[1]_0\(104),
      O => \p_2_in__0\(104)
    );
\buf_data[0][105]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(13),
      I3 => \buf_data_reg[1]_0\(105),
      O => \p_2_in__0\(105)
    );
\buf_data[0][106]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(14),
      I3 => \buf_data_reg[1]_0\(106),
      O => \p_2_in__0\(106)
    );
\buf_data[0][107]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(15),
      I3 => \buf_data_reg[1]_0\(107),
      O => \p_2_in__0\(107)
    );
\buf_data[0][108]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(16),
      I3 => \buf_data_reg[1]_0\(108),
      O => \p_2_in__0\(108)
    );
\buf_data[0][109]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(17),
      I3 => \buf_data_reg[1]_0\(109),
      O => \p_2_in__0\(109)
    );
\buf_data[0][110]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(18),
      I3 => \buf_data_reg[1]_0\(110),
      O => \p_2_in__0\(110)
    );
\buf_data[0][111]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(19),
      I3 => \buf_data_reg[1]_0\(111),
      O => \p_2_in__0\(111)
    );
\buf_data[0][112]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(20),
      I3 => \buf_data_reg[1]_0\(112),
      O => \p_2_in__0\(112)
    );
\buf_data[0][113]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(21),
      I3 => \buf_data_reg[1]_0\(113),
      O => \p_2_in__0\(113)
    );
\buf_data[0][114]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(22),
      I3 => \buf_data_reg[1]_0\(114),
      O => \p_2_in__0\(114)
    );
\buf_data[0][115]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(23),
      I3 => \buf_data_reg[1]_0\(115),
      O => \p_2_in__0\(115)
    );
\buf_data[0][116]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(24),
      I3 => \buf_data_reg[1]_0\(116),
      O => \p_2_in__0\(116)
    );
\buf_data[0][117]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(25),
      I3 => \buf_data_reg[1]_0\(117),
      O => \p_2_in__0\(117)
    );
\buf_data[0][118]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(26),
      I3 => \buf_data_reg[1]_0\(118),
      O => \p_2_in__0\(118)
    );
\buf_data[0][119]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(27),
      I3 => \buf_data_reg[1]_0\(119),
      O => \p_2_in__0\(119)
    );
\buf_data[0][120]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(28),
      I3 => \buf_data_reg[1]_0\(120),
      O => \p_2_in__0\(120)
    );
\buf_data[0][121]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(29),
      I3 => \buf_data_reg[1]_0\(121),
      O => \p_2_in__0\(121)
    );
\buf_data[0][122]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(30),
      I3 => \buf_data_reg[1]_0\(122),
      O => \p_2_in__0\(122)
    );
\buf_data[0][123]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(31),
      I3 => \buf_data_reg[1]_0\(123),
      O => \p_2_in__0\(123)
    );
\buf_data[0][124]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(32),
      I3 => \buf_data_reg[1]_0\(124),
      O => \p_2_in__0\(124)
    );
\buf_data[0][125]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(33),
      I3 => \buf_data_reg[1]_0\(125),
      O => \p_2_in__0\(125)
    );
\buf_data[0][126]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(34),
      I3 => \buf_data_reg[1]_0\(126),
      O => \p_2_in__0\(126)
    );
\buf_data[0][127]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(35),
      I3 => \buf_data_reg[1]_0\(127),
      O => \p_2_in__0\(127)
    );
\buf_data[0][128]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(36),
      I3 => \buf_data_reg[1]_0\(128),
      O => \p_2_in__0\(128)
    );
\buf_data[0][129]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(37),
      I3 => \buf_data_reg[1]_0\(129),
      O => \p_2_in__0\(129)
    );
\buf_data[0][130]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(38),
      I3 => \buf_data_reg[1]_0\(130),
      O => \p_2_in__0\(130)
    );
\buf_data[0][131]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(39),
      I3 => \buf_data_reg[1]_0\(131),
      O => \p_2_in__0\(131)
    );
\buf_data[0][132]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(40),
      I3 => \buf_data_reg[1]_0\(132),
      O => \p_2_in__0\(132)
    );
\buf_data[0][133]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(41),
      I3 => \buf_data_reg[1]_0\(133),
      O => \p_2_in__0\(133)
    );
\buf_data[0][134]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(42),
      I3 => \buf_data_reg[1]_0\(134),
      O => \p_2_in__0\(134)
    );
\buf_data[0][135]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(43),
      I3 => \buf_data_reg[1]_0\(135),
      O => \p_2_in__0\(135)
    );
\buf_data[0][136]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(44),
      I3 => \buf_data_reg[1]_0\(136),
      O => \p_2_in__0\(136)
    );
\buf_data[0][137]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(45),
      I3 => \buf_data_reg[1]_0\(137),
      O => \p_2_in__0\(137)
    );
\buf_data[0][138]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(46),
      I3 => \buf_data_reg[1]_0\(138),
      O => \p_2_in__0\(138)
    );
\buf_data[0][139]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(47),
      I3 => \buf_data_reg[1]_0\(139),
      O => \p_2_in__0\(139)
    );
\buf_data[0][140]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(48),
      I3 => \buf_data_reg[1]_0\(140),
      O => \p_2_in__0\(140)
    );
\buf_data[0][141]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(49),
      I3 => \buf_data_reg[1]_0\(141),
      O => \p_2_in__0\(141)
    );
\buf_data[0][142]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(50),
      I3 => \buf_data_reg[1]_0\(142),
      O => \p_2_in__0\(142)
    );
\buf_data[0][143]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(51),
      I3 => \buf_data_reg[1]_0\(143),
      O => \p_2_in__0\(143)
    );
\buf_data[0][144]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(52),
      I3 => \buf_data_reg[1]_0\(144),
      O => \p_2_in__0\(144)
    );
\buf_data[0][145]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(53),
      I3 => \buf_data_reg[1]_0\(145),
      O => \p_2_in__0\(145)
    );
\buf_data[0][146]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(54),
      I3 => \buf_data_reg[1]_0\(146),
      O => \p_2_in__0\(146)
    );
\buf_data[0][147]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(55),
      I3 => \buf_data_reg[1]_0\(147),
      O => \p_2_in__0\(147)
    );
\buf_data[0][148]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(56),
      I3 => \buf_data_reg[1]_0\(148),
      O => \p_2_in__0\(148)
    );
\buf_data[0][149]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(57),
      I3 => \buf_data_reg[1]_0\(149),
      O => \p_2_in__0\(149)
    );
\buf_data[0][150]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(58),
      I3 => \buf_data_reg[1]_0\(150),
      O => \p_2_in__0\(150)
    );
\buf_data[0][151]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(59),
      I3 => \buf_data_reg[1]_0\(151),
      O => \p_2_in__0\(151)
    );
\buf_data[0][152]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(60),
      I3 => \buf_data_reg[1]_0\(152),
      O => \p_2_in__0\(152)
    );
\buf_data[0][153]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(61),
      I3 => \buf_data_reg[1]_0\(153),
      O => \p_2_in__0\(153)
    );
\buf_data[0][154]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(62),
      I3 => \buf_data_reg[1]_0\(154),
      O => \p_2_in__0\(154)
    );
\buf_data[0][155]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(63),
      I3 => \buf_data_reg[1]_0\(155),
      O => \p_2_in__0\(155)
    );
\buf_data[0][156]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(64),
      I3 => \buf_data_reg[1]_0\(156),
      O => \p_2_in__0\(156)
    );
\buf_data[0][157]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(65),
      I3 => \buf_data_reg[1]_0\(157),
      O => \p_2_in__0\(157)
    );
\buf_data[0][158]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(66),
      I3 => \buf_data_reg[1]_0\(158),
      O => \p_2_in__0\(158)
    );
\buf_data[0][159]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(67),
      I3 => \buf_data_reg[1]_0\(159),
      O => \p_2_in__0\(159)
    );
\buf_data[0][160]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(68),
      I3 => \buf_data_reg[1]_0\(160),
      O => \p_2_in__0\(160)
    );
\buf_data[0][161]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(69),
      I3 => \buf_data_reg[1]_0\(161),
      O => \p_2_in__0\(161)
    );
\buf_data[0][162]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(70),
      I3 => \buf_data_reg[1]_0\(162),
      O => \p_2_in__0\(162)
    );
\buf_data[0][163]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(71),
      I3 => \buf_data_reg[1]_0\(163),
      O => \p_2_in__0\(163)
    );
\buf_data[0][164]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(72),
      I3 => \buf_data_reg[1]_0\(164),
      O => \p_2_in__0\(164)
    );
\buf_data[0][165]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(73),
      I3 => \buf_data_reg[1]_0\(165),
      O => \p_2_in__0\(165)
    );
\buf_data[0][166]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(74),
      I3 => \buf_data_reg[1]_0\(166),
      O => \p_2_in__0\(166)
    );
\buf_data[0][167]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(75),
      I3 => \buf_data_reg[1]_0\(167),
      O => \p_2_in__0\(167)
    );
\buf_data[0][168]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(76),
      I3 => \buf_data_reg[1]_0\(168),
      O => \p_2_in__0\(168)
    );
\buf_data[0][169]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(77),
      I3 => \buf_data_reg[1]_0\(169),
      O => \p_2_in__0\(169)
    );
\buf_data[0][170]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(78),
      I3 => \buf_data_reg[1]_0\(170),
      O => \p_2_in__0\(170)
    );
\buf_data[0][171]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(79),
      I3 => \buf_data_reg[1]_0\(171),
      O => \p_2_in__0\(171)
    );
\buf_data[0][172]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F1A0"
    )
        port map (
      I0 => p_0_in,
      I1 => \buf_valid_reg_n_0_[0]\,
      I2 => cur_dtype_pxls1,
      I3 => s_axis_tvalid,
      O => \buf_data[0][172]_i_1_n_0\
    );
\buf_data[0][172]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(80),
      I3 => \buf_data_reg[1]_0\(172),
      O => \p_2_in__0\(172)
    );
\buf_data[0][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(0),
      I3 => \buf_data_reg[1]_0\(4),
      O => \p_2_in__0\(4)
    );
\buf_data[0][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(1),
      I3 => \buf_data_reg[1]_0\(5),
      O => \p_2_in__0\(5)
    );
\buf_data[0][68]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(2),
      I3 => \buf_data_reg[1]_0\(68),
      O => \p_2_in__0\(68)
    );
\buf_data[0][69]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(3),
      I3 => \buf_data_reg[1]_0\(69),
      O => \p_2_in__0\(69)
    );
\buf_data[0][70]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(4),
      I3 => \buf_data_reg[1]_0\(70),
      O => \p_2_in__0\(70)
    );
\buf_data[0][71]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(5),
      I3 => \buf_data_reg[1]_0\(71),
      O => \p_2_in__0\(71)
    );
\buf_data[0][72]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(6),
      I3 => \buf_data_reg[1]_0\(72),
      O => \p_2_in__0\(72)
    );
\buf_data[0][73]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => D(7),
      I3 => \buf_data_reg[1]_0\(73),
      O => \p_2_in__0\(73)
    );
\buf_data[1][172]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \buf_valid_reg_n_0_[0]\,
      I1 => s_axis_tvalid,
      I2 => p_0_in,
      I3 => cur_dtype_pxls1,
      O => \buf_data[1][172]_i_1_n_0\
    );
\buf_data_reg[0][100]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(100),
      Q => sband_tk(0),
      R => \^sr\(0)
    );
\buf_data_reg[0][101]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(101),
      Q => sband_tk(1),
      R => \^sr\(0)
    );
\buf_data_reg[0][102]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(102),
      Q => \^q\(6),
      R => \^sr\(0)
    );
\buf_data_reg[0][103]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(103),
      Q => sband_tk(3),
      R => \^sr\(0)
    );
\buf_data_reg[0][104]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(104),
      Q => sband_tk(4),
      R => \^sr\(0)
    );
\buf_data_reg[0][105]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(105),
      Q => sband_tk(5),
      R => \^sr\(0)
    );
\buf_data_reg[0][106]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(106),
      Q => sband_tk(6),
      R => \^sr\(0)
    );
\buf_data_reg[0][107]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(107),
      Q => sband_tk(7),
      R => \^sr\(0)
    );
\buf_data_reg[0][108]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(108),
      Q => \^q\(7),
      R => \^sr\(0)
    );
\buf_data_reg[0][109]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(109),
      Q => \^q\(8),
      R => \^sr\(0)
    );
\buf_data_reg[0][110]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(110),
      Q => \^q\(9),
      R => \^sr\(0)
    );
\buf_data_reg[0][111]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(111),
      Q => \^q\(10),
      R => \^sr\(0)
    );
\buf_data_reg[0][112]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(112),
      Q => \^q\(11),
      R => \^sr\(0)
    );
\buf_data_reg[0][113]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(113),
      Q => \^q\(12),
      R => \^sr\(0)
    );
\buf_data_reg[0][114]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(114),
      Q => \^q\(13),
      R => \^sr\(0)
    );
\buf_data_reg[0][115]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(115),
      Q => \^q\(14),
      R => \^sr\(0)
    );
\buf_data_reg[0][116]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(116),
      Q => \^q\(15),
      R => \^sr\(0)
    );
\buf_data_reg[0][117]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(117),
      Q => \^q\(16),
      R => \^sr\(0)
    );
\buf_data_reg[0][118]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(118),
      Q => \^q\(17),
      R => \^sr\(0)
    );
\buf_data_reg[0][119]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(119),
      Q => \^q\(18),
      R => \^sr\(0)
    );
\buf_data_reg[0][120]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(120),
      Q => \^q\(19),
      R => \^sr\(0)
    );
\buf_data_reg[0][121]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(121),
      Q => \^q\(20),
      R => \^sr\(0)
    );
\buf_data_reg[0][122]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(122),
      Q => \^q\(21),
      R => \^sr\(0)
    );
\buf_data_reg[0][123]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(123),
      Q => \^q\(22),
      R => \^sr\(0)
    );
\buf_data_reg[0][124]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(124),
      Q => sband_td(16),
      R => \^sr\(0)
    );
\buf_data_reg[0][125]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(125),
      Q => sband_td(17),
      R => \^sr\(0)
    );
\buf_data_reg[0][126]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(126),
      Q => sband_td(18),
      R => \^sr\(0)
    );
\buf_data_reg[0][127]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(127),
      Q => sband_td(19),
      R => \^sr\(0)
    );
\buf_data_reg[0][128]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(128),
      Q => sband_td(20),
      R => \^sr\(0)
    );
\buf_data_reg[0][129]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(129),
      Q => sband_td(21),
      R => \^sr\(0)
    );
\buf_data_reg[0][130]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(130),
      Q => sband_td(22),
      R => \^sr\(0)
    );
\buf_data_reg[0][131]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(131),
      Q => sband_td(23),
      R => \^sr\(0)
    );
\buf_data_reg[0][132]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(132),
      Q => sband_td(24),
      R => \^sr\(0)
    );
\buf_data_reg[0][133]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(133),
      Q => sband_td(25),
      R => \^sr\(0)
    );
\buf_data_reg[0][134]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(134),
      Q => sband_td(26),
      R => \^sr\(0)
    );
\buf_data_reg[0][135]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(135),
      Q => sband_td(27),
      R => \^sr\(0)
    );
\buf_data_reg[0][136]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(136),
      Q => sband_td(28),
      R => \^sr\(0)
    );
\buf_data_reg[0][137]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(137),
      Q => sband_td(29),
      R => \^sr\(0)
    );
\buf_data_reg[0][138]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(138),
      Q => sband_td(30),
      R => \^sr\(0)
    );
\buf_data_reg[0][139]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(139),
      Q => sband_td(31),
      R => \^sr\(0)
    );
\buf_data_reg[0][140]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(140),
      Q => sband_td(32),
      R => \^sr\(0)
    );
\buf_data_reg[0][141]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(141),
      Q => sband_td(33),
      R => \^sr\(0)
    );
\buf_data_reg[0][142]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(142),
      Q => sband_td(34),
      R => \^sr\(0)
    );
\buf_data_reg[0][143]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(143),
      Q => sband_td(35),
      R => \^sr\(0)
    );
\buf_data_reg[0][144]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(144),
      Q => sband_td(36),
      R => \^sr\(0)
    );
\buf_data_reg[0][145]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(145),
      Q => sband_td(37),
      R => \^sr\(0)
    );
\buf_data_reg[0][146]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(146),
      Q => sband_td(38),
      R => \^sr\(0)
    );
\buf_data_reg[0][147]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(147),
      Q => sband_td(39),
      R => \^sr\(0)
    );
\buf_data_reg[0][148]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(148),
      Q => sband_td(40),
      R => \^sr\(0)
    );
\buf_data_reg[0][149]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(149),
      Q => sband_td(41),
      R => \^sr\(0)
    );
\buf_data_reg[0][150]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(150),
      Q => sband_td(42),
      R => \^sr\(0)
    );
\buf_data_reg[0][151]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(151),
      Q => sband_td(43),
      R => \^sr\(0)
    );
\buf_data_reg[0][152]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(152),
      Q => sband_td(44),
      R => \^sr\(0)
    );
\buf_data_reg[0][153]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(153),
      Q => sband_td(45),
      R => \^sr\(0)
    );
\buf_data_reg[0][154]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(154),
      Q => sband_td(46),
      R => \^sr\(0)
    );
\buf_data_reg[0][155]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(155),
      Q => sband_td(47),
      R => \^sr\(0)
    );
\buf_data_reg[0][156]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(156),
      Q => sband_td(48),
      R => \^sr\(0)
    );
\buf_data_reg[0][157]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(157),
      Q => sband_td(49),
      R => \^sr\(0)
    );
\buf_data_reg[0][158]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(158),
      Q => sband_td(50),
      R => \^sr\(0)
    );
\buf_data_reg[0][159]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(159),
      Q => sband_td(51),
      R => \^sr\(0)
    );
\buf_data_reg[0][160]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(160),
      Q => sband_td(52),
      R => \^sr\(0)
    );
\buf_data_reg[0][161]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(161),
      Q => sband_td(53),
      R => \^sr\(0)
    );
\buf_data_reg[0][162]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(162),
      Q => sband_td(54),
      R => \^sr\(0)
    );
\buf_data_reg[0][163]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(163),
      Q => sband_td(55),
      R => \^sr\(0)
    );
\buf_data_reg[0][164]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(164),
      Q => sband_td(56),
      R => \^sr\(0)
    );
\buf_data_reg[0][165]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(165),
      Q => sband_td(57),
      R => \^sr\(0)
    );
\buf_data_reg[0][166]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(166),
      Q => sband_td(58),
      R => \^sr\(0)
    );
\buf_data_reg[0][167]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(167),
      Q => sband_td(59),
      R => \^sr\(0)
    );
\buf_data_reg[0][168]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(168),
      Q => sband_td(60),
      R => \^sr\(0)
    );
\buf_data_reg[0][169]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(169),
      Q => sband_td(61),
      R => \^sr\(0)
    );
\buf_data_reg[0][170]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(170),
      Q => sband_td(62),
      R => \^sr\(0)
    );
\buf_data_reg[0][171]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(171),
      Q => sband_td(63),
      R => \^sr\(0)
    );
\buf_data_reg[0][172]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(172),
      Q => s_axis_tlast_0,
      R => \^sr\(0)
    );
\buf_data_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(4),
      Q => \buf_data_reg_n_0_[0][4]\,
      R => \^sr\(0)
    );
\buf_data_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(5),
      Q => p_0_in39_in,
      R => \^sr\(0)
    );
\buf_data_reg[0][68]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(68),
      Q => \^q\(0),
      R => \^sr\(0)
    );
\buf_data_reg[0][69]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(69),
      Q => \^q\(1),
      R => \^sr\(0)
    );
\buf_data_reg[0][70]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(70),
      Q => \^q\(2),
      R => \^sr\(0)
    );
\buf_data_reg[0][71]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(71),
      Q => \^q\(3),
      R => \^sr\(0)
    );
\buf_data_reg[0][72]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(72),
      Q => \^q\(4),
      R => \^sr\(0)
    );
\buf_data_reg[0][73]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[0][172]_i_1_n_0\,
      D => \p_2_in__0\(73),
      Q => \^q\(5),
      R => \^sr\(0)
    );
\buf_data_reg[1][100]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(8),
      Q => \buf_data_reg[1]_0\(100),
      R => \^sr\(0)
    );
\buf_data_reg[1][101]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(9),
      Q => \buf_data_reg[1]_0\(101),
      R => \^sr\(0)
    );
\buf_data_reg[1][102]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(10),
      Q => \buf_data_reg[1]_0\(102),
      R => \^sr\(0)
    );
\buf_data_reg[1][103]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(11),
      Q => \buf_data_reg[1]_0\(103),
      R => \^sr\(0)
    );
\buf_data_reg[1][104]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(12),
      Q => \buf_data_reg[1]_0\(104),
      R => \^sr\(0)
    );
\buf_data_reg[1][105]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(13),
      Q => \buf_data_reg[1]_0\(105),
      R => \^sr\(0)
    );
\buf_data_reg[1][106]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(14),
      Q => \buf_data_reg[1]_0\(106),
      R => \^sr\(0)
    );
\buf_data_reg[1][107]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(15),
      Q => \buf_data_reg[1]_0\(107),
      R => \^sr\(0)
    );
\buf_data_reg[1][108]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(16),
      Q => \buf_data_reg[1]_0\(108),
      R => \^sr\(0)
    );
\buf_data_reg[1][109]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(17),
      Q => \buf_data_reg[1]_0\(109),
      R => \^sr\(0)
    );
\buf_data_reg[1][110]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(18),
      Q => \buf_data_reg[1]_0\(110),
      R => \^sr\(0)
    );
\buf_data_reg[1][111]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(19),
      Q => \buf_data_reg[1]_0\(111),
      R => \^sr\(0)
    );
\buf_data_reg[1][112]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(20),
      Q => \buf_data_reg[1]_0\(112),
      R => \^sr\(0)
    );
\buf_data_reg[1][113]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(21),
      Q => \buf_data_reg[1]_0\(113),
      R => \^sr\(0)
    );
\buf_data_reg[1][114]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(22),
      Q => \buf_data_reg[1]_0\(114),
      R => \^sr\(0)
    );
\buf_data_reg[1][115]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(23),
      Q => \buf_data_reg[1]_0\(115),
      R => \^sr\(0)
    );
\buf_data_reg[1][116]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(24),
      Q => \buf_data_reg[1]_0\(116),
      R => \^sr\(0)
    );
\buf_data_reg[1][117]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(25),
      Q => \buf_data_reg[1]_0\(117),
      R => \^sr\(0)
    );
\buf_data_reg[1][118]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(26),
      Q => \buf_data_reg[1]_0\(118),
      R => \^sr\(0)
    );
\buf_data_reg[1][119]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(27),
      Q => \buf_data_reg[1]_0\(119),
      R => \^sr\(0)
    );
\buf_data_reg[1][120]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(28),
      Q => \buf_data_reg[1]_0\(120),
      R => \^sr\(0)
    );
\buf_data_reg[1][121]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(29),
      Q => \buf_data_reg[1]_0\(121),
      R => \^sr\(0)
    );
\buf_data_reg[1][122]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(30),
      Q => \buf_data_reg[1]_0\(122),
      R => \^sr\(0)
    );
\buf_data_reg[1][123]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(31),
      Q => \buf_data_reg[1]_0\(123),
      R => \^sr\(0)
    );
\buf_data_reg[1][124]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(32),
      Q => \buf_data_reg[1]_0\(124),
      R => \^sr\(0)
    );
\buf_data_reg[1][125]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(33),
      Q => \buf_data_reg[1]_0\(125),
      R => \^sr\(0)
    );
\buf_data_reg[1][126]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(34),
      Q => \buf_data_reg[1]_0\(126),
      R => \^sr\(0)
    );
\buf_data_reg[1][127]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(35),
      Q => \buf_data_reg[1]_0\(127),
      R => \^sr\(0)
    );
\buf_data_reg[1][128]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(36),
      Q => \buf_data_reg[1]_0\(128),
      R => \^sr\(0)
    );
\buf_data_reg[1][129]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(37),
      Q => \buf_data_reg[1]_0\(129),
      R => \^sr\(0)
    );
\buf_data_reg[1][130]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(38),
      Q => \buf_data_reg[1]_0\(130),
      R => \^sr\(0)
    );
\buf_data_reg[1][131]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(39),
      Q => \buf_data_reg[1]_0\(131),
      R => \^sr\(0)
    );
\buf_data_reg[1][132]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(40),
      Q => \buf_data_reg[1]_0\(132),
      R => \^sr\(0)
    );
\buf_data_reg[1][133]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(41),
      Q => \buf_data_reg[1]_0\(133),
      R => \^sr\(0)
    );
\buf_data_reg[1][134]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(42),
      Q => \buf_data_reg[1]_0\(134),
      R => \^sr\(0)
    );
\buf_data_reg[1][135]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(43),
      Q => \buf_data_reg[1]_0\(135),
      R => \^sr\(0)
    );
\buf_data_reg[1][136]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(44),
      Q => \buf_data_reg[1]_0\(136),
      R => \^sr\(0)
    );
\buf_data_reg[1][137]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(45),
      Q => \buf_data_reg[1]_0\(137),
      R => \^sr\(0)
    );
\buf_data_reg[1][138]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(46),
      Q => \buf_data_reg[1]_0\(138),
      R => \^sr\(0)
    );
\buf_data_reg[1][139]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(47),
      Q => \buf_data_reg[1]_0\(139),
      R => \^sr\(0)
    );
\buf_data_reg[1][140]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(48),
      Q => \buf_data_reg[1]_0\(140),
      R => \^sr\(0)
    );
\buf_data_reg[1][141]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(49),
      Q => \buf_data_reg[1]_0\(141),
      R => \^sr\(0)
    );
\buf_data_reg[1][142]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(50),
      Q => \buf_data_reg[1]_0\(142),
      R => \^sr\(0)
    );
\buf_data_reg[1][143]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(51),
      Q => \buf_data_reg[1]_0\(143),
      R => \^sr\(0)
    );
\buf_data_reg[1][144]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(52),
      Q => \buf_data_reg[1]_0\(144),
      R => \^sr\(0)
    );
\buf_data_reg[1][145]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(53),
      Q => \buf_data_reg[1]_0\(145),
      R => \^sr\(0)
    );
\buf_data_reg[1][146]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(54),
      Q => \buf_data_reg[1]_0\(146),
      R => \^sr\(0)
    );
\buf_data_reg[1][147]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(55),
      Q => \buf_data_reg[1]_0\(147),
      R => \^sr\(0)
    );
\buf_data_reg[1][148]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(56),
      Q => \buf_data_reg[1]_0\(148),
      R => \^sr\(0)
    );
\buf_data_reg[1][149]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(57),
      Q => \buf_data_reg[1]_0\(149),
      R => \^sr\(0)
    );
\buf_data_reg[1][150]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(58),
      Q => \buf_data_reg[1]_0\(150),
      R => \^sr\(0)
    );
\buf_data_reg[1][151]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(59),
      Q => \buf_data_reg[1]_0\(151),
      R => \^sr\(0)
    );
\buf_data_reg[1][152]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(60),
      Q => \buf_data_reg[1]_0\(152),
      R => \^sr\(0)
    );
\buf_data_reg[1][153]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(61),
      Q => \buf_data_reg[1]_0\(153),
      R => \^sr\(0)
    );
\buf_data_reg[1][154]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(62),
      Q => \buf_data_reg[1]_0\(154),
      R => \^sr\(0)
    );
\buf_data_reg[1][155]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(63),
      Q => \buf_data_reg[1]_0\(155),
      R => \^sr\(0)
    );
\buf_data_reg[1][156]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(64),
      Q => \buf_data_reg[1]_0\(156),
      R => \^sr\(0)
    );
\buf_data_reg[1][157]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(65),
      Q => \buf_data_reg[1]_0\(157),
      R => \^sr\(0)
    );
\buf_data_reg[1][158]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(66),
      Q => \buf_data_reg[1]_0\(158),
      R => \^sr\(0)
    );
\buf_data_reg[1][159]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(67),
      Q => \buf_data_reg[1]_0\(159),
      R => \^sr\(0)
    );
\buf_data_reg[1][160]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(68),
      Q => \buf_data_reg[1]_0\(160),
      R => \^sr\(0)
    );
\buf_data_reg[1][161]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(69),
      Q => \buf_data_reg[1]_0\(161),
      R => \^sr\(0)
    );
\buf_data_reg[1][162]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(70),
      Q => \buf_data_reg[1]_0\(162),
      R => \^sr\(0)
    );
\buf_data_reg[1][163]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(71),
      Q => \buf_data_reg[1]_0\(163),
      R => \^sr\(0)
    );
\buf_data_reg[1][164]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(72),
      Q => \buf_data_reg[1]_0\(164),
      R => \^sr\(0)
    );
\buf_data_reg[1][165]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(73),
      Q => \buf_data_reg[1]_0\(165),
      R => \^sr\(0)
    );
\buf_data_reg[1][166]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(74),
      Q => \buf_data_reg[1]_0\(166),
      R => \^sr\(0)
    );
\buf_data_reg[1][167]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(75),
      Q => \buf_data_reg[1]_0\(167),
      R => \^sr\(0)
    );
\buf_data_reg[1][168]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(76),
      Q => \buf_data_reg[1]_0\(168),
      R => \^sr\(0)
    );
\buf_data_reg[1][169]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(77),
      Q => \buf_data_reg[1]_0\(169),
      R => \^sr\(0)
    );
\buf_data_reg[1][170]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(78),
      Q => \buf_data_reg[1]_0\(170),
      R => \^sr\(0)
    );
\buf_data_reg[1][171]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(79),
      Q => \buf_data_reg[1]_0\(171),
      R => \^sr\(0)
    );
\buf_data_reg[1][172]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(80),
      Q => \buf_data_reg[1]_0\(172),
      R => \^sr\(0)
    );
\buf_data_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(0),
      Q => \buf_data_reg[1]_0\(4),
      R => \^sr\(0)
    );
\buf_data_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(1),
      Q => \buf_data_reg[1]_0\(5),
      R => \^sr\(0)
    );
\buf_data_reg[1][68]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(2),
      Q => \buf_data_reg[1]_0\(68),
      R => \^sr\(0)
    );
\buf_data_reg[1][69]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(3),
      Q => \buf_data_reg[1]_0\(69),
      R => \^sr\(0)
    );
\buf_data_reg[1][70]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(4),
      Q => \buf_data_reg[1]_0\(70),
      R => \^sr\(0)
    );
\buf_data_reg[1][71]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(5),
      Q => \buf_data_reg[1]_0\(71),
      R => \^sr\(0)
    );
\buf_data_reg[1][72]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(6),
      Q => \buf_data_reg[1]_0\(72),
      R => \^sr\(0)
    );
\buf_data_reg[1][73]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \buf_data[1][172]_i_1_n_0\,
      D => D(7),
      Q => \buf_data_reg[1]_0\(73),
      R => \^sr\(0)
    );
\buf_valid[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FDB8"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => p_0_in,
      I2 => s_axis_tvalid,
      I3 => \buf_valid_reg_n_0_[0]\,
      O => \buf_valid[0]_i_1_n_0\
    );
\buf_valid[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F8"
    )
        port map (
      I0 => \buf_valid_reg_n_0_[0]\,
      I1 => s_axis_tvalid,
      I2 => p_0_in,
      I3 => cur_dtype_pxls1,
      O => \buf_valid[1]_i_1_n_0\
    );
\buf_valid[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF88800000000"
    )
        port map (
      I0 => \buf_valid_reg[1]_1\,
      I1 => sband_tl_r_reg,
      I2 => buff_tr141_in,
      I3 => \buf_valid[1]_i_4_n_0\,
      I4 => cur_dtype_sink_reg_n_0,
      I5 => \buf_valid_reg_n_0_[0]\,
      O => cur_dtype_pxls1
    );
\buf_valid[1]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tl_i_reg_n_0\,
      I1 => \REQ_BUFFER_RAW12.filt_tl_on\,
      I2 => cur_dtype_pxls,
      O => \buf_valid[1]_i_4_n_0\
    );
\buf_valid_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => \buf_valid[0]_i_1_n_0\,
      Q => \buf_valid_reg_n_0_[0]\,
      R => \^sr\(0)
    );
\buf_valid_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => \buf_valid[1]_i_1_n_0\,
      Q => p_0_in,
      R => \^sr\(0)
    );
cur_dtype_pxls_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^sband_tl\,
      I1 => vfb_arstn,
      O => cur_dtype_sink
    );
cur_dtype_pxls_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => cur_dtype_pxls0,
      I1 => cur_dtype_pxls,
      O => cur_dtype_pxls_i_2_n_0
    );
cur_dtype_pxls_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000000000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => cur_dtype_pxls_i_4_n_0,
      I5 => \buf_valid_reg_n_0_[0]\,
      O => cur_dtype_pxls0
    );
cur_dtype_pxls_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^q\(5),
      I1 => \^q\(4),
      O => cur_dtype_pxls_i_4_n_0
    );
cur_dtype_pxls_reg: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => cur_dtype_pxls_i_2_n_0,
      Q => cur_dtype_pxls,
      R => cur_dtype_sink
    );
cur_dtype_sink_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF04"
    )
        port map (
      I0 => sban_dtvc,
      I1 => \buf_valid_reg_n_0_[0]\,
      I2 => \main_dtvc__4\,
      I3 => cur_dtype_sink_reg_n_0,
      O => cur_dtype_sink_i_1_n_0
    );
cur_dtype_sink_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(4),
      I5 => \^q\(5),
      O => \main_dtvc__4\
    );
cur_dtype_sink_reg: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => cur_dtype_sink_i_1_n_0,
      Q => cur_dtype_sink_reg_n_0,
      R => cur_dtype_sink
    );
cur_dtype_udef_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => sban_dtvc,
      I1 => \buf_valid_reg_n_0_[0]\,
      I2 => \^cur_dtype_udef\,
      O => cur_dtype_udef_i_1_n_0
    );
cur_dtype_udef_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020088888888"
    )
        port map (
      I0 => \^q\(5),
      I1 => \^q\(4),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => sban_dtvc
    );
cur_dtype_udef_reg: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => cur_dtype_udef_i_1_n_0,
      Q => \^cur_dtype_udef\,
      R => cur_dtype_sink
    );
s_axis_tready_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in,
      O => \buf_valid_reg[1]_0\
    );
\s_fifo_td[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(48),
      I1 => \REQ_BUFFER_RAW12.res_data\(32),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[16]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[0]\,
      O => buff_td(16)
    );
\s_fifo_td[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(38),
      I1 => \REQ_BUFFER_RAW12.res_data\(22),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[6]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(54),
      O => buff_td(6)
    );
\s_fifo_td[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(39),
      I1 => \REQ_BUFFER_RAW12.res_data\(23),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[7]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(55),
      O => buff_td(7)
    );
\s_fifo_td[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(52),
      I1 => \REQ_BUFFER_RAW12.res_data\(36),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[20]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[4]\,
      O => buff_td(20)
    );
\s_fifo_td[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(53),
      I1 => \REQ_BUFFER_RAW12.res_data\(37),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[21]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[5]\,
      O => buff_td(21)
    );
\s_fifo_td[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(54),
      I1 => \REQ_BUFFER_RAW12.res_data\(38),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[22]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[6]\,
      O => buff_td(22)
    );
\s_fifo_td[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(55),
      I1 => \REQ_BUFFER_RAW12.res_data\(39),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[23]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[7]\,
      O => buff_td(23)
    );
\s_fifo_td[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(49),
      I1 => \REQ_BUFFER_RAW12.res_data\(33),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[17]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[1]\,
      O => buff_td(17)
    );
\s_fifo_td[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(40),
      I1 => \REQ_BUFFER_RAW12.res_data\(24),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[8]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(56),
      O => buff_td(8)
    );
\s_fifo_td[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(41),
      I1 => \REQ_BUFFER_RAW12.res_data\(25),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[9]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(57),
      O => buff_td(9)
    );
\s_fifo_td[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(42),
      I1 => \REQ_BUFFER_RAW12.res_data\(26),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[10]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(58),
      O => buff_td(10)
    );
\s_fifo_td[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(43),
      I1 => \REQ_BUFFER_RAW12.res_data\(27),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[11]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(59),
      O => buff_td(11)
    );
\s_fifo_td[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(44),
      I1 => \REQ_BUFFER_RAW12.res_data\(28),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[12]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(60),
      O => buff_td(12)
    );
\s_fifo_td[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(45),
      I1 => \REQ_BUFFER_RAW12.res_data\(29),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[13]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(61),
      O => buff_td(13)
    );
\s_fifo_td[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(46),
      I1 => \REQ_BUFFER_RAW12.res_data\(30),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[14]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(62),
      O => buff_td(14)
    );
\s_fifo_td[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(47),
      I1 => \REQ_BUFFER_RAW12.res_data\(31),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[15]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(63),
      O => buff_td(15)
    );
\s_fifo_td[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(50),
      I1 => \REQ_BUFFER_RAW12.res_data\(34),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[18]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[2]\,
      O => buff_td(18)
    );
\s_fifo_td[32]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[8]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(56),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[40]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[24]\,
      O => buff_td(40)
    );
\s_fifo_td[33]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[9]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(57),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[41]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[25]\,
      O => buff_td(41)
    );
\s_fifo_td[34]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[10]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(58),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[42]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[26]\,
      O => buff_td(42)
    );
\s_fifo_td[35]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[11]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(59),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[43]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[27]\,
      O => buff_td(43)
    );
\s_fifo_td[36]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(56),
      I1 => \REQ_BUFFER_RAW12.res_data\(40),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[24]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[8]\,
      O => buff_td(24)
    );
\s_fifo_td[37]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(57),
      I1 => \REQ_BUFFER_RAW12.res_data\(41),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[25]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[9]\,
      O => buff_td(25)
    );
\s_fifo_td[38]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(58),
      I1 => \REQ_BUFFER_RAW12.res_data\(42),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[26]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[10]\,
      O => buff_td(26)
    );
\s_fifo_td[39]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(59),
      I1 => \REQ_BUFFER_RAW12.res_data\(43),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[27]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[11]\,
      O => buff_td(27)
    );
\s_fifo_td[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(51),
      I1 => \REQ_BUFFER_RAW12.res_data\(35),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[19]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[3]\,
      O => buff_td(19)
    );
\s_fifo_td[40]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(60),
      I1 => \REQ_BUFFER_RAW12.res_data\(44),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[28]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[12]\,
      O => buff_td(28)
    );
\s_fifo_td[41]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(61),
      I1 => \REQ_BUFFER_RAW12.res_data\(45),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[29]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[13]\,
      O => buff_td(29)
    );
\s_fifo_td[42]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(62),
      I1 => \REQ_BUFFER_RAW12.res_data\(46),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[30]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[14]\,
      O => buff_td(30)
    );
\s_fifo_td[43]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(63),
      I1 => \REQ_BUFFER_RAW12.res_data\(47),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[31]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[15]\,
      O => buff_td(31)
    );
\s_fifo_td[48]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[12]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(60),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[44]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[28]\,
      O => buff_td(44)
    );
\s_fifo_td[49]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[13]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(61),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[45]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[29]\,
      O => buff_td(45)
    );
\s_fifo_td[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(32),
      I1 => \REQ_BUFFER_RAW12.res_data\(16),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[0]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(48),
      O => buff_td(0)
    );
\s_fifo_td[50]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[14]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(62),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[46]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[30]\,
      O => buff_td(46)
    );
\s_fifo_td[51]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[15]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(63),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[47]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[31]\,
      O => buff_td(47)
    );
\s_fifo_td[52]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[0]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(48),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[32]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[16]\,
      O => buff_td(32)
    );
\s_fifo_td[53]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[1]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(49),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[33]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[17]\,
      O => buff_td(33)
    );
\s_fifo_td[54]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[2]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(50),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[34]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[18]\,
      O => buff_td(34)
    );
\s_fifo_td[55]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[3]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(51),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[35]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[19]\,
      O => buff_td(35)
    );
\s_fifo_td[56]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[4]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(52),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[36]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[20]\,
      O => buff_td(36)
    );
\s_fifo_td[57]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[5]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(53),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[37]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[21]\,
      O => buff_td(37)
    );
\s_fifo_td[58]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[6]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(54),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[38]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[22]\,
      O => buff_td(38)
    );
\s_fifo_td[59]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[7]\,
      I1 => \REQ_BUFFER_RAW12.res_data\(55),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[39]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[23]\,
      O => buff_td(39)
    );
\s_fifo_td[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(33),
      I1 => \REQ_BUFFER_RAW12.res_data\(17),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[1]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(49),
      O => buff_td(1)
    );
\s_fifo_td[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(34),
      I1 => \REQ_BUFFER_RAW12.res_data\(18),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[2]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(50),
      O => buff_td(2)
    );
\s_fifo_td[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(35),
      I1 => \REQ_BUFFER_RAW12.res_data\(19),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[3]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(51),
      O => buff_td(3)
    );
\s_fifo_td[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(36),
      I1 => \REQ_BUFFER_RAW12.res_data\(20),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[4]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(52),
      O => buff_td(4)
    );
\s_fifo_td[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.res_data\(37),
      I1 => \REQ_BUFFER_RAW12.res_data\(21),
      I2 => \REQ_BUFFER_RAW12.cur_data_reg_n_0_[5]\,
      I3 => \REQ_BUFFER_RAW12.indx_cntr\(1),
      I4 => \REQ_BUFFER_RAW12.indx_cntr\(0),
      I5 => \REQ_BUFFER_RAW12.res_data\(53),
      O => buff_td(5)
    );
\s_fifo_td_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(16),
      Q => \s_fifo_td_reg[59]_0\(0),
      R => \^sr\(0)
    );
\s_fifo_td_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(6),
      Q => \s_fifo_td_reg[59]_0\(10),
      R => \^sr\(0)
    );
\s_fifo_td_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(7),
      Q => \s_fifo_td_reg[59]_0\(11),
      R => \^sr\(0)
    );
\s_fifo_td_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(20),
      Q => \s_fifo_td_reg[59]_0\(12),
      R => \^sr\(0)
    );
\s_fifo_td_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(21),
      Q => \s_fifo_td_reg[59]_0\(13),
      R => \^sr\(0)
    );
\s_fifo_td_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(22),
      Q => \s_fifo_td_reg[59]_0\(14),
      R => \^sr\(0)
    );
\s_fifo_td_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(23),
      Q => \s_fifo_td_reg[59]_0\(15),
      R => \^sr\(0)
    );
\s_fifo_td_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(17),
      Q => \s_fifo_td_reg[59]_0\(1),
      R => \^sr\(0)
    );
\s_fifo_td_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(8),
      Q => \s_fifo_td_reg[59]_0\(16),
      R => \^sr\(0)
    );
\s_fifo_td_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(9),
      Q => \s_fifo_td_reg[59]_0\(17),
      R => \^sr\(0)
    );
\s_fifo_td_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(10),
      Q => \s_fifo_td_reg[59]_0\(18),
      R => \^sr\(0)
    );
\s_fifo_td_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(11),
      Q => \s_fifo_td_reg[59]_0\(19),
      R => \^sr\(0)
    );
\s_fifo_td_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(12),
      Q => \s_fifo_td_reg[59]_0\(20),
      R => \^sr\(0)
    );
\s_fifo_td_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(13),
      Q => \s_fifo_td_reg[59]_0\(21),
      R => \^sr\(0)
    );
\s_fifo_td_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(14),
      Q => \s_fifo_td_reg[59]_0\(22),
      R => \^sr\(0)
    );
\s_fifo_td_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(15),
      Q => \s_fifo_td_reg[59]_0\(23),
      R => \^sr\(0)
    );
\s_fifo_td_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(18),
      Q => \s_fifo_td_reg[59]_0\(2),
      R => \^sr\(0)
    );
\s_fifo_td_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(40),
      Q => \s_fifo_td_reg[59]_0\(24),
      R => \^sr\(0)
    );
\s_fifo_td_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(41),
      Q => \s_fifo_td_reg[59]_0\(25),
      R => \^sr\(0)
    );
\s_fifo_td_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(42),
      Q => \s_fifo_td_reg[59]_0\(26),
      R => \^sr\(0)
    );
\s_fifo_td_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(43),
      Q => \s_fifo_td_reg[59]_0\(27),
      R => \^sr\(0)
    );
\s_fifo_td_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(24),
      Q => \s_fifo_td_reg[59]_0\(28),
      R => \^sr\(0)
    );
\s_fifo_td_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(25),
      Q => \s_fifo_td_reg[59]_0\(29),
      R => \^sr\(0)
    );
\s_fifo_td_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(26),
      Q => \s_fifo_td_reg[59]_0\(30),
      R => \^sr\(0)
    );
\s_fifo_td_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(27),
      Q => \s_fifo_td_reg[59]_0\(31),
      R => \^sr\(0)
    );
\s_fifo_td_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(19),
      Q => \s_fifo_td_reg[59]_0\(3),
      R => \^sr\(0)
    );
\s_fifo_td_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(28),
      Q => \s_fifo_td_reg[59]_0\(32),
      R => \^sr\(0)
    );
\s_fifo_td_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(29),
      Q => \s_fifo_td_reg[59]_0\(33),
      R => \^sr\(0)
    );
\s_fifo_td_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(30),
      Q => \s_fifo_td_reg[59]_0\(34),
      R => \^sr\(0)
    );
\s_fifo_td_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(31),
      Q => \s_fifo_td_reg[59]_0\(35),
      R => \^sr\(0)
    );
\s_fifo_td_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(44),
      Q => \s_fifo_td_reg[59]_0\(36),
      R => \^sr\(0)
    );
\s_fifo_td_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(45),
      Q => \s_fifo_td_reg[59]_0\(37),
      R => \^sr\(0)
    );
\s_fifo_td_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(0),
      Q => \s_fifo_td_reg[59]_0\(4),
      R => \^sr\(0)
    );
\s_fifo_td_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(46),
      Q => \s_fifo_td_reg[59]_0\(38),
      R => \^sr\(0)
    );
\s_fifo_td_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(47),
      Q => \s_fifo_td_reg[59]_0\(39),
      R => \^sr\(0)
    );
\s_fifo_td_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(32),
      Q => \s_fifo_td_reg[59]_0\(40),
      R => \^sr\(0)
    );
\s_fifo_td_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(33),
      Q => \s_fifo_td_reg[59]_0\(41),
      R => \^sr\(0)
    );
\s_fifo_td_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(34),
      Q => \s_fifo_td_reg[59]_0\(42),
      R => \^sr\(0)
    );
\s_fifo_td_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(35),
      Q => \s_fifo_td_reg[59]_0\(43),
      R => \^sr\(0)
    );
\s_fifo_td_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(36),
      Q => \s_fifo_td_reg[59]_0\(44),
      R => \^sr\(0)
    );
\s_fifo_td_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(37),
      Q => \s_fifo_td_reg[59]_0\(45),
      R => \^sr\(0)
    );
\s_fifo_td_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(38),
      Q => \s_fifo_td_reg[59]_0\(46),
      R => \^sr\(0)
    );
\s_fifo_td_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(39),
      Q => \s_fifo_td_reg[59]_0\(47),
      R => \^sr\(0)
    );
\s_fifo_td_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(1),
      Q => \s_fifo_td_reg[59]_0\(5),
      R => \^sr\(0)
    );
\s_fifo_td_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(2),
      Q => \s_fifo_td_reg[59]_0\(6),
      R => \^sr\(0)
    );
\s_fifo_td_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(3),
      Q => \s_fifo_td_reg[59]_0\(7),
      R => \^sr\(0)
    );
\s_fifo_td_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(4),
      Q => \s_fifo_td_reg[59]_0\(8),
      R => \^sr\(0)
    );
\s_fifo_td_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => buff_td(5),
      Q => \s_fifo_td_reg[59]_0\(9),
      R => \^sr\(0)
    );
\s_fifo_tid_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[4]\,
      Q => \s_fifo_tid_reg[9]_0\(0),
      R => \^sr\(0)
    );
\s_fifo_tid_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[5]\,
      Q => \s_fifo_tid_reg[9]_0\(1),
      R => \^sr\(0)
    );
\s_fifo_tid_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[6]\,
      Q => \s_fifo_tid_reg[9]_0\(2),
      R => \^sr\(0)
    );
\s_fifo_tid_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[7]\,
      Q => \s_fifo_tid_reg[9]_0\(3),
      R => \^sr\(0)
    );
\s_fifo_tid_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[8]\,
      Q => \s_fifo_tid_reg[9]_0\(4),
      R => \^sr\(0)
    );
\s_fifo_tid_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.buff_ts_i_reg_n_0_[9]\,
      Q => \s_fifo_tid_reg[9]_0\(5),
      R => \^sr\(0)
    );
\s_fifo_tk[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC8C888800808888"
    )
        port map (
      I0 => \^s_axis_tkeep\(0),
      I1 => vfb_arstn,
      I2 => \^s_fifo_tv\,
      I3 => s_axis_tready,
      I4 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I5 => \s_fifo_tk[7]_i_2_n_0\,
      O => \s_fifo_tk[7]_i_1_n_0\
    );
\s_fifo_tk[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \REQ_REORDER_RAW12.tk_partial_i1__2\,
      I1 => \REQ_BUFFER_RAW12.buff_tl_i_reg_n_0\,
      O => \s_fifo_tk[7]_i_2_n_0\
    );
\s_fifo_tk[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A00000000000E00C"
    )
        port map (
      I0 => \s_fifo_tk[7]_i_4_n_0\,
      I1 => \s_fifo_tk[7]_i_5_n_0\,
      I2 => \REQ_BUFFER_RAW12.buff_tk_i\(1),
      I3 => \REQ_BUFFER_RAW12.buff_tk_i\(2),
      I4 => \REQ_BUFFER_RAW12.buff_tk_i\(6),
      I5 => \REQ_BUFFER_RAW12.buff_tk_i\(5),
      O => \REQ_REORDER_RAW12.tk_partial_i1__2\
    );
\s_fifo_tk[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tk_i\(3),
      I1 => \REQ_BUFFER_RAW12.buff_tk_i\(0),
      I2 => \REQ_BUFFER_RAW12.buff_tk_i\(7),
      I3 => \REQ_BUFFER_RAW12.buff_tk_i\(4),
      O => \s_fifo_tk[7]_i_4_n_0\
    );
\s_fifo_tk[7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tk_i\(3),
      I1 => \REQ_BUFFER_RAW12.buff_tk_i\(0),
      I2 => \REQ_BUFFER_RAW12.buff_tk_i\(7),
      I3 => \REQ_BUFFER_RAW12.buff_tk_i\(4),
      O => \s_fifo_tk[7]_i_5_n_0\
    );
\s_fifo_tk_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => \s_fifo_tk[7]_i_1_n_0\,
      Q => \^s_axis_tkeep\(0),
      R => '0'
    );
s_fifo_tl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0C0A0A000C00000"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tl_i_reg_n_0\,
      I1 => \^s_axis_tlast\,
      I2 => vfb_arstn,
      I3 => s_axis_tready,
      I4 => \^s_fifo_tv\,
      I5 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      O => s_fifo_tl_i_1_n_0
    );
s_fifo_tl_reg: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => s_fifo_tl_i_1_n_0,
      Q => \^s_axis_tlast\,
      R => '0'
    );
\s_fifo_tu_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => \REQ_BUFFER_RAW12.indx_cntr0\,
      D => \REQ_BUFFER_RAW12.buff_tu_i\,
      Q => s_axis_tuser(0),
      R => \^sr\(0)
    );
s_fifo_tv_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.buff_tv_i_reg_n_0\,
      I1 => s_axis_tready,
      I2 => \^s_fifo_tv\,
      O => s_fifo_tv_i_1_n_0
    );
s_fifo_tv_reg: unisim.vcomponents.FDRE
     port map (
      C => vfb_clk,
      CE => '1',
      D => s_fifo_tv_i_1_n_0,
      Q => \^s_fifo_tv\,
      R => \^sr\(0)
    );
\sband_td_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(16),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(0),
      O => \buf_data_reg[0][171]_0\(0)
    );
\sband_td_r[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(26),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(10),
      O => \buf_data_reg[0][171]_0\(10)
    );
\sband_td_r[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(27),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(11),
      O => \buf_data_reg[0][171]_0\(11)
    );
\sband_td_r[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(28),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(12),
      O => \buf_data_reg[0][171]_0\(12)
    );
\sband_td_r[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(29),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(13),
      O => \buf_data_reg[0][171]_0\(13)
    );
\sband_td_r[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(30),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(14),
      O => \buf_data_reg[0][171]_0\(14)
    );
\sband_td_r[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(31),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(15),
      O => \buf_data_reg[0][171]_0\(15)
    );
\sband_td_r[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(32),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(16),
      O => \buf_data_reg[0][171]_0\(16)
    );
\sband_td_r[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(33),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(17),
      O => \buf_data_reg[0][171]_0\(17)
    );
\sband_td_r[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(34),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(18),
      O => \buf_data_reg[0][171]_0\(18)
    );
\sband_td_r[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(35),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(19),
      O => \buf_data_reg[0][171]_0\(19)
    );
\sband_td_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(17),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(1),
      O => \buf_data_reg[0][171]_0\(1)
    );
\sband_td_r[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(36),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(20),
      O => \buf_data_reg[0][171]_0\(20)
    );
\sband_td_r[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(37),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(21),
      O => \buf_data_reg[0][171]_0\(21)
    );
\sband_td_r[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(38),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(22),
      O => \buf_data_reg[0][171]_0\(22)
    );
\sband_td_r[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(39),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(23),
      O => \buf_data_reg[0][171]_0\(23)
    );
\sband_td_r[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(40),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(24),
      O => \buf_data_reg[0][171]_0\(24)
    );
\sband_td_r[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(41),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(25),
      O => \buf_data_reg[0][171]_0\(25)
    );
\sband_td_r[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(42),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(26),
      O => \buf_data_reg[0][171]_0\(26)
    );
\sband_td_r[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(43),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(27),
      O => \buf_data_reg[0][171]_0\(27)
    );
\sband_td_r[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(44),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(28),
      O => \buf_data_reg[0][171]_0\(28)
    );
\sband_td_r[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(45),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(29),
      O => \buf_data_reg[0][171]_0\(29)
    );
\sband_td_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(18),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(2),
      O => \buf_data_reg[0][171]_0\(2)
    );
\sband_td_r[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(46),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(30),
      O => \buf_data_reg[0][171]_0\(30)
    );
\sband_td_r[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(47),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(31),
      O => \buf_data_reg[0][171]_0\(31)
    );
\sband_td_r[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(48),
      O => \buf_data_reg[0][171]_0\(32)
    );
\sband_td_r[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(49),
      O => \buf_data_reg[0][171]_0\(33)
    );
\sband_td_r[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(50),
      O => \buf_data_reg[0][171]_0\(34)
    );
\sband_td_r[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(51),
      O => \buf_data_reg[0][171]_0\(35)
    );
\sband_td_r[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(52),
      O => \buf_data_reg[0][171]_0\(36)
    );
\sband_td_r[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(53),
      O => \buf_data_reg[0][171]_0\(37)
    );
\sband_td_r[38]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(54),
      O => \buf_data_reg[0][171]_0\(38)
    );
\sband_td_r[39]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(55),
      O => \buf_data_reg[0][171]_0\(39)
    );
\sband_td_r[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(19),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(3),
      O => \buf_data_reg[0][171]_0\(3)
    );
\sband_td_r[40]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(56),
      O => \buf_data_reg[0][171]_0\(40)
    );
\sband_td_r[41]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(57),
      O => \buf_data_reg[0][171]_0\(41)
    );
\sband_td_r[42]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(58),
      O => \buf_data_reg[0][171]_0\(42)
    );
\sband_td_r[43]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(59),
      O => \buf_data_reg[0][171]_0\(43)
    );
\sband_td_r[44]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(60),
      O => \buf_data_reg[0][171]_0\(44)
    );
\sband_td_r[45]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(61),
      O => \buf_data_reg[0][171]_0\(45)
    );
\sband_td_r[46]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(62),
      O => \buf_data_reg[0][171]_0\(46)
    );
\sband_td_r[47]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_td(63),
      O => \buf_data_reg[0][171]_0\(47)
    );
\sband_td_r[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(20),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(4),
      O => \buf_data_reg[0][171]_0\(4)
    );
\sband_td_r[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(21),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(5),
      O => \buf_data_reg[0][171]_0\(5)
    );
\sband_td_r[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(22),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(6),
      O => \buf_data_reg[0][171]_0\(6)
    );
\sband_td_r[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(23),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(7),
      O => \buf_data_reg[0][171]_0\(7)
    );
\sband_td_r[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(24),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(8),
      O => \buf_data_reg[0][171]_0\(8)
    );
\sband_td_r[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_td(25),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_td_r_reg[31]\(9),
      O => \buf_data_reg[0][171]_0\(9)
    );
\sband_tk_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => sband_tk(4),
      I1 => \^vfb_sof119_out\,
      I2 => \sband_tk_r_reg[2]\(0),
      O => \buf_data_reg[0][106]_0\(0)
    );
\sband_tk_r[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => sband_tk(6),
      O => \buf_data_reg[0][106]_0\(1)
    );
sband_tl_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020000000000000"
    )
        port map (
      I0 => sband_tl_r_reg,
      I1 => m_axis_tvalid,
      I2 => \^cur_dtype_udef\,
      I3 => sband_tl_r_reg_0,
      I4 => \buf_valid_reg_n_0_[0]\,
      I5 => sban_dtvc,
      O => \^vfb_sof119_out\
    );
sband_tl_r_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => cur_dtype_pxls1,
      I1 => s_axis_tlast_0,
      O => \^sband_tl\
    );
\sband_tu_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => sban_dtvc,
      I1 => \buf_valid_reg_n_0_[0]\,
      I2 => \buf_data_reg_n_0_[0][4]\,
      I3 => \s_axis_tready__3\,
      O => sband_tu(0)
    );
\sband_tu_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEAAAEAAAEAAA"
    )
        port map (
      I0 => cur_dtype_sink_reg_n_0,
      I1 => cur_dtype_pxls,
      I2 => \sband_tu_r[0]_i_3_n_0\,
      I3 => buff_tr141_in,
      I4 => sband_tl_r_reg,
      I5 => \buf_valid_reg[1]_1\,
      O => \s_axis_tready__3\
    );
\sband_tu_r[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \REQ_BUFFER_RAW12.filt_tl_on\,
      I1 => \REQ_BUFFER_RAW12.buff_tl_i_reg_n_0\,
      O => \sband_tu_r[0]_i_3_n_0\
    );
\vfb_data[23]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \^vfb_sof119_out\,
      I1 => vfb_sof015_out,
      I2 => m_axis_tvalid,
      I3 => vfb_arstn,
      O => \state_reg[1]_0\
    );
\vfb_sof[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800080F08000800"
    )
        port map (
      I0 => \vfb_sof[0]_i_6_n_0\,
      I1 => \s_axis_tready__3\,
      I2 => m_axis_tvalid,
      I3 => \^vfb_sof119_out\,
      I4 => \vfb_sof_reg[0]\,
      I5 => sband_tu_r(0),
      O => \state_reg[1]\
    );
\vfb_sof[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7000000000000000"
    )
        port map (
      I0 => E(0),
      I1 => sband_tl_r_reg_0,
      I2 => \^cur_dtype_udef\,
      I3 => \buf_data_reg_n_0_[0][4]\,
      I4 => \buf_valid_reg_n_0_[0]\,
      I5 => sban_dtvc,
      O => \vfb_sof[0]_i_6_n_0\
    );
vfb_valid_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => vfb_arstn,
      O => \^sr\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_cdc_array_single is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_array_single : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_array_single : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_cdc_array_single : entity is "xpm_cdc_array_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of design_1_Vsp_core_0_0_xpm_cdc_array_single : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of design_1_Vsp_core_0_0_xpm_cdc_array_single : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of design_1_Vsp_core_0_0_xpm_cdc_array_single : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of design_1_Vsp_core_0_0_xpm_cdc_array_single : entity is 2;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of design_1_Vsp_core_0_0_xpm_cdc_array_single : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of design_1_Vsp_core_0_0_xpm_cdc_array_single : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of design_1_Vsp_core_0_0_xpm_cdc_array_single : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of design_1_Vsp_core_0_0_xpm_cdc_array_single : entity is "ARRAY_SINGLE";
end design_1_Vsp_core_0_0_xpm_cdc_array_single;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_cdc_array_single is
  signal async_path_bit : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \syncstages_ff[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \syncstages_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \syncstages_ff[0]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[0]\ : signal is "ARRAY_SINGLE";
  signal \syncstages_ff[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP of \syncstages_ff[1]\ : signal is "true";
  attribute async_reg of \syncstages_ff[1]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[1]\ : signal is "ARRAY_SINGLE";
  signal \syncstages_ff[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP of \syncstages_ff[2]\ : signal is "true";
  attribute async_reg of \syncstages_ff[2]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[2]\ : signal is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][1]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][1]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][0]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][1]\ : label is "ARRAY_SINGLE";
begin
  async_path_bit(1 downto 0) <= src_in(1 downto 0);
  dest_out(1 downto 0) <= \syncstages_ff[2]\(1 downto 0);
\syncstages_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(0),
      Q => \syncstages_ff[0]\(0),
      R => '0'
    );
\syncstages_ff_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(1),
      Q => \syncstages_ff[0]\(1),
      R => '0'
    );
\syncstages_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(0),
      Q => \syncstages_ff[1]\(0),
      R => '0'
    );
\syncstages_ff_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(1),
      Q => \syncstages_ff[1]\(1),
      R => '0'
    );
\syncstages_ff_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(0),
      Q => \syncstages_ff[2]\(0),
      R => '0'
    );
\syncstages_ff_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(1),
      Q => \syncstages_ff[2]\(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_array_single__4\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_array_single__4\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_array_single__4\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_array_single__4\ : entity is "xpm_cdc_array_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_array_single__4\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_array_single__4\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_array_single__4\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_array_single__4\ : entity is 2;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_array_single__4\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_array_single__4\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_array_single__4\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_array_single__4\ : entity is "ARRAY_SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_array_single__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_array_single__4\ is
  signal async_path_bit : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \syncstages_ff[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \syncstages_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \syncstages_ff[0]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[0]\ : signal is "ARRAY_SINGLE";
  signal \syncstages_ff[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP of \syncstages_ff[1]\ : signal is "true";
  attribute async_reg of \syncstages_ff[1]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[1]\ : signal is "ARRAY_SINGLE";
  signal \syncstages_ff[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP of \syncstages_ff[2]\ : signal is "true";
  attribute async_reg of \syncstages_ff[2]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[2]\ : signal is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][1]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][1]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][0]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][1]\ : label is "ARRAY_SINGLE";
begin
  async_path_bit(1 downto 0) <= src_in(1 downto 0);
  dest_out(1 downto 0) <= \syncstages_ff[2]\(1 downto 0);
\syncstages_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(0),
      Q => \syncstages_ff[0]\(0),
      R => '0'
    );
\syncstages_ff_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(1),
      Q => \syncstages_ff[0]\(1),
      R => '0'
    );
\syncstages_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(0),
      Q => \syncstages_ff[1]\(0),
      R => '0'
    );
\syncstages_ff_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(1),
      Q => \syncstages_ff[1]\(1),
      R => '0'
    );
\syncstages_ff_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(0),
      Q => \syncstages_ff[2]\(0),
      R => '0'
    );
\syncstages_ff_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(1),
      Q => \syncstages_ff[2]\(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_array_single__5\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_array_single__5\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_array_single__5\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_array_single__5\ : entity is "xpm_cdc_array_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_array_single__5\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_array_single__5\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_array_single__5\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_array_single__5\ : entity is 2;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_array_single__5\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_array_single__5\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_array_single__5\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_array_single__5\ : entity is "ARRAY_SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_array_single__5\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_array_single__5\ is
  signal async_path_bit : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \syncstages_ff[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \syncstages_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \syncstages_ff[0]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[0]\ : signal is "ARRAY_SINGLE";
  signal \syncstages_ff[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP of \syncstages_ff[1]\ : signal is "true";
  attribute async_reg of \syncstages_ff[1]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[1]\ : signal is "ARRAY_SINGLE";
  signal \syncstages_ff[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP of \syncstages_ff[2]\ : signal is "true";
  attribute async_reg of \syncstages_ff[2]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[2]\ : signal is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][1]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][1]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][0]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][1]\ : label is "ARRAY_SINGLE";
begin
  dest_out(1 downto 0) <= \syncstages_ff[2]\(1 downto 0);
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => async_path_bit(1)
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => async_path_bit(0)
    );
\syncstages_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(0),
      Q => \syncstages_ff[0]\(0),
      R => '0'
    );
\syncstages_ff_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(1),
      Q => \syncstages_ff[0]\(1),
      R => '0'
    );
\syncstages_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(0),
      Q => \syncstages_ff[1]\(0),
      R => '0'
    );
\syncstages_ff_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(1),
      Q => \syncstages_ff[1]\(1),
      R => '0'
    );
\syncstages_ff_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(0),
      Q => \syncstages_ff[2]\(0),
      R => '0'
    );
\syncstages_ff_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(1),
      Q => \syncstages_ff[2]\(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_array_single__6\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_array_single__6\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_array_single__6\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_array_single__6\ : entity is "xpm_cdc_array_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_array_single__6\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_array_single__6\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_array_single__6\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_array_single__6\ : entity is 2;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_array_single__6\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_array_single__6\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_array_single__6\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_array_single__6\ : entity is "ARRAY_SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_array_single__6\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_array_single__6\ is
  signal async_path_bit : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \syncstages_ff[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \syncstages_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \syncstages_ff[0]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[0]\ : signal is "ARRAY_SINGLE";
  signal \syncstages_ff[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP of \syncstages_ff[1]\ : signal is "true";
  attribute async_reg of \syncstages_ff[1]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[1]\ : signal is "ARRAY_SINGLE";
  signal \syncstages_ff[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP of \syncstages_ff[2]\ : signal is "true";
  attribute async_reg of \syncstages_ff[2]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[2]\ : signal is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][1]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][1]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][0]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][1]\ : label is "ARRAY_SINGLE";
begin
  async_path_bit(1 downto 0) <= src_in(1 downto 0);
  dest_out(1 downto 0) <= \syncstages_ff[2]\(1 downto 0);
\syncstages_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(0),
      Q => \syncstages_ff[0]\(0),
      R => '0'
    );
\syncstages_ff_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(1),
      Q => \syncstages_ff[0]\(1),
      R => '0'
    );
\syncstages_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(0),
      Q => \syncstages_ff[1]\(0),
      R => '0'
    );
\syncstages_ff_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(1),
      Q => \syncstages_ff[1]\(1),
      R => '0'
    );
\syncstages_ff_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(0),
      Q => \syncstages_ff[2]\(0),
      R => '0'
    );
\syncstages_ff_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(1),
      Q => \syncstages_ff[2]\(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized0\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized0\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized0\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized0\ : entity is "xpm_cdc_array_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized0\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized0\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized0\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized0\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized0\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized0\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized0\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized0\ : entity is "ARRAY_SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized0\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized0\ is
  signal async_path_bit : STD_LOGIC;
  signal \syncstages_ff[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \syncstages_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \syncstages_ff[0]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[0]\ : signal is "ARRAY_SINGLE";
  signal \syncstages_ff[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \syncstages_ff[1]\ : signal is "true";
  attribute async_reg of \syncstages_ff[1]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[1]\ : signal is "ARRAY_SINGLE";
  signal \syncstages_ff[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \syncstages_ff[2]\ : signal is "true";
  attribute async_reg of \syncstages_ff[2]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[2]\ : signal is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][0]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][0]\ : label is "ARRAY_SINGLE";
begin
  dest_out(0) <= \syncstages_ff[2]\;
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => async_path_bit
    );
\syncstages_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit,
      Q => \syncstages_ff[0]\,
      R => '0'
    );
\syncstages_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\,
      Q => \syncstages_ff[1]\,
      R => '0'
    );
\syncstages_ff_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\,
      Q => \syncstages_ff[2]\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized1\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 45 downto 0 );
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 45 downto 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized1\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized1\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized1\ : entity is "xpm_cdc_array_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized1\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized1\ : entity is 1;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized1\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized1\ : entity is 46;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized1\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized1\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized1\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized1\ : entity is "ARRAY_SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized1\ is
  signal async_path_bit : STD_LOGIC_VECTOR ( 45 downto 0 );
  signal \syncstages_ff[0]\ : STD_LOGIC_VECTOR ( 45 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \syncstages_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \syncstages_ff[0]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[0]\ : signal is "ARRAY_SINGLE";
  signal \syncstages_ff[1]\ : STD_LOGIC_VECTOR ( 45 downto 0 );
  attribute RTL_KEEP of \syncstages_ff[1]\ : signal is "true";
  attribute async_reg of \syncstages_ff[1]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[1]\ : signal is "ARRAY_SINGLE";
  signal \syncstages_ff[2]\ : STD_LOGIC_VECTOR ( 45 downto 0 );
  attribute RTL_KEEP of \syncstages_ff[2]\ : signal is "true";
  attribute async_reg of \syncstages_ff[2]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[2]\ : signal is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][10]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][10]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][10]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][11]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][11]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][11]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][12]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][12]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][12]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][13]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][13]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][13]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][14]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][14]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][14]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][15]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][15]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][15]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][16]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][16]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][16]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][17]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][17]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][17]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][18]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][18]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][18]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][19]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][19]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][19]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][1]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][20]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][20]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][20]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][21]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][21]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][21]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][22]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][22]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][22]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][23]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][23]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][23]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][24]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][24]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][24]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][25]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][25]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][25]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][26]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][26]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][26]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][27]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][27]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][27]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][28]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][28]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][28]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][29]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][29]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][29]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][2]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][30]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][30]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][30]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][31]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][31]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][31]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][32]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][32]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][32]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][33]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][33]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][33]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][34]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][34]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][34]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][35]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][35]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][35]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][36]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][36]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][36]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][37]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][37]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][37]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][38]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][38]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][38]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][39]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][39]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][39]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][3]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][3]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][3]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][40]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][40]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][40]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][41]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][41]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][41]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][42]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][42]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][42]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][43]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][43]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][43]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][44]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][44]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][44]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][45]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][45]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][45]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][4]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][4]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][4]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][5]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][5]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][5]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][6]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][6]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][6]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][7]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][7]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][7]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][8]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][8]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][8]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][9]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][9]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][9]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][10]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][10]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][10]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][11]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][11]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][11]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][12]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][12]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][12]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][13]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][13]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][13]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][14]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][14]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][14]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][15]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][15]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][15]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][16]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][16]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][16]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][17]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][17]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][17]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][18]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][18]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][18]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][19]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][19]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][19]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][1]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][20]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][20]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][20]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][21]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][21]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][21]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][22]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][22]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][22]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][23]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][23]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][23]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][24]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][24]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][24]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][25]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][25]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][25]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][26]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][26]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][26]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][27]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][27]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][27]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][28]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][28]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][28]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][29]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][29]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][29]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][2]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][30]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][30]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][30]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][31]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][31]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][31]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][32]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][32]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][32]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][33]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][33]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][33]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][34]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][34]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][34]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][35]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][35]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][35]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][36]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][36]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][36]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][37]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][37]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][37]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][38]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][38]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][38]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][39]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][39]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][39]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][3]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][3]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][3]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][40]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][40]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][40]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][41]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][41]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][41]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][42]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][42]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][42]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][43]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][43]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][43]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][44]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][44]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][44]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][45]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][45]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][45]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][4]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][4]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][4]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][5]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][5]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][5]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][6]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][6]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][6]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][7]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][7]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][7]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][8]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][8]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][8]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][9]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][9]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][9]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][0]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][10]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][10]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][10]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][11]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][11]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][11]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][12]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][12]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][12]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][13]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][13]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][13]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][14]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][14]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][14]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][15]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][15]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][15]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][16]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][16]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][16]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][17]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][17]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][17]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][18]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][18]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][18]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][19]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][19]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][19]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][1]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][20]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][20]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][20]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][21]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][21]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][21]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][22]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][22]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][22]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][23]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][23]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][23]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][24]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][24]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][24]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][25]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][25]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][25]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][26]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][26]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][26]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][27]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][27]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][27]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][28]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][28]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][28]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][29]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][29]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][29]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][2]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][30]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][30]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][30]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][31]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][31]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][31]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][32]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][32]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][32]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][33]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][33]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][33]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][34]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][34]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][34]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][35]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][35]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][35]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][36]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][36]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][36]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][37]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][37]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][37]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][38]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][38]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][38]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][39]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][39]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][39]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][3]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][3]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][3]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][40]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][40]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][40]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][41]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][41]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][41]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][42]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][42]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][42]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][43]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][43]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][43]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][44]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][44]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][44]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][45]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][45]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][45]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][4]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][4]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][4]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][5]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][5]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][5]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][6]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][6]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][6]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][7]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][7]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][7]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][8]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][8]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][8]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][9]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][9]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][9]\ : label is "ARRAY_SINGLE";
begin
  dest_out(45 downto 0) <= \syncstages_ff[2]\(45 downto 0);
\src_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(0),
      Q => async_path_bit(0),
      R => '0'
    );
\src_ff_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(10),
      Q => async_path_bit(10),
      R => '0'
    );
\src_ff_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(11),
      Q => async_path_bit(11),
      R => '0'
    );
\src_ff_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(12),
      Q => async_path_bit(12),
      R => '0'
    );
\src_ff_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(13),
      Q => async_path_bit(13),
      R => '0'
    );
\src_ff_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(14),
      Q => async_path_bit(14),
      R => '0'
    );
\src_ff_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(15),
      Q => async_path_bit(15),
      R => '0'
    );
\src_ff_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(16),
      Q => async_path_bit(16),
      R => '0'
    );
\src_ff_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(17),
      Q => async_path_bit(17),
      R => '0'
    );
\src_ff_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(18),
      Q => async_path_bit(18),
      R => '0'
    );
\src_ff_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(19),
      Q => async_path_bit(19),
      R => '0'
    );
\src_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(1),
      Q => async_path_bit(1),
      R => '0'
    );
\src_ff_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(20),
      Q => async_path_bit(20),
      R => '0'
    );
\src_ff_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(21),
      Q => async_path_bit(21),
      R => '0'
    );
\src_ff_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(22),
      Q => async_path_bit(22),
      R => '0'
    );
\src_ff_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(23),
      Q => async_path_bit(23),
      R => '0'
    );
\src_ff_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(24),
      Q => async_path_bit(24),
      R => '0'
    );
\src_ff_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(25),
      Q => async_path_bit(25),
      R => '0'
    );
\src_ff_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(26),
      Q => async_path_bit(26),
      R => '0'
    );
\src_ff_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(27),
      Q => async_path_bit(27),
      R => '0'
    );
\src_ff_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(28),
      Q => async_path_bit(28),
      R => '0'
    );
\src_ff_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(29),
      Q => async_path_bit(29),
      R => '0'
    );
\src_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(2),
      Q => async_path_bit(2),
      R => '0'
    );
\src_ff_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(30),
      Q => async_path_bit(30),
      R => '0'
    );
\src_ff_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(31),
      Q => async_path_bit(31),
      R => '0'
    );
\src_ff_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(32),
      Q => async_path_bit(32),
      R => '0'
    );
\src_ff_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(33),
      Q => async_path_bit(33),
      R => '0'
    );
\src_ff_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(34),
      Q => async_path_bit(34),
      R => '0'
    );
\src_ff_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(35),
      Q => async_path_bit(35),
      R => '0'
    );
\src_ff_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(36),
      Q => async_path_bit(36),
      R => '0'
    );
\src_ff_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(37),
      Q => async_path_bit(37),
      R => '0'
    );
\src_ff_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(38),
      Q => async_path_bit(38),
      R => '0'
    );
\src_ff_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(39),
      Q => async_path_bit(39),
      R => '0'
    );
\src_ff_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(3),
      Q => async_path_bit(3),
      R => '0'
    );
\src_ff_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(40),
      Q => async_path_bit(40),
      R => '0'
    );
\src_ff_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(41),
      Q => async_path_bit(41),
      R => '0'
    );
\src_ff_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(42),
      Q => async_path_bit(42),
      R => '0'
    );
\src_ff_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(43),
      Q => async_path_bit(43),
      R => '0'
    );
\src_ff_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(44),
      Q => async_path_bit(44),
      R => '0'
    );
\src_ff_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(45),
      Q => async_path_bit(45),
      R => '0'
    );
\src_ff_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(4),
      Q => async_path_bit(4),
      R => '0'
    );
\src_ff_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(5),
      Q => async_path_bit(5),
      R => '0'
    );
\src_ff_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(6),
      Q => async_path_bit(6),
      R => '0'
    );
\src_ff_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(7),
      Q => async_path_bit(7),
      R => '0'
    );
\src_ff_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(8),
      Q => async_path_bit(8),
      R => '0'
    );
\src_ff_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in(9),
      Q => async_path_bit(9),
      R => '0'
    );
\syncstages_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(0),
      Q => \syncstages_ff[0]\(0),
      R => '0'
    );
\syncstages_ff_reg[0][10]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(10),
      Q => \syncstages_ff[0]\(10),
      R => '0'
    );
\syncstages_ff_reg[0][11]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(11),
      Q => \syncstages_ff[0]\(11),
      R => '0'
    );
\syncstages_ff_reg[0][12]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(12),
      Q => \syncstages_ff[0]\(12),
      R => '0'
    );
\syncstages_ff_reg[0][13]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(13),
      Q => \syncstages_ff[0]\(13),
      R => '0'
    );
\syncstages_ff_reg[0][14]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(14),
      Q => \syncstages_ff[0]\(14),
      R => '0'
    );
\syncstages_ff_reg[0][15]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(15),
      Q => \syncstages_ff[0]\(15),
      R => '0'
    );
\syncstages_ff_reg[0][16]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(16),
      Q => \syncstages_ff[0]\(16),
      R => '0'
    );
\syncstages_ff_reg[0][17]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(17),
      Q => \syncstages_ff[0]\(17),
      R => '0'
    );
\syncstages_ff_reg[0][18]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(18),
      Q => \syncstages_ff[0]\(18),
      R => '0'
    );
\syncstages_ff_reg[0][19]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(19),
      Q => \syncstages_ff[0]\(19),
      R => '0'
    );
\syncstages_ff_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(1),
      Q => \syncstages_ff[0]\(1),
      R => '0'
    );
\syncstages_ff_reg[0][20]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(20),
      Q => \syncstages_ff[0]\(20),
      R => '0'
    );
\syncstages_ff_reg[0][21]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(21),
      Q => \syncstages_ff[0]\(21),
      R => '0'
    );
\syncstages_ff_reg[0][22]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(22),
      Q => \syncstages_ff[0]\(22),
      R => '0'
    );
\syncstages_ff_reg[0][23]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(23),
      Q => \syncstages_ff[0]\(23),
      R => '0'
    );
\syncstages_ff_reg[0][24]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(24),
      Q => \syncstages_ff[0]\(24),
      R => '0'
    );
\syncstages_ff_reg[0][25]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(25),
      Q => \syncstages_ff[0]\(25),
      R => '0'
    );
\syncstages_ff_reg[0][26]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(26),
      Q => \syncstages_ff[0]\(26),
      R => '0'
    );
\syncstages_ff_reg[0][27]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(27),
      Q => \syncstages_ff[0]\(27),
      R => '0'
    );
\syncstages_ff_reg[0][28]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(28),
      Q => \syncstages_ff[0]\(28),
      R => '0'
    );
\syncstages_ff_reg[0][29]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(29),
      Q => \syncstages_ff[0]\(29),
      R => '0'
    );
\syncstages_ff_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(2),
      Q => \syncstages_ff[0]\(2),
      R => '0'
    );
\syncstages_ff_reg[0][30]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(30),
      Q => \syncstages_ff[0]\(30),
      R => '0'
    );
\syncstages_ff_reg[0][31]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(31),
      Q => \syncstages_ff[0]\(31),
      R => '0'
    );
\syncstages_ff_reg[0][32]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(32),
      Q => \syncstages_ff[0]\(32),
      R => '0'
    );
\syncstages_ff_reg[0][33]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(33),
      Q => \syncstages_ff[0]\(33),
      R => '0'
    );
\syncstages_ff_reg[0][34]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(34),
      Q => \syncstages_ff[0]\(34),
      R => '0'
    );
\syncstages_ff_reg[0][35]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(35),
      Q => \syncstages_ff[0]\(35),
      R => '0'
    );
\syncstages_ff_reg[0][36]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(36),
      Q => \syncstages_ff[0]\(36),
      R => '0'
    );
\syncstages_ff_reg[0][37]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(37),
      Q => \syncstages_ff[0]\(37),
      R => '0'
    );
\syncstages_ff_reg[0][38]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(38),
      Q => \syncstages_ff[0]\(38),
      R => '0'
    );
\syncstages_ff_reg[0][39]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(39),
      Q => \syncstages_ff[0]\(39),
      R => '0'
    );
\syncstages_ff_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(3),
      Q => \syncstages_ff[0]\(3),
      R => '0'
    );
\syncstages_ff_reg[0][40]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(40),
      Q => \syncstages_ff[0]\(40),
      R => '0'
    );
\syncstages_ff_reg[0][41]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(41),
      Q => \syncstages_ff[0]\(41),
      R => '0'
    );
\syncstages_ff_reg[0][42]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(42),
      Q => \syncstages_ff[0]\(42),
      R => '0'
    );
\syncstages_ff_reg[0][43]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(43),
      Q => \syncstages_ff[0]\(43),
      R => '0'
    );
\syncstages_ff_reg[0][44]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(44),
      Q => \syncstages_ff[0]\(44),
      R => '0'
    );
\syncstages_ff_reg[0][45]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(45),
      Q => \syncstages_ff[0]\(45),
      R => '0'
    );
\syncstages_ff_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(4),
      Q => \syncstages_ff[0]\(4),
      R => '0'
    );
\syncstages_ff_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(5),
      Q => \syncstages_ff[0]\(5),
      R => '0'
    );
\syncstages_ff_reg[0][6]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(6),
      Q => \syncstages_ff[0]\(6),
      R => '0'
    );
\syncstages_ff_reg[0][7]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(7),
      Q => \syncstages_ff[0]\(7),
      R => '0'
    );
\syncstages_ff_reg[0][8]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(8),
      Q => \syncstages_ff[0]\(8),
      R => '0'
    );
\syncstages_ff_reg[0][9]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(9),
      Q => \syncstages_ff[0]\(9),
      R => '0'
    );
\syncstages_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(0),
      Q => \syncstages_ff[1]\(0),
      R => '0'
    );
\syncstages_ff_reg[1][10]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(10),
      Q => \syncstages_ff[1]\(10),
      R => '0'
    );
\syncstages_ff_reg[1][11]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(11),
      Q => \syncstages_ff[1]\(11),
      R => '0'
    );
\syncstages_ff_reg[1][12]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(12),
      Q => \syncstages_ff[1]\(12),
      R => '0'
    );
\syncstages_ff_reg[1][13]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(13),
      Q => \syncstages_ff[1]\(13),
      R => '0'
    );
\syncstages_ff_reg[1][14]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(14),
      Q => \syncstages_ff[1]\(14),
      R => '0'
    );
\syncstages_ff_reg[1][15]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(15),
      Q => \syncstages_ff[1]\(15),
      R => '0'
    );
\syncstages_ff_reg[1][16]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(16),
      Q => \syncstages_ff[1]\(16),
      R => '0'
    );
\syncstages_ff_reg[1][17]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(17),
      Q => \syncstages_ff[1]\(17),
      R => '0'
    );
\syncstages_ff_reg[1][18]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(18),
      Q => \syncstages_ff[1]\(18),
      R => '0'
    );
\syncstages_ff_reg[1][19]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(19),
      Q => \syncstages_ff[1]\(19),
      R => '0'
    );
\syncstages_ff_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(1),
      Q => \syncstages_ff[1]\(1),
      R => '0'
    );
\syncstages_ff_reg[1][20]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(20),
      Q => \syncstages_ff[1]\(20),
      R => '0'
    );
\syncstages_ff_reg[1][21]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(21),
      Q => \syncstages_ff[1]\(21),
      R => '0'
    );
\syncstages_ff_reg[1][22]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(22),
      Q => \syncstages_ff[1]\(22),
      R => '0'
    );
\syncstages_ff_reg[1][23]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(23),
      Q => \syncstages_ff[1]\(23),
      R => '0'
    );
\syncstages_ff_reg[1][24]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(24),
      Q => \syncstages_ff[1]\(24),
      R => '0'
    );
\syncstages_ff_reg[1][25]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(25),
      Q => \syncstages_ff[1]\(25),
      R => '0'
    );
\syncstages_ff_reg[1][26]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(26),
      Q => \syncstages_ff[1]\(26),
      R => '0'
    );
\syncstages_ff_reg[1][27]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(27),
      Q => \syncstages_ff[1]\(27),
      R => '0'
    );
\syncstages_ff_reg[1][28]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(28),
      Q => \syncstages_ff[1]\(28),
      R => '0'
    );
\syncstages_ff_reg[1][29]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(29),
      Q => \syncstages_ff[1]\(29),
      R => '0'
    );
\syncstages_ff_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(2),
      Q => \syncstages_ff[1]\(2),
      R => '0'
    );
\syncstages_ff_reg[1][30]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(30),
      Q => \syncstages_ff[1]\(30),
      R => '0'
    );
\syncstages_ff_reg[1][31]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(31),
      Q => \syncstages_ff[1]\(31),
      R => '0'
    );
\syncstages_ff_reg[1][32]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(32),
      Q => \syncstages_ff[1]\(32),
      R => '0'
    );
\syncstages_ff_reg[1][33]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(33),
      Q => \syncstages_ff[1]\(33),
      R => '0'
    );
\syncstages_ff_reg[1][34]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(34),
      Q => \syncstages_ff[1]\(34),
      R => '0'
    );
\syncstages_ff_reg[1][35]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(35),
      Q => \syncstages_ff[1]\(35),
      R => '0'
    );
\syncstages_ff_reg[1][36]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(36),
      Q => \syncstages_ff[1]\(36),
      R => '0'
    );
\syncstages_ff_reg[1][37]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(37),
      Q => \syncstages_ff[1]\(37),
      R => '0'
    );
\syncstages_ff_reg[1][38]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(38),
      Q => \syncstages_ff[1]\(38),
      R => '0'
    );
\syncstages_ff_reg[1][39]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(39),
      Q => \syncstages_ff[1]\(39),
      R => '0'
    );
\syncstages_ff_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(3),
      Q => \syncstages_ff[1]\(3),
      R => '0'
    );
\syncstages_ff_reg[1][40]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(40),
      Q => \syncstages_ff[1]\(40),
      R => '0'
    );
\syncstages_ff_reg[1][41]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(41),
      Q => \syncstages_ff[1]\(41),
      R => '0'
    );
\syncstages_ff_reg[1][42]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(42),
      Q => \syncstages_ff[1]\(42),
      R => '0'
    );
\syncstages_ff_reg[1][43]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(43),
      Q => \syncstages_ff[1]\(43),
      R => '0'
    );
\syncstages_ff_reg[1][44]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(44),
      Q => \syncstages_ff[1]\(44),
      R => '0'
    );
\syncstages_ff_reg[1][45]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(45),
      Q => \syncstages_ff[1]\(45),
      R => '0'
    );
\syncstages_ff_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(4),
      Q => \syncstages_ff[1]\(4),
      R => '0'
    );
\syncstages_ff_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(5),
      Q => \syncstages_ff[1]\(5),
      R => '0'
    );
\syncstages_ff_reg[1][6]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(6),
      Q => \syncstages_ff[1]\(6),
      R => '0'
    );
\syncstages_ff_reg[1][7]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(7),
      Q => \syncstages_ff[1]\(7),
      R => '0'
    );
\syncstages_ff_reg[1][8]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(8),
      Q => \syncstages_ff[1]\(8),
      R => '0'
    );
\syncstages_ff_reg[1][9]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(9),
      Q => \syncstages_ff[1]\(9),
      R => '0'
    );
\syncstages_ff_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(0),
      Q => \syncstages_ff[2]\(0),
      R => '0'
    );
\syncstages_ff_reg[2][10]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(10),
      Q => \syncstages_ff[2]\(10),
      R => '0'
    );
\syncstages_ff_reg[2][11]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(11),
      Q => \syncstages_ff[2]\(11),
      R => '0'
    );
\syncstages_ff_reg[2][12]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(12),
      Q => \syncstages_ff[2]\(12),
      R => '0'
    );
\syncstages_ff_reg[2][13]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(13),
      Q => \syncstages_ff[2]\(13),
      R => '0'
    );
\syncstages_ff_reg[2][14]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(14),
      Q => \syncstages_ff[2]\(14),
      R => '0'
    );
\syncstages_ff_reg[2][15]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(15),
      Q => \syncstages_ff[2]\(15),
      R => '0'
    );
\syncstages_ff_reg[2][16]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(16),
      Q => \syncstages_ff[2]\(16),
      R => '0'
    );
\syncstages_ff_reg[2][17]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(17),
      Q => \syncstages_ff[2]\(17),
      R => '0'
    );
\syncstages_ff_reg[2][18]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(18),
      Q => \syncstages_ff[2]\(18),
      R => '0'
    );
\syncstages_ff_reg[2][19]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(19),
      Q => \syncstages_ff[2]\(19),
      R => '0'
    );
\syncstages_ff_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(1),
      Q => \syncstages_ff[2]\(1),
      R => '0'
    );
\syncstages_ff_reg[2][20]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(20),
      Q => \syncstages_ff[2]\(20),
      R => '0'
    );
\syncstages_ff_reg[2][21]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(21),
      Q => \syncstages_ff[2]\(21),
      R => '0'
    );
\syncstages_ff_reg[2][22]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(22),
      Q => \syncstages_ff[2]\(22),
      R => '0'
    );
\syncstages_ff_reg[2][23]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(23),
      Q => \syncstages_ff[2]\(23),
      R => '0'
    );
\syncstages_ff_reg[2][24]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(24),
      Q => \syncstages_ff[2]\(24),
      R => '0'
    );
\syncstages_ff_reg[2][25]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(25),
      Q => \syncstages_ff[2]\(25),
      R => '0'
    );
\syncstages_ff_reg[2][26]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(26),
      Q => \syncstages_ff[2]\(26),
      R => '0'
    );
\syncstages_ff_reg[2][27]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(27),
      Q => \syncstages_ff[2]\(27),
      R => '0'
    );
\syncstages_ff_reg[2][28]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(28),
      Q => \syncstages_ff[2]\(28),
      R => '0'
    );
\syncstages_ff_reg[2][29]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(29),
      Q => \syncstages_ff[2]\(29),
      R => '0'
    );
\syncstages_ff_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(2),
      Q => \syncstages_ff[2]\(2),
      R => '0'
    );
\syncstages_ff_reg[2][30]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(30),
      Q => \syncstages_ff[2]\(30),
      R => '0'
    );
\syncstages_ff_reg[2][31]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(31),
      Q => \syncstages_ff[2]\(31),
      R => '0'
    );
\syncstages_ff_reg[2][32]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(32),
      Q => \syncstages_ff[2]\(32),
      R => '0'
    );
\syncstages_ff_reg[2][33]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(33),
      Q => \syncstages_ff[2]\(33),
      R => '0'
    );
\syncstages_ff_reg[2][34]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(34),
      Q => \syncstages_ff[2]\(34),
      R => '0'
    );
\syncstages_ff_reg[2][35]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(35),
      Q => \syncstages_ff[2]\(35),
      R => '0'
    );
\syncstages_ff_reg[2][36]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(36),
      Q => \syncstages_ff[2]\(36),
      R => '0'
    );
\syncstages_ff_reg[2][37]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(37),
      Q => \syncstages_ff[2]\(37),
      R => '0'
    );
\syncstages_ff_reg[2][38]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(38),
      Q => \syncstages_ff[2]\(38),
      R => '0'
    );
\syncstages_ff_reg[2][39]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(39),
      Q => \syncstages_ff[2]\(39),
      R => '0'
    );
\syncstages_ff_reg[2][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(3),
      Q => \syncstages_ff[2]\(3),
      R => '0'
    );
\syncstages_ff_reg[2][40]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(40),
      Q => \syncstages_ff[2]\(40),
      R => '0'
    );
\syncstages_ff_reg[2][41]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(41),
      Q => \syncstages_ff[2]\(41),
      R => '0'
    );
\syncstages_ff_reg[2][42]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(42),
      Q => \syncstages_ff[2]\(42),
      R => '0'
    );
\syncstages_ff_reg[2][43]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(43),
      Q => \syncstages_ff[2]\(43),
      R => '0'
    );
\syncstages_ff_reg[2][44]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(44),
      Q => \syncstages_ff[2]\(44),
      R => '0'
    );
\syncstages_ff_reg[2][45]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(45),
      Q => \syncstages_ff[2]\(45),
      R => '0'
    );
\syncstages_ff_reg[2][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(4),
      Q => \syncstages_ff[2]\(4),
      R => '0'
    );
\syncstages_ff_reg[2][5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(5),
      Q => \syncstages_ff[2]\(5),
      R => '0'
    );
\syncstages_ff_reg[2][6]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(6),
      Q => \syncstages_ff[2]\(6),
      R => '0'
    );
\syncstages_ff_reg[2][7]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(7),
      Q => \syncstages_ff[2]\(7),
      R => '0'
    );
\syncstages_ff_reg[2][8]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(8),
      Q => \syncstages_ff[2]\(8),
      R => '0'
    );
\syncstages_ff_reg[2][9]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(9),
      Q => \syncstages_ff[2]\(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized2\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized2\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized2\ : entity is "xpm_cdc_array_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized2\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized2\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized2\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized2\ : entity is 16;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized2\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized2\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized2\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized2\ : entity is "ARRAY_SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized2\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_array_single__parameterized2\ is
  signal async_path_bit : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \syncstages_ff[0]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \syncstages_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \syncstages_ff[0]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[0]\ : signal is "ARRAY_SINGLE";
  signal \syncstages_ff[1]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute RTL_KEEP of \syncstages_ff[1]\ : signal is "true";
  attribute async_reg of \syncstages_ff[1]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[1]\ : signal is "ARRAY_SINGLE";
  signal \syncstages_ff[2]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute RTL_KEEP of \syncstages_ff[2]\ : signal is "true";
  attribute async_reg of \syncstages_ff[2]\ : signal is "true";
  attribute xpm_cdc of \syncstages_ff[2]\ : signal is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][10]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][10]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][10]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][11]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][11]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][11]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][12]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][12]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][12]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][13]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][13]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][13]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][14]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][14]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][14]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][15]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][15]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][15]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][1]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][2]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][3]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][3]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][3]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][4]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][4]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][4]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][5]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][5]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][5]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][6]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][6]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][6]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][7]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][7]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][7]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][8]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][8]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][8]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0][9]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[0][9]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0][9]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][10]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][10]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][10]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][11]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][11]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][11]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][12]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][12]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][12]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][13]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][13]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][13]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][14]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][14]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][14]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][15]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][15]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][15]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][1]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][2]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][3]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][3]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][3]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][4]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][4]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][4]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][5]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][5]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][5]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][6]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][6]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][6]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][7]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][7]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][7]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][8]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][8]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][8]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1][9]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1][9]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1][9]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][0]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][0]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][10]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][10]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][10]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][11]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][11]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][11]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][12]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][12]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][12]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][13]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][13]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][13]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][14]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][14]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][14]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][15]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][15]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][15]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][1]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][2]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][3]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][3]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][3]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][4]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][4]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][4]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][5]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][5]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][5]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][6]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][6]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][6]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][7]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][7]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][7]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][8]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][8]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][8]\ : label is "ARRAY_SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2][9]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2][9]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2][9]\ : label is "ARRAY_SINGLE";
begin
  async_path_bit(15 downto 0) <= src_in(15 downto 0);
  dest_out(15 downto 0) <= \syncstages_ff[2]\(15 downto 0);
\syncstages_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(0),
      Q => \syncstages_ff[0]\(0),
      R => '0'
    );
\syncstages_ff_reg[0][10]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(10),
      Q => \syncstages_ff[0]\(10),
      R => '0'
    );
\syncstages_ff_reg[0][11]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(11),
      Q => \syncstages_ff[0]\(11),
      R => '0'
    );
\syncstages_ff_reg[0][12]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(12),
      Q => \syncstages_ff[0]\(12),
      R => '0'
    );
\syncstages_ff_reg[0][13]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(13),
      Q => \syncstages_ff[0]\(13),
      R => '0'
    );
\syncstages_ff_reg[0][14]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(14),
      Q => \syncstages_ff[0]\(14),
      R => '0'
    );
\syncstages_ff_reg[0][15]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(15),
      Q => \syncstages_ff[0]\(15),
      R => '0'
    );
\syncstages_ff_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(1),
      Q => \syncstages_ff[0]\(1),
      R => '0'
    );
\syncstages_ff_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(2),
      Q => \syncstages_ff[0]\(2),
      R => '0'
    );
\syncstages_ff_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(3),
      Q => \syncstages_ff[0]\(3),
      R => '0'
    );
\syncstages_ff_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(4),
      Q => \syncstages_ff[0]\(4),
      R => '0'
    );
\syncstages_ff_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(5),
      Q => \syncstages_ff[0]\(5),
      R => '0'
    );
\syncstages_ff_reg[0][6]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(6),
      Q => \syncstages_ff[0]\(6),
      R => '0'
    );
\syncstages_ff_reg[0][7]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(7),
      Q => \syncstages_ff[0]\(7),
      R => '0'
    );
\syncstages_ff_reg[0][8]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(8),
      Q => \syncstages_ff[0]\(8),
      R => '0'
    );
\syncstages_ff_reg[0][9]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path_bit(9),
      Q => \syncstages_ff[0]\(9),
      R => '0'
    );
\syncstages_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(0),
      Q => \syncstages_ff[1]\(0),
      R => '0'
    );
\syncstages_ff_reg[1][10]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(10),
      Q => \syncstages_ff[1]\(10),
      R => '0'
    );
\syncstages_ff_reg[1][11]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(11),
      Q => \syncstages_ff[1]\(11),
      R => '0'
    );
\syncstages_ff_reg[1][12]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(12),
      Q => \syncstages_ff[1]\(12),
      R => '0'
    );
\syncstages_ff_reg[1][13]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(13),
      Q => \syncstages_ff[1]\(13),
      R => '0'
    );
\syncstages_ff_reg[1][14]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(14),
      Q => \syncstages_ff[1]\(14),
      R => '0'
    );
\syncstages_ff_reg[1][15]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(15),
      Q => \syncstages_ff[1]\(15),
      R => '0'
    );
\syncstages_ff_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(1),
      Q => \syncstages_ff[1]\(1),
      R => '0'
    );
\syncstages_ff_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(2),
      Q => \syncstages_ff[1]\(2),
      R => '0'
    );
\syncstages_ff_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(3),
      Q => \syncstages_ff[1]\(3),
      R => '0'
    );
\syncstages_ff_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(4),
      Q => \syncstages_ff[1]\(4),
      R => '0'
    );
\syncstages_ff_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(5),
      Q => \syncstages_ff[1]\(5),
      R => '0'
    );
\syncstages_ff_reg[1][6]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(6),
      Q => \syncstages_ff[1]\(6),
      R => '0'
    );
\syncstages_ff_reg[1][7]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(7),
      Q => \syncstages_ff[1]\(7),
      R => '0'
    );
\syncstages_ff_reg[1][8]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(8),
      Q => \syncstages_ff[1]\(8),
      R => '0'
    );
\syncstages_ff_reg[1][9]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[0]\(9),
      Q => \syncstages_ff[1]\(9),
      R => '0'
    );
\syncstages_ff_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(0),
      Q => \syncstages_ff[2]\(0),
      R => '0'
    );
\syncstages_ff_reg[2][10]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(10),
      Q => \syncstages_ff[2]\(10),
      R => '0'
    );
\syncstages_ff_reg[2][11]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(11),
      Q => \syncstages_ff[2]\(11),
      R => '0'
    );
\syncstages_ff_reg[2][12]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(12),
      Q => \syncstages_ff[2]\(12),
      R => '0'
    );
\syncstages_ff_reg[2][13]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(13),
      Q => \syncstages_ff[2]\(13),
      R => '0'
    );
\syncstages_ff_reg[2][14]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(14),
      Q => \syncstages_ff[2]\(14),
      R => '0'
    );
\syncstages_ff_reg[2][15]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(15),
      Q => \syncstages_ff[2]\(15),
      R => '0'
    );
\syncstages_ff_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(1),
      Q => \syncstages_ff[2]\(1),
      R => '0'
    );
\syncstages_ff_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(2),
      Q => \syncstages_ff[2]\(2),
      R => '0'
    );
\syncstages_ff_reg[2][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(3),
      Q => \syncstages_ff[2]\(3),
      R => '0'
    );
\syncstages_ff_reg[2][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(4),
      Q => \syncstages_ff[2]\(4),
      R => '0'
    );
\syncstages_ff_reg[2][5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(5),
      Q => \syncstages_ff[2]\(5),
      R => '0'
    );
\syncstages_ff_reg[2][6]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(6),
      Q => \syncstages_ff[2]\(6),
      R => '0'
    );
\syncstages_ff_reg[2][7]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(7),
      Q => \syncstages_ff[2]\(7),
      R => '0'
    );
\syncstages_ff_reg[2][8]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(8),
      Q => \syncstages_ff[2]\(8),
      R => '0'
    );
\syncstages_ff_reg[2][9]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \syncstages_ff[1]\(9),
      Q => \syncstages_ff[2]\(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_cdc_async_rst is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of design_1_Vsp_core_0_0_xpm_cdc_async_rst : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_async_rst : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_async_rst : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of design_1_Vsp_core_0_0_xpm_cdc_async_rst : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_cdc_async_rst : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of design_1_Vsp_core_0_0_xpm_cdc_async_rst : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of design_1_Vsp_core_0_0_xpm_cdc_async_rst : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of design_1_Vsp_core_0_0_xpm_cdc_async_rst : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of design_1_Vsp_core_0_0_xpm_cdc_async_rst : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of design_1_Vsp_core_0_0_xpm_cdc_async_rst : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of design_1_Vsp_core_0_0_xpm_cdc_async_rst : entity is "ASYNC_RST";
end design_1_Vsp_core_0_0_xpm_cdc_async_rst;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_cdc_async_rst is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_async_rst__1\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__1\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__1\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__1\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__1\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__1\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__1\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__1\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__1\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__1\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__1\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__1\ : entity is "ASYNC_RST";
end \design_1_Vsp_core_0_0_xpm_cdc_async_rst__1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__1\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_async_rst__2\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__2\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__2\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__2\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__2\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__2\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__2\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__2\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__2\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__2\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__2\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__2\ : entity is "ASYNC_RST";
end \design_1_Vsp_core_0_0_xpm_cdc_async_rst__2\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__2\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_async_rst__3\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__3\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__3\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__3\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__3\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__3\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__3\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__3\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__3\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__3\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__3\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__3\ : entity is "ASYNC_RST";
end \design_1_Vsp_core_0_0_xpm_cdc_async_rst__3\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__3\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_async_rst__4\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__4\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__4\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__4\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__4\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__4\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__4\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__4\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__4\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__4\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__4\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__4\ : entity is "ASYNC_RST";
end \design_1_Vsp_core_0_0_xpm_cdc_async_rst__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__4\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_async_rst__5\ is
  port (
    src_arst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_arst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__5\ : entity is "1'b1";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__5\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__5\ : entity is 0;
  attribute INV_DEF_VAL : string;
  attribute INV_DEF_VAL of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__5\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__5\ : entity is "xpm_cdc_async_rst";
  attribute RST_ACTIVE_HIGH : integer;
  attribute RST_ACTIVE_HIGH of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__5\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__5\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__5\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__5\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__5\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__5\ : entity is "ASYNC_RST";
end \design_1_Vsp_core_0_0_xpm_cdc_async_rst__5\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_async_rst__5\ is
  signal arststages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of arststages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of arststages_ff : signal is "true";
  attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST";
  signal reset_pol : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \arststages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST";
  attribute ASYNC_REG_boolean of \arststages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \arststages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \arststages_ff_reg[2]\ : label is "ASYNC_RST";
begin
  dest_arst <= arststages_ff(2);
\arststages_ff[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_arst,
      O => reset_pol
    );
\arststages_ff_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => '1',
      Q => arststages_ff(0)
    );
\arststages_ff_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(0),
      Q => arststages_ff(1)
    );
\arststages_ff_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '1'
    )
        port map (
      C => dest_clk,
      CE => '1',
      CLR => reset_pol,
      D => arststages_ff(1),
      Q => arststages_ff(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_cdc_gray is
  port (
    src_clk : in STD_LOGIC;
    src_in_bin : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dest_clk : in STD_LOGIC;
    dest_out_bin : out STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_gray : entity is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_gray : entity is 1;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_cdc_gray : entity is "xpm_cdc_gray";
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of design_1_Vsp_core_0_0_xpm_cdc_gray : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of design_1_Vsp_core_0_0_xpm_cdc_gray : entity is 0;
  attribute SIM_LOSSLESS_GRAY_CHK : integer;
  attribute SIM_LOSSLESS_GRAY_CHK of design_1_Vsp_core_0_0_xpm_cdc_gray : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of design_1_Vsp_core_0_0_xpm_cdc_gray : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of design_1_Vsp_core_0_0_xpm_cdc_gray : entity is 5;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of design_1_Vsp_core_0_0_xpm_cdc_gray : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of design_1_Vsp_core_0_0_xpm_cdc_gray : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of design_1_Vsp_core_0_0_xpm_cdc_gray : entity is "GRAY";
end design_1_Vsp_core_0_0_xpm_cdc_gray;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_cdc_gray is
  signal async_path : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
  signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
  attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
  signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal gray_enc : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair233";
  attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair233";
  attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair234";
  attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair234";
begin
  dest_out_bin(4) <= \dest_graysync_ff[1]\(4);
  dest_out_bin(3 downto 0) <= \^dest_out_bin\(3 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(0),
      Q => \dest_graysync_ff[0]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(1),
      Q => \dest_graysync_ff[0]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(2),
      Q => \dest_graysync_ff[0]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(3),
      Q => \dest_graysync_ff[0]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(4),
      Q => \dest_graysync_ff[0]\(4),
      R => '0'
    );
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(0),
      Q => \dest_graysync_ff[1]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(1),
      Q => \dest_graysync_ff[1]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(2),
      Q => \dest_graysync_ff[1]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(3),
      Q => \dest_graysync_ff[1]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(4),
      Q => \dest_graysync_ff[1]\(4),
      R => '0'
    );
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(0),
      I1 => \dest_graysync_ff[1]\(2),
      I2 => \dest_graysync_ff[1]\(4),
      I3 => \dest_graysync_ff[1]\(3),
      I4 => \dest_graysync_ff[1]\(1),
      O => \^dest_out_bin\(0)
    );
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(1),
      I1 => \dest_graysync_ff[1]\(3),
      I2 => \dest_graysync_ff[1]\(4),
      I3 => \dest_graysync_ff[1]\(2),
      O => \^dest_out_bin\(1)
    );
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(2),
      I1 => \dest_graysync_ff[1]\(4),
      I2 => \dest_graysync_ff[1]\(3),
      O => \^dest_out_bin\(2)
    );
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(3),
      I1 => \dest_graysync_ff[1]\(4),
      O => \^dest_out_bin\(3)
    );
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(1),
      I1 => src_in_bin(0),
      O => gray_enc(0)
    );
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(2),
      I1 => src_in_bin(1),
      O => gray_enc(1)
    );
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(3),
      I1 => src_in_bin(2),
      O => gray_enc(2)
    );
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(4),
      I1 => src_in_bin(3),
      O => gray_enc(3)
    );
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(0),
      Q => async_path(0),
      R => '0'
    );
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(1),
      Q => async_path(1),
      R => '0'
    );
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(2),
      Q => async_path(2),
      R => '0'
    );
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(3),
      Q => async_path(3),
      R => '0'
    );
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in_bin(4),
      Q => async_path(4),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_gray__4\ is
  port (
    src_clk : in STD_LOGIC;
    src_in_bin : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dest_clk : in STD_LOGIC;
    dest_out_bin : out STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_gray__4\ : entity is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_gray__4\ : entity is 1;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_gray__4\ : entity is "xpm_cdc_gray";
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of \design_1_Vsp_core_0_0_xpm_cdc_gray__4\ : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_gray__4\ : entity is 0;
  attribute SIM_LOSSLESS_GRAY_CHK : integer;
  attribute SIM_LOSSLESS_GRAY_CHK of \design_1_Vsp_core_0_0_xpm_cdc_gray__4\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_gray__4\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_gray__4\ : entity is 5;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_gray__4\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_gray__4\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_gray__4\ : entity is "GRAY";
end \design_1_Vsp_core_0_0_xpm_cdc_gray__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_gray__4\ is
  signal async_path : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
  signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
  attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
  signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal gray_enc : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair412";
  attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair412";
  attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair413";
  attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair413";
begin
  dest_out_bin(4) <= \dest_graysync_ff[1]\(4);
  dest_out_bin(3 downto 0) <= \^dest_out_bin\(3 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(0),
      Q => \dest_graysync_ff[0]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(1),
      Q => \dest_graysync_ff[0]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(2),
      Q => \dest_graysync_ff[0]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(3),
      Q => \dest_graysync_ff[0]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(4),
      Q => \dest_graysync_ff[0]\(4),
      R => '0'
    );
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(0),
      Q => \dest_graysync_ff[1]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(1),
      Q => \dest_graysync_ff[1]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(2),
      Q => \dest_graysync_ff[1]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(3),
      Q => \dest_graysync_ff[1]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(4),
      Q => \dest_graysync_ff[1]\(4),
      R => '0'
    );
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(0),
      I1 => \dest_graysync_ff[1]\(2),
      I2 => \dest_graysync_ff[1]\(4),
      I3 => \dest_graysync_ff[1]\(3),
      I4 => \dest_graysync_ff[1]\(1),
      O => \^dest_out_bin\(0)
    );
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(1),
      I1 => \dest_graysync_ff[1]\(3),
      I2 => \dest_graysync_ff[1]\(4),
      I3 => \dest_graysync_ff[1]\(2),
      O => \^dest_out_bin\(1)
    );
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(2),
      I1 => \dest_graysync_ff[1]\(4),
      I2 => \dest_graysync_ff[1]\(3),
      O => \^dest_out_bin\(2)
    );
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(3),
      I1 => \dest_graysync_ff[1]\(4),
      O => \^dest_out_bin\(3)
    );
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(1),
      I1 => src_in_bin(0),
      O => gray_enc(0)
    );
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(2),
      I1 => src_in_bin(1),
      O => gray_enc(1)
    );
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(3),
      I1 => src_in_bin(2),
      O => gray_enc(2)
    );
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(4),
      I1 => src_in_bin(3),
      O => gray_enc(3)
    );
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(0),
      Q => async_path(0),
      R => '0'
    );
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(1),
      Q => async_path(1),
      R => '0'
    );
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(2),
      Q => async_path(2),
      R => '0'
    );
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(3),
      Q => async_path(3),
      R => '0'
    );
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in_bin(4),
      Q => async_path(4),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_gray__5\ is
  port (
    src_clk : in STD_LOGIC;
    src_in_bin : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dest_clk : in STD_LOGIC;
    dest_out_bin : out STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_gray__5\ : entity is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_gray__5\ : entity is 1;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_gray__5\ : entity is "xpm_cdc_gray";
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of \design_1_Vsp_core_0_0_xpm_cdc_gray__5\ : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_gray__5\ : entity is 0;
  attribute SIM_LOSSLESS_GRAY_CHK : integer;
  attribute SIM_LOSSLESS_GRAY_CHK of \design_1_Vsp_core_0_0_xpm_cdc_gray__5\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_gray__5\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_gray__5\ : entity is 5;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_gray__5\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_gray__5\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_gray__5\ : entity is "GRAY";
end \design_1_Vsp_core_0_0_xpm_cdc_gray__5\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_gray__5\ is
  signal async_path : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
  signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
  attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
  signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal gray_enc : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair416";
  attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair416";
  attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair417";
  attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair417";
begin
  dest_out_bin(4) <= \dest_graysync_ff[1]\(4);
  dest_out_bin(3 downto 0) <= \^dest_out_bin\(3 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(0),
      Q => \dest_graysync_ff[0]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(1),
      Q => \dest_graysync_ff[0]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(2),
      Q => \dest_graysync_ff[0]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(3),
      Q => \dest_graysync_ff[0]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(4),
      Q => \dest_graysync_ff[0]\(4),
      R => '0'
    );
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(0),
      Q => \dest_graysync_ff[1]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(1),
      Q => \dest_graysync_ff[1]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(2),
      Q => \dest_graysync_ff[1]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(3),
      Q => \dest_graysync_ff[1]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(4),
      Q => \dest_graysync_ff[1]\(4),
      R => '0'
    );
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(0),
      I1 => \dest_graysync_ff[1]\(2),
      I2 => \dest_graysync_ff[1]\(4),
      I3 => \dest_graysync_ff[1]\(3),
      I4 => \dest_graysync_ff[1]\(1),
      O => \^dest_out_bin\(0)
    );
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(1),
      I1 => \dest_graysync_ff[1]\(3),
      I2 => \dest_graysync_ff[1]\(4),
      I3 => \dest_graysync_ff[1]\(2),
      O => \^dest_out_bin\(1)
    );
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(2),
      I1 => \dest_graysync_ff[1]\(4),
      I2 => \dest_graysync_ff[1]\(3),
      O => \^dest_out_bin\(2)
    );
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(3),
      I1 => \dest_graysync_ff[1]\(4),
      O => \^dest_out_bin\(3)
    );
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(1),
      I1 => src_in_bin(0),
      O => gray_enc(0)
    );
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(2),
      I1 => src_in_bin(1),
      O => gray_enc(1)
    );
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(3),
      I1 => src_in_bin(2),
      O => gray_enc(2)
    );
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(4),
      I1 => src_in_bin(3),
      O => gray_enc(3)
    );
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(0),
      Q => async_path(0),
      R => '0'
    );
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(1),
      Q => async_path(1),
      R => '0'
    );
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(2),
      Q => async_path(2),
      R => '0'
    );
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(3),
      Q => async_path(3),
      R => '0'
    );
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in_bin(4),
      Q => async_path(4),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_gray__6\ is
  port (
    src_clk : in STD_LOGIC;
    src_in_bin : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dest_clk : in STD_LOGIC;
    dest_out_bin : out STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_gray__6\ : entity is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_gray__6\ : entity is 1;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_gray__6\ : entity is "xpm_cdc_gray";
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of \design_1_Vsp_core_0_0_xpm_cdc_gray__6\ : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_gray__6\ : entity is 0;
  attribute SIM_LOSSLESS_GRAY_CHK : integer;
  attribute SIM_LOSSLESS_GRAY_CHK of \design_1_Vsp_core_0_0_xpm_cdc_gray__6\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_gray__6\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_gray__6\ : entity is 5;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_gray__6\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_gray__6\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_gray__6\ : entity is "GRAY";
end \design_1_Vsp_core_0_0_xpm_cdc_gray__6\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_gray__6\ is
  signal async_path : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
  signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
  attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
  signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal gray_enc : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair229";
  attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair229";
  attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair230";
  attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair230";
begin
  dest_out_bin(4) <= \dest_graysync_ff[1]\(4);
  dest_out_bin(3 downto 0) <= \^dest_out_bin\(3 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(0),
      Q => \dest_graysync_ff[0]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(1),
      Q => \dest_graysync_ff[0]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(2),
      Q => \dest_graysync_ff[0]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(3),
      Q => \dest_graysync_ff[0]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(4),
      Q => \dest_graysync_ff[0]\(4),
      R => '0'
    );
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(0),
      Q => \dest_graysync_ff[1]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(1),
      Q => \dest_graysync_ff[1]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(2),
      Q => \dest_graysync_ff[1]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(3),
      Q => \dest_graysync_ff[1]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(4),
      Q => \dest_graysync_ff[1]\(4),
      R => '0'
    );
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(0),
      I1 => \dest_graysync_ff[1]\(2),
      I2 => \dest_graysync_ff[1]\(4),
      I3 => \dest_graysync_ff[1]\(3),
      I4 => \dest_graysync_ff[1]\(1),
      O => \^dest_out_bin\(0)
    );
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(1),
      I1 => \dest_graysync_ff[1]\(3),
      I2 => \dest_graysync_ff[1]\(4),
      I3 => \dest_graysync_ff[1]\(2),
      O => \^dest_out_bin\(1)
    );
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(2),
      I1 => \dest_graysync_ff[1]\(4),
      I2 => \dest_graysync_ff[1]\(3),
      O => \^dest_out_bin\(2)
    );
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(3),
      I1 => \dest_graysync_ff[1]\(4),
      O => \^dest_out_bin\(3)
    );
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(1),
      I1 => src_in_bin(0),
      O => gray_enc(0)
    );
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(2),
      I1 => src_in_bin(1),
      O => gray_enc(1)
    );
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(3),
      I1 => src_in_bin(2),
      O => gray_enc(2)
    );
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(4),
      I1 => src_in_bin(3),
      O => gray_enc(3)
    );
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(0),
      Q => async_path(0),
      R => '0'
    );
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(1),
      Q => async_path(1),
      R => '0'
    );
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(2),
      Q => async_path(2),
      R => '0'
    );
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(3),
      Q => async_path(3),
      R => '0'
    );
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in_bin(4),
      Q => async_path(4),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\ is
  port (
    src_clk : in STD_LOGIC;
    src_in_bin : in STD_LOGIC_VECTOR ( 5 downto 0 );
    dest_clk : in STD_LOGIC;
    dest_out_bin : out STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\ : entity is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\ : entity is 1;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\ : entity is "xpm_cdc_gray";
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\ : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\ : entity is 0;
  attribute SIM_LOSSLESS_GRAY_CHK : integer;
  attribute SIM_LOSSLESS_GRAY_CHK of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\ : entity is 6;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\ : entity is "GRAY";
end \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\ is
  signal async_path : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
  signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
  attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
  signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal gray_enc : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair235";
  attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair235";
  attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair236";
  attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair236";
begin
  dest_out_bin(5) <= \dest_graysync_ff[1]\(5);
  dest_out_bin(4 downto 0) <= \^dest_out_bin\(4 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(0),
      Q => \dest_graysync_ff[0]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(1),
      Q => \dest_graysync_ff[0]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(2),
      Q => \dest_graysync_ff[0]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(3),
      Q => \dest_graysync_ff[0]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(4),
      Q => \dest_graysync_ff[0]\(4),
      R => '0'
    );
\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(5),
      Q => \dest_graysync_ff[0]\(5),
      R => '0'
    );
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(0),
      Q => \dest_graysync_ff[1]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(1),
      Q => \dest_graysync_ff[1]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(2),
      Q => \dest_graysync_ff[1]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(3),
      Q => \dest_graysync_ff[1]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(4),
      Q => \dest_graysync_ff[1]\(4),
      R => '0'
    );
\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(5),
      Q => \dest_graysync_ff[1]\(5),
      R => '0'
    );
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(0),
      I1 => \dest_graysync_ff[1]\(2),
      I2 => \dest_graysync_ff[1]\(4),
      I3 => \dest_graysync_ff[1]\(5),
      I4 => \dest_graysync_ff[1]\(3),
      I5 => \dest_graysync_ff[1]\(1),
      O => \^dest_out_bin\(0)
    );
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(1),
      I1 => \dest_graysync_ff[1]\(3),
      I2 => \dest_graysync_ff[1]\(5),
      I3 => \dest_graysync_ff[1]\(4),
      I4 => \dest_graysync_ff[1]\(2),
      O => \^dest_out_bin\(1)
    );
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(2),
      I1 => \dest_graysync_ff[1]\(4),
      I2 => \dest_graysync_ff[1]\(5),
      I3 => \dest_graysync_ff[1]\(3),
      O => \^dest_out_bin\(2)
    );
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(3),
      I1 => \dest_graysync_ff[1]\(5),
      I2 => \dest_graysync_ff[1]\(4),
      O => \^dest_out_bin\(3)
    );
\dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(4),
      I1 => \dest_graysync_ff[1]\(5),
      O => \^dest_out_bin\(4)
    );
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(1),
      I1 => src_in_bin(0),
      O => gray_enc(0)
    );
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(2),
      I1 => src_in_bin(1),
      O => gray_enc(1)
    );
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(3),
      I1 => src_in_bin(2),
      O => gray_enc(2)
    );
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(4),
      I1 => src_in_bin(3),
      O => gray_enc(3)
    );
\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(5),
      I1 => src_in_bin(4),
      O => gray_enc(4)
    );
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(0),
      Q => async_path(0),
      R => '0'
    );
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(1),
      Q => async_path(1),
      R => '0'
    );
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(2),
      Q => async_path(2),
      R => '0'
    );
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(3),
      Q => async_path(3),
      R => '0'
    );
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(4),
      Q => async_path(4),
      R => '0'
    );
\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in_bin(5),
      Q => async_path(5),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\ is
  port (
    src_clk : in STD_LOGIC;
    src_in_bin : in STD_LOGIC_VECTOR ( 5 downto 0 );
    dest_clk : in STD_LOGIC;
    dest_out_bin : out STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\ : entity is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\ : entity is 1;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\ : entity is "xpm_cdc_gray";
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\ : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\ : entity is 0;
  attribute SIM_LOSSLESS_GRAY_CHK : integer;
  attribute SIM_LOSSLESS_GRAY_CHK of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\ : entity is 6;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\ : entity is "GRAY";
end \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\ is
  signal async_path : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
  signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
  attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
  signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal gray_enc : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair414";
  attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair414";
  attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair415";
  attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair415";
begin
  dest_out_bin(5) <= \dest_graysync_ff[1]\(5);
  dest_out_bin(4 downto 0) <= \^dest_out_bin\(4 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(0),
      Q => \dest_graysync_ff[0]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(1),
      Q => \dest_graysync_ff[0]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(2),
      Q => \dest_graysync_ff[0]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(3),
      Q => \dest_graysync_ff[0]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(4),
      Q => \dest_graysync_ff[0]\(4),
      R => '0'
    );
\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(5),
      Q => \dest_graysync_ff[0]\(5),
      R => '0'
    );
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(0),
      Q => \dest_graysync_ff[1]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(1),
      Q => \dest_graysync_ff[1]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(2),
      Q => \dest_graysync_ff[1]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(3),
      Q => \dest_graysync_ff[1]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(4),
      Q => \dest_graysync_ff[1]\(4),
      R => '0'
    );
\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(5),
      Q => \dest_graysync_ff[1]\(5),
      R => '0'
    );
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(0),
      I1 => \dest_graysync_ff[1]\(2),
      I2 => \dest_graysync_ff[1]\(4),
      I3 => \dest_graysync_ff[1]\(5),
      I4 => \dest_graysync_ff[1]\(3),
      I5 => \dest_graysync_ff[1]\(1),
      O => \^dest_out_bin\(0)
    );
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(1),
      I1 => \dest_graysync_ff[1]\(3),
      I2 => \dest_graysync_ff[1]\(5),
      I3 => \dest_graysync_ff[1]\(4),
      I4 => \dest_graysync_ff[1]\(2),
      O => \^dest_out_bin\(1)
    );
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(2),
      I1 => \dest_graysync_ff[1]\(4),
      I2 => \dest_graysync_ff[1]\(5),
      I3 => \dest_graysync_ff[1]\(3),
      O => \^dest_out_bin\(2)
    );
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(3),
      I1 => \dest_graysync_ff[1]\(5),
      I2 => \dest_graysync_ff[1]\(4),
      O => \^dest_out_bin\(3)
    );
\dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(4),
      I1 => \dest_graysync_ff[1]\(5),
      O => \^dest_out_bin\(4)
    );
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(1),
      I1 => src_in_bin(0),
      O => gray_enc(0)
    );
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(2),
      I1 => src_in_bin(1),
      O => gray_enc(1)
    );
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(3),
      I1 => src_in_bin(2),
      O => gray_enc(2)
    );
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(4),
      I1 => src_in_bin(3),
      O => gray_enc(3)
    );
\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(5),
      I1 => src_in_bin(4),
      O => gray_enc(4)
    );
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(0),
      Q => async_path(0),
      R => '0'
    );
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(1),
      Q => async_path(1),
      R => '0'
    );
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(2),
      Q => async_path(2),
      R => '0'
    );
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(3),
      Q => async_path(3),
      R => '0'
    );
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(4),
      Q => async_path(4),
      R => '0'
    );
\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in_bin(5),
      Q => async_path(5),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\ is
  port (
    src_clk : in STD_LOGIC;
    src_in_bin : in STD_LOGIC_VECTOR ( 5 downto 0 );
    dest_clk : in STD_LOGIC;
    dest_out_bin : out STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\ : entity is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\ : entity is 1;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\ : entity is "xpm_cdc_gray";
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\ : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\ : entity is 0;
  attribute SIM_LOSSLESS_GRAY_CHK : integer;
  attribute SIM_LOSSLESS_GRAY_CHK of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\ : entity is 6;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\ : entity is "GRAY";
end \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\ is
  signal async_path : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
  signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
  attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
  signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal gray_enc : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair418";
  attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair418";
  attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair419";
  attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair419";
begin
  dest_out_bin(5) <= \dest_graysync_ff[1]\(5);
  dest_out_bin(4 downto 0) <= \^dest_out_bin\(4 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(0),
      Q => \dest_graysync_ff[0]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(1),
      Q => \dest_graysync_ff[0]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(2),
      Q => \dest_graysync_ff[0]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(3),
      Q => \dest_graysync_ff[0]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(4),
      Q => \dest_graysync_ff[0]\(4),
      R => '0'
    );
\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(5),
      Q => \dest_graysync_ff[0]\(5),
      R => '0'
    );
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(0),
      Q => \dest_graysync_ff[1]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(1),
      Q => \dest_graysync_ff[1]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(2),
      Q => \dest_graysync_ff[1]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(3),
      Q => \dest_graysync_ff[1]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(4),
      Q => \dest_graysync_ff[1]\(4),
      R => '0'
    );
\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(5),
      Q => \dest_graysync_ff[1]\(5),
      R => '0'
    );
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(0),
      I1 => \dest_graysync_ff[1]\(2),
      I2 => \dest_graysync_ff[1]\(4),
      I3 => \dest_graysync_ff[1]\(5),
      I4 => \dest_graysync_ff[1]\(3),
      I5 => \dest_graysync_ff[1]\(1),
      O => \^dest_out_bin\(0)
    );
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(1),
      I1 => \dest_graysync_ff[1]\(3),
      I2 => \dest_graysync_ff[1]\(5),
      I3 => \dest_graysync_ff[1]\(4),
      I4 => \dest_graysync_ff[1]\(2),
      O => \^dest_out_bin\(1)
    );
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(2),
      I1 => \dest_graysync_ff[1]\(4),
      I2 => \dest_graysync_ff[1]\(5),
      I3 => \dest_graysync_ff[1]\(3),
      O => \^dest_out_bin\(2)
    );
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(3),
      I1 => \dest_graysync_ff[1]\(5),
      I2 => \dest_graysync_ff[1]\(4),
      O => \^dest_out_bin\(3)
    );
\dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(4),
      I1 => \dest_graysync_ff[1]\(5),
      O => \^dest_out_bin\(4)
    );
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(1),
      I1 => src_in_bin(0),
      O => gray_enc(0)
    );
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(2),
      I1 => src_in_bin(1),
      O => gray_enc(1)
    );
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(3),
      I1 => src_in_bin(2),
      O => gray_enc(2)
    );
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(4),
      I1 => src_in_bin(3),
      O => gray_enc(3)
    );
\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(5),
      I1 => src_in_bin(4),
      O => gray_enc(4)
    );
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(0),
      Q => async_path(0),
      R => '0'
    );
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(1),
      Q => async_path(1),
      R => '0'
    );
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(2),
      Q => async_path(2),
      R => '0'
    );
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(3),
      Q => async_path(3),
      R => '0'
    );
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(4),
      Q => async_path(4),
      R => '0'
    );
\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in_bin(5),
      Q => async_path(5),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\ is
  port (
    src_clk : in STD_LOGIC;
    src_in_bin : in STD_LOGIC_VECTOR ( 5 downto 0 );
    dest_clk : in STD_LOGIC;
    dest_out_bin : out STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\ : entity is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\ : entity is 1;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\ : entity is "xpm_cdc_gray";
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\ : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\ : entity is 0;
  attribute SIM_LOSSLESS_GRAY_CHK : integer;
  attribute SIM_LOSSLESS_GRAY_CHK of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\ : entity is 6;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\ : entity is "GRAY";
end \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\ is
  signal async_path : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
  attribute async_reg : string;
  attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
  signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
  attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
  attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
  signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal gray_enc : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
  attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true;
  attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true";
  attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair231";
  attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair231";
  attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair232";
  attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair232";
begin
  dest_out_bin(5) <= \dest_graysync_ff[1]\(5);
  dest_out_bin(4 downto 0) <= \^dest_out_bin\(4 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(0),
      Q => \dest_graysync_ff[0]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(1),
      Q => \dest_graysync_ff[0]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(2),
      Q => \dest_graysync_ff[0]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(3),
      Q => \dest_graysync_ff[0]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(4),
      Q => \dest_graysync_ff[0]\(4),
      R => '0'
    );
\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => async_path(5),
      Q => \dest_graysync_ff[0]\(5),
      R => '0'
    );
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(0),
      Q => \dest_graysync_ff[1]\(0),
      R => '0'
    );
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(1),
      Q => \dest_graysync_ff[1]\(1),
      R => '0'
    );
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(2),
      Q => \dest_graysync_ff[1]\(2),
      R => '0'
    );
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(3),
      Q => \dest_graysync_ff[1]\(3),
      R => '0'
    );
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(4),
      Q => \dest_graysync_ff[1]\(4),
      R => '0'
    );
\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \dest_graysync_ff[0]\(5),
      Q => \dest_graysync_ff[1]\(5),
      R => '0'
    );
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(0),
      I1 => \dest_graysync_ff[1]\(2),
      I2 => \dest_graysync_ff[1]\(4),
      I3 => \dest_graysync_ff[1]\(5),
      I4 => \dest_graysync_ff[1]\(3),
      I5 => \dest_graysync_ff[1]\(1),
      O => \^dest_out_bin\(0)
    );
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(1),
      I1 => \dest_graysync_ff[1]\(3),
      I2 => \dest_graysync_ff[1]\(5),
      I3 => \dest_graysync_ff[1]\(4),
      I4 => \dest_graysync_ff[1]\(2),
      O => \^dest_out_bin\(1)
    );
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(2),
      I1 => \dest_graysync_ff[1]\(4),
      I2 => \dest_graysync_ff[1]\(5),
      I3 => \dest_graysync_ff[1]\(3),
      O => \^dest_out_bin\(2)
    );
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(3),
      I1 => \dest_graysync_ff[1]\(5),
      I2 => \dest_graysync_ff[1]\(4),
      O => \^dest_out_bin\(3)
    );
\dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \dest_graysync_ff[1]\(4),
      I1 => \dest_graysync_ff[1]\(5),
      O => \^dest_out_bin\(4)
    );
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(1),
      I1 => src_in_bin(0),
      O => gray_enc(0)
    );
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(2),
      I1 => src_in_bin(1),
      O => gray_enc(1)
    );
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(3),
      I1 => src_in_bin(2),
      O => gray_enc(2)
    );
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(4),
      I1 => src_in_bin(3),
      O => gray_enc(3)
    );
\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => src_in_bin(5),
      I1 => src_in_bin(4),
      O => gray_enc(4)
    );
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(0),
      Q => async_path(0),
      R => '0'
    );
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(1),
      Q => async_path(1),
      R => '0'
    );
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(2),
      Q => async_path(2),
      R => '0'
    );
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(3),
      Q => async_path(3),
      R => '0'
    );
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => gray_enc(4),
      Q => async_path(4),
      R => '0'
    );
\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in_bin(5),
      Q => async_path(5),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_cdc_single is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_single : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_single : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_cdc_single : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of design_1_Vsp_core_0_0_xpm_cdc_single : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of design_1_Vsp_core_0_0_xpm_cdc_single : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of design_1_Vsp_core_0_0_xpm_cdc_single : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of design_1_Vsp_core_0_0_xpm_cdc_single : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of design_1_Vsp_core_0_0_xpm_cdc_single : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of design_1_Vsp_core_0_0_xpm_cdc_single : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of design_1_Vsp_core_0_0_xpm_cdc_single : entity is "SINGLE";
end design_1_Vsp_core_0_0_xpm_cdc_single;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_cdc_single is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__132\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__132\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__132\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__132\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__132\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__132\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__132\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__132\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__132\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__132\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__132\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__132\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__132\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__133\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__133\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__133\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__133\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__133\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__133\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__133\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__133\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__133\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__133\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__133\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__133\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__133\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__134\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__134\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__134\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__134\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__134\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__134\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__134\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__134\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__134\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__134\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__134\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__134\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__134\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__135\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__135\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__135\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__135\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__135\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__135\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__135\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__135\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__135\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__135\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__135\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__135\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__135\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__136\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__136\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__136\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__136\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__136\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__136\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__136\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__136\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__136\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__136\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__136\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__136\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__136\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__137\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__137\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__137\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__137\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__137\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__137\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__137\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__137\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__137\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__137\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__137\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__137\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__137\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__138\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__138\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__138\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__138\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__138\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__138\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__138\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__138\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__138\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__138\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__138\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__138\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__138\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__139\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__139\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__139\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__139\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__139\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__139\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__139\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__139\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__139\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__139\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__139\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__139\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__139\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__140\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__140\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__140\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__140\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__140\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__140\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__140\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__140\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__140\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__140\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__140\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__140\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__140\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__141\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__141\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__141\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__141\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__141\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__141\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__141\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__141\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__141\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__141\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__141\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__141\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__141\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__142\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__142\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__142\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__142\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__142\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__142\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__142\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__142\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__142\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__142\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__142\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__142\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__142\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__143\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__143\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__143\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__143\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__143\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__143\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__143\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__143\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__143\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__143\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__143\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__143\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__143\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__144\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__144\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__144\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__144\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__144\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__144\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__144\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__144\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__144\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__144\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__144\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__144\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__144\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '1',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__145\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__145\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__145\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__145\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__145\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__145\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__145\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__145\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__145\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__145\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__145\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__145\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__145\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__146\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__146\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__146\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__146\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__146\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__146\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__146\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__146\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__146\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__146\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__146\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__146\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__146\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__147\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__147\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__147\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__147\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__147\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__147\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__147\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__147\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__147\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__147\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__147\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__147\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__147\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__148\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__148\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__148\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__148\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__148\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__148\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__148\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__148\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__148\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__148\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__148\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__148\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__148\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__149\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__149\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__149\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__149\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__149\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__149\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__149\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__149\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__149\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__149\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__149\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__149\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__149\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__150\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__150\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__150\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__150\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__150\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__150\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__150\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__150\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__150\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__150\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__150\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__150\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__150\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__151\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__151\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__151\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__151\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__151\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__151\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__151\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__151\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__151\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__151\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__151\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__151\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__151\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__152\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__152\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__152\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__152\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__152\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__152\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__152\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__152\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__152\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__152\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__152\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__152\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__152\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__153\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__153\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__153\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__153\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__153\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__153\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__153\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__153\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__153\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__153\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__153\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__153\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__153\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__154\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__154\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__154\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__154\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__154\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__154\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__154\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__154\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__154\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__154\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__154\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__154\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__154\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__155\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__155\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__155\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__155\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__155\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__155\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__155\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__155\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__155\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__155\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__155\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__155\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__155\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__156\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__156\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__156\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__156\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__156\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__156\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__156\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__156\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__156\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__156\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__156\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__156\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__156\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__157\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__157\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__157\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__157\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__157\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__157\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__157\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__157\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__157\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__157\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__157\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__157\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__157\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__158\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__158\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__158\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__158\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__158\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__158\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__158\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__158\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__158\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__158\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__158\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__158\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__158\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__159\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__159\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__159\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__159\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__159\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__159\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__159\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__159\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__159\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__159\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__159\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__159\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__159\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__160\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__160\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__160\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__160\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__160\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__160\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__160\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__160\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__160\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__160\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__160\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__160\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__160\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__161\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__161\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__161\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__161\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__161\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__161\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__161\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__161\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__161\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__161\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__161\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__161\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__161\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__162\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__162\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__162\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__162\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__162\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__162\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__162\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__162\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__162\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__162\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__162\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__162\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__162\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__163\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__163\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__163\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__163\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__163\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__163\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__163\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__163\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__163\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__163\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__163\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__163\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__163\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__164\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__164\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__164\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__164\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__164\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__164\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__164\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__164\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__164\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__164\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__164\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__164\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__164\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__165\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__165\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__165\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__165\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__165\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__165\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__165\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__165\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__165\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__165\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__165\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__165\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__165\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__166\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__166\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__166\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__166\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__166\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__166\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__166\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__166\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__166\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__166\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__166\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__166\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__166\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__167\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__167\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__167\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__167\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__167\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__167\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__167\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__167\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__167\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__167\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__167\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__167\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__167\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__168\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__168\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__168\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__168\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__168\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__168\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__168\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__168\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__168\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__168\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__168\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__168\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__168\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__169\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__169\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__169\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__169\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__169\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__169\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__169\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__169\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__169\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__169\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__169\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__169\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__169\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__170\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__170\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__170\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__170\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__170\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__170\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__170\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__170\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__170\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__170\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__170\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__170\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__170\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__171\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__171\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__171\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__171\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__171\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__171\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__171\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__171\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__171\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__171\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__171\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__171\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__171\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__172\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__172\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__172\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__172\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__172\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__172\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__172\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__172\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__172\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__172\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__172\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__172\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__172\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__173\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__173\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__173\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__173\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__173\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__173\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__173\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__173\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__173\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__173\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__173\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__173\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__173\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__174\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__174\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__174\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__174\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__174\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__174\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__174\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__174\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__174\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__174\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__174\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__174\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__174\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__175\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__175\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__175\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__175\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__175\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__175\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__175\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__175\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__175\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__175\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__175\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__175\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__175\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__176\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__176\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__176\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__176\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__176\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__176\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__176\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__176\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__176\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__176\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__176\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__176\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__176\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__177\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__177\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__177\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__177\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__177\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__177\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__177\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__177\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__177\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__177\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__177\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__177\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__177\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__178\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__178\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__178\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__178\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__178\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__178\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__178\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__178\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__178\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__178\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__178\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__178\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__178\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__179\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__179\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__179\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__179\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__179\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__179\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__179\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__179\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__179\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__179\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__179\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__179\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__179\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__180\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__180\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__180\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__180\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__180\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__180\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__180\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__180\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__180\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__180\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__180\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__180\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__180\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__181\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__181\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__181\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__181\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__181\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__181\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__181\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__181\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__181\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__181\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__181\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__181\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__181\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__182\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__182\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__182\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__182\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__182\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__182\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__182\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__182\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__182\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__182\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__182\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__182\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__182\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__183\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__183\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__183\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__183\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__183\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__183\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__183\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__183\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__183\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__183\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__183\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__183\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__183\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__184\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__184\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__184\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__184\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__184\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__184\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__184\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__184\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__184\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__184\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__184\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__184\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__184\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__185\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__185\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__185\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__185\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__185\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__185\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__185\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__185\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__185\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__185\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__185\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__185\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__185\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__186\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__186\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__186\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__186\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__186\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__186\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__186\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__186\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__186\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__186\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__186\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__186\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__186\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__187\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__187\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__187\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__187\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__187\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__187\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__187\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__187\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__187\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__187\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__187\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__187\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__187\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__188\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__188\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__188\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__188\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__188\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__188\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__188\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__188\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__188\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__188\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__188\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__188\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__188\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__189\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__189\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__189\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__189\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__189\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__189\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__189\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__189\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__189\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__189\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__189\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__189\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__189\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__190\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__190\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__190\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__190\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__190\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__190\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__190\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__190\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__190\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__190\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__190\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__190\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__190\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__191\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__191\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__191\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__191\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__191\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__191\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__191\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__191\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__191\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__191\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__191\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__191\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__191\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__192\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__192\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__192\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__192\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__192\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__192\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__192\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__192\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__192\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__192\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__192\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__192\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__192\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__193\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__193\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__193\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__193\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__193\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__193\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__193\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__193\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__193\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__193\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__193\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__193\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__193\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__194\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__194\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__194\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__194\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__194\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__194\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__194\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__194\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__194\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__194\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__194\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__194\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__194\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__195\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__195\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__195\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__195\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__195\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__195\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__195\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__195\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__195\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__195\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__195\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__195\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__195\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__196\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__196\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__196\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__196\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__196\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__196\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__196\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__196\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__196\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__196\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__196\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__196\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__196\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__197\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__197\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__197\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__197\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__197\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__197\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__197\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__197\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__197\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__197\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__197\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__197\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__197\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__198\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__198\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__198\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__198\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__198\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__198\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__198\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__198\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__198\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__198\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__198\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__198\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__198\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__199\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__199\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__199\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__199\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__199\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__199\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__199\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__199\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__199\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__199\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__199\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__199\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__199\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__200\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__200\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__200\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__200\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__200\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__200\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__200\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__200\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__200\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__200\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__200\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__200\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__200\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__201\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__201\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__201\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__201\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__201\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__201\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__201\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__201\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__201\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__201\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__201\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__201\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__201\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__202\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__202\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__202\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__202\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__202\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__202\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__202\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__202\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__202\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__202\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__202\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__202\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__202\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__203\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__203\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__203\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__203\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__203\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__203\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__203\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__203\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__203\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__203\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__203\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__203\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__203\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__204\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__204\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__204\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__204\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__204\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__204\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__204\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__204\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__204\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__204\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__204\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__204\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__204\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__205\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__205\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__205\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__205\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__205\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__205\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__205\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__205\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__205\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__205\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__205\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__205\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__205\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__206\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__206\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__206\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__206\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__206\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__206\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__206\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__206\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__206\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__206\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__206\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__206\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__206\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__207\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__207\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__207\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__207\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__207\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__207\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__207\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__207\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__207\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__207\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__207\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__207\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__207\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__208\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__208\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__208\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__208\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__208\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__208\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__208\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__208\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__208\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__208\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__208\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__208\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__208\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__209\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__209\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__209\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__209\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__209\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__209\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__209\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__209\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__209\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__209\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__209\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__209\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__209\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__210\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__210\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__210\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__210\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__210\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__210\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__210\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__210\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__210\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__210\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__210\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__210\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__210\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__211\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__211\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__211\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__211\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__211\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__211\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__211\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__211\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__211\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__211\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__211\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__211\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__211\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__212\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__212\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__212\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__212\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__212\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__212\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__212\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__212\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__212\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__212\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__212\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__212\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__212\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__213\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__213\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__213\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__213\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__213\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__213\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__213\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__213\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__213\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__213\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__213\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__213\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__213\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__214\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__214\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__214\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__214\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__214\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__214\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__214\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__214\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__214\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__214\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__214\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__214\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__214\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__215\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__215\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__215\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__215\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__215\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__215\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__215\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__215\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__215\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__215\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__215\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__215\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__215\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__216\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__216\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__216\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__216\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__216\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__216\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__216\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__216\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__216\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__216\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__216\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__216\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__216\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__217\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__217\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__217\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__217\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__217\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__217\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__217\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__217\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__217\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__217\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__217\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__217\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__217\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__218\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__218\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__218\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__218\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__218\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__218\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__218\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__218\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__218\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__218\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__218\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__218\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__218\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__219\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__219\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__219\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__219\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__219\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__219\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__219\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__219\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__219\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__219\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__219\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__219\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__219\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__220\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__220\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__220\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__220\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__220\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__220\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__220\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__220\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__220\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__220\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__220\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__220\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__220\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__221\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__221\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__221\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__221\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__221\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__221\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__221\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__221\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__221\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__221\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__221\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__221\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__221\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__222\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__222\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__222\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__222\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__222\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__222\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__222\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__222\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__222\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__222\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__222\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__222\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__222\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__223\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__223\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__223\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__223\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__223\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__223\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__223\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__223\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__223\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__223\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__223\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__223\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__223\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__224\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__224\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__224\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__224\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__224\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__224\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__224\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__224\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__224\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__224\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__224\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__224\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__224\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__225\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__225\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__225\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__225\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__225\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__225\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__225\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__225\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__225\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__225\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__225\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__225\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__225\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__226\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__226\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__226\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__226\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__226\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__226\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__226\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__226\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__226\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__226\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__226\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__226\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__226\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__227\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__227\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__227\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__227\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__227\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__227\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__227\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__227\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__227\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__227\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__227\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__227\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__227\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__228\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__228\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__228\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__228\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__228\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__228\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__228\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__228\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__228\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__228\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__228\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__228\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__228\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__229\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__229\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__229\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__229\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__229\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__229\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__229\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__229\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__229\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__229\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__229\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__229\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__229\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__230\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__230\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__230\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__230\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__230\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__230\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__230\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__230\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__230\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__230\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__230\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__230\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__230\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__231\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__231\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__231\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__231\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__231\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__231\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__231\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__231\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__231\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__231\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__231\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__231\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__231\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__232\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__232\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__232\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__232\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__232\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__232\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__232\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__232\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__232\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__232\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__232\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__232\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__232\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__233\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__233\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__233\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__233\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__233\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__233\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__233\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__233\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__233\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__233\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__233\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__233\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__233\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__234\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__234\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__234\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__234\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__234\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__234\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__234\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__234\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__234\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__234\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__234\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__234\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__234\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__235\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__235\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__235\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__235\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__235\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__235\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__235\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__235\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__235\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__235\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__235\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__235\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__235\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__236\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__236\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__236\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__236\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__236\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__236\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__236\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__236\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__236\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__236\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__236\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__236\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__236\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__237\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__237\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__237\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__237\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__237\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__237\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__237\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__237\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__237\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__237\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__237\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__237\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__237\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__238\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__238\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__238\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__238\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__238\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__238\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__238\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__238\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__238\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__238\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__238\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__238\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__238\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__239\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__239\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__239\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__239\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__239\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__239\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__239\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__239\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__239\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__239\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__239\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__239\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__239\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__240\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__240\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__240\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__240\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__240\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__240\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__240\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__240\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__240\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__240\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__240\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__240\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__240\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__241\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__241\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__241\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__241\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__241\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__241\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__241\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__241\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__241\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__241\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__241\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__241\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__241\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__242\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__242\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__242\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__242\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__242\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__242\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__242\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__242\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__242\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__242\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__242\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__242\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__242\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__243\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__243\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__243\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__243\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__243\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__243\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__243\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__243\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__243\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__243\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__243\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__243\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__243\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__244\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__244\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__244\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__244\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__244\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__244\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__244\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__244\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__244\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__244\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__244\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__244\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__244\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__245\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__245\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__245\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__245\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__245\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__245\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__245\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__245\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__245\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__245\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__245\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__245\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__245\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__246\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__246\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__246\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__246\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__246\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__246\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__246\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__246\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__246\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__246\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__246\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__246\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__246\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__247\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__247\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__247\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__247\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__247\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__247\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__247\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__247\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__247\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__247\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__247\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__247\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__247\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__248\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__248\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__248\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__248\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__248\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__248\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__248\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__248\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__248\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__248\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__248\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__248\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__248\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__249\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__249\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__249\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__249\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__249\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__249\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__249\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__249\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__249\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__249\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__249\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__249\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__249\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__250\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__250\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__250\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__250\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__250\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__250\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__250\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__250\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__250\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__250\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__250\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__250\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__250\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__251\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__251\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__251\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__251\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__251\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__251\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__251\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__251\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__251\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__251\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__251\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__251\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__251\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__252\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__252\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__252\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__252\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__252\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__252\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__252\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__252\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__252\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__252\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__252\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__252\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__252\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__253\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__253\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__253\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__253\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__253\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__253\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__253\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__253\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__253\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__253\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__253\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__253\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__253\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__254\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__254\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__254\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__254\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__254\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__254\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__254\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__254\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__254\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__254\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__254\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__254\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__254\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__255\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__255\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__255\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__255\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__255\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__255\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__255\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__255\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__255\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__255\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__255\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__255\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__255\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__256\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__256\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__256\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__256\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__256\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__256\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__256\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__256\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__256\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__256\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__256\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__256\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__256\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__257\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__257\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__257\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__257\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__257\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__257\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__257\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__257\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__257\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__257\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__257\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__257\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__257\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__258\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__258\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__258\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__258\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__258\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__258\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__258\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__258\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__258\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__258\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__258\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__258\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__258\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => '0',
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__259\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__259\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__259\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__259\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__259\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__259\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__259\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__259\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__259\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__259\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__259\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__259\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__259\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__260\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__260\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__260\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__260\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__260\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__260\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__260\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__260\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__260\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__260\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__260\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__260\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__260\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__261\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__261\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__261\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__261\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__261\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__261\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__261\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__261\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__261\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__261\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__261\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__261\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__261\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__262\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__262\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__262\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__262\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__262\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__262\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__262\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__262\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__262\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__262\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__262\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__262\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__262\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__263\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__263\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__263\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__263\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__263\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__263\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__263\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__263\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__263\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__263\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__263\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__263\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__263\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__264\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__264\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__264\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__264\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__264\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__264\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__264\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__264\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__264\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__264\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__264\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__264\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__264\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0\ : entity is 1;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0\ is
  signal p_0_in : STD_LOGIC_VECTOR ( 0 to 0 );
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
src_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in,
      Q => p_0_in(0),
      R => '0'
    );
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => p_0_in(0),
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__3\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__3\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__3\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__3\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__3\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__3\ : entity is 1;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__3\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__3\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__3\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__3\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__3\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__3\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__3\ is
  signal p_0_in : STD_LOGIC_VECTOR ( 0 to 0 );
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
src_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => p_0_in(0),
      R => '0'
    );
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => p_0_in(0),
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__4\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__4\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__4\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__4\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__4\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__4\ : entity is 1;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__4\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__4\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__4\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__4\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__4\ : entity is "SINGLE";
end \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_single__parameterized0__4\ is
  signal p_0_in : STD_LOGIC_VECTOR ( 0 to 0 );
  signal syncstages_ff : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(2);
src_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_in,
      Q => p_0_in(0),
      R => '0'
    );
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => p_0_in(0),
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_cdc_sync_rst is
  port (
    src_rst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_rst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of design_1_Vsp_core_0_0_xpm_cdc_sync_rst : entity is "1'b0";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_sync_rst : entity is 2;
  attribute INIT : string;
  attribute INIT of design_1_Vsp_core_0_0_xpm_cdc_sync_rst : entity is "0";
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_sync_rst : entity is 1;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_cdc_sync_rst : entity is "xpm_cdc_sync_rst";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of design_1_Vsp_core_0_0_xpm_cdc_sync_rst : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of design_1_Vsp_core_0_0_xpm_cdc_sync_rst : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of design_1_Vsp_core_0_0_xpm_cdc_sync_rst : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of design_1_Vsp_core_0_0_xpm_cdc_sync_rst : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of design_1_Vsp_core_0_0_xpm_cdc_sync_rst : entity is "SYNC_RST";
end design_1_Vsp_core_0_0_xpm_cdc_sync_rst;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_cdc_sync_rst is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST";
begin
  dest_rst <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => dest_clk,
      CE => '1',
      D => src_rst,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__4\ is
  port (
    src_rst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_rst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__4\ : entity is "1'b0";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__4\ : entity is 2;
  attribute INIT : string;
  attribute INIT of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__4\ : entity is "0";
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__4\ : entity is 1;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__4\ : entity is "xpm_cdc_sync_rst";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__4\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__4\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__4\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__4\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__4\ : entity is "SYNC_RST";
end \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__4\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST";
begin
  dest_rst <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => dest_clk,
      CE => '1',
      D => src_rst,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__5\ is
  port (
    src_rst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_rst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__5\ : entity is "1'b0";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__5\ : entity is 2;
  attribute INIT : string;
  attribute INIT of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__5\ : entity is "0";
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__5\ : entity is 1;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__5\ : entity is "xpm_cdc_sync_rst";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__5\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__5\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__5\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__5\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__5\ : entity is "SYNC_RST";
end \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__5\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__5\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST";
begin
  dest_rst <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => dest_clk,
      CE => '1',
      D => src_rst,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__6\ is
  port (
    src_rst : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_rst : out STD_LOGIC
  );
  attribute DEF_VAL : string;
  attribute DEF_VAL of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__6\ : entity is "1'b0";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__6\ : entity is 2;
  attribute INIT : string;
  attribute INIT of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__6\ : entity is "0";
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__6\ : entity is 1;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__6\ : entity is "xpm_cdc_sync_rst";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__6\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__6\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__6\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__6\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__6\ : entity is "SYNC_RST";
end \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__6\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_sync_rst__6\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST";
begin
  dest_rst <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => dest_clk,
      CE => '1',
      D => src_rst,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0\ is
  port (
    ram_full_i0 : out STD_LOGIC;
    leaving_empty0 : out STD_LOGIC;
    enb : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\ : in STD_LOGIC;
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rd_en : in STD_LOGIC;
    ram_empty_i : in STD_LOGIC;
    \count_value_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \^enb\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\ : STD_LOGIC;
  signal going_full1 : STD_LOGIC;
  signal \^leaving_empty0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[0]_i_1__1\ : label is "soft_lutpair310";
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair310";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair311";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair311";
  attribute SOFT_HLUTNM of \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2\ : label is "soft_lutpair312";
  attribute SOFT_HLUTNM of \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3\ : label is "soft_lutpair312";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  enb <= \^enb\;
  leaving_empty0 <= \^leaving_empty0\;
\count_value_i[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"10EF"
    )
        port map (
      I0 => rd_en,
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => \count_value_i_reg[0]_0\(1),
      I3 => \^q\(0),
      O => \count_value_i[0]_i_1__1_n_0\
    );
\count_value_i[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02FFFD00"
    )
        port map (
      I0 => \count_value_i_reg[0]_0\(1),
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => rd_en,
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => \count_value_i[1]_i_1__1_n_0\
    );
\count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__1_n_0\
    );
\count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__1_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^enb\,
      D => \count_value_i[0]_i_1__1_n_0\,
      Q => \^q\(0),
      R => \count_value_i_reg[3]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^enb\,
      D => \count_value_i[1]_i_1__1_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[3]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^enb\,
      D => \count_value_i[2]_i_1__1_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[3]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^enb\,
      D => \count_value_i[3]_i_1__1_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[3]_0\(0)
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FFF0088"
    )
        port map (
      I0 => E(0),
      I1 => going_full1,
      I2 => \^leaving_empty0\,
      I3 => \^enb\,
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\,
      O => ram_full_i0
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(3),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\,
      O => going_full1
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(3),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\,
      O => \^leaving_empty0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(0),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(0),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\
    );
\gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FD"
    )
        port map (
      I0 => \count_value_i_reg[0]_0\(1),
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => rd_en,
      I3 => ram_empty_i,
      O => \^enb\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_133\ is
  port (
    ram_empty_i0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    enb : in STD_LOGIC;
    leaving_empty0 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    ram_empty_i : in STD_LOGIC;
    \gen_pntr_flags_cc.ram_empty_i_reg\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_133\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_133\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_133\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\ : STD_LOGIC;
  signal going_empty1 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair315";
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1\ : label is "soft_lutpair315";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair314";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair314";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
\count_value_i[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1_n_0\
    );
\count_value_i[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1_n_0\
    );
\count_value_i[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1_n_0\
    );
\count_value_i[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1_n_0\,
      Q => \^q\(0),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[0]_0\(0)
    );
\gen_pntr_flags_cc.ram_empty_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FFF0088"
    )
        port map (
      I0 => enb,
      I1 => going_empty1,
      I2 => leaving_empty0,
      I3 => E(0),
      I4 => ram_empty_i,
      O => ram_empty_i0
    );
\gen_pntr_flags_cc.ram_empty_i_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ram_empty_i_reg\(3),
      I2 => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\,
      O => going_empty1
    );
\gen_pntr_flags_cc.ram_empty_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ram_empty_i_reg\(0),
      I2 => \gen_pntr_flags_cc.ram_empty_i_reg\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ram_empty_i_reg\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_136\ is
  port (
    ram_full_i0 : out STD_LOGIC;
    leaving_empty0 : out STD_LOGIC;
    enb : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\ : in STD_LOGIC;
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rd_en : in STD_LOGIC;
    ram_empty_i : in STD_LOGIC;
    \count_value_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_136\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_136\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_136\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \^enb\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\ : STD_LOGIC;
  signal going_full1 : STD_LOGIC;
  signal \^leaving_empty0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[0]_i_1__1\ : label is "soft_lutpair295";
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair295";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair296";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair296";
  attribute SOFT_HLUTNM of \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2\ : label is "soft_lutpair297";
  attribute SOFT_HLUTNM of \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3\ : label is "soft_lutpair297";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  enb <= \^enb\;
  leaving_empty0 <= \^leaving_empty0\;
\count_value_i[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"10EF"
    )
        port map (
      I0 => rd_en,
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => \count_value_i_reg[0]_0\(1),
      I3 => \^q\(0),
      O => \count_value_i[0]_i_1__1_n_0\
    );
\count_value_i[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02FFFD00"
    )
        port map (
      I0 => \count_value_i_reg[0]_0\(1),
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => rd_en,
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => \count_value_i[1]_i_1__1_n_0\
    );
\count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__1_n_0\
    );
\count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__1_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^enb\,
      D => \count_value_i[0]_i_1__1_n_0\,
      Q => \^q\(0),
      R => \count_value_i_reg[3]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^enb\,
      D => \count_value_i[1]_i_1__1_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[3]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^enb\,
      D => \count_value_i[2]_i_1__1_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[3]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^enb\,
      D => \count_value_i[3]_i_1__1_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[3]_0\(0)
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FFF0088"
    )
        port map (
      I0 => E(0),
      I1 => going_full1,
      I2 => \^leaving_empty0\,
      I3 => \^enb\,
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\,
      O => ram_full_i0
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(3),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\,
      O => going_full1
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(3),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\,
      O => \^leaving_empty0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(0),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(0),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\
    );
\gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FD"
    )
        port map (
      I0 => \count_value_i_reg[0]_0\(1),
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => rd_en,
      I3 => ram_empty_i,
      O => \^enb\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_139\ is
  port (
    ram_empty_i0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    enb : in STD_LOGIC;
    leaving_empty0 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    ram_empty_i : in STD_LOGIC;
    \gen_pntr_flags_cc.ram_empty_i_reg\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_139\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_139\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_139\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\ : STD_LOGIC;
  signal going_empty1 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair300";
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1\ : label is "soft_lutpair300";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair299";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair299";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
\count_value_i[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1_n_0\
    );
\count_value_i[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1_n_0\
    );
\count_value_i[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1_n_0\
    );
\count_value_i[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1_n_0\,
      Q => \^q\(0),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[0]_0\(0)
    );
\gen_pntr_flags_cc.ram_empty_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FFF0088"
    )
        port map (
      I0 => enb,
      I1 => going_empty1,
      I2 => leaving_empty0,
      I3 => E(0),
      I4 => ram_empty_i,
      O => ram_empty_i0
    );
\gen_pntr_flags_cc.ram_empty_i_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ram_empty_i_reg\(3),
      I2 => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\,
      O => going_empty1
    );
\gen_pntr_flags_cc.ram_empty_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ram_empty_i_reg\(0),
      I2 => \gen_pntr_flags_cc.ram_empty_i_reg\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ram_empty_i_reg\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_142\ is
  port (
    ram_full_i0 : out STD_LOGIC;
    leaving_empty0 : out STD_LOGIC;
    enb : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\ : in STD_LOGIC;
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rd_en : in STD_LOGIC;
    ram_empty_i : in STD_LOGIC;
    \count_value_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_142\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_142\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_142\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \^enb\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\ : STD_LOGIC;
  signal going_full1 : STD_LOGIC;
  signal \^leaving_empty0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[0]_i_1__1\ : label is "soft_lutpair285";
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair285";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair286";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair286";
  attribute SOFT_HLUTNM of \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2\ : label is "soft_lutpair287";
  attribute SOFT_HLUTNM of \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3\ : label is "soft_lutpair287";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  enb <= \^enb\;
  leaving_empty0 <= \^leaving_empty0\;
\count_value_i[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"10EF"
    )
        port map (
      I0 => rd_en,
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => \count_value_i_reg[0]_0\(1),
      I3 => \^q\(0),
      O => \count_value_i[0]_i_1__1_n_0\
    );
\count_value_i[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02FFFD00"
    )
        port map (
      I0 => \count_value_i_reg[0]_0\(1),
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => rd_en,
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => \count_value_i[1]_i_1__1_n_0\
    );
\count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__1_n_0\
    );
\count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__1_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^enb\,
      D => \count_value_i[0]_i_1__1_n_0\,
      Q => \^q\(0),
      R => \count_value_i_reg[3]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^enb\,
      D => \count_value_i[1]_i_1__1_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[3]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^enb\,
      D => \count_value_i[2]_i_1__1_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[3]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^enb\,
      D => \count_value_i[3]_i_1__1_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[3]_0\(0)
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FFF0088"
    )
        port map (
      I0 => E(0),
      I1 => going_full1,
      I2 => \^leaving_empty0\,
      I3 => \^enb\,
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\,
      O => ram_full_i0
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(3),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\,
      O => going_full1
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(3),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\,
      O => \^leaving_empty0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(0),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(0),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\
    );
\gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FD"
    )
        port map (
      I0 => \count_value_i_reg[0]_0\(1),
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => rd_en,
      I3 => ram_empty_i,
      O => \^enb\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_145\ is
  port (
    ram_empty_i0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    enb : in STD_LOGIC;
    leaving_empty0 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    ram_empty_i : in STD_LOGIC;
    \gen_pntr_flags_cc.ram_empty_i_reg\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_145\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_145\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_145\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\ : STD_LOGIC;
  signal going_empty1 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair290";
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1\ : label is "soft_lutpair290";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair289";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair289";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
\count_value_i[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1_n_0\
    );
\count_value_i[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1_n_0\
    );
\count_value_i[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1_n_0\
    );
\count_value_i[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1_n_0\,
      Q => \^q\(0),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[0]_0\(0)
    );
\gen_pntr_flags_cc.ram_empty_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FFF0088"
    )
        port map (
      I0 => enb,
      I1 => going_empty1,
      I2 => leaving_empty0,
      I3 => E(0),
      I4 => ram_empty_i,
      O => ram_empty_i0
    );
\gen_pntr_flags_cc.ram_empty_i_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ram_empty_i_reg\(3),
      I2 => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\,
      O => going_empty1
    );
\gen_pntr_flags_cc.ram_empty_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ram_empty_i_reg\(0),
      I2 => \gen_pntr_flags_cc.ram_empty_i_reg\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ram_empty_i_reg\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_148\ is
  port (
    ram_full_i0 : out STD_LOGIC;
    leaving_empty0 : out STD_LOGIC;
    enb : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\ : in STD_LOGIC;
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rd_en : in STD_LOGIC;
    ram_empty_i : in STD_LOGIC;
    \count_value_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_148\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_148\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_148\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \^enb\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\ : STD_LOGIC;
  signal going_full1 : STD_LOGIC;
  signal \^leaving_empty0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[0]_i_1__1\ : label is "soft_lutpair275";
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair275";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair276";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair276";
  attribute SOFT_HLUTNM of \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2\ : label is "soft_lutpair277";
  attribute SOFT_HLUTNM of \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3\ : label is "soft_lutpair277";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  enb <= \^enb\;
  leaving_empty0 <= \^leaving_empty0\;
\count_value_i[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"10EF"
    )
        port map (
      I0 => rd_en,
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => \count_value_i_reg[0]_0\(1),
      I3 => \^q\(0),
      O => \count_value_i[0]_i_1__1_n_0\
    );
\count_value_i[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02FFFD00"
    )
        port map (
      I0 => \count_value_i_reg[0]_0\(1),
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => rd_en,
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => \count_value_i[1]_i_1__1_n_0\
    );
\count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__1_n_0\
    );
\count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__1_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => \^enb\,
      D => \count_value_i[0]_i_1__1_n_0\,
      Q => \^q\(0),
      R => \count_value_i_reg[3]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => \^enb\,
      D => \count_value_i[1]_i_1__1_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[3]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => \^enb\,
      D => \count_value_i[2]_i_1__1_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[3]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => \^enb\,
      D => \count_value_i[3]_i_1__1_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[3]_0\(0)
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FFF0088"
    )
        port map (
      I0 => E(0),
      I1 => going_full1,
      I2 => \^leaving_empty0\,
      I3 => \^enb\,
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\,
      O => ram_full_i0
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(3),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\,
      O => going_full1
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(3),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\,
      O => \^leaving_empty0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(0),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(0),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\
    );
\gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FD"
    )
        port map (
      I0 => \count_value_i_reg[0]_0\(1),
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => rd_en,
      I3 => ram_empty_i,
      O => \^enb\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_151\ is
  port (
    ram_empty_i0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    enb : in STD_LOGIC;
    leaving_empty0 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    ram_empty_i : in STD_LOGIC;
    \gen_pntr_flags_cc.ram_empty_i_reg\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_151\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_151\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_151\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\ : STD_LOGIC;
  signal going_empty1 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair280";
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1\ : label is "soft_lutpair280";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair279";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair279";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
\count_value_i[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1_n_0\
    );
\count_value_i[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1_n_0\
    );
\count_value_i[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1_n_0\
    );
\count_value_i[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1_n_0\,
      Q => \^q\(0),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[0]_0\(0)
    );
\gen_pntr_flags_cc.ram_empty_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FFF0088"
    )
        port map (
      I0 => enb,
      I1 => going_empty1,
      I2 => leaving_empty0,
      I3 => E(0),
      I4 => ram_empty_i,
      O => ram_empty_i0
    );
\gen_pntr_flags_cc.ram_empty_i_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ram_empty_i_reg\(3),
      I2 => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\,
      O => going_empty1
    );
\gen_pntr_flags_cc.ram_empty_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ram_empty_i_reg\(0),
      I2 => \gen_pntr_flags_cc.ram_empty_i_reg\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ram_empty_i_reg\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rd_en : in STD_LOGIC;
    \count_value_i_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__2\ : label is "soft_lutpair313";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair313";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
\count_value_i[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"10EF"
    )
        port map (
      I0 => rd_en,
      I1 => \count_value_i_reg[1]_0\(0),
      I2 => \count_value_i_reg[1]_0\(1),
      I3 => \^q\(0),
      O => \count_value_i[0]_i_1__2_n_0\
    );
\count_value_i[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02FFFD00"
    )
        port map (
      I0 => \count_value_i_reg[1]_0\(1),
      I1 => \count_value_i_reg[1]_0\(0),
      I2 => rd_en,
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => \count_value_i[1]_i_1__2_n_0\
    );
\count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__2_n_0\
    );
\count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__2_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1__2_n_0\,
      Q => \^q\(0),
      S => \count_value_i_reg[1]_1\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1__2_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[1]_1\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1__2_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[1]_1\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1__2_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[1]_1\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_134\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_134\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_134\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_134\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair316";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair316";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
\count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1__0_n_0\
    );
\count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1__0_n_0\
    );
\count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__0_n_0\
    );
\count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__0_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1__0_n_0\,
      Q => \^q\(0),
      S => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1__0_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1__0_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1__0_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[1]_0\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_137\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rd_en : in STD_LOGIC;
    \count_value_i_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_137\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_137\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_137\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__2\ : label is "soft_lutpair298";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair298";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
\count_value_i[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"10EF"
    )
        port map (
      I0 => rd_en,
      I1 => \count_value_i_reg[1]_0\(0),
      I2 => \count_value_i_reg[1]_0\(1),
      I3 => \^q\(0),
      O => \count_value_i[0]_i_1__2_n_0\
    );
\count_value_i[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02FFFD00"
    )
        port map (
      I0 => \count_value_i_reg[1]_0\(1),
      I1 => \count_value_i_reg[1]_0\(0),
      I2 => rd_en,
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => \count_value_i[1]_i_1__2_n_0\
    );
\count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__2_n_0\
    );
\count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__2_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1__2_n_0\,
      Q => \^q\(0),
      S => \count_value_i_reg[1]_1\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1__2_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[1]_1\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1__2_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[1]_1\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1__2_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[1]_1\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_140\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_140\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_140\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_140\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair301";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair301";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
\count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1__0_n_0\
    );
\count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1__0_n_0\
    );
\count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__0_n_0\
    );
\count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__0_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1__0_n_0\,
      Q => \^q\(0),
      S => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1__0_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1__0_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1__0_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[1]_0\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_143\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rd_en : in STD_LOGIC;
    \count_value_i_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_143\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_143\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_143\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__2\ : label is "soft_lutpair288";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair288";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
\count_value_i[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"10EF"
    )
        port map (
      I0 => rd_en,
      I1 => \count_value_i_reg[1]_0\(0),
      I2 => \count_value_i_reg[1]_0\(1),
      I3 => \^q\(0),
      O => \count_value_i[0]_i_1__2_n_0\
    );
\count_value_i[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02FFFD00"
    )
        port map (
      I0 => \count_value_i_reg[1]_0\(1),
      I1 => \count_value_i_reg[1]_0\(0),
      I2 => rd_en,
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => \count_value_i[1]_i_1__2_n_0\
    );
\count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__2_n_0\
    );
\count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__2_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1__2_n_0\,
      Q => \^q\(0),
      S => \count_value_i_reg[1]_1\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1__2_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[1]_1\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1__2_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[1]_1\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1__2_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[1]_1\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_146\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_146\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_146\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_146\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair291";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair291";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
\count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1__0_n_0\
    );
\count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1__0_n_0\
    );
\count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__0_n_0\
    );
\count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__0_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1__0_n_0\,
      Q => \^q\(0),
      S => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1__0_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1__0_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1__0_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[1]_0\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_149\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rd_en : in STD_LOGIC;
    \count_value_i_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_149\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_149\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_149\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__2\ : label is "soft_lutpair278";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair278";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
\count_value_i[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"10EF"
    )
        port map (
      I0 => rd_en,
      I1 => \count_value_i_reg[1]_0\(0),
      I2 => \count_value_i_reg[1]_0\(1),
      I3 => \^q\(0),
      O => \count_value_i[0]_i_1__2_n_0\
    );
\count_value_i[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02FFFD00"
    )
        port map (
      I0 => \count_value_i_reg[1]_0\(1),
      I1 => \count_value_i_reg[1]_0\(0),
      I2 => rd_en,
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => \count_value_i[1]_i_1__2_n_0\
    );
\count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__2_n_0\
    );
\count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__2_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1__2_n_0\,
      Q => \^q\(0),
      S => \count_value_i_reg[1]_1\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1__2_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[1]_1\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1__2_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[1]_1\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1__2_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[1]_1\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_152\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_152\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_152\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_152\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair281";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair281";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
\count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1__0_n_0\
    );
\count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1__0_n_0\
    );
\count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__0_n_0\
    );
\count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__0_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1__0_n_0\,
      Q => \^q\(0),
      S => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1__0_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1__0_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1__0_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[1]_0\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized4\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 10 downto 0 );
    ram_wr_en_pf : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    \count_value_i_reg[5]_0\ : in STD_LOGIC;
    \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_d1 : in STD_LOGIC;
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized4\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized4\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[10]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[10]_i_2_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[5]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[6]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[6]_i_2_n_0\ : STD_LOGIC;
  signal \count_value_i[7]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[8]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[9]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[9]_i_2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[0]_i_1__1\ : label is "soft_lutpair335";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair335";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair334";
  attribute SOFT_HLUTNM of \count_value_i[4]_i_1__1\ : label is "soft_lutpair334";
  attribute SOFT_HLUTNM of \count_value_i[7]_i_1\ : label is "soft_lutpair333";
  attribute SOFT_HLUTNM of \count_value_i[8]_i_1\ : label is "soft_lutpair333";
begin
  Q(10 downto 0) <= \^q\(10 downto 0);
\count_value_i[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1__1_n_0\
    );
\count_value_i[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(8),
      I1 => \count_value_i[10]_i_2_n_0\,
      I2 => \^q\(7),
      I3 => \^q\(9),
      I4 => \^q\(10),
      O => \count_value_i[10]_i_1_n_0\
    );
\count_value_i[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(6),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \count_value_i[6]_i_2_n_0\,
      I4 => \^q\(3),
      I5 => \^q\(5),
      O => \count_value_i[10]_i_2_n_0\
    );
\count_value_i[1]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1__1_n_0\
    );
\count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__1_n_0\
    );
\count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__1_n_0\
    );
\count_value_i[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \count_value_i[4]_i_1__1_n_0\
    );
\count_value_i[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \count_value_i[6]_i_2_n_0\,
      I2 => \^q\(2),
      I3 => \^q\(4),
      I4 => \^q\(5),
      O => \count_value_i[5]_i_1_n_0\
    );
\count_value_i[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \count_value_i[6]_i_2_n_0\,
      I3 => \^q\(3),
      I4 => \^q\(5),
      I5 => \^q\(6),
      O => \count_value_i[6]_i_1_n_0\
    );
\count_value_i[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => wr_en,
      I2 => \count_value_i_reg[5]_0\,
      I3 => \count_value_i_reg[0]_0\(0),
      I4 => rst_d1,
      I5 => \^q\(0),
      O => \count_value_i[6]_i_2_n_0\
    );
\count_value_i[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(5),
      I1 => \count_value_i[9]_i_2_n_0\,
      I2 => \^q\(6),
      I3 => \^q\(7),
      O => \count_value_i[7]_i_1_n_0\
    );
\count_value_i[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(6),
      I1 => \count_value_i[9]_i_2_n_0\,
      I2 => \^q\(5),
      I3 => \^q\(7),
      I4 => \^q\(8),
      O => \count_value_i[8]_i_1_n_0\
    );
\count_value_i[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(7),
      I1 => \^q\(5),
      I2 => \count_value_i[9]_i_2_n_0\,
      I3 => \^q\(6),
      I4 => \^q\(8),
      I5 => \^q\(9),
      O => \count_value_i[9]_i_1_n_0\
    );
\count_value_i[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => ram_wr_en_pf,
      I4 => \^q\(1),
      I5 => \^q\(3),
      O => \count_value_i[9]_i_2_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[0]_i_1__1_n_0\,
      Q => \^q\(0),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[10]_i_1_n_0\,
      Q => \^q\(10),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[1]_i_1__1_n_0\,
      Q => \^q\(1),
      S => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[2]_i_1__1_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[3]_i_1__1_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[4]_i_1__1_n_0\,
      Q => \^q\(4),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[5]_i_1_n_0\,
      Q => \^q\(5),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[6]_i_1_n_0\,
      Q => \^q\(6),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[7]_i_1_n_0\,
      Q => \^q\(7),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[8]_i_1_n_0\,
      Q => \^q\(8),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[9]_i_1_n_0\,
      Q => \^q\(9),
      R => \count_value_i_reg[0]_0\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized5\ is
  port (
    \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg\ : out STD_LOGIC;
    ram_full_i0 : out STD_LOGIC;
    leaving_empty0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 10 downto 0 );
    almost_full : in STD_LOGIC;
    \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_0\ : in STD_LOGIC;
    rst : in STD_LOGIC;
    \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_1\ : in STD_LOGIC;
    \count_value_i_reg[0]_0\ : in STD_LOGIC;
    ram_wr_en_pf : in STD_LOGIC;
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\ : in STD_LOGIC;
    \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rd_en : in STD_LOGIC;
    ram_empty_i : in STD_LOGIC;
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \count_value_i_reg[10]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized5\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized5\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized5\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[10]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[10]_i_2__2_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[5]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[6]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[6]_i_2__2_n_0\ : STD_LOGIC;
  signal \count_value_i[7]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[8]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[9]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[9]_i_2__2_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_7_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_8_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_10_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_11_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_6_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_7_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_8_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_9_n_0\ : STD_LOGIC;
  signal going_afull : STD_LOGIC;
  signal going_full1 : STD_LOGIC;
  signal \^leaving_empty0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[0]_i_1__2\ : label is "soft_lutpair324";
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1__2\ : label is "soft_lutpair324";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair323";
  attribute SOFT_HLUTNM of \count_value_i[4]_i_1__2\ : label is "soft_lutpair323";
  attribute SOFT_HLUTNM of \count_value_i[7]_i_1__2\ : label is "soft_lutpair322";
  attribute SOFT_HLUTNM of \count_value_i[8]_i_1__2\ : label is "soft_lutpair322";
begin
  Q(10 downto 0) <= \^q\(10 downto 0);
  leaving_empty0 <= \^leaving_empty0\;
\count_value_i[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"10EF"
    )
        port map (
      I0 => rd_en,
      I1 => \count_value_i_reg[1]_0\(0),
      I2 => \count_value_i_reg[1]_0\(1),
      I3 => \^q\(0),
      O => \count_value_i[0]_i_1__2_n_0\
    );
\count_value_i[10]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(8),
      I1 => \count_value_i[10]_i_2__2_n_0\,
      I2 => \^q\(7),
      I3 => \^q\(9),
      I4 => \^q\(10),
      O => \count_value_i[10]_i_1__2_n_0\
    );
\count_value_i[10]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(6),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \count_value_i[6]_i_2__2_n_0\,
      I4 => \^q\(3),
      I5 => \^q\(5),
      O => \count_value_i[10]_i_2__2_n_0\
    );
\count_value_i[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02FFFD00"
    )
        port map (
      I0 => \count_value_i_reg[1]_0\(1),
      I1 => \count_value_i_reg[1]_0\(0),
      I2 => rd_en,
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => \count_value_i[1]_i_1__2_n_0\
    );
\count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__2_n_0\
    );
\count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__2_n_0\
    );
\count_value_i[4]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \count_value_i[4]_i_1__2_n_0\
    );
\count_value_i[5]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \count_value_i[6]_i_2__2_n_0\,
      I2 => \^q\(2),
      I3 => \^q\(4),
      I4 => \^q\(5),
      O => \count_value_i[5]_i_1__2_n_0\
    );
\count_value_i[6]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \count_value_i[6]_i_2__2_n_0\,
      I3 => \^q\(3),
      I4 => \^q\(5),
      I5 => \^q\(6),
      O => \count_value_i[6]_i_1__2_n_0\
    );
\count_value_i[6]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AAA200000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \count_value_i_reg[1]_0\(1),
      I2 => \count_value_i_reg[1]_0\(0),
      I3 => rd_en,
      I4 => ram_empty_i,
      I5 => \^q\(0),
      O => \count_value_i[6]_i_2__2_n_0\
    );
\count_value_i[7]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(5),
      I1 => \count_value_i[9]_i_2__2_n_0\,
      I2 => \^q\(6),
      I3 => \^q\(7),
      O => \count_value_i[7]_i_1__2_n_0\
    );
\count_value_i[8]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(6),
      I1 => \count_value_i[9]_i_2__2_n_0\,
      I2 => \^q\(5),
      I3 => \^q\(7),
      I4 => \^q\(8),
      O => \count_value_i[8]_i_1__2_n_0\
    );
\count_value_i[9]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(7),
      I1 => \^q\(5),
      I2 => \count_value_i[9]_i_2__2_n_0\,
      I3 => \^q\(6),
      I4 => \^q\(8),
      I5 => \^q\(9),
      O => \count_value_i[9]_i_1__2_n_0\
    );
\count_value_i[9]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \count_value_i_reg[0]_0\,
      I4 => \^q\(1),
      I5 => \^q\(3),
      O => \count_value_i[9]_i_2__2_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \count_value_i_reg[0]_0\,
      D => \count_value_i[0]_i_1__2_n_0\,
      Q => \^q\(0),
      R => \count_value_i_reg[10]_0\(0)
    );
\count_value_i_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \count_value_i_reg[0]_0\,
      D => \count_value_i[10]_i_1__2_n_0\,
      Q => \^q\(10),
      R => \count_value_i_reg[10]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \count_value_i_reg[0]_0\,
      D => \count_value_i[1]_i_1__2_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[10]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \count_value_i_reg[0]_0\,
      D => \count_value_i[2]_i_1__2_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[10]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \count_value_i_reg[0]_0\,
      D => \count_value_i[3]_i_1__2_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[10]_0\(0)
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \count_value_i_reg[0]_0\,
      D => \count_value_i[4]_i_1__2_n_0\,
      Q => \^q\(4),
      R => \count_value_i_reg[10]_0\(0)
    );
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \count_value_i_reg[0]_0\,
      D => \count_value_i[5]_i_1__2_n_0\,
      Q => \^q\(5),
      R => \count_value_i_reg[10]_0\(0)
    );
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \count_value_i_reg[0]_0\,
      D => \count_value_i[6]_i_1__2_n_0\,
      Q => \^q\(6),
      R => \count_value_i_reg[10]_0\(0)
    );
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \count_value_i_reg[0]_0\,
      D => \count_value_i[7]_i_1__2_n_0\,
      Q => \^q\(7),
      R => \count_value_i_reg[10]_0\(0)
    );
\count_value_i_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \count_value_i_reg[0]_0\,
      D => \count_value_i[8]_i_1__2_n_0\,
      Q => \^q\(8),
      R => \count_value_i_reg[10]_0\(0)
    );
\count_value_i_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \count_value_i_reg[0]_0\,
      D => \count_value_i[9]_i_1__2_n_0\,
      Q => \^q\(9),
      R => \count_value_i_reg[10]_0\(0)
    );
\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAFF2A"
    )
        port map (
      I0 => almost_full,
      I1 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_0\,
      I2 => going_full1,
      I3 => going_afull,
      I4 => rst,
      I5 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_1\,
      O => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg\
    );
\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000400000000000"
    )
        port map (
      I0 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0\,
      I1 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0\,
      I2 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_7_n_0\,
      I3 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_8_n_0\,
      I4 => \count_value_i_reg[0]_0\,
      I5 => ram_wr_en_pf,
      O => going_afull
    );
\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => \^q\(9),
      I1 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(9),
      I2 => \^q\(10),
      I3 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(10),
      O => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_5_n_0\
    );
\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(3),
      I2 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(5),
      I3 => \^q\(5),
      I4 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(4),
      I5 => \^q\(4),
      O => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_6_n_0\
    );
\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(0),
      I2 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_7_n_0\
    );
\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(6),
      I1 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(6),
      I2 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(8),
      I3 => \^q\(8),
      I4 => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(7),
      I5 => \^q\(7),
      O => \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_8_n_0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FFF0088"
    )
        port map (
      I0 => ram_wr_en_pf,
      I1 => going_full1,
      I2 => \^leaving_empty0\,
      I3 => \count_value_i_reg[0]_0\,
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\,
      O => ram_full_i0
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3_0\(3),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3_0\(5),
      I3 => \^q\(5),
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3_0\(4),
      I5 => \^q\(4),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_10_n_0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => \^q\(9),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3_0\(9),
      I2 => \^q\(10),
      I3 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3_0\(10),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_11_n_0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\,
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\,
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_6_n_0\,
      I3 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_7_n_0\,
      O => going_full1
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_8_n_0\,
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_9_n_0\,
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_10_n_0\,
      I3 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_11_n_0\,
      O => \^leaving_empty0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(6),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(6),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(8),
      I3 => \^q\(8),
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(7),
      I5 => \^q\(7),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_4_n_0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(0),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_5_n_0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(3),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(5),
      I3 => \^q\(5),
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(4),
      I5 => \^q\(4),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_6_n_0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => \^q\(9),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(9),
      I2 => \^q\(10),
      I3 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(10),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_7_n_0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(6),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3_0\(6),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3_0\(8),
      I3 => \^q\(8),
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3_0\(7),
      I5 => \^q\(7),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_8_n_0\
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3_0\(0),
      I2 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3_0\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3_0\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_9_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized5_130\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 10 downto 0 );
    ram_empty_i0 : out STD_LOGIC;
    ram_wr_en_pf : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    \count_value_i_reg[5]_0\ : in STD_LOGIC;
    \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_d1 : in STD_LOGIC;
    \gen_pntr_flags_cc.ram_empty_i_reg\ : in STD_LOGIC;
    leaving_empty0 : in STD_LOGIC;
    ram_empty_i : in STD_LOGIC;
    \gen_pntr_flags_cc.ram_empty_i_reg_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized5_130\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized5_130\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized5_130\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[10]_i_2__0_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[6]_i_2__0_n_0\ : STD_LOGIC;
  signal \count_value_i[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[9]_i_2__0_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ram_empty_i_i_2_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ram_empty_i_i_4_n_0\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ram_empty_i_i_5_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1\ : label is "soft_lutpair329";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair329";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair328";
  attribute SOFT_HLUTNM of \count_value_i[4]_i_1\ : label is "soft_lutpair328";
  attribute SOFT_HLUTNM of \count_value_i[7]_i_1__0\ : label is "soft_lutpair327";
  attribute SOFT_HLUTNM of \count_value_i[8]_i_1__0\ : label is "soft_lutpair327";
begin
  Q(10 downto 0) <= \^q\(10 downto 0);
\count_value_i[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1_n_0\
    );
\count_value_i[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(8),
      I1 => \count_value_i[10]_i_2__0_n_0\,
      I2 => \^q\(7),
      I3 => \^q\(9),
      I4 => \^q\(10),
      O => \count_value_i[10]_i_1__0_n_0\
    );
\count_value_i[10]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(6),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \count_value_i[6]_i_2__0_n_0\,
      I4 => \^q\(3),
      I5 => \^q\(5),
      O => \count_value_i[10]_i_2__0_n_0\
    );
\count_value_i[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1_n_0\
    );
\count_value_i[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1_n_0\
    );
\count_value_i[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1_n_0\
    );
\count_value_i[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \count_value_i[4]_i_1_n_0\
    );
\count_value_i[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \count_value_i[6]_i_2__0_n_0\,
      I2 => \^q\(2),
      I3 => \^q\(4),
      I4 => \^q\(5),
      O => \count_value_i[5]_i_1__0_n_0\
    );
\count_value_i[6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \count_value_i[6]_i_2__0_n_0\,
      I3 => \^q\(3),
      I4 => \^q\(5),
      I5 => \^q\(6),
      O => \count_value_i[6]_i_1__0_n_0\
    );
\count_value_i[6]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => wr_en,
      I2 => \count_value_i_reg[5]_0\,
      I3 => \count_value_i_reg[0]_0\(0),
      I4 => rst_d1,
      I5 => \^q\(0),
      O => \count_value_i[6]_i_2__0_n_0\
    );
\count_value_i[7]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(5),
      I1 => \count_value_i[9]_i_2__0_n_0\,
      I2 => \^q\(6),
      I3 => \^q\(7),
      O => \count_value_i[7]_i_1__0_n_0\
    );
\count_value_i[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(6),
      I1 => \count_value_i[9]_i_2__0_n_0\,
      I2 => \^q\(5),
      I3 => \^q\(7),
      I4 => \^q\(8),
      O => \count_value_i[8]_i_1__0_n_0\
    );
\count_value_i[9]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(7),
      I1 => \^q\(5),
      I2 => \count_value_i[9]_i_2__0_n_0\,
      I3 => \^q\(6),
      I4 => \^q\(8),
      I5 => \^q\(9),
      O => \count_value_i[9]_i_1__0_n_0\
    );
\count_value_i[9]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => ram_wr_en_pf,
      I4 => \^q\(1),
      I5 => \^q\(3),
      O => \count_value_i[9]_i_2__0_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[0]_i_1_n_0\,
      Q => \^q\(0),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[10]_i_1__0_n_0\,
      Q => \^q\(10),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[1]_i_1_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[2]_i_1_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[3]_i_1_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[4]_i_1_n_0\,
      Q => \^q\(4),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[5]_i_1__0_n_0\,
      Q => \^q\(5),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[6]_i_1__0_n_0\,
      Q => \^q\(6),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[7]_i_1__0_n_0\,
      Q => \^q\(7),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[8]_i_1__0_n_0\,
      Q => \^q\(8),
      R => \count_value_i_reg[0]_0\(0)
    );
\count_value_i_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[9]_i_1__0_n_0\,
      Q => \^q\(9),
      R => \count_value_i_reg[0]_0\(0)
    );
\gen_pntr_flags_cc.ram_empty_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FFFFFF00008080"
    )
        port map (
      I0 => \gen_pntr_flags_cc.ram_empty_i_reg\,
      I1 => \gen_pntr_flags_cc.ram_empty_i_i_2_n_0\,
      I2 => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\,
      I3 => leaving_empty0,
      I4 => ram_wr_en_pf,
      I5 => ram_empty_i,
      O => ram_empty_i0
    );
\gen_pntr_flags_cc.ram_empty_i_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(6),
      I1 => \gen_pntr_flags_cc.ram_empty_i_reg_0\(6),
      I2 => \gen_pntr_flags_cc.ram_empty_i_reg_0\(8),
      I3 => \^q\(8),
      I4 => \gen_pntr_flags_cc.ram_empty_i_reg_0\(7),
      I5 => \^q\(7),
      O => \gen_pntr_flags_cc.ram_empty_i_i_2_n_0\
    );
\gen_pntr_flags_cc.ram_empty_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000000000"
    )
        port map (
      I0 => \gen_pntr_flags_cc.ram_empty_i_reg_0\(10),
      I1 => \^q\(10),
      I2 => \gen_pntr_flags_cc.ram_empty_i_reg_0\(9),
      I3 => \^q\(9),
      I4 => \gen_pntr_flags_cc.ram_empty_i_i_4_n_0\,
      I5 => \gen_pntr_flags_cc.ram_empty_i_i_5_n_0\,
      O => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\
    );
\gen_pntr_flags_cc.ram_empty_i_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pntr_flags_cc.ram_empty_i_reg_0\(3),
      I2 => \gen_pntr_flags_cc.ram_empty_i_reg_0\(5),
      I3 => \^q\(5),
      I4 => \gen_pntr_flags_cc.ram_empty_i_reg_0\(4),
      I5 => \^q\(4),
      O => \gen_pntr_flags_cc.ram_empty_i_i_4_n_0\
    );
\gen_pntr_flags_cc.ram_empty_i_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pntr_flags_cc.ram_empty_i_reg_0\(0),
      I2 => \gen_pntr_flags_cc.ram_empty_i_reg_0\(2),
      I3 => \^q\(2),
      I4 => \gen_pntr_flags_cc.ram_empty_i_reg_0\(1),
      I5 => \^q\(1),
      O => \gen_pntr_flags_cc.ram_empty_i_i_5_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized6\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 10 downto 0 );
    \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : out STD_LOGIC;
    \count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rd_en : in STD_LOGIC;
    ram_empty_i : in STD_LOGIC;
    \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized6\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized6\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized6\ is
  signal \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \count_value_i[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[10]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[10]_i_2__3_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[5]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[6]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[6]_i_2__3_n_0\ : STD_LOGIC;
  signal \count_value_i[7]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[8]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[9]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[9]_i_2__3_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__3\ : label is "soft_lutpair326";
  attribute SOFT_HLUTNM of \count_value_i[4]_i_1__3\ : label is "soft_lutpair326";
  attribute SOFT_HLUTNM of \count_value_i[7]_i_1__3\ : label is "soft_lutpair325";
  attribute SOFT_HLUTNM of \count_value_i[8]_i_1__3\ : label is "soft_lutpair325";
begin
  \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ <= \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\;
  Q(10 downto 0) <= \^q\(10 downto 0);
\count_value_i[0]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"10EF"
    )
        port map (
      I0 => rd_en,
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => \count_value_i_reg[0]_0\(1),
      I3 => \^q\(0),
      O => \count_value_i[0]_i_1__3_n_0\
    );
\count_value_i[10]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(8),
      I1 => \count_value_i[10]_i_2__3_n_0\,
      I2 => \^q\(7),
      I3 => \^q\(9),
      I4 => \^q\(10),
      O => \count_value_i[10]_i_1__3_n_0\
    );
\count_value_i[10]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(6),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \count_value_i[6]_i_2__3_n_0\,
      I4 => \^q\(3),
      I5 => \^q\(5),
      O => \count_value_i[10]_i_2__3_n_0\
    );
\count_value_i[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02FFFD00"
    )
        port map (
      I0 => \count_value_i_reg[0]_0\(1),
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => rd_en,
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => \count_value_i[1]_i_1__3_n_0\
    );
\count_value_i[2]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__3_n_0\
    );
\count_value_i[3]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__3_n_0\
    );
\count_value_i[4]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \count_value_i[4]_i_1__3_n_0\
    );
\count_value_i[5]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \count_value_i[6]_i_2__3_n_0\,
      I2 => \^q\(2),
      I3 => \^q\(4),
      I4 => \^q\(5),
      O => \count_value_i[5]_i_1__3_n_0\
    );
\count_value_i[6]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \count_value_i[6]_i_2__3_n_0\,
      I3 => \^q\(3),
      I4 => \^q\(5),
      I5 => \^q\(6),
      O => \count_value_i[6]_i_1__3_n_0\
    );
\count_value_i[6]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AAA200000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \count_value_i_reg[0]_0\(1),
      I2 => \count_value_i_reg[0]_0\(0),
      I3 => rd_en,
      I4 => ram_empty_i,
      I5 => \^q\(0),
      O => \count_value_i[6]_i_2__3_n_0\
    );
\count_value_i[7]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(5),
      I1 => \count_value_i[9]_i_2__3_n_0\,
      I2 => \^q\(6),
      I3 => \^q\(7),
      O => \count_value_i[7]_i_1__3_n_0\
    );
\count_value_i[8]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(6),
      I1 => \count_value_i[9]_i_2__3_n_0\,
      I2 => \^q\(5),
      I3 => \^q\(7),
      I4 => \^q\(8),
      O => \count_value_i[8]_i_1__3_n_0\
    );
\count_value_i[9]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(7),
      I1 => \^q\(5),
      I2 => \count_value_i[9]_i_2__3_n_0\,
      I3 => \^q\(6),
      I4 => \^q\(8),
      I5 => \^q\(9),
      O => \count_value_i[9]_i_1__3_n_0\
    );
\count_value_i[9]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
      I4 => \^q\(1),
      I5 => \^q\(3),
      O => \count_value_i[9]_i_2__3_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
      D => \count_value_i[0]_i_1__3_n_0\,
      Q => \^q\(0),
      S => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
      D => \count_value_i[10]_i_1__3_n_0\,
      Q => \^q\(10),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
      D => \count_value_i[1]_i_1__3_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
      D => \count_value_i[2]_i_1__3_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
      D => \count_value_i[3]_i_1__3_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
      D => \count_value_i[4]_i_1__3_n_0\,
      Q => \^q\(4),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
      D => \count_value_i[5]_i_1__3_n_0\,
      Q => \^q\(5),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
      D => \count_value_i[6]_i_1__3_n_0\,
      Q => \^q\(6),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
      D => \count_value_i[7]_i_1__3_n_0\,
      Q => \^q\(7),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
      D => \count_value_i[8]_i_1__3_n_0\,
      Q => \^q\(8),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
      D => \count_value_i[9]_i_1__3_n_0\,
      Q => \^q\(9),
      R => \count_value_i_reg[1]_0\(0)
    );
\gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FD"
    )
        port map (
      I0 => \count_value_i_reg[0]_0\(1),
      I1 => \count_value_i_reg[0]_0\(0),
      I2 => rd_en,
      I3 => ram_empty_i,
      O => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized6_131\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 10 downto 0 );
    ram_wr_en_pf : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    \count_value_i_reg[5]_0\ : in STD_LOGIC;
    \count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_d1 : in STD_LOGIC;
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized6_131\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized6_131\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized6_131\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[10]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[10]_i_2__1_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[6]_i_2__1_n_0\ : STD_LOGIC;
  signal \count_value_i[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[9]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[9]_i_2__1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1__0\ : label is "soft_lutpair332";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair332";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair331";
  attribute SOFT_HLUTNM of \count_value_i[4]_i_1__0\ : label is "soft_lutpair331";
  attribute SOFT_HLUTNM of \count_value_i[7]_i_1__1\ : label is "soft_lutpair330";
  attribute SOFT_HLUTNM of \count_value_i[8]_i_1__1\ : label is "soft_lutpair330";
begin
  Q(10 downto 0) <= \^q\(10 downto 0);
\count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1__0_n_0\
    );
\count_value_i[10]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(8),
      I1 => \count_value_i[10]_i_2__1_n_0\,
      I2 => \^q\(7),
      I3 => \^q\(9),
      I4 => \^q\(10),
      O => \count_value_i[10]_i_1__1_n_0\
    );
\count_value_i[10]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(6),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \count_value_i[6]_i_2__1_n_0\,
      I4 => \^q\(3),
      I5 => \^q\(5),
      O => \count_value_i[10]_i_2__1_n_0\
    );
\count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1__0_n_0\
    );
\count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__0_n_0\
    );
\count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__0_n_0\
    );
\count_value_i[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \count_value_i[4]_i_1__0_n_0\
    );
\count_value_i[5]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \count_value_i[6]_i_2__1_n_0\,
      I2 => \^q\(2),
      I3 => \^q\(4),
      I4 => \^q\(5),
      O => \count_value_i[5]_i_1__1_n_0\
    );
\count_value_i[6]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \count_value_i[6]_i_2__1_n_0\,
      I3 => \^q\(3),
      I4 => \^q\(5),
      I5 => \^q\(6),
      O => \count_value_i[6]_i_1__1_n_0\
    );
\count_value_i[6]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => wr_en,
      I2 => \count_value_i_reg[5]_0\,
      I3 => \count_value_i_reg[1]_0\(0),
      I4 => rst_d1,
      I5 => \^q\(0),
      O => \count_value_i[6]_i_2__1_n_0\
    );
\count_value_i[7]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(5),
      I1 => \count_value_i[9]_i_2__1_n_0\,
      I2 => \^q\(6),
      I3 => \^q\(7),
      O => \count_value_i[7]_i_1__1_n_0\
    );
\count_value_i[8]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(6),
      I1 => \count_value_i[9]_i_2__1_n_0\,
      I2 => \^q\(5),
      I3 => \^q\(7),
      I4 => \^q\(8),
      O => \count_value_i[8]_i_1__1_n_0\
    );
\count_value_i[9]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(7),
      I1 => \^q\(5),
      I2 => \count_value_i[9]_i_2__1_n_0\,
      I3 => \^q\(6),
      I4 => \^q\(8),
      I5 => \^q\(9),
      O => \count_value_i[9]_i_1__1_n_0\
    );
\count_value_i[9]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => ram_wr_en_pf,
      I4 => \^q\(1),
      I5 => \^q\(3),
      O => \count_value_i[9]_i_2__1_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[0]_i_1__0_n_0\,
      Q => \^q\(0),
      S => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[10]_i_1__1_n_0\,
      Q => \^q\(10),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[1]_i_1__0_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[2]_i_1__0_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[3]_i_1__0_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[4]_i_1__0_n_0\,
      Q => \^q\(4),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[5]_i_1__1_n_0\,
      Q => \^q\(5),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[6]_i_1__1_n_0\,
      Q => \^q\(6),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[7]_i_1__1_n_0\,
      Q => \^q\(7),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[8]_i_1__1_n_0\,
      Q => \^q\(8),
      R => \count_value_i_reg[1]_0\(0)
    );
\count_value_i_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => ram_wr_en_pf,
      D => \count_value_i[9]_i_1__1_n_0\,
      Q => \^q\(9),
      R => \count_value_i_reg[1]_0\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7\ is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \gen_pf_ic_rc.ram_empty_i_reg\ : out STD_LOGIC;
    \count_value_i_reg[2]_0\ : out STD_LOGIC;
    \count_value_i_reg[4]_0\ : out STD_LOGIC;
    rd_en : in STD_LOGIC;
    \count_value_i_reg[5]_0\ : in STD_LOGIC;
    \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \count_value_i_reg[5]_1\ : in STD_LOGIC;
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \count_value_i[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \^gen_pf_ic_rc.ram_empty_i_reg\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1__3\ : label is "soft_lutpair422";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__3\ : label is "soft_lutpair421";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__3\ : label is "soft_lutpair422";
  attribute SOFT_HLUTNM of \count_value_i[5]_i_2__0\ : label is "soft_lutpair421";
begin
  E(0) <= \^e\(0);
  Q(5 downto 0) <= \^q\(5 downto 0);
  \gen_pf_ic_rc.ram_empty_i_reg\ <= \^gen_pf_ic_rc.ram_empty_i_reg\;
\count_value_i[0]_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1__3_n_0\
    );
\count_value_i[1]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1__3_n_0\
    );
\count_value_i[2]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__3_n_0\
    );
\count_value_i[3]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__3_n_0\
    );
\count_value_i[4]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFF08000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^gen_pf_ic_rc.ram_empty_i_reg\,
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => \^q\(4),
      O => \count_value_i[4]_i_1__3_n_0\
    );
\count_value_i[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \count_value_i_reg[5]_0\,
      I1 => rd_en,
      O => \^gen_pf_ic_rc.ram_empty_i_reg\
    );
\count_value_i[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \count_value_i[5]_i_2__0_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(2),
      I4 => \^q\(5),
      O => \count_value_i[5]_i_1__0_n_0\
    );
\count_value_i[5]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \count_value_i_reg[5]_0\,
      I3 => rd_en,
      O => \count_value_i[5]_i_2__0_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^e\(0),
      D => \count_value_i[0]_i_1__3_n_0\,
      Q => \^q\(0),
      R => \count_value_i_reg[5]_1\
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^e\(0),
      D => \count_value_i[1]_i_1__3_n_0\,
      Q => \^q\(1),
      R => \count_value_i_reg[5]_1\
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^e\(0),
      D => \count_value_i[2]_i_1__3_n_0\,
      Q => \^q\(2),
      R => \count_value_i_reg[5]_1\
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^e\(0),
      D => \count_value_i[3]_i_1__3_n_0\,
      Q => \^q\(3),
      R => \count_value_i_reg[5]_1\
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^e\(0),
      D => \count_value_i[4]_i_1__3_n_0\,
      Q => \^q\(4),
      R => \count_value_i_reg[5]_1\
    );
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^e\(0),
      D => \count_value_i[5]_i_1__0_n_0\,
      Q => \^q\(5),
      R => \count_value_i_reg[5]_1\
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20BADF45DF4520BA"
    )
        port map (
      I0 => \^q\(0),
      I1 => \count_value_i_reg[5]_0\,
      I2 => rd_en,
      I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(0),
      I4 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(1),
      I5 => \^q\(1),
      O => D(0)
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(4),
      I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(3),
      O => \count_value_i_reg[4]_0\
    );
\gen_pf_ic_rc.ram_empty_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(2),
      I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(2),
      I2 => \^q\(1),
      I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(1),
      I4 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(0),
      I5 => \^q\(0),
      O => \count_value_i_reg[2]_0\
    );
\gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rd_en,
      I1 => \count_value_i_reg[5]_0\,
      O => \^e\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_127\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    O : out STD_LOGIC_VECTOR ( 0 to 0 );
    wr_en : in STD_LOGIC;
    \count_value_i_reg[5]_0\ : in STD_LOGIC;
    wrst_busy : in STD_LOGIC;
    rst_d1 : in STD_LOGIC;
    \gwdc.wr_data_count_i_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_127\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_127\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_127\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[5]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[5]_i_2_n_0\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i[5]_i_2_n_0\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i[5]_i_3_n_0\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i[5]_i_4_n_0\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i[5]_i_5_n_0\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i[5]_i_6_n_0\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i[5]_i_7_n_0\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i_reg[5]_i_1_n_4\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i_reg[5]_i_1_n_5\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i_reg[5]_i_1_n_6\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i_reg[5]_i_1_n_7\ : STD_LOGIC;
  signal \NLW_gwdc.wr_data_count_i_reg[5]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_gwdc.wr_data_count_i_reg[5]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair426";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair426";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair425";
  attribute SOFT_HLUTNM of \count_value_i[4]_i_1__1\ : label is "soft_lutpair425";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[5]_i_1\ : label is 35;
begin
  Q(5 downto 0) <= \^q\(5 downto 0);
\count_value_i[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1__1_n_0\
    );
\count_value_i[1]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1__1_n_0\
    );
\count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__1_n_0\
    );
\count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__1_n_0\
    );
\count_value_i[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \count_value_i[4]_i_1__1_n_0\
    );
\count_value_i[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \count_value_i[5]_i_2_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(2),
      I4 => \^q\(5),
      O => \count_value_i[5]_i_1_n_0\
    );
\count_value_i[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => wr_en,
      I2 => \count_value_i_reg[5]_0\,
      I3 => wrst_busy,
      I4 => rst_d1,
      I5 => \^q\(1),
      O => \count_value_i[5]_i_2_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1__1_n_0\,
      Q => \^q\(0),
      R => wrst_busy
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1__1_n_0\,
      Q => \^q\(1),
      R => wrst_busy
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1__1_n_0\,
      Q => \^q\(2),
      R => wrst_busy
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1__1_n_0\,
      Q => \^q\(3),
      R => wrst_busy
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[4]_i_1__1_n_0\,
      Q => \^q\(4),
      R => wrst_busy
    );
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[5]_i_1_n_0\,
      Q => \^q\(5),
      R => wrst_busy
    );
\gwdc.wr_data_count_i[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(5),
      I1 => \gwdc.wr_data_count_i_reg[5]\(5),
      O => \gwdc.wr_data_count_i[5]_i_2_n_0\
    );
\gwdc.wr_data_count_i[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(4),
      I1 => \gwdc.wr_data_count_i_reg[5]\(4),
      O => \gwdc.wr_data_count_i[5]_i_3_n_0\
    );
\gwdc.wr_data_count_i[5]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gwdc.wr_data_count_i_reg[5]\(3),
      O => \gwdc.wr_data_count_i[5]_i_4_n_0\
    );
\gwdc.wr_data_count_i[5]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(2),
      I1 => \gwdc.wr_data_count_i_reg[5]\(2),
      O => \gwdc.wr_data_count_i[5]_i_5_n_0\
    );
\gwdc.wr_data_count_i[5]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(1),
      I1 => \gwdc.wr_data_count_i_reg[5]\(1),
      O => \gwdc.wr_data_count_i[5]_i_6_n_0\
    );
\gwdc.wr_data_count_i[5]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gwdc.wr_data_count_i_reg[5]\(0),
      O => \gwdc.wr_data_count_i[5]_i_7_n_0\
    );
\gwdc.wr_data_count_i_reg[5]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_gwdc.wr_data_count_i_reg[5]_i_1_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \gwdc.wr_data_count_i_reg[5]_i_1_n_3\,
      CO(3) => \gwdc.wr_data_count_i_reg[5]_i_1_n_4\,
      CO(2) => \gwdc.wr_data_count_i_reg[5]_i_1_n_5\,
      CO(1) => \gwdc.wr_data_count_i_reg[5]_i_1_n_6\,
      CO(0) => \gwdc.wr_data_count_i_reg[5]_i_1_n_7\,
      DI(7 downto 5) => B"000",
      DI(4 downto 0) => \^q\(4 downto 0),
      O(7 downto 6) => \NLW_gwdc.wr_data_count_i_reg[5]_i_1_O_UNCONNECTED\(7 downto 6),
      O(5) => O(0),
      O(4 downto 0) => \NLW_gwdc.wr_data_count_i_reg[5]_i_1_O_UNCONNECTED\(4 downto 0),
      S(7 downto 6) => B"00",
      S(5) => \gwdc.wr_data_count_i[5]_i_2_n_0\,
      S(4) => \gwdc.wr_data_count_i[5]_i_3_n_0\,
      S(3) => \gwdc.wr_data_count_i[5]_i_4_n_0\,
      S(2) => \gwdc.wr_data_count_i[5]_i_5_n_0\,
      S(1) => \gwdc.wr_data_count_i[5]_i_6_n_0\,
      S(0) => \gwdc.wr_data_count_i[5]_i_7_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_158\ is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \gen_pf_ic_rc.ram_empty_i_reg\ : out STD_LOGIC;
    \count_value_i_reg[2]_0\ : out STD_LOGIC;
    \count_value_i_reg[4]_0\ : out STD_LOGIC;
    rd_en : in STD_LOGIC;
    \count_value_i_reg[5]_0\ : in STD_LOGIC;
    \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_158\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_158\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_158\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \count_value_i[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \count_value_i[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \^gen_pf_ic_rc.ram_empty_i_reg\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1__3\ : label is "soft_lutpair239";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__3\ : label is "soft_lutpair238";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__3\ : label is "soft_lutpair239";
  attribute SOFT_HLUTNM of \count_value_i[5]_i_2__0\ : label is "soft_lutpair238";
begin
  E(0) <= \^e\(0);
  Q(5 downto 0) <= \^q\(5 downto 0);
  \gen_pf_ic_rc.ram_empty_i_reg\ <= \^gen_pf_ic_rc.ram_empty_i_reg\;
\count_value_i[0]_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1__3_n_0\
    );
\count_value_i[1]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1__3_n_0\
    );
\count_value_i[2]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__3_n_0\
    );
\count_value_i[3]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__3_n_0\
    );
\count_value_i[4]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFF08000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^gen_pf_ic_rc.ram_empty_i_reg\,
      I3 => \^q\(2),
      I4 => \^q\(3),
      I5 => \^q\(4),
      O => \count_value_i[4]_i_1__3_n_0\
    );
\count_value_i[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \count_value_i_reg[5]_0\,
      I1 => rd_en,
      O => \^gen_pf_ic_rc.ram_empty_i_reg\
    );
\count_value_i[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \count_value_i[5]_i_2__0_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(2),
      I4 => \^q\(5),
      O => \count_value_i[5]_i_1__0_n_0\
    );
\count_value_i[5]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \count_value_i_reg[5]_0\,
      I3 => rd_en,
      O => \count_value_i[5]_i_2__0_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^e\(0),
      D => \count_value_i[0]_i_1__3_n_0\,
      Q => \^q\(0),
      R => SR(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^e\(0),
      D => \count_value_i[1]_i_1__3_n_0\,
      Q => \^q\(1),
      R => SR(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^e\(0),
      D => \count_value_i[2]_i_1__3_n_0\,
      Q => \^q\(2),
      R => SR(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^e\(0),
      D => \count_value_i[3]_i_1__3_n_0\,
      Q => \^q\(3),
      R => SR(0)
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^e\(0),
      D => \count_value_i[4]_i_1__3_n_0\,
      Q => \^q\(4),
      R => SR(0)
    );
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => \^e\(0),
      D => \count_value_i[5]_i_1__0_n_0\,
      Q => \^q\(5),
      R => SR(0)
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20BADF45DF4520BA"
    )
        port map (
      I0 => \^q\(0),
      I1 => \count_value_i_reg[5]_0\,
      I2 => rd_en,
      I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(0),
      I4 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(1),
      I5 => \^q\(1),
      O => D(0)
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(4),
      I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(3),
      O => \count_value_i_reg[4]_0\
    );
\gen_pf_ic_rc.ram_empty_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \^q\(2),
      I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(2),
      I2 => \^q\(1),
      I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(1),
      I4 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(0),
      I5 => \^q\(0),
      O => \count_value_i_reg[2]_0\
    );
\gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rd_en,
      I1 => \count_value_i_reg[5]_0\,
      O => \^e\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_161\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    D : out STD_LOGIC_VECTOR ( 4 downto 0 );
    wr_en : in STD_LOGIC;
    \count_value_i_reg[5]_0\ : in STD_LOGIC;
    wrst_busy : in STD_LOGIC;
    rst_d1 : in STD_LOGIC;
    \gwdc.wr_data_count_i_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_161\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_161\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_161\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_value_i[5]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[5]_i_2_n_0\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i[5]_i_2_n_0\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i[5]_i_3_n_0\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i[5]_i_4_n_0\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i[5]_i_5_n_0\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i[5]_i_6_n_0\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i[5]_i_7_n_0\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i_reg[5]_i_1_n_4\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i_reg[5]_i_1_n_5\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i_reg[5]_i_1_n_6\ : STD_LOGIC;
  signal \gwdc.wr_data_count_i_reg[5]_i_1_n_7\ : STD_LOGIC;
  signal \NLW_gwdc.wr_data_count_i_reg[5]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_gwdc.wr_data_count_i_reg[5]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair243";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair243";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair242";
  attribute SOFT_HLUTNM of \count_value_i[4]_i_1__1\ : label is "soft_lutpair242";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[5]_i_1\ : label is 35;
begin
  Q(5 downto 0) <= \^q\(5 downto 0);
\count_value_i[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \count_value_i[0]_i_1__1_n_0\
    );
\count_value_i[1]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \count_value_i[1]_i_1__1_n_0\
    );
\count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      O => \count_value_i[2]_i_1__1_n_0\
    );
\count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(3),
      O => \count_value_i[3]_i_1__1_n_0\
    );
\count_value_i[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \count_value_i[4]_i_1__1_n_0\
    );
\count_value_i[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \count_value_i[5]_i_2_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(2),
      I4 => \^q\(5),
      O => \count_value_i[5]_i_1_n_0\
    );
\count_value_i[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => wr_en,
      I2 => \count_value_i_reg[5]_0\,
      I3 => wrst_busy,
      I4 => rst_d1,
      I5 => \^q\(1),
      O => \count_value_i[5]_i_2_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1__1_n_0\,
      Q => \^q\(0),
      R => wrst_busy
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1__1_n_0\,
      Q => \^q\(1),
      R => wrst_busy
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1__1_n_0\,
      Q => \^q\(2),
      R => wrst_busy
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1__1_n_0\,
      Q => \^q\(3),
      R => wrst_busy
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[4]_i_1__1_n_0\,
      Q => \^q\(4),
      R => wrst_busy
    );
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[5]_i_1_n_0\,
      Q => \^q\(5),
      R => wrst_busy
    );
\gwdc.wr_data_count_i[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(5),
      I1 => \gwdc.wr_data_count_i_reg[5]\(5),
      O => \gwdc.wr_data_count_i[5]_i_2_n_0\
    );
\gwdc.wr_data_count_i[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(4),
      I1 => \gwdc.wr_data_count_i_reg[5]\(4),
      O => \gwdc.wr_data_count_i[5]_i_3_n_0\
    );
\gwdc.wr_data_count_i[5]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gwdc.wr_data_count_i_reg[5]\(3),
      O => \gwdc.wr_data_count_i[5]_i_4_n_0\
    );
\gwdc.wr_data_count_i[5]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(2),
      I1 => \gwdc.wr_data_count_i_reg[5]\(2),
      O => \gwdc.wr_data_count_i[5]_i_5_n_0\
    );
\gwdc.wr_data_count_i[5]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(1),
      I1 => \gwdc.wr_data_count_i_reg[5]\(1),
      O => \gwdc.wr_data_count_i[5]_i_6_n_0\
    );
\gwdc.wr_data_count_i[5]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gwdc.wr_data_count_i_reg[5]\(0),
      O => \gwdc.wr_data_count_i[5]_i_7_n_0\
    );
\gwdc.wr_data_count_i_reg[5]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_gwdc.wr_data_count_i_reg[5]_i_1_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \gwdc.wr_data_count_i_reg[5]_i_1_n_3\,
      CO(3) => \gwdc.wr_data_count_i_reg[5]_i_1_n_4\,
      CO(2) => \gwdc.wr_data_count_i_reg[5]_i_1_n_5\,
      CO(1) => \gwdc.wr_data_count_i_reg[5]_i_1_n_6\,
      CO(0) => \gwdc.wr_data_count_i_reg[5]_i_1_n_7\,
      DI(7 downto 5) => B"000",
      DI(4 downto 0) => \^q\(4 downto 0),
      O(7 downto 6) => \NLW_gwdc.wr_data_count_i_reg[5]_i_1_O_UNCONNECTED\(7 downto 6),
      O(5 downto 1) => D(4 downto 0),
      O(0) => \NLW_gwdc.wr_data_count_i_reg[5]_i_1_O_UNCONNECTED\(0),
      S(7 downto 6) => B"00",
      S(5) => \gwdc.wr_data_count_i[5]_i_2_n_0\,
      S(4) => \gwdc.wr_data_count_i[5]_i_3_n_0\,
      S(3) => \gwdc.wr_data_count_i[5]_i_4_n_0\,
      S(2) => \gwdc.wr_data_count_i[5]_i_5_n_0\,
      S(1) => \gwdc.wr_data_count_i[5]_i_6_n_0\,
      S(0) => \gwdc.wr_data_count_i[5]_i_7_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8\ is
  port (
    empty_i0 : out STD_LOGIC;
    \gen_pf_ic_rc.ram_empty_i_reg\ : in STD_LOGIC;
    \gen_pf_ic_rc.ram_empty_i_reg_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    rd_en : in STD_LOGIC;
    \gen_pf_ic_rc.ram_empty_i_reg_1\ : in STD_LOGIC;
    \count_value_i_reg[4]_0\ : in STD_LOGIC;
    \count_value_i_reg[0]_0\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8\ is
  signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i_reg_n_0_[0]\ : STD_LOGIC;
  signal \count_value_i_reg_n_0_[1]\ : STD_LOGIC;
  signal \count_value_i_reg_n_0_[2]\ : STD_LOGIC;
  signal \count_value_i_reg_n_0_[3]\ : STD_LOGIC;
  signal \count_value_i_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_pf_ic_rc.ram_empty_i_i_4_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.ram_empty_i_i_5_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.ram_empty_i_i_6_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1__2\ : label is "soft_lutpair424";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__2\ : label is "soft_lutpair423";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair424";
  attribute SOFT_HLUTNM of \gen_pf_ic_rc.ram_empty_i_i_5\ : label is "soft_lutpair423";
begin
\count_value_i[0]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      O => \count_value_i[0]_i_1__2_n_0\
    );
\count_value_i[1]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      I1 => \count_value_i_reg_n_0_[1]\,
      O => \count_value_i[1]_i_1__2_n_0\
    );
\count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[1]\,
      I1 => \count_value_i_reg_n_0_[0]\,
      I2 => \count_value_i_reg_n_0_[2]\,
      O => \count_value_i[2]_i_1__2_n_0\
    );
\count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      I1 => \count_value_i_reg_n_0_[1]\,
      I2 => \count_value_i_reg_n_0_[2]\,
      I3 => \count_value_i_reg_n_0_[3]\,
      O => \count_value_i[3]_i_1__2_n_0\
    );
\count_value_i[4]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFFFFFFF20000000"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      I1 => \count_value_i_reg[4]_0\,
      I2 => \count_value_i_reg_n_0_[3]\,
      I3 => \count_value_i_reg_n_0_[2]\,
      I4 => \count_value_i_reg_n_0_[1]\,
      I5 => \count_value_i_reg_n_0_[4]\,
      O => \count_value_i[4]_i_1__2_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1__2_n_0\,
      Q => \count_value_i_reg_n_0_[0]\,
      S => \count_value_i_reg[0]_0\
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1__2_n_0\,
      Q => \count_value_i_reg_n_0_[1]\,
      R => \count_value_i_reg[0]_0\
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1__2_n_0\,
      Q => \count_value_i_reg_n_0_[2]\,
      R => \count_value_i_reg[0]_0\
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1__2_n_0\,
      Q => \count_value_i_reg_n_0_[3]\,
      R => \count_value_i_reg[0]_0\
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[4]_i_1__2_n_0\,
      Q => \count_value_i_reg_n_0_[4]\,
      R => \count_value_i_reg[0]_0\
    );
\gen_pf_ic_rc.ram_empty_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8888888"
    )
        port map (
      I0 => \gen_pf_ic_rc.ram_empty_i_reg\,
      I1 => \gen_pf_ic_rc.ram_empty_i_reg_0\,
      I2 => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\,
      I3 => \gen_pf_ic_rc.ram_empty_i_i_5_n_0\,
      I4 => \gen_pf_ic_rc.ram_empty_i_i_6_n_0\,
      O => empty_i0
    );
\gen_pf_ic_rc.ram_empty_i_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0090"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[4]\,
      I1 => Q(4),
      I2 => rd_en,
      I3 => \gen_pf_ic_rc.ram_empty_i_reg_1\,
      O => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\
    );
\gen_pf_ic_rc.ram_empty_i_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      I1 => Q(0),
      I2 => \count_value_i_reg_n_0_[1]\,
      I3 => Q(1),
      O => \gen_pf_ic_rc.ram_empty_i_i_5_n_0\
    );
\gen_pf_ic_rc.ram_empty_i_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[2]\,
      I1 => Q(2),
      I2 => \count_value_i_reg_n_0_[3]\,
      I3 => Q(3),
      O => \gen_pf_ic_rc.ram_empty_i_i_6_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_128\ is
  port (
    \count_value_i_reg[2]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    wrst_busy : in STD_LOGIC;
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_128\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_128\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_128\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_3_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_4_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_5_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_6_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_4\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_5\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_6\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_7\ : STD_LOGIC;
  signal wr_pntr_plus1_pf : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1__0\ : label is "soft_lutpair428";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair428";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair427";
  attribute SOFT_HLUTNM of \count_value_i[4]_i_1__0\ : label is "soft_lutpair427";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1\ : label is 35;
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
\count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wr_pntr_plus1_pf(1),
      O => \count_value_i[0]_i_1__0_n_0\
    );
\count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wr_pntr_plus1_pf(1),
      I1 => wr_pntr_plus1_pf(2),
      O => \count_value_i[1]_i_1__0_n_0\
    );
\count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => wr_pntr_plus1_pf(2),
      I1 => wr_pntr_plus1_pf(1),
      I2 => wr_pntr_plus1_pf(3),
      O => \count_value_i[2]_i_1__0_n_0\
    );
\count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => wr_pntr_plus1_pf(1),
      I1 => wr_pntr_plus1_pf(2),
      I2 => wr_pntr_plus1_pf(3),
      I3 => \^q\(0),
      O => \count_value_i[3]_i_1__0_n_0\
    );
\count_value_i[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => wr_pntr_plus1_pf(1),
      I1 => \^q\(0),
      I2 => wr_pntr_plus1_pf(3),
      I3 => wr_pntr_plus1_pf(2),
      I4 => \^q\(1),
      O => \count_value_i[4]_i_1__0_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1__0_n_0\,
      Q => wr_pntr_plus1_pf(1),
      S => wrst_busy
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1__0_n_0\,
      Q => wr_pntr_plus1_pf(2),
      R => wrst_busy
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1__0_n_0\,
      Q => wr_pntr_plus1_pf(3),
      R => wrst_busy
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1__0_n_0\,
      Q => \^q\(0),
      R => wrst_busy
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[4]_i_1__0_n_0\,
      Q => \^q\(1),
      R => wrst_busy
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(1),
      I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(4),
      O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_2_n_0\
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(3),
      O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_3_n_0\
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_pntr_plus1_pf(3),
      I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(2),
      O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_4_n_0\
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_pntr_plus1_pf(2),
      I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(1),
      O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_5_n_0\
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_pntr_plus1_pf(1),
      I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(0),
      O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_6_n_0\
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => E(0),
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_4\,
      CO(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_5\,
      CO(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_6\,
      CO(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3) => \^q\(0),
      DI(2 downto 0) => wr_pntr_plus1_pf(3 downto 1),
      O(7 downto 5) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_O_UNCONNECTED\(7 downto 5),
      O(4 downto 1) => D(3 downto 0),
      O(0) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_O_UNCONNECTED\(0),
      S(7 downto 5) => B"000",
      S(4) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_2_n_0\,
      S(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_3_n_0\,
      S(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_4_n_0\,
      S(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_5_n_0\,
      S(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_6_n_0\
    );
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wr_pntr_plus1_pf(3),
      I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(2),
      I2 => wr_pntr_plus1_pf(2),
      I3 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(1),
      I4 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(0),
      I5 => wr_pntr_plus1_pf(1),
      O => \count_value_i_reg[2]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_159\ is
  port (
    empty_i0 : out STD_LOGIC;
    \gen_pf_ic_rc.ram_empty_i_reg\ : in STD_LOGIC;
    \gen_pf_ic_rc.ram_empty_i_reg_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    rd_en : in STD_LOGIC;
    \gen_pf_ic_rc.ram_empty_i_reg_1\ : in STD_LOGIC;
    \count_value_i_reg[4]_0\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_159\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_159\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_159\ is
  signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_value_i_reg_n_0_[0]\ : STD_LOGIC;
  signal \count_value_i_reg_n_0_[1]\ : STD_LOGIC;
  signal \count_value_i_reg_n_0_[2]\ : STD_LOGIC;
  signal \count_value_i_reg_n_0_[3]\ : STD_LOGIC;
  signal \count_value_i_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_pf_ic_rc.ram_empty_i_i_4_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.ram_empty_i_i_5_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.ram_empty_i_i_6_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1__2\ : label is "soft_lutpair241";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__2\ : label is "soft_lutpair240";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair241";
  attribute SOFT_HLUTNM of \gen_pf_ic_rc.ram_empty_i_i_5\ : label is "soft_lutpair240";
begin
\count_value_i[0]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      O => \count_value_i[0]_i_1__2_n_0\
    );
\count_value_i[1]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      I1 => \count_value_i_reg_n_0_[1]\,
      O => \count_value_i[1]_i_1__2_n_0\
    );
\count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[1]\,
      I1 => \count_value_i_reg_n_0_[0]\,
      I2 => \count_value_i_reg_n_0_[2]\,
      O => \count_value_i[2]_i_1__2_n_0\
    );
\count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      I1 => \count_value_i_reg_n_0_[1]\,
      I2 => \count_value_i_reg_n_0_[2]\,
      I3 => \count_value_i_reg_n_0_[3]\,
      O => \count_value_i[3]_i_1__2_n_0\
    );
\count_value_i[4]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFFFFFFF20000000"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      I1 => \count_value_i_reg[4]_0\,
      I2 => \count_value_i_reg_n_0_[3]\,
      I3 => \count_value_i_reg_n_0_[2]\,
      I4 => \count_value_i_reg_n_0_[1]\,
      I5 => \count_value_i_reg_n_0_[4]\,
      O => \count_value_i[4]_i_1__2_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1__2_n_0\,
      Q => \count_value_i_reg_n_0_[0]\,
      S => SR(0)
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1__2_n_0\,
      Q => \count_value_i_reg_n_0_[1]\,
      R => SR(0)
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1__2_n_0\,
      Q => \count_value_i_reg_n_0_[2]\,
      R => SR(0)
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1__2_n_0\,
      Q => \count_value_i_reg_n_0_[3]\,
      R => SR(0)
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => E(0),
      D => \count_value_i[4]_i_1__2_n_0\,
      Q => \count_value_i_reg_n_0_[4]\,
      R => SR(0)
    );
\gen_pf_ic_rc.ram_empty_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8888888"
    )
        port map (
      I0 => \gen_pf_ic_rc.ram_empty_i_reg\,
      I1 => \gen_pf_ic_rc.ram_empty_i_reg_0\,
      I2 => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\,
      I3 => \gen_pf_ic_rc.ram_empty_i_i_5_n_0\,
      I4 => \gen_pf_ic_rc.ram_empty_i_i_6_n_0\,
      O => empty_i0
    );
\gen_pf_ic_rc.ram_empty_i_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0090"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[4]\,
      I1 => Q(4),
      I2 => rd_en,
      I3 => \gen_pf_ic_rc.ram_empty_i_reg_1\,
      O => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\
    );
\gen_pf_ic_rc.ram_empty_i_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      I1 => Q(0),
      I2 => \count_value_i_reg_n_0_[1]\,
      I3 => Q(1),
      O => \gen_pf_ic_rc.ram_empty_i_i_5_n_0\
    );
\gen_pf_ic_rc.ram_empty_i_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[2]\,
      I1 => Q(2),
      I2 => \count_value_i_reg_n_0_[3]\,
      I3 => Q(3),
      O => \gen_pf_ic_rc.ram_empty_i_i_6_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_162\ is
  port (
    \count_value_i_reg[2]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    D : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    wrst_busy : in STD_LOGIC;
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_162\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_162\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_162\ is
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_2_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_3_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_4_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_5_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_6_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_4\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_5\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_6\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_7\ : STD_LOGIC;
  signal wr_pntr_plus1_pf : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[1]_i_1__0\ : label is "soft_lutpair245";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair245";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair244";
  attribute SOFT_HLUTNM of \count_value_i[4]_i_1__0\ : label is "soft_lutpair244";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1\ : label is 35;
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
\count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wr_pntr_plus1_pf(1),
      O => \count_value_i[0]_i_1__0_n_0\
    );
\count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wr_pntr_plus1_pf(1),
      I1 => wr_pntr_plus1_pf(2),
      O => \count_value_i[1]_i_1__0_n_0\
    );
\count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => wr_pntr_plus1_pf(2),
      I1 => wr_pntr_plus1_pf(1),
      I2 => wr_pntr_plus1_pf(3),
      O => \count_value_i[2]_i_1__0_n_0\
    );
\count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => wr_pntr_plus1_pf(1),
      I1 => wr_pntr_plus1_pf(2),
      I2 => wr_pntr_plus1_pf(3),
      I3 => \^q\(0),
      O => \count_value_i[3]_i_1__0_n_0\
    );
\count_value_i[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => wr_pntr_plus1_pf(1),
      I1 => \^q\(0),
      I2 => wr_pntr_plus1_pf(3),
      I3 => wr_pntr_plus1_pf(2),
      I4 => \^q\(1),
      O => \count_value_i[4]_i_1__0_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1__0_n_0\,
      Q => wr_pntr_plus1_pf(1),
      S => wrst_busy
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1__0_n_0\,
      Q => wr_pntr_plus1_pf(2),
      R => wrst_busy
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1__0_n_0\,
      Q => wr_pntr_plus1_pf(3),
      R => wrst_busy
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1__0_n_0\,
      Q => \^q\(0),
      R => wrst_busy
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[4]_i_1__0_n_0\,
      Q => \^q\(1),
      R => wrst_busy
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(1),
      I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(4),
      O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_2_n_0\
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(3),
      O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_3_n_0\
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_pntr_plus1_pf(3),
      I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(2),
      O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_4_n_0\
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_pntr_plus1_pf(2),
      I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(1),
      O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_5_n_0\
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wr_pntr_plus1_pf(1),
      I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(0),
      O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_6_n_0\
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => E(0),
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_4\,
      CO(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_5\,
      CO(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_6\,
      CO(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3) => \^q\(0),
      DI(2 downto 0) => wr_pntr_plus1_pf(3 downto 1),
      O(7 downto 5) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]_i_1_O_UNCONNECTED\(7 downto 5),
      O(4 downto 0) => D(4 downto 0),
      S(7 downto 5) => B"000",
      S(4) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_2_n_0\,
      S(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_3_n_0\,
      S(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_4_n_0\,
      S(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_5_n_0\,
      S(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[5]_i_6_n_0\
    );
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wr_pntr_plus1_pf(3),
      I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(2),
      I2 => wr_pntr_plus1_pf(2),
      I3 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(1),
      I4 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(0),
      I5 => wr_pntr_plus1_pf(1),
      O => \count_value_i_reg[2]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized9\ is
  port (
    \count_value_i_reg[2]_0\ : out STD_LOGIC;
    \count_value_i_reg[4]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    wrst_busy : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized9\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized9\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized9\ is
  signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1_n_0\ : STD_LOGIC;
  signal \^count_value_i_reg[4]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \count_value_i_reg_n_0_[0]\ : STD_LOGIC;
  signal \count_value_i_reg_n_0_[1]\ : STD_LOGIC;
  signal \count_value_i_reg_n_0_[2]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair430";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair430";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair429";
  attribute SOFT_HLUTNM of \count_value_i[4]_i_1\ : label is "soft_lutpair429";
begin
  \count_value_i_reg[4]_0\(1 downto 0) <= \^count_value_i_reg[4]_0\(1 downto 0);
\count_value_i[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      O => \count_value_i[0]_i_1_n_0\
    );
\count_value_i[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      I1 => \count_value_i_reg_n_0_[1]\,
      O => \count_value_i[1]_i_1_n_0\
    );
\count_value_i[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[1]\,
      I1 => \count_value_i_reg_n_0_[0]\,
      I2 => \count_value_i_reg_n_0_[2]\,
      O => \count_value_i[2]_i_1_n_0\
    );
\count_value_i[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      I1 => \count_value_i_reg_n_0_[1]\,
      I2 => \count_value_i_reg_n_0_[2]\,
      I3 => \^count_value_i_reg[4]_0\(0),
      O => \count_value_i[3]_i_1_n_0\
    );
\count_value_i[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      I1 => \^count_value_i_reg[4]_0\(0),
      I2 => \count_value_i_reg_n_0_[2]\,
      I3 => \count_value_i_reg_n_0_[1]\,
      I4 => \^count_value_i_reg[4]_0\(1),
      O => \count_value_i[4]_i_1_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1_n_0\,
      Q => \count_value_i_reg_n_0_[0]\,
      R => wrst_busy
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1_n_0\,
      Q => \count_value_i_reg_n_0_[1]\,
      S => wrst_busy
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1_n_0\,
      Q => \count_value_i_reg_n_0_[2]\,
      R => wrst_busy
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1_n_0\,
      Q => \^count_value_i_reg[4]_0\(0),
      R => wrst_busy
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[4]_i_1_n_0\,
      Q => \^count_value_i_reg[4]_0\(1),
      R => wrst_busy
    );
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[2]\,
      I1 => Q(2),
      I2 => \count_value_i_reg_n_0_[1]\,
      I3 => Q(1),
      I4 => Q(0),
      I5 => \count_value_i_reg_n_0_[0]\,
      O => \count_value_i_reg[2]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized9_163\ is
  port (
    \count_value_i_reg[2]_0\ : out STD_LOGIC;
    \count_value_i_reg[4]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    wrst_busy : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized9_163\ : entity is "xpm_counter_updn";
end \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized9_163\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_counter_updn__parameterized9_163\ is
  signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC;
  signal \count_value_i[4]_i_1_n_0\ : STD_LOGIC;
  signal \^count_value_i_reg[4]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \count_value_i_reg_n_0_[0]\ : STD_LOGIC;
  signal \count_value_i_reg_n_0_[1]\ : STD_LOGIC;
  signal \count_value_i_reg_n_0_[2]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair247";
  attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair247";
  attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair246";
  attribute SOFT_HLUTNM of \count_value_i[4]_i_1\ : label is "soft_lutpair246";
begin
  \count_value_i_reg[4]_0\(1 downto 0) <= \^count_value_i_reg[4]_0\(1 downto 0);
\count_value_i[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      O => \count_value_i[0]_i_1_n_0\
    );
\count_value_i[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      I1 => \count_value_i_reg_n_0_[1]\,
      O => \count_value_i[1]_i_1_n_0\
    );
\count_value_i[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[1]\,
      I1 => \count_value_i_reg_n_0_[0]\,
      I2 => \count_value_i_reg_n_0_[2]\,
      O => \count_value_i[2]_i_1_n_0\
    );
\count_value_i[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      I1 => \count_value_i_reg_n_0_[1]\,
      I2 => \count_value_i_reg_n_0_[2]\,
      I3 => \^count_value_i_reg[4]_0\(0),
      O => \count_value_i[3]_i_1_n_0\
    );
\count_value_i[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[0]\,
      I1 => \^count_value_i_reg[4]_0\(0),
      I2 => \count_value_i_reg_n_0_[2]\,
      I3 => \count_value_i_reg_n_0_[1]\,
      I4 => \^count_value_i_reg[4]_0\(1),
      O => \count_value_i[4]_i_1_n_0\
    );
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[0]_i_1_n_0\,
      Q => \count_value_i_reg_n_0_[0]\,
      R => wrst_busy
    );
\count_value_i_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[1]_i_1_n_0\,
      Q => \count_value_i_reg_n_0_[1]\,
      S => wrst_busy
    );
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[2]_i_1_n_0\,
      Q => \count_value_i_reg_n_0_[2]\,
      R => wrst_busy
    );
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[3]_i_1_n_0\,
      Q => \^count_value_i_reg[4]_0\(0),
      R => wrst_busy
    );
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => E(0),
      D => \count_value_i[4]_i_1_n_0\,
      Q => \^count_value_i_reg[4]_0\(1),
      R => wrst_busy
    );
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \count_value_i_reg_n_0_[2]\,
      I1 => Q(2),
      I2 => \count_value_i_reg_n_0_[1]\,
      I3 => Q(1),
      I4 => Q(0),
      I5 => \count_value_i_reg_n_0_[0]\,
      O => \count_value_i_reg[2]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_reg_bit is
  port (
    rst_d1 : out STD_LOGIC;
    d_out_int_reg_0 : out STD_LOGIC;
    wrst_busy : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    rst : in STD_LOGIC;
    prog_full : in STD_LOGIC;
    \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_reg_bit : entity is "xpm_fifo_reg_bit";
end design_1_Vsp_core_0_0_xpm_fifo_reg_bit;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_reg_bit is
  signal \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\ : STD_LOGIC;
  signal \^rst_d1\ : STD_LOGIC;
begin
  rst_d1 <= \^rst_d1\;
d_out_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => wrst_busy,
      Q => \^rst_d1\,
      R => '0'
    );
\gen_pf_ic_rc.gpf_ic.prog_full_i_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C4"
    )
        port map (
      I0 => \^rst_d1\,
      I1 => \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\,
      I2 => rst,
      I3 => wrst_busy,
      O => d_out_int_reg_0
    );
\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBB8B8B8B8B8"
    )
        port map (
      I0 => prog_full,
      I1 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\,
      I2 => Q(3),
      I3 => Q(1),
      I4 => Q(0),
      I5 => Q(2),
      O => \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_reg_bit_129 is
  port (
    rst_d1 : out STD_LOGIC;
    d_out_int_reg_0 : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC;
    rst : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_reg_bit_129 : entity is "xpm_fifo_reg_bit";
end design_1_Vsp_core_0_0_xpm_fifo_reg_bit_129;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_reg_bit_129 is
  signal \^rst_d1\ : STD_LOGIC;
begin
  rst_d1 <= \^rst_d1\;
d_out_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => Q(0),
      Q => \^rst_d1\,
      R => '0'
    );
\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => rst,
      I1 => \^rst_d1\,
      I2 => Q(0),
      O => d_out_int_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_reg_bit_132 is
  port (
    rst_d1 : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_reg_bit_132 : entity is "xpm_fifo_reg_bit";
end design_1_Vsp_core_0_0_xpm_fifo_reg_bit_132;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_reg_bit_132 is
begin
d_out_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => Q(0),
      Q => rst_d1,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_reg_bit_138 is
  port (
    rst_d1 : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_reg_bit_138 : entity is "xpm_fifo_reg_bit";
end design_1_Vsp_core_0_0_xpm_fifo_reg_bit_138;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_reg_bit_138 is
begin
d_out_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => Q(0),
      Q => rst_d1,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_reg_bit_144 is
  port (
    rst_d1 : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_reg_bit_144 : entity is "xpm_fifo_reg_bit";
end design_1_Vsp_core_0_0_xpm_fifo_reg_bit_144;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_reg_bit_144 is
begin
d_out_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => Q(0),
      Q => rst_d1,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_reg_bit_150 is
  port (
    rst_d1 : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_reg_bit_150 : entity is "xpm_fifo_reg_bit";
end design_1_Vsp_core_0_0_xpm_fifo_reg_bit_150;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_reg_bit_150 is
begin
d_out_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => Q(0),
      Q => rst_d1,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_reg_bit_160 is
  port (
    rst_d1 : out STD_LOGIC;
    d_out_int_reg_0 : out STD_LOGIC;
    wrst_busy : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    prog_full : in STD_LOGIC;
    \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ : in STD_LOGIC;
    rst : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_reg_bit_160 : entity is "xpm_fifo_reg_bit";
end design_1_Vsp_core_0_0_xpm_fifo_reg_bit_160;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_reg_bit_160 is
  signal p_1_in : STD_LOGIC;
  signal \^rst_d1\ : STD_LOGIC;
begin
  rst_d1 <= \^rst_d1\;
d_out_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => wrst_busy,
      Q => \^rst_d1\,
      R => '0'
    );
\gen_pf_ic_rc.gpf_ic.prog_full_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CFC04540"
    )
        port map (
      I0 => \^rst_d1\,
      I1 => prog_full,
      I2 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\,
      I3 => p_1_in,
      I4 => rst,
      I5 => wrst_busy,
      O => d_out_int_reg_0
    );
\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88800000"
    )
        port map (
      I0 => Q(3),
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(0),
      I4 => Q(4),
      O => p_1_in
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_reg_vec is
  port (
    ram_full_i0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_0\ : in STD_LOGIC;
    \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    wrst_busy : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 4 downto 0 );
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_reg_vec : entity is "xpm_fifo_reg_vec";
end design_1_Vsp_core_0_0_xpm_fifo_reg_vec;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_reg_vec is
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_2_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5_n_0\ : STD_LOGIC;
begin
  Q(4 downto 0) <= \^q\(4 downto 0);
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8888888"
    )
        port map (
      I0 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_2_n_0\,
      I1 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\,
      I2 => E(0),
      I3 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_0\,
      I4 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5_n_0\,
      O => ram_full_i0
    );
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_2\(0),
      I2 => \^q\(4),
      I3 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_2\(1),
      O => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_2_n_0\
    );
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_1\(0),
      I2 => \^q\(4),
      I3 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_1\(1),
      O => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5_n_0\
    );
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(0),
      Q => \^q\(0),
      R => wrst_busy
    );
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(1),
      Q => \^q\(1),
      R => wrst_busy
    );
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(2),
      Q => \^q\(2),
      R => wrst_busy
    );
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(3),
      Q => \^q\(3),
      R => wrst_busy
    );
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(4),
      Q => \^q\(4),
      R => wrst_busy
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_reg_vec_125 is
  port (
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \reg_out_i_reg[3]_0\ : out STD_LOGIC;
    \gen_pf_ic_rc.ram_empty_i_reg\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\ : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\ : in STD_LOGIC;
    \reg_out_i_reg[0]_0\ : in STD_LOGIC;
    \reg_out_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_reg_vec_125 : entity is "xpm_fifo_reg_vec";
end design_1_Vsp_core_0_0_xpm_fifo_reg_vec_125;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_reg_vec_125 is
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[2]_i_1\ : label is "soft_lutpair420";
  attribute SOFT_HLUTNM of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_1\ : label is "soft_lutpair420";
begin
  Q(4 downto 0) <= \^q\(4 downto 0);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6966"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pf_ic_rc.ram_empty_i_reg\(0),
      I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\,
      I3 => rd_en,
      O => D(0)
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_2_n_0\,
      I1 => \^q\(2),
      I2 => \gen_pf_ic_rc.ram_empty_i_reg\(2),
      O => D(1)
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4DB2B24D"
    )
        port map (
      I0 => \^q\(2),
      I1 => \gen_pf_ic_rc.ram_empty_i_reg\(2),
      I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_2_n_0\,
      I3 => \^q\(3),
      I4 => \gen_pf_ic_rc.ram_empty_i_reg\(3),
      O => D(2)
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4D00FF4DB2FF00B2"
    )
        port map (
      I0 => \^q\(2),
      I1 => \gen_pf_ic_rc.ram_empty_i_reg\(2),
      I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_2_n_0\,
      I3 => \gen_pf_ic_rc.ram_empty_i_reg\(3),
      I4 => \^q\(3),
      I5 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\,
      O => D(3)
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2FBFFFF0000A2FB"
    )
        port map (
      I0 => \^q\(0),
      I1 => rd_en,
      I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\,
      I3 => \gen_pf_ic_rc.ram_empty_i_reg\(0),
      I4 => \gen_pf_ic_rc.ram_empty_i_reg\(1),
      I5 => \^q\(1),
      O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_2_n_0\
    );
\gen_pf_ic_rc.ram_empty_i_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pf_ic_rc.ram_empty_i_reg\(3),
      I2 => \^q\(4),
      I3 => \gen_pf_ic_rc.ram_empty_i_reg\(4),
      O => \reg_out_i_reg[3]_0\
    );
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[4]_0\(0),
      Q => \^q\(0),
      R => \reg_out_i_reg[0]_0\
    );
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[4]_0\(1),
      Q => \^q\(1),
      R => \reg_out_i_reg[0]_0\
    );
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[4]_0\(2),
      Q => \^q\(2),
      R => \reg_out_i_reg[0]_0\
    );
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[4]_0\(3),
      Q => \^q\(3),
      R => \reg_out_i_reg[0]_0\
    );
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[4]_0\(4),
      Q => \^q\(4),
      R => \reg_out_i_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_reg_vec_154 is
  port (
    ram_full_i0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_0\ : in STD_LOGIC;
    \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    wrst_busy : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 4 downto 0 );
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_reg_vec_154 : entity is "xpm_fifo_reg_vec";
end design_1_Vsp_core_0_0_xpm_fifo_reg_vec_154;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_reg_vec_154 is
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_2_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5_n_0\ : STD_LOGIC;
begin
  Q(4 downto 0) <= \^q\(4 downto 0);
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8888888"
    )
        port map (
      I0 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_2_n_0\,
      I1 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\,
      I2 => E(0),
      I3 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_0\,
      I4 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5_n_0\,
      O => ram_full_i0
    );
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_2\(0),
      I2 => \^q\(4),
      I3 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_2\(1),
      O => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_2_n_0\
    );
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_1\(0),
      I2 => \^q\(4),
      I3 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_1\(1),
      O => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5_n_0\
    );
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(0),
      Q => \^q\(0),
      R => wrst_busy
    );
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(1),
      Q => \^q\(1),
      R => wrst_busy
    );
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(2),
      Q => \^q\(2),
      R => wrst_busy
    );
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(3),
      Q => \^q\(3),
      R => wrst_busy
    );
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(4),
      Q => \^q\(4),
      R => wrst_busy
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_reg_vec_156 is
  port (
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \reg_out_i_reg[3]_0\ : out STD_LOGIC;
    \gen_pf_ic_rc.ram_empty_i_reg\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\ : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \reg_out_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_reg_vec_156 : entity is "xpm_fifo_reg_vec";
end design_1_Vsp_core_0_0_xpm_fifo_reg_vec_156;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_reg_vec_156 is
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[2]_i_1\ : label is "soft_lutpair237";
  attribute SOFT_HLUTNM of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_1\ : label is "soft_lutpair237";
begin
  Q(4 downto 0) <= \^q\(4 downto 0);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6966"
    )
        port map (
      I0 => \^q\(0),
      I1 => \gen_pf_ic_rc.ram_empty_i_reg\(0),
      I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\,
      I3 => rd_en,
      O => D(0)
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_2_n_0\,
      I1 => \^q\(2),
      I2 => \gen_pf_ic_rc.ram_empty_i_reg\(2),
      O => D(1)
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4DB2B24D"
    )
        port map (
      I0 => \^q\(2),
      I1 => \gen_pf_ic_rc.ram_empty_i_reg\(2),
      I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_2_n_0\,
      I3 => \^q\(3),
      I4 => \gen_pf_ic_rc.ram_empty_i_reg\(3),
      O => D(2)
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4D00FF4DB2FF00B2"
    )
        port map (
      I0 => \^q\(2),
      I1 => \gen_pf_ic_rc.ram_empty_i_reg\(2),
      I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_2_n_0\,
      I3 => \gen_pf_ic_rc.ram_empty_i_reg\(3),
      I4 => \^q\(3),
      I5 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\,
      O => D(3)
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2FBFFFF0000A2FB"
    )
        port map (
      I0 => \^q\(0),
      I1 => rd_en,
      I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\,
      I3 => \gen_pf_ic_rc.ram_empty_i_reg\(0),
      I4 => \gen_pf_ic_rc.ram_empty_i_reg\(1),
      I5 => \^q\(1),
      O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[4]_i_2_n_0\
    );
\gen_pf_ic_rc.ram_empty_i_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \^q\(3),
      I1 => \gen_pf_ic_rc.ram_empty_i_reg\(3),
      I2 => \^q\(4),
      I3 => \gen_pf_ic_rc.ram_empty_i_reg\(4),
      O => \reg_out_i_reg[3]_0\
    );
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[4]_0\(0),
      Q => \^q\(0),
      R => SR(0)
    );
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[4]_0\(1),
      Q => \^q\(1),
      R => SR(0)
    );
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[4]_0\(2),
      Q => \^q\(2),
      R => SR(0)
    );
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[4]_0\(3),
      Q => \^q\(3),
      R => SR(0)
    );
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[4]_0\(4),
      Q => \^q\(4),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    wrst_busy : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 5 downto 0 );
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0\ : entity is "xpm_fifo_reg_vec";
end \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0\ is
begin
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(0),
      Q => Q(0),
      R => wrst_busy
    );
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(1),
      Q => Q(1),
      R => wrst_busy
    );
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(2),
      Q => Q(2),
      R => wrst_busy
    );
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(3),
      Q => Q(3),
      R => wrst_busy
    );
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(4),
      Q => Q(4),
      R => wrst_busy
    );
\reg_out_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(5),
      Q => Q(5),
      R => wrst_busy
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_126\ is
  port (
    O : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \reg_out_i_reg[0]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 5 downto 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_126\ : entity is "xpm_fifo_reg_vec";
end \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_126\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_126\ is
  signal \grdc.rd_data_count_i[5]_i_2_n_0\ : STD_LOGIC;
  signal \grdc.rd_data_count_i[5]_i_3_n_0\ : STD_LOGIC;
  signal \grdc.rd_data_count_i[5]_i_4_n_0\ : STD_LOGIC;
  signal \grdc.rd_data_count_i[5]_i_5_n_0\ : STD_LOGIC;
  signal \grdc.rd_data_count_i[5]_i_6_n_0\ : STD_LOGIC;
  signal \grdc.rd_data_count_i[5]_i_7_n_0\ : STD_LOGIC;
  signal \grdc.rd_data_count_i_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \grdc.rd_data_count_i_reg[5]_i_1_n_4\ : STD_LOGIC;
  signal \grdc.rd_data_count_i_reg[5]_i_1_n_5\ : STD_LOGIC;
  signal \grdc.rd_data_count_i_reg[5]_i_1_n_6\ : STD_LOGIC;
  signal \grdc.rd_data_count_i_reg[5]_i_1_n_7\ : STD_LOGIC;
  signal \reg_out_i_reg_n_0_[0]\ : STD_LOGIC;
  signal \reg_out_i_reg_n_0_[1]\ : STD_LOGIC;
  signal \reg_out_i_reg_n_0_[2]\ : STD_LOGIC;
  signal \reg_out_i_reg_n_0_[3]\ : STD_LOGIC;
  signal \reg_out_i_reg_n_0_[4]\ : STD_LOGIC;
  signal \reg_out_i_reg_n_0_[5]\ : STD_LOGIC;
  signal \NLW_grdc.rd_data_count_i_reg[5]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_grdc.rd_data_count_i_reg[5]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[5]_i_1\ : label is 35;
begin
\grdc.rd_data_count_i[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \reg_out_i_reg_n_0_[5]\,
      I1 => Q(5),
      O => \grdc.rd_data_count_i[5]_i_2_n_0\
    );
\grdc.rd_data_count_i[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \reg_out_i_reg_n_0_[4]\,
      I1 => Q(4),
      O => \grdc.rd_data_count_i[5]_i_3_n_0\
    );
\grdc.rd_data_count_i[5]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \reg_out_i_reg_n_0_[3]\,
      I1 => Q(3),
      O => \grdc.rd_data_count_i[5]_i_4_n_0\
    );
\grdc.rd_data_count_i[5]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \reg_out_i_reg_n_0_[2]\,
      I1 => Q(2),
      O => \grdc.rd_data_count_i[5]_i_5_n_0\
    );
\grdc.rd_data_count_i[5]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \reg_out_i_reg_n_0_[1]\,
      I1 => Q(1),
      O => \grdc.rd_data_count_i[5]_i_6_n_0\
    );
\grdc.rd_data_count_i[5]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \reg_out_i_reg_n_0_[0]\,
      I1 => Q(0),
      O => \grdc.rd_data_count_i[5]_i_7_n_0\
    );
\grdc.rd_data_count_i_reg[5]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_grdc.rd_data_count_i_reg[5]_i_1_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \grdc.rd_data_count_i_reg[5]_i_1_n_3\,
      CO(3) => \grdc.rd_data_count_i_reg[5]_i_1_n_4\,
      CO(2) => \grdc.rd_data_count_i_reg[5]_i_1_n_5\,
      CO(1) => \grdc.rd_data_count_i_reg[5]_i_1_n_6\,
      CO(0) => \grdc.rd_data_count_i_reg[5]_i_1_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \reg_out_i_reg_n_0_[4]\,
      DI(3) => \reg_out_i_reg_n_0_[3]\,
      DI(2) => \reg_out_i_reg_n_0_[2]\,
      DI(1) => \reg_out_i_reg_n_0_[1]\,
      DI(0) => \reg_out_i_reg_n_0_[0]\,
      O(7 downto 6) => \NLW_grdc.rd_data_count_i_reg[5]_i_1_O_UNCONNECTED\(7 downto 6),
      O(5) => O(0),
      O(4 downto 0) => \NLW_grdc.rd_data_count_i_reg[5]_i_1_O_UNCONNECTED\(4 downto 0),
      S(7 downto 6) => B"00",
      S(5) => \grdc.rd_data_count_i[5]_i_2_n_0\,
      S(4) => \grdc.rd_data_count_i[5]_i_3_n_0\,
      S(3) => \grdc.rd_data_count_i[5]_i_4_n_0\,
      S(2) => \grdc.rd_data_count_i[5]_i_5_n_0\,
      S(1) => \grdc.rd_data_count_i[5]_i_6_n_0\,
      S(0) => \grdc.rd_data_count_i[5]_i_7_n_0\
    );
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => D(0),
      Q => \reg_out_i_reg_n_0_[0]\,
      R => \reg_out_i_reg[0]_0\
    );
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => D(1),
      Q => \reg_out_i_reg_n_0_[1]\,
      R => \reg_out_i_reg[0]_0\
    );
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => D(2),
      Q => \reg_out_i_reg_n_0_[2]\,
      R => \reg_out_i_reg[0]_0\
    );
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => D(3),
      Q => \reg_out_i_reg_n_0_[3]\,
      R => \reg_out_i_reg[0]_0\
    );
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => D(4),
      Q => \reg_out_i_reg_n_0_[4]\,
      R => \reg_out_i_reg[0]_0\
    );
\reg_out_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => D(5),
      Q => \reg_out_i_reg_n_0_[5]\,
      R => \reg_out_i_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_155\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    wrst_busy : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 5 downto 0 );
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_155\ : entity is "xpm_fifo_reg_vec";
end \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_155\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_155\ is
begin
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(0),
      Q => Q(0),
      R => wrst_busy
    );
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(1),
      Q => Q(1),
      R => wrst_busy
    );
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(2),
      Q => Q(2),
      R => wrst_busy
    );
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(3),
      Q => Q(3),
      R => wrst_busy
    );
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(4),
      Q => Q(4),
      R => wrst_busy
    );
\reg_out_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => D(5),
      Q => Q(5),
      R => wrst_busy
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_157\ is
  port (
    D : out STD_LOGIC_VECTOR ( 4 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \reg_out_i_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_157\ : entity is "xpm_fifo_reg_vec";
end \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_157\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_157\ is
  signal \grdc.rd_data_count_i[5]_i_2_n_0\ : STD_LOGIC;
  signal \grdc.rd_data_count_i[5]_i_3_n_0\ : STD_LOGIC;
  signal \grdc.rd_data_count_i[5]_i_4_n_0\ : STD_LOGIC;
  signal \grdc.rd_data_count_i[5]_i_5_n_0\ : STD_LOGIC;
  signal \grdc.rd_data_count_i[5]_i_6_n_0\ : STD_LOGIC;
  signal \grdc.rd_data_count_i[5]_i_7_n_0\ : STD_LOGIC;
  signal \grdc.rd_data_count_i_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \grdc.rd_data_count_i_reg[5]_i_1_n_4\ : STD_LOGIC;
  signal \grdc.rd_data_count_i_reg[5]_i_1_n_5\ : STD_LOGIC;
  signal \grdc.rd_data_count_i_reg[5]_i_1_n_6\ : STD_LOGIC;
  signal \grdc.rd_data_count_i_reg[5]_i_1_n_7\ : STD_LOGIC;
  signal \reg_out_i_reg_n_0_[0]\ : STD_LOGIC;
  signal \reg_out_i_reg_n_0_[1]\ : STD_LOGIC;
  signal \reg_out_i_reg_n_0_[2]\ : STD_LOGIC;
  signal \reg_out_i_reg_n_0_[3]\ : STD_LOGIC;
  signal \reg_out_i_reg_n_0_[4]\ : STD_LOGIC;
  signal \reg_out_i_reg_n_0_[5]\ : STD_LOGIC;
  signal \NLW_grdc.rd_data_count_i_reg[5]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_grdc.rd_data_count_i_reg[5]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[5]_i_1\ : label is 35;
begin
\grdc.rd_data_count_i[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \reg_out_i_reg_n_0_[5]\,
      I1 => Q(5),
      O => \grdc.rd_data_count_i[5]_i_2_n_0\
    );
\grdc.rd_data_count_i[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \reg_out_i_reg_n_0_[4]\,
      I1 => Q(4),
      O => \grdc.rd_data_count_i[5]_i_3_n_0\
    );
\grdc.rd_data_count_i[5]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \reg_out_i_reg_n_0_[3]\,
      I1 => Q(3),
      O => \grdc.rd_data_count_i[5]_i_4_n_0\
    );
\grdc.rd_data_count_i[5]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \reg_out_i_reg_n_0_[2]\,
      I1 => Q(2),
      O => \grdc.rd_data_count_i[5]_i_5_n_0\
    );
\grdc.rd_data_count_i[5]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \reg_out_i_reg_n_0_[1]\,
      I1 => Q(1),
      O => \grdc.rd_data_count_i[5]_i_6_n_0\
    );
\grdc.rd_data_count_i[5]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \reg_out_i_reg_n_0_[0]\,
      I1 => Q(0),
      O => \grdc.rd_data_count_i[5]_i_7_n_0\
    );
\grdc.rd_data_count_i_reg[5]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_grdc.rd_data_count_i_reg[5]_i_1_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \grdc.rd_data_count_i_reg[5]_i_1_n_3\,
      CO(3) => \grdc.rd_data_count_i_reg[5]_i_1_n_4\,
      CO(2) => \grdc.rd_data_count_i_reg[5]_i_1_n_5\,
      CO(1) => \grdc.rd_data_count_i_reg[5]_i_1_n_6\,
      CO(0) => \grdc.rd_data_count_i_reg[5]_i_1_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \reg_out_i_reg_n_0_[4]\,
      DI(3) => \reg_out_i_reg_n_0_[3]\,
      DI(2) => \reg_out_i_reg_n_0_[2]\,
      DI(1) => \reg_out_i_reg_n_0_[1]\,
      DI(0) => \reg_out_i_reg_n_0_[0]\,
      O(7 downto 6) => \NLW_grdc.rd_data_count_i_reg[5]_i_1_O_UNCONNECTED\(7 downto 6),
      O(5 downto 1) => D(4 downto 0),
      O(0) => \NLW_grdc.rd_data_count_i_reg[5]_i_1_O_UNCONNECTED\(0),
      S(7 downto 6) => B"00",
      S(5) => \grdc.rd_data_count_i[5]_i_2_n_0\,
      S(4) => \grdc.rd_data_count_i[5]_i_3_n_0\,
      S(3) => \grdc.rd_data_count_i[5]_i_4_n_0\,
      S(2) => \grdc.rd_data_count_i[5]_i_5_n_0\,
      S(1) => \grdc.rd_data_count_i[5]_i_6_n_0\,
      S(0) => \grdc.rd_data_count_i[5]_i_7_n_0\
    );
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[5]_0\(0),
      Q => \reg_out_i_reg_n_0_[0]\,
      R => SR(0)
    );
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[5]_0\(1),
      Q => \reg_out_i_reg_n_0_[1]\,
      R => SR(0)
    );
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[5]_0\(2),
      Q => \reg_out_i_reg_n_0_[2]\,
      R => SR(0)
    );
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[5]_0\(3),
      Q => \reg_out_i_reg_n_0_[3]\,
      R => SR(0)
    );
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[5]_0\(4),
      Q => \reg_out_i_reg_n_0_[4]\,
      R => SR(0)
    );
\reg_out_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \reg_out_i_reg[5]_0\(5),
      Q => \reg_out_i_reg_n_0_[5]\,
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_rst is
  port (
    \gen_pntr_flags_cc.ram_empty_i_reg\ : out STD_LOGIC;
    ram_wr_en_pf : out STD_LOGIC;
    \gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    rst : in STD_LOGIC;
    ram_empty_i : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    wr_en : in STD_LOGIC;
    \count_value_i_reg[10]\ : in STD_LOGIC;
    rst_d1 : in STD_LOGIC;
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_rst : entity is "xpm_fifo_rst";
end design_1_Vsp_core_0_0_xpm_fifo_rst;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_rst is
  signal \gen_rst_cc.fifo_wr_rst_cc\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal p_0_in : STD_LOGIC;
  signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC;
  signal \^ram_wr_en_pf\ : STD_LOGIC;
  signal rst_i : STD_LOGIC;
begin
  \gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\(0) <= \^gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\(0);
  ram_wr_en_pf <= \^ram_wr_en_pf\;
\gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00005455"
    )
        port map (
      I0 => ram_empty_i,
      I1 => rd_en,
      I2 => Q(0),
      I3 => Q(1),
      I4 => \^ram_wr_en_pf\,
      O => \gen_pntr_flags_cc.ram_empty_i_reg\
    );
\gen_rst_cc.fifo_wr_rst_cc[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in,
      I1 => rst,
      O => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => '0',
      Q => \gen_rst_cc.fifo_wr_rst_cc\(0),
      S => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_rst_cc.fifo_wr_rst_cc\(0),
      Q => \gen_rst_cc.fifo_wr_rst_cc\(1),
      S => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_rst_cc.fifo_wr_rst_cc\(1),
      Q => \^gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\(0),
      S => rst_i
    );
\gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => wr_en,
      I1 => \count_value_i_reg[10]\,
      I2 => \^gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\(0),
      I3 => rst_d1,
      O => \^ram_wr_en_pf\
    );
\power_on_rst_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => '0',
      Q => \power_on_rst_reg_n_0_[0]\,
      R => '0'
    );
\power_on_rst_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \power_on_rst_reg_n_0_[0]\,
      Q => p_0_in,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_rst_135 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    wr_en : in STD_LOGIC;
    \count_value_i_reg[3]\ : in STD_LOGIC;
    rst_d1 : in STD_LOGIC;
    rst : in STD_LOGIC;
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_rst_135 : entity is "xpm_fifo_rst";
end design_1_Vsp_core_0_0_xpm_fifo_rst_135;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_rst_135 is
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \gen_rst_cc.fifo_wr_rst_cc\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal p_0_in : STD_LOGIC;
  signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC;
  signal rst_i : STD_LOGIC;
begin
  Q(0) <= \^q\(0);
\gen_rst_cc.fifo_wr_rst_cc[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in,
      I1 => rst,
      O => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => '0',
      Q => \gen_rst_cc.fifo_wr_rst_cc\(0),
      S => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_rst_cc.fifo_wr_rst_cc\(0),
      Q => \gen_rst_cc.fifo_wr_rst_cc\(1),
      S => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_rst_cc.fifo_wr_rst_cc\(1),
      Q => \^q\(0),
      S => rst_i
    );
\gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => wr_en,
      I1 => \count_value_i_reg[3]\,
      I2 => \^q\(0),
      I3 => rst_d1,
      O => E(0)
    );
\power_on_rst_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => '0',
      Q => \power_on_rst_reg_n_0_[0]\,
      R => '0'
    );
\power_on_rst_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \power_on_rst_reg_n_0_[0]\,
      Q => p_0_in,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_rst_141 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    wr_en : in STD_LOGIC;
    \count_value_i_reg[3]\ : in STD_LOGIC;
    rst_d1 : in STD_LOGIC;
    rst : in STD_LOGIC;
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_rst_141 : entity is "xpm_fifo_rst";
end design_1_Vsp_core_0_0_xpm_fifo_rst_141;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_rst_141 is
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \gen_rst_cc.fifo_wr_rst_cc\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal p_0_in : STD_LOGIC;
  signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC;
  signal rst_i : STD_LOGIC;
begin
  Q(0) <= \^q\(0);
\gen_rst_cc.fifo_wr_rst_cc[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in,
      I1 => rst,
      O => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => '0',
      Q => \gen_rst_cc.fifo_wr_rst_cc\(0),
      S => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_rst_cc.fifo_wr_rst_cc\(0),
      Q => \gen_rst_cc.fifo_wr_rst_cc\(1),
      S => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_rst_cc.fifo_wr_rst_cc\(1),
      Q => \^q\(0),
      S => rst_i
    );
\gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => wr_en,
      I1 => \count_value_i_reg[3]\,
      I2 => \^q\(0),
      I3 => rst_d1,
      O => E(0)
    );
\power_on_rst_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => '0',
      Q => \power_on_rst_reg_n_0_[0]\,
      R => '0'
    );
\power_on_rst_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \power_on_rst_reg_n_0_[0]\,
      Q => p_0_in,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_rst_147 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    wr_en : in STD_LOGIC;
    \count_value_i_reg[3]\ : in STD_LOGIC;
    rst_d1 : in STD_LOGIC;
    rst : in STD_LOGIC;
    rd_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_rst_147 : entity is "xpm_fifo_rst";
end design_1_Vsp_core_0_0_xpm_fifo_rst_147;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_rst_147 is
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \gen_rst_cc.fifo_wr_rst_cc\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal p_0_in : STD_LOGIC;
  signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC;
  signal rst_i : STD_LOGIC;
begin
  Q(0) <= \^q\(0);
\gen_rst_cc.fifo_wr_rst_cc[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in,
      I1 => rst,
      O => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => '0',
      Q => \gen_rst_cc.fifo_wr_rst_cc\(0),
      S => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_rst_cc.fifo_wr_rst_cc\(0),
      Q => \gen_rst_cc.fifo_wr_rst_cc\(1),
      S => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_rst_cc.fifo_wr_rst_cc\(1),
      Q => \^q\(0),
      S => rst_i
    );
\gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => wr_en,
      I1 => \count_value_i_reg[3]\,
      I2 => \^q\(0),
      I3 => rst_d1,
      O => E(0)
    );
\power_on_rst_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => '0',
      Q => \power_on_rst_reg_n_0_[0]\,
      R => '0'
    );
\power_on_rst_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \power_on_rst_reg_n_0_[0]\,
      Q => p_0_in,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_rst_153 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    wr_en : in STD_LOGIC;
    \count_value_i_reg[3]\ : in STD_LOGIC;
    rst_d1 : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_rst_153 : entity is "xpm_fifo_rst";
end design_1_Vsp_core_0_0_xpm_fifo_rst_153;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_rst_153 is
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \gen_rst_cc.fifo_wr_rst_cc\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal p_0_in : STD_LOGIC;
  signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC;
  signal rst_i : STD_LOGIC;
begin
  Q(0) <= \^q\(0);
\gen_rst_cc.fifo_wr_rst_cc[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in,
      I1 => rst,
      O => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => '0',
      Q => \gen_rst_cc.fifo_wr_rst_cc\(0),
      S => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \gen_rst_cc.fifo_wr_rst_cc\(0),
      Q => \gen_rst_cc.fifo_wr_rst_cc\(1),
      S => rst_i
    );
\gen_rst_cc.fifo_wr_rst_cc_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \gen_rst_cc.fifo_wr_rst_cc\(1),
      Q => \^q\(0),
      S => rst_i
    );
\gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => wr_en,
      I1 => \count_value_i_reg[3]\,
      I2 => \^q\(0),
      I3 => rst_d1,
      O => E(0)
    );
\power_on_rst_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => '0',
      Q => \power_on_rst_reg_n_0_[0]\,
      R => '0'
    );
\power_on_rst_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \power_on_rst_reg_n_0_[0]\,
      Q => p_0_in,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_memory_base is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 4;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 4;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of design_1_Vsp_core_0_0_xpm_memory_base : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of design_1_Vsp_core_0_0_xpm_memory_base : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of design_1_Vsp_core_0_0_xpm_memory_base : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of design_1_Vsp_core_0_0_xpm_memory_base : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of design_1_Vsp_core_0_0_xpm_memory_base : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of design_1_Vsp_core_0_0_xpm_memory_base : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of design_1_Vsp_core_0_0_xpm_memory_base : entity is 192;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of design_1_Vsp_core_0_0_xpm_memory_base : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_memory_base : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of design_1_Vsp_core_0_0_xpm_memory_base : entity is 16;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of design_1_Vsp_core_0_0_xpm_memory_base : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : string;
  attribute P_MEMORY_PRIMITIVE of design_1_Vsp_core_0_0_xpm_memory_base : entity is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of design_1_Vsp_core_0_0_xpm_memory_base : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of design_1_Vsp_core_0_0_xpm_memory_base : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 4;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 4;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 4;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 4;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of design_1_Vsp_core_0_0_xpm_memory_base : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 2;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of design_1_Vsp_core_0_0_xpm_memory_base : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of design_1_Vsp_core_0_0_xpm_memory_base : entity is 2;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of design_1_Vsp_core_0_0_xpm_memory_base : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of design_1_Vsp_core_0_0_xpm_memory_base : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of design_1_Vsp_core_0_0_xpm_memory_base : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of design_1_Vsp_core_0_0_xpm_memory_base : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of design_1_Vsp_core_0_0_xpm_memory_base : entity is 12;
end design_1_Vsp_core_0_0_xpm_memory_base;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_memory_base is
  signal \<const0>\ : STD_LOGIC;
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOG_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[0]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[10]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[11]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[1]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[2]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[3]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[4]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[5]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[7]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[8]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[9]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 192;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 15;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 11;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(0),
      Q => doutb(0),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(10),
      Q => doutb(10),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(11),
      Q => doutb(11),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(1),
      Q => doutb(1),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(2),
      Q => doutb(2),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(3),
      Q => doutb(3),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(4),
      Q => doutb(4),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(5),
      Q => doutb(5),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(6),
      Q => doutb(6),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(7),
      Q => doutb(7),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(8),
      Q => doutb(8),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(9),
      Q => doutb(9),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(0),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(0),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(10),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(10),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(11),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(11),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(1),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(1),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(2),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(2),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(3),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(3),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(4),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(4),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(5),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(5),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(6),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(6),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(7),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(7),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(8),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(8),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(9),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(9),
      R => '0'
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => addrb(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => addrb(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => addrb(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => addrb(3 downto 0),
      ADDRE(4) => '0',
      ADDRE(3 downto 0) => addrb(3 downto 0),
      ADDRF(4) => '0',
      ADDRF(3 downto 0) => addrb(3 downto 0),
      ADDRG(4) => '0',
      ADDRG(3 downto 0) => addrb(3 downto 0),
      ADDRH(4) => '0',
      ADDRH(3 downto 0) => addra(3 downto 0),
      DIA(1 downto 0) => dina(1 downto 0),
      DIB(1 downto 0) => dina(3 downto 2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1 downto 0) => dina(7 downto 6),
      DIE(1 downto 0) => dina(9 downto 8),
      DIF(1 downto 0) => dina(11 downto 10),
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(1 downto 0),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(3 downto 2),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(5 downto 4),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(7 downto 6),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(9 downto 8),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(11 downto 10),
      DOG(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOG_UNCONNECTED\(1 downto 0),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => ena
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_memory_base__4\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 4;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 4;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 192;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 16;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : string;
  attribute P_MEMORY_PRIMITIVE of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 4;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 4;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 4;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 4;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 2;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 2;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \design_1_Vsp_core_0_0_xpm_memory_base__4\ : entity is 12;
end \design_1_Vsp_core_0_0_xpm_memory_base__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_memory_base__4\ is
  signal \<const0>\ : STD_LOGIC;
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOG_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[0]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[10]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[11]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[1]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[2]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[3]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[4]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[5]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[7]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[8]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[9]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 192;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 15;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 11;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(0),
      Q => doutb(0),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(10),
      Q => doutb(10),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(11),
      Q => doutb(11),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(1),
      Q => doutb(1),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(2),
      Q => doutb(2),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(3),
      Q => doutb(3),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(4),
      Q => doutb(4),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(5),
      Q => doutb(5),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(6),
      Q => doutb(6),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(7),
      Q => doutb(7),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(8),
      Q => doutb(8),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(9),
      Q => doutb(9),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(0),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(0),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(10),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(10),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(11),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(11),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(1),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(1),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(2),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(2),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(3),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(3),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(4),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(4),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(5),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(5),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(6),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(6),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(7),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(7),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(8),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(8),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(9),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(9),
      R => '0'
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => addrb(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => addrb(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => addrb(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => addrb(3 downto 0),
      ADDRE(4) => '0',
      ADDRE(3 downto 0) => addrb(3 downto 0),
      ADDRF(4) => '0',
      ADDRF(3 downto 0) => addrb(3 downto 0),
      ADDRG(4) => '0',
      ADDRG(3 downto 0) => addrb(3 downto 0),
      ADDRH(4) => '0',
      ADDRH(3 downto 0) => addra(3 downto 0),
      DIA(1 downto 0) => dina(1 downto 0),
      DIB(1 downto 0) => dina(3 downto 2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1 downto 0) => dina(7 downto 6),
      DIE(1 downto 0) => dina(9 downto 8),
      DIF(1 downto 0) => dina(11 downto 10),
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(1 downto 0),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(3 downto 2),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(5 downto 4),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(7 downto 6),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(9 downto 8),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(11 downto 10),
      DOG(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOG_UNCONNECTED\(1 downto 0),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => ena
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_memory_base__5\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 4;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 4;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 192;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 16;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : string;
  attribute P_MEMORY_PRIMITIVE of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 4;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 4;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 4;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 4;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 2;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 2;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \design_1_Vsp_core_0_0_xpm_memory_base__5\ : entity is 12;
end \design_1_Vsp_core_0_0_xpm_memory_base__5\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_memory_base__5\ is
  signal \<const0>\ : STD_LOGIC;
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOG_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[0]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[10]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[11]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[1]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[2]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[3]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[4]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[5]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[7]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[8]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[9]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 192;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 15;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 11;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(0),
      Q => doutb(0),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(10),
      Q => doutb(10),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(11),
      Q => doutb(11),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(1),
      Q => doutb(1),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(2),
      Q => doutb(2),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(3),
      Q => doutb(3),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(4),
      Q => doutb(4),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(5),
      Q => doutb(5),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(6),
      Q => doutb(6),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(7),
      Q => doutb(7),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(8),
      Q => doutb(8),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(9),
      Q => doutb(9),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(0),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(0),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(10),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(10),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(11),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(11),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(1),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(1),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(2),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(2),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(3),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(3),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(4),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(4),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(5),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(5),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(6),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(6),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(7),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(7),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(8),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(8),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(9),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(9),
      R => '0'
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => addrb(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => addrb(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => addrb(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => addrb(3 downto 0),
      ADDRE(4) => '0',
      ADDRE(3 downto 0) => addrb(3 downto 0),
      ADDRF(4) => '0',
      ADDRF(3 downto 0) => addrb(3 downto 0),
      ADDRG(4) => '0',
      ADDRG(3 downto 0) => addrb(3 downto 0),
      ADDRH(4) => '0',
      ADDRH(3 downto 0) => addra(3 downto 0),
      DIA(1 downto 0) => dina(1 downto 0),
      DIB(1 downto 0) => dina(3 downto 2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1 downto 0) => dina(7 downto 6),
      DIE(1 downto 0) => dina(9 downto 8),
      DIF(1 downto 0) => dina(11 downto 10),
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(1 downto 0),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(3 downto 2),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(5 downto 4),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(7 downto 6),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(9 downto 8),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(11 downto 10),
      DOG(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOG_UNCONNECTED\(1 downto 0),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => ena
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_memory_base__6\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 4;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 4;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 192;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 16;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : string;
  attribute P_MEMORY_PRIMITIVE of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 4;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 4;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 4;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 4;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 2;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 2;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \design_1_Vsp_core_0_0_xpm_memory_base__6\ : entity is 12;
end \design_1_Vsp_core_0_0_xpm_memory_base__6\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_memory_base__6\ is
  signal \<const0>\ : STD_LOGIC;
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOG_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[0]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[10]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[11]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[1]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[2]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[3]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[4]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[5]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[7]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[8]\ : label is "no";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[9]\ : label is "no";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 192;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 15;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\ : label is 11;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(0),
      Q => doutb(0),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(10),
      Q => doutb(10),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(11),
      Q => doutb(11),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(1),
      Q => doutb(1),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(2),
      Q => doutb(2),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(3),
      Q => doutb(3),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(4),
      Q => doutb(4),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(5),
      Q => doutb(5),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(6),
      Q => doutb(6),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(7),
      Q => doutb(7),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(8),
      Q => doutb(8),
      R => rstb
    );
\gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => regceb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(9),
      Q => doutb(9),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(0),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(0),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(10),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(10),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(11),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(11),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(1),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(1),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(2),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(2),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(3),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(3),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(4),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(4),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(5),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(5),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(6),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(6),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(7),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(7),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(8),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(8),
      R => '0'
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clka,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(9),
      Q => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg\(9),
      R => '0'
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4) => '0',
      ADDRA(3 downto 0) => addrb(3 downto 0),
      ADDRB(4) => '0',
      ADDRB(3 downto 0) => addrb(3 downto 0),
      ADDRC(4) => '0',
      ADDRC(3 downto 0) => addrb(3 downto 0),
      ADDRD(4) => '0',
      ADDRD(3 downto 0) => addrb(3 downto 0),
      ADDRE(4) => '0',
      ADDRE(3 downto 0) => addrb(3 downto 0),
      ADDRF(4) => '0',
      ADDRF(3 downto 0) => addrb(3 downto 0),
      ADDRG(4) => '0',
      ADDRG(3 downto 0) => addrb(3 downto 0),
      ADDRH(4) => '0',
      ADDRH(3 downto 0) => addra(3 downto 0),
      DIA(1 downto 0) => dina(1 downto 0),
      DIB(1 downto 0) => dina(3 downto 2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1 downto 0) => dina(7 downto 6),
      DIE(1 downto 0) => dina(9 downto 8),
      DIF(1 downto 0) => dina(11 downto 10),
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(1 downto 0),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(3 downto 2),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(5 downto 4),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(7 downto 6),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(9 downto 8),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0\(11 downto 10),
      DOG(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOG_UNCONNECTED\(1 downto 0),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_0_11_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => ena
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 67 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 67 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 67 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 67 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 11;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 11;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 2;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 139264;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 2048;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : string;
  attribute P_MEMORY_PRIMITIVE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "block";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "no";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 11;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 11;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 11;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 11;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 2;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 2;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 2;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ : entity is 68;
end \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\ is
  signal \<const0>\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_1_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_2_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_3_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_1\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_136\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_137\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_138\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_139\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_36\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_37\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_38\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_39\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_40\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_41\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_42\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_43\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_44\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_45\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_46\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_47\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_48\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_49\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_50\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_51\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_52\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_53\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_54\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_55\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_56\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_57\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_58\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_59\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_60\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_61\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_62\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_63\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_64\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_65\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_66\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_67\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_1_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_2_n_0\ : STD_LOGIC;
  signal \gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_3_n_0\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_CASDOUTA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_CASDOUTPA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_DOUTADOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_DOUTBDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_DOUTPADOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_DOUTPBDOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_CASOUTDBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_CASOUTSBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_CASDOUTA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_CASDOUTB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_CASDOUTPA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_CASDOUTPB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_DOUTADOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_DOUTPADOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_CASOUTDBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_CASOUTSBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_CASDOUTA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_CASDOUTB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_CASDOUTPA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_CASDOUTPB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_DOUTADOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_DOUTBDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_DOUTPADOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_DOUTPBDOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_CASOUTDBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_CASOUTSBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_CASDOUTA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_CASDOUTB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_CASDOUTPA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_CASDOUTPB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_DOUTADOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_DOUTBDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 14 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_DOUTPADOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_DOUTPBDOUTP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer;
  attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is 0;
  attribute \MEM.PORTA.ADDRESS_END\ : integer;
  attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is 1023;
  attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
  attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is "p4_d32";
  attribute \MEM.PORTA.DATA_LSB\ : integer;
  attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is 0;
  attribute \MEM.PORTA.DATA_MSB\ : integer;
  attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is 35;
  attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer;
  attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is 0;
  attribute \MEM.PORTB.ADDRESS_END\ : integer;
  attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is 1023;
  attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string;
  attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is "p4_d32";
  attribute \MEM.PORTB.DATA_LSB\ : integer;
  attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is 0;
  attribute \MEM.PORTB.DATA_MSB\ : integer;
  attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is "";
  attribute RDADDR_COLLISION_HWCONFIG : string;
  attribute RDADDR_COLLISION_HWCONFIG of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is "DELAYED_WRITE";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is 139264;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is "block";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is 1023;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_bram_0\ : label is 35;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_2\ : label is "soft_lutpair321";
  attribute SOFT_HLUTNM of \gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_3\ : label is "soft_lutpair320";
  attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is 1024;
  attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is 2047;
  attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is "p4_d32";
  attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is 0;
  attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is 35;
  attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is 1024;
  attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is 2047;
  attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is "p4_d32";
  attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is 0;
  attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is "";
  attribute RDADDR_COLLISION_HWCONFIG of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is "DELAYED_WRITE";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is 139264;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is "block";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is 1024;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is 2047;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is 0;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_bram_1\ : label is 35;
  attribute SOFT_HLUTNM of \gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_2\ : label is "soft_lutpair321";
  attribute SOFT_HLUTNM of \gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_3\ : label is "soft_lutpair320";
  attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is 0;
  attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is 2047;
  attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is "p2_d16";
  attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is 36;
  attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is 53;
  attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is 0;
  attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is 2047;
  attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is "p2_d16";
  attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is 36;
  attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is 53;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is "";
  attribute RDADDR_COLLISION_HWCONFIG of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is "DELAYED_WRITE";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is 139264;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is "block";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is 2047;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is 36;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_bram_2\ : label is 53;
  attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is 0;
  attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is 2047;
  attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is "p0_d14";
  attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is 54;
  attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is 67;
  attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is 0;
  attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is 2047;
  attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is "p0_d14";
  attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is 54;
  attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is 67;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is "";
  attribute RDADDR_COLLISION_HWCONFIG of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is "DELAYED_WRITE";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is 139264;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is "block";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is "RAM_SDP";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is 2047;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is 54;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_bram_3\ : label is 67;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(67) <= \<const0>\;
  douta(66) <= \<const0>\;
  douta(65) <= \<const0>\;
  douta(64) <= \<const0>\;
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_wr_a.gen_word_narrow.mem_reg_bram_0\: unisim.vcomponents.RAMB36E2
    generic map(
      CASCADE_ORDER_A => "NONE",
      CASCADE_ORDER_B => "FIRST",
      CLOCK_DOMAINS => "COMMON",
      DOA_REG => 0,
      DOB_REG => 0,
      ENADDRENA => "FALSE",
      ENADDRENB => "FALSE",
      EN_ECC_PIPE => "FALSE",
      EN_ECC_READ => "FALSE",
      EN_ECC_WRITE => "FALSE",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      RDADDRCHANGEA => "FALSE",
      RDADDRCHANGEB => "FALSE",
      READ_WIDTH_A => 36,
      READ_WIDTH_B => 36,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SLEEP_ASYNC => "FALSE",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "NO_CHANGE",
      WRITE_WIDTH_A => 36,
      WRITE_WIDTH_B => 36
    )
        port map (
      ADDRARDADDR(14 downto 5) => addra(9 downto 0),
      ADDRARDADDR(4 downto 0) => B"00000",
      ADDRBWRADDR(14 downto 5) => addrb(9 downto 0),
      ADDRBWRADDR(4 downto 0) => B"00000",
      ADDRENA => '1',
      ADDRENB => '1',
      CASDIMUXA => '0',
      CASDIMUXB => '0',
      CASDINA(31 downto 0) => B"00000000000000000000000000000000",
      CASDINB(31 downto 0) => B"00000000000000000000000000000000",
      CASDINPA(3 downto 0) => B"0000",
      CASDINPB(3 downto 0) => B"0000",
      CASDOMUXA => '0',
      CASDOMUXB => '0',
      CASDOMUXEN_A => '1',
      CASDOMUXEN_B => '1',
      CASDOUTA(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_CASDOUTA_UNCONNECTED\(31 downto 0),
      CASDOUTB(31) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_36\,
      CASDOUTB(30) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_37\,
      CASDOUTB(29) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_38\,
      CASDOUTB(28) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_39\,
      CASDOUTB(27) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_40\,
      CASDOUTB(26) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_41\,
      CASDOUTB(25) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_42\,
      CASDOUTB(24) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_43\,
      CASDOUTB(23) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_44\,
      CASDOUTB(22) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_45\,
      CASDOUTB(21) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_46\,
      CASDOUTB(20) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_47\,
      CASDOUTB(19) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_48\,
      CASDOUTB(18) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_49\,
      CASDOUTB(17) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_50\,
      CASDOUTB(16) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_51\,
      CASDOUTB(15) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_52\,
      CASDOUTB(14) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_53\,
      CASDOUTB(13) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_54\,
      CASDOUTB(12) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_55\,
      CASDOUTB(11) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_56\,
      CASDOUTB(10) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_57\,
      CASDOUTB(9) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_58\,
      CASDOUTB(8) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_59\,
      CASDOUTB(7) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_60\,
      CASDOUTB(6) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_61\,
      CASDOUTB(5) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_62\,
      CASDOUTB(4) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_63\,
      CASDOUTB(3) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_64\,
      CASDOUTB(2) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_65\,
      CASDOUTB(1) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_66\,
      CASDOUTB(0) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_67\,
      CASDOUTPA(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_CASDOUTPA_UNCONNECTED\(3 downto 0),
      CASDOUTPB(3) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_136\,
      CASDOUTPB(2) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_137\,
      CASDOUTPB(1) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_138\,
      CASDOUTPB(0) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_139\,
      CASINDBITERR => '0',
      CASINSBITERR => '0',
      CASOREGIMUXA => '0',
      CASOREGIMUXB => '0',
      CASOREGIMUXEN_A => '1',
      CASOREGIMUXEN_B => '1',
      CASOUTDBITERR => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_0\,
      CASOUTSBITERR => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_1\,
      CLKARDCLK => clka,
      CLKBWRCLK => clka,
      DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_DBITERR_UNCONNECTED\,
      DINADIN(31 downto 0) => dina(31 downto 0),
      DINBDIN(31 downto 0) => B"11111111111111111111111111111111",
      DINPADINP(3 downto 0) => dina(35 downto 32),
      DINPBDINP(3 downto 0) => B"1111",
      DOUTADOUT(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_DOUTADOUT_UNCONNECTED\(31 downto 0),
      DOUTBDOUT(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_DOUTBDOUT_UNCONNECTED\(31 downto 0),
      DOUTPADOUTP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_DOUTPADOUTP_UNCONNECTED\(3 downto 0),
      DOUTPBDOUTP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_DOUTPBDOUTP_UNCONNECTED\(3 downto 0),
      ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_ECCPARITY_UNCONNECTED\(7 downto 0),
      ECCPIPECE => '1',
      ENARDEN => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_1_n_0\,
      ENBWREN => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_2_n_0\,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '1',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_0_SBITERR_UNCONNECTED\,
      SLEEP => '0',
      WEA(3) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_3_n_0\,
      WEA(2) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_3_n_0\,
      WEA(1) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_3_n_0\,
      WEA(0) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_3_n_0\,
      WEBWE(7 downto 0) => B"00000000"
    );
\gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => addra(10),
      O => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_1_n_0\
    );
\gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => enb,
      I1 => addrb(10),
      O => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_2_n_0\
    );
\gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wea(0),
      I1 => addra(10),
      O => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_i_3_n_0\
    );
\gen_wr_a.gen_word_narrow.mem_reg_bram_1\: unisim.vcomponents.RAMB36E2
    generic map(
      CASCADE_ORDER_A => "NONE",
      CASCADE_ORDER_B => "LAST",
      CLOCK_DOMAINS => "COMMON",
      DOA_REG => 0,
      DOB_REG => 1,
      ENADDRENA => "FALSE",
      ENADDRENB => "FALSE",
      EN_ECC_PIPE => "FALSE",
      EN_ECC_READ => "FALSE",
      EN_ECC_WRITE => "FALSE",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      RDADDRCHANGEA => "FALSE",
      RDADDRCHANGEB => "FALSE",
      READ_WIDTH_A => 36,
      READ_WIDTH_B => 36,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SLEEP_ASYNC => "FALSE",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "NO_CHANGE",
      WRITE_WIDTH_A => 36,
      WRITE_WIDTH_B => 36
    )
        port map (
      ADDRARDADDR(14 downto 5) => addra(9 downto 0),
      ADDRARDADDR(4 downto 0) => B"00000",
      ADDRBWRADDR(14 downto 5) => addrb(9 downto 0),
      ADDRBWRADDR(4 downto 0) => B"00000",
      ADDRENA => '1',
      ADDRENB => '1',
      CASDIMUXA => '0',
      CASDIMUXB => '0',
      CASDINA(31 downto 0) => B"00000000000000000000000000000000",
      CASDINB(31) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_36\,
      CASDINB(30) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_37\,
      CASDINB(29) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_38\,
      CASDINB(28) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_39\,
      CASDINB(27) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_40\,
      CASDINB(26) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_41\,
      CASDINB(25) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_42\,
      CASDINB(24) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_43\,
      CASDINB(23) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_44\,
      CASDINB(22) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_45\,
      CASDINB(21) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_46\,
      CASDINB(20) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_47\,
      CASDINB(19) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_48\,
      CASDINB(18) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_49\,
      CASDINB(17) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_50\,
      CASDINB(16) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_51\,
      CASDINB(15) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_52\,
      CASDINB(14) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_53\,
      CASDINB(13) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_54\,
      CASDINB(12) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_55\,
      CASDINB(11) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_56\,
      CASDINB(10) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_57\,
      CASDINB(9) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_58\,
      CASDINB(8) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_59\,
      CASDINB(7) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_60\,
      CASDINB(6) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_61\,
      CASDINB(5) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_62\,
      CASDINB(4) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_63\,
      CASDINB(3) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_64\,
      CASDINB(2) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_65\,
      CASDINB(1) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_66\,
      CASDINB(0) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_67\,
      CASDINPA(3 downto 0) => B"0000",
      CASDINPB(3) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_136\,
      CASDINPB(2) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_137\,
      CASDINPB(1) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_138\,
      CASDINPB(0) => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_139\,
      CASDOMUXA => '0',
      CASDOMUXB => '0',
      CASDOMUXEN_A => '1',
      CASDOMUXEN_B => '0',
      CASDOUTA(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_CASDOUTA_UNCONNECTED\(31 downto 0),
      CASDOUTB(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_CASDOUTB_UNCONNECTED\(31 downto 0),
      CASDOUTPA(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_CASDOUTPA_UNCONNECTED\(3 downto 0),
      CASDOUTPB(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_CASDOUTPB_UNCONNECTED\(3 downto 0),
      CASINDBITERR => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_0\,
      CASINSBITERR => \gen_wr_a.gen_word_narrow.mem_reg_bram_0_n_1\,
      CASOREGIMUXA => '0',
      CASOREGIMUXB => \gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_1_n_0\,
      CASOREGIMUXEN_A => '1',
      CASOREGIMUXEN_B => enb,
      CASOUTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_CASOUTDBITERR_UNCONNECTED\,
      CASOUTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_CASOUTSBITERR_UNCONNECTED\,
      CLKARDCLK => clka,
      CLKBWRCLK => clka,
      DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_DBITERR_UNCONNECTED\,
      DINADIN(31 downto 0) => dina(31 downto 0),
      DINBDIN(31 downto 0) => B"11111111111111111111111111111111",
      DINPADINP(3 downto 0) => dina(35 downto 32),
      DINPBDINP(3 downto 0) => B"1111",
      DOUTADOUT(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_DOUTADOUT_UNCONNECTED\(31 downto 0),
      DOUTBDOUT(31 downto 0) => doutb(31 downto 0),
      DOUTPADOUTP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_DOUTPADOUTP_UNCONNECTED\(3 downto 0),
      DOUTPBDOUTP(3 downto 0) => doutb(35 downto 32),
      ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_ECCPARITY_UNCONNECTED\(7 downto 0),
      ECCPIPECE => '1',
      ENARDEN => addra(10),
      ENBWREN => \gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_2_n_0\,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '1',
      REGCEB => regceb,
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => rstb,
      SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_1_SBITERR_UNCONNECTED\,
      SLEEP => '0',
      WEA(3) => \gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_3_n_0\,
      WEA(2) => \gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_3_n_0\,
      WEA(1) => \gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_3_n_0\,
      WEA(0) => \gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_3_n_0\,
      WEBWE(7 downto 0) => B"00000000"
    );
\gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => addrb(10),
      O => \gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_1_n_0\
    );
\gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => enb,
      I1 => addrb(10),
      O => \gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_2_n_0\
    );
\gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => wea(0),
      I1 => addra(10),
      O => \gen_wr_a.gen_word_narrow.mem_reg_bram_1_i_3_n_0\
    );
\gen_wr_a.gen_word_narrow.mem_reg_bram_2\: unisim.vcomponents.RAMB36E2
    generic map(
      CASCADE_ORDER_A => "NONE",
      CASCADE_ORDER_B => "NONE",
      CLOCK_DOMAINS => "COMMON",
      DOA_REG => 0,
      DOB_REG => 1,
      ENADDRENA => "FALSE",
      ENADDRENB => "FALSE",
      EN_ECC_PIPE => "FALSE",
      EN_ECC_READ => "FALSE",
      EN_ECC_WRITE => "FALSE",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      RDADDRCHANGEA => "FALSE",
      RDADDRCHANGEB => "FALSE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SLEEP_ASYNC => "FALSE",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "NO_CHANGE",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(14 downto 4) => addra(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"0000",
      ADDRBWRADDR(14 downto 4) => addrb(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"0000",
      ADDRENA => '1',
      ADDRENB => '1',
      CASDIMUXA => '0',
      CASDIMUXB => '0',
      CASDINA(31 downto 0) => B"00000000000000000000000000000000",
      CASDINB(31 downto 0) => B"00000000000000000000000000000000",
      CASDINPA(3 downto 0) => B"0000",
      CASDINPB(3 downto 0) => B"0000",
      CASDOMUXA => '0',
      CASDOMUXB => '0',
      CASDOMUXEN_A => '1',
      CASDOMUXEN_B => '1',
      CASDOUTA(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_CASDOUTA_UNCONNECTED\(31 downto 0),
      CASDOUTB(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_CASDOUTB_UNCONNECTED\(31 downto 0),
      CASDOUTPA(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_CASDOUTPA_UNCONNECTED\(3 downto 0),
      CASDOUTPB(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_CASDOUTPB_UNCONNECTED\(3 downto 0),
      CASINDBITERR => '0',
      CASINSBITERR => '0',
      CASOREGIMUXA => '0',
      CASOREGIMUXB => '0',
      CASOREGIMUXEN_A => '1',
      CASOREGIMUXEN_B => '1',
      CASOUTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_CASOUTDBITERR_UNCONNECTED\,
      CASOUTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_CASOUTSBITERR_UNCONNECTED\,
      CLKARDCLK => clka,
      CLKBWRCLK => clka,
      DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_DBITERR_UNCONNECTED\,
      DINADIN(31 downto 16) => B"0000000000000000",
      DINADIN(15 downto 0) => dina(51 downto 36),
      DINBDIN(31 downto 0) => B"00000000000000001111111111111111",
      DINPADINP(3 downto 2) => B"00",
      DINPADINP(1 downto 0) => dina(53 downto 52),
      DINPBDINP(3 downto 0) => B"0011",
      DOUTADOUT(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_DOUTADOUT_UNCONNECTED\(31 downto 0),
      DOUTBDOUT(31 downto 16) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_DOUTBDOUT_UNCONNECTED\(31 downto 16),
      DOUTBDOUT(15 downto 0) => doutb(51 downto 36),
      DOUTPADOUTP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_DOUTPADOUTP_UNCONNECTED\(3 downto 0),
      DOUTPBDOUTP(3 downto 2) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_DOUTPBDOUTP_UNCONNECTED\(3 downto 2),
      DOUTPBDOUTP(1 downto 0) => doutb(53 downto 52),
      ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_ECCPARITY_UNCONNECTED\(7 downto 0),
      ECCPIPECE => '1',
      ENARDEN => '1',
      ENBWREN => enb,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '1',
      REGCEB => regceb,
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => rstb,
      SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_2_SBITERR_UNCONNECTED\,
      SLEEP => '0',
      WEA(3) => wea(0),
      WEA(2) => wea(0),
      WEA(1) => wea(0),
      WEA(0) => wea(0),
      WEBWE(7 downto 0) => B"00000000"
    );
\gen_wr_a.gen_word_narrow.mem_reg_bram_3\: unisim.vcomponents.RAMB36E2
    generic map(
      CASCADE_ORDER_A => "NONE",
      CASCADE_ORDER_B => "NONE",
      CLOCK_DOMAINS => "COMMON",
      DOA_REG => 0,
      DOB_REG => 1,
      ENADDRENA => "FALSE",
      ENADDRENB => "FALSE",
      EN_ECC_PIPE => "FALSE",
      EN_ECC_READ => "FALSE",
      EN_ECC_WRITE => "FALSE",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      RDADDRCHANGEA => "FALSE",
      RDADDRCHANGEB => "FALSE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SLEEP_ASYNC => "FALSE",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "NO_CHANGE",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(14 downto 4) => addra(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"0000",
      ADDRBWRADDR(14 downto 4) => addrb(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"0000",
      ADDRENA => '1',
      ADDRENB => '1',
      CASDIMUXA => '0',
      CASDIMUXB => '0',
      CASDINA(31 downto 0) => B"00000000000000000000000000000000",
      CASDINB(31 downto 0) => B"00000000000000000000000000000000",
      CASDINPA(3 downto 0) => B"0000",
      CASDINPB(3 downto 0) => B"0000",
      CASDOMUXA => '0',
      CASDOMUXB => '0',
      CASDOMUXEN_A => '1',
      CASDOMUXEN_B => '1',
      CASDOUTA(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_CASDOUTA_UNCONNECTED\(31 downto 0),
      CASDOUTB(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_CASDOUTB_UNCONNECTED\(31 downto 0),
      CASDOUTPA(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_CASDOUTPA_UNCONNECTED\(3 downto 0),
      CASDOUTPB(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_CASDOUTPB_UNCONNECTED\(3 downto 0),
      CASINDBITERR => '0',
      CASINSBITERR => '0',
      CASOREGIMUXA => '0',
      CASOREGIMUXB => '0',
      CASOREGIMUXEN_A => '1',
      CASOREGIMUXEN_B => '1',
      CASOUTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_CASOUTDBITERR_UNCONNECTED\,
      CASOUTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_CASOUTSBITERR_UNCONNECTED\,
      CLKARDCLK => clka,
      CLKBWRCLK => clka,
      DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_DBITERR_UNCONNECTED\,
      DINADIN(31 downto 14) => B"000000000000000000",
      DINADIN(13 downto 0) => dina(67 downto 54),
      DINBDIN(31 downto 0) => B"00000000000000000011111111111111",
      DINPADINP(3 downto 0) => B"0000",
      DINPBDINP(3 downto 0) => B"0000",
      DOUTADOUT(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_DOUTADOUT_UNCONNECTED\(31 downto 0),
      DOUTBDOUT(31 downto 14) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_DOUTBDOUT_UNCONNECTED\(31 downto 14),
      DOUTBDOUT(13 downto 0) => doutb(67 downto 54),
      DOUTPADOUTP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_DOUTPADOUTP_UNCONNECTED\(3 downto 0),
      DOUTPBDOUTP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_DOUTPBDOUTP_UNCONNECTED\(3 downto 0),
      ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_ECCPARITY_UNCONNECTED\(7 downto 0),
      ECCPIPECE => '1',
      ENARDEN => '1',
      ENBWREN => enb,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '1',
      REGCEB => regceb,
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => rstb,
      SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_bram_3_SBITERR_UNCONNECTED\,
      SLEEP => '0',
      WEA(3) => wea(0),
      WEA(2) => wea(0),
      WEA(1) => wea(0),
      WEA(0) => wea(0),
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 25 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 25 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 25 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 25 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 26;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 26;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 832;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : string;
  attribute P_MEMORY_PRIMITIVE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 26;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 26;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 26;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 26;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 26;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 26;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 26;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 26;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 26;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 26;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 26;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 2;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 28;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ : entity is 28;
end \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\ is
  signal \<const0>\ : STD_LOGIC;
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 25 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25_DOG_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[0]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[10]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[11]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[12]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[13]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[14]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[15]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[16]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[17]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[18]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[19]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[20]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[21]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[22]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[23]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[24]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[25]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[7]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[9]\ : label is "yes";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 832;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "RAM_SDP";
  attribute dram_emb_xdc of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "yes";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 13;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25\ : label is 832;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25\ : label is "RAM_SDP";
  attribute dram_emb_xdc of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25\ : label is "yes";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25\ : label is 14;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25\ : label is 25;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(0),
      Q => doutb(0),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(10),
      Q => doutb(10),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(11),
      Q => doutb(11),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(12),
      Q => doutb(12),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(13),
      Q => doutb(13),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(14),
      Q => doutb(14),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(15),
      Q => doutb(15),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(16),
      Q => doutb(16),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(17),
      Q => doutb(17),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(18),
      Q => doutb(18),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(19),
      Q => doutb(19),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      Q => doutb(1),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(20),
      Q => doutb(20),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(21),
      Q => doutb(21),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(22),
      Q => doutb(22),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(23),
      Q => doutb(23),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(24),
      Q => doutb(24),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(25),
      Q => doutb(25),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(2),
      Q => doutb(2),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3),
      Q => doutb(3),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(4),
      Q => doutb(4),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5),
      Q => doutb(5),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(6),
      Q => doutb(6),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(7),
      Q => doutb(7),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(8),
      Q => doutb(8),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(9),
      Q => doutb(9),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(1 downto 0),
      DIB(1 downto 0) => dina(3 downto 2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1 downto 0) => dina(7 downto 6),
      DIE(1 downto 0) => dina(9 downto 8),
      DIF(1 downto 0) => dina(11 downto 10),
      DIG(1 downto 0) => dina(13 downto 12),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1 downto 0),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3 downto 2),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5 downto 4),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(7 downto 6),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(9 downto 8),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(11 downto 10),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(13 downto 12),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => ena
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(15 downto 14),
      DIB(1 downto 0) => dina(17 downto 16),
      DIC(1 downto 0) => dina(19 downto 18),
      DID(1 downto 0) => dina(21 downto 20),
      DIE(1 downto 0) => dina(23 downto 22),
      DIF(1 downto 0) => dina(25 downto 24),
      DIG(1 downto 0) => B"00",
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(15 downto 14),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(17 downto 16),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(19 downto 18),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(21 downto 20),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(23 downto 22),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(25 downto 24),
      DOG(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25_DOG_UNCONNECTED\(1 downto 0),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_25_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => ena
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ is
  port (
    sleep : in STD_LOGIC;
    clka : in STD_LOGIC;
    rsta : in STD_LOGIC;
    ena : in STD_LOGIC;
    regcea : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 41 downto 0 );
    injectsbiterra : in STD_LOGIC;
    injectdbiterra : in STD_LOGIC;
    douta : out STD_LOGIC_VECTOR ( 41 downto 0 );
    sbiterra : out STD_LOGIC;
    dbiterra : out STD_LOGIC;
    clkb : in STD_LOGIC;
    rstb : in STD_LOGIC;
    enb : in STD_LOGIC;
    regceb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 41 downto 0 );
    injectsbiterrb : in STD_LOGIC;
    injectdbiterrb : in STD_LOGIC;
    doutb : out STD_LOGIC_VECTOR ( 41 downto 0 );
    sbiterrb : out STD_LOGIC;
    dbiterrb : out STD_LOGIC
  );
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 42;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 42;
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "[7:0]";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 1344;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "xpm_memory_base";
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "yes";
  attribute P_MEMORY_PRIMITIVE : string;
  attribute P_MEMORY_PRIMITIVE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 42;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 42;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 42;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 42;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 42;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 42;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 42;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 42;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 42;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "SYNC";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 42;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 42;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 2;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is "soft";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 44;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ : entity is 44;
end \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\ is
  signal \<const0>\ : STD_LOGIC;
  signal \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\ : STD_LOGIC_VECTOR ( 41 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41_DOH_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute dram_emb_xdc : string;
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[0]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[10]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[11]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[12]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[13]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[14]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[15]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[16]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[17]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[18]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[19]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[20]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[21]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[22]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[23]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[24]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[25]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[26]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[27]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[28]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[29]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[30]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[31]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[32]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[33]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[34]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[35]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[36]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[37]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[38]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[39]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[40]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[7]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\ : label is "yes";
  attribute dram_emb_xdc of \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[9]\ : label is "yes";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 1344;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE : string;
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "distributed";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "RAM_SDP";
  attribute dram_emb_xdc of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is "yes";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 31;
  attribute ram_offset : integer;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\ : label is 13;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 1344;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "RAM_SDP";
  attribute dram_emb_xdc of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is "yes";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 14;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\ : label is 27;
  attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "";
  attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 1344;
  attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "xpm_memory_base/gen_wr_a.gen_word_narrow.mem_reg";
  attribute RTL_RAM_STYLE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "distributed";
  attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "RAM_SDP";
  attribute dram_emb_xdc of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is "yes";
  attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 0;
  attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 31;
  attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 0;
  attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 28;
  attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\ : label is 41;
begin
  dbiterra <= \<const0>\;
  dbiterrb <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  sbiterra <= \<const0>\;
  sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(0),
      Q => doutb(0),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(10),
      Q => doutb(10),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(11),
      Q => doutb(11),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(12),
      Q => doutb(12),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(13),
      Q => doutb(13),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(14),
      Q => doutb(14),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(15),
      Q => doutb(15),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(16),
      Q => doutb(16),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(17),
      Q => doutb(17),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(18),
      Q => doutb(18),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(19),
      Q => doutb(19),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1),
      Q => doutb(1),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(20),
      Q => doutb(20),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(21),
      Q => doutb(21),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(22),
      Q => doutb(22),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(23),
      Q => doutb(23),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(24),
      Q => doutb(24),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(25),
      Q => doutb(25),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(26),
      Q => doutb(26),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(27),
      Q => doutb(27),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(28),
      Q => doutb(28),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(29),
      Q => doutb(29),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(2),
      Q => doutb(2),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(30),
      Q => doutb(30),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(31),
      Q => doutb(31),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(32),
      Q => doutb(32),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(33),
      Q => doutb(33),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(34),
      Q => doutb(34),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(35),
      Q => doutb(35),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(36),
      Q => doutb(36),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(37),
      Q => doutb(37),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(38),
      Q => doutb(38),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(39),
      Q => doutb(39),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3),
      Q => doutb(3),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(40),
      Q => doutb(40),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(41),
      Q => doutb(41),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(4),
      Q => doutb(4),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5),
      Q => doutb(5),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(6),
      Q => doutb(6),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(7),
      Q => doutb(7),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(8),
      Q => doutb(8),
      R => rstb
    );
\gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clkb,
      CE => enb,
      D => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(9),
      Q => doutb(9),
      R => rstb
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(1 downto 0),
      DIB(1 downto 0) => dina(3 downto 2),
      DIC(1 downto 0) => dina(5 downto 4),
      DID(1 downto 0) => dina(7 downto 6),
      DIE(1 downto 0) => dina(9 downto 8),
      DIF(1 downto 0) => dina(11 downto 10),
      DIG(1 downto 0) => dina(13 downto 12),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(1 downto 0),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(3 downto 2),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(5 downto 4),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(7 downto 6),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(9 downto 8),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(11 downto 10),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(13 downto 12),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => ena
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(15 downto 14),
      DIB(1 downto 0) => dina(17 downto 16),
      DIC(1 downto 0) => dina(19 downto 18),
      DID(1 downto 0) => dina(21 downto 20),
      DIE(1 downto 0) => dina(23 downto 22),
      DIF(1 downto 0) => dina(25 downto 24),
      DIG(1 downto 0) => dina(27 downto 26),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(15 downto 14),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(17 downto 16),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(19 downto 18),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(21 downto 20),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(23 downto 22),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(25 downto 24),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(27 downto 26),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => ena
    );
\gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41\: unisim.vcomponents.RAM32M16
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_E => X"0000000000000000",
      INIT_F => X"0000000000000000",
      INIT_G => X"0000000000000000",
      INIT_H => X"0000000000000000"
    )
        port map (
      ADDRA(4 downto 0) => addrb(4 downto 0),
      ADDRB(4 downto 0) => addrb(4 downto 0),
      ADDRC(4 downto 0) => addrb(4 downto 0),
      ADDRD(4 downto 0) => addrb(4 downto 0),
      ADDRE(4 downto 0) => addrb(4 downto 0),
      ADDRF(4 downto 0) => addrb(4 downto 0),
      ADDRG(4 downto 0) => addrb(4 downto 0),
      ADDRH(4 downto 0) => addra(4 downto 0),
      DIA(1 downto 0) => dina(29 downto 28),
      DIB(1 downto 0) => dina(31 downto 30),
      DIC(1 downto 0) => dina(33 downto 32),
      DID(1 downto 0) => dina(35 downto 34),
      DIE(1 downto 0) => dina(37 downto 36),
      DIF(1 downto 0) => dina(39 downto 38),
      DIG(1 downto 0) => dina(41 downto 40),
      DIH(1 downto 0) => B"00",
      DOA(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(29 downto 28),
      DOB(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(31 downto 30),
      DOC(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(33 downto 32),
      DOD(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(35 downto 34),
      DOE(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(37 downto 36),
      DOF(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(39 downto 38),
      DOG(1 downto 0) => \gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0\(41 downto 40),
      DOH(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41_DOH_UNCONNECTED\(1 downto 0),
      WCLK => clka,
      WE => ena
    );
end STRUCTURE;
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`protect end_protected
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2024.2"
`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
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`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Xilinx", key_keyname="xilinxt_2023_11", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=384)
`protect key_block
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`protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 1390000)
`protect data_block
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Hostif is
  port (
    commok : out STD_LOGIC;
    rng_reg : out STD_LOGIC;
    hdrNotFix : out STD_LOGIC;
    reqInvDecimConfig : out STD_LOGIC;
    reqInvDecimAcquire : out STD_LOGIC;
    reqInvDecimSet : out STD_LOGIC;
    tixVState1 : out STD_LOGIC;
    stateOp_reg : out STD_LOGIC;
    reqInvHdrengSet : out STD_LOGIC;
    reqInvAssign : out STD_LOGIC;
    stateOp_reg_0 : out STD_LOGIC;
    rng_reg_0 : out STD_LOGIC;
    reqInvMemtrackSet : out STD_LOGIC;
    reqInvMemtrackClearMask : out STD_LOGIC;
    reqInvMemtrackSelect : out STD_LOGIC;
    stateOp_reg_1 : out STD_LOGIC;
    reqInvStepmuxSet : out STD_LOGIC;
    reqReset_sig_reg_0 : out STD_LOGIC;
    \i_reg[2]__0\ : out STD_LOGIC;
    \tixVController_reg[1]_0\ : out STD_LOGIC;
    reqInvTkclksrcSetTkst : out STD_LOGIC;
    \stateOp_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    apuAXIL_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \tixVCommand_reg[0]_0\ : out STD_LOGIC;
    reqInvDirectorConfig : out STD_LOGIC;
    rng_reg_1 : out STD_LOGIC;
    reqInvRotaryMoveto : out STD_LOGIC;
    \step1__6\ : out STD_LOGIC;
    reqInvRotaryConfig : out STD_LOGIC;
    S : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \invbuf_reg[0][7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \invbuf_reg[1][7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D : out STD_LOGIC_VECTOR ( 23 downto 0 );
    rng_reg_2 : out STD_LOGIC;
    reqInvHshktrackSet : out STD_LOGIC;
    reqInvHshktrackClearMask : out STD_LOGIC;
    reqInvHshktrackSelect : out STD_LOGIC;
    \mask_reg[5]\ : out STD_LOGIC;
    \mask_reg[4]\ : out STD_LOGIC;
    \invbuf_reg[0][0]_0\ : out STD_LOGIC;
    \invbuf_reg[0][0]_1\ : out STD_LOGIC;
    \mask_reg[1]\ : out STD_LOGIC;
    \mask_reg[0]\ : out STD_LOGIC;
    rng_reg_3 : out STD_LOGIC_VECTOR ( 0 to 0 );
    rng_reg_4 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    reqInvDecimUnlock : out STD_LOGIC;
    \stateOp_reg[0]_0\ : out STD_LOGIC;
    \stateOp_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \tixVCommand_reg[0]_1\ : out STD_LOGIC;
    ackInvSet_sig : out STD_LOGIC;
    stateOp47_out : out STD_LOGIC;
    reqInvConfigSynth : out STD_LOGIC;
    reqInvConfig : out STD_LOGIC;
    stateOp_reg_2 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateLive_reg[2]\ : out STD_LOGIC;
    reqInvSetReg : out STD_LOGIC;
    reqInvGetReg : out STD_LOGIC;
    reqInvModReg : out STD_LOGIC;
    \invbuf_reg[0][7]_1\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    \i2cRegaddr[15]_i_6_0\ : out STD_LOGIC;
    ackInvModReg_sig_reg : out STD_LOGIC;
    \invbuf_reg[0][5]_0\ : out STD_LOGIC;
    \invbuf_reg[0][4]_0\ : out STD_LOGIC;
    \invbuf_reg[1][6]_0\ : out STD_LOGIC;
    \invbuf_reg[1][4]_0\ : out STD_LOGIC;
    \invbuf_reg[1][3]_0\ : out STD_LOGIC;
    \invbuf_reg[1][0]_0\ : out STD_LOGIC;
    stateCorecfg0 : out STD_LOGIC;
    reqInvGetCorereg : out STD_LOGIC;
    reqInvSetCorereg : out STD_LOGIC;
    \invbuf_reg[0][7]_2\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
    \invbuf_reg[0][7]_3\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
    \stateCorecfg[2]_i_4_0\ : out STD_LOGIC;
    \invbuf_reg[2][7]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \invbuf_reg[5][7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \invbuf_reg[4][7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \tixVController_reg[1]_1\ : out STD_LOGIC;
    reqInvVidtrackSelect : out STD_LOGIC;
    reqInvVidtrackSet : out STD_LOGIC;
    \mask_reg[7]\ : out STD_LOGIC;
    \mask_reg[6]\ : out STD_LOGIC;
    \mask_reg[5]_0\ : out STD_LOGIC;
    \mask_reg[4]_0\ : out STD_LOGIC;
    \invbuf_reg[0][1]_0\ : out STD_LOGIC;
    \mask_reg[3]\ : out STD_LOGIC;
    \mask_reg[2]\ : out STD_LOGIC;
    \mask_reg[1]_0\ : out STD_LOGIC;
    \mask_reg[0]_0\ : out STD_LOGIC;
    \stateOp_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[2]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \tixVController_reg[2]_0\ : out STD_LOGIC;
    reqInvMemtrackSetMask : out STD_LOGIC;
    ackInvSetMask_sig_reg : out STD_LOGIC;
    stateOp5_out : out STD_LOGIC;
    reqInvTraceConfig : out STD_LOGIC;
    reqInvTraceAcquire : out STD_LOGIC;
    ackInvAcquire_sig3_out : out STD_LOGIC;
    ackInvConfig_sig : out STD_LOGIC;
    stateOp_reg_3 : out STD_LOGIC;
    reqInvDirectorSet : out STD_LOGIC;
    stateOp0_out : out STD_LOGIC;
    reqReset_sig_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    reqInvRotaryZero : out STD_LOGIC;
    ccwNotCw5_in : out STD_LOGIC;
    \stateOp_reg[0]_2\ : out STD_LOGIC;
    tkclk_sig_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ackInvConfig_sig0__6\ : out STD_LOGIC;
    \stateOp_reg[1]_1\ : out STD_LOGIC;
    \stateOp_reg[1]_2\ : out STD_LOGIC;
    \invbuf_reg[0][5]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \invbuf_reg[0][5]_2\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    DI : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \invbuf_reg[0][5]_3\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \invbuf_reg[0][5]_4\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    ccwNotCw0 : out STD_LOGIC;
    \mask_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    targetNotSteady : out STD_LOGIC;
    \stateOp_reg[1]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    ackInvSet_sig_0 : out STD_LOGIC;
    \stateOp_reg[0]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[0]_4\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    reqInvHshktrackSetMask : out STD_LOGIC;
    \ackInvSetMask_sig_i_2__0_0\ : out STD_LOGIC;
    \staTixVTrigger[7]_i_3__0_0\ : out STD_LOGIC;
    ackInvClearMask_sig_reg : out STD_LOGIC;
    ackInvSelect_sig_reg : out STD_LOGIC;
    ackInvSelect_sig_reg_0 : out STD_LOGIC;
    reqInvSelect : out STD_LOGIC;
    reqInvCputrackSet : out STD_LOGIC;
    \tixVController_reg[0]_0\ : out STD_LOGIC;
    \stateOp_reg[1]_4\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    reqInvAcquire : out STD_LOGIC;
    reqInvCornerConfig : out STD_LOGIC;
    \tixVState_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    ackInvUnlock_sig0_in : out STD_LOGIC;
    \stateOp_reg[0]_5\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[0]_6\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_5\ : out STD_LOGIC;
    ackInvSet_sig_i_8_0 : out STD_LOGIC;
    ackInvSet_sig_1 : out STD_LOGIC;
    rng_reg_5 : out STD_LOGIC;
    rng_reg_6 : out STD_LOGIC_VECTOR ( 0 to 0 );
    ackInvAssign_sig : out STD_LOGIC;
    \invbuf_reg[0][7]_4\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    stateOp_reg_4 : out STD_LOGIC;
    reqCoobufCornerToHostif : out STD_LOGIC;
    reqFlgbufTraceToHostif : out STD_LOGIC;
    reqSeqbufHshktrackToHostif : out STD_LOGIC;
    reqSeqbufMemtrackToHostif : out STD_LOGIC;
    reqSeqbufVidtrackToHostif : out STD_LOGIC;
    reqSeqbufCputrackToHostif : out STD_LOGIC;
    reqPvwbufDecimToHostif : out STD_LOGIC;
    dnePvwbufDecimToHostif : out STD_LOGIC;
    dneSeqbufCputrackToHostif : out STD_LOGIC;
    dneSeqbufMemtrackToHostif : out STD_LOGIC;
    dneSeqbufVidtrackToHostif : out STD_LOGIC;
    dneSeqbufHshktrackToHostif : out STD_LOGIC;
    dneFlgbufTraceToHostif : out STD_LOGIC;
    dneCoobufCornerToHostif : out STD_LOGIC;
    reqInvLaserSet : out STD_LOGIC;
    pvwbufDecimToHostifAXIS_tready : out STD_LOGIC;
    seqbufCputrackToHostifAXIS_tready : out STD_LOGIC;
    seqbufMemtrackToHostifAXIS_tready : out STD_LOGIC;
    seqbufVidtrackToHostifAXIS_tready : out STD_LOGIC;
    seqbufHshktrackToHostifAXIS_tready : out STD_LOGIC;
    flgbufTraceToHostifAXIS_tready : out STD_LOGIC;
    coobufCornerToHostifAXIS_tready : out STD_LOGIC;
    \invbuf_reg[6][2]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    \invbuf_reg[8][2]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    commok_sig_reg_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \seq[1]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \invbuf_reg[0][7]_5\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    synthNotLive : out STD_LOGIC;
    AXIL_wready_sig_reg : out STD_LOGIC;
    AXIL_awready_sig_reg : out STD_LOGIC;
    AXIL_arready : out STD_LOGIC;
    AXIL_bvalid_sig_reg : out STD_LOGIC;
    apuAXIL_rvalid : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    \stateOp_reg[1]_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    rng_reg_7 : in STD_LOGIC;
    rng_reg_8 : in STD_LOGIC;
    \mask_reg[7]_0\ : in STD_LOGIC;
    rng_reg_9 : in STD_LOGIC;
    ackInvStepmuxSet : in STD_LOGIC;
    linNotRot_reg : in STD_LOGIC;
    stateMclk : in STD_LOGIC;
    reset_reg : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tkclk : in STD_LOGIC;
    \retbuf_reg[1][7]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    rng_reg_10 : in STD_LOGIC;
    \ccwNotCw2_carry__0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \mask_reg[5]_1\ : in STD_LOGIC;
    rng_reg_11 : in STD_LOGIC;
    \mask_reg[5]_2\ : in STD_LOGIC;
    \mask_reg[4]_1\ : in STD_LOGIC;
    \mask_reg[3]_1\ : in STD_LOGIC;
    \mask_reg[2]_0\ : in STD_LOGIC;
    \mask_reg[1]_1\ : in STD_LOGIC;
    \mask_reg[0]_1\ : in STD_LOGIC;
    \tixVState_reg[1]_0\ : in STD_LOGIC;
    \stateOp_reg[0]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \tixVState_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    stateOp_reg_5 : in STD_LOGIC;
    i2cReadNotWrite_reg : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \i2cRegaddr_reg[15]\ : in STD_LOGIC;
    DO : in STD_LOGIC_VECTOR ( 6 downto 0 );
    ackInvCamifModReg : in STD_LOGIC;
    ackInvCamifGetReg : in STD_LOGIC;
    ackInvCamifSetReg : in STD_LOGIC;
    \i2cRegaddr_reg[13]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ackInvCamifGetCorereg : in STD_LOGIC;
    ackInvCamifSetCorereg : in STD_LOGIC;
    \mask_reg[7]_1\ : in STD_LOGIC;
    \mask_reg[6]_0\ : in STD_LOGIC;
    \mask_reg[5]_3\ : in STD_LOGIC;
    \mask_reg[4]_2\ : in STD_LOGIC;
    \mask_reg[3]_2\ : in STD_LOGIC;
    \mask_reg[2]_1\ : in STD_LOGIC;
    \mask_reg[1]_2\ : in STD_LOGIC;
    \mask_reg[0]_2\ : in STD_LOGIC;
    ackInvMemtrackSetMask : in STD_LOGIC;
    ackInvMemtrackSet : in STD_LOGIC;
    ackInvMemtrackSelect : in STD_LOGIC;
    ackInvMemtrackClearMask : in STD_LOGIC;
    stateOp_reg_6 : in STD_LOGIC;
    rng_sig_reg : in STD_LOGIC;
    rng : in STD_LOGIC;
    ackInvSet_sig_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateOp_reg[0]_8\ : in STD_LOGIC;
    ackInvRotarySet : in STD_LOGIC;
    ackInvRotaryMoveto : in STD_LOGIC;
    ackInvRotaryZero : in STD_LOGIC;
    ackInvRotaryConfig : in STD_LOGIC;
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    O : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ccwNotCw_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    ccwNotCw_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    ccwNotCw_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    ackInvHshktrackClearMask : in STD_LOGIC;
    ackInvHshktrackSet : in STD_LOGIC;
    ackInvHshktrackSelect : in STD_LOGIC;
    ackInvHshktrackSetMask : in STD_LOGIC;
    ackInvCputrackSelect : in STD_LOGIC;
    ackInvCputrackSet : in STD_LOGIC;
    \stateOp_reg[0]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \tixVState_reg[1]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \tixVState_reg[1]_3\ : in STD_LOGIC;
    ackInvCornerUnlock : in STD_LOGIC;
    ackInvCornerAcquire : in STD_LOGIC;
    ackInvCornerSet : in STD_LOGIC;
    ackInvCornerConfig : in STD_LOGIC;
    rng_reg_12 : in STD_LOGIC;
    rng_reg_13 : in STD_LOGIC;
    \retbuf[4][7]_i_12_0\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    vidtrackGetInfoPtr0Seqbuf : in STD_LOGIC_VECTOR ( 9 downto 0 );
    vidtrackGetInfoTixVState : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \retbuf_reg[12][7]_0\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \retbuf_reg[8][7]_0\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \pollbuf_reg[2][7]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ackSeqbufHshktrackToHostif : in STD_LOGIC;
    \pollbuf_reg[2][4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    seqbufHshktrackToHostifAXIS_tvalid : in STD_LOGIC;
    \pollbuf[2][7]_i_2_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pollbuf[2][3]_i_2_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ackCoobufCornerToHostif : in STD_LOGIC;
    ackFlgbufTraceToHostif : in STD_LOGIC;
    ackSeqbufVidtrackToHostif : in STD_LOGIC;
    ackSeqbufCputrackToHostif : in STD_LOGIC;
    ackSeqbufMemtrackToHostif : in STD_LOGIC;
    ackPvwbufDecimToHostif : in STD_LOGIC;
    ackInvTraceAcquire : in STD_LOGIC;
    ackInvTkclksrcSetTkst : in STD_LOGIC;
    \retbuf[0][7]_i_20_0\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
    \retbuf_reg[1][7]_i_13_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    ackInvTraceConfig : in STD_LOGIC;
    \retbuf_reg[1][7]_i_13_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \retbuf_reg[1][7]_i_13_2\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \retbuf[0][7]_i_10\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \retbuf[1][7]_i_8_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \retbuf[1][7]_i_8_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \retbuf[1][7]_i_8_2\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \retbuf[0][7]_i_20_1\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    ackInvCamifConfigSynth : in STD_LOGIC;
    ackInvCamifConfig : in STD_LOGIC;
    ackInvDecimUnlock : in STD_LOGIC;
    ackInvDirectorSet : in STD_LOGIC;
    ackInvDirectorConfig : in STD_LOGIC;
    ackInvVidtrackSet : in STD_LOGIC;
    ackInvVidtrackSelect : in STD_LOGIC;
    ackInvLaserSet : in STD_LOGIC;
    ackInvHdrengSet : in STD_LOGIC;
    ackInvHdrengAssign : in STD_LOGIC;
    ackInvDecimConfig : in STD_LOGIC;
    ackInvDecimSet : in STD_LOGIC;
    ackInvDecimAcquire : in STD_LOGIC;
    \retbuf[0][7]_i_10_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \retbuf[0][7]_i_20_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \retbuf[0][6]_i_4_0\ : in STD_LOGIC;
    \retbuf[0][5]_i_3_0\ : in STD_LOGIC;
    \retbuf[0][4]_i_3_0\ : in STD_LOGIC;
    \retbuf[0][3]_i_3_0\ : in STD_LOGIC;
    \retbuf_reg[0][1]_i_5_0\ : in STD_LOGIC;
    \retbuf[0][0]_i_2_0\ : in STD_LOGIC;
    \retbuf[5][7]_i_5_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \retbuf[5][7]_i_5_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \retbuf[6][7]_i_4_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \retbuf[6][7]_i_4_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    memtrackGetInfoTixVState : in STD_LOGIC_VECTOR ( 1 downto 0 );
    hshktrackGetInfoTixVState : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cputrackGetInfoTixVState : in STD_LOGIC_VECTOR ( 1 downto 0 );
    traceGetInfoTixVState : in STD_LOGIC_VECTOR ( 0 to 0 );
    cputrackGetInfoPtr0Seqbuf : in STD_LOGIC_VECTOR ( 9 downto 0 );
    hshktrackGetInfoPtr0Seqbuf : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \retbuf[5][1]_i_2_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    seqbufVidtrackToHostifAXIS_tvalid : in STD_LOGIC;
    seqbufCputrackToHostifAXIS_tvalid : in STD_LOGIC;
    seqbufMemtrackToHostifAXIS_tvalid : in STD_LOGIC;
    \pollbuf[2][4]_i_2_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pollbuf[2][4]_i_2_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    avllenSeqbufMemtrackToHostif : in STD_LOGIC_VECTOR ( 0 to 0 );
    doutb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \txAXIS_tdata[63]_i_8_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \txAXIS_tdata[63]_i_8_1\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \txAXIS_tdata[63]_i_8_2\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \txAXIS_tdata[63]_i_8_3\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \txAXIS_tdata[63]_i_8_4\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \txAXIS_tdata[63]_i_8_5\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    apuAXIL_wvalid : in STD_LOGIC;
    apuAXIL_awvalid : in STD_LOGIC;
    apuAXIL_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    apuAXIL_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    apuAXIL_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    apuAXIL_bready : in STD_LOGIC;
    apuAXIL_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
    apuAXIL_arvalid : in STD_LOGIC;
    apuAXIL_rready : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Hostif : entity is "Hostif";
end design_1_Vsp_core_0_0_Hostif;

architecture STRUCTURE of design_1_Vsp_core_0_0_Hostif is
  signal AXIS_tdata : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal AXIS_tkeep : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal AXIS_tlast : STD_LOGIC;
  signal AXIS_tvalid : STD_LOGIC;
  signal \^d\ : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal \FSM_onehot_stateCoobufB[0]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateCoobufB[3]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateCoobufB[5]_i_4_n_0\ : STD_LOGIC;
  signal ackInvConfigSynth_sig_i_5_n_0 : STD_LOGIC;
  signal \^ackinvconfig_sig0__6\ : STD_LOGIC;
  signal ackInvConfig_sig_i_7_n_0 : STD_LOGIC;
  signal ackInvMoveto_sig_i_6_n_0 : STD_LOGIC;
  signal \^ackinvselect_sig_reg\ : STD_LOGIC;
  signal ackInvSet_sig_i_3_n_0 : STD_LOGIC;
  signal ackInvSet_sig_i_4_n_0 : STD_LOGIC;
  signal ackInvSet_sig_i_9_n_0 : STD_LOGIC;
  signal \^ackinvunlock_sig0_in\ : STD_LOGIC;
  signal ackInvUnlock_sig_i_3_n_0 : STD_LOGIC;
  signal ackInvUnlock_sig_i_4_n_0 : STD_LOGIC;
  signal \^ccwnotcw5_in\ : STD_LOGIC;
  signal ccwNotCw_i_2_n_0 : STD_LOGIC;
  signal ccwNotCw_i_3_n_0 : STD_LOGIC;
  signal \^commok\ : STD_LOGIC;
  signal \crcAXIS_tkeep[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[1]_i_10_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[1]_i_11_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[1]_i_12_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[1]_i_13_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[1]_i_14_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[1]_i_4_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[1]_i_5_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[1]_i_6_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[1]_i_7_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[1]_i_8_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[1]_i_9_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_2_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_3_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_10_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_12_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_13_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_15_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_16_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_17_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_18_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_19_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_20_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_21_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_22_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_23_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_24_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_25_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_5_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_6_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_8_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[7]_i_9_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[1]_i_2_n_5\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[1]_i_2_n_6\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[1]_i_2_n_7\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[1]_i_3_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[1]_i_3_n_1\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[1]_i_3_n_2\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[1]_i_3_n_3\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[1]_i_3_n_4\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[1]_i_3_n_5\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[1]_i_3_n_6\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[1]_i_3_n_7\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[7]_i_11_n_12\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[7]_i_11_n_6\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[7]_i_11_n_7\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[7]_i_14_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[7]_i_14_n_1\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[7]_i_14_n_2\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[7]_i_14_n_3\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[7]_i_14_n_4\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[7]_i_14_n_5\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[7]_i_14_n_6\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[7]_i_14_n_7\ : STD_LOGIC;
  signal crcAXIS_tlast_sig0 : STD_LOGIC;
  signal crcAXIS_tlast_sig2 : STD_LOGIC_VECTOR ( 28 downto 1 );
  signal crcAXIS_tlast_sig_i_13_n_0 : STD_LOGIC;
  signal crcAXIS_tlast_sig_i_14_n_0 : STD_LOGIC;
  signal crcAXIS_tlast_sig_i_15_n_0 : STD_LOGIC;
  signal crcAXIS_tlast_sig_i_2_n_0 : STD_LOGIC;
  signal crcAXIS_tlast_sig_i_4_n_0 : STD_LOGIC;
  signal crcAXIS_tlast_sig_i_5_n_0 : STD_LOGIC;
  signal crcAXIS_tlast_sig_i_7_n_0 : STD_LOGIC;
  signal crcAXIS_tlast_sig_i_9_n_0 : STD_LOGIC;
  signal crcAXIS_tlast_sig_reg_n_0 : STD_LOGIC;
  signal crc_imd0100_out : STD_LOGIC;
  signal crc_imd0112_out : STD_LOGIC;
  signal crc_imd0115_out : STD_LOGIC;
  signal crc_imd0118_out : STD_LOGIC;
  signal crc_imd0121_out : STD_LOGIC;
  signal crc_imd0124_out : STD_LOGIC;
  signal crc_imd0148_out : STD_LOGIC;
  signal crc_imd0149_out : STD_LOGIC;
  signal crc_imd0150_out : STD_LOGIC;
  signal crc_imd0151_out : STD_LOGIC;
  signal crc_imd0152_out : STD_LOGIC;
  signal crc_imd0165_out : STD_LOGIC;
  signal crc_imd0172_out : STD_LOGIC;
  signal crc_imd0173_out : STD_LOGIC;
  signal crc_imd0174_out : STD_LOGIC;
  signal crc_imd0175_out : STD_LOGIC;
  signal crc_imd0176_out : STD_LOGIC;
  signal crc_imd0198_out : STD_LOGIC;
  signal crc_imd0200_out : STD_LOGIC;
  signal crc_imd0202_out : STD_LOGIC;
  signal crc_imd041_out : STD_LOGIC;
  signal crc_imd042_out : STD_LOGIC;
  signal crc_imd043_out : STD_LOGIC;
  signal crc_imd065_out : STD_LOGIC;
  signal crc_imd066_out : STD_LOGIC;
  signal crc_imd067_out : STD_LOGIC;
  signal crc_imd068_out : STD_LOGIC;
  signal crc_imd069_out : STD_LOGIC;
  signal crc_imd081_out : STD_LOGIC;
  signal crc_imd083_out : STD_LOGIC;
  signal crc_imd085_out : STD_LOGIC;
  signal crc_imd086_out : STD_LOGIC;
  signal crc_imd087_out : STD_LOGIC;
  signal \^hdrnotfix\ : STD_LOGIC;
  signal hdrNotFix_i_2_n_0 : STD_LOGIC;
  signal \i2cRegaddr[15]_i_11_n_0\ : STD_LOGIC;
  signal \i__i_3_n_0\ : STD_LOGIC;
  signal \i__i_4_n_0\ : STD_LOGIC;
  signal \i__i_5_n_0\ : STD_LOGIC;
  signal \invbuf[0][7]_i_2_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_10_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_11_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_13_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_14_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_15_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_16_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_17_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_18_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_19_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_20_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_21_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_22_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_24_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_25_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_26_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_27_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_28_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_29_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_30_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_31_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_32_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_3_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_5_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_6_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_7_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_8_n_0\ : STD_LOGIC;
  signal \invbuf[9][7]_i_9_n_0\ : STD_LOGIC;
  signal \^invbuf_reg[0][1]_0\ : STD_LOGIC;
  signal \^invbuf_reg[0][7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^invbuf_reg[4][7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^invbuf_reg[5][7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \invbuf_reg[9][7]_i_12_n_0\ : STD_LOGIC;
  signal \invbuf_reg[9][7]_i_12_n_1\ : STD_LOGIC;
  signal \invbuf_reg[9][7]_i_12_n_2\ : STD_LOGIC;
  signal \invbuf_reg[9][7]_i_12_n_3\ : STD_LOGIC;
  signal \invbuf_reg[9][7]_i_12_n_4\ : STD_LOGIC;
  signal \invbuf_reg[9][7]_i_12_n_5\ : STD_LOGIC;
  signal \invbuf_reg[9][7]_i_12_n_6\ : STD_LOGIC;
  signal \invbuf_reg[9][7]_i_12_n_7\ : STD_LOGIC;
  signal \ixMemNext[7]_i_4_n_0\ : STD_LOGIC;
  signal ixRetbufCrc : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \ixRetbufCrc[4]_i_2_n_0\ : STD_LOGIC;
  signal \ixRetbufCrc[4]_i_3_n_0\ : STD_LOGIC;
  signal \ixRetbufCrc[4]_i_4_n_0\ : STD_LOGIC;
  signal \ixRetbufCrc[4]_i_5_n_0\ : STD_LOGIC;
  signal \ixRetbufCrc[5]_i_3_n_0\ : STD_LOGIC;
  signal \ixRetbufCrc[5]_i_4_n_0\ : STD_LOGIC;
  signal \lastAXIS_tkeep[3]_i_2_n_0\ : STD_LOGIC;
  signal \lastAXIS_tkeep[6]_i_2_n_0\ : STD_LOGIC;
  signal \lastAXIS_tkeep[7]_i_2_n_0\ : STD_LOGIC;
  signal \lastAXIS_tkeep_reg_n_0_[1]\ : STD_LOGIC;
  signal \lastAXIS_tkeep_reg_n_0_[2]\ : STD_LOGIC;
  signal \lastAXIS_tkeep_reg_n_0_[3]\ : STD_LOGIC;
  signal \lastAXIS_tkeep_reg_n_0_[4]\ : STD_LOGIC;
  signal \lastAXIS_tkeep_reg_n_0_[5]\ : STD_LOGIC;
  signal \lastAXIS_tkeep_reg_n_0_[6]\ : STD_LOGIC;
  signal \lastAXIS_tkeep_reg_n_0_[7]\ : STD_LOGIC;
  signal \len_reg_n_0_[0]\ : STD_LOGIC;
  signal \len_reg_n_0_[10]\ : STD_LOGIC;
  signal \len_reg_n_0_[11]\ : STD_LOGIC;
  signal \len_reg_n_0_[12]\ : STD_LOGIC;
  signal \len_reg_n_0_[13]\ : STD_LOGIC;
  signal \len_reg_n_0_[14]\ : STD_LOGIC;
  signal \len_reg_n_0_[15]\ : STD_LOGIC;
  signal \len_reg_n_0_[16]\ : STD_LOGIC;
  signal \len_reg_n_0_[17]\ : STD_LOGIC;
  signal \len_reg_n_0_[18]\ : STD_LOGIC;
  signal \len_reg_n_0_[19]\ : STD_LOGIC;
  signal \len_reg_n_0_[1]\ : STD_LOGIC;
  signal \len_reg_n_0_[20]\ : STD_LOGIC;
  signal \len_reg_n_0_[21]\ : STD_LOGIC;
  signal \len_reg_n_0_[22]\ : STD_LOGIC;
  signal \len_reg_n_0_[23]\ : STD_LOGIC;
  signal \len_reg_n_0_[24]\ : STD_LOGIC;
  signal \len_reg_n_0_[25]\ : STD_LOGIC;
  signal \len_reg_n_0_[26]\ : STD_LOGIC;
  signal \len_reg_n_0_[27]\ : STD_LOGIC;
  signal \len_reg_n_0_[28]\ : STD_LOGIC;
  signal \len_reg_n_0_[29]\ : STD_LOGIC;
  signal \len_reg_n_0_[2]\ : STD_LOGIC;
  signal \len_reg_n_0_[30]\ : STD_LOGIC;
  signal \len_reg_n_0_[31]\ : STD_LOGIC;
  signal \len_reg_n_0_[3]\ : STD_LOGIC;
  signal \len_reg_n_0_[4]\ : STD_LOGIC;
  signal \len_reg_n_0_[5]\ : STD_LOGIC;
  signal \len_reg_n_0_[6]\ : STD_LOGIC;
  signal \len_reg_n_0_[7]\ : STD_LOGIC;
  signal \len_reg_n_0_[8]\ : STD_LOGIC;
  signal \len_reg_n_0_[9]\ : STD_LOGIC;
  signal linNotRot_i_2_n_0 : STD_LOGIC;
  signal \lsb[1]_i_2_n_0\ : STD_LOGIC;
  signal \mask[1]_i_2_n_0\ : STD_LOGIC;
  signal \mask[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \mask[3]_i_2_n_0\ : STD_LOGIC;
  signal \mask[4]_i_2_n_0\ : STD_LOGIC;
  signal \mask[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \mask[5]_i_2_n_0\ : STD_LOGIC;
  signal \mask[5]_i_3_n_0\ : STD_LOGIC;
  signal \mask[6]_i_2_n_0\ : STD_LOGIC;
  signal \mask[7]_i_2_n_0\ : STD_LOGIC;
  signal \mask[7]_i_3_n_0\ : STD_LOGIC;
  signal myCrc_n_0 : STD_LOGIC;
  signal myCrc_n_1 : STD_LOGIC;
  signal myCrc_n_10 : STD_LOGIC;
  signal myCrc_n_100 : STD_LOGIC;
  signal myCrc_n_101 : STD_LOGIC;
  signal myCrc_n_102 : STD_LOGIC;
  signal myCrc_n_103 : STD_LOGIC;
  signal myCrc_n_104 : STD_LOGIC;
  signal myCrc_n_105 : STD_LOGIC;
  signal myCrc_n_106 : STD_LOGIC;
  signal myCrc_n_107 : STD_LOGIC;
  signal myCrc_n_108 : STD_LOGIC;
  signal myCrc_n_109 : STD_LOGIC;
  signal myCrc_n_110 : STD_LOGIC;
  signal myCrc_n_111 : STD_LOGIC;
  signal myCrc_n_112 : STD_LOGIC;
  signal myCrc_n_113 : STD_LOGIC;
  signal myCrc_n_114 : STD_LOGIC;
  signal myCrc_n_115 : STD_LOGIC;
  signal myCrc_n_116 : STD_LOGIC;
  signal myCrc_n_117 : STD_LOGIC;
  signal myCrc_n_118 : STD_LOGIC;
  signal myCrc_n_119 : STD_LOGIC;
  signal myCrc_n_120 : STD_LOGIC;
  signal myCrc_n_121 : STD_LOGIC;
  signal myCrc_n_122 : STD_LOGIC;
  signal myCrc_n_123 : STD_LOGIC;
  signal myCrc_n_124 : STD_LOGIC;
  signal myCrc_n_125 : STD_LOGIC;
  signal myCrc_n_126 : STD_LOGIC;
  signal myCrc_n_127 : STD_LOGIC;
  signal myCrc_n_128 : STD_LOGIC;
  signal myCrc_n_129 : STD_LOGIC;
  signal myCrc_n_130 : STD_LOGIC;
  signal myCrc_n_131 : STD_LOGIC;
  signal myCrc_n_132 : STD_LOGIC;
  signal myCrc_n_133 : STD_LOGIC;
  signal myCrc_n_134 : STD_LOGIC;
  signal myCrc_n_135 : STD_LOGIC;
  signal myCrc_n_136 : STD_LOGIC;
  signal myCrc_n_137 : STD_LOGIC;
  signal myCrc_n_138 : STD_LOGIC;
  signal myCrc_n_139 : STD_LOGIC;
  signal myCrc_n_140 : STD_LOGIC;
  signal myCrc_n_141 : STD_LOGIC;
  signal myCrc_n_142 : STD_LOGIC;
  signal myCrc_n_143 : STD_LOGIC;
  signal myCrc_n_144 : STD_LOGIC;
  signal myCrc_n_145 : STD_LOGIC;
  signal myCrc_n_146 : STD_LOGIC;
  signal myCrc_n_147 : STD_LOGIC;
  signal myCrc_n_148 : STD_LOGIC;
  signal myCrc_n_149 : STD_LOGIC;
  signal myCrc_n_150 : STD_LOGIC;
  signal myCrc_n_151 : STD_LOGIC;
  signal myCrc_n_152 : STD_LOGIC;
  signal myCrc_n_153 : STD_LOGIC;
  signal myCrc_n_154 : STD_LOGIC;
  signal myCrc_n_155 : STD_LOGIC;
  signal myCrc_n_156 : STD_LOGIC;
  signal myCrc_n_157 : STD_LOGIC;
  signal myCrc_n_158 : STD_LOGIC;
  signal myCrc_n_159 : STD_LOGIC;
  signal myCrc_n_160 : STD_LOGIC;
  signal myCrc_n_161 : STD_LOGIC;
  signal myCrc_n_162 : STD_LOGIC;
  signal myCrc_n_163 : STD_LOGIC;
  signal myCrc_n_164 : STD_LOGIC;
  signal myCrc_n_165 : STD_LOGIC;
  signal myCrc_n_166 : STD_LOGIC;
  signal myCrc_n_167 : STD_LOGIC;
  signal myCrc_n_168 : STD_LOGIC;
  signal myCrc_n_169 : STD_LOGIC;
  signal myCrc_n_170 : STD_LOGIC;
  signal myCrc_n_171 : STD_LOGIC;
  signal myCrc_n_172 : STD_LOGIC;
  signal myCrc_n_173 : STD_LOGIC;
  signal myCrc_n_174 : STD_LOGIC;
  signal myCrc_n_175 : STD_LOGIC;
  signal myCrc_n_176 : STD_LOGIC;
  signal myCrc_n_177 : STD_LOGIC;
  signal myCrc_n_178 : STD_LOGIC;
  signal myCrc_n_179 : STD_LOGIC;
  signal myCrc_n_180 : STD_LOGIC;
  signal myCrc_n_181 : STD_LOGIC;
  signal myCrc_n_182 : STD_LOGIC;
  signal myCrc_n_183 : STD_LOGIC;
  signal myCrc_n_184 : STD_LOGIC;
  signal myCrc_n_185 : STD_LOGIC;
  signal myCrc_n_186 : STD_LOGIC;
  signal myCrc_n_187 : STD_LOGIC;
  signal myCrc_n_188 : STD_LOGIC;
  signal myCrc_n_189 : STD_LOGIC;
  signal myCrc_n_19 : STD_LOGIC;
  signal myCrc_n_190 : STD_LOGIC;
  signal myCrc_n_191 : STD_LOGIC;
  signal myCrc_n_192 : STD_LOGIC;
  signal myCrc_n_193 : STD_LOGIC;
  signal myCrc_n_194 : STD_LOGIC;
  signal myCrc_n_195 : STD_LOGIC;
  signal myCrc_n_196 : STD_LOGIC;
  signal myCrc_n_197 : STD_LOGIC;
  signal myCrc_n_198 : STD_LOGIC;
  signal myCrc_n_199 : STD_LOGIC;
  signal myCrc_n_2 : STD_LOGIC;
  signal myCrc_n_20 : STD_LOGIC;
  signal myCrc_n_200 : STD_LOGIC;
  signal myCrc_n_201 : STD_LOGIC;
  signal myCrc_n_202 : STD_LOGIC;
  signal myCrc_n_203 : STD_LOGIC;
  signal myCrc_n_204 : STD_LOGIC;
  signal myCrc_n_205 : STD_LOGIC;
  signal myCrc_n_206 : STD_LOGIC;
  signal myCrc_n_207 : STD_LOGIC;
  signal myCrc_n_208 : STD_LOGIC;
  signal myCrc_n_209 : STD_LOGIC;
  signal myCrc_n_21 : STD_LOGIC;
  signal myCrc_n_210 : STD_LOGIC;
  signal myCrc_n_211 : STD_LOGIC;
  signal myCrc_n_212 : STD_LOGIC;
  signal myCrc_n_213 : STD_LOGIC;
  signal myCrc_n_214 : STD_LOGIC;
  signal myCrc_n_215 : STD_LOGIC;
  signal myCrc_n_216 : STD_LOGIC;
  signal myCrc_n_217 : STD_LOGIC;
  signal myCrc_n_218 : STD_LOGIC;
  signal myCrc_n_219 : STD_LOGIC;
  signal myCrc_n_22 : STD_LOGIC;
  signal myCrc_n_220 : STD_LOGIC;
  signal myCrc_n_221 : STD_LOGIC;
  signal myCrc_n_222 : STD_LOGIC;
  signal myCrc_n_223 : STD_LOGIC;
  signal myCrc_n_224 : STD_LOGIC;
  signal myCrc_n_225 : STD_LOGIC;
  signal myCrc_n_226 : STD_LOGIC;
  signal myCrc_n_227 : STD_LOGIC;
  signal myCrc_n_228 : STD_LOGIC;
  signal myCrc_n_229 : STD_LOGIC;
  signal myCrc_n_23 : STD_LOGIC;
  signal myCrc_n_230 : STD_LOGIC;
  signal myCrc_n_231 : STD_LOGIC;
  signal myCrc_n_232 : STD_LOGIC;
  signal myCrc_n_233 : STD_LOGIC;
  signal myCrc_n_234 : STD_LOGIC;
  signal myCrc_n_235 : STD_LOGIC;
  signal myCrc_n_236 : STD_LOGIC;
  signal myCrc_n_237 : STD_LOGIC;
  signal myCrc_n_238 : STD_LOGIC;
  signal myCrc_n_239 : STD_LOGIC;
  signal myCrc_n_24 : STD_LOGIC;
  signal myCrc_n_240 : STD_LOGIC;
  signal myCrc_n_241 : STD_LOGIC;
  signal myCrc_n_242 : STD_LOGIC;
  signal myCrc_n_243 : STD_LOGIC;
  signal myCrc_n_244 : STD_LOGIC;
  signal myCrc_n_245 : STD_LOGIC;
  signal myCrc_n_246 : STD_LOGIC;
  signal myCrc_n_247 : STD_LOGIC;
  signal myCrc_n_248 : STD_LOGIC;
  signal myCrc_n_249 : STD_LOGIC;
  signal myCrc_n_25 : STD_LOGIC;
  signal myCrc_n_250 : STD_LOGIC;
  signal myCrc_n_251 : STD_LOGIC;
  signal myCrc_n_252 : STD_LOGIC;
  signal myCrc_n_253 : STD_LOGIC;
  signal myCrc_n_254 : STD_LOGIC;
  signal myCrc_n_255 : STD_LOGIC;
  signal myCrc_n_256 : STD_LOGIC;
  signal myCrc_n_257 : STD_LOGIC;
  signal myCrc_n_258 : STD_LOGIC;
  signal myCrc_n_259 : STD_LOGIC;
  signal myCrc_n_26 : STD_LOGIC;
  signal myCrc_n_260 : STD_LOGIC;
  signal myCrc_n_261 : STD_LOGIC;
  signal myCrc_n_262 : STD_LOGIC;
  signal myCrc_n_263 : STD_LOGIC;
  signal myCrc_n_264 : STD_LOGIC;
  signal myCrc_n_265 : STD_LOGIC;
  signal myCrc_n_266 : STD_LOGIC;
  signal myCrc_n_267 : STD_LOGIC;
  signal myCrc_n_268 : STD_LOGIC;
  signal myCrc_n_269 : STD_LOGIC;
  signal myCrc_n_27 : STD_LOGIC;
  signal myCrc_n_270 : STD_LOGIC;
  signal myCrc_n_271 : STD_LOGIC;
  signal myCrc_n_272 : STD_LOGIC;
  signal myCrc_n_273 : STD_LOGIC;
  signal myCrc_n_274 : STD_LOGIC;
  signal myCrc_n_275 : STD_LOGIC;
  signal myCrc_n_276 : STD_LOGIC;
  signal myCrc_n_277 : STD_LOGIC;
  signal myCrc_n_278 : STD_LOGIC;
  signal myCrc_n_279 : STD_LOGIC;
  signal myCrc_n_28 : STD_LOGIC;
  signal myCrc_n_280 : STD_LOGIC;
  signal myCrc_n_281 : STD_LOGIC;
  signal myCrc_n_282 : STD_LOGIC;
  signal myCrc_n_283 : STD_LOGIC;
  signal myCrc_n_284 : STD_LOGIC;
  signal myCrc_n_285 : STD_LOGIC;
  signal myCrc_n_286 : STD_LOGIC;
  signal myCrc_n_287 : STD_LOGIC;
  signal myCrc_n_288 : STD_LOGIC;
  signal myCrc_n_289 : STD_LOGIC;
  signal myCrc_n_29 : STD_LOGIC;
  signal myCrc_n_290 : STD_LOGIC;
  signal myCrc_n_291 : STD_LOGIC;
  signal myCrc_n_292 : STD_LOGIC;
  signal myCrc_n_293 : STD_LOGIC;
  signal myCrc_n_294 : STD_LOGIC;
  signal myCrc_n_295 : STD_LOGIC;
  signal myCrc_n_296 : STD_LOGIC;
  signal myCrc_n_297 : STD_LOGIC;
  signal myCrc_n_298 : STD_LOGIC;
  signal myCrc_n_299 : STD_LOGIC;
  signal myCrc_n_3 : STD_LOGIC;
  signal myCrc_n_30 : STD_LOGIC;
  signal myCrc_n_300 : STD_LOGIC;
  signal myCrc_n_301 : STD_LOGIC;
  signal myCrc_n_302 : STD_LOGIC;
  signal myCrc_n_303 : STD_LOGIC;
  signal myCrc_n_304 : STD_LOGIC;
  signal myCrc_n_305 : STD_LOGIC;
  signal myCrc_n_306 : STD_LOGIC;
  signal myCrc_n_307 : STD_LOGIC;
  signal myCrc_n_308 : STD_LOGIC;
  signal myCrc_n_309 : STD_LOGIC;
  signal myCrc_n_31 : STD_LOGIC;
  signal myCrc_n_310 : STD_LOGIC;
  signal myCrc_n_311 : STD_LOGIC;
  signal myCrc_n_312 : STD_LOGIC;
  signal myCrc_n_313 : STD_LOGIC;
  signal myCrc_n_314 : STD_LOGIC;
  signal myCrc_n_315 : STD_LOGIC;
  signal myCrc_n_316 : STD_LOGIC;
  signal myCrc_n_317 : STD_LOGIC;
  signal myCrc_n_318 : STD_LOGIC;
  signal myCrc_n_319 : STD_LOGIC;
  signal myCrc_n_32 : STD_LOGIC;
  signal myCrc_n_320 : STD_LOGIC;
  signal myCrc_n_321 : STD_LOGIC;
  signal myCrc_n_322 : STD_LOGIC;
  signal myCrc_n_323 : STD_LOGIC;
  signal myCrc_n_324 : STD_LOGIC;
  signal myCrc_n_325 : STD_LOGIC;
  signal myCrc_n_326 : STD_LOGIC;
  signal myCrc_n_327 : STD_LOGIC;
  signal myCrc_n_328 : STD_LOGIC;
  signal myCrc_n_329 : STD_LOGIC;
  signal myCrc_n_33 : STD_LOGIC;
  signal myCrc_n_330 : STD_LOGIC;
  signal myCrc_n_331 : STD_LOGIC;
  signal myCrc_n_332 : STD_LOGIC;
  signal myCrc_n_333 : STD_LOGIC;
  signal myCrc_n_334 : STD_LOGIC;
  signal myCrc_n_335 : STD_LOGIC;
  signal myCrc_n_336 : STD_LOGIC;
  signal myCrc_n_337 : STD_LOGIC;
  signal myCrc_n_338 : STD_LOGIC;
  signal myCrc_n_339 : STD_LOGIC;
  signal myCrc_n_34 : STD_LOGIC;
  signal myCrc_n_340 : STD_LOGIC;
  signal myCrc_n_341 : STD_LOGIC;
  signal myCrc_n_342 : STD_LOGIC;
  signal myCrc_n_343 : STD_LOGIC;
  signal myCrc_n_344 : STD_LOGIC;
  signal myCrc_n_345 : STD_LOGIC;
  signal myCrc_n_346 : STD_LOGIC;
  signal myCrc_n_347 : STD_LOGIC;
  signal myCrc_n_348 : STD_LOGIC;
  signal myCrc_n_349 : STD_LOGIC;
  signal myCrc_n_350 : STD_LOGIC;
  signal myCrc_n_351 : STD_LOGIC;
  signal myCrc_n_352 : STD_LOGIC;
  signal myCrc_n_353 : STD_LOGIC;
  signal myCrc_n_354 : STD_LOGIC;
  signal myCrc_n_355 : STD_LOGIC;
  signal myCrc_n_356 : STD_LOGIC;
  signal myCrc_n_357 : STD_LOGIC;
  signal myCrc_n_358 : STD_LOGIC;
  signal myCrc_n_359 : STD_LOGIC;
  signal myCrc_n_36 : STD_LOGIC;
  signal myCrc_n_360 : STD_LOGIC;
  signal myCrc_n_361 : STD_LOGIC;
  signal myCrc_n_362 : STD_LOGIC;
  signal myCrc_n_363 : STD_LOGIC;
  signal myCrc_n_364 : STD_LOGIC;
  signal myCrc_n_365 : STD_LOGIC;
  signal myCrc_n_37 : STD_LOGIC;
  signal myCrc_n_38 : STD_LOGIC;
  signal myCrc_n_39 : STD_LOGIC;
  signal myCrc_n_4 : STD_LOGIC;
  signal myCrc_n_40 : STD_LOGIC;
  signal myCrc_n_41 : STD_LOGIC;
  signal myCrc_n_42 : STD_LOGIC;
  signal myCrc_n_43 : STD_LOGIC;
  signal myCrc_n_44 : STD_LOGIC;
  signal myCrc_n_45 : STD_LOGIC;
  signal myCrc_n_46 : STD_LOGIC;
  signal myCrc_n_47 : STD_LOGIC;
  signal myCrc_n_48 : STD_LOGIC;
  signal myCrc_n_49 : STD_LOGIC;
  signal myCrc_n_5 : STD_LOGIC;
  signal myCrc_n_50 : STD_LOGIC;
  signal myCrc_n_51 : STD_LOGIC;
  signal myCrc_n_52 : STD_LOGIC;
  signal myCrc_n_53 : STD_LOGIC;
  signal myCrc_n_54 : STD_LOGIC;
  signal myCrc_n_55 : STD_LOGIC;
  signal myCrc_n_56 : STD_LOGIC;
  signal myCrc_n_57 : STD_LOGIC;
  signal myCrc_n_58 : STD_LOGIC;
  signal myCrc_n_59 : STD_LOGIC;
  signal myCrc_n_6 : STD_LOGIC;
  signal myCrc_n_60 : STD_LOGIC;
  signal myCrc_n_61 : STD_LOGIC;
  signal myCrc_n_62 : STD_LOGIC;
  signal myCrc_n_63 : STD_LOGIC;
  signal myCrc_n_64 : STD_LOGIC;
  signal myCrc_n_65 : STD_LOGIC;
  signal myCrc_n_66 : STD_LOGIC;
  signal myCrc_n_67 : STD_LOGIC;
  signal myCrc_n_68 : STD_LOGIC;
  signal myCrc_n_69 : STD_LOGIC;
  signal myCrc_n_7 : STD_LOGIC;
  signal myCrc_n_70 : STD_LOGIC;
  signal myCrc_n_71 : STD_LOGIC;
  signal myCrc_n_72 : STD_LOGIC;
  signal myCrc_n_73 : STD_LOGIC;
  signal myCrc_n_74 : STD_LOGIC;
  signal myCrc_n_75 : STD_LOGIC;
  signal myCrc_n_76 : STD_LOGIC;
  signal myCrc_n_77 : STD_LOGIC;
  signal myCrc_n_78 : STD_LOGIC;
  signal myCrc_n_79 : STD_LOGIC;
  signal myCrc_n_8 : STD_LOGIC;
  signal myCrc_n_80 : STD_LOGIC;
  signal myCrc_n_81 : STD_LOGIC;
  signal myCrc_n_82 : STD_LOGIC;
  signal myCrc_n_83 : STD_LOGIC;
  signal myCrc_n_84 : STD_LOGIC;
  signal myCrc_n_85 : STD_LOGIC;
  signal myCrc_n_86 : STD_LOGIC;
  signal myCrc_n_87 : STD_LOGIC;
  signal myCrc_n_88 : STD_LOGIC;
  signal myCrc_n_89 : STD_LOGIC;
  signal myCrc_n_9 : STD_LOGIC;
  signal myCrc_n_90 : STD_LOGIC;
  signal myCrc_n_91 : STD_LOGIC;
  signal myCrc_n_92 : STD_LOGIC;
  signal myCrc_n_93 : STD_LOGIC;
  signal myCrc_n_94 : STD_LOGIC;
  signal myCrc_n_95 : STD_LOGIC;
  signal myCrc_n_96 : STD_LOGIC;
  signal myCrc_n_97 : STD_LOGIC;
  signal myCrc_n_98 : STD_LOGIC;
  signal myCrc_n_99 : STD_LOGIC;
  signal \myHdreng/rng\ : STD_LOGIC;
  signal myRxtx_n_0 : STD_LOGIC;
  signal myRxtx_n_1 : STD_LOGIC;
  signal myRxtx_n_10 : STD_LOGIC;
  signal myRxtx_n_11 : STD_LOGIC;
  signal myRxtx_n_12 : STD_LOGIC;
  signal myRxtx_n_129 : STD_LOGIC;
  signal myRxtx_n_13 : STD_LOGIC;
  signal myRxtx_n_130 : STD_LOGIC;
  signal myRxtx_n_131 : STD_LOGIC;
  signal myRxtx_n_132 : STD_LOGIC;
  signal myRxtx_n_133 : STD_LOGIC;
  signal myRxtx_n_134 : STD_LOGIC;
  signal myRxtx_n_135 : STD_LOGIC;
  signal myRxtx_n_136 : STD_LOGIC;
  signal myRxtx_n_137 : STD_LOGIC;
  signal myRxtx_n_138 : STD_LOGIC;
  signal myRxtx_n_139 : STD_LOGIC;
  signal myRxtx_n_140 : STD_LOGIC;
  signal myRxtx_n_141 : STD_LOGIC;
  signal myRxtx_n_142 : STD_LOGIC;
  signal myRxtx_n_143 : STD_LOGIC;
  signal myRxtx_n_144 : STD_LOGIC;
  signal myRxtx_n_145 : STD_LOGIC;
  signal myRxtx_n_146 : STD_LOGIC;
  signal myRxtx_n_147 : STD_LOGIC;
  signal myRxtx_n_148 : STD_LOGIC;
  signal myRxtx_n_149 : STD_LOGIC;
  signal myRxtx_n_150 : STD_LOGIC;
  signal myRxtx_n_151 : STD_LOGIC;
  signal myRxtx_n_152 : STD_LOGIC;
  signal myRxtx_n_153 : STD_LOGIC;
  signal myRxtx_n_154 : STD_LOGIC;
  signal myRxtx_n_155 : STD_LOGIC;
  signal myRxtx_n_156 : STD_LOGIC;
  signal myRxtx_n_157 : STD_LOGIC;
  signal myRxtx_n_158 : STD_LOGIC;
  signal myRxtx_n_159 : STD_LOGIC;
  signal myRxtx_n_160 : STD_LOGIC;
  signal myRxtx_n_161 : STD_LOGIC;
  signal myRxtx_n_162 : STD_LOGIC;
  signal myRxtx_n_163 : STD_LOGIC;
  signal myRxtx_n_164 : STD_LOGIC;
  signal myRxtx_n_165 : STD_LOGIC;
  signal myRxtx_n_166 : STD_LOGIC;
  signal myRxtx_n_167 : STD_LOGIC;
  signal myRxtx_n_168 : STD_LOGIC;
  signal myRxtx_n_169 : STD_LOGIC;
  signal myRxtx_n_170 : STD_LOGIC;
  signal myRxtx_n_171 : STD_LOGIC;
  signal myRxtx_n_172 : STD_LOGIC;
  signal myRxtx_n_173 : STD_LOGIC;
  signal myRxtx_n_174 : STD_LOGIC;
  signal myRxtx_n_175 : STD_LOGIC;
  signal myRxtx_n_176 : STD_LOGIC;
  signal myRxtx_n_177 : STD_LOGIC;
  signal myRxtx_n_178 : STD_LOGIC;
  signal myRxtx_n_179 : STD_LOGIC;
  signal myRxtx_n_180 : STD_LOGIC;
  signal myRxtx_n_181 : STD_LOGIC;
  signal myRxtx_n_182 : STD_LOGIC;
  signal myRxtx_n_183 : STD_LOGIC;
  signal myRxtx_n_184 : STD_LOGIC;
  signal myRxtx_n_185 : STD_LOGIC;
  signal myRxtx_n_186 : STD_LOGIC;
  signal myRxtx_n_187 : STD_LOGIC;
  signal myRxtx_n_188 : STD_LOGIC;
  signal myRxtx_n_189 : STD_LOGIC;
  signal myRxtx_n_190 : STD_LOGIC;
  signal myRxtx_n_191 : STD_LOGIC;
  signal myRxtx_n_192 : STD_LOGIC;
  signal myRxtx_n_193 : STD_LOGIC;
  signal myRxtx_n_194 : STD_LOGIC;
  signal myRxtx_n_195 : STD_LOGIC;
  signal myRxtx_n_196 : STD_LOGIC;
  signal myRxtx_n_197 : STD_LOGIC;
  signal myRxtx_n_198 : STD_LOGIC;
  signal myRxtx_n_199 : STD_LOGIC;
  signal myRxtx_n_2 : STD_LOGIC;
  signal myRxtx_n_20 : STD_LOGIC;
  signal myRxtx_n_200 : STD_LOGIC;
  signal myRxtx_n_201 : STD_LOGIC;
  signal myRxtx_n_202 : STD_LOGIC;
  signal myRxtx_n_203 : STD_LOGIC;
  signal myRxtx_n_204 : STD_LOGIC;
  signal myRxtx_n_205 : STD_LOGIC;
  signal myRxtx_n_206 : STD_LOGIC;
  signal myRxtx_n_207 : STD_LOGIC;
  signal myRxtx_n_208 : STD_LOGIC;
  signal myRxtx_n_209 : STD_LOGIC;
  signal myRxtx_n_21 : STD_LOGIC;
  signal myRxtx_n_210 : STD_LOGIC;
  signal myRxtx_n_211 : STD_LOGIC;
  signal myRxtx_n_212 : STD_LOGIC;
  signal myRxtx_n_213 : STD_LOGIC;
  signal myRxtx_n_214 : STD_LOGIC;
  signal myRxtx_n_215 : STD_LOGIC;
  signal myRxtx_n_216 : STD_LOGIC;
  signal myRxtx_n_217 : STD_LOGIC;
  signal myRxtx_n_218 : STD_LOGIC;
  signal myRxtx_n_219 : STD_LOGIC;
  signal myRxtx_n_22 : STD_LOGIC;
  signal myRxtx_n_220 : STD_LOGIC;
  signal myRxtx_n_221 : STD_LOGIC;
  signal myRxtx_n_222 : STD_LOGIC;
  signal myRxtx_n_223 : STD_LOGIC;
  signal myRxtx_n_224 : STD_LOGIC;
  signal myRxtx_n_225 : STD_LOGIC;
  signal myRxtx_n_226 : STD_LOGIC;
  signal myRxtx_n_227 : STD_LOGIC;
  signal myRxtx_n_228 : STD_LOGIC;
  signal myRxtx_n_229 : STD_LOGIC;
  signal myRxtx_n_23 : STD_LOGIC;
  signal myRxtx_n_230 : STD_LOGIC;
  signal myRxtx_n_231 : STD_LOGIC;
  signal myRxtx_n_232 : STD_LOGIC;
  signal myRxtx_n_233 : STD_LOGIC;
  signal myRxtx_n_234 : STD_LOGIC;
  signal myRxtx_n_235 : STD_LOGIC;
  signal myRxtx_n_236 : STD_LOGIC;
  signal myRxtx_n_237 : STD_LOGIC;
  signal myRxtx_n_238 : STD_LOGIC;
  signal myRxtx_n_239 : STD_LOGIC;
  signal myRxtx_n_24 : STD_LOGIC;
  signal myRxtx_n_240 : STD_LOGIC;
  signal myRxtx_n_241 : STD_LOGIC;
  signal myRxtx_n_242 : STD_LOGIC;
  signal myRxtx_n_243 : STD_LOGIC;
  signal myRxtx_n_244 : STD_LOGIC;
  signal myRxtx_n_245 : STD_LOGIC;
  signal myRxtx_n_246 : STD_LOGIC;
  signal myRxtx_n_247 : STD_LOGIC;
  signal myRxtx_n_248 : STD_LOGIC;
  signal myRxtx_n_249 : STD_LOGIC;
  signal myRxtx_n_25 : STD_LOGIC;
  signal myRxtx_n_250 : STD_LOGIC;
  signal myRxtx_n_251 : STD_LOGIC;
  signal myRxtx_n_252 : STD_LOGIC;
  signal myRxtx_n_253 : STD_LOGIC;
  signal myRxtx_n_254 : STD_LOGIC;
  signal myRxtx_n_255 : STD_LOGIC;
  signal myRxtx_n_256 : STD_LOGIC;
  signal myRxtx_n_257 : STD_LOGIC;
  signal myRxtx_n_258 : STD_LOGIC;
  signal myRxtx_n_259 : STD_LOGIC;
  signal myRxtx_n_26 : STD_LOGIC;
  signal myRxtx_n_260 : STD_LOGIC;
  signal myRxtx_n_261 : STD_LOGIC;
  signal myRxtx_n_262 : STD_LOGIC;
  signal myRxtx_n_263 : STD_LOGIC;
  signal myRxtx_n_264 : STD_LOGIC;
  signal myRxtx_n_265 : STD_LOGIC;
  signal myRxtx_n_266 : STD_LOGIC;
  signal myRxtx_n_267 : STD_LOGIC;
  signal myRxtx_n_268 : STD_LOGIC;
  signal myRxtx_n_269 : STD_LOGIC;
  signal myRxtx_n_27 : STD_LOGIC;
  signal myRxtx_n_270 : STD_LOGIC;
  signal myRxtx_n_271 : STD_LOGIC;
  signal myRxtx_n_272 : STD_LOGIC;
  signal myRxtx_n_273 : STD_LOGIC;
  signal myRxtx_n_274 : STD_LOGIC;
  signal myRxtx_n_275 : STD_LOGIC;
  signal myRxtx_n_276 : STD_LOGIC;
  signal myRxtx_n_277 : STD_LOGIC;
  signal myRxtx_n_278 : STD_LOGIC;
  signal myRxtx_n_279 : STD_LOGIC;
  signal myRxtx_n_280 : STD_LOGIC;
  signal myRxtx_n_281 : STD_LOGIC;
  signal myRxtx_n_282 : STD_LOGIC;
  signal myRxtx_n_283 : STD_LOGIC;
  signal myRxtx_n_284 : STD_LOGIC;
  signal myRxtx_n_285 : STD_LOGIC;
  signal myRxtx_n_286 : STD_LOGIC;
  signal myRxtx_n_287 : STD_LOGIC;
  signal myRxtx_n_288 : STD_LOGIC;
  signal myRxtx_n_289 : STD_LOGIC;
  signal myRxtx_n_29 : STD_LOGIC;
  signal myRxtx_n_290 : STD_LOGIC;
  signal myRxtx_n_291 : STD_LOGIC;
  signal myRxtx_n_292 : STD_LOGIC;
  signal myRxtx_n_293 : STD_LOGIC;
  signal myRxtx_n_294 : STD_LOGIC;
  signal myRxtx_n_295 : STD_LOGIC;
  signal myRxtx_n_296 : STD_LOGIC;
  signal myRxtx_n_297 : STD_LOGIC;
  signal myRxtx_n_298 : STD_LOGIC;
  signal myRxtx_n_299 : STD_LOGIC;
  signal myRxtx_n_3 : STD_LOGIC;
  signal myRxtx_n_30 : STD_LOGIC;
  signal myRxtx_n_300 : STD_LOGIC;
  signal myRxtx_n_301 : STD_LOGIC;
  signal myRxtx_n_302 : STD_LOGIC;
  signal myRxtx_n_303 : STD_LOGIC;
  signal myRxtx_n_304 : STD_LOGIC;
  signal myRxtx_n_305 : STD_LOGIC;
  signal myRxtx_n_306 : STD_LOGIC;
  signal myRxtx_n_307 : STD_LOGIC;
  signal myRxtx_n_308 : STD_LOGIC;
  signal myRxtx_n_309 : STD_LOGIC;
  signal myRxtx_n_31 : STD_LOGIC;
  signal myRxtx_n_310 : STD_LOGIC;
  signal myRxtx_n_311 : STD_LOGIC;
  signal myRxtx_n_312 : STD_LOGIC;
  signal myRxtx_n_313 : STD_LOGIC;
  signal myRxtx_n_314 : STD_LOGIC;
  signal myRxtx_n_315 : STD_LOGIC;
  signal myRxtx_n_316 : STD_LOGIC;
  signal myRxtx_n_317 : STD_LOGIC;
  signal myRxtx_n_318 : STD_LOGIC;
  signal myRxtx_n_319 : STD_LOGIC;
  signal myRxtx_n_32 : STD_LOGIC;
  signal myRxtx_n_320 : STD_LOGIC;
  signal myRxtx_n_321 : STD_LOGIC;
  signal myRxtx_n_322 : STD_LOGIC;
  signal myRxtx_n_323 : STD_LOGIC;
  signal myRxtx_n_324 : STD_LOGIC;
  signal myRxtx_n_325 : STD_LOGIC;
  signal myRxtx_n_326 : STD_LOGIC;
  signal myRxtx_n_327 : STD_LOGIC;
  signal myRxtx_n_328 : STD_LOGIC;
  signal myRxtx_n_329 : STD_LOGIC;
  signal myRxtx_n_330 : STD_LOGIC;
  signal myRxtx_n_331 : STD_LOGIC;
  signal myRxtx_n_332 : STD_LOGIC;
  signal myRxtx_n_333 : STD_LOGIC;
  signal myRxtx_n_334 : STD_LOGIC;
  signal myRxtx_n_335 : STD_LOGIC;
  signal myRxtx_n_336 : STD_LOGIC;
  signal myRxtx_n_337 : STD_LOGIC;
  signal myRxtx_n_338 : STD_LOGIC;
  signal myRxtx_n_339 : STD_LOGIC;
  signal myRxtx_n_34 : STD_LOGIC;
  signal myRxtx_n_340 : STD_LOGIC;
  signal myRxtx_n_341 : STD_LOGIC;
  signal myRxtx_n_342 : STD_LOGIC;
  signal myRxtx_n_343 : STD_LOGIC;
  signal myRxtx_n_344 : STD_LOGIC;
  signal myRxtx_n_345 : STD_LOGIC;
  signal myRxtx_n_346 : STD_LOGIC;
  signal myRxtx_n_347 : STD_LOGIC;
  signal myRxtx_n_348 : STD_LOGIC;
  signal myRxtx_n_349 : STD_LOGIC;
  signal myRxtx_n_35 : STD_LOGIC;
  signal myRxtx_n_350 : STD_LOGIC;
  signal myRxtx_n_351 : STD_LOGIC;
  signal myRxtx_n_352 : STD_LOGIC;
  signal myRxtx_n_353 : STD_LOGIC;
  signal myRxtx_n_354 : STD_LOGIC;
  signal myRxtx_n_355 : STD_LOGIC;
  signal myRxtx_n_356 : STD_LOGIC;
  signal myRxtx_n_357 : STD_LOGIC;
  signal myRxtx_n_358 : STD_LOGIC;
  signal myRxtx_n_359 : STD_LOGIC;
  signal myRxtx_n_36 : STD_LOGIC;
  signal myRxtx_n_360 : STD_LOGIC;
  signal myRxtx_n_361 : STD_LOGIC;
  signal myRxtx_n_362 : STD_LOGIC;
  signal myRxtx_n_363 : STD_LOGIC;
  signal myRxtx_n_364 : STD_LOGIC;
  signal myRxtx_n_365 : STD_LOGIC;
  signal myRxtx_n_366 : STD_LOGIC;
  signal myRxtx_n_367 : STD_LOGIC;
  signal myRxtx_n_368 : STD_LOGIC;
  signal myRxtx_n_369 : STD_LOGIC;
  signal myRxtx_n_37 : STD_LOGIC;
  signal myRxtx_n_370 : STD_LOGIC;
  signal myRxtx_n_371 : STD_LOGIC;
  signal myRxtx_n_372 : STD_LOGIC;
  signal myRxtx_n_373 : STD_LOGIC;
  signal myRxtx_n_374 : STD_LOGIC;
  signal myRxtx_n_375 : STD_LOGIC;
  signal myRxtx_n_376 : STD_LOGIC;
  signal myRxtx_n_377 : STD_LOGIC;
  signal myRxtx_n_378 : STD_LOGIC;
  signal myRxtx_n_379 : STD_LOGIC;
  signal myRxtx_n_38 : STD_LOGIC;
  signal myRxtx_n_380 : STD_LOGIC;
  signal myRxtx_n_381 : STD_LOGIC;
  signal myRxtx_n_382 : STD_LOGIC;
  signal myRxtx_n_383 : STD_LOGIC;
  signal myRxtx_n_384 : STD_LOGIC;
  signal myRxtx_n_385 : STD_LOGIC;
  signal myRxtx_n_386 : STD_LOGIC;
  signal myRxtx_n_387 : STD_LOGIC;
  signal myRxtx_n_388 : STD_LOGIC;
  signal myRxtx_n_389 : STD_LOGIC;
  signal myRxtx_n_39 : STD_LOGIC;
  signal myRxtx_n_390 : STD_LOGIC;
  signal myRxtx_n_391 : STD_LOGIC;
  signal myRxtx_n_392 : STD_LOGIC;
  signal myRxtx_n_393 : STD_LOGIC;
  signal myRxtx_n_394 : STD_LOGIC;
  signal myRxtx_n_395 : STD_LOGIC;
  signal myRxtx_n_396 : STD_LOGIC;
  signal myRxtx_n_397 : STD_LOGIC;
  signal myRxtx_n_398 : STD_LOGIC;
  signal myRxtx_n_399 : STD_LOGIC;
  signal myRxtx_n_4 : STD_LOGIC;
  signal myRxtx_n_40 : STD_LOGIC;
  signal myRxtx_n_400 : STD_LOGIC;
  signal myRxtx_n_401 : STD_LOGIC;
  signal myRxtx_n_402 : STD_LOGIC;
  signal myRxtx_n_403 : STD_LOGIC;
  signal myRxtx_n_404 : STD_LOGIC;
  signal myRxtx_n_405 : STD_LOGIC;
  signal myRxtx_n_406 : STD_LOGIC;
  signal myRxtx_n_407 : STD_LOGIC;
  signal myRxtx_n_408 : STD_LOGIC;
  signal myRxtx_n_409 : STD_LOGIC;
  signal myRxtx_n_41 : STD_LOGIC;
  signal myRxtx_n_410 : STD_LOGIC;
  signal myRxtx_n_411 : STD_LOGIC;
  signal myRxtx_n_412 : STD_LOGIC;
  signal myRxtx_n_413 : STD_LOGIC;
  signal myRxtx_n_414 : STD_LOGIC;
  signal myRxtx_n_415 : STD_LOGIC;
  signal myRxtx_n_416 : STD_LOGIC;
  signal myRxtx_n_417 : STD_LOGIC;
  signal myRxtx_n_418 : STD_LOGIC;
  signal myRxtx_n_419 : STD_LOGIC;
  signal myRxtx_n_42 : STD_LOGIC;
  signal myRxtx_n_420 : STD_LOGIC;
  signal myRxtx_n_421 : STD_LOGIC;
  signal myRxtx_n_422 : STD_LOGIC;
  signal myRxtx_n_423 : STD_LOGIC;
  signal myRxtx_n_424 : STD_LOGIC;
  signal myRxtx_n_425 : STD_LOGIC;
  signal myRxtx_n_426 : STD_LOGIC;
  signal myRxtx_n_427 : STD_LOGIC;
  signal myRxtx_n_428 : STD_LOGIC;
  signal myRxtx_n_429 : STD_LOGIC;
  signal myRxtx_n_43 : STD_LOGIC;
  signal myRxtx_n_430 : STD_LOGIC;
  signal myRxtx_n_431 : STD_LOGIC;
  signal myRxtx_n_432 : STD_LOGIC;
  signal myRxtx_n_433 : STD_LOGIC;
  signal myRxtx_n_434 : STD_LOGIC;
  signal myRxtx_n_435 : STD_LOGIC;
  signal myRxtx_n_436 : STD_LOGIC;
  signal myRxtx_n_437 : STD_LOGIC;
  signal myRxtx_n_438 : STD_LOGIC;
  signal myRxtx_n_439 : STD_LOGIC;
  signal myRxtx_n_44 : STD_LOGIC;
  signal myRxtx_n_440 : STD_LOGIC;
  signal myRxtx_n_441 : STD_LOGIC;
  signal myRxtx_n_442 : STD_LOGIC;
  signal myRxtx_n_443 : STD_LOGIC;
  signal myRxtx_n_444 : STD_LOGIC;
  signal myRxtx_n_445 : STD_LOGIC;
  signal myRxtx_n_446 : STD_LOGIC;
  signal myRxtx_n_447 : STD_LOGIC;
  signal myRxtx_n_448 : STD_LOGIC;
  signal myRxtx_n_449 : STD_LOGIC;
  signal myRxtx_n_45 : STD_LOGIC;
  signal myRxtx_n_450 : STD_LOGIC;
  signal myRxtx_n_451 : STD_LOGIC;
  signal myRxtx_n_452 : STD_LOGIC;
  signal myRxtx_n_453 : STD_LOGIC;
  signal myRxtx_n_454 : STD_LOGIC;
  signal myRxtx_n_455 : STD_LOGIC;
  signal myRxtx_n_456 : STD_LOGIC;
  signal myRxtx_n_457 : STD_LOGIC;
  signal myRxtx_n_458 : STD_LOGIC;
  signal myRxtx_n_459 : STD_LOGIC;
  signal myRxtx_n_46 : STD_LOGIC;
  signal myRxtx_n_460 : STD_LOGIC;
  signal myRxtx_n_461 : STD_LOGIC;
  signal myRxtx_n_462 : STD_LOGIC;
  signal myRxtx_n_463 : STD_LOGIC;
  signal myRxtx_n_464 : STD_LOGIC;
  signal myRxtx_n_465 : STD_LOGIC;
  signal myRxtx_n_466 : STD_LOGIC;
  signal myRxtx_n_467 : STD_LOGIC;
  signal myRxtx_n_468 : STD_LOGIC;
  signal myRxtx_n_469 : STD_LOGIC;
  signal myRxtx_n_47 : STD_LOGIC;
  signal myRxtx_n_470 : STD_LOGIC;
  signal myRxtx_n_471 : STD_LOGIC;
  signal myRxtx_n_472 : STD_LOGIC;
  signal myRxtx_n_473 : STD_LOGIC;
  signal myRxtx_n_474 : STD_LOGIC;
  signal myRxtx_n_475 : STD_LOGIC;
  signal myRxtx_n_476 : STD_LOGIC;
  signal myRxtx_n_477 : STD_LOGIC;
  signal myRxtx_n_478 : STD_LOGIC;
  signal myRxtx_n_479 : STD_LOGIC;
  signal myRxtx_n_48 : STD_LOGIC;
  signal myRxtx_n_480 : STD_LOGIC;
  signal myRxtx_n_481 : STD_LOGIC;
  signal myRxtx_n_482 : STD_LOGIC;
  signal myRxtx_n_483 : STD_LOGIC;
  signal myRxtx_n_484 : STD_LOGIC;
  signal myRxtx_n_485 : STD_LOGIC;
  signal myRxtx_n_486 : STD_LOGIC;
  signal myRxtx_n_487 : STD_LOGIC;
  signal myRxtx_n_488 : STD_LOGIC;
  signal myRxtx_n_489 : STD_LOGIC;
  signal myRxtx_n_49 : STD_LOGIC;
  signal myRxtx_n_490 : STD_LOGIC;
  signal myRxtx_n_491 : STD_LOGIC;
  signal myRxtx_n_492 : STD_LOGIC;
  signal myRxtx_n_493 : STD_LOGIC;
  signal myRxtx_n_5 : STD_LOGIC;
  signal myRxtx_n_50 : STD_LOGIC;
  signal myRxtx_n_51 : STD_LOGIC;
  signal myRxtx_n_52 : STD_LOGIC;
  signal myRxtx_n_53 : STD_LOGIC;
  signal myRxtx_n_534 : STD_LOGIC;
  signal myRxtx_n_535 : STD_LOGIC;
  signal myRxtx_n_536 : STD_LOGIC;
  signal myRxtx_n_54 : STD_LOGIC;
  signal myRxtx_n_55 : STD_LOGIC;
  signal myRxtx_n_552 : STD_LOGIC;
  signal myRxtx_n_553 : STD_LOGIC;
  signal myRxtx_n_554 : STD_LOGIC;
  signal myRxtx_n_555 : STD_LOGIC;
  signal myRxtx_n_556 : STD_LOGIC;
  signal myRxtx_n_557 : STD_LOGIC;
  signal myRxtx_n_558 : STD_LOGIC;
  signal myRxtx_n_559 : STD_LOGIC;
  signal myRxtx_n_56 : STD_LOGIC;
  signal myRxtx_n_560 : STD_LOGIC;
  signal myRxtx_n_561 : STD_LOGIC;
  signal myRxtx_n_562 : STD_LOGIC;
  signal myRxtx_n_563 : STD_LOGIC;
  signal myRxtx_n_564 : STD_LOGIC;
  signal myRxtx_n_567 : STD_LOGIC;
  signal myRxtx_n_568 : STD_LOGIC;
  signal myRxtx_n_569 : STD_LOGIC;
  signal myRxtx_n_57 : STD_LOGIC;
  signal myRxtx_n_570 : STD_LOGIC;
  signal myRxtx_n_571 : STD_LOGIC;
  signal myRxtx_n_572 : STD_LOGIC;
  signal myRxtx_n_575 : STD_LOGIC;
  signal myRxtx_n_58 : STD_LOGIC;
  signal myRxtx_n_581 : STD_LOGIC;
  signal myRxtx_n_59 : STD_LOGIC;
  signal myRxtx_n_598 : STD_LOGIC;
  signal myRxtx_n_6 : STD_LOGIC;
  signal myRxtx_n_60 : STD_LOGIC;
  signal myRxtx_n_608 : STD_LOGIC;
  signal myRxtx_n_61 : STD_LOGIC;
  signal myRxtx_n_62 : STD_LOGIC;
  signal myRxtx_n_63 : STD_LOGIC;
  signal myRxtx_n_7 : STD_LOGIC;
  signal myRxtx_n_8 : STD_LOGIC;
  signal myRxtx_n_9 : STD_LOGIC;
  signal myWordto_n_0 : STD_LOGIC;
  signal myWordto_n_1 : STD_LOGIC;
  signal myWordto_n_2 : STD_LOGIC;
  signal myXferto_n_0 : STD_LOGIC;
  signal myXferto_n_1 : STD_LOGIC;
  signal myXferto_n_2 : STD_LOGIC;
  signal myXferto_n_3 : STD_LOGIC;
  signal myXferto_n_4 : STD_LOGIC;
  signal \opbuf[0][7]_i_10_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_11_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_14_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_15_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_18_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_19_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_20_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_21_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_22_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_23_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_24_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_25_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_26_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_27_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_28_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_29_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_30_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_31_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_32_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_33_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_34_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_35_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_36_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_37_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_38_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_39_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_3_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_40_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_41_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_42_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_43_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_44_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_45_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_46_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_4_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_50_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_51_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_52_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_53_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_54_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_55_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_56_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_57_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_58_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_59_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_60_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_61_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_62_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_63_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_64_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_65_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_66_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_67_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_6_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_7_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_8_n_0\ : STD_LOGIC;
  signal \opbuf[0][7]_i_9_n_0\ : STD_LOGIC;
  signal \opbuf[1]_75\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \opbuf[2]_72\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \opbuf[3]_70\ : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal \opbuf[4]_73\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \opbuf[5]_71\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \opbuf[6]_74\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \opbuf_reg[0]3\ : STD_LOGIC_VECTOR ( 27 downto 4 );
  signal \opbuf_reg[0]5\ : STD_LOGIC_VECTOR ( 30 downto 6 );
  signal \opbuf_reg[0]51_in\ : STD_LOGIC_VECTOR ( 30 downto 6 );
  signal \opbuf_reg[0][7]_i_12_n_0\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_12_n_1\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_12_n_2\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_12_n_3\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_12_n_4\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_12_n_5\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_12_n_6\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_12_n_7\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_13_n_0\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_13_n_1\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_13_n_2\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_13_n_3\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_13_n_4\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_13_n_5\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_13_n_6\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_13_n_7\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_16_n_7\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_17_n_0\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_17_n_1\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_17_n_2\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_17_n_3\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_17_n_4\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_17_n_5\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_17_n_6\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_17_n_7\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_47_n_0\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_47_n_1\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_47_n_2\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_47_n_3\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_47_n_4\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_47_n_5\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_47_n_6\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_47_n_7\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_48_n_0\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_48_n_1\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_48_n_2\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_48_n_3\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_48_n_4\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_48_n_5\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_48_n_6\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_48_n_7\ : STD_LOGIC;
  signal \opbuf_reg[0][7]_i_49_n_7\ : STD_LOGIC;
  signal \opbuf_reg[1]_60\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \opbuf_reg[3]_64\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \opbuf_reg[4]_63\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \opbuf_reg[5]_62\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \opbuf_reg[6]_61\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \opbuf_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[0][3]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[0][4]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[0][5]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[0][6]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[0][7]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][0]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][1]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][2]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][3]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][4]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][5]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][6]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][7]\ : STD_LOGIC;
  signal p_0_in0 : STD_LOGIC;
  signal p_10_out : STD_LOGIC_VECTOR ( 9 to 9 );
  signal p_136_in : STD_LOGIC;
  signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal plusOp : STD_LOGIC_VECTOR ( 31 downto 3 );
  signal \pollbuf[0][7]_i_3_n_0\ : STD_LOGIC;
  signal \pollbuf[0][7]_i_4_n_0\ : STD_LOGIC;
  signal \pollbuf[0][7]_i_5_n_0\ : STD_LOGIC;
  signal \pollbuf[0][7]_i_6_n_0\ : STD_LOGIC;
  signal \pollbuf[0][7]_i_7_n_0\ : STD_LOGIC;
  signal \pollbuf[2][3]_i_2_n_0\ : STD_LOGIC;
  signal \pollbuf[2][3]_i_3_n_0\ : STD_LOGIC;
  signal \pollbuf[2][4]_i_2_n_0\ : STD_LOGIC;
  signal \pollbuf[2][4]_i_3_n_0\ : STD_LOGIC;
  signal \pollbuf[2][7]_i_2_n_0\ : STD_LOGIC;
  signal \pollbuf[2][7]_i_3_n_0\ : STD_LOGIC;
  signal \pollbuf_reg[0]_66\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \pollbuf_reg[1]_67\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \pollbuf_reg[2]_68\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \pollbuf_reg[3]_69\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal recvAXIS_tlast : STD_LOGIC;
  signal \^reqinvacquire\ : STD_LOGIC;
  signal \^reqinvassign\ : STD_LOGIC;
  signal \^reqinvconfig\ : STD_LOGIC;
  signal \^reqinvconfigsynth\ : STD_LOGIC;
  signal \^reqinvcornerconfig\ : STD_LOGIC;
  signal \^reqinvcputrackset\ : STD_LOGIC;
  signal \^reqinvdecimacquire\ : STD_LOGIC;
  signal \^reqinvdecimconfig\ : STD_LOGIC;
  signal \^reqinvdecimset\ : STD_LOGIC;
  signal \^reqinvdecimunlock\ : STD_LOGIC;
  signal \^reqinvdirectorconfig\ : STD_LOGIC;
  signal \^reqinvdirectorset\ : STD_LOGIC;
  signal \^reqinvgetcorereg\ : STD_LOGIC;
  signal \^reqinvgetreg\ : STD_LOGIC;
  signal \^reqinvhdrengset\ : STD_LOGIC;
  signal \^reqinvhshktrackclearmask\ : STD_LOGIC;
  signal \^reqinvhshktrackselect\ : STD_LOGIC;
  signal \^reqinvhshktrackset\ : STD_LOGIC;
  signal \^reqinvhshktracksetmask\ : STD_LOGIC;
  signal \^reqinvmemtrackclearmask\ : STD_LOGIC;
  signal \^reqinvmemtrackselect\ : STD_LOGIC;
  signal \^reqinvmemtrackset\ : STD_LOGIC;
  signal \^reqinvmemtracksetmask\ : STD_LOGIC;
  signal \^reqinvmodreg\ : STD_LOGIC;
  signal \^reqinvrotaryconfig\ : STD_LOGIC;
  signal \^reqinvrotarymoveto\ : STD_LOGIC;
  signal reqInvRotarySet : STD_LOGIC;
  signal \^reqinvrotaryzero\ : STD_LOGIC;
  signal \^reqinvselect\ : STD_LOGIC;
  signal reqInvSet : STD_LOGIC;
  signal \^reqinvsetcorereg\ : STD_LOGIC;
  signal \^reqinvsetreg\ : STD_LOGIC;
  signal \^reqinvstepmuxset\ : STD_LOGIC;
  signal \^reqinvtkclksrcsettkst\ : STD_LOGIC;
  signal \^reqinvtraceacquire\ : STD_LOGIC;
  signal \^reqinvtraceconfig\ : STD_LOGIC;
  signal reqInvTraceUnlock : STD_LOGIC;
  signal reqInvUnlock : STD_LOGIC;
  signal \^reqinvvidtrackselect\ : STD_LOGIC;
  signal \^reqinvvidtrackset\ : STD_LOGIC;
  signal reqResetFromHostif : STD_LOGIC;
  signal reqReset_sig_i_2_n_0 : STD_LOGIC;
  signal resid : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \resid[0]_i_2_n_0\ : STD_LOGIC;
  signal \resid[0]_i_3_n_0\ : STD_LOGIC;
  signal \resid[0]_i_4_n_0\ : STD_LOGIC;
  signal \resid[0]_i_5_n_0\ : STD_LOGIC;
  signal \resid[0]_i_6_n_0\ : STD_LOGIC;
  signal \resid[1]_i_10_n_0\ : STD_LOGIC;
  signal \resid[1]_i_11_n_0\ : STD_LOGIC;
  signal \resid[1]_i_12_n_0\ : STD_LOGIC;
  signal \resid[1]_i_13_n_0\ : STD_LOGIC;
  signal \resid[1]_i_14_n_0\ : STD_LOGIC;
  signal \resid[1]_i_15_n_0\ : STD_LOGIC;
  signal \resid[1]_i_16_n_0\ : STD_LOGIC;
  signal \resid[1]_i_17_n_0\ : STD_LOGIC;
  signal \resid[1]_i_18_n_0\ : STD_LOGIC;
  signal \resid[1]_i_19_n_0\ : STD_LOGIC;
  signal \resid[1]_i_20_n_0\ : STD_LOGIC;
  signal \resid[1]_i_21_n_0\ : STD_LOGIC;
  signal \resid[1]_i_22_n_0\ : STD_LOGIC;
  signal \resid[1]_i_2_n_0\ : STD_LOGIC;
  signal \resid[1]_i_3_n_0\ : STD_LOGIC;
  signal \resid[1]_i_4_n_0\ : STD_LOGIC;
  signal \resid[1]_i_5_n_0\ : STD_LOGIC;
  signal \resid[1]_i_6_n_0\ : STD_LOGIC;
  signal \resid[1]_i_7_n_0\ : STD_LOGIC;
  signal \resid[1]_i_8_n_0\ : STD_LOGIC;
  signal \resid[1]_i_9_n_0\ : STD_LOGIC;
  signal \resid[2]_i_10_n_0\ : STD_LOGIC;
  signal \resid[2]_i_11_n_0\ : STD_LOGIC;
  signal \resid[2]_i_12_n_0\ : STD_LOGIC;
  signal \resid[2]_i_13_n_0\ : STD_LOGIC;
  signal \resid[2]_i_14_n_0\ : STD_LOGIC;
  signal \resid[2]_i_15_n_0\ : STD_LOGIC;
  signal \resid[2]_i_16_n_0\ : STD_LOGIC;
  signal \resid[2]_i_17_n_0\ : STD_LOGIC;
  signal \resid[2]_i_18_n_0\ : STD_LOGIC;
  signal \resid[2]_i_19_n_0\ : STD_LOGIC;
  signal \resid[2]_i_20_n_0\ : STD_LOGIC;
  signal \resid[2]_i_21_n_0\ : STD_LOGIC;
  signal \resid[2]_i_22_n_0\ : STD_LOGIC;
  signal \resid[2]_i_23_n_0\ : STD_LOGIC;
  signal \resid[2]_i_24_n_0\ : STD_LOGIC;
  signal \resid[2]_i_25_n_0\ : STD_LOGIC;
  signal \resid[2]_i_26_n_0\ : STD_LOGIC;
  signal \resid[2]_i_27_n_0\ : STD_LOGIC;
  signal \resid[2]_i_28_n_0\ : STD_LOGIC;
  signal \resid[2]_i_29_n_0\ : STD_LOGIC;
  signal \resid[2]_i_30_n_0\ : STD_LOGIC;
  signal \resid[2]_i_31_n_0\ : STD_LOGIC;
  signal \resid[2]_i_32_n_0\ : STD_LOGIC;
  signal \resid[2]_i_3_n_0\ : STD_LOGIC;
  signal \resid[2]_i_4_n_0\ : STD_LOGIC;
  signal \resid[2]_i_5_n_0\ : STD_LOGIC;
  signal \resid[2]_i_6_n_0\ : STD_LOGIC;
  signal \resid[2]_i_7_n_0\ : STD_LOGIC;
  signal \resid[2]_i_8_n_0\ : STD_LOGIC;
  signal \resid[2]_i_9_n_0\ : STD_LOGIC;
  signal restart_i_3_n_0 : STD_LOGIC;
  signal \retbuf[0][0]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[0][0]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[0][0]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[0][0]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[0][0]_i_8_n_0\ : STD_LOGIC;
  signal \retbuf[0][1]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[0][1]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[0][1]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[0][1]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[0][1]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[0][2]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[0][2]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[0][3]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[0][3]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[0][3]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[0][4]_i_2__0_n_0\ : STD_LOGIC;
  signal \retbuf[0][4]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[0][4]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[0][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[0][5]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[0][5]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[0][6]_i_2__0_n_0\ : STD_LOGIC;
  signal \retbuf[0][6]_i_3__0_n_0\ : STD_LOGIC;
  signal \retbuf[0][6]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[0][6]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_11_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_12_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_13_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_14_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_15_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_16_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_17_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_18_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_19_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_20_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_21_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_22_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_23_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_24_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_25_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_26_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_27_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_28_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_29_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_30_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_8_n_0\ : STD_LOGIC;
  signal \retbuf[10][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[10][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[10][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[10][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[11][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[11][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[11][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[11][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[12][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[12][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[12][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[12][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[12][7]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[13][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[13][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[14][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[14][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[14][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[15][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[15][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[16][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[16][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[16][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[16][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[16][7]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[17][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[17][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[17][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[18][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[18][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[19][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[19][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[1][0]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[1][0]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[1][0]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[1][0]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[1][1]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[1][1]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[1][1]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[1][1]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[1][2]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[1][2]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[1][2]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[1][2]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[1][3]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[1][3]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[1][3]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[1][3]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[1][4]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[1][4]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[1][4]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[1][4]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[1][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[1][5]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[1][5]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[1][5]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[1][6]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[1][6]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[1][6]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[1][6]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[1][7]_i_10_n_0\ : STD_LOGIC;
  signal \retbuf[1][7]_i_11_n_0\ : STD_LOGIC;
  signal \retbuf[1][7]_i_12_n_0\ : STD_LOGIC;
  signal \retbuf[1][7]_i_14_n_0\ : STD_LOGIC;
  signal \retbuf[1][7]_i_15_n_0\ : STD_LOGIC;
  signal \retbuf[1][7]_i_16_n_0\ : STD_LOGIC;
  signal \retbuf[1][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[1][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[1][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[1][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[1][7]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[1][7]_i_8_n_0\ : STD_LOGIC;
  signal \retbuf[20][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[20][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[21][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[21][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[22][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[22][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[23][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[23][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[24][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[24][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[25][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[25][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[26][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[26][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[27][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[27][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[28][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[28][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[29][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[29][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[2][0]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[2][0]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[2][0]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[2][0]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[2][1]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[2][1]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[2][1]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[2][1]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[2][2]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[2][2]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[2][2]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[2][2]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[2][3]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[2][3]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[2][3]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[2][3]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[2][4]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[2][4]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[2][4]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[2][4]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[2][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[2][5]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[2][5]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[2][5]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[2][6]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[2][6]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[2][6]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[2][6]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[2][7]_i_10_n_0\ : STD_LOGIC;
  signal \retbuf[2][7]_i_11_n_0\ : STD_LOGIC;
  signal \retbuf[2][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[2][7]_i_4__0_n_0\ : STD_LOGIC;
  signal \retbuf[2][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[2][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[2][7]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[2][7]_i_9_n_0\ : STD_LOGIC;
  signal \retbuf[30][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[30][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[30][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[31][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[32][6]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[32][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[32][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[33][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[34][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[34][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[34][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[35][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[35][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[36][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[36][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[36][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[37][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[37][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[38][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[38][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[38][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[38][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[39][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[39][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[39][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[39][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[3][0]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[3][0]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[3][0]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[3][0]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[3][0]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[3][1]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[3][1]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[3][1]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[3][1]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[3][1]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[3][2]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[3][2]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[3][2]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[3][2]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[3][3]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[3][3]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[3][3]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[3][3]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[3][4]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[3][4]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[3][4]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[3][4]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[3][4]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[3][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[3][5]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[3][5]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[3][5]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[3][5]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[3][5]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[3][5]_i_8_n_0\ : STD_LOGIC;
  signal \retbuf[3][6]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[3][6]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[3][6]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[3][6]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_10_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_11_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_12_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_13_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_14_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_15_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_16_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_17_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_18_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_19_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_20_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_8_n_0\ : STD_LOGIC;
  signal \retbuf[3][7]_i_9_n_0\ : STD_LOGIC;
  signal \retbuf[4][0]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[4][0]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[4][0]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[4][0]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[4][1]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[4][1]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[4][1]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[4][1]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[4][2]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[4][2]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[4][2]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[4][2]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[4][3]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[4][3]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[4][3]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[4][3]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[4][4]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[4][4]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[4][4]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[4][4]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[4][4]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[4][4]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[4][4]_i_8_n_0\ : STD_LOGIC;
  signal \retbuf[4][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[4][5]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[4][5]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[4][5]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[4][5]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[4][5]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[4][5]_i_8_n_0\ : STD_LOGIC;
  signal \retbuf[4][6]_i_10_n_0\ : STD_LOGIC;
  signal \retbuf[4][6]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[4][6]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[4][6]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[4][6]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[4][6]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[4][6]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[4][6]_i_8_n_0\ : STD_LOGIC;
  signal \retbuf[4][6]_i_9_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_10_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_11_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_12_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_13_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_14_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_15_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_16_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_17_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_18_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_9_n_0\ : STD_LOGIC;
  signal \retbuf[5][0]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[5][0]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[5][0]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[5][1]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[5][1]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[5][1]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[5][2]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[5][2]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[5][3]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[5][3]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[5][4]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[5][4]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[5][5]_i_2__0_n_0\ : STD_LOGIC;
  signal \retbuf[5][5]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[5][5]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[5][6]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[5][6]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_10_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_11_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_12_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_13_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_14_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_15_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_16_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_17_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_18_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_8_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_9_n_0\ : STD_LOGIC;
  signal \retbuf[6][0]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[6][0]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[6][0]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[6][1]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[6][1]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[6][1]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[6][2]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[6][2]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[6][2]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[6][3]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[6][3]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[6][3]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[6][4]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[6][4]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[6][4]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[6][5]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[6][5]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[6][6]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[6][6]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[6][6]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[6][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[6][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[6][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[6][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[6][7]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[6][7]_i_8_n_0\ : STD_LOGIC;
  signal \retbuf[7][3]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[7][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[7][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[7][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[7][7]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_10_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_11_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_12_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_13_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_14_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_15_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_16_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_17_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_18_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_19_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_20_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_21_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_22_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_23_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_24_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_25_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_6_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_7_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_8_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_9_n_0\ : STD_LOGIC;
  signal \retbuf[9][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[9][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf_reg[0][1]_i_5_n_0\ : STD_LOGIC;
  signal \retbuf_reg[16]_65\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \retbuf_reg[1][0]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf_reg[1][1]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf_reg[1][2]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf_reg[1][3]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf_reg[1][4]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf_reg[1][5]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf_reg[1][6]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf_reg[1][7]_i_13_n_0\ : STD_LOGIC;
  signal \retbuf_reg[2][0]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf_reg[2][1]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf_reg[2][2]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf_reg[2][3]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf_reg[2][4]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf_reg[2][5]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf_reg[2][6]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf_reg[2][7]_i_8_n_0\ : STD_LOGIC;
  signal \retbuf_reg[6][5]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[10][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[10][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[10][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[10][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[10][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[10][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[10][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[10][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[12][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[12][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[12][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[12][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[12][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[12][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[12][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[12][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[13][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[13][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[13][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[13][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[13][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[13][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[13][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[13][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[14][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[14][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[14][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[14][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[14][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[14][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[14][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[14][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[15][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[15][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[15][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[15][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[15][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[15][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[15][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[15][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[17][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[17][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[17][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[17][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[17][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[17][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[17][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[17][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[18][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[18][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[18][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[18][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[18][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[18][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[18][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[18][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[19][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[19][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[19][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[19][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[19][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[19][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[19][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[19][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[20][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[20][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[20][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[20][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[20][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[20][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[20][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[20][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[21][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[21][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[21][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[21][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[21][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[21][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[21][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[21][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[22][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[22][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[22][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[22][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[22][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[22][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[22][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[22][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[23][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[23][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[23][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[23][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[23][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[23][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[23][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[23][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[24][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[24][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[24][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[24][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[24][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[24][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[24][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[24][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[25][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[25][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[25][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[25][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[25][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[25][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[25][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[25][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[26][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[26][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[26][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[26][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[26][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[26][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[26][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[26][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[27][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[27][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[27][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[27][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[27][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[27][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[27][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[27][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[28][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[28][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[28][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[28][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[28][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[28][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[28][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[28][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[29][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[29][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[29][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[29][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[29][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[29][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[29][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[29][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[30][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[30][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[30][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[30][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[30][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[30][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[30][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[30][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[31][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[31][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[31][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[31][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[31][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[31][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[31][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[31][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[34][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[34][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[34][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[34][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[34][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[34][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[34][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[34][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[7][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[7][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[7][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[7][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[7][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[7][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[7][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[7][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[9][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[9][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[9][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[9][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[9][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[9][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[9][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[9][7]\ : STD_LOGIC;
  signal rxAXIS_tdata : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \rxlen[0]_i_3_n_0\ : STD_LOGIC;
  signal \rxlen[0]_i_5_n_0\ : STD_LOGIC;
  signal \rxlen[0]_i_6_n_0\ : STD_LOGIC;
  signal \rxlen_reg_n_0_[0]\ : STD_LOGIC;
  signal \staTixVTrigger[7]_i_3__1_n_0\ : STD_LOGIC;
  signal \staTixVTrigger[7]_i_4__1_n_0\ : STD_LOGIC;
  signal \staTixVTrigger[7]_i_5_n_0\ : STD_LOGIC;
  signal \stateCorecfg[2]_i_6_n_0\ : STD_LOGIC;
  signal \stateCorecfg[2]_i_7_n_0\ : STD_LOGIC;
  signal \stateCorecfg[2]_i_8_n_0\ : STD_LOGIC;
  signal \stateCorecfg[2]_i_9_n_0\ : STD_LOGIC;
  signal \stateOp[0]_i_7_n_0\ : STD_LOGIC;
  signal \stateOp[0]_i_8_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_10__1_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_12_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_13_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_14_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_15_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_16_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_17_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_18_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_19_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_20_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_21_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_22_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_23_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_24_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_25_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_26_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_27_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_28_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_29_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_2__4_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_30_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_31_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_32_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_33_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_34_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_35_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_36_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_37_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_38_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_39_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_3__4_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_40_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_41_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_42_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_5__1_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_6__1_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_8__1_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_9__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_10__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_11__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_12__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_13__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_14__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_15__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_16__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_17__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_18__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_19__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_20__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_25__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_26__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_27__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_28__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_29__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_30__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_31__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_32__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_33__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_34__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_35__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_36__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_37__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_38__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_39__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_40__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_41__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_42__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_43__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_44__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_45__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_46__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_47__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_48__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_49__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_50__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_51__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_52__1_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_5_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_4_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_5_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_12_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_13_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_14_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_15_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_16_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_17_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_19_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_20_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_21_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_22_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_23_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_24_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_25_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_26_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_27_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_28_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_29_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_30_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_31_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_32_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_33_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_34_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_35_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_36_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_37_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_38_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_39_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_3_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_40_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_41_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_42_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_43_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_44_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_45_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_46_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_47_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_48_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_49_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_50_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_51_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_52_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_53_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_54_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_55_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_56_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_57_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_58_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_59_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_60_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_61_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_62_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_63_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_64_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_65_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_66_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_68_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_69_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_70_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_71_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_72_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_73_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_75_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_76_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_77_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_7_n_0\ : STD_LOGIC;
  signal \stateOp[5]_i_8_n_0\ : STD_LOGIC;
  signal \stateOp_i_2__0_n_0\ : STD_LOGIC;
  signal \stateOp_i_3__1_n_0\ : STD_LOGIC;
  signal \stateOp_i_4__1_n_0\ : STD_LOGIC;
  signal \stateOp_i_5__0_n_0\ : STD_LOGIC;
  signal \stateOp_i_5__1_n_0\ : STD_LOGIC;
  signal stateOp_next3144_in : STD_LOGIC;
  signal \stateOp_next[1]_i_2_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_11_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_13_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_14_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_15_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_16_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_17_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_18_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_19_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_20_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_21_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_22_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_23_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_2_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_3_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_4_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_5_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_6_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_7_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_8_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_9_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_10_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_11_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_12_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_13_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_14_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_15_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_16_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_17_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_18_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_19_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_20_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_21_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_22_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_23_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_3_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_4_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_5_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_6_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_7_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_8_n_0\ : STD_LOGIC;
  signal \stateOp_next[5]_i_9_n_0\ : STD_LOGIC;
  signal \stateOp_next_reg[4]_i_10_n_6\ : STD_LOGIC;
  signal \stateOp_next_reg[4]_i_10_n_7\ : STD_LOGIC;
  signal \stateOp_next_reg[4]_i_12_n_0\ : STD_LOGIC;
  signal \stateOp_next_reg[4]_i_12_n_1\ : STD_LOGIC;
  signal \stateOp_next_reg[4]_i_12_n_2\ : STD_LOGIC;
  signal \stateOp_next_reg[4]_i_12_n_3\ : STD_LOGIC;
  signal \stateOp_next_reg[4]_i_12_n_4\ : STD_LOGIC;
  signal \stateOp_next_reg[4]_i_12_n_5\ : STD_LOGIC;
  signal \stateOp_next_reg[4]_i_12_n_6\ : STD_LOGIC;
  signal \stateOp_next_reg[4]_i_12_n_7\ : STD_LOGIC;
  signal \stateOp_next_reg_n_0_[0]\ : STD_LOGIC;
  signal \stateOp_next_reg_n_0_[1]\ : STD_LOGIC;
  signal \stateOp_next_reg_n_0_[3]\ : STD_LOGIC;
  signal \stateOp_next_reg_n_0_[4]\ : STD_LOGIC;
  signal \stateOp_next_reg_n_0_[5]\ : STD_LOGIC;
  signal \^stateop_reg[0]_5\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^stateop_reg[1]_5\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_11_n_0\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_11_n_1\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_11_n_2\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_11_n_3\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_11_n_4\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_11_n_5\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_11_n_6\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_11_n_7\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_7_n_0\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_7_n_1\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_7_n_2\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_7_n_3\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_7_n_4\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_7_n_5\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_7_n_6\ : STD_LOGIC;
  signal \stateOp_reg[1]_i_7_n_7\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_21_n_3\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_21_n_5\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_21_n_6\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_21_n_7\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_22_n_0\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_22_n_1\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_22_n_2\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_22_n_3\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_22_n_4\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_22_n_5\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_22_n_6\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_22_n_7\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_23_n_0\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_23_n_1\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_23_n_2\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_23_n_3\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_23_n_4\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_23_n_5\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_23_n_6\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_23_n_7\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_24_n_0\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_24_n_1\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_24_n_2\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_24_n_3\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_24_n_4\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_24_n_5\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_24_n_6\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_24_n_7\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_6__0_n_5\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_6__0_n_6\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_6__0_n_7\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9__0_n_0\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9__0_n_1\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9__0_n_2\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9__0_n_3\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9__0_n_4\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9__0_n_5\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9__0_n_6\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9__0_n_7\ : STD_LOGIC;
  signal \^stateop_reg[5]_0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \stateSeqbufB[2]_i_10_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[2]_i_8_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[2]_i_9_n_0\ : STD_LOGIC;
  signal \^step1__6\ : STD_LOGIC;
  signal synthNotLive_i_2_n_0 : STD_LOGIC;
  signal targetNotSteady_i_3_n_0 : STD_LOGIC;
  signal targetNotSteady_i_4_n_0 : STD_LOGIC;
  signal \tixVBuffer[7]_i_3_n_0\ : STD_LOGIC;
  signal \tixVBuffer[7]_i_4_n_0\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[0]\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[1]\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[2]\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[3]\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[5]\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[6]\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[7]\ : STD_LOGIC;
  signal tixVBufxfop : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal tixVCommand : STD_LOGIC;
  signal \^tixvcommand_reg[0]_0\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[0]\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[1]\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[2]\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[3]\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[4]\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[5]\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[6]\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[7]\ : STD_LOGIC;
  signal \tixVController[7]_i_3_n_0\ : STD_LOGIC;
  signal \tixVController[7]_i_4_n_0\ : STD_LOGIC;
  signal \tixVController[7]_i_5_n_0\ : STD_LOGIC;
  signal \tixVController[7]_i_6_n_0\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[0]\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[1]\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[2]\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[3]\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[4]\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[5]\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[6]\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[7]\ : STD_LOGIC;
  signal \^tixvstate1\ : STD_LOGIC;
  signal \tixVState[1]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[0]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[0]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[0]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[0]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[10]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[10]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[10]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[10]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[11]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[11]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[11]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[11]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[12]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[12]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[12]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[12]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[13]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[13]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[13]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[13]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[14]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[14]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[14]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[14]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_10_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_11_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_12_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_14_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_15_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_17_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_9_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[16]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[16]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[16]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[16]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[16]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[17]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[17]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[17]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[17]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[17]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[18]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[18]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[18]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[18]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[18]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[19]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[19]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[19]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[19]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[19]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[1]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[1]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[1]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[1]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[20]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[20]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[20]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[20]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[20]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[21]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[21]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[21]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[21]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[21]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[22]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[22]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[22]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[22]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[22]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[22]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[23]_i_10_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[23]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[23]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[23]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[23]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[23]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[23]_i_9_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[24]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[24]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[24]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[24]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[24]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[25]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[25]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[25]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[25]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[25]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[26]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[26]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[26]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[26]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[26]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[27]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[27]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[27]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[27]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[27]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[28]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[28]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[28]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[28]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[28]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[29]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[29]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[29]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[29]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[29]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[29]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[29]_i_9_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[2]_i_10_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[2]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[2]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[2]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[2]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[2]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[2]_i_9_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[30]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[30]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[30]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[30]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[30]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_10_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_9_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[32]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[32]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[32]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[32]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[32]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[33]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[33]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[33]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[33]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[33]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[34]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[34]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[34]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[34]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[34]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[35]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[35]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[35]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[35]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[35]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[36]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[36]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[36]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[36]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[36]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[37]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[37]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[37]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[37]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[37]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[38]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[38]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[38]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[38]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[38]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[39]_i_10_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[39]_i_11_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[39]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[39]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[39]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[39]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[39]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[39]_i_9_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[3]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[3]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[3]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[3]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[3]_i_9_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[40]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[40]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[40]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[40]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[41]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[41]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[41]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[41]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[42]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[42]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[42]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[42]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[43]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[43]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[43]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[43]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[44]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[44]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[44]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[44]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[45]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[45]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[45]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[45]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[46]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[46]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[46]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[46]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[47]_i_10_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[47]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[47]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[47]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[47]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[47]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[48]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[48]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[48]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[48]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[49]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[49]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[49]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[49]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[4]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[4]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[4]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[4]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[4]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[50]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[50]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[50]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[50]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[51]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[51]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[51]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[51]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[52]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[52]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[52]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[52]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[53]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[53]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[53]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[53]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[54]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[54]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[54]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[54]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[55]_i_10_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[55]_i_11_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[55]_i_13_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[55]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[55]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[55]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[55]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[55]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[55]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[56]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[56]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[56]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[56]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[56]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[57]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[57]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[57]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[57]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[57]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[58]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[58]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[58]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[58]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[59]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[59]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[59]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[59]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[5]_i_10_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[5]_i_11_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[5]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[5]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[5]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[5]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[5]_i_9_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[60]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[60]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[60]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[60]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[60]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[61]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[61]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[61]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[61]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[61]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[62]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[62]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[62]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[62]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[63]_i_10_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[63]_i_11_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[63]_i_12_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[63]_i_13_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[63]_i_14_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[63]_i_15_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[63]_i_16_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[63]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[63]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[63]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[63]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[63]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[63]_i_9_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_10_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_11_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_12_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_7__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_9_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_10__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_11_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_13_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_14_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_15_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_16_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_8_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_9__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[8]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[8]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[8]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[8]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[9]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[9]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[9]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[9]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[1]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[3]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[5]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[0]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[10]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[11]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[12]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[13]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[14]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[15]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[16]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[17]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[18]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[19]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[1]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[20]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[21]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[22]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[23]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[24]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[25]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[26]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[27]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[28]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[29]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[2]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[30]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[31]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[32]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[33]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[34]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[35]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[36]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[37]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[38]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[39]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[3]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[40]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[41]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[42]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[43]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[44]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[45]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[46]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[47]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[48]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[49]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[4]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[50]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[51]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[52]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[53]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[54]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[55]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[56]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[57]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[58]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[59]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[5]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[60]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[61]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[62]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[63]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[6]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[7]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[8]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[9]\ : STD_LOGIC;
  signal txlast1 : STD_LOGIC_VECTOR ( 30 downto 0 );
  signal txlen : STD_LOGIC_VECTOR ( 28 downto 0 );
  signal \txlen[0]_i_2_n_0\ : STD_LOGIC;
  signal \txlen[28]_i_4_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[0]_i_2_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[16]_i_10_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[16]_i_3_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[16]_i_4_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[16]_i_5_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[16]_i_6_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[16]_i_7_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[16]_i_8_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[16]_i_9_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[24]_i_10_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[24]_i_11_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[24]_i_12_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[24]_i_13_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[24]_i_14_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[24]_i_3_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[24]_i_4_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[24]_i_6_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[24]_i_7_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[24]_i_8_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[24]_i_9_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[8]_i_10_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[8]_i_3_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[8]_i_4_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[8]_i_5_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[8]_i_6_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[8]_i_7_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[8]_i_8_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast[8]_i_9_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_1\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_10\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_11\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_12\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_13\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_14\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_15\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_2\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_3\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_4\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_5\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_6\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_7\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_8\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[16]_i_2_n_9\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_1\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_10\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_11\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_12\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_13\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_14\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_15\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_2\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_3\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_4\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_5\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_6\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_7\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_8\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[24]_i_5_n_9\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_1\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_10\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_11\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_12\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_13\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_14\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_15\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_2\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_3\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_4\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_5\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_6\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_7\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_8\ : STD_LOGIC;
  signal \wordcntCrcLast_reg[8]_i_2_n_9\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[0]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[10]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[11]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[12]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[13]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[14]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[15]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[16]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[17]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[18]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[19]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[1]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[20]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[21]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[22]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[23]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[24]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[2]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[3]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[4]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[5]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[6]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[7]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[8]\ : STD_LOGIC;
  signal \wordcntCrcLast_reg_n_0_[9]\ : STD_LOGIC;
  signal wordcntLast : STD_LOGIC_VECTOR ( 28 downto 0 );
  signal \wordcntLast[0]_i_10_n_0\ : STD_LOGIC;
  signal \wordcntLast[0]_i_11_n_0\ : STD_LOGIC;
  signal \wordcntLast[0]_i_12_n_0\ : STD_LOGIC;
  signal \wordcntLast[0]_i_2_n_0\ : STD_LOGIC;
  signal \wordcntLast[0]_i_3_n_0\ : STD_LOGIC;
  signal \wordcntLast[0]_i_4_n_0\ : STD_LOGIC;
  signal \wordcntLast[0]_i_5_n_0\ : STD_LOGIC;
  signal \wordcntLast[0]_i_6_n_0\ : STD_LOGIC;
  signal \wordcntLast[0]_i_7_n_0\ : STD_LOGIC;
  signal \wordcntLast[0]_i_8_n_0\ : STD_LOGIC;
  signal \wordcntLast[0]_i_9_n_0\ : STD_LOGIC;
  signal \wordcntLast[28]_i_10_n_0\ : STD_LOGIC;
  signal \wordcntLast[28]_i_12_n_0\ : STD_LOGIC;
  signal \wordcntLast[28]_i_19_n_0\ : STD_LOGIC;
  signal \wordcntLast[28]_i_3_n_0\ : STD_LOGIC;
  signal \wordcntLast[28]_i_4_n_0\ : STD_LOGIC;
  signal \wordcntLast[28]_i_5_n_0\ : STD_LOGIC;
  signal \wordcntLast[28]_i_6_n_0\ : STD_LOGIC;
  signal \wordcntLast[28]_i_8_n_0\ : STD_LOGIC;
  signal \wordcntLast[28]_i_9_n_0\ : STD_LOGIC;
  signal \wordcntLast[2]_i_2_n_0\ : STD_LOGIC;
  signal \wordcntLast_reg[13]_i_2_n_0\ : STD_LOGIC;
  signal \wordcntLast_reg[13]_i_2_n_1\ : STD_LOGIC;
  signal \wordcntLast_reg[13]_i_2_n_2\ : STD_LOGIC;
  signal \wordcntLast_reg[13]_i_2_n_3\ : STD_LOGIC;
  signal \wordcntLast_reg[13]_i_2_n_4\ : STD_LOGIC;
  signal \wordcntLast_reg[13]_i_2_n_5\ : STD_LOGIC;
  signal \wordcntLast_reg[13]_i_2_n_6\ : STD_LOGIC;
  signal \wordcntLast_reg[13]_i_2_n_7\ : STD_LOGIC;
  signal \wordcntLast_reg[21]_i_2_n_0\ : STD_LOGIC;
  signal \wordcntLast_reg[21]_i_2_n_1\ : STD_LOGIC;
  signal \wordcntLast_reg[21]_i_2_n_2\ : STD_LOGIC;
  signal \wordcntLast_reg[21]_i_2_n_3\ : STD_LOGIC;
  signal \wordcntLast_reg[21]_i_2_n_4\ : STD_LOGIC;
  signal \wordcntLast_reg[21]_i_2_n_5\ : STD_LOGIC;
  signal \wordcntLast_reg[21]_i_2_n_6\ : STD_LOGIC;
  signal \wordcntLast_reg[21]_i_2_n_7\ : STD_LOGIC;
  signal \wordcntLast_reg[28]_i_7_n_2\ : STD_LOGIC;
  signal \wordcntLast_reg[28]_i_7_n_3\ : STD_LOGIC;
  signal \wordcntLast_reg[28]_i_7_n_4\ : STD_LOGIC;
  signal \wordcntLast_reg[28]_i_7_n_5\ : STD_LOGIC;
  signal \wordcntLast_reg[28]_i_7_n_6\ : STD_LOGIC;
  signal \wordcntLast_reg[28]_i_7_n_7\ : STD_LOGIC;
  signal \wordcntLast_reg[5]_i_2_n_0\ : STD_LOGIC;
  signal \wordcntLast_reg[5]_i_2_n_1\ : STD_LOGIC;
  signal \wordcntLast_reg[5]_i_2_n_2\ : STD_LOGIC;
  signal \wordcntLast_reg[5]_i_2_n_3\ : STD_LOGIC;
  signal \wordcntLast_reg[5]_i_2_n_4\ : STD_LOGIC;
  signal \wordcntLast_reg[5]_i_2_n_5\ : STD_LOGIC;
  signal \wordcntLast_reg[5]_i_2_n_6\ : STD_LOGIC;
  signal \wordcntLast_reg[5]_i_2_n_7\ : STD_LOGIC;
  signal \wordcnt[30]_i_11_n_0\ : STD_LOGIC;
  signal \wordcnt[30]_i_6_n_0\ : STD_LOGIC;
  signal \wordcnt[30]_i_7_n_0\ : STD_LOGIC;
  signal \wordcnt[30]_i_9_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[30]_i_10_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[30]_i_10_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[30]_i_10_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[30]_i_10_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[30]_i_10_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2_n_7\ : STD_LOGIC;
  signal \wordcnt_reg_n_0_[25]\ : STD_LOGIC;
  signal \wordcnt_reg_n_0_[26]\ : STD_LOGIC;
  signal \wordcnt_reg_n_0_[27]\ : STD_LOGIC;
  signal \wordcnt_reg_n_0_[28]\ : STD_LOGIC;
  signal \wordcnt_reg_n_0_[29]\ : STD_LOGIC;
  signal \wordcnt_reg_n_0_[30]\ : STD_LOGIC;
  signal \NLW_crcAXIS_tkeep_reg[1]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_crcAXIS_tkeep_reg[1]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_crcAXIS_tkeep_reg[1]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_crcAXIS_tkeep_reg[7]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_crcAXIS_tkeep_reg[7]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_crcAXIS_tkeep_reg[7]_i_14_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_invbuf_reg[9][7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_opbuf_reg[0][7]_i_16_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_opbuf_reg[0][7]_i_16_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_opbuf_reg[0][7]_i_49_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_opbuf_reg[0][7]_i_49_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_stateOp_next_reg[4]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_stateOp_next_reg[4]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateOp_next_reg[4]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateOp_reg[1]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateOp_reg[1]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateOp_reg[2]_i_21_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_stateOp_reg[2]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_stateOp_reg[2]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_stateOp_reg[2]_i_6__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateOp_reg[2]_i_9__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_wordcntCrcLast_reg[24]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_wordcntLast_reg[28]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_wordcntLast_reg[28]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_wordcntLast_reg[5]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_wordcnt_reg[30]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_wordcnt_reg[30]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \TCaptMax[31]_i_1__0\ : label is "soft_lutpair2316";
  attribute SOFT_HLUTNM of \TCaptMax[31]_i_1__1\ : label is "soft_lutpair2320";
  attribute SOFT_HLUTNM of \TCaptMax[31]_i_2__1\ : label is "soft_lutpair2361";
  attribute SOFT_HLUTNM of \ackInvAcquire_sig_i_1__1\ : label is "soft_lutpair2319";
  attribute SOFT_HLUTNM of ackInvAssign_sig_i_1 : label is "soft_lutpair2359";
  attribute SOFT_HLUTNM of ackInvConfigSynth_sig_i_2 : label is "soft_lutpair2353";
  attribute SOFT_HLUTNM of ackInvConfigSynth_sig_i_3 : label is "soft_lutpair2326";
  attribute SOFT_HLUTNM of ackInvConfigSynth_sig_i_4 : label is "soft_lutpair2327";
  attribute SOFT_HLUTNM of ackInvConfig_sig_i_3 : label is "soft_lutpair2326";
  attribute SOFT_HLUTNM of ackInvConfig_sig_i_6 : label is "soft_lutpair2366";
  attribute SOFT_HLUTNM of ackInvGetCorereg_sig_i_2 : label is "soft_lutpair2315";
  attribute SOFT_HLUTNM of ackInvGetCorereg_sig_i_3 : label is "soft_lutpair2315";
  attribute SOFT_HLUTNM of ackInvMoveto_sig_i_3 : label is "soft_lutpair2271";
  attribute SOFT_HLUTNM of ackInvMoveto_sig_i_5 : label is "soft_lutpair2363";
  attribute SOFT_HLUTNM of \ackInvSelect_sig_i_2__0\ : label is "soft_lutpair2323";
  attribute SOFT_HLUTNM of \ackInvSetMask_sig_i_2__0\ : label is "soft_lutpair2330";
  attribute SOFT_HLUTNM of ackInvSetMask_sig_i_3 : label is "soft_lutpair2322";
  attribute SOFT_HLUTNM of \ackInvSet_sig_i_1__3\ : label is "soft_lutpair2349";
  attribute SOFT_HLUTNM of \ackInvSet_sig_i_1__5\ : label is "soft_lutpair2272";
  attribute SOFT_HLUTNM of \ackInvSet_sig_i_2__1\ : label is "soft_lutpair2361";
  attribute SOFT_HLUTNM of \ackInvSet_sig_i_2__2\ : label is "soft_lutpair2365";
  attribute SOFT_HLUTNM of ackInvSet_sig_i_5 : label is "soft_lutpair2273";
  attribute SOFT_HLUTNM of ackInvSet_sig_i_6 : label is "soft_lutpair2403";
  attribute SOFT_HLUTNM of ackInvSet_sig_i_7 : label is "soft_lutpair2366";
  attribute SOFT_HLUTNM of ackInvSet_sig_i_8 : label is "soft_lutpair2333";
  attribute SOFT_HLUTNM of ackInvUnlock_sig_i_2 : label is "soft_lutpair2364";
  attribute SOFT_HLUTNM of \ackInvUnlock_sig_i_2__0\ : label is "soft_lutpair2367";
  attribute SOFT_HLUTNM of ackInvUnlock_sig_i_4 : label is "soft_lutpair2411";
  attribute SOFT_HLUTNM of ackInvZero_sig_i_2 : label is "soft_lutpair2364";
  attribute SOFT_HLUTNM of \corecfgAXIL_araddr[2]_i_1\ : label is "soft_lutpair2385";
  attribute SOFT_HLUTNM of \corecfgAXIL_araddr[3]_i_1\ : label is "soft_lutpair2385";
  attribute SOFT_HLUTNM of \corecfgAXIL_araddr[4]_i_1\ : label is "soft_lutpair2386";
  attribute SOFT_HLUTNM of \corecfgAXIL_araddr[5]_i_1\ : label is "soft_lutpair2386";
  attribute SOFT_HLUTNM of \corecfgAXIL_araddr[6]_i_1\ : label is "soft_lutpair2387";
  attribute SOFT_HLUTNM of \corecfgAXIL_araddr[7]_i_1\ : label is "soft_lutpair2387";
  attribute SOFT_HLUTNM of \corecfgAXIL_awaddr[2]_i_1\ : label is "soft_lutpair2348";
  attribute SOFT_HLUTNM of \corecfgAXIL_awaddr[3]_i_1\ : label is "soft_lutpair2382";
  attribute SOFT_HLUTNM of \corecfgAXIL_awaddr[4]_i_1\ : label is "soft_lutpair2382";
  attribute SOFT_HLUTNM of \corecfgAXIL_awaddr[5]_i_1\ : label is "soft_lutpair2383";
  attribute SOFT_HLUTNM of \corecfgAXIL_awaddr[6]_i_1\ : label is "soft_lutpair2383";
  attribute SOFT_HLUTNM of \corecfgAXIL_awaddr[7]_i_1\ : label is "soft_lutpair2384";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[0]_i_1\ : label is "soft_lutpair2384";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[10]_i_1\ : label is "soft_lutpair2392";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[11]_i_1\ : label is "soft_lutpair2393";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[12]_i_1\ : label is "soft_lutpair2393";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[13]_i_1\ : label is "soft_lutpair2394";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[14]_i_1\ : label is "soft_lutpair2394";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[15]_i_1\ : label is "soft_lutpair2395";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[16]_i_1\ : label is "soft_lutpair2395";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[17]_i_1\ : label is "soft_lutpair2396";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[18]_i_1\ : label is "soft_lutpair2396";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[19]_i_1\ : label is "soft_lutpair2397";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[1]_i_1\ : label is "soft_lutpair2388";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[20]_i_1\ : label is "soft_lutpair2397";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[21]_i_1\ : label is "soft_lutpair2398";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[22]_i_1\ : label is "soft_lutpair2398";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[23]_i_1\ : label is "soft_lutpair2399";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[24]_i_1\ : label is "soft_lutpair2399";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[25]_i_1\ : label is "soft_lutpair2400";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[26]_i_1\ : label is "soft_lutpair2400";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[27]_i_1\ : label is "soft_lutpair2401";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[28]_i_1\ : label is "soft_lutpair2401";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[29]_i_1\ : label is "soft_lutpair2402";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[2]_i_1\ : label is "soft_lutpair2388";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[30]_i_1\ : label is "soft_lutpair2402";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[3]_i_1\ : label is "soft_lutpair2389";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[4]_i_1\ : label is "soft_lutpair2389";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[5]_i_1\ : label is "soft_lutpair2390";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[6]_i_1\ : label is "soft_lutpair2390";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[7]_i_1\ : label is "soft_lutpair2391";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[8]_i_1\ : label is "soft_lutpair2391";
  attribute SOFT_HLUTNM of \corecfgAXIL_wdata[9]_i_1\ : label is "soft_lutpair2392";
  attribute SOFT_HLUTNM of crcAXIS_tlast_sig_i_13 : label is "soft_lutpair2406";
  attribute SOFT_HLUTNM of crcAXIS_tlast_sig_i_15 : label is "soft_lutpair2368";
  attribute SOFT_HLUTNM of crcAXIS_tlast_sig_i_9 : label is "soft_lutpair2381";
  attribute SOFT_HLUTNM of hdrNotFix_i_1 : label is "soft_lutpair2268";
  attribute SOFT_HLUTNM of i2cReadNotWrite_i_2 : label is "soft_lutpair2270";
  attribute SOFT_HLUTNM of \i2cRegaddr[13]_i_2\ : label is "soft_lutpair2270";
  attribute SOFT_HLUTNM of \i2cRegaddr[15]_i_11\ : label is "soft_lutpair2291";
  attribute SOFT_HLUTNM of \i2cRegaddr[15]_i_5\ : label is "soft_lutpair2403";
  attribute SOFT_HLUTNM of \i2cRegaddr[15]_i_6\ : label is "soft_lutpair2365";
  attribute SOFT_HLUTNM of \i2cRegaddr[15]_i_7\ : label is "soft_lutpair2367";
  attribute SOFT_HLUTNM of \i__i_1\ : label is "soft_lutpair2352";
  attribute SOFT_HLUTNM of \i__i_2\ : label is "soft_lutpair2352";
  attribute SOFT_HLUTNM of \invbuf[0][7]_i_2\ : label is "soft_lutpair2324";
  attribute SOFT_HLUTNM of \invbuf[9][7]_i_11\ : label is "soft_lutpair2298";
  attribute SOFT_HLUTNM of \invbuf[9][7]_i_18\ : label is "soft_lutpair2298";
  attribute SOFT_HLUTNM of \invbuf[9][7]_i_3\ : label is "soft_lutpair2413";
  attribute SOFT_HLUTNM of \invbuf[9][7]_i_5\ : label is "soft_lutpair2410";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \invbuf_reg[9][7]_i_12\ : label is 35;
  attribute SOFT_HLUTNM of \ixMemNext[0]_i_1\ : label is "soft_lutpair2359";
  attribute SOFT_HLUTNM of \ixMemNext[1]_i_1\ : label is "soft_lutpair2358";
  attribute SOFT_HLUTNM of \ixMemNext[2]_i_1\ : label is "soft_lutpair2355";
  attribute SOFT_HLUTNM of \ixMemNext[3]_i_1\ : label is "soft_lutpair2358";
  attribute SOFT_HLUTNM of \ixMemNext[4]_i_1\ : label is "soft_lutpair2357";
  attribute SOFT_HLUTNM of \ixMemNext[5]_i_1\ : label is "soft_lutpair2357";
  attribute SOFT_HLUTNM of \ixMemNext[6]_i_1\ : label is "soft_lutpair2356";
  attribute SOFT_HLUTNM of \ixMemNext[7]_i_1\ : label is "soft_lutpair2274";
  attribute SOFT_HLUTNM of \ixMemNext[7]_i_2\ : label is "soft_lutpair2356";
  attribute SOFT_HLUTNM of \ixRetbufCrc[4]_i_3\ : label is "soft_lutpair2338";
  attribute SOFT_HLUTNM of \ixRetbufCrc[4]_i_4\ : label is "soft_lutpair2304";
  attribute SOFT_HLUTNM of \ixRetbufCrc[4]_i_5\ : label is "soft_lutpair2377";
  attribute SOFT_HLUTNM of \ixTExp_lcl[3]_i_1\ : label is "soft_lutpair2269";
  attribute SOFT_HLUTNM of \lastAXIS_tkeep[3]_i_2\ : label is "soft_lutpair2314";
  attribute SOFT_HLUTNM of \lastAXIS_tkeep[6]_i_2\ : label is "soft_lutpair2314";
  attribute SOFT_HLUTNM of \lastAXIS_tkeep[7]_i_2\ : label is "soft_lutpair2351";
  attribute SOFT_HLUTNM of linNotRot_i_2 : label is "soft_lutpair2268";
  attribute SOFT_HLUTNM of \lsb[0]_i_1\ : label is "soft_lutpair2300";
  attribute SOFT_HLUTNM of \lsb[1]_i_1\ : label is "soft_lutpair2300";
  attribute SOFT_HLUTNM of \lsb[1]_i_2\ : label is "soft_lutpair2347";
  attribute SOFT_HLUTNM of \mask[1]_i_2\ : label is "soft_lutpair2354";
  attribute SOFT_HLUTNM of \mask[3]_i_2\ : label is "soft_lutpair2347";
  attribute SOFT_HLUTNM of \mask[4]_i_2\ : label is "soft_lutpair2321";
  attribute SOFT_HLUTNM of \mask[5]_i_2\ : label is "soft_lutpair2317";
  attribute SOFT_HLUTNM of \mask[5]_i_2__0\ : label is "soft_lutpair2355";
  attribute SOFT_HLUTNM of \mask[5]_i_3\ : label is "soft_lutpair2321";
  attribute SOFT_HLUTNM of \mask[6]_i_2\ : label is "soft_lutpair2318";
  attribute SOFT_HLUTNM of \mask[7]_i_2\ : label is "soft_lutpair2354";
  attribute SOFT_HLUTNM of \mask[7]_i_3\ : label is "soft_lutpair2317";
  attribute SOFT_HLUTNM of \mask[8]_i_3\ : label is "soft_lutpair2318";
  attribute ADDER_THRESHOLD of \opbuf_reg[0][7]_i_47\ : label is 35;
  attribute ADDER_THRESHOLD of \opbuf_reg[0][7]_i_48\ : label is 35;
  attribute ADDER_THRESHOLD of \opbuf_reg[0][7]_i_49\ : label is 35;
  attribute SOFT_HLUTNM of \pollbuf[0][7]_i_3\ : label is "soft_lutpair2264";
  attribute SOFT_HLUTNM of \pollbuf[0][7]_i_4\ : label is "soft_lutpair2264";
  attribute SOFT_HLUTNM of \pollbuf[0][7]_i_5\ : label is "soft_lutpair2324";
  attribute SOFT_HLUTNM of \resid[0]_i_3\ : label is "soft_lutpair2289";
  attribute SOFT_HLUTNM of \resid[0]_i_5\ : label is "soft_lutpair2286";
  attribute SOFT_HLUTNM of \resid[1]_i_10\ : label is "soft_lutpair2284";
  attribute SOFT_HLUTNM of \resid[1]_i_17\ : label is "soft_lutpair2304";
  attribute SOFT_HLUTNM of \resid[1]_i_18\ : label is "soft_lutpair2377";
  attribute SOFT_HLUTNM of \resid[1]_i_19\ : label is "soft_lutpair2293";
  attribute SOFT_HLUTNM of \resid[1]_i_20\ : label is "soft_lutpair2412";
  attribute SOFT_HLUTNM of \resid[1]_i_22\ : label is "soft_lutpair2338";
  attribute SOFT_HLUTNM of \resid[1]_i_7\ : label is "soft_lutpair2333";
  attribute SOFT_HLUTNM of \resid[1]_i_9\ : label is "soft_lutpair2287";
  attribute SOFT_HLUTNM of \resid[2]_i_15\ : label is "soft_lutpair2289";
  attribute SOFT_HLUTNM of \resid[2]_i_18\ : label is "soft_lutpair2374";
  attribute SOFT_HLUTNM of \resid[2]_i_19\ : label is "soft_lutpair2283";
  attribute SOFT_HLUTNM of \resid[2]_i_24\ : label is "soft_lutpair2335";
  attribute SOFT_HLUTNM of \resid[2]_i_25\ : label is "soft_lutpair2276";
  attribute SOFT_HLUTNM of \resid[2]_i_26\ : label is "soft_lutpair2265";
  attribute SOFT_HLUTNM of \resid[2]_i_29\ : label is "soft_lutpair2336";
  attribute SOFT_HLUTNM of \resid[2]_i_5\ : label is "soft_lutpair2331";
  attribute SOFT_HLUTNM of \retbuf[0][7]_i_13\ : label is "soft_lutpair2265";
  attribute SOFT_HLUTNM of \retbuf[0][7]_i_16\ : label is "soft_lutpair2284";
  attribute SOFT_HLUTNM of \retbuf[0][7]_i_18\ : label is "soft_lutpair2416";
  attribute SOFT_HLUTNM of \retbuf[0][7]_i_19\ : label is "soft_lutpair2292";
  attribute SOFT_HLUTNM of \retbuf[0][7]_i_21\ : label is "soft_lutpair2282";
  attribute SOFT_HLUTNM of \retbuf[0][7]_i_22\ : label is "soft_lutpair2282";
  attribute SOFT_HLUTNM of \retbuf[0][7]_i_25\ : label is "soft_lutpair2285";
  attribute SOFT_HLUTNM of \retbuf[0][7]_i_29\ : label is "soft_lutpair2412";
  attribute SOFT_HLUTNM of \retbuf[0][7]_i_5\ : label is "soft_lutpair2406";
  attribute SOFT_HLUTNM of \retbuf[0][7]_i_7\ : label is "soft_lutpair2277";
  attribute SOFT_HLUTNM of \retbuf[11][7]_i_5\ : label is "soft_lutpair2419";
  attribute SOFT_HLUTNM of \retbuf[11][7]_i_6\ : label is "soft_lutpair2417";
  attribute SOFT_HLUTNM of \retbuf[12][7]_i_7\ : label is "soft_lutpair2418";
  attribute SOFT_HLUTNM of \retbuf[14][7]_i_5\ : label is "soft_lutpair2419";
  attribute SOFT_HLUTNM of \retbuf[16][5]_i_2\ : label is "soft_lutpair2340";
  attribute SOFT_HLUTNM of \retbuf[16][7]_i_7\ : label is "soft_lutpair2306";
  attribute SOFT_HLUTNM of \retbuf[17][7]_i_4\ : label is "soft_lutpair2307";
  attribute SOFT_HLUTNM of \retbuf[1][7]_i_11\ : label is "soft_lutpair2295";
  attribute SOFT_HLUTNM of \retbuf[1][7]_i_12\ : label is "soft_lutpair2416";
  attribute SOFT_HLUTNM of \retbuf[1][7]_i_4\ : label is "soft_lutpair2275";
  attribute SOFT_HLUTNM of \retbuf[20][7]_i_4\ : label is "soft_lutpair2307";
  attribute SOFT_HLUTNM of \retbuf[21][7]_i_4\ : label is "soft_lutpair2308";
  attribute SOFT_HLUTNM of \retbuf[22][7]_i_4\ : label is "soft_lutpair2308";
  attribute SOFT_HLUTNM of \retbuf[23][7]_i_4\ : label is "soft_lutpair2309";
  attribute SOFT_HLUTNM of \retbuf[24][7]_i_4\ : label is "soft_lutpair2309";
  attribute SOFT_HLUTNM of \retbuf[25][7]_i_4\ : label is "soft_lutpair2310";
  attribute SOFT_HLUTNM of \retbuf[26][7]_i_4\ : label is "soft_lutpair2310";
  attribute SOFT_HLUTNM of \retbuf[27][7]_i_4\ : label is "soft_lutpair2311";
  attribute SOFT_HLUTNM of \retbuf[28][7]_i_4\ : label is "soft_lutpair2311";
  attribute SOFT_HLUTNM of \retbuf[29][7]_i_3\ : label is "soft_lutpair2346";
  attribute SOFT_HLUTNM of \retbuf[29][7]_i_4\ : label is "soft_lutpair2418";
  attribute SOFT_HLUTNM of \retbuf[2][7]_i_6\ : label is "soft_lutpair2343";
  attribute SOFT_HLUTNM of \retbuf[2][7]_i_7\ : label is "soft_lutpair2417";
  attribute SOFT_HLUTNM of \retbuf[30][7]_i_5\ : label is "soft_lutpair2312";
  attribute SOFT_HLUTNM of \retbuf[33][7]_i_3\ : label is "soft_lutpair2295";
  attribute SOFT_HLUTNM of \retbuf[34][7]_i_5\ : label is "soft_lutpair2312";
  attribute SOFT_HLUTNM of \retbuf[36][7]_i_4\ : label is "soft_lutpair2369";
  attribute SOFT_HLUTNM of \retbuf[38][7]_i_4\ : label is "soft_lutpair2343";
  attribute SOFT_HLUTNM of \retbuf[38][7]_i_5\ : label is "soft_lutpair2369";
  attribute SOFT_HLUTNM of \retbuf[39][7]_i_3\ : label is "soft_lutpair2262";
  attribute SOFT_HLUTNM of \retbuf[39][7]_i_4\ : label is "soft_lutpair2342";
  attribute SOFT_HLUTNM of \retbuf[39][7]_i_5\ : label is "soft_lutpair2277";
  attribute SOFT_HLUTNM of \retbuf[3][5]_i_2\ : label is "soft_lutpair2306";
  attribute SOFT_HLUTNM of \retbuf[3][7]_i_11\ : label is "soft_lutpair2281";
  attribute SOFT_HLUTNM of \retbuf[3][7]_i_13\ : label is "soft_lutpair2267";
  attribute SOFT_HLUTNM of \retbuf[3][7]_i_17\ : label is "soft_lutpair2376";
  attribute SOFT_HLUTNM of \retbuf[3][7]_i_18\ : label is "soft_lutpair2281";
  attribute SOFT_HLUTNM of \retbuf[3][7]_i_19\ : label is "soft_lutpair2293";
  attribute SOFT_HLUTNM of \retbuf[3][7]_i_4\ : label is "soft_lutpair2313";
  attribute SOFT_HLUTNM of \retbuf[4][4]_i_7\ : label is "soft_lutpair2296";
  attribute SOFT_HLUTNM of \retbuf[4][5]_i_7\ : label is "soft_lutpair2297";
  attribute SOFT_HLUTNM of \retbuf[4][6]_i_5\ : label is "soft_lutpair2376";
  attribute SOFT_HLUTNM of \retbuf[4][7]_i_13\ : label is "soft_lutpair2337";
  attribute SOFT_HLUTNM of \retbuf[4][7]_i_16\ : label is "soft_lutpair2297";
  attribute SOFT_HLUTNM of \retbuf[4][7]_i_17\ : label is "soft_lutpair2339";
  attribute SOFT_HLUTNM of \retbuf[4][7]_i_18\ : label is "soft_lutpair2337";
  attribute SOFT_HLUTNM of \retbuf[4][7]_i_4\ : label is "soft_lutpair2313";
  attribute SOFT_HLUTNM of \retbuf[5][3]_i_2\ : label is "soft_lutpair2303";
  attribute SOFT_HLUTNM of \retbuf[5][4]_i_2\ : label is "soft_lutpair2303";
  attribute SOFT_HLUTNM of \retbuf[5][6]_i_2\ : label is "soft_lutpair2302";
  attribute SOFT_HLUTNM of \retbuf[5][7]_i_10\ : label is "soft_lutpair2294";
  attribute SOFT_HLUTNM of \retbuf[5][7]_i_13\ : label is "soft_lutpair2346";
  attribute SOFT_HLUTNM of \retbuf[5][7]_i_15\ : label is "soft_lutpair2266";
  attribute SOFT_HLUTNM of \retbuf[5][7]_i_16\ : label is "soft_lutpair2290";
  attribute SOFT_HLUTNM of \retbuf[5][7]_i_17\ : label is "soft_lutpair2266";
  attribute SOFT_HLUTNM of \retbuf[5][7]_i_18\ : label is "soft_lutpair2267";
  attribute SOFT_HLUTNM of \retbuf[5][7]_i_5\ : label is "soft_lutpair2302";
  attribute SOFT_HLUTNM of \retbuf[5][7]_i_8\ : label is "soft_lutpair2292";
  attribute SOFT_HLUTNM of \retbuf[7][3]_i_2\ : label is "soft_lutpair2332";
  attribute SOFT_HLUTNM of \retbuf[7][7]_i_4\ : label is "soft_lutpair2283";
  attribute SOFT_HLUTNM of \retbuf[7][7]_i_6\ : label is "soft_lutpair2340";
  attribute SOFT_HLUTNM of \retbuf[8][7]_i_11\ : label is "soft_lutpair2375";
  attribute SOFT_HLUTNM of \retbuf[8][7]_i_23\ : label is "soft_lutpair2305";
  attribute SOFT_HLUTNM of \retbuf[8][7]_i_24\ : label is "soft_lutpair2305";
  attribute SOFT_HLUTNM of \retbuf[8][7]_i_25\ : label is "soft_lutpair2339";
  attribute SOFT_HLUTNM of \retbuf[8][7]_i_6\ : label is "soft_lutpair2325";
  attribute SOFT_HLUTNM of \rng_i_1__1\ : label is "soft_lutpair2274";
  attribute SOFT_HLUTNM of \rxlen[0]_i_5\ : label is "soft_lutpair2370";
  attribute SOFT_HLUTNM of \seq[0][5]_i_1\ : label is "soft_lutpair2421";
  attribute SOFT_HLUTNM of \seq[1][13]_i_1\ : label is "soft_lutpair2421";
  attribute SOFT_HLUTNM of \staTixVTrigger[7]_i_1__0\ : label is "soft_lutpair2316";
  attribute SOFT_HLUTNM of \staTixVTrigger[7]_i_1__1\ : label is "soft_lutpair2320";
  attribute SOFT_HLUTNM of \staTixVTrigger[7]_i_3__0\ : label is "soft_lutpair2362";
  attribute SOFT_HLUTNM of \staTixVTrigger[7]_i_3__1\ : label is "soft_lutpair2288";
  attribute SOFT_HLUTNM of \staTixVTrigger[7]_i_4__0\ : label is "soft_lutpair2363";
  attribute SOFT_HLUTNM of \staTixVTrigger[7]_i_4__1\ : label is "soft_lutpair2290";
  attribute SOFT_HLUTNM of \stateCorecfg[2]_i_4\ : label is "soft_lutpair2327";
  attribute SOFT_HLUTNM of \stateCorecfg[2]_i_6\ : label is "soft_lutpair2291";
  attribute SOFT_HLUTNM of \stateCorecfg[2]_i_8\ : label is "soft_lutpair2336";
  attribute SOFT_HLUTNM of \stateCorecfg[2]_i_9\ : label is "soft_lutpair2294";
  attribute SOFT_HLUTNM of \stateOp[0]_i_2__1\ : label is "soft_lutpair2271";
  attribute SOFT_HLUTNM of \stateOp[0]_i_8\ : label is "soft_lutpair2278";
  attribute SOFT_HLUTNM of \stateOp[1]_i_10__1\ : label is "soft_lutpair2350";
  attribute SOFT_HLUTNM of \stateOp[1]_i_2\ : label is "soft_lutpair2273";
  attribute SOFT_HLUTNM of \stateOp[1]_i_2__11\ : label is "soft_lutpair2322";
  attribute SOFT_HLUTNM of \stateOp[1]_i_2__12\ : label is "soft_lutpair2323";
  attribute SOFT_HLUTNM of \stateOp[1]_i_3__4\ : label is "soft_lutpair2381";
  attribute SOFT_HLUTNM of \stateOp[1]_i_6__1\ : label is "soft_lutpair2414";
  attribute SOFT_HLUTNM of \stateOp[1]_i_9__0\ : label is "soft_lutpair2413";
  attribute SOFT_HLUTNM of \stateOp[5]_i_12\ : label is "soft_lutpair2375";
  attribute SOFT_HLUTNM of \stateOp[5]_i_19\ : label is "soft_lutpair2378";
  attribute SOFT_HLUTNM of \stateOp[5]_i_20\ : label is "soft_lutpair2279";
  attribute SOFT_HLUTNM of \stateOp[5]_i_21\ : label is "soft_lutpair2371";
  attribute SOFT_HLUTNM of \stateOp[5]_i_22\ : label is "soft_lutpair2410";
  attribute SOFT_HLUTNM of \stateOp[5]_i_24\ : label is "soft_lutpair2372";
  attribute SOFT_HLUTNM of \stateOp[5]_i_31\ : label is "soft_lutpair2287";
  attribute SOFT_HLUTNM of \stateOp[5]_i_32\ : label is "soft_lutpair2286";
  attribute SOFT_HLUTNM of \stateOp[5]_i_33\ : label is "soft_lutpair2285";
  attribute SOFT_HLUTNM of \stateOp[5]_i_34\ : label is "soft_lutpair2374";
  attribute SOFT_HLUTNM of \stateOp[5]_i_39\ : label is "soft_lutpair2331";
  attribute SOFT_HLUTNM of \stateOp[5]_i_40\ : label is "soft_lutpair2332";
  attribute SOFT_HLUTNM of \stateOp[5]_i_41\ : label is "soft_lutpair2330";
  attribute SOFT_HLUTNM of \stateOp[5]_i_51\ : label is "soft_lutpair2373";
  attribute SOFT_HLUTNM of \stateOp[5]_i_55\ : label is "soft_lutpair2372";
  attribute SOFT_HLUTNM of \stateOp[5]_i_75\ : label is "soft_lutpair2411";
  attribute SOFT_HLUTNM of \stateOp[5]_i_76\ : label is "soft_lutpair2335";
  attribute SOFT_HLUTNM of \stateOp[5]_i_77\ : label is "soft_lutpair2296";
  attribute SOFT_HLUTNM of stateOp_i_1 : label is "soft_lutpair2353";
  attribute SOFT_HLUTNM of \stateOp_i_1__2\ : label is "soft_lutpair2276";
  attribute SOFT_HLUTNM of stateOp_i_2 : label is "soft_lutpair2349";
  attribute SOFT_HLUTNM of \stateOp_i_2__1\ : label is "soft_lutpair2319";
  attribute SOFT_HLUTNM of \stateOp_i_5__0\ : label is "soft_lutpair2288";
  attribute SOFT_HLUTNM of \stateOp_next[4]_i_11\ : label is "soft_lutpair2345";
  attribute SOFT_HLUTNM of \stateOp_next[5]_i_10\ : label is "soft_lutpair2345";
  attribute SOFT_HLUTNM of \stateOp_next[5]_i_12\ : label is "soft_lutpair2373";
  attribute SOFT_HLUTNM of \stateOp_next[5]_i_22\ : label is "soft_lutpair2328";
  attribute SOFT_HLUTNM of \stateOp_next[5]_i_3\ : label is "soft_lutpair2350";
  attribute SOFT_HLUTNM of \stateOp_next[5]_i_5\ : label is "soft_lutpair2351";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of \stateOp_reg[1]_i_11\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \stateOp_reg[1]_i_7\ : label is 11;
  attribute SOFT_HLUTNM of \stateSeqbufB[2]_i_10\ : label is "soft_lutpair2380";
  attribute SOFT_HLUTNM of \stateSeqbufB[2]_i_4\ : label is "soft_lutpair2360";
  attribute SOFT_HLUTNM of \stateSeqbufB[2]_i_5__2\ : label is "soft_lutpair2360";
  attribute SOFT_HLUTNM of \stateSeqbufB[2]_i_9\ : label is "soft_lutpair2404";
  attribute SOFT_HLUTNM of synthNotLive_i_2 : label is "soft_lutpair2348";
  attribute SOFT_HLUTNM of targetNotSteady_i_1 : label is "soft_lutpair2272";
  attribute SOFT_HLUTNM of targetNotSteady_i_2 : label is "soft_lutpair2362";
  attribute SOFT_HLUTNM of \tixVBuffer[7]_i_3\ : label is "soft_lutpair2404";
  attribute SOFT_HLUTNM of \tixVBuffer[7]_i_4\ : label is "soft_lutpair2334";
  attribute SOFT_HLUTNM of \tixVState[1]_i_1__0\ : label is "soft_lutpair2269";
  attribute SOFT_HLUTNM of \txAXIS_tdata[15]_i_10\ : label is "soft_lutpair2407";
  attribute SOFT_HLUTNM of \txAXIS_tdata[15]_i_4\ : label is "soft_lutpair2409";
  attribute SOFT_HLUTNM of \txAXIS_tdata[15]_i_8\ : label is "soft_lutpair2408";
  attribute SOFT_HLUTNM of \txAXIS_tdata[15]_i_9\ : label is "soft_lutpair2342";
  attribute SOFT_HLUTNM of \txAXIS_tdata[22]_i_4\ : label is "soft_lutpair2341";
  attribute SOFT_HLUTNM of \txAXIS_tdata[23]_i_3\ : label is "soft_lutpair2405";
  attribute SOFT_HLUTNM of \txAXIS_tdata[23]_i_4\ : label is "soft_lutpair2420";
  attribute SOFT_HLUTNM of \txAXIS_tdata[29]_i_3\ : label is "soft_lutpair2409";
  attribute SOFT_HLUTNM of \txAXIS_tdata[29]_i_7\ : label is "soft_lutpair2414";
  attribute SOFT_HLUTNM of \txAXIS_tdata[2]_i_10\ : label is "soft_lutpair2263";
  attribute SOFT_HLUTNM of \txAXIS_tdata[2]_i_5\ : label is "soft_lutpair2279";
  attribute SOFT_HLUTNM of \txAXIS_tdata[31]_i_7\ : label is "soft_lutpair2415";
  attribute SOFT_HLUTNM of \txAXIS_tdata[39]_i_3\ : label is "soft_lutpair2329";
  attribute SOFT_HLUTNM of \txAXIS_tdata[39]_i_4\ : label is "soft_lutpair2262";
  attribute SOFT_HLUTNM of \txAXIS_tdata[39]_i_9\ : label is "soft_lutpair2344";
  attribute SOFT_HLUTNM of \txAXIS_tdata[47]_i_10\ : label is "soft_lutpair2380";
  attribute SOFT_HLUTNM of \txAXIS_tdata[55]_i_13\ : label is "soft_lutpair2344";
  attribute SOFT_HLUTNM of \txAXIS_tdata[55]_i_3\ : label is "soft_lutpair2378";
  attribute SOFT_HLUTNM of \txAXIS_tdata[55]_i_4\ : label is "soft_lutpair2405";
  attribute SOFT_HLUTNM of \txAXIS_tdata[55]_i_5\ : label is "soft_lutpair2420";
  attribute SOFT_HLUTNM of \txAXIS_tdata[5]_i_10\ : label is "soft_lutpair2379";
  attribute SOFT_HLUTNM of \txAXIS_tdata[5]_i_11\ : label is "soft_lutpair2379";
  attribute SOFT_HLUTNM of \txAXIS_tdata[5]_i_3\ : label is "soft_lutpair2407";
  attribute SOFT_HLUTNM of \txAXIS_tdata[63]_i_3\ : label is "soft_lutpair2329";
  attribute SOFT_HLUTNM of \txAXIS_tdata[6]_i_10\ : label is "soft_lutpair2415";
  attribute SOFT_HLUTNM of \txAXIS_tdata[6]_i_7__0\ : label is "soft_lutpair2301";
  attribute SOFT_HLUTNM of \txAXIS_tdata[6]_i_9\ : label is "soft_lutpair2341";
  attribute SOFT_HLUTNM of \txAXIS_tdata[7]_i_10__0\ : label is "soft_lutpair2301";
  attribute SOFT_HLUTNM of \txAXIS_tdata[7]_i_15\ : label is "soft_lutpair2278";
  attribute SOFT_HLUTNM of \txAXIS_tdata[7]_i_3\ : label is "soft_lutpair2370";
  attribute SOFT_HLUTNM of \txAXIS_tdata[7]_i_4\ : label is "soft_lutpair2371";
  attribute SOFT_HLUTNM of \txlen[0]_i_2\ : label is "soft_lutpair2280";
  attribute SOFT_HLUTNM of \txlen[28]_i_4\ : label is "soft_lutpair2368";
  attribute SOFT_HLUTNM of \wordcntCrcLast[0]_i_2\ : label is "soft_lutpair2299";
  attribute SOFT_HLUTNM of \wordcntCrcLast[24]_i_3\ : label is "soft_lutpair2263";
  attribute SOFT_HLUTNM of \wordcntCrcLast[24]_i_6\ : label is "soft_lutpair2325";
  attribute ADDER_THRESHOLD of \wordcntCrcLast_reg[16]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \wordcntCrcLast_reg[24]_i_5\ : label is 35;
  attribute ADDER_THRESHOLD of \wordcntCrcLast_reg[8]_i_2\ : label is 35;
  attribute SOFT_HLUTNM of \wordcntLast[0]_i_2\ : label is "soft_lutpair2334";
  attribute SOFT_HLUTNM of \wordcntLast[0]_i_6\ : label is "soft_lutpair2408";
  attribute SOFT_HLUTNM of \wordcntLast[0]_i_7\ : label is "soft_lutpair2280";
  attribute SOFT_HLUTNM of \wordcntLast[28]_i_10\ : label is "soft_lutpair2328";
  attribute SOFT_HLUTNM of \wordcntLast[28]_i_4\ : label is "soft_lutpair2275";
  attribute SOFT_HLUTNM of \wordcntLast[2]_i_2\ : label is "soft_lutpair2299";
  attribute ADDER_THRESHOLD of \wordcntLast_reg[13]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \wordcntLast_reg[21]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \wordcntLast_reg[28]_i_7\ : label is 35;
  attribute ADDER_THRESHOLD of \wordcntLast_reg[5]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \wordcnt_reg[16]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \wordcnt_reg[24]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \wordcnt_reg[30]_i_10\ : label is 35;
  attribute ADDER_THRESHOLD of \wordcnt_reg[8]_i_2\ : label is 35;
begin
  D(23 downto 0) <= \^d\(23 downto 0);
  \ackInvConfig_sig0__6\ <= \^ackinvconfig_sig0__6\;
  ackInvSelect_sig_reg <= \^ackinvselect_sig_reg\;
  ackInvUnlock_sig0_in <= \^ackinvunlock_sig0_in\;
  ccwNotCw5_in <= \^ccwnotcw5_in\;
  commok <= \^commok\;
  hdrNotFix <= \^hdrnotfix\;
  \invbuf_reg[0][1]_0\ <= \^invbuf_reg[0][1]_0\;
  \invbuf_reg[0][7]_0\(7 downto 0) <= \^invbuf_reg[0][7]_0\(7 downto 0);
  \invbuf_reg[4][7]_0\(7 downto 0) <= \^invbuf_reg[4][7]_0\(7 downto 0);
  \invbuf_reg[5][7]_0\(7 downto 0) <= \^invbuf_reg[5][7]_0\(7 downto 0);
  reqInvAcquire <= \^reqinvacquire\;
  reqInvAssign <= \^reqinvassign\;
  reqInvConfig <= \^reqinvconfig\;
  reqInvConfigSynth <= \^reqinvconfigsynth\;
  reqInvCornerConfig <= \^reqinvcornerconfig\;
  reqInvCputrackSet <= \^reqinvcputrackset\;
  reqInvDecimAcquire <= \^reqinvdecimacquire\;
  reqInvDecimConfig <= \^reqinvdecimconfig\;
  reqInvDecimSet <= \^reqinvdecimset\;
  reqInvDecimUnlock <= \^reqinvdecimunlock\;
  reqInvDirectorConfig <= \^reqinvdirectorconfig\;
  reqInvDirectorSet <= \^reqinvdirectorset\;
  reqInvGetCorereg <= \^reqinvgetcorereg\;
  reqInvGetReg <= \^reqinvgetreg\;
  reqInvHdrengSet <= \^reqinvhdrengset\;
  reqInvHshktrackClearMask <= \^reqinvhshktrackclearmask\;
  reqInvHshktrackSelect <= \^reqinvhshktrackselect\;
  reqInvHshktrackSet <= \^reqinvhshktrackset\;
  reqInvHshktrackSetMask <= \^reqinvhshktracksetmask\;
  reqInvMemtrackClearMask <= \^reqinvmemtrackclearmask\;
  reqInvMemtrackSelect <= \^reqinvmemtrackselect\;
  reqInvMemtrackSet <= \^reqinvmemtrackset\;
  reqInvMemtrackSetMask <= \^reqinvmemtracksetmask\;
  reqInvModReg <= \^reqinvmodreg\;
  reqInvRotaryConfig <= \^reqinvrotaryconfig\;
  reqInvRotaryMoveto <= \^reqinvrotarymoveto\;
  reqInvRotaryZero <= \^reqinvrotaryzero\;
  reqInvSelect <= \^reqinvselect\;
  reqInvSetCorereg <= \^reqinvsetcorereg\;
  reqInvSetReg <= \^reqinvsetreg\;
  reqInvStepmuxSet <= \^reqinvstepmuxset\;
  reqInvTkclksrcSetTkst <= \^reqinvtkclksrcsettkst\;
  reqInvTraceAcquire <= \^reqinvtraceacquire\;
  reqInvTraceConfig <= \^reqinvtraceconfig\;
  reqInvVidtrackSelect <= \^reqinvvidtrackselect\;
  reqInvVidtrackSet <= \^reqinvvidtrackset\;
  \stateOp_reg[0]_5\(0) <= \^stateop_reg[0]_5\(0);
  \stateOp_reg[1]_5\ <= \^stateop_reg[1]_5\;
  \stateOp_reg[5]_0\(5 downto 0) <= \^stateop_reg[5]_0\(5 downto 0);
  \step1__6\ <= \^step1__6\;
  \tixVCommand_reg[0]_0\ <= \^tixvcommand_reg[0]_0\;
  tixVState1 <= \^tixvstate1\;
\FSM_onehot_stateCoobufB[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB[0]_i_3_n_0\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => \tixVBuffer_reg_n_0_[3]\,
      I3 => \pollbuf[0][7]_i_7_n_0\,
      I4 => \tixVBuffer_reg_n_0_[1]\,
      I5 => \tixVBuffer_reg_n_0_[0]\,
      O => reqCoobufCornerToHostif
    );
\FSM_onehot_stateCoobufB[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFA5FF95FFFFFFFF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(2),
      I3 => \^stateop_reg[5]_0\(5),
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(4),
      O => \FSM_onehot_stateCoobufB[0]_i_3_n_0\
    );
\FSM_onehot_stateCoobufB[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001000000000"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[3]\,
      I1 => \pollbuf[0][7]_i_7_n_0\,
      I2 => \tixVBuffer_reg_n_0_[1]\,
      I3 => \tixVBuffer_reg_n_0_[0]\,
      I4 => \tixVBuffer_reg_n_0_[2]\,
      I5 => \FSM_onehot_stateCoobufB[3]_i_4_n_0\,
      O => coobufCornerToHostifAXIS_tready
    );
\FSM_onehot_stateCoobufB[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000000"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(2),
      I3 => \^stateop_reg[5]_0\(5),
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(4),
      O => \FSM_onehot_stateCoobufB[3]_i_4_n_0\
    );
\FSM_onehot_stateCoobufB[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001000000000"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[3]\,
      I1 => \pollbuf[0][7]_i_7_n_0\,
      I2 => \tixVBuffer_reg_n_0_[1]\,
      I3 => \tixVBuffer_reg_n_0_[0]\,
      I4 => \tixVBuffer_reg_n_0_[2]\,
      I5 => \FSM_onehot_stateCoobufB[5]_i_4_n_0\,
      O => dneCoobufCornerToHostif
    );
\FSM_onehot_stateCoobufB[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000004000000000"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(2),
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(4),
      I3 => \^stateop_reg[5]_0\(1),
      I4 => \^stateop_reg[5]_0\(5),
      I5 => \^stateop_reg[5]_0\(3),
      O => \FSM_onehot_stateCoobufB[5]_i_4_n_0\
    );
\FSM_onehot_stateFlgbufB[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB[0]_i_3_n_0\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => \tixVBuffer_reg_n_0_[0]\,
      I3 => \tixVBuffer_reg_n_0_[1]\,
      I4 => \tixVBuffer_reg_n_0_[3]\,
      I5 => \pollbuf[0][7]_i_7_n_0\,
      O => reqFlgbufTraceToHostif
    );
\FSM_onehot_stateFlgbufB[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000004000"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[2]\,
      I1 => \FSM_onehot_stateCoobufB[3]_i_4_n_0\,
      I2 => \tixVBuffer_reg_n_0_[0]\,
      I3 => \tixVBuffer_reg_n_0_[1]\,
      I4 => \tixVBuffer_reg_n_0_[3]\,
      I5 => \pollbuf[0][7]_i_7_n_0\,
      O => flgbufTraceToHostifAXIS_tready
    );
\FSM_onehot_stateFlgbufB[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000004000"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[2]\,
      I1 => \FSM_onehot_stateCoobufB[5]_i_4_n_0\,
      I2 => \tixVBuffer_reg_n_0_[0]\,
      I3 => \tixVBuffer_reg_n_0_[1]\,
      I4 => \tixVBuffer_reg_n_0_[3]\,
      I5 => \pollbuf[0][7]_i_7_n_0\,
      O => dneFlgbufTraceToHostif
    );
\FSM_onehot_statePvwbufB[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \pollbuf[0][7]_i_7_n_0\,
      I1 => \tixVBuffer_reg_n_0_[3]\,
      I2 => \tixVBuffer_reg_n_0_[2]\,
      I3 => \tixVBuffer_reg_n_0_[1]\,
      I4 => \FSM_onehot_stateCoobufB[0]_i_3_n_0\,
      I5 => \tixVBuffer_reg_n_0_[0]\,
      O => reqPvwbufDecimToHostif
    );
\FSM_onehot_statePvwbufB[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000100000"
    )
        port map (
      I0 => \pollbuf[0][7]_i_7_n_0\,
      I1 => \tixVBuffer_reg_n_0_[3]\,
      I2 => \tixVBuffer_reg_n_0_[2]\,
      I3 => \tixVBuffer_reg_n_0_[1]\,
      I4 => \FSM_onehot_stateCoobufB[3]_i_4_n_0\,
      I5 => \tixVBuffer_reg_n_0_[0]\,
      O => pvwbufDecimToHostifAXIS_tready
    );
\FSM_onehot_statePvwbufB[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000100000"
    )
        port map (
      I0 => \pollbuf[0][7]_i_7_n_0\,
      I1 => \tixVBuffer_reg_n_0_[3]\,
      I2 => \tixVBuffer_reg_n_0_[2]\,
      I3 => \tixVBuffer_reg_n_0_[1]\,
      I4 => \FSM_onehot_stateCoobufB[5]_i_4_n_0\,
      I5 => \tixVBuffer_reg_n_0_[0]\,
      O => dnePvwbufDecimToHostif
    );
\FSM_sequential_stateOp[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \stateOp_i_3__1_n_0\,
      I3 => \stateOp_i_5__0_n_0\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \tixVController_reg_n_0_[1]\,
      O => reqInvLaserSet
    );
\TCaptMax[31]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \mask_reg[7]_0\,
      I1 => \^reqinvmemtrackset\,
      I2 => \^reqinvmemtrackclearmask\,
      I3 => \^reqinvmemtrackselect\,
      O => \stateOp_reg[2]_0\(0)
    );
\TCaptMax[31]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \mask_reg[5]_1\,
      I1 => \^reqinvhshktrackset\,
      I2 => \^reqinvhshktrackclearmask\,
      I3 => \^reqinvhshktrackselect\,
      O => \stateOp_reg[0]_3\(0)
    );
\TCaptMax[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000800000"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => targetNotSteady_i_3_n_0,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \staTixVTrigger[7]_i_3__1_n_0\,
      O => \^reqinvvidtrackset\
    );
\TCaptMax[31]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \staTixVTrigger[7]_i_3__1_n_0\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[1]\,
      I5 => \^tixvcommand_reg[0]_0\,
      O => \^reqinvmemtrackset\
    );
\TCaptMax[31]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \^tixvcommand_reg[0]_0\,
      I2 => \staTixVTrigger[7]_i_5_n_0\,
      O => \^reqinvhshktrackset\
    );
\TCaptMax[31]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000008000000000"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \staTixVTrigger[7]_i_3__1_n_0\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => targetNotSteady_i_3_n_0,
      O => \^reqinvcputrackset\
    );
\ackInvAcquire_sig_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5504"
    )
        port map (
      I0 => stateOp_reg_6,
      I1 => reqInvTraceUnlock,
      I2 => \^reqinvtraceconfig\,
      I3 => \^reqinvtraceacquire\,
      O => ackInvAcquire_sig3_out
    );
ackInvAssign_sig_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^reqinvassign\,
      I1 => rng_reg_8,
      O => ackInvAssign_sig
    );
ackInvConfigSynth_sig_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => stateOp_reg_5,
      I1 => \^reqinvconfig\,
      I2 => \^reqinvconfigsynth\,
      O => stateOp_reg_2(0)
    );
ackInvConfigSynth_sig_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \ixRetbufCrc[5]_i_4_n_0\,
      I2 => ackInvConfigSynth_sig_i_5_n_0,
      I3 => \tixVCommand_reg_n_0_[0]\,
      O => \^reqinvconfigsynth\
    );
ackInvConfigSynth_sig_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \ixRetbufCrc[5]_i_4_n_0\,
      I2 => ackInvConfigSynth_sig_i_5_n_0,
      I3 => \tixVCommand_reg_n_0_[0]\,
      O => \^reqinvconfig\
    );
ackInvConfigSynth_sig_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEFFFFFF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[2]\,
      I1 => \tixVController_reg_n_0_[4]\,
      I2 => \tixVController_reg_n_0_[3]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \tixVController_reg_n_0_[0]\,
      I5 => \retbuf[0][0]_i_3_n_0\,
      O => ackInvConfigSynth_sig_i_5_n_0
    );
\ackInvConfig_sig_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^reqinvtraceacquire\,
      I1 => stateOp_reg_6,
      I2 => \^reqinvtraceconfig\,
      O => ackInvConfig_sig
    );
ackInvConfig_sig_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \tixVCommand_reg_n_0_[0]\,
      I2 => \ixRetbufCrc[5]_i_4_n_0\,
      I3 => ackInvConfig_sig_i_7_n_0,
      O => \^reqinvdecimconfig\
    );
ackInvConfig_sig_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => ackInvConfig_sig_i_7_n_0,
      I2 => \stateOp_i_3__1_n_0\,
      O => \^reqinvdecimacquire\
    );
ackInvConfig_sig_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEFFFFF"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[3]\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \tixVController_reg_n_0_[4]\,
      O => ackInvConfig_sig_i_7_n_0
    );
ackInvGetCorereg_sig_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^reqinvgetcorereg\,
      I1 => ackInvCamifGetCorereg,
      I2 => \^reqinvsetcorereg\,
      I3 => ackInvCamifSetCorereg,
      O => stateCorecfg0
    );
ackInvGetCorereg_sig_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^reqinvgetcorereg\,
      O => \stateCorecfg[2]_i_4_0\
    );
ackInvGetReg_sig_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44F444F4FFFF44F4"
    )
        port map (
      I0 => \^reqinvmodreg\,
      I1 => ackInvCamifModReg,
      I2 => ackInvCamifGetReg,
      I3 => \^reqinvgetreg\,
      I4 => ackInvCamifSetReg,
      I5 => \^reqinvsetreg\,
      O => ackInvModReg_sig_reg
    );
ackInvMoveto_sig_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4044"
    )
        port map (
      I0 => \^reqinvrotaryconfig\,
      I1 => \^reqinvrotarymoveto\,
      I2 => ackInvSet_sig_reg(1),
      I3 => ackInvSet_sig_reg(0),
      O => \stateOp_reg[1]_3\(0)
    );
ackInvMoveto_sig_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF22F2"
    )
        port map (
      I0 => ackInvRotarySet,
      I1 => reqInvRotarySet,
      I2 => ackInvRotaryMoveto,
      I3 => \^reqinvrotarymoveto\,
      I4 => ackInvMoveto_sig_i_6_n_0,
      O => \^ackinvconfig_sig0__6\
    );
ackInvMoveto_sig_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFE0000FFFEFFFF"
    )
        port map (
      I0 => \^reqinvrotaryzero\,
      I1 => \^reqinvrotaryconfig\,
      I2 => \^reqinvrotarymoveto\,
      I3 => reqInvRotarySet,
      I4 => ackInvSet_sig_reg(1),
      I5 => ackInvSet_sig_reg(0),
      O => \^step1__6\
    );
ackInvMoveto_sig_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \stateOp_i_3__1_n_0\,
      I2 => targetNotSteady_i_4_n_0,
      O => \^reqinvrotaryconfig\
    );
ackInvMoveto_sig_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^reqinvrotaryzero\,
      I1 => ackInvRotaryZero,
      I2 => \^reqinvrotaryconfig\,
      I3 => ackInvRotaryConfig,
      O => ackInvMoveto_sig_i_6_n_0
    );
\ackInvSelect_sig_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B0BB"
    )
        port map (
      I0 => \^reqinvselect\,
      I1 => ackInvCputrackSelect,
      I2 => \^reqinvcputrackset\,
      I3 => ackInvCputrackSet,
      O => ackInvSelect_sig_reg_0
    );
\ackInvSetMask_sig_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \i2cRegaddr[15]_i_11_n_0\,
      I2 => \staTixVTrigger[7]_i_5_n_0\,
      O => \^reqinvhshktracksetmask\
    );
ackInvSetMask_sig_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^reqinvhshktrackset\,
      I1 => \^reqinvhshktrackselect\,
      O => \staTixVTrigger[7]_i_3__0_0\
    );
ackInvSet_sig_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FFFD"
    )
        port map (
      I0 => \stateOp_reg[0]_9\(0),
      I1 => \stateOp_reg[0]_9\(1),
      I2 => ackInvSet_sig_i_3_n_0,
      I3 => ackInvSet_sig_i_4_n_0,
      I4 => \^stateop_reg[1]_5\,
      O => \stateOp_reg[0]_6\(0)
    );
\ackInvSet_sig_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000D0000"
    )
        port map (
      I0 => \stateOp_reg[0]_7\(0),
      I1 => \stateOp_reg[0]_7\(1),
      I2 => \^reqinvdecimacquire\,
      I3 => \^reqinvdecimconfig\,
      I4 => \^reqinvdecimset\,
      O => ackInvSet_sig
    );
\ackInvSet_sig_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => rng_reg_8,
      I1 => \^reqinvhdrengset\,
      I2 => \^reqinvassign\,
      O => stateOp_reg_0
    );
\ackInvSet_sig_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10001010"
    )
        port map (
      I0 => \^reqinvrotaryconfig\,
      I1 => \^reqinvrotarymoveto\,
      I2 => reqInvRotarySet,
      I3 => ackInvSet_sig_reg(1),
      I4 => ackInvSet_sig_reg(0),
      O => ackInvSet_sig_0
    );
ackInvSet_sig_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03000100"
    )
        port map (
      I0 => \stateOp_reg[0]_9\(0),
      I1 => \^reqinvcornerconfig\,
      I2 => \^reqinvacquire\,
      I3 => reqInvSet,
      I4 => \stateOp_reg[0]_9\(1),
      O => ackInvSet_sig_1
    );
\ackInvSet_sig_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => targetNotSteady_i_4_n_0,
      I2 => \^tixvcommand_reg[0]_0\,
      O => reqInvRotarySet
    );
\ackInvSet_sig_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \^tixvcommand_reg[0]_0\,
      I2 => ackInvConfig_sig_i_7_n_0,
      O => \^reqinvdecimset\
    );
ackInvSet_sig_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => reqInvSet,
      I1 => ackInvCornerSet,
      I2 => \^reqinvcornerconfig\,
      I3 => ackInvCornerConfig,
      O => ackInvSet_sig_i_3_n_0
    );
ackInvSet_sig_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => reqInvUnlock,
      I1 => ackInvCornerUnlock,
      I2 => \^reqinvacquire\,
      I3 => ackInvCornerAcquire,
      O => ackInvSet_sig_i_4_n_0
    );
ackInvSet_sig_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \stateOp_reg[0]_9\(1),
      I1 => reqInvSet,
      I2 => reqInvUnlock,
      I3 => \^reqinvacquire\,
      I4 => \^reqinvcornerconfig\,
      O => \^stateop_reg[1]_5\
    );
ackInvSet_sig_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \wordcntLast[0]_i_5_n_0\,
      O => \^reqinvcornerconfig\
    );
ackInvSet_sig_i_7: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \stateOp_i_3__1_n_0\,
      I2 => ackInvSet_sig_i_9_n_0,
      O => \^reqinvacquire\
    );
ackInvSet_sig_i_8: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \^tixvcommand_reg[0]_0\,
      I2 => ackInvSet_sig_i_9_n_0,
      O => reqInvSet
    );
ackInvSet_sig_i_9: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[3]\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \tixVController_reg_n_0_[4]\,
      I5 => \retbuf[0][0]_i_3_n_0\,
      O => ackInvSet_sig_i_9_n_0
    );
ackInvUnlock_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000003010000"
    )
        port map (
      I0 => \stateOp_reg[0]_9\(0),
      I1 => \^reqinvcornerconfig\,
      I2 => \^reqinvacquire\,
      I3 => \stateOp_reg[0]_9\(1),
      I4 => reqInvUnlock,
      I5 => reqInvSet,
      O => \^ackinvunlock_sig0_in\
    );
\ackInvUnlock_sig_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000000000D0"
    )
        port map (
      I0 => \stateOp_reg[0]_7\(0),
      I1 => \stateOp_reg[0]_7\(1),
      I2 => \^reqinvdecimunlock\,
      I3 => \^reqinvdecimacquire\,
      I4 => \^reqinvdecimconfig\,
      I5 => \^reqinvdecimset\,
      O => \stateOp_reg[0]_0\
    );
ackInvUnlock_sig_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => ackInvConfig_sig_i_7_n_0,
      I2 => \i2cRegaddr[15]_i_11_n_0\,
      O => \^reqinvdecimunlock\
    );
\ackInvUnlock_sig_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => ackInvUnlock_sig_i_3_n_0,
      O => reqInvUnlock
    );
ackInvUnlock_sig_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFD"
    )
        port map (
      I0 => \i2cRegaddr[15]_i_11_n_0\,
      I1 => \retbuf[0][0]_i_3_n_0\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => ackInvUnlock_sig_i_4_n_0,
      I4 => \tixVController_reg_n_0_[3]\,
      I5 => \tixVController_reg_n_0_[0]\,
      O => ackInvUnlock_sig_i_3_n_0
    );
ackInvUnlock_sig_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \tixVController_reg_n_0_[1]\,
      I1 => \tixVController_reg_n_0_[2]\,
      O => ackInvUnlock_sig_i_4_n_0
    );
ackInvZero_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000000020002"
    )
        port map (
      I0 => \^reqinvrotaryzero\,
      I1 => \^reqinvrotaryconfig\,
      I2 => \^reqinvrotarymoveto\,
      I3 => reqInvRotarySet,
      I4 => ackInvSet_sig_reg(1),
      I5 => ackInvSet_sig_reg(0),
      O => \stateOp_reg[1]_2\
    );
ackInvZero_sig_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => targetNotSteady_i_4_n_0,
      I2 => \i2cRegaddr[15]_i_11_n_0\,
      O => \^reqinvrotaryzero\
    );
\capt[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => reqInvRotarySet,
      I1 => \mask_reg[3]_1\,
      O => \mask_reg[3]_0\(0)
    );
ccwNotCw1_carry_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => O(4),
      I1 => O(5),
      O => \invbuf_reg[0][5]_2\(2)
    );
ccwNotCw1_carry_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => O(2),
      I1 => O(3),
      O => \invbuf_reg[0][5]_2\(1)
    );
ccwNotCw1_carry_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => O(0),
      I1 => O(1),
      O => \invbuf_reg[0][5]_2\(0)
    );
\ccwNotCw2_carry__0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(5),
      I1 => \ccwNotCw2_carry__0\(13),
      O => S(5)
    );
\ccwNotCw2_carry__0_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(4),
      I1 => \ccwNotCw2_carry__0\(12),
      O => S(4)
    );
\ccwNotCw2_carry__0_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(3),
      I1 => \ccwNotCw2_carry__0\(11),
      O => S(3)
    );
\ccwNotCw2_carry__0_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(2),
      I1 => \ccwNotCw2_carry__0\(10),
      O => S(2)
    );
\ccwNotCw2_carry__0_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(1),
      I1 => \ccwNotCw2_carry__0\(9),
      O => S(1)
    );
\ccwNotCw2_carry__0_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(0),
      I1 => \ccwNotCw2_carry__0\(8),
      O => S(0)
    );
ccwNotCw2_carry_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^d\(23),
      I1 => \ccwNotCw2_carry__0\(7),
      O => \invbuf_reg[1][7]_0\(7)
    );
ccwNotCw2_carry_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^d\(22),
      I1 => \ccwNotCw2_carry__0\(6),
      O => \invbuf_reg[1][7]_0\(6)
    );
ccwNotCw2_carry_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^d\(21),
      I1 => \ccwNotCw2_carry__0\(5),
      O => \invbuf_reg[1][7]_0\(5)
    );
ccwNotCw2_carry_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^d\(20),
      I1 => \ccwNotCw2_carry__0\(4),
      O => \invbuf_reg[1][7]_0\(4)
    );
ccwNotCw2_carry_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^d\(19),
      I1 => \ccwNotCw2_carry__0\(3),
      O => \invbuf_reg[1][7]_0\(3)
    );
ccwNotCw2_carry_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^d\(18),
      I1 => \ccwNotCw2_carry__0\(2),
      O => \invbuf_reg[1][7]_0\(2)
    );
ccwNotCw2_carry_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^d\(17),
      I1 => \ccwNotCw2_carry__0\(1),
      O => \invbuf_reg[1][7]_0\(1)
    );
ccwNotCw2_carry_i_8: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^d\(16),
      I1 => \ccwNotCw2_carry__0\(0),
      O => \invbuf_reg[1][7]_0\(0)
    );
ccwNotCw_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAEAFA"
    )
        port map (
      I0 => ccwNotCw_i_2_n_0,
      I1 => ccwNotCw_reg(0),
      I2 => \^reqinvrotarymoveto\,
      I3 => ccwNotCw_reg_0(0),
      I4 => ccwNotCw_reg_1(0),
      O => ccwNotCw0
    );
ccwNotCw_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => ccwNotCw_i_3_n_0,
      I1 => \^reqinvrotarymoveto\,
      I2 => \^d\(16),
      I3 => \^d\(17),
      O => ccwNotCw_i_2_n_0
    );
ccwNotCw_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => \^d\(18),
      I1 => \^d\(19),
      I2 => \^d\(20),
      I3 => \^d\(21),
      I4 => \^d\(23),
      I5 => \^d\(22),
      O => ccwNotCw_i_3_n_0
    );
commok_sig_reg: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => myRxtx_n_554,
      PRE => \stateOp_reg[1]_6\(0),
      Q => \^commok\
    );
\corecfgAXIL_araddr[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^reqinvgetcorereg\,
      I1 => hdrNotFix_i_2_n_0,
      I2 => \^invbuf_reg[0][7]_0\(7),
      I3 => \^invbuf_reg[0][7]_0\(3),
      I4 => \^invbuf_reg[0][7]_0\(1),
      I5 => \^invbuf_reg[0][7]_0\(5),
      O => \invbuf_reg[0][7]_2\(6)
    );
\corecfgAXIL_araddr[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvgetcorereg\,
      I1 => \^d\(18),
      O => \invbuf_reg[0][7]_2\(0)
    );
\corecfgAXIL_araddr[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvgetcorereg\,
      I1 => \^d\(19),
      O => \invbuf_reg[0][7]_2\(1)
    );
\corecfgAXIL_araddr[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvgetcorereg\,
      I1 => \^d\(20),
      O => \invbuf_reg[0][7]_2\(2)
    );
\corecfgAXIL_araddr[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvgetcorereg\,
      I1 => \^d\(21),
      O => \invbuf_reg[0][7]_2\(3)
    );
\corecfgAXIL_araddr[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvgetcorereg\,
      I1 => \^d\(22),
      O => \invbuf_reg[0][7]_2\(4)
    );
\corecfgAXIL_araddr[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvgetcorereg\,
      I1 => \^d\(23),
      O => \invbuf_reg[0][7]_2\(5)
    );
\corecfgAXIL_awaddr[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => hdrNotFix_i_2_n_0,
      I2 => \^invbuf_reg[0][7]_0\(7),
      I3 => \^invbuf_reg[0][7]_0\(3),
      I4 => \^invbuf_reg[0][7]_0\(1),
      I5 => \^invbuf_reg[0][7]_0\(5),
      O => \invbuf_reg[0][7]_3\(6)
    );
\corecfgAXIL_awaddr[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(18),
      O => \invbuf_reg[0][7]_3\(0)
    );
\corecfgAXIL_awaddr[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(19),
      O => \invbuf_reg[0][7]_3\(1)
    );
\corecfgAXIL_awaddr[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(20),
      O => \invbuf_reg[0][7]_3\(2)
    );
\corecfgAXIL_awaddr[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(21),
      O => \invbuf_reg[0][7]_3\(3)
    );
\corecfgAXIL_awaddr[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(22),
      O => \invbuf_reg[0][7]_3\(4)
    );
\corecfgAXIL_awaddr[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(23),
      O => \invbuf_reg[0][7]_3\(5)
    );
\corecfgAXIL_wdata[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[5][7]_0\(0),
      O => \invbuf_reg[2][7]_0\(0)
    );
\corecfgAXIL_wdata[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[4][7]_0\(2),
      O => \invbuf_reg[2][7]_0\(10)
    );
\corecfgAXIL_wdata[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[4][7]_0\(3),
      O => \invbuf_reg[2][7]_0\(11)
    );
\corecfgAXIL_wdata[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[4][7]_0\(4),
      O => \invbuf_reg[2][7]_0\(12)
    );
\corecfgAXIL_wdata[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[4][7]_0\(5),
      O => \invbuf_reg[2][7]_0\(13)
    );
\corecfgAXIL_wdata[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[4][7]_0\(6),
      O => \invbuf_reg[2][7]_0\(14)
    );
\corecfgAXIL_wdata[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[4][7]_0\(7),
      O => \invbuf_reg[2][7]_0\(15)
    );
\corecfgAXIL_wdata[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(0),
      O => \invbuf_reg[2][7]_0\(16)
    );
\corecfgAXIL_wdata[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(1),
      O => \invbuf_reg[2][7]_0\(17)
    );
\corecfgAXIL_wdata[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(2),
      O => \invbuf_reg[2][7]_0\(18)
    );
\corecfgAXIL_wdata[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(3),
      O => \invbuf_reg[2][7]_0\(19)
    );
\corecfgAXIL_wdata[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[5][7]_0\(1),
      O => \invbuf_reg[2][7]_0\(1)
    );
\corecfgAXIL_wdata[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(4),
      O => \invbuf_reg[2][7]_0\(20)
    );
\corecfgAXIL_wdata[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(5),
      O => \invbuf_reg[2][7]_0\(21)
    );
\corecfgAXIL_wdata[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(6),
      O => \invbuf_reg[2][7]_0\(22)
    );
\corecfgAXIL_wdata[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(7),
      O => \invbuf_reg[2][7]_0\(23)
    );
\corecfgAXIL_wdata[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(8),
      O => \invbuf_reg[2][7]_0\(24)
    );
\corecfgAXIL_wdata[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(9),
      O => \invbuf_reg[2][7]_0\(25)
    );
\corecfgAXIL_wdata[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(10),
      O => \invbuf_reg[2][7]_0\(26)
    );
\corecfgAXIL_wdata[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(11),
      O => \invbuf_reg[2][7]_0\(27)
    );
\corecfgAXIL_wdata[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(12),
      O => \invbuf_reg[2][7]_0\(28)
    );
\corecfgAXIL_wdata[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(13),
      O => \invbuf_reg[2][7]_0\(29)
    );
\corecfgAXIL_wdata[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[5][7]_0\(2),
      O => \invbuf_reg[2][7]_0\(2)
    );
\corecfgAXIL_wdata[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(14),
      O => \invbuf_reg[2][7]_0\(30)
    );
\corecfgAXIL_wdata[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^d\(15),
      O => \invbuf_reg[2][7]_0\(31)
    );
\corecfgAXIL_wdata[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[5][7]_0\(3),
      O => \invbuf_reg[2][7]_0\(3)
    );
\corecfgAXIL_wdata[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[5][7]_0\(4),
      O => \invbuf_reg[2][7]_0\(4)
    );
\corecfgAXIL_wdata[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[5][7]_0\(5),
      O => \invbuf_reg[2][7]_0\(5)
    );
\corecfgAXIL_wdata[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[5][7]_0\(6),
      O => \invbuf_reg[2][7]_0\(6)
    );
\corecfgAXIL_wdata[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[5][7]_0\(7),
      O => \invbuf_reg[2][7]_0\(7)
    );
\corecfgAXIL_wdata[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[4][7]_0\(0),
      O => \invbuf_reg[2][7]_0\(8)
    );
\corecfgAXIL_wdata[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^reqinvsetcorereg\,
      I1 => \^invbuf_reg[4][7]_0\(1),
      O => \invbuf_reg[2][7]_0\(9)
    );
\crcAXIS_tkeep[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEFDFFEFEBF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(2),
      I1 => \^stateop_reg[5]_0\(5),
      I2 => \^stateop_reg[5]_0\(1),
      I3 => \^stateop_reg[5]_0\(3),
      I4 => \^stateop_reg[5]_0\(4),
      I5 => \^stateop_reg[5]_0\(0),
      O => \crcAXIS_tkeep[0]_i_2__0_n_0\
    );
\crcAXIS_tkeep[1]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntLast(12),
      I1 => \opbuf_reg[0]51_in\(18),
      I2 => \opbuf_reg[0]51_in\(20),
      I3 => wordcntLast(14),
      I4 => \opbuf_reg[0]51_in\(19),
      I5 => wordcntLast(13),
      O => \crcAXIS_tkeep[1]_i_10_n_0\
    );
\crcAXIS_tkeep[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntLast(10),
      I1 => \opbuf_reg[0]51_in\(16),
      I2 => \opbuf_reg[0]51_in\(17),
      I3 => wordcntLast(11),
      I4 => \opbuf_reg[0]51_in\(15),
      I5 => wordcntLast(9),
      O => \crcAXIS_tkeep[1]_i_11_n_0\
    );
\crcAXIS_tkeep[1]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntLast(7),
      I1 => \opbuf_reg[0]51_in\(13),
      I2 => \opbuf_reg[0]51_in\(14),
      I3 => wordcntLast(8),
      I4 => \opbuf_reg[0]51_in\(12),
      I5 => wordcntLast(6),
      O => \crcAXIS_tkeep[1]_i_12_n_0\
    );
\crcAXIS_tkeep[1]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntLast(3),
      I1 => \opbuf_reg[0]51_in\(9),
      I2 => \opbuf_reg[0]51_in\(11),
      I3 => wordcntLast(5),
      I4 => \opbuf_reg[0]51_in\(10),
      I5 => wordcntLast(4),
      O => \crcAXIS_tkeep[1]_i_13_n_0\
    );
\crcAXIS_tkeep[1]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(7),
      I1 => wordcntLast(1),
      I2 => \opbuf_reg[0]51_in\(8),
      I3 => wordcntLast(2),
      I4 => wordcntLast(0),
      I5 => \opbuf_reg[0]51_in\(6),
      O => \crcAXIS_tkeep[1]_i_14_n_0\
    );
\crcAXIS_tkeep[1]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[30]\,
      O => \crcAXIS_tkeep[1]_i_4_n_0\
    );
\crcAXIS_tkeep[1]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00009009"
    )
        port map (
      I0 => wordcntLast(27),
      I1 => \wordcnt_reg_n_0_[27]\,
      I2 => \wordcnt_reg_n_0_[28]\,
      I3 => wordcntLast(28),
      I4 => \wordcnt_reg_n_0_[29]\,
      O => \crcAXIS_tkeep[1]_i_5_n_0\
    );
\crcAXIS_tkeep[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntLast(25),
      I1 => \wordcnt_reg_n_0_[25]\,
      I2 => \wordcnt_reg_n_0_[26]\,
      I3 => wordcntLast(26),
      I4 => \opbuf_reg[0]51_in\(30),
      I5 => wordcntLast(24),
      O => \crcAXIS_tkeep[1]_i_6_n_0\
    );
\crcAXIS_tkeep[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntLast(21),
      I1 => \opbuf_reg[0]51_in\(27),
      I2 => \opbuf_reg[0]51_in\(29),
      I3 => wordcntLast(23),
      I4 => \opbuf_reg[0]51_in\(28),
      I5 => wordcntLast(22),
      O => \crcAXIS_tkeep[1]_i_7_n_0\
    );
\crcAXIS_tkeep[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntLast(18),
      I1 => \opbuf_reg[0]51_in\(24),
      I2 => \opbuf_reg[0]51_in\(26),
      I3 => wordcntLast(20),
      I4 => \opbuf_reg[0]51_in\(25),
      I5 => wordcntLast(19),
      O => \crcAXIS_tkeep[1]_i_8_n_0\
    );
\crcAXIS_tkeep[1]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntLast(15),
      I1 => \opbuf_reg[0]51_in\(21),
      I2 => \opbuf_reg[0]51_in\(23),
      I3 => wordcntLast(17),
      I4 => \opbuf_reg[0]51_in\(22),
      I5 => wordcntLast(16),
      O => \crcAXIS_tkeep[1]_i_9_n_0\
    );
\crcAXIS_tkeep[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0600020008000024"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(4),
      I2 => \^stateop_reg[5]_0\(5),
      I3 => \^stateop_reg[5]_0\(3),
      I4 => \^stateop_reg[5]_0\(2),
      I5 => \^stateop_reg[5]_0\(0),
      O => \crcAXIS_tkeep[3]_i_2_n_0\
    );
\crcAXIS_tkeep[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200080000010828"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(5),
      I3 => \^stateop_reg[5]_0\(3),
      I4 => \^stateop_reg[5]_0\(4),
      I5 => \^stateop_reg[5]_0\(2),
      O => \crcAXIS_tkeep[3]_i_3_n_0\
    );
\crcAXIS_tkeep[7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000640400008000"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \^stateop_reg[5]_0\(2),
      I3 => \^stateop_reg[5]_0\(3),
      I4 => \^stateop_reg[5]_0\(5),
      I5 => \^stateop_reg[5]_0\(0),
      O => \crcAXIS_tkeep[7]_i_10_n_0\
    );
\crcAXIS_tkeep[7]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[6]\,
      I1 => \tixVCommand_reg_n_0_[7]\,
      I2 => \tixVCommand_reg_n_0_[4]\,
      I3 => \tixVCommand_reg_n_0_[5]\,
      I4 => \tixVCommand_reg_n_0_[3]\,
      I5 => \tixVCommand_reg_n_0_[2]\,
      O => \crcAXIS_tkeep[7]_i_12_n_0\
    );
\crcAXIS_tkeep[7]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[1]\,
      I1 => \tixVCommand_reg_n_0_[0]\,
      O => \crcAXIS_tkeep[7]_i_13_n_0\
    );
\crcAXIS_tkeep[7]_i_15\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[30]\,
      O => \crcAXIS_tkeep[7]_i_15_n_0\
    );
\crcAXIS_tkeep[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[28]\,
      I1 => \wordcnt_reg_n_0_[27]\,
      I2 => \wordcnt_reg_n_0_[29]\,
      O => \crcAXIS_tkeep[7]_i_16_n_0\
    );
\crcAXIS_tkeep[7]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1001"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[26]\,
      I1 => \wordcnt_reg_n_0_[25]\,
      I2 => \wordcntCrcLast_reg_n_0_[24]\,
      I3 => \opbuf_reg[0]51_in\(30),
      O => \crcAXIS_tkeep[7]_i_17_n_0\
    );
\crcAXIS_tkeep[7]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[23]\,
      I1 => \opbuf_reg[0]51_in\(29),
      I2 => \opbuf_reg[0]51_in\(27),
      I3 => \wordcntCrcLast_reg_n_0_[21]\,
      I4 => \opbuf_reg[0]51_in\(28),
      I5 => \wordcntCrcLast_reg_n_0_[22]\,
      O => \crcAXIS_tkeep[7]_i_18_n_0\
    );
\crcAXIS_tkeep[7]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[20]\,
      I1 => \opbuf_reg[0]51_in\(26),
      I2 => \opbuf_reg[0]51_in\(24),
      I3 => \wordcntCrcLast_reg_n_0_[18]\,
      I4 => \opbuf_reg[0]51_in\(25),
      I5 => \wordcntCrcLast_reg_n_0_[19]\,
      O => \crcAXIS_tkeep[7]_i_19_n_0\
    );
\crcAXIS_tkeep[7]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[16]\,
      I1 => \opbuf_reg[0]51_in\(22),
      I2 => \opbuf_reg[0]51_in\(23),
      I3 => \wordcntCrcLast_reg_n_0_[17]\,
      I4 => \opbuf_reg[0]51_in\(21),
      I5 => \wordcntCrcLast_reg_n_0_[15]\,
      O => \crcAXIS_tkeep[7]_i_20_n_0\
    );
\crcAXIS_tkeep[7]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[13]\,
      I1 => \opbuf_reg[0]51_in\(19),
      I2 => \opbuf_reg[0]51_in\(20),
      I3 => \wordcntCrcLast_reg_n_0_[14]\,
      I4 => \opbuf_reg[0]51_in\(18),
      I5 => \wordcntCrcLast_reg_n_0_[12]\,
      O => \crcAXIS_tkeep[7]_i_21_n_0\
    );
\crcAXIS_tkeep[7]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[10]\,
      I1 => \opbuf_reg[0]51_in\(16),
      I2 => \opbuf_reg[0]51_in\(17),
      I3 => \wordcntCrcLast_reg_n_0_[11]\,
      I4 => \opbuf_reg[0]51_in\(15),
      I5 => \wordcntCrcLast_reg_n_0_[9]\,
      O => \crcAXIS_tkeep[7]_i_22_n_0\
    );
\crcAXIS_tkeep[7]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[7]\,
      I1 => \opbuf_reg[0]51_in\(13),
      I2 => \opbuf_reg[0]51_in\(14),
      I3 => \wordcntCrcLast_reg_n_0_[8]\,
      I4 => \opbuf_reg[0]51_in\(12),
      I5 => \wordcntCrcLast_reg_n_0_[6]\,
      O => \crcAXIS_tkeep[7]_i_23_n_0\
    );
\crcAXIS_tkeep[7]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[5]\,
      I1 => \opbuf_reg[0]51_in\(11),
      I2 => \opbuf_reg[0]51_in\(9),
      I3 => \wordcntCrcLast_reg_n_0_[3]\,
      I4 => \opbuf_reg[0]51_in\(10),
      I5 => \wordcntCrcLast_reg_n_0_[4]\,
      O => \crcAXIS_tkeep[7]_i_24_n_0\
    );
\crcAXIS_tkeep[7]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(7),
      I1 => \wordcntCrcLast_reg_n_0_[1]\,
      I2 => \opbuf_reg[0]51_in\(8),
      I3 => \wordcntCrcLast_reg_n_0_[2]\,
      I4 => \wordcntCrcLast_reg_n_0_[0]\,
      I5 => \opbuf_reg[0]51_in\(6),
      O => \crcAXIS_tkeep[7]_i_25_n_0\
    );
\crcAXIS_tkeep[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBFFBFFCFFEDFFFB"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(0),
      I3 => \^stateop_reg[5]_0\(4),
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(2),
      O => \crcAXIS_tkeep[7]_i_5_n_0\
    );
\crcAXIS_tkeep[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFB7F7FFFDFFEF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(4),
      I3 => \^stateop_reg[5]_0\(2),
      I4 => \^stateop_reg[5]_0\(5),
      I5 => \^stateop_reg[5]_0\(3),
      O => \crcAXIS_tkeep[7]_i_6_n_0\
    );
\crcAXIS_tkeep[7]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80AA"
    )
        port map (
      I0 => \crcAXIS_tkeep[0]_i_2__0_n_0\,
      I1 => \crcAXIS_tkeep_reg[1]_i_2_n_5\,
      I2 => \crcAXIS_tkeep[3]_i_2_n_0\,
      I3 => \crcAXIS_tkeep[3]_i_3_n_0\,
      O => \crcAXIS_tkeep[7]_i_8_n_0\
    );
\crcAXIS_tkeep[7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040010000010000"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(0),
      I1 => \^stateop_reg[5]_0\(2),
      I2 => \^stateop_reg[5]_0\(3),
      I3 => \^stateop_reg[5]_0\(5),
      I4 => \^stateop_reg[5]_0\(4),
      I5 => \^stateop_reg[5]_0\(1),
      O => \crcAXIS_tkeep[7]_i_9_n_0\
    );
\crcAXIS_tkeep_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_205,
      D => myRxtx_n_277,
      PRE => \stateOp_reg[1]_6\(0),
      Q => AXIS_tkeep(0)
    );
\crcAXIS_tkeep_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_205,
      D => myRxtx_n_276,
      PRE => \stateOp_reg[1]_6\(0),
      Q => AXIS_tkeep(1)
    );
\crcAXIS_tkeep_reg[1]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \crcAXIS_tkeep_reg[1]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_crcAXIS_tkeep_reg[1]_i_2_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \crcAXIS_tkeep_reg[1]_i_2_n_5\,
      CO(1) => \crcAXIS_tkeep_reg[1]_i_2_n_6\,
      CO(0) => \crcAXIS_tkeep_reg[1]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_crcAXIS_tkeep_reg[1]_i_2_O_UNCONNECTED\(7 downto 0),
      S(7 downto 3) => B"00000",
      S(2) => \crcAXIS_tkeep[1]_i_4_n_0\,
      S(1) => \crcAXIS_tkeep[1]_i_5_n_0\,
      S(0) => \crcAXIS_tkeep[1]_i_6_n_0\
    );
\crcAXIS_tkeep_reg[1]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \crcAXIS_tkeep_reg[1]_i_3_n_0\,
      CO(6) => \crcAXIS_tkeep_reg[1]_i_3_n_1\,
      CO(5) => \crcAXIS_tkeep_reg[1]_i_3_n_2\,
      CO(4) => \crcAXIS_tkeep_reg[1]_i_3_n_3\,
      CO(3) => \crcAXIS_tkeep_reg[1]_i_3_n_4\,
      CO(2) => \crcAXIS_tkeep_reg[1]_i_3_n_5\,
      CO(1) => \crcAXIS_tkeep_reg[1]_i_3_n_6\,
      CO(0) => \crcAXIS_tkeep_reg[1]_i_3_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_crcAXIS_tkeep_reg[1]_i_3_O_UNCONNECTED\(7 downto 0),
      S(7) => \crcAXIS_tkeep[1]_i_7_n_0\,
      S(6) => \crcAXIS_tkeep[1]_i_8_n_0\,
      S(5) => \crcAXIS_tkeep[1]_i_9_n_0\,
      S(4) => \crcAXIS_tkeep[1]_i_10_n_0\,
      S(3) => \crcAXIS_tkeep[1]_i_11_n_0\,
      S(2) => \crcAXIS_tkeep[1]_i_12_n_0\,
      S(1) => \crcAXIS_tkeep[1]_i_13_n_0\,
      S(0) => \crcAXIS_tkeep[1]_i_14_n_0\
    );
\crcAXIS_tkeep_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_205,
      D => myRxtx_n_275,
      PRE => \stateOp_reg[1]_6\(0),
      Q => AXIS_tkeep(2)
    );
\crcAXIS_tkeep_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_205,
      D => myRxtx_n_274,
      PRE => \stateOp_reg[1]_6\(0),
      Q => AXIS_tkeep(3)
    );
\crcAXIS_tkeep_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_205,
      D => myRxtx_n_273,
      PRE => \stateOp_reg[1]_6\(0),
      Q => AXIS_tkeep(4)
    );
\crcAXIS_tkeep_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_205,
      D => myRxtx_n_272,
      PRE => \stateOp_reg[1]_6\(0),
      Q => AXIS_tkeep(5)
    );
\crcAXIS_tkeep_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_205,
      D => myRxtx_n_271,
      PRE => \stateOp_reg[1]_6\(0),
      Q => AXIS_tkeep(6)
    );
\crcAXIS_tkeep_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_205,
      D => myRxtx_n_270,
      PRE => \stateOp_reg[1]_6\(0),
      Q => AXIS_tkeep(7)
    );
\crcAXIS_tkeep_reg[7]_i_11\: unisim.vcomponents.CARRY8
     port map (
      CI => \crcAXIS_tkeep_reg[7]_i_14_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_crcAXIS_tkeep_reg[7]_i_11_CO_UNCONNECTED\(7 downto 3),
      CO(2) => crcAXIS_tlast_sig0,
      CO(1) => \crcAXIS_tkeep_reg[7]_i_11_n_6\,
      CO(0) => \crcAXIS_tkeep_reg[7]_i_11_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 4) => \NLW_crcAXIS_tkeep_reg[7]_i_11_O_UNCONNECTED\(7 downto 4),
      O(3) => \crcAXIS_tkeep_reg[7]_i_11_n_12\,
      O(2 downto 0) => \NLW_crcAXIS_tkeep_reg[7]_i_11_O_UNCONNECTED\(2 downto 0),
      S(7 downto 3) => B"00001",
      S(2) => \crcAXIS_tkeep[7]_i_15_n_0\,
      S(1) => \crcAXIS_tkeep[7]_i_16_n_0\,
      S(0) => \crcAXIS_tkeep[7]_i_17_n_0\
    );
\crcAXIS_tkeep_reg[7]_i_14\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \crcAXIS_tkeep_reg[7]_i_14_n_0\,
      CO(6) => \crcAXIS_tkeep_reg[7]_i_14_n_1\,
      CO(5) => \crcAXIS_tkeep_reg[7]_i_14_n_2\,
      CO(4) => \crcAXIS_tkeep_reg[7]_i_14_n_3\,
      CO(3) => \crcAXIS_tkeep_reg[7]_i_14_n_4\,
      CO(2) => \crcAXIS_tkeep_reg[7]_i_14_n_5\,
      CO(1) => \crcAXIS_tkeep_reg[7]_i_14_n_6\,
      CO(0) => \crcAXIS_tkeep_reg[7]_i_14_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_crcAXIS_tkeep_reg[7]_i_14_O_UNCONNECTED\(7 downto 0),
      S(7) => \crcAXIS_tkeep[7]_i_18_n_0\,
      S(6) => \crcAXIS_tkeep[7]_i_19_n_0\,
      S(5) => \crcAXIS_tkeep[7]_i_20_n_0\,
      S(4) => \crcAXIS_tkeep[7]_i_21_n_0\,
      S(3) => \crcAXIS_tkeep[7]_i_22_n_0\,
      S(2) => \crcAXIS_tkeep[7]_i_23_n_0\,
      S(1) => \crcAXIS_tkeep[7]_i_24_n_0\,
      S(0) => \crcAXIS_tkeep[7]_i_25_n_0\
    );
crcAXIS_tlast_sig_i_13: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(0),
      I1 => \^stateop_reg[5]_0\(5),
      O => crcAXIS_tlast_sig_i_13_n_0
    );
crcAXIS_tlast_sig_i_14: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \stateOp_next[5]_i_3_n_0\,
      I1 => \stateOp_next_reg_n_0_[5]\,
      I2 => \stateOp_next_reg_n_0_[4]\,
      I3 => \stateOp_next_reg_n_0_[3]\,
      I4 => \stateOp_next_reg_n_0_[0]\,
      I5 => \stateOp_next_reg_n_0_[1]\,
      O => crcAXIS_tlast_sig_i_14_n_0
    );
crcAXIS_tlast_sig_i_15: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \^stateop_reg[5]_0\(4),
      I2 => \crcAXIS_tkeep_reg[7]_i_11_n_12\,
      O => crcAXIS_tlast_sig_i_15_n_0
    );
crcAXIS_tlast_sig_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F7FF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \wordcntLast[0]_i_5_n_0\,
      I3 => \txAXIS_tdata[7]_i_15_n_0\,
      I4 => crcAXIS_tlast_sig_i_4_n_0,
      I5 => crcAXIS_tlast_sig_i_5_n_0,
      O => crcAXIS_tlast_sig_i_2_n_0
    );
crcAXIS_tlast_sig_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000090100"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(2),
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \^stateop_reg[5]_0\(0),
      I3 => \^stateop_reg[5]_0\(3),
      I4 => \^stateop_reg[5]_0\(4),
      I5 => \crcAXIS_tkeep_reg[7]_i_11_n_12\,
      O => crcAXIS_tlast_sig_i_4_n_0
    );
crcAXIS_tlast_sig_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0AA8AA0AAAA2"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[1]_i_2_n_5\,
      I1 => \^stateop_reg[5]_0\(4),
      I2 => \^stateop_reg[5]_0\(2),
      I3 => \^stateop_reg[5]_0\(3),
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(0),
      O => crcAXIS_tlast_sig_i_5_n_0
    );
crcAXIS_tlast_sig_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFD9"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \^stateop_reg[5]_0\(4),
      I2 => \crcAXIS_tkeep_reg[7]_i_11_n_12\,
      I3 => \^stateop_reg[5]_0\(2),
      I4 => \^stateop_reg[5]_0\(0),
      I5 => \^stateop_reg[5]_0\(1),
      O => crcAXIS_tlast_sig_i_7_n_0
    );
crcAXIS_tlast_sig_i_9: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(0),
      O => crcAXIS_tlast_sig_i_9_n_0
    );
crcAXIS_tlast_sig_reg: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => myRxtx_n_553,
      PRE => \stateOp_reg[1]_6\(0),
      Q => crcAXIS_tlast_sig_reg_n_0
    );
hdrNotFix_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(5),
      I1 => \^invbuf_reg[0][7]_0\(1),
      I2 => \^invbuf_reg[0][7]_0\(3),
      I3 => \^invbuf_reg[0][7]_0\(7),
      I4 => hdrNotFix_i_2_n_0,
      O => \^hdrnotfix\
    );
hdrNotFix_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(2),
      I1 => \^invbuf_reg[0][7]_0\(6),
      I2 => \^invbuf_reg[0][7]_0\(0),
      I3 => \^invbuf_reg[0][7]_0\(4),
      O => hdrNotFix_i_2_n_0
    );
i2cReadNotWrite_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvmodreg\,
      I2 => \^reqinvgetreg\,
      O => \i2cRegaddr[15]_i_6_0\
    );
i2cReadNotWrite_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0101010101010001"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^reqinvmodreg\,
      I3 => i2cReadNotWrite_reg(2),
      I4 => i2cReadNotWrite_reg(0),
      I5 => i2cReadNotWrite_reg(1),
      O => \stateLive_reg[2]\
    );
\i2cRegaddr[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F1F0E0"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^d\(16),
      I3 => \^reqinvmodreg\,
      I4 => \i2cRegaddr_reg[13]\(0),
      O => \invbuf_reg[1][0]_0\
    );
\i2cRegaddr[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FFFFFE000000"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^reqinvmodreg\,
      I3 => \^invbuf_reg[0][7]_0\(2),
      I4 => \i2cRegaddr_reg[15]\,
      I5 => DO(2),
      O => \invbuf_reg[0][7]_1\(6)
    );
\i2cRegaddr[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FFFFFE000000"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^reqinvmodreg\,
      I3 => \^invbuf_reg[0][7]_0\(3),
      I4 => \i2cRegaddr_reg[15]\,
      I5 => DO(3),
      O => \invbuf_reg[0][7]_1\(7)
    );
\i2cRegaddr[12]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F1F0E0"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^invbuf_reg[0][7]_0\(4),
      I3 => \^reqinvmodreg\,
      I4 => \i2cRegaddr_reg[13]\(1),
      O => \invbuf_reg[0][4]_0\
    );
\i2cRegaddr[13]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F1F0E0"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^invbuf_reg[0][7]_0\(5),
      I3 => \^reqinvmodreg\,
      I4 => \i2cRegaddr_reg[13]\(1),
      O => \invbuf_reg[0][5]_0\
    );
\i2cRegaddr[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FFFFFE000000"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^reqinvmodreg\,
      I3 => \^invbuf_reg[0][7]_0\(6),
      I4 => \i2cRegaddr_reg[15]\,
      I5 => DO(5),
      O => \invbuf_reg[0][7]_1\(8)
    );
\i2cRegaddr[15]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00040000"
    )
        port map (
      I0 => \stateOp_i_5__1_n_0\,
      I1 => \tixVCommand_reg_n_0_[0]\,
      I2 => \tixVCommand_reg_n_0_[4]\,
      I3 => \tixVCommand_reg_n_0_[5]\,
      I4 => \tixVCommand_reg_n_0_[1]\,
      O => \^tixvcommand_reg[0]_0\
    );
\i2cRegaddr[15]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[1]\,
      I1 => \tixVCommand_reg_n_0_[4]\,
      I2 => \tixVCommand_reg_n_0_[5]\,
      I3 => \tixVCommand_reg_n_0_[0]\,
      I4 => \stateCorecfg[2]_i_8_n_0\,
      O => \i2cRegaddr[15]_i_11_n_0\
    );
\i2cRegaddr[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FFFFFE000000"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^reqinvmodreg\,
      I3 => \^invbuf_reg[0][7]_0\(7),
      I4 => \i2cRegaddr_reg[15]\,
      I5 => DO(6),
      O => \invbuf_reg[0][7]_1\(9)
    );
\i2cRegaddr[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \resid[2]_i_5_n_0\,
      O => \^reqinvsetreg\
    );
\i2cRegaddr[15]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => ackInvConfigSynth_sig_i_5_n_0,
      I2 => \^tixvcommand_reg[0]_0\,
      O => \^reqinvgetreg\
    );
\i2cRegaddr[15]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => ackInvConfigSynth_sig_i_5_n_0,
      I2 => \i2cRegaddr[15]_i_11_n_0\,
      O => \^reqinvmodreg\
    );
\i2cRegaddr[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FFFFFE000000"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^reqinvmodreg\,
      I3 => \^d\(17),
      I4 => \i2cRegaddr_reg[15]\,
      I5 => DO(1),
      O => \invbuf_reg[0][7]_1\(0)
    );
\i2cRegaddr[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FFFFFE000000"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^reqinvmodreg\,
      I3 => \^d\(18),
      I4 => \i2cRegaddr_reg[15]\,
      I5 => DO(2),
      O => \invbuf_reg[0][7]_1\(1)
    );
\i2cRegaddr[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F1F0E0"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^d\(19),
      I3 => \^reqinvmodreg\,
      I4 => \i2cRegaddr_reg[13]\(1),
      O => \invbuf_reg[1][3]_0\
    );
\i2cRegaddr[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F1F0E0"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^d\(20),
      I3 => \^reqinvmodreg\,
      I4 => \i2cRegaddr_reg[13]\(1),
      O => \invbuf_reg[1][4]_0\
    );
\i2cRegaddr[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FFFFFE000000"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^reqinvmodreg\,
      I3 => \^d\(21),
      I4 => \i2cRegaddr_reg[15]\,
      I5 => DO(4),
      O => \invbuf_reg[0][7]_1\(2)
    );
\i2cRegaddr[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F1F0E0"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^d\(22),
      I3 => \^reqinvmodreg\,
      I4 => \i2cRegaddr_reg[13]\(1),
      O => \invbuf_reg[1][6]_0\
    );
\i2cRegaddr[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FFFFFE000000"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^reqinvmodreg\,
      I3 => \^d\(23),
      I4 => \i2cRegaddr_reg[15]\,
      I5 => DO(6),
      O => \invbuf_reg[0][7]_1\(3)
    );
\i2cRegaddr[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FFFFFE000000"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^reqinvmodreg\,
      I3 => \^invbuf_reg[0][7]_0\(0),
      I4 => \i2cRegaddr_reg[15]\,
      I5 => DO(0),
      O => \invbuf_reg[0][7]_1\(4)
    );
\i2cRegaddr[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FFFFFE000000"
    )
        port map (
      I0 => \^reqinvsetreg\,
      I1 => \^reqinvgetreg\,
      I2 => \^reqinvmodreg\,
      I3 => \^invbuf_reg[0][7]_0\(1),
      I4 => \i2cRegaddr_reg[15]\,
      I5 => DO(1),
      O => \invbuf_reg[0][7]_1\(5)
    );
\i[3]__0_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBBB8BBBB"
    )
        port map (
      I0 => reqResetFromHostif,
      I1 => stateMclk,
      I2 => Q(0),
      I3 => Q(1),
      I4 => Q(3),
      I5 => Q(2),
      O => reqReset_sig_reg_1(0)
    );
\i[4]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDDDDDDDDDDD5"
    )
        port map (
      I0 => ackInvSet_sig_reg(0),
      I1 => ackInvSet_sig_reg(1),
      I2 => reqInvRotarySet,
      I3 => \^reqinvrotarymoveto\,
      I4 => \^reqinvrotaryconfig\,
      I5 => \^reqinvrotaryzero\,
      O => \stateOp_reg[0]_2\
    );
\i__carry_i_10__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => O(1),
      I1 => O(0),
      O => \invbuf_reg[0][5]_3\(0)
    );
\i__carry_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => O(5),
      O => \invbuf_reg[0][5]_4\(0)
    );
\i__carry_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => O(5),
      I1 => O(4),
      O => DI(2)
    );
\i__carry_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => O(2),
      I1 => O(3),
      O => DI(1)
    );
\i__carry_i_4__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => CO(0),
      O => \invbuf_reg[0][5]_1\(3)
    );
\i__carry_i_4__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => O(0),
      I1 => O(1),
      O => DI(0)
    );
\i__carry_i_5__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => O(5),
      I1 => O(4),
      O => \invbuf_reg[0][5]_1\(2)
    );
\i__carry_i_6__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => O(3),
      I1 => O(2),
      O => \invbuf_reg[0][5]_1\(1)
    );
\i__carry_i_7__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => O(1),
      I1 => O(0),
      O => \invbuf_reg[0][5]_1\(0)
    );
\i__carry_i_8__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => O(4),
      I1 => O(5),
      O => \invbuf_reg[0][5]_3\(2)
    );
\i__carry_i_9__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => O(3),
      I1 => O(2),
      O => \invbuf_reg[0][5]_3\(1)
    );
\i__i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \i__i_3_n_0\,
      I1 => \tixVCommand_reg_n_0_[0]\,
      I2 => \stateOp_i_2__0_n_0\,
      O => \^reqinvdirectorconfig\
    );
\i__i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \tixVCommand_reg_n_0_[0]\,
      I2 => \i__i_3_n_0\,
      O => \^reqinvdirectorset\
    );
\i__i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000100000000000"
    )
        port map (
      I0 => \ixRetbufCrc[4]_i_5_n_0\,
      I1 => \stateOp_i_5__1_n_0\,
      I2 => \i__i_4_n_0\,
      I3 => \i__i_5_n_0\,
      I4 => \retbuf[0][0]_i_3_n_0\,
      I5 => \tixVController_reg_n_0_[0]\,
      O => \i__i_3_n_0\
    );
\i__i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tixVController_reg_n_0_[2]\,
      I1 => \tixVController_reg_n_0_[3]\,
      O => \i__i_4_n_0\
    );
\i__i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tixVController_reg_n_0_[1]\,
      I1 => \tixVController_reg_n_0_[4]\,
      O => \i__i_5_n_0\
    );
\invbuf[0][7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7FF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \^stateop_reg[5]_0\(5),
      I3 => \^stateop_reg[5]_0\(4),
      O => \invbuf[0][7]_i_2_n_0\
    );
\invbuf[9][7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFEFFFFAEFEA"
    )
        port map (
      I0 => \invbuf[9][7]_i_22_n_0\,
      I1 => \opbuf_reg[0]3\(27),
      I2 => \wordcnt_reg_n_0_[25]\,
      I3 => \opbuf_reg[0]51_in\(30),
      I4 => \opbuf_reg[0]3\(26),
      I5 => \opbuf_reg[0]51_in\(29),
      O => \invbuf[9][7]_i_10_n_0\
    );
\invbuf[9][7]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[25]\,
      I1 => \opbuf_reg[0][7]_i_16_n_7\,
      O => \invbuf[9][7]_i_11_n_0\
    );
\invbuf[9][7]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFDDFAD8"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[25]\,
      I1 => \opbuf_reg[0]3\(13),
      I2 => \opbuf_reg[0]51_in\(16),
      I3 => \opbuf_reg[0]3\(12),
      I4 => \opbuf_reg[0]51_in\(15),
      I5 => \invbuf[9][7]_i_30_n_0\,
      O => \invbuf[9][7]_i_13_n_0\
    );
\invbuf[9][7]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFDDFAD8"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[25]\,
      I1 => \opbuf_reg[0]3\(17),
      I2 => \opbuf_reg[0]51_in\(20),
      I3 => \opbuf_reg[0]3\(16),
      I4 => \opbuf_reg[0]51_in\(19),
      I5 => \invbuf[9][7]_i_31_n_0\,
      O => \invbuf[9][7]_i_14_n_0\
    );
\invbuf[9][7]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(9),
      I1 => \opbuf_reg[0]3\(6),
      I2 => \opbuf_reg[0]51_in\(10),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(7),
      O => \invbuf[9][7]_i_15_n_0\
    );
\invbuf[9][7]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(7),
      I1 => \opbuf_reg[0]3\(4),
      I2 => \opbuf_reg[0]51_in\(8),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(5),
      O => \invbuf[9][7]_i_16_n_0\
    );
\invbuf[9][7]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFDDFAD8"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[25]\,
      I1 => \opbuf_reg[0]3\(8),
      I2 => \opbuf_reg[0]51_in\(11),
      I3 => \opbuf_reg[0]3\(9),
      I4 => \opbuf_reg[0]51_in\(12),
      I5 => \invbuf[9][7]_i_20_n_0\,
      O => \invbuf[9][7]_i_17_n_0\
    );
\invbuf[9][7]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFF4"
    )
        port map (
      I0 => \opbuf_reg[0][7]_i_16_n_7\,
      I1 => \wordcnt_reg_n_0_[25]\,
      I2 => \invbuf[9][7]_i_10_n_0\,
      I3 => \invbuf[9][7]_i_32_n_0\,
      I4 => \invbuf[9][7]_i_21_n_0\,
      O => \invbuf[9][7]_i_18_n_0\
    );
\invbuf[9][7]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(12),
      I1 => \opbuf_reg[0]3\(9),
      I2 => \opbuf_reg[0]51_in\(11),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(8),
      O => \invbuf[9][7]_i_19_n_0\
    );
\invbuf[9][7]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(13),
      I1 => \opbuf_reg[0]3\(10),
      I2 => \opbuf_reg[0]51_in\(14),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(11),
      O => \invbuf[9][7]_i_20_n_0\
    );
\invbuf[9][7]_i_21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(25),
      I1 => \opbuf_reg[0]3\(22),
      I2 => \opbuf_reg[0]51_in\(26),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(23),
      O => \invbuf[9][7]_i_21_n_0\
    );
\invbuf[9][7]_i_22\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(27),
      I1 => \opbuf_reg[0]3\(24),
      I2 => \opbuf_reg[0]51_in\(28),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(25),
      O => \invbuf[9][7]_i_22_n_0\
    );
\invbuf[9][7]_i_23\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(6),
      O => txlast1(0)
    );
\invbuf[9][7]_i_24\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(12),
      O => \invbuf[9][7]_i_24_n_0\
    );
\invbuf[9][7]_i_25\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(11),
      O => \invbuf[9][7]_i_25_n_0\
    );
\invbuf[9][7]_i_26\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(10),
      O => \invbuf[9][7]_i_26_n_0\
    );
\invbuf[9][7]_i_27\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(9),
      O => \invbuf[9][7]_i_27_n_0\
    );
\invbuf[9][7]_i_28\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(8),
      O => \invbuf[9][7]_i_28_n_0\
    );
\invbuf[9][7]_i_29\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(7),
      O => \invbuf[9][7]_i_29_n_0\
    );
\invbuf[9][7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(0),
      O => \invbuf[9][7]_i_3_n_0\
    );
\invbuf[9][7]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(17),
      I1 => \opbuf_reg[0]3\(14),
      I2 => \opbuf_reg[0]51_in\(18),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(15),
      O => \invbuf[9][7]_i_30_n_0\
    );
\invbuf[9][7]_i_31\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(21),
      I1 => \opbuf_reg[0]3\(18),
      I2 => \opbuf_reg[0]51_in\(22),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(19),
      O => \invbuf[9][7]_i_31_n_0\
    );
\invbuf[9][7]_i_32\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(23),
      I1 => \opbuf_reg[0]3\(20),
      I2 => \opbuf_reg[0]51_in\(24),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(21),
      O => \invbuf[9][7]_i_32_n_0\
    );
\invbuf[9][7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \^stateop_reg[5]_0\(2),
      O => \invbuf[9][7]_i_5_n_0\
    );
\invbuf[9][7]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]5\(6),
      I1 => \wordcnt_reg_n_0_[25]\,
      I2 => \opbuf_reg[0]51_in\(6),
      O => \invbuf[9][7]_i_6_n_0\
    );
\invbuf[9][7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \invbuf[9][7]_i_13_n_0\,
      I1 => \invbuf[9][7]_i_14_n_0\,
      I2 => \invbuf[9][7]_i_15_n_0\,
      I3 => \invbuf[9][7]_i_16_n_0\,
      I4 => \invbuf[9][7]_i_17_n_0\,
      I5 => \invbuf[9][7]_i_18_n_0\,
      O => \invbuf[9][7]_i_7_n_0\
    );
\invbuf[9][7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \invbuf[9][7]_i_19_n_0\,
      I1 => \invbuf[9][7]_i_20_n_0\,
      I2 => \invbuf[9][7]_i_16_n_0\,
      I3 => \invbuf[9][7]_i_15_n_0\,
      I4 => \invbuf[9][7]_i_14_n_0\,
      I5 => \invbuf[9][7]_i_13_n_0\,
      O => \invbuf[9][7]_i_8_n_0\
    );
\invbuf[9][7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFDDFAD8"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[25]\,
      I1 => \opbuf_reg[0]3\(21),
      I2 => \opbuf_reg[0]51_in\(24),
      I3 => \opbuf_reg[0]3\(20),
      I4 => \opbuf_reg[0]51_in\(23),
      I5 => \invbuf[9][7]_i_21_n_0\,
      O => \invbuf[9][7]_i_9_n_0\
    );
\invbuf_reg[0][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_12,
      Q => \^invbuf_reg[0][7]_0\(0)
    );
\invbuf_reg[0][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_11,
      Q => \^invbuf_reg[0][7]_0\(1)
    );
\invbuf_reg[0][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_10,
      Q => \^invbuf_reg[0][7]_0\(2)
    );
\invbuf_reg[0][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_9,
      Q => \^invbuf_reg[0][7]_0\(3)
    );
\invbuf_reg[0][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_8,
      Q => \^invbuf_reg[0][7]_0\(4)
    );
\invbuf_reg[0][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_7,
      Q => \^invbuf_reg[0][7]_0\(5)
    );
\invbuf_reg[0][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_6,
      Q => \^invbuf_reg[0][7]_0\(6)
    );
\invbuf_reg[0][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_5,
      Q => \^invbuf_reg[0][7]_0\(7)
    );
\invbuf_reg[1][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(0),
      Q => \^d\(16)
    );
\invbuf_reg[1][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(1),
      Q => \^d\(17)
    );
\invbuf_reg[1][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(2),
      Q => \^d\(18)
    );
\invbuf_reg[1][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(3),
      Q => \^d\(19)
    );
\invbuf_reg[1][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(4),
      Q => \^d\(20)
    );
\invbuf_reg[1][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(5),
      Q => \^d\(21)
    );
\invbuf_reg[1][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(6),
      Q => \^d\(22)
    );
\invbuf_reg[1][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(7),
      Q => \^d\(23)
    );
\invbuf_reg[2][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(0),
      Q => \^d\(8)
    );
\invbuf_reg[2][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(1),
      Q => \^d\(9)
    );
\invbuf_reg[2][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(2),
      Q => \^d\(10)
    );
\invbuf_reg[2][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(3),
      Q => \^d\(11)
    );
\invbuf_reg[2][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(4),
      Q => \^d\(12)
    );
\invbuf_reg[2][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(5),
      Q => \^d\(13)
    );
\invbuf_reg[2][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(6),
      Q => \^d\(14)
    );
\invbuf_reg[2][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(7),
      Q => \^d\(15)
    );
\invbuf_reg[3][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_34,
      Q => \^d\(0)
    );
\invbuf_reg[3][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[3]_70\(1),
      Q => \^d\(1)
    );
\invbuf_reg[3][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_32,
      Q => \^d\(2)
    );
\invbuf_reg[3][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_31,
      Q => \^d\(3)
    );
\invbuf_reg[3][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_30,
      Q => \^d\(4)
    );
\invbuf_reg[3][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_29,
      Q => \^d\(5)
    );
\invbuf_reg[3][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[3]_70\(6),
      Q => \^d\(6)
    );
\invbuf_reg[3][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_27,
      Q => \^d\(7)
    );
\invbuf_reg[4][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(0),
      Q => \^invbuf_reg[4][7]_0\(0)
    );
\invbuf_reg[4][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(1),
      Q => \^invbuf_reg[4][7]_0\(1)
    );
\invbuf_reg[4][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(2),
      Q => \^invbuf_reg[4][7]_0\(2)
    );
\invbuf_reg[4][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(3),
      Q => \^invbuf_reg[4][7]_0\(3)
    );
\invbuf_reg[4][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(4),
      Q => \^invbuf_reg[4][7]_0\(4)
    );
\invbuf_reg[4][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(5),
      Q => \^invbuf_reg[4][7]_0\(5)
    );
\invbuf_reg[4][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(6),
      Q => \^invbuf_reg[4][7]_0\(6)
    );
\invbuf_reg[4][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(7),
      Q => \^invbuf_reg[4][7]_0\(7)
    );
\invbuf_reg[5][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(0),
      Q => \^invbuf_reg[5][7]_0\(0)
    );
\invbuf_reg[5][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(1),
      Q => \^invbuf_reg[5][7]_0\(1)
    );
\invbuf_reg[5][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(2),
      Q => \^invbuf_reg[5][7]_0\(2)
    );
\invbuf_reg[5][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(3),
      Q => \^invbuf_reg[5][7]_0\(3)
    );
\invbuf_reg[5][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(4),
      Q => \^invbuf_reg[5][7]_0\(4)
    );
\invbuf_reg[5][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(5),
      Q => \^invbuf_reg[5][7]_0\(5)
    );
\invbuf_reg[5][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(6),
      Q => \^invbuf_reg[5][7]_0\(6)
    );
\invbuf_reg[5][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(7),
      Q => \^invbuf_reg[5][7]_0\(7)
    );
\invbuf_reg[6][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[6]_74\(0),
      Q => \invbuf_reg[6][2]_0\(8)
    );
\invbuf_reg[6][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[6]_74\(1),
      Q => \invbuf_reg[6][2]_0\(9)
    );
\invbuf_reg[6][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[6]_74\(2),
      Q => \invbuf_reg[6][2]_0\(10)
    );
\invbuf_reg[7][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_46,
      Q => \invbuf_reg[6][2]_0\(0)
    );
\invbuf_reg[7][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_45,
      Q => \invbuf_reg[6][2]_0\(1)
    );
\invbuf_reg[7][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_44,
      Q => \invbuf_reg[6][2]_0\(2)
    );
\invbuf_reg[7][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_43,
      Q => \invbuf_reg[6][2]_0\(3)
    );
\invbuf_reg[7][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_42,
      Q => \invbuf_reg[6][2]_0\(4)
    );
\invbuf_reg[7][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_41,
      Q => \invbuf_reg[6][2]_0\(5)
    );
\invbuf_reg[7][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_40,
      Q => \invbuf_reg[6][2]_0\(6)
    );
\invbuf_reg[7][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_24,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_39,
      Q => \invbuf_reg[6][2]_0\(7)
    );
\invbuf_reg[8][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_0,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_12,
      Q => \invbuf_reg[8][2]_0\(8)
    );
\invbuf_reg[8][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_0,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_11,
      Q => \invbuf_reg[8][2]_0\(9)
    );
\invbuf_reg[8][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_0,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_10,
      Q => \invbuf_reg[8][2]_0\(10)
    );
\invbuf_reg[9][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_0,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_435,
      Q => \invbuf_reg[8][2]_0\(0)
    );
\invbuf_reg[9][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_0,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_434,
      Q => \invbuf_reg[8][2]_0\(1)
    );
\invbuf_reg[9][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_0,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_433,
      Q => \invbuf_reg[8][2]_0\(2)
    );
\invbuf_reg[9][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_0,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_432,
      Q => \invbuf_reg[8][2]_0\(3)
    );
\invbuf_reg[9][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_0,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_431,
      Q => \invbuf_reg[8][2]_0\(4)
    );
\invbuf_reg[9][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_0,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_430,
      Q => \invbuf_reg[8][2]_0\(5)
    );
\invbuf_reg[9][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_0,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_429,
      Q => \invbuf_reg[8][2]_0\(6)
    );
\invbuf_reg[9][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_0,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_428,
      Q => \invbuf_reg[8][2]_0\(7)
    );
\invbuf_reg[9][7]_i_12\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \invbuf_reg[9][7]_i_12_n_0\,
      CO(6) => \invbuf_reg[9][7]_i_12_n_1\,
      CO(5) => \invbuf_reg[9][7]_i_12_n_2\,
      CO(4) => \invbuf_reg[9][7]_i_12_n_3\,
      CO(3) => \invbuf_reg[9][7]_i_12_n_4\,
      CO(2) => \invbuf_reg[9][7]_i_12_n_5\,
      CO(1) => \invbuf_reg[9][7]_i_12_n_6\,
      CO(0) => \invbuf_reg[9][7]_i_12_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => txlast1(0),
      DI(0) => '0',
      O(7 downto 1) => \opbuf_reg[0]5\(12 downto 6),
      O(0) => \NLW_invbuf_reg[9][7]_i_12_O_UNCONNECTED\(0),
      S(7) => \invbuf[9][7]_i_24_n_0\,
      S(6) => \invbuf[9][7]_i_25_n_0\,
      S(5) => \invbuf[9][7]_i_26_n_0\,
      S(4) => \invbuf[9][7]_i_27_n_0\,
      S(3) => \invbuf[9][7]_i_28_n_0\,
      S(2) => \invbuf[9][7]_i_29_n_0\,
      S(1) => \opbuf_reg[0]51_in\(6),
      S(0) => '0'
    );
\ixMemNext[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(0),
      I1 => \^reqinvassign\,
      I2 => \^reqinvhdrengset\,
      O => \invbuf_reg[0][7]_4\(0)
    );
\ixMemNext[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(1),
      I1 => \^reqinvassign\,
      I2 => \^reqinvhdrengset\,
      O => \invbuf_reg[0][7]_4\(1)
    );
\ixMemNext[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(2),
      I1 => \^reqinvassign\,
      I2 => \^reqinvhdrengset\,
      O => \invbuf_reg[0][7]_4\(2)
    );
\ixMemNext[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(3),
      I1 => \^reqinvassign\,
      I2 => \^reqinvhdrengset\,
      O => \invbuf_reg[0][7]_4\(3)
    );
\ixMemNext[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(4),
      I1 => \^reqinvassign\,
      I2 => \^reqinvhdrengset\,
      O => \invbuf_reg[0][7]_4\(4)
    );
\ixMemNext[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(5),
      I1 => \^reqinvassign\,
      I2 => \^reqinvhdrengset\,
      O => \invbuf_reg[0][7]_4\(5)
    );
\ixMemNext[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(6),
      I1 => \^reqinvassign\,
      I2 => \^reqinvhdrengset\,
      O => \invbuf_reg[0][7]_4\(6)
    );
\ixMemNext[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0A0A0300"
    )
        port map (
      I0 => rng_reg_13,
      I1 => \myHdreng/rng\,
      I2 => rng_reg_8,
      I3 => \^reqinvhdrengset\,
      I4 => \^reqinvassign\,
      O => rng_reg_6(0)
    );
\ixMemNext[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(7),
      I1 => \^reqinvassign\,
      I2 => \^reqinvhdrengset\,
      O => \invbuf_reg[0][7]_4\(7)
    );
\ixMemNext[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(4),
      I1 => \^invbuf_reg[0][7]_0\(6),
      I2 => \^invbuf_reg[0][7]_0\(3),
      I3 => \^invbuf_reg[0][7]_0\(5),
      I4 => \ixMemNext[7]_i_4_n_0\,
      O => \myHdreng/rng\
    );
\ixMemNext[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(2),
      I1 => \^invbuf_reg[0][7]_0\(0),
      I2 => \^invbuf_reg[0][7]_0\(1),
      I3 => \^invbuf_reg[0][7]_0\(7),
      O => \ixMemNext[7]_i_4_n_0\
    );
\ixRetbufCrc[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \ixRetbufCrc[4]_i_3_n_0\,
      I1 => \ixRetbufCrc[4]_i_4_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      I3 => \ixRetbufCrc[4]_i_5_n_0\,
      I4 => \stateOp_i_5__1_n_0\,
      I5 => \tixVController_reg_n_0_[0]\,
      O => \ixRetbufCrc[4]_i_2_n_0\
    );
\ixRetbufCrc[4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[1]\,
      O => \ixRetbufCrc[4]_i_3_n_0\
    );
\ixRetbufCrc[4]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \tixVController_reg_n_0_[4]\,
      I1 => \tixVController_reg_n_0_[6]\,
      I2 => \tixVController_reg_n_0_[5]\,
      I3 => \tixVController_reg_n_0_[7]\,
      O => \ixRetbufCrc[4]_i_4_n_0\
    );
\ixRetbufCrc[4]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[1]\,
      I1 => \tixVCommand_reg_n_0_[4]\,
      I2 => \tixVCommand_reg_n_0_[5]\,
      O => \ixRetbufCrc[4]_i_5_n_0\
    );
\ixRetbufCrc[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \tixVController_reg_n_0_[4]\,
      I1 => \tixVController_reg_n_0_[3]\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => \tixVController_reg_n_0_[1]\,
      I5 => \tixVController_reg_n_0_[0]\,
      O => \ixRetbufCrc[5]_i_3_n_0\
    );
\ixRetbufCrc[5]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \stateOp_i_5__1_n_0\,
      I1 => \tixVCommand_reg_n_0_[5]\,
      I2 => \tixVCommand_reg_n_0_[4]\,
      I3 => \tixVCommand_reg_n_0_[1]\,
      O => \ixRetbufCrc[5]_i_4_n_0\
    );
\ixRetbufCrc_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_3,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_63,
      Q => ixRetbufCrc(0)
    );
\ixRetbufCrc_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_3,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_62,
      Q => ixRetbufCrc(1)
    );
\ixRetbufCrc_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_3,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_61,
      Q => ixRetbufCrc(2)
    );
\ixRetbufCrc_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_3,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_60,
      Q => ixRetbufCrc(3)
    );
\ixRetbufCrc_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_3,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_59,
      Q => ixRetbufCrc(4)
    );
\ixRetbufCrc_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_3,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_58,
      Q => ixRetbufCrc(5)
    );
\ixTExp_lcl[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^reqinvdecimacquire\,
      I1 => \^tixvstate1\,
      I2 => rng_reg_7,
      O => E(0)
    );
\lastAXIS_tkeep[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1101"
    )
        port map (
      I0 => \resid[2]_i_5_n_0\,
      I1 => \resid[2]_i_6_n_0\,
      I2 => \resid[1]_i_2_n_0\,
      I3 => \resid[1]_i_3_n_0\,
      O => \lastAXIS_tkeep[3]_i_2_n_0\
    );
\lastAXIS_tkeep[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0070"
    )
        port map (
      I0 => \resid[1]_i_2_n_0\,
      I1 => \resid[1]_i_3_n_0\,
      I2 => \resid[2]_i_6_n_0\,
      I3 => \resid[2]_i_5_n_0\,
      O => \lastAXIS_tkeep[6]_i_2_n_0\
    );
\lastAXIS_tkeep[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \resid[1]_i_2_n_0\,
      I1 => \resid[1]_i_3_n_0\,
      I2 => \resid[2]_i_6_n_0\,
      O => \lastAXIS_tkeep[7]_i_2_n_0\
    );
\lastAXIS_tkeep_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_188,
      D => myRxtx_n_135,
      PRE => \stateOp_reg[1]_6\(0),
      Q => \lastAXIS_tkeep_reg_n_0_[1]\
    );
\lastAXIS_tkeep_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_188,
      D => myRxtx_n_134,
      PRE => \stateOp_reg[1]_6\(0),
      Q => \lastAXIS_tkeep_reg_n_0_[2]\
    );
\lastAXIS_tkeep_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_188,
      D => myRxtx_n_133,
      PRE => \stateOp_reg[1]_6\(0),
      Q => \lastAXIS_tkeep_reg_n_0_[3]\
    );
\lastAXIS_tkeep_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_188,
      D => myRxtx_n_132,
      PRE => \stateOp_reg[1]_6\(0),
      Q => \lastAXIS_tkeep_reg_n_0_[4]\
    );
\lastAXIS_tkeep_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_188,
      D => myRxtx_n_131,
      PRE => \stateOp_reg[1]_6\(0),
      Q => \lastAXIS_tkeep_reg_n_0_[5]\
    );
\lastAXIS_tkeep_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_188,
      D => myRxtx_n_130,
      PRE => \stateOp_reg[1]_6\(0),
      Q => \lastAXIS_tkeep_reg_n_0_[6]\
    );
\lastAXIS_tkeep_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_188,
      D => myRxtx_n_129,
      PRE => \stateOp_reg[1]_6\(0),
      Q => \lastAXIS_tkeep_reg_n_0_[7]\
    );
\len_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_467,
      Q => \len_reg_n_0_[0]\
    );
\len_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_457,
      Q => \len_reg_n_0_[10]\
    );
\len_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_456,
      Q => \len_reg_n_0_[11]\
    );
\len_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_455,
      Q => \len_reg_n_0_[12]\
    );
\len_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_454,
      Q => \len_reg_n_0_[13]\
    );
\len_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_453,
      Q => \len_reg_n_0_[14]\
    );
\len_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_452,
      Q => \len_reg_n_0_[15]\
    );
\len_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_451,
      Q => \len_reg_n_0_[16]\
    );
\len_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_450,
      Q => \len_reg_n_0_[17]\
    );
\len_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_449,
      Q => \len_reg_n_0_[18]\
    );
\len_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_448,
      Q => \len_reg_n_0_[19]\
    );
\len_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_466,
      Q => \len_reg_n_0_[1]\
    );
\len_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_447,
      Q => \len_reg_n_0_[20]\
    );
\len_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_446,
      Q => \len_reg_n_0_[21]\
    );
\len_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_445,
      Q => \len_reg_n_0_[22]\
    );
\len_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_444,
      Q => \len_reg_n_0_[23]\
    );
\len_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_443,
      Q => \len_reg_n_0_[24]\
    );
\len_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_442,
      Q => \len_reg_n_0_[25]\
    );
\len_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_441,
      Q => \len_reg_n_0_[26]\
    );
\len_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_440,
      Q => \len_reg_n_0_[27]\
    );
\len_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_439,
      Q => \len_reg_n_0_[28]\
    );
\len_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_438,
      Q => \len_reg_n_0_[29]\
    );
\len_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_465,
      Q => \len_reg_n_0_[2]\
    );
\len_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_437,
      Q => \len_reg_n_0_[30]\
    );
\len_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_436,
      Q => \len_reg_n_0_[31]\
    );
\len_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_464,
      Q => \len_reg_n_0_[3]\
    );
\len_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_463,
      Q => \len_reg_n_0_[4]\
    );
\len_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_462,
      Q => \len_reg_n_0_[5]\
    );
\len_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_461,
      Q => \len_reg_n_0_[6]\
    );
\len_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_460,
      Q => \len_reg_n_0_[7]\
    );
\len_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_459,
      Q => \len_reg_n_0_[8]\
    );
\len_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_458,
      Q => \len_reg_n_0_[9]\
    );
linNotRot_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F1FF0100"
    )
        port map (
      I0 => linNotRot_i_2_n_0,
      I1 => hdrNotFix_i_2_n_0,
      I2 => ackInvStepmuxSet,
      I3 => \^reqinvstepmuxset\,
      I4 => linNotRot_reg,
      O => stateOp_reg_1
    );
linNotRot_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(7),
      I1 => \^invbuf_reg[0][7]_0\(3),
      I2 => \^invbuf_reg[0][7]_0\(1),
      I3 => \^invbuf_reg[0][7]_0\(5),
      O => linNotRot_i_2_n_0
    );
\lsb[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(0),
      I1 => \lsb[1]_i_2_n_0\,
      I2 => \^invbuf_reg[0][7]_0\(7),
      I3 => \^invbuf_reg[0][7]_0\(5),
      I4 => \^invbuf_reg[0][7]_0\(6),
      O => \invbuf_reg[0][7]_5\(0)
    );
\lsb[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \lsb[1]_i_2_n_0\,
      I1 => \^invbuf_reg[0][7]_0\(7),
      I2 => \^invbuf_reg[0][7]_0\(5),
      I3 => \^invbuf_reg[0][7]_0\(6),
      I4 => \^invbuf_reg[0][7]_0\(0),
      O => \invbuf_reg[0][7]_5\(1)
    );
\lsb[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(3),
      I1 => \^invbuf_reg[0][7]_0\(4),
      I2 => \^invbuf_reg[0][7]_0\(1),
      I3 => \^invbuf_reg[0][7]_0\(2),
      O => \lsb[1]_i_2_n_0\
    );
\mask[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF0008"
    )
        port map (
      I0 => \mask_reg[7]_0\,
      I1 => \^invbuf_reg[0][1]_0\,
      I2 => \mask[3]_i_2_n_0\,
      I3 => \^reqinvmemtrackclearmask\,
      I4 => \mask_reg[0]_2\,
      O => \mask_reg[0]_0\
    );
\mask[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF0008"
    )
        port map (
      I0 => \mask_reg[5]_1\,
      I1 => \mask[4]_i_2_n_0\,
      I2 => \mask[1]_i_2_n_0\,
      I3 => \^reqinvhshktrackclearmask\,
      I4 => \mask_reg[0]_1\,
      O => \mask_reg[0]\
    );
\mask[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF0008"
    )
        port map (
      I0 => \mask_reg[7]_0\,
      I1 => \mask[5]_i_2_n_0\,
      I2 => \mask[3]_i_2_n_0\,
      I3 => \^reqinvmemtrackclearmask\,
      I4 => \mask_reg[1]_2\,
      O => \mask_reg[1]_0\
    );
\mask[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF0008"
    )
        port map (
      I0 => \mask_reg[5]_1\,
      I1 => \mask[5]_i_3_n_0\,
      I2 => \mask[1]_i_2_n_0\,
      I3 => \^reqinvhshktrackclearmask\,
      I4 => \mask_reg[1]_1\,
      O => \mask_reg[1]\
    );
\mask[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(2),
      I1 => \^reqinvhshktracksetmask\,
      I2 => \^invbuf_reg[0][7]_0\(3),
      O => \mask[1]_i_2_n_0\
    );
\mask[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF0008"
    )
        port map (
      I0 => \mask_reg[7]_0\,
      I1 => \mask[6]_i_2_n_0\,
      I2 => \mask[3]_i_2_n_0\,
      I3 => \^reqinvmemtrackclearmask\,
      I4 => \mask_reg[2]_1\,
      O => \mask_reg[2]\
    );
\mask[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF0002"
    )
        port map (
      I0 => \mask_reg[5]_1\,
      I1 => \^invbuf_reg[0][7]_0\(0),
      I2 => \mask[3]_i_2__0_n_0\,
      I3 => \^reqinvhshktrackclearmask\,
      I4 => \mask_reg[2]_0\,
      O => \invbuf_reg[0][0]_1\
    );
\mask[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF0008"
    )
        port map (
      I0 => \mask_reg[7]_0\,
      I1 => \mask[7]_i_3_n_0\,
      I2 => \mask[3]_i_2_n_0\,
      I3 => \^reqinvmemtrackclearmask\,
      I4 => \mask_reg[3]_2\,
      O => \mask_reg[3]\
    );
\mask[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF0008"
    )
        port map (
      I0 => \mask_reg[5]_1\,
      I1 => \^invbuf_reg[0][7]_0\(0),
      I2 => \mask[3]_i_2__0_n_0\,
      I3 => \^reqinvhshktrackclearmask\,
      I4 => \mask_reg[3]_1\,
      O => \invbuf_reg[0][0]_0\
    );
\mask[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(2),
      I1 => \^reqinvmemtracksetmask\,
      I2 => \^invbuf_reg[0][7]_0\(3),
      O => \mask[3]_i_2_n_0\
    );
\mask[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFBFFFFFFFF"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(3),
      I1 => \^reqinvhshktracksetmask\,
      I2 => \^invbuf_reg[0][7]_0\(2),
      I3 => \^reqinvhshktrackset\,
      I4 => \^reqinvhshktrackselect\,
      I5 => \^invbuf_reg[0][7]_0\(1),
      O => \mask[3]_i_2__0_n_0\
    );
\mask[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF0080"
    )
        port map (
      I0 => \mask_reg[7]_0\,
      I1 => \^invbuf_reg[0][1]_0\,
      I2 => \mask[7]_i_2_n_0\,
      I3 => \^reqinvmemtrackclearmask\,
      I4 => \mask_reg[4]_2\,
      O => \mask_reg[4]_0\
    );
\mask[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF4000"
    )
        port map (
      I0 => \^reqinvhshktrackclearmask\,
      I1 => \mask[5]_i_2__0_n_0\,
      I2 => \mask[4]_i_2_n_0\,
      I3 => \mask_reg[5]_1\,
      I4 => \mask_reg[4]_1\,
      O => \mask_reg[4]\
    );
\mask[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^reqinvhshktrackselect\,
      I1 => \^reqinvhshktrackset\,
      I2 => \^invbuf_reg[0][7]_0\(1),
      I3 => \^invbuf_reg[0][7]_0\(0),
      O => \mask[4]_i_2_n_0\
    );
\mask[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF4000"
    )
        port map (
      I0 => \^reqinvmemtrackclearmask\,
      I1 => \mask[7]_i_2_n_0\,
      I2 => \mask[5]_i_2_n_0\,
      I3 => \mask_reg[7]_0\,
      I4 => \mask_reg[5]_3\,
      O => \mask_reg[5]_0\
    );
\mask[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF0080"
    )
        port map (
      I0 => \mask_reg[5]_1\,
      I1 => \mask[5]_i_2__0_n_0\,
      I2 => \mask[5]_i_3_n_0\,
      I3 => \^reqinvhshktrackclearmask\,
      I4 => \mask_reg[5]_2\,
      O => \mask_reg[5]\
    );
\mask[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^reqinvmemtrackselect\,
      I1 => \^reqinvmemtrackset\,
      I2 => \^invbuf_reg[0][7]_0\(0),
      I3 => \^invbuf_reg[0][7]_0\(1),
      O => \mask[5]_i_2_n_0\
    );
\mask[5]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(2),
      I1 => \^reqinvhshktracksetmask\,
      I2 => \^invbuf_reg[0][7]_0\(3),
      O => \mask[5]_i_2__0_n_0\
    );
\mask[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^reqinvhshktrackselect\,
      I1 => \^reqinvhshktrackset\,
      I2 => \^invbuf_reg[0][7]_0\(0),
      I3 => \^invbuf_reg[0][7]_0\(1),
      O => \mask[5]_i_3_n_0\
    );
\mask[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF0080"
    )
        port map (
      I0 => \mask_reg[7]_0\,
      I1 => \mask[6]_i_2_n_0\,
      I2 => \mask[7]_i_2_n_0\,
      I3 => \^reqinvmemtrackclearmask\,
      I4 => \mask_reg[6]_0\,
      O => \mask_reg[6]\
    );
\mask[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(1),
      I1 => \^reqinvmemtrackset\,
      I2 => \^reqinvmemtrackselect\,
      I3 => \^invbuf_reg[0][7]_0\(0),
      O => \mask[6]_i_2_n_0\
    );
\mask[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF0080"
    )
        port map (
      I0 => \mask_reg[7]_0\,
      I1 => \mask[7]_i_2_n_0\,
      I2 => \mask[7]_i_3_n_0\,
      I3 => \^reqinvmemtrackclearmask\,
      I4 => \mask_reg[7]_1\,
      O => \mask_reg[7]\
    );
\mask[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(2),
      I1 => \^reqinvmemtracksetmask\,
      I2 => \^invbuf_reg[0][7]_0\(3),
      O => \mask[7]_i_2_n_0\
    );
\mask[7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^reqinvmemtrackselect\,
      I1 => \^reqinvmemtrackset\,
      I2 => \^invbuf_reg[0][7]_0\(1),
      I3 => \^invbuf_reg[0][7]_0\(0),
      O => \mask[7]_i_3_n_0\
    );
\mask[8]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^invbuf_reg[0][7]_0\(1),
      I1 => \^reqinvmemtrackset\,
      I2 => \^reqinvmemtrackselect\,
      I3 => \^invbuf_reg[0][7]_0\(0),
      O => \^invbuf_reg[0][1]_0\
    );
\mask[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \staTixVTrigger[7]_i_3__1_n_0\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[1]\,
      I5 => \i2cRegaddr[15]_i_11_n_0\,
      O => \^reqinvmemtracksetmask\
    );
myCrc: entity work.design_1_Vsp_core_0_0_Crc8005_64
     port map (
      AXIS_tdata(12 downto 8) => AXIS_tdata(15 downto 11),
      AXIS_tdata(7 downto 0) => AXIS_tdata(7 downto 0),
      AXIS_tlast => AXIS_tlast,
      AXIS_tvalid => AXIS_tvalid,
      CO(0) => \stateOp_reg[2]_i_6__0_n_5\,
      D(7) => myCrc_n_3,
      D(6) => myCrc_n_4,
      D(5) => myCrc_n_5,
      D(4) => myCrc_n_6,
      D(3) => myCrc_n_7,
      D(2) => myCrc_n_8,
      D(1) => myCrc_n_9,
      D(0) => myCrc_n_10,
      E(0) => myCrc_n_1,
      Q(5 downto 0) => \^stateop_reg[5]_0\(5 downto 0),
      aclk_sig => aclk_sig,
      \crcAXIS_tkeep_reg[2]\ => myCrc_n_347,
      \crcAXIS_tkeep_reg[2]_0\ => myCrc_n_348,
      \crcAXIS_tkeep_reg[4]\ => myCrc_n_352,
      \crcAXIS_tkeep_reg[4]_0\ => myCrc_n_353,
      \crcAXIS_tkeep_reg[6]\ => myCrc_n_350,
      \crcAXIS_tkeep_reg[6]_0\ => myCrc_n_351,
      \crcAXIS_tkeep_reg[6]_1\ => myCrc_n_354,
      \crcAXIS_tkeep_reg[6]_2\ => myCrc_n_355,
      \crcAXIS_tkeep_reg[6]_3\ => myCrc_n_356,
      \crcAXIS_tkeep_reg[6]_4\ => myCrc_n_357,
      crc_imd0100_out => crc_imd0100_out,
      crc_imd0112_out => crc_imd0112_out,
      crc_imd0115_out => crc_imd0115_out,
      crc_imd0118_out => crc_imd0118_out,
      crc_imd0121_out => crc_imd0121_out,
      crc_imd0124_out => crc_imd0124_out,
      crc_imd0148_out => crc_imd0148_out,
      crc_imd0149_out => crc_imd0149_out,
      crc_imd0150_out => crc_imd0150_out,
      crc_imd0151_out => crc_imd0151_out,
      crc_imd0152_out => crc_imd0152_out,
      crc_imd0165_out => crc_imd0165_out,
      crc_imd0172_out => crc_imd0172_out,
      crc_imd0173_out => crc_imd0173_out,
      crc_imd0174_out => crc_imd0174_out,
      crc_imd0175_out => crc_imd0175_out,
      crc_imd0176_out => crc_imd0176_out,
      crc_imd0198_out => crc_imd0198_out,
      crc_imd0200_out => crc_imd0200_out,
      crc_imd0202_out => crc_imd0202_out,
      crc_imd041_out => crc_imd041_out,
      crc_imd042_out => crc_imd042_out,
      crc_imd043_out => crc_imd043_out,
      crc_imd065_out => crc_imd065_out,
      crc_imd066_out => crc_imd066_out,
      crc_imd067_out => crc_imd067_out,
      crc_imd068_out => crc_imd068_out,
      crc_imd069_out => crc_imd069_out,
      crc_imd081_out => crc_imd081_out,
      crc_imd083_out => crc_imd083_out,
      crc_imd085_out => crc_imd085_out,
      crc_imd086_out => crc_imd086_out,
      crc_imd087_out => crc_imd087_out,
      \crc_imd[15]_i_18\ => myRxtx_n_572,
      \crc_imd[15]_i_21\(5) => \txAXIS_tdata_reg_n_0_[15]\,
      \crc_imd[15]_i_21\(4) => \txAXIS_tdata_reg_n_0_[12]\,
      \crc_imd[15]_i_21\(3) => \txAXIS_tdata_reg_n_0_[11]\,
      \crc_imd[15]_i_21\(2) => \txAXIS_tdata_reg_n_0_[10]\,
      \crc_imd[15]_i_21\(1) => \txAXIS_tdata_reg_n_0_[7]\,
      \crc_imd[15]_i_21\(0) => \txAXIS_tdata_reg_n_0_[0]\,
      \crc_imd[15]_i_21_0\(5) => rxAXIS_tdata(15),
      \crc_imd[15]_i_21_0\(4 downto 2) => rxAXIS_tdata(12 downto 10),
      \crc_imd[15]_i_21_0\(1) => rxAXIS_tdata(7),
      \crc_imd[15]_i_21_0\(0) => rxAXIS_tdata(0),
      \crc_imd_reg[0]_0\ => myCrc_n_303,
      \crc_imd_reg[0]_1\(0) => \stateOp_reg[1]_6\(0),
      \crc_imd_reg[0]_2\ => myRxtx_n_2,
      \crc_imd_reg[0]_3\(6 downto 0) => AXIS_tkeep(7 downto 1),
      \crc_imd_reg[0]_4\ => crcAXIS_tlast_sig_reg_n_0,
      \crc_imd_reg[0]_5\ => myRxtx_n_581,
      \crc_imd_reg[10]_0\ => myCrc_n_316,
      \crc_imd_reg[10]_1\ => myCrc_n_320,
      \crc_imd_reg[11]_0\(3) => myCrc_n_233,
      \crc_imd_reg[11]_0\(2) => myCrc_n_234,
      \crc_imd_reg[11]_0\(1) => myCrc_n_235,
      \crc_imd_reg[11]_0\(0) => myCrc_n_236,
      \crc_imd_reg[11]_1\(3) => myCrc_n_263,
      \crc_imd_reg[11]_1\(2) => myCrc_n_264,
      \crc_imd_reg[11]_1\(1) => myCrc_n_265,
      \crc_imd_reg[11]_1\(0) => myCrc_n_266,
      \crc_imd_reg[12]_0\ => myCrc_n_333,
      \crc_imd_reg[13]_0\(3) => myCrc_n_237,
      \crc_imd_reg[13]_0\(2) => myCrc_n_238,
      \crc_imd_reg[13]_0\(1) => myCrc_n_239,
      \crc_imd_reg[13]_0\(0) => myCrc_n_240,
      \crc_imd_reg[13]_1\ => myCrc_n_312,
      \crc_imd_reg[13]_2\ => myCrc_n_332,
      \crc_imd_reg[14]_0\(4) => myCrc_n_36,
      \crc_imd_reg[14]_0\(3) => myCrc_n_37,
      \crc_imd_reg[14]_0\(2) => myCrc_n_38,
      \crc_imd_reg[14]_0\(1) => myCrc_n_39,
      \crc_imd_reg[14]_0\(0) => myCrc_n_40,
      \crc_imd_reg[14]_1\(6) => myCrc_n_241,
      \crc_imd_reg[14]_1\(5) => myCrc_n_242,
      \crc_imd_reg[14]_1\(4) => myCrc_n_243,
      \crc_imd_reg[14]_1\(3) => myCrc_n_244,
      \crc_imd_reg[14]_1\(2) => myCrc_n_245,
      \crc_imd_reg[14]_1\(1) => myCrc_n_246,
      \crc_imd_reg[14]_1\(0) => myCrc_n_247,
      \crc_imd_reg[14]_2\ => myCrc_n_310,
      \crc_imd_reg[14]_3\ => myCrc_n_345,
      \crc_imd_reg[15]_0\(15 downto 8) => p_1_in(7 downto 0),
      \crc_imd_reg[15]_0\(7) => myCrc_n_19,
      \crc_imd_reg[15]_0\(6) => myCrc_n_20,
      \crc_imd_reg[15]_0\(5) => myCrc_n_21,
      \crc_imd_reg[15]_0\(4) => myCrc_n_22,
      \crc_imd_reg[15]_0\(3) => myCrc_n_23,
      \crc_imd_reg[15]_0\(2) => myCrc_n_24,
      \crc_imd_reg[15]_0\(1) => myCrc_n_25,
      \crc_imd_reg[15]_0\(0) => myCrc_n_26,
      \crc_imd_reg[15]_1\(6) => myCrc_n_27,
      \crc_imd_reg[15]_1\(5) => myCrc_n_28,
      \crc_imd_reg[15]_1\(4) => myCrc_n_29,
      \crc_imd_reg[15]_1\(3) => myCrc_n_30,
      \crc_imd_reg[15]_1\(2) => myCrc_n_31,
      \crc_imd_reg[15]_1\(1) => myCrc_n_32,
      \crc_imd_reg[15]_1\(0) => myCrc_n_33,
      \crc_imd_reg[15]_10\ => myCrc_n_323,
      \crc_imd_reg[15]_11\ => myCrc_n_331,
      \crc_imd_reg[15]_12\ => myCrc_n_346,
      \crc_imd_reg[15]_13\ => myCrc_n_359,
      \crc_imd_reg[15]_14\(6) => myRxtx_n_557,
      \crc_imd_reg[15]_14\(5) => myRxtx_n_558,
      \crc_imd_reg[15]_14\(4) => myRxtx_n_559,
      \crc_imd_reg[15]_14\(3) => myRxtx_n_560,
      \crc_imd_reg[15]_14\(2) => myRxtx_n_561,
      \crc_imd_reg[15]_14\(1) => myRxtx_n_562,
      \crc_imd_reg[15]_14\(0) => myRxtx_n_563,
      \crc_imd_reg[15]_2\(7) => myCrc_n_41,
      \crc_imd_reg[15]_2\(6) => myCrc_n_42,
      \crc_imd_reg[15]_2\(5) => myCrc_n_43,
      \crc_imd_reg[15]_2\(4) => myCrc_n_44,
      \crc_imd_reg[15]_2\(3) => myCrc_n_45,
      \crc_imd_reg[15]_2\(2) => myCrc_n_46,
      \crc_imd_reg[15]_2\(1) => myCrc_n_47,
      \crc_imd_reg[15]_2\(0) => myCrc_n_48,
      \crc_imd_reg[15]_3\(7) => myCrc_n_49,
      \crc_imd_reg[15]_3\(6) => myCrc_n_50,
      \crc_imd_reg[15]_3\(5) => myCrc_n_51,
      \crc_imd_reg[15]_3\(4) => myCrc_n_52,
      \crc_imd_reg[15]_3\(3) => myCrc_n_53,
      \crc_imd_reg[15]_3\(2) => myCrc_n_54,
      \crc_imd_reg[15]_3\(1) => myCrc_n_55,
      \crc_imd_reg[15]_3\(0) => myCrc_n_56,
      \crc_imd_reg[15]_4\(7) => myCrc_n_57,
      \crc_imd_reg[15]_4\(6) => myCrc_n_58,
      \crc_imd_reg[15]_4\(5) => myCrc_n_59,
      \crc_imd_reg[15]_4\(4) => myCrc_n_60,
      \crc_imd_reg[15]_4\(3) => myCrc_n_61,
      \crc_imd_reg[15]_4\(2) => myCrc_n_62,
      \crc_imd_reg[15]_4\(1) => myCrc_n_63,
      \crc_imd_reg[15]_4\(0) => myCrc_n_64,
      \crc_imd_reg[15]_5\(7) => myCrc_n_65,
      \crc_imd_reg[15]_5\(6) => myCrc_n_66,
      \crc_imd_reg[15]_5\(5) => myCrc_n_67,
      \crc_imd_reg[15]_5\(4) => myCrc_n_68,
      \crc_imd_reg[15]_5\(3) => myCrc_n_69,
      \crc_imd_reg[15]_5\(2) => myCrc_n_70,
      \crc_imd_reg[15]_5\(1) => myCrc_n_71,
      \crc_imd_reg[15]_5\(0) => myCrc_n_72,
      \crc_imd_reg[15]_6\(7) => myCrc_n_81,
      \crc_imd_reg[15]_6\(6) => myCrc_n_82,
      \crc_imd_reg[15]_6\(5) => myCrc_n_83,
      \crc_imd_reg[15]_6\(4) => myCrc_n_84,
      \crc_imd_reg[15]_6\(3) => myCrc_n_85,
      \crc_imd_reg[15]_6\(2) => myCrc_n_86,
      \crc_imd_reg[15]_6\(1) => myCrc_n_87,
      \crc_imd_reg[15]_6\(0) => myCrc_n_88,
      \crc_imd_reg[15]_7\(7) => myCrc_n_89,
      \crc_imd_reg[15]_7\(6) => myCrc_n_90,
      \crc_imd_reg[15]_7\(5) => myCrc_n_91,
      \crc_imd_reg[15]_7\(4) => myCrc_n_92,
      \crc_imd_reg[15]_7\(3) => myCrc_n_93,
      \crc_imd_reg[15]_7\(2) => myCrc_n_94,
      \crc_imd_reg[15]_7\(1) => myCrc_n_95,
      \crc_imd_reg[15]_7\(0) => myCrc_n_96,
      \crc_imd_reg[15]_8\(7) => myCrc_n_209,
      \crc_imd_reg[15]_8\(6) => myCrc_n_210,
      \crc_imd_reg[15]_8\(5) => myCrc_n_211,
      \crc_imd_reg[15]_8\(4) => myCrc_n_212,
      \crc_imd_reg[15]_8\(3) => myCrc_n_213,
      \crc_imd_reg[15]_8\(2) => myCrc_n_214,
      \crc_imd_reg[15]_8\(1) => myCrc_n_215,
      \crc_imd_reg[15]_8\(0) => myCrc_n_216,
      \crc_imd_reg[15]_9\(7) => myCrc_n_217,
      \crc_imd_reg[15]_9\(6) => myCrc_n_218,
      \crc_imd_reg[15]_9\(5) => myCrc_n_219,
      \crc_imd_reg[15]_9\(4) => myCrc_n_220,
      \crc_imd_reg[15]_9\(3) => myCrc_n_221,
      \crc_imd_reg[15]_9\(2) => myCrc_n_222,
      \crc_imd_reg[15]_9\(1) => myCrc_n_223,
      \crc_imd_reg[15]_9\(0) => myCrc_n_224,
      \crc_imd_reg[2]_0\ => myCrc_n_301,
      \crc_imd_reg[2]_1\ => myCrc_n_365,
      \crc_imd_reg[3]_0\ => myCrc_n_300,
      \crc_imd_reg[3]_1\ => myCrc_n_361,
      \crc_imd_reg[3]_2\ => myCrc_n_362,
      \crc_imd_reg[3]_3\ => myRxtx_n_564,
      \crc_imd_reg[3]_4\ => myRxtx_n_575,
      \crc_imd_reg[4]_0\ => myCrc_n_299,
      \crc_imd_reg[4]_1\ => myCrc_n_363,
      \crc_imd_reg[5]_0\ => myRxtx_n_567,
      \crc_imd_reg[6]_0\ => myCrc_n_297,
      \crc_imd_reg[6]_1\ => myCrc_n_358,
      \crc_imd_reg[6]_2\ => myRxtx_n_568,
      \crc_imd_reg[7]_0\(7) => myCrc_n_73,
      \crc_imd_reg[7]_0\(6) => myCrc_n_74,
      \crc_imd_reg[7]_0\(5) => myCrc_n_75,
      \crc_imd_reg[7]_0\(4) => myCrc_n_76,
      \crc_imd_reg[7]_0\(3) => myCrc_n_77,
      \crc_imd_reg[7]_0\(2) => myCrc_n_78,
      \crc_imd_reg[7]_0\(1) => myCrc_n_79,
      \crc_imd_reg[7]_0\(0) => myCrc_n_80,
      \crc_imd_reg[7]_1\(7) => myCrc_n_97,
      \crc_imd_reg[7]_1\(6) => myCrc_n_98,
      \crc_imd_reg[7]_1\(5) => myCrc_n_99,
      \crc_imd_reg[7]_1\(4) => myCrc_n_100,
      \crc_imd_reg[7]_1\(3) => myCrc_n_101,
      \crc_imd_reg[7]_1\(2) => myCrc_n_102,
      \crc_imd_reg[7]_1\(1) => myCrc_n_103,
      \crc_imd_reg[7]_1\(0) => myCrc_n_104,
      \crc_imd_reg[7]_10\(7) => myCrc_n_169,
      \crc_imd_reg[7]_10\(6) => myCrc_n_170,
      \crc_imd_reg[7]_10\(5) => myCrc_n_171,
      \crc_imd_reg[7]_10\(4) => myCrc_n_172,
      \crc_imd_reg[7]_10\(3) => myCrc_n_173,
      \crc_imd_reg[7]_10\(2) => myCrc_n_174,
      \crc_imd_reg[7]_10\(1) => myCrc_n_175,
      \crc_imd_reg[7]_10\(0) => myCrc_n_176,
      \crc_imd_reg[7]_11\(7) => myCrc_n_177,
      \crc_imd_reg[7]_11\(6) => myCrc_n_178,
      \crc_imd_reg[7]_11\(5) => myCrc_n_179,
      \crc_imd_reg[7]_11\(4) => myCrc_n_180,
      \crc_imd_reg[7]_11\(3) => myCrc_n_181,
      \crc_imd_reg[7]_11\(2) => myCrc_n_182,
      \crc_imd_reg[7]_11\(1) => myCrc_n_183,
      \crc_imd_reg[7]_11\(0) => myCrc_n_184,
      \crc_imd_reg[7]_12\(7) => myCrc_n_185,
      \crc_imd_reg[7]_12\(6) => myCrc_n_186,
      \crc_imd_reg[7]_12\(5) => myCrc_n_187,
      \crc_imd_reg[7]_12\(4) => myCrc_n_188,
      \crc_imd_reg[7]_12\(3) => myCrc_n_189,
      \crc_imd_reg[7]_12\(2) => myCrc_n_190,
      \crc_imd_reg[7]_12\(1) => myCrc_n_191,
      \crc_imd_reg[7]_12\(0) => myCrc_n_192,
      \crc_imd_reg[7]_13\(7) => myCrc_n_193,
      \crc_imd_reg[7]_13\(6) => myCrc_n_194,
      \crc_imd_reg[7]_13\(5) => myCrc_n_195,
      \crc_imd_reg[7]_13\(4) => myCrc_n_196,
      \crc_imd_reg[7]_13\(3) => myCrc_n_197,
      \crc_imd_reg[7]_13\(2) => myCrc_n_198,
      \crc_imd_reg[7]_13\(1) => myCrc_n_199,
      \crc_imd_reg[7]_13\(0) => myCrc_n_200,
      \crc_imd_reg[7]_14\(7) => myCrc_n_201,
      \crc_imd_reg[7]_14\(6) => myCrc_n_202,
      \crc_imd_reg[7]_14\(5) => myCrc_n_203,
      \crc_imd_reg[7]_14\(4) => myCrc_n_204,
      \crc_imd_reg[7]_14\(3) => myCrc_n_205,
      \crc_imd_reg[7]_14\(2) => myCrc_n_206,
      \crc_imd_reg[7]_14\(1) => myCrc_n_207,
      \crc_imd_reg[7]_14\(0) => myCrc_n_208,
      \crc_imd_reg[7]_15\(7) => myCrc_n_225,
      \crc_imd_reg[7]_15\(6) => myCrc_n_226,
      \crc_imd_reg[7]_15\(5) => myCrc_n_227,
      \crc_imd_reg[7]_15\(4) => myCrc_n_228,
      \crc_imd_reg[7]_15\(3) => myCrc_n_229,
      \crc_imd_reg[7]_15\(2) => myCrc_n_230,
      \crc_imd_reg[7]_15\(1) => myCrc_n_231,
      \crc_imd_reg[7]_15\(0) => myCrc_n_232,
      \crc_imd_reg[7]_16\(7) => myCrc_n_248,
      \crc_imd_reg[7]_16\(6) => myCrc_n_249,
      \crc_imd_reg[7]_16\(5) => myCrc_n_250,
      \crc_imd_reg[7]_16\(4) => myCrc_n_251,
      \crc_imd_reg[7]_16\(3) => myCrc_n_252,
      \crc_imd_reg[7]_16\(2) => myCrc_n_253,
      \crc_imd_reg[7]_16\(1) => myCrc_n_254,
      \crc_imd_reg[7]_16\(0) => myCrc_n_255,
      \crc_imd_reg[7]_17\(5) => myCrc_n_256,
      \crc_imd_reg[7]_17\(4) => myCrc_n_257,
      \crc_imd_reg[7]_17\(3) => myCrc_n_258,
      \crc_imd_reg[7]_17\(2) => myCrc_n_259,
      \crc_imd_reg[7]_17\(1) => myCrc_n_260,
      \crc_imd_reg[7]_17\(0) => myCrc_n_261,
      \crc_imd_reg[7]_18\ => myCrc_n_296,
      \crc_imd_reg[7]_19\ => myCrc_n_364,
      \crc_imd_reg[7]_2\(7) => myCrc_n_105,
      \crc_imd_reg[7]_2\(6) => myCrc_n_106,
      \crc_imd_reg[7]_2\(5) => myCrc_n_107,
      \crc_imd_reg[7]_2\(4) => myCrc_n_108,
      \crc_imd_reg[7]_2\(3) => myCrc_n_109,
      \crc_imd_reg[7]_2\(2) => myCrc_n_110,
      \crc_imd_reg[7]_2\(1) => myCrc_n_111,
      \crc_imd_reg[7]_2\(0) => myCrc_n_112,
      \crc_imd_reg[7]_20\ => myRxtx_n_571,
      \crc_imd_reg[7]_21\ => myRxtx_n_570,
      \crc_imd_reg[7]_22\ => myRxtx_n_598,
      \crc_imd_reg[7]_23\ => myRxtx_n_569,
      \crc_imd_reg[7]_3\(7) => myCrc_n_113,
      \crc_imd_reg[7]_3\(6) => myCrc_n_114,
      \crc_imd_reg[7]_3\(5) => myCrc_n_115,
      \crc_imd_reg[7]_3\(4) => myCrc_n_116,
      \crc_imd_reg[7]_3\(3) => myCrc_n_117,
      \crc_imd_reg[7]_3\(2) => myCrc_n_118,
      \crc_imd_reg[7]_3\(1) => myCrc_n_119,
      \crc_imd_reg[7]_3\(0) => myCrc_n_120,
      \crc_imd_reg[7]_4\(7) => myCrc_n_121,
      \crc_imd_reg[7]_4\(6) => myCrc_n_122,
      \crc_imd_reg[7]_4\(5) => myCrc_n_123,
      \crc_imd_reg[7]_4\(4) => myCrc_n_124,
      \crc_imd_reg[7]_4\(3) => myCrc_n_125,
      \crc_imd_reg[7]_4\(2) => myCrc_n_126,
      \crc_imd_reg[7]_4\(1) => myCrc_n_127,
      \crc_imd_reg[7]_4\(0) => myCrc_n_128,
      \crc_imd_reg[7]_5\(7) => myCrc_n_129,
      \crc_imd_reg[7]_5\(6) => myCrc_n_130,
      \crc_imd_reg[7]_5\(5) => myCrc_n_131,
      \crc_imd_reg[7]_5\(4) => myCrc_n_132,
      \crc_imd_reg[7]_5\(3) => myCrc_n_133,
      \crc_imd_reg[7]_5\(2) => myCrc_n_134,
      \crc_imd_reg[7]_5\(1) => myCrc_n_135,
      \crc_imd_reg[7]_5\(0) => myCrc_n_136,
      \crc_imd_reg[7]_6\(7) => myCrc_n_137,
      \crc_imd_reg[7]_6\(6) => myCrc_n_138,
      \crc_imd_reg[7]_6\(5) => myCrc_n_139,
      \crc_imd_reg[7]_6\(4) => myCrc_n_140,
      \crc_imd_reg[7]_6\(3) => myCrc_n_141,
      \crc_imd_reg[7]_6\(2) => myCrc_n_142,
      \crc_imd_reg[7]_6\(1) => myCrc_n_143,
      \crc_imd_reg[7]_6\(0) => myCrc_n_144,
      \crc_imd_reg[7]_7\(7) => myCrc_n_145,
      \crc_imd_reg[7]_7\(6) => myCrc_n_146,
      \crc_imd_reg[7]_7\(5) => myCrc_n_147,
      \crc_imd_reg[7]_7\(4) => myCrc_n_148,
      \crc_imd_reg[7]_7\(3) => myCrc_n_149,
      \crc_imd_reg[7]_7\(2) => myCrc_n_150,
      \crc_imd_reg[7]_7\(1) => myCrc_n_151,
      \crc_imd_reg[7]_7\(0) => myCrc_n_152,
      \crc_imd_reg[7]_8\(7) => myCrc_n_153,
      \crc_imd_reg[7]_8\(6) => myCrc_n_154,
      \crc_imd_reg[7]_8\(5) => myCrc_n_155,
      \crc_imd_reg[7]_8\(4) => myCrc_n_156,
      \crc_imd_reg[7]_8\(3) => myCrc_n_157,
      \crc_imd_reg[7]_8\(2) => myCrc_n_158,
      \crc_imd_reg[7]_8\(1) => myCrc_n_159,
      \crc_imd_reg[7]_8\(0) => myCrc_n_160,
      \crc_imd_reg[7]_9\(7) => myCrc_n_161,
      \crc_imd_reg[7]_9\(6) => myCrc_n_162,
      \crc_imd_reg[7]_9\(5) => myCrc_n_163,
      \crc_imd_reg[7]_9\(4) => myCrc_n_164,
      \crc_imd_reg[7]_9\(3) => myCrc_n_165,
      \crc_imd_reg[7]_9\(2) => myCrc_n_166,
      \crc_imd_reg[7]_9\(1) => myCrc_n_167,
      \crc_imd_reg[7]_9\(0) => myCrc_n_168,
      \crc_imd_reg[8]_0\(0) => myCrc_n_262,
      \crc_imd_reg[8]_1\ => myCrc_n_319,
      \crc_imd_reg[8]_2\ => myCrc_n_335,
      \crc_imd_reg[8]_3\ => myCrc_n_360,
      \crc_imd_reg[9]_0\ => myCrc_n_304,
      \crc_imd_reg[9]_1\ => myCrc_n_334,
      \len_reg[0]\ => \tixVBuffer[7]_i_3_n_0\,
      \len_reg[0]_0\ => \tixVBuffer[7]_i_4_n_0\,
      \opbuf_reg[2][0]\(0) => tixVCommand,
      p_10_out(0) => p_10_out(9),
      p_136_in => p_136_in,
      \pollbuf_reg[0][4]\ => myCrc_n_321,
      \pollbuf_reg[0][6]\ => myCrc_n_322,
      \recvAXIS_tdata_sig_reg[11]\ => myCrc_n_349,
      recvAXIS_tlast => recvAXIS_tlast,
      \resid_reg[0]\ => myCrc_n_324,
      \resid_reg[0]_0\ => myCrc_n_325,
      \resid_reg[0]_1\ => myCrc_n_326,
      \resid_reg[0]_2\ => myCrc_n_327,
      \resid_reg[0]_3\ => myCrc_n_328,
      \resid_reg[0]_4\ => myCrc_n_329,
      \resid_reg[0]_5\ => myCrc_n_330,
      \resid_reg[1]\ => myCrc_n_336,
      \resid_reg[1]_0\ => myCrc_n_337,
      \resid_reg[1]_1\ => myCrc_n_338,
      \resid_reg[2]\ => myCrc_n_339,
      \resid_reg[2]_0\ => myCrc_n_340,
      \resid_reg[2]_1\ => myCrc_n_341,
      \resid_reg[2]_2\ => myCrc_n_342,
      \resid_reg[2]_3\ => myCrc_n_343,
      \resid_reg[2]_4\ => myCrc_n_344,
      \retbuf_reg[0][0]\(2 downto 0) => resid(2 downto 0),
      \retbuf_reg[0][0]_0\ => \retbuf[0][7]_i_11_n_0\,
      \retbuf_reg[0][1]\ => \retbuf[0][7]_i_8_n_0\,
      \retbuf_reg[0][1]_0\ => \retbuf[0][1]_i_2_n_0\,
      \retbuf_reg[0][3]\ => \retbuf[0][3]_i_2_n_0\,
      \retbuf_reg[0][4]\ => \retbuf[0][4]_i_2__0_n_0\,
      \retbuf_reg[0][5]\ => \retbuf[0][5]_i_2_n_0\,
      \retbuf_reg[0][6]\ => myRxtx_n_4,
      \retbuf_reg[0][6]_0\ => \retbuf[0][6]_i_3__0_n_0\,
      \retbuf_reg[0][7]\ => myRxtx_n_402,
      \retbuf_reg[11][0]\ => \retbuf[11][7]_i_4_n_0\,
      \retbuf_reg[15][0]\ => \retbuf[15][7]_i_4_n_0\,
      \retbuf_reg[16][0]\ => \retbuf[16][7]_i_4_n_0\,
      \retbuf_reg[16][1]\ => \retbuf[16][7]_i_7_n_0\,
      \retbuf_reg[17][0]\ => \retbuf[17][5]_i_2_n_0\,
      \retbuf_reg[17][1]\ => \retbuf[17][7]_i_4_n_0\,
      \retbuf_reg[18][0]\ => \retbuf[18][7]_i_4_n_0\,
      \retbuf_reg[18][5]\ => \retbuf[17][7]_i_3_n_0\,
      \retbuf_reg[19][0]\ => \retbuf[19][7]_i_4_n_0\,
      \retbuf_reg[19][5]\ => \retbuf[18][7]_i_3_n_0\,
      \retbuf_reg[1][0]\ => \retbuf[1][7]_i_7_n_0\,
      \retbuf_reg[1][0]_0\ => \retbuf[1][0]_i_2_n_0\,
      \retbuf_reg[1][1]\ => \retbuf[1][1]_i_2_n_0\,
      \retbuf_reg[1][2]\ => \retbuf[1][2]_i_2_n_0\,
      \retbuf_reg[1][3]\ => \retbuf[1][3]_i_2_n_0\,
      \retbuf_reg[1][4]\ => \retbuf[1][4]_i_2_n_0\,
      \retbuf_reg[1][5]\ => \retbuf[1][5]_i_2_n_0\,
      \retbuf_reg[1][6]\ => \retbuf[1][6]_i_2_n_0\,
      \retbuf_reg[1][7]\ => myRxtx_n_346,
      \retbuf_reg[1][7]_0\ => \retbuf[1][7]_i_8_n_0\,
      \retbuf_reg[1][7]_1\ => myRxtx_n_345,
      \retbuf_reg[20][0]\ => \retbuf[19][7]_i_3_n_0\,
      \retbuf_reg[20][1]\ => \retbuf[20][7]_i_4_n_0\,
      \retbuf_reg[21][0]\ => \retbuf[21][7]_i_4_n_0\,
      \retbuf_reg[21][3]\ => \retbuf[20][7]_i_3_n_0\,
      \retbuf_reg[22][0]\ => \retbuf[21][7]_i_3_n_0\,
      \retbuf_reg[22][1]\ => \retbuf[22][7]_i_4_n_0\,
      \retbuf_reg[23][0]\ => \retbuf[23][7]_i_4_n_0\,
      \retbuf_reg[23][1]\ => \retbuf[22][7]_i_3_n_0\,
      \retbuf_reg[24][0]\ => \retbuf[23][7]_i_3_n_0\,
      \retbuf_reg[24][1]\ => \retbuf[24][7]_i_4_n_0\,
      \retbuf_reg[25][0]\ => \retbuf[24][7]_i_3_n_0\,
      \retbuf_reg[25][1]\ => \retbuf[25][7]_i_4_n_0\,
      \retbuf_reg[26][0]\ => \retbuf[26][7]_i_4_n_0\,
      \retbuf_reg[26][1]\ => \retbuf[25][7]_i_3_n_0\,
      \retbuf_reg[27][0]\ => \retbuf[27][7]_i_4_n_0\,
      \retbuf_reg[27][5]\ => \retbuf[26][7]_i_3_n_0\,
      \retbuf_reg[28][0]\ => \retbuf[27][7]_i_3_n_0\,
      \retbuf_reg[28][1]\ => \retbuf[28][7]_i_4_n_0\,
      \retbuf_reg[29][0]\ => \retbuf[28][7]_i_3_n_0\,
      \retbuf_reg[2][0]\ => \retbuf[2][7]_i_4__0_n_0\,
      \retbuf_reg[2][0]_0\ => \retbuf[2][0]_i_2_n_0\,
      \retbuf_reg[2][1]\ => \retbuf[2][1]_i_2_n_0\,
      \retbuf_reg[2][2]\ => \retbuf[2][2]_i_2_n_0\,
      \retbuf_reg[2][3]\ => \retbuf[2][3]_i_2_n_0\,
      \retbuf_reg[2][4]\ => \retbuf[2][4]_i_2_n_0\,
      \retbuf_reg[2][5]\ => \retbuf[2][5]_i_2_n_0\,
      \retbuf_reg[2][6]\ => \retbuf[2][6]_i_2_n_0\,
      \retbuf_reg[30][0]\ => \retbuf[30][7]_i_5_n_0\,
      \retbuf_reg[30][1]\ => myRxtx_n_36,
      \retbuf_reg[30][1]_0\ => \retbuf[30][7]_i_3_n_0\,
      \retbuf_reg[31][0]\ => \retbuf[30][7]_i_4_n_0\,
      \retbuf_reg[32][0]\ => \retbuf[32][7]_i_4_n_0\,
      \retbuf_reg[32][4]\ => \retbuf[32][6]_i_3_n_0\,
      \retbuf_reg[32][6]\ => myRxtx_n_54,
      \retbuf_reg[33][0]\ => \retbuf[32][7]_i_3_n_0\,
      \retbuf_reg[34][0]\ => \retbuf[34][7]_i_4_n_0\,
      \retbuf_reg[34][7]\ => \retbuf[34][7]_i_5_n_0\,
      \retbuf_reg[35][0]\ => \retbuf[35][7]_i_4_n_0\,
      \retbuf_reg[35][5]\ => \retbuf[16][5]_i_2_n_0\,
      \retbuf_reg[35][5]_0\ => \retbuf[34][7]_i_3_n_0\,
      \retbuf_reg[36][0]\ => \retbuf[36][7]_i_5_n_0\,
      \retbuf_reg[37][0]\ => \retbuf[37][7]_i_4_n_0\,
      \retbuf_reg[38][0]\ => \retbuf[38][7]_i_6_n_0\,
      \retbuf_reg[39][0]\ => \retbuf[39][7]_i_6_n_0\,
      \retbuf_reg[3][0]\ => \retbuf[3][5]_i_2_n_0\,
      \retbuf_reg[3][0]_0\ => \retbuf[3][0]_i_2_n_0\,
      \retbuf_reg[3][1]\ => \retbuf[3][1]_i_2_n_0\,
      \retbuf_reg[3][4]\ => \retbuf[3][4]_i_2_n_0\,
      \retbuf_reg[3][5]\ => myRxtx_n_13,
      \retbuf_reg[3][5]_0\ => \retbuf[3][5]_i_3_n_0\,
      \retbuf_reg[3][7]\ => \retbuf[3][7]_i_15_n_0\,
      \retbuf_reg[4][1]\ => myRxtx_n_400,
      \retbuf_reg[4][2]\ => myRxtx_n_401,
      \retbuf_reg[4][4]\ => \retbuf[4][4]_i_2_n_0\,
      \retbuf_reg[4][5]\ => \retbuf[4][5]_i_2_n_0\,
      \retbuf_reg[4][6]\ => \retbuf[0][6]_i_2__0_n_0\,
      \retbuf_reg[4][6]_0\ => \retbuf[4][6]_i_2_n_0\,
      \retbuf_reg[4][6]_1\ => \retbuf[4][6]_i_3_n_0\,
      \retbuf_reg[5][0]\ => \retbuf[5][0]_i_2_n_0\,
      \retbuf_reg[5][1]\ => \retbuf[5][1]_i_2_n_0\,
      \retbuf_reg[5][2]\ => \retbuf[5][2]_i_2_n_0\,
      \retbuf_reg[5][3]\ => \retbuf[5][3]_i_2_n_0\,
      \retbuf_reg[5][4]\ => \retbuf[5][4]_i_2_n_0\,
      \retbuf_reg[5][5]\ => \retbuf[5][5]_i_2__0_n_0\,
      \retbuf_reg[5][6]\ => \retbuf[5][6]_i_2_n_0\,
      \retbuf_reg[5][7]\ => \retbuf[5][7]_i_5_n_0\,
      \retbuf_reg[5][7]_0\ => \retbuf[5][7]_i_6_n_0\,
      \retbuf_reg[6][0]\ => myRxtx_n_1,
      \retbuf_reg[6][0]_0\ => \retbuf[6][0]_i_2_n_0\,
      \retbuf_reg[6][1]\ => \retbuf[6][1]_i_2_n_0\,
      \retbuf_reg[6][2]\ => \retbuf[6][2]_i_2_n_0\,
      \retbuf_reg[6][3]\ => \retbuf[6][3]_i_2_n_0\,
      \retbuf_reg[6][4]\ => \retbuf[6][4]_i_2_n_0\,
      \retbuf_reg[6][5]\ => \retbuf[5][7]_i_11_n_0\,
      \retbuf_reg[6][6]\ => \retbuf[6][6]_i_2_n_0\,
      \retbuf_reg[6][7]\ => \retbuf[6][7]_i_4_n_0\,
      \retbuf_reg[6][7]_0\ => \retbuf[6][7]_i_5_n_0\,
      \retbuf_reg[7][3]\ => \retbuf[7][3]_i_2_n_0\,
      \retbuf_reg[7][3]_0\ => \retbuf[7][7]_i_6_n_0\,
      \retbuf_reg[7][5]\ => \retbuf[6][7]_i_6_n_0\,
      \stateOp_reg[0]\ => myCrc_n_34,
      \stateOp_reg[0]_0\ => \stateOp[0]_i_8_n_0\,
      \stateOp_reg[0]_1\ => \stateOp[0]_i_7_n_0\,
      \stateOp_reg[1]\(17) => myCrc_n_267,
      \stateOp_reg[1]\(16) => myCrc_n_268,
      \stateOp_reg[1]\(15) => myCrc_n_269,
      \stateOp_reg[1]\(14) => myCrc_n_270,
      \stateOp_reg[1]\(13) => myCrc_n_271,
      \stateOp_reg[1]\(12) => myCrc_n_272,
      \stateOp_reg[1]\(11) => myCrc_n_273,
      \stateOp_reg[1]\(10) => myCrc_n_274,
      \stateOp_reg[1]\(9) => myCrc_n_275,
      \stateOp_reg[1]\(8) => myCrc_n_276,
      \stateOp_reg[1]\(7) => myCrc_n_277,
      \stateOp_reg[1]\(6) => myCrc_n_278,
      \stateOp_reg[1]\(5) => myCrc_n_279,
      \stateOp_reg[1]\(4) => myCrc_n_280,
      \stateOp_reg[1]\(3) => myCrc_n_281,
      \stateOp_reg[1]\(2) => myCrc_n_282,
      \stateOp_reg[1]\(1) => myCrc_n_283,
      \stateOp_reg[1]\(0) => myCrc_n_284,
      \stateOp_reg[1]_0\ => myCrc_n_289,
      \stateOp_reg[1]_1\ => myCrc_n_290,
      \stateOp_reg[1]_2\ => myCrc_n_295,
      \stateOp_reg[2]\ => myCrc_n_288,
      \stateOp_reg[2]_0\(0) => \crcAXIS_tkeep_reg[1]_i_2_n_5\,
      \stateOp_reg[2]_1\ => myRxtx_n_552,
      \stateOp_reg[3]\ => myCrc_n_287,
      \stateOp_reg[3]_0\ => myCrc_n_291,
      \stateOp_reg[3]_1\ => myCrc_n_292,
      \stateOp_reg[3]_2\ => myCrc_n_298,
      \stateOp_reg[3]_3\ => myCrc_n_302,
      \stateOp_reg[4]\(0) => myCrc_n_2,
      \stateOp_reg[4]_0\ => myCrc_n_293,
      \stateOp_reg[4]_1\ => myCrc_n_294,
      \stateOp_reg[5]\(0) => myCrc_n_285,
      \stateOp_reg[5]_0\(0) => myCrc_n_286,
      \stateOp_reg[5]_1\(1) => \stateOp_next_reg_n_0_[5]\,
      \stateOp_reg[5]_1\(0) => \stateOp_next_reg_n_0_[0]\,
      \stateOp_reg[5]_2\ => \stateOp[5]_i_19_n_0\,
      \stateOp_reg[5]_3\ => \stateOp[5]_i_20_n_0\,
      \stateOp_reg[5]_4\ => \stateOp[5]_i_21_n_0\,
      \stateOp_reg[5]_5\ => \stateOp[5]_i_22_n_0\,
      stateOp_reg_0 => myCrc_n_0,
      stateOp_reg_1 => myRxtx_n_608,
      \tixVBuffer_reg[7]\ => myCrc_n_305,
      \tixVBuffer_reg[7]_0\ => myCrc_n_306,
      \tixVBuffer_reg[7]_1\ => myCrc_n_307,
      \tixVBuffer_reg[7]_2\ => myCrc_n_308,
      \tixVBuffer_reg[7]_3\ => myCrc_n_309,
      \tixVBuffer_reg[7]_4\ => myCrc_n_311,
      \tixVBuffer_reg[7]_5\ => myCrc_n_313,
      \tixVBuffer_reg[7]_6\ => myCrc_n_314,
      \tixVBuffer_reg[7]_7\ => myCrc_n_315,
      \tixVBuffer_reg[7]_8\ => myCrc_n_317,
      \tixVBuffer_reg[7]_9\ => myCrc_n_318,
      \tixVCommand_reg[0]\ => \tixVController[7]_i_3_n_0\,
      \tixVCommand_reg[0]_0\(0) => \opbuf_reg_n_0_[2][0]\,
      \txAXIS_tdata[0]_i_2_0\ => \txAXIS_tdata[0]_i_5__0_n_0\,
      \txAXIS_tdata[0]_i_2_1\ => \txAXIS_tdata[0]_i_6_n_0\,
      \txAXIS_tdata[0]_i_2_2\ => \txAXIS_tdata[0]_i_7_n_0\,
      \txAXIS_tdata[15]_i_6_0\(7 downto 0) => \pollbuf_reg[1]_67\(7 downto 0),
      \txAXIS_tdata[2]_i_3_0\ => \txAXIS_tdata[2]_i_10_n_0\,
      \txAXIS_tdata_reg[0]\ => \txAXIS_tdata[55]_i_6_n_0\,
      \txAXIS_tdata_reg[0]_0\ => \txAXIS_tdata[0]_i_3_n_0\,
      \txAXIS_tdata_reg[0]_1\ => \txAXIS_tdata[6]_i_7__0_n_0\,
      \txAXIS_tdata_reg[10]\ => \txAXIS_tdata[10]_i_3_n_0\,
      \txAXIS_tdata_reg[10]_0\ => \txAXIS_tdata[10]_i_4_n_0\,
      \txAXIS_tdata_reg[10]_1\ => \txAXIS_tdata[10]_i_5_n_0\,
      \txAXIS_tdata_reg[11]\ => \txAXIS_tdata[11]_i_3_n_0\,
      \txAXIS_tdata_reg[11]_0\ => \txAXIS_tdata[11]_i_4_n_0\,
      \txAXIS_tdata_reg[11]_1\ => \txAXIS_tdata[11]_i_5_n_0\,
      \txAXIS_tdata_reg[12]\ => \txAXIS_tdata[12]_i_3_n_0\,
      \txAXIS_tdata_reg[12]_0\ => \txAXIS_tdata[12]_i_4_n_0\,
      \txAXIS_tdata_reg[12]_1\ => \txAXIS_tdata[12]_i_5_n_0\,
      \txAXIS_tdata_reg[13]\ => \txAXIS_tdata[13]_i_3_n_0\,
      \txAXIS_tdata_reg[13]_0\ => \txAXIS_tdata[13]_i_4_n_0\,
      \txAXIS_tdata_reg[13]_1\ => \txAXIS_tdata[13]_i_5_n_0\,
      \txAXIS_tdata_reg[14]\ => \txAXIS_tdata[14]_i_3_n_0\,
      \txAXIS_tdata_reg[14]_0\ => \txAXIS_tdata[14]_i_4_n_0\,
      \txAXIS_tdata_reg[14]_1\ => \txAXIS_tdata[14]_i_5_n_0\,
      \txAXIS_tdata_reg[15]\ => \txAXIS_tdata[15]_i_7_n_0\,
      \txAXIS_tdata_reg[15]_0\ => \txAXIS_tdata[15]_i_14_n_0\,
      \txAXIS_tdata_reg[15]_1\ => \txAXIS_tdata[15]_i_15_n_0\,
      \txAXIS_tdata_reg[1]\ => \txAXIS_tdata[1]_i_5_n_0\,
      \txAXIS_tdata_reg[1]_0\ => myRxtx_n_484,
      \txAXIS_tdata_reg[1]_1\ => \txAXIS_tdata[5]_i_3_n_0\,
      \txAXIS_tdata_reg[1]_2\ => \txAXIS_tdata[1]_i_4_n_0\,
      \txAXIS_tdata_reg[1]_3\ => \txAXIS_tdata[7]_i_8_n_0\,
      \txAXIS_tdata_reg[1]_4\ => \retbuf[36][7]_i_4_n_0\,
      \txAXIS_tdata_reg[2]\ => \txAXIS_tdata[29]_i_7_n_0\,
      \txAXIS_tdata_reg[32]\ => \txAXIS_tdata[32]_i_5_n_0\,
      \txAXIS_tdata_reg[33]\ => \txAXIS_tdata[33]_i_5_n_0\,
      \txAXIS_tdata_reg[34]\ => \txAXIS_tdata[34]_i_5_n_0\,
      \txAXIS_tdata_reg[35]\ => \txAXIS_tdata[35]_i_5_n_0\,
      \txAXIS_tdata_reg[36]\ => \txAXIS_tdata[36]_i_5_n_0\,
      \txAXIS_tdata_reg[37]\ => \txAXIS_tdata[37]_i_5_n_0\,
      \txAXIS_tdata_reg[38]\ => \txAXIS_tdata[38]_i_5_n_0\,
      \txAXIS_tdata_reg[39]\ => \txAXIS_tdata[39]_i_8_n_0\,
      \txAXIS_tdata_reg[39]_0\ => \txAXIS_tdata[39]_i_9_n_0\,
      \txAXIS_tdata_reg[3]\(2) => \retbuf_reg_n_0_[32][3]\,
      \txAXIS_tdata_reg[3]\(1) => \retbuf_reg_n_0_[32][1]\,
      \txAXIS_tdata_reg[3]\(0) => \retbuf_reg_n_0_[32][0]\,
      \txAXIS_tdata_reg[3]_0\ => \txAXIS_tdata[3]_i_5_n_0\,
      \txAXIS_tdata_reg[3]_1\ => \txAXIS_tdata[3]_i_4_n_0\,
      \txAXIS_tdata_reg[40]\ => \txAXIS_tdata[40]_i_2_n_0\,
      \txAXIS_tdata_reg[40]_0\ => \txAXIS_tdata[40]_i_5_n_0\,
      \txAXIS_tdata_reg[40]_1\ => \txAXIS_tdata[40]_i_6_n_0\,
      \txAXIS_tdata_reg[41]\ => \txAXIS_tdata[41]_i_2_n_0\,
      \txAXIS_tdata_reg[41]_0\ => \txAXIS_tdata[41]_i_5_n_0\,
      \txAXIS_tdata_reg[41]_1\ => \txAXIS_tdata[41]_i_6_n_0\,
      \txAXIS_tdata_reg[42]\ => \txAXIS_tdata[42]_i_2_n_0\,
      \txAXIS_tdata_reg[42]_0\ => \txAXIS_tdata[42]_i_5_n_0\,
      \txAXIS_tdata_reg[42]_1\ => \txAXIS_tdata[42]_i_6_n_0\,
      \txAXIS_tdata_reg[43]\ => \txAXIS_tdata[43]_i_2_n_0\,
      \txAXIS_tdata_reg[43]_0\ => \txAXIS_tdata[43]_i_5_n_0\,
      \txAXIS_tdata_reg[43]_1\ => \txAXIS_tdata[43]_i_6_n_0\,
      \txAXIS_tdata_reg[44]\ => \txAXIS_tdata[44]_i_2_n_0\,
      \txAXIS_tdata_reg[44]_0\ => \txAXIS_tdata[44]_i_5_n_0\,
      \txAXIS_tdata_reg[44]_1\ => \txAXIS_tdata[44]_i_6_n_0\,
      \txAXIS_tdata_reg[45]\ => \txAXIS_tdata[45]_i_2_n_0\,
      \txAXIS_tdata_reg[45]_0\ => \txAXIS_tdata[45]_i_5_n_0\,
      \txAXIS_tdata_reg[45]_1\ => \txAXIS_tdata[45]_i_6_n_0\,
      \txAXIS_tdata_reg[46]\ => \txAXIS_tdata[46]_i_2_n_0\,
      \txAXIS_tdata_reg[46]_0\ => \txAXIS_tdata[46]_i_5_n_0\,
      \txAXIS_tdata_reg[46]_1\ => \txAXIS_tdata[46]_i_6_n_0\,
      \txAXIS_tdata_reg[47]\ => \txAXIS_tdata[47]_i_4_n_0\,
      \txAXIS_tdata_reg[47]_0\ => \pollbuf[0][7]_i_7_n_0\,
      \txAXIS_tdata_reg[47]_1\ => \txAXIS_tdata[47]_i_7_n_0\,
      \txAXIS_tdata_reg[47]_2\ => \txAXIS_tdata[47]_i_8_n_0\,
      \txAXIS_tdata_reg[48]\ => \txAXIS_tdata[48]_i_5_n_0\,
      \txAXIS_tdata_reg[48]_0\ => \txAXIS_tdata[48]_i_6_n_0\,
      \txAXIS_tdata_reg[49]\ => \txAXIS_tdata[49]_i_5_n_0\,
      \txAXIS_tdata_reg[49]_0\ => \txAXIS_tdata[49]_i_6_n_0\,
      \txAXIS_tdata_reg[4]\ => \txAXIS_tdata[6]_i_9_n_0\,
      \txAXIS_tdata_reg[4]_0\ => \txAXIS_tdata[6]_i_10_n_0\,
      \txAXIS_tdata_reg[50]\ => \txAXIS_tdata[50]_i_5_n_0\,
      \txAXIS_tdata_reg[50]_0\ => \txAXIS_tdata[50]_i_6_n_0\,
      \txAXIS_tdata_reg[51]\ => \txAXIS_tdata[51]_i_5_n_0\,
      \txAXIS_tdata_reg[51]_0\ => \txAXIS_tdata[51]_i_6_n_0\,
      \txAXIS_tdata_reg[52]\ => \txAXIS_tdata[52]_i_5_n_0\,
      \txAXIS_tdata_reg[52]_0\ => \txAXIS_tdata[52]_i_6_n_0\,
      \txAXIS_tdata_reg[53]\ => \txAXIS_tdata[53]_i_5_n_0\,
      \txAXIS_tdata_reg[53]_0\ => \txAXIS_tdata[53]_i_6_n_0\,
      \txAXIS_tdata_reg[54]\ => \txAXIS_tdata[54]_i_5_n_0\,
      \txAXIS_tdata_reg[54]_0\ => \txAXIS_tdata[54]_i_6_n_0\,
      \txAXIS_tdata_reg[55]\ => \txAXIS_tdata[55]_i_10_n_0\,
      \txAXIS_tdata_reg[55]_0\ => \txAXIS_tdata[55]_i_11_n_0\,
      \txAXIS_tdata_reg[55]_1\ => \txAXIS_tdata[55]_i_13_n_0\,
      \txAXIS_tdata_reg[58]\ => \txAXIS_tdata[58]_i_5_n_0\,
      \txAXIS_tdata_reg[58]_0\ => \txAXIS_tdata[58]_i_6_n_0\,
      \txAXIS_tdata_reg[59]\ => \txAXIS_tdata[59]_i_5_n_0\,
      \txAXIS_tdata_reg[59]_0\ => \txAXIS_tdata[59]_i_6_n_0\,
      \txAXIS_tdata_reg[5]\ => \txAXIS_tdata[5]_i_6_n_0\,
      \txAXIS_tdata_reg[62]\ => \txAXIS_tdata[63]_i_13_n_0\,
      \txAXIS_tdata_reg[62]_0\ => \txAXIS_tdata[63]_i_12_n_0\,
      \txAXIS_tdata_reg[62]_1\ => \txAXIS_tdata[62]_i_5_n_0\,
      \txAXIS_tdata_reg[62]_2\ => \txAXIS_tdata[62]_i_6_n_0\,
      \txAXIS_tdata_reg[7]\ => \txAXIS_tdata[7]_i_3_n_0\,
      \txAXIS_tdata_reg[7]_0\ => \stateOp_next[5]_i_3_n_0\,
      \txAXIS_tdata_reg[7]_1\ => \txAXIS_tdata[7]_i_4_n_0\,
      \txAXIS_tdata_reg[7]_2\(0) => myRxtx_n_485,
      \txAXIS_tdata_reg[7]_3\ => \txAXIS_tdata[7]_i_9__0_n_0\,
      \txAXIS_tdata_reg[7]_4\ => \txAXIS_tdata[7]_i_10__0_n_0\,
      \txAXIS_tdata_reg[7]_5\ => \txAXIS_tdata[7]_i_11_n_0\,
      \txAXIS_tdata_reg[7]_6\(7 downto 0) => \pollbuf_reg[0]_66\(7 downto 0),
      \txAXIS_tdata_reg[8]\ => \txAXIS_tdata[15]_i_8_n_0\,
      \txAXIS_tdata_reg[8]_0\ => \txAXIS_tdata[8]_i_3_n_0\,
      \txAXIS_tdata_reg[8]_1\ => \txAXIS_tdata[8]_i_4_n_0\,
      \txAXIS_tdata_reg[8]_2\ => \txAXIS_tdata[8]_i_5_n_0\,
      \txAXIS_tdata_reg[9]\ => \txAXIS_tdata[9]_i_3_n_0\,
      \txAXIS_tdata_reg[9]_0\ => \txAXIS_tdata[9]_i_4_n_0\,
      \txAXIS_tdata_reg[9]_1\ => \txAXIS_tdata[9]_i_5_n_0\,
      \txlen_reg[28]\ => \wordcntLast[28]_i_5_n_0\,
      \txlen_reg[28]_0\ => \txlen[28]_i_4_n_0\
    );
myRxtx: entity work.design_1_Vsp_core_0_0_Axislave_v1_0
     port map (
      AXIL_arready => AXIL_arready,
      AXIL_awready_sig_reg_0 => AXIL_awready_sig_reg,
      AXIL_bvalid_sig_reg_0 => AXIL_bvalid_sig_reg,
      AXIL_rvalid_sig_reg_0(0) => \stateOp_reg[1]_6\(0),
      AXIL_wready_sig_reg_0 => AXIL_wready_sig_reg,
      AXIS_tlast => AXIS_tlast,
      AXIS_tvalid => AXIS_tvalid,
      CO(0) => \stateOp_reg[2]_i_6__0_n_5\,
      D(7) => myRxtx_n_5,
      D(6) => myRxtx_n_6,
      D(5) => myRxtx_n_7,
      D(4) => myRxtx_n_8,
      D(3) => myRxtx_n_9,
      D(2) => myRxtx_n_10,
      D(1) => myRxtx_n_11,
      D(0) => myRxtx_n_12,
      E(0) => myRxtx_n_0,
      \NWrA_reg[15]\(7) => myRxtx_n_375,
      \NWrA_reg[15]\(6) => myRxtx_n_376,
      \NWrA_reg[15]\(5) => myRxtx_n_377,
      \NWrA_reg[15]\(4) => myRxtx_n_378,
      \NWrA_reg[15]\(3) => myRxtx_n_379,
      \NWrA_reg[15]\(2) => myRxtx_n_380,
      \NWrA_reg[15]\(1) => myRxtx_n_381,
      \NWrA_reg[15]\(0) => myRxtx_n_382,
      \NWrA_reg[23]\(7) => myRxtx_n_383,
      \NWrA_reg[23]\(6) => myRxtx_n_384,
      \NWrA_reg[23]\(5) => myRxtx_n_385,
      \NWrA_reg[23]\(4) => myRxtx_n_386,
      \NWrA_reg[23]\(3) => myRxtx_n_387,
      \NWrA_reg[23]\(2) => myRxtx_n_388,
      \NWrA_reg[23]\(1) => myRxtx_n_389,
      \NWrA_reg[23]\(0) => myRxtx_n_390,
      \NWrA_reg[31]\(7) => myRxtx_n_391,
      \NWrA_reg[31]\(6) => myRxtx_n_392,
      \NWrA_reg[31]\(5) => myRxtx_n_393,
      \NWrA_reg[31]\(4) => myRxtx_n_394,
      \NWrA_reg[31]\(3) => myRxtx_n_395,
      \NWrA_reg[31]\(2) => myRxtx_n_396,
      \NWrA_reg[31]\(1) => myRxtx_n_397,
      \NWrA_reg[31]\(0) => myRxtx_n_398,
      \NWrA_reg[7]\(3) => myRxtx_n_371,
      \NWrA_reg[7]\(2) => myRxtx_n_372,
      \NWrA_reg[7]\(1) => myRxtx_n_373,
      \NWrA_reg[7]\(0) => myRxtx_n_374,
      \NWrB_reg[15]\(7) => myRxtx_n_347,
      \NWrB_reg[15]\(6) => myRxtx_n_348,
      \NWrB_reg[15]\(5) => myRxtx_n_349,
      \NWrB_reg[15]\(4) => myRxtx_n_350,
      \NWrB_reg[15]\(3) => myRxtx_n_351,
      \NWrB_reg[15]\(2) => myRxtx_n_352,
      \NWrB_reg[15]\(1) => myRxtx_n_353,
      \NWrB_reg[15]\(0) => myRxtx_n_354,
      \NWrB_reg[23]\(7) => myRxtx_n_355,
      \NWrB_reg[23]\(6) => myRxtx_n_356,
      \NWrB_reg[23]\(5) => myRxtx_n_357,
      \NWrB_reg[23]\(4) => myRxtx_n_358,
      \NWrB_reg[23]\(3) => myRxtx_n_359,
      \NWrB_reg[23]\(2) => myRxtx_n_360,
      \NWrB_reg[23]\(1) => myRxtx_n_361,
      \NWrB_reg[23]\(0) => myRxtx_n_362,
      \NWrB_reg[31]\(7) => myRxtx_n_363,
      \NWrB_reg[31]\(6) => myRxtx_n_364,
      \NWrB_reg[31]\(5) => myRxtx_n_365,
      \NWrB_reg[31]\(4) => myRxtx_n_366,
      \NWrB_reg[31]\(3) => myRxtx_n_367,
      \NWrB_reg[31]\(2) => myRxtx_n_368,
      \NWrB_reg[31]\(1) => myRxtx_n_369,
      \NWrB_reg[31]\(0) => myRxtx_n_370,
      \NWrB_reg[7]\(6) => myRxtx_n_338,
      \NWrB_reg[7]\(5) => myRxtx_n_339,
      \NWrB_reg[7]\(4) => myRxtx_n_340,
      \NWrB_reg[7]\(3) => myRxtx_n_341,
      \NWrB_reg[7]\(2) => myRxtx_n_342,
      \NWrB_reg[7]\(1) => myRxtx_n_343,
      \NWrB_reg[7]\(0) => myRxtx_n_344,
      O(7) => \wordcntCrcLast_reg[8]_i_2_n_8\,
      O(6) => \wordcntCrcLast_reg[8]_i_2_n_9\,
      O(5) => \wordcntCrcLast_reg[8]_i_2_n_10\,
      O(4) => \wordcntCrcLast_reg[8]_i_2_n_11\,
      O(3) => \wordcntCrcLast_reg[8]_i_2_n_12\,
      O(2) => \wordcntCrcLast_reg[8]_i_2_n_13\,
      O(1) => \wordcntCrcLast_reg[8]_i_2_n_14\,
      O(0) => \wordcntCrcLast_reg[8]_i_2_n_15\,
      Q(5 downto 0) => \^stateop_reg[5]_0\(5 downto 0),
      \TCapt_reg[15]\(3) => myRxtx_n_332,
      \TCapt_reg[15]\(2) => myRxtx_n_333,
      \TCapt_reg[15]\(1) => myRxtx_n_334,
      \TCapt_reg[15]\(0) => myRxtx_n_335,
      \TCapt_reg[7]\(2) => myRxtx_n_267,
      \TCapt_reg[7]\(1) => myRxtx_n_268,
      \TCapt_reg[7]\(0) => myRxtx_n_269,
      aclk_sig => aclk_sig,
      apuAXIL_araddr(1 downto 0) => apuAXIL_araddr(1 downto 0),
      apuAXIL_arvalid => apuAXIL_arvalid,
      apuAXIL_awaddr(1 downto 0) => apuAXIL_awaddr(1 downto 0),
      apuAXIL_awvalid => apuAXIL_awvalid,
      apuAXIL_bready => apuAXIL_bready,
      apuAXIL_rdata(63 downto 0) => apuAXIL_rdata(63 downto 0),
      apuAXIL_rready => apuAXIL_rready,
      apuAXIL_rvalid => apuAXIL_rvalid,
      apuAXIL_wdata(63 downto 0) => apuAXIL_wdata(63 downto 0),
      apuAXIL_wstrb(7 downto 0) => apuAXIL_wstrb(7 downto 0),
      apuAXIL_wvalid => apuAXIL_wvalid,
      commok_sig_reg => myRxtx_n_554,
      commok_sig_reg_0 => \opbuf[0][7]_i_4_n_0\,
      commok_sig_reg_1 => \tixVBuffer[7]_i_4_n_0\,
      commok_sig_reg_2 => myCrc_n_287,
      commok_sig_reg_3 => \^commok\,
      \crcAXIS_tkeep_reg[0]\ => myRxtx_n_581,
      \crcAXIS_tkeep_reg[0]_0\ => \crcAXIS_tkeep[0]_i_2__0_n_0\,
      \crcAXIS_tkeep_reg[0]_1\ => \crcAXIS_tkeep[7]_i_5_n_0\,
      \crcAXIS_tkeep_reg[0]_2\ => \crcAXIS_tkeep[7]_i_6_n_0\,
      \crcAXIS_tkeep_reg[0]_3\ => ackInvSet_sig_i_9_n_0,
      \crcAXIS_tkeep_reg[0]_4\ => \crcAXIS_tkeep[7]_i_12_n_0\,
      \crcAXIS_tkeep_reg[0]_5\ => \crcAXIS_tkeep[7]_i_13_n_0\,
      \crcAXIS_tkeep_reg[0]_6\ => \crcAXIS_tkeep[7]_i_10_n_0\,
      \crcAXIS_tkeep_reg[0]_7\(0) => \crcAXIS_tkeep_reg[7]_i_11_n_12\,
      \crcAXIS_tkeep_reg[3]\ => \crcAXIS_tkeep[3]_i_2_n_0\,
      \crcAXIS_tkeep_reg[3]_0\ => \crcAXIS_tkeep[3]_i_3_n_0\,
      \crcAXIS_tkeep_reg[3]_1\ => \lastAXIS_tkeep[3]_i_2_n_0\,
      \crcAXIS_tkeep_reg[4]\ => \resid[2]_i_5_n_0\,
      \crcAXIS_tkeep_reg[6]\ => \lastAXIS_tkeep[6]_i_2_n_0\,
      \crcAXIS_tkeep_reg[7]\ => \crcAXIS_tkeep[7]_i_8_n_0\,
      \crcAXIS_tkeep_reg[7]_0\ => \lastAXIS_tkeep[7]_i_2_n_0\,
      \crcAXIS_tkeep_reg[7]_1\(6) => \lastAXIS_tkeep_reg_n_0_[7]\,
      \crcAXIS_tkeep_reg[7]_1\(5) => \lastAXIS_tkeep_reg_n_0_[6]\,
      \crcAXIS_tkeep_reg[7]_1\(4) => \lastAXIS_tkeep_reg_n_0_[5]\,
      \crcAXIS_tkeep_reg[7]_1\(3) => \lastAXIS_tkeep_reg_n_0_[4]\,
      \crcAXIS_tkeep_reg[7]_1\(2) => \lastAXIS_tkeep_reg_n_0_[3]\,
      \crcAXIS_tkeep_reg[7]_1\(1) => \lastAXIS_tkeep_reg_n_0_[2]\,
      \crcAXIS_tkeep_reg[7]_1\(0) => \lastAXIS_tkeep_reg_n_0_[1]\,
      \crcAXIS_tkeep_reg[7]_2\ => \crcAXIS_tkeep[7]_i_9_n_0\,
      crcAXIS_tlast_sig_i_6_0 => crcAXIS_tlast_sig_i_13_n_0,
      crcAXIS_tlast_sig_i_6_1(3) => \tixVBuffer_reg_n_0_[3]\,
      crcAXIS_tlast_sig_i_6_1(2) => \tixVBuffer_reg_n_0_[2]\,
      crcAXIS_tlast_sig_i_6_1(1) => \tixVBuffer_reg_n_0_[1]\,
      crcAXIS_tlast_sig_i_6_1(0) => \tixVBuffer_reg_n_0_[0]\,
      crcAXIS_tlast_sig_i_8_0 => crcAXIS_tlast_sig_i_14_n_0,
      crcAXIS_tlast_sig_i_8_1 => crcAXIS_tlast_sig_i_15_n_0,
      crcAXIS_tlast_sig_i_8_2 => \stateOp[5]_i_22_n_0\,
      crcAXIS_tlast_sig_reg => myRxtx_n_608,
      crcAXIS_tlast_sig_reg_0(0) => \crcAXIS_tkeep_reg[1]_i_2_n_5\,
      crcAXIS_tlast_sig_reg_1 => crcAXIS_tlast_sig_i_7_n_0,
      crcAXIS_tlast_sig_reg_2 => crcAXIS_tlast_sig_i_9_n_0,
      crcAXIS_tlast_sig_reg_3 => crcAXIS_tlast_sig_reg_n_0,
      crcAXIS_tlast_sig_reg_4 => crcAXIS_tlast_sig_i_2_n_0,
      crc_imd0100_out => crc_imd0100_out,
      crc_imd0112_out => crc_imd0112_out,
      crc_imd0115_out => crc_imd0115_out,
      crc_imd0118_out => crc_imd0118_out,
      crc_imd0121_out => crc_imd0121_out,
      crc_imd0124_out => crc_imd0124_out,
      crc_imd0148_out => crc_imd0148_out,
      crc_imd0149_out => crc_imd0149_out,
      crc_imd0150_out => crc_imd0150_out,
      crc_imd0151_out => crc_imd0151_out,
      crc_imd0152_out => crc_imd0152_out,
      crc_imd0165_out => crc_imd0165_out,
      crc_imd0172_out => crc_imd0172_out,
      crc_imd0173_out => crc_imd0173_out,
      crc_imd0174_out => crc_imd0174_out,
      crc_imd0175_out => crc_imd0175_out,
      crc_imd0176_out => crc_imd0176_out,
      crc_imd0198_out => crc_imd0198_out,
      crc_imd0200_out => crc_imd0200_out,
      crc_imd0202_out => crc_imd0202_out,
      crc_imd041_out => crc_imd041_out,
      crc_imd042_out => crc_imd042_out,
      crc_imd043_out => crc_imd043_out,
      crc_imd065_out => crc_imd065_out,
      crc_imd066_out => crc_imd066_out,
      crc_imd067_out => crc_imd067_out,
      crc_imd068_out => crc_imd068_out,
      crc_imd069_out => crc_imd069_out,
      crc_imd081_out => crc_imd081_out,
      crc_imd083_out => crc_imd083_out,
      crc_imd085_out => crc_imd085_out,
      crc_imd086_out => crc_imd086_out,
      crc_imd087_out => crc_imd087_out,
      \crc_imd[12]_i_3\ => myCrc_n_360,
      \crc_imd[12]_i_3_0\ => myCrc_n_365,
      \crc_imd[14]_i_5\ => myCrc_n_363,
      \crc_imd[14]_i_5_0\ => myCrc_n_362,
      \crc_imd[15]_i_41_0\ => myCrc_n_364,
      \crc_imd[1]_i_4_0\ => myCrc_n_349,
      \crc_imd_reg[0]\(2 downto 0) => AXIS_tkeep(2 downto 0),
      \crc_imd_reg[0]_0\ => myCrc_n_0,
      \crc_imd_reg[0]_1\ => myCrc_n_352,
      \crc_imd_reg[0]_2\ => myCrc_n_357,
      \crc_imd_reg[11]\ => myRxtx_n_570,
      \crc_imd_reg[12]\ => myRxtx_n_567,
      \crc_imd_reg[12]_0\ => myRxtx_n_568,
      \crc_imd_reg[13]\ => myRxtx_n_569,
      \crc_imd_reg[15]\ => myRxtx_n_575,
      \crc_imd_reg[1]\ => myCrc_n_350,
      \crc_imd_reg[1]_0\ => myCrc_n_353,
      \crc_imd_reg[1]_1\ => myCrc_n_361,
      \crc_imd_reg[2]\(1) => myRxtx_n_336,
      \crc_imd_reg[2]\(0) => myRxtx_n_337,
      \crc_imd_reg[2]_0\ => myCrc_n_348,
      \crc_imd_reg[2]_1\ => myCrc_n_351,
      \crc_imd_reg[2]_2\ => myCrc_n_355,
      \crc_imd_reg[3]\ => myRxtx_n_571,
      \crc_imd_reg[4]\ => myCrc_n_288,
      \crc_imd_reg[4]_0\ => myCrc_n_354,
      \crc_imd_reg[7]\(3) => myRxtx_n_327,
      \crc_imd_reg[7]\(2) => myRxtx_n_328,
      \crc_imd_reg[7]\(1) => myRxtx_n_329,
      \crc_imd_reg[7]\(0) => myRxtx_n_330,
      \crc_imd_reg[7]_0\(0) => myRxtx_n_399,
      \crc_imd_reg[7]_1\(6) => myRxtx_n_557,
      \crc_imd_reg[7]_1\(5) => myRxtx_n_558,
      \crc_imd_reg[7]_1\(4) => myRxtx_n_559,
      \crc_imd_reg[7]_1\(3) => myRxtx_n_560,
      \crc_imd_reg[7]_1\(2) => myRxtx_n_561,
      \crc_imd_reg[7]_1\(1) => myRxtx_n_562,
      \crc_imd_reg[7]_1\(0) => myRxtx_n_563,
      \crc_imd_reg[8]\ => myCrc_n_359,
      \crc_imd_reg[8]_0\ => myCrc_n_358,
      \crc_imd_reg[8]_1\ => myCrc_n_356,
      \crc_imd_reg[9]\ => myCrc_n_347,
      \invbuf_reg[7][0]\ => \opbuf[0][7]_i_3_n_0\,
      \invbuf_reg[7][0]_0\ => \invbuf[0][7]_i_2_n_0\,
      \invbuf_reg[9][0]\ => \invbuf[9][7]_i_3_n_0\,
      \invbuf_reg[9][0]_0\ => \invbuf[9][7]_i_5_n_0\,
      \invbuf_reg[9][0]_1\ => \invbuf[9][7]_i_6_n_0\,
      \invbuf_reg[9][0]_2\ => \invbuf[9][7]_i_8_n_0\,
      \invbuf_reg[9][0]_3\ => \invbuf[9][7]_i_9_n_0\,
      \invbuf_reg[9][0]_4\ => \invbuf[9][7]_i_10_n_0\,
      \invbuf_reg[9][0]_5\ => \invbuf[9][7]_i_11_n_0\,
      \invbuf_reg[9][0]_6\ => \invbuf[9][7]_i_7_n_0\,
      \ixRetbufCrc_reg[0]\(0) => myRxtx_n_264,
      \ixRetbufCrc_reg[0]_0\ => \resid[0]_i_2_n_0\,
      \ixRetbufCrc_reg[2]\ => \resid[2]_i_7_n_0\,
      \ixRetbufCrc_reg[3]\(0) => myRxtx_n_260,
      \ixRetbufCrc_reg[4]\(0) => myRxtx_n_21,
      \ixRetbufCrc_reg[4]_0\(0) => myRxtx_n_37,
      \lastAXIS_tkeep_reg[1]\ => \resid[2]_i_4_n_0\,
      \lastAXIS_tkeep_reg[1]_0\ => \resid[2]_i_3_n_0\,
      \lastAXIS_tkeep_reg[2]\ => \resid[1]_i_4_n_0\,
      \lastAXIS_tkeep_reg[5]\ => \resid[2]_i_6_n_0\,
      \lastAXIS_tkeep_reg[7]\(7) => myRxtx_n_270,
      \lastAXIS_tkeep_reg[7]\(6) => myRxtx_n_271,
      \lastAXIS_tkeep_reg[7]\(5) => myRxtx_n_272,
      \lastAXIS_tkeep_reg[7]\(4) => myRxtx_n_273,
      \lastAXIS_tkeep_reg[7]\(3) => myRxtx_n_274,
      \lastAXIS_tkeep_reg[7]\(2) => myRxtx_n_275,
      \lastAXIS_tkeep_reg[7]\(1) => myRxtx_n_276,
      \lastAXIS_tkeep_reg[7]\(0) => myRxtx_n_277,
      \len_reg[15]\(7 downto 0) => \opbuf_reg[5]_62\(7 downto 0),
      \len_reg[23]\(7 downto 0) => \opbuf_reg[4]_63\(7 downto 0),
      \len_reg[2]\(4) => myRxtx_n_142,
      \len_reg[2]\(3) => myRxtx_n_143,
      \len_reg[2]\(2) => myRxtx_n_144,
      \len_reg[2]\(1) => myRxtx_n_145,
      \len_reg[2]\(0) => myRxtx_n_146,
      \len_reg[31]\(7 downto 0) => \opbuf_reg[3]_64\(7 downto 0),
      \len_reg[7]\(7 downto 0) => \opbuf_reg[6]_61\(7 downto 0),
      \opbuf_reg[0][7]\(7) => myRxtx_n_476,
      \opbuf_reg[0][7]\(6) => myRxtx_n_477,
      \opbuf_reg[0][7]\(5) => myRxtx_n_478,
      \opbuf_reg[0][7]\(4) => myRxtx_n_479,
      \opbuf_reg[0][7]\(3) => myRxtx_n_480,
      \opbuf_reg[0][7]\(2) => myRxtx_n_481,
      \opbuf_reg[0][7]\(1) => myRxtx_n_482,
      \opbuf_reg[0][7]\(0) => myRxtx_n_483,
      \opbuf_reg[1][7]\(7) => myRxtx_n_468,
      \opbuf_reg[1][7]\(6) => myRxtx_n_469,
      \opbuf_reg[1][7]\(5) => myRxtx_n_470,
      \opbuf_reg[1][7]\(4) => myRxtx_n_471,
      \opbuf_reg[1][7]\(3) => myRxtx_n_472,
      \opbuf_reg[1][7]\(2) => myRxtx_n_473,
      \opbuf_reg[1][7]\(1) => myRxtx_n_474,
      \opbuf_reg[1][7]\(0) => myRxtx_n_475,
      \opbuf_reg[2][7]\(7) => myRxtx_n_486,
      \opbuf_reg[2][7]\(6) => myRxtx_n_487,
      \opbuf_reg[2][7]\(5) => myRxtx_n_488,
      \opbuf_reg[2][7]\(4) => myRxtx_n_489,
      \opbuf_reg[2][7]\(3) => myRxtx_n_490,
      \opbuf_reg[2][7]\(2) => myRxtx_n_491,
      \opbuf_reg[2][7]\(1) => myRxtx_n_492,
      \opbuf_reg[2][7]\(0) => myRxtx_n_493,
      \opbuf_reg[3][7]\(31) => myRxtx_n_436,
      \opbuf_reg[3][7]\(30) => myRxtx_n_437,
      \opbuf_reg[3][7]\(29) => myRxtx_n_438,
      \opbuf_reg[3][7]\(28) => myRxtx_n_439,
      \opbuf_reg[3][7]\(27) => myRxtx_n_440,
      \opbuf_reg[3][7]\(26) => myRxtx_n_441,
      \opbuf_reg[3][7]\(25) => myRxtx_n_442,
      \opbuf_reg[3][7]\(24) => myRxtx_n_443,
      \opbuf_reg[3][7]\(23) => myRxtx_n_444,
      \opbuf_reg[3][7]\(22) => myRxtx_n_445,
      \opbuf_reg[3][7]\(21) => myRxtx_n_446,
      \opbuf_reg[3][7]\(20) => myRxtx_n_447,
      \opbuf_reg[3][7]\(19) => myRxtx_n_448,
      \opbuf_reg[3][7]\(18) => myRxtx_n_449,
      \opbuf_reg[3][7]\(17) => myRxtx_n_450,
      \opbuf_reg[3][7]\(16) => myRxtx_n_451,
      \opbuf_reg[3][7]\(15) => myRxtx_n_452,
      \opbuf_reg[3][7]\(14) => myRxtx_n_453,
      \opbuf_reg[3][7]\(13) => myRxtx_n_454,
      \opbuf_reg[3][7]\(12) => myRxtx_n_455,
      \opbuf_reg[3][7]\(11) => myRxtx_n_456,
      \opbuf_reg[3][7]\(10) => myRxtx_n_457,
      \opbuf_reg[3][7]\(9) => myRxtx_n_458,
      \opbuf_reg[3][7]\(8) => myRxtx_n_459,
      \opbuf_reg[3][7]\(7) => myRxtx_n_460,
      \opbuf_reg[3][7]\(6) => myRxtx_n_461,
      \opbuf_reg[3][7]\(5) => myRxtx_n_462,
      \opbuf_reg[3][7]\(4) => myRxtx_n_463,
      \opbuf_reg[3][7]\(3) => myRxtx_n_464,
      \opbuf_reg[3][7]\(2) => myRxtx_n_465,
      \opbuf_reg[3][7]\(1) => myRxtx_n_466,
      \opbuf_reg[3][7]\(0) => myRxtx_n_467,
      p_10_out(0) => p_10_out(9),
      p_136_in => p_136_in,
      plusOp(28 downto 0) => plusOp(31 downto 3),
      \pollbuf_reg[0][7]\ => \pollbuf[0][7]_i_6_n_0\,
      \pollbuf_reg[0][7]_0\(7) => \tixVController_reg_n_0_[7]\,
      \pollbuf_reg[0][7]_0\(6) => \tixVController_reg_n_0_[6]\,
      \pollbuf_reg[0][7]_0\(5) => \tixVController_reg_n_0_[5]\,
      \pollbuf_reg[0][7]_0\(4) => \tixVController_reg_n_0_[4]\,
      \pollbuf_reg[0][7]_0\(3) => \tixVController_reg_n_0_[3]\,
      \pollbuf_reg[0][7]_0\(2) => \tixVController_reg_n_0_[2]\,
      \pollbuf_reg[0][7]_0\(1) => \tixVController_reg_n_0_[1]\,
      \pollbuf_reg[0][7]_0\(0) => \tixVController_reg_n_0_[0]\,
      \pollbuf_reg[0][7]_1\ => \pollbuf[0][7]_i_7_n_0\,
      \pollbuf_reg[1][7]\(7) => \tixVCommand_reg_n_0_[7]\,
      \pollbuf_reg[1][7]\(6) => \tixVCommand_reg_n_0_[6]\,
      \pollbuf_reg[1][7]\(5) => \tixVCommand_reg_n_0_[5]\,
      \pollbuf_reg[1][7]\(4) => \tixVCommand_reg_n_0_[4]\,
      \pollbuf_reg[1][7]\(3) => \tixVCommand_reg_n_0_[3]\,
      \pollbuf_reg[1][7]\(2) => \tixVCommand_reg_n_0_[2]\,
      \pollbuf_reg[1][7]\(1) => \tixVCommand_reg_n_0_[1]\,
      \pollbuf_reg[1][7]\(0) => \tixVCommand_reg_n_0_[0]\,
      \pollbuf_reg[2][3]\ => \pollbuf[0][7]_i_3_n_0\,
      \pollbuf_reg[2][3]_0\ => \pollbuf[0][7]_i_4_n_0\,
      \pollbuf_reg[2][3]_1\ => \pollbuf[0][7]_i_5_n_0\,
      \pollbuf_reg[2][3]_2\ => \pollbuf[2][3]_i_2_n_0\,
      \pollbuf_reg[2][4]\ => \pollbuf[2][4]_i_2_n_0\,
      \pollbuf_reg[2][7]\ => \pollbuf[2][7]_i_2_n_0\,
      \pollbuf_reg[3][1]\ => \resid[2]_i_8_n_0\,
      \pollbuf_reg[3][5]\ => \ixRetbufCrc[5]_i_4_n_0\,
      \pollbuf_reg[3][5]_0\ => \ixRetbufCrc[5]_i_3_n_0\,
      recvAXIS_tdata(5) => rxAXIS_tdata(15),
      recvAXIS_tdata(4 downto 2) => rxAXIS_tdata(12 downto 10),
      recvAXIS_tdata(1) => rxAXIS_tdata(7),
      recvAXIS_tdata(0) => rxAXIS_tdata(0),
      \recvAXIS_tdata_sig_reg[15]_0\(12 downto 8) => AXIS_tdata(15 downto 11),
      \recvAXIS_tdata_sig_reg[15]_0\(7 downto 0) => AXIS_tdata(7 downto 0),
      \recvAXIS_tdata_sig_reg[47]_0\(7 downto 0) => \opbuf[5]_71\(7 downto 0),
      \recvAXIS_tdata_sig_reg[7]_0\(7) => myRxtx_n_27,
      \recvAXIS_tdata_sig_reg[7]_0\(6) => \opbuf[3]_70\(6),
      \recvAXIS_tdata_sig_reg[7]_0\(5) => myRxtx_n_29,
      \recvAXIS_tdata_sig_reg[7]_0\(4) => myRxtx_n_30,
      \recvAXIS_tdata_sig_reg[7]_0\(3) => myRxtx_n_31,
      \recvAXIS_tdata_sig_reg[7]_0\(2) => myRxtx_n_32,
      \recvAXIS_tdata_sig_reg[7]_0\(1) => \opbuf[3]_70\(1),
      \recvAXIS_tdata_sig_reg[7]_0\(0) => myRxtx_n_34,
      \recvAXIS_tdata_sig_reg[7]_1\(7) => myRxtx_n_39,
      \recvAXIS_tdata_sig_reg[7]_1\(6) => myRxtx_n_40,
      \recvAXIS_tdata_sig_reg[7]_1\(5) => myRxtx_n_41,
      \recvAXIS_tdata_sig_reg[7]_1\(4) => myRxtx_n_42,
      \recvAXIS_tdata_sig_reg[7]_1\(3) => myRxtx_n_43,
      \recvAXIS_tdata_sig_reg[7]_1\(2) => myRxtx_n_44,
      \recvAXIS_tdata_sig_reg[7]_1\(1) => myRxtx_n_45,
      \recvAXIS_tdata_sig_reg[7]_1\(0) => myRxtx_n_46,
      \recvAXIS_tdata_sig_reg[7]_2\(7) => myRxtx_n_428,
      \recvAXIS_tdata_sig_reg[7]_2\(6) => myRxtx_n_429,
      \recvAXIS_tdata_sig_reg[7]_2\(5) => myRxtx_n_430,
      \recvAXIS_tdata_sig_reg[7]_2\(4) => myRxtx_n_431,
      \recvAXIS_tdata_sig_reg[7]_2\(3) => myRxtx_n_432,
      \recvAXIS_tdata_sig_reg[7]_2\(2) => myRxtx_n_433,
      \recvAXIS_tdata_sig_reg[7]_2\(1) => myRxtx_n_434,
      \recvAXIS_tdata_sig_reg[7]_2\(0) => myRxtx_n_435,
      \recvAXIS_tdata_sig_reg[7]_3\(7 downto 0) => \opbuf[2]_72\(7 downto 0),
      \recvAXIS_tdata_sig_reg[7]_4\(7 downto 0) => \opbuf[4]_73\(7 downto 0),
      \recvAXIS_tdata_sig_reg[7]_5\(7 downto 0) => \opbuf[6]_74\(7 downto 0),
      \recvAXIS_tdata_sig_reg[7]_6\(7 downto 0) => \opbuf[1]_75\(7 downto 0),
      recvAXIS_tlast => recvAXIS_tlast,
      recvAXIS_tlast_sig_reg_0 => myRxtx_n_564,
      recvAXIS_tlast_sig_reg_i_2_0(28 downto 0) => txlen(28 downto 0),
      reqResetFromHostif => reqResetFromHostif,
      reqReset_sig_reg => myRxtx_n_555,
      reqReset_sig_reg_0 => \stateOp_i_2__0_n_0\,
      reqReset_sig_reg_1 => reqReset_sig_i_2_n_0,
      \resid_reg[0]\(0) => myRxtx_n_20,
      \resid_reg[0]_0\(0) => myRxtx_n_55,
      \resid_reg[0]_1\(0) => myRxtx_n_56,
      \resid_reg[0]_10\(0) => myRxtx_n_254,
      \resid_reg[0]_11\(0) => myRxtx_n_255,
      \resid_reg[0]_12\(0) => myRxtx_n_256,
      \resid_reg[0]_13\(0) => myRxtx_n_257,
      \resid_reg[0]_14\(0) => myRxtx_n_258,
      \resid_reg[0]_15\(0) => myRxtx_n_259,
      \resid_reg[0]_16\(0) => myRxtx_n_261,
      \resid_reg[0]_17\(0) => myRxtx_n_262,
      \resid_reg[0]_18\(0) => myRxtx_n_263,
      \resid_reg[0]_19\(0) => myRxtx_n_265,
      \resid_reg[0]_2\(0) => myRxtx_n_57,
      \resid_reg[0]_20\(0) => myRxtx_n_266,
      \resid_reg[0]_21\ => \resid[1]_i_2_n_0\,
      \resid_reg[0]_3\(0) => myRxtx_n_247,
      \resid_reg[0]_4\(0) => myRxtx_n_248,
      \resid_reg[0]_5\(0) => myRxtx_n_249,
      \resid_reg[0]_6\(0) => myRxtx_n_250,
      \resid_reg[0]_7\(0) => myRxtx_n_251,
      \resid_reg[0]_8\(0) => myRxtx_n_252,
      \resid_reg[0]_9\(0) => myRxtx_n_253,
      \resid_reg[1]\ => \resid[1]_i_3_n_0\,
      \retbuf_reg[0][0]\ => \retbuf[0][0]_i_2_n_0\,
      \retbuf_reg[0][0]_0\ => myCrc_n_324,
      \retbuf_reg[0][2]\ => \retbuf[0][7]_i_8_n_0\,
      \retbuf_reg[0][2]_0\ => \retbuf[0][2]_i_3_n_0\,
      \retbuf_reg[0][2]_1\ => \retbuf[0][7]_i_19_n_0\,
      \retbuf_reg[0][7]\ => \retbuf[0][7]_i_3_n_0\,
      \retbuf_reg[0][7]_0\ => \retbuf[0][7]_i_4_n_0\,
      \retbuf_reg[0][7]_1\ => \retbuf[0][7]_i_5_n_0\,
      \retbuf_reg[0][7]_2\ => \retbuf[0][7]_i_6_n_0\,
      \retbuf_reg[0][7]_3\ => \retbuf[0][7]_i_7_n_0\,
      \retbuf_reg[0][7]_4\ => \retbuf[0][7]_i_20_n_0\,
      \retbuf_reg[10][0]\ => \retbuf[10][7]_i_3_n_0\,
      \retbuf_reg[10][0]_0\ => \retbuf[10][7]_i_4_n_0\,
      \retbuf_reg[11][0]\ => \retbuf[11][7]_i_3_n_0\,
      \retbuf_reg[11][4]\ => \retbuf[11][7]_i_4_n_0\,
      \retbuf_reg[12][0]\ => \retbuf[12][7]_i_3_n_0\,
      \retbuf_reg[12][0]_0\ => \retbuf[12][7]_i_4_n_0\,
      \retbuf_reg[12][7]\(27 downto 0) => \retbuf_reg[12][7]_0\(27 downto 0),
      \retbuf_reg[13][0]\ => \retbuf[13][7]_i_3_n_0\,
      \retbuf_reg[13][0]_0\ => \retbuf[13][7]_i_4_n_0\,
      \retbuf_reg[14][0]\ => \retbuf[14][7]_i_3_n_0\,
      \retbuf_reg[14][0]_0\ => \retbuf[14][7]_i_4_n_0\,
      \retbuf_reg[15][0]\ => \retbuf[8][7]_i_6_n_0\,
      \retbuf_reg[15][0]_0\ => \retbuf[8][7]_i_7_n_0\,
      \retbuf_reg[15][0]_1\ => \retbuf[8][7]_i_8_n_0\,
      \retbuf_reg[15][0]_2\ => \retbuf[15][7]_i_3_n_0\,
      \retbuf_reg[15][1]\ => \retbuf[15][7]_i_4_n_0\,
      \retbuf_reg[15][7]\(15 downto 8) => p_1_in(7 downto 0),
      \retbuf_reg[15][7]\(7) => myCrc_n_19,
      \retbuf_reg[15][7]\(6) => myCrc_n_20,
      \retbuf_reg[15][7]\(5) => myCrc_n_21,
      \retbuf_reg[15][7]\(4) => myCrc_n_22,
      \retbuf_reg[15][7]\(3) => myCrc_n_23,
      \retbuf_reg[15][7]\(2) => myCrc_n_24,
      \retbuf_reg[15][7]\(1) => myCrc_n_25,
      \retbuf_reg[15][7]\(0) => myCrc_n_26,
      \retbuf_reg[16][0]\ => \retbuf[16][7]_i_4_n_0\,
      \retbuf_reg[16][0]_0\ => \retbuf[16][7]_i_5_n_0\,
      \retbuf_reg[16][0]_1\ => \retbuf[16][7]_i_6_n_0\,
      \retbuf_reg[17][0]\ => \retbuf[17][7]_i_3_n_0\,
      \retbuf_reg[18][0]\ => \retbuf[18][7]_i_3_n_0\,
      \retbuf_reg[19][0]\ => \retbuf[19][7]_i_3_n_0\,
      \retbuf_reg[1][0]\ => \retbuf[1][7]_i_3_n_0\,
      \retbuf_reg[1][0]_0\ => \retbuf[1][7]_i_4_n_0\,
      \retbuf_reg[1][0]_1\ => \retbuf[1][7]_i_5_n_0\,
      \retbuf_reg[1][0]_2\ => \retbuf[1][7]_i_6_n_0\,
      \retbuf_reg[20][0]\ => \retbuf[20][7]_i_3_n_0\,
      \retbuf_reg[21][0]\ => \retbuf[21][7]_i_3_n_0\,
      \retbuf_reg[22][0]\ => \retbuf[22][7]_i_3_n_0\,
      \retbuf_reg[23][0]\ => \retbuf[23][7]_i_3_n_0\,
      \retbuf_reg[24][0]\ => \retbuf[24][7]_i_3_n_0\,
      \retbuf_reg[25][0]\ => \retbuf[25][7]_i_3_n_0\,
      \retbuf_reg[26][0]\ => \retbuf[26][7]_i_3_n_0\,
      \retbuf_reg[27][0]\ => \retbuf[27][7]_i_3_n_0\,
      \retbuf_reg[28][0]\ => \retbuf[28][7]_i_3_n_0\,
      \retbuf_reg[29][0]\ => \retbuf[29][7]_i_3_n_0\,
      \retbuf_reg[29][0]_0\ => \retbuf[29][7]_i_4_n_0\,
      \retbuf_reg[2][0]\ => \retbuf[2][7]_i_3_n_0\,
      \retbuf_reg[2][7]\ => \retbuf[2][7]_i_4__0_n_0\,
      \retbuf_reg[2][7]_0\ => \retbuf[2][7]_i_5_n_0\,
      \retbuf_reg[30][0]\ => \retbuf[30][7]_i_3_n_0\,
      \retbuf_reg[30][0]_0\ => \retbuf[30][7]_i_4_n_0\,
      \retbuf_reg[31][0]\ => \retbuf[31][7]_i_3_n_0\,
      \retbuf_reg[32][0]\ => \retbuf[32][7]_i_3_n_0\,
      \retbuf_reg[33][0]\ => \retbuf[33][7]_i_3_n_0\,
      \retbuf_reg[34][0]\ => \retbuf[34][7]_i_3_n_0\,
      \retbuf_reg[34][0]_0\ => \retbuf[34][7]_i_4_n_0\,
      \retbuf_reg[35][0]\ => \retbuf[35][7]_i_3_n_0\,
      \retbuf_reg[36][7]\ => \retbuf[36][7]_i_3_n_0\,
      \retbuf_reg[36][7]_0\ => \retbuf[36][7]_i_4_n_0\,
      \retbuf_reg[37][7]\ => \retbuf[37][7]_i_3_n_0\,
      \retbuf_reg[38][7]\ => \retbuf[38][7]_i_3_n_0\,
      \retbuf_reg[38][7]_0\ => \retbuf[38][7]_i_5_n_0\,
      \retbuf_reg[39][7]\ => \retbuf[39][7]_i_3_n_0\,
      \retbuf_reg[39][7]_0\ => \retbuf[39][7]_i_4_n_0\,
      \retbuf_reg[39][7]_1\ => \retbuf[39][7]_i_5_n_0\,
      \retbuf_reg[39][7]_2\(2 downto 1) => ixRetbufCrc(4 downto 3),
      \retbuf_reg[39][7]_2\(0) => ixRetbufCrc(0),
      \retbuf_reg[39][7]_3\ => \retbuf[38][7]_i_4_n_0\,
      \retbuf_reg[3][2]\ => \retbuf[3][2]_i_2_n_0\,
      \retbuf_reg[3][2]_0\ => myCrc_n_328,
      \retbuf_reg[3][3]\ => \retbuf[3][3]_i_2_n_0\,
      \retbuf_reg[3][3]_0\ => myCrc_n_327,
      \retbuf_reg[3][6]\ => \retbuf[3][6]_i_2_n_0\,
      \retbuf_reg[3][6]_0\ => myCrc_n_326,
      \retbuf_reg[3][7]\ => \retbuf[3][7]_i_3_n_0\,
      \retbuf_reg[3][7]_0\ => \retbuf[3][7]_i_4_n_0\,
      \retbuf_reg[3][7]_1\ => \retbuf[3][7]_i_5_n_0\,
      \retbuf_reg[3][7]_2\(4 downto 3) => \retbuf_reg[1][7]_0\(15 downto 14),
      \retbuf_reg[3][7]_2\(2 downto 1) => \retbuf_reg[1][7]_0\(11 downto 10),
      \retbuf_reg[3][7]_2\(0) => \retbuf_reg[1][7]_0\(7),
      \retbuf_reg[3][7]_3\ => \retbuf[3][7]_i_6_n_0\,
      \retbuf_reg[3][7]_4\ => myCrc_n_325,
      \retbuf_reg[4][0]\ => \retbuf[4][6]_i_3_n_0\,
      \retbuf_reg[4][0]_0\ => \retbuf[4][0]_i_3_n_0\,
      \retbuf_reg[4][0]_1\ => \retbuf[4][0]_i_4_n_0\,
      \retbuf_reg[4][1]\ => \retbuf[4][1]_i_3_n_0\,
      \retbuf_reg[4][1]_0\ => \retbuf[4][1]_i_4_n_0\,
      \retbuf_reg[4][2]\ => \retbuf[4][2]_i_3_n_0\,
      \retbuf_reg[4][2]_0\ => \retbuf[4][2]_i_4_n_0\,
      \retbuf_reg[4][3]\ => \retbuf[4][3]_i_3_n_0\,
      \retbuf_reg[4][3]_0\ => \retbuf[4][3]_i_4_n_0\,
      \retbuf_reg[4][7]\ => \retbuf[4][7]_i_3_n_0\,
      \retbuf_reg[4][7]_0\ => \retbuf[4][7]_i_4_n_0\,
      \retbuf_reg[4][7]_1\ => \retbuf[4][7]_i_5_n_0\,
      \retbuf_reg[4][7]_2\ => \retbuf[0][6]_i_2__0_n_0\,
      \retbuf_reg[4][7]_3\ => \retbuf[4][7]_i_6_n_0\,
      \retbuf_reg[4][7]_4\ => \retbuf[4][7]_i_7_n_0\,
      \retbuf_reg[4][7]_5\ => myCrc_n_323,
      \retbuf_reg[5][0]\ => \retbuf[5][7]_i_3_n_0\,
      \retbuf_reg[5][0]_0\ => \retbuf[5][7]_i_4_n_0\,
      \retbuf_reg[6][0]\ => \retbuf[6][7]_i_3_n_0\,
      \retbuf_reg[6][5]\ => \retbuf[0][0]_i_3_n_0\,
      \retbuf_reg[6][5]_0\ => \retbuf_reg[6][5]_i_2_n_0\,
      \retbuf_reg[6][5]_1\ => myCrc_n_329,
      \retbuf_reg[7][4]\ => \retbuf[7][7]_i_6_n_0\,
      \retbuf_reg[7][5]\ => \stateOp_i_3__1_n_0\,
      \retbuf_reg[7][5]_0\ => myCrc_n_330,
      \retbuf_reg[7][7]\ => \retbuf[7][7]_i_3_n_0\,
      \retbuf_reg[7][7]_0\ => \ixRetbufCrc[4]_i_2_n_0\,
      \retbuf_reg[7][7]_1\ => \retbuf[7][7]_i_4_n_0\,
      \retbuf_reg[7][7]_2\(3 downto 0) => \retbuf[4][7]_i_12_0\(3 downto 0),
      \retbuf_reg[8][0]\ => \retbuf[8][7]_i_4_n_0\,
      \retbuf_reg[8][0]_0\ => \retbuf[8][7]_i_5_n_0\,
      \retbuf_reg[8][7]\(27 downto 0) => \retbuf_reg[8][7]_0\(27 downto 0),
      \retbuf_reg[9][0]\ => \retbuf[9][7]_i_3_n_0\,
      \retbuf_reg[9][0]_0\ => \retbuf[9][7]_i_4_n_0\,
      \rxlen_reg[0]\ => myRxtx_n_556,
      \rxlen_reg[0]_0\ => \rxlen[0]_i_5_n_0\,
      \rxlen_reg[0]_1\ => \stateOp[5]_i_20_n_0\,
      \rxlen_reg[0]_2\ => \rxlen[0]_i_6_n_0\,
      \rxlen_reg[0]_3\ => \rxlen[0]_i_3_n_0\,
      \rxlen_reg[0]_4\ => \rxlen_reg_n_0_[0]\,
      \sendAXIL_rdata_reg[63]_0\(63) => \txAXIS_tdata_reg_n_0_[63]\,
      \sendAXIL_rdata_reg[63]_0\(62) => \txAXIS_tdata_reg_n_0_[62]\,
      \sendAXIL_rdata_reg[63]_0\(61) => \txAXIS_tdata_reg_n_0_[61]\,
      \sendAXIL_rdata_reg[63]_0\(60) => \txAXIS_tdata_reg_n_0_[60]\,
      \sendAXIL_rdata_reg[63]_0\(59) => \txAXIS_tdata_reg_n_0_[59]\,
      \sendAXIL_rdata_reg[63]_0\(58) => \txAXIS_tdata_reg_n_0_[58]\,
      \sendAXIL_rdata_reg[63]_0\(57) => \txAXIS_tdata_reg_n_0_[57]\,
      \sendAXIL_rdata_reg[63]_0\(56) => \txAXIS_tdata_reg_n_0_[56]\,
      \sendAXIL_rdata_reg[63]_0\(55) => \txAXIS_tdata_reg_n_0_[55]\,
      \sendAXIL_rdata_reg[63]_0\(54) => \txAXIS_tdata_reg_n_0_[54]\,
      \sendAXIL_rdata_reg[63]_0\(53) => \txAXIS_tdata_reg_n_0_[53]\,
      \sendAXIL_rdata_reg[63]_0\(52) => \txAXIS_tdata_reg_n_0_[52]\,
      \sendAXIL_rdata_reg[63]_0\(51) => \txAXIS_tdata_reg_n_0_[51]\,
      \sendAXIL_rdata_reg[63]_0\(50) => \txAXIS_tdata_reg_n_0_[50]\,
      \sendAXIL_rdata_reg[63]_0\(49) => \txAXIS_tdata_reg_n_0_[49]\,
      \sendAXIL_rdata_reg[63]_0\(48) => \txAXIS_tdata_reg_n_0_[48]\,
      \sendAXIL_rdata_reg[63]_0\(47) => \txAXIS_tdata_reg_n_0_[47]\,
      \sendAXIL_rdata_reg[63]_0\(46) => \txAXIS_tdata_reg_n_0_[46]\,
      \sendAXIL_rdata_reg[63]_0\(45) => \txAXIS_tdata_reg_n_0_[45]\,
      \sendAXIL_rdata_reg[63]_0\(44) => \txAXIS_tdata_reg_n_0_[44]\,
      \sendAXIL_rdata_reg[63]_0\(43) => \txAXIS_tdata_reg_n_0_[43]\,
      \sendAXIL_rdata_reg[63]_0\(42) => \txAXIS_tdata_reg_n_0_[42]\,
      \sendAXIL_rdata_reg[63]_0\(41) => \txAXIS_tdata_reg_n_0_[41]\,
      \sendAXIL_rdata_reg[63]_0\(40) => \txAXIS_tdata_reg_n_0_[40]\,
      \sendAXIL_rdata_reg[63]_0\(39) => \txAXIS_tdata_reg_n_0_[39]\,
      \sendAXIL_rdata_reg[63]_0\(38) => \txAXIS_tdata_reg_n_0_[38]\,
      \sendAXIL_rdata_reg[63]_0\(37) => \txAXIS_tdata_reg_n_0_[37]\,
      \sendAXIL_rdata_reg[63]_0\(36) => \txAXIS_tdata_reg_n_0_[36]\,
      \sendAXIL_rdata_reg[63]_0\(35) => \txAXIS_tdata_reg_n_0_[35]\,
      \sendAXIL_rdata_reg[63]_0\(34) => \txAXIS_tdata_reg_n_0_[34]\,
      \sendAXIL_rdata_reg[63]_0\(33) => \txAXIS_tdata_reg_n_0_[33]\,
      \sendAXIL_rdata_reg[63]_0\(32) => \txAXIS_tdata_reg_n_0_[32]\,
      \sendAXIL_rdata_reg[63]_0\(31) => \txAXIS_tdata_reg_n_0_[31]\,
      \sendAXIL_rdata_reg[63]_0\(30) => \txAXIS_tdata_reg_n_0_[30]\,
      \sendAXIL_rdata_reg[63]_0\(29) => \txAXIS_tdata_reg_n_0_[29]\,
      \sendAXIL_rdata_reg[63]_0\(28) => \txAXIS_tdata_reg_n_0_[28]\,
      \sendAXIL_rdata_reg[63]_0\(27) => \txAXIS_tdata_reg_n_0_[27]\,
      \sendAXIL_rdata_reg[63]_0\(26) => \txAXIS_tdata_reg_n_0_[26]\,
      \sendAXIL_rdata_reg[63]_0\(25) => \txAXIS_tdata_reg_n_0_[25]\,
      \sendAXIL_rdata_reg[63]_0\(24) => \txAXIS_tdata_reg_n_0_[24]\,
      \sendAXIL_rdata_reg[63]_0\(23) => \txAXIS_tdata_reg_n_0_[23]\,
      \sendAXIL_rdata_reg[63]_0\(22) => \txAXIS_tdata_reg_n_0_[22]\,
      \sendAXIL_rdata_reg[63]_0\(21) => \txAXIS_tdata_reg_n_0_[21]\,
      \sendAXIL_rdata_reg[63]_0\(20) => \txAXIS_tdata_reg_n_0_[20]\,
      \sendAXIL_rdata_reg[63]_0\(19) => \txAXIS_tdata_reg_n_0_[19]\,
      \sendAXIL_rdata_reg[63]_0\(18) => \txAXIS_tdata_reg_n_0_[18]\,
      \sendAXIL_rdata_reg[63]_0\(17) => \txAXIS_tdata_reg_n_0_[17]\,
      \sendAXIL_rdata_reg[63]_0\(16) => \txAXIS_tdata_reg_n_0_[16]\,
      \sendAXIL_rdata_reg[63]_0\(15) => \txAXIS_tdata_reg_n_0_[15]\,
      \sendAXIL_rdata_reg[63]_0\(14) => \txAXIS_tdata_reg_n_0_[14]\,
      \sendAXIL_rdata_reg[63]_0\(13) => \txAXIS_tdata_reg_n_0_[13]\,
      \sendAXIL_rdata_reg[63]_0\(12) => \txAXIS_tdata_reg_n_0_[12]\,
      \sendAXIL_rdata_reg[63]_0\(11) => \txAXIS_tdata_reg_n_0_[11]\,
      \sendAXIL_rdata_reg[63]_0\(10) => \txAXIS_tdata_reg_n_0_[10]\,
      \sendAXIL_rdata_reg[63]_0\(9) => \txAXIS_tdata_reg_n_0_[9]\,
      \sendAXIL_rdata_reg[63]_0\(8) => \txAXIS_tdata_reg_n_0_[8]\,
      \sendAXIL_rdata_reg[63]_0\(7) => \txAXIS_tdata_reg_n_0_[7]\,
      \sendAXIL_rdata_reg[63]_0\(6) => \txAXIS_tdata_reg_n_0_[6]\,
      \sendAXIL_rdata_reg[63]_0\(5) => \txAXIS_tdata_reg_n_0_[5]\,
      \sendAXIL_rdata_reg[63]_0\(4) => \txAXIS_tdata_reg_n_0_[4]\,
      \sendAXIL_rdata_reg[63]_0\(3) => \txAXIS_tdata_reg_n_0_[3]\,
      \sendAXIL_rdata_reg[63]_0\(2) => \txAXIS_tdata_reg_n_0_[2]\,
      \sendAXIL_rdata_reg[63]_0\(1) => \txAXIS_tdata_reg_n_0_[1]\,
      \sendAXIL_rdata_reg[63]_0\(0) => \txAXIS_tdata_reg_n_0_[0]\,
      \stateOp[3]_i_3_0\(0) => \stateOp_reg[1]_i_7_n_0\,
      \stateOp_next_reg[0]\ => \stateOp_next[5]_i_3_n_0\,
      \stateOp_next_reg[1]\ => \stateOp_next[1]_i_2_n_0\,
      \stateOp_next_reg[4]\ => \stateOp_next[4]_i_2_n_0\,
      \stateOp_next_reg[5]\ => \stateOp_next[5]_i_5_n_0\,
      \stateOp_next_reg[5]_0\ => \stateOp_next[5]_i_4_n_0\,
      \stateOp_next_reg[5]_1\ => \stateOp_next[5]_i_6_n_0\,
      stateOp_reg => myCrc_n_34,
      \stateOp_reg[0]\(0) => myRxtx_n_24,
      \stateOp_reg[0]_0\ => myRxtx_n_535,
      \stateOp_reg[0]_1\ => \stateOp[5]_i_16_n_0\,
      \stateOp_reg[0]_10\ => myWordto_n_2,
      \stateOp_reg[0]_11\ => myXferto_n_2,
      \stateOp_reg[0]_12\ => myXferto_n_4,
      \stateOp_reg[0]_13\ => myXferto_n_3,
      \stateOp_reg[0]_2\ => \stateOp[5]_i_8_n_0\,
      \stateOp_reg[0]_3\ => \stateOp[5]_i_17_n_0\,
      \stateOp_reg[0]_4\ => \stateOp[5]_i_3_n_0\,
      \stateOp_reg[0]_5\ => \stateOp[5]_i_7_n_0\,
      \stateOp_reg[0]_6\ => myCrc_n_292,
      \stateOp_reg[0]_7\ => myCrc_n_290,
      \stateOp_reg[0]_8\(1) => myXferto_n_0,
      \stateOp_reg[0]_8\(0) => myXferto_n_1,
      \stateOp_reg[0]_9\(1) => myWordto_n_0,
      \stateOp_reg[0]_9\(0) => myWordto_n_1,
      \stateOp_reg[1]\(0) => myRxtx_n_237,
      \stateOp_reg[1]_0\(0) => myRxtx_n_238,
      \stateOp_reg[1]_1\(0) => myRxtx_n_239,
      \stateOp_reg[1]_10\ => \stateOp[1]_i_2__4_n_0\,
      \stateOp_reg[1]_11\ => \stateOp[1]_i_3__4_n_0\,
      \stateOp_reg[1]_12\ => \stateOp[1]_i_5__1_n_0\,
      \stateOp_reg[1]_13\ => \stateOp[1]_i_9__0_n_0\,
      \stateOp_reg[1]_2\(0) => myRxtx_n_240,
      \stateOp_reg[1]_3\(0) => myRxtx_n_241,
      \stateOp_reg[1]_4\(0) => myRxtx_n_242,
      \stateOp_reg[1]_5\(0) => myRxtx_n_243,
      \stateOp_reg[1]_6\(0) => myRxtx_n_244,
      \stateOp_reg[1]_7\(0) => myRxtx_n_245,
      \stateOp_reg[1]_8\(0) => myRxtx_n_246,
      \stateOp_reg[1]_9\(45) => myRxtx_n_278,
      \stateOp_reg[1]_9\(44) => myRxtx_n_279,
      \stateOp_reg[1]_9\(43) => myRxtx_n_280,
      \stateOp_reg[1]_9\(42) => myRxtx_n_281,
      \stateOp_reg[1]_9\(41) => myRxtx_n_282,
      \stateOp_reg[1]_9\(40) => myRxtx_n_283,
      \stateOp_reg[1]_9\(39) => myRxtx_n_284,
      \stateOp_reg[1]_9\(38) => myRxtx_n_285,
      \stateOp_reg[1]_9\(37) => myRxtx_n_286,
      \stateOp_reg[1]_9\(36) => myRxtx_n_287,
      \stateOp_reg[1]_9\(35) => myRxtx_n_288,
      \stateOp_reg[1]_9\(34) => myRxtx_n_289,
      \stateOp_reg[1]_9\(33) => myRxtx_n_290,
      \stateOp_reg[1]_9\(32) => myRxtx_n_291,
      \stateOp_reg[1]_9\(31) => myRxtx_n_292,
      \stateOp_reg[1]_9\(30) => myRxtx_n_293,
      \stateOp_reg[1]_9\(29) => myRxtx_n_294,
      \stateOp_reg[1]_9\(28) => myRxtx_n_295,
      \stateOp_reg[1]_9\(27) => myRxtx_n_296,
      \stateOp_reg[1]_9\(26) => myRxtx_n_297,
      \stateOp_reg[1]_9\(25) => myRxtx_n_298,
      \stateOp_reg[1]_9\(24) => myRxtx_n_299,
      \stateOp_reg[1]_9\(23) => myRxtx_n_300,
      \stateOp_reg[1]_9\(22) => myRxtx_n_301,
      \stateOp_reg[1]_9\(21) => myRxtx_n_302,
      \stateOp_reg[1]_9\(20) => myRxtx_n_303,
      \stateOp_reg[1]_9\(19) => myRxtx_n_304,
      \stateOp_reg[1]_9\(18) => myRxtx_n_305,
      \stateOp_reg[1]_9\(17) => myRxtx_n_306,
      \stateOp_reg[1]_9\(16) => myRxtx_n_307,
      \stateOp_reg[1]_9\(15) => myRxtx_n_308,
      \stateOp_reg[1]_9\(14) => myRxtx_n_309,
      \stateOp_reg[1]_9\(13) => myRxtx_n_310,
      \stateOp_reg[1]_9\(12) => myRxtx_n_311,
      \stateOp_reg[1]_9\(11) => myRxtx_n_312,
      \stateOp_reg[1]_9\(10) => myRxtx_n_313,
      \stateOp_reg[1]_9\(9) => myRxtx_n_314,
      \stateOp_reg[1]_9\(8) => myRxtx_n_315,
      \stateOp_reg[1]_9\(7) => myRxtx_n_316,
      \stateOp_reg[1]_9\(6) => myRxtx_n_317,
      \stateOp_reg[1]_9\(5) => myRxtx_n_318,
      \stateOp_reg[1]_9\(4) => myRxtx_n_319,
      \stateOp_reg[1]_9\(3) => myRxtx_n_320,
      \stateOp_reg[1]_9\(2) => myRxtx_n_321,
      \stateOp_reg[1]_9\(1) => myRxtx_n_322,
      \stateOp_reg[1]_9\(0) => myRxtx_n_323,
      \stateOp_reg[2]\(0) => myRxtx_n_38,
      \stateOp_reg[2]_0\(0) => myRxtx_n_485,
      \stateOp_reg[2]_1\ => myRxtx_n_552,
      \stateOp_reg[2]_2\ => myCrc_n_289,
      \stateOp_reg[2]_3\ => myCrc_n_291,
      \stateOp_reg[3]\(6) => myRxtx_n_47,
      \stateOp_reg[3]\(5) => myRxtx_n_48,
      \stateOp_reg[3]\(4) => myRxtx_n_49,
      \stateOp_reg[3]\(3) => myRxtx_n_50,
      \stateOp_reg[3]\(2) => myRxtx_n_51,
      \stateOp_reg[3]\(1) => myRxtx_n_52,
      \stateOp_reg[3]\(0) => myRxtx_n_53,
      \stateOp_reg[3]_0\(0) => myRxtx_n_181,
      \stateOp_reg[3]_1\ => \stateOp[3]_i_5_n_0\,
      \stateOp_reg[3]_2\ => \txlen[28]_i_4_n_0\,
      \stateOp_reg[4]\ => myRxtx_n_1,
      \stateOp_reg[4]_0\ => myRxtx_n_4,
      \stateOp_reg[4]_1\ => myRxtx_n_13,
      \stateOp_reg[4]_10\(0) => myRxtx_n_331,
      \stateOp_reg[4]_11\ => myRxtx_n_345,
      \stateOp_reg[4]_12\ => myRxtx_n_346,
      \stateOp_reg[4]_13\(24) => myRxtx_n_403,
      \stateOp_reg[4]_13\(23) => myRxtx_n_404,
      \stateOp_reg[4]_13\(22) => myRxtx_n_405,
      \stateOp_reg[4]_13\(21) => myRxtx_n_406,
      \stateOp_reg[4]_13\(20) => myRxtx_n_407,
      \stateOp_reg[4]_13\(19) => myRxtx_n_408,
      \stateOp_reg[4]_13\(18) => myRxtx_n_409,
      \stateOp_reg[4]_13\(17) => myRxtx_n_410,
      \stateOp_reg[4]_13\(16) => myRxtx_n_411,
      \stateOp_reg[4]_13\(15) => myRxtx_n_412,
      \stateOp_reg[4]_13\(14) => myRxtx_n_413,
      \stateOp_reg[4]_13\(13) => myRxtx_n_414,
      \stateOp_reg[4]_13\(12) => myRxtx_n_415,
      \stateOp_reg[4]_13\(11) => myRxtx_n_416,
      \stateOp_reg[4]_13\(10) => myRxtx_n_417,
      \stateOp_reg[4]_13\(9) => myRxtx_n_418,
      \stateOp_reg[4]_13\(8) => myRxtx_n_419,
      \stateOp_reg[4]_13\(7) => myRxtx_n_420,
      \stateOp_reg[4]_13\(6) => myRxtx_n_421,
      \stateOp_reg[4]_13\(5) => myRxtx_n_422,
      \stateOp_reg[4]_13\(4) => myRxtx_n_423,
      \stateOp_reg[4]_13\(3) => myRxtx_n_424,
      \stateOp_reg[4]_13\(2) => myRxtx_n_425,
      \stateOp_reg[4]_13\(1) => myRxtx_n_426,
      \stateOp_reg[4]_13\(0) => myRxtx_n_427,
      \stateOp_reg[4]_14\(0) => myRxtx_n_534,
      \stateOp_reg[4]_15\ => \stateOp[4]_i_4_n_0\,
      \stateOp_reg[4]_16\ => \stateOp[4]_i_5_n_0\,
      \stateOp_reg[4]_2\(0) => myRxtx_n_35,
      \stateOp_reg[4]_3\ => myRxtx_n_36,
      \stateOp_reg[4]_4\ => myRxtx_n_54,
      \stateOp_reg[4]_5\(6) => myRxtx_n_129,
      \stateOp_reg[4]_5\(5) => myRxtx_n_130,
      \stateOp_reg[4]_5\(4) => myRxtx_n_131,
      \stateOp_reg[4]_5\(3) => myRxtx_n_132,
      \stateOp_reg[4]_5\(2) => myRxtx_n_133,
      \stateOp_reg[4]_5\(1) => myRxtx_n_134,
      \stateOp_reg[4]_5\(0) => myRxtx_n_135,
      \stateOp_reg[4]_6\(30) => myRxtx_n_150,
      \stateOp_reg[4]_6\(29) => myRxtx_n_151,
      \stateOp_reg[4]_6\(28) => myRxtx_n_152,
      \stateOp_reg[4]_6\(27) => myRxtx_n_153,
      \stateOp_reg[4]_6\(26) => myRxtx_n_154,
      \stateOp_reg[4]_6\(25) => myRxtx_n_155,
      \stateOp_reg[4]_6\(24) => myRxtx_n_156,
      \stateOp_reg[4]_6\(23) => myRxtx_n_157,
      \stateOp_reg[4]_6\(22) => myRxtx_n_158,
      \stateOp_reg[4]_6\(21) => myRxtx_n_159,
      \stateOp_reg[4]_6\(20) => myRxtx_n_160,
      \stateOp_reg[4]_6\(19) => myRxtx_n_161,
      \stateOp_reg[4]_6\(18) => myRxtx_n_162,
      \stateOp_reg[4]_6\(17) => myRxtx_n_163,
      \stateOp_reg[4]_6\(16) => myRxtx_n_164,
      \stateOp_reg[4]_6\(15) => myRxtx_n_165,
      \stateOp_reg[4]_6\(14) => myRxtx_n_166,
      \stateOp_reg[4]_6\(13) => myRxtx_n_167,
      \stateOp_reg[4]_6\(12) => myRxtx_n_168,
      \stateOp_reg[4]_6\(11) => myRxtx_n_169,
      \stateOp_reg[4]_6\(10) => myRxtx_n_170,
      \stateOp_reg[4]_6\(9) => myRxtx_n_171,
      \stateOp_reg[4]_6\(8) => myRxtx_n_172,
      \stateOp_reg[4]_6\(7) => myRxtx_n_173,
      \stateOp_reg[4]_6\(6) => myRxtx_n_174,
      \stateOp_reg[4]_6\(5) => myRxtx_n_175,
      \stateOp_reg[4]_6\(4) => myRxtx_n_176,
      \stateOp_reg[4]_6\(3) => myRxtx_n_177,
      \stateOp_reg[4]_6\(2) => myRxtx_n_178,
      \stateOp_reg[4]_6\(1) => myRxtx_n_179,
      \stateOp_reg[4]_6\(0) => myRxtx_n_180,
      \stateOp_reg[4]_7\(28) => myRxtx_n_206,
      \stateOp_reg[4]_7\(27) => myRxtx_n_207,
      \stateOp_reg[4]_7\(26) => myRxtx_n_208,
      \stateOp_reg[4]_7\(25) => myRxtx_n_209,
      \stateOp_reg[4]_7\(24) => myRxtx_n_210,
      \stateOp_reg[4]_7\(23) => myRxtx_n_211,
      \stateOp_reg[4]_7\(22) => myRxtx_n_212,
      \stateOp_reg[4]_7\(21) => myRxtx_n_213,
      \stateOp_reg[4]_7\(20) => myRxtx_n_214,
      \stateOp_reg[4]_7\(19) => myRxtx_n_215,
      \stateOp_reg[4]_7\(18) => myRxtx_n_216,
      \stateOp_reg[4]_7\(17) => myRxtx_n_217,
      \stateOp_reg[4]_7\(16) => myRxtx_n_218,
      \stateOp_reg[4]_7\(15) => myRxtx_n_219,
      \stateOp_reg[4]_7\(14) => myRxtx_n_220,
      \stateOp_reg[4]_7\(13) => myRxtx_n_221,
      \stateOp_reg[4]_7\(12) => myRxtx_n_222,
      \stateOp_reg[4]_7\(11) => myRxtx_n_223,
      \stateOp_reg[4]_7\(10) => myRxtx_n_224,
      \stateOp_reg[4]_7\(9) => myRxtx_n_225,
      \stateOp_reg[4]_7\(8) => myRxtx_n_226,
      \stateOp_reg[4]_7\(7) => myRxtx_n_227,
      \stateOp_reg[4]_7\(6) => myRxtx_n_228,
      \stateOp_reg[4]_7\(5) => myRxtx_n_229,
      \stateOp_reg[4]_7\(4) => myRxtx_n_230,
      \stateOp_reg[4]_7\(3) => myRxtx_n_231,
      \stateOp_reg[4]_7\(2) => myRxtx_n_232,
      \stateOp_reg[4]_7\(1) => myRxtx_n_233,
      \stateOp_reg[4]_7\(0) => myRxtx_n_234,
      \stateOp_reg[4]_8\(0) => myRxtx_n_235,
      \stateOp_reg[4]_9\(0) => myRxtx_n_236,
      \stateOp_reg[5]\(0) => myRxtx_n_3,
      \stateOp_reg[5]_0\(0) => myRxtx_n_22,
      \stateOp_reg[5]_1\(0) => myRxtx_n_23,
      \stateOp_reg[5]_2\(0) => myRxtx_n_26,
      \stateOp_reg[5]_3\(2) => myRxtx_n_147,
      \stateOp_reg[5]_3\(1) => myRxtx_n_148,
      \stateOp_reg[5]_3\(0) => myRxtx_n_149,
      \stateOp_reg[5]_4\(4) => myRxtx_n_183,
      \stateOp_reg[5]_4\(3) => myRxtx_n_184,
      \stateOp_reg[5]_4\(2) => myRxtx_n_185,
      \stateOp_reg[5]_4\(1) => myRxtx_n_186,
      \stateOp_reg[5]_4\(0) => myRxtx_n_187,
      \stateOp_reg[5]_5\(0) => myRxtx_n_188,
      \stateOp_reg[5]_6\ => myRxtx_n_484,
      \stateOp_reg[5]_7\ => myRxtx_n_553,
      \stateRecv_reg[0]_0\ => myRxtx_n_2,
      \stateRecv_reg[0]_1\ => myRxtx_n_536,
      \stateRecv_reg[1]_0\(0) => myRxtx_n_25,
      \stateSend_reg[2]_0\(0) => myRxtx_n_182,
      \stateSend_reg[2]_1\(0) => myRxtx_n_205,
      \tixVBuffer_reg[1]\(2) => myRxtx_n_324,
      \tixVBuffer_reg[1]\(1) => myRxtx_n_325,
      \tixVBuffer_reg[1]\(0) => myRxtx_n_326,
      \tixVBuffer_reg[7]\(7) => \opbuf_reg_n_0_[0][7]\,
      \tixVBuffer_reg[7]\(6) => \opbuf_reg_n_0_[0][6]\,
      \tixVBuffer_reg[7]\(5) => \opbuf_reg_n_0_[0][5]\,
      \tixVBuffer_reg[7]\(4) => \opbuf_reg_n_0_[0][4]\,
      \tixVBuffer_reg[7]\(3) => \opbuf_reg_n_0_[0][3]\,
      \tixVBuffer_reg[7]\(2) => \opbuf_reg_n_0_[0][2]\,
      \tixVBuffer_reg[7]\(1) => \opbuf_reg_n_0_[0][1]\,
      \tixVBuffer_reg[7]\(0) => \opbuf_reg_n_0_[0][0]\,
      \tixVBufxfop_reg[7]\(7) => \opbuf_reg_n_0_[2][7]\,
      \tixVBufxfop_reg[7]\(6) => \opbuf_reg_n_0_[2][6]\,
      \tixVBufxfop_reg[7]\(5) => \opbuf_reg_n_0_[2][5]\,
      \tixVBufxfop_reg[7]\(4) => \opbuf_reg_n_0_[2][4]\,
      \tixVBufxfop_reg[7]\(3) => \opbuf_reg_n_0_[2][3]\,
      \tixVBufxfop_reg[7]\(2) => \opbuf_reg_n_0_[2][2]\,
      \tixVBufxfop_reg[7]\(1) => \opbuf_reg_n_0_[2][1]\,
      \tixVBufxfop_reg[7]\(0) => \opbuf_reg_n_0_[2][0]\,
      \tixVCommand_reg[0]\(5) => myRxtx_n_58,
      \tixVCommand_reg[0]\(4) => myRxtx_n_59,
      \tixVCommand_reg[0]\(3) => myRxtx_n_60,
      \tixVCommand_reg[0]\(2) => myRxtx_n_61,
      \tixVCommand_reg[0]\(1) => myRxtx_n_62,
      \tixVCommand_reg[0]\(0) => myRxtx_n_63,
      \tixVCommand_reg[0]_0\(5) => myRxtx_n_136,
      \tixVCommand_reg[0]_0\(4) => myRxtx_n_137,
      \tixVCommand_reg[0]_0\(3) => myRxtx_n_138,
      \tixVCommand_reg[0]_0\(2) => myRxtx_n_139,
      \tixVCommand_reg[0]_0\(1) => myRxtx_n_140,
      \tixVCommand_reg[0]_0\(0) => myRxtx_n_141,
      \tixVCommand_reg[7]\(7) => myRxtx_n_197,
      \tixVCommand_reg[7]\(6) => myRxtx_n_198,
      \tixVCommand_reg[7]\(5) => myRxtx_n_199,
      \tixVCommand_reg[7]\(4) => myRxtx_n_200,
      \tixVCommand_reg[7]\(3) => myRxtx_n_201,
      \tixVCommand_reg[7]\(2) => myRxtx_n_202,
      \tixVCommand_reg[7]\(1) => myRxtx_n_203,
      \tixVCommand_reg[7]\(0) => myRxtx_n_204,
      \tixVController_reg[3]\ => myRxtx_n_400,
      \tixVController_reg[3]_0\ => myRxtx_n_401,
      \tixVController_reg[7]\(7) => myRxtx_n_189,
      \tixVController_reg[7]\(6) => myRxtx_n_190,
      \tixVController_reg[7]\(5) => myRxtx_n_191,
      \tixVController_reg[7]\(4) => myRxtx_n_192,
      \tixVController_reg[7]\(3) => myRxtx_n_193,
      \tixVController_reg[7]\(2) => myRxtx_n_194,
      \tixVController_reg[7]\(1) => myRxtx_n_195,
      \tixVController_reg[7]\(0) => myRxtx_n_196,
      \tixVController_reg[7]_0\ => myRxtx_n_402,
      \tixVController_reg[7]_1\(7 downto 0) => \opbuf_reg[1]_60\(7 downto 0),
      \txAXIS_tdata_reg[0]\ => myCrc_n_293,
      \txAXIS_tdata_reg[0]_0\ => \txAXIS_tdata[6]_i_6__0_n_0\,
      \txAXIS_tdata_reg[0]_1\ => \txAXIS_tdata[2]_i_5_n_0\,
      \txAXIS_tdata_reg[13]\ => myRxtx_n_572,
      \txAXIS_tdata_reg[16]\ => \txAXIS_tdata[23]_i_3_n_0\,
      \txAXIS_tdata_reg[16]_0\ => \txAXIS_tdata[23]_i_4_n_0\,
      \txAXIS_tdata_reg[16]_1\ => \txAXIS_tdata[16]_i_2_n_0\,
      \txAXIS_tdata_reg[16]_2\ => myCrc_n_319,
      \txAXIS_tdata_reg[16]_3\ => \txAXIS_tdata[22]_i_4_n_0\,
      \txAXIS_tdata_reg[16]_4\ => \txAXIS_tdata[16]_i_4_n_0\,
      \txAXIS_tdata_reg[17]\ => \txAXIS_tdata[17]_i_2_n_0\,
      \txAXIS_tdata_reg[17]_0\ => myCrc_n_304,
      \txAXIS_tdata_reg[17]_1\ => \txAXIS_tdata[17]_i_4_n_0\,
      \txAXIS_tdata_reg[18]\ => \txAXIS_tdata[18]_i_2_n_0\,
      \txAXIS_tdata_reg[18]_0\ => myCrc_n_316,
      \txAXIS_tdata_reg[18]_1\ => \txAXIS_tdata[18]_i_4_n_0\,
      \txAXIS_tdata_reg[19]\ => \txAXIS_tdata[19]_i_2_n_0\,
      \txAXIS_tdata_reg[19]_0\ => myCrc_n_336,
      \txAXIS_tdata_reg[19]_1\ => \txAXIS_tdata[29]_i_3_n_0\,
      \txAXIS_tdata_reg[19]_2\ => \txAXIS_tdata[19]_i_4_n_0\,
      \txAXIS_tdata_reg[20]\ => \txAXIS_tdata[20]_i_2_n_0\,
      \txAXIS_tdata_reg[20]_0\ => myCrc_n_337,
      \txAXIS_tdata_reg[20]_1\ => \txAXIS_tdata[20]_i_4_n_0\,
      \txAXIS_tdata_reg[21]\ => \txAXIS_tdata[21]_i_2_n_0\,
      \txAXIS_tdata_reg[21]_0\ => myCrc_n_312,
      \txAXIS_tdata_reg[21]_1\ => \txAXIS_tdata[21]_i_4_n_0\,
      \txAXIS_tdata_reg[22]\ => \txAXIS_tdata[22]_i_2_n_0\,
      \txAXIS_tdata_reg[22]_0\ => myCrc_n_310,
      \txAXIS_tdata_reg[22]_1\ => \txAXIS_tdata[22]_i_5_n_0\,
      \txAXIS_tdata_reg[23]\(2) => \pollbuf_reg[2]_68\(7),
      \txAXIS_tdata_reg[23]\(1 downto 0) => \pollbuf_reg[2]_68\(4 downto 3),
      \txAXIS_tdata_reg[23]_0\ => \txAXIS_tdata[23]_i_5_n_0\,
      \txAXIS_tdata_reg[23]_1\ => myCrc_n_338,
      \txAXIS_tdata_reg[23]_2\ => \txAXIS_tdata[23]_i_7_n_0\,
      \txAXIS_tdata_reg[24]\ => \txAXIS_tdata[31]_i_3_n_0\,
      \txAXIS_tdata_reg[24]_0\ => \txAXIS_tdata[24]_i_2_n_0\,
      \txAXIS_tdata_reg[24]_1\ => myCrc_n_339,
      \txAXIS_tdata_reg[24]_2\ => \txAXIS_tdata[24]_i_4_n_0\,
      \txAXIS_tdata_reg[25]\ => \txAXIS_tdata[25]_i_2_n_0\,
      \txAXIS_tdata_reg[25]_0\ => myCrc_n_340,
      \txAXIS_tdata_reg[25]_1\ => \txAXIS_tdata[25]_i_4_n_0\,
      \txAXIS_tdata_reg[26]\ => \txAXIS_tdata[26]_i_2_n_0\,
      \txAXIS_tdata_reg[26]_0\ => myCrc_n_341,
      \txAXIS_tdata_reg[26]_1\ => \txAXIS_tdata[26]_i_4_n_0\,
      \txAXIS_tdata_reg[27]\ => \txAXIS_tdata[27]_i_2_n_0\,
      \txAXIS_tdata_reg[27]_0\ => myCrc_n_342,
      \txAXIS_tdata_reg[27]_1\ => \txAXIS_tdata[27]_i_4_n_0\,
      \txAXIS_tdata_reg[28]\ => \txAXIS_tdata[28]_i_2_n_0\,
      \txAXIS_tdata_reg[28]_0\ => myCrc_n_343,
      \txAXIS_tdata_reg[28]_1\ => \txAXIS_tdata[28]_i_4_n_0\,
      \txAXIS_tdata_reg[29]\(5 downto 0) => \pollbuf_reg[3]_69\(5 downto 0),
      \txAXIS_tdata_reg[29]_0\ => \txAXIS_tdata[29]_i_2_n_0\,
      \txAXIS_tdata_reg[29]_1\ => myCrc_n_344,
      \txAXIS_tdata_reg[29]_2\ => \txAXIS_tdata[29]_i_5_n_0\,
      \txAXIS_tdata_reg[2]\ => \txAXIS_tdata[2]_i_2_n_0\,
      \txAXIS_tdata_reg[2]_0\ => myCrc_n_320,
      \txAXIS_tdata_reg[2]_1\ => \txAXIS_tdata[2]_i_4_n_0\,
      \txAXIS_tdata_reg[30]\ => \txAXIS_tdata[30]_i_2_n_0\,
      \txAXIS_tdata_reg[30]_0\ => myCrc_n_345,
      \txAXIS_tdata_reg[30]_1\ => \txAXIS_tdata[30]_i_4_n_0\,
      \txAXIS_tdata_reg[31]\ => \txAXIS_tdata[31]_i_4_n_0\,
      \txAXIS_tdata_reg[31]_0\ => myCrc_n_346,
      \txAXIS_tdata_reg[31]_1\ => \txAXIS_tdata[31]_i_6_n_0\,
      \txAXIS_tdata_reg[32]\ => \txAXIS_tdata[39]_i_3_n_0\,
      \txAXIS_tdata_reg[32]_0\(2 downto 0) => resid(2 downto 0),
      \txAXIS_tdata_reg[32]_1\ => \txAXIS_tdata[39]_i_4_n_0\,
      \txAXIS_tdata_reg[32]_2\ => \txAXIS_tdata[32]_i_2_n_0\,
      \txAXIS_tdata_reg[32]_3\ => myCrc_n_303,
      \txAXIS_tdata_reg[33]\ => \txAXIS_tdata[33]_i_2_n_0\,
      \txAXIS_tdata_reg[33]_0\ => myCrc_n_302,
      \txAXIS_tdata_reg[34]\ => \txAXIS_tdata[34]_i_2_n_0\,
      \txAXIS_tdata_reg[34]_0\ => myCrc_n_301,
      \txAXIS_tdata_reg[35]\ => \txAXIS_tdata[35]_i_2_n_0\,
      \txAXIS_tdata_reg[35]_0\ => myCrc_n_300,
      \txAXIS_tdata_reg[36]\ => \txAXIS_tdata[36]_i_2_n_0\,
      \txAXIS_tdata_reg[36]_0\ => myCrc_n_299,
      \txAXIS_tdata_reg[37]\ => \txAXIS_tdata[37]_i_2_n_0\,
      \txAXIS_tdata_reg[37]_0\ => myCrc_n_298,
      \txAXIS_tdata_reg[38]\ => \txAXIS_tdata[38]_i_2_n_0\,
      \txAXIS_tdata_reg[38]_0\ => myCrc_n_297,
      \txAXIS_tdata_reg[39]\ => \txAXIS_tdata[39]_i_5_n_0\,
      \txAXIS_tdata_reg[39]_0\ => myCrc_n_296,
      \txAXIS_tdata_reg[40]\ => \txAXIS_tdata[47]_i_3_n_0\,
      \txAXIS_tdata_reg[48]\ => \txAXIS_tdata[55]_i_3_n_0\,
      \txAXIS_tdata_reg[48]_0\ => \txAXIS_tdata[55]_i_4_n_0\,
      \txAXIS_tdata_reg[48]_1\ => \txAXIS_tdata[55]_i_5_n_0\,
      \txAXIS_tdata_reg[48]_2\ => \txAXIS_tdata[55]_i_6_n_0\,
      \txAXIS_tdata_reg[48]_3\ => \txAXIS_tdata[48]_i_2_n_0\,
      \txAXIS_tdata_reg[48]_4\ => \txAXIS_tdata[48]_i_3_n_0\,
      \txAXIS_tdata_reg[48]_5\ => myCrc_n_318,
      \txAXIS_tdata_reg[49]\ => \txAXIS_tdata[49]_i_2_n_0\,
      \txAXIS_tdata_reg[49]_0\ => \txAXIS_tdata[49]_i_3_n_0\,
      \txAXIS_tdata_reg[49]_1\ => myCrc_n_317,
      \txAXIS_tdata_reg[4]\ => \txAXIS_tdata[4]_i_2_n_0\,
      \txAXIS_tdata_reg[4]_0\ => \txAXIS_tdata[6]_i_3_n_0\,
      \txAXIS_tdata_reg[4]_1\ => myCrc_n_321,
      \txAXIS_tdata_reg[4]_2\ => \txAXIS_tdata[4]_i_4_n_0\,
      \txAXIS_tdata_reg[50]\ => \txAXIS_tdata[50]_i_2_n_0\,
      \txAXIS_tdata_reg[50]_0\ => \txAXIS_tdata[50]_i_3_n_0\,
      \txAXIS_tdata_reg[50]_1\ => myCrc_n_315,
      \txAXIS_tdata_reg[51]\ => \txAXIS_tdata[51]_i_2_n_0\,
      \txAXIS_tdata_reg[51]_0\ => \txAXIS_tdata[51]_i_3_n_0\,
      \txAXIS_tdata_reg[51]_1\ => myCrc_n_314,
      \txAXIS_tdata_reg[52]\ => \txAXIS_tdata[52]_i_2_n_0\,
      \txAXIS_tdata_reg[52]_0\ => \txAXIS_tdata[52]_i_3_n_0\,
      \txAXIS_tdata_reg[52]_1\ => myCrc_n_313,
      \txAXIS_tdata_reg[53]\ => \txAXIS_tdata[53]_i_2_n_0\,
      \txAXIS_tdata_reg[53]_0\ => \txAXIS_tdata[53]_i_3_n_0\,
      \txAXIS_tdata_reg[53]_1\ => myCrc_n_311,
      \txAXIS_tdata_reg[54]\ => \txAXIS_tdata[54]_i_2_n_0\,
      \txAXIS_tdata_reg[54]_0\ => \txAXIS_tdata[54]_i_3_n_0\,
      \txAXIS_tdata_reg[54]_1\ => myCrc_n_309,
      \txAXIS_tdata_reg[55]\ => \txAXIS_tdata[55]_i_7_n_0\,
      \txAXIS_tdata_reg[55]_0\ => \txAXIS_tdata[55]_i_8_n_0\,
      \txAXIS_tdata_reg[55]_1\ => myCrc_n_308,
      \txAXIS_tdata_reg[56]\ => \txAXIS_tdata[63]_i_3_n_0\,
      \txAXIS_tdata_reg[56]_0\ => \txAXIS_tdata[63]_i_4_n_0\,
      \txAXIS_tdata_reg[56]_1\ => \txAXIS_tdata[63]_i_5_n_0\,
      \txAXIS_tdata_reg[56]_2\ => myCrc_n_335,
      \txAXIS_tdata_reg[56]_3\ => \txAXIS_tdata[56]_i_3_n_0\,
      \txAXIS_tdata_reg[56]_4\ => \txAXIS_tdata[56]_i_4_n_0\,
      \txAXIS_tdata_reg[57]\ => myCrc_n_334,
      \txAXIS_tdata_reg[57]_0\ => \txAXIS_tdata[57]_i_3_n_0\,
      \txAXIS_tdata_reg[57]_1\ => \txAXIS_tdata[57]_i_4_n_0\,
      \txAXIS_tdata_reg[58]\ => \txAXIS_tdata[58]_i_2_n_0\,
      \txAXIS_tdata_reg[58]_0\ => myCrc_n_307,
      \txAXIS_tdata_reg[59]\ => \txAXIS_tdata[59]_i_2_n_0\,
      \txAXIS_tdata_reg[59]_0\ => myCrc_n_306,
      \txAXIS_tdata_reg[5]\ => myCrc_n_295,
      \txAXIS_tdata_reg[5]_0\ => \txAXIS_tdata[5]_i_3_n_0\,
      \txAXIS_tdata_reg[5]_1\ => \txAXIS_tdata_reg[5]_i_4_n_0\,
      \txAXIS_tdata_reg[5]_2\ => \txAXIS_tdata[5]_i_5_n_0\,
      \txAXIS_tdata_reg[5]_3\ => \txAXIS_tdata[7]_i_8_n_0\,
      \txAXIS_tdata_reg[60]\ => myCrc_n_333,
      \txAXIS_tdata_reg[60]_0\ => \txAXIS_tdata[60]_i_3_n_0\,
      \txAXIS_tdata_reg[60]_1\ => \txAXIS_tdata[60]_i_4_n_0\,
      \txAXIS_tdata_reg[61]\ => myCrc_n_332,
      \txAXIS_tdata_reg[61]_0\ => \txAXIS_tdata[61]_i_3_n_0\,
      \txAXIS_tdata_reg[61]_1\ => \txAXIS_tdata[61]_i_4_n_0\,
      \txAXIS_tdata_reg[62]\ => \txAXIS_tdata[62]_i_2_n_0\,
      \txAXIS_tdata_reg[62]_0\ => myCrc_n_305,
      \txAXIS_tdata_reg[63]\ => myCrc_n_331,
      \txAXIS_tdata_reg[63]_0\ => \txAXIS_tdata[63]_i_7_n_0\,
      \txAXIS_tdata_reg[63]_1\ => \txAXIS_tdata[63]_i_8_n_0\,
      \txAXIS_tdata_reg[6]\ => \txAXIS_tdata[6]_i_2_n_0\,
      \txAXIS_tdata_reg[6]_0\ => myCrc_n_322,
      \txAXIS_tdata_reg[6]_1\ => \txAXIS_tdata[6]_i_5_n_0\,
      \txAXIS_tdata_reg[7]\ => myRxtx_n_598,
      \txAXIS_tdata_reg[7]_0\ => myCrc_n_294,
      \txAXIS_tdata_reg[7]_1\ => \txAXIS_tdata[7]_i_7_n_0\,
      \txAXIS_tdata_reg[8]\ => \txAXIS_tdata[15]_i_3_n_0\,
      \txAXIS_tdata_reg[8]_0\ => \txAXIS_tdata[15]_i_4_n_0\,
      \txAXIS_tdata_reg[8]_1\ => \txAXIS_tdata[15]_i_5_n_0\,
      txlast1(29 downto 0) => txlast1(30 downto 1),
      \txlen_reg[0]\ => \txlen[0]_i_2_n_0\,
      vidtrackGetInfoPtr0Seqbuf(0) => vidtrackGetInfoPtr0Seqbuf(5),
      vidtrackGetInfoTixVState(0) => vidtrackGetInfoTixVState(0),
      \wordcntCrcLast_reg[0]\ => \wordcntCrcLast[0]_i_2_n_0\,
      \wordcntCrcLast_reg[16]\(7) => \wordcntCrcLast_reg[16]_i_2_n_8\,
      \wordcntCrcLast_reg[16]\(6) => \wordcntCrcLast_reg[16]_i_2_n_9\,
      \wordcntCrcLast_reg[16]\(5) => \wordcntCrcLast_reg[16]_i_2_n_10\,
      \wordcntCrcLast_reg[16]\(4) => \wordcntCrcLast_reg[16]_i_2_n_11\,
      \wordcntCrcLast_reg[16]\(3) => \wordcntCrcLast_reg[16]_i_2_n_12\,
      \wordcntCrcLast_reg[16]\(2) => \wordcntCrcLast_reg[16]_i_2_n_13\,
      \wordcntCrcLast_reg[16]\(1) => \wordcntCrcLast_reg[16]_i_2_n_14\,
      \wordcntCrcLast_reg[16]\(0) => \wordcntCrcLast_reg[16]_i_2_n_15\,
      \wordcntCrcLast_reg[1]\ => \wordcntCrcLast[24]_i_4_n_0\,
      \wordcntCrcLast_reg[24]\ => \wordcntCrcLast[24]_i_3_n_0\,
      \wordcntCrcLast_reg[24]_0\(7) => \wordcntCrcLast_reg[24]_i_5_n_8\,
      \wordcntCrcLast_reg[24]_0\(6) => \wordcntCrcLast_reg[24]_i_5_n_9\,
      \wordcntCrcLast_reg[24]_0\(5) => \wordcntCrcLast_reg[24]_i_5_n_10\,
      \wordcntCrcLast_reg[24]_0\(4) => \wordcntCrcLast_reg[24]_i_5_n_11\,
      \wordcntCrcLast_reg[24]_0\(3) => \wordcntCrcLast_reg[24]_i_5_n_12\,
      \wordcntCrcLast_reg[24]_0\(2) => \wordcntCrcLast_reg[24]_i_5_n_13\,
      \wordcntCrcLast_reg[24]_0\(1) => \wordcntCrcLast_reg[24]_i_5_n_14\,
      \wordcntCrcLast_reg[24]_0\(0) => \wordcntCrcLast_reg[24]_i_5_n_15\,
      \wordcntCrcLast_reg[2]\ => \wordcntLast[2]_i_2_n_0\,
      \wordcntLast_reg[0]\ => \wordcntLast[0]_i_2_n_0\,
      \wordcntLast_reg[0]_0\ => \wordcntLast[0]_i_3_n_0\,
      \wordcntLast_reg[0]_1\ => \wordcntLast[0]_i_4_n_0\,
      \wordcntLast_reg[0]_2\ => \wordcntLast[0]_i_5_n_0\,
      \wordcntLast_reg[28]\ => \wordcntLast[28]_i_5_n_0\,
      \wordcntLast_reg[28]_0\ => \wordcntLast[28]_i_3_n_0\,
      \wordcntLast_reg[28]_1\ => \wordcntLast[28]_i_4_n_0\,
      \wordcntLast_reg[3]\ => \wordcntLast[28]_i_6_n_0\,
      \wordcnt_reg[0]_0\(0) => \opbuf_reg[0]51_in\(6),
      \wordcnt_reg[0]_1\ => \wordcnt[30]_i_6_n_0\,
      \wordcnt_reg[0]_2\ => \wordcnt[30]_i_7_n_0\,
      \wordcnt_reg[0]_3\ => \wordcnt[30]_i_11_n_0\,
      \wordcnt_reg[1]_0\ => \wordcnt[30]_i_9_n_0\
    );
myWordto: entity work.design_1_Vsp_core_0_0_Timeout_v1_0_56
     port map (
      Q(1) => myWordto_n_0,
      Q(0) => myWordto_n_1,
      aclk_sig => aclk_sig,
      \stateOp[1]_i_3\(5 downto 0) => \^stateop_reg[5]_0\(5 downto 0),
      \stateOp_reg[0]_0\(0) => \stateOp_reg[1]_6\(0),
      \stateOp_reg[0]_1\ => myRxtx_n_536,
      \stateOp_reg[2]\ => myWordto_n_2,
      tkclk => tkclk
    );
myXferto: entity work.\design_1_Vsp_core_0_0_Timeout_v1_0__parameterized1_57\
     port map (
      Q(1) => myXferto_n_0,
      Q(0) => myXferto_n_1,
      aclk_sig => aclk_sig,
      \stateOp[1]_i_3__0\(5 downto 0) => \^stateop_reg[5]_0\(5 downto 0),
      \stateOp_reg[0]_0\ => myXferto_n_2,
      \stateOp_reg[0]_1\ => myRxtx_n_535,
      \stateOp_reg[1]_0\(0) => \stateOp_reg[1]_6\(0),
      \stateOp_reg[2]\ => myXferto_n_3,
      \stateOp_reg[3]\ => myXferto_n_4,
      tkclk => tkclk
    );
\opbuf[0][7]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(13),
      I1 => \opbuf_reg[0]3\(10),
      I2 => \opbuf_reg[0]51_in\(12),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(9),
      O => \opbuf[0][7]_i_10_n_0\
    );
\opbuf[0][7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEE2E"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(30),
      I1 => \wordcnt_reg_n_0_[25]\,
      I2 => \opbuf_reg[0][7]_i_16_n_7\,
      I3 => \opbuf_reg[0]3\(27),
      I4 => \opbuf[0][7]_i_18_n_0\,
      I5 => \opbuf[0][7]_i_19_n_0\,
      O => \opbuf[0][7]_i_11_n_0\
    );
\opbuf[0][7]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(17),
      I1 => \opbuf_reg[0]3\(14),
      I2 => \opbuf_reg[0]51_in\(16),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(13),
      O => \opbuf[0][7]_i_14_n_0\
    );
\opbuf[0][7]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(19),
      I1 => \opbuf_reg[0]3\(16),
      I2 => \opbuf_reg[0]51_in\(18),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(15),
      O => \opbuf[0][7]_i_15_n_0\
    );
\opbuf[0][7]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFDDFAD8"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[25]\,
      I1 => \opbuf_reg[0]3\(25),
      I2 => \opbuf_reg[0]51_in\(28),
      I3 => \opbuf_reg[0]3\(26),
      I4 => \opbuf_reg[0]51_in\(29),
      I5 => \opbuf[0][7]_i_45_n_0\,
      O => \opbuf[0][7]_i_18_n_0\
    );
\opbuf[0][7]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFDDFAD8"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[25]\,
      I1 => \opbuf_reg[0]3\(19),
      I2 => \opbuf_reg[0]51_in\(22),
      I3 => \opbuf_reg[0]3\(20),
      I4 => \opbuf_reg[0]51_in\(23),
      I5 => \opbuf[0][7]_i_46_n_0\,
      O => \opbuf[0][7]_i_19_n_0\
    );
\opbuf[0][7]_i_20\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1D"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(6),
      I1 => \wordcnt_reg_n_0_[25]\,
      I2 => \opbuf_reg[0]5\(6),
      O => \opbuf[0][7]_i_20_n_0\
    );
\opbuf[0][7]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(14),
      I1 => \opbuf_reg[0]5\(14),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_21_n_0\
    );
\opbuf[0][7]_i_22\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(13),
      I1 => \opbuf_reg[0]5\(13),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_22_n_0\
    );
\opbuf[0][7]_i_23\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(12),
      I1 => \opbuf_reg[0]5\(12),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_23_n_0\
    );
\opbuf[0][7]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(11),
      I1 => \opbuf_reg[0]5\(11),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_24_n_0\
    );
\opbuf[0][7]_i_25\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(10),
      I1 => \opbuf_reg[0]5\(10),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_25_n_0\
    );
\opbuf[0][7]_i_26\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(9),
      I1 => \opbuf_reg[0]5\(9),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_26_n_0\
    );
\opbuf[0][7]_i_27\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \opbuf_reg[0]5\(8),
      I1 => \wordcnt_reg_n_0_[25]\,
      I2 => \opbuf_reg[0]51_in\(8),
      O => \opbuf[0][7]_i_27_n_0\
    );
\opbuf[0][7]_i_28\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(7),
      I1 => \opbuf_reg[0]5\(7),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_28_n_0\
    );
\opbuf[0][7]_i_29\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(22),
      I1 => \opbuf_reg[0]5\(22),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_29_n_0\
    );
\opbuf[0][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \opbuf[0][7]_i_6_n_0\,
      I1 => \opbuf[0][7]_i_7_n_0\,
      I2 => \opbuf[0][7]_i_8_n_0\,
      I3 => \opbuf[0][7]_i_9_n_0\,
      I4 => \opbuf[0][7]_i_10_n_0\,
      I5 => \opbuf[0][7]_i_11_n_0\,
      O => \opbuf[0][7]_i_3_n_0\
    );
\opbuf[0][7]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(21),
      I1 => \opbuf_reg[0]5\(21),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_30_n_0\
    );
\opbuf[0][7]_i_31\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(20),
      I1 => \opbuf_reg[0]5\(20),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_31_n_0\
    );
\opbuf[0][7]_i_32\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(19),
      I1 => \opbuf_reg[0]5\(19),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_32_n_0\
    );
\opbuf[0][7]_i_33\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(18),
      I1 => \opbuf_reg[0]5\(18),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_33_n_0\
    );
\opbuf[0][7]_i_34\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(17),
      I1 => \opbuf_reg[0]5\(17),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_34_n_0\
    );
\opbuf[0][7]_i_35\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(16),
      I1 => \opbuf_reg[0]5\(16),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_35_n_0\
    );
\opbuf[0][7]_i_36\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(15),
      I1 => \opbuf_reg[0]5\(15),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_36_n_0\
    );
\opbuf[0][7]_i_37\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \opbuf_reg[0]5\(30),
      I1 => \wordcnt_reg_n_0_[25]\,
      I2 => \opbuf_reg[0]51_in\(30),
      O => \opbuf[0][7]_i_37_n_0\
    );
\opbuf[0][7]_i_38\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(29),
      I1 => \opbuf_reg[0]5\(29),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_38_n_0\
    );
\opbuf[0][7]_i_39\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(28),
      I1 => \opbuf_reg[0]5\(28),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_39_n_0\
    );
\opbuf[0][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(2),
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(1),
      I3 => \^stateop_reg[5]_0\(3),
      I4 => \^stateop_reg[5]_0\(5),
      I5 => \^stateop_reg[5]_0\(4),
      O => \opbuf[0][7]_i_4_n_0\
    );
\opbuf[0][7]_i_40\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(27),
      I1 => \opbuf_reg[0]5\(27),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_40_n_0\
    );
\opbuf[0][7]_i_41\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(26),
      I1 => \opbuf_reg[0]5\(26),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_41_n_0\
    );
\opbuf[0][7]_i_42\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(25),
      I1 => \opbuf_reg[0]5\(25),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_42_n_0\
    );
\opbuf[0][7]_i_43\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(24),
      I1 => \opbuf_reg[0]5\(24),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_43_n_0\
    );
\opbuf[0][7]_i_44\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(23),
      I1 => \opbuf_reg[0]5\(23),
      I2 => \wordcnt_reg_n_0_[25]\,
      O => \opbuf[0][7]_i_44_n_0\
    );
\opbuf[0][7]_i_45\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(27),
      I1 => \opbuf_reg[0]3\(24),
      I2 => \opbuf_reg[0]51_in\(26),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(23),
      O => \opbuf[0][7]_i_45_n_0\
    );
\opbuf[0][7]_i_46\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(25),
      I1 => \opbuf_reg[0]3\(22),
      I2 => \opbuf_reg[0]51_in\(24),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(21),
      O => \opbuf[0][7]_i_46_n_0\
    );
\opbuf[0][7]_i_50\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(20),
      O => \opbuf[0][7]_i_50_n_0\
    );
\opbuf[0][7]_i_51\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(19),
      O => \opbuf[0][7]_i_51_n_0\
    );
\opbuf[0][7]_i_52\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(18),
      O => \opbuf[0][7]_i_52_n_0\
    );
\opbuf[0][7]_i_53\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(17),
      O => \opbuf[0][7]_i_53_n_0\
    );
\opbuf[0][7]_i_54\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(16),
      O => \opbuf[0][7]_i_54_n_0\
    );
\opbuf[0][7]_i_55\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(15),
      O => \opbuf[0][7]_i_55_n_0\
    );
\opbuf[0][7]_i_56\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(14),
      O => \opbuf[0][7]_i_56_n_0\
    );
\opbuf[0][7]_i_57\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(13),
      O => \opbuf[0][7]_i_57_n_0\
    );
\opbuf[0][7]_i_58\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(28),
      O => \opbuf[0][7]_i_58_n_0\
    );
\opbuf[0][7]_i_59\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(27),
      O => \opbuf[0][7]_i_59_n_0\
    );
\opbuf[0][7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFDDFAD8"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[25]\,
      I1 => \opbuf_reg[0]3\(11),
      I2 => \opbuf_reg[0]51_in\(14),
      I3 => \opbuf_reg[0]3\(12),
      I4 => \opbuf_reg[0]51_in\(15),
      I5 => \opbuf[0][7]_i_14_n_0\,
      O => \opbuf[0][7]_i_6_n_0\
    );
\opbuf[0][7]_i_60\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(26),
      O => \opbuf[0][7]_i_60_n_0\
    );
\opbuf[0][7]_i_61\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(25),
      O => \opbuf[0][7]_i_61_n_0\
    );
\opbuf[0][7]_i_62\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(24),
      O => \opbuf[0][7]_i_62_n_0\
    );
\opbuf[0][7]_i_63\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(23),
      O => \opbuf[0][7]_i_63_n_0\
    );
\opbuf[0][7]_i_64\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(22),
      O => \opbuf[0][7]_i_64_n_0\
    );
\opbuf[0][7]_i_65\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(21),
      O => \opbuf[0][7]_i_65_n_0\
    );
\opbuf[0][7]_i_66\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(30),
      O => \opbuf[0][7]_i_66_n_0\
    );
\opbuf[0][7]_i_67\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(29),
      O => \opbuf[0][7]_i_67_n_0\
    );
\opbuf[0][7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFDDFAD8"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[25]\,
      I1 => \opbuf_reg[0]3\(17),
      I2 => \opbuf_reg[0]51_in\(20),
      I3 => \opbuf_reg[0]3\(18),
      I4 => \opbuf_reg[0]51_in\(21),
      I5 => \opbuf[0][7]_i_15_n_0\,
      O => \opbuf[0][7]_i_7_n_0\
    );
\opbuf[0][7]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01000111"
    )
        port map (
      I0 => \invbuf[9][7]_i_6_n_0\,
      I1 => \invbuf[9][7]_i_16_n_0\,
      I2 => \opbuf_reg[0]3\(6),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]51_in\(9),
      O => \opbuf[0][7]_i_8_n_0\
    );
\opbuf[0][7]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(11),
      I1 => \opbuf_reg[0]3\(8),
      I2 => \opbuf_reg[0]51_in\(10),
      I3 => \wordcnt_reg_n_0_[25]\,
      I4 => \opbuf_reg[0]3\(7),
      O => \opbuf[0][7]_i_9_n_0\
    );
\opbuf_reg[0][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_12,
      Q => \opbuf_reg_n_0_[0][0]\
    );
\opbuf_reg[0][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_11,
      Q => \opbuf_reg_n_0_[0][1]\
    );
\opbuf_reg[0][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_10,
      Q => \opbuf_reg_n_0_[0][2]\
    );
\opbuf_reg[0][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_9,
      Q => \opbuf_reg_n_0_[0][3]\
    );
\opbuf_reg[0][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_8,
      Q => \opbuf_reg_n_0_[0][4]\
    );
\opbuf_reg[0][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_7,
      Q => \opbuf_reg_n_0_[0][5]\
    );
\opbuf_reg[0][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_6,
      Q => \opbuf_reg_n_0_[0][6]\
    );
\opbuf_reg[0][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_5,
      Q => \opbuf_reg_n_0_[0][7]\
    );
\opbuf_reg[0][7]_i_12\: unisim.vcomponents.CARRY8
     port map (
      CI => \opbuf[0][7]_i_20_n_0\,
      CI_TOP => '0',
      CO(7) => \opbuf_reg[0][7]_i_12_n_0\,
      CO(6) => \opbuf_reg[0][7]_i_12_n_1\,
      CO(5) => \opbuf_reg[0][7]_i_12_n_2\,
      CO(4) => \opbuf_reg[0][7]_i_12_n_3\,
      CO(3) => \opbuf_reg[0][7]_i_12_n_4\,
      CO(2) => \opbuf_reg[0][7]_i_12_n_5\,
      CO(1) => \opbuf_reg[0][7]_i_12_n_6\,
      CO(0) => \opbuf_reg[0][7]_i_12_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \opbuf_reg[0]3\(11 downto 4),
      S(7) => \opbuf[0][7]_i_21_n_0\,
      S(6) => \opbuf[0][7]_i_22_n_0\,
      S(5) => \opbuf[0][7]_i_23_n_0\,
      S(4) => \opbuf[0][7]_i_24_n_0\,
      S(3) => \opbuf[0][7]_i_25_n_0\,
      S(2) => \opbuf[0][7]_i_26_n_0\,
      S(1) => \opbuf[0][7]_i_27_n_0\,
      S(0) => \opbuf[0][7]_i_28_n_0\
    );
\opbuf_reg[0][7]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => \opbuf_reg[0][7]_i_12_n_0\,
      CI_TOP => '0',
      CO(7) => \opbuf_reg[0][7]_i_13_n_0\,
      CO(6) => \opbuf_reg[0][7]_i_13_n_1\,
      CO(5) => \opbuf_reg[0][7]_i_13_n_2\,
      CO(4) => \opbuf_reg[0][7]_i_13_n_3\,
      CO(3) => \opbuf_reg[0][7]_i_13_n_4\,
      CO(2) => \opbuf_reg[0][7]_i_13_n_5\,
      CO(1) => \opbuf_reg[0][7]_i_13_n_6\,
      CO(0) => \opbuf_reg[0][7]_i_13_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \opbuf_reg[0]3\(19 downto 12),
      S(7) => \opbuf[0][7]_i_29_n_0\,
      S(6) => \opbuf[0][7]_i_30_n_0\,
      S(5) => \opbuf[0][7]_i_31_n_0\,
      S(4) => \opbuf[0][7]_i_32_n_0\,
      S(3) => \opbuf[0][7]_i_33_n_0\,
      S(2) => \opbuf[0][7]_i_34_n_0\,
      S(1) => \opbuf[0][7]_i_35_n_0\,
      S(0) => \opbuf[0][7]_i_36_n_0\
    );
\opbuf_reg[0][7]_i_16\: unisim.vcomponents.CARRY8
     port map (
      CI => \opbuf_reg[0][7]_i_17_n_0\,
      CI_TOP => '0',
      CO(7 downto 1) => \NLW_opbuf_reg[0][7]_i_16_CO_UNCONNECTED\(7 downto 1),
      CO(0) => \opbuf_reg[0][7]_i_16_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_opbuf_reg[0][7]_i_16_O_UNCONNECTED\(7 downto 0),
      S(7 downto 0) => B"00000001"
    );
\opbuf_reg[0][7]_i_17\: unisim.vcomponents.CARRY8
     port map (
      CI => \opbuf_reg[0][7]_i_13_n_0\,
      CI_TOP => '0',
      CO(7) => \opbuf_reg[0][7]_i_17_n_0\,
      CO(6) => \opbuf_reg[0][7]_i_17_n_1\,
      CO(5) => \opbuf_reg[0][7]_i_17_n_2\,
      CO(4) => \opbuf_reg[0][7]_i_17_n_3\,
      CO(3) => \opbuf_reg[0][7]_i_17_n_4\,
      CO(2) => \opbuf_reg[0][7]_i_17_n_5\,
      CO(1) => \opbuf_reg[0][7]_i_17_n_6\,
      CO(0) => \opbuf_reg[0][7]_i_17_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \opbuf_reg[0]3\(27 downto 20),
      S(7) => \opbuf[0][7]_i_37_n_0\,
      S(6) => \opbuf[0][7]_i_38_n_0\,
      S(5) => \opbuf[0][7]_i_39_n_0\,
      S(4) => \opbuf[0][7]_i_40_n_0\,
      S(3) => \opbuf[0][7]_i_41_n_0\,
      S(2) => \opbuf[0][7]_i_42_n_0\,
      S(1) => \opbuf[0][7]_i_43_n_0\,
      S(0) => \opbuf[0][7]_i_44_n_0\
    );
\opbuf_reg[0][7]_i_47\: unisim.vcomponents.CARRY8
     port map (
      CI => \invbuf_reg[9][7]_i_12_n_0\,
      CI_TOP => '0',
      CO(7) => \opbuf_reg[0][7]_i_47_n_0\,
      CO(6) => \opbuf_reg[0][7]_i_47_n_1\,
      CO(5) => \opbuf_reg[0][7]_i_47_n_2\,
      CO(4) => \opbuf_reg[0][7]_i_47_n_3\,
      CO(3) => \opbuf_reg[0][7]_i_47_n_4\,
      CO(2) => \opbuf_reg[0][7]_i_47_n_5\,
      CO(1) => \opbuf_reg[0][7]_i_47_n_6\,
      CO(0) => \opbuf_reg[0][7]_i_47_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \opbuf_reg[0]5\(20 downto 13),
      S(7) => \opbuf[0][7]_i_50_n_0\,
      S(6) => \opbuf[0][7]_i_51_n_0\,
      S(5) => \opbuf[0][7]_i_52_n_0\,
      S(4) => \opbuf[0][7]_i_53_n_0\,
      S(3) => \opbuf[0][7]_i_54_n_0\,
      S(2) => \opbuf[0][7]_i_55_n_0\,
      S(1) => \opbuf[0][7]_i_56_n_0\,
      S(0) => \opbuf[0][7]_i_57_n_0\
    );
\opbuf_reg[0][7]_i_48\: unisim.vcomponents.CARRY8
     port map (
      CI => \opbuf_reg[0][7]_i_47_n_0\,
      CI_TOP => '0',
      CO(7) => \opbuf_reg[0][7]_i_48_n_0\,
      CO(6) => \opbuf_reg[0][7]_i_48_n_1\,
      CO(5) => \opbuf_reg[0][7]_i_48_n_2\,
      CO(4) => \opbuf_reg[0][7]_i_48_n_3\,
      CO(3) => \opbuf_reg[0][7]_i_48_n_4\,
      CO(2) => \opbuf_reg[0][7]_i_48_n_5\,
      CO(1) => \opbuf_reg[0][7]_i_48_n_6\,
      CO(0) => \opbuf_reg[0][7]_i_48_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \opbuf_reg[0]5\(28 downto 21),
      S(7) => \opbuf[0][7]_i_58_n_0\,
      S(6) => \opbuf[0][7]_i_59_n_0\,
      S(5) => \opbuf[0][7]_i_60_n_0\,
      S(4) => \opbuf[0][7]_i_61_n_0\,
      S(3) => \opbuf[0][7]_i_62_n_0\,
      S(2) => \opbuf[0][7]_i_63_n_0\,
      S(1) => \opbuf[0][7]_i_64_n_0\,
      S(0) => \opbuf[0][7]_i_65_n_0\
    );
\opbuf_reg[0][7]_i_49\: unisim.vcomponents.CARRY8
     port map (
      CI => \opbuf_reg[0][7]_i_48_n_0\,
      CI_TOP => '0',
      CO(7 downto 1) => \NLW_opbuf_reg[0][7]_i_49_CO_UNCONNECTED\(7 downto 1),
      CO(0) => \opbuf_reg[0][7]_i_49_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 2) => \NLW_opbuf_reg[0][7]_i_49_O_UNCONNECTED\(7 downto 2),
      O(1 downto 0) => \opbuf_reg[0]5\(30 downto 29),
      S(7 downto 2) => B"000000",
      S(1) => \opbuf[0][7]_i_66_n_0\,
      S(0) => \opbuf[0][7]_i_67_n_0\
    );
\opbuf_reg[1][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(0),
      Q => \opbuf_reg[1]_60\(0)
    );
\opbuf_reg[1][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(1),
      Q => \opbuf_reg[1]_60\(1)
    );
\opbuf_reg[1][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(2),
      Q => \opbuf_reg[1]_60\(2)
    );
\opbuf_reg[1][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(3),
      Q => \opbuf_reg[1]_60\(3)
    );
\opbuf_reg[1][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(4),
      Q => \opbuf_reg[1]_60\(4)
    );
\opbuf_reg[1][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(5),
      Q => \opbuf_reg[1]_60\(5)
    );
\opbuf_reg[1][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(6),
      Q => \opbuf_reg[1]_60\(6)
    );
\opbuf_reg[1][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[1]_75\(7),
      Q => \opbuf_reg[1]_60\(7)
    );
\opbuf_reg[2][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(0),
      Q => \opbuf_reg_n_0_[2][0]\
    );
\opbuf_reg[2][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(1),
      Q => \opbuf_reg_n_0_[2][1]\
    );
\opbuf_reg[2][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(2),
      Q => \opbuf_reg_n_0_[2][2]\
    );
\opbuf_reg[2][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(3),
      Q => \opbuf_reg_n_0_[2][3]\
    );
\opbuf_reg[2][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(4),
      Q => \opbuf_reg_n_0_[2][4]\
    );
\opbuf_reg[2][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(5),
      Q => \opbuf_reg_n_0_[2][5]\
    );
\opbuf_reg[2][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(6),
      Q => \opbuf_reg_n_0_[2][6]\
    );
\opbuf_reg[2][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[2]_72\(7),
      Q => \opbuf_reg_n_0_[2][7]\
    );
\opbuf_reg[3][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_34,
      Q => \opbuf_reg[3]_64\(0)
    );
\opbuf_reg[3][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[3]_70\(1),
      Q => \opbuf_reg[3]_64\(1)
    );
\opbuf_reg[3][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_32,
      Q => \opbuf_reg[3]_64\(2)
    );
\opbuf_reg[3][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_31,
      Q => \opbuf_reg[3]_64\(3)
    );
\opbuf_reg[3][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_30,
      Q => \opbuf_reg[3]_64\(4)
    );
\opbuf_reg[3][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_29,
      Q => \opbuf_reg[3]_64\(5)
    );
\opbuf_reg[3][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[3]_70\(6),
      Q => \opbuf_reg[3]_64\(6)
    );
\opbuf_reg[3][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_27,
      Q => \opbuf_reg[3]_64\(7)
    );
\opbuf_reg[4][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(0),
      Q => \opbuf_reg[4]_63\(0)
    );
\opbuf_reg[4][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(1),
      Q => \opbuf_reg[4]_63\(1)
    );
\opbuf_reg[4][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(2),
      Q => \opbuf_reg[4]_63\(2)
    );
\opbuf_reg[4][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(3),
      Q => \opbuf_reg[4]_63\(3)
    );
\opbuf_reg[4][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(4),
      Q => \opbuf_reg[4]_63\(4)
    );
\opbuf_reg[4][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(5),
      Q => \opbuf_reg[4]_63\(5)
    );
\opbuf_reg[4][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(6),
      Q => \opbuf_reg[4]_63\(6)
    );
\opbuf_reg[4][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[4]_73\(7),
      Q => \opbuf_reg[4]_63\(7)
    );
\opbuf_reg[5][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(0),
      Q => \opbuf_reg[5]_62\(0)
    );
\opbuf_reg[5][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(1),
      Q => \opbuf_reg[5]_62\(1)
    );
\opbuf_reg[5][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(2),
      Q => \opbuf_reg[5]_62\(2)
    );
\opbuf_reg[5][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(3),
      Q => \opbuf_reg[5]_62\(3)
    );
\opbuf_reg[5][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(4),
      Q => \opbuf_reg[5]_62\(4)
    );
\opbuf_reg[5][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(5),
      Q => \opbuf_reg[5]_62\(5)
    );
\opbuf_reg[5][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(6),
      Q => \opbuf_reg[5]_62\(6)
    );
\opbuf_reg[5][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[5]_71\(7),
      Q => \opbuf_reg[5]_62\(7)
    );
\opbuf_reg[6][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[6]_74\(0),
      Q => \opbuf_reg[6]_61\(0)
    );
\opbuf_reg[6][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[6]_74\(1),
      Q => \opbuf_reg[6]_61\(1)
    );
\opbuf_reg[6][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[6]_74\(2),
      Q => \opbuf_reg[6]_61\(2)
    );
\opbuf_reg[6][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[6]_74\(3),
      Q => \opbuf_reg[6]_61\(3)
    );
\opbuf_reg[6][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[6]_74\(4),
      Q => \opbuf_reg[6]_61\(4)
    );
\opbuf_reg[6][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[6]_74\(5),
      Q => \opbuf_reg[6]_61\(5)
    );
\opbuf_reg[6][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[6]_74\(6),
      Q => \opbuf_reg[6]_61\(6)
    );
\opbuf_reg[6][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_25,
      CLR => \stateOp_reg[1]_6\(0),
      D => \opbuf[6]_74\(7),
      Q => \opbuf_reg[6]_61\(7)
    );
\pollbuf[0][7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEAAAF"
    )
        port map (
      I0 => \pollbuf[0][7]_i_7_n_0\,
      I1 => \tixVBuffer_reg_n_0_[0]\,
      I2 => \tixVBuffer_reg_n_0_[2]\,
      I3 => \tixVBuffer_reg_n_0_[1]\,
      I4 => \tixVBuffer_reg_n_0_[3]\,
      O => \pollbuf[0][7]_i_3_n_0\
    );
\pollbuf[0][7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[0]\,
      I1 => \tixVBuffer_reg_n_0_[1]\,
      I2 => \pollbuf[0][7]_i_7_n_0\,
      I3 => \tixVBuffer_reg_n_0_[2]\,
      I4 => \tixVBuffer_reg_n_0_[3]\,
      O => \pollbuf[0][7]_i_4_n_0\
    );
\pollbuf[0][7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(5),
      I2 => \^stateop_reg[5]_0\(3),
      I3 => \^stateop_reg[5]_0\(1),
      O => \pollbuf[0][7]_i_5_n_0\
    );
\pollbuf[0][7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000001010001"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[0]\,
      I1 => \tixVBuffer_reg_n_0_[1]\,
      I2 => \tixVBuffer_reg_n_0_[2]\,
      I3 => \tixVBuffer_reg_n_0_[3]\,
      I4 => p_0_in0,
      I5 => \tixVBuffer_reg_n_0_[5]\,
      O => \pollbuf[0][7]_i_6_n_0\
    );
\pollbuf[0][7]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => p_0_in0,
      I1 => \tixVBuffer_reg_n_0_[5]\,
      I2 => \tixVBuffer_reg_n_0_[6]\,
      I3 => \tixVBuffer_reg_n_0_[7]\,
      O => \pollbuf[0][7]_i_7_n_0\
    );
\pollbuf[2][3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFEFFFFF"
    )
        port map (
      I0 => \pollbuf[0][7]_i_7_n_0\,
      I1 => \tixVBuffer_reg_n_0_[1]\,
      I2 => \pollbuf_reg[2][7]_0\(1),
      I3 => \tixVBuffer_reg_n_0_[0]\,
      I4 => \wordcntLast[28]_i_9_n_0\,
      I5 => \pollbuf[2][3]_i_3_n_0\,
      O => \pollbuf[2][3]_i_2_n_0\
    );
\pollbuf[2][3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000022200020"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[1]\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => \pollbuf[2][3]_i_2_0\(1),
      I3 => \tixVBuffer_reg_n_0_[0]\,
      I4 => \pollbuf[2][7]_i_2_0\(1),
      I5 => \wordcntLast[28]_i_19_n_0\,
      O => \pollbuf[2][3]_i_3_n_0\
    );
\pollbuf[2][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF0DDD"
    )
        port map (
      I0 => \pollbuf_reg[2][4]_0\(0),
      I1 => \wordcntLast[28]_i_10_n_0\,
      I2 => \wordcntLast[28]_i_9_n_0\,
      I3 => \pollbuf[2][4]_i_3_n_0\,
      I4 => \pollbuf[0][7]_i_7_n_0\,
      I5 => \pollbuf[2][7]_i_3_n_0\,
      O => \pollbuf[2][4]_i_2_n_0\
    );
\pollbuf[2][4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \pollbuf[2][4]_i_2_0\(0),
      I1 => \pollbuf[2][4]_i_2_1\(0),
      I2 => \tixVBuffer_reg_n_0_[1]\,
      I3 => avllenSeqbufMemtrackToHostif(0),
      I4 => \tixVBuffer_reg_n_0_[0]\,
      I5 => \pollbuf_reg[2][7]_0\(1),
      O => \pollbuf[2][4]_i_3_n_0\
    );
\pollbuf[2][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000020"
    )
        port map (
      I0 => \wordcntLast[28]_i_9_n_0\,
      I1 => \tixVBuffer_reg_n_0_[1]\,
      I2 => \pollbuf_reg[2][7]_0\(1),
      I3 => \tixVBuffer_reg_n_0_[0]\,
      I4 => \pollbuf[0][7]_i_7_n_0\,
      I5 => \pollbuf[2][7]_i_3_n_0\,
      O => \pollbuf[2][7]_i_2_n_0\
    );
\pollbuf[2][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002000"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[1]\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => \pollbuf[2][7]_i_2_0\(1),
      I3 => \tixVBuffer_reg_n_0_[0]\,
      I4 => \pollbuf[0][7]_i_7_n_0\,
      I5 => \tixVBuffer_reg_n_0_[3]\,
      O => \pollbuf[2][7]_i_3_n_0\
    );
\pollbuf_reg[0][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_196,
      Q => \pollbuf_reg[0]_66\(0)
    );
\pollbuf_reg[0][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_195,
      Q => \pollbuf_reg[0]_66\(1)
    );
\pollbuf_reg[0][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_194,
      Q => \pollbuf_reg[0]_66\(2)
    );
\pollbuf_reg[0][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_193,
      Q => \pollbuf_reg[0]_66\(3)
    );
\pollbuf_reg[0][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_192,
      Q => \pollbuf_reg[0]_66\(4)
    );
\pollbuf_reg[0][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_191,
      Q => \pollbuf_reg[0]_66\(5)
    );
\pollbuf_reg[0][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_190,
      Q => \pollbuf_reg[0]_66\(6)
    );
\pollbuf_reg[0][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_189,
      Q => \pollbuf_reg[0]_66\(7)
    );
\pollbuf_reg[1][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_204,
      Q => \pollbuf_reg[1]_67\(0)
    );
\pollbuf_reg[1][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_203,
      Q => \pollbuf_reg[1]_67\(1)
    );
\pollbuf_reg[1][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_202,
      Q => \pollbuf_reg[1]_67\(2)
    );
\pollbuf_reg[1][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_201,
      Q => \pollbuf_reg[1]_67\(3)
    );
\pollbuf_reg[1][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_200,
      Q => \pollbuf_reg[1]_67\(4)
    );
\pollbuf_reg[1][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_199,
      Q => \pollbuf_reg[1]_67\(5)
    );
\pollbuf_reg[1][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_198,
      Q => \pollbuf_reg[1]_67\(6)
    );
\pollbuf_reg[1][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_197,
      Q => \pollbuf_reg[1]_67\(7)
    );
\pollbuf_reg[2][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_326,
      Q => \pollbuf_reg[2]_68\(3)
    );
\pollbuf_reg[2][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_325,
      Q => \pollbuf_reg[2]_68\(4)
    );
\pollbuf_reg[2][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_324,
      Q => \pollbuf_reg[2]_68\(7)
    );
\pollbuf_reg[3][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_141,
      Q => \pollbuf_reg[3]_69\(0)
    );
\pollbuf_reg[3][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_140,
      Q => \pollbuf_reg[3]_69\(1)
    );
\pollbuf_reg[3][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_139,
      Q => \pollbuf_reg[3]_69\(2)
    );
\pollbuf_reg[3][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_138,
      Q => \pollbuf_reg[3]_69\(3)
    );
\pollbuf_reg[3][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_137,
      Q => \pollbuf_reg[3]_69\(4)
    );
\pollbuf_reg[3][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_38,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_136,
      Q => \pollbuf_reg[3]_69\(5)
    );
reqReset_sig_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \stateOp_i_5__1_n_0\,
      I1 => \ixRetbufCrc[4]_i_5_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \tixVController_reg_n_0_[0]\,
      I5 => \retbuf[1][7]_i_10_n_0\,
      O => reqReset_sig_i_2_n_0
    );
reqReset_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_555,
      Q => reqResetFromHostif
    );
reset_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FC88"
    )
        port map (
      I0 => reqResetFromHostif,
      I1 => stateMclk,
      I2 => reset_reg,
      I3 => \stateOp_reg[1]_6\(0),
      O => reqReset_sig_reg_0
    );
\resid[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FF10101010"
    )
        port map (
      I0 => \resid[0]_i_3_n_0\,
      I1 => \resid[2]_i_22_n_0\,
      I2 => \resid[0]_i_4_n_0\,
      I3 => \resid[0]_i_5_n_0\,
      I4 => \resid[2]_i_20_n_0\,
      I5 => \resid[0]_i_6_n_0\,
      O => \resid[0]_i_2_n_0\
    );
\resid[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => targetNotSteady_i_3_n_0,
      I1 => ackInvConfig_sig_i_7_n_0,
      O => \resid[0]_i_3_n_0\
    );
\resid[0]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \resid[2]_i_32_n_0\,
      I1 => \resid[2]_i_17_n_0\,
      O => \resid[0]_i_4_n_0\
    );
\resid[0]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^tixvcommand_reg[0]_0\,
      I1 => ackInvConfigSynth_sig_i_5_n_0,
      O => \resid[0]_i_5_n_0\
    );
\resid[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFAFAE"
    )
        port map (
      I0 => \resid[2]_i_20_n_0\,
      I1 => \stateCorecfg[2]_i_6_n_0\,
      I2 => ackInvConfigSynth_sig_i_5_n_0,
      I3 => \^tixvcommand_reg[0]_0\,
      I4 => \retbuf[7][7]_i_4_n_0\,
      I5 => \ixRetbufCrc[4]_i_2_n_0\,
      O => \resid[0]_i_6_n_0\
    );
\resid[1]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"32"
    )
        port map (
      I0 => targetNotSteady_i_3_n_0,
      I1 => ackInvConfigSynth_sig_i_5_n_0,
      I2 => \^tixvcommand_reg[0]_0\,
      O => \resid[1]_i_10_n_0\
    );
\resid[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010100"
    )
        port map (
      I0 => \stateCorecfg[2]_i_9_n_0\,
      I1 => \resid[1]_i_17_n_0\,
      I2 => \resid[1]_i_18_n_0\,
      I3 => \tixVCommand_reg_n_0_[1]\,
      I4 => \tixVCommand_reg_n_0_[0]\,
      I5 => \stateCorecfg[2]_i_8_n_0\,
      O => \resid[1]_i_11_n_0\
    );
\resid[1]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => \resid[1]_i_19_n_0\,
      I1 => \retbuf[0][0]_i_3_n_0\,
      I2 => \stateOp_i_5__1_n_0\,
      I3 => \resid[1]_i_18_n_0\,
      I4 => \tixVCommand_reg_n_0_[1]\,
      I5 => \tixVCommand_reg_n_0_[0]\,
      O => \resid[1]_i_12_n_0\
    );
\resid[1]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000D00000000"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[0]\,
      I1 => \tixVCommand_reg_n_0_[1]\,
      I2 => \resid[1]_i_18_n_0\,
      I3 => \stateOp_i_5__1_n_0\,
      I4 => \stateOp_i_4__1_n_0\,
      I5 => \resid[2]_i_25_n_0\,
      O => \resid[1]_i_13_n_0\
    );
\resid[1]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000110"
    )
        port map (
      I0 => \stateOp_i_5__1_n_0\,
      I1 => \resid[1]_i_18_n_0\,
      I2 => \tixVCommand_reg_n_0_[1]\,
      I3 => \tixVCommand_reg_n_0_[0]\,
      I4 => \resid[1]_i_20_n_0\,
      I5 => \resid[1]_i_21_n_0\,
      O => \resid[1]_i_14_n_0\
    );
\resid[1]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \retbuf[0][0]_i_3_n_0\,
      I2 => \resid[1]_i_22_n_0\,
      I3 => \stateOp_i_5__1_n_0\,
      I4 => \ixRetbufCrc[4]_i_5_n_0\,
      I5 => \tixVCommand_reg_n_0_[0]\,
      O => \resid[1]_i_15_n_0\
    );
\resid[1]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEFFFFF"
    )
        port map (
      I0 => \resid[1]_i_19_n_0\,
      I1 => \retbuf[0][0]_i_3_n_0\,
      I2 => \tixVCommand_reg_n_0_[1]\,
      I3 => \resid[1]_i_18_n_0\,
      I4 => \tixVCommand_reg_n_0_[0]\,
      I5 => \stateOp_i_5__1_n_0\,
      O => \resid[1]_i_16_n_0\
    );
\resid[1]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \tixVController_reg_n_0_[0]\,
      O => \resid[1]_i_17_n_0\
    );
\resid[1]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[5]\,
      I1 => \tixVCommand_reg_n_0_[4]\,
      O => \resid[1]_i_18_n_0\
    );
\resid[1]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFBFF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[4]\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[3]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \tixVController_reg_n_0_[0]\,
      O => \resid[1]_i_19_n_0\
    );
\resid[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \resid[1]_i_5_n_0\,
      I1 => \resid[2]_i_9_n_0\,
      I2 => \resid[2]_i_5_n_0\,
      I3 => \resid[1]_i_6_n_0\,
      I4 => \resid[1]_i_7_n_0\,
      I5 => \resid[1]_i_8_n_0\,
      O => \resid[1]_i_2_n_0\
    );
\resid[1]_i_20\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[1]\,
      O => \resid[1]_i_20_n_0\
    );
\resid[1]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFBFFFFFFFF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \tixVController_reg_n_0_[4]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \tixVController_reg_n_0_[5]\,
      I4 => \tixVController_reg_n_0_[6]\,
      I5 => \tixVController_reg_n_0_[2]\,
      O => \resid[1]_i_21_n_0\
    );
\resid[1]_i_22\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \tixVController_reg_n_0_[1]\,
      O => \resid[1]_i_22_n_0\
    );
\resid[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000020000"
    )
        port map (
      I0 => \resid[1]_i_9_n_0\,
      I1 => \resid[1]_i_10_n_0\,
      I2 => \resid[1]_i_11_n_0\,
      I3 => \wordcntLast[0]_i_5_n_0\,
      I4 => \resid[1]_i_12_n_0\,
      I5 => \resid[1]_i_13_n_0\,
      O => \resid[1]_i_3_n_0\
    );
\resid[1]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \resid[0]_i_2_n_0\,
      I1 => \resid[2]_i_8_n_0\,
      O => \resid[1]_i_4_n_0\
    );
\resid[1]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBBFFB0"
    )
        port map (
      I0 => \staTixVTrigger[7]_i_5_n_0\,
      I1 => \resid[2]_i_28_n_0\,
      I2 => \i2cRegaddr[15]_i_11_n_0\,
      I3 => \resid[1]_i_14_n_0\,
      I4 => \^tixvcommand_reg[0]_0\,
      O => \resid[1]_i_5_n_0\
    );
\resid[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFB"
    )
        port map (
      I0 => \stateOp_i_4__1_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \stateOp_i_5__1_n_0\,
      I3 => \ixRetbufCrc[4]_i_5_n_0\,
      I4 => \tixVCommand_reg_n_0_[0]\,
      I5 => \tixVController_reg_n_0_[1]\,
      O => \resid[1]_i_6_n_0\
    );
\resid[1]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \^tixvcommand_reg[0]_0\,
      I1 => ackInvSet_sig_i_9_n_0,
      I2 => ackInvConfig_sig_i_7_n_0,
      I3 => \stateOp_i_3__1_n_0\,
      O => \resid[1]_i_7_n_0\
    );
\resid[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBBFFBBFB"
    )
        port map (
      I0 => \resid[1]_i_15_n_0\,
      I1 => \resid[1]_i_16_n_0\,
      I2 => \stateOp_i_3__1_n_0\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => targetNotSteady_i_3_n_0,
      I5 => \resid[2]_i_26_n_0\,
      O => \resid[1]_i_8_n_0\
    );
\resid[1]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[0]\,
      I1 => ackInvConfigSynth_sig_i_5_n_0,
      I2 => \ixRetbufCrc[5]_i_4_n_0\,
      O => \resid[1]_i_9_n_0\
    );
\resid[2]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002000"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[0]\,
      I1 => \stateOp_i_4__1_n_0\,
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \stateOp_i_5__1_n_0\,
      I5 => \ixRetbufCrc[4]_i_5_n_0\,
      O => \resid[2]_i_10_n_0\
    );
\resid[2]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => \stateOp_i_5__1_n_0\,
      I1 => \resid[2]_i_24_n_0\,
      I2 => \resid[2]_i_25_n_0\,
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \staTixVTrigger[7]_i_3__1_n_0\,
      O => \resid[2]_i_11_n_0\
    );
\resid[2]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000FFFFF000F0022"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \resid[2]_i_26_n_0\,
      I2 => ackInvConfig_sig_i_7_n_0,
      I3 => \ixRetbufCrc[5]_i_4_n_0\,
      I4 => \tixVCommand_reg_n_0_[0]\,
      I5 => \i__i_3_n_0\,
      O => \resid[2]_i_12_n_0\
    );
\resid[2]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555FFFF1010FF10"
    )
        port map (
      I0 => \resid[2]_i_27_n_0\,
      I1 => \ixRetbufCrc[5]_i_4_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      I3 => \^tixvcommand_reg[0]_0\,
      I4 => \resid[2]_i_28_n_0\,
      I5 => targetNotSteady_i_3_n_0,
      O => \resid[2]_i_13_n_0\
    );
\resid[2]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000110010"
    )
        port map (
      I0 => ackInvConfigSynth_sig_i_5_n_0,
      I1 => \tixVCommand_reg_n_0_[3]\,
      I2 => \tixVCommand_reg_n_0_[2]\,
      I3 => \resid[2]_i_29_n_0\,
      I4 => \tixVCommand_reg_n_0_[0]\,
      I5 => \ixRetbufCrc[4]_i_5_n_0\,
      O => \resid[2]_i_14_n_0\
    );
\resid[2]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44444F44"
    )
        port map (
      I0 => ackInvConfig_sig_i_7_n_0,
      I1 => targetNotSteady_i_3_n_0,
      I2 => \resid[2]_i_30_n_0\,
      I3 => \tixVCommand_reg_n_0_[0]\,
      I4 => \ixRetbufCrc[5]_i_4_n_0\,
      O => \resid[2]_i_15_n_0\
    );
\resid[2]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5F00004400000044"
    )
        port map (
      I0 => \resid[2]_i_31_n_0\,
      I1 => targetNotSteady_i_3_n_0,
      I2 => \stateOp_i_4__1_n_0\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[1]\,
      I5 => \stateOp_i_3__1_n_0\,
      O => \resid[2]_i_16_n_0\
    );
\resid[2]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000000C0040"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \ixRetbufCrc[5]_i_4_n_0\,
      I4 => \tixVCommand_reg_n_0_[0]\,
      I5 => \staTixVTrigger[7]_i_3__1_n_0\,
      O => \resid[2]_i_17_n_0\
    );
\resid[2]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => ackInvConfigSynth_sig_i_5_n_0,
      I1 => \stateCorecfg[2]_i_6_n_0\,
      I2 => \resid[2]_i_20_n_0\,
      O => \resid[2]_i_18_n_0\
    );
\resid[2]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAEFFAE"
    )
        port map (
      I0 => \ixRetbufCrc[4]_i_2_n_0\,
      I1 => \ixRetbufCrc[5]_i_3_n_0\,
      I2 => \ixRetbufCrc[5]_i_4_n_0\,
      I3 => \^tixvcommand_reg[0]_0\,
      I4 => ackInvConfigSynth_sig_i_5_n_0,
      O => \resid[2]_i_19_n_0\
    );
\resid[2]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => ackInvUnlock_sig_i_4_n_0,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => targetNotSteady_i_3_n_0,
      I5 => \tixVController_reg_n_0_[0]\,
      O => \resid[2]_i_20_n_0\
    );
\resid[2]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF7FF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[1]\,
      I2 => \retbuf[0][0]_i_3_n_0\,
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[3]\,
      I5 => \tixVController_reg_n_0_[2]\,
      O => \resid[2]_i_21_n_0\
    );
\resid[2]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001000000000"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \tixVController_reg_n_0_[4]\,
      I2 => \tixVController_reg_n_0_[3]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[1]\,
      I5 => \staTixVTrigger[7]_i_4__1_n_0\,
      O => \resid[2]_i_22_n_0\
    );
\resid[2]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAA2AAA"
    )
        port map (
      I0 => \resid[2]_i_17_n_0\,
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \stateOp_i_4__1_n_0\,
      I5 => \resid[2]_i_32_n_0\,
      O => \resid[2]_i_23_n_0\
    );
\resid[2]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[4]\,
      I1 => \tixVCommand_reg_n_0_[5]\,
      I2 => \tixVCommand_reg_n_0_[1]\,
      O => \resid[2]_i_24_n_0\
    );
\resid[2]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \tixVController_reg_n_0_[1]\,
      I1 => \tixVController_reg_n_0_[0]\,
      O => \resid[2]_i_25_n_0\
    );
\resid[2]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFD"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \tixVController_reg_n_0_[4]\,
      I2 => \retbuf[0][0]_i_3_n_0\,
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \tixVController_reg_n_0_[1]\,
      O => \resid[2]_i_26_n_0\
    );
\resid[2]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFDFFFFF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[1]\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => \tixVController_reg_n_0_[4]\,
      I5 => \tixVController_reg_n_0_[3]\,
      O => \resid[2]_i_27_n_0\
    );
\resid[2]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFBFFFFFF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \tixVController_reg_n_0_[4]\,
      I2 => \retbuf[0][0]_i_3_n_0\,
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \tixVController_reg_n_0_[0]\,
      I5 => \tixVController_reg_n_0_[1]\,
      O => \resid[2]_i_28_n_0\
    );
\resid[2]_i_29\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[7]\,
      I1 => \tixVCommand_reg_n_0_[6]\,
      O => \resid[2]_i_29_n_0\
    );
\resid[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040000000000000"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => \^stateop_reg[5]_0\(4),
      I2 => \^stateop_reg[5]_0\(0),
      I3 => \^stateop_reg[5]_0\(1),
      I4 => \^stateop_reg[5]_0\(3),
      I5 => \^stateop_reg[5]_0\(2),
      O => \resid[2]_i_3_n_0\
    );
\resid[2]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[1]\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => \tixVController_reg_n_0_[4]\,
      I5 => \tixVController_reg_n_0_[3]\,
      O => \resid[2]_i_30_n_0\
    );
\resid[2]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFEF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[2]\,
      I1 => \tixVController_reg_n_0_[3]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \tixVController_reg_n_0_[7]\,
      I4 => \tixVController_reg_n_0_[5]\,
      I5 => \tixVController_reg_n_0_[6]\,
      O => \resid[2]_i_31_n_0\
    );
\resid[2]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000C200000002"
    )
        port map (
      I0 => targetNotSteady_i_3_n_0,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \staTixVTrigger[7]_i_3__1_n_0\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \stateOp_i_3__1_n_0\,
      O => \resid[2]_i_32_n_0\
    );
\resid[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(2),
      I3 => \^stateop_reg[5]_0\(4),
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(0),
      O => \resid[2]_i_4_n_0\
    );
\resid[2]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => targetNotSteady_i_3_n_0,
      I1 => ackInvConfigSynth_sig_i_5_n_0,
      O => \resid[2]_i_5_n_0\
    );
\resid[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \resid[2]_i_9_n_0\,
      I1 => \resid[2]_i_10_n_0\,
      I2 => \resid[2]_i_11_n_0\,
      I3 => \resid[2]_i_12_n_0\,
      I4 => \resid[2]_i_13_n_0\,
      I5 => \resid[2]_i_14_n_0\,
      O => \resid[2]_i_6_n_0\
    );
\resid[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FF00000101"
    )
        port map (
      I0 => \resid[2]_i_15_n_0\,
      I1 => \resid[2]_i_16_n_0\,
      I2 => \resid[2]_i_17_n_0\,
      I3 => \wordcntLast[2]_i_2_n_0\,
      I4 => \resid[2]_i_18_n_0\,
      I5 => \resid[2]_i_19_n_0\,
      O => \resid[2]_i_7_n_0\
    );
\resid[2]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000045"
    )
        port map (
      I0 => \resid[2]_i_20_n_0\,
      I1 => \resid[2]_i_21_n_0\,
      I2 => \stateOp_i_3__1_n_0\,
      I3 => \resid[2]_i_22_n_0\,
      I4 => \resid[2]_i_23_n_0\,
      O => \resid[2]_i_8_n_0\
    );
\resid[2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000C380"
    )
        port map (
      I0 => targetNotSteady_i_3_n_0,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \staTixVTrigger[7]_i_4__1_n_0\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \staTixVTrigger[7]_i_3__1_n_0\,
      O => \resid[2]_i_9_n_0\
    );
\resid_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_188,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_149,
      Q => resid(0)
    );
\resid_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_188,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_148,
      Q => resid(1)
    );
\resid_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_188,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_147,
      Q => resid(2)
    );
\restart_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000DD0D"
    )
        port map (
      I0 => ackInvMemtrackSetMask,
      I1 => \^reqinvmemtracksetmask\,
      I2 => ackInvMemtrackSet,
      I3 => \^reqinvmemtrackset\,
      I4 => restart_i_3_n_0,
      O => ackInvSetMask_sig_reg
    );
\restart_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000DD0D"
    )
        port map (
      I0 => ackInvHshktrackClearMask,
      I1 => \^reqinvhshktrackclearmask\,
      I2 => ackInvHshktrackSet,
      I3 => \^reqinvhshktrackset\,
      I4 => \^ackinvselect_sig_reg\,
      O => ackInvClearMask_sig_reg
    );
restart_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^reqinvmemtrackselect\,
      I1 => ackInvMemtrackSelect,
      I2 => \^reqinvmemtrackclearmask\,
      I3 => ackInvMemtrackClearMask,
      O => restart_i_3_n_0
    );
\restart_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^reqinvhshktrackselect\,
      I1 => ackInvHshktrackSelect,
      I2 => \^reqinvhshktracksetmask\,
      I3 => ackInvHshktrackSetMask,
      O => \^ackinvselect_sig_reg\
    );
\retbuf[0][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0AFCFCFA0AFC0C0"
    )
        port map (
      I0 => \retbuf[0][0]_i_6_n_0\,
      I1 => \retbuf[0][0]_i_7_n_0\,
      I2 => \retbuf[0][7]_i_19_n_0\,
      I3 => vidtrackGetInfoTixVState(0),
      I4 => \retbuf[0][1]_i_3_n_0\,
      I5 => \retbuf[0][0]_i_8_n_0\,
      O => \retbuf[0][0]_i_2_n_0\
    );
\retbuf[0][0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \tixVController_reg_n_0_[7]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[6]\,
      O => \retbuf[0][0]_i_3_n_0\
    );
\retbuf[0][0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(24),
      I1 => ackInvSet_sig_reg(1),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_10_0\(0),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \tixVState_reg[1]_1\(0),
      O => \retbuf[0][0]_i_6_n_0\
    );
\retbuf[0][0]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"503F5F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_1\(20),
      I1 => \tixVState_reg[1]_2\(0),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[0][0]_i_2_0\,
      O => \retbuf[0][0]_i_7_n_0\
    );
\retbuf[0][0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => memtrackGetInfoTixVState(0),
      I1 => hshktrackGetInfoTixVState(0),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => cputrackGetInfoTixVState(0),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => traceGetInfoTixVState(0),
      O => \retbuf[0][0]_i_8_n_0\
    );
\retbuf[0][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888CDC8DDDDCDC8"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => vidtrackGetInfoTixVState(1),
      I2 => \retbuf[0][1]_i_3_n_0\,
      I3 => \retbuf[0][1]_i_4_n_0\,
      I4 => \retbuf[0][7]_i_19_n_0\,
      I5 => \retbuf_reg[0][1]_i_5_n_0\,
      O => \retbuf[0][1]_i_2_n_0\
    );
\retbuf[0][1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFAEAAFB"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \tixVController_reg_n_0_[4]\,
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \tixVController_reg_n_0_[1]\,
      O => \retbuf[0][1]_i_3_n_0\
    );
\retbuf[0][1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => memtrackGetInfoTixVState(1),
      I1 => hshktrackGetInfoTixVState(1),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => cputrackGetInfoTixVState(1),
      O => \retbuf[0][1]_i_4_n_0\
    );
\retbuf[0][1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => \retbuf_reg[0][1]_i_5_0\,
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_1\(21),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \tixVState_reg[1]_2\(1),
      O => \retbuf[0][1]_i_6_n_0\
    );
\retbuf[0][1]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"47CC47FF"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(25),
      I1 => \retbuf[0][7]_i_27_n_0\,
      I2 => \retbuf[0][7]_i_10_0\(1),
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \tixVState_reg[1]_1\(1),
      O => \retbuf[0][1]_i_7_n_0\
    );
\retbuf[0][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FFFFFF47FF0000"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(26),
      I1 => \retbuf[0][7]_i_27_n_0\,
      I2 => \retbuf[0][7]_i_10_0\(2),
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[0][1]_i_3_n_0\,
      I5 => \retbuf[0][2]_i_4_n_0\,
      O => \retbuf[0][2]_i_3_n_0\
    );
\retbuf[0][2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F4F4F7F7F7F4F7F"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_1\(22),
      I1 => \retbuf[0][7]_i_27_n_0\,
      I2 => \retbuf[0][7]_i_28_n_0\,
      I3 => \retbuf[0][7]_i_20_0\(24),
      I4 => \^tixvcommand_reg[0]_0\,
      I5 => \retbuf[0][7]_i_20_2\(0),
      O => \retbuf[0][2]_i_4_n_0\
    );
\retbuf[0][3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \retbuf[0][7]_i_19_n_0\,
      I4 => \retbuf[0][3]_i_3_n_0\,
      O => \retbuf[0][3]_i_2_n_0\
    );
\retbuf[0][3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FFFFFF47FF0000"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(27),
      I1 => \retbuf[0][7]_i_27_n_0\,
      I2 => \retbuf[0][7]_i_10_0\(2),
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[0][1]_i_3_n_0\,
      I5 => \retbuf[0][3]_i_4_n_0\,
      O => \retbuf[0][3]_i_3_n_0\
    );
\retbuf[0][3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"05F3F5F3"
    )
        port map (
      I0 => \retbuf[0][3]_i_3_0\,
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[0][7]_i_20_1\(23),
      O => \retbuf[0][3]_i_4_n_0\
    );
\retbuf[0][4]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \retbuf[0][7]_i_19_n_0\,
      I4 => \retbuf[0][4]_i_3_n_0\,
      O => \retbuf[0][4]_i_2__0_n_0\
    );
\retbuf[0][4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FFFFFF47FF0000"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(28),
      I1 => \retbuf[0][7]_i_27_n_0\,
      I2 => \retbuf[0][7]_i_10_0\(2),
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[0][1]_i_3_n_0\,
      I5 => \retbuf[0][4]_i_4_n_0\,
      O => \retbuf[0][4]_i_3_n_0\
    );
\retbuf[0][4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"05F3F5F3"
    )
        port map (
      I0 => \retbuf[0][4]_i_3_0\,
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[0][7]_i_20_1\(24),
      O => \retbuf[0][4]_i_4_n_0\
    );
\retbuf[0][5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \retbuf[0][7]_i_19_n_0\,
      I4 => \retbuf[0][5]_i_3_n_0\,
      O => \retbuf[0][5]_i_2_n_0\
    );
\retbuf[0][5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FFFFFF47FF0000"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(29),
      I1 => \retbuf[0][7]_i_27_n_0\,
      I2 => \retbuf[0][7]_i_10_0\(2),
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[0][1]_i_3_n_0\,
      I5 => \retbuf[0][5]_i_4_n_0\,
      O => \retbuf[0][5]_i_3_n_0\
    );
\retbuf[0][5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"05F3F5F3"
    )
        port map (
      I0 => \retbuf[0][5]_i_3_0\,
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[0][7]_i_20_1\(25),
      O => \retbuf[0][5]_i_4_n_0\
    );
\retbuf[0][6]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000100000"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(0),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(4),
      I3 => \^stateop_reg[5]_0\(5),
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(2),
      O => \retbuf[0][6]_i_2__0_n_0\
    );
\retbuf[0][6]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \retbuf[0][7]_i_19_n_0\,
      I4 => \retbuf[0][6]_i_4_n_0\,
      O => \retbuf[0][6]_i_3__0_n_0\
    );
\retbuf[0][6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FFFFFF47FF0000"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(30),
      I1 => \retbuf[0][7]_i_27_n_0\,
      I2 => \retbuf[0][7]_i_10_0\(2),
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[0][1]_i_3_n_0\,
      I5 => \retbuf[0][6]_i_5_n_0\,
      O => \retbuf[0][6]_i_4_n_0\
    );
\retbuf[0][6]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03F5F3F5"
    )
        port map (
      I0 => \stateOp_i_3__1_n_0\,
      I1 => \retbuf[0][6]_i_4_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[0][7]_i_20_1\(26),
      O => \retbuf[0][6]_i_5_n_0\
    );
\retbuf[0][7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => ixRetbufCrc(3),
      I1 => ixRetbufCrc(4),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(0),
      I4 => ixRetbufCrc(5),
      I5 => ixRetbufCrc(2),
      O => \retbuf[0][7]_i_11_n_0\
    );
\retbuf[0][7]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => ixRetbufCrc(0),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(5),
      I3 => ixRetbufCrc(3),
      I4 => ixRetbufCrc(2),
      I5 => ixRetbufCrc(4),
      O => \retbuf[0][7]_i_12_n_0\
    );
\retbuf[0][7]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[4]\,
      I1 => \tixVController_reg_n_0_[3]\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => \tixVController_reg_n_0_[1]\,
      O => \retbuf[0][7]_i_13_n_0\
    );
\retbuf[0][7]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FF51FFFFFFFF"
    )
        port map (
      I0 => \retbuf[0][7]_i_21_n_0\,
      I1 => \retbuf[0][7]_i_22_n_0\,
      I2 => \retbuf[0][7]_i_23_n_0\,
      I3 => \retbuf[0][7]_i_24_n_0\,
      I4 => \ixRetbufCrc[4]_i_4_n_0\,
      I5 => \resid[0]_i_4_n_0\,
      O => \retbuf[0][7]_i_14_n_0\
    );
\retbuf[0][7]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"220F2200220F22FF"
    )
        port map (
      I0 => \retbuf[0][7]_i_25_n_0\,
      I1 => \stateOp[5]_i_32_n_0\,
      I2 => ackInvCamifConfigSynth,
      I3 => \stateOp[5]_i_34_n_0\,
      I4 => \tixVCommand_reg_n_0_[0]\,
      I5 => ackInvCamifConfig,
      O => \retbuf[0][7]_i_15_n_0\
    );
\retbuf[0][7]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F0F0F0B"
    )
        port map (
      I0 => \i2cRegaddr[15]_i_11_n_0\,
      I1 => \ixRetbufCrc[5]_i_4_n_0\,
      I2 => ackInvConfigSynth_sig_i_5_n_0,
      I3 => targetNotSteady_i_3_n_0,
      I4 => \^tixvcommand_reg[0]_0\,
      O => \retbuf[0][7]_i_16_n_0\
    );
\retbuf[0][7]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \stateOp[5]_i_24_n_0\,
      I1 => \stateOp[5]_i_23_n_0\,
      O => \retbuf[0][7]_i_17_n_0\
    );
\retbuf[0][7]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => ixRetbufCrc(3),
      I1 => ixRetbufCrc(4),
      O => \retbuf[0][7]_i_18_n_0\
    );
\retbuf[0][7]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00970034"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[3]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[2]\,
      O => \retbuf[0][7]_i_19_n_0\
    );
\retbuf[0][7]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFC0000055555555"
    )
        port map (
      I0 => \retbuf[0][7]_i_26_n_0\,
      I1 => \retbuf[0][7]_i_10\(31),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_10_0\(2),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf[0][1]_i_3_n_0\,
      O => \retbuf[0][7]_i_20_n_0\
    );
\retbuf[0][7]_i_21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0322032A"
    )
        port map (
      I0 => \tixVController_reg_n_0_[2]\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[3]\,
      I4 => \stateOp_i_3__1_n_0\,
      O => \retbuf[0][7]_i_21_n_0\
    );
\retbuf[0][7]_i_22\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FCF7"
    )
        port map (
      I0 => \tixVController_reg_n_0_[2]\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[3]\,
      O => \retbuf[0][7]_i_22_n_0\
    );
\retbuf[0][7]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEFFFEEEEEEEE"
    )
        port map (
      I0 => \retbuf[5][7]_i_14_n_0\,
      I1 => \resid[2]_i_32_n_0\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \retbuf[0][7]_i_29_n_0\,
      I4 => \retbuf[0][7]_i_30_n_0\,
      I5 => \stateOp_i_3__1_n_0\,
      O => \retbuf[0][7]_i_23_n_0\
    );
\retbuf[0][7]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000800F800080008"
    )
        port map (
      I0 => targetNotSteady_i_3_n_0,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[3]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[1]\,
      I5 => \staTixVTrigger[7]_i_4__1_n_0\,
      O => \retbuf[0][7]_i_24_n_0\
    );
\retbuf[0][7]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EFEE"
    )
        port map (
      I0 => \^tixvcommand_reg[0]_0\,
      I1 => targetNotSteady_i_3_n_0,
      I2 => ackInvCamifModReg,
      I3 => \i2cRegaddr[15]_i_11_n_0\,
      I4 => ackInvConfigSynth_sig_i_5_n_0,
      O => \retbuf[0][7]_i_25_n_0\
    );
\retbuf[0][7]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44477747FFFFFFFF"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_1\(27),
      I1 => \retbuf[0][7]_i_27_n_0\,
      I2 => \retbuf[0][7]_i_20_0\(25),
      I3 => \^tixvcommand_reg[0]_0\,
      I4 => \retbuf[0][7]_i_20_2\(1),
      I5 => \retbuf[0][7]_i_28_n_0\,
      O => \retbuf[0][7]_i_26_n_0\
    );
\retbuf[0][7]_i_27\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"400400CC"
    )
        port map (
      I0 => \tixVController_reg_n_0_[4]\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \tixVController_reg_n_0_[3]\,
      O => \retbuf[0][7]_i_27_n_0\
    );
\retbuf[0][7]_i_28\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"403C0100"
    )
        port map (
      I0 => \tixVController_reg_n_0_[4]\,
      I1 => \tixVController_reg_n_0_[1]\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \tixVController_reg_n_0_[3]\,
      I4 => \tixVController_reg_n_0_[0]\,
      O => \retbuf[0][7]_i_28_n_0\
    );
\retbuf[0][7]_i_29\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \tixVController_reg_n_0_[1]\,
      I1 => \tixVController_reg_n_0_[0]\,
      O => \retbuf[0][7]_i_29_n_0\
    );
\retbuf[0][7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF15FF"
    )
        port map (
      I0 => \retbuf[0][7]_i_11_n_0\,
      I1 => resid(0),
      I2 => \retbuf[0][7]_i_12_n_0\,
      I3 => \retbuf[4][7]_i_4_n_0\,
      I4 => \^stateop_reg[5]_0\(5),
      O => \retbuf[0][7]_i_3_n_0\
    );
\retbuf[0][7]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBFBFFFFFBFFF"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \tixVController_reg_n_0_[1]\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \tixVController_reg_n_0_[5]\,
      I4 => \tixVController_reg_n_0_[4]\,
      I5 => \tixVController_reg_n_0_[3]\,
      O => \retbuf[0][7]_i_30_n_0\
    );
\retbuf[0][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF1F10"
    )
        port map (
      I0 => \^tixvcommand_reg[0]_0\,
      I1 => \stateCorecfg[2]_i_6_n_0\,
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \ixRetbufCrc[5]_i_4_n_0\,
      I4 => \retbuf[0][7]_i_13_n_0\,
      I5 => \retbuf[0][7]_i_14_n_0\,
      O => \retbuf[0][7]_i_4_n_0\
    );
\retbuf[0][7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => \^stateop_reg[5]_0\(4),
      O => \retbuf[0][7]_i_5_n_0\
    );
\retbuf[0][7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4544454445444555"
    )
        port map (
      I0 => reqReset_sig_i_2_n_0,
      I1 => \stateOp[5]_i_15_n_0\,
      I2 => \retbuf[0][7]_i_15_n_0\,
      I3 => \retbuf[0][7]_i_16_n_0\,
      I4 => \stateOp[5]_i_13_n_0\,
      I5 => \retbuf[0][7]_i_17_n_0\,
      O => \retbuf[0][7]_i_6_n_0\
    );
\retbuf[0][7]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200200"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(2),
      I3 => \^stateop_reg[5]_0\(4),
      I4 => \^stateop_reg[5]_0\(0),
      O => \retbuf[0][7]_i_7_n_0\
    );
\retbuf[0][7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555515555555"
    )
        port map (
      I0 => \retbuf[16][5]_i_2_n_0\,
      I1 => ixRetbufCrc(2),
      I2 => ixRetbufCrc(5),
      I3 => ixRetbufCrc(0),
      I4 => ixRetbufCrc(1),
      I5 => \retbuf[0][7]_i_18_n_0\,
      O => \retbuf[0][7]_i_8_n_0\
    );
\retbuf[10][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010100010001000"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => \^stateop_reg[5]_0\(4),
      I3 => \retbuf[10][7]_i_5_n_0\,
      I4 => resid(0),
      I5 => \retbuf[10][7]_i_6_n_0\,
      O => \retbuf[10][7]_i_3_n_0\
    );
\retbuf[10][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF01000000"
    )
        port map (
      I0 => \retbuf[5][7]_i_13_n_0\,
      I1 => ixRetbufCrc(5),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(0),
      I4 => ixRetbufCrc(3),
      I5 => \retbuf[16][5]_i_2_n_0\,
      O => \retbuf[10][7]_i_4_n_0\
    );
\retbuf[10][7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => ixRetbufCrc(3),
      I1 => ixRetbufCrc(0),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(1),
      I5 => ixRetbufCrc(4),
      O => \retbuf[10][7]_i_5_n_0\
    );
\retbuf[10][7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => ixRetbufCrc(0),
      I1 => ixRetbufCrc(2),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(3),
      I4 => ixRetbufCrc(5),
      I5 => ixRetbufCrc(4),
      O => \retbuf[10][7]_i_6_n_0\
    );
\retbuf[11][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFDFFFFFFFCFF"
    )
        port map (
      I0 => resid(0),
      I1 => ixRetbufCrc(4),
      I2 => ixRetbufCrc(5),
      I3 => \retbuf[11][7]_i_5_n_0\,
      I4 => ixRetbufCrc(2),
      I5 => ixRetbufCrc(0),
      O => \retbuf[11][7]_i_3_n_0\
    );
\retbuf[11][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00001000"
    )
        port map (
      I0 => ixRetbufCrc(4),
      I1 => ixRetbufCrc(5),
      I2 => ixRetbufCrc(3),
      I3 => ixRetbufCrc(1),
      I4 => \retbuf[11][7]_i_6_n_0\,
      I5 => \retbuf[16][5]_i_2_n_0\,
      O => \retbuf[11][7]_i_4_n_0\
    );
\retbuf[11][7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ixRetbufCrc(1),
      I1 => ixRetbufCrc(3),
      O => \retbuf[11][7]_i_5_n_0\
    );
\retbuf[11][7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => ixRetbufCrc(2),
      I1 => ixRetbufCrc(0),
      O => \retbuf[11][7]_i_6_n_0\
    );
\retbuf[12][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010100010001000"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => \^stateop_reg[5]_0\(4),
      I3 => \retbuf[12][7]_i_5_n_0\,
      I4 => resid(0),
      I5 => \retbuf[12][7]_i_6_n_0\,
      O => \retbuf[12][7]_i_3_n_0\
    );
\retbuf[12][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF01000000"
    )
        port map (
      I0 => ixRetbufCrc(4),
      I1 => ixRetbufCrc(2),
      I2 => \retbuf[12][7]_i_7_n_0\,
      I3 => ixRetbufCrc(1),
      I4 => ixRetbufCrc(3),
      I5 => \retbuf[16][5]_i_2_n_0\,
      O => \retbuf[12][7]_i_4_n_0\
    );
\retbuf[12][7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000800"
    )
        port map (
      I0 => ixRetbufCrc(3),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(5),
      I3 => ixRetbufCrc(0),
      I4 => ixRetbufCrc(2),
      I5 => ixRetbufCrc(4),
      O => \retbuf[12][7]_i_5_n_0\
    );
\retbuf[12][7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => ixRetbufCrc(3),
      I1 => ixRetbufCrc(2),
      I2 => ixRetbufCrc(0),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(1),
      I5 => ixRetbufCrc(4),
      O => \retbuf[12][7]_i_6_n_0\
    );
\retbuf[12][7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => ixRetbufCrc(5),
      I1 => ixRetbufCrc(0),
      O => \retbuf[12][7]_i_7_n_0\
    );
\retbuf[13][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFCFFFFFFFFFFFF"
    )
        port map (
      I0 => resid(0),
      I1 => \retbuf[5][7]_i_13_n_0\,
      I2 => ixRetbufCrc(5),
      I3 => ixRetbufCrc(0),
      I4 => ixRetbufCrc(2),
      I5 => ixRetbufCrc(3),
      O => \retbuf[13][7]_i_3_n_0\
    );
\retbuf[13][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF01000000"
    )
        port map (
      I0 => \retbuf[5][7]_i_13_n_0\,
      I1 => ixRetbufCrc(5),
      I2 => ixRetbufCrc(0),
      I3 => ixRetbufCrc(2),
      I4 => ixRetbufCrc(3),
      I5 => \retbuf[16][5]_i_2_n_0\,
      O => \retbuf[13][7]_i_4_n_0\
    );
\retbuf[14][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001400000004"
    )
        port map (
      I0 => ixRetbufCrc(4),
      I1 => ixRetbufCrc(0),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(5),
      I4 => \retbuf[14][7]_i_5_n_0\,
      I5 => resid(0),
      O => \retbuf[14][7]_i_3_n_0\
    );
\retbuf[14][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00004000"
    )
        port map (
      I0 => \retbuf[5][7]_i_13_n_0\,
      I1 => ixRetbufCrc(3),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(0),
      I4 => ixRetbufCrc(5),
      I5 => \retbuf[16][5]_i_2_n_0\,
      O => \retbuf[14][7]_i_4_n_0\
    );
\retbuf[14][7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => ixRetbufCrc(2),
      I1 => ixRetbufCrc(3),
      O => \retbuf[14][7]_i_5_n_0\
    );
\retbuf[15][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFF7FFFF"
    )
        port map (
      I0 => ixRetbufCrc(1),
      I1 => ixRetbufCrc(3),
      I2 => ixRetbufCrc(5),
      I3 => ixRetbufCrc(4),
      I4 => ixRetbufCrc(2),
      I5 => \retbuf[29][7]_i_4_n_0\,
      O => \retbuf[15][7]_i_3_n_0\
    );
\retbuf[15][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000010"
    )
        port map (
      I0 => \retbuf[14][7]_i_5_n_0\,
      I1 => ixRetbufCrc(5),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(0),
      I4 => ixRetbufCrc(4),
      I5 => \retbuf[16][5]_i_2_n_0\,
      O => \retbuf[15][7]_i_4_n_0\
    );
\retbuf[16][5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => resid(0),
      I1 => resid(2),
      I2 => resid(1),
      O => \retbuf[16][5]_i_2_n_0\
    );
\retbuf[16][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => ixRetbufCrc(0),
      I1 => ixRetbufCrc(2),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(3),
      I4 => ixRetbufCrc(5),
      I5 => ixRetbufCrc(4),
      O => \retbuf[16][7]_i_4_n_0\
    );
\retbuf[16][7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFD"
    )
        port map (
      I0 => ixRetbufCrc(4),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(3),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(2),
      I5 => ixRetbufCrc(0),
      O => \retbuf[16][7]_i_5_n_0\
    );
\retbuf[16][7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEAFFFFFF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(2),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(4),
      I3 => \retbuf[4][7]_i_4_n_0\,
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(0),
      O => \retbuf[16][7]_i_6_n_0\
    );
\retbuf[16][7]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => resid(0),
      I3 => \retbuf[16][7]_i_4_n_0\,
      O => \retbuf[16][7]_i_7_n_0\
    );
\retbuf[17][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => ixRetbufCrc(1),
      I1 => ixRetbufCrc(5),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(3),
      I4 => ixRetbufCrc(4),
      I5 => ixRetbufCrc(0),
      O => \retbuf[17][5]_i_2_n_0\
    );
\retbuf[17][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => ixRetbufCrc(4),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(3),
      I4 => ixRetbufCrc(5),
      I5 => ixRetbufCrc(0),
      O => \retbuf[17][7]_i_3_n_0\
    );
\retbuf[17][7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => resid(0),
      I3 => \retbuf[17][5]_i_2_n_0\,
      O => \retbuf[17][7]_i_4_n_0\
    );
\retbuf[18][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => ixRetbufCrc(4),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(3),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(2),
      I5 => ixRetbufCrc(0),
      O => \retbuf[18][7]_i_3_n_0\
    );
\retbuf[18][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555455555555"
    )
        port map (
      I0 => \retbuf[16][5]_i_2_n_0\,
      I1 => \retbuf[12][7]_i_7_n_0\,
      I2 => ixRetbufCrc(3),
      I3 => ixRetbufCrc(2),
      I4 => ixRetbufCrc(1),
      I5 => ixRetbufCrc(4),
      O => \retbuf[18][7]_i_4_n_0\
    );
\retbuf[19][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => ixRetbufCrc(4),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(3),
      I4 => ixRetbufCrc(5),
      I5 => ixRetbufCrc(0),
      O => \retbuf[19][7]_i_3_n_0\
    );
\retbuf[19][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5455555555555555"
    )
        port map (
      I0 => \retbuf[16][5]_i_2_n_0\,
      I1 => ixRetbufCrc(0),
      I2 => ixRetbufCrc(2),
      I3 => \retbuf[1][7]_i_12_n_0\,
      I4 => ixRetbufCrc(1),
      I5 => ixRetbufCrc(4),
      O => \retbuf[19][7]_i_4_n_0\
    );
\retbuf[1][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888CDC8DDDDCDC8"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][7]_0\(24),
      I2 => \retbuf[0][1]_i_3_n_0\,
      I3 => \retbuf[1][0]_i_3_n_0\,
      I4 => \retbuf[0][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][0]_i_4_n_0\,
      O => \retbuf[1][0]_i_2_n_0\
    );
\retbuf[1][0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(24),
      I1 => \retbuf[1][7]_i_8_1\(24),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[1][7]_i_8_0\(24),
      O => \retbuf[1][0]_i_3_n_0\
    );
\retbuf[1][0]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"50305F30"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_1\(12),
      I1 => \retbuf_reg[1][7]_i_13_0\(24),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[0][7]_i_20_0\(16),
      O => \retbuf[1][0]_i_5_n_0\
    );
\retbuf[1][0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(16),
      I1 => \ccwNotCw2_carry__0\(8),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf_reg[1][7]_i_13_2\(24),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_1\(24),
      O => \retbuf[1][0]_i_6_n_0\
    );
\retbuf[1][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888CDC8DDDDCDC8"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][7]_0\(25),
      I2 => \retbuf[0][1]_i_3_n_0\,
      I3 => \retbuf[1][1]_i_3_n_0\,
      I4 => \retbuf[0][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][1]_i_4_n_0\,
      O => \retbuf[1][1]_i_2_n_0\
    );
\retbuf[1][1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(25),
      I1 => \retbuf[1][7]_i_8_1\(25),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[1][7]_i_8_0\(25),
      O => \retbuf[1][1]_i_3_n_0\
    );
\retbuf[1][1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F50C0C05F5FCFC"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_0\(17),
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_1\(13),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_0\(25),
      O => \retbuf[1][1]_i_5_n_0\
    );
\retbuf[1][1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(17),
      I1 => \ccwNotCw2_carry__0\(9),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf_reg[1][7]_i_13_2\(25),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_1\(25),
      O => \retbuf[1][1]_i_6_n_0\
    );
\retbuf[1][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888CDC8DDDDCDC8"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][7]_0\(26),
      I2 => \retbuf[0][1]_i_3_n_0\,
      I3 => \retbuf[1][2]_i_3_n_0\,
      I4 => \retbuf[0][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][2]_i_4_n_0\,
      O => \retbuf[1][2]_i_2_n_0\
    );
\retbuf[1][2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(26),
      I1 => \retbuf[1][7]_i_8_1\(26),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[1][7]_i_8_0\(26),
      O => \retbuf[1][2]_i_3_n_0\
    );
\retbuf[1][2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_0\(18),
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_1\(14),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_0\(26),
      O => \retbuf[1][2]_i_5_n_0\
    );
\retbuf[1][2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(18),
      I1 => \ccwNotCw2_carry__0\(10),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf_reg[1][7]_i_13_2\(26),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_1\(26),
      O => \retbuf[1][2]_i_6_n_0\
    );
\retbuf[1][3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40EF45EF40EF40EA"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][3]_i_3_n_0\,
      I2 => \retbuf[0][7]_i_19_n_0\,
      I3 => \retbuf_reg[1][7]_0\(27),
      I4 => \retbuf[0][1]_i_3_n_0\,
      I5 => \retbuf[1][3]_i_4_n_0\,
      O => \retbuf[1][3]_i_2_n_0\
    );
\retbuf[1][3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"505F3F3F"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(27),
      I1 => \retbuf[1][7]_i_8_1\(27),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[1][7]_i_8_0\(27),
      I4 => \retbuf[0][7]_i_28_n_0\,
      O => \retbuf[1][3]_i_4_n_0\
    );
\retbuf[1][3]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_1\(15),
      I1 => \retbuf_reg[1][7]_i_13_0\(27),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_0\(19),
      I4 => \retbuf[0][7]_i_28_n_0\,
      O => \retbuf[1][3]_i_5_n_0\
    );
\retbuf[1][3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(19),
      I1 => \ccwNotCw2_carry__0\(11),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf_reg[1][7]_i_13_2\(27),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_1\(27),
      O => \retbuf[1][3]_i_6_n_0\
    );
\retbuf[1][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888CDC8DDDDCDC8"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][7]_0\(28),
      I2 => \retbuf[0][1]_i_3_n_0\,
      I3 => \retbuf[1][4]_i_3_n_0\,
      I4 => \retbuf[0][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][4]_i_4_n_0\,
      O => \retbuf[1][4]_i_2_n_0\
    );
\retbuf[1][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(28),
      I1 => \retbuf[1][7]_i_8_1\(28),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[1][7]_i_8_0\(28),
      O => \retbuf[1][4]_i_3_n_0\
    );
\retbuf[1][4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_0\(20),
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_1\(16),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_0\(28),
      O => \retbuf[1][4]_i_5_n_0\
    );
\retbuf[1][4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(20),
      I1 => \ccwNotCw2_carry__0\(12),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf_reg[1][7]_i_13_2\(28),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_1\(28),
      O => \retbuf[1][4]_i_6_n_0\
    );
\retbuf[1][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888CDC8DDDDCDC8"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][7]_0\(29),
      I2 => \retbuf[0][1]_i_3_n_0\,
      I3 => \retbuf[1][5]_i_3_n_0\,
      I4 => \retbuf[0][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][5]_i_4_n_0\,
      O => \retbuf[1][5]_i_2_n_0\
    );
\retbuf[1][5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(29),
      I1 => \retbuf[1][7]_i_8_1\(29),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[1][7]_i_8_0\(29),
      O => \retbuf[1][5]_i_3_n_0\
    );
\retbuf[1][5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_0\(21),
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_1\(17),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_0\(29),
      O => \retbuf[1][5]_i_5_n_0\
    );
\retbuf[1][5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(21),
      I1 => \ccwNotCw2_carry__0\(13),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf_reg[1][7]_i_13_2\(29),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_1\(29),
      O => \retbuf[1][5]_i_6_n_0\
    );
\retbuf[1][6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888CDC8DDDDCDC8"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][7]_0\(30),
      I2 => \retbuf[0][1]_i_3_n_0\,
      I3 => \retbuf[1][6]_i_3_n_0\,
      I4 => \retbuf[0][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][6]_i_4_n_0\,
      O => \retbuf[1][6]_i_2_n_0\
    );
\retbuf[1][6]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(30),
      I1 => \retbuf[1][7]_i_8_1\(30),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[1][7]_i_8_0\(30),
      O => \retbuf[1][6]_i_3_n_0\
    );
\retbuf[1][6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_0\(22),
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_1\(18),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_0\(30),
      O => \retbuf[1][6]_i_5_n_0\
    );
\retbuf[1][6]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"47CC47FF"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(22),
      I1 => \retbuf[0][7]_i_27_n_0\,
      I2 => \retbuf_reg[1][7]_i_13_2\(30),
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf_reg[1][7]_i_13_1\(30),
      O => \retbuf[1][6]_i_6_n_0\
    );
\retbuf[1][7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \tixVController_reg_n_0_[3]\,
      I5 => \tixVController_reg_n_0_[4]\,
      O => \retbuf[1][7]_i_10_n_0\
    );
\retbuf[1][7]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => ixRetbufCrc(4),
      I1 => ixRetbufCrc(2),
      I2 => ixRetbufCrc(3),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(1),
      O => \retbuf[1][7]_i_11_n_0\
    );
\retbuf[1][7]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ixRetbufCrc(3),
      I1 => ixRetbufCrc(5),
      O => \retbuf[1][7]_i_12_n_0\
    );
\retbuf[1][7]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"505F3F3F"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(31),
      I1 => \retbuf[1][7]_i_8_1\(31),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[1][7]_i_8_0\(31),
      I4 => \retbuf[0][7]_i_28_n_0\,
      O => \retbuf[1][7]_i_14_n_0\
    );
\retbuf[1][7]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_1\(19),
      I1 => \retbuf_reg[1][7]_i_13_0\(31),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_0\(23),
      I4 => \retbuf[0][7]_i_28_n_0\,
      O => \retbuf[1][7]_i_15_n_0\
    );
\retbuf[1][7]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"47CC47FF"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(23),
      I1 => \retbuf[0][7]_i_27_n_0\,
      I2 => \retbuf_reg[1][7]_i_13_2\(31),
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf_reg[1][7]_i_13_1\(31),
      O => \retbuf[1][7]_i_16_n_0\
    );
\retbuf[1][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4555555545554545"
    )
        port map (
      I0 => \retbuf[0][7]_i_14_n_0\,
      I1 => \retbuf[1][7]_i_10_n_0\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \stateCorecfg[2]_i_6_n_0\,
      I4 => \tixVController_reg_n_0_[0]\,
      I5 => \ixRetbufCrc[5]_i_4_n_0\,
      O => \retbuf[1][7]_i_3_n_0\
    );
\retbuf[1][7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEAEE"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(2),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(4),
      I3 => \^stateop_reg[5]_0\(1),
      I4 => \^stateop_reg[5]_0\(0),
      O => \retbuf[1][7]_i_4_n_0\
    );
\retbuf[1][7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA88A8AAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \retbuf[1][7]_i_11_n_0\,
      I2 => ixRetbufCrc(0),
      I3 => resid(0),
      I4 => \retbuf[36][7]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \retbuf[1][7]_i_5_n_0\
    );
\retbuf[1][7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(5),
      O => \retbuf[1][7]_i_6_n_0\
    );
\retbuf[1][7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555455"
    )
        port map (
      I0 => \retbuf[16][5]_i_2_n_0\,
      I1 => ixRetbufCrc(4),
      I2 => ixRetbufCrc(2),
      I3 => \retbuf[1][7]_i_12_n_0\,
      I4 => ixRetbufCrc(1),
      I5 => ixRetbufCrc(0),
      O => \retbuf[1][7]_i_7_n_0\
    );
\retbuf[1][7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40EF45EF40EF40EA"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][7]_i_13_n_0\,
      I2 => \retbuf[0][7]_i_19_n_0\,
      I3 => \retbuf_reg[1][7]_0\(31),
      I4 => \retbuf[0][1]_i_3_n_0\,
      I5 => \retbuf[1][7]_i_14_n_0\,
      O => \retbuf[1][7]_i_8_n_0\
    );
\retbuf[20][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => ixRetbufCrc(4),
      I1 => ixRetbufCrc(2),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(0),
      I4 => ixRetbufCrc(3),
      I5 => ixRetbufCrc(5),
      O => \retbuf[20][7]_i_3_n_0\
    );
\retbuf[20][7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => resid(0),
      I3 => \retbuf[19][7]_i_3_n_0\,
      O => \retbuf[20][7]_i_4_n_0\
    );
\retbuf[21][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => ixRetbufCrc(5),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(3),
      I3 => ixRetbufCrc(4),
      I4 => ixRetbufCrc(2),
      I5 => ixRetbufCrc(0),
      O => \retbuf[21][7]_i_3_n_0\
    );
\retbuf[21][7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => resid(0),
      I3 => \retbuf[20][7]_i_3_n_0\,
      O => \retbuf[21][7]_i_4_n_0\
    );
\retbuf[22][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => ixRetbufCrc(4),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(0),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(3),
      I5 => ixRetbufCrc(2),
      O => \retbuf[22][7]_i_3_n_0\
    );
\retbuf[22][7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => resid(0),
      I3 => \retbuf[21][7]_i_3_n_0\,
      O => \retbuf[22][7]_i_4_n_0\
    );
\retbuf[23][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400000000000000"
    )
        port map (
      I0 => ixRetbufCrc(5),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(3),
      I3 => ixRetbufCrc(4),
      I4 => ixRetbufCrc(2),
      I5 => ixRetbufCrc(0),
      O => \retbuf[23][7]_i_3_n_0\
    );
\retbuf[23][7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => resid(0),
      I3 => \retbuf[22][7]_i_3_n_0\,
      O => \retbuf[23][7]_i_4_n_0\
    );
\retbuf[24][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => ixRetbufCrc(5),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(0),
      I4 => ixRetbufCrc(3),
      I5 => ixRetbufCrc(4),
      O => \retbuf[24][7]_i_3_n_0\
    );
\retbuf[24][7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => resid(0),
      I3 => \retbuf[23][7]_i_3_n_0\,
      O => \retbuf[24][7]_i_4_n_0\
    );
\retbuf[25][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => ixRetbufCrc(2),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(5),
      I3 => ixRetbufCrc(0),
      I4 => ixRetbufCrc(3),
      I5 => ixRetbufCrc(4),
      O => \retbuf[25][7]_i_3_n_0\
    );
\retbuf[25][7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => resid(0),
      I3 => \retbuf[24][7]_i_3_n_0\,
      O => \retbuf[25][7]_i_4_n_0\
    );
\retbuf[26][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000000"
    )
        port map (
      I0 => ixRetbufCrc(0),
      I1 => ixRetbufCrc(2),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(3),
      I5 => ixRetbufCrc(4),
      O => \retbuf[26][7]_i_3_n_0\
    );
\retbuf[26][7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => resid(0),
      I3 => \retbuf[25][7]_i_3_n_0\,
      O => \retbuf[26][7]_i_4_n_0\
    );
\retbuf[27][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => ixRetbufCrc(3),
      I1 => ixRetbufCrc(4),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(0),
      I4 => ixRetbufCrc(5),
      I5 => ixRetbufCrc(2),
      O => \retbuf[27][7]_i_3_n_0\
    );
\retbuf[27][7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => resid(0),
      I3 => \retbuf[26][7]_i_3_n_0\,
      O => \retbuf[27][7]_i_4_n_0\
    );
\retbuf[28][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => ixRetbufCrc(4),
      I1 => ixRetbufCrc(2),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(0),
      I5 => ixRetbufCrc(3),
      O => \retbuf[28][7]_i_3_n_0\
    );
\retbuf[28][7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => resid(0),
      I3 => \retbuf[27][7]_i_3_n_0\,
      O => \retbuf[28][7]_i_4_n_0\
    );
\retbuf[29][7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => ixRetbufCrc(5),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(4),
      I3 => ixRetbufCrc(2),
      O => \retbuf[29][7]_i_3_n_0\
    );
\retbuf[29][7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => ixRetbufCrc(0),
      I1 => resid(0),
      O => \retbuf[29][7]_i_4_n_0\
    );
\retbuf[2][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888CDC8DDDDCDC8"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][7]_0\(16),
      I2 => \retbuf[0][1]_i_3_n_0\,
      I3 => \retbuf[2][0]_i_3_n_0\,
      I4 => \retbuf[0][7]_i_19_n_0\,
      I5 => \retbuf_reg[2][0]_i_4_n_0\,
      O => \retbuf[2][0]_i_2_n_0\
    );
\retbuf[2][0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(16),
      I1 => \retbuf[1][7]_i_8_1\(16),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[1][7]_i_8_0\(16),
      O => \retbuf[2][0]_i_3_n_0\
    );
\retbuf[2][0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F50C0C05F5FCFC"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_0\(8),
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_1\(4),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_0\(16),
      O => \retbuf[2][0]_i_5_n_0\
    );
\retbuf[2][0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(8),
      I1 => \ccwNotCw2_carry__0\(0),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf_reg[1][7]_i_13_2\(16),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_1\(16),
      O => \retbuf[2][0]_i_6_n_0\
    );
\retbuf[2][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888CDC8DDDDCDC8"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][7]_0\(17),
      I2 => \retbuf[0][1]_i_3_n_0\,
      I3 => \retbuf[2][1]_i_3_n_0\,
      I4 => \retbuf[0][7]_i_19_n_0\,
      I5 => \retbuf_reg[2][1]_i_4_n_0\,
      O => \retbuf[2][1]_i_2_n_0\
    );
\retbuf[2][1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(17),
      I1 => \retbuf[1][7]_i_8_1\(17),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[1][7]_i_8_0\(17),
      O => \retbuf[2][1]_i_3_n_0\
    );
\retbuf[2][1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_0\(9),
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_1\(5),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_0\(17),
      O => \retbuf[2][1]_i_5_n_0\
    );
\retbuf[2][1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(9),
      I1 => \ccwNotCw2_carry__0\(1),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf_reg[1][7]_i_13_2\(17),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_1\(17),
      O => \retbuf[2][1]_i_6_n_0\
    );
\retbuf[2][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888CDC8DDDDCDC8"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][7]_0\(18),
      I2 => \retbuf[0][1]_i_3_n_0\,
      I3 => \retbuf[2][2]_i_3_n_0\,
      I4 => \retbuf[0][7]_i_19_n_0\,
      I5 => \retbuf_reg[2][2]_i_4_n_0\,
      O => \retbuf[2][2]_i_2_n_0\
    );
\retbuf[2][2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(18),
      I1 => \retbuf[1][7]_i_8_1\(18),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[1][7]_i_8_0\(18),
      O => \retbuf[2][2]_i_3_n_0\
    );
\retbuf[2][2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"50305F30"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_1\(6),
      I1 => \retbuf_reg[1][7]_i_13_0\(18),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[0][7]_i_20_0\(10),
      O => \retbuf[2][2]_i_5_n_0\
    );
\retbuf[2][2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(10),
      I1 => \ccwNotCw2_carry__0\(2),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf_reg[1][7]_i_13_2\(18),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_1\(18),
      O => \retbuf[2][2]_i_6_n_0\
    );
\retbuf[2][3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888CDC8DDDDCDC8"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][7]_0\(19),
      I2 => \retbuf[0][1]_i_3_n_0\,
      I3 => \retbuf[2][3]_i_3_n_0\,
      I4 => \retbuf[0][7]_i_19_n_0\,
      I5 => \retbuf_reg[2][3]_i_4_n_0\,
      O => \retbuf[2][3]_i_2_n_0\
    );
\retbuf[2][3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(19),
      I1 => \retbuf[1][7]_i_8_1\(19),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[1][7]_i_8_0\(19),
      O => \retbuf[2][3]_i_3_n_0\
    );
\retbuf[2][3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F50C0C05F5FCFC"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_0\(11),
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_1\(7),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_0\(19),
      O => \retbuf[2][3]_i_5_n_0\
    );
\retbuf[2][3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(11),
      I1 => \ccwNotCw2_carry__0\(3),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf_reg[1][7]_i_13_2\(19),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_1\(19),
      O => \retbuf[2][3]_i_6_n_0\
    );
\retbuf[2][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888CDC8DDDDCDC8"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][7]_0\(20),
      I2 => \retbuf[0][1]_i_3_n_0\,
      I3 => \retbuf[2][4]_i_3_n_0\,
      I4 => \retbuf[0][7]_i_19_n_0\,
      I5 => \retbuf_reg[2][4]_i_4_n_0\,
      O => \retbuf[2][4]_i_2_n_0\
    );
\retbuf[2][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(20),
      I1 => \retbuf[1][7]_i_8_1\(20),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[1][7]_i_8_0\(20),
      O => \retbuf[2][4]_i_3_n_0\
    );
\retbuf[2][4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_0\(12),
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_1\(8),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_0\(20),
      O => \retbuf[2][4]_i_5_n_0\
    );
\retbuf[2][4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(12),
      I1 => \ccwNotCw2_carry__0\(4),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf_reg[1][7]_i_13_2\(20),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_1\(20),
      O => \retbuf[2][4]_i_6_n_0\
    );
\retbuf[2][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888CDC8DDDDCDC8"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][7]_0\(21),
      I2 => \retbuf[0][1]_i_3_n_0\,
      I3 => \retbuf[2][5]_i_3_n_0\,
      I4 => \retbuf[0][7]_i_19_n_0\,
      I5 => \retbuf_reg[2][5]_i_4_n_0\,
      O => \retbuf[2][5]_i_2_n_0\
    );
\retbuf[2][5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(21),
      I1 => \retbuf[1][7]_i_8_1\(21),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[1][7]_i_8_0\(21),
      O => \retbuf[2][5]_i_3_n_0\
    );
\retbuf[2][5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_0\(13),
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_1\(9),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_0\(21),
      O => \retbuf[2][5]_i_5_n_0\
    );
\retbuf[2][5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(13),
      I1 => \ccwNotCw2_carry__0\(5),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf_reg[1][7]_i_13_2\(21),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_1\(21),
      O => \retbuf[2][5]_i_6_n_0\
    );
\retbuf[2][6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888CDC8DDDDCDC8"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[1][7]_0\(22),
      I2 => \retbuf[0][1]_i_3_n_0\,
      I3 => \retbuf[2][6]_i_3_n_0\,
      I4 => \retbuf[0][7]_i_19_n_0\,
      I5 => \retbuf_reg[2][6]_i_4_n_0\,
      O => \retbuf[2][6]_i_2_n_0\
    );
\retbuf[2][6]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(22),
      I1 => \retbuf[1][7]_i_8_1\(22),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_28_n_0\,
      I4 => \retbuf[1][7]_i_8_0\(22),
      O => \retbuf[2][6]_i_3_n_0\
    );
\retbuf[2][6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_0\(14),
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_1\(10),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_0\(22),
      O => \retbuf[2][6]_i_5_n_0\
    );
\retbuf[2][6]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(14),
      I1 => \ccwNotCw2_carry__0\(6),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf_reg[1][7]_i_13_2\(22),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_1\(22),
      O => \retbuf[2][6]_i_6_n_0\
    );
\retbuf[2][7]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_1\(11),
      I1 => \retbuf_reg[1][7]_i_13_0\(23),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[0][7]_i_20_0\(15),
      I4 => \retbuf[0][7]_i_28_n_0\,
      O => \retbuf[2][7]_i_10_n_0\
    );
\retbuf[2][7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[0][7]_i_10\(15),
      I1 => \ccwNotCw2_carry__0\(7),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf_reg[1][7]_i_13_2\(23),
      I4 => \retbuf[0][7]_i_28_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_1\(23),
      O => \retbuf[2][7]_i_11_n_0\
    );
\retbuf[2][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A02AAAAAAAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => resid(0),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(0),
      I4 => \retbuf[2][7]_i_6_n_0\,
      I5 => \retbuf[4][7]_i_4_n_0\,
      O => \retbuf[2][7]_i_3_n_0\
    );
\retbuf[2][7]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555545"
    )
        port map (
      I0 => \retbuf[16][5]_i_2_n_0\,
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(0),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(3),
      I5 => \retbuf[2][7]_i_7_n_0\,
      O => \retbuf[2][7]_i_4__0_n_0\
    );
\retbuf[2][7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40EF45EF40EF40EA"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf_reg[2][7]_i_8_n_0\,
      I2 => \retbuf[0][7]_i_19_n_0\,
      I3 => \retbuf_reg[1][7]_0\(23),
      I4 => \retbuf[0][1]_i_3_n_0\,
      I5 => \retbuf[2][7]_i_9_n_0\,
      O => \retbuf[2][7]_i_5_n_0\
    );
\retbuf[2][7]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => ixRetbufCrc(5),
      I1 => ixRetbufCrc(3),
      I2 => ixRetbufCrc(4),
      I3 => ixRetbufCrc(2),
      O => \retbuf[2][7]_i_6_n_0\
    );
\retbuf[2][7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => ixRetbufCrc(2),
      I1 => ixRetbufCrc(4),
      O => \retbuf[2][7]_i_7_n_0\
    );
\retbuf[2][7]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"505F3F3F"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_2\(23),
      I1 => \retbuf[1][7]_i_8_1\(23),
      I2 => \retbuf[0][7]_i_27_n_0\,
      I3 => \retbuf[1][7]_i_8_0\(23),
      I4 => \retbuf[0][7]_i_28_n_0\,
      O => \retbuf[2][7]_i_9_n_0\
    );
\retbuf[30][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => ixRetbufCrc(3),
      I1 => ixRetbufCrc(0),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(4),
      I4 => ixRetbufCrc(1),
      I5 => ixRetbufCrc(5),
      O => \retbuf[30][7]_i_3_n_0\
    );
\retbuf[30][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => ixRetbufCrc(5),
      I1 => ixRetbufCrc(0),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(3),
      I4 => ixRetbufCrc(1),
      I5 => ixRetbufCrc(4),
      O => \retbuf[30][7]_i_4_n_0\
    );
\retbuf[30][7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => resid(0),
      I3 => \retbuf[30][7]_i_3_n_0\,
      O => \retbuf[30][7]_i_5_n_0\
    );
\retbuf[31][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFFFFFFF"
    )
        port map (
      I0 => ixRetbufCrc(2),
      I1 => ixRetbufCrc(4),
      I2 => ixRetbufCrc(5),
      I3 => ixRetbufCrc(0),
      I4 => ixRetbufCrc(3),
      I5 => ixRetbufCrc(1),
      O => \retbuf[31][7]_i_3_n_0\
    );
\retbuf[32][6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000000000000000"
    )
        port map (
      I0 => ixRetbufCrc(0),
      I1 => ixRetbufCrc(5),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(3),
      I4 => ixRetbufCrc(1),
      I5 => ixRetbufCrc(4),
      O => \retbuf[32][6]_i_3_n_0\
    );
\retbuf[32][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => ixRetbufCrc(0),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(4),
      I3 => ixRetbufCrc(2),
      I4 => ixRetbufCrc(3),
      I5 => ixRetbufCrc(5),
      O => \retbuf[32][7]_i_3_n_0\
    );
\retbuf[32][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555515555555"
    )
        port map (
      I0 => \retbuf[16][5]_i_2_n_0\,
      I1 => ixRetbufCrc(4),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(3),
      I4 => ixRetbufCrc(2),
      I5 => \retbuf[12][7]_i_7_n_0\,
      O => \retbuf[32][7]_i_4_n_0\
    );
\retbuf[33][7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFD"
    )
        port map (
      I0 => ixRetbufCrc(5),
      I1 => ixRetbufCrc(3),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(4),
      I4 => ixRetbufCrc(1),
      O => \retbuf[33][7]_i_3_n_0\
    );
\retbuf[34][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => ixRetbufCrc(4),
      I1 => ixRetbufCrc(2),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(0),
      I5 => ixRetbufCrc(3),
      O => \retbuf[34][7]_i_3_n_0\
    );
\retbuf[34][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => ixRetbufCrc(0),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(4),
      I3 => ixRetbufCrc(2),
      I4 => ixRetbufCrc(3),
      I5 => ixRetbufCrc(5),
      O => \retbuf[34][7]_i_4_n_0\
    );
\retbuf[34][7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => resid(0),
      I3 => \retbuf[34][7]_i_4_n_0\,
      O => \retbuf[34][7]_i_5_n_0\
    );
\retbuf[35][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002000"
    )
        port map (
      I0 => ixRetbufCrc(5),
      I1 => ixRetbufCrc(3),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(0),
      I4 => ixRetbufCrc(2),
      I5 => ixRetbufCrc(4),
      O => \retbuf[35][7]_i_3_n_0\
    );
\retbuf[35][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555554555555"
    )
        port map (
      I0 => \retbuf[16][5]_i_2_n_0\,
      I1 => ixRetbufCrc(3),
      I2 => ixRetbufCrc(0),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(1),
      I5 => \retbuf[2][7]_i_7_n_0\,
      O => \retbuf[35][7]_i_4_n_0\
    );
\retbuf[36][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => ixRetbufCrc(4),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(0),
      I3 => ixRetbufCrc(3),
      I4 => ixRetbufCrc(2),
      I5 => ixRetbufCrc(5),
      O => \retbuf[36][7]_i_3_n_0\
    );
\retbuf[36][7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      O => \retbuf[36][7]_i_4_n_0\
    );
\retbuf[36][7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00400000"
    )
        port map (
      I0 => \retbuf[2][7]_i_7_n_0\,
      I1 => ixRetbufCrc(0),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(3),
      I4 => ixRetbufCrc(5),
      I5 => \retbuf[16][5]_i_2_n_0\,
      O => \retbuf[36][7]_i_5_n_0\
    );
\retbuf[37][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => ixRetbufCrc(4),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(3),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(2),
      I5 => ixRetbufCrc(0),
      O => \retbuf[37][7]_i_3_n_0\
    );
\retbuf[37][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAEA"
    )
        port map (
      I0 => \retbuf[16][5]_i_2_n_0\,
      I1 => ixRetbufCrc(5),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(3),
      I4 => ixRetbufCrc(0),
      I5 => \retbuf[5][7]_i_13_n_0\,
      O => \retbuf[37][7]_i_4_n_0\
    );
\retbuf[38][7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ixRetbufCrc(0),
      I1 => ixRetbufCrc(4),
      O => \retbuf[38][7]_i_3_n_0\
    );
\retbuf[38][7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => ixRetbufCrc(2),
      I1 => ixRetbufCrc(3),
      I2 => ixRetbufCrc(5),
      I3 => ixRetbufCrc(1),
      O => \retbuf[38][7]_i_4_n_0\
    );
\retbuf[38][7]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \retbuf[0][6]_i_2__0_n_0\,
      I1 => resid(2),
      I2 => resid(1),
      O => \retbuf[38][7]_i_5_n_0\
    );
\retbuf[38][7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAA"
    )
        port map (
      I0 => \retbuf[16][5]_i_2_n_0\,
      I1 => ixRetbufCrc(0),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(3),
      I5 => \retbuf[5][7]_i_13_n_0\,
      O => \retbuf[38][7]_i_6_n_0\
    );
\retbuf[39][7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(2),
      I1 => \^stateop_reg[5]_0\(5),
      I2 => \^stateop_reg[5]_0\(0),
      O => \retbuf[39][7]_i_3_n_0\
    );
\retbuf[39][7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFEE"
    )
        port map (
      I0 => resid(2),
      I1 => resid(1),
      I2 => resid(0),
      I3 => ixRetbufCrc(0),
      O => \retbuf[39][7]_i_4_n_0\
    );
\retbuf[39][7]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \^stateop_reg[5]_0\(3),
      O => \retbuf[39][7]_i_5_n_0\
    );
\retbuf[39][7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01010101010101FF"
    )
        port map (
      I0 => \retbuf[38][7]_i_4_n_0\,
      I1 => ixRetbufCrc(0),
      I2 => ixRetbufCrc(4),
      I3 => resid(1),
      I4 => resid(2),
      I5 => resid(0),
      O => \retbuf[39][7]_i_6_n_0\
    );
\retbuf[3][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABAAA8"
    )
        port map (
      I0 => \retbuf_reg[1][7]_0\(8),
      I1 => \tixVController_reg_n_0_[7]\,
      I2 => \tixVController_reg_n_0_[5]\,
      I3 => \tixVController_reg_n_0_[6]\,
      I4 => \retbuf[3][0]_i_3_n_0\,
      O => \retbuf[3][0]_i_2_n_0\
    );
\retbuf[3][0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88CCBBFC"
    )
        port map (
      I0 => \retbuf[3][0]_i_4_n_0\,
      I1 => \retbuf[3][7]_i_11_n_0\,
      I2 => \retbuf[3][0]_i_5_n_0\,
      I3 => \retbuf[3][7]_i_13_n_0\,
      I4 => \retbuf[3][0]_i_6_n_0\,
      O => \retbuf[3][0]_i_3_n_0\
    );
\retbuf[3][0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_0\(8),
      I1 => \retbuf[1][7]_i_8_1\(8),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[1][7]_i_8_2\(8),
      I4 => \retbuf[3][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][7]_0\(8),
      O => \retbuf[3][0]_i_4_n_0\
    );
\retbuf[3][0]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(8),
      I1 => \retbuf_reg[1][7]_i_13_2\(8),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[3][7]_i_19_n_0\,
      I4 => \retbuf[0][7]_i_10\(0),
      O => \retbuf[3][0]_i_5_n_0\
    );
\retbuf[3][0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44000CCC44CC0CCC"
    )
        port map (
      I0 => \stateOp_i_3__1_n_0\,
      I1 => \retbuf[3][7]_i_13_n_0\,
      I2 => \retbuf[0][7]_i_20_0\(0),
      I3 => \retbuf[3][7]_i_18_n_0\,
      I4 => \retbuf[3][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_0\(8),
      O => \retbuf[3][0]_i_6_n_0\
    );
\retbuf[3][1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABAAA8"
    )
        port map (
      I0 => \retbuf_reg[1][7]_0\(9),
      I1 => \tixVController_reg_n_0_[7]\,
      I2 => \tixVController_reg_n_0_[5]\,
      I3 => \tixVController_reg_n_0_[6]\,
      I4 => \retbuf[3][1]_i_3_n_0\,
      O => \retbuf[3][1]_i_2_n_0\
    );
\retbuf[3][1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88CCBBFC"
    )
        port map (
      I0 => \retbuf[3][1]_i_4_n_0\,
      I1 => \retbuf[3][7]_i_11_n_0\,
      I2 => \retbuf[3][1]_i_5_n_0\,
      I3 => \retbuf[3][7]_i_13_n_0\,
      I4 => \retbuf[3][1]_i_6_n_0\,
      O => \retbuf[3][1]_i_3_n_0\
    );
\retbuf[3][1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_0\(9),
      I1 => \retbuf[1][7]_i_8_1\(9),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[1][7]_i_8_2\(9),
      I4 => \retbuf[3][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][7]_0\(9),
      O => \retbuf[3][1]_i_4_n_0\
    );
\retbuf[3][1]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(9),
      I1 => \retbuf_reg[1][7]_i_13_2\(9),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[3][7]_i_19_n_0\,
      I4 => \retbuf[0][7]_i_10\(1),
      O => \retbuf[3][1]_i_5_n_0\
    );
\retbuf[3][1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44000CCC44CC0CCC"
    )
        port map (
      I0 => \stateOp_i_3__1_n_0\,
      I1 => \retbuf[3][7]_i_13_n_0\,
      I2 => \retbuf[0][7]_i_20_0\(1),
      I3 => \retbuf[3][7]_i_18_n_0\,
      I4 => \retbuf[3][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][7]_i_13_0\(9),
      O => \retbuf[3][1]_i_6_n_0\
    );
\retbuf[3][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA03F3FAFA03030"
    )
        port map (
      I0 => \retbuf[3][2]_i_4_n_0\,
      I1 => \retbuf_reg[1][7]_0\(10),
      I2 => \retbuf[3][7]_i_11_n_0\,
      I3 => \retbuf[3][2]_i_5_n_0\,
      I4 => \retbuf[3][7]_i_13_n_0\,
      I5 => \retbuf[3][2]_i_6_n_0\,
      O => \retbuf[3][2]_i_2_n_0\
    );
\retbuf[3][2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_0\(10),
      I1 => \retbuf[1][7]_i_8_1\(10),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[1][7]_i_8_2\(10),
      I4 => \retbuf[3][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][7]_0\(10),
      O => \retbuf[3][2]_i_4_n_0\
    );
\retbuf[3][2]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CF77"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_0\(2),
      I1 => \retbuf[3][7]_i_18_n_0\,
      I2 => \retbuf_reg[1][7]_i_13_0\(10),
      I3 => \retbuf[3][7]_i_19_n_0\,
      O => \retbuf[3][2]_i_5_n_0\
    );
\retbuf[3][2]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"505F3F3F"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(10),
      I1 => \retbuf_reg[1][7]_i_13_2\(10),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[0][7]_i_10\(2),
      I4 => \retbuf[3][7]_i_19_n_0\,
      O => \retbuf[3][2]_i_6_n_0\
    );
\retbuf[3][3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA03F3FAFA03030"
    )
        port map (
      I0 => \retbuf[3][3]_i_4_n_0\,
      I1 => \retbuf_reg[1][7]_0\(11),
      I2 => \retbuf[3][7]_i_11_n_0\,
      I3 => \retbuf[3][3]_i_5_n_0\,
      I4 => \retbuf[3][7]_i_13_n_0\,
      I5 => \retbuf[3][3]_i_6_n_0\,
      O => \retbuf[3][3]_i_2_n_0\
    );
\retbuf[3][3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_0\(11),
      I1 => \retbuf[1][7]_i_8_1\(11),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[1][7]_i_8_2\(11),
      I4 => \retbuf[3][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][7]_0\(11),
      O => \retbuf[3][3]_i_4_n_0\
    );
\retbuf[3][3]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CF77"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_0\(3),
      I1 => \retbuf[3][7]_i_18_n_0\,
      I2 => \retbuf_reg[1][7]_i_13_0\(11),
      I3 => \retbuf[3][7]_i_19_n_0\,
      O => \retbuf[3][3]_i_5_n_0\
    );
\retbuf[3][3]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"505F3F3F"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(11),
      I1 => \retbuf_reg[1][7]_i_13_2\(11),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[0][7]_i_10\(3),
      I4 => \retbuf[3][7]_i_19_n_0\,
      O => \retbuf[3][3]_i_6_n_0\
    );
\retbuf[3][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABAAA8"
    )
        port map (
      I0 => \retbuf_reg[1][7]_0\(12),
      I1 => \tixVController_reg_n_0_[7]\,
      I2 => \tixVController_reg_n_0_[5]\,
      I3 => \tixVController_reg_n_0_[6]\,
      I4 => \retbuf[3][4]_i_3_n_0\,
      O => \retbuf[3][4]_i_2_n_0\
    );
\retbuf[3][4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBFCBBFC88CCBBFC"
    )
        port map (
      I0 => \retbuf[3][4]_i_4_n_0\,
      I1 => \retbuf[3][7]_i_11_n_0\,
      I2 => \retbuf[3][4]_i_5_n_0\,
      I3 => \retbuf[3][7]_i_13_n_0\,
      I4 => \retbuf[3][5]_i_7_n_0\,
      I5 => \retbuf[3][4]_i_6_n_0\,
      O => \retbuf[3][4]_i_3_n_0\
    );
\retbuf[3][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_0\(12),
      I1 => \retbuf[1][7]_i_8_1\(12),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[1][7]_i_8_2\(12),
      I4 => \retbuf[3][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][7]_0\(12),
      O => \retbuf[3][4]_i_4_n_0\
    );
\retbuf[3][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(12),
      I1 => \retbuf_reg[1][7]_i_13_2\(12),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[3][7]_i_19_n_0\,
      I4 => \retbuf[0][7]_i_10\(4),
      O => \retbuf[3][4]_i_5_n_0\
    );
\retbuf[3][4]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FAC00AC"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_0\(12),
      I1 => \retbuf[0][7]_i_20_1\(0),
      I2 => \retbuf[3][7]_i_19_n_0\,
      I3 => \retbuf[3][7]_i_18_n_0\,
      I4 => \retbuf[0][7]_i_20_0\(4),
      O => \retbuf[3][4]_i_6_n_0\
    );
\retbuf[3][5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => resid(0),
      I3 => \retbuf[3][7]_i_15_n_0\,
      O => \retbuf[3][5]_i_2_n_0\
    );
\retbuf[3][5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABAAA8"
    )
        port map (
      I0 => \retbuf_reg[1][7]_0\(13),
      I1 => \tixVController_reg_n_0_[7]\,
      I2 => \tixVController_reg_n_0_[5]\,
      I3 => \tixVController_reg_n_0_[6]\,
      I4 => \retbuf[3][5]_i_4_n_0\,
      O => \retbuf[3][5]_i_3_n_0\
    );
\retbuf[3][5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBFCBBFC88CCBBFC"
    )
        port map (
      I0 => \retbuf[3][5]_i_5_n_0\,
      I1 => \retbuf[3][7]_i_11_n_0\,
      I2 => \retbuf[3][5]_i_6_n_0\,
      I3 => \retbuf[3][7]_i_13_n_0\,
      I4 => \retbuf[3][5]_i_7_n_0\,
      I5 => \retbuf[3][5]_i_8_n_0\,
      O => \retbuf[3][5]_i_4_n_0\
    );
\retbuf[3][5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_0\(13),
      I1 => \retbuf[1][7]_i_8_1\(13),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[1][7]_i_8_2\(13),
      I4 => \retbuf[3][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][7]_0\(13),
      O => \retbuf[3][5]_i_5_n_0\
    );
\retbuf[3][5]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFC0A0C0"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(13),
      I1 => \retbuf_reg[1][7]_i_13_2\(13),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[3][7]_i_19_n_0\,
      I4 => \retbuf[0][7]_i_10\(5),
      O => \retbuf[3][5]_i_6_n_0\
    );
\retbuf[3][5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFDFFC3FFCF1FF"
    )
        port map (
      I0 => \stateOp_i_3__1_n_0\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \tixVController_reg_n_0_[3]\,
      I5 => \tixVController_reg_n_0_[4]\,
      O => \retbuf[3][5]_i_7_n_0\
    );
\retbuf[3][5]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FAC00AC"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_0\(13),
      I1 => \retbuf[0][7]_i_20_1\(1),
      I2 => \retbuf[3][7]_i_19_n_0\,
      I3 => \retbuf[3][7]_i_18_n_0\,
      I4 => \retbuf[0][7]_i_20_0\(5),
      O => \retbuf[3][5]_i_8_n_0\
    );
\retbuf[3][6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA03F3FAFA03030"
    )
        port map (
      I0 => \retbuf[3][6]_i_4_n_0\,
      I1 => \retbuf_reg[1][7]_0\(14),
      I2 => \retbuf[3][7]_i_11_n_0\,
      I3 => \retbuf[3][6]_i_5_n_0\,
      I4 => \retbuf[3][7]_i_13_n_0\,
      I5 => \retbuf[3][6]_i_6_n_0\,
      O => \retbuf[3][6]_i_2_n_0\
    );
\retbuf[3][6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_0\(14),
      I1 => \retbuf[1][7]_i_8_1\(14),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[1][7]_i_8_2\(14),
      I4 => \retbuf[3][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][7]_0\(14),
      O => \retbuf[3][6]_i_4_n_0\
    );
\retbuf[3][6]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03440377"
    )
        port map (
      I0 => \retbuf[0][7]_i_20_0\(6),
      I1 => \retbuf[3][7]_i_18_n_0\,
      I2 => \retbuf_reg[1][7]_i_13_0\(14),
      I3 => \retbuf[3][7]_i_19_n_0\,
      I4 => \retbuf[0][7]_i_20_1\(2),
      O => \retbuf[3][6]_i_5_n_0\
    );
\retbuf[3][6]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"505F3F3F"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(14),
      I1 => \retbuf_reg[1][7]_i_13_2\(14),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[0][7]_i_10\(6),
      I4 => \retbuf[3][7]_i_19_n_0\,
      O => \retbuf[3][6]_i_6_n_0\
    );
\retbuf[3][7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_0\(15),
      I1 => \retbuf[1][7]_i_8_1\(15),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[1][7]_i_8_2\(15),
      I4 => \retbuf[3][7]_i_19_n_0\,
      I5 => \retbuf_reg[1][7]_0\(15),
      O => \retbuf[3][7]_i_10_n_0\
    );
\retbuf[3][7]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F6FBFAE9"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \tixVController_reg_n_0_[0]\,
      O => \retbuf[3][7]_i_11_n_0\
    );
\retbuf[3][7]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F053FF53"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_0\(15),
      I1 => \retbuf[0][7]_i_20_1\(3),
      I2 => \retbuf[3][7]_i_19_n_0\,
      I3 => \retbuf[3][7]_i_18_n_0\,
      I4 => \retbuf[0][7]_i_20_0\(7),
      O => \retbuf[3][7]_i_12_n_0\
    );
\retbuf[3][7]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFEFFFF9"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \tixVController_reg_n_0_[4]\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[1]\,
      O => \retbuf[3][7]_i_13_n_0\
    );
\retbuf[3][7]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"505F3F3F"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(15),
      I1 => \retbuf_reg[1][7]_i_13_2\(15),
      I2 => \retbuf[3][7]_i_18_n_0\,
      I3 => \retbuf[0][7]_i_10\(7),
      I4 => \retbuf[3][7]_i_19_n_0\,
      O => \retbuf[3][7]_i_14_n_0\
    );
\retbuf[3][7]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => ixRetbufCrc(2),
      I1 => ixRetbufCrc(4),
      I2 => ixRetbufCrc(3),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(1),
      I5 => ixRetbufCrc(0),
      O => \retbuf[3][7]_i_15_n_0\
    );
\retbuf[3][7]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAEAAAFAFFFFA"
    )
        port map (
      I0 => \retbuf[3][7]_i_20_n_0\,
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \tixVController_reg_n_0_[3]\,
      I5 => \tixVController_reg_n_0_[0]\,
      O => \retbuf[3][7]_i_16_n_0\
    );
\retbuf[3][7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CE"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \ixRetbufCrc[5]_i_4_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      O => \retbuf[3][7]_i_17_n_0\
    );
\retbuf[3][7]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000A0162"
    )
        port map (
      I0 => \tixVController_reg_n_0_[1]\,
      I1 => \tixVController_reg_n_0_[4]\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \tixVController_reg_n_0_[3]\,
      I4 => \tixVController_reg_n_0_[0]\,
      O => \retbuf[3][7]_i_18_n_0\
    );
\retbuf[3][7]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"42112010"
    )
        port map (
      I0 => \tixVController_reg_n_0_[4]\,
      I1 => \tixVController_reg_n_0_[3]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[2]\,
      O => \retbuf[3][7]_i_19_n_0\
    );
\retbuf[3][7]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000000"
    )
        port map (
      I0 => \tixVController_reg_n_0_[2]\,
      I1 => \tixVController_reg_n_0_[3]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => \resid[2]_i_25_n_0\,
      I5 => targetNotSteady_i_3_n_0,
      O => \retbuf[3][7]_i_20_n_0\
    );
\retbuf[3][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFDFDFFFDF"
    )
        port map (
      I0 => \retbuf[1][7]_i_12_n_0\,
      I1 => ixRetbufCrc(4),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(0),
      I4 => resid(0),
      I5 => ixRetbufCrc(2),
      O => \retbuf[3][7]_i_3_n_0\
    );
\retbuf[3][7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => resid(1),
      I2 => resid(2),
      I3 => \^stateop_reg[5]_0\(4),
      O => \retbuf[3][7]_i_4_n_0\
    );
\retbuf[3][7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFD00FFFFFFFF"
    )
        port map (
      I0 => \retbuf[3][7]_i_8_n_0\,
      I1 => \retbuf[3][7]_i_9_n_0\,
      I2 => \ixRetbufCrc[4]_i_4_n_0\,
      I3 => \resid[0]_i_4_n_0\,
      I4 => \^stateop_reg[5]_0\(4),
      I5 => \^stateop_reg[5]_0\(5),
      O => \retbuf[3][7]_i_5_n_0\
    );
\retbuf[3][7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA03F3FAFA03030"
    )
        port map (
      I0 => \retbuf[3][7]_i_10_n_0\,
      I1 => \retbuf_reg[1][7]_0\(15),
      I2 => \retbuf[3][7]_i_11_n_0\,
      I3 => \retbuf[3][7]_i_12_n_0\,
      I4 => \retbuf[3][7]_i_13_n_0\,
      I5 => \retbuf[3][7]_i_14_n_0\,
      O => \retbuf[3][7]_i_6_n_0\
    );
\retbuf[3][7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFE000200"
    )
        port map (
      I0 => \stateCorecfg[2]_i_6_n_0\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[3]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \retbuf[0][7]_i_23_n_0\,
      I5 => \retbuf[3][7]_i_16_n_0\,
      O => \retbuf[3][7]_i_8_n_0\
    );
\retbuf[3][7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002320000323230"
    )
        port map (
      I0 => \retbuf[3][7]_i_17_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \tixVController_reg_n_0_[3]\,
      I4 => \tixVController_reg_n_0_[1]\,
      I5 => targetNotSteady_i_3_n_0,
      O => \retbuf[3][7]_i_9_n_0\
    );
\retbuf[4][0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5DFF0C0055550000"
    )
        port map (
      I0 => \retbuf[4][7]_i_6_n_0\,
      I1 => \retbuf_reg[1][7]_i_13_2\(0),
      I2 => \retbuf[0][0]_i_3_n_0\,
      I3 => \retbuf[4][7]_i_13_n_0\,
      I4 => \retbuf_reg[1][7]_0\(0),
      I5 => \tixVController_reg_n_0_[3]\,
      O => \retbuf[4][0]_i_3_n_0\
    );
\retbuf[4][0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3320332333233323"
    )
        port map (
      I0 => \retbuf[4][0]_i_5_n_0\,
      I1 => \retbuf[4][0]_i_6_n_0\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \retbuf[4][7]_i_16_n_0\,
      I5 => \retbuf_reg[1][7]_0\(0),
      O => \retbuf[4][0]_i_4_n_0\
    );
\retbuf[4][0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3355000F3355FF0F"
    )
        port map (
      I0 => \retbuf[4][7]_i_12_0\(20),
      I1 => \retbuf[1][7]_i_8_2\(0),
      I2 => \retbuf_reg[1][7]_i_13_0\(0),
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[0]\,
      I5 => \retbuf[1][7]_i_8_1\(0),
      O => \retbuf[4][0]_i_5_n_0\
    );
\retbuf[4][0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020C00000200000"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(0),
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \retbuf[1][7]_i_8_0\(0),
      O => \retbuf[4][0]_i_6_n_0\
    );
\retbuf[4][1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7300FFFF40004000"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf[4][7]_i_13_n_0\,
      I2 => \retbuf_reg[1][7]_i_13_2\(1),
      I3 => \tixVController_reg_n_0_[3]\,
      I4 => \retbuf[4][7]_i_6_n_0\,
      I5 => \retbuf_reg[1][7]_0\(1),
      O => \retbuf[4][1]_i_3_n_0\
    );
\retbuf[4][1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3333333322220333"
    )
        port map (
      I0 => \retbuf[4][1]_i_5_n_0\,
      I1 => \retbuf[4][1]_i_6_n_0\,
      I2 => \retbuf_reg[1][7]_0\(1),
      I3 => \retbuf[4][7]_i_16_n_0\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \tixVController_reg_n_0_[1]\,
      O => \retbuf[4][1]_i_4_n_0\
    );
\retbuf[4][1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3355000F3355FF0F"
    )
        port map (
      I0 => \retbuf[4][7]_i_12_0\(21),
      I1 => \retbuf[1][7]_i_8_2\(1),
      I2 => \retbuf_reg[1][7]_i_13_0\(1),
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[0]\,
      I5 => \retbuf[1][7]_i_8_1\(1),
      O => \retbuf[4][1]_i_5_n_0\
    );
\retbuf[4][1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020C00000200000"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(1),
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \retbuf[1][7]_i_8_0\(1),
      O => \retbuf[4][1]_i_6_n_0\
    );
\retbuf[4][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7300FFFF40004000"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf[4][7]_i_13_n_0\,
      I2 => \retbuf_reg[1][7]_i_13_2\(2),
      I3 => \tixVController_reg_n_0_[3]\,
      I4 => \retbuf[4][7]_i_6_n_0\,
      I5 => \retbuf_reg[1][7]_0\(2),
      O => \retbuf[4][2]_i_3_n_0\
    );
\retbuf[4][2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3333333322220333"
    )
        port map (
      I0 => \retbuf[4][2]_i_5_n_0\,
      I1 => \retbuf[4][2]_i_6_n_0\,
      I2 => \retbuf_reg[1][7]_0\(2),
      I3 => \retbuf[4][7]_i_16_n_0\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \tixVController_reg_n_0_[1]\,
      O => \retbuf[4][2]_i_4_n_0\
    );
\retbuf[4][2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3355000F3355FF0F"
    )
        port map (
      I0 => \retbuf[4][7]_i_12_0\(22),
      I1 => \retbuf[1][7]_i_8_2\(2),
      I2 => \retbuf_reg[1][7]_i_13_0\(2),
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[0]\,
      I5 => \retbuf[1][7]_i_8_1\(2),
      O => \retbuf[4][2]_i_5_n_0\
    );
\retbuf[4][2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020C00000200000"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(2),
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \retbuf[1][7]_i_8_0\(2),
      O => \retbuf[4][2]_i_6_n_0\
    );
\retbuf[4][3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7300FFFF40004000"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \retbuf[4][7]_i_13_n_0\,
      I2 => \retbuf_reg[1][7]_i_13_2\(3),
      I3 => \tixVController_reg_n_0_[3]\,
      I4 => \retbuf[4][7]_i_6_n_0\,
      I5 => \retbuf_reg[1][7]_0\(3),
      O => \retbuf[4][3]_i_3_n_0\
    );
\retbuf[4][3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3333333322220333"
    )
        port map (
      I0 => \retbuf[4][3]_i_5_n_0\,
      I1 => \retbuf[4][3]_i_6_n_0\,
      I2 => \retbuf_reg[1][7]_0\(3),
      I3 => \retbuf[4][7]_i_16_n_0\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \tixVController_reg_n_0_[1]\,
      O => \retbuf[4][3]_i_4_n_0\
    );
\retbuf[4][3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3355000F3355FF0F"
    )
        port map (
      I0 => \retbuf[4][7]_i_12_0\(23),
      I1 => \retbuf[1][7]_i_8_2\(3),
      I2 => \retbuf_reg[1][7]_i_13_0\(3),
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[0]\,
      I5 => \retbuf[1][7]_i_8_1\(3),
      O => \retbuf[4][3]_i_5_n_0\
    );
\retbuf[4][3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020C00000200000"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(3),
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \retbuf[1][7]_i_8_0\(3),
      O => \retbuf[4][3]_i_6_n_0\
    );
\retbuf[4][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF00F1F1"
    )
        port map (
      I0 => \retbuf[4][4]_i_3_n_0\,
      I1 => \retbuf[4][6]_i_5_n_0\,
      I2 => \retbuf[4][4]_i_4_n_0\,
      I3 => \retbuf_reg[1][7]_0\(4),
      I4 => \retbuf[0][0]_i_3_n_0\,
      I5 => \retbuf[0][6]_i_2__0_n_0\,
      O => \retbuf[4][4]_i_2_n_0\
    );
\retbuf[4][4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFF47"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(4),
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \stateOp_i_3__1_n_0\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[4]\,
      I5 => \retbuf[4][4]_i_5_n_0\,
      O => \retbuf[4][4]_i_3_n_0\
    );
\retbuf[4][4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFB080"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_2\(4),
      I1 => \retbuf[4][7]_i_13_n_0\,
      I2 => \tixVController_reg_n_0_[3]\,
      I3 => \retbuf_reg[1][7]_0\(4),
      I4 => \retbuf[4][4]_i_6_n_0\,
      O => \retbuf[4][4]_i_4_n_0\
    );
\retbuf[4][4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8E8A828"
    )
        port map (
      I0 => \retbuf_reg[1][7]_0\(4),
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \retbuf[1][7]_i_8_0\(4),
      O => \retbuf[4][4]_i_5_n_0\
    );
\retbuf[4][4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EAFAEAAA"
    )
        port map (
      I0 => \retbuf[4][4]_i_7_n_0\,
      I1 => \retbuf[1][7]_i_8_2\(4),
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \retbuf[4][7]_i_12_0\(24),
      I5 => \retbuf[4][4]_i_8_n_0\,
      O => \retbuf[4][4]_i_6_n_0\
    );
\retbuf[4][4]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3333BBF3"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_1\(4),
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \retbuf_reg[1][7]_i_13_0\(4),
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[0]\,
      O => \retbuf[4][4]_i_7_n_0\
    );
\retbuf[4][4]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF002F"
    )
        port map (
      I0 => \tixVController_reg_n_0_[4]\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \retbuf_reg[1][7]_0\(4),
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \tixVController_reg_n_0_[3]\,
      I5 => \tixVController_reg_n_0_[1]\,
      O => \retbuf[4][4]_i_8_n_0\
    );
\retbuf[4][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF00F1F1"
    )
        port map (
      I0 => \retbuf[4][5]_i_3_n_0\,
      I1 => \retbuf[4][6]_i_5_n_0\,
      I2 => \retbuf[4][5]_i_4_n_0\,
      I3 => \retbuf_reg[1][7]_0\(5),
      I4 => \retbuf[0][0]_i_3_n_0\,
      I5 => \retbuf[0][6]_i_2__0_n_0\,
      O => \retbuf[4][5]_i_2_n_0\
    );
\retbuf[4][5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFF47"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(5),
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \stateOp_i_3__1_n_0\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[4]\,
      I5 => \retbuf[4][5]_i_5_n_0\,
      O => \retbuf[4][5]_i_3_n_0\
    );
\retbuf[4][5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFB080"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_2\(5),
      I1 => \retbuf[4][7]_i_13_n_0\,
      I2 => \tixVController_reg_n_0_[3]\,
      I3 => \retbuf_reg[1][7]_0\(5),
      I4 => \retbuf[4][5]_i_6_n_0\,
      O => \retbuf[4][5]_i_4_n_0\
    );
\retbuf[4][5]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8E8A828"
    )
        port map (
      I0 => \retbuf_reg[1][7]_0\(5),
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \retbuf[1][7]_i_8_0\(5),
      O => \retbuf[4][5]_i_5_n_0\
    );
\retbuf[4][5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EAFAEAAA"
    )
        port map (
      I0 => \retbuf[4][5]_i_7_n_0\,
      I1 => \retbuf[1][7]_i_8_2\(5),
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \retbuf[4][7]_i_12_0\(25),
      I5 => \retbuf[4][5]_i_8_n_0\,
      O => \retbuf[4][5]_i_6_n_0\
    );
\retbuf[4][5]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3333F3BB"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_0\(5),
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \retbuf[1][7]_i_8_1\(5),
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[0]\,
      O => \retbuf[4][5]_i_7_n_0\
    );
\retbuf[4][5]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF002F"
    )
        port map (
      I0 => \tixVController_reg_n_0_[4]\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \retbuf_reg[1][7]_0\(5),
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \tixVController_reg_n_0_[3]\,
      I5 => \tixVController_reg_n_0_[1]\,
      O => \retbuf[4][5]_i_8_n_0\
    );
\retbuf[4][6]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF002F"
    )
        port map (
      I0 => \tixVController_reg_n_0_[4]\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \retbuf_reg[1][7]_0\(6),
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \tixVController_reg_n_0_[3]\,
      I5 => \tixVController_reg_n_0_[1]\,
      O => \retbuf[4][6]_i_10_n_0\
    );
\retbuf[4][6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF00F1F1"
    )
        port map (
      I0 => \retbuf[4][6]_i_4_n_0\,
      I1 => \retbuf[4][6]_i_5_n_0\,
      I2 => \retbuf[4][6]_i_6_n_0\,
      I3 => \retbuf_reg[1][7]_0\(6),
      I4 => \retbuf[0][0]_i_3_n_0\,
      I5 => \retbuf[0][6]_i_2__0_n_0\,
      O => \retbuf[4][6]_i_2_n_0\
    );
\retbuf[4][6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555515"
    )
        port map (
      I0 => \retbuf[16][5]_i_2_n_0\,
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(0),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(3),
      I5 => \retbuf[2][7]_i_7_n_0\,
      O => \retbuf[4][6]_i_3_n_0\
    );
\retbuf[4][6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFF47"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_1\(6),
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \stateOp_i_3__1_n_0\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[4]\,
      I5 => \retbuf[4][6]_i_7_n_0\,
      O => \retbuf[4][6]_i_4_n_0\
    );
\retbuf[4][6]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \tixVController_reg_n_0_[1]\,
      O => \retbuf[4][6]_i_5_n_0\
    );
\retbuf[4][6]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFB080"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_2\(6),
      I1 => \retbuf[4][7]_i_13_n_0\,
      I2 => \tixVController_reg_n_0_[3]\,
      I3 => \retbuf_reg[1][7]_0\(6),
      I4 => \retbuf[4][6]_i_8_n_0\,
      O => \retbuf[4][6]_i_6_n_0\
    );
\retbuf[4][6]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFF02000"
    )
        port map (
      I0 => \retbuf[1][7]_i_8_0\(6),
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \retbuf_reg[1][7]_0\(6),
      O => \retbuf[4][6]_i_7_n_0\
    );
\retbuf[4][6]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EAFAEAAA"
    )
        port map (
      I0 => \retbuf[4][6]_i_9_n_0\,
      I1 => \retbuf[1][7]_i_8_2\(6),
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \retbuf[4][7]_i_12_0\(26),
      I5 => \retbuf[4][6]_i_10_n_0\,
      O => \retbuf[4][6]_i_8_n_0\
    );
\retbuf[4][6]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3333F3BB"
    )
        port map (
      I0 => \retbuf_reg[1][7]_i_13_0\(6),
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \retbuf[1][7]_i_8_1\(6),
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[0]\,
      O => \retbuf[4][6]_i_9_n_0\
    );
\retbuf[4][7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0322000000220000"
    )
        port map (
      I0 => targetNotSteady_i_3_n_0,
      I1 => \tixVController_reg_n_0_[3]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \stateOp_i_3__1_n_0\,
      O => \retbuf[4][7]_i_10_n_0\
    );
\retbuf[4][7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1330001113350511"
    )
        port map (
      I0 => \tixVController_reg_n_0_[2]\,
      I1 => \resid[0]_i_4_n_0\,
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \tixVController_reg_n_0_[3]\,
      I5 => \retbuf[3][7]_i_17_n_0\,
      O => \retbuf[4][7]_i_11_n_0\
    );
\retbuf[4][7]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CDCFCDCCCDCCCDCC"
    )
        port map (
      I0 => \retbuf[4][7]_i_14_n_0\,
      I1 => \retbuf[4][7]_i_15_n_0\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \retbuf[4][7]_i_16_n_0\,
      I5 => \retbuf_reg[1][7]_0\(7),
      O => \retbuf[4][7]_i_12_n_0\
    );
\retbuf[4][7]_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \tixVController_reg_n_0_[2]\,
      I1 => \tixVController_reg_n_0_[1]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \tixVController_reg_n_0_[0]\,
      O => \retbuf[4][7]_i_13_n_0\
    );
\retbuf[4][7]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3355000F3355FF0F"
    )
        port map (
      I0 => \retbuf[4][7]_i_12_0\(27),
      I1 => \retbuf[1][7]_i_8_2\(7),
      I2 => \retbuf_reg[1][7]_i_13_0\(7),
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[0]\,
      I5 => \retbuf[1][7]_i_8_1\(7),
      O => \retbuf[4][7]_i_14_n_0\
    );
\retbuf[4][7]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF44F4"
    )
        port map (
      I0 => \retbuf[4][7]_i_17_n_0\,
      I1 => \retbuf[1][7]_i_8_0\(7),
      I2 => \retbuf_reg[1][7]_i_13_1\(7),
      I3 => \retbuf[4][7]_i_18_n_0\,
      I4 => \tixVController_reg_n_0_[3]\,
      O => \retbuf[4][7]_i_15_n_0\
    );
\retbuf[4][7]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[4]\,
      O => \retbuf[4][7]_i_16_n_0\
    );
\retbuf[4][7]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[1]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \tixVController_reg_n_0_[2]\,
      O => \retbuf[4][7]_i_17_n_0\
    );
\retbuf[4][7]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[2]\,
      I1 => \tixVController_reg_n_0_[4]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[0]\,
      O => \retbuf[4][7]_i_18_n_0\
    );
\retbuf[4][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7777777707777777"
    )
        port map (
      I0 => \retbuf[4][7]_i_9_n_0\,
      I1 => resid(0),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(0),
      I4 => \retbuf[1][7]_i_12_n_0\,
      I5 => \retbuf[2][7]_i_7_n_0\,
      O => \retbuf[4][7]_i_3_n_0\
    );
\retbuf[4][7]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => resid(2),
      I2 => resid(1),
      O => \retbuf[4][7]_i_4_n_0\
    );
\retbuf[4][7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000F000E000E0"
    )
        port map (
      I0 => \retbuf[4][7]_i_10_n_0\,
      I1 => \retbuf[4][7]_i_11_n_0\,
      I2 => \^stateop_reg[5]_0\(5),
      I3 => \^stateop_reg[5]_0\(4),
      I4 => \resid[0]_i_4_n_0\,
      I5 => \ixRetbufCrc[4]_i_4_n_0\,
      O => \retbuf[4][7]_i_5_n_0\
    );
\retbuf[4][7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555501415555"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \tixVController_reg_n_0_[1]\,
      I5 => \tixVController_reg_n_0_[3]\,
      O => \retbuf[4][7]_i_6_n_0\
    );
\retbuf[4][7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAA222A2"
    )
        port map (
      I0 => \retbuf[4][7]_i_12_n_0\,
      I1 => \tixVController_reg_n_0_[3]\,
      I2 => \retbuf_reg[1][7]_0\(7),
      I3 => \retbuf[4][7]_i_13_n_0\,
      I4 => \retbuf_reg[1][7]_i_13_2\(7),
      I5 => \retbuf[0][0]_i_3_n_0\,
      O => \retbuf[4][7]_i_7_n_0\
    );
\retbuf[4][7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => ixRetbufCrc(2),
      I1 => ixRetbufCrc(3),
      I2 => ixRetbufCrc(0),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(1),
      I5 => ixRetbufCrc(4),
      O => \retbuf[4][7]_i_9_n_0\
    );
\retbuf[5][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF470047"
    )
        port map (
      I0 => \retbuf[5][0]_i_3_n_0\,
      I1 => \retbuf[5][5]_i_4_n_0\,
      I2 => \retbuf[5][0]_i_4_n_0\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => vidtrackGetInfoPtr0Seqbuf(8),
      O => \retbuf[5][0]_i_2_n_0\
    );
\retbuf[5][0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => cputrackGetInfoPtr0Seqbuf(8),
      I1 => hshktrackGetInfoPtr0Seqbuf(8),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[5][1]_i_2_0\(8),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => vidtrackGetInfoPtr0Seqbuf(8),
      O => \retbuf[5][0]_i_3_n_0\
    );
\retbuf[5][0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CF44CF77"
    )
        port map (
      I0 => \retbuf[5][7]_i_5_0\(0),
      I1 => \retbuf[5][7]_i_18_n_0\,
      I2 => \retbuf[4][7]_i_12_0\(12),
      I3 => \retbuf[5][7]_i_17_n_0\,
      I4 => \retbuf[5][7]_i_5_1\(0),
      O => \retbuf[5][0]_i_4_n_0\
    );
\retbuf[5][1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF470047"
    )
        port map (
      I0 => \retbuf[5][1]_i_3_n_0\,
      I1 => \retbuf[5][5]_i_4_n_0\,
      I2 => \retbuf[5][1]_i_4_n_0\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => vidtrackGetInfoPtr0Seqbuf(9),
      O => \retbuf[5][1]_i_2_n_0\
    );
\retbuf[5][1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => cputrackGetInfoPtr0Seqbuf(9),
      I1 => hshktrackGetInfoPtr0Seqbuf(9),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[5][1]_i_2_0\(9),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => vidtrackGetInfoPtr0Seqbuf(9),
      O => \retbuf[5][1]_i_3_n_0\
    );
\retbuf[5][1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CF44CF77"
    )
        port map (
      I0 => \retbuf[5][7]_i_5_0\(1),
      I1 => \retbuf[5][7]_i_18_n_0\,
      I2 => \retbuf[4][7]_i_12_0\(13),
      I3 => \retbuf[5][7]_i_17_n_0\,
      I4 => \retbuf[5][7]_i_5_1\(1),
      O => \retbuf[5][1]_i_4_n_0\
    );
\retbuf[5][2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \retbuf[5][2]_i_3_n_0\,
      I4 => \retbuf[5][5]_i_4_n_0\,
      O => \retbuf[5][2]_i_2_n_0\
    );
\retbuf[5][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0AF3030A0AF3F3F"
    )
        port map (
      I0 => \stateOp_i_3__1_n_0\,
      I1 => \retbuf[5][7]_i_5_0\(2),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[4][7]_i_12_0\(14),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => \retbuf[5][7]_i_5_1\(2),
      O => \retbuf[5][2]_i_3_n_0\
    );
\retbuf[5][3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \retbuf[5][3]_i_3_n_0\,
      O => \retbuf[5][3]_i_2_n_0\
    );
\retbuf[5][3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FAFAABFBFFFFABFB"
    )
        port map (
      I0 => \retbuf[5][5]_i_4_n_0\,
      I1 => \retbuf[5][7]_i_5_1\(3),
      I2 => \retbuf[5][7]_i_17_n_0\,
      I3 => \retbuf[4][7]_i_12_0\(15),
      I4 => \retbuf[5][7]_i_18_n_0\,
      I5 => \retbuf[5][7]_i_5_0\(3),
      O => \retbuf[5][3]_i_3_n_0\
    );
\retbuf[5][4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \retbuf[5][4]_i_3_n_0\,
      O => \retbuf[5][4]_i_2_n_0\
    );
\retbuf[5][4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FAFAABFBFFFFABFB"
    )
        port map (
      I0 => \retbuf[5][5]_i_4_n_0\,
      I1 => \retbuf[5][7]_i_5_1\(4),
      I2 => \retbuf[5][7]_i_17_n_0\,
      I3 => \retbuf[4][7]_i_12_0\(16),
      I4 => \retbuf[5][7]_i_18_n_0\,
      I5 => \retbuf[5][7]_i_5_0\(4),
      O => \retbuf[5][4]_i_3_n_0\
    );
\retbuf[5][5]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \retbuf[5][5]_i_3_n_0\,
      I4 => \retbuf[5][5]_i_4_n_0\,
      O => \retbuf[5][5]_i_2__0_n_0\
    );
\retbuf[5][5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \stateOp_i_3__1_n_0\,
      I1 => \retbuf[5][7]_i_5_0\(5),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[4][7]_i_12_0\(17),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => \retbuf[5][7]_i_5_1\(5),
      O => \retbuf[5][5]_i_3_n_0\
    );
\retbuf[5][5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFCEB"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[3]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \tixVController_reg_n_0_[4]\,
      O => \retbuf[5][5]_i_4_n_0\
    );
\retbuf[5][6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \retbuf[5][6]_i_3_n_0\,
      O => \retbuf[5][6]_i_2_n_0\
    );
\retbuf[5][6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FAFAABFBFFFFABFB"
    )
        port map (
      I0 => \retbuf[5][5]_i_4_n_0\,
      I1 => \retbuf[5][7]_i_5_1\(6),
      I2 => \retbuf[5][7]_i_17_n_0\,
      I3 => \retbuf[4][7]_i_12_0\(18),
      I4 => \retbuf[5][7]_i_18_n_0\,
      I5 => \retbuf[5][7]_i_5_0\(6),
      O => \retbuf[5][6]_i_3_n_0\
    );
\retbuf[5][7]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000118"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[3]\,
      I4 => \tixVController_reg_n_0_[4]\,
      O => \retbuf[5][7]_i_10_n_0\
    );
\retbuf[5][7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => ixRetbufCrc(1),
      I1 => ixRetbufCrc(4),
      I2 => ixRetbufCrc(3),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(0),
      I5 => ixRetbufCrc(2),
      O => \retbuf[5][7]_i_11_n_0\
    );
\retbuf[5][7]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FAFAABFBFFFFABFB"
    )
        port map (
      I0 => \retbuf[5][5]_i_4_n_0\,
      I1 => \retbuf[5][7]_i_5_1\(7),
      I2 => \retbuf[5][7]_i_17_n_0\,
      I3 => \retbuf[4][7]_i_12_0\(19),
      I4 => \retbuf[5][7]_i_18_n_0\,
      I5 => \retbuf[5][7]_i_5_0\(7),
      O => \retbuf[5][7]_i_12_n_0\
    );
\retbuf[5][7]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => ixRetbufCrc(1),
      I1 => ixRetbufCrc(4),
      O => \retbuf[5][7]_i_13_n_0\
    );
\retbuf[5][7]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040F04000"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \retbuf[5][7]_i_16_n_0\,
      I5 => \staTixVTrigger[7]_i_3__1_n_0\,
      O => \retbuf[5][7]_i_14_n_0\
    );
\retbuf[5][7]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010110"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[4]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[3]\,
      I4 => \tixVController_reg_n_0_[2]\,
      O => \retbuf[5][7]_i_15_n_0\
    );
\retbuf[5][7]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => \stateOp_i_5__1_n_0\,
      I1 => \tixVCommand_reg_n_0_[1]\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      I3 => \tixVCommand_reg_n_0_[5]\,
      I4 => \tixVCommand_reg_n_0_[4]\,
      O => \retbuf[5][7]_i_16_n_0\
    );
\retbuf[5][7]_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00444100"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \tixVController_reg_n_0_[2]\,
      O => \retbuf[5][7]_i_17_n_0\
    );
\retbuf[5][7]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00114100"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \tixVController_reg_n_0_[2]\,
      O => \retbuf[5][7]_i_18_n_0\
    );
\retbuf[5][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEE2E222E"
    )
        port map (
      I0 => \retbuf[5][7]_i_7_n_0\,
      I1 => \retbuf[5][7]_i_8_n_0\,
      I2 => \retbuf[5][7]_i_9_n_0\,
      I3 => \retbuf[5][7]_i_10_n_0\,
      I4 => \ixRetbufCrc[5]_i_4_n_0\,
      I5 => \retbuf[0][0]_i_3_n_0\,
      O => \retbuf[5][7]_i_3_n_0\
    );
\retbuf[5][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBFBFBFAAAAAAAA"
    )
        port map (
      I0 => \retbuf[1][7]_i_4_n_0\,
      I1 => \retbuf[4][7]_i_4_n_0\,
      I2 => \retbuf[4][7]_i_9_n_0\,
      I3 => resid(0),
      I4 => \retbuf[5][7]_i_11_n_0\,
      I5 => \^stateop_reg[5]_0\(1),
      O => \retbuf[5][7]_i_4_n_0\
    );
\retbuf[5][7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \retbuf[5][7]_i_12_n_0\,
      O => \retbuf[5][7]_i_5_n_0\
    );
\retbuf[5][7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00010000"
    )
        port map (
      I0 => \retbuf[5][7]_i_13_n_0\,
      I1 => ixRetbufCrc(5),
      I2 => ixRetbufCrc(0),
      I3 => ixRetbufCrc(3),
      I4 => ixRetbufCrc(2),
      I5 => \retbuf[16][5]_i_2_n_0\,
      O => \retbuf[5][7]_i_6_n_0\
    );
\retbuf[5][7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404055544045555"
    )
        port map (
      I0 => \retbuf[5][7]_i_14_n_0\,
      I1 => \resid[2]_i_21_n_0\,
      I2 => \retbuf[5][7]_i_10_n_0\,
      I3 => \retbuf[5][7]_i_15_n_0\,
      I4 => \stateOp_i_3__1_n_0\,
      I5 => \retbuf[5][7]_i_16_n_0\,
      O => \retbuf[5][7]_i_7_n_0\
    );
\retbuf[5][7]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40151012"
    )
        port map (
      I0 => \tixVController_reg_n_0_[4]\,
      I1 => \tixVController_reg_n_0_[3]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[2]\,
      O => \retbuf[5][7]_i_8_n_0\
    );
\retbuf[5][7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200020200"
    )
        port map (
      I0 => targetNotSteady_i_3_n_0,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \tixVController_reg_n_0_[3]\,
      I5 => \tixVController_reg_n_0_[2]\,
      O => \retbuf[5][7]_i_9_n_0\
    );
\retbuf[6][0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF470047"
    )
        port map (
      I0 => \retbuf[6][0]_i_3_n_0\,
      I1 => \retbuf[5][5]_i_4_n_0\,
      I2 => \retbuf[6][0]_i_4_n_0\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => vidtrackGetInfoPtr0Seqbuf(0),
      O => \retbuf[6][0]_i_2_n_0\
    );
\retbuf[6][0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => cputrackGetInfoPtr0Seqbuf(0),
      I1 => hshktrackGetInfoPtr0Seqbuf(0),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[5][1]_i_2_0\(0),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => vidtrackGetInfoPtr0Seqbuf(0),
      O => \retbuf[6][0]_i_3_n_0\
    );
\retbuf[6][0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0AF3030A0AF3F3F"
    )
        port map (
      I0 => \stateOp_i_3__1_n_0\,
      I1 => \retbuf[6][7]_i_4_0\(0),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[4][7]_i_12_0\(4),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => \retbuf[6][7]_i_4_1\(0),
      O => \retbuf[6][0]_i_4_n_0\
    );
\retbuf[6][1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF470047"
    )
        port map (
      I0 => \retbuf[6][1]_i_3_n_0\,
      I1 => \retbuf[5][5]_i_4_n_0\,
      I2 => \retbuf[6][1]_i_4_n_0\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => vidtrackGetInfoPtr0Seqbuf(1),
      O => \retbuf[6][1]_i_2_n_0\
    );
\retbuf[6][1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => cputrackGetInfoPtr0Seqbuf(1),
      I1 => hshktrackGetInfoPtr0Seqbuf(1),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[5][1]_i_2_0\(1),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => vidtrackGetInfoPtr0Seqbuf(1),
      O => \retbuf[6][1]_i_3_n_0\
    );
\retbuf[6][1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CF44CF77"
    )
        port map (
      I0 => \retbuf[6][7]_i_4_0\(1),
      I1 => \retbuf[5][7]_i_18_n_0\,
      I2 => \retbuf[4][7]_i_12_0\(5),
      I3 => \retbuf[5][7]_i_17_n_0\,
      I4 => \retbuf[6][7]_i_4_1\(1),
      O => \retbuf[6][1]_i_4_n_0\
    );
\retbuf[6][2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF470047"
    )
        port map (
      I0 => \retbuf[6][2]_i_3_n_0\,
      I1 => \retbuf[5][5]_i_4_n_0\,
      I2 => \retbuf[6][2]_i_4_n_0\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => vidtrackGetInfoPtr0Seqbuf(2),
      O => \retbuf[6][2]_i_2_n_0\
    );
\retbuf[6][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => cputrackGetInfoPtr0Seqbuf(2),
      I1 => hshktrackGetInfoPtr0Seqbuf(2),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[5][1]_i_2_0\(2),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => vidtrackGetInfoPtr0Seqbuf(2),
      O => \retbuf[6][2]_i_3_n_0\
    );
\retbuf[6][2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0AF3030A0AF3F3F"
    )
        port map (
      I0 => \stateOp_i_3__1_n_0\,
      I1 => \retbuf[6][7]_i_4_0\(2),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[4][7]_i_12_0\(6),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => \retbuf[6][7]_i_4_1\(2),
      O => \retbuf[6][2]_i_4_n_0\
    );
\retbuf[6][3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF470047"
    )
        port map (
      I0 => \retbuf[6][3]_i_3_n_0\,
      I1 => \retbuf[5][5]_i_4_n_0\,
      I2 => \retbuf[6][3]_i_4_n_0\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => vidtrackGetInfoPtr0Seqbuf(3),
      O => \retbuf[6][3]_i_2_n_0\
    );
\retbuf[6][3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => cputrackGetInfoPtr0Seqbuf(3),
      I1 => hshktrackGetInfoPtr0Seqbuf(3),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[5][1]_i_2_0\(3),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => vidtrackGetInfoPtr0Seqbuf(3),
      O => \retbuf[6][3]_i_3_n_0\
    );
\retbuf[6][3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CF44CF77"
    )
        port map (
      I0 => \retbuf[6][7]_i_4_0\(3),
      I1 => \retbuf[5][7]_i_18_n_0\,
      I2 => \retbuf[4][7]_i_12_0\(7),
      I3 => \retbuf[5][7]_i_17_n_0\,
      I4 => \retbuf[6][7]_i_4_1\(3),
      O => \retbuf[6][3]_i_4_n_0\
    );
\retbuf[6][4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF470047"
    )
        port map (
      I0 => \retbuf[6][4]_i_3_n_0\,
      I1 => \retbuf[5][5]_i_4_n_0\,
      I2 => \retbuf[6][4]_i_4_n_0\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => vidtrackGetInfoPtr0Seqbuf(4),
      O => \retbuf[6][4]_i_2_n_0\
    );
\retbuf[6][4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => cputrackGetInfoPtr0Seqbuf(4),
      I1 => hshktrackGetInfoPtr0Seqbuf(4),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[5][1]_i_2_0\(4),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => vidtrackGetInfoPtr0Seqbuf(4),
      O => \retbuf[6][4]_i_3_n_0\
    );
\retbuf[6][4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0AF3030A0AF3F3F"
    )
        port map (
      I0 => \stateOp_i_3__1_n_0\,
      I1 => \retbuf[6][7]_i_4_0\(4),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[4][7]_i_12_0\(8),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => \retbuf[6][7]_i_4_1\(4),
      O => \retbuf[6][4]_i_4_n_0\
    );
\retbuf[6][5]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03440377"
    )
        port map (
      I0 => \retbuf[6][7]_i_4_0\(5),
      I1 => \retbuf[5][7]_i_18_n_0\,
      I2 => \retbuf[4][7]_i_12_0\(9),
      I3 => \retbuf[5][7]_i_17_n_0\,
      I4 => \retbuf[6][7]_i_4_1\(5),
      O => \retbuf[6][5]_i_5_n_0\
    );
\retbuf[6][5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => cputrackGetInfoPtr0Seqbuf(5),
      I1 => hshktrackGetInfoPtr0Seqbuf(5),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[5][1]_i_2_0\(5),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => vidtrackGetInfoPtr0Seqbuf(5),
      O => \retbuf[6][5]_i_6_n_0\
    );
\retbuf[6][6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF470047"
    )
        port map (
      I0 => \retbuf[6][6]_i_3_n_0\,
      I1 => \retbuf[5][5]_i_4_n_0\,
      I2 => \retbuf[6][6]_i_4_n_0\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => vidtrackGetInfoPtr0Seqbuf(6),
      O => \retbuf[6][6]_i_2_n_0\
    );
\retbuf[6][6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => cputrackGetInfoPtr0Seqbuf(6),
      I1 => hshktrackGetInfoPtr0Seqbuf(6),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[5][1]_i_2_0\(6),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => vidtrackGetInfoPtr0Seqbuf(6),
      O => \retbuf[6][6]_i_3_n_0\
    );
\retbuf[6][6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0AF3030A0AF3F3F"
    )
        port map (
      I0 => \stateOp_i_3__1_n_0\,
      I1 => \retbuf[6][7]_i_4_0\(6),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[4][7]_i_12_0\(10),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => \retbuf[6][7]_i_4_1\(6),
      O => \retbuf[6][6]_i_4_n_0\
    );
\retbuf[6][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBFBFBFAAAAAAAA"
    )
        port map (
      I0 => \retbuf[1][7]_i_4_n_0\,
      I1 => \retbuf[4][7]_i_4_n_0\,
      I2 => \retbuf[5][7]_i_11_n_0\,
      I3 => resid(0),
      I4 => \retbuf[6][7]_i_6_n_0\,
      I5 => \^stateop_reg[5]_0\(1),
      O => \retbuf[6][7]_i_3_n_0\
    );
\retbuf[6][7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF470047"
    )
        port map (
      I0 => \retbuf[6][7]_i_7_n_0\,
      I1 => \retbuf[5][5]_i_4_n_0\,
      I2 => \retbuf[6][7]_i_8_n_0\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => vidtrackGetInfoPtr0Seqbuf(7),
      O => \retbuf[6][7]_i_4_n_0\
    );
\retbuf[6][7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000008"
    )
        port map (
      I0 => ixRetbufCrc(2),
      I1 => ixRetbufCrc(0),
      I2 => ixRetbufCrc(5),
      I3 => ixRetbufCrc(3),
      I4 => \retbuf[5][7]_i_13_n_0\,
      I5 => \retbuf[16][5]_i_2_n_0\,
      O => \retbuf[6][7]_i_5_n_0\
    );
\retbuf[6][7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => ixRetbufCrc(1),
      I1 => ixRetbufCrc(4),
      I2 => ixRetbufCrc(0),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(3),
      I5 => ixRetbufCrc(2),
      O => \retbuf[6][7]_i_6_n_0\
    );
\retbuf[6][7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => cputrackGetInfoPtr0Seqbuf(7),
      I1 => hshktrackGetInfoPtr0Seqbuf(7),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[5][1]_i_2_0\(7),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => vidtrackGetInfoPtr0Seqbuf(7),
      O => \retbuf[6][7]_i_7_n_0\
    );
\retbuf[6][7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0AF3030A0AF3F3F"
    )
        port map (
      I0 => \stateOp_i_3__1_n_0\,
      I1 => \retbuf[6][7]_i_4_0\(7),
      I2 => \retbuf[5][7]_i_18_n_0\,
      I3 => \retbuf[4][7]_i_12_0\(11),
      I4 => \retbuf[5][7]_i_17_n_0\,
      I5 => \retbuf[6][7]_i_4_1\(7),
      O => \retbuf[6][7]_i_8_n_0\
    );
\retbuf[7][3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \stateOp_i_3__1_n_0\,
      I1 => \ixRetbufCrc[5]_i_3_n_0\,
      O => \retbuf[7][3]_i_2_n_0\
    );
\retbuf[7][7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDFDFDF"
    )
        port map (
      I0 => \retbuf[4][7]_i_4_n_0\,
      I1 => \^stateop_reg[5]_0\(5),
      I2 => \retbuf[6][7]_i_6_n_0\,
      I3 => resid(0),
      I4 => \retbuf[7][7]_i_7_n_0\,
      O => \retbuf[7][7]_i_3_n_0\
    );
\retbuf[7][7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \ixRetbufCrc[5]_i_3_n_0\,
      I1 => \ixRetbufCrc[5]_i_4_n_0\,
      O => \retbuf[7][7]_i_4_n_0\
    );
\retbuf[7][7]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => \retbuf[6][7]_i_6_n_0\,
      I1 => resid(1),
      I2 => resid(2),
      I3 => resid(0),
      O => \retbuf[7][7]_i_6_n_0\
    );
\retbuf[7][7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => ixRetbufCrc(3),
      I1 => ixRetbufCrc(5),
      I2 => ixRetbufCrc(4),
      I3 => ixRetbufCrc(1),
      I4 => ixRetbufCrc(0),
      I5 => ixRetbufCrc(2),
      O => \retbuf[7][7]_i_7_n_0\
    );
\retbuf[8][7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEFEFEFEEEFEEEF"
    )
        port map (
      I0 => \retbuf[8][7]_i_12_n_0\,
      I1 => \stateOp[5]_i_43_n_0\,
      I2 => \retbuf[8][7]_i_13_n_0\,
      I3 => \stateOp[5]_i_40_n_0\,
      I4 => \stateOp[5]_i_39_n_0\,
      I5 => \retbuf[8][7]_i_14_n_0\,
      O => \retbuf[8][7]_i_10_n_0\
    );
\retbuf[8][7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \stateOp[5]_i_36_n_0\,
      I1 => \stateOp[5]_i_24_n_0\,
      I2 => \stateOp[5]_i_23_n_0\,
      O => \retbuf[8][7]_i_11_n_0\
    );
\retbuf[8][7]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A0A0A0A0A0A0A3"
    )
        port map (
      I0 => ackInvHshktrackSelect,
      I1 => \retbuf[8][7]_i_15_n_0\,
      I2 => \retbuf[8][7]_i_16_n_0\,
      I3 => \retbuf[8][7]_i_17_n_0\,
      I4 => \stateOp[5]_i_66_n_0\,
      I5 => \resid[1]_i_14_n_0\,
      O => \retbuf[8][7]_i_12_n_0\
    );
\retbuf[8][7]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4F4F4F4F4F4F444"
    )
        port map (
      I0 => ackInvMemtrackClearMask,
      I1 => \retbuf[8][7]_i_18_n_0\,
      I2 => \staTixVTrigger[7]_i_5_n_0\,
      I3 => \i2cRegaddr[15]_i_11_n_0\,
      I4 => \^tixvcommand_reg[0]_0\,
      I5 => targetNotSteady_i_3_n_0,
      O => \retbuf[8][7]_i_13_n_0\
    );
\retbuf[8][7]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF005454"
    )
        port map (
      I0 => \retbuf[8][7]_i_19_n_0\,
      I1 => \retbuf[8][7]_i_20_n_0\,
      I2 => \retbuf[8][7]_i_21_n_0\,
      I3 => ackInvMemtrackSetMask,
      I4 => \stateOp[5]_i_66_n_0\,
      I5 => \retbuf[8][7]_i_22_n_0\,
      O => \retbuf[8][7]_i_14_n_0\
    );
\retbuf[8][7]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040004000404444"
    )
        port map (
      I0 => \resid[1]_i_21_n_0\,
      I1 => \resid[2]_i_25_n_0\,
      I2 => \retbuf[8][7]_i_23_n_0\,
      I3 => \stateCorecfg[2]_i_8_n_0\,
      I4 => \stateOp_i_5__1_n_0\,
      I5 => \retbuf[8][7]_i_24_n_0\,
      O => \retbuf[8][7]_i_15_n_0\
    );
\retbuf[8][7]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => \staTixVTrigger[7]_i_3__1_n_0\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \stateOp[5]_i_76_n_0\,
      I5 => \stateOp_i_5__1_n_0\,
      O => \retbuf[8][7]_i_16_n_0\
    );
\retbuf[8][7]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000023"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[1]\,
      I1 => \resid[1]_i_18_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      I3 => \stateOp_i_5__1_n_0\,
      I4 => \retbuf[8][7]_i_25_n_0\,
      I5 => \staTixVTrigger[7]_i_3__1_n_0\,
      O => \retbuf[8][7]_i_17_n_0\
    );
\retbuf[8][7]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \stateOp_i_5__1_n_0\,
      I1 => \ixRetbufCrc[4]_i_5_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \stateOp[5]_i_77_n_0\,
      I5 => \staTixVTrigger[7]_i_3__1_n_0\,
      O => \retbuf[8][7]_i_18_n_0\
    );
\retbuf[8][7]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \resid[1]_i_20_n_0\,
      I1 => \resid[1]_i_21_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      I3 => \ixRetbufCrc[4]_i_5_n_0\,
      I4 => \stateOp_i_5__1_n_0\,
      I5 => ackInvVidtrackSelect,
      O => \retbuf[8][7]_i_19_n_0\
    );
\retbuf[8][7]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFBFF"
    )
        port map (
      I0 => \staTixVTrigger[7]_i_3__1_n_0\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \stateOp[5]_i_76_n_0\,
      I5 => \stateOp_i_5__1_n_0\,
      O => \retbuf[8][7]_i_20_n_0\
    );
\retbuf[8][7]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAAA"
    )
        port map (
      I0 => ackInvVidtrackSet,
      I1 => \stateOp_i_5__1_n_0\,
      I2 => \tixVCommand_reg_n_0_[5]\,
      I3 => \tixVCommand_reg_n_0_[4]\,
      I4 => \tixVCommand_reg_n_0_[1]\,
      I5 => \tixVCommand_reg_n_0_[0]\,
      O => \retbuf[8][7]_i_21_n_0\
    );
\retbuf[8][7]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => \resid[2]_i_24_n_0\,
      I1 => \tixVCommand_reg_n_0_[0]\,
      I2 => \stateOp_i_5__1_n_0\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \stateOp[5]_i_77_n_0\,
      I5 => \staTixVTrigger[7]_i_3__1_n_0\,
      O => \retbuf[8][7]_i_22_n_0\
    );
\retbuf[8][7]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[0]\,
      I1 => \tixVCommand_reg_n_0_[5]\,
      I2 => \tixVCommand_reg_n_0_[4]\,
      I3 => \tixVCommand_reg_n_0_[1]\,
      O => \retbuf[8][7]_i_23_n_0\
    );
\retbuf[8][7]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FDFF"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[1]\,
      I1 => \tixVCommand_reg_n_0_[5]\,
      I2 => \tixVCommand_reg_n_0_[4]\,
      I3 => \tixVCommand_reg_n_0_[0]\,
      O => \retbuf[8][7]_i_24_n_0\
    );
\retbuf[8][7]_i_25\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[1]\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[2]\,
      O => \retbuf[8][7]_i_25_n_0\
    );
\retbuf[8][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010100010001000"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => \^stateop_reg[5]_0\(4),
      I3 => \retbuf[7][7]_i_7_n_0\,
      I4 => resid(0),
      I5 => \retbuf[8][7]_i_9_n_0\,
      O => \retbuf[8][7]_i_4_n_0\
    );
\retbuf[8][7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00800000"
    )
        port map (
      I0 => ixRetbufCrc(2),
      I1 => ixRetbufCrc(0),
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(4),
      I4 => \retbuf[1][7]_i_12_n_0\,
      I5 => \retbuf[16][5]_i_2_n_0\,
      O => \retbuf[8][7]_i_5_n_0\
    );
\retbuf[8][7]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5545"
    )
        port map (
      I0 => \ixRetbufCrc[4]_i_2_n_0\,
      I1 => \tixVCommand_reg_n_0_[0]\,
      I2 => \ixRetbufCrc[5]_i_3_n_0\,
      I3 => \ixRetbufCrc[5]_i_4_n_0\,
      O => \retbuf[8][7]_i_6_n_0\
    );
\retbuf[8][7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0B030B0B"
    )
        port map (
      I0 => \stateOp[5]_i_30_n_0\,
      I1 => \stateOp[5]_i_29_n_0\,
      I2 => \stateOp[5]_i_28_n_0\,
      I3 => \stateOp[5]_i_27_n_0\,
      I4 => \retbuf[8][7]_i_10_n_0\,
      I5 => \stateOp[5]_i_12_n_0\,
      O => \retbuf[8][7]_i_7_n_0\
    );
\retbuf[8][7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55555044"
    )
        port map (
      I0 => \retbuf[8][7]_i_11_n_0\,
      I1 => \stateOp[5]_i_35_n_0\,
      I2 => ackInvCornerConfig,
      I3 => \wordcntLast[0]_i_5_n_0\,
      I4 => \stateOp[5]_i_24_n_0\,
      I5 => \stateOp[5]_i_14_n_0\,
      O => \retbuf[8][7]_i_8_n_0\
    );
\retbuf[8][7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => ixRetbufCrc(3),
      I1 => ixRetbufCrc(0),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(5),
      I4 => ixRetbufCrc(1),
      I5 => ixRetbufCrc(4),
      O => \retbuf[8][7]_i_9_n_0\
    );
\retbuf[9][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDFFFCFFFFFFFF"
    )
        port map (
      I0 => resid(0),
      I1 => \retbuf[5][7]_i_13_n_0\,
      I2 => ixRetbufCrc(5),
      I3 => ixRetbufCrc(2),
      I4 => ixRetbufCrc(0),
      I5 => ixRetbufCrc(3),
      O => \retbuf[9][7]_i_3_n_0\
    );
\retbuf[9][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00010000"
    )
        port map (
      I0 => \retbuf[5][7]_i_13_n_0\,
      I1 => ixRetbufCrc(5),
      I2 => ixRetbufCrc(2),
      I3 => ixRetbufCrc(0),
      I4 => ixRetbufCrc(3),
      I5 => \retbuf[16][5]_i_2_n_0\,
      O => \retbuf[9][7]_i_4_n_0\
    );
\retbuf_reg[0][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_20,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_337,
      Q => \retbuf_reg_n_0_[0][0]\
    );
\retbuf_reg[0][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_20,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_261,
      Q => \retbuf_reg_n_0_[0][1]\
    );
\retbuf_reg[0][1]_i_5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[0][1]_i_6_n_0\,
      I1 => \retbuf[0][1]_i_7_n_0\,
      O => \retbuf_reg[0][1]_i_5_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[0][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_20,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_336,
      Q => \retbuf_reg_n_0_[0][2]\
    );
\retbuf_reg[0][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_20,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_260,
      Q => \retbuf_reg_n_0_[0][3]\
    );
\retbuf_reg[0][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_20,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_259,
      Q => \retbuf_reg_n_0_[0][4]\
    );
\retbuf_reg[0][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_20,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_258,
      Q => \retbuf_reg_n_0_[0][5]\
    );
\retbuf_reg[0][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_20,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_257,
      Q => \retbuf_reg_n_0_[0][6]\
    );
\retbuf_reg[0][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_20,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_256,
      Q => \retbuf_reg_n_0_[0][7]\
    );
\retbuf_reg[10][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_241,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_382,
      Q => \retbuf_reg_n_0_[10][0]\
    );
\retbuf_reg[10][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_241,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_381,
      Q => \retbuf_reg_n_0_[10][1]\
    );
\retbuf_reg[10][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_241,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_380,
      Q => \retbuf_reg_n_0_[10][2]\
    );
\retbuf_reg[10][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_241,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_379,
      Q => \retbuf_reg_n_0_[10][3]\
    );
\retbuf_reg[10][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_241,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_378,
      Q => \retbuf_reg_n_0_[10][4]\
    );
\retbuf_reg[10][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_241,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_377,
      Q => \retbuf_reg_n_0_[10][5]\
    );
\retbuf_reg[10][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_241,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_376,
      Q => \retbuf_reg_n_0_[10][6]\
    );
\retbuf_reg[10][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_241,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_375,
      Q => \retbuf_reg_n_0_[10][7]\
    );
\retbuf_reg[11][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_242,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_266,
      Q => \retbuf_reg_n_0_[11][0]\
    );
\retbuf_reg[11][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_242,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_265,
      Q => \retbuf_reg_n_0_[11][1]\
    );
\retbuf_reg[11][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_242,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_264,
      Q => \retbuf_reg_n_0_[11][2]\
    );
\retbuf_reg[11][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_242,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_263,
      Q => \retbuf_reg_n_0_[11][3]\
    );
\retbuf_reg[11][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_242,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_374,
      Q => \retbuf_reg_n_0_[11][4]\
    );
\retbuf_reg[11][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_242,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_373,
      Q => \retbuf_reg_n_0_[11][5]\
    );
\retbuf_reg[11][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_242,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_372,
      Q => \retbuf_reg_n_0_[11][6]\
    );
\retbuf_reg[11][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_242,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_371,
      Q => \retbuf_reg_n_0_[11][7]\
    );
\retbuf_reg[12][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_243,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_370,
      Q => \retbuf_reg_n_0_[12][0]\
    );
\retbuf_reg[12][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_243,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_369,
      Q => \retbuf_reg_n_0_[12][1]\
    );
\retbuf_reg[12][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_243,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_368,
      Q => \retbuf_reg_n_0_[12][2]\
    );
\retbuf_reg[12][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_243,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_367,
      Q => \retbuf_reg_n_0_[12][3]\
    );
\retbuf_reg[12][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_243,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_366,
      Q => \retbuf_reg_n_0_[12][4]\
    );
\retbuf_reg[12][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_243,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_365,
      Q => \retbuf_reg_n_0_[12][5]\
    );
\retbuf_reg[12][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_243,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_364,
      Q => \retbuf_reg_n_0_[12][6]\
    );
\retbuf_reg[12][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_243,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_363,
      Q => \retbuf_reg_n_0_[12][7]\
    );
\retbuf_reg[13][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_244,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_362,
      Q => \retbuf_reg_n_0_[13][0]\
    );
\retbuf_reg[13][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_244,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_361,
      Q => \retbuf_reg_n_0_[13][1]\
    );
\retbuf_reg[13][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_244,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_360,
      Q => \retbuf_reg_n_0_[13][2]\
    );
\retbuf_reg[13][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_244,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_359,
      Q => \retbuf_reg_n_0_[13][3]\
    );
\retbuf_reg[13][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_244,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_358,
      Q => \retbuf_reg_n_0_[13][4]\
    );
\retbuf_reg[13][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_244,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_357,
      Q => \retbuf_reg_n_0_[13][5]\
    );
\retbuf_reg[13][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_244,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_356,
      Q => \retbuf_reg_n_0_[13][6]\
    );
\retbuf_reg[13][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_244,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_355,
      Q => \retbuf_reg_n_0_[13][7]\
    );
\retbuf_reg[14][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_245,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_354,
      Q => \retbuf_reg_n_0_[14][0]\
    );
\retbuf_reg[14][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_245,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_353,
      Q => \retbuf_reg_n_0_[14][1]\
    );
\retbuf_reg[14][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_245,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_352,
      Q => \retbuf_reg_n_0_[14][2]\
    );
\retbuf_reg[14][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_245,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_351,
      Q => \retbuf_reg_n_0_[14][3]\
    );
\retbuf_reg[14][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_245,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_350,
      Q => \retbuf_reg_n_0_[14][4]\
    );
\retbuf_reg[14][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_245,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_349,
      Q => \retbuf_reg_n_0_[14][5]\
    );
\retbuf_reg[14][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_245,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_348,
      Q => \retbuf_reg_n_0_[14][6]\
    );
\retbuf_reg[14][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_245,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_347,
      Q => \retbuf_reg_n_0_[14][7]\
    );
\retbuf_reg[15][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_246,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_262,
      Q => \retbuf_reg_n_0_[15][0]\
    );
\retbuf_reg[15][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_246,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_344,
      Q => \retbuf_reg_n_0_[15][1]\
    );
\retbuf_reg[15][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_246,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_343,
      Q => \retbuf_reg_n_0_[15][2]\
    );
\retbuf_reg[15][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_246,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_342,
      Q => \retbuf_reg_n_0_[15][3]\
    );
\retbuf_reg[15][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_246,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_341,
      Q => \retbuf_reg_n_0_[15][4]\
    );
\retbuf_reg[15][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_246,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_340,
      Q => \retbuf_reg_n_0_[15][5]\
    );
\retbuf_reg[15][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_246,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_339,
      Q => \retbuf_reg_n_0_[15][6]\
    );
\retbuf_reg[15][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_246,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_338,
      Q => \retbuf_reg_n_0_[15][7]\
    );
\retbuf_reg[16][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_247,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_232,
      Q => \retbuf_reg[16]_65\(0)
    );
\retbuf_reg[16][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_247,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_231,
      Q => \retbuf_reg[16]_65\(1)
    );
\retbuf_reg[16][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_247,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_230,
      Q => \retbuf_reg[16]_65\(2)
    );
\retbuf_reg[16][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_247,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_229,
      Q => \retbuf_reg[16]_65\(3)
    );
\retbuf_reg[16][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_247,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_228,
      Q => \retbuf_reg[16]_65\(4)
    );
\retbuf_reg[16][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_247,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_227,
      Q => \retbuf_reg[16]_65\(5)
    );
\retbuf_reg[16][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_247,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_226,
      Q => \retbuf_reg[16]_65\(6)
    );
\retbuf_reg[16][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_247,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_225,
      Q => \retbuf_reg[16]_65\(7)
    );
\retbuf_reg[17][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_248,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_224,
      Q => \retbuf_reg_n_0_[17][0]\
    );
\retbuf_reg[17][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_248,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_223,
      Q => \retbuf_reg_n_0_[17][1]\
    );
\retbuf_reg[17][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_248,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_222,
      Q => \retbuf_reg_n_0_[17][2]\
    );
\retbuf_reg[17][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_248,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_221,
      Q => \retbuf_reg_n_0_[17][3]\
    );
\retbuf_reg[17][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_248,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_220,
      Q => \retbuf_reg_n_0_[17][4]\
    );
\retbuf_reg[17][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_248,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_219,
      Q => \retbuf_reg_n_0_[17][5]\
    );
\retbuf_reg[17][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_248,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_218,
      Q => \retbuf_reg_n_0_[17][6]\
    );
\retbuf_reg[17][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_248,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_217,
      Q => \retbuf_reg_n_0_[17][7]\
    );
\retbuf_reg[18][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_249,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_216,
      Q => \retbuf_reg_n_0_[18][0]\
    );
\retbuf_reg[18][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_249,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_215,
      Q => \retbuf_reg_n_0_[18][1]\
    );
\retbuf_reg[18][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_249,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_214,
      Q => \retbuf_reg_n_0_[18][2]\
    );
\retbuf_reg[18][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_249,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_213,
      Q => \retbuf_reg_n_0_[18][3]\
    );
\retbuf_reg[18][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_249,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_212,
      Q => \retbuf_reg_n_0_[18][4]\
    );
\retbuf_reg[18][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_249,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_211,
      Q => \retbuf_reg_n_0_[18][5]\
    );
\retbuf_reg[18][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_249,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_210,
      Q => \retbuf_reg_n_0_[18][6]\
    );
\retbuf_reg[18][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_249,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_209,
      Q => \retbuf_reg_n_0_[18][7]\
    );
\retbuf_reg[19][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_250,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_208,
      Q => \retbuf_reg_n_0_[19][0]\
    );
\retbuf_reg[19][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_250,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_207,
      Q => \retbuf_reg_n_0_[19][1]\
    );
\retbuf_reg[19][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_250,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_206,
      Q => \retbuf_reg_n_0_[19][2]\
    );
\retbuf_reg[19][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_250,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_205,
      Q => \retbuf_reg_n_0_[19][3]\
    );
\retbuf_reg[19][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_250,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_204,
      Q => \retbuf_reg_n_0_[19][4]\
    );
\retbuf_reg[19][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_250,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_203,
      Q => \retbuf_reg_n_0_[19][5]\
    );
\retbuf_reg[19][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_250,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_202,
      Q => \retbuf_reg_n_0_[19][6]\
    );
\retbuf_reg[19][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_250,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_201,
      Q => \retbuf_reg_n_0_[19][7]\
    );
\retbuf_reg[1][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_235,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_255,
      Q => \retbuf_reg_n_0_[1][0]\
    );
\retbuf_reg[1][0]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[1][0]_i_5_n_0\,
      I1 => \retbuf[1][0]_i_6_n_0\,
      O => \retbuf_reg[1][0]_i_4_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[1][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_235,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_254,
      Q => \retbuf_reg_n_0_[1][1]\
    );
\retbuf_reg[1][1]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[1][1]_i_5_n_0\,
      I1 => \retbuf[1][1]_i_6_n_0\,
      O => \retbuf_reg[1][1]_i_4_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[1][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_235,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_253,
      Q => \retbuf_reg_n_0_[1][2]\
    );
\retbuf_reg[1][2]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[1][2]_i_5_n_0\,
      I1 => \retbuf[1][2]_i_6_n_0\,
      O => \retbuf_reg[1][2]_i_4_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[1][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_235,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_252,
      Q => \retbuf_reg_n_0_[1][3]\
    );
\retbuf_reg[1][3]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[1][3]_i_5_n_0\,
      I1 => \retbuf[1][3]_i_6_n_0\,
      O => \retbuf_reg[1][3]_i_3_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[1][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_235,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_251,
      Q => \retbuf_reg_n_0_[1][4]\
    );
\retbuf_reg[1][4]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[1][4]_i_5_n_0\,
      I1 => \retbuf[1][4]_i_6_n_0\,
      O => \retbuf_reg[1][4]_i_4_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[1][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_235,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_250,
      Q => \retbuf_reg_n_0_[1][5]\
    );
\retbuf_reg[1][5]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[1][5]_i_5_n_0\,
      I1 => \retbuf[1][5]_i_6_n_0\,
      O => \retbuf_reg[1][5]_i_4_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[1][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_235,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_249,
      Q => \retbuf_reg_n_0_[1][6]\
    );
\retbuf_reg[1][6]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[1][6]_i_5_n_0\,
      I1 => \retbuf[1][6]_i_6_n_0\,
      O => \retbuf_reg[1][6]_i_4_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[1][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_235,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_248,
      Q => \retbuf_reg_n_0_[1][7]\
    );
\retbuf_reg[1][7]_i_13\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[1][7]_i_15_n_0\,
      I1 => \retbuf[1][7]_i_16_n_0\,
      O => \retbuf_reg[1][7]_i_13_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[20][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_251,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_200,
      Q => \retbuf_reg_n_0_[20][0]\
    );
\retbuf_reg[20][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_251,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_199,
      Q => \retbuf_reg_n_0_[20][1]\
    );
\retbuf_reg[20][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_251,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_198,
      Q => \retbuf_reg_n_0_[20][2]\
    );
\retbuf_reg[20][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_251,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_197,
      Q => \retbuf_reg_n_0_[20][3]\
    );
\retbuf_reg[20][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_251,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_196,
      Q => \retbuf_reg_n_0_[20][4]\
    );
\retbuf_reg[20][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_251,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_195,
      Q => \retbuf_reg_n_0_[20][5]\
    );
\retbuf_reg[20][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_251,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_194,
      Q => \retbuf_reg_n_0_[20][6]\
    );
\retbuf_reg[20][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_251,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_193,
      Q => \retbuf_reg_n_0_[20][7]\
    );
\retbuf_reg[21][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_252,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_192,
      Q => \retbuf_reg_n_0_[21][0]\
    );
\retbuf_reg[21][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_252,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_191,
      Q => \retbuf_reg_n_0_[21][1]\
    );
\retbuf_reg[21][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_252,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_190,
      Q => \retbuf_reg_n_0_[21][2]\
    );
\retbuf_reg[21][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_252,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_189,
      Q => \retbuf_reg_n_0_[21][3]\
    );
\retbuf_reg[21][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_252,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_188,
      Q => \retbuf_reg_n_0_[21][4]\
    );
\retbuf_reg[21][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_252,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_187,
      Q => \retbuf_reg_n_0_[21][5]\
    );
\retbuf_reg[21][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_252,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_186,
      Q => \retbuf_reg_n_0_[21][6]\
    );
\retbuf_reg[21][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_252,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_185,
      Q => \retbuf_reg_n_0_[21][7]\
    );
\retbuf_reg[22][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_253,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_184,
      Q => \retbuf_reg_n_0_[22][0]\
    );
\retbuf_reg[22][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_253,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_183,
      Q => \retbuf_reg_n_0_[22][1]\
    );
\retbuf_reg[22][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_253,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_182,
      Q => \retbuf_reg_n_0_[22][2]\
    );
\retbuf_reg[22][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_253,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_181,
      Q => \retbuf_reg_n_0_[22][3]\
    );
\retbuf_reg[22][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_253,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_180,
      Q => \retbuf_reg_n_0_[22][4]\
    );
\retbuf_reg[22][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_253,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_179,
      Q => \retbuf_reg_n_0_[22][5]\
    );
\retbuf_reg[22][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_253,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_178,
      Q => \retbuf_reg_n_0_[22][6]\
    );
\retbuf_reg[22][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_253,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_177,
      Q => \retbuf_reg_n_0_[22][7]\
    );
\retbuf_reg[23][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_254,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_176,
      Q => \retbuf_reg_n_0_[23][0]\
    );
\retbuf_reg[23][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_254,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_175,
      Q => \retbuf_reg_n_0_[23][1]\
    );
\retbuf_reg[23][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_254,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_174,
      Q => \retbuf_reg_n_0_[23][2]\
    );
\retbuf_reg[23][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_254,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_173,
      Q => \retbuf_reg_n_0_[23][3]\
    );
\retbuf_reg[23][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_254,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_172,
      Q => \retbuf_reg_n_0_[23][4]\
    );
\retbuf_reg[23][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_254,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_171,
      Q => \retbuf_reg_n_0_[23][5]\
    );
\retbuf_reg[23][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_254,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_170,
      Q => \retbuf_reg_n_0_[23][6]\
    );
\retbuf_reg[23][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_254,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_169,
      Q => \retbuf_reg_n_0_[23][7]\
    );
\retbuf_reg[24][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_255,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_168,
      Q => \retbuf_reg_n_0_[24][0]\
    );
\retbuf_reg[24][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_255,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_167,
      Q => \retbuf_reg_n_0_[24][1]\
    );
\retbuf_reg[24][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_255,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_166,
      Q => \retbuf_reg_n_0_[24][2]\
    );
\retbuf_reg[24][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_255,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_165,
      Q => \retbuf_reg_n_0_[24][3]\
    );
\retbuf_reg[24][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_255,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_164,
      Q => \retbuf_reg_n_0_[24][4]\
    );
\retbuf_reg[24][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_255,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_163,
      Q => \retbuf_reg_n_0_[24][5]\
    );
\retbuf_reg[24][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_255,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_162,
      Q => \retbuf_reg_n_0_[24][6]\
    );
\retbuf_reg[24][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_255,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_161,
      Q => \retbuf_reg_n_0_[24][7]\
    );
\retbuf_reg[25][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_256,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_160,
      Q => \retbuf_reg_n_0_[25][0]\
    );
\retbuf_reg[25][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_256,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_159,
      Q => \retbuf_reg_n_0_[25][1]\
    );
\retbuf_reg[25][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_256,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_158,
      Q => \retbuf_reg_n_0_[25][2]\
    );
\retbuf_reg[25][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_256,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_157,
      Q => \retbuf_reg_n_0_[25][3]\
    );
\retbuf_reg[25][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_256,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_156,
      Q => \retbuf_reg_n_0_[25][4]\
    );
\retbuf_reg[25][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_256,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_155,
      Q => \retbuf_reg_n_0_[25][5]\
    );
\retbuf_reg[25][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_256,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_154,
      Q => \retbuf_reg_n_0_[25][6]\
    );
\retbuf_reg[25][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_256,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_153,
      Q => \retbuf_reg_n_0_[25][7]\
    );
\retbuf_reg[26][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_257,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_152,
      Q => \retbuf_reg_n_0_[26][0]\
    );
\retbuf_reg[26][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_257,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_151,
      Q => \retbuf_reg_n_0_[26][1]\
    );
\retbuf_reg[26][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_257,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_150,
      Q => \retbuf_reg_n_0_[26][2]\
    );
\retbuf_reg[26][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_257,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_149,
      Q => \retbuf_reg_n_0_[26][3]\
    );
\retbuf_reg[26][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_257,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_148,
      Q => \retbuf_reg_n_0_[26][4]\
    );
\retbuf_reg[26][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_257,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_147,
      Q => \retbuf_reg_n_0_[26][5]\
    );
\retbuf_reg[26][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_257,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_146,
      Q => \retbuf_reg_n_0_[26][6]\
    );
\retbuf_reg[26][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_257,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_145,
      Q => \retbuf_reg_n_0_[26][7]\
    );
\retbuf_reg[27][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_258,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_144,
      Q => \retbuf_reg_n_0_[27][0]\
    );
\retbuf_reg[27][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_258,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_143,
      Q => \retbuf_reg_n_0_[27][1]\
    );
\retbuf_reg[27][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_258,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_142,
      Q => \retbuf_reg_n_0_[27][2]\
    );
\retbuf_reg[27][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_258,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_141,
      Q => \retbuf_reg_n_0_[27][3]\
    );
\retbuf_reg[27][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_258,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_140,
      Q => \retbuf_reg_n_0_[27][4]\
    );
\retbuf_reg[27][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_258,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_139,
      Q => \retbuf_reg_n_0_[27][5]\
    );
\retbuf_reg[27][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_258,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_138,
      Q => \retbuf_reg_n_0_[27][6]\
    );
\retbuf_reg[27][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_258,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_137,
      Q => \retbuf_reg_n_0_[27][7]\
    );
\retbuf_reg[28][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_259,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_136,
      Q => \retbuf_reg_n_0_[28][0]\
    );
\retbuf_reg[28][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_259,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_135,
      Q => \retbuf_reg_n_0_[28][1]\
    );
\retbuf_reg[28][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_259,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_134,
      Q => \retbuf_reg_n_0_[28][2]\
    );
\retbuf_reg[28][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_259,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_133,
      Q => \retbuf_reg_n_0_[28][3]\
    );
\retbuf_reg[28][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_259,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_132,
      Q => \retbuf_reg_n_0_[28][4]\
    );
\retbuf_reg[28][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_259,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_131,
      Q => \retbuf_reg_n_0_[28][5]\
    );
\retbuf_reg[28][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_259,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_130,
      Q => \retbuf_reg_n_0_[28][6]\
    );
\retbuf_reg[28][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_259,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_129,
      Q => \retbuf_reg_n_0_[28][7]\
    );
\retbuf_reg[29][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_260,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_128,
      Q => \retbuf_reg_n_0_[29][0]\
    );
\retbuf_reg[29][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_260,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_127,
      Q => \retbuf_reg_n_0_[29][1]\
    );
\retbuf_reg[29][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_260,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_126,
      Q => \retbuf_reg_n_0_[29][2]\
    );
\retbuf_reg[29][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_260,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_125,
      Q => \retbuf_reg_n_0_[29][3]\
    );
\retbuf_reg[29][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_260,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_124,
      Q => \retbuf_reg_n_0_[29][4]\
    );
\retbuf_reg[29][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_260,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_123,
      Q => \retbuf_reg_n_0_[29][5]\
    );
\retbuf_reg[29][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_260,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_122,
      Q => \retbuf_reg_n_0_[29][6]\
    );
\retbuf_reg[29][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_260,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_121,
      Q => \retbuf_reg_n_0_[29][7]\
    );
\retbuf_reg[2][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_236,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_247,
      Q => \retbuf_reg_n_0_[2][0]\
    );
\retbuf_reg[2][0]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[2][0]_i_5_n_0\,
      I1 => \retbuf[2][0]_i_6_n_0\,
      O => \retbuf_reg[2][0]_i_4_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[2][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_236,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_246,
      Q => \retbuf_reg_n_0_[2][1]\
    );
\retbuf_reg[2][1]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[2][1]_i_5_n_0\,
      I1 => \retbuf[2][1]_i_6_n_0\,
      O => \retbuf_reg[2][1]_i_4_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[2][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_236,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_245,
      Q => \retbuf_reg_n_0_[2][2]\
    );
\retbuf_reg[2][2]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[2][2]_i_5_n_0\,
      I1 => \retbuf[2][2]_i_6_n_0\,
      O => \retbuf_reg[2][2]_i_4_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[2][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_236,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_244,
      Q => \retbuf_reg_n_0_[2][3]\
    );
\retbuf_reg[2][3]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[2][3]_i_5_n_0\,
      I1 => \retbuf[2][3]_i_6_n_0\,
      O => \retbuf_reg[2][3]_i_4_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[2][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_236,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_243,
      Q => \retbuf_reg_n_0_[2][4]\
    );
\retbuf_reg[2][4]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[2][4]_i_5_n_0\,
      I1 => \retbuf[2][4]_i_6_n_0\,
      O => \retbuf_reg[2][4]_i_4_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[2][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_236,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_242,
      Q => \retbuf_reg_n_0_[2][5]\
    );
\retbuf_reg[2][5]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[2][5]_i_5_n_0\,
      I1 => \retbuf[2][5]_i_6_n_0\,
      O => \retbuf_reg[2][5]_i_4_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[2][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_236,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_241,
      Q => \retbuf_reg_n_0_[2][6]\
    );
\retbuf_reg[2][6]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[2][6]_i_5_n_0\,
      I1 => \retbuf[2][6]_i_6_n_0\,
      O => \retbuf_reg[2][6]_i_4_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[2][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_236,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_399,
      Q => \retbuf_reg_n_0_[2][7]\
    );
\retbuf_reg[2][7]_i_8\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[2][7]_i_10_n_0\,
      I1 => \retbuf[2][7]_i_11_n_0\,
      O => \retbuf_reg[2][7]_i_8_n_0\,
      S => \retbuf[0][1]_i_3_n_0\
    );
\retbuf_reg[30][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_261,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_120,
      Q => \retbuf_reg_n_0_[30][0]\
    );
\retbuf_reg[30][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_261,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_119,
      Q => \retbuf_reg_n_0_[30][1]\
    );
\retbuf_reg[30][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_261,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_118,
      Q => \retbuf_reg_n_0_[30][2]\
    );
\retbuf_reg[30][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_261,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_117,
      Q => \retbuf_reg_n_0_[30][3]\
    );
\retbuf_reg[30][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_261,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_116,
      Q => \retbuf_reg_n_0_[30][4]\
    );
\retbuf_reg[30][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_261,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_115,
      Q => \retbuf_reg_n_0_[30][5]\
    );
\retbuf_reg[30][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_261,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_114,
      Q => \retbuf_reg_n_0_[30][6]\
    );
\retbuf_reg[30][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_261,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_113,
      Q => \retbuf_reg_n_0_[30][7]\
    );
\retbuf_reg[31][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_262,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_112,
      Q => \retbuf_reg_n_0_[31][0]\
    );
\retbuf_reg[31][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_262,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_111,
      Q => \retbuf_reg_n_0_[31][1]\
    );
\retbuf_reg[31][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_262,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_110,
      Q => \retbuf_reg_n_0_[31][2]\
    );
\retbuf_reg[31][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_262,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_109,
      Q => \retbuf_reg_n_0_[31][3]\
    );
\retbuf_reg[31][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_262,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_108,
      Q => \retbuf_reg_n_0_[31][4]\
    );
\retbuf_reg[31][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_262,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_107,
      Q => \retbuf_reg_n_0_[31][5]\
    );
\retbuf_reg[31][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_262,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_106,
      Q => \retbuf_reg_n_0_[31][6]\
    );
\retbuf_reg[31][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_262,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_105,
      Q => \retbuf_reg_n_0_[31][7]\
    );
\retbuf_reg[32][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_263,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_104,
      Q => \retbuf_reg_n_0_[32][0]\
    );
\retbuf_reg[32][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_263,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_103,
      Q => \retbuf_reg_n_0_[32][1]\
    );
\retbuf_reg[32][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_263,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_102,
      Q => \retbuf_reg_n_0_[32][2]\
    );
\retbuf_reg[32][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_263,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_101,
      Q => \retbuf_reg_n_0_[32][3]\
    );
\retbuf_reg[32][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_263,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_100,
      Q => \retbuf_reg_n_0_[32][4]\
    );
\retbuf_reg[32][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_263,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_99,
      Q => \retbuf_reg_n_0_[32][5]\
    );
\retbuf_reg[32][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_263,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_98,
      Q => \retbuf_reg_n_0_[32][6]\
    );
\retbuf_reg[32][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_263,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_97,
      Q => \retbuf_reg_n_0_[32][7]\
    );
\retbuf_reg[33][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_264,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_96,
      Q => \retbuf_reg_n_0_[33][0]\
    );
\retbuf_reg[33][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_264,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_95,
      Q => \retbuf_reg_n_0_[33][1]\
    );
\retbuf_reg[33][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_264,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_94,
      Q => \retbuf_reg_n_0_[33][2]\
    );
\retbuf_reg[33][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_264,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_93,
      Q => \retbuf_reg_n_0_[33][3]\
    );
\retbuf_reg[33][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_264,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_92,
      Q => \retbuf_reg_n_0_[33][4]\
    );
\retbuf_reg[33][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_264,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_91,
      Q => \retbuf_reg_n_0_[33][5]\
    );
\retbuf_reg[33][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_264,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_90,
      Q => \retbuf_reg_n_0_[33][6]\
    );
\retbuf_reg[33][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_264,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_89,
      Q => \retbuf_reg_n_0_[33][7]\
    );
\retbuf_reg[34][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_265,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_88,
      Q => \retbuf_reg_n_0_[34][0]\
    );
\retbuf_reg[34][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_265,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_87,
      Q => \retbuf_reg_n_0_[34][1]\
    );
\retbuf_reg[34][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_265,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_86,
      Q => \retbuf_reg_n_0_[34][2]\
    );
\retbuf_reg[34][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_265,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_85,
      Q => \retbuf_reg_n_0_[34][3]\
    );
\retbuf_reg[34][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_265,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_84,
      Q => \retbuf_reg_n_0_[34][4]\
    );
\retbuf_reg[34][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_265,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_83,
      Q => \retbuf_reg_n_0_[34][5]\
    );
\retbuf_reg[34][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_265,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_82,
      Q => \retbuf_reg_n_0_[34][6]\
    );
\retbuf_reg[34][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_265,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_81,
      Q => \retbuf_reg_n_0_[34][7]\
    );
\retbuf_reg[35][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_266,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_80,
      Q => \retbuf_reg_n_0_[35][0]\
    );
\retbuf_reg[35][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_266,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_79,
      Q => \retbuf_reg_n_0_[35][1]\
    );
\retbuf_reg[35][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_266,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_78,
      Q => \retbuf_reg_n_0_[35][2]\
    );
\retbuf_reg[35][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_266,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_77,
      Q => \retbuf_reg_n_0_[35][3]\
    );
\retbuf_reg[35][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_266,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_76,
      Q => \retbuf_reg_n_0_[35][4]\
    );
\retbuf_reg[35][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_266,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_75,
      Q => \retbuf_reg_n_0_[35][5]\
    );
\retbuf_reg[35][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_266,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_74,
      Q => \retbuf_reg_n_0_[35][6]\
    );
\retbuf_reg[35][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_266,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_73,
      Q => \retbuf_reg_n_0_[35][7]\
    );
\retbuf_reg[36][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_72,
      Q => \retbuf_reg_n_0_[36][0]\
    );
\retbuf_reg[36][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_71,
      Q => \retbuf_reg_n_0_[36][1]\
    );
\retbuf_reg[36][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_70,
      Q => \retbuf_reg_n_0_[36][2]\
    );
\retbuf_reg[36][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_69,
      Q => \retbuf_reg_n_0_[36][3]\
    );
\retbuf_reg[36][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_68,
      Q => \retbuf_reg_n_0_[36][4]\
    );
\retbuf_reg[36][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_67,
      Q => \retbuf_reg_n_0_[36][5]\
    );
\retbuf_reg[36][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_66,
      Q => \retbuf_reg_n_0_[36][6]\
    );
\retbuf_reg[36][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_65,
      Q => \retbuf_reg_n_0_[36][7]\
    );
\retbuf_reg[37][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_56,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_64,
      Q => \retbuf_reg_n_0_[37][0]\
    );
\retbuf_reg[37][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_56,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_63,
      Q => \retbuf_reg_n_0_[37][1]\
    );
\retbuf_reg[37][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_56,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_62,
      Q => \retbuf_reg_n_0_[37][2]\
    );
\retbuf_reg[37][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_56,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_61,
      Q => \retbuf_reg_n_0_[37][3]\
    );
\retbuf_reg[37][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_56,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_60,
      Q => \retbuf_reg_n_0_[37][4]\
    );
\retbuf_reg[37][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_56,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_59,
      Q => \retbuf_reg_n_0_[37][5]\
    );
\retbuf_reg[37][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_56,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_58,
      Q => \retbuf_reg_n_0_[37][6]\
    );
\retbuf_reg[37][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_56,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_57,
      Q => \retbuf_reg_n_0_[37][7]\
    );
\retbuf_reg[38][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_56,
      Q => \retbuf_reg_n_0_[38][0]\
    );
\retbuf_reg[38][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_55,
      Q => \retbuf_reg_n_0_[38][1]\
    );
\retbuf_reg[38][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_54,
      Q => \retbuf_reg_n_0_[38][2]\
    );
\retbuf_reg[38][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_53,
      Q => \retbuf_reg_n_0_[38][3]\
    );
\retbuf_reg[38][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_52,
      Q => \retbuf_reg_n_0_[38][4]\
    );
\retbuf_reg[38][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_51,
      Q => \retbuf_reg_n_0_[38][5]\
    );
\retbuf_reg[38][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_50,
      Q => \retbuf_reg_n_0_[38][6]\
    );
\retbuf_reg[38][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_49,
      Q => \retbuf_reg_n_0_[38][7]\
    );
\retbuf_reg[39][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_37,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_48,
      Q => \retbuf_reg_n_0_[39][0]\
    );
\retbuf_reg[39][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_37,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_47,
      Q => \retbuf_reg_n_0_[39][1]\
    );
\retbuf_reg[39][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_37,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_46,
      Q => \retbuf_reg_n_0_[39][2]\
    );
\retbuf_reg[39][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_37,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_45,
      Q => \retbuf_reg_n_0_[39][3]\
    );
\retbuf_reg[39][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_37,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_44,
      Q => \retbuf_reg_n_0_[39][4]\
    );
\retbuf_reg[39][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_37,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_43,
      Q => \retbuf_reg_n_0_[39][5]\
    );
\retbuf_reg[39][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_37,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_42,
      Q => \retbuf_reg_n_0_[39][6]\
    );
\retbuf_reg[39][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_37,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_41,
      Q => \retbuf_reg_n_0_[39][7]\
    );
\retbuf_reg[3][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_21,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_240,
      Q => \retbuf_reg_n_0_[3][0]\
    );
\retbuf_reg[3][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_21,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_239,
      Q => \retbuf_reg_n_0_[3][1]\
    );
\retbuf_reg[3][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_21,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_335,
      Q => \retbuf_reg_n_0_[3][2]\
    );
\retbuf_reg[3][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_21,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_334,
      Q => \retbuf_reg_n_0_[3][3]\
    );
\retbuf_reg[3][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_21,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_238,
      Q => \retbuf_reg_n_0_[3][4]\
    );
\retbuf_reg[3][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_21,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_237,
      Q => \retbuf_reg_n_0_[3][5]\
    );
\retbuf_reg[3][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_21,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_333,
      Q => \retbuf_reg_n_0_[3][6]\
    );
\retbuf_reg[3][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_21,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_332,
      Q => \retbuf_reg_n_0_[3][7]\
    );
\retbuf_reg[4][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_22,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_269,
      Q => \retbuf_reg_n_0_[4][0]\
    );
\retbuf_reg[4][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_22,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_40,
      Q => \retbuf_reg_n_0_[4][1]\
    );
\retbuf_reg[4][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_22,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_39,
      Q => \retbuf_reg_n_0_[4][2]\
    );
\retbuf_reg[4][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_22,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_268,
      Q => \retbuf_reg_n_0_[4][3]\
    );
\retbuf_reg[4][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_22,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_38,
      Q => \retbuf_reg_n_0_[4][4]\
    );
\retbuf_reg[4][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_22,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_37,
      Q => \retbuf_reg_n_0_[4][5]\
    );
\retbuf_reg[4][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_22,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_36,
      Q => \retbuf_reg_n_0_[4][6]\
    );
\retbuf_reg[4][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_22,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_267,
      Q => \retbuf_reg_n_0_[4][7]\
    );
\retbuf_reg[5][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_237,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_10,
      Q => \retbuf_reg_n_0_[5][0]\
    );
\retbuf_reg[5][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_237,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_9,
      Q => \retbuf_reg_n_0_[5][1]\
    );
\retbuf_reg[5][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_237,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_8,
      Q => \retbuf_reg_n_0_[5][2]\
    );
\retbuf_reg[5][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_237,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_7,
      Q => \retbuf_reg_n_0_[5][3]\
    );
\retbuf_reg[5][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_237,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_6,
      Q => \retbuf_reg_n_0_[5][4]\
    );
\retbuf_reg[5][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_237,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_5,
      Q => \retbuf_reg_n_0_[5][5]\
    );
\retbuf_reg[5][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_237,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_4,
      Q => \retbuf_reg_n_0_[5][6]\
    );
\retbuf_reg[5][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_237,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_3,
      Q => \retbuf_reg_n_0_[5][7]\
    );
\retbuf_reg[6][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_238,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_33,
      Q => \retbuf_reg_n_0_[6][0]\
    );
\retbuf_reg[6][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_238,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_32,
      Q => \retbuf_reg_n_0_[6][1]\
    );
\retbuf_reg[6][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_238,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_31,
      Q => \retbuf_reg_n_0_[6][2]\
    );
\retbuf_reg[6][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_238,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_30,
      Q => \retbuf_reg_n_0_[6][3]\
    );
\retbuf_reg[6][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_238,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_29,
      Q => \retbuf_reg_n_0_[6][4]\
    );
\retbuf_reg[6][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_238,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_331,
      Q => \retbuf_reg_n_0_[6][5]\
    );
\retbuf_reg[6][5]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \retbuf[6][5]_i_5_n_0\,
      I1 => \retbuf[6][5]_i_6_n_0\,
      O => \retbuf_reg[6][5]_i_2_n_0\,
      S => \retbuf[5][5]_i_4_n_0\
    );
\retbuf_reg[6][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_238,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_28,
      Q => \retbuf_reg_n_0_[6][6]\
    );
\retbuf_reg[6][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_238,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_27,
      Q => \retbuf_reg_n_0_[6][7]\
    );
\retbuf_reg[7][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_23,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_236,
      Q => \retbuf_reg_n_0_[7][0]\
    );
\retbuf_reg[7][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_23,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_235,
      Q => \retbuf_reg_n_0_[7][1]\
    );
\retbuf_reg[7][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_23,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_234,
      Q => \retbuf_reg_n_0_[7][2]\
    );
\retbuf_reg[7][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_23,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_233,
      Q => \retbuf_reg_n_0_[7][3]\
    );
\retbuf_reg[7][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_23,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_330,
      Q => \retbuf_reg_n_0_[7][4]\
    );
\retbuf_reg[7][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_23,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_329,
      Q => \retbuf_reg_n_0_[7][5]\
    );
\retbuf_reg[7][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_23,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_328,
      Q => \retbuf_reg_n_0_[7][6]\
    );
\retbuf_reg[7][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_23,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_327,
      Q => \retbuf_reg_n_0_[7][7]\
    );
\retbuf_reg[8][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_239,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_398,
      Q => \retbuf_reg_n_0_[8][0]\
    );
\retbuf_reg[8][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_239,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_397,
      Q => \retbuf_reg_n_0_[8][1]\
    );
\retbuf_reg[8][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_239,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_396,
      Q => \retbuf_reg_n_0_[8][2]\
    );
\retbuf_reg[8][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_239,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_395,
      Q => \retbuf_reg_n_0_[8][3]\
    );
\retbuf_reg[8][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_239,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_394,
      Q => \retbuf_reg_n_0_[8][4]\
    );
\retbuf_reg[8][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_239,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_393,
      Q => \retbuf_reg_n_0_[8][5]\
    );
\retbuf_reg[8][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_239,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_392,
      Q => \retbuf_reg_n_0_[8][6]\
    );
\retbuf_reg[8][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_239,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_391,
      Q => \retbuf_reg_n_0_[8][7]\
    );
\retbuf_reg[9][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_240,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_390,
      Q => \retbuf_reg_n_0_[9][0]\
    );
\retbuf_reg[9][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_240,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_389,
      Q => \retbuf_reg_n_0_[9][1]\
    );
\retbuf_reg[9][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_240,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_388,
      Q => \retbuf_reg_n_0_[9][2]\
    );
\retbuf_reg[9][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_240,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_387,
      Q => \retbuf_reg_n_0_[9][3]\
    );
\retbuf_reg[9][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_240,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_386,
      Q => \retbuf_reg_n_0_[9][4]\
    );
\retbuf_reg[9][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_240,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_385,
      Q => \retbuf_reg_n_0_[9][5]\
    );
\retbuf_reg[9][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_240,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_384,
      Q => \retbuf_reg_n_0_[9][6]\
    );
\retbuf_reg[9][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_240,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_383,
      Q => \retbuf_reg_n_0_[9][7]\
    );
rng_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFB00000008"
    )
        port map (
      I0 => \^hdrnotfix\,
      I1 => reqInvSet,
      I2 => \^stateop_reg[0]_5\(0),
      I3 => \^reqinvacquire\,
      I4 => \^reqinvcornerconfig\,
      I5 => rng_reg_12,
      O => rng_reg_5
    );
\rng_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFFFF02000000"
    )
        port map (
      I0 => \^hdrnotfix\,
      I1 => \^reqinvdecimconfig\,
      I2 => \^reqinvdecimacquire\,
      I3 => \^reqinvdecimset\,
      I4 => \^tixvstate1\,
      I5 => rng_reg_7,
      O => rng_reg
    );
\rng_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEF0020"
    )
        port map (
      I0 => \myHdreng/rng\,
      I1 => rng_reg_8,
      I2 => \^reqinvhdrengset\,
      I3 => \^reqinvassign\,
      I4 => rng_reg_13,
      O => stateOp_reg_4
    );
\rng_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF700080000"
    )
        port map (
      I0 => \mask_reg[7]_0\,
      I1 => \^reqinvmemtrackset\,
      I2 => \^reqinvmemtrackclearmask\,
      I3 => \^reqinvmemtrackselect\,
      I4 => \^hdrnotfix\,
      I5 => rng_reg_9,
      O => rng_reg_0
    );
\rng_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => \^hdrnotfix\,
      I1 => \^reqinvrotarymoveto\,
      I2 => reqInvRotarySet,
      I3 => \^step1__6\,
      I4 => \^reqinvrotaryconfig\,
      I5 => rng_reg_10,
      O => rng_reg_1
    );
\rng_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF700080000"
    )
        port map (
      I0 => \mask_reg[5]_1\,
      I1 => \^reqinvhshktrackset\,
      I2 => \^reqinvhshktrackclearmask\,
      I3 => \^reqinvhshktrackselect\,
      I4 => \^hdrnotfix\,
      I5 => rng_reg_11,
      O => rng_reg_2
    );
rng_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF1FFFF00010000"
    )
        port map (
      I0 => linNotRot_i_2_n_0,
      I1 => hdrNotFix_i_2_n_0,
      I2 => rng_sig_reg,
      I3 => \^reqinvdirectorconfig\,
      I4 => \^reqinvdirectorset\,
      I5 => rng,
      O => stateOp_reg_3
    );
\rxlen[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFFFEFFFFBFBFEF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => \^stateop_reg[5]_0\(4),
      I2 => \^stateop_reg[5]_0\(1),
      I3 => \^stateop_reg[5]_0\(3),
      I4 => \^stateop_reg[5]_0\(0),
      I5 => \^stateop_reg[5]_0\(2),
      O => \rxlen[0]_i_3_n_0\
    );
\rxlen[0]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \^stateop_reg[5]_0\(2),
      O => \rxlen[0]_i_5_n_0\
    );
\rxlen[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEBFFFFFFFFFBFF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(0),
      I3 => \^stateop_reg[5]_0\(2),
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(4),
      O => \rxlen[0]_i_6_n_0\
    );
\rxlen_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_556,
      Q => \rxlen_reg_n_0_[0]\
    );
\seq[0][21]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^commok\,
      O => commok_sig_reg_0(1)
    );
\seq[0][5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^commok\,
      I1 => rng,
      O => commok_sig_reg_0(0)
    );
\seq[1][13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^commok\,
      I1 => rng,
      O => \seq[1]_2\(0)
    );
\staTixVTrigger[7]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \mask_reg[7]_0\,
      I1 => \^reqinvmemtrackselect\,
      I2 => \^reqinvmemtrackclearmask\,
      O => \stateOp_reg[2]_1\(0)
    );
\staTixVTrigger[7]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \mask_reg[5]_1\,
      I1 => \^reqinvhshktrackselect\,
      I2 => \^reqinvhshktrackclearmask\,
      O => \stateOp_reg[0]_4\(0)
    );
\staTixVTrigger[7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000000000"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \tixVController_reg_n_0_[1]\,
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \staTixVTrigger[7]_i_3__1_n_0\,
      I5 => \staTixVTrigger[7]_i_4__1_n_0\,
      O => \^reqinvvidtrackselect\
    );
\staTixVTrigger[7]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000008000000000"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \staTixVTrigger[7]_i_3__1_n_0\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \staTixVTrigger[7]_i_4__1_n_0\,
      O => \^reqinvselect\
    );
\staTixVTrigger[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \staTixVTrigger[7]_i_3__1_n_0\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[1]\,
      I5 => targetNotSteady_i_3_n_0,
      O => \^reqinvmemtrackselect\
    );
\staTixVTrigger[7]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => targetNotSteady_i_3_n_0,
      I2 => \staTixVTrigger[7]_i_5_n_0\,
      O => \^reqinvhshktrackselect\
    );
\staTixVTrigger[7]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEFF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[3]\,
      O => \staTixVTrigger[7]_i_3__1_n_0\
    );
\staTixVTrigger[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \staTixVTrigger[7]_i_3__1_n_0\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[1]\,
      I5 => \stateOp_i_3__1_n_0\,
      O => \^reqinvmemtrackclearmask\
    );
\staTixVTrigger[7]_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \staTixVTrigger[7]_i_5_n_0\,
      I2 => \stateOp_i_3__1_n_0\,
      O => \^reqinvhshktrackclearmask\
    );
\staTixVTrigger[7]_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[0]\,
      I1 => \tixVCommand_reg_n_0_[1]\,
      I2 => \tixVCommand_reg_n_0_[4]\,
      I3 => \tixVCommand_reg_n_0_[5]\,
      I4 => \stateOp_i_5__1_n_0\,
      O => \staTixVTrigger[7]_i_4__1_n_0\
    );
\staTixVTrigger[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000100000"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[1]\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => \tixVController_reg_n_0_[4]\,
      I5 => \tixVController_reg_n_0_[3]\,
      O => \staTixVTrigger[7]_i_5_n_0\
    );
\stateCorecfg[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => ackInvConfigSynth_sig_i_5_n_0,
      I2 => \stateCorecfg[2]_i_6_n_0\,
      O => \^reqinvgetcorereg\
    );
\stateCorecfg[2]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \stateCorecfg[2]_i_7_n_0\,
      O => \^reqinvsetcorereg\
    );
\stateCorecfg[2]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[4]\,
      I1 => \tixVCommand_reg_n_0_[5]\,
      I2 => \tixVCommand_reg_n_0_[1]\,
      I3 => \tixVCommand_reg_n_0_[0]\,
      I4 => \stateCorecfg[2]_i_8_n_0\,
      O => \stateCorecfg[2]_i_6_n_0\
    );
\stateCorecfg[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000040000"
    )
        port map (
      I0 => \retbuf[0][0]_i_3_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \stateCorecfg[2]_i_9_n_0\,
      I3 => \stateCorecfg[2]_i_8_n_0\,
      I4 => \tixVCommand_reg_n_0_[0]\,
      I5 => \ixRetbufCrc[4]_i_5_n_0\,
      O => \stateCorecfg[2]_i_7_n_0\
    );
\stateCorecfg[2]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[6]\,
      I1 => \tixVCommand_reg_n_0_[7]\,
      I2 => \tixVCommand_reg_n_0_[2]\,
      I3 => \tixVCommand_reg_n_0_[3]\,
      O => \stateCorecfg[2]_i_8_n_0\
    );
\stateCorecfg[2]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \tixVController_reg_n_0_[1]\,
      I1 => \tixVController_reg_n_0_[3]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \tixVController_reg_n_0_[2]\,
      O => \stateCorecfg[2]_i_9_n_0\
    );
stateMclk_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF00040004"
    )
        port map (
      I0 => Q(2),
      I1 => Q(3),
      I2 => Q(1),
      I3 => Q(0),
      I4 => reqResetFromHostif,
      I5 => stateMclk,
      O => \i_reg[2]__0\
    );
\stateOp[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBBBBBBB0"
    )
        port map (
      I0 => \stateOp_reg[0]_9\(1),
      I1 => \stateOp_reg[0]_9\(0),
      I2 => reqInvSet,
      I3 => reqInvUnlock,
      I4 => \^reqinvacquire\,
      I5 => \^reqinvcornerconfig\,
      O => \stateOp_reg[1]_4\(0)
    );
\stateOp[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDDDDDDDDDDD0"
    )
        port map (
      I0 => \stateOp_reg[0]_7\(0),
      I1 => \stateOp_reg[0]_7\(1),
      I2 => \^reqinvdecimunlock\,
      I3 => \^reqinvdecimacquire\,
      I4 => \^reqinvdecimconfig\,
      I5 => \^reqinvdecimset\,
      O => rng_reg_4(0)
    );
\stateOp[0]_i_1__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FFFFFE00FFFE"
    )
        port map (
      I0 => \^reqinvrotaryzero\,
      I1 => \^reqinvrotaryconfig\,
      I2 => \^ccwnotcw5_in\,
      I3 => ackInvSet_sig_reg(1),
      I4 => ackInvSet_sig_reg(0),
      I5 => \stateOp_reg[0]_8\,
      O => \stateOp_reg[1]_0\(0)
    );
\stateOp[0]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => reqInvRotarySet,
      I1 => \^reqinvrotarymoveto\,
      O => \^ccwnotcw5_in\
    );
\stateOp[0]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3EC0FEC0"
    )
        port map (
      I0 => crcAXIS_tlast_sig_reg_n_0,
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \^stateop_reg[5]_0\(2),
      I3 => \^stateop_reg[5]_0\(0),
      I4 => \crcAXIS_tkeep_reg[1]_i_2_n_5\,
      O => \stateOp[0]_i_7_n_0\
    );
\stateOp[0]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000F7"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \crcAXIS_tkeep_reg[1]_i_2_n_5\,
      I2 => \stateOp_reg[2]_i_6__0_n_5\,
      I3 => \^stateop_reg[5]_0\(0),
      I4 => \^stateop_reg[5]_0\(2),
      O => \stateOp[0]_i_8_n_0\
    );
\stateOp[1]_i_10__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(5),
      O => \stateOp[1]_i_10__1_n_0\
    );
\stateOp[1]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => txlast1(29),
      I1 => txlast1(28),
      O => \stateOp[1]_i_12_n_0\
    );
\stateOp[1]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => txlast1(27),
      I1 => txlast1(26),
      O => \stateOp[1]_i_13_n_0\
    );
\stateOp[1]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => txlast1(25),
      I1 => \wordcntCrcLast_reg_n_0_[24]\,
      I2 => txlast1(24),
      O => \stateOp[1]_i_14_n_0\
    );
\stateOp[1]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => txlast1(23),
      I1 => \wordcntCrcLast_reg_n_0_[23]\,
      I2 => txlast1(22),
      I3 => \wordcntCrcLast_reg_n_0_[22]\,
      O => \stateOp[1]_i_15_n_0\
    );
\stateOp[1]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => txlast1(21),
      I1 => \wordcntCrcLast_reg_n_0_[21]\,
      I2 => txlast1(20),
      I3 => \wordcntCrcLast_reg_n_0_[20]\,
      O => \stateOp[1]_i_16_n_0\
    );
\stateOp[1]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => txlast1(19),
      I1 => \wordcntCrcLast_reg_n_0_[19]\,
      I2 => txlast1(18),
      I3 => \wordcntCrcLast_reg_n_0_[18]\,
      O => \stateOp[1]_i_17_n_0\
    );
\stateOp[1]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => txlast1(17),
      I1 => \wordcntCrcLast_reg_n_0_[17]\,
      I2 => txlast1(16),
      I3 => \wordcntCrcLast_reg_n_0_[16]\,
      O => \stateOp[1]_i_18_n_0\
    );
\stateOp[1]_i_19\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => txlast1(30),
      O => \stateOp[1]_i_19_n_0\
    );
\stateOp[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => \^reqinvdecimset\,
      I1 => \^reqinvdecimconfig\,
      I2 => \^reqinvdecimacquire\,
      I3 => \^reqinvdecimunlock\,
      I4 => rng_reg_7,
      I5 => \^tixvstate1\,
      O => rng_reg_4(1)
    );
\stateOp[1]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFEEFAAA"
    )
        port map (
      I0 => \^step1__6\,
      I1 => \^ackinvconfig_sig0__6\,
      I2 => tkclk,
      I3 => ackInvSet_sig_reg(1),
      I4 => ackInvSet_sig_reg(0),
      O => tkclk_sig_reg(0)
    );
\stateOp[1]_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^reqinvtkclksrcsettkst\,
      O => \tixVController_reg[1]_0\
    );
\stateOp[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^reqinvcornerconfig\,
      I1 => \^reqinvacquire\,
      I2 => reqInvUnlock,
      I3 => reqInvSet,
      O => ackInvSet_sig_i_8_0
    );
\stateOp[1]_i_20\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => txlast1(28),
      I1 => txlast1(29),
      O => \stateOp[1]_i_20_n_0\
    );
\stateOp[1]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => txlast1(26),
      I1 => txlast1(27),
      O => \stateOp[1]_i_21_n_0\
    );
\stateOp[1]_i_22\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"41"
    )
        port map (
      I0 => txlast1(25),
      I1 => \wordcntCrcLast_reg_n_0_[24]\,
      I2 => txlast1(24),
      O => \stateOp[1]_i_22_n_0\
    );
\stateOp[1]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[23]\,
      I1 => txlast1(23),
      I2 => \wordcntCrcLast_reg_n_0_[22]\,
      I3 => txlast1(22),
      O => \stateOp[1]_i_23_n_0\
    );
\stateOp[1]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[21]\,
      I1 => txlast1(21),
      I2 => \wordcntCrcLast_reg_n_0_[20]\,
      I3 => txlast1(20),
      O => \stateOp[1]_i_24_n_0\
    );
\stateOp[1]_i_25\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[19]\,
      I1 => txlast1(19),
      I2 => \wordcntCrcLast_reg_n_0_[18]\,
      I3 => txlast1(18),
      O => \stateOp[1]_i_25_n_0\
    );
\stateOp[1]_i_26\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[17]\,
      I1 => txlast1(17),
      I2 => \wordcntCrcLast_reg_n_0_[16]\,
      I3 => txlast1(16),
      O => \stateOp[1]_i_26_n_0\
    );
\stateOp[1]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => txlast1(15),
      I1 => \wordcntCrcLast_reg_n_0_[15]\,
      I2 => txlast1(14),
      I3 => \wordcntCrcLast_reg_n_0_[14]\,
      O => \stateOp[1]_i_27_n_0\
    );
\stateOp[1]_i_28\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => txlast1(13),
      I1 => \wordcntCrcLast_reg_n_0_[13]\,
      I2 => txlast1(12),
      I3 => \wordcntCrcLast_reg_n_0_[12]\,
      O => \stateOp[1]_i_28_n_0\
    );
\stateOp[1]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => txlast1(11),
      I1 => \wordcntCrcLast_reg_n_0_[11]\,
      I2 => txlast1(10),
      I3 => \wordcntCrcLast_reg_n_0_[10]\,
      O => \stateOp[1]_i_29_n_0\
    );
\stateOp[1]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^reqinvvidtrackselect\,
      I1 => \^reqinvvidtrackset\,
      O => \tixVController_reg[1]_1\
    );
\stateOp[1]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFE0000FFFEFFFF"
    )
        port map (
      I0 => \^reqinvdecimset\,
      I1 => \^reqinvdecimconfig\,
      I2 => \^reqinvdecimacquire\,
      I3 => \^reqinvdecimunlock\,
      I4 => \stateOp_reg[0]_7\(1),
      I5 => \stateOp_reg[0]_7\(0),
      O => \^tixvstate1\
    );
\stateOp[1]_i_2__11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^reqinvhshktrackclearmask\,
      I1 => \^reqinvhshktrackset\,
      I2 => \^reqinvhshktrackselect\,
      I3 => \^reqinvhshktracksetmask\,
      O => \ackInvSetMask_sig_i_2__0_0\
    );
\stateOp[1]_i_2__12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^reqinvselect\,
      I1 => \^reqinvcputrackset\,
      O => \tixVController_reg[0]_0\
    );
\stateOp[1]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^reqinvmemtrackclearmask\,
      I1 => \^reqinvmemtrackset\,
      I2 => \^reqinvmemtrackselect\,
      I3 => \^reqinvmemtracksetmask\,
      O => \tixVController_reg[2]_0\
    );
\stateOp[1]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \ixRetbufCrc[5]_i_4_n_0\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \stateOp_i_4__1_n_0\,
      I5 => \tixVCommand_reg_n_0_[0]\,
      O => \^reqinvtkclksrcsettkst\
    );
\stateOp[1]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055D55555"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \stateOp[1]_i_6__1_n_0\,
      I2 => \^stateop_reg[5]_0\(3),
      I3 => \crcAXIS_tkeep_reg[1]_i_2_n_5\,
      I4 => \stateOp_reg[1]_i_7_n_0\,
      I5 => \stateOp[1]_i_8__1_n_0\,
      O => \stateOp[1]_i_2__4_n_0\
    );
\stateOp[1]_i_30\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => txlast1(9),
      I1 => \wordcntCrcLast_reg_n_0_[9]\,
      I2 => txlast1(8),
      I3 => \wordcntCrcLast_reg_n_0_[8]\,
      O => \stateOp[1]_i_30_n_0\
    );
\stateOp[1]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => txlast1(7),
      I1 => \wordcntCrcLast_reg_n_0_[7]\,
      I2 => txlast1(6),
      I3 => \wordcntCrcLast_reg_n_0_[6]\,
      O => \stateOp[1]_i_31_n_0\
    );
\stateOp[1]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => txlast1(5),
      I1 => \wordcntCrcLast_reg_n_0_[5]\,
      I2 => txlast1(4),
      I3 => \wordcntCrcLast_reg_n_0_[4]\,
      O => \stateOp[1]_i_32_n_0\
    );
\stateOp[1]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => txlast1(3),
      I1 => \wordcntCrcLast_reg_n_0_[3]\,
      I2 => txlast1(2),
      I3 => \wordcntCrcLast_reg_n_0_[2]\,
      O => \stateOp[1]_i_33_n_0\
    );
\stateOp[1]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"222B"
    )
        port map (
      I0 => txlast1(1),
      I1 => \wordcntCrcLast_reg_n_0_[1]\,
      I2 => \opbuf_reg[0]51_in\(6),
      I3 => \wordcntCrcLast_reg_n_0_[0]\,
      O => \stateOp[1]_i_34_n_0\
    );
\stateOp[1]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[15]\,
      I1 => txlast1(15),
      I2 => \wordcntCrcLast_reg_n_0_[14]\,
      I3 => txlast1(14),
      O => \stateOp[1]_i_35_n_0\
    );
\stateOp[1]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[13]\,
      I1 => txlast1(13),
      I2 => \wordcntCrcLast_reg_n_0_[12]\,
      I3 => txlast1(12),
      O => \stateOp[1]_i_36_n_0\
    );
\stateOp[1]_i_37\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[11]\,
      I1 => txlast1(11),
      I2 => \wordcntCrcLast_reg_n_0_[10]\,
      I3 => txlast1(10),
      O => \stateOp[1]_i_37_n_0\
    );
\stateOp[1]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[9]\,
      I1 => txlast1(9),
      I2 => \wordcntCrcLast_reg_n_0_[8]\,
      I3 => txlast1(8),
      O => \stateOp[1]_i_38_n_0\
    );
\stateOp[1]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[7]\,
      I1 => txlast1(7),
      I2 => \wordcntCrcLast_reg_n_0_[6]\,
      I3 => txlast1(6),
      O => \stateOp[1]_i_39_n_0\
    );
\stateOp[1]_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(0),
      I1 => \^stateop_reg[5]_0\(1),
      O => \stateOp[1]_i_3__4_n_0\
    );
\stateOp[1]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400000000"
    )
        port map (
      I0 => \^reqinvrotaryconfig\,
      I1 => \^step1__6\,
      I2 => \^reqinvrotarymoveto\,
      I3 => reqInvRotarySet,
      I4 => \^reqinvrotaryzero\,
      I5 => \stateOp_reg[0]_8\,
      O => \stateOp_reg[1]_1\
    );
\stateOp[1]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[5]\,
      I1 => txlast1(5),
      I2 => \wordcntCrcLast_reg_n_0_[4]\,
      I3 => txlast1(4),
      O => \stateOp[1]_i_40_n_0\
    );
\stateOp[1]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[3]\,
      I1 => txlast1(3),
      I2 => \wordcntCrcLast_reg_n_0_[2]\,
      I3 => txlast1(2),
      O => \stateOp[1]_i_41_n_0\
    );
\stateOp[1]_i_42\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6006"
    )
        port map (
      I0 => \wordcntCrcLast_reg_n_0_[0]\,
      I1 => \opbuf_reg[0]51_in\(6),
      I2 => \wordcntCrcLast_reg_n_0_[1]\,
      I3 => txlast1(1),
      O => \stateOp[1]_i_42_n_0\
    );
\stateOp[1]_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFFFFFFFF55D5"
    )
        port map (
      I0 => \stateOp[1]_i_10__1_n_0\,
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \crcAXIS_tkeep_reg[1]_i_2_n_5\,
      I3 => \stateOp_reg[2]_i_6__0_n_5\,
      I4 => \^stateop_reg[5]_0\(0),
      I5 => \^stateop_reg[5]_0\(2),
      O => \stateOp[1]_i_5__1_n_0\
    );
\stateOp[1]_i_6__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(2),
      O => \stateOp[1]_i_6__1_n_0\
    );
\stateOp[1]_i_8__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000FFBAFF"
    )
        port map (
      I0 => \stateOp_next_reg_n_0_[1]\,
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \^stateop_reg[5]_0\(0),
      I3 => \^stateop_reg[5]_0\(2),
      I4 => \^stateop_reg[5]_0\(3),
      I5 => \^stateop_reg[5]_0\(4),
      O => \stateOp[1]_i_8__1_n_0\
    );
\stateOp[1]_i_9__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \^stateop_reg[5]_0\(4),
      O => \stateOp[1]_i_9__0_n_0\
    );
\stateOp[2]_i_10__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateOp_reg[2]_i_21_n_3\,
      I1 => \wordcnt_reg_n_0_[30]\,
      O => \stateOp[2]_i_10__1_n_0\
    );
\stateOp[2]_i_11__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0990000000000990"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[27]\,
      I1 => crcAXIS_tlast_sig2(27),
      I2 => \wordcnt_reg_n_0_[29]\,
      I3 => \stateOp_reg[2]_i_21_n_3\,
      I4 => crcAXIS_tlast_sig2(28),
      I5 => \wordcnt_reg_n_0_[28]\,
      O => \stateOp[2]_i_11__1_n_0\
    );
\stateOp[2]_i_12__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[25]\,
      I1 => crcAXIS_tlast_sig2(25),
      I2 => \opbuf_reg[0]51_in\(30),
      I3 => crcAXIS_tlast_sig2(24),
      I4 => crcAXIS_tlast_sig2(26),
      I5 => \wordcnt_reg_n_0_[26]\,
      O => \stateOp[2]_i_12__0_n_0\
    );
\stateOp[2]_i_13__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crcAXIS_tlast_sig2(22),
      I1 => \opbuf_reg[0]51_in\(28),
      I2 => \opbuf_reg[0]51_in\(29),
      I3 => crcAXIS_tlast_sig2(23),
      I4 => \opbuf_reg[0]51_in\(27),
      I5 => crcAXIS_tlast_sig2(21),
      O => \stateOp[2]_i_13__1_n_0\
    );
\stateOp[2]_i_14__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crcAXIS_tlast_sig2(20),
      I1 => \opbuf_reg[0]51_in\(26),
      I2 => \opbuf_reg[0]51_in\(24),
      I3 => crcAXIS_tlast_sig2(18),
      I4 => \opbuf_reg[0]51_in\(25),
      I5 => crcAXIS_tlast_sig2(19),
      O => \stateOp[2]_i_14__0_n_0\
    );
\stateOp[2]_i_15__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crcAXIS_tlast_sig2(17),
      I1 => \opbuf_reg[0]51_in\(23),
      I2 => \opbuf_reg[0]51_in\(21),
      I3 => crcAXIS_tlast_sig2(15),
      I4 => \opbuf_reg[0]51_in\(22),
      I5 => crcAXIS_tlast_sig2(16),
      O => \stateOp[2]_i_15__1_n_0\
    );
\stateOp[2]_i_16__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crcAXIS_tlast_sig2(14),
      I1 => \opbuf_reg[0]51_in\(20),
      I2 => \opbuf_reg[0]51_in\(18),
      I3 => crcAXIS_tlast_sig2(12),
      I4 => \opbuf_reg[0]51_in\(19),
      I5 => crcAXIS_tlast_sig2(13),
      O => \stateOp[2]_i_16__1_n_0\
    );
\stateOp[2]_i_17__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crcAXIS_tlast_sig2(11),
      I1 => \opbuf_reg[0]51_in\(17),
      I2 => \opbuf_reg[0]51_in\(15),
      I3 => crcAXIS_tlast_sig2(9),
      I4 => \opbuf_reg[0]51_in\(16),
      I5 => crcAXIS_tlast_sig2(10),
      O => \stateOp[2]_i_17__1_n_0\
    );
\stateOp[2]_i_18__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crcAXIS_tlast_sig2(8),
      I1 => \opbuf_reg[0]51_in\(14),
      I2 => \opbuf_reg[0]51_in\(12),
      I3 => crcAXIS_tlast_sig2(6),
      I4 => \opbuf_reg[0]51_in\(13),
      I5 => crcAXIS_tlast_sig2(7),
      O => \stateOp[2]_i_18__1_n_0\
    );
\stateOp[2]_i_19__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crcAXIS_tlast_sig2(5),
      I1 => \opbuf_reg[0]51_in\(11),
      I2 => \opbuf_reg[0]51_in\(10),
      I3 => crcAXIS_tlast_sig2(4),
      I4 => \opbuf_reg[0]51_in\(9),
      I5 => crcAXIS_tlast_sig2(3),
      O => \stateOp[2]_i_19__1_n_0\
    );
\stateOp[2]_i_20__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6006000000006006"
    )
        port map (
      I0 => wordcntLast(0),
      I1 => \opbuf_reg[0]51_in\(6),
      I2 => \opbuf_reg[0]51_in\(7),
      I3 => crcAXIS_tlast_sig2(1),
      I4 => \opbuf_reg[0]51_in\(8),
      I5 => crcAXIS_tlast_sig2(2),
      O => \stateOp[2]_i_20__1_n_0\
    );
\stateOp[2]_i_25__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(28),
      O => \stateOp[2]_i_25__1_n_0\
    );
\stateOp[2]_i_26__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(27),
      O => \stateOp[2]_i_26__1_n_0\
    );
\stateOp[2]_i_27__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(26),
      O => \stateOp[2]_i_27__1_n_0\
    );
\stateOp[2]_i_28__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(25),
      O => \stateOp[2]_i_28__1_n_0\
    );
\stateOp[2]_i_29__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(24),
      O => \stateOp[2]_i_29__1_n_0\
    );
\stateOp[2]_i_30__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(23),
      O => \stateOp[2]_i_30__1_n_0\
    );
\stateOp[2]_i_31__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(22),
      O => \stateOp[2]_i_31__1_n_0\
    );
\stateOp[2]_i_32__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(21),
      O => \stateOp[2]_i_32__1_n_0\
    );
\stateOp[2]_i_33__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(20),
      O => \stateOp[2]_i_33__1_n_0\
    );
\stateOp[2]_i_34__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(19),
      O => \stateOp[2]_i_34__1_n_0\
    );
\stateOp[2]_i_35__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(18),
      O => \stateOp[2]_i_35__1_n_0\
    );
\stateOp[2]_i_36__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(17),
      O => \stateOp[2]_i_36__1_n_0\
    );
\stateOp[2]_i_37__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(16),
      O => \stateOp[2]_i_37__1_n_0\
    );
\stateOp[2]_i_38__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(15),
      O => \stateOp[2]_i_38__1_n_0\
    );
\stateOp[2]_i_39__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(14),
      O => \stateOp[2]_i_39__1_n_0\
    );
\stateOp[2]_i_40__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(13),
      O => \stateOp[2]_i_40__1_n_0\
    );
\stateOp[2]_i_41__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(12),
      O => \stateOp[2]_i_41__1_n_0\
    );
\stateOp[2]_i_42__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(11),
      O => \stateOp[2]_i_42__1_n_0\
    );
\stateOp[2]_i_43__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(10),
      O => \stateOp[2]_i_43__1_n_0\
    );
\stateOp[2]_i_44__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(9),
      O => \stateOp[2]_i_44__1_n_0\
    );
\stateOp[2]_i_45__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(8),
      O => \stateOp[2]_i_45__1_n_0\
    );
\stateOp[2]_i_46__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(7),
      O => \stateOp[2]_i_46__1_n_0\
    );
\stateOp[2]_i_47__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(6),
      O => \stateOp[2]_i_47__1_n_0\
    );
\stateOp[2]_i_48__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(5),
      O => \stateOp[2]_i_48__1_n_0\
    );
\stateOp[2]_i_49__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(4),
      O => \stateOp[2]_i_49__1_n_0\
    );
\stateOp[2]_i_50__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(3),
      O => \stateOp[2]_i_50__1_n_0\
    );
\stateOp[2]_i_51__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(2),
      O => \stateOp[2]_i_51__1_n_0\
    );
\stateOp[2]_i_52__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wordcntLast(1),
      O => \stateOp[2]_i_52__1_n_0\
    );
\stateOp[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF010F0F0F"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(0),
      I1 => \stateOp_next_reg_n_0_[3]\,
      I2 => \^stateop_reg[5]_0\(3),
      I3 => \^stateop_reg[5]_0\(2),
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(4),
      O => \stateOp[3]_i_5_n_0\
    );
\stateOp[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000F20000000000"
    )
        port map (
      I0 => \stateOp_next_reg_n_0_[4]\,
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(3),
      I3 => \^stateop_reg[5]_0\(1),
      I4 => \^stateop_reg[5]_0\(4),
      I5 => \^stateop_reg[5]_0\(2),
      O => \stateOp[4]_i_4_n_0\
    );
\stateOp[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C0C0C000C00080C"
    )
        port map (
      I0 => crcAXIS_tlast_sig_reg_n_0,
      I1 => \^stateop_reg[5]_0\(4),
      I2 => \^stateop_reg[5]_0\(3),
      I3 => \^stateop_reg[5]_0\(0),
      I4 => \^stateop_reg[5]_0\(2),
      I5 => \^stateop_reg[5]_0\(1),
      O => \stateOp[4]_i_5_n_0\
    );
\stateOp[5]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \retbuf[0][7]_i_16_n_0\,
      I1 => \stateOp[5]_i_23_n_0\,
      I2 => \stateOp[5]_i_24_n_0\,
      O => \stateOp[5]_i_12_n_0\
    );
\stateOp[5]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F200FF000000FF"
    )
        port map (
      I0 => \stateOp[5]_i_25_n_0\,
      I1 => \stateOp[5]_i_26_n_0\,
      I2 => \stateOp[5]_i_27_n_0\,
      I3 => \stateOp[5]_i_28_n_0\,
      I4 => \stateOp[5]_i_29_n_0\,
      I5 => \stateOp[5]_i_30_n_0\,
      O => \stateOp[5]_i_13_n_0\
    );
\stateOp[5]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEE0E0AAAAAAAA"
    )
        port map (
      I0 => \stateOp[5]_i_31_n_0\,
      I1 => \stateOp[5]_i_32_n_0\,
      I2 => \resid[1]_i_10_n_0\,
      I3 => ackInvCamifModReg,
      I4 => \stateOp[5]_i_33_n_0\,
      I5 => \stateOp[5]_i_34_n_0\,
      O => \stateOp[5]_i_14_n_0\
    );
\stateOp[5]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000D8FFFF00D8"
    )
        port map (
      I0 => \wordcntLast[0]_i_5_n_0\,
      I1 => ackInvCornerConfig,
      I2 => \stateOp[5]_i_35_n_0\,
      I3 => \stateOp[5]_i_23_n_0\,
      I4 => \stateOp[5]_i_24_n_0\,
      I5 => \stateOp[5]_i_36_n_0\,
      O => \stateOp[5]_i_15_n_0\
    );
\stateOp[5]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1112002000921084"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(0),
      I1 => \^stateop_reg[5]_0\(5),
      I2 => \^stateop_reg[5]_0\(2),
      I3 => \^stateop_reg[5]_0\(3),
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(4),
      O => \stateOp[5]_i_16_n_0\
    );
\stateOp[5]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFF9FBBFFFFD77F"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(3),
      I3 => \^stateop_reg[5]_0\(2),
      I4 => \^stateop_reg[5]_0\(5),
      I5 => \^stateop_reg[5]_0\(1),
      O => \stateOp[5]_i_17_n_0\
    );
\stateOp[5]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(2),
      I1 => \^stateop_reg[5]_0\(3),
      O => \stateOp[5]_i_19_n_0\
    );
\stateOp[5]_i_20\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(0),
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \^stateop_reg[5]_0\(4),
      O => \stateOp[5]_i_20_n_0\
    );
\stateOp[5]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(2),
      I2 => \^stateop_reg[5]_0\(0),
      O => \stateOp[5]_i_21_n_0\
    );
\stateOp[5]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \^stateop_reg[5]_0\(4),
      O => \stateOp[5]_i_22_n_0\
    );
\stateOp[5]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0500CFCC0504CFCC"
    )
        port map (
      I0 => \i2cRegaddr[15]_i_11_n_0\,
      I1 => ackInvConfig_sig_i_7_n_0,
      I2 => \^tixvcommand_reg[0]_0\,
      I3 => \ixRetbufCrc[5]_i_4_n_0\,
      I4 => ackInvSet_sig_i_9_n_0,
      I5 => \tixVCommand_reg_n_0_[0]\,
      O => \stateOp[5]_i_23_n_0\
    );
\stateOp[5]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \stateOp_i_3__1_n_0\,
      I1 => ackInvSet_sig_i_9_n_0,
      I2 => \resid[1]_i_11_n_0\,
      O => \stateOp[5]_i_24_n_0\
    );
\stateOp[5]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF100"
    )
        port map (
      I0 => \stateOp[5]_i_37_n_0\,
      I1 => \stateOp[5]_i_38_n_0\,
      I2 => \stateOp[5]_i_39_n_0\,
      I3 => \stateOp[5]_i_40_n_0\,
      I4 => \stateOp[5]_i_41_n_0\,
      I5 => \stateOp[5]_i_42_n_0\,
      O => \stateOp[5]_i_25_n_0\
    );
\stateOp[5]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFABABABABABABAB"
    )
        port map (
      I0 => \stateOp[5]_i_43_n_0\,
      I1 => \stateOp[5]_i_44_n_0\,
      I2 => \stateOp[5]_i_45_n_0\,
      I3 => ackInvHshktrackSelect,
      I4 => targetNotSteady_i_3_n_0,
      I5 => \staTixVTrigger[7]_i_5_n_0\,
      O => \stateOp[5]_i_26_n_0\
    );
\stateOp[5]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A888A888A888AAA"
    )
        port map (
      I0 => \stateOp[5]_i_46_n_0\,
      I1 => \stateOp[5]_i_47_n_0\,
      I2 => ackInvTraceAcquire,
      I3 => \stateOp[5]_i_48_n_0\,
      I4 => \stateOp[5]_i_49_n_0\,
      I5 => \stateOp[5]_i_50_n_0\,
      O => \stateOp[5]_i_27_n_0\
    );
\stateOp[5]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF45454540"
    )
        port map (
      I0 => \stateOp[5]_i_51_n_0\,
      I1 => \stateOp[5]_i_52_n_0\,
      I2 => \stateOp[5]_i_53_n_0\,
      I3 => \stateOp[5]_i_54_n_0\,
      I4 => \stateOp[5]_i_55_n_0\,
      I5 => \stateOp[5]_i_56_n_0\,
      O => \stateOp[5]_i_28_n_0\
    );
\stateOp[5]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \stateOp[5]_i_57_n_0\,
      I1 => \stateOp[5]_i_58_n_0\,
      I2 => \stateOp[5]_i_59_n_0\,
      I3 => \stateOp[5]_i_60_n_0\,
      I4 => \i__i_3_n_0\,
      I5 => \resid[1]_i_13_n_0\,
      O => \stateOp[5]_i_29_n_0\
    );
\stateOp[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAA02"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \stateOp[5]_i_12_n_0\,
      I2 => \stateOp[5]_i_13_n_0\,
      I3 => \stateOp[5]_i_14_n_0\,
      I4 => \stateOp[5]_i_15_n_0\,
      I5 => reqReset_sig_i_2_n_0,
      O => \stateOp[5]_i_3_n_0\
    );
\stateOp[5]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \stateOp[5]_i_45_n_0\,
      I1 => \stateOp[5]_i_44_n_0\,
      I2 => \stateOp[5]_i_61_n_0\,
      I3 => \stateOp[5]_i_62_n_0\,
      I4 => \stateOp[5]_i_47_n_0\,
      O => \stateOp[5]_i_30_n_0\
    );
\stateOp[5]_i_31\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000E0002"
    )
        port map (
      I0 => ackInvCamifConfig,
      I1 => \tixVCommand_reg_n_0_[0]\,
      I2 => ackInvConfigSynth_sig_i_5_n_0,
      I3 => \ixRetbufCrc[5]_i_4_n_0\,
      I4 => ackInvCamifConfigSynth,
      O => \stateOp[5]_i_31_n_0\
    );
\stateOp[5]_i_32\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000B888"
    )
        port map (
      I0 => ackInvCamifSetReg,
      I1 => targetNotSteady_i_3_n_0,
      I2 => ackInvCamifGetReg,
      I3 => \^tixvcommand_reg[0]_0\,
      I4 => ackInvConfigSynth_sig_i_5_n_0,
      O => \stateOp[5]_i_32_n_0\
    );
\stateOp[5]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \i2cRegaddr[15]_i_11_n_0\,
      I1 => ackInvConfigSynth_sig_i_5_n_0,
      O => \stateOp[5]_i_33_n_0\
    );
\stateOp[5]_i_34\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \ixRetbufCrc[5]_i_4_n_0\,
      I1 => ackInvConfigSynth_sig_i_5_n_0,
      O => \stateOp[5]_i_34_n_0\
    );
\stateOp[5]_i_35\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFE4EE0000E4EE"
    )
        port map (
      I0 => ackInvUnlock_sig_i_3_n_0,
      I1 => ackInvCornerUnlock,
      I2 => \stateOp[5]_i_63_n_0\,
      I3 => \stateOp[5]_i_64_n_0\,
      I4 => \stateOp[5]_i_65_n_0\,
      I5 => ackInvCornerSet,
      O => \stateOp[5]_i_35_n_0\
    );
\stateOp[5]_i_36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000F3FF53555355"
    )
        port map (
      I0 => ackInvCornerAcquire,
      I1 => ackInvCamifGetCorereg,
      I2 => ackInvConfigSynth_sig_i_5_n_0,
      I3 => \stateCorecfg[2]_i_6_n_0\,
      I4 => ackInvCamifSetCorereg,
      I5 => \stateCorecfg[2]_i_7_n_0\,
      O => \stateOp[5]_i_36_n_0\
    );
\stateOp[5]_i_37\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0E0A"
    )
        port map (
      I0 => \^tixvcommand_reg[0]_0\,
      I1 => \i2cRegaddr[15]_i_11_n_0\,
      I2 => \resid[2]_i_28_n_0\,
      I3 => ackInvMemtrackSetMask,
      O => \stateOp[5]_i_37_n_0\
    );
\stateOp[5]_i_38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFBF0FB"
    )
        port map (
      I0 => ackInvVidtrackSet,
      I1 => targetNotSteady_i_3_n_0,
      I2 => \resid[2]_i_27_n_0\,
      I3 => \staTixVTrigger[7]_i_4__1_n_0\,
      I4 => ackInvVidtrackSelect,
      I5 => \stateOp[5]_i_66_n_0\,
      O => \stateOp[5]_i_38_n_0\
    );
\stateOp[5]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00BA"
    )
        port map (
      I0 => targetNotSteady_i_3_n_0,
      I1 => ackInvMemtrackSet,
      I2 => \^tixvcommand_reg[0]_0\,
      I3 => \resid[2]_i_28_n_0\,
      O => \stateOp[5]_i_39_n_0\
    );
\stateOp[5]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F0F7"
    )
        port map (
      I0 => targetNotSteady_i_3_n_0,
      I1 => ackInvMemtrackSelect,
      I2 => \resid[2]_i_28_n_0\,
      I3 => \stateOp_i_3__1_n_0\,
      O => \stateOp[5]_i_40_n_0\
    );
\stateOp[5]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE00"
    )
        port map (
      I0 => targetNotSteady_i_3_n_0,
      I1 => \^tixvcommand_reg[0]_0\,
      I2 => \i2cRegaddr[15]_i_11_n_0\,
      I3 => \staTixVTrigger[7]_i_5_n_0\,
      O => \stateOp[5]_i_41_n_0\
    );
\stateOp[5]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \staTixVTrigger[7]_i_3__1_n_0\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \stateOp_i_3__1_n_0\,
      I5 => ackInvMemtrackClearMask,
      O => \stateOp[5]_i_42_n_0\
    );
\stateOp[5]_i_43\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000E0200000C000"
    )
        port map (
      I0 => \i2cRegaddr[15]_i_11_n_0\,
      I1 => \^tixvcommand_reg[0]_0\,
      I2 => \staTixVTrigger[7]_i_5_n_0\,
      I3 => ackInvHshktrackSet,
      I4 => targetNotSteady_i_3_n_0,
      I5 => ackInvHshktrackSetMask,
      O => \stateOp[5]_i_43_n_0\
    );
\stateOp[5]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F444F4F4F444F44"
    )
        port map (
      I0 => \resid[2]_i_28_n_0\,
      I1 => \i2cRegaddr[15]_i_11_n_0\,
      I2 => \resid[2]_i_27_n_0\,
      I3 => targetNotSteady_i_3_n_0,
      I4 => \ixRetbufCrc[5]_i_4_n_0\,
      I5 => \tixVCommand_reg_n_0_[0]\,
      O => \stateOp[5]_i_44_n_0\
    );
\stateOp[5]_i_45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFFA8FFAAFFA8F8"
    )
        port map (
      I0 => \staTixVTrigger[7]_i_5_n_0\,
      I1 => \i2cRegaddr[15]_i_11_n_0\,
      I2 => targetNotSteady_i_3_n_0,
      I3 => \resid[2]_i_28_n_0\,
      I4 => \^tixvcommand_reg[0]_0\,
      I5 => \stateOp_i_3__1_n_0\,
      O => \stateOp[5]_i_45_n_0\
    );
\stateOp[5]_i_46\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F55770F0FFF33"
    )
        port map (
      I0 => ackInvTkclksrcSetTkst,
      I1 => ackInvStepmuxSet,
      I2 => ackInvRotaryZero,
      I3 => \resid[1]_i_6_n_0\,
      I4 => \stateOp[5]_i_68_n_0\,
      I5 => \resid[2]_i_10_n_0\,
      O => \stateOp[5]_i_46_n_0\
    );
\stateOp[5]_i_47\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000C32222"
    )
        port map (
      I0 => \i2cRegaddr[15]_i_11_n_0\,
      I1 => \tixVController_reg_n_0_[1]\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      I3 => \ixRetbufCrc[5]_i_4_n_0\,
      I4 => \tixVController_reg_n_0_[0]\,
      I5 => \stateOp_i_4__1_n_0\,
      O => \stateOp[5]_i_47_n_0\
    );
\stateOp[5]_i_48\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000000"
    )
        port map (
      I0 => \tixVController_reg_n_0_[2]\,
      I1 => \tixVController_reg_n_0_[3]\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \retbuf[0][0]_i_3_n_0\,
      I4 => \resid[2]_i_25_n_0\,
      I5 => \stateOp_i_3__1_n_0\,
      O => \stateOp[5]_i_48_n_0\
    );
\stateOp[5]_i_49\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88D8000000000000"
    )
        port map (
      I0 => \stateOp[5]_i_69_n_0\,
      I1 => ackInvCputrackSelect,
      I2 => \stateOp[5]_i_70_n_0\,
      I3 => \stateOp[5]_i_71_n_0\,
      I4 => \stateOp[5]_i_72_n_0\,
      I5 => \stateOp[5]_i_73_n_0\,
      O => \stateOp[5]_i_49_n_0\
    );
\stateOp[5]_i_50\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000200"
    )
        port map (
      I0 => ackInvTraceConfig,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \staTixVTrigger[7]_i_4__1_n_0\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \staTixVTrigger[7]_i_3__1_n_0\,
      O => \stateOp[5]_i_50_n_0\
    );
\stateOp[5]_i_51\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => ackInvConfig_sig_i_7_n_0,
      I1 => \i2cRegaddr[15]_i_11_n_0\,
      I2 => \i__i_3_n_0\,
      O => \stateOp[5]_i_51_n_0\
    );
\stateOp[5]_i_52\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22E222E2FFE200E2"
    )
        port map (
      I0 => ackInvLaserSet,
      I1 => \stateOp[5]_i_58_n_0\,
      I2 => ackInvHdrengSet,
      I3 => \stateOp_i_3__1_n_0\,
      I4 => ackInvHdrengAssign,
      I5 => \resid[2]_i_30_n_0\,
      O => \stateOp[5]_i_52_n_0\
    );
\stateOp[5]_i_53\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0101010100000100"
    )
        port map (
      I0 => \tixVController_reg_n_0_[1]\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \stateOp_i_5__0_n_0\,
      I3 => targetNotSteady_i_3_n_0,
      I4 => \tixVController_reg_n_0_[0]\,
      I5 => \stateOp_i_3__1_n_0\,
      O => \stateOp[5]_i_53_n_0\
    );
\stateOp[5]_i_54\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00CA00C0"
    )
        port map (
      I0 => \^tixvcommand_reg[0]_0\,
      I1 => ackInvRotaryMoveto,
      I2 => targetNotSteady_i_3_n_0,
      I3 => targetNotSteady_i_4_n_0,
      I4 => ackInvRotarySet,
      O => \stateOp[5]_i_54_n_0\
    );
\stateOp[5]_i_55\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => ackInvRotaryConfig,
      I1 => \stateOp_i_3__1_n_0\,
      I2 => targetNotSteady_i_4_n_0,
      O => \stateOp[5]_i_55_n_0\
    );
\stateOp[5]_i_56\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8FF8888F8888888"
    )
        port map (
      I0 => \stateOp[5]_i_60_n_0\,
      I1 => ackInvDecimUnlock,
      I2 => ackInvDirectorSet,
      I3 => \tixVCommand_reg_n_0_[0]\,
      I4 => \i__i_3_n_0\,
      I5 => ackInvDirectorConfig,
      O => \stateOp[5]_i_56_n_0\
    );
\stateOp[5]_i_57\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \stateOp_i_5__1_n_0\,
      I1 => \ixRetbufCrc[4]_i_5_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      I3 => \stateOp_i_5__0_n_0\,
      I4 => \stateOp[5]_i_75_n_0\,
      I5 => \tixVController_reg_n_0_[0]\,
      O => \stateOp[5]_i_57_n_0\
    );
\stateOp[5]_i_58\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \tixVController_reg_n_0_[1]\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \stateOp_i_5__0_n_0\,
      I3 => \stateOp_i_5__1_n_0\,
      I4 => \stateOp[5]_i_76_n_0\,
      I5 => \tixVController_reg_n_0_[0]\,
      O => \stateOp[5]_i_58_n_0\
    );
\stateOp[5]_i_59\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \stateOp[5]_i_75_n_0\,
      I1 => \stateOp_i_5__0_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      I3 => \ixRetbufCrc[4]_i_5_n_0\,
      I4 => \stateOp_i_5__1_n_0\,
      I5 => \tixVController_reg_n_0_[0]\,
      O => \stateOp[5]_i_59_n_0\
    );
\stateOp[5]_i_60\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \stateCorecfg[2]_i_8_n_0\,
      I1 => \tixVCommand_reg_n_0_[0]\,
      I2 => \resid[1]_i_18_n_0\,
      I3 => \tixVCommand_reg_n_0_[1]\,
      I4 => \resid[1]_i_19_n_0\,
      I5 => \retbuf[0][0]_i_3_n_0\,
      O => \stateOp[5]_i_60_n_0\
    );
\stateOp[5]_i_61\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000C000000080"
    )
        port map (
      I0 => \staTixVTrigger[7]_i_4__1_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \staTixVTrigger[7]_i_3__1_n_0\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => targetNotSteady_i_3_n_0,
      O => \stateOp[5]_i_61_n_0\
    );
\stateOp[5]_i_62\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00080008000C00CC"
    )
        port map (
      I0 => \^tixvcommand_reg[0]_0\,
      I1 => \resid[2]_i_25_n_0\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \staTixVTrigger[7]_i_3__1_n_0\,
      I4 => \tixVCommand_reg_n_0_[0]\,
      I5 => \ixRetbufCrc[5]_i_4_n_0\,
      O => \stateOp[5]_i_62_n_0\
    );
\stateOp[5]_i_63\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCFFF8AFFCFFF00"
    )
        port map (
      I0 => ackInvDecimConfig,
      I1 => ackInvDecimSet,
      I2 => \^tixvcommand_reg[0]_0\,
      I3 => ackInvConfig_sig_i_7_n_0,
      I4 => \ixRetbufCrc[5]_i_4_n_0\,
      I5 => \tixVCommand_reg_n_0_[0]\,
      O => \stateOp[5]_i_63_n_0\
    );
\stateOp[5]_i_64\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => ackInvDecimAcquire,
      I1 => ackInvConfig_sig_i_7_n_0,
      I2 => \stateOp_i_3__1_n_0\,
      O => \stateOp[5]_i_64_n_0\
    );
\stateOp[5]_i_65\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \ixRetbufCrc[4]_i_4_n_0\,
      I1 => \ixRetbufCrc[4]_i_3_n_0\,
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \resid[2]_i_24_n_0\,
      I4 => \tixVCommand_reg_n_0_[0]\,
      I5 => \stateOp_i_5__1_n_0\,
      O => \stateOp[5]_i_65_n_0\
    );
\stateOp[5]_i_66\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \stateCorecfg[2]_i_8_n_0\,
      I1 => \tixVCommand_reg_n_0_[0]\,
      I2 => \ixRetbufCrc[4]_i_5_n_0\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \stateOp[5]_i_77_n_0\,
      I5 => \staTixVTrigger[7]_i_3__1_n_0\,
      O => \stateOp[5]_i_66_n_0\
    );
\stateOp[5]_i_68\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \stateCorecfg[2]_i_8_n_0\,
      I1 => \tixVCommand_reg_n_0_[0]\,
      I2 => \ixRetbufCrc[4]_i_5_n_0\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \tixVController_reg_n_0_[0]\,
      I5 => \stateOp_i_4__1_n_0\,
      O => \stateOp[5]_i_68_n_0\
    );
\stateOp[5]_i_69\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000000"
    )
        port map (
      I0 => \stateOp_i_5__1_n_0\,
      I1 => \ixRetbufCrc[4]_i_5_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      I3 => \resid[2]_i_31_n_0\,
      I4 => \tixVController_reg_n_0_[1]\,
      I5 => \tixVController_reg_n_0_[0]\,
      O => \stateOp[5]_i_69_n_0\
    );
\stateOp[5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02060A0804041000"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \^stateop_reg[5]_0\(4),
      I2 => \^stateop_reg[5]_0\(5),
      I3 => \^stateop_reg[5]_0\(1),
      I4 => \^stateop_reg[5]_0\(2),
      I5 => \^stateop_reg[5]_0\(0),
      O => \stateOp[5]_i_7_n_0\
    );
\stateOp[5]_i_70\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFB"
    )
        port map (
      I0 => ackInvHshktrackClearMask,
      I1 => \resid[2]_i_25_n_0\,
      I2 => \resid[1]_i_21_n_0\,
      I3 => \tixVCommand_reg_n_0_[0]\,
      I4 => \ixRetbufCrc[4]_i_5_n_0\,
      I5 => \stateOp_i_5__1_n_0\,
      O => \stateOp[5]_i_70_n_0\
    );
\stateOp[5]_i_71\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[1]\,
      I2 => \resid[2]_i_31_n_0\,
      I3 => \stateOp_i_5__1_n_0\,
      I4 => \stateOp[5]_i_76_n_0\,
      I5 => ackInvCputrackSet,
      O => \stateOp[5]_i_71_n_0\
    );
\stateOp[5]_i_72\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFDFFFFFFFFF"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[1]\,
      I1 => \resid[1]_i_18_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      I3 => \stateOp_i_5__1_n_0\,
      I4 => \resid[2]_i_31_n_0\,
      I5 => \resid[2]_i_25_n_0\,
      O => \stateOp[5]_i_72_n_0\
    );
\stateOp[5]_i_73\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFB"
    )
        port map (
      I0 => \resid[2]_i_31_n_0\,
      I1 => \tixVCommand_reg_n_0_[0]\,
      I2 => \ixRetbufCrc[4]_i_5_n_0\,
      I3 => \stateOp_i_5__1_n_0\,
      I4 => \tixVController_reg_n_0_[1]\,
      I5 => \tixVController_reg_n_0_[0]\,
      O => \stateOp[5]_i_73_n_0\
    );
\stateOp[5]_i_75\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \tixVController_reg_n_0_[1]\,
      I1 => \tixVController_reg_n_0_[2]\,
      O => \stateOp[5]_i_75_n_0\
    );
\stateOp[5]_i_76\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFB"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[0]\,
      I1 => \tixVCommand_reg_n_0_[1]\,
      I2 => \tixVCommand_reg_n_0_[5]\,
      I3 => \tixVCommand_reg_n_0_[4]\,
      O => \stateOp[5]_i_76_n_0\
    );
\stateOp[5]_i_77\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \tixVController_reg_n_0_[2]\,
      I1 => \tixVController_reg_n_0_[0]\,
      O => \stateOp[5]_i_77_n_0\
    );
\stateOp[5]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01011101FFFFF7FE"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(0),
      I3 => \^stateop_reg[5]_0\(2),
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(5),
      O => \stateOp[5]_i_8_n_0\
    );
stateOp_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => stateOp_reg_5,
      I1 => \^reqinvconfigsynth\,
      I2 => \^reqinvconfig\,
      O => stateOp47_out
    );
\stateOp_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002000"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \tixVController_reg_n_0_[1]\,
      I2 => \stateOp_i_3__1_n_0\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \stateOp_i_4__1_n_0\,
      O => \^reqinvstepmuxset\
    );
\stateOp_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => rng_sig_reg,
      I1 => \^reqinvdirectorset\,
      I2 => \^reqinvdirectorconfig\,
      O => stateOp0_out
    );
stateOp_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => rng_reg_8,
      I1 => \^reqinvhdrengset\,
      I2 => \^reqinvassign\,
      O => stateOp_reg
    );
\stateOp_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000000000000"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(4),
      I3 => \^stateop_reg[5]_0\(0),
      I4 => \^stateop_reg[5]_0\(2),
      I5 => \^stateop_reg[5]_0\(1),
      O => \stateOp_i_2__0_n_0\
    );
\stateOp_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5554"
    )
        port map (
      I0 => stateOp_reg_6,
      I1 => reqInvTraceUnlock,
      I2 => \^reqinvtraceconfig\,
      I3 => \^reqinvtraceacquire\,
      O => stateOp5_out
    );
stateOp_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000200"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \staTixVTrigger[7]_i_4__1_n_0\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \staTixVTrigger[7]_i_3__1_n_0\,
      O => \^reqinvtraceconfig\
    );
\stateOp_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[2]\,
      I4 => \stateOp_i_5__0_n_0\,
      I5 => \stateOp_i_3__1_n_0\,
      O => \^reqinvassign\
    );
\stateOp_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[0]\,
      I1 => \tixVCommand_reg_n_0_[1]\,
      I2 => \tixVCommand_reg_n_0_[4]\,
      I3 => \tixVCommand_reg_n_0_[5]\,
      I4 => \stateOp_i_5__1_n_0\,
      O => \stateOp_i_3__1_n_0\
    );
stateOp_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \stateOp_i_3__1_n_0\,
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \tixVController_reg_n_0_[1]\,
      I4 => \staTixVTrigger[7]_i_3__1_n_0\,
      I5 => \tixVController_reg_n_0_[2]\,
      O => \^reqinvtraceacquire\
    );
\stateOp_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => targetNotSteady_i_3_n_0,
      I3 => \stateOp_i_5__0_n_0\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \tixVController_reg_n_0_[1]\,
      O => \^reqinvhdrengset\
    );
\stateOp_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFDFFFFFFFF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \tixVController_reg_n_0_[4]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \tixVController_reg_n_0_[5]\,
      I4 => \tixVController_reg_n_0_[6]\,
      I5 => \tixVController_reg_n_0_[2]\,
      O => \stateOp_i_4__1_n_0\
    );
stateOp_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \staTixVTrigger[7]_i_3__1_n_0\,
      I4 => \tixVController_reg_n_0_[2]\,
      I5 => \^tixvcommand_reg[0]_0\,
      O => reqInvTraceUnlock
    );
\stateOp_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[5]\,
      I2 => \tixVController_reg_n_0_[7]\,
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \tixVController_reg_n_0_[3]\,
      O => \stateOp_i_5__0_n_0\
    );
\stateOp_i_5__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[6]\,
      I1 => \tixVCommand_reg_n_0_[7]\,
      I2 => \tixVCommand_reg_n_0_[3]\,
      I3 => \tixVCommand_reg_n_0_[2]\,
      O => \stateOp_i_5__1_n_0\
    );
\stateOp_next[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000022202228"
    )
        port map (
      I0 => \stateOp_next[5]_i_11_n_0\,
      I1 => \tixVBuffer_reg_n_0_[3]\,
      I2 => \tixVBuffer_reg_n_0_[1]\,
      I3 => \tixVBuffer_reg_n_0_[2]\,
      I4 => \tixVBuffer_reg_n_0_[0]\,
      I5 => \pollbuf[0][7]_i_7_n_0\,
      O => \stateOp_next[1]_i_2_n_0\
    );
\stateOp_next[4]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \stateOp_next[5]_i_19_n_0\,
      I1 => \len_reg_n_0_[0]\,
      I2 => \len_reg_n_0_[1]\,
      I3 => \len_reg_n_0_[2]\,
      O => \stateOp_next[4]_i_11_n_0\
    );
\stateOp_next[4]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \len_reg_n_0_[30]\,
      I1 => \len_reg_n_0_[31]\,
      O => \stateOp_next[4]_i_13_n_0\
    );
\stateOp_next[4]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \len_reg_n_0_[27]\,
      I1 => \len_reg_n_0_[28]\,
      I2 => \len_reg_n_0_[29]\,
      O => \stateOp_next[4]_i_14_n_0\
    );
\stateOp_next[4]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \len_reg_n_0_[26]\,
      I1 => \len_reg_n_0_[24]\,
      I2 => \len_reg_n_0_[25]\,
      O => \stateOp_next[4]_i_15_n_0\
    );
\stateOp_next[4]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \len_reg_n_0_[21]\,
      I1 => \len_reg_n_0_[23]\,
      I2 => \len_reg_n_0_[22]\,
      O => \stateOp_next[4]_i_16_n_0\
    );
\stateOp_next[4]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \len_reg_n_0_[19]\,
      I1 => \len_reg_n_0_[20]\,
      I2 => \len_reg_n_0_[18]\,
      O => \stateOp_next[4]_i_17_n_0\
    );
\stateOp_next[4]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1001"
    )
        port map (
      I0 => \len_reg_n_0_[17]\,
      I1 => \len_reg_n_0_[16]\,
      I2 => \len_reg_n_0_[15]\,
      I3 => \pollbuf[2][7]_i_2_n_0\,
      O => \stateOp_next[4]_i_18_n_0\
    );
\stateOp_next[4]_i_19\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => \pollbuf[2][4]_i_2_n_0\,
      I1 => \len_reg_n_0_[12]\,
      I2 => \len_reg_n_0_[14]\,
      I3 => \len_reg_n_0_[13]\,
      O => \stateOp_next[4]_i_19_n_0\
    );
\stateOp_next[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000FE"
    )
        port map (
      I0 => \stateOp_next[4]_i_3_n_0\,
      I1 => \stateOp_next[4]_i_4_n_0\,
      I2 => \stateOp_next[4]_i_5_n_0\,
      I3 => \stateOp_next[4]_i_6_n_0\,
      I4 => \pollbuf[0][7]_i_3_n_0\,
      O => \stateOp_next[4]_i_2_n_0\
    );
\stateOp_next[4]_i_20\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => \pollbuf[2][3]_i_2_n_0\,
      I1 => \len_reg_n_0_[11]\,
      I2 => \len_reg_n_0_[10]\,
      I3 => \len_reg_n_0_[9]\,
      O => \stateOp_next[4]_i_20_n_0\
    );
\stateOp_next[4]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \len_reg_n_0_[8]\,
      I1 => \len_reg_n_0_[7]\,
      I2 => \len_reg_n_0_[6]\,
      O => \stateOp_next[4]_i_21_n_0\
    );
\stateOp_next[4]_i_22\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \len_reg_n_0_[3]\,
      I1 => \len_reg_n_0_[5]\,
      I2 => \len_reg_n_0_[4]\,
      O => \stateOp_next[4]_i_22_n_0\
    );
\stateOp_next[4]_i_23\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \len_reg_n_0_[1]\,
      I1 => \len_reg_n_0_[0]\,
      I2 => \len_reg_n_0_[2]\,
      O => \stateOp_next[4]_i_23_n_0\
    );
\stateOp_next[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \len_reg_n_0_[27]\,
      I1 => \len_reg_n_0_[20]\,
      I2 => \len_reg_n_0_[17]\,
      I3 => \len_reg_n_0_[31]\,
      I4 => \len_reg_n_0_[25]\,
      I5 => \len_reg_n_0_[28]\,
      O => \stateOp_next[4]_i_3_n_0\
    );
\stateOp_next[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \stateOp_next[4]_i_7_n_0\,
      I1 => \len_reg_n_0_[24]\,
      I2 => \len_reg_n_0_[23]\,
      I3 => \len_reg_n_0_[18]\,
      I4 => \len_reg_n_0_[16]\,
      I5 => \stateOp_next[4]_i_8_n_0\,
      O => \stateOp_next[4]_i_4_n_0\
    );
\stateOp_next[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \stateOp_next[5]_i_9_n_0\,
      I1 => \stateOp_next[4]_i_9_n_0\,
      I2 => \len_reg_n_0_[14]\,
      I3 => \len_reg_n_0_[13]\,
      I4 => \len_reg_n_0_[15]\,
      I5 => \len_reg_n_0_[12]\,
      O => \stateOp_next[4]_i_5_n_0\
    );
\stateOp_next[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFBF"
    )
        port map (
      I0 => tixVBufxfop(0),
      I1 => tixVBufxfop(1),
      I2 => stateOp_next3144_in,
      I3 => tixVBufxfop(2),
      I4 => tixVBufxfop(3),
      I5 => \stateOp_next[4]_i_11_n_0\,
      O => \stateOp_next[4]_i_6_n_0\
    );
\stateOp_next[4]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \len_reg_n_0_[30]\,
      I1 => \len_reg_n_0_[29]\,
      I2 => \len_reg_n_0_[26]\,
      I3 => \len_reg_n_0_[21]\,
      O => \stateOp_next[4]_i_7_n_0\
    );
\stateOp_next[4]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \len_reg_n_0_[0]\,
      I1 => \len_reg_n_0_[1]\,
      I2 => \len_reg_n_0_[2]\,
      I3 => \len_reg_n_0_[19]\,
      I4 => \len_reg_n_0_[22]\,
      I5 => \len_reg_n_0_[3]\,
      O => \stateOp_next[4]_i_8_n_0\
    );
\stateOp_next[4]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \len_reg_n_0_[11]\,
      I1 => \len_reg_n_0_[8]\,
      I2 => \len_reg_n_0_[10]\,
      I3 => \len_reg_n_0_[9]\,
      O => \stateOp_next[4]_i_9_n_0\
    );
\stateOp_next[5]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \len_reg_n_0_[0]\,
      I1 => \len_reg_n_0_[1]\,
      O => \stateOp_next[5]_i_10_n_0\
    );
\stateOp_next[5]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => \stateOp_next[5]_i_19_n_0\,
      I1 => tixVBufxfop(1),
      I2 => tixVBufxfop(0),
      I3 => tixVBufxfop(2),
      I4 => tixVBufxfop(3),
      O => \stateOp_next[5]_i_11_n_0\
    );
\stateOp_next[5]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \crcAXIS_tkeep[7]_i_12_n_0\,
      I1 => \i2cRegaddr[15]_i_11_n_0\,
      I2 => \stateOp_next[5]_i_20_n_0\,
      O => \stateOp_next[5]_i_12_n_0\
    );
\stateOp_next[5]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"200230022002F002"
    )
        port map (
      I0 => targetNotSteady_i_3_n_0,
      I1 => \resid[2]_i_31_n_0\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \ixRetbufCrc[5]_i_4_n_0\,
      I5 => \stateOp_i_4__1_n_0\,
      O => \stateOp_next[5]_i_13_n_0\
    );
\stateOp_next[5]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFDFFFFFF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \tixVController_reg_n_0_[4]\,
      I2 => \retbuf[0][0]_i_3_n_0\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \stateOp_i_3__1_n_0\,
      I5 => \tixVController_reg_n_0_[1]\,
      O => \stateOp_next[5]_i_14_n_0\
    );
\stateOp_next[5]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAABFBF"
    )
        port map (
      I0 => \ixRetbufCrc[4]_i_2_n_0\,
      I1 => \resid[2]_i_30_n_0\,
      I2 => \resid[2]_i_27_n_0\,
      I3 => targetNotSteady_i_3_n_0,
      I4 => \ixRetbufCrc[5]_i_4_n_0\,
      O => \stateOp_next[5]_i_15_n_0\
    );
\stateOp_next[5]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFBA"
    )
        port map (
      I0 => \i__i_3_n_0\,
      I1 => \ixRetbufCrc[5]_i_4_n_0\,
      I2 => \ixRetbufCrc[5]_i_3_n_0\,
      I3 => \resid[1]_i_11_n_0\,
      I4 => \stateOp_next[5]_i_21_n_0\,
      I5 => reqReset_sig_i_2_n_0,
      O => \stateOp_next[5]_i_16_n_0\
    );
\stateOp_next[5]_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBFFFFFB"
    )
        port map (
      I0 => \stateOp_next[5]_i_22_n_0\,
      I1 => \tixVBuffer_reg_n_0_[0]\,
      I2 => \stateOp_next[4]_i_5_n_0\,
      I3 => \len_reg_n_0_[3]\,
      I4 => \wordcntLast[0]_i_5_n_0\,
      O => \stateOp_next[5]_i_17_n_0\
    );
\stateOp_next[5]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
        port map (
      I0 => \stateOp_next[5]_i_23_n_0\,
      I1 => \stateOp[5]_i_65_n_0\,
      I2 => \stateOp[5]_i_58_n_0\,
      I3 => \stateOp[5]_i_57_n_0\,
      I4 => \resid[1]_i_16_n_0\,
      I5 => \resid[1]_i_15_n_0\,
      O => \stateOp_next[5]_i_18_n_0\
    );
\stateOp_next[5]_i_19\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => tixVBufxfop(6),
      I1 => tixVBufxfop(4),
      I2 => tixVBufxfop(7),
      I3 => tixVBufxfop(5),
      O => \stateOp_next[5]_i_19_n_0\
    );
\stateOp_next[5]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFAECFFFFFFF7"
    )
        port map (
      I0 => \tixVController_reg_n_0_[1]\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \tixVController_reg_n_0_[3]\,
      I3 => \tixVController_reg_n_0_[4]\,
      I4 => \retbuf[0][0]_i_3_n_0\,
      I5 => \tixVController_reg_n_0_[2]\,
      O => \stateOp_next[5]_i_20_n_0\
    );
\stateOp_next[5]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000040000000404"
    )
        port map (
      I0 => \resid[2]_i_31_n_0\,
      I1 => \resid[2]_i_25_n_0\,
      I2 => \stateOp_i_5__1_n_0\,
      I3 => \tixVCommand_reg_n_0_[0]\,
      I4 => \resid[1]_i_18_n_0\,
      I5 => \tixVCommand_reg_n_0_[1]\,
      O => \stateOp_next[5]_i_21_n_0\
    );
\stateOp_next[5]_i_22\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[3]\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => \pollbuf[0][7]_i_7_n_0\,
      I3 => \tixVBuffer_reg_n_0_[1]\,
      O => \stateOp_next[5]_i_22_n_0\
    );
\stateOp_next[5]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \stateOp_i_5__1_n_0\,
      I1 => \resid[1]_i_18_n_0\,
      I2 => \tixVCommand_reg_n_0_[1]\,
      I3 => \tixVCommand_reg_n_0_[0]\,
      I4 => \resid[1]_i_19_n_0\,
      I5 => \retbuf[0][0]_i_3_n_0\,
      O => \stateOp_next[5]_i_23_n_0\
    );
\stateOp_next[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \^stateop_reg[5]_0\(4),
      O => \stateOp_next[5]_i_3_n_0\
    );
\stateOp_next[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0009090000000000"
    )
        port map (
      I0 => \resid[2]_i_6_n_0\,
      I1 => \len_reg_n_0_[2]\,
      I2 => \stateOp_next[5]_i_7_n_0\,
      I3 => \resid[1]_i_3_n_0\,
      I4 => \len_reg_n_0_[1]\,
      I5 => \stateOp_next[5]_i_8_n_0\,
      O => \stateOp_next[5]_i_4_n_0\
    );
\stateOp_next[5]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F7"
    )
        port map (
      I0 => \resid[1]_i_2_n_0\,
      I1 => \resid[1]_i_3_n_0\,
      I2 => \resid[2]_i_6_n_0\,
      O => \stateOp_next[5]_i_5_n_0\
    );
\stateOp_next[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \pollbuf[0][7]_i_4_n_0\,
      I1 => \stateOp_next[5]_i_9_n_0\,
      I2 => \len_reg_n_0_[3]\,
      I3 => \len_reg_n_0_[2]\,
      I4 => \stateOp_next[5]_i_10_n_0\,
      I5 => \stateOp_next[5]_i_11_n_0\,
      O => \stateOp_next[5]_i_6_n_0\
    );
\stateOp_next[5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000010"
    )
        port map (
      I0 => \stateOp_next[5]_i_12_n_0\,
      I1 => \stateOp_next[5]_i_13_n_0\,
      I2 => \stateOp_next[5]_i_14_n_0\,
      I3 => \stateOp_next[5]_i_15_n_0\,
      I4 => \stateOp_next[5]_i_16_n_0\,
      I5 => \stateOp_next[5]_i_17_n_0\,
      O => \stateOp_next[5]_i_7_n_0\
    );
\stateOp_next[5]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAA9A"
    )
        port map (
      I0 => \len_reg_n_0_[0]\,
      I1 => \stateOp_next[5]_i_18_n_0\,
      I2 => \resid[1]_i_6_n_0\,
      I3 => \resid[2]_i_5_n_0\,
      I4 => \resid[2]_i_9_n_0\,
      I5 => \resid[1]_i_5_n_0\,
      O => \stateOp_next[5]_i_8_n_0\
    );
\stateOp_next[5]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \len_reg_n_0_[5]\,
      I1 => \len_reg_n_0_[4]\,
      I2 => \len_reg_n_0_[7]\,
      I3 => \len_reg_n_0_[6]\,
      O => \stateOp_next[5]_i_9_n_0\
    );
\stateOp_next_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_485,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_146,
      Q => \stateOp_next_reg_n_0_[0]\
    );
\stateOp_next_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_485,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_145,
      Q => \stateOp_next_reg_n_0_[1]\
    );
\stateOp_next_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_485,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_144,
      Q => \stateOp_next_reg_n_0_[3]\
    );
\stateOp_next_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_485,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_143,
      Q => \stateOp_next_reg_n_0_[4]\
    );
\stateOp_next_reg[4]_i_10\: unisim.vcomponents.CARRY8
     port map (
      CI => \stateOp_next_reg[4]_i_12_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_stateOp_next_reg[4]_i_10_CO_UNCONNECTED\(7 downto 3),
      CO(2) => stateOp_next3144_in,
      CO(1) => \stateOp_next_reg[4]_i_10_n_6\,
      CO(0) => \stateOp_next_reg[4]_i_10_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_stateOp_next_reg[4]_i_10_O_UNCONNECTED\(7 downto 0),
      S(7 downto 3) => B"00000",
      S(2) => \stateOp_next[4]_i_13_n_0\,
      S(1) => \stateOp_next[4]_i_14_n_0\,
      S(0) => \stateOp_next[4]_i_15_n_0\
    );
\stateOp_next_reg[4]_i_12\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \stateOp_next_reg[4]_i_12_n_0\,
      CO(6) => \stateOp_next_reg[4]_i_12_n_1\,
      CO(5) => \stateOp_next_reg[4]_i_12_n_2\,
      CO(4) => \stateOp_next_reg[4]_i_12_n_3\,
      CO(3) => \stateOp_next_reg[4]_i_12_n_4\,
      CO(2) => \stateOp_next_reg[4]_i_12_n_5\,
      CO(1) => \stateOp_next_reg[4]_i_12_n_6\,
      CO(0) => \stateOp_next_reg[4]_i_12_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_stateOp_next_reg[4]_i_12_O_UNCONNECTED\(7 downto 0),
      S(7) => \stateOp_next[4]_i_16_n_0\,
      S(6) => \stateOp_next[4]_i_17_n_0\,
      S(5) => \stateOp_next[4]_i_18_n_0\,
      S(4) => \stateOp_next[4]_i_19_n_0\,
      S(3) => \stateOp_next[4]_i_20_n_0\,
      S(2) => \stateOp_next[4]_i_21_n_0\,
      S(1) => \stateOp_next[4]_i_22_n_0\,
      S(0) => \stateOp_next[4]_i_23_n_0\
    );
\stateOp_next_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_485,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_142,
      Q => \stateOp_next_reg_n_0_[5]\
    );
\stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_181,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_187,
      Q => \^stateop_reg[5]_0\(0)
    );
\stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_181,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_186,
      Q => \^stateop_reg[5]_0\(1)
    );
\stateOp_reg[1]_i_11\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \stateOp_reg[1]_i_11_n_0\,
      CO(6) => \stateOp_reg[1]_i_11_n_1\,
      CO(5) => \stateOp_reg[1]_i_11_n_2\,
      CO(4) => \stateOp_reg[1]_i_11_n_3\,
      CO(3) => \stateOp_reg[1]_i_11_n_4\,
      CO(2) => \stateOp_reg[1]_i_11_n_5\,
      CO(1) => \stateOp_reg[1]_i_11_n_6\,
      CO(0) => \stateOp_reg[1]_i_11_n_7\,
      DI(7) => \stateOp[1]_i_27_n_0\,
      DI(6) => \stateOp[1]_i_28_n_0\,
      DI(5) => \stateOp[1]_i_29_n_0\,
      DI(4) => \stateOp[1]_i_30_n_0\,
      DI(3) => \stateOp[1]_i_31_n_0\,
      DI(2) => \stateOp[1]_i_32_n_0\,
      DI(1) => \stateOp[1]_i_33_n_0\,
      DI(0) => \stateOp[1]_i_34_n_0\,
      O(7 downto 0) => \NLW_stateOp_reg[1]_i_11_O_UNCONNECTED\(7 downto 0),
      S(7) => \stateOp[1]_i_35_n_0\,
      S(6) => \stateOp[1]_i_36_n_0\,
      S(5) => \stateOp[1]_i_37_n_0\,
      S(4) => \stateOp[1]_i_38_n_0\,
      S(3) => \stateOp[1]_i_39_n_0\,
      S(2) => \stateOp[1]_i_40_n_0\,
      S(1) => \stateOp[1]_i_41_n_0\,
      S(0) => \stateOp[1]_i_42_n_0\
    );
\stateOp_reg[1]_i_7\: unisim.vcomponents.CARRY8
     port map (
      CI => \stateOp_reg[1]_i_11_n_0\,
      CI_TOP => '0',
      CO(7) => \stateOp_reg[1]_i_7_n_0\,
      CO(6) => \stateOp_reg[1]_i_7_n_1\,
      CO(5) => \stateOp_reg[1]_i_7_n_2\,
      CO(4) => \stateOp_reg[1]_i_7_n_3\,
      CO(3) => \stateOp_reg[1]_i_7_n_4\,
      CO(2) => \stateOp_reg[1]_i_7_n_5\,
      CO(1) => \stateOp_reg[1]_i_7_n_6\,
      CO(0) => \stateOp_reg[1]_i_7_n_7\,
      DI(7) => txlast1(30),
      DI(6) => \stateOp[1]_i_12_n_0\,
      DI(5) => \stateOp[1]_i_13_n_0\,
      DI(4) => \stateOp[1]_i_14_n_0\,
      DI(3) => \stateOp[1]_i_15_n_0\,
      DI(2) => \stateOp[1]_i_16_n_0\,
      DI(1) => \stateOp[1]_i_17_n_0\,
      DI(0) => \stateOp[1]_i_18_n_0\,
      O(7 downto 0) => \NLW_stateOp_reg[1]_i_7_O_UNCONNECTED\(7 downto 0),
      S(7) => \stateOp[1]_i_19_n_0\,
      S(6) => \stateOp[1]_i_20_n_0\,
      S(5) => \stateOp[1]_i_21_n_0\,
      S(4) => \stateOp[1]_i_22_n_0\,
      S(3) => \stateOp[1]_i_23_n_0\,
      S(2) => \stateOp[1]_i_24_n_0\,
      S(1) => \stateOp[1]_i_25_n_0\,
      S(0) => \stateOp[1]_i_26_n_0\
    );
\stateOp_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_181,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_185,
      Q => \^stateop_reg[5]_0\(2)
    );
\stateOp_reg[2]_i_21\: unisim.vcomponents.CARRY8
     port map (
      CI => \stateOp_reg[2]_i_22_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_stateOp_reg[2]_i_21_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \stateOp_reg[2]_i_21_n_3\,
      CO(3) => \NLW_stateOp_reg[2]_i_21_CO_UNCONNECTED\(3),
      CO(2) => \stateOp_reg[2]_i_21_n_5\,
      CO(1) => \stateOp_reg[2]_i_21_n_6\,
      CO(0) => \stateOp_reg[2]_i_21_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3 downto 0) => wordcntLast(28 downto 25),
      O(7 downto 4) => \NLW_stateOp_reg[2]_i_21_O_UNCONNECTED\(7 downto 4),
      O(3 downto 0) => crcAXIS_tlast_sig2(28 downto 25),
      S(7 downto 4) => B"0001",
      S(3) => \stateOp[2]_i_25__1_n_0\,
      S(2) => \stateOp[2]_i_26__1_n_0\,
      S(1) => \stateOp[2]_i_27__1_n_0\,
      S(0) => \stateOp[2]_i_28__1_n_0\
    );
\stateOp_reg[2]_i_22\: unisim.vcomponents.CARRY8
     port map (
      CI => \stateOp_reg[2]_i_23_n_0\,
      CI_TOP => '0',
      CO(7) => \stateOp_reg[2]_i_22_n_0\,
      CO(6) => \stateOp_reg[2]_i_22_n_1\,
      CO(5) => \stateOp_reg[2]_i_22_n_2\,
      CO(4) => \stateOp_reg[2]_i_22_n_3\,
      CO(3) => \stateOp_reg[2]_i_22_n_4\,
      CO(2) => \stateOp_reg[2]_i_22_n_5\,
      CO(1) => \stateOp_reg[2]_i_22_n_6\,
      CO(0) => \stateOp_reg[2]_i_22_n_7\,
      DI(7 downto 0) => wordcntLast(24 downto 17),
      O(7 downto 0) => crcAXIS_tlast_sig2(24 downto 17),
      S(7) => \stateOp[2]_i_29__1_n_0\,
      S(6) => \stateOp[2]_i_30__1_n_0\,
      S(5) => \stateOp[2]_i_31__1_n_0\,
      S(4) => \stateOp[2]_i_32__1_n_0\,
      S(3) => \stateOp[2]_i_33__1_n_0\,
      S(2) => \stateOp[2]_i_34__1_n_0\,
      S(1) => \stateOp[2]_i_35__1_n_0\,
      S(0) => \stateOp[2]_i_36__1_n_0\
    );
\stateOp_reg[2]_i_23\: unisim.vcomponents.CARRY8
     port map (
      CI => \stateOp_reg[2]_i_24_n_0\,
      CI_TOP => '0',
      CO(7) => \stateOp_reg[2]_i_23_n_0\,
      CO(6) => \stateOp_reg[2]_i_23_n_1\,
      CO(5) => \stateOp_reg[2]_i_23_n_2\,
      CO(4) => \stateOp_reg[2]_i_23_n_3\,
      CO(3) => \stateOp_reg[2]_i_23_n_4\,
      CO(2) => \stateOp_reg[2]_i_23_n_5\,
      CO(1) => \stateOp_reg[2]_i_23_n_6\,
      CO(0) => \stateOp_reg[2]_i_23_n_7\,
      DI(7 downto 0) => wordcntLast(16 downto 9),
      O(7 downto 0) => crcAXIS_tlast_sig2(16 downto 9),
      S(7) => \stateOp[2]_i_37__1_n_0\,
      S(6) => \stateOp[2]_i_38__1_n_0\,
      S(5) => \stateOp[2]_i_39__1_n_0\,
      S(4) => \stateOp[2]_i_40__1_n_0\,
      S(3) => \stateOp[2]_i_41__1_n_0\,
      S(2) => \stateOp[2]_i_42__1_n_0\,
      S(1) => \stateOp[2]_i_43__1_n_0\,
      S(0) => \stateOp[2]_i_44__1_n_0\
    );
\stateOp_reg[2]_i_24\: unisim.vcomponents.CARRY8
     port map (
      CI => wordcntLast(0),
      CI_TOP => '0',
      CO(7) => \stateOp_reg[2]_i_24_n_0\,
      CO(6) => \stateOp_reg[2]_i_24_n_1\,
      CO(5) => \stateOp_reg[2]_i_24_n_2\,
      CO(4) => \stateOp_reg[2]_i_24_n_3\,
      CO(3) => \stateOp_reg[2]_i_24_n_4\,
      CO(2) => \stateOp_reg[2]_i_24_n_5\,
      CO(1) => \stateOp_reg[2]_i_24_n_6\,
      CO(0) => \stateOp_reg[2]_i_24_n_7\,
      DI(7 downto 0) => wordcntLast(8 downto 1),
      O(7 downto 0) => crcAXIS_tlast_sig2(8 downto 1),
      S(7) => \stateOp[2]_i_45__1_n_0\,
      S(6) => \stateOp[2]_i_46__1_n_0\,
      S(5) => \stateOp[2]_i_47__1_n_0\,
      S(4) => \stateOp[2]_i_48__1_n_0\,
      S(3) => \stateOp[2]_i_49__1_n_0\,
      S(2) => \stateOp[2]_i_50__1_n_0\,
      S(1) => \stateOp[2]_i_51__1_n_0\,
      S(0) => \stateOp[2]_i_52__1_n_0\
    );
\stateOp_reg[2]_i_6__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \stateOp_reg[2]_i_9__0_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_stateOp_reg[2]_i_6__0_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \stateOp_reg[2]_i_6__0_n_5\,
      CO(1) => \stateOp_reg[2]_i_6__0_n_6\,
      CO(0) => \stateOp_reg[2]_i_6__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_stateOp_reg[2]_i_6__0_O_UNCONNECTED\(7 downto 0),
      S(7 downto 3) => B"00000",
      S(2) => \stateOp[2]_i_10__1_n_0\,
      S(1) => \stateOp[2]_i_11__1_n_0\,
      S(0) => \stateOp[2]_i_12__0_n_0\
    );
\stateOp_reg[2]_i_9__0\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \stateOp_reg[2]_i_9__0_n_0\,
      CO(6) => \stateOp_reg[2]_i_9__0_n_1\,
      CO(5) => \stateOp_reg[2]_i_9__0_n_2\,
      CO(4) => \stateOp_reg[2]_i_9__0_n_3\,
      CO(3) => \stateOp_reg[2]_i_9__0_n_4\,
      CO(2) => \stateOp_reg[2]_i_9__0_n_5\,
      CO(1) => \stateOp_reg[2]_i_9__0_n_6\,
      CO(0) => \stateOp_reg[2]_i_9__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_stateOp_reg[2]_i_9__0_O_UNCONNECTED\(7 downto 0),
      S(7) => \stateOp[2]_i_13__1_n_0\,
      S(6) => \stateOp[2]_i_14__0_n_0\,
      S(5) => \stateOp[2]_i_15__1_n_0\,
      S(4) => \stateOp[2]_i_16__1_n_0\,
      S(3) => \stateOp[2]_i_17__1_n_0\,
      S(2) => \stateOp[2]_i_18__1_n_0\,
      S(1) => \stateOp[2]_i_19__1_n_0\,
      S(0) => \stateOp[2]_i_20__1_n_0\
    );
\stateOp_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_181,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_184,
      Q => \^stateop_reg[5]_0\(3)
    );
\stateOp_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_181,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_183,
      Q => \^stateop_reg[5]_0\(4)
    );
\stateOp_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_181,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_285,
      Q => \^stateop_reg[5]_0\(5)
    );
\stateSeqbufB[2]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[0]\,
      I1 => \tixVBuffer_reg_n_0_[1]\,
      O => \stateSeqbufB[2]_i_10_n_0\
    );
\stateSeqbufB[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB[0]_i_3_n_0\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => \stateSeqbufB[2]_i_8_n_0\,
      O => reqSeqbufHshktrackToHostif
    );
\stateSeqbufB[2]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000040000"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[1]\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => \tixVBuffer_reg_n_0_[3]\,
      I3 => \pollbuf[0][7]_i_7_n_0\,
      I4 => \tixVBuffer_reg_n_0_[0]\,
      I5 => \FSM_onehot_stateCoobufB[0]_i_3_n_0\,
      O => reqSeqbufMemtrackToHostif
    );
\stateSeqbufB[2]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000000000000"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB[0]_i_3_n_0\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => \pollbuf[0][7]_i_7_n_0\,
      I3 => \tixVBuffer_reg_n_0_[3]\,
      I4 => \tixVBuffer_reg_n_0_[1]\,
      I5 => \tixVBuffer_reg_n_0_[0]\,
      O => reqSeqbufVidtrackToHostif
    );
\stateSeqbufB[2]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => \pollbuf[0][7]_i_7_n_0\,
      I1 => \tixVBuffer_reg_n_0_[3]\,
      I2 => \tixVBuffer_reg_n_0_[2]\,
      I3 => \tixVBuffer_reg_n_0_[1]\,
      I4 => \FSM_onehot_stateCoobufB[0]_i_3_n_0\,
      I5 => \tixVBuffer_reg_n_0_[0]\,
      O => reqSeqbufCputrackToHostif
    );
\stateSeqbufB[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \pollbuf[0][7]_i_7_n_0\,
      I1 => \tixVBuffer_reg_n_0_[3]\,
      I2 => \tixVBuffer_reg_n_0_[2]\,
      I3 => \tixVBuffer_reg_n_0_[1]\,
      I4 => \FSM_onehot_stateCoobufB[3]_i_4_n_0\,
      I5 => \tixVBuffer_reg_n_0_[0]\,
      O => seqbufCputrackToHostifAXIS_tready
    );
\stateSeqbufB[2]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB[3]_i_4_n_0\,
      I1 => \tixVBuffer_reg_n_0_[1]\,
      I2 => \tixVBuffer_reg_n_0_[2]\,
      I3 => \tixVBuffer_reg_n_0_[3]\,
      I4 => \pollbuf[0][7]_i_7_n_0\,
      I5 => \tixVBuffer_reg_n_0_[0]\,
      O => seqbufMemtrackToHostifAXIS_tready
    );
\stateSeqbufB[2]_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000000000000"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB[3]_i_4_n_0\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => \pollbuf[0][7]_i_7_n_0\,
      I3 => \tixVBuffer_reg_n_0_[3]\,
      I4 => \tixVBuffer_reg_n_0_[1]\,
      I5 => \tixVBuffer_reg_n_0_[0]\,
      O => seqbufVidtrackToHostifAXIS_tready
    );
\stateSeqbufB[2]_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[2]\,
      I1 => \FSM_onehot_stateCoobufB[3]_i_4_n_0\,
      I2 => \stateSeqbufB[2]_i_8_n_0\,
      O => seqbufHshktrackToHostifAXIS_tready
    );
\stateSeqbufB[2]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \pollbuf[0][7]_i_7_n_0\,
      I1 => \tixVBuffer_reg_n_0_[3]\,
      I2 => \tixVBuffer_reg_n_0_[2]\,
      I3 => \tixVBuffer_reg_n_0_[1]\,
      I4 => \FSM_onehot_stateCoobufB[5]_i_4_n_0\,
      I5 => \tixVBuffer_reg_n_0_[0]\,
      O => dneSeqbufCputrackToHostif
    );
\stateSeqbufB[2]_i_6__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000000000000"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB[5]_i_4_n_0\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => \pollbuf[0][7]_i_7_n_0\,
      I3 => \tixVBuffer_reg_n_0_[3]\,
      I4 => \tixVBuffer_reg_n_0_[1]\,
      I5 => \tixVBuffer_reg_n_0_[0]\,
      O => dneSeqbufVidtrackToHostif
    );
\stateSeqbufB[2]_i_6__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[2]\,
      I1 => \stateSeqbufB[2]_i_9_n_0\,
      I2 => \txAXIS_tdata[15]_i_8_n_0\,
      I3 => \^stateop_reg[5]_0\(5),
      I4 => \^stateop_reg[5]_0\(3),
      I5 => \stateSeqbufB[2]_i_8_n_0\,
      O => dneSeqbufHshktrackToHostif
    );
\stateSeqbufB[2]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB[5]_i_4_n_0\,
      I1 => \tixVBuffer_reg_n_0_[1]\,
      I2 => \tixVBuffer_reg_n_0_[2]\,
      I3 => \tixVBuffer_reg_n_0_[3]\,
      I4 => \pollbuf[0][7]_i_7_n_0\,
      I5 => \tixVBuffer_reg_n_0_[0]\,
      O => dneSeqbufMemtrackToHostif
    );
\stateSeqbufB[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[5]\,
      I1 => \tixVBuffer_reg_n_0_[6]\,
      I2 => \tixVBuffer_reg_n_0_[7]\,
      I3 => \tixVBuffer_reg_n_0_[3]\,
      I4 => p_0_in0,
      I5 => \stateSeqbufB[2]_i_10_n_0\,
      O => \stateSeqbufB[2]_i_8_n_0\
    );
\stateSeqbufB[2]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(0),
      I1 => \^stateop_reg[5]_0\(2),
      O => \stateSeqbufB[2]_i_9_n_0\
    );
synthNotLive_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^d\(21),
      I1 => \^d\(17),
      I2 => \^d\(19),
      I3 => \^d\(23),
      I4 => synthNotLive_i_2_n_0,
      O => synthNotLive
    );
synthNotLive_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^d\(18),
      I1 => \^d\(22),
      I2 => \^d\(16),
      I3 => \^d\(20),
      O => synthNotLive_i_2_n_0
    );
targetNotSteady_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"54005454"
    )
        port map (
      I0 => \^reqinvrotaryconfig\,
      I1 => \^reqinvrotarymoveto\,
      I2 => reqInvRotarySet,
      I3 => ackInvSet_sig_reg(1),
      I4 => ackInvSet_sig_reg(0),
      O => targetNotSteady
    );
targetNotSteady_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \stateOp_i_2__0_n_0\,
      I1 => targetNotSteady_i_3_n_0,
      I2 => targetNotSteady_i_4_n_0,
      O => \^reqinvrotarymoveto\
    );
targetNotSteady_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => \stateOp_i_5__1_n_0\,
      I1 => \tixVCommand_reg_n_0_[4]\,
      I2 => \tixVCommand_reg_n_0_[5]\,
      I3 => \tixVCommand_reg_n_0_[1]\,
      I4 => \tixVCommand_reg_n_0_[0]\,
      O => targetNotSteady_i_3_n_0
    );
targetNotSteady_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFDFF"
    )
        port map (
      I0 => \tixVController_reg_n_0_[2]\,
      I1 => \retbuf[0][0]_i_3_n_0\,
      I2 => \tixVController_reg_n_0_[4]\,
      I3 => \tixVController_reg_n_0_[3]\,
      I4 => \tixVController_reg_n_0_[0]\,
      I5 => \tixVController_reg_n_0_[1]\,
      O => targetNotSteady_i_4_n_0
    );
\tixVBuffer[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(2),
      I1 => \^stateop_reg[5]_0\(0),
      O => \tixVBuffer[7]_i_3_n_0\
    );
\tixVBuffer[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(3),
      O => \tixVBuffer[7]_i_4_n_0\
    );
\tixVBuffer_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_483,
      Q => \tixVBuffer_reg_n_0_[0]\
    );
\tixVBuffer_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_482,
      Q => \tixVBuffer_reg_n_0_[1]\
    );
\tixVBuffer_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_481,
      Q => \tixVBuffer_reg_n_0_[2]\
    );
\tixVBuffer_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_480,
      Q => \tixVBuffer_reg_n_0_[3]\
    );
\tixVBuffer_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_479,
      Q => p_0_in0
    );
\tixVBuffer_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_478,
      Q => \tixVBuffer_reg_n_0_[5]\
    );
\tixVBuffer_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_477,
      Q => \tixVBuffer_reg_n_0_[6]\
    );
\tixVBuffer_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_476,
      Q => \tixVBuffer_reg_n_0_[7]\
    );
\tixVBufxfop_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_493,
      Q => tixVBufxfop(0)
    );
\tixVBufxfop_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_492,
      Q => tixVBufxfop(1)
    );
\tixVBufxfop_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_491,
      Q => tixVBufxfop(2)
    );
\tixVBufxfop_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_490,
      Q => tixVBufxfop(3)
    );
\tixVBufxfop_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_489,
      Q => tixVBufxfop(4)
    );
\tixVBufxfop_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_488,
      Q => tixVBufxfop(5)
    );
\tixVBufxfop_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_487,
      Q => tixVBufxfop(6)
    );
\tixVBufxfop_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_486,
      Q => tixVBufxfop(7)
    );
\tixVCommand_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_493,
      Q => \tixVCommand_reg_n_0_[0]\
    );
\tixVCommand_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_492,
      Q => \tixVCommand_reg_n_0_[1]\
    );
\tixVCommand_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_491,
      Q => \tixVCommand_reg_n_0_[2]\
    );
\tixVCommand_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_490,
      Q => \tixVCommand_reg_n_0_[3]\
    );
\tixVCommand_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_489,
      Q => \tixVCommand_reg_n_0_[4]\
    );
\tixVCommand_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_488,
      Q => \tixVCommand_reg_n_0_[5]\
    );
\tixVCommand_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_487,
      Q => \tixVCommand_reg_n_0_[6]\
    );
\tixVCommand_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_486,
      Q => \tixVCommand_reg_n_0_[7]\
    );
\tixVController[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \tixVController[7]_i_4_n_0\,
      I1 => \tixVController[7]_i_5_n_0\,
      I2 => \tixVController[7]_i_6_n_0\,
      I3 => \opbuf_reg_n_0_[2][1]\,
      I4 => \opbuf_reg_n_0_[2][5]\,
      I5 => \opbuf_reg_n_0_[2][2]\,
      O => \tixVController[7]_i_3_n_0\
    );
\tixVController[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \opbuf_reg_n_0_[2][3]\,
      I1 => \opbuf_reg_n_0_[2][7]\,
      I2 => \opbuf_reg_n_0_[0][0]\,
      I3 => \opbuf_reg_n_0_[2][4]\,
      O => \tixVController[7]_i_4_n_0\
    );
\tixVController[7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \opbuf_reg_n_0_[0][5]\,
      I1 => \opbuf_reg_n_0_[0][4]\,
      I2 => \opbuf_reg_n_0_[2][6]\,
      I3 => \opbuf_reg_n_0_[0][1]\,
      O => \tixVController[7]_i_5_n_0\
    );
\tixVController[7]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \opbuf_reg_n_0_[0][6]\,
      I1 => \opbuf_reg_n_0_[0][7]\,
      I2 => \opbuf_reg_n_0_[0][3]\,
      I3 => \opbuf_reg_n_0_[0][2]\,
      O => \tixVController[7]_i_6_n_0\
    );
\tixVController_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_475,
      Q => \tixVController_reg_n_0_[0]\
    );
\tixVController_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_474,
      Q => \tixVController_reg_n_0_[1]\
    );
\tixVController_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_473,
      Q => \tixVController_reg_n_0_[2]\
    );
\tixVController_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_472,
      Q => \tixVController_reg_n_0_[3]\
    );
\tixVController_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_471,
      Q => \tixVController_reg_n_0_[4]\
    );
\tixVController_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_470,
      Q => \tixVController_reg_n_0_[5]\
    );
\tixVController_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_469,
      Q => \tixVController_reg_n_0_[6]\
    );
\tixVController_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_468,
      Q => \tixVController_reg_n_0_[7]\
    );
\tixVState[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F880F8F0F880F88"
    )
        port map (
      I0 => \^ackinvunlock_sig0_in\,
      I1 => \tixVState_reg[1]_2\(1),
      I2 => \tixVState_reg[1]_3\,
      I3 => \tixVState_reg[1]_2\(0),
      I4 => \^stateop_reg[0]_5\(0),
      I5 => \^reqinvacquire\,
      O => \tixVState_reg[1]\(0)
    );
\tixVState[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FCAACCAA"
    )
        port map (
      I0 => \tixVState_reg[1]_0\,
      I1 => \tixVState[1]_i_4_n_0\,
      I2 => rng_reg_7,
      I3 => \^tixvstate1\,
      I4 => \^reqinvdecimacquire\,
      O => rng_reg_3(0)
    );
\tixVState[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000003AAAAAAAA"
    )
        port map (
      I0 => \stateOp_reg[0]_9\(0),
      I1 => \^reqinvcornerconfig\,
      I2 => \^reqinvacquire\,
      I3 => reqInvUnlock,
      I4 => reqInvSet,
      I5 => \stateOp_reg[0]_9\(1),
      O => \^stateop_reg[0]_5\(0)
    );
\tixVState[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"222222222222222E"
    )
        port map (
      I0 => \stateOp_reg[0]_7\(0),
      I1 => \stateOp_reg[0]_7\(1),
      I2 => \^reqinvdecimunlock\,
      I3 => \^reqinvdecimacquire\,
      I4 => \^reqinvdecimconfig\,
      I5 => \^reqinvdecimset\,
      O => \stateOp_reg[0]_1\(0)
    );
\tixVState[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000AAEA"
    )
        port map (
      I0 => \^reqinvdecimset\,
      I1 => \^reqinvdecimunlock\,
      I2 => \tixVState_reg[1]_1\(1),
      I3 => \tixVState_reg[1]_1\(0),
      I4 => \^reqinvdecimacquire\,
      I5 => \^reqinvdecimconfig\,
      O => \tixVState[1]_i_4_n_0\
    );
\txAXIS_tdata[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[24][0]\,
      I1 => \retbuf_reg[16]_65\(0),
      I2 => \txAXIS_tdata[3]_i_7_n_0\,
      I3 => \retbuf_reg_n_0_[8][0]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[0][0]\,
      O => \txAXIS_tdata[0]_i_3_n_0\
    );
\txAXIS_tdata[0]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[7]\,
      I1 => \tixVBuffer_reg_n_0_[6]\,
      I2 => \tixVBuffer_reg_n_0_[5]\,
      I3 => p_0_in0,
      I4 => \^stateop_reg[5]_0\(0),
      I5 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[0]_i_5__0_n_0\
    );
\txAXIS_tdata[0]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(0),
      I1 => \txAXIS_tdata[63]_i_8_4\(0),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(0),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[0]_i_6_n_0\
    );
\txAXIS_tdata[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(0),
      I1 => \txAXIS_tdata[63]_i_8_0\(0),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(0),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(0),
      O => \txAXIS_tdata[0]_i_7_n_0\
    );
\txAXIS_tdata[10]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888BBB8B"
    )
        port map (
      I0 => \txAXIS_tdata[10]_i_7_n_0\,
      I1 => \txAXIS_tdata[55]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[0][2]\,
      I3 => \txAXIS_tdata[63]_i_9_n_0\,
      I4 => \retbuf_reg_n_0_[33][2]\,
      O => \txAXIS_tdata[10]_i_3_n_0\
    );
\txAXIS_tdata[10]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(10),
      I1 => \txAXIS_tdata[63]_i_8_4\(10),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(10),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[10]_i_4_n_0\
    );
\txAXIS_tdata[10]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(10),
      I1 => \txAXIS_tdata[63]_i_8_0\(10),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(10),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(10),
      O => \txAXIS_tdata[10]_i_5_n_0\
    );
\txAXIS_tdata[10]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[9][2]\,
      I1 => \retbuf_reg_n_0_[1][2]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[25][2]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[17][2]\,
      O => \txAXIS_tdata[10]_i_7_n_0\
    );
\txAXIS_tdata[11]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888BBB8B"
    )
        port map (
      I0 => \txAXIS_tdata[11]_i_7_n_0\,
      I1 => \txAXIS_tdata[55]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[0][3]\,
      I3 => \txAXIS_tdata[63]_i_9_n_0\,
      I4 => \retbuf_reg_n_0_[33][3]\,
      O => \txAXIS_tdata[11]_i_3_n_0\
    );
\txAXIS_tdata[11]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(11),
      I1 => \txAXIS_tdata[63]_i_8_4\(11),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(11),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[11]_i_4_n_0\
    );
\txAXIS_tdata[11]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(11),
      I1 => \txAXIS_tdata[63]_i_8_0\(11),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(11),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(11),
      O => \txAXIS_tdata[11]_i_5_n_0\
    );
\txAXIS_tdata[11]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[9][3]\,
      I1 => \retbuf_reg_n_0_[1][3]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[25][3]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[17][3]\,
      O => \txAXIS_tdata[11]_i_7_n_0\
    );
\txAXIS_tdata[12]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888BBB8B"
    )
        port map (
      I0 => \txAXIS_tdata[12]_i_7_n_0\,
      I1 => \txAXIS_tdata[55]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[0][4]\,
      I3 => \txAXIS_tdata[63]_i_9_n_0\,
      I4 => \retbuf_reg_n_0_[33][4]\,
      O => \txAXIS_tdata[12]_i_3_n_0\
    );
\txAXIS_tdata[12]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(12),
      I1 => \txAXIS_tdata[63]_i_8_4\(12),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(12),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[12]_i_4_n_0\
    );
\txAXIS_tdata[12]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(12),
      I1 => \txAXIS_tdata[63]_i_8_0\(12),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(12),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(12),
      O => \txAXIS_tdata[12]_i_5_n_0\
    );
\txAXIS_tdata[12]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[9][4]\,
      I1 => \retbuf_reg_n_0_[1][4]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[25][4]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[17][4]\,
      O => \txAXIS_tdata[12]_i_7_n_0\
    );
\txAXIS_tdata[13]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888BBB8B"
    )
        port map (
      I0 => \txAXIS_tdata[13]_i_7_n_0\,
      I1 => \txAXIS_tdata[55]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[0][5]\,
      I3 => \txAXIS_tdata[63]_i_9_n_0\,
      I4 => \retbuf_reg_n_0_[33][5]\,
      O => \txAXIS_tdata[13]_i_3_n_0\
    );
\txAXIS_tdata[13]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(13),
      I1 => \txAXIS_tdata[63]_i_8_4\(13),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(13),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[13]_i_4_n_0\
    );
\txAXIS_tdata[13]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(13),
      I1 => \txAXIS_tdata[63]_i_8_0\(13),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(13),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(13),
      O => \txAXIS_tdata[13]_i_5_n_0\
    );
\txAXIS_tdata[13]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[9][5]\,
      I1 => \retbuf_reg_n_0_[1][5]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[25][5]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[17][5]\,
      O => \txAXIS_tdata[13]_i_7_n_0\
    );
\txAXIS_tdata[14]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888BBB8B"
    )
        port map (
      I0 => \txAXIS_tdata[14]_i_7_n_0\,
      I1 => \txAXIS_tdata[55]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[0][6]\,
      I3 => \txAXIS_tdata[63]_i_9_n_0\,
      I4 => \retbuf_reg_n_0_[33][6]\,
      O => \txAXIS_tdata[14]_i_3_n_0\
    );
\txAXIS_tdata[14]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(14),
      I1 => \txAXIS_tdata[63]_i_8_4\(14),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(14),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[14]_i_4_n_0\
    );
\txAXIS_tdata[14]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(14),
      I1 => \txAXIS_tdata[63]_i_8_0\(14),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(14),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(14),
      O => \txAXIS_tdata[14]_i_5_n_0\
    );
\txAXIS_tdata[14]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[9][6]\,
      I1 => \retbuf_reg_n_0_[1][6]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[25][6]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[17][6]\,
      O => \txAXIS_tdata[14]_i_7_n_0\
    );
\txAXIS_tdata[15]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => \^stateop_reg[5]_0\(0),
      O => \txAXIS_tdata[15]_i_10_n_0\
    );
\txAXIS_tdata[15]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000022200020"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[1]\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => \pollbuf[2][3]_i_2_0\(0),
      I3 => \tixVBuffer_reg_n_0_[0]\,
      I4 => \pollbuf[2][7]_i_2_0\(0),
      I5 => \wordcntLast[28]_i_19_n_0\,
      O => \txAXIS_tdata[15]_i_11_n_0\
    );
\txAXIS_tdata[15]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => seqbufVidtrackToHostifAXIS_tvalid,
      I1 => seqbufCputrackToHostifAXIS_tvalid,
      I2 => \tixVBuffer_reg_n_0_[1]\,
      I3 => seqbufMemtrackToHostifAXIS_tvalid,
      I4 => \tixVBuffer_reg_n_0_[0]\,
      I5 => \pollbuf_reg[2][7]_0\(0),
      O => \txAXIS_tdata[15]_i_12_n_0\
    );
\txAXIS_tdata[15]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(15),
      I1 => \txAXIS_tdata[63]_i_8_4\(15),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(15),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[15]_i_14_n_0\
    );
\txAXIS_tdata[15]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(15),
      I1 => \txAXIS_tdata[63]_i_8_0\(15),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(15),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(15),
      O => \txAXIS_tdata[15]_i_15_n_0\
    );
\txAXIS_tdata[15]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[9][7]\,
      I1 => \retbuf_reg_n_0_[1][7]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[25][7]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[17][7]\,
      O => \txAXIS_tdata[15]_i_17_n_0\
    );
\txAXIS_tdata[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0C080C0F"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_9_n_0\,
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \^stateop_reg[5]_0\(2),
      I3 => \^stateop_reg[5]_0\(3),
      I4 => \^stateop_reg[5]_0\(4),
      I5 => \txAXIS_tdata[15]_i_10_n_0\,
      O => \txAXIS_tdata[15]_i_3_n_0\
    );
\txAXIS_tdata[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[15]_i_4_n_0\
    );
\txAXIS_tdata[15]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAEAFFEAEA"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_11_n_0\,
      I1 => \txAXIS_tdata[15]_i_12_n_0\,
      I2 => \wordcntLast[28]_i_9_n_0\,
      I3 => \wordcntLast[28]_i_10_n_0\,
      I4 => seqbufHshktrackToHostifAXIS_tvalid,
      I5 => \pollbuf[0][7]_i_7_n_0\,
      O => \txAXIS_tdata[15]_i_5_n_0\
    );
\txAXIS_tdata[15]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888BBB8B"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_17_n_0\,
      I1 => \txAXIS_tdata[55]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[0][7]\,
      I3 => \txAXIS_tdata[63]_i_9_n_0\,
      I4 => \retbuf_reg_n_0_[33][7]\,
      O => \txAXIS_tdata[15]_i_7_n_0\
    );
\txAXIS_tdata[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(1),
      O => \txAXIS_tdata[15]_i_8_n_0\
    );
\txAXIS_tdata[15]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => resid(2),
      I1 => resid(1),
      I2 => resid(0),
      O => \txAXIS_tdata[15]_i_9_n_0\
    );
\txAXIS_tdata[16]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[34][0]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][0]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[16]_i_5_n_0\,
      O => \txAXIS_tdata[16]_i_2_n_0\
    );
\txAXIS_tdata[16]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[16]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[16]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[16]_i_4_n_0\
    );
\txAXIS_tdata[16]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[10][0]\,
      I1 => \retbuf_reg_n_0_[2][0]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[26][0]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[18][0]\,
      O => \txAXIS_tdata[16]_i_5_n_0\
    );
\txAXIS_tdata[16]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(16),
      I1 => \txAXIS_tdata[63]_i_8_0\(16),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(16),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(16),
      O => \txAXIS_tdata[16]_i_6_n_0\
    );
\txAXIS_tdata[16]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(16),
      I1 => \txAXIS_tdata[63]_i_8_4\(16),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(16),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[16]_i_7_n_0\
    );
\txAXIS_tdata[17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[34][1]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][1]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[17]_i_5_n_0\,
      O => \txAXIS_tdata[17]_i_2_n_0\
    );
\txAXIS_tdata[17]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[17]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[17]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[17]_i_4_n_0\
    );
\txAXIS_tdata[17]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[10][1]\,
      I1 => \retbuf_reg_n_0_[2][1]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[26][1]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[18][1]\,
      O => \txAXIS_tdata[17]_i_5_n_0\
    );
\txAXIS_tdata[17]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(17),
      I1 => \txAXIS_tdata[63]_i_8_0\(17),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(17),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(17),
      O => \txAXIS_tdata[17]_i_6_n_0\
    );
\txAXIS_tdata[17]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(17),
      I1 => \txAXIS_tdata[63]_i_8_4\(17),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(17),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[17]_i_7_n_0\
    );
\txAXIS_tdata[18]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[34][2]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][2]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[18]_i_5_n_0\,
      O => \txAXIS_tdata[18]_i_2_n_0\
    );
\txAXIS_tdata[18]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[18]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[18]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[18]_i_4_n_0\
    );
\txAXIS_tdata[18]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[10][2]\,
      I1 => \retbuf_reg_n_0_[2][2]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[26][2]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[18][2]\,
      O => \txAXIS_tdata[18]_i_5_n_0\
    );
\txAXIS_tdata[18]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(18),
      I1 => \txAXIS_tdata[63]_i_8_0\(18),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(18),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(18),
      O => \txAXIS_tdata[18]_i_6_n_0\
    );
\txAXIS_tdata[18]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(18),
      I1 => \txAXIS_tdata[63]_i_8_4\(18),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(18),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[18]_i_7_n_0\
    );
\txAXIS_tdata[19]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[34][3]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][3]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[19]_i_5_n_0\,
      O => \txAXIS_tdata[19]_i_2_n_0\
    );
\txAXIS_tdata[19]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[19]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[19]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[19]_i_4_n_0\
    );
\txAXIS_tdata[19]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[10][3]\,
      I1 => \retbuf_reg_n_0_[2][3]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[26][3]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[18][3]\,
      O => \txAXIS_tdata[19]_i_5_n_0\
    );
\txAXIS_tdata[19]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(19),
      I1 => \txAXIS_tdata[63]_i_8_0\(19),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(19),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(19),
      O => \txAXIS_tdata[19]_i_6_n_0\
    );
\txAXIS_tdata[19]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(19),
      I1 => \txAXIS_tdata[63]_i_8_4\(19),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(19),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[19]_i_7_n_0\
    );
\txAXIS_tdata[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \pollbuf[0][7]_i_7_n_0\,
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(1),
      I3 => \^stateop_reg[5]_0\(2),
      I4 => \txlen[28]_i_4_n_0\,
      I5 => \txAXIS_tdata_reg[1]_i_6_n_0\,
      O => \txAXIS_tdata[1]_i_4_n_0\
    );
\txAXIS_tdata[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf_reg_n_0_[24][1]\,
      I1 => \retbuf_reg[16]_65\(1),
      I2 => \txAXIS_tdata[3]_i_7_n_0\,
      I3 => \retbuf_reg_n_0_[8][1]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[0][1]\,
      O => \txAXIS_tdata[1]_i_5_n_0\
    );
\txAXIS_tdata[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => doutb(1),
      I1 => \txAXIS_tdata[63]_i_8_0\(1),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(1),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(1),
      O => \txAXIS_tdata[1]_i_7_n_0\
    );
\txAXIS_tdata[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"470047FF47FF47FF"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(1),
      I1 => \txAXIS_tdata[47]_i_10_n_0\,
      I2 => \txAXIS_tdata[63]_i_8_4\(1),
      I3 => \txAXIS_tdata[63]_i_15_n_0\,
      I4 => \txAXIS_tdata[63]_i_8_5\(1),
      I5 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[1]_i_8_n_0\
    );
\txAXIS_tdata[20]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[34][4]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][4]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[20]_i_5_n_0\,
      O => \txAXIS_tdata[20]_i_2_n_0\
    );
\txAXIS_tdata[20]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[20]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[20]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[20]_i_4_n_0\
    );
\txAXIS_tdata[20]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[10][4]\,
      I1 => \retbuf_reg_n_0_[2][4]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[26][4]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[18][4]\,
      O => \txAXIS_tdata[20]_i_5_n_0\
    );
\txAXIS_tdata[20]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(20),
      I1 => \txAXIS_tdata[63]_i_8_0\(20),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(20),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(20),
      O => \txAXIS_tdata[20]_i_6_n_0\
    );
\txAXIS_tdata[20]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(20),
      I1 => \txAXIS_tdata[63]_i_8_4\(20),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(20),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[20]_i_7_n_0\
    );
\txAXIS_tdata[21]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[34][5]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][5]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[21]_i_5_n_0\,
      O => \txAXIS_tdata[21]_i_2_n_0\
    );
\txAXIS_tdata[21]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[21]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[21]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[21]_i_4_n_0\
    );
\txAXIS_tdata[21]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[10][5]\,
      I1 => \retbuf_reg_n_0_[2][5]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[26][5]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[18][5]\,
      O => \txAXIS_tdata[21]_i_5_n_0\
    );
\txAXIS_tdata[21]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(21),
      I1 => \txAXIS_tdata[63]_i_8_0\(21),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(21),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(21),
      O => \txAXIS_tdata[21]_i_6_n_0\
    );
\txAXIS_tdata[21]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(21),
      I1 => \txAXIS_tdata[63]_i_8_4\(21),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(21),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[21]_i_7_n_0\
    );
\txAXIS_tdata[22]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[34][6]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][6]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[22]_i_6_n_0\,
      O => \txAXIS_tdata[22]_i_2_n_0\
    );
\txAXIS_tdata[22]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(2),
      I1 => \^stateop_reg[5]_0\(1),
      I2 => resid(2),
      I3 => resid(1),
      O => \txAXIS_tdata[22]_i_4_n_0\
    );
\txAXIS_tdata[22]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[22]_i_7_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[22]_i_8_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[22]_i_5_n_0\
    );
\txAXIS_tdata[22]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[10][6]\,
      I1 => \retbuf_reg_n_0_[2][6]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[26][6]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[18][6]\,
      O => \txAXIS_tdata[22]_i_6_n_0\
    );
\txAXIS_tdata[22]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(22),
      I1 => \txAXIS_tdata[63]_i_8_0\(22),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(22),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(22),
      O => \txAXIS_tdata[22]_i_7_n_0\
    );
\txAXIS_tdata[22]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(22),
      I1 => \txAXIS_tdata[63]_i_8_4\(22),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(22),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[22]_i_8_n_0\
    );
\txAXIS_tdata[23]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(23),
      I1 => \txAXIS_tdata[63]_i_8_4\(23),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(23),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[23]_i_10_n_0\
    );
\txAXIS_tdata[23]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(3),
      O => \txAXIS_tdata[23]_i_3_n_0\
    );
\txAXIS_tdata[23]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      O => \txAXIS_tdata[23]_i_4_n_0\
    );
\txAXIS_tdata[23]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[34][7]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][7]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[23]_i_8_n_0\,
      O => \txAXIS_tdata[23]_i_5_n_0\
    );
\txAXIS_tdata[23]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[23]_i_9_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[23]_i_10_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[23]_i_7_n_0\
    );
\txAXIS_tdata[23]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[10][7]\,
      I1 => \retbuf_reg_n_0_[2][7]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[26][7]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[18][7]\,
      O => \txAXIS_tdata[23]_i_8_n_0\
    );
\txAXIS_tdata[23]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(23),
      I1 => \txAXIS_tdata[63]_i_8_0\(23),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(23),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(23),
      O => \txAXIS_tdata[23]_i_9_n_0\
    );
\txAXIS_tdata[24]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[35][0]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][0]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[24]_i_5_n_0\,
      O => \txAXIS_tdata[24]_i_2_n_0\
    );
\txAXIS_tdata[24]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[24]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[24]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[24]_i_4_n_0\
    );
\txAXIS_tdata[24]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][0]\,
      I1 => \retbuf_reg_n_0_[3][0]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[27][0]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[19][0]\,
      O => \txAXIS_tdata[24]_i_5_n_0\
    );
\txAXIS_tdata[24]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(24),
      I1 => \txAXIS_tdata[63]_i_8_0\(24),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(24),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(24),
      O => \txAXIS_tdata[24]_i_6_n_0\
    );
\txAXIS_tdata[24]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(24),
      I1 => \txAXIS_tdata[63]_i_8_4\(24),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(24),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[24]_i_7_n_0\
    );
\txAXIS_tdata[25]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[35][1]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][1]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[25]_i_5_n_0\,
      O => \txAXIS_tdata[25]_i_2_n_0\
    );
\txAXIS_tdata[25]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[25]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[25]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[25]_i_4_n_0\
    );
\txAXIS_tdata[25]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][1]\,
      I1 => \retbuf_reg_n_0_[3][1]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[27][1]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[19][1]\,
      O => \txAXIS_tdata[25]_i_5_n_0\
    );
\txAXIS_tdata[25]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(25),
      I1 => \txAXIS_tdata[63]_i_8_0\(25),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(25),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(25),
      O => \txAXIS_tdata[25]_i_6_n_0\
    );
\txAXIS_tdata[25]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(25),
      I1 => \txAXIS_tdata[63]_i_8_4\(25),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(25),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[25]_i_7_n_0\
    );
\txAXIS_tdata[26]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[35][2]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][2]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[26]_i_5_n_0\,
      O => \txAXIS_tdata[26]_i_2_n_0\
    );
\txAXIS_tdata[26]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[26]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[26]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[26]_i_4_n_0\
    );
\txAXIS_tdata[26]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][2]\,
      I1 => \retbuf_reg_n_0_[3][2]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[27][2]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[19][2]\,
      O => \txAXIS_tdata[26]_i_5_n_0\
    );
\txAXIS_tdata[26]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(26),
      I1 => \txAXIS_tdata[63]_i_8_0\(26),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(26),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(26),
      O => \txAXIS_tdata[26]_i_6_n_0\
    );
\txAXIS_tdata[26]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(26),
      I1 => \txAXIS_tdata[63]_i_8_4\(26),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(26),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[26]_i_7_n_0\
    );
\txAXIS_tdata[27]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[35][3]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][3]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[27]_i_5_n_0\,
      O => \txAXIS_tdata[27]_i_2_n_0\
    );
\txAXIS_tdata[27]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[27]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[27]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[27]_i_4_n_0\
    );
\txAXIS_tdata[27]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][3]\,
      I1 => \retbuf_reg_n_0_[3][3]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[27][3]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[19][3]\,
      O => \txAXIS_tdata[27]_i_5_n_0\
    );
\txAXIS_tdata[27]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(27),
      I1 => \txAXIS_tdata[63]_i_8_0\(27),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(27),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(27),
      O => \txAXIS_tdata[27]_i_6_n_0\
    );
\txAXIS_tdata[27]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(27),
      I1 => \txAXIS_tdata[63]_i_8_4\(27),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(27),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[27]_i_7_n_0\
    );
\txAXIS_tdata[28]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[35][4]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][4]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[28]_i_5_n_0\,
      O => \txAXIS_tdata[28]_i_2_n_0\
    );
\txAXIS_tdata[28]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[28]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[28]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[28]_i_4_n_0\
    );
\txAXIS_tdata[28]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][4]\,
      I1 => \retbuf_reg_n_0_[3][4]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[27][4]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[19][4]\,
      O => \txAXIS_tdata[28]_i_5_n_0\
    );
\txAXIS_tdata[28]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(28),
      I1 => \txAXIS_tdata[63]_i_8_0\(28),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(28),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(28),
      O => \txAXIS_tdata[28]_i_6_n_0\
    );
\txAXIS_tdata[28]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(28),
      I1 => \txAXIS_tdata[63]_i_8_4\(28),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(28),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[28]_i_7_n_0\
    );
\txAXIS_tdata[29]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[35][5]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][5]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[29]_i_6_n_0\,
      O => \txAXIS_tdata[29]_i_2_n_0\
    );
\txAXIS_tdata[29]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[29]_i_3_n_0\
    );
\txAXIS_tdata[29]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[29]_i_8_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[29]_i_9_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[29]_i_5_n_0\
    );
\txAXIS_tdata[29]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][5]\,
      I1 => \retbuf_reg_n_0_[3][5]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[27][5]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[19][5]\,
      O => \txAXIS_tdata[29]_i_6_n_0\
    );
\txAXIS_tdata[29]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[29]_i_7_n_0\
    );
\txAXIS_tdata[29]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(29),
      I1 => \txAXIS_tdata[63]_i_8_0\(29),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(29),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(29),
      O => \txAXIS_tdata[29]_i_8_n_0\
    );
\txAXIS_tdata[29]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(29),
      I1 => \txAXIS_tdata[63]_i_8_4\(29),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(29),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[29]_i_9_n_0\
    );
\txAXIS_tdata[2]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(2),
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(1),
      I3 => \^stateop_reg[5]_0\(3),
      O => \txAXIS_tdata[2]_i_10_n_0\
    );
\txAXIS_tdata[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20AAA8AA"
    )
        port map (
      I0 => \txAXIS_tdata[6]_i_7__0_n_0\,
      I1 => \txAXIS_tdata[55]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[32][2]\,
      I3 => \^stateop_reg[5]_0\(4),
      I4 => \txAXIS_tdata[2]_i_6_n_0\,
      O => \txAXIS_tdata[2]_i_2_n_0\
    );
\txAXIS_tdata[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000E200000000"
    )
        port map (
      I0 => \txAXIS_tdata[2]_i_8_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[2]_i_9_n_0\,
      I3 => \pollbuf[0][7]_i_7_n_0\,
      I4 => \^stateop_reg[5]_0\(0),
      I5 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[2]_i_4_n_0\
    );
\txAXIS_tdata[2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF4FFF44"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \^stateop_reg[5]_0\(2),
      I3 => \^stateop_reg[5]_0\(5),
      I4 => \^stateop_reg[5]_0\(0),
      O => \txAXIS_tdata[2]_i_5_n_0\
    );
\txAXIS_tdata[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[24][2]\,
      I1 => \retbuf_reg[16]_65\(2),
      I2 => \txAXIS_tdata[3]_i_7_n_0\,
      I3 => \retbuf_reg_n_0_[8][2]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[0][2]\,
      O => \txAXIS_tdata[2]_i_6_n_0\
    );
\txAXIS_tdata[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(2),
      I1 => \txAXIS_tdata[63]_i_8_0\(2),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(2),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(2),
      O => \txAXIS_tdata[2]_i_8_n_0\
    );
\txAXIS_tdata[2]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(2),
      I1 => \txAXIS_tdata[63]_i_8_4\(2),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(2),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[2]_i_9_n_0\
    );
\txAXIS_tdata[30]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[35][6]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][6]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[30]_i_5_n_0\,
      O => \txAXIS_tdata[30]_i_2_n_0\
    );
\txAXIS_tdata[30]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[30]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[30]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[30]_i_4_n_0\
    );
\txAXIS_tdata[30]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][6]\,
      I1 => \retbuf_reg_n_0_[3][6]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[27][6]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[19][6]\,
      O => \txAXIS_tdata[30]_i_5_n_0\
    );
\txAXIS_tdata[30]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(30),
      I1 => \txAXIS_tdata[63]_i_8_0\(30),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(30),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(30),
      O => \txAXIS_tdata[30]_i_6_n_0\
    );
\txAXIS_tdata[30]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(30),
      I1 => \txAXIS_tdata[63]_i_8_4\(30),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(30),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[30]_i_7_n_0\
    );
\txAXIS_tdata[31]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(31),
      I1 => \txAXIS_tdata[63]_i_8_4\(31),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(31),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[31]_i_10_n_0\
    );
\txAXIS_tdata[31]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000E700FFFF"
    )
        port map (
      I0 => resid(1),
      I1 => resid(0),
      I2 => resid(2),
      I3 => \^stateop_reg[5]_0\(1),
      I4 => \txAXIS_tdata[31]_i_7_n_0\,
      I5 => \^stateop_reg[5]_0\(3),
      O => \txAXIS_tdata[31]_i_3_n_0\
    );
\txAXIS_tdata[31]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[35][7]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][7]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[31]_i_8_n_0\,
      O => \txAXIS_tdata[31]_i_4_n_0\
    );
\txAXIS_tdata[31]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_9_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[31]_i_10_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[31]_i_6_n_0\
    );
\txAXIS_tdata[31]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[31]_i_7_n_0\
    );
\txAXIS_tdata[31]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][7]\,
      I1 => \retbuf_reg_n_0_[3][7]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[27][7]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[19][7]\,
      O => \txAXIS_tdata[31]_i_8_n_0\
    );
\txAXIS_tdata[31]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(31),
      I1 => \txAXIS_tdata[63]_i_8_0\(31),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(31),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(31),
      O => \txAXIS_tdata[31]_i_9_n_0\
    );
\txAXIS_tdata[32]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[36][0]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][0]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[32]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[32]_i_2_n_0\
    );
\txAXIS_tdata[32]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[12][0]\,
      I1 => \retbuf_reg_n_0_[4][0]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[28][0]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[20][0]\,
      O => \txAXIS_tdata[32]_i_4_n_0\
    );
\txAXIS_tdata[32]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF1DFFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata[32]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[32]_i_7_n_0\,
      I3 => \pollbuf[0][7]_i_7_n_0\,
      I4 => \^stateop_reg[5]_0\(3),
      I5 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[32]_i_5_n_0\
    );
\txAXIS_tdata[32]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(32),
      I1 => \txAXIS_tdata[63]_i_8_0\(32),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(32),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(32),
      O => \txAXIS_tdata[32]_i_6_n_0\
    );
\txAXIS_tdata[32]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(32),
      I1 => \txAXIS_tdata[63]_i_8_4\(32),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(32),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[32]_i_7_n_0\
    );
\txAXIS_tdata[33]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[36][1]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][1]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[33]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[33]_i_2_n_0\
    );
\txAXIS_tdata[33]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[12][1]\,
      I1 => \retbuf_reg_n_0_[4][1]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[28][1]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[20][1]\,
      O => \txAXIS_tdata[33]_i_4_n_0\
    );
\txAXIS_tdata[33]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000E200000000"
    )
        port map (
      I0 => \txAXIS_tdata[33]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[33]_i_7_n_0\,
      I3 => \pollbuf[0][7]_i_7_n_0\,
      I4 => \^stateop_reg[5]_0\(3),
      I5 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[33]_i_5_n_0\
    );
\txAXIS_tdata[33]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(33),
      I1 => \txAXIS_tdata[63]_i_8_0\(33),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(33),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(33),
      O => \txAXIS_tdata[33]_i_6_n_0\
    );
\txAXIS_tdata[33]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(33),
      I1 => \txAXIS_tdata[63]_i_8_4\(33),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(33),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[33]_i_7_n_0\
    );
\txAXIS_tdata[34]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[36][2]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][2]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[34]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[34]_i_2_n_0\
    );
\txAXIS_tdata[34]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[12][2]\,
      I1 => \retbuf_reg_n_0_[4][2]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[28][2]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[20][2]\,
      O => \txAXIS_tdata[34]_i_4_n_0\
    );
\txAXIS_tdata[34]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF1DFFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata[34]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[34]_i_7_n_0\,
      I3 => \pollbuf[0][7]_i_7_n_0\,
      I4 => \^stateop_reg[5]_0\(3),
      I5 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[34]_i_5_n_0\
    );
\txAXIS_tdata[34]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(34),
      I1 => \txAXIS_tdata[63]_i_8_0\(34),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(34),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(34),
      O => \txAXIS_tdata[34]_i_6_n_0\
    );
\txAXIS_tdata[34]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(34),
      I1 => \txAXIS_tdata[63]_i_8_4\(34),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(34),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[34]_i_7_n_0\
    );
\txAXIS_tdata[35]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[36][3]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][3]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[35]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[35]_i_2_n_0\
    );
\txAXIS_tdata[35]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[12][3]\,
      I1 => \retbuf_reg_n_0_[4][3]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[28][3]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[20][3]\,
      O => \txAXIS_tdata[35]_i_4_n_0\
    );
\txAXIS_tdata[35]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF1DFFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata[35]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[35]_i_7_n_0\,
      I3 => \pollbuf[0][7]_i_7_n_0\,
      I4 => \^stateop_reg[5]_0\(3),
      I5 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[35]_i_5_n_0\
    );
\txAXIS_tdata[35]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(35),
      I1 => \txAXIS_tdata[63]_i_8_0\(35),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(35),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(35),
      O => \txAXIS_tdata[35]_i_6_n_0\
    );
\txAXIS_tdata[35]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(35),
      I1 => \txAXIS_tdata[63]_i_8_4\(35),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(35),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[35]_i_7_n_0\
    );
\txAXIS_tdata[36]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[36][4]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][4]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[36]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[36]_i_2_n_0\
    );
\txAXIS_tdata[36]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[12][4]\,
      I1 => \retbuf_reg_n_0_[4][4]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[28][4]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[20][4]\,
      O => \txAXIS_tdata[36]_i_4_n_0\
    );
\txAXIS_tdata[36]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF1DFFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata[36]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[36]_i_7_n_0\,
      I3 => \pollbuf[0][7]_i_7_n_0\,
      I4 => \^stateop_reg[5]_0\(3),
      I5 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[36]_i_5_n_0\
    );
\txAXIS_tdata[36]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(36),
      I1 => \txAXIS_tdata[63]_i_8_0\(36),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(36),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(36),
      O => \txAXIS_tdata[36]_i_6_n_0\
    );
\txAXIS_tdata[36]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(36),
      I1 => \txAXIS_tdata[63]_i_8_4\(36),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(36),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[36]_i_7_n_0\
    );
\txAXIS_tdata[37]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[36][5]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][5]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[37]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[37]_i_2_n_0\
    );
\txAXIS_tdata[37]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[12][5]\,
      I1 => \retbuf_reg_n_0_[4][5]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[28][5]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[20][5]\,
      O => \txAXIS_tdata[37]_i_4_n_0\
    );
\txAXIS_tdata[37]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000E200000000"
    )
        port map (
      I0 => \txAXIS_tdata[37]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[37]_i_7_n_0\,
      I3 => \pollbuf[0][7]_i_7_n_0\,
      I4 => \^stateop_reg[5]_0\(3),
      I5 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[37]_i_5_n_0\
    );
\txAXIS_tdata[37]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(37),
      I1 => \txAXIS_tdata[63]_i_8_0\(37),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(37),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(37),
      O => \txAXIS_tdata[37]_i_6_n_0\
    );
\txAXIS_tdata[37]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(37),
      I1 => \txAXIS_tdata[63]_i_8_4\(37),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(37),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[37]_i_7_n_0\
    );
\txAXIS_tdata[38]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[36][6]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][6]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[38]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[38]_i_2_n_0\
    );
\txAXIS_tdata[38]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[12][6]\,
      I1 => \retbuf_reg_n_0_[4][6]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[28][6]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[20][6]\,
      O => \txAXIS_tdata[38]_i_4_n_0\
    );
\txAXIS_tdata[38]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000E200000000"
    )
        port map (
      I0 => \txAXIS_tdata[38]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[38]_i_7_n_0\,
      I3 => \pollbuf[0][7]_i_7_n_0\,
      I4 => \^stateop_reg[5]_0\(3),
      I5 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[38]_i_5_n_0\
    );
\txAXIS_tdata[38]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(38),
      I1 => \txAXIS_tdata[63]_i_8_0\(38),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(38),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(38),
      O => \txAXIS_tdata[38]_i_6_n_0\
    );
\txAXIS_tdata[38]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(38),
      I1 => \txAXIS_tdata[63]_i_8_4\(38),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(38),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[38]_i_7_n_0\
    );
\txAXIS_tdata[39]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(39),
      I1 => \txAXIS_tdata[63]_i_8_0\(39),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(39),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(39),
      O => \txAXIS_tdata[39]_i_10_n_0\
    );
\txAXIS_tdata[39]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(39),
      I1 => \txAXIS_tdata[63]_i_8_4\(39),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(39),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[39]_i_11_n_0\
    );
\txAXIS_tdata[39]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"007C"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_5_n_0\,
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \^stateop_reg[5]_0\(2),
      I3 => \^stateop_reg[5]_0\(3),
      O => \txAXIS_tdata[39]_i_3_n_0\
    );
\txAXIS_tdata[39]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEEEFF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(2),
      I3 => \^stateop_reg[5]_0\(4),
      I4 => \^stateop_reg[5]_0\(3),
      O => \txAXIS_tdata[39]_i_4_n_0\
    );
\txAXIS_tdata[39]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[36][7]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][7]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[39]_i_7_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[39]_i_5_n_0\
    );
\txAXIS_tdata[39]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[12][7]\,
      I1 => \retbuf_reg_n_0_[4][7]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[28][7]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[20][7]\,
      O => \txAXIS_tdata[39]_i_7_n_0\
    );
\txAXIS_tdata[39]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF1DFFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata[39]_i_10_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[39]_i_11_n_0\,
      I3 => \pollbuf[0][7]_i_7_n_0\,
      I4 => \^stateop_reg[5]_0\(3),
      I5 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[39]_i_8_n_0\
    );
\txAXIS_tdata[39]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      I2 => \^stateop_reg[5]_0\(2),
      I3 => \^stateop_reg[5]_0\(3),
      O => \txAXIS_tdata[39]_i_9_n_0\
    );
\txAXIS_tdata[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \pollbuf[0][7]_i_7_n_0\,
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(1),
      I3 => \^stateop_reg[5]_0\(2),
      I4 => \txlen[28]_i_4_n_0\,
      I5 => \txAXIS_tdata_reg[3]_i_6_n_0\,
      O => \txAXIS_tdata[3]_i_4_n_0\
    );
\txAXIS_tdata[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf_reg_n_0_[24][3]\,
      I1 => \retbuf_reg[16]_65\(3),
      I2 => \txAXIS_tdata[3]_i_7_n_0\,
      I3 => \retbuf_reg_n_0_[8][3]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[0][3]\,
      O => \txAXIS_tdata[3]_i_5_n_0\
    );
\txAXIS_tdata[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"058D8D0500888800"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[25]\,
      I1 => \opbuf_reg[0]5\(8),
      I2 => \opbuf_reg[0]51_in\(8),
      I3 => \opbuf_reg[0]5\(7),
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \opbuf_reg[0]51_in\(7),
      O => \txAXIS_tdata[3]_i_7_n_0\
    );
\txAXIS_tdata[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => doutb(3),
      I1 => \txAXIS_tdata[63]_i_8_0\(3),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(3),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(3),
      O => \txAXIS_tdata[3]_i_8_n_0\
    );
\txAXIS_tdata[3]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"470047FF47FF47FF"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(3),
      I1 => \txAXIS_tdata[47]_i_10_n_0\,
      I2 => \txAXIS_tdata[63]_i_8_4\(3),
      I3 => \txAXIS_tdata[63]_i_15_n_0\,
      I4 => \txAXIS_tdata[63]_i_8_5\(3),
      I5 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[3]_i_9_n_0\
    );
\txAXIS_tdata[40]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[37][0]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][0]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[40]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[40]_i_2_n_0\
    );
\txAXIS_tdata[40]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[13][0]\,
      I1 => \retbuf_reg_n_0_[5][0]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[29][0]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[21][0]\,
      O => \txAXIS_tdata[40]_i_4_n_0\
    );
\txAXIS_tdata[40]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(40),
      I1 => \txAXIS_tdata[63]_i_8_0\(40),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(40),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(40),
      O => \txAXIS_tdata[40]_i_5_n_0\
    );
\txAXIS_tdata[40]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8FFB800B800B800"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(40),
      I1 => \txAXIS_tdata[47]_i_10_n_0\,
      I2 => \txAXIS_tdata[63]_i_8_4\(40),
      I3 => \txAXIS_tdata[63]_i_15_n_0\,
      I4 => \txAXIS_tdata[63]_i_8_5\(40),
      I5 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[40]_i_6_n_0\
    );
\txAXIS_tdata[41]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[37][1]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][1]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[41]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[41]_i_2_n_0\
    );
\txAXIS_tdata[41]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[13][1]\,
      I1 => \retbuf_reg_n_0_[5][1]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[29][1]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[21][1]\,
      O => \txAXIS_tdata[41]_i_4_n_0\
    );
\txAXIS_tdata[41]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(41),
      I1 => \txAXIS_tdata[63]_i_8_0\(41),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(41),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(41),
      O => \txAXIS_tdata[41]_i_5_n_0\
    );
\txAXIS_tdata[41]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8FFB800B800B800"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(41),
      I1 => \txAXIS_tdata[47]_i_10_n_0\,
      I2 => \txAXIS_tdata[63]_i_8_4\(41),
      I3 => \txAXIS_tdata[63]_i_15_n_0\,
      I4 => \txAXIS_tdata[63]_i_8_5\(41),
      I5 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[41]_i_6_n_0\
    );
\txAXIS_tdata[42]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[37][2]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][2]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[42]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[42]_i_2_n_0\
    );
\txAXIS_tdata[42]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[13][2]\,
      I1 => \retbuf_reg_n_0_[5][2]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[29][2]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[21][2]\,
      O => \txAXIS_tdata[42]_i_4_n_0\
    );
\txAXIS_tdata[42]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(42),
      I1 => \txAXIS_tdata[63]_i_8_0\(42),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(42),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(42),
      O => \txAXIS_tdata[42]_i_5_n_0\
    );
\txAXIS_tdata[42]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8FFB800B800B800"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(42),
      I1 => \txAXIS_tdata[47]_i_10_n_0\,
      I2 => \txAXIS_tdata[63]_i_8_4\(42),
      I3 => \txAXIS_tdata[63]_i_15_n_0\,
      I4 => \txAXIS_tdata[63]_i_8_5\(42),
      I5 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[42]_i_6_n_0\
    );
\txAXIS_tdata[43]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[37][3]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][3]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[43]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[43]_i_2_n_0\
    );
\txAXIS_tdata[43]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[13][3]\,
      I1 => \retbuf_reg_n_0_[5][3]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[29][3]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[21][3]\,
      O => \txAXIS_tdata[43]_i_4_n_0\
    );
\txAXIS_tdata[43]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(43),
      I1 => \txAXIS_tdata[63]_i_8_0\(43),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(43),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(43),
      O => \txAXIS_tdata[43]_i_5_n_0\
    );
\txAXIS_tdata[43]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8FFB800B800B800"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(43),
      I1 => \txAXIS_tdata[47]_i_10_n_0\,
      I2 => \txAXIS_tdata[63]_i_8_4\(43),
      I3 => \txAXIS_tdata[63]_i_15_n_0\,
      I4 => \txAXIS_tdata[63]_i_8_5\(43),
      I5 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[43]_i_6_n_0\
    );
\txAXIS_tdata[44]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[37][4]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][4]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[44]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[44]_i_2_n_0\
    );
\txAXIS_tdata[44]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[13][4]\,
      I1 => \retbuf_reg_n_0_[5][4]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[29][4]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[21][4]\,
      O => \txAXIS_tdata[44]_i_4_n_0\
    );
\txAXIS_tdata[44]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(44),
      I1 => \txAXIS_tdata[63]_i_8_0\(44),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(44),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(44),
      O => \txAXIS_tdata[44]_i_5_n_0\
    );
\txAXIS_tdata[44]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8FFB800B800B800"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(44),
      I1 => \txAXIS_tdata[47]_i_10_n_0\,
      I2 => \txAXIS_tdata[63]_i_8_4\(44),
      I3 => \txAXIS_tdata[63]_i_15_n_0\,
      I4 => \txAXIS_tdata[63]_i_8_5\(44),
      I5 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[44]_i_6_n_0\
    );
\txAXIS_tdata[45]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[37][5]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][5]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[45]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[45]_i_2_n_0\
    );
\txAXIS_tdata[45]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[13][5]\,
      I1 => \retbuf_reg_n_0_[5][5]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[29][5]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[21][5]\,
      O => \txAXIS_tdata[45]_i_4_n_0\
    );
\txAXIS_tdata[45]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(45),
      I1 => \txAXIS_tdata[63]_i_8_0\(45),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(45),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(45),
      O => \txAXIS_tdata[45]_i_5_n_0\
    );
\txAXIS_tdata[45]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8FFB800B800B800"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(45),
      I1 => \txAXIS_tdata[47]_i_10_n_0\,
      I2 => \txAXIS_tdata[63]_i_8_4\(45),
      I3 => \txAXIS_tdata[63]_i_15_n_0\,
      I4 => \txAXIS_tdata[63]_i_8_5\(45),
      I5 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[45]_i_6_n_0\
    );
\txAXIS_tdata[46]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[37][6]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][6]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[46]_i_4_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[46]_i_2_n_0\
    );
\txAXIS_tdata[46]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[13][6]\,
      I1 => \retbuf_reg_n_0_[5][6]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[29][6]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[21][6]\,
      O => \txAXIS_tdata[46]_i_4_n_0\
    );
\txAXIS_tdata[46]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(46),
      I1 => \txAXIS_tdata[63]_i_8_0\(46),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(46),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(46),
      O => \txAXIS_tdata[46]_i_5_n_0\
    );
\txAXIS_tdata[46]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8FFB800B800B800"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(46),
      I1 => \txAXIS_tdata[47]_i_10_n_0\,
      I2 => \txAXIS_tdata[63]_i_8_4\(46),
      I3 => \txAXIS_tdata[63]_i_15_n_0\,
      I4 => \txAXIS_tdata[63]_i_8_5\(46),
      I5 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[46]_i_6_n_0\
    );
\txAXIS_tdata[47]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9C"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[0]\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => \tixVBuffer_reg_n_0_[1]\,
      O => \txAXIS_tdata[47]_i_10_n_0\
    );
\txAXIS_tdata[47]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055757555"
    )
        port map (
      I0 => \txAXIS_tdata[39]_i_3_n_0\,
      I1 => \^stateop_reg[5]_0\(2),
      I2 => resid(2),
      I3 => resid(0),
      I4 => resid(1),
      I5 => \txAXIS_tdata[39]_i_4_n_0\,
      O => \txAXIS_tdata[47]_i_3_n_0\
    );
\txAXIS_tdata[47]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF470047FFFFFFFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[37][7]\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[0][7]\,
      I3 => \txAXIS_tdata[55]_i_6_n_0\,
      I4 => \txAXIS_tdata[47]_i_6_n_0\,
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[47]_i_4_n_0\
    );
\txAXIS_tdata[47]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[13][7]\,
      I1 => \retbuf_reg_n_0_[5][7]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[29][7]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[21][7]\,
      O => \txAXIS_tdata[47]_i_6_n_0\
    );
\txAXIS_tdata[47]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(47),
      I1 => \txAXIS_tdata[63]_i_8_0\(47),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(47),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(47),
      O => \txAXIS_tdata[47]_i_7_n_0\
    );
\txAXIS_tdata[47]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8FFB800B800B800"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(47),
      I1 => \txAXIS_tdata[47]_i_10_n_0\,
      I2 => \txAXIS_tdata[63]_i_8_4\(47),
      I3 => \txAXIS_tdata[63]_i_15_n_0\,
      I4 => \txAXIS_tdata[63]_i_8_5\(47),
      I5 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[47]_i_8_n_0\
    );
\txAXIS_tdata[48]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf_reg_n_0_[14][0]\,
      I1 => \retbuf_reg_n_0_[6][0]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[30][0]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[22][0]\,
      O => \txAXIS_tdata[48]_i_2_n_0\
    );
\txAXIS_tdata[48]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0415FFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata[55]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[38][0]\,
      I3 => \retbuf_reg_n_0_[0][0]\,
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[48]_i_3_n_0\
    );
\txAXIS_tdata[48]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(48),
      I1 => \txAXIS_tdata[63]_i_8_0\(48),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(48),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(48),
      O => \txAXIS_tdata[48]_i_5_n_0\
    );
\txAXIS_tdata[48]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(48),
      I1 => \txAXIS_tdata[63]_i_8_4\(48),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(48),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[48]_i_6_n_0\
    );
\txAXIS_tdata[49]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf_reg_n_0_[14][1]\,
      I1 => \retbuf_reg_n_0_[6][1]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[30][1]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[22][1]\,
      O => \txAXIS_tdata[49]_i_2_n_0\
    );
\txAXIS_tdata[49]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0415FFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata[55]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[38][1]\,
      I3 => \retbuf_reg_n_0_[0][1]\,
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[49]_i_3_n_0\
    );
\txAXIS_tdata[49]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(49),
      I1 => \txAXIS_tdata[63]_i_8_0\(49),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(49),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(49),
      O => \txAXIS_tdata[49]_i_5_n_0\
    );
\txAXIS_tdata[49]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(49),
      I1 => \txAXIS_tdata[63]_i_8_4\(49),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(49),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[49]_i_6_n_0\
    );
\txAXIS_tdata[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20AAA8AA"
    )
        port map (
      I0 => \txAXIS_tdata[6]_i_7__0_n_0\,
      I1 => \txAXIS_tdata[55]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[32][4]\,
      I3 => \^stateop_reg[5]_0\(4),
      I4 => \txAXIS_tdata[4]_i_5_n_0\,
      O => \txAXIS_tdata[4]_i_2_n_0\
    );
\txAXIS_tdata[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000E200000000"
    )
        port map (
      I0 => \txAXIS_tdata[4]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[4]_i_7_n_0\,
      I3 => \pollbuf[0][7]_i_7_n_0\,
      I4 => \^stateop_reg[5]_0\(0),
      I5 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[4]_i_4_n_0\
    );
\txAXIS_tdata[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[8][4]\,
      I1 => \retbuf_reg_n_0_[0][4]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[24][4]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg[16]_65\(4),
      O => \txAXIS_tdata[4]_i_5_n_0\
    );
\txAXIS_tdata[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(4),
      I1 => \txAXIS_tdata[63]_i_8_0\(4),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(4),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(4),
      O => \txAXIS_tdata[4]_i_6_n_0\
    );
\txAXIS_tdata[4]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(4),
      I1 => \txAXIS_tdata[63]_i_8_4\(4),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(4),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[4]_i_7_n_0\
    );
\txAXIS_tdata[50]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf_reg_n_0_[14][2]\,
      I1 => \retbuf_reg_n_0_[6][2]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[30][2]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[22][2]\,
      O => \txAXIS_tdata[50]_i_2_n_0\
    );
\txAXIS_tdata[50]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0415FFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata[55]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[38][2]\,
      I3 => \retbuf_reg_n_0_[0][2]\,
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[50]_i_3_n_0\
    );
\txAXIS_tdata[50]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(50),
      I1 => \txAXIS_tdata[63]_i_8_0\(50),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(50),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(50),
      O => \txAXIS_tdata[50]_i_5_n_0\
    );
\txAXIS_tdata[50]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(50),
      I1 => \txAXIS_tdata[63]_i_8_4\(50),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(50),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[50]_i_6_n_0\
    );
\txAXIS_tdata[51]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf_reg_n_0_[14][3]\,
      I1 => \retbuf_reg_n_0_[6][3]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[30][3]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[22][3]\,
      O => \txAXIS_tdata[51]_i_2_n_0\
    );
\txAXIS_tdata[51]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0415FFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata[55]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[38][3]\,
      I3 => \retbuf_reg_n_0_[0][3]\,
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[51]_i_3_n_0\
    );
\txAXIS_tdata[51]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(51),
      I1 => \txAXIS_tdata[63]_i_8_0\(51),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(51),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(51),
      O => \txAXIS_tdata[51]_i_5_n_0\
    );
\txAXIS_tdata[51]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(51),
      I1 => \txAXIS_tdata[63]_i_8_4\(51),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(51),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[51]_i_6_n_0\
    );
\txAXIS_tdata[52]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf_reg_n_0_[14][4]\,
      I1 => \retbuf_reg_n_0_[6][4]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[30][4]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[22][4]\,
      O => \txAXIS_tdata[52]_i_2_n_0\
    );
\txAXIS_tdata[52]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0415FFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata[55]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[38][4]\,
      I3 => \retbuf_reg_n_0_[0][4]\,
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[52]_i_3_n_0\
    );
\txAXIS_tdata[52]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(52),
      I1 => \txAXIS_tdata[63]_i_8_0\(52),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(52),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(52),
      O => \txAXIS_tdata[52]_i_5_n_0\
    );
\txAXIS_tdata[52]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(52),
      I1 => \txAXIS_tdata[63]_i_8_4\(52),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(52),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[52]_i_6_n_0\
    );
\txAXIS_tdata[53]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf_reg_n_0_[14][5]\,
      I1 => \retbuf_reg_n_0_[6][5]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[30][5]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[22][5]\,
      O => \txAXIS_tdata[53]_i_2_n_0\
    );
\txAXIS_tdata[53]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0415FFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata[55]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[38][5]\,
      I3 => \retbuf_reg_n_0_[0][5]\,
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[53]_i_3_n_0\
    );
\txAXIS_tdata[53]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(53),
      I1 => \txAXIS_tdata[63]_i_8_0\(53),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(53),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(53),
      O => \txAXIS_tdata[53]_i_5_n_0\
    );
\txAXIS_tdata[53]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(53),
      I1 => \txAXIS_tdata[63]_i_8_4\(53),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(53),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[53]_i_6_n_0\
    );
\txAXIS_tdata[54]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf_reg_n_0_[14][6]\,
      I1 => \retbuf_reg_n_0_[6][6]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[30][6]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[22][6]\,
      O => \txAXIS_tdata[54]_i_2_n_0\
    );
\txAXIS_tdata[54]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0415FFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata[55]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[38][6]\,
      I3 => \retbuf_reg_n_0_[0][6]\,
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[54]_i_3_n_0\
    );
\txAXIS_tdata[54]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(54),
      I1 => \txAXIS_tdata[63]_i_8_0\(54),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(54),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(54),
      O => \txAXIS_tdata[54]_i_5_n_0\
    );
\txAXIS_tdata[54]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(54),
      I1 => \txAXIS_tdata[63]_i_8_4\(54),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(54),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[54]_i_6_n_0\
    );
\txAXIS_tdata[55]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(55),
      I1 => \txAXIS_tdata[63]_i_8_0\(55),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(55),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(55),
      O => \txAXIS_tdata[55]_i_10_n_0\
    );
\txAXIS_tdata[55]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(55),
      I1 => \txAXIS_tdata[63]_i_8_4\(55),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(55),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[55]_i_11_n_0\
    );
\txAXIS_tdata[55]_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(2),
      I1 => \^stateop_reg[5]_0\(1),
      I2 => resid(2),
      I3 => resid(1),
      O => \txAXIS_tdata[55]_i_13_n_0\
    );
\txAXIS_tdata[55]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \^stateop_reg[5]_0\(2),
      I2 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[55]_i_3_n_0\
    );
\txAXIS_tdata[55]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(3),
      O => \txAXIS_tdata[55]_i_4_n_0\
    );
\txAXIS_tdata[55]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => resid(1),
      I1 => resid(2),
      O => \txAXIS_tdata[55]_i_5_n_0\
    );
\txAXIS_tdata[55]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F5C50535"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(8),
      I1 => \invbuf[9][7]_i_6_n_0\,
      I2 => \wordcnt_reg_n_0_[25]\,
      I3 => \opbuf_reg[0]5\(7),
      I4 => \opbuf_reg[0]5\(8),
      O => \txAXIS_tdata[55]_i_6_n_0\
    );
\txAXIS_tdata[55]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf_reg_n_0_[14][7]\,
      I1 => \retbuf_reg_n_0_[6][7]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[30][7]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[22][7]\,
      O => \txAXIS_tdata[55]_i_7_n_0\
    );
\txAXIS_tdata[55]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0415FFFFFFFF"
    )
        port map (
      I0 => \txAXIS_tdata[55]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_9_n_0\,
      I2 => \retbuf_reg_n_0_[38][7]\,
      I3 => \retbuf_reg_n_0_[0][7]\,
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[55]_i_8_n_0\
    );
\txAXIS_tdata[56]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[39][0]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][0]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[56]_i_5_n_0\,
      O => \txAXIS_tdata[56]_i_3_n_0\
    );
\txAXIS_tdata[56]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[56]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[56]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[56]_i_4_n_0\
    );
\txAXIS_tdata[56]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[15][0]\,
      I1 => \retbuf_reg_n_0_[7][0]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[31][0]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[23][0]\,
      O => \txAXIS_tdata[56]_i_5_n_0\
    );
\txAXIS_tdata[56]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(56),
      I1 => \txAXIS_tdata[63]_i_8_0\(56),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(56),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(56),
      O => \txAXIS_tdata[56]_i_6_n_0\
    );
\txAXIS_tdata[56]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(56),
      I1 => \txAXIS_tdata[63]_i_8_4\(56),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(56),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[56]_i_7_n_0\
    );
\txAXIS_tdata[57]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[39][1]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][1]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[57]_i_5_n_0\,
      O => \txAXIS_tdata[57]_i_3_n_0\
    );
\txAXIS_tdata[57]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[57]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[57]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[57]_i_4_n_0\
    );
\txAXIS_tdata[57]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[15][1]\,
      I1 => \retbuf_reg_n_0_[7][1]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[31][1]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[23][1]\,
      O => \txAXIS_tdata[57]_i_5_n_0\
    );
\txAXIS_tdata[57]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(57),
      I1 => \txAXIS_tdata[63]_i_8_0\(57),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(57),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(57),
      O => \txAXIS_tdata[57]_i_6_n_0\
    );
\txAXIS_tdata[57]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(57),
      I1 => \txAXIS_tdata[63]_i_8_4\(57),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(57),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[57]_i_7_n_0\
    );
\txAXIS_tdata[58]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888BBB8B"
    )
        port map (
      I0 => \txAXIS_tdata[58]_i_4_n_0\,
      I1 => \txAXIS_tdata[55]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[0][2]\,
      I3 => \txAXIS_tdata[63]_i_9_n_0\,
      I4 => \retbuf_reg_n_0_[39][2]\,
      O => \txAXIS_tdata[58]_i_2_n_0\
    );
\txAXIS_tdata[58]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[15][2]\,
      I1 => \retbuf_reg_n_0_[7][2]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[31][2]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[23][2]\,
      O => \txAXIS_tdata[58]_i_4_n_0\
    );
\txAXIS_tdata[58]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(58),
      I1 => \txAXIS_tdata[63]_i_8_0\(58),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(58),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(58),
      O => \txAXIS_tdata[58]_i_5_n_0\
    );
\txAXIS_tdata[58]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(58),
      I1 => \txAXIS_tdata[63]_i_8_4\(58),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(58),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[58]_i_6_n_0\
    );
\txAXIS_tdata[59]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888BBB8B"
    )
        port map (
      I0 => \txAXIS_tdata[59]_i_4_n_0\,
      I1 => \txAXIS_tdata[55]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[0][3]\,
      I3 => \txAXIS_tdata[63]_i_9_n_0\,
      I4 => \retbuf_reg_n_0_[39][3]\,
      O => \txAXIS_tdata[59]_i_2_n_0\
    );
\txAXIS_tdata[59]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[15][3]\,
      I1 => \retbuf_reg_n_0_[7][3]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[31][3]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[23][3]\,
      O => \txAXIS_tdata[59]_i_4_n_0\
    );
\txAXIS_tdata[59]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(59),
      I1 => \txAXIS_tdata[63]_i_8_0\(59),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(59),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(59),
      O => \txAXIS_tdata[59]_i_5_n_0\
    );
\txAXIS_tdata[59]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(59),
      I1 => \txAXIS_tdata[63]_i_8_4\(59),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(59),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[59]_i_6_n_0\
    );
\txAXIS_tdata[5]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \retbuf_reg_n_0_[24][5]\,
      I1 => \invbuf[9][7]_i_6_n_0\,
      I2 => \retbuf_reg[16]_65\(5),
      O => \txAXIS_tdata[5]_i_10_n_0\
    );
\txAXIS_tdata[5]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \retbuf_reg_n_0_[0][5]\,
      I1 => \retbuf_reg_n_0_[8][5]\,
      I2 => \invbuf[9][7]_i_6_n_0\,
      O => \txAXIS_tdata[5]_i_11_n_0\
    );
\txAXIS_tdata[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(0),
      I1 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[5]_i_3_n_0\
    );
\txAXIS_tdata[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002000"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(2),
      I3 => \^stateop_reg[5]_0\(1),
      I4 => \^stateop_reg[5]_0\(0),
      I5 => \pollbuf[0][7]_i_7_n_0\,
      O => \txAXIS_tdata[5]_i_5_n_0\
    );
\txAXIS_tdata[5]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0A3AFA3A"
    )
        port map (
      I0 => \retbuf_reg_n_0_[32][5]\,
      I1 => \txAXIS_tdata[5]_i_10_n_0\,
      I2 => \txAXIS_tdata[55]_i_6_n_0\,
      I3 => \txAXIS_tdata[63]_i_9_n_0\,
      I4 => \txAXIS_tdata[5]_i_11_n_0\,
      O => \txAXIS_tdata[5]_i_6_n_0\
    );
\txAXIS_tdata[5]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => doutb(5),
      I1 => \txAXIS_tdata[63]_i_8_0\(5),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(5),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(5),
      O => \txAXIS_tdata[5]_i_8_n_0\
    );
\txAXIS_tdata[5]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"470047FF47FF47FF"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(5),
      I1 => \txAXIS_tdata[47]_i_10_n_0\,
      I2 => \txAXIS_tdata[63]_i_8_4\(5),
      I3 => \txAXIS_tdata[63]_i_15_n_0\,
      I4 => \txAXIS_tdata[63]_i_8_5\(5),
      I5 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[5]_i_9_n_0\
    );
\txAXIS_tdata[60]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[39][4]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][4]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[60]_i_5_n_0\,
      O => \txAXIS_tdata[60]_i_3_n_0\
    );
\txAXIS_tdata[60]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[60]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[60]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[60]_i_4_n_0\
    );
\txAXIS_tdata[60]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[15][4]\,
      I1 => \retbuf_reg_n_0_[7][4]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[31][4]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[23][4]\,
      O => \txAXIS_tdata[60]_i_5_n_0\
    );
\txAXIS_tdata[60]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(60),
      I1 => \txAXIS_tdata[63]_i_8_0\(60),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(60),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(60),
      O => \txAXIS_tdata[60]_i_6_n_0\
    );
\txAXIS_tdata[60]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(60),
      I1 => \txAXIS_tdata[63]_i_8_4\(60),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(60),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[60]_i_7_n_0\
    );
\txAXIS_tdata[61]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[39][5]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][5]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[61]_i_5_n_0\,
      O => \txAXIS_tdata[61]_i_3_n_0\
    );
\txAXIS_tdata[61]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \txAXIS_tdata[61]_i_6_n_0\,
      I1 => \txAXIS_tdata[63]_i_13_n_0\,
      I2 => \txAXIS_tdata[61]_i_7_n_0\,
      I3 => \txAXIS_tdata[63]_i_12_n_0\,
      O => \txAXIS_tdata[61]_i_4_n_0\
    );
\txAXIS_tdata[61]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[15][5]\,
      I1 => \retbuf_reg_n_0_[7][5]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[31][5]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[23][5]\,
      O => \txAXIS_tdata[61]_i_5_n_0\
    );
\txAXIS_tdata[61]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(61),
      I1 => \txAXIS_tdata[63]_i_8_0\(61),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(61),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(61),
      O => \txAXIS_tdata[61]_i_6_n_0\
    );
\txAXIS_tdata[61]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(61),
      I1 => \txAXIS_tdata[63]_i_8_4\(61),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(61),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[61]_i_7_n_0\
    );
\txAXIS_tdata[62]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888BBB8B"
    )
        port map (
      I0 => \txAXIS_tdata[62]_i_4_n_0\,
      I1 => \txAXIS_tdata[55]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[0][6]\,
      I3 => \txAXIS_tdata[63]_i_9_n_0\,
      I4 => \retbuf_reg_n_0_[39][6]\,
      O => \txAXIS_tdata[62]_i_2_n_0\
    );
\txAXIS_tdata[62]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[15][6]\,
      I1 => \retbuf_reg_n_0_[7][6]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[31][6]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[23][6]\,
      O => \txAXIS_tdata[62]_i_4_n_0\
    );
\txAXIS_tdata[62]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(62),
      I1 => \txAXIS_tdata[63]_i_8_0\(62),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(62),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(62),
      O => \txAXIS_tdata[62]_i_5_n_0\
    );
\txAXIS_tdata[62]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(62),
      I1 => \txAXIS_tdata[63]_i_8_4\(62),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(62),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[62]_i_6_n_0\
    );
\txAXIS_tdata[63]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[15][7]\,
      I1 => \retbuf_reg_n_0_[7][7]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[31][7]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[23][7]\,
      O => \txAXIS_tdata[63]_i_10_n_0\
    );
\txAXIS_tdata[63]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(63),
      I1 => \txAXIS_tdata[63]_i_8_0\(63),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(63),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(63),
      O => \txAXIS_tdata[63]_i_11_n_0\
    );
\txAXIS_tdata[63]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFFFFFF"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[7]\,
      I1 => \tixVBuffer_reg_n_0_[6]\,
      I2 => \tixVBuffer_reg_n_0_[5]\,
      I3 => p_0_in0,
      I4 => \^stateop_reg[5]_0\(2),
      I5 => \^stateop_reg[5]_0\(1),
      O => \txAXIS_tdata[63]_i_12_n_0\
    );
\txAXIS_tdata[63]_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEE3"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[0]\,
      I1 => \tixVBuffer_reg_n_0_[1]\,
      I2 => \tixVBuffer_reg_n_0_[2]\,
      I3 => \tixVBuffer_reg_n_0_[3]\,
      O => \txAXIS_tdata[63]_i_13_n_0\
    );
\txAXIS_tdata[63]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(63),
      I1 => \txAXIS_tdata[63]_i_8_4\(63),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(63),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[63]_i_14_n_0\
    );
\txAXIS_tdata[63]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[1]\,
      I1 => \tixVBuffer_reg_n_0_[0]\,
      I2 => \tixVBuffer_reg_n_0_[2]\,
      I3 => \tixVBuffer_reg_n_0_[3]\,
      O => \txAXIS_tdata[63]_i_15_n_0\
    );
\txAXIS_tdata[63]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C6"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[1]\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => \tixVBuffer_reg_n_0_[0]\,
      I3 => \tixVBuffer_reg_n_0_[3]\,
      O => \txAXIS_tdata[63]_i_16_n_0\
    );
\txAXIS_tdata[63]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \txAXIS_tdata[15]_i_5_n_0\,
      I2 => \^stateop_reg[5]_0\(1),
      I3 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[63]_i_3_n_0\
    );
\txAXIS_tdata[63]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000444444444"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(2),
      I1 => \^stateop_reg[5]_0\(4),
      I2 => resid(0),
      I3 => resid(1),
      I4 => resid(2),
      I5 => \^stateop_reg[5]_0\(1),
      O => \txAXIS_tdata[63]_i_4_n_0\
    );
\txAXIS_tdata[63]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000003300000133"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(5),
      I2 => \^stateop_reg[5]_0\(4),
      I3 => \^stateop_reg[5]_0\(3),
      I4 => \^stateop_reg[5]_0\(0),
      I5 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[63]_i_5_n_0\
    );
\txAXIS_tdata[63]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008A80AAAA8A80"
    )
        port map (
      I0 => \txAXIS_tdata[15]_i_8_n_0\,
      I1 => \retbuf_reg_n_0_[39][7]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[0][7]\,
      I4 => \txAXIS_tdata[55]_i_6_n_0\,
      I5 => \txAXIS_tdata[63]_i_10_n_0\,
      O => \txAXIS_tdata[63]_i_7_n_0\
    );
\txAXIS_tdata[63]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CDFD"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_11_n_0\,
      I1 => \txAXIS_tdata[63]_i_12_n_0\,
      I2 => \txAXIS_tdata[63]_i_13_n_0\,
      I3 => \txAXIS_tdata[63]_i_14_n_0\,
      O => \txAXIS_tdata[63]_i_8_n_0\
    );
\txAXIS_tdata[63]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C355"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(7),
      I1 => \invbuf[9][7]_i_6_n_0\,
      I2 => \opbuf_reg[0]5\(7),
      I3 => \wordcnt_reg_n_0_[25]\,
      O => \txAXIS_tdata[63]_i_9_n_0\
    );
\txAXIS_tdata[6]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(0),
      I1 => \^stateop_reg[5]_0\(4),
      O => \txAXIS_tdata[6]_i_10_n_0\
    );
\txAXIS_tdata[6]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(6),
      I1 => \txAXIS_tdata[63]_i_8_0\(6),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(6),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(6),
      O => \txAXIS_tdata[6]_i_11_n_0\
    );
\txAXIS_tdata[6]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(6),
      I1 => \txAXIS_tdata[63]_i_8_4\(6),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(6),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[6]_i_12_n_0\
    );
\txAXIS_tdata[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20AAA8AA"
    )
        port map (
      I0 => \txAXIS_tdata[6]_i_7__0_n_0\,
      I1 => \txAXIS_tdata[55]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[32][6]\,
      I3 => \^stateop_reg[5]_0\(4),
      I4 => \txAXIS_tdata[6]_i_8_n_0\,
      O => \txAXIS_tdata[6]_i_2_n_0\
    );
\txAXIS_tdata[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFAFBFFFFFFFBAA"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => \^stateop_reg[5]_0\(4),
      I2 => \^stateop_reg[5]_0\(3),
      I3 => \^stateop_reg[5]_0\(1),
      I4 => \^stateop_reg[5]_0\(0),
      I5 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[6]_i_3_n_0\
    );
\txAXIS_tdata[6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0300020000000200"
    )
        port map (
      I0 => \txAXIS_tdata[6]_i_11_n_0\,
      I1 => \pollbuf[0][7]_i_7_n_0\,
      I2 => \^stateop_reg[5]_0\(0),
      I3 => \^stateop_reg[5]_0\(2),
      I4 => \txAXIS_tdata[63]_i_13_n_0\,
      I5 => \txAXIS_tdata[6]_i_12_n_0\,
      O => \txAXIS_tdata[6]_i_5_n_0\
    );
\txAXIS_tdata[6]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000001FFFFFFFF"
    )
        port map (
      I0 => \stateOp_next[5]_i_4_n_0\,
      I1 => \stateOp_next[4]_i_2_n_0\,
      I2 => \stateOp_next[1]_i_2_n_0\,
      I3 => \stateOp_next[5]_i_6_n_0\,
      I4 => \txAXIS_tdata[29]_i_3_n_0\,
      I5 => \^stateop_reg[5]_0\(0),
      O => \txAXIS_tdata[6]_i_6__0_n_0\
    );
\txAXIS_tdata[6]_i_7__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(0),
      O => \txAXIS_tdata[6]_i_7__0_n_0\
    );
\txAXIS_tdata[6]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[8][6]\,
      I1 => \retbuf_reg_n_0_[0][6]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[24][6]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg[16]_65\(6),
      O => \txAXIS_tdata[6]_i_8_n_0\
    );
\txAXIS_tdata[6]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(2),
      I1 => \^stateop_reg[5]_0\(1),
      I2 => resid(2),
      I3 => resid(1),
      O => \txAXIS_tdata[6]_i_9_n_0\
    );
\txAXIS_tdata[7]_i_10__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF1"
    )
        port map (
      I0 => \txAXIS_tdata[55]_i_6_n_0\,
      I1 => \retbuf_reg_n_0_[32][7]\,
      I2 => \^stateop_reg[5]_0\(3),
      I3 => \^stateop_reg[5]_0\(1),
      O => \txAXIS_tdata[7]_i_10__0_n_0\
    );
\txAXIS_tdata[7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2227772700000000"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_9_n_0\,
      I1 => \txAXIS_tdata[7]_i_16_n_0\,
      I2 => \retbuf_reg[16]_65\(7),
      I3 => \invbuf[9][7]_i_6_n_0\,
      I4 => \retbuf_reg_n_0_[24][7]\,
      I5 => \txAXIS_tdata[55]_i_6_n_0\,
      O => \txAXIS_tdata[7]_i_11_n_0\
    );
\txAXIS_tdata[7]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(7),
      I1 => \txAXIS_tdata[63]_i_8_0\(7),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(7),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(7),
      O => \txAXIS_tdata[7]_i_13_n_0\
    );
\txAXIS_tdata[7]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8FFB800B800B800"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(7),
      I1 => \txAXIS_tdata[47]_i_10_n_0\,
      I2 => \txAXIS_tdata[63]_i_8_4\(7),
      I3 => \txAXIS_tdata[63]_i_15_n_0\,
      I4 => \txAXIS_tdata[63]_i_8_5\(7),
      I5 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[7]_i_14_n_0\
    );
\txAXIS_tdata[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[7]_i_15_n_0\
    );
\txAXIS_tdata[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \retbuf_reg_n_0_[8][7]\,
      I1 => \invbuf[9][7]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[0][7]\,
      O => \txAXIS_tdata[7]_i_16_n_0\
    );
\txAXIS_tdata[7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \txAXIS_tdata[63]_i_3_n_0\,
      O => \txAXIS_tdata[7]_i_3_n_0\
    );
\txAXIS_tdata[7]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[7]_i_4_n_0\
    );
\txAXIS_tdata[7]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C808"
    )
        port map (
      I0 => \txAXIS_tdata[7]_i_13_n_0\,
      I1 => \txAXIS_tdata[5]_i_5_n_0\,
      I2 => \txAXIS_tdata[63]_i_13_n_0\,
      I3 => \txAXIS_tdata[7]_i_14_n_0\,
      O => \txAXIS_tdata[7]_i_7_n_0\
    );
\txAXIS_tdata[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF7"
    )
        port map (
      I0 => \txAXIS_tdata[7]_i_15_n_0\,
      I1 => \stateOp_next[5]_i_3_n_0\,
      I2 => \stateOp_next[5]_i_6_n_0\,
      I3 => \stateOp_next[1]_i_2_n_0\,
      I4 => \stateOp_next[4]_i_2_n_0\,
      I5 => \stateOp_next[5]_i_4_n_0\,
      O => \txAXIS_tdata[7]_i_8_n_0\
    );
\txAXIS_tdata[7]_i_9__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFFFFDFFFFFFFF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(4),
      I3 => \^stateop_reg[5]_0\(0),
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(2),
      O => \txAXIS_tdata[7]_i_9__0_n_0\
    );
\txAXIS_tdata[8]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888BBB8B"
    )
        port map (
      I0 => \txAXIS_tdata[8]_i_7_n_0\,
      I1 => \txAXIS_tdata[55]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[0][0]\,
      I3 => \txAXIS_tdata[63]_i_9_n_0\,
      I4 => \retbuf_reg_n_0_[33][0]\,
      O => \txAXIS_tdata[8]_i_3_n_0\
    );
\txAXIS_tdata[8]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(8),
      I1 => \txAXIS_tdata[63]_i_8_4\(8),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(8),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[8]_i_4_n_0\
    );
\txAXIS_tdata[8]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(8),
      I1 => \txAXIS_tdata[63]_i_8_0\(8),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(8),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(8),
      O => \txAXIS_tdata[8]_i_5_n_0\
    );
\txAXIS_tdata[8]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[9][0]\,
      I1 => \retbuf_reg_n_0_[1][0]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[25][0]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[17][0]\,
      O => \txAXIS_tdata[8]_i_7_n_0\
    );
\txAXIS_tdata[9]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888BBB8B"
    )
        port map (
      I0 => \txAXIS_tdata[9]_i_7_n_0\,
      I1 => \txAXIS_tdata[55]_i_6_n_0\,
      I2 => \retbuf_reg_n_0_[0][1]\,
      I3 => \txAXIS_tdata[63]_i_9_n_0\,
      I4 => \retbuf_reg_n_0_[33][1]\,
      O => \txAXIS_tdata[9]_i_3_n_0\
    );
\txAXIS_tdata[9]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFA0C0C0"
    )
        port map (
      I0 => \txAXIS_tdata[63]_i_8_3\(9),
      I1 => \txAXIS_tdata[63]_i_8_4\(9),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_5\(9),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      O => \txAXIS_tdata[9]_i_4_n_0\
    );
\txAXIS_tdata[9]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => doutb(9),
      I1 => \txAXIS_tdata[63]_i_8_0\(9),
      I2 => \txAXIS_tdata[63]_i_15_n_0\,
      I3 => \txAXIS_tdata[63]_i_8_1\(9),
      I4 => \txAXIS_tdata[63]_i_16_n_0\,
      I5 => \txAXIS_tdata[63]_i_8_2\(9),
      O => \txAXIS_tdata[9]_i_5_n_0\
    );
\txAXIS_tdata[9]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[9][1]\,
      I1 => \retbuf_reg_n_0_[1][1]\,
      I2 => \txAXIS_tdata[63]_i_9_n_0\,
      I3 => \retbuf_reg_n_0_[25][1]\,
      I4 => \invbuf[9][7]_i_6_n_0\,
      I5 => \retbuf_reg_n_0_[17][1]\,
      O => \txAXIS_tdata[9]_i_7_n_0\
    );
\txAXIS_tdata_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_286,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_323,
      Q => \txAXIS_tdata_reg_n_0_[0]\
    );
\txAXIS_tdata_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_53,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_280,
      Q => \txAXIS_tdata_reg_n_0_[10]\
    );
\txAXIS_tdata_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_53,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_279,
      Q => \txAXIS_tdata_reg_n_0_[11]\
    );
\txAXIS_tdata_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_53,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_278,
      Q => \txAXIS_tdata_reg_n_0_[12]\
    );
\txAXIS_tdata_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_53,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_277,
      Q => \txAXIS_tdata_reg_n_0_[13]\
    );
\txAXIS_tdata_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_53,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_276,
      Q => \txAXIS_tdata_reg_n_0_[14]\
    );
\txAXIS_tdata_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_53,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_275,
      Q => \txAXIS_tdata_reg_n_0_[15]\
    );
\txAXIS_tdata_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_52,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_317,
      Q => \txAXIS_tdata_reg_n_0_[16]\
    );
\txAXIS_tdata_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_52,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_316,
      Q => \txAXIS_tdata_reg_n_0_[17]\
    );
\txAXIS_tdata_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_52,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_315,
      Q => \txAXIS_tdata_reg_n_0_[18]\
    );
\txAXIS_tdata_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_52,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_314,
      Q => \txAXIS_tdata_reg_n_0_[19]\
    );
\txAXIS_tdata_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_286,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_284,
      Q => \txAXIS_tdata_reg_n_0_[1]\
    );
\txAXIS_tdata_reg[1]_i_6\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txAXIS_tdata[1]_i_7_n_0\,
      I1 => \txAXIS_tdata[1]_i_8_n_0\,
      O => \txAXIS_tdata_reg[1]_i_6_n_0\,
      S => \txAXIS_tdata[63]_i_13_n_0\
    );
\txAXIS_tdata_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_52,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_313,
      Q => \txAXIS_tdata_reg_n_0_[20]\
    );
\txAXIS_tdata_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_52,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_312,
      Q => \txAXIS_tdata_reg_n_0_[21]\
    );
\txAXIS_tdata_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_52,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_311,
      Q => \txAXIS_tdata_reg_n_0_[22]\
    );
\txAXIS_tdata_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_52,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_310,
      Q => \txAXIS_tdata_reg_n_0_[23]\
    );
\txAXIS_tdata_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_51,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_309,
      Q => \txAXIS_tdata_reg_n_0_[24]\
    );
\txAXIS_tdata_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_51,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_308,
      Q => \txAXIS_tdata_reg_n_0_[25]\
    );
\txAXIS_tdata_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_51,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_307,
      Q => \txAXIS_tdata_reg_n_0_[26]\
    );
\txAXIS_tdata_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_51,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_306,
      Q => \txAXIS_tdata_reg_n_0_[27]\
    );
\txAXIS_tdata_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_51,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_305,
      Q => \txAXIS_tdata_reg_n_0_[28]\
    );
\txAXIS_tdata_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_51,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_304,
      Q => \txAXIS_tdata_reg_n_0_[29]\
    );
\txAXIS_tdata_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_286,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_322,
      Q => \txAXIS_tdata_reg_n_0_[2]\
    );
\txAXIS_tdata_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_51,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_303,
      Q => \txAXIS_tdata_reg_n_0_[30]\
    );
\txAXIS_tdata_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_51,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_302,
      Q => \txAXIS_tdata_reg_n_0_[31]\
    );
\txAXIS_tdata_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_50,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_301,
      Q => \txAXIS_tdata_reg_n_0_[32]\
    );
\txAXIS_tdata_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_50,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_300,
      Q => \txAXIS_tdata_reg_n_0_[33]\
    );
\txAXIS_tdata_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_50,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_299,
      Q => \txAXIS_tdata_reg_n_0_[34]\
    );
\txAXIS_tdata_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_50,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_298,
      Q => \txAXIS_tdata_reg_n_0_[35]\
    );
\txAXIS_tdata_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_50,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_297,
      Q => \txAXIS_tdata_reg_n_0_[36]\
    );
\txAXIS_tdata_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_50,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_296,
      Q => \txAXIS_tdata_reg_n_0_[37]\
    );
\txAXIS_tdata_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_50,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_295,
      Q => \txAXIS_tdata_reg_n_0_[38]\
    );
\txAXIS_tdata_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_50,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_294,
      Q => \txAXIS_tdata_reg_n_0_[39]\
    );
\txAXIS_tdata_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_286,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_283,
      Q => \txAXIS_tdata_reg_n_0_[3]\
    );
\txAXIS_tdata_reg[3]_i_6\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txAXIS_tdata[3]_i_8_n_0\,
      I1 => \txAXIS_tdata[3]_i_9_n_0\,
      O => \txAXIS_tdata_reg[3]_i_6_n_0\,
      S => \txAXIS_tdata[63]_i_13_n_0\
    );
\txAXIS_tdata_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_49,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_274,
      Q => \txAXIS_tdata_reg_n_0_[40]\
    );
\txAXIS_tdata_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_49,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_273,
      Q => \txAXIS_tdata_reg_n_0_[41]\
    );
\txAXIS_tdata_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_49,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_272,
      Q => \txAXIS_tdata_reg_n_0_[42]\
    );
\txAXIS_tdata_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_49,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_271,
      Q => \txAXIS_tdata_reg_n_0_[43]\
    );
\txAXIS_tdata_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_49,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_270,
      Q => \txAXIS_tdata_reg_n_0_[44]\
    );
\txAXIS_tdata_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_49,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_269,
      Q => \txAXIS_tdata_reg_n_0_[45]\
    );
\txAXIS_tdata_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_49,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_268,
      Q => \txAXIS_tdata_reg_n_0_[46]\
    );
\txAXIS_tdata_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_49,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_267,
      Q => \txAXIS_tdata_reg_n_0_[47]\
    );
\txAXIS_tdata_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_48,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_293,
      Q => \txAXIS_tdata_reg_n_0_[48]\
    );
\txAXIS_tdata_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_48,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_292,
      Q => \txAXIS_tdata_reg_n_0_[49]\
    );
\txAXIS_tdata_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_286,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_321,
      Q => \txAXIS_tdata_reg_n_0_[4]\
    );
\txAXIS_tdata_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_48,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_291,
      Q => \txAXIS_tdata_reg_n_0_[50]\
    );
\txAXIS_tdata_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_48,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_290,
      Q => \txAXIS_tdata_reg_n_0_[51]\
    );
\txAXIS_tdata_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_48,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_289,
      Q => \txAXIS_tdata_reg_n_0_[52]\
    );
\txAXIS_tdata_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_48,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_288,
      Q => \txAXIS_tdata_reg_n_0_[53]\
    );
\txAXIS_tdata_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_48,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_287,
      Q => \txAXIS_tdata_reg_n_0_[54]\
    );
\txAXIS_tdata_reg[55]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_48,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_286,
      Q => \txAXIS_tdata_reg_n_0_[55]\
    );
\txAXIS_tdata_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_47,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_285,
      Q => \txAXIS_tdata_reg_n_0_[56]\
    );
\txAXIS_tdata_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_47,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_284,
      Q => \txAXIS_tdata_reg_n_0_[57]\
    );
\txAXIS_tdata_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_47,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_283,
      Q => \txAXIS_tdata_reg_n_0_[58]\
    );
\txAXIS_tdata_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_47,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_282,
      Q => \txAXIS_tdata_reg_n_0_[59]\
    );
\txAXIS_tdata_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_286,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_320,
      Q => \txAXIS_tdata_reg_n_0_[5]\
    );
\txAXIS_tdata_reg[5]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txAXIS_tdata[5]_i_8_n_0\,
      I1 => \txAXIS_tdata[5]_i_9_n_0\,
      O => \txAXIS_tdata_reg[5]_i_4_n_0\,
      S => \txAXIS_tdata[63]_i_13_n_0\
    );
\txAXIS_tdata_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_47,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_281,
      Q => \txAXIS_tdata_reg_n_0_[60]\
    );
\txAXIS_tdata_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_47,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_280,
      Q => \txAXIS_tdata_reg_n_0_[61]\
    );
\txAXIS_tdata_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_47,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_279,
      Q => \txAXIS_tdata_reg_n_0_[62]\
    );
\txAXIS_tdata_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_47,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_278,
      Q => \txAXIS_tdata_reg_n_0_[63]\
    );
\txAXIS_tdata_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_286,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_319,
      Q => \txAXIS_tdata_reg_n_0_[6]\
    );
\txAXIS_tdata_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_286,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_318,
      Q => \txAXIS_tdata_reg_n_0_[7]\
    );
\txAXIS_tdata_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_53,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_282,
      Q => \txAXIS_tdata_reg_n_0_[8]\
    );
\txAXIS_tdata_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_53,
      CLR => \stateOp_reg[1]_6\(0),
      D => myCrc_n_281,
      Q => \txAXIS_tdata_reg_n_0_[9]\
    );
\txlen[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"080808FF"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[0]\,
      I1 => \ixRetbufCrc[5]_i_3_n_0\,
      I2 => \ixRetbufCrc[5]_i_4_n_0\,
      I3 => \resid[2]_i_7_n_0\,
      I4 => \resid[2]_i_8_n_0\,
      O => \txlen[0]_i_2_n_0\
    );
\txlen[28]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(3),
      O => \txlen[28]_i_4_n_0\
    );
\txlen_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_534,
      Q => txlen(0)
    );
\txlen_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_224,
      Q => txlen(10)
    );
\txlen_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_223,
      Q => txlen(11)
    );
\txlen_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_222,
      Q => txlen(12)
    );
\txlen_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_221,
      Q => txlen(13)
    );
\txlen_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_220,
      Q => txlen(14)
    );
\txlen_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_219,
      Q => txlen(15)
    );
\txlen_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_218,
      Q => txlen(16)
    );
\txlen_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_217,
      Q => txlen(17)
    );
\txlen_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_216,
      Q => txlen(18)
    );
\txlen_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_215,
      Q => txlen(19)
    );
\txlen_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_233,
      Q => txlen(1)
    );
\txlen_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_214,
      Q => txlen(20)
    );
\txlen_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_213,
      Q => txlen(21)
    );
\txlen_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_212,
      Q => txlen(22)
    );
\txlen_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_211,
      Q => txlen(23)
    );
\txlen_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_210,
      Q => txlen(24)
    );
\txlen_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_209,
      Q => txlen(25)
    );
\txlen_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_208,
      Q => txlen(26)
    );
\txlen_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_207,
      Q => txlen(27)
    );
\txlen_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_206,
      Q => txlen(28)
    );
\txlen_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_232,
      Q => txlen(2)
    );
\txlen_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_231,
      Q => txlen(3)
    );
\txlen_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_230,
      Q => txlen(4)
    );
\txlen_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_229,
      Q => txlen(5)
    );
\txlen_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_228,
      Q => txlen(6)
    );
\txlen_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_227,
      Q => txlen(7)
    );
\txlen_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_226,
      Q => txlen(8)
    );
\txlen_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_225,
      Q => txlen(9)
    );
vsync_last_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^reqinvdecimset\,
      I1 => \^reqinvdecimconfig\,
      I2 => \^reqinvdecimacquire\,
      I3 => \^reqinvdecimunlock\,
      O => \tixVCommand_reg[0]_1\
    );
\wordcntCrcLast[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40FFFFFF"
    )
        port map (
      I0 => \ixRetbufCrc[5]_i_4_n_0\,
      I1 => \ixRetbufCrc[5]_i_3_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      I3 => \resid[2]_i_7_n_0\,
      I4 => \resid[0]_i_2_n_0\,
      O => \wordcntCrcLast[0]_i_2_n_0\
    );
\wordcntCrcLast[16]_i_10\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(12),
      O => \wordcntCrcLast[16]_i_10_n_0\
    );
\wordcntCrcLast[16]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(19),
      O => \wordcntCrcLast[16]_i_3_n_0\
    );
\wordcntCrcLast[16]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(18),
      O => \wordcntCrcLast[16]_i_4_n_0\
    );
\wordcntCrcLast[16]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(17),
      O => \wordcntCrcLast[16]_i_5_n_0\
    );
\wordcntCrcLast[16]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(16),
      O => \wordcntCrcLast[16]_i_6_n_0\
    );
\wordcntCrcLast[16]_i_7\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(15),
      O => \wordcntCrcLast[16]_i_7_n_0\
    );
\wordcntCrcLast[16]_i_8\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(14),
      O => \wordcntCrcLast[16]_i_8_n_0\
    );
\wordcntCrcLast[16]_i_9\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(13),
      O => \wordcntCrcLast[16]_i_9_n_0\
    );
\wordcntCrcLast[24]_i_10\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(24),
      O => \wordcntCrcLast[24]_i_10_n_0\
    );
\wordcntCrcLast[24]_i_11\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(23),
      O => \wordcntCrcLast[24]_i_11_n_0\
    );
\wordcntCrcLast[24]_i_12\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(22),
      O => \wordcntCrcLast[24]_i_12_n_0\
    );
\wordcntCrcLast[24]_i_13\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(21),
      O => \wordcntCrcLast[24]_i_13_n_0\
    );
\wordcntCrcLast[24]_i_14\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(20),
      O => \wordcntCrcLast[24]_i_14_n_0\
    );
\wordcntCrcLast[24]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE7FFFF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \^stateop_reg[5]_0\(0),
      I3 => \^stateop_reg[5]_0\(5),
      I4 => \^stateop_reg[5]_0\(2),
      O => \wordcntCrcLast[24]_i_3_n_0\
    );
\wordcntCrcLast[24]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002000"
    )
        port map (
      I0 => \wordcntCrcLast[24]_i_6_n_0\,
      I1 => \wordcntLast[0]_i_7_n_0\,
      I2 => \resid[2]_i_7_n_0\,
      I3 => \resid[0]_i_2_n_0\,
      I4 => \ixRetbufCrc[4]_i_2_n_0\,
      O => \wordcntCrcLast[24]_i_4_n_0\
    );
\wordcntCrcLast[24]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA8A"
    )
        port map (
      I0 => \resid[2]_i_4_n_0\,
      I1 => \tixVCommand_reg_n_0_[0]\,
      I2 => \ixRetbufCrc[5]_i_3_n_0\,
      I3 => \ixRetbufCrc[5]_i_4_n_0\,
      O => \wordcntCrcLast[24]_i_6_n_0\
    );
\wordcntCrcLast[24]_i_7\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(27),
      O => \wordcntCrcLast[24]_i_7_n_0\
    );
\wordcntCrcLast[24]_i_8\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(26),
      O => \wordcntCrcLast[24]_i_8_n_0\
    );
\wordcntCrcLast[24]_i_9\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(25),
      O => \wordcntCrcLast[24]_i_9_n_0\
    );
\wordcntCrcLast[8]_i_10\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(4),
      O => \wordcntCrcLast[8]_i_10_n_0\
    );
\wordcntCrcLast[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(11),
      O => \wordcntCrcLast[8]_i_3_n_0\
    );
\wordcntCrcLast[8]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(10),
      O => \wordcntCrcLast[8]_i_4_n_0\
    );
\wordcntCrcLast[8]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(9),
      O => \wordcntCrcLast[8]_i_5_n_0\
    );
\wordcntCrcLast[8]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(8),
      O => \wordcntCrcLast[8]_i_6_n_0\
    );
\wordcntCrcLast[8]_i_7\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(7),
      O => \wordcntCrcLast[8]_i_7_n_0\
    );
\wordcntCrcLast[8]_i_8\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(6),
      O => \wordcntCrcLast[8]_i_8_n_0\
    );
\wordcntCrcLast[8]_i_9\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => plusOp(5),
      O => \wordcntCrcLast[8]_i_9_n_0\
    );
\wordcntCrcLast_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_427,
      Q => \wordcntCrcLast_reg_n_0_[0]\
    );
\wordcntCrcLast_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_417,
      Q => \wordcntCrcLast_reg_n_0_[10]\
    );
\wordcntCrcLast_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_416,
      Q => \wordcntCrcLast_reg_n_0_[11]\
    );
\wordcntCrcLast_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_415,
      Q => \wordcntCrcLast_reg_n_0_[12]\
    );
\wordcntCrcLast_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_414,
      Q => \wordcntCrcLast_reg_n_0_[13]\
    );
\wordcntCrcLast_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_413,
      Q => \wordcntCrcLast_reg_n_0_[14]\
    );
\wordcntCrcLast_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_412,
      Q => \wordcntCrcLast_reg_n_0_[15]\
    );
\wordcntCrcLast_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_411,
      Q => \wordcntCrcLast_reg_n_0_[16]\
    );
\wordcntCrcLast_reg[16]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcntCrcLast_reg[8]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcntCrcLast_reg[16]_i_2_n_0\,
      CO(6) => \wordcntCrcLast_reg[16]_i_2_n_1\,
      CO(5) => \wordcntCrcLast_reg[16]_i_2_n_2\,
      CO(4) => \wordcntCrcLast_reg[16]_i_2_n_3\,
      CO(3) => \wordcntCrcLast_reg[16]_i_2_n_4\,
      CO(2) => \wordcntCrcLast_reg[16]_i_2_n_5\,
      CO(1) => \wordcntCrcLast_reg[16]_i_2_n_6\,
      CO(0) => \wordcntCrcLast_reg[16]_i_2_n_7\,
      DI(7 downto 0) => plusOp(19 downto 12),
      O(7) => \wordcntCrcLast_reg[16]_i_2_n_8\,
      O(6) => \wordcntCrcLast_reg[16]_i_2_n_9\,
      O(5) => \wordcntCrcLast_reg[16]_i_2_n_10\,
      O(4) => \wordcntCrcLast_reg[16]_i_2_n_11\,
      O(3) => \wordcntCrcLast_reg[16]_i_2_n_12\,
      O(2) => \wordcntCrcLast_reg[16]_i_2_n_13\,
      O(1) => \wordcntCrcLast_reg[16]_i_2_n_14\,
      O(0) => \wordcntCrcLast_reg[16]_i_2_n_15\,
      S(7) => \wordcntCrcLast[16]_i_3_n_0\,
      S(6) => \wordcntCrcLast[16]_i_4_n_0\,
      S(5) => \wordcntCrcLast[16]_i_5_n_0\,
      S(4) => \wordcntCrcLast[16]_i_6_n_0\,
      S(3) => \wordcntCrcLast[16]_i_7_n_0\,
      S(2) => \wordcntCrcLast[16]_i_8_n_0\,
      S(1) => \wordcntCrcLast[16]_i_9_n_0\,
      S(0) => \wordcntCrcLast[16]_i_10_n_0\
    );
\wordcntCrcLast_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_410,
      Q => \wordcntCrcLast_reg_n_0_[17]\
    );
\wordcntCrcLast_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_409,
      Q => \wordcntCrcLast_reg_n_0_[18]\
    );
\wordcntCrcLast_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_408,
      Q => \wordcntCrcLast_reg_n_0_[19]\
    );
\wordcntCrcLast_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_426,
      Q => \wordcntCrcLast_reg_n_0_[1]\
    );
\wordcntCrcLast_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_407,
      Q => \wordcntCrcLast_reg_n_0_[20]\
    );
\wordcntCrcLast_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_406,
      Q => \wordcntCrcLast_reg_n_0_[21]\
    );
\wordcntCrcLast_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_405,
      Q => \wordcntCrcLast_reg_n_0_[22]\
    );
\wordcntCrcLast_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_404,
      Q => \wordcntCrcLast_reg_n_0_[23]\
    );
\wordcntCrcLast_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_403,
      Q => \wordcntCrcLast_reg_n_0_[24]\
    );
\wordcntCrcLast_reg[24]_i_5\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcntCrcLast_reg[16]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \NLW_wordcntCrcLast_reg[24]_i_5_CO_UNCONNECTED\(7),
      CO(6) => \wordcntCrcLast_reg[24]_i_5_n_1\,
      CO(5) => \wordcntCrcLast_reg[24]_i_5_n_2\,
      CO(4) => \wordcntCrcLast_reg[24]_i_5_n_3\,
      CO(3) => \wordcntCrcLast_reg[24]_i_5_n_4\,
      CO(2) => \wordcntCrcLast_reg[24]_i_5_n_5\,
      CO(1) => \wordcntCrcLast_reg[24]_i_5_n_6\,
      CO(0) => \wordcntCrcLast_reg[24]_i_5_n_7\,
      DI(7) => '0',
      DI(6 downto 0) => plusOp(26 downto 20),
      O(7) => \wordcntCrcLast_reg[24]_i_5_n_8\,
      O(6) => \wordcntCrcLast_reg[24]_i_5_n_9\,
      O(5) => \wordcntCrcLast_reg[24]_i_5_n_10\,
      O(4) => \wordcntCrcLast_reg[24]_i_5_n_11\,
      O(3) => \wordcntCrcLast_reg[24]_i_5_n_12\,
      O(2) => \wordcntCrcLast_reg[24]_i_5_n_13\,
      O(1) => \wordcntCrcLast_reg[24]_i_5_n_14\,
      O(0) => \wordcntCrcLast_reg[24]_i_5_n_15\,
      S(7) => \wordcntCrcLast[24]_i_7_n_0\,
      S(6) => \wordcntCrcLast[24]_i_8_n_0\,
      S(5) => \wordcntCrcLast[24]_i_9_n_0\,
      S(4) => \wordcntCrcLast[24]_i_10_n_0\,
      S(3) => \wordcntCrcLast[24]_i_11_n_0\,
      S(2) => \wordcntCrcLast[24]_i_12_n_0\,
      S(1) => \wordcntCrcLast[24]_i_13_n_0\,
      S(0) => \wordcntCrcLast[24]_i_14_n_0\
    );
\wordcntCrcLast_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_425,
      Q => \wordcntCrcLast_reg_n_0_[2]\
    );
\wordcntCrcLast_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_424,
      Q => \wordcntCrcLast_reg_n_0_[3]\
    );
\wordcntCrcLast_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_423,
      Q => \wordcntCrcLast_reg_n_0_[4]\
    );
\wordcntCrcLast_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_422,
      Q => \wordcntCrcLast_reg_n_0_[5]\
    );
\wordcntCrcLast_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_421,
      Q => \wordcntCrcLast_reg_n_0_[6]\
    );
\wordcntCrcLast_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_420,
      Q => \wordcntCrcLast_reg_n_0_[7]\
    );
\wordcntCrcLast_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_419,
      Q => \wordcntCrcLast_reg_n_0_[8]\
    );
\wordcntCrcLast_reg[8]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => plusOp(3),
      CI_TOP => '0',
      CO(7) => \wordcntCrcLast_reg[8]_i_2_n_0\,
      CO(6) => \wordcntCrcLast_reg[8]_i_2_n_1\,
      CO(5) => \wordcntCrcLast_reg[8]_i_2_n_2\,
      CO(4) => \wordcntCrcLast_reg[8]_i_2_n_3\,
      CO(3) => \wordcntCrcLast_reg[8]_i_2_n_4\,
      CO(2) => \wordcntCrcLast_reg[8]_i_2_n_5\,
      CO(1) => \wordcntCrcLast_reg[8]_i_2_n_6\,
      CO(0) => \wordcntCrcLast_reg[8]_i_2_n_7\,
      DI(7 downto 0) => plusOp(11 downto 4),
      O(7) => \wordcntCrcLast_reg[8]_i_2_n_8\,
      O(6) => \wordcntCrcLast_reg[8]_i_2_n_9\,
      O(5) => \wordcntCrcLast_reg[8]_i_2_n_10\,
      O(4) => \wordcntCrcLast_reg[8]_i_2_n_11\,
      O(3) => \wordcntCrcLast_reg[8]_i_2_n_12\,
      O(2) => \wordcntCrcLast_reg[8]_i_2_n_13\,
      O(1) => \wordcntCrcLast_reg[8]_i_2_n_14\,
      O(0) => \wordcntCrcLast_reg[8]_i_2_n_15\,
      S(7) => \wordcntCrcLast[8]_i_3_n_0\,
      S(6) => \wordcntCrcLast[8]_i_4_n_0\,
      S(5) => \wordcntCrcLast[8]_i_5_n_0\,
      S(4) => \wordcntCrcLast[8]_i_6_n_0\,
      S(3) => \wordcntCrcLast[8]_i_7_n_0\,
      S(2) => \wordcntCrcLast[8]_i_8_n_0\,
      S(1) => \wordcntCrcLast[8]_i_9_n_0\,
      S(0) => \wordcntCrcLast[8]_i_10_n_0\
    );
\wordcntCrcLast_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_35,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_418,
      Q => \wordcntCrcLast_reg_n_0_[9]\
    );
\wordcntLast[0]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000F000E0000000E"
    )
        port map (
      I0 => \resid[0]_i_5_n_0\,
      I1 => \ixRetbufCrc[4]_i_2_n_0\,
      I2 => \wordcntLast[0]_i_12_n_0\,
      I3 => \resid[2]_i_20_n_0\,
      I4 => \retbuf[7][7]_i_4_n_0\,
      I5 => \tixVCommand_reg_n_0_[0]\,
      O => \wordcntLast[0]_i_10_n_0\
    );
\wordcntLast[0]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAABAFFFFAABA"
    )
        port map (
      I0 => \resid[2]_i_16_n_0\,
      I1 => \ixRetbufCrc[5]_i_4_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      I3 => \resid[2]_i_30_n_0\,
      I4 => targetNotSteady_i_3_n_0,
      I5 => ackInvConfig_sig_i_7_n_0,
      O => \wordcntLast[0]_i_11_n_0\
    );
\wordcntLast[0]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => \stateCorecfg[2]_i_8_n_0\,
      I1 => \stateOp[5]_i_76_n_0\,
      I2 => \retbuf[0][0]_i_3_n_0\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \stateCorecfg[2]_i_9_n_0\,
      O => \wordcntLast[0]_i_12_n_0\
    );
\wordcntLast[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0DDD"
    )
        port map (
      I0 => plusOp(3),
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \^stateop_reg[5]_0\(3),
      I3 => \wordcntLast[0]_i_5_n_0\,
      O => \wordcntLast[0]_i_2_n_0\
    );
\wordcntLast[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A2000000A200A00"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(0),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(4),
      I3 => \^stateop_reg[5]_0\(1),
      I4 => \^stateop_reg[5]_0\(2),
      I5 => \wordcntLast[0]_i_5_n_0\,
      O => \wordcntLast[0]_i_3_n_0\
    );
\wordcntLast[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"080000007F77BBBB"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(3),
      I1 => \wordcntLast[0]_i_6_n_0\,
      I2 => \wordcntLast[0]_i_7_n_0\,
      I3 => \wordcntLast[0]_i_8_n_0\,
      I4 => \^stateop_reg[5]_0\(2),
      I5 => \wordcntLast[0]_i_5_n_0\,
      O => \wordcntLast[0]_i_4_n_0\
    );
\wordcntLast[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \ixRetbufCrc[4]_i_4_n_0\,
      I1 => \ixRetbufCrc[4]_i_3_n_0\,
      I2 => \tixVController_reg_n_0_[0]\,
      I3 => \stateOp_i_5__1_n_0\,
      I4 => \ixRetbufCrc[4]_i_5_n_0\,
      I5 => \tixVCommand_reg_n_0_[0]\,
      O => \wordcntLast[0]_i_5_n_0\
    );
\wordcntLast[0]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(4),
      O => \wordcntLast[0]_i_6_n_0\
    );
\wordcntLast[0]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \ixRetbufCrc[5]_i_4_n_0\,
      I1 => \ixRetbufCrc[5]_i_3_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      O => \wordcntLast[0]_i_7_n_0\
    );
\wordcntLast[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F1F0F1F0F1F0FF"
    )
        port map (
      I0 => \wordcntLast[0]_i_9_n_0\,
      I1 => \resid[2]_i_20_n_0\,
      I2 => \wordcntLast[0]_i_10_n_0\,
      I3 => \resid[2]_i_23_n_0\,
      I4 => \wordcntLast[0]_i_11_n_0\,
      I5 => \resid[0]_i_6_n_0\,
      O => \wordcntLast[0]_i_8_n_0\
    );
\wordcntLast[0]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"010101010D010101"
    )
        port map (
      I0 => \resid[2]_i_21_n_0\,
      I1 => \tixVCommand_reg_n_0_[0]\,
      I2 => \ixRetbufCrc[5]_i_4_n_0\,
      I3 => \resid[2]_i_25_n_0\,
      I4 => \tixVController_reg_n_0_[3]\,
      I5 => \ixRetbufCrc[4]_i_4_n_0\,
      O => \wordcntLast[0]_i_9_n_0\
    );
\wordcntLast[28]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[3]\,
      I1 => \tixVBuffer_reg_n_0_[0]\,
      I2 => \tixVBuffer_reg_n_0_[1]\,
      I3 => \tixVBuffer_reg_n_0_[2]\,
      O => \wordcntLast[28]_i_10_n_0\
    );
\wordcntLast[28]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000022200020"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[1]\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => ackCoobufCornerToHostif,
      I3 => \tixVBuffer_reg_n_0_[0]\,
      I4 => ackFlgbufTraceToHostif,
      I5 => \wordcntLast[28]_i_19_n_0\,
      O => \wordcntLast[28]_i_12_n_0\
    );
\wordcntLast[28]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[3]\,
      I1 => \tixVBuffer_reg_n_0_[7]\,
      I2 => \tixVBuffer_reg_n_0_[6]\,
      I3 => \tixVBuffer_reg_n_0_[5]\,
      I4 => p_0_in0,
      O => \wordcntLast[28]_i_19_n_0\
    );
\wordcntLast[28]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCF3FFFCBFFFFFFF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => \^stateop_reg[5]_0\(0),
      I2 => \^stateop_reg[5]_0\(4),
      I3 => \^stateop_reg[5]_0\(3),
      I4 => \^stateop_reg[5]_0\(2),
      I5 => \^stateop_reg[5]_0\(1),
      O => \wordcntLast[28]_i_3_n_0\
    );
\wordcntLast[28]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBD7FFFB"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(0),
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \^stateop_reg[5]_0\(4),
      I3 => \^stateop_reg[5]_0\(3),
      I4 => \^stateop_reg[5]_0\(2),
      O => \wordcntLast[28]_i_4_n_0\
    );
\wordcntLast[28]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00008F88"
    )
        port map (
      I0 => \wordcntLast[28]_i_8_n_0\,
      I1 => \wordcntLast[28]_i_9_n_0\,
      I2 => \wordcntLast[28]_i_10_n_0\,
      I3 => ackSeqbufHshktrackToHostif,
      I4 => \pollbuf[0][7]_i_7_n_0\,
      I5 => \wordcntLast[28]_i_12_n_0\,
      O => \wordcntLast[28]_i_5_n_0\
    );
\wordcntLast[28]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000004000000"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => \^stateop_reg[5]_0\(4),
      I2 => \^stateop_reg[5]_0\(3),
      I3 => \^stateop_reg[5]_0\(2),
      I4 => \^stateop_reg[5]_0\(0),
      I5 => \^stateop_reg[5]_0\(1),
      O => \wordcntLast[28]_i_6_n_0\
    );
\wordcntLast[28]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => ackSeqbufVidtrackToHostif,
      I1 => ackSeqbufCputrackToHostif,
      I2 => \tixVBuffer_reg_n_0_[1]\,
      I3 => ackSeqbufMemtrackToHostif,
      I4 => \tixVBuffer_reg_n_0_[0]\,
      I5 => ackPvwbufDecimToHostif,
      O => \wordcntLast[28]_i_8_n_0\
    );
\wordcntLast[28]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[2]\,
      I1 => \tixVBuffer_reg_n_0_[3]\,
      O => \wordcntLast[28]_i_9_n_0\
    );
\wordcntLast[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \ixRetbufCrc[5]_i_4_n_0\,
      I1 => \ixRetbufCrc[5]_i_3_n_0\,
      I2 => \tixVCommand_reg_n_0_[0]\,
      O => \wordcntLast[2]_i_2_n_0\
    );
\wordcntLast_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_234,
      Q => wordcntLast(0)
    );
\wordcntLast_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_224,
      Q => wordcntLast(10)
    );
\wordcntLast_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_223,
      Q => wordcntLast(11)
    );
\wordcntLast_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_222,
      Q => wordcntLast(12)
    );
\wordcntLast_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_221,
      Q => wordcntLast(13)
    );
\wordcntLast_reg[13]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcntLast_reg[5]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcntLast_reg[13]_i_2_n_0\,
      CO(6) => \wordcntLast_reg[13]_i_2_n_1\,
      CO(5) => \wordcntLast_reg[13]_i_2_n_2\,
      CO(4) => \wordcntLast_reg[13]_i_2_n_3\,
      CO(3) => \wordcntLast_reg[13]_i_2_n_4\,
      CO(2) => \wordcntLast_reg[13]_i_2_n_5\,
      CO(1) => \wordcntLast_reg[13]_i_2_n_6\,
      CO(0) => \wordcntLast_reg[13]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => plusOp(16 downto 9),
      S(7) => \len_reg_n_0_[16]\,
      S(6) => \len_reg_n_0_[15]\,
      S(5) => \len_reg_n_0_[14]\,
      S(4) => \len_reg_n_0_[13]\,
      S(3) => \len_reg_n_0_[12]\,
      S(2) => \len_reg_n_0_[11]\,
      S(1) => \len_reg_n_0_[10]\,
      S(0) => \len_reg_n_0_[9]\
    );
\wordcntLast_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_220,
      Q => wordcntLast(14)
    );
\wordcntLast_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_219,
      Q => wordcntLast(15)
    );
\wordcntLast_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_218,
      Q => wordcntLast(16)
    );
\wordcntLast_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_217,
      Q => wordcntLast(17)
    );
\wordcntLast_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_216,
      Q => wordcntLast(18)
    );
\wordcntLast_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_215,
      Q => wordcntLast(19)
    );
\wordcntLast_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_233,
      Q => wordcntLast(1)
    );
\wordcntLast_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_214,
      Q => wordcntLast(20)
    );
\wordcntLast_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_213,
      Q => wordcntLast(21)
    );
\wordcntLast_reg[21]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcntLast_reg[13]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcntLast_reg[21]_i_2_n_0\,
      CO(6) => \wordcntLast_reg[21]_i_2_n_1\,
      CO(5) => \wordcntLast_reg[21]_i_2_n_2\,
      CO(4) => \wordcntLast_reg[21]_i_2_n_3\,
      CO(3) => \wordcntLast_reg[21]_i_2_n_4\,
      CO(2) => \wordcntLast_reg[21]_i_2_n_5\,
      CO(1) => \wordcntLast_reg[21]_i_2_n_6\,
      CO(0) => \wordcntLast_reg[21]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => plusOp(24 downto 17),
      S(7) => \len_reg_n_0_[24]\,
      S(6) => \len_reg_n_0_[23]\,
      S(5) => \len_reg_n_0_[22]\,
      S(4) => \len_reg_n_0_[21]\,
      S(3) => \len_reg_n_0_[20]\,
      S(2) => \len_reg_n_0_[19]\,
      S(1) => \len_reg_n_0_[18]\,
      S(0) => \len_reg_n_0_[17]\
    );
\wordcntLast_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_212,
      Q => wordcntLast(22)
    );
\wordcntLast_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_211,
      Q => wordcntLast(23)
    );
\wordcntLast_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_210,
      Q => wordcntLast(24)
    );
\wordcntLast_reg[25]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_209,
      Q => wordcntLast(25)
    );
\wordcntLast_reg[26]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_208,
      Q => wordcntLast(26)
    );
\wordcntLast_reg[27]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_207,
      Q => wordcntLast(27)
    );
\wordcntLast_reg[28]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_206,
      Q => wordcntLast(28)
    );
\wordcntLast_reg[28]_i_7\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcntLast_reg[21]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_wordcntLast_reg[28]_i_7_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \wordcntLast_reg[28]_i_7_n_2\,
      CO(4) => \wordcntLast_reg[28]_i_7_n_3\,
      CO(3) => \wordcntLast_reg[28]_i_7_n_4\,
      CO(2) => \wordcntLast_reg[28]_i_7_n_5\,
      CO(1) => \wordcntLast_reg[28]_i_7_n_6\,
      CO(0) => \wordcntLast_reg[28]_i_7_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NLW_wordcntLast_reg[28]_i_7_O_UNCONNECTED\(7),
      O(6 downto 0) => plusOp(31 downto 25),
      S(7) => '0',
      S(6) => \len_reg_n_0_[31]\,
      S(5) => \len_reg_n_0_[30]\,
      S(4) => \len_reg_n_0_[29]\,
      S(3) => \len_reg_n_0_[28]\,
      S(2) => \len_reg_n_0_[27]\,
      S(1) => \len_reg_n_0_[26]\,
      S(0) => \len_reg_n_0_[25]\
    );
\wordcntLast_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_232,
      Q => wordcntLast(2)
    );
\wordcntLast_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_231,
      Q => wordcntLast(3)
    );
\wordcntLast_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_230,
      Q => wordcntLast(4)
    );
\wordcntLast_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_229,
      Q => wordcntLast(5)
    );
\wordcntLast_reg[5]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \len_reg_n_0_[0]\,
      CI_TOP => '0',
      CO(7) => \wordcntLast_reg[5]_i_2_n_0\,
      CO(6) => \wordcntLast_reg[5]_i_2_n_1\,
      CO(5) => \wordcntLast_reg[5]_i_2_n_2\,
      CO(4) => \wordcntLast_reg[5]_i_2_n_3\,
      CO(3) => \wordcntLast_reg[5]_i_2_n_4\,
      CO(2) => \wordcntLast_reg[5]_i_2_n_5\,
      CO(1) => \wordcntLast_reg[5]_i_2_n_6\,
      CO(0) => \wordcntLast_reg[5]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 2) => plusOp(8 downto 3),
      O(1 downto 0) => \NLW_wordcntLast_reg[5]_i_2_O_UNCONNECTED\(1 downto 0),
      S(7) => \len_reg_n_0_[8]\,
      S(6) => \len_reg_n_0_[7]\,
      S(5) => \len_reg_n_0_[6]\,
      S(4) => \len_reg_n_0_[5]\,
      S(3) => \len_reg_n_0_[4]\,
      S(2) => \len_reg_n_0_[3]\,
      S(1) => \len_reg_n_0_[2]\,
      S(0) => \len_reg_n_0_[1]\
    );
\wordcntLast_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_228,
      Q => wordcntLast(6)
    );
\wordcntLast_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_227,
      Q => wordcntLast(7)
    );
\wordcntLast_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_226,
      Q => wordcntLast(8)
    );
\wordcntLast_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_26,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_225,
      Q => wordcntLast(9)
    );
\wordcnt[30]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000404054430000"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(5),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(0),
      I3 => \^stateop_reg[5]_0\(2),
      I4 => \^stateop_reg[5]_0\(1),
      I5 => \^stateop_reg[5]_0\(4),
      O => \wordcnt[30]_i_11_n_0\
    );
\wordcnt[30]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDF9FFFFFBFFFFDF"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(1),
      I1 => \^stateop_reg[5]_0\(4),
      I2 => \^stateop_reg[5]_0\(5),
      I3 => \^stateop_reg[5]_0\(2),
      I4 => \^stateop_reg[5]_0\(0),
      I5 => \^stateop_reg[5]_0\(3),
      O => \wordcnt[30]_i_6_n_0\
    );
\wordcnt[30]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDF3FBFFFFFFFBBB"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(1),
      I2 => \^stateop_reg[5]_0\(5),
      I3 => \^stateop_reg[5]_0\(0),
      I4 => \^stateop_reg[5]_0\(3),
      I5 => \^stateop_reg[5]_0\(2),
      O => \wordcnt[30]_i_7_n_0\
    );
\wordcnt[30]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000014A000000100"
    )
        port map (
      I0 => \^stateop_reg[5]_0\(4),
      I1 => \^stateop_reg[5]_0\(3),
      I2 => \^stateop_reg[5]_0\(0),
      I3 => \^stateop_reg[5]_0\(1),
      I4 => \^stateop_reg[5]_0\(5),
      I5 => \^stateop_reg[5]_0\(2),
      O => \wordcnt[30]_i_9_n_0\
    );
\wordcnt_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_180,
      Q => \opbuf_reg[0]51_in\(6)
    );
\wordcnt_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_170,
      Q => \opbuf_reg[0]51_in\(16)
    );
\wordcnt_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_169,
      Q => \opbuf_reg[0]51_in\(17)
    );
\wordcnt_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_168,
      Q => \opbuf_reg[0]51_in\(18)
    );
\wordcnt_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_167,
      Q => \opbuf_reg[0]51_in\(19)
    );
\wordcnt_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_166,
      Q => \opbuf_reg[0]51_in\(20)
    );
\wordcnt_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_165,
      Q => \opbuf_reg[0]51_in\(21)
    );
\wordcnt_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_164,
      Q => \opbuf_reg[0]51_in\(22)
    );
\wordcnt_reg[16]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[8]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[16]_i_2_n_0\,
      CO(6) => \wordcnt_reg[16]_i_2_n_1\,
      CO(5) => \wordcnt_reg[16]_i_2_n_2\,
      CO(4) => \wordcnt_reg[16]_i_2_n_3\,
      CO(3) => \wordcnt_reg[16]_i_2_n_4\,
      CO(2) => \wordcnt_reg[16]_i_2_n_5\,
      CO(1) => \wordcnt_reg[16]_i_2_n_6\,
      CO(0) => \wordcnt_reg[16]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => txlast1(16 downto 9),
      S(7 downto 0) => \opbuf_reg[0]51_in\(22 downto 15)
    );
\wordcnt_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_163,
      Q => \opbuf_reg[0]51_in\(23)
    );
\wordcnt_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_162,
      Q => \opbuf_reg[0]51_in\(24)
    );
\wordcnt_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_161,
      Q => \opbuf_reg[0]51_in\(25)
    );
\wordcnt_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_179,
      Q => \opbuf_reg[0]51_in\(7)
    );
\wordcnt_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_160,
      Q => \opbuf_reg[0]51_in\(26)
    );
\wordcnt_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_159,
      Q => \opbuf_reg[0]51_in\(27)
    );
\wordcnt_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_158,
      Q => \opbuf_reg[0]51_in\(28)
    );
\wordcnt_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_157,
      Q => \opbuf_reg[0]51_in\(29)
    );
\wordcnt_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_156,
      Q => \opbuf_reg[0]51_in\(30)
    );
\wordcnt_reg[24]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[16]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[24]_i_2_n_0\,
      CO(6) => \wordcnt_reg[24]_i_2_n_1\,
      CO(5) => \wordcnt_reg[24]_i_2_n_2\,
      CO(4) => \wordcnt_reg[24]_i_2_n_3\,
      CO(3) => \wordcnt_reg[24]_i_2_n_4\,
      CO(2) => \wordcnt_reg[24]_i_2_n_5\,
      CO(1) => \wordcnt_reg[24]_i_2_n_6\,
      CO(0) => \wordcnt_reg[24]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => txlast1(24 downto 17),
      S(7 downto 0) => \opbuf_reg[0]51_in\(30 downto 23)
    );
\wordcnt_reg[25]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_155,
      Q => \wordcnt_reg_n_0_[25]\
    );
\wordcnt_reg[26]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_154,
      Q => \wordcnt_reg_n_0_[26]\
    );
\wordcnt_reg[27]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_153,
      Q => \wordcnt_reg_n_0_[27]\
    );
\wordcnt_reg[28]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_152,
      Q => \wordcnt_reg_n_0_[28]\
    );
\wordcnt_reg[29]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_151,
      Q => \wordcnt_reg_n_0_[29]\
    );
\wordcnt_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_178,
      Q => \opbuf_reg[0]51_in\(8)
    );
\wordcnt_reg[30]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_150,
      Q => \wordcnt_reg_n_0_[30]\
    );
\wordcnt_reg[30]_i_10\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[24]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_wordcnt_reg[30]_i_10_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \wordcnt_reg[30]_i_10_n_3\,
      CO(3) => \wordcnt_reg[30]_i_10_n_4\,
      CO(2) => \wordcnt_reg[30]_i_10_n_5\,
      CO(1) => \wordcnt_reg[30]_i_10_n_6\,
      CO(0) => \wordcnt_reg[30]_i_10_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 6) => \NLW_wordcnt_reg[30]_i_10_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => txlast1(30 downto 25),
      S(7 downto 6) => B"00",
      S(5) => \wordcnt_reg_n_0_[30]\,
      S(4) => \wordcnt_reg_n_0_[29]\,
      S(3) => \wordcnt_reg_n_0_[28]\,
      S(2) => \wordcnt_reg_n_0_[27]\,
      S(1) => \wordcnt_reg_n_0_[26]\,
      S(0) => \wordcnt_reg_n_0_[25]\
    );
\wordcnt_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_177,
      Q => \opbuf_reg[0]51_in\(9)
    );
\wordcnt_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_176,
      Q => \opbuf_reg[0]51_in\(10)
    );
\wordcnt_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_175,
      Q => \opbuf_reg[0]51_in\(11)
    );
\wordcnt_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_174,
      Q => \opbuf_reg[0]51_in\(12)
    );
\wordcnt_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_173,
      Q => \opbuf_reg[0]51_in\(13)
    );
\wordcnt_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_172,
      Q => \opbuf_reg[0]51_in\(14)
    );
\wordcnt_reg[8]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \opbuf_reg[0]51_in\(6),
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[8]_i_2_n_0\,
      CO(6) => \wordcnt_reg[8]_i_2_n_1\,
      CO(5) => \wordcnt_reg[8]_i_2_n_2\,
      CO(4) => \wordcnt_reg[8]_i_2_n_3\,
      CO(3) => \wordcnt_reg[8]_i_2_n_4\,
      CO(2) => \wordcnt_reg[8]_i_2_n_5\,
      CO(1) => \wordcnt_reg[8]_i_2_n_6\,
      CO(0) => \wordcnt_reg[8]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => txlast1(8 downto 1),
      S(7 downto 0) => \opbuf_reg[0]51_in\(14 downto 7)
    );
\wordcnt_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_182,
      CLR => \stateOp_reg[1]_6\(0),
      D => myRxtx_n_171,
      Q => \opbuf_reg[0]51_in\(15)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Laser is
  port (
    cs : out STD_LOGIC;
    sclk : out STD_LOGIC;
    ackInvLaserSet : out STD_LOGIC;
    mosi : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    \FSM_sequential_stateXfer_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 17 downto 0 );
    reqInvLaserSet : in STD_LOGIC;
    \txbuf_reg[0][3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Laser : entity is "Laser";
end design_1_Vsp_core_0_0_Laser;

architecture STRUCTURE of design_1_Vsp_core_0_0_Laser is
  signal \FSM_sequential_stateOp[0]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateOp[2]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateOp[2]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateOp[2]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateOp[2]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateOp[2]_i_8_n_0\ : STD_LOGIC;
  signal bytecnt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \bytecnt[0]_i_2__0_n_0\ : STD_LOGIC;
  signal i : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \i[10]_i_4_n_0\ : STD_LOGIC;
  signal \i[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \i_reg_n_0_[0]\ : STD_LOGIC;
  signal \i_reg_n_0_[10]\ : STD_LOGIC;
  signal \i_reg_n_0_[1]\ : STD_LOGIC;
  signal \i_reg_n_0_[2]\ : STD_LOGIC;
  signal \i_reg_n_0_[3]\ : STD_LOGIC;
  signal \i_reg_n_0_[4]\ : STD_LOGIC;
  signal \i_reg_n_0_[5]\ : STD_LOGIC;
  signal \i_reg_n_0_[6]\ : STD_LOGIC;
  signal \i_reg_n_0_[7]\ : STD_LOGIC;
  signal \i_reg_n_0_[8]\ : STD_LOGIC;
  signal \i_reg_n_0_[9]\ : STD_LOGIC;
  signal in9 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal j : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \j[6]_i_2_n_0\ : STD_LOGIC;
  signal \j[6]_i_3_n_0\ : STD_LOGIC;
  signal \j[7]_i_3__0_n_0\ : STD_LOGIC;
  signal \j_reg_n_0_[0]\ : STD_LOGIC;
  signal \j_reg_n_0_[1]\ : STD_LOGIC;
  signal \j_reg_n_0_[2]\ : STD_LOGIC;
  signal \j_reg_n_0_[3]\ : STD_LOGIC;
  signal \j_reg_n_0_[4]\ : STD_LOGIC;
  signal \j_reg_n_0_[5]\ : STD_LOGIC;
  signal \j_reg_n_0_[6]\ : STD_LOGIC;
  signal \j_reg_n_0_[7]\ : STD_LOGIC;
  signal len : STD_LOGIC_VECTOR ( 1 to 1 );
  signal mySpi_n_10 : STD_LOGIC;
  signal mySpi_n_3 : STD_LOGIC;
  signal mySpi_n_4 : STD_LOGIC;
  signal mySpi_n_5 : STD_LOGIC;
  signal mySpi_n_6 : STD_LOGIC;
  signal mySpi_n_7 : STD_LOGIC;
  signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal p_4_out : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rNotL : STD_LOGIC;
  signal rNotL_reg_n_0 : STD_LOGIC;
  signal \r_lcl[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[0]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[1]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[2]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[3]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[4]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[5]\ : STD_LOGIC;
  signal send : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal spilen : STD_LOGIC;
  signal \spilen[1]_i_1_n_0\ : STD_LOGIC;
  signal \spisend[0]_i_1_n_0\ : STD_LOGIC;
  signal \spisend[1]_i_1_n_0\ : STD_LOGIC;
  signal \spisend[1]_i_2_n_0\ : STD_LOGIC;
  signal \spisend[1]_i_3_n_0\ : STD_LOGIC;
  signal \spisend[2]_i_1_n_0\ : STD_LOGIC;
  signal \spisend[2]_i_2_n_0\ : STD_LOGIC;
  signal \spisend[3]_i_1_n_0\ : STD_LOGIC;
  signal \spisend[3]_i_2_n_0\ : STD_LOGIC;
  signal \spisend[3]_i_3_n_0\ : STD_LOGIC;
  signal \spisend[4]_i_1_n_0\ : STD_LOGIC;
  signal \spisend[5]_i_1_n_0\ : STD_LOGIC;
  signal \spisend[6]_i_1_n_0\ : STD_LOGIC;
  signal \spisend[7]_i_1_n_0\ : STD_LOGIC;
  signal stateOp : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \txbuf[0]_59\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txbuf_reg[0]_58\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \txbuf_reg[1]_57\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal updNotPrep_i_1_n_0 : STD_LOGIC;
  signal updNotPrep_reg_n_0 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_stateOp[2]_i_12\ : label is "soft_lutpair2506";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateOp_reg[0]\ : label is "iSTATE:000,iSTATE0:110,iSTATE1:111,iSTATE2:010,iSTATE3:011,iSTATE4:101,iSTATE5:100,iSTATE6:001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateOp_reg[1]\ : label is "iSTATE:000,iSTATE0:110,iSTATE1:111,iSTATE2:010,iSTATE3:011,iSTATE4:101,iSTATE5:100,iSTATE6:001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateOp_reg[2]\ : label is "iSTATE:000,iSTATE0:110,iSTATE1:111,iSTATE2:010,iSTATE3:011,iSTATE4:101,iSTATE5:100,iSTATE6:001";
  attribute SOFT_HLUTNM of \bytecnt[0]_i_2__0\ : label is "soft_lutpair2498";
  attribute SOFT_HLUTNM of \i[0]_i_1__17\ : label is "soft_lutpair2505";
  attribute SOFT_HLUTNM of \i[1]_i_1__17\ : label is "soft_lutpair2505";
  attribute SOFT_HLUTNM of \i[7]_i_1__9\ : label is "soft_lutpair2506";
  attribute SOFT_HLUTNM of \j[0]_i_1__2\ : label is "soft_lutpair2507";
  attribute SOFT_HLUTNM of \j[1]_i_1__1\ : label is "soft_lutpair2507";
  attribute SOFT_HLUTNM of \j[3]_i_1__1\ : label is "soft_lutpair2508";
  attribute SOFT_HLUTNM of \j[6]_i_2\ : label is "soft_lutpair2508";
  attribute SOFT_HLUTNM of \j[6]_i_3\ : label is "soft_lutpair2502";
  attribute SOFT_HLUTNM of \spisend[1]_i_2\ : label is "soft_lutpair2499";
  attribute SOFT_HLUTNM of \spisend[1]_i_3\ : label is "soft_lutpair2498";
  attribute SOFT_HLUTNM of \spisend[3]_i_2\ : label is "soft_lutpair2504";
  attribute SOFT_HLUTNM of \stateOp[5]_i_74\ : label is "soft_lutpair2503";
  attribute SOFT_HLUTNM of \txbuf[0][0]_i_1\ : label is "soft_lutpair2502";
  attribute SOFT_HLUTNM of \txbuf[0][1]_i_1\ : label is "soft_lutpair2501";
  attribute SOFT_HLUTNM of \txbuf[0][2]_i_1\ : label is "soft_lutpair2500";
  attribute SOFT_HLUTNM of \txbuf[0][3]_i_1\ : label is "soft_lutpair2499";
  attribute SOFT_HLUTNM of \txbuf[0][4]_i_1\ : label is "soft_lutpair2501";
  attribute SOFT_HLUTNM of \txbuf[0][7]_i_1\ : label is "soft_lutpair2500";
  attribute SOFT_HLUTNM of \txbuf[1][2]_i_1\ : label is "soft_lutpair2503";
  attribute SOFT_HLUTNM of \txbuf[1][3]_i_1\ : label is "soft_lutpair2504";
begin
\FSM_sequential_stateOp[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rNotL_reg_n_0,
      I1 => updNotPrep_reg_n_0,
      O => \FSM_sequential_stateOp[0]_i_3_n_0\
    );
\FSM_sequential_stateOp[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08CC0BCC"
    )
        port map (
      I0 => \FSM_sequential_stateOp[2]_i_8_n_0\,
      I1 => stateOp(0),
      I2 => stateOp(2),
      I3 => stateOp(1),
      I4 => updNotPrep_reg_n_0,
      O => p_4_out(1)
    );
\FSM_sequential_stateOp[2]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => \j_reg_n_0_[2]\,
      I1 => \j_reg_n_0_[0]\,
      I2 => \j_reg_n_0_[3]\,
      I3 => \j_reg_n_0_[4]\,
      O => \FSM_sequential_stateOp[2]_i_10_n_0\
    );
\FSM_sequential_stateOp[2]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEFFF"
    )
        port map (
      I0 => \i_reg_n_0_[8]\,
      I1 => \i_reg_n_0_[7]\,
      I2 => \i_reg_n_0_[9]\,
      I3 => \i_reg_n_0_[10]\,
      I4 => \i_reg_n_0_[0]\,
      I5 => \FSM_sequential_stateOp[2]_i_12_n_0\,
      O => \FSM_sequential_stateOp[2]_i_11_n_0\
    );
\FSM_sequential_stateOp[2]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \i_reg_n_0_[5]\,
      I1 => \i_reg_n_0_[6]\,
      O => \FSM_sequential_stateOp[2]_i_12_n_0\
    );
\FSM_sequential_stateOp[2]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFBFF"
    )
        port map (
      I0 => \j_reg_n_0_[1]\,
      I1 => \j_reg_n_0_[6]\,
      I2 => \j_reg_n_0_[5]\,
      I3 => \j_reg_n_0_[7]\,
      I4 => \FSM_sequential_stateOp[2]_i_10_n_0\,
      O => \FSM_sequential_stateOp[2]_i_6_n_0\
    );
\FSM_sequential_stateOp[2]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \FSM_sequential_stateOp[2]_i_11_n_0\,
      I1 => \i_reg_n_0_[3]\,
      I2 => \i_reg_n_0_[4]\,
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[2]\,
      O => \FSM_sequential_stateOp[2]_i_8_n_0\
    );
\FSM_sequential_stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_4,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => p_4_out(0),
      Q => stateOp(0)
    );
\FSM_sequential_stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_4,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => p_4_out(1),
      Q => stateOp(1)
    );
\FSM_sequential_stateOp_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_4,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => p_4_out(2),
      Q => stateOp(2)
    );
\bytecnt[0]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCC0C50"
    )
        port map (
      I0 => bytecnt(0),
      I1 => rNotL_reg_n_0,
      I2 => stateOp(0),
      I3 => stateOp(2),
      I4 => stateOp(1),
      O => \bytecnt[0]_i_2__0_n_0\
    );
\bytecnt_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_6,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => \bytecnt[0]_i_2__0_n_0\,
      Q => bytecnt(0)
    );
\i[0]_i_1__17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FB"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(1),
      I2 => stateOp(0),
      I3 => \i_reg_n_0_[0]\,
      O => i(0)
    );
\i[10]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBB0BB44444044"
    )
        port map (
      I0 => \i[10]_i_4_n_0\,
      I1 => \i_reg_n_0_[9]\,
      I2 => stateOp(2),
      I3 => stateOp(1),
      I4 => stateOp(0),
      I5 => \i_reg_n_0_[10]\,
      O => i(10)
    );
\i[10]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \i_reg_n_0_[7]\,
      I1 => \i_reg_n_0_[6]\,
      I2 => \i_reg_n_0_[5]\,
      I3 => \i[8]_i_2__0_n_0\,
      I4 => \i_reg_n_0_[8]\,
      O => \i[10]_i_4_n_0\
    );
\i[1]_i_1__17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FBFB00"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(1),
      I2 => stateOp(2),
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[1]\,
      O => i(1)
    );
\i[2]_i_1__13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FBFBFBFB000000"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(1),
      I2 => stateOp(2),
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[0]\,
      I5 => \i_reg_n_0_[2]\,
      O => i(2)
    );
\i[3]_i_1__13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"007F0080"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[2]\,
      I3 => \j[6]_i_3_n_0\,
      I4 => \i_reg_n_0_[3]\,
      O => i(3)
    );
\i[4]_i_1__13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007FFF00008000"
    )
        port map (
      I0 => \i_reg_n_0_[2]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \i_reg_n_0_[3]\,
      I4 => \j[6]_i_3_n_0\,
      I5 => \i_reg_n_0_[4]\,
      O => i(4)
    );
\i[5]_i_1__12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5545AA8A"
    )
        port map (
      I0 => \i[8]_i_2__0_n_0\,
      I1 => stateOp(2),
      I2 => stateOp(1),
      I3 => stateOp(0),
      I4 => \i_reg_n_0_[5]\,
      O => i(5)
    );
\i[6]_i_1__11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5545FFCFAA8A0000"
    )
        port map (
      I0 => \i[8]_i_2__0_n_0\,
      I1 => stateOp(0),
      I2 => stateOp(1),
      I3 => stateOp(2),
      I4 => \i_reg_n_0_[5]\,
      I5 => \i_reg_n_0_[6]\,
      O => i(6)
    );
\i[7]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"007F0080"
    )
        port map (
      I0 => \i_reg_n_0_[6]\,
      I1 => \i_reg_n_0_[5]\,
      I2 => \i[8]_i_2__0_n_0\,
      I3 => \j[6]_i_3_n_0\,
      I4 => \i_reg_n_0_[7]\,
      O => i(7)
    );
\i[8]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007FFF00008000"
    )
        port map (
      I0 => \i[8]_i_2__0_n_0\,
      I1 => \i_reg_n_0_[5]\,
      I2 => \i_reg_n_0_[6]\,
      I3 => \i_reg_n_0_[7]\,
      I4 => \j[6]_i_3_n_0\,
      I5 => \i_reg_n_0_[8]\,
      O => i(8)
    );
\i[8]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \i_reg_n_0_[4]\,
      I1 => \i_reg_n_0_[3]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[2]\,
      O => \i[8]_i_2__0_n_0\
    );
\i[9]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA8A5545"
    )
        port map (
      I0 => \i[10]_i_4_n_0\,
      I1 => stateOp(2),
      I2 => stateOp(1),
      I3 => stateOp(0),
      I4 => \i_reg_n_0_[9]\,
      O => i(9)
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_5,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => i(0),
      Q => \i_reg_n_0_[0]\
    );
\i_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_5,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => i(10),
      Q => \i_reg_n_0_[10]\
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_5,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => i(1),
      Q => \i_reg_n_0_[1]\
    );
\i_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_5,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => i(2),
      Q => \i_reg_n_0_[2]\
    );
\i_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_5,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => i(3),
      Q => \i_reg_n_0_[3]\
    );
\i_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_5,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => i(4),
      Q => \i_reg_n_0_[4]\
    );
\i_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_5,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => i(5),
      Q => \i_reg_n_0_[5]\
    );
\i_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_5,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => i(6),
      Q => \i_reg_n_0_[6]\
    );
\i_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_5,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => i(7),
      Q => \i_reg_n_0_[7]\
    );
\i_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_5,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => i(8),
      Q => \i_reg_n_0_[8]\
    );
\i_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_5,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => i(9),
      Q => \i_reg_n_0_[9]\
    );
\j[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FB"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(1),
      I2 => stateOp(0),
      I3 => \j_reg_n_0_[0]\,
      O => j(0)
    );
\j[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FBFB00"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(1),
      I2 => stateOp(2),
      I3 => \j_reg_n_0_[0]\,
      I4 => \j_reg_n_0_[1]\,
      O => j(1)
    );
\j[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FBFBFBFB000000"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(1),
      I2 => stateOp(2),
      I3 => \j_reg_n_0_[0]\,
      I4 => \j_reg_n_0_[1]\,
      I5 => \j_reg_n_0_[2]\,
      O => j(2)
    );
\j[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"007F0080"
    )
        port map (
      I0 => \j_reg_n_0_[0]\,
      I1 => \j_reg_n_0_[1]\,
      I2 => \j_reg_n_0_[2]\,
      I3 => \j[6]_i_3_n_0\,
      I4 => \j_reg_n_0_[3]\,
      O => j(3)
    );
\j[4]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => \j[6]_i_3_n_0\,
      I1 => \j_reg_n_0_[2]\,
      I2 => \j_reg_n_0_[1]\,
      I3 => \j_reg_n_0_[0]\,
      I4 => \j_reg_n_0_[3]\,
      I5 => \j_reg_n_0_[4]\,
      O => j(4)
    );
\j[5]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00F70008"
    )
        port map (
      I0 => \j_reg_n_0_[4]\,
      I1 => \j_reg_n_0_[3]\,
      I2 => \j[6]_i_2_n_0\,
      I3 => \j[6]_i_3_n_0\,
      I4 => \j_reg_n_0_[5]\,
      O => j(5)
    );
\j[6]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000BFFF00004000"
    )
        port map (
      I0 => \j[6]_i_2_n_0\,
      I1 => \j_reg_n_0_[3]\,
      I2 => \j_reg_n_0_[4]\,
      I3 => \j_reg_n_0_[5]\,
      I4 => \j[6]_i_3_n_0\,
      I5 => \j_reg_n_0_[6]\,
      O => j(6)
    );
\j[6]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \j_reg_n_0_[0]\,
      I1 => \j_reg_n_0_[1]\,
      I2 => \j_reg_n_0_[2]\,
      O => \j[6]_i_2_n_0\
    );
\j[6]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(1),
      I2 => stateOp(2),
      O => \j[6]_i_3_n_0\
    );
\j[7]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBB0BB44444044"
    )
        port map (
      I0 => \j[7]_i_3__0_n_0\,
      I1 => \j_reg_n_0_[6]\,
      I2 => stateOp(2),
      I3 => stateOp(1),
      I4 => stateOp(0),
      I5 => \j_reg_n_0_[7]\,
      O => j(7)
    );
\j[7]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \j_reg_n_0_[2]\,
      I1 => \j_reg_n_0_[1]\,
      I2 => \j_reg_n_0_[0]\,
      I3 => \j_reg_n_0_[3]\,
      I4 => \j_reg_n_0_[4]\,
      I5 => \j_reg_n_0_[5]\,
      O => \j[7]_i_3__0_n_0\
    );
\j_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_7,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => j(0),
      Q => \j_reg_n_0_[0]\
    );
\j_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_7,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => j(1),
      Q => \j_reg_n_0_[1]\
    );
\j_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_7,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => j(2),
      Q => \j_reg_n_0_[2]\
    );
\j_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_7,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => j(3),
      Q => \j_reg_n_0_[3]\
    );
\j_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_7,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => j(4),
      Q => \j_reg_n_0_[4]\
    );
\j_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_7,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => j(5),
      Q => \j_reg_n_0_[5]\
    );
\j_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_7,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => j(6),
      Q => \j_reg_n_0_[6]\
    );
\j_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => mySpi_n_7,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => j(7),
      Q => \j_reg_n_0_[7]\
    );
mySpi: entity work.design_1_Vsp_core_0_0_Spimaster_v1_0
     port map (
      D(1) => p_4_out(2),
      D(0) => p_4_out(0),
      E(0) => mySpi_n_3,
      \FSM_sequential_stateOp_reg[0]\ => mySpi_n_10,
      \FSM_sequential_stateOp_reg[0]_0\ => \FSM_sequential_stateOp[2]_i_6_n_0\,
      \FSM_sequential_stateOp_reg[0]_1\ => \FSM_sequential_stateOp[0]_i_3_n_0\,
      \FSM_sequential_stateOp_reg[1]\(0) => mySpi_n_4,
      \FSM_sequential_stateOp_reg[1]_0\(0) => mySpi_n_5,
      \FSM_sequential_stateOp_reg[1]_1\(0) => mySpi_n_7,
      \FSM_sequential_stateOp_reg[2]\(0) => mySpi_n_6,
      \FSM_sequential_stateXfer_reg[2]_0\(0) => \FSM_sequential_stateXfer_reg[2]\(0),
      Q(2 downto 0) => stateOp(2 downto 0),
      aclk_sig => aclk_sig,
      cs => cs,
      \i_reg[0]_0\ => \FSM_sequential_stateOp[2]_i_8_n_0\,
      \i_reg[0]_1\ => updNotPrep_reg_n_0,
      len(0) => len(1),
      mosi => mosi,
      rNotL_reg => rNotL_reg_n_0,
      reqInvLaserSet => reqInvLaserSet,
      sclk => sclk,
      \send_var_reg[7]_0\(7 downto 0) => send(7 downto 0)
    );
rNotL_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => mySpi_n_10,
      Q => rNotL_reg_n_0
    );
\r_lcl[9]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => reqInvLaserSet,
      I1 => stateOp(2),
      I2 => stateOp(1),
      I3 => stateOp(0),
      O => \r_lcl[9]_i_1__0_n_0\
    );
\r_lcl_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \r_lcl[9]_i_1__0_n_0\,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => D(0),
      Q => \r_lcl_reg_n_0_[0]\
    );
\r_lcl_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \r_lcl[9]_i_1__0_n_0\,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => D(1),
      Q => \r_lcl_reg_n_0_[1]\
    );
\r_lcl_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \r_lcl[9]_i_1__0_n_0\,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => D(2),
      Q => \r_lcl_reg_n_0_[2]\
    );
\r_lcl_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \r_lcl[9]_i_1__0_n_0\,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => D(3),
      Q => \r_lcl_reg_n_0_[3]\
    );
\r_lcl_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \r_lcl[9]_i_1__0_n_0\,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => D(4),
      Q => \r_lcl_reg_n_0_[4]\
    );
\r_lcl_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \r_lcl[9]_i_1__0_n_0\,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => D(5),
      Q => \r_lcl_reg_n_0_[5]\
    );
\r_lcl_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \r_lcl[9]_i_1__0_n_0\,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => D(6),
      Q => in9(0)
    );
\r_lcl_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \r_lcl[9]_i_1__0_n_0\,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => D(7),
      Q => in9(1)
    );
\r_lcl_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \r_lcl[9]_i_1__0_n_0\,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => D(8),
      Q => in9(2)
    );
\r_lcl_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \r_lcl[9]_i_1__0_n_0\,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => D(9),
      Q => in9(3)
    );
\spilen[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => len(1),
      I1 => stateOp(0),
      I2 => stateOp(1),
      I3 => stateOp(2),
      O => \spilen[1]_i_1_n_0\
    );
\spilen_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => \spilen[1]_i_1_n_0\,
      Q => len(1)
    );
\spisend[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888FFFFF888F888"
    )
        port map (
      I0 => \spisend[1]_i_2_n_0\,
      I1 => in9(0),
      I2 => \spisend[1]_i_3_n_0\,
      I3 => \txbuf_reg[0]_58\(0),
      I4 => rNotL,
      I5 => D(16),
      O => \spisend[0]_i_1_n_0\
    );
\spisend[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888FFFFF888F888"
    )
        port map (
      I0 => \spisend[1]_i_2_n_0\,
      I1 => in9(1),
      I2 => \spisend[1]_i_3_n_0\,
      I3 => \txbuf_reg[0]_58\(1),
      I4 => rNotL,
      I5 => D(17),
      O => \spisend[1]_i_1_n_0\
    );
\spisend[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(2),
      I2 => stateOp(1),
      O => \spisend[1]_i_2_n_0\
    );
\spisend[1]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(1),
      I2 => stateOp(0),
      I3 => bytecnt(0),
      O => \spisend[1]_i_3_n_0\
    );
\spisend[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF32300200"
    )
        port map (
      I0 => bytecnt(0),
      I1 => \spisend[3]_i_2_n_0\,
      I2 => stateOp(2),
      I3 => \txbuf_reg[0]_58\(2),
      I4 => \txbuf_reg[0][3]_0\(0),
      I5 => \spisend[2]_i_2_n_0\,
      O => \spisend[2]_i_1_n_0\
    );
\spisend[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0F0F000F02200"
    )
        port map (
      I0 => \txbuf_reg[1]_57\(2),
      I1 => bytecnt(0),
      I2 => in9(2),
      I3 => stateOp(0),
      I4 => stateOp(2),
      I5 => stateOp(1),
      O => \spisend[2]_i_2_n_0\
    );
\spisend[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF32300200"
    )
        port map (
      I0 => bytecnt(0),
      I1 => \spisend[3]_i_2_n_0\,
      I2 => stateOp(2),
      I3 => \txbuf_reg[0]_58\(3),
      I4 => \txbuf_reg[0][3]_0\(1),
      I5 => \spisend[3]_i_3_n_0\,
      O => \spisend[3]_i_1_n_0\
    );
\spisend[3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => stateOp(1),
      I1 => stateOp(0),
      O => \spisend[3]_i_2_n_0\
    );
\spisend[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0F0F000F02200"
    )
        port map (
      I0 => \txbuf_reg[1]_57\(3),
      I1 => bytecnt(0),
      I2 => in9(3),
      I3 => stateOp(0),
      I4 => stateOp(2),
      I5 => stateOp(1),
      O => \spisend[3]_i_3_n_0\
    );
\spisend[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBFFBBFBBBBBBBFB"
    )
        port map (
      I0 => stateOp(1),
      I1 => stateOp(0),
      I2 => \txbuf_reg[1]_57\(4),
      I3 => stateOp(2),
      I4 => bytecnt(0),
      I5 => \txbuf_reg[0]_58\(4),
      O => \spisend[4]_i_1_n_0\
    );
\spisend[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000B000B000F0003"
    )
        port map (
      I0 => \txbuf_reg[0]_58\(7),
      I1 => stateOp(0),
      I2 => stateOp(1),
      I3 => stateOp(2),
      I4 => \txbuf_reg[1]_57\(5),
      I5 => bytecnt(0),
      O => \spisend[5]_i_1_n_0\
    );
\spisend[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000B000B000F0003"
    )
        port map (
      I0 => \txbuf_reg[0]_58\(7),
      I1 => stateOp(0),
      I2 => stateOp(1),
      I3 => stateOp(2),
      I4 => \txbuf_reg[1]_57\(6),
      I5 => bytecnt(0),
      O => \spisend[6]_i_1_n_0\
    );
\spisend[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000B000B000F0003"
    )
        port map (
      I0 => \txbuf_reg[0]_58\(7),
      I1 => stateOp(0),
      I2 => stateOp(1),
      I3 => stateOp(2),
      I4 => \txbuf_reg[1]_57\(7),
      I5 => bytecnt(0),
      O => \spisend[7]_i_1_n_0\
    );
\spisend_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_6,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => \spisend[0]_i_1_n_0\,
      Q => send(0)
    );
\spisend_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_6,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => \spisend[1]_i_1_n_0\,
      Q => send(1)
    );
\spisend_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_6,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => \spisend[2]_i_1_n_0\,
      Q => send(2)
    );
\spisend_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_6,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => \spisend[3]_i_1_n_0\,
      Q => send(3)
    );
\spisend_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_6,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => \spisend[4]_i_1_n_0\,
      Q => send(4)
    );
\spisend_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_6,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => \spisend[5]_i_1_n_0\,
      Q => send(5)
    );
\spisend_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_6,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => \spisend[6]_i_1_n_0\,
      Q => send(6)
    );
\spisend_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_6,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => \spisend[7]_i_1_n_0\,
      Q => send(7)
    );
\stateOp[5]_i_74\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(1),
      I2 => stateOp(2),
      O => ackInvLaserSet
    );
\txbuf[0][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAACAA0"
    )
        port map (
      I0 => in9(0),
      I1 => D(16),
      I2 => stateOp(0),
      I3 => stateOp(2),
      I4 => stateOp(1),
      O => \txbuf[0]_59\(0)
    );
\txbuf[0][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAACAA0"
    )
        port map (
      I0 => in9(1),
      I1 => D(17),
      I2 => stateOp(0),
      I3 => stateOp(2),
      I4 => stateOp(1),
      O => \txbuf[0]_59\(1)
    );
\txbuf[0][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAACAA0"
    )
        port map (
      I0 => in9(2),
      I1 => \txbuf_reg[0][3]_0\(0),
      I2 => stateOp(0),
      I3 => stateOp(2),
      I4 => stateOp(1),
      O => \txbuf[0]_59\(2)
    );
\txbuf[0][3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAACAA0"
    )
        port map (
      I0 => in9(3),
      I1 => \txbuf_reg[0][3]_0\(1),
      I2 => stateOp(0),
      I3 => stateOp(2),
      I4 => stateOp(1),
      O => \txbuf[0]_59\(3)
    );
\txbuf[0][4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(1),
      I2 => stateOp(2),
      O => rNotL
    );
\txbuf[0][7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(1),
      I2 => stateOp(2),
      O => spilen
    );
\txbuf[1][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCACCCC0"
    )
        port map (
      I0 => D(10),
      I1 => \r_lcl_reg_n_0_[0]\,
      I2 => stateOp(0),
      I3 => stateOp(1),
      I4 => stateOp(2),
      O => p_1_in(2)
    );
\txbuf[1][3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCACCCC0"
    )
        port map (
      I0 => D(11),
      I1 => \r_lcl_reg_n_0_[1]\,
      I2 => stateOp(0),
      I3 => stateOp(1),
      I4 => stateOp(2),
      O => p_1_in(3)
    );
\txbuf[1][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEABA2AB"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[2]\,
      I1 => stateOp(0),
      I2 => stateOp(1),
      I3 => stateOp(2),
      I4 => D(12),
      O => p_1_in(4)
    );
\txbuf[1][5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCACCCC0"
    )
        port map (
      I0 => D(13),
      I1 => \r_lcl_reg_n_0_[3]\,
      I2 => stateOp(0),
      I3 => stateOp(1),
      I4 => stateOp(2),
      O => p_1_in(5)
    );
\txbuf[1][6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCACCCC0"
    )
        port map (
      I0 => D(14),
      I1 => \r_lcl_reg_n_0_[4]\,
      I2 => stateOp(0),
      I3 => stateOp(1),
      I4 => stateOp(2),
      O => p_1_in(6)
    );
\txbuf[1][7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCACCCC0"
    )
        port map (
      I0 => D(15),
      I1 => \r_lcl_reg_n_0_[5]\,
      I2 => stateOp(0),
      I3 => stateOp(1),
      I4 => stateOp(2),
      O => p_1_in(7)
    );
\txbuf_reg[0][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_3,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => \txbuf[0]_59\(0),
      Q => \txbuf_reg[0]_58\(0)
    );
\txbuf_reg[0][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_3,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => \txbuf[0]_59\(1),
      Q => \txbuf_reg[0]_58\(1)
    );
\txbuf_reg[0][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_3,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => \txbuf[0]_59\(2),
      Q => \txbuf_reg[0]_58\(2)
    );
\txbuf_reg[0][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_3,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => \txbuf[0]_59\(3),
      Q => \txbuf_reg[0]_58\(3)
    );
\txbuf_reg[0][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_3,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => rNotL,
      Q => \txbuf_reg[0]_58\(4)
    );
\txbuf_reg[0][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_3,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => spilen,
      Q => \txbuf_reg[0]_58\(7)
    );
\txbuf_reg[1][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_3,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => p_1_in(2),
      Q => \txbuf_reg[1]_57\(2)
    );
\txbuf_reg[1][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_3,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => p_1_in(3),
      Q => \txbuf_reg[1]_57\(3)
    );
\txbuf_reg[1][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_3,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => p_1_in(4),
      Q => \txbuf_reg[1]_57\(4)
    );
\txbuf_reg[1][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_3,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => p_1_in(5),
      Q => \txbuf_reg[1]_57\(5)
    );
\txbuf_reg[1][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_3,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => p_1_in(6),
      Q => \txbuf_reg[1]_57\(6)
    );
\txbuf_reg[1][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => mySpi_n_3,
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => p_1_in(7),
      Q => \txbuf_reg[1]_57\(7)
    );
updNotPrep_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0800"
    )
        port map (
      I0 => reqInvLaserSet,
      I1 => stateOp(0),
      I2 => stateOp(1),
      I3 => stateOp(2),
      I4 => updNotPrep_reg_n_0,
      O => updNotPrep_i_1_n_0
    );
updNotPrep_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \FSM_sequential_stateXfer_reg[2]\(0),
      D => updNotPrep_i_1_n_0,
      Q => updNotPrep_reg_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Rpuif is
  port (
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    rpuAXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \mask_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    AXIL_wready_sig_reg : out STD_LOGIC;
    AXIL_awready_sig_reg : out STD_LOGIC;
    AXIL_arready : out STD_LOGIC;
    AXIL_bvalid_sig_reg : out STD_LOGIC;
    rpuAXIL_rvalid : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    \stateOp_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    tkclk : in STD_LOGIC;
    \capt_reg[4]\ : in STD_LOGIC;
    \retbuf_reg[5][7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \retbuf_reg[1][7]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \retbuf_reg[0][1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \retbuf_reg[6][7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    rpuAXIL_wvalid : in STD_LOGIC;
    rpuAXIL_awvalid : in STD_LOGIC;
    rpuAXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    rpuAXIL_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rpuAXIL_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rpuAXIL_bready : in STD_LOGIC;
    rpuAXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rpuAXIL_arvalid : in STD_LOGIC;
    rpuAXIL_rready : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Rpuif : entity is "Rpuif";
end design_1_Vsp_core_0_0_Rpuif;

architecture STRUCTURE of design_1_Vsp_core_0_0_Rpuif is
  signal AXIS_tdata : STD_LOGIC_VECTOR ( 30 downto 0 );
  signal AXIS_tkeep : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal AXIS_tlast : STD_LOGIC;
  signal AXIS_tvalid : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal crcAXIS_tkeep1 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \crcAXIS_tkeep[0]_i_2_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[1]_i_2_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_12_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_13_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_14_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_15_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_16_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_17_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_18_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_20_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_21_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_22_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_24_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_25_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_26_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_27_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_28_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_29_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_30_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_31_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_32_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_33_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_34_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_35_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_36_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_37_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_38_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_39_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_40_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_41_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_42_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_43_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_44_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_45_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_47_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_48_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep[3]_i_7_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_10_n_5\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_10_n_6\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_10_n_7\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_11_n_5\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_11_n_6\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_11_n_7\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_19_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_19_n_1\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_19_n_2\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_19_n_3\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_19_n_4\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_19_n_5\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_19_n_6\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_19_n_7\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_23_n_0\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_23_n_1\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_23_n_2\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_23_n_3\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_23_n_4\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_23_n_5\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_23_n_6\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_23_n_7\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_46_n_5\ : STD_LOGIC;
  signal \crcAXIS_tkeep_reg[3]_i_46_n_7\ : STD_LOGIC;
  signal \crcAXIS_tlast_sig_i_10__0_n_0\ : STD_LOGIC;
  signal \crcAXIS_tlast_sig_i_3__0_n_0\ : STD_LOGIC;
  signal \crcAXIS_tlast_sig_i_6__0_n_0\ : STD_LOGIC;
  signal \crcAXIS_tlast_sig_i_7__0_n_0\ : STD_LOGIC;
  signal crcAXIS_tlast_sig_reg_n_0 : STD_LOGIC;
  signal crc_imd013_out : STD_LOGIC;
  signal crc_imd015_out : STD_LOGIC;
  signal crc_imd017_out : STD_LOGIC;
  signal crc_imd019_out : STD_LOGIC;
  signal crc_imd020_out : STD_LOGIC;
  signal crc_imd032_out : STD_LOGIC;
  signal crc_imd033_out : STD_LOGIC;
  signal crc_imd059_out : STD_LOGIC;
  signal crc_imd060_out : STD_LOGIC;
  signal ixRetbufCrc : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \ixRetbufCrc[2]_i_2_n_0\ : STD_LOGIC;
  signal \lastAXIS_tkeep__0\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal lenRet1 : STD_LOGIC;
  signal \len_reg_n_0_[0]\ : STD_LOGIC;
  signal \len_reg_n_0_[10]\ : STD_LOGIC;
  signal \len_reg_n_0_[11]\ : STD_LOGIC;
  signal \len_reg_n_0_[12]\ : STD_LOGIC;
  signal \len_reg_n_0_[13]\ : STD_LOGIC;
  signal \len_reg_n_0_[14]\ : STD_LOGIC;
  signal \len_reg_n_0_[15]\ : STD_LOGIC;
  signal \len_reg_n_0_[1]\ : STD_LOGIC;
  signal \len_reg_n_0_[2]\ : STD_LOGIC;
  signal \len_reg_n_0_[3]\ : STD_LOGIC;
  signal \len_reg_n_0_[4]\ : STD_LOGIC;
  signal \len_reg_n_0_[5]\ : STD_LOGIC;
  signal \len_reg_n_0_[6]\ : STD_LOGIC;
  signal \len_reg_n_0_[7]\ : STD_LOGIC;
  signal \len_reg_n_0_[8]\ : STD_LOGIC;
  signal \len_reg_n_0_[9]\ : STD_LOGIC;
  signal myCrc_n_0 : STD_LOGIC;
  signal myCrc_n_1 : STD_LOGIC;
  signal myCrc_n_10 : STD_LOGIC;
  signal myCrc_n_100 : STD_LOGIC;
  signal myCrc_n_101 : STD_LOGIC;
  signal myCrc_n_102 : STD_LOGIC;
  signal myCrc_n_103 : STD_LOGIC;
  signal myCrc_n_104 : STD_LOGIC;
  signal myCrc_n_105 : STD_LOGIC;
  signal myCrc_n_106 : STD_LOGIC;
  signal myCrc_n_107 : STD_LOGIC;
  signal myCrc_n_108 : STD_LOGIC;
  signal myCrc_n_109 : STD_LOGIC;
  signal myCrc_n_11 : STD_LOGIC;
  signal myCrc_n_110 : STD_LOGIC;
  signal myCrc_n_111 : STD_LOGIC;
  signal myCrc_n_112 : STD_LOGIC;
  signal myCrc_n_113 : STD_LOGIC;
  signal myCrc_n_114 : STD_LOGIC;
  signal myCrc_n_115 : STD_LOGIC;
  signal myCrc_n_116 : STD_LOGIC;
  signal myCrc_n_117 : STD_LOGIC;
  signal myCrc_n_118 : STD_LOGIC;
  signal myCrc_n_119 : STD_LOGIC;
  signal myCrc_n_12 : STD_LOGIC;
  signal myCrc_n_120 : STD_LOGIC;
  signal myCrc_n_121 : STD_LOGIC;
  signal myCrc_n_122 : STD_LOGIC;
  signal myCrc_n_123 : STD_LOGIC;
  signal myCrc_n_124 : STD_LOGIC;
  signal myCrc_n_125 : STD_LOGIC;
  signal myCrc_n_126 : STD_LOGIC;
  signal myCrc_n_127 : STD_LOGIC;
  signal myCrc_n_128 : STD_LOGIC;
  signal myCrc_n_129 : STD_LOGIC;
  signal myCrc_n_13 : STD_LOGIC;
  signal myCrc_n_130 : STD_LOGIC;
  signal myCrc_n_131 : STD_LOGIC;
  signal myCrc_n_132 : STD_LOGIC;
  signal myCrc_n_133 : STD_LOGIC;
  signal myCrc_n_134 : STD_LOGIC;
  signal myCrc_n_135 : STD_LOGIC;
  signal myCrc_n_136 : STD_LOGIC;
  signal myCrc_n_137 : STD_LOGIC;
  signal myCrc_n_138 : STD_LOGIC;
  signal myCrc_n_139 : STD_LOGIC;
  signal myCrc_n_14 : STD_LOGIC;
  signal myCrc_n_140 : STD_LOGIC;
  signal myCrc_n_141 : STD_LOGIC;
  signal myCrc_n_142 : STD_LOGIC;
  signal myCrc_n_143 : STD_LOGIC;
  signal myCrc_n_144 : STD_LOGIC;
  signal myCrc_n_145 : STD_LOGIC;
  signal myCrc_n_146 : STD_LOGIC;
  signal myCrc_n_147 : STD_LOGIC;
  signal myCrc_n_148 : STD_LOGIC;
  signal myCrc_n_149 : STD_LOGIC;
  signal myCrc_n_15 : STD_LOGIC;
  signal myCrc_n_150 : STD_LOGIC;
  signal myCrc_n_151 : STD_LOGIC;
  signal myCrc_n_152 : STD_LOGIC;
  signal myCrc_n_153 : STD_LOGIC;
  signal myCrc_n_154 : STD_LOGIC;
  signal myCrc_n_155 : STD_LOGIC;
  signal myCrc_n_156 : STD_LOGIC;
  signal myCrc_n_157 : STD_LOGIC;
  signal myCrc_n_158 : STD_LOGIC;
  signal myCrc_n_159 : STD_LOGIC;
  signal myCrc_n_16 : STD_LOGIC;
  signal myCrc_n_160 : STD_LOGIC;
  signal myCrc_n_161 : STD_LOGIC;
  signal myCrc_n_162 : STD_LOGIC;
  signal myCrc_n_163 : STD_LOGIC;
  signal myCrc_n_164 : STD_LOGIC;
  signal myCrc_n_165 : STD_LOGIC;
  signal myCrc_n_166 : STD_LOGIC;
  signal myCrc_n_167 : STD_LOGIC;
  signal myCrc_n_168 : STD_LOGIC;
  signal myCrc_n_169 : STD_LOGIC;
  signal myCrc_n_17 : STD_LOGIC;
  signal myCrc_n_170 : STD_LOGIC;
  signal myCrc_n_171 : STD_LOGIC;
  signal myCrc_n_172 : STD_LOGIC;
  signal myCrc_n_173 : STD_LOGIC;
  signal myCrc_n_18 : STD_LOGIC;
  signal myCrc_n_19 : STD_LOGIC;
  signal myCrc_n_2 : STD_LOGIC;
  signal myCrc_n_20 : STD_LOGIC;
  signal myCrc_n_21 : STD_LOGIC;
  signal myCrc_n_22 : STD_LOGIC;
  signal myCrc_n_23 : STD_LOGIC;
  signal myCrc_n_24 : STD_LOGIC;
  signal myCrc_n_25 : STD_LOGIC;
  signal myCrc_n_26 : STD_LOGIC;
  signal myCrc_n_27 : STD_LOGIC;
  signal myCrc_n_28 : STD_LOGIC;
  signal myCrc_n_29 : STD_LOGIC;
  signal myCrc_n_3 : STD_LOGIC;
  signal myCrc_n_30 : STD_LOGIC;
  signal myCrc_n_32 : STD_LOGIC;
  signal myCrc_n_34 : STD_LOGIC;
  signal myCrc_n_35 : STD_LOGIC;
  signal myCrc_n_36 : STD_LOGIC;
  signal myCrc_n_37 : STD_LOGIC;
  signal myCrc_n_4 : STD_LOGIC;
  signal myCrc_n_41 : STD_LOGIC;
  signal myCrc_n_42 : STD_LOGIC;
  signal myCrc_n_43 : STD_LOGIC;
  signal myCrc_n_44 : STD_LOGIC;
  signal myCrc_n_45 : STD_LOGIC;
  signal myCrc_n_46 : STD_LOGIC;
  signal myCrc_n_47 : STD_LOGIC;
  signal myCrc_n_48 : STD_LOGIC;
  signal myCrc_n_49 : STD_LOGIC;
  signal myCrc_n_5 : STD_LOGIC;
  signal myCrc_n_50 : STD_LOGIC;
  signal myCrc_n_51 : STD_LOGIC;
  signal myCrc_n_53 : STD_LOGIC;
  signal myCrc_n_54 : STD_LOGIC;
  signal myCrc_n_55 : STD_LOGIC;
  signal myCrc_n_57 : STD_LOGIC;
  signal myCrc_n_58 : STD_LOGIC;
  signal myCrc_n_59 : STD_LOGIC;
  signal myCrc_n_6 : STD_LOGIC;
  signal myCrc_n_60 : STD_LOGIC;
  signal myCrc_n_61 : STD_LOGIC;
  signal myCrc_n_62 : STD_LOGIC;
  signal myCrc_n_63 : STD_LOGIC;
  signal myCrc_n_64 : STD_LOGIC;
  signal myCrc_n_65 : STD_LOGIC;
  signal myCrc_n_66 : STD_LOGIC;
  signal myCrc_n_67 : STD_LOGIC;
  signal myCrc_n_68 : STD_LOGIC;
  signal myCrc_n_69 : STD_LOGIC;
  signal myCrc_n_7 : STD_LOGIC;
  signal myCrc_n_70 : STD_LOGIC;
  signal myCrc_n_71 : STD_LOGIC;
  signal myCrc_n_72 : STD_LOGIC;
  signal myCrc_n_73 : STD_LOGIC;
  signal myCrc_n_74 : STD_LOGIC;
  signal myCrc_n_75 : STD_LOGIC;
  signal myCrc_n_76 : STD_LOGIC;
  signal myCrc_n_77 : STD_LOGIC;
  signal myCrc_n_78 : STD_LOGIC;
  signal myCrc_n_79 : STD_LOGIC;
  signal myCrc_n_8 : STD_LOGIC;
  signal myCrc_n_80 : STD_LOGIC;
  signal myCrc_n_81 : STD_LOGIC;
  signal myCrc_n_82 : STD_LOGIC;
  signal myCrc_n_83 : STD_LOGIC;
  signal myCrc_n_84 : STD_LOGIC;
  signal myCrc_n_85 : STD_LOGIC;
  signal myCrc_n_86 : STD_LOGIC;
  signal myCrc_n_87 : STD_LOGIC;
  signal myCrc_n_88 : STD_LOGIC;
  signal myCrc_n_89 : STD_LOGIC;
  signal myCrc_n_9 : STD_LOGIC;
  signal myCrc_n_90 : STD_LOGIC;
  signal myCrc_n_91 : STD_LOGIC;
  signal myCrc_n_92 : STD_LOGIC;
  signal myCrc_n_93 : STD_LOGIC;
  signal myCrc_n_94 : STD_LOGIC;
  signal myCrc_n_95 : STD_LOGIC;
  signal myCrc_n_96 : STD_LOGIC;
  signal myCrc_n_97 : STD_LOGIC;
  signal myCrc_n_98 : STD_LOGIC;
  signal myCrc_n_99 : STD_LOGIC;
  signal myRxtx_n_0 : STD_LOGIC;
  signal myRxtx_n_1 : STD_LOGIC;
  signal myRxtx_n_125 : STD_LOGIC;
  signal myRxtx_n_126 : STD_LOGIC;
  signal myRxtx_n_127 : STD_LOGIC;
  signal myRxtx_n_128 : STD_LOGIC;
  signal myRxtx_n_129 : STD_LOGIC;
  signal myRxtx_n_130 : STD_LOGIC;
  signal myRxtx_n_131 : STD_LOGIC;
  signal myRxtx_n_132 : STD_LOGIC;
  signal myRxtx_n_133 : STD_LOGIC;
  signal myRxtx_n_134 : STD_LOGIC;
  signal myRxtx_n_135 : STD_LOGIC;
  signal myRxtx_n_136 : STD_LOGIC;
  signal myRxtx_n_137 : STD_LOGIC;
  signal myRxtx_n_138 : STD_LOGIC;
  signal myRxtx_n_141 : STD_LOGIC;
  signal myRxtx_n_142 : STD_LOGIC;
  signal myRxtx_n_143 : STD_LOGIC;
  signal myRxtx_n_144 : STD_LOGIC;
  signal myRxtx_n_145 : STD_LOGIC;
  signal myRxtx_n_158 : STD_LOGIC;
  signal myRxtx_n_161 : STD_LOGIC;
  signal myRxtx_n_162 : STD_LOGIC;
  signal myRxtx_n_163 : STD_LOGIC;
  signal myRxtx_n_164 : STD_LOGIC;
  signal myRxtx_n_165 : STD_LOGIC;
  signal myRxtx_n_166 : STD_LOGIC;
  signal myRxtx_n_167 : STD_LOGIC;
  signal myRxtx_n_168 : STD_LOGIC;
  signal myRxtx_n_169 : STD_LOGIC;
  signal myRxtx_n_170 : STD_LOGIC;
  signal myRxtx_n_171 : STD_LOGIC;
  signal myRxtx_n_172 : STD_LOGIC;
  signal myRxtx_n_173 : STD_LOGIC;
  signal myRxtx_n_174 : STD_LOGIC;
  signal myRxtx_n_175 : STD_LOGIC;
  signal myRxtx_n_177 : STD_LOGIC;
  signal myRxtx_n_178 : STD_LOGIC;
  signal myRxtx_n_179 : STD_LOGIC;
  signal myRxtx_n_18 : STD_LOGIC;
  signal myRxtx_n_180 : STD_LOGIC;
  signal myRxtx_n_181 : STD_LOGIC;
  signal myRxtx_n_182 : STD_LOGIC;
  signal myRxtx_n_183 : STD_LOGIC;
  signal myRxtx_n_184 : STD_LOGIC;
  signal myRxtx_n_185 : STD_LOGIC;
  signal myRxtx_n_186 : STD_LOGIC;
  signal myRxtx_n_187 : STD_LOGIC;
  signal myRxtx_n_188 : STD_LOGIC;
  signal myRxtx_n_189 : STD_LOGIC;
  signal myRxtx_n_19 : STD_LOGIC;
  signal myRxtx_n_190 : STD_LOGIC;
  signal myRxtx_n_191 : STD_LOGIC;
  signal myRxtx_n_192 : STD_LOGIC;
  signal myRxtx_n_193 : STD_LOGIC;
  signal myRxtx_n_194 : STD_LOGIC;
  signal myRxtx_n_195 : STD_LOGIC;
  signal myRxtx_n_196 : STD_LOGIC;
  signal myRxtx_n_197 : STD_LOGIC;
  signal myRxtx_n_198 : STD_LOGIC;
  signal myRxtx_n_199 : STD_LOGIC;
  signal myRxtx_n_2 : STD_LOGIC;
  signal myRxtx_n_20 : STD_LOGIC;
  signal myRxtx_n_200 : STD_LOGIC;
  signal myRxtx_n_201 : STD_LOGIC;
  signal myRxtx_n_202 : STD_LOGIC;
  signal myRxtx_n_203 : STD_LOGIC;
  signal myRxtx_n_204 : STD_LOGIC;
  signal myRxtx_n_205 : STD_LOGIC;
  signal myRxtx_n_206 : STD_LOGIC;
  signal myRxtx_n_207 : STD_LOGIC;
  signal myRxtx_n_208 : STD_LOGIC;
  signal myRxtx_n_209 : STD_LOGIC;
  signal myRxtx_n_21 : STD_LOGIC;
  signal myRxtx_n_210 : STD_LOGIC;
  signal myRxtx_n_211 : STD_LOGIC;
  signal myRxtx_n_212 : STD_LOGIC;
  signal myRxtx_n_213 : STD_LOGIC;
  signal myRxtx_n_214 : STD_LOGIC;
  signal myRxtx_n_215 : STD_LOGIC;
  signal myRxtx_n_216 : STD_LOGIC;
  signal myRxtx_n_217 : STD_LOGIC;
  signal myRxtx_n_218 : STD_LOGIC;
  signal myRxtx_n_219 : STD_LOGIC;
  signal myRxtx_n_22 : STD_LOGIC;
  signal myRxtx_n_220 : STD_LOGIC;
  signal myRxtx_n_221 : STD_LOGIC;
  signal myRxtx_n_222 : STD_LOGIC;
  signal myRxtx_n_223 : STD_LOGIC;
  signal myRxtx_n_224 : STD_LOGIC;
  signal myRxtx_n_225 : STD_LOGIC;
  signal myRxtx_n_226 : STD_LOGIC;
  signal myRxtx_n_227 : STD_LOGIC;
  signal myRxtx_n_228 : STD_LOGIC;
  signal myRxtx_n_229 : STD_LOGIC;
  signal myRxtx_n_23 : STD_LOGIC;
  signal myRxtx_n_230 : STD_LOGIC;
  signal myRxtx_n_231 : STD_LOGIC;
  signal myRxtx_n_232 : STD_LOGIC;
  signal myRxtx_n_233 : STD_LOGIC;
  signal myRxtx_n_234 : STD_LOGIC;
  signal myRxtx_n_235 : STD_LOGIC;
  signal myRxtx_n_236 : STD_LOGIC;
  signal myRxtx_n_237 : STD_LOGIC;
  signal myRxtx_n_238 : STD_LOGIC;
  signal myRxtx_n_239 : STD_LOGIC;
  signal myRxtx_n_24 : STD_LOGIC;
  signal myRxtx_n_240 : STD_LOGIC;
  signal myRxtx_n_241 : STD_LOGIC;
  signal myRxtx_n_242 : STD_LOGIC;
  signal myRxtx_n_243 : STD_LOGIC;
  signal myRxtx_n_244 : STD_LOGIC;
  signal myRxtx_n_245 : STD_LOGIC;
  signal myRxtx_n_246 : STD_LOGIC;
  signal myRxtx_n_247 : STD_LOGIC;
  signal myRxtx_n_248 : STD_LOGIC;
  signal myRxtx_n_249 : STD_LOGIC;
  signal myRxtx_n_25 : STD_LOGIC;
  signal myRxtx_n_250 : STD_LOGIC;
  signal myRxtx_n_251 : STD_LOGIC;
  signal myRxtx_n_252 : STD_LOGIC;
  signal myRxtx_n_253 : STD_LOGIC;
  signal myRxtx_n_254 : STD_LOGIC;
  signal myRxtx_n_255 : STD_LOGIC;
  signal myRxtx_n_256 : STD_LOGIC;
  signal myRxtx_n_257 : STD_LOGIC;
  signal myRxtx_n_258 : STD_LOGIC;
  signal myRxtx_n_259 : STD_LOGIC;
  signal myRxtx_n_26 : STD_LOGIC;
  signal myRxtx_n_260 : STD_LOGIC;
  signal myRxtx_n_261 : STD_LOGIC;
  signal myRxtx_n_262 : STD_LOGIC;
  signal myRxtx_n_263 : STD_LOGIC;
  signal myRxtx_n_264 : STD_LOGIC;
  signal myRxtx_n_265 : STD_LOGIC;
  signal myRxtx_n_266 : STD_LOGIC;
  signal myRxtx_n_267 : STD_LOGIC;
  signal myRxtx_n_268 : STD_LOGIC;
  signal myRxtx_n_269 : STD_LOGIC;
  signal myRxtx_n_27 : STD_LOGIC;
  signal myRxtx_n_270 : STD_LOGIC;
  signal myRxtx_n_271 : STD_LOGIC;
  signal myRxtx_n_272 : STD_LOGIC;
  signal myRxtx_n_273 : STD_LOGIC;
  signal myRxtx_n_274 : STD_LOGIC;
  signal myRxtx_n_275 : STD_LOGIC;
  signal myRxtx_n_276 : STD_LOGIC;
  signal myRxtx_n_277 : STD_LOGIC;
  signal myRxtx_n_278 : STD_LOGIC;
  signal myRxtx_n_279 : STD_LOGIC;
  signal myRxtx_n_28 : STD_LOGIC;
  signal myRxtx_n_280 : STD_LOGIC;
  signal myRxtx_n_281 : STD_LOGIC;
  signal myRxtx_n_282 : STD_LOGIC;
  signal myRxtx_n_283 : STD_LOGIC;
  signal myRxtx_n_284 : STD_LOGIC;
  signal myRxtx_n_285 : STD_LOGIC;
  signal myRxtx_n_286 : STD_LOGIC;
  signal myRxtx_n_287 : STD_LOGIC;
  signal myRxtx_n_288 : STD_LOGIC;
  signal myRxtx_n_289 : STD_LOGIC;
  signal myRxtx_n_29 : STD_LOGIC;
  signal myRxtx_n_290 : STD_LOGIC;
  signal myRxtx_n_291 : STD_LOGIC;
  signal myRxtx_n_292 : STD_LOGIC;
  signal myRxtx_n_293 : STD_LOGIC;
  signal myRxtx_n_294 : STD_LOGIC;
  signal myRxtx_n_295 : STD_LOGIC;
  signal myRxtx_n_296 : STD_LOGIC;
  signal myRxtx_n_297 : STD_LOGIC;
  signal myRxtx_n_298 : STD_LOGIC;
  signal myRxtx_n_299 : STD_LOGIC;
  signal myRxtx_n_3 : STD_LOGIC;
  signal myRxtx_n_30 : STD_LOGIC;
  signal myRxtx_n_300 : STD_LOGIC;
  signal myRxtx_n_301 : STD_LOGIC;
  signal myRxtx_n_302 : STD_LOGIC;
  signal myRxtx_n_303 : STD_LOGIC;
  signal myRxtx_n_304 : STD_LOGIC;
  signal myRxtx_n_305 : STD_LOGIC;
  signal myRxtx_n_306 : STD_LOGIC;
  signal myRxtx_n_307 : STD_LOGIC;
  signal myRxtx_n_308 : STD_LOGIC;
  signal myRxtx_n_309 : STD_LOGIC;
  signal myRxtx_n_31 : STD_LOGIC;
  signal myRxtx_n_310 : STD_LOGIC;
  signal myRxtx_n_311 : STD_LOGIC;
  signal myRxtx_n_312 : STD_LOGIC;
  signal myRxtx_n_313 : STD_LOGIC;
  signal myRxtx_n_314 : STD_LOGIC;
  signal myRxtx_n_315 : STD_LOGIC;
  signal myRxtx_n_316 : STD_LOGIC;
  signal myRxtx_n_317 : STD_LOGIC;
  signal myRxtx_n_318 : STD_LOGIC;
  signal myRxtx_n_319 : STD_LOGIC;
  signal myRxtx_n_32 : STD_LOGIC;
  signal myRxtx_n_320 : STD_LOGIC;
  signal myRxtx_n_321 : STD_LOGIC;
  signal myRxtx_n_322 : STD_LOGIC;
  signal myRxtx_n_323 : STD_LOGIC;
  signal myRxtx_n_326 : STD_LOGIC;
  signal myRxtx_n_327 : STD_LOGIC;
  signal myRxtx_n_328 : STD_LOGIC;
  signal myRxtx_n_329 : STD_LOGIC;
  signal myRxtx_n_33 : STD_LOGIC;
  signal myRxtx_n_330 : STD_LOGIC;
  signal myRxtx_n_331 : STD_LOGIC;
  signal myRxtx_n_332 : STD_LOGIC;
  signal myRxtx_n_333 : STD_LOGIC;
  signal myRxtx_n_334 : STD_LOGIC;
  signal myRxtx_n_335 : STD_LOGIC;
  signal myRxtx_n_34 : STD_LOGIC;
  signal myRxtx_n_344 : STD_LOGIC;
  signal myRxtx_n_347 : STD_LOGIC;
  signal myRxtx_n_348 : STD_LOGIC;
  signal myRxtx_n_35 : STD_LOGIC;
  signal myRxtx_n_351 : STD_LOGIC;
  signal myRxtx_n_352 : STD_LOGIC;
  signal myRxtx_n_353 : STD_LOGIC;
  signal myRxtx_n_354 : STD_LOGIC;
  signal myRxtx_n_355 : STD_LOGIC;
  signal myRxtx_n_356 : STD_LOGIC;
  signal myRxtx_n_357 : STD_LOGIC;
  signal myRxtx_n_358 : STD_LOGIC;
  signal myRxtx_n_359 : STD_LOGIC;
  signal myRxtx_n_36 : STD_LOGIC;
  signal myRxtx_n_360 : STD_LOGIC;
  signal myRxtx_n_361 : STD_LOGIC;
  signal myRxtx_n_362 : STD_LOGIC;
  signal myRxtx_n_363 : STD_LOGIC;
  signal myRxtx_n_364 : STD_LOGIC;
  signal myRxtx_n_365 : STD_LOGIC;
  signal myRxtx_n_366 : STD_LOGIC;
  signal myRxtx_n_367 : STD_LOGIC;
  signal myRxtx_n_368 : STD_LOGIC;
  signal myRxtx_n_369 : STD_LOGIC;
  signal myRxtx_n_37 : STD_LOGIC;
  signal myRxtx_n_370 : STD_LOGIC;
  signal myRxtx_n_371 : STD_LOGIC;
  signal myRxtx_n_372 : STD_LOGIC;
  signal myRxtx_n_373 : STD_LOGIC;
  signal myRxtx_n_374 : STD_LOGIC;
  signal myRxtx_n_375 : STD_LOGIC;
  signal myRxtx_n_38 : STD_LOGIC;
  signal myRxtx_n_39 : STD_LOGIC;
  signal myRxtx_n_4 : STD_LOGIC;
  signal myRxtx_n_40 : STD_LOGIC;
  signal myRxtx_n_41 : STD_LOGIC;
  signal myRxtx_n_42 : STD_LOGIC;
  signal myRxtx_n_43 : STD_LOGIC;
  signal myRxtx_n_44 : STD_LOGIC;
  signal myRxtx_n_45 : STD_LOGIC;
  signal myRxtx_n_46 : STD_LOGIC;
  signal myRxtx_n_47 : STD_LOGIC;
  signal myRxtx_n_48 : STD_LOGIC;
  signal myRxtx_n_49 : STD_LOGIC;
  signal myRxtx_n_5 : STD_LOGIC;
  signal myRxtx_n_50 : STD_LOGIC;
  signal myRxtx_n_51 : STD_LOGIC;
  signal myRxtx_n_52 : STD_LOGIC;
  signal myRxtx_n_53 : STD_LOGIC;
  signal myRxtx_n_55 : STD_LOGIC;
  signal myRxtx_n_57 : STD_LOGIC;
  signal myRxtx_n_58 : STD_LOGIC;
  signal myRxtx_n_59 : STD_LOGIC;
  signal myRxtx_n_6 : STD_LOGIC;
  signal myRxtx_n_60 : STD_LOGIC;
  signal myRxtx_n_61 : STD_LOGIC;
  signal myRxtx_n_62 : STD_LOGIC;
  signal myRxtx_n_63 : STD_LOGIC;
  signal myRxtx_n_64 : STD_LOGIC;
  signal myRxtx_n_65 : STD_LOGIC;
  signal myRxtx_n_66 : STD_LOGIC;
  signal myRxtx_n_67 : STD_LOGIC;
  signal myRxtx_n_68 : STD_LOGIC;
  signal myRxtx_n_69 : STD_LOGIC;
  signal myRxtx_n_7 : STD_LOGIC;
  signal myRxtx_n_70 : STD_LOGIC;
  signal myRxtx_n_71 : STD_LOGIC;
  signal myRxtx_n_72 : STD_LOGIC;
  signal myRxtx_n_73 : STD_LOGIC;
  signal myRxtx_n_74 : STD_LOGIC;
  signal myRxtx_n_75 : STD_LOGIC;
  signal myRxtx_n_76 : STD_LOGIC;
  signal myRxtx_n_77 : STD_LOGIC;
  signal myRxtx_n_78 : STD_LOGIC;
  signal myRxtx_n_79 : STD_LOGIC;
  signal myRxtx_n_8 : STD_LOGIC;
  signal myRxtx_n_80 : STD_LOGIC;
  signal myRxtx_n_81 : STD_LOGIC;
  signal myRxtx_n_82 : STD_LOGIC;
  signal myRxtx_n_83 : STD_LOGIC;
  signal myRxtx_n_84 : STD_LOGIC;
  signal myRxtx_n_85 : STD_LOGIC;
  signal myRxtx_n_86 : STD_LOGIC;
  signal myRxtx_n_87 : STD_LOGIC;
  signal myRxtx_n_88 : STD_LOGIC;
  signal myRxtx_n_89 : STD_LOGIC;
  signal myRxtx_n_90 : STD_LOGIC;
  signal myRxtx_n_91 : STD_LOGIC;
  signal myWordto_n_0 : STD_LOGIC;
  signal myWordto_n_1 : STD_LOGIC;
  signal myWordto_n_2 : STD_LOGIC;
  signal myXferto_n_0 : STD_LOGIC;
  signal myXferto_n_1 : STD_LOGIC;
  signal \opbuf[0]1\ : STD_LOGIC;
  signal \opbuf[1][7]_i_10_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_11_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_12_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_13_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_14_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_15_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_16_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_18_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_19_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_20_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_21_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_22_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_24_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_25_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_26_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_27_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_28_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_29_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_30_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_31_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_32_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_33_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_34_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_35_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_36_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_37_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_38_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_39_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_3_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_40_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_43_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_44_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_45_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_46_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_47_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_48_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_49_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_4_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_50_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_51_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_52_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_53_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_5_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_6_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_7_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_8_n_0\ : STD_LOGIC;
  signal \opbuf[1][7]_i_9_n_0\ : STD_LOGIC;
  signal \opbuf[1]_56\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \opbuf[6][7]_i_10_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_11_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_13_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_14_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_15_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_17_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_18_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_19_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_20_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_21_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_22_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_23_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_24_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_25_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_26_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_27_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_28_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_29_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_30_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_31_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_32_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_33_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_35_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_36_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_37_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_38_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_39_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_3_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_40_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_41_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_42_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_4_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_5_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_6_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_7_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_8_n_0\ : STD_LOGIC;
  signal \opbuf[6][7]_i_9_n_0\ : STD_LOGIC;
  signal \opbuf_reg[0]3\ : STD_LOGIC_VECTOR ( 27 downto 3 );
  signal \opbuf_reg[0]5\ : STD_LOGIC_VECTOR ( 30 downto 5 );
  signal \opbuf_reg[0]51_in\ : STD_LOGIC_VECTOR ( 30 downto 5 );
  signal \opbuf_reg[1][7]_i_17_n_0\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_17_n_1\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_17_n_2\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_17_n_3\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_17_n_4\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_17_n_5\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_17_n_6\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_17_n_7\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_23_n_6\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_41_n_0\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_41_n_1\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_41_n_2\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_41_n_3\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_41_n_4\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_41_n_5\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_41_n_6\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_41_n_7\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_42_n_6\ : STD_LOGIC;
  signal \opbuf_reg[1][7]_i_42_n_7\ : STD_LOGIC;
  signal \opbuf_reg[1]_45\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \opbuf_reg[5]_47\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \opbuf_reg[6][7]_i_12_n_0\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_12_n_1\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_12_n_2\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_12_n_3\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_12_n_4\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_12_n_5\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_12_n_6\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_12_n_7\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_16_n_0\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_16_n_1\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_16_n_2\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_16_n_3\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_16_n_4\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_16_n_5\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_16_n_6\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_16_n_7\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_34_n_0\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_34_n_1\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_34_n_2\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_34_n_3\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_34_n_4\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_34_n_5\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_34_n_6\ : STD_LOGIC;
  signal \opbuf_reg[6][7]_i_34_n_7\ : STD_LOGIC;
  signal \opbuf_reg[6]_46\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \opbuf_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[0][3]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[0][4]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[0][5]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[0][6]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[0][7]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][0]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][1]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][2]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][3]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][4]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][5]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][6]\ : STD_LOGIC;
  signal \opbuf_reg_n_0_[2][7]\ : STD_LOGIC;
  signal p_10_out : STD_LOGIC_VECTOR ( 0 to 0 );
  signal p_24_in : STD_LOGIC;
  signal \pollbuf[3]_55\ : STD_LOGIC;
  signal \pollbuf[5]_54\ : STD_LOGIC;
  signal \pollbuf_reg[0]_49\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \pollbuf_reg[1]_50\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \pollbuf_reg[3]_51\ : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \pollbuf_reg[4]_52\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \pollbuf_reg[5]_53\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal recvAXIS_tlast : STD_LOGIC;
  signal reqInvRpuifToRotarySet : STD_LOGIC;
  signal \resid[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \resid_reg_n_0_[0]\ : STD_LOGIC;
  signal \resid_reg_n_0_[1]\ : STD_LOGIC;
  signal \retbuf[0][4]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[0][6]_i_2_n_0\ : STD_LOGIC;
  signal \retbuf[0][6]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_3__0_n_0\ : STD_LOGIC;
  signal \retbuf[0][7]_i_4__0_n_0\ : STD_LOGIC;
  signal \retbuf[1][7]_i_3__0_n_0\ : STD_LOGIC;
  signal \retbuf[2][7]_i_3__0_n_0\ : STD_LOGIC;
  signal \retbuf[2][7]_i_4_n_0\ : STD_LOGIC;
  signal \retbuf[2][7]_i_5__0_n_0\ : STD_LOGIC;
  signal \retbuf[2][7]_i_6__0_n_0\ : STD_LOGIC;
  signal \retbuf[33][7]_i_3__0_n_0\ : STD_LOGIC;
  signal \retbuf[36][7]_i_3__0_n_0\ : STD_LOGIC;
  signal \retbuf[37][7]_i_3__0_n_0\ : STD_LOGIC;
  signal \retbuf[39][7]_i_2__0_n_0\ : STD_LOGIC;
  signal \retbuf[4][7]_i_3__0_n_0\ : STD_LOGIC;
  signal \retbuf[5][7]_i_3__0_n_0\ : STD_LOGIC;
  signal \retbuf[8][5]_i_2__0_n_0\ : STD_LOGIC;
  signal \retbuf[8][7]_i_3_n_0\ : STD_LOGIC;
  signal \retbuf_reg[7]_48\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \retbuf_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[0][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[11][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[14][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[15][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[15][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[15][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[1][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[23][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[2][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[31][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[32][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[33][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[35][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[36][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[37][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[38][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[39][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[3][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[4][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[5][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[6][7]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][0]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][1]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][2]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][3]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][4]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][5]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][6]\ : STD_LOGIC;
  signal \retbuf_reg_n_0_[8][7]\ : STD_LOGIC;
  signal rxAXIS_tdata : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal rxAXIS_tvalid : STD_LOGIC;
  signal rxlen : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \rxlen[1]_i_3_n_0\ : STD_LOGIC;
  signal \stateOp[0]_i_5__0_n_0\ : STD_LOGIC;
  signal \stateOp[0]_i_7__0_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_3__3_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_4__4_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_4__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_6__0_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_5__0_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_6__0_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_7__0_n_0\ : STD_LOGIC;
  signal \stateOp[3]_i_9_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_12_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_13_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_14_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_15_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_16_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_17_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_18_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_20_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_21_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_22_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_23_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_24_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_25_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_26_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_27_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_3_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_6__0_n_0\ : STD_LOGIC;
  signal \stateOp[4]_i_9_n_0\ : STD_LOGIC;
  signal stateOp_next : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \stateOp_next[0]_i_2_n_0\ : STD_LOGIC;
  signal \stateOp_next[2]_i_2_n_0\ : STD_LOGIC;
  signal \stateOp_next[2]_i_3_n_0\ : STD_LOGIC;
  signal \stateOp_next[2]_i_4_n_0\ : STD_LOGIC;
  signal \stateOp_next[2]_i_5_n_0\ : STD_LOGIC;
  signal \stateOp_next[2]_i_6_n_0\ : STD_LOGIC;
  signal \stateOp_next[2]_i_7_n_0\ : STD_LOGIC;
  signal \stateOp_next[2]_i_8_n_0\ : STD_LOGIC;
  signal \stateOp_next[2]_i_9_n_0\ : STD_LOGIC;
  signal \stateOp_next[3]_i_2_n_0\ : STD_LOGIC;
  signal \stateOp_next[3]_i_3_n_0\ : STD_LOGIC;
  signal \stateOp_next[3]_i_4_n_0\ : STD_LOGIC;
  signal \stateOp_next[3]_i_5_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_5__0_n_0\ : STD_LOGIC;
  signal \stateOp_next[4]_i_6__0_n_0\ : STD_LOGIC;
  signal \stateOp_reg[4]_i_11_n_0\ : STD_LOGIC;
  signal \stateOp_reg[4]_i_11_n_1\ : STD_LOGIC;
  signal \stateOp_reg[4]_i_11_n_2\ : STD_LOGIC;
  signal \stateOp_reg[4]_i_11_n_3\ : STD_LOGIC;
  signal \stateOp_reg[4]_i_11_n_4\ : STD_LOGIC;
  signal \stateOp_reg[4]_i_11_n_5\ : STD_LOGIC;
  signal \stateOp_reg[4]_i_11_n_6\ : STD_LOGIC;
  signal \stateOp_reg[4]_i_11_n_7\ : STD_LOGIC;
  signal \stateOp_reg[4]_i_5_n_5\ : STD_LOGIC;
  signal \stateOp_reg[4]_i_5_n_6\ : STD_LOGIC;
  signal \stateOp_reg[4]_i_5_n_7\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[0]\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[1]\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[2]\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[3]\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[4]\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[5]\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[6]\ : STD_LOGIC;
  signal \tixVBuffer_reg_n_0_[7]\ : STD_LOGIC;
  signal tixVBufxfop : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal tixVCommand : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[0]\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[1]\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[2]\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[3]\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[4]\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[5]\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[6]\ : STD_LOGIC;
  signal \tixVCommand_reg_n_0_[7]\ : STD_LOGIC;
  signal \tixVController[7]_i_4__0_n_0\ : STD_LOGIC;
  signal \tixVController[7]_i_5__0_n_0\ : STD_LOGIC;
  signal \tixVController[7]_i_6__0_n_0\ : STD_LOGIC;
  signal \tixVController[7]_i_7_n_0\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[0]\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[1]\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[2]\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[3]\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[4]\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[5]\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[6]\ : STD_LOGIC;
  signal \tixVController_reg_n_0_[7]\ : STD_LOGIC;
  signal \txAXIS_tdata[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[0]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[10]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[10]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[10]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[11]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[11]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[11]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[11]_i_7__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[12]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[12]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[12]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[12]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[13]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[13]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[13]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[14]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[14]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[14]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[14]_i_7__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[15]_i_7__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[16]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[16]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[16]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[16]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[17]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[17]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[17]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[18]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[18]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[18]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[18]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[19]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[19]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[1]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[1]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[1]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[1]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[20]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[20]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[20]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[21]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[21]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[22]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[22]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[23]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[23]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[23]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[24]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[24]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[24]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[25]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[25]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[25]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[25]_i_7__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[26]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[26]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[26]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[27]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[27]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[27]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[27]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[28]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[28]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[28]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[29]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[29]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[29]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[2]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[2]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[30]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[30]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[30]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_10__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_11_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_13_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_14_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_15_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_16_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_17_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_18_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_19_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_20_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_7__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[31]_i_9__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[3]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[3]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[4]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[4]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[5]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[5]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[5]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[5]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_6_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_7_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[6]_i_8__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_10_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_7__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_8__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[7]_i_9_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[8]_i_3__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[8]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[8]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[8]_i_7__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[9]_i_2__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[9]_i_5__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[9]_i_6__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata[9]_i_7__0_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[11]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[13]_i_4_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[14]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[15]_i_5_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[24]_i_2_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[25]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[31]_i_12_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[31]_i_12_n_1\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[31]_i_12_n_2\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[31]_i_12_n_3\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[31]_i_12_n_4\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[31]_i_12_n_5\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[31]_i_12_n_6\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[31]_i_12_n_7\ : STD_LOGIC;
  signal \txAXIS_tdata_reg[9]_i_3_n_0\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[0]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[10]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[11]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[12]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[13]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[14]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[15]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[16]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[17]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[18]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[19]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[1]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[20]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[21]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[22]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[23]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[24]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[25]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[26]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[27]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[28]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[29]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[2]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[30]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[31]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[3]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[4]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[5]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[6]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[7]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[8]\ : STD_LOGIC;
  signal \txAXIS_tdata_reg_n_0_[9]\ : STD_LOGIC;
  signal txlast1 : STD_LOGIC_VECTOR ( 30 downto 1 );
  signal \txlen_reg_n_0_[0]\ : STD_LOGIC;
  signal \txlen_reg_n_0_[1]\ : STD_LOGIC;
  signal \txlen_reg_n_0_[3]\ : STD_LOGIC;
  signal wordcntCrcLast : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal wordcntLast : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \wordcntLast[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \wordcntLast[1]_i_2_n_0\ : STD_LOGIC;
  signal \wordcntLast_reg_n_0_[0]\ : STD_LOGIC;
  signal \wordcntLast_reg_n_0_[1]\ : STD_LOGIC;
  signal \wordcntLast_reg_n_0_[3]\ : STD_LOGIC;
  signal \wordcnt[30]_i_4_n_0\ : STD_LOGIC;
  signal \wordcnt[30]_i_7__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2__0_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2__0_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2__0_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2__0_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2__0_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2__0_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[16]_i_2__0_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2__0_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2__0_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2__0_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2__0_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2__0_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2__0_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[24]_i_2__0_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[30]_i_6_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[30]_i_6_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[30]_i_6_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[30]_i_6_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[30]_i_6_n_7\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2__0_n_1\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2__0_n_2\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2__0_n_3\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2__0_n_4\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2__0_n_5\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2__0_n_6\ : STD_LOGIC;
  signal \wordcnt_reg[8]_i_2__0_n_7\ : STD_LOGIC;
  signal \wordcnt_reg_n_0_[26]\ : STD_LOGIC;
  signal \wordcnt_reg_n_0_[27]\ : STD_LOGIC;
  signal \wordcnt_reg_n_0_[28]\ : STD_LOGIC;
  signal \wordcnt_reg_n_0_[29]\ : STD_LOGIC;
  signal \wordcnt_reg_n_0_[30]\ : STD_LOGIC;
  signal \NLW_crcAXIS_tkeep_reg[3]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_crcAXIS_tkeep_reg[3]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_crcAXIS_tkeep_reg[3]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_crcAXIS_tkeep_reg[3]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_crcAXIS_tkeep_reg[3]_i_19_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_crcAXIS_tkeep_reg[3]_i_23_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_crcAXIS_tkeep_reg[3]_i_46_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_crcAXIS_tkeep_reg[3]_i_46_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_opbuf_reg[1][7]_i_23_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_opbuf_reg[1][7]_i_23_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_opbuf_reg[1][7]_i_42_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_opbuf_reg[1][7]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_stateOp_reg[4]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateOp_reg[4]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_stateOp_reg[4]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_txAXIS_tdata_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_wordcnt_reg[30]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_wordcnt_reg[30]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \crcAXIS_tkeep[3]_i_13\ : label is "soft_lutpair2847";
  attribute SOFT_HLUTNM of \crcAXIS_tkeep[3]_i_14\ : label is "soft_lutpair2846";
  attribute SOFT_HLUTNM of \crcAXIS_tkeep[3]_i_15\ : label is "soft_lutpair2849";
  attribute SOFT_HLUTNM of \crcAXIS_tkeep[3]_i_16\ : label is "soft_lutpair2848";
  attribute SOFT_HLUTNM of \crcAXIS_tkeep[3]_i_27\ : label is "soft_lutpair2861";
  attribute SOFT_HLUTNM of \crcAXIS_tlast_sig_i_10__0\ : label is "soft_lutpair2827";
  attribute SOFT_HLUTNM of \crcAXIS_tlast_sig_i_6__0\ : label is "soft_lutpair2829";
  attribute SOFT_HLUTNM of \crcAXIS_tlast_sig_i_7__0\ : label is "soft_lutpair2836";
  attribute SOFT_HLUTNM of \ixRetbufCrc[2]_i_2\ : label is "soft_lutpair2831";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_11\ : label is "soft_lutpair2841";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_12\ : label is "soft_lutpair2868";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_13\ : label is "soft_lutpair2868";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_14\ : label is "soft_lutpair2867";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_15\ : label is "soft_lutpair2848";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_18\ : label is "soft_lutpair2841";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_19\ : label is "soft_lutpair2862";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_20\ : label is "soft_lutpair2863";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_21\ : label is "soft_lutpair2862";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_22\ : label is "soft_lutpair2861";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_24\ : label is "soft_lutpair2865";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_25\ : label is "soft_lutpair2865";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_26\ : label is "soft_lutpair2849";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_27\ : label is "soft_lutpair2864";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_28\ : label is "soft_lutpair2866";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_4\ : label is "soft_lutpair2845";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_40\ : label is "soft_lutpair2864";
  attribute SOFT_HLUTNM of \opbuf[1][7]_i_6\ : label is "soft_lutpair2869";
  attribute SOFT_HLUTNM of \opbuf[6][7]_i_11\ : label is "soft_lutpair2863";
  attribute SOFT_HLUTNM of \opbuf[6][7]_i_13\ : label is "soft_lutpair2866";
  attribute SOFT_HLUTNM of \opbuf[6][7]_i_14\ : label is "soft_lutpair2867";
  attribute SOFT_HLUTNM of \opbuf[6][7]_i_15\ : label is "soft_lutpair2847";
  attribute SOFT_HLUTNM of \opbuf[6][7]_i_17\ : label is "soft_lutpair2846";
  attribute SOFT_HLUTNM of \opbuf[6][7]_i_3\ : label is "soft_lutpair2851";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \opbuf_reg[1][7]_i_41\ : label is 35;
  attribute ADDER_THRESHOLD of \opbuf_reg[1][7]_i_42\ : label is 35;
  attribute ADDER_THRESHOLD of \opbuf_reg[6][7]_i_34\ : label is 35;
  attribute SOFT_HLUTNM of \resid[0]_i_2__0\ : label is "soft_lutpair2836";
  attribute SOFT_HLUTNM of \retbuf[0][4]_i_2\ : label is "soft_lutpair2831";
  attribute SOFT_HLUTNM of \retbuf[0][6]_i_2\ : label is "soft_lutpair2872";
  attribute SOFT_HLUTNM of \retbuf[0][7]_i_4__0\ : label is "soft_lutpair2827";
  attribute SOFT_HLUTNM of \retbuf[1][7]_i_3__0\ : label is "soft_lutpair2837";
  attribute SOFT_HLUTNM of \retbuf[2][7]_i_4\ : label is "soft_lutpair2832";
  attribute SOFT_HLUTNM of \retbuf[2][7]_i_5__0\ : label is "soft_lutpair2842";
  attribute SOFT_HLUTNM of \retbuf[2][7]_i_6__0\ : label is "soft_lutpair2850";
  attribute SOFT_HLUTNM of \retbuf[33][7]_i_3__0\ : label is "soft_lutpair2852";
  attribute SOFT_HLUTNM of \retbuf[36][7]_i_3__0\ : label is "soft_lutpair2839";
  attribute SOFT_HLUTNM of \retbuf[37][7]_i_3__0\ : label is "soft_lutpair2839";
  attribute SOFT_HLUTNM of \retbuf[4][7]_i_3__0\ : label is "soft_lutpair2838";
  attribute SOFT_HLUTNM of \retbuf[5][7]_i_3__0\ : label is "soft_lutpair2837";
  attribute SOFT_HLUTNM of \retbuf[8][5]_i_2__0\ : label is "soft_lutpair2852";
  attribute SOFT_HLUTNM of \retbuf[8][7]_i_3\ : label is "soft_lutpair2838";
  attribute SOFT_HLUTNM of \rxlen[1]_i_3\ : label is "soft_lutpair2834";
  attribute SOFT_HLUTNM of \stateOp[0]_i_5__0\ : label is "soft_lutpair2828";
  attribute SOFT_HLUTNM of \stateOp[0]_i_7__0\ : label is "soft_lutpair2828";
  attribute SOFT_HLUTNM of \stateOp[3]_i_5__0\ : label is "soft_lutpair2870";
  attribute SOFT_HLUTNM of \stateOp[3]_i_6__0\ : label is "soft_lutpair2845";
  attribute SOFT_HLUTNM of \stateOp[3]_i_9\ : label is "soft_lutpair2844";
  attribute SOFT_HLUTNM of \stateOp[4]_i_15\ : label is "soft_lutpair2834";
  attribute SOFT_HLUTNM of \stateOp[4]_i_16\ : label is "soft_lutpair2832";
  attribute SOFT_HLUTNM of \stateOp[4]_i_17\ : label is "soft_lutpair2833";
  attribute SOFT_HLUTNM of \stateOp[4]_i_3\ : label is "soft_lutpair2835";
  attribute SOFT_HLUTNM of \stateOp[4]_i_4__0\ : label is "soft_lutpair2829";
  attribute SOFT_HLUTNM of \stateOp_next[3]_i_4\ : label is "soft_lutpair2843";
  attribute SOFT_HLUTNM of \stateOp_next[3]_i_5\ : label is "soft_lutpair2833";
  attribute SOFT_HLUTNM of \stateOp_next[4]_i_4__0\ : label is "soft_lutpair2842";
  attribute SOFT_HLUTNM of \stateOp_next[4]_i_5__0\ : label is "soft_lutpair2843";
  attribute SOFT_HLUTNM of \txAXIS_tdata[11]_i_2__0\ : label is "soft_lutpair2855";
  attribute SOFT_HLUTNM of \txAXIS_tdata[11]_i_7__0\ : label is "soft_lutpair2855";
  attribute SOFT_HLUTNM of \txAXIS_tdata[12]_i_2__0\ : label is "soft_lutpair2856";
  attribute SOFT_HLUTNM of \txAXIS_tdata[12]_i_5__0\ : label is "soft_lutpair2856";
  attribute SOFT_HLUTNM of \txAXIS_tdata[13]_i_3__0\ : label is "soft_lutpair2857";
  attribute SOFT_HLUTNM of \txAXIS_tdata[14]_i_2__0\ : label is "soft_lutpair2857";
  attribute SOFT_HLUTNM of \txAXIS_tdata[14]_i_7__0\ : label is "soft_lutpair2858";
  attribute SOFT_HLUTNM of \txAXIS_tdata[15]_i_4__0\ : label is "soft_lutpair2858";
  attribute SOFT_HLUTNM of \txAXIS_tdata[16]_i_5__0\ : label is "soft_lutpair2859";
  attribute SOFT_HLUTNM of \txAXIS_tdata[18]_i_4__0\ : label is "soft_lutpair2840";
  attribute SOFT_HLUTNM of \txAXIS_tdata[1]_i_6\ : label is "soft_lutpair2853";
  attribute SOFT_HLUTNM of \txAXIS_tdata[20]_i_5__0\ : label is "soft_lutpair2859";
  attribute SOFT_HLUTNM of \txAXIS_tdata[23]_i_5__0\ : label is "soft_lutpair2872";
  attribute SOFT_HLUTNM of \txAXIS_tdata[25]_i_2__0\ : label is "soft_lutpair2860";
  attribute SOFT_HLUTNM of \txAXIS_tdata[26]_i_4__0\ : label is "soft_lutpair2840";
  attribute SOFT_HLUTNM of \txAXIS_tdata[27]_i_6__0\ : label is "soft_lutpair2860";
  attribute SOFT_HLUTNM of \txAXIS_tdata[31]_i_13\ : label is "soft_lutpair2869";
  attribute SOFT_HLUTNM of \txAXIS_tdata[31]_i_3__0\ : label is "soft_lutpair2830";
  attribute SOFT_HLUTNM of \txAXIS_tdata[31]_i_7__0\ : label is "soft_lutpair2871";
  attribute SOFT_HLUTNM of \txAXIS_tdata[6]_i_2__0\ : label is "soft_lutpair2870";
  attribute SOFT_HLUTNM of \txAXIS_tdata[6]_i_5__0\ : label is "soft_lutpair2830";
  attribute SOFT_HLUTNM of \txAXIS_tdata[7]_i_10\ : label is "soft_lutpair2844";
  attribute SOFT_HLUTNM of \txAXIS_tdata[8]_i_2__0\ : label is "soft_lutpair2853";
  attribute SOFT_HLUTNM of \txAXIS_tdata[8]_i_5__0\ : label is "soft_lutpair2854";
  attribute SOFT_HLUTNM of \txAXIS_tdata[9]_i_2__0\ : label is "soft_lutpair2854";
  attribute ADDER_THRESHOLD of \txAXIS_tdata_reg[31]_i_12\ : label is 35;
  attribute SOFT_HLUTNM of \wordcntLast[0]_i_2__0\ : label is "soft_lutpair2835";
  attribute SOFT_HLUTNM of \wordcntLast[1]_i_2\ : label is "soft_lutpair2871";
  attribute SOFT_HLUTNM of \wordcnt[30]_i_4\ : label is "soft_lutpair2850";
  attribute SOFT_HLUTNM of \wordcnt[30]_i_7__0\ : label is "soft_lutpair2851";
  attribute ADDER_THRESHOLD of \wordcnt_reg[16]_i_2__0\ : label is 35;
  attribute ADDER_THRESHOLD of \wordcnt_reg[24]_i_2__0\ : label is 35;
  attribute ADDER_THRESHOLD of \wordcnt_reg[30]_i_6\ : label is 35;
  attribute ADDER_THRESHOLD of \wordcnt_reg[8]_i_2__0\ : label is 35;
begin
  Q(4 downto 0) <= \^q\(4 downto 0);
\capt[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => reqInvRpuifToRotarySet,
      I1 => \capt_reg[4]\,
      O => \mask_reg[4]\(0)
    );
\capt[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(4),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \stateOp_next[3]_i_2_n_0\,
      O => reqInvRpuifToRotarySet
    );
\crcAXIS_tkeep[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEFFFFFFFFFFFAFF"
    )
        port map (
      I0 => \^q\(4),
      I1 => \stateOp_reg[4]_i_5_n_5\,
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \^q\(0),
      I5 => \^q\(1),
      O => \crcAXIS_tkeep[0]_i_2_n_0\
    );
\crcAXIS_tkeep[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF7F7F7FCF3F0F3"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \stateOp_reg[4]_i_5_n_5\,
      I5 => \^q\(2),
      O => \crcAXIS_tkeep[1]_i_2_n_0\
    );
\crcAXIS_tkeep[3]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAD8AFDFAFFFFAF5"
    )
        port map (
      I0 => \^q\(3),
      I1 => \stateOp_reg[4]_i_5_n_5\,
      I2 => \^q\(2),
      I3 => \^q\(4),
      I4 => \^q\(1),
      I5 => \^q\(0),
      O => \crcAXIS_tkeep[3]_i_12_n_0\
    );
\crcAXIS_tkeep[3]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(17),
      I1 => \opbuf_reg[0]51_in\(19),
      I2 => \opbuf_reg[0]51_in\(18),
      O => \crcAXIS_tkeep[3]_i_13_n_0\
    );
\crcAXIS_tkeep[3]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(26),
      I1 => \opbuf_reg[0]51_in\(28),
      I2 => \opbuf_reg[0]51_in\(27),
      O => \crcAXIS_tkeep[3]_i_14_n_0\
    );
\crcAXIS_tkeep[3]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(20),
      I1 => \opbuf_reg[0]51_in\(22),
      I2 => \opbuf_reg[0]51_in\(21),
      O => \crcAXIS_tkeep[3]_i_15_n_0\
    );
\crcAXIS_tkeep[3]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(14),
      I1 => \opbuf_reg[0]51_in\(16),
      I2 => \opbuf_reg[0]51_in\(15),
      O => \crcAXIS_tkeep[3]_i_16_n_0\
    );
\crcAXIS_tkeep[3]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[27]\,
      I1 => \wordcnt_reg_n_0_[29]\,
      I2 => \wordcnt_reg_n_0_[28]\,
      I3 => \opbuf_reg[0]51_in\(29),
      I4 => \crcAXIS_tkeep[3]_i_27_n_0\,
      I5 => \crcAXIS_tkeep[3]_i_28_n_0\,
      O => \crcAXIS_tkeep[3]_i_17_n_0\
    );
\crcAXIS_tkeep[3]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(5),
      I1 => \opbuf_reg[0]51_in\(7),
      I2 => \wordcnt_reg_n_0_[30]\,
      I3 => \opbuf_reg[0]51_in\(6),
      I4 => \opbuf_reg[0]51_in\(8),
      I5 => \crcAXIS_tkeep[3]_i_29_n_0\,
      O => \crcAXIS_tkeep[3]_i_18_n_0\
    );
\crcAXIS_tkeep[3]_i_20\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[30]\,
      O => \crcAXIS_tkeep[3]_i_20_n_0\
    );
\crcAXIS_tkeep[3]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[28]\,
      I1 => \wordcnt_reg_n_0_[29]\,
      I2 => \wordcnt_reg_n_0_[27]\,
      O => \crcAXIS_tkeep[3]_i_21_n_0\
    );
\crcAXIS_tkeep[3]_i_22\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1001"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[26]\,
      I1 => \opbuf_reg[0]51_in\(30),
      I2 => wordcntCrcLast(24),
      I3 => \opbuf_reg[0]51_in\(29),
      O => \crcAXIS_tkeep[3]_i_22_n_0\
    );
\crcAXIS_tkeep[3]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[3]_i_46_n_5\,
      I1 => \wordcnt_reg_n_0_[30]\,
      O => \crcAXIS_tkeep[3]_i_24_n_0\
    );
\crcAXIS_tkeep[3]_i_25\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2004"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[27]\,
      I1 => \crcAXIS_tkeep_reg[3]_i_46_n_5\,
      I2 => \wordcnt_reg_n_0_[28]\,
      I3 => \wordcnt_reg_n_0_[29]\,
      O => \crcAXIS_tkeep[3]_i_25_n_0\
    );
\crcAXIS_tkeep[3]_i_26\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0810"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(30),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \crcAXIS_tkeep_reg[3]_i_46_n_5\,
      I3 => \opbuf_reg[0]51_in\(29),
      O => \crcAXIS_tkeep[3]_i_26_n_0\
    );
\crcAXIS_tkeep[3]_i_27\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(30),
      I1 => \wordcnt_reg_n_0_[26]\,
      O => \crcAXIS_tkeep[3]_i_27_n_0\
    );
\crcAXIS_tkeep[3]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(12),
      I1 => \opbuf_reg[0]51_in\(13),
      I2 => \opbuf_reg[0]51_in\(11),
      I3 => \opbuf_reg[0]51_in\(24),
      I4 => \opbuf_reg[0]51_in\(25),
      I5 => \opbuf_reg[0]51_in\(23),
      O => \crcAXIS_tkeep[3]_i_28_n_0\
    );
\crcAXIS_tkeep[3]_i_29\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(9),
      I1 => \opbuf_reg[0]51_in\(10),
      O => \crcAXIS_tkeep[3]_i_29_n_0\
    );
\crcAXIS_tkeep[3]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntCrcLast(23),
      I1 => \opbuf_reg[0]51_in\(28),
      I2 => \opbuf_reg[0]51_in\(26),
      I3 => wordcntCrcLast(21),
      I4 => \opbuf_reg[0]51_in\(27),
      I5 => wordcntCrcLast(22),
      O => \crcAXIS_tkeep[3]_i_30_n_0\
    );
\crcAXIS_tkeep[3]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntCrcLast(20),
      I1 => \opbuf_reg[0]51_in\(25),
      I2 => \opbuf_reg[0]51_in\(23),
      I3 => wordcntCrcLast(18),
      I4 => \opbuf_reg[0]51_in\(24),
      I5 => wordcntCrcLast(19),
      O => \crcAXIS_tkeep[3]_i_31_n_0\
    );
\crcAXIS_tkeep[3]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntCrcLast(17),
      I1 => \opbuf_reg[0]51_in\(22),
      I2 => \opbuf_reg[0]51_in\(20),
      I3 => wordcntCrcLast(15),
      I4 => \opbuf_reg[0]51_in\(21),
      I5 => wordcntCrcLast(16),
      O => \crcAXIS_tkeep[3]_i_32_n_0\
    );
\crcAXIS_tkeep[3]_i_33\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntCrcLast(14),
      I1 => \opbuf_reg[0]51_in\(19),
      I2 => \opbuf_reg[0]51_in\(17),
      I3 => wordcntCrcLast(12),
      I4 => \opbuf_reg[0]51_in\(18),
      I5 => wordcntCrcLast(13),
      O => \crcAXIS_tkeep[3]_i_33_n_0\
    );
\crcAXIS_tkeep[3]_i_34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntCrcLast(11),
      I1 => \opbuf_reg[0]51_in\(16),
      I2 => \opbuf_reg[0]51_in\(14),
      I3 => wordcntCrcLast(9),
      I4 => \opbuf_reg[0]51_in\(15),
      I5 => wordcntCrcLast(10),
      O => \crcAXIS_tkeep[3]_i_34_n_0\
    );
\crcAXIS_tkeep[3]_i_35\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntCrcLast(8),
      I1 => \opbuf_reg[0]51_in\(13),
      I2 => \opbuf_reg[0]51_in\(11),
      I3 => wordcntCrcLast(6),
      I4 => \opbuf_reg[0]51_in\(12),
      I5 => wordcntCrcLast(7),
      O => \crcAXIS_tkeep[3]_i_35_n_0\
    );
\crcAXIS_tkeep[3]_i_36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntCrcLast(5),
      I1 => \opbuf_reg[0]51_in\(10),
      I2 => \opbuf_reg[0]51_in\(8),
      I3 => wordcntCrcLast(3),
      I4 => \opbuf_reg[0]51_in\(9),
      I5 => wordcntCrcLast(4),
      O => \crcAXIS_tkeep[3]_i_36_n_0\
    );
\crcAXIS_tkeep[3]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => wordcntCrcLast(2),
      I1 => \opbuf_reg[0]51_in\(7),
      I2 => \opbuf_reg[0]51_in\(6),
      I3 => wordcntCrcLast(1),
      I4 => \opbuf_reg[0]51_in\(5),
      I5 => wordcntCrcLast(0),
      O => \crcAXIS_tkeep[3]_i_37_n_0\
    );
\crcAXIS_tkeep[3]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4002"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[3]_i_46_n_5\,
      I1 => \opbuf_reg[0]51_in\(27),
      I2 => \opbuf_reg[0]51_in\(28),
      I3 => \opbuf_reg[0]51_in\(26),
      O => \crcAXIS_tkeep[3]_i_38_n_0\
    );
\crcAXIS_tkeep[3]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4002"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[3]_i_46_n_5\,
      I1 => \opbuf_reg[0]51_in\(24),
      I2 => \opbuf_reg[0]51_in\(25),
      I3 => \opbuf_reg[0]51_in\(23),
      O => \crcAXIS_tkeep[3]_i_39_n_0\
    );
\crcAXIS_tkeep[3]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4002"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[3]_i_46_n_5\,
      I1 => \opbuf_reg[0]51_in\(21),
      I2 => \opbuf_reg[0]51_in\(22),
      I3 => \opbuf_reg[0]51_in\(20),
      O => \crcAXIS_tkeep[3]_i_40_n_0\
    );
\crcAXIS_tkeep[3]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4002"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[3]_i_46_n_5\,
      I1 => \opbuf_reg[0]51_in\(18),
      I2 => \opbuf_reg[0]51_in\(19),
      I3 => \opbuf_reg[0]51_in\(17),
      O => \crcAXIS_tkeep[3]_i_41_n_0\
    );
\crcAXIS_tkeep[3]_i_42\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4002"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[3]_i_46_n_5\,
      I1 => \opbuf_reg[0]51_in\(15),
      I2 => \opbuf_reg[0]51_in\(16),
      I3 => \opbuf_reg[0]51_in\(14),
      O => \crcAXIS_tkeep[3]_i_42_n_0\
    );
\crcAXIS_tkeep[3]_i_43\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4002"
    )
        port map (
      I0 => \crcAXIS_tkeep_reg[3]_i_46_n_5\,
      I1 => \opbuf_reg[0]51_in\(12),
      I2 => \opbuf_reg[0]51_in\(13),
      I3 => \opbuf_reg[0]51_in\(11),
      O => \crcAXIS_tkeep[3]_i_43_n_0\
    );
\crcAXIS_tkeep[3]_i_44\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00900900"
    )
        port map (
      I0 => crcAXIS_tkeep1(3),
      I1 => \opbuf_reg[0]51_in\(8),
      I2 => \opbuf_reg[0]51_in\(9),
      I3 => \crcAXIS_tkeep_reg[3]_i_46_n_5\,
      I4 => \opbuf_reg[0]51_in\(10),
      O => \crcAXIS_tkeep[3]_i_44_n_0\
    );
\crcAXIS_tkeep[3]_i_45\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10080210"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(5),
      I1 => \opbuf_reg[0]51_in\(7),
      I2 => \wordcntLast_reg_n_0_[0]\,
      I3 => \wordcntLast_reg_n_0_[1]\,
      I4 => \opbuf_reg[0]51_in\(6),
      O => \crcAXIS_tkeep[3]_i_45_n_0\
    );
\crcAXIS_tkeep[3]_i_47\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \wordcntLast_reg_n_0_[1]\,
      I1 => \wordcntLast_reg_n_0_[0]\,
      O => \crcAXIS_tkeep[3]_i_47_n_0\
    );
\crcAXIS_tkeep[3]_i_48\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wordcntLast_reg_n_0_[3]\,
      O => \crcAXIS_tkeep[3]_i_48_n_0\
    );
\crcAXIS_tkeep[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF7FFF"
    )
        port map (
      I0 => \crcAXIS_tkeep[3]_i_13_n_0\,
      I1 => \crcAXIS_tkeep[3]_i_14_n_0\,
      I2 => \crcAXIS_tkeep[3]_i_15_n_0\,
      I3 => \crcAXIS_tkeep[3]_i_16_n_0\,
      I4 => \crcAXIS_tkeep[3]_i_17_n_0\,
      I5 => \crcAXIS_tkeep[3]_i_18_n_0\,
      O => \crcAXIS_tkeep[3]_i_7_n_0\
    );
\crcAXIS_tkeep_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_180,
      D => myRxtx_n_51,
      PRE => \stateOp_reg[0]_0\(0),
      Q => AXIS_tkeep(0)
    );
\crcAXIS_tkeep_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_180,
      D => myRxtx_n_50,
      PRE => \stateOp_reg[0]_0\(0),
      Q => AXIS_tkeep(1)
    );
\crcAXIS_tkeep_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_180,
      D => myRxtx_n_49,
      PRE => \stateOp_reg[0]_0\(0),
      Q => AXIS_tkeep(2)
    );
\crcAXIS_tkeep_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_180,
      D => myRxtx_n_48,
      PRE => \stateOp_reg[0]_0\(0),
      Q => AXIS_tkeep(3)
    );
\crcAXIS_tkeep_reg[3]_i_10\: unisim.vcomponents.CARRY8
     port map (
      CI => \crcAXIS_tkeep_reg[3]_i_19_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_crcAXIS_tkeep_reg[3]_i_10_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \crcAXIS_tkeep_reg[3]_i_10_n_5\,
      CO(1) => \crcAXIS_tkeep_reg[3]_i_10_n_6\,
      CO(0) => \crcAXIS_tkeep_reg[3]_i_10_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_crcAXIS_tkeep_reg[3]_i_10_O_UNCONNECTED\(7 downto 0),
      S(7 downto 3) => B"00000",
      S(2) => \crcAXIS_tkeep[3]_i_20_n_0\,
      S(1) => \crcAXIS_tkeep[3]_i_21_n_0\,
      S(0) => \crcAXIS_tkeep[3]_i_22_n_0\
    );
\crcAXIS_tkeep_reg[3]_i_11\: unisim.vcomponents.CARRY8
     port map (
      CI => \crcAXIS_tkeep_reg[3]_i_23_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_crcAXIS_tkeep_reg[3]_i_11_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \crcAXIS_tkeep_reg[3]_i_11_n_5\,
      CO(1) => \crcAXIS_tkeep_reg[3]_i_11_n_6\,
      CO(0) => \crcAXIS_tkeep_reg[3]_i_11_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_crcAXIS_tkeep_reg[3]_i_11_O_UNCONNECTED\(7 downto 0),
      S(7 downto 3) => B"00000",
      S(2) => \crcAXIS_tkeep[3]_i_24_n_0\,
      S(1) => \crcAXIS_tkeep[3]_i_25_n_0\,
      S(0) => \crcAXIS_tkeep[3]_i_26_n_0\
    );
\crcAXIS_tkeep_reg[3]_i_19\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \crcAXIS_tkeep_reg[3]_i_19_n_0\,
      CO(6) => \crcAXIS_tkeep_reg[3]_i_19_n_1\,
      CO(5) => \crcAXIS_tkeep_reg[3]_i_19_n_2\,
      CO(4) => \crcAXIS_tkeep_reg[3]_i_19_n_3\,
      CO(3) => \crcAXIS_tkeep_reg[3]_i_19_n_4\,
      CO(2) => \crcAXIS_tkeep_reg[3]_i_19_n_5\,
      CO(1) => \crcAXIS_tkeep_reg[3]_i_19_n_6\,
      CO(0) => \crcAXIS_tkeep_reg[3]_i_19_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_crcAXIS_tkeep_reg[3]_i_19_O_UNCONNECTED\(7 downto 0),
      S(7) => \crcAXIS_tkeep[3]_i_30_n_0\,
      S(6) => \crcAXIS_tkeep[3]_i_31_n_0\,
      S(5) => \crcAXIS_tkeep[3]_i_32_n_0\,
      S(4) => \crcAXIS_tkeep[3]_i_33_n_0\,
      S(3) => \crcAXIS_tkeep[3]_i_34_n_0\,
      S(2) => \crcAXIS_tkeep[3]_i_35_n_0\,
      S(1) => \crcAXIS_tkeep[3]_i_36_n_0\,
      S(0) => \crcAXIS_tkeep[3]_i_37_n_0\
    );
\crcAXIS_tkeep_reg[3]_i_23\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \crcAXIS_tkeep_reg[3]_i_23_n_0\,
      CO(6) => \crcAXIS_tkeep_reg[3]_i_23_n_1\,
      CO(5) => \crcAXIS_tkeep_reg[3]_i_23_n_2\,
      CO(4) => \crcAXIS_tkeep_reg[3]_i_23_n_3\,
      CO(3) => \crcAXIS_tkeep_reg[3]_i_23_n_4\,
      CO(2) => \crcAXIS_tkeep_reg[3]_i_23_n_5\,
      CO(1) => \crcAXIS_tkeep_reg[3]_i_23_n_6\,
      CO(0) => \crcAXIS_tkeep_reg[3]_i_23_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_crcAXIS_tkeep_reg[3]_i_23_O_UNCONNECTED\(7 downto 0),
      S(7) => \crcAXIS_tkeep[3]_i_38_n_0\,
      S(6) => \crcAXIS_tkeep[3]_i_39_n_0\,
      S(5) => \crcAXIS_tkeep[3]_i_40_n_0\,
      S(4) => \crcAXIS_tkeep[3]_i_41_n_0\,
      S(3) => \crcAXIS_tkeep[3]_i_42_n_0\,
      S(2) => \crcAXIS_tkeep[3]_i_43_n_0\,
      S(1) => \crcAXIS_tkeep[3]_i_44_n_0\,
      S(0) => \crcAXIS_tkeep[3]_i_45_n_0\
    );
\crcAXIS_tkeep_reg[3]_i_46\: unisim.vcomponents.CARRY8
     port map (
      CI => \crcAXIS_tkeep[3]_i_47_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_crcAXIS_tkeep_reg[3]_i_46_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \crcAXIS_tkeep_reg[3]_i_46_n_5\,
      CO(1) => \NLW_crcAXIS_tkeep_reg[3]_i_46_CO_UNCONNECTED\(1),
      CO(0) => \crcAXIS_tkeep_reg[3]_i_46_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \wordcntLast_reg_n_0_[3]\,
      DI(0) => '0',
      O(7 downto 2) => \NLW_crcAXIS_tkeep_reg[3]_i_46_O_UNCONNECTED\(7 downto 2),
      O(1) => crcAXIS_tkeep1(3),
      O(0) => \NLW_crcAXIS_tkeep_reg[3]_i_46_O_UNCONNECTED\(0),
      S(7 downto 2) => B"000001",
      S(1) => \crcAXIS_tkeep[3]_i_48_n_0\,
      S(0) => '1'
    );
\crcAXIS_tlast_sig_i_10__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00400000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \crcAXIS_tlast_sig_i_10__0_n_0\
    );
\crcAXIS_tlast_sig_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFEEFFFFFFFEF"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(3),
      I3 => \^q\(4),
      I4 => \crcAXIS_tkeep[3]_i_7_n_0\,
      I5 => \crcAXIS_tkeep_reg[3]_i_10_n_5\,
      O => \crcAXIS_tlast_sig_i_3__0_n_0\
    );
\crcAXIS_tlast_sig_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFBB6FD"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \^q\(4),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => \crcAXIS_tlast_sig_i_6__0_n_0\
    );
\crcAXIS_tlast_sig_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEDFFFEB"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(4),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      O => \crcAXIS_tlast_sig_i_7__0_n_0\
    );
crcAXIS_tlast_sig_reg: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => myRxtx_n_130,
      PRE => \stateOp_reg[0]_0\(0),
      Q => crcAXIS_tlast_sig_reg_n_0
    );
\ixRetbufCrc[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \stateOp[4]_i_17_n_0\,
      I4 => \retbuf[2][7]_i_5__0_n_0\,
      O => \ixRetbufCrc[2]_i_2_n_0\
    );
\ixRetbufCrc[5]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \stateOp[4]_i_17_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \retbuf[2][7]_i_4_n_0\,
      O => lenRet1
    );
\ixRetbufCrc_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_47,
      Q => ixRetbufCrc(1)
    );
\ixRetbufCrc_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_46,
      Q => ixRetbufCrc(2)
    );
\ixRetbufCrc_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_45,
      Q => ixRetbufCrc(5)
    );
\lastAXIS_tkeep_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_344,
      D => myRxtx_n_187,
      PRE => \stateOp_reg[0]_0\(0),
      Q => \lastAXIS_tkeep__0\(2)
    );
\lastAXIS_tkeep_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_344,
      D => myRxtx_n_186,
      PRE => \stateOp_reg[0]_0\(0),
      Q => \lastAXIS_tkeep__0\(3)
    );
\len_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_291,
      Q => \len_reg_n_0_[0]\
    );
\len_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_281,
      Q => \len_reg_n_0_[10]\
    );
\len_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_280,
      Q => \len_reg_n_0_[11]\
    );
\len_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_279,
      Q => \len_reg_n_0_[12]\
    );
\len_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_278,
      Q => \len_reg_n_0_[13]\
    );
\len_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_277,
      Q => \len_reg_n_0_[14]\
    );
\len_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_276,
      Q => \len_reg_n_0_[15]\
    );
\len_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_290,
      Q => \len_reg_n_0_[1]\
    );
\len_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_289,
      Q => \len_reg_n_0_[2]\
    );
\len_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_288,
      Q => \len_reg_n_0_[3]\
    );
\len_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_287,
      Q => \len_reg_n_0_[4]\
    );
\len_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_286,
      Q => \len_reg_n_0_[5]\
    );
\len_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_285,
      Q => \len_reg_n_0_[6]\
    );
\len_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_284,
      Q => \len_reg_n_0_[7]\
    );
\len_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_283,
      Q => \len_reg_n_0_[8]\
    );
\len_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_282,
      Q => \len_reg_n_0_[9]\
    );
myCrc: entity work.design_1_Vsp_core_0_0_Crc8005_32
     port map (
      AXIS_tdata(11 downto 10) => AXIS_tdata(30 downto 29),
      AXIS_tdata(9 downto 7) => AXIS_tdata(23 downto 21),
      AXIS_tdata(6 downto 4) => AXIS_tdata(15 downto 13),
      AXIS_tdata(3) => AXIS_tdata(6),
      AXIS_tdata(2) => AXIS_tdata(3),
      AXIS_tdata(1 downto 0) => AXIS_tdata(1 downto 0),
      AXIS_tlast => AXIS_tlast,
      AXIS_tvalid => AXIS_tvalid,
      D(7) => myCrc_n_3,
      D(6) => myCrc_n_4,
      D(5) => myCrc_n_5,
      D(4) => myCrc_n_6,
      D(3) => myCrc_n_7,
      D(2) => myCrc_n_8,
      D(1) => myCrc_n_9,
      D(0) => myCrc_n_10,
      E(0) => myCrc_n_1,
      Q(4 downto 0) => \^q\(4 downto 0),
      aclk_sig => aclk_sig,
      \crcAXIS_tkeep_reg[1]\ => myCrc_n_43,
      \crcAXIS_tkeep_reg[2]\ => myCrc_n_32,
      \crcAXIS_tkeep_reg[2]_0\ => myCrc_n_37,
      crc_imd013_out => crc_imd013_out,
      crc_imd015_out => crc_imd015_out,
      crc_imd017_out => crc_imd017_out,
      crc_imd019_out => crc_imd019_out,
      crc_imd020_out => crc_imd020_out,
      crc_imd032_out => crc_imd032_out,
      crc_imd033_out => crc_imd033_out,
      crc_imd059_out => crc_imd059_out,
      crc_imd060_out => crc_imd060_out,
      \crc_imd[15]_i_9__0\(8) => \txAXIS_tdata_reg_n_0_[15]\,
      \crc_imd[15]_i_9__0\(7) => \txAXIS_tdata_reg_n_0_[14]\,
      \crc_imd[15]_i_9__0\(6) => \txAXIS_tdata_reg_n_0_[11]\,
      \crc_imd[15]_i_9__0\(5) => \txAXIS_tdata_reg_n_0_[10]\,
      \crc_imd[15]_i_9__0\(4) => \txAXIS_tdata_reg_n_0_[8]\,
      \crc_imd[15]_i_9__0\(3) => \txAXIS_tdata_reg_n_0_[5]\,
      \crc_imd[15]_i_9__0\(2) => \txAXIS_tdata_reg_n_0_[4]\,
      \crc_imd[15]_i_9__0\(1) => \txAXIS_tdata_reg_n_0_[3]\,
      \crc_imd[15]_i_9__0\(0) => \txAXIS_tdata_reg_n_0_[0]\,
      \crc_imd[15]_i_9__0_0\(8 downto 7) => rxAXIS_tdata(15 downto 14),
      \crc_imd[15]_i_9__0_0\(6 downto 5) => rxAXIS_tdata(11 downto 10),
      \crc_imd[15]_i_9__0_0\(4) => rxAXIS_tdata(8),
      \crc_imd[15]_i_9__0_0\(3 downto 1) => rxAXIS_tdata(5 downto 3),
      \crc_imd[15]_i_9__0_0\(0) => rxAXIS_tdata(0),
      \crc_imd[1]_i_2__0_0\ => myRxtx_n_162,
      \crc_imd[1]_i_2__0_1\ => myRxtx_n_161,
      \crc_imd_reg[0]_0\ => myCrc_n_55,
      \crc_imd_reg[0]_1\ => myCrc_n_115,
      \crc_imd_reg[0]_10\ => myRxtx_n_170,
      \crc_imd_reg[0]_11\ => myRxtx_n_173,
      \crc_imd_reg[0]_2\ => myCrc_n_144,
      \crc_imd_reg[0]_3\ => myCrc_n_157,
      \crc_imd_reg[0]_4\ => myRxtx_n_138,
      \crc_imd_reg[0]_5\ => myRxtx_n_142,
      \crc_imd_reg[0]_6\ => myRxtx_n_141,
      \crc_imd_reg[0]_7\(3 downto 0) => AXIS_tkeep(3 downto 0),
      \crc_imd_reg[0]_8\ => crcAXIS_tlast_sig_reg_n_0,
      \crc_imd_reg[0]_9\ => myRxtx_n_143,
      \crc_imd_reg[10]_0\ => myRxtx_n_165,
      \crc_imd_reg[11]_0\ => myCrc_n_140,
      \crc_imd_reg[11]_1\ => myRxtx_n_171,
      \crc_imd_reg[12]_0\ => myCrc_n_42,
      \crc_imd_reg[12]_1\ => myCrc_n_168,
      \crc_imd_reg[13]_0\ => myCrc_n_48,
      \crc_imd_reg[13]_1\ => myCrc_n_139,
      \crc_imd_reg[13]_2\ => myCrc_n_160,
      \crc_imd_reg[13]_3\ => myRxtx_n_166,
      \crc_imd_reg[14]_0\ => myCrc_n_49,
      \crc_imd_reg[14]_1\(1) => myCrc_n_132,
      \crc_imd_reg[14]_1\(0) => myCrc_n_133,
      \crc_imd_reg[14]_2\ => myCrc_n_170,
      \crc_imd_reg[14]_3\ => myRxtx_n_167,
      \crc_imd_reg[15]_0\(15) => myCrc_n_11,
      \crc_imd_reg[15]_0\(14) => myCrc_n_12,
      \crc_imd_reg[15]_0\(13) => myCrc_n_13,
      \crc_imd_reg[15]_0\(12) => myCrc_n_14,
      \crc_imd_reg[15]_0\(11) => myCrc_n_15,
      \crc_imd_reg[15]_0\(10) => myCrc_n_16,
      \crc_imd_reg[15]_0\(9) => myCrc_n_17,
      \crc_imd_reg[15]_0\(8) => myCrc_n_18,
      \crc_imd_reg[15]_0\(7) => myCrc_n_19,
      \crc_imd_reg[15]_0\(6) => myCrc_n_20,
      \crc_imd_reg[15]_0\(5) => myCrc_n_21,
      \crc_imd_reg[15]_0\(4) => myCrc_n_22,
      \crc_imd_reg[15]_0\(3) => myCrc_n_23,
      \crc_imd_reg[15]_0\(2) => myCrc_n_24,
      \crc_imd_reg[15]_0\(1) => myCrc_n_25,
      \crc_imd_reg[15]_0\(0) => myCrc_n_26,
      \crc_imd_reg[15]_1\(7) => myCrc_n_83,
      \crc_imd_reg[15]_1\(6) => myCrc_n_84,
      \crc_imd_reg[15]_1\(5) => myCrc_n_85,
      \crc_imd_reg[15]_1\(4) => myCrc_n_86,
      \crc_imd_reg[15]_1\(3) => myCrc_n_87,
      \crc_imd_reg[15]_1\(2) => myCrc_n_88,
      \crc_imd_reg[15]_1\(1) => myCrc_n_89,
      \crc_imd_reg[15]_1\(0) => myCrc_n_90,
      \crc_imd_reg[15]_10\ => myRxtx_n_158,
      \crc_imd_reg[15]_11\ => myRxtx_n_144,
      \crc_imd_reg[15]_2\(7) => myCrc_n_91,
      \crc_imd_reg[15]_2\(6) => myCrc_n_92,
      \crc_imd_reg[15]_2\(5) => myCrc_n_93,
      \crc_imd_reg[15]_2\(4) => myCrc_n_94,
      \crc_imd_reg[15]_2\(3) => myCrc_n_95,
      \crc_imd_reg[15]_2\(2) => myCrc_n_96,
      \crc_imd_reg[15]_2\(1) => myCrc_n_97,
      \crc_imd_reg[15]_2\(0) => myCrc_n_98,
      \crc_imd_reg[15]_3\(7) => myCrc_n_99,
      \crc_imd_reg[15]_3\(6) => myCrc_n_100,
      \crc_imd_reg[15]_3\(5) => myCrc_n_101,
      \crc_imd_reg[15]_3\(4) => myCrc_n_102,
      \crc_imd_reg[15]_3\(3) => myCrc_n_103,
      \crc_imd_reg[15]_3\(2) => myCrc_n_104,
      \crc_imd_reg[15]_3\(1) => myCrc_n_105,
      \crc_imd_reg[15]_3\(0) => myCrc_n_106,
      \crc_imd_reg[15]_4\(7) => myCrc_n_107,
      \crc_imd_reg[15]_4\(6) => myCrc_n_108,
      \crc_imd_reg[15]_4\(5) => myCrc_n_109,
      \crc_imd_reg[15]_4\(4) => myCrc_n_110,
      \crc_imd_reg[15]_4\(3) => myCrc_n_111,
      \crc_imd_reg[15]_4\(2) => myCrc_n_112,
      \crc_imd_reg[15]_4\(1) => myCrc_n_113,
      \crc_imd_reg[15]_4\(0) => myCrc_n_114,
      \crc_imd_reg[15]_5\(7) => myCrc_n_116,
      \crc_imd_reg[15]_5\(6) => myCrc_n_117,
      \crc_imd_reg[15]_5\(5) => myCrc_n_118,
      \crc_imd_reg[15]_5\(4) => myCrc_n_119,
      \crc_imd_reg[15]_5\(3) => myCrc_n_120,
      \crc_imd_reg[15]_5\(2) => myCrc_n_121,
      \crc_imd_reg[15]_5\(1) => myCrc_n_122,
      \crc_imd_reg[15]_5\(0) => myCrc_n_123,
      \crc_imd_reg[15]_6\ => myCrc_n_138,
      \crc_imd_reg[15]_7\ => myCrc_n_159,
      \crc_imd_reg[15]_8\ => myRxtx_n_168,
      \crc_imd_reg[15]_9\ => myRxtx_n_172,
      \crc_imd_reg[1]_0\ => myCrc_n_124,
      \crc_imd_reg[1]_1\ => myCrc_n_158,
      \crc_imd_reg[1]_2\ => myRxtx_n_145,
      \crc_imd_reg[1]_3\ => myRxtx_n_174,
      \crc_imd_reg[1]_4\ => myRxtx_n_169,
      \crc_imd_reg[2]_0\ => myCrc_n_47,
      \crc_imd_reg[2]_1\(1) => myCrc_n_81,
      \crc_imd_reg[2]_1\(0) => myCrc_n_82,
      \crc_imd_reg[2]_2\ => myCrc_n_125,
      \crc_imd_reg[2]_3\ => myCrc_n_145,
      \crc_imd_reg[3]_0\ => myCrc_n_27,
      \crc_imd_reg[3]_1\ => myCrc_n_46,
      \crc_imd_reg[3]_2\ => myCrc_n_131,
      \crc_imd_reg[3]_3\ => myCrc_n_135,
      \crc_imd_reg[4]_0\ => myCrc_n_146,
      \crc_imd_reg[4]_1\ => myCrc_n_150,
      \crc_imd_reg[4]_2\ => myCrc_n_172,
      \crc_imd_reg[5]_0\ => myCrc_n_147,
      \crc_imd_reg[5]_1\ => myCrc_n_149,
      \crc_imd_reg[5]_2\ => myCrc_n_151,
      \crc_imd_reg[6]_0\ => myCrc_n_35,
      \crc_imd_reg[6]_1\(4) => myCrc_n_126,
      \crc_imd_reg[6]_1\(3) => myCrc_n_127,
      \crc_imd_reg[6]_1\(2) => myCrc_n_128,
      \crc_imd_reg[6]_1\(1) => myCrc_n_129,
      \crc_imd_reg[6]_1\(0) => myCrc_n_130,
      \crc_imd_reg[6]_2\ => myCrc_n_148,
      \crc_imd_reg[6]_3\ => myCrc_n_152,
      \crc_imd_reg[6]_4\ => myCrc_n_173,
      \crc_imd_reg[7]_0\ => myCrc_n_44,
      \crc_imd_reg[7]_1\ => myCrc_n_167,
      \crc_imd_reg[7]_2\ => myRxtx_n_164,
      \crc_imd_reg[8]_0\ => myCrc_n_51,
      \crc_imd_reg[8]_1\ => myRxtx_n_175,
      \crc_imd_reg[8]_2\ => myRxtx_n_163,
      \crc_imd_reg[9]_0\ => myCrc_n_53,
      \crc_imd_reg[9]_1\ => myCrc_n_141,
      \crc_imd_reg[9]_2\ => myCrc_n_162,
      \crc_imd_reg[9]_3\(5) => myRxtx_n_132,
      \crc_imd_reg[9]_3\(4) => myRxtx_n_133,
      \crc_imd_reg[9]_3\(3) => myRxtx_n_134,
      \crc_imd_reg[9]_3\(2) => myRxtx_n_135,
      \crc_imd_reg[9]_3\(1) => myRxtx_n_136,
      \crc_imd_reg[9]_3\(0) => myRxtx_n_137,
      first_reg_0(0) => \stateOp_reg[0]_0\(0),
      p_10_out(0) => p_10_out(0),
      p_24_in => p_24_in,
      \recvAXIS_tdata_sig_reg[13]\ => myCrc_n_36,
      recvAXIS_tlast => recvAXIS_tlast,
      \resid_reg[1]\ => myCrc_n_28,
      \resid_reg[1]_0\ => myCrc_n_29,
      \resid_reg[1]_1\ => myCrc_n_30,
      \resid_reg[1]_2\ => myCrc_n_161,
      \retbuf_reg[0][0]\ => \retbuf[0][6]_i_2_n_0\,
      \retbuf_reg[0][0]_0\ => myRxtx_n_214,
      \retbuf_reg[0][0]_1\ => myRxtx_n_44,
      \retbuf_reg[0][1]\(1 downto 0) => \retbuf_reg[0][1]_0\(1 downto 0),
      \retbuf_reg[0][3]\ => \retbuf[0][4]_i_2_n_0\,
      \retbuf_reg[0][6]\ => \retbuf[0][6]_i_3_n_0\,
      \retbuf_reg[1][0]\(2) => ixRetbufCrc(5),
      \retbuf_reg[1][0]\(1 downto 0) => ixRetbufCrc(2 downto 1),
      \retbuf_reg[2][7]\(15 downto 0) => \retbuf_reg[1][7]_0\(23 downto 8),
      \retbuf_reg[31][0]\(1) => \resid_reg_n_0_[1]\,
      \retbuf_reg[31][0]\(0) => \resid_reg_n_0_[0]\,
      \retbuf_reg[33][0]\ => \retbuf[0][7]_i_4__0_n_0\,
      \retbuf_reg[33][0]_0\ => \retbuf[33][7]_i_3__0_n_0\,
      \retbuf_reg[36][0]\ => \retbuf[36][7]_i_3__0_n_0\,
      \retbuf_reg[37][0]\ => \retbuf[37][7]_i_3__0_n_0\,
      \retbuf_reg[6][7]\(7 downto 0) => \retbuf_reg[6][7]_0\(7 downto 0),
      \retbuf_reg[8][0]\ => \retbuf[8][7]_i_3_n_0\,
      \retbuf_reg[8][5]\ => \retbuf[8][5]_i_2__0_n_0\,
      rxAXIS_tvalid => rxAXIS_tvalid,
      \scoreMax_reg[7]\(7) => myCrc_n_73,
      \scoreMax_reg[7]\(6) => myCrc_n_74,
      \scoreMax_reg[7]\(5) => myCrc_n_75,
      \scoreMax_reg[7]\(4) => myCrc_n_76,
      \scoreMax_reg[7]\(3) => myCrc_n_77,
      \scoreMax_reg[7]\(2) => myCrc_n_78,
      \scoreMax_reg[7]\(1) => myCrc_n_79,
      \scoreMax_reg[7]\(0) => myCrc_n_80,
      \stateOp_next_reg[0]\ => myCrc_n_137,
      \stateOp_next_reg[2]\ => myCrc_n_134,
      \stateOp_reg[1]\ => myCrc_n_136,
      \stateOp_reg[1]_0\ => myCrc_n_163,
      \stateOp_reg[1]_1\ => myCrc_n_164,
      \stateOp_reg[1]_2\ => myCrc_n_165,
      \stateOp_reg[1]_3\ => myCrc_n_166,
      \stateOp_reg[1]_4\ => myCrc_n_169,
      \stateOp_reg[1]_5\ => myCrc_n_171,
      \stateOp_reg[2]\ => myCrc_n_50,
      \stateOp_reg[2]_0\(1) => stateOp_next(2),
      \stateOp_reg[2]_0\(0) => stateOp_next(0),
      \stateOp_reg[3]\(0) => myCrc_n_2,
      \stateOp_reg[3]_0\(0) => tixVCommand,
      \stateOp_reg[3]_1\ => myCrc_n_45,
      \stateOp_reg[3]_2\ => myCrc_n_153,
      \stateOp_reg[3]_3\ => myCrc_n_154,
      \stateOp_reg[3]_4\ => myCrc_n_155,
      \stateOp_reg[3]_5\ => myCrc_n_156,
      \stateOp_reg[4]\ => myCrc_n_142,
      \stateOp_reg[4]_0\ => myCrc_n_143,
      \stateOp_reg[4]_1\ => \stateOp[3]_i_6__0_n_0\,
      \stateOp_reg[4]_2\ => \stateOp[1]_i_4__4_n_0\,
      stateOp_reg_0 => myCrc_n_0,
      stateOp_reg_1 => myCrc_n_34,
      stateOp_reg_2 => myCrc_n_41,
      stateOp_reg_3 => myRxtx_n_177,
      \tixVCommand_reg[0]\ => \tixVController[7]_i_4__0_n_0\,
      \tixVCommand_reg[0]_0\(0) => \opbuf_reg_n_0_[2][0]\,
      \tkst_reg[15]\(7) => myCrc_n_65,
      \tkst_reg[15]\(6) => myCrc_n_66,
      \tkst_reg[15]\(5) => myCrc_n_67,
      \tkst_reg[15]\(4) => myCrc_n_68,
      \tkst_reg[15]\(3) => myCrc_n_69,
      \tkst_reg[15]\(2) => myCrc_n_70,
      \tkst_reg[15]\(1) => myCrc_n_71,
      \tkst_reg[15]\(0) => myCrc_n_72,
      \tkst_reg[23]\(7) => myCrc_n_57,
      \tkst_reg[23]\(6) => myCrc_n_58,
      \tkst_reg[23]\(5) => myCrc_n_59,
      \tkst_reg[23]\(4) => myCrc_n_60,
      \tkst_reg[23]\(3) => myCrc_n_61,
      \tkst_reg[23]\(2) => myCrc_n_62,
      \tkst_reg[23]\(1) => myCrc_n_63,
      \tkst_reg[23]\(0) => myCrc_n_64,
      \txAXIS_tdata_reg[10]\ => \txAXIS_tdata[31]_i_9__0_n_0\,
      \txAXIS_tdata_reg[10]_0\(0) => \pollbuf_reg[1]_50\(2),
      \txAXIS_tdata_reg[10]_1\(0) => \pollbuf_reg[5]_53\(2),
      \txAXIS_tdata_reg[16]\ => \txAXIS_tdata[16]_i_2__0_n_0\,
      \txAXIS_tdata_reg[16]_0\ => \txAXIS_tdata[23]_i_5__0_n_0\,
      \txAXIS_tdata_reg[18]\ => \txAXIS_tdata[18]_i_2__0_n_0\,
      \txAXIS_tdata_reg[26]\(0) => \pollbuf_reg[3]_51\(2),
      \txAXIS_tdata_reg[6]\(3) => \pollbuf_reg[4]_52\(6),
      \txAXIS_tdata_reg[6]\(2) => \pollbuf_reg[4]_52\(4),
      \txAXIS_tdata_reg[6]\(1) => \pollbuf_reg[4]_52\(2),
      \txAXIS_tdata_reg[6]\(0) => \pollbuf_reg[4]_52\(0),
      \txAXIS_tdata_reg[6]_0\(3) => \pollbuf_reg[0]_49\(6),
      \txAXIS_tdata_reg[6]_0\(2) => \pollbuf_reg[0]_49\(4),
      \txAXIS_tdata_reg[6]_0\(1) => \pollbuf_reg[0]_49\(2),
      \txAXIS_tdata_reg[6]_0\(0) => \pollbuf_reg[0]_49\(0),
      \txAXIS_tdata_reg[8]\ => myCrc_n_54,
      \txlen_reg[3]\ => myRxtx_n_8
    );
myRxtx: entity work.\design_1_Vsp_core_0_0_Axislave_v1_0__parameterized1\
     port map (
      AXIL_arready => AXIL_arready,
      AXIL_awready_sig_reg_0 => AXIL_awready_sig_reg,
      AXIL_bvalid_sig_reg_0 => AXIL_bvalid_sig_reg,
      AXIL_wready_sig_reg_0 => AXIL_wready_sig_reg,
      AXIS_tlast => AXIS_tlast,
      AXIS_tvalid => AXIS_tvalid,
      CO(0) => \stateOp_reg[4]_i_5_n_5\,
      D(7) => myRxtx_n_0,
      D(6) => myRxtx_n_1,
      D(5) => myRxtx_n_2,
      D(4) => myRxtx_n_3,
      D(3) => myRxtx_n_4,
      D(2) => myRxtx_n_5,
      D(1) => myRxtx_n_6,
      D(0) => myRxtx_n_7,
      E(0) => myRxtx_n_34,
      Q(4 downto 0) => \^q\(4 downto 0),
      aclk_sig => aclk_sig,
      \crcAXIS_tkeep_reg[0]\ => \crcAXIS_tkeep[0]_i_2_n_0\,
      \crcAXIS_tkeep_reg[0]_0\ => \crcAXIS_tkeep[3]_i_7_n_0\,
      \crcAXIS_tkeep_reg[0]_1\(0) => \crcAXIS_tkeep_reg[3]_i_11_n_5\,
      \crcAXIS_tkeep_reg[1]\ => \crcAXIS_tkeep[1]_i_2_n_0\,
      \crcAXIS_tkeep_reg[3]\(1 downto 0) => \lastAXIS_tkeep__0\(3 downto 2),
      \crcAXIS_tkeep_reg[3]_0\ => \crcAXIS_tkeep[3]_i_12_n_0\,
      \crcAXIS_tlast_sig_i_4__0_0\(4 downto 0) => stateOp_next(4 downto 0),
      \crcAXIS_tlast_sig_i_9__0_0\(3) => \tixVBuffer_reg_n_0_[3]\,
      \crcAXIS_tlast_sig_i_9__0_0\(2) => \tixVBuffer_reg_n_0_[2]\,
      \crcAXIS_tlast_sig_i_9__0_0\(1) => \tixVBuffer_reg_n_0_[1]\,
      \crcAXIS_tlast_sig_i_9__0_0\(0) => \tixVBuffer_reg_n_0_[0]\,
      \crcAXIS_tlast_sig_i_9__0_1\ => \stateOp[2]_i_6__0_n_0\,
      crcAXIS_tlast_sig_reg => myRxtx_n_177,
      crcAXIS_tlast_sig_reg_0 => \wordcnt[30]_i_7__0_n_0\,
      crcAXIS_tlast_sig_reg_1 => \crcAXIS_tlast_sig_i_3__0_n_0\,
      crcAXIS_tlast_sig_reg_2 => crcAXIS_tlast_sig_reg_n_0,
      crcAXIS_tlast_sig_reg_3 => \crcAXIS_tlast_sig_i_6__0_n_0\,
      crcAXIS_tlast_sig_reg_4(0) => \crcAXIS_tkeep_reg[3]_i_10_n_5\,
      crcAXIS_tlast_sig_reg_5 => \crcAXIS_tlast_sig_i_7__0_n_0\,
      crcAXIS_tlast_sig_reg_6 => \crcAXIS_tlast_sig_i_10__0_n_0\,
      crc_imd013_out => crc_imd013_out,
      crc_imd015_out => crc_imd015_out,
      crc_imd017_out => crc_imd017_out,
      crc_imd019_out => crc_imd019_out,
      crc_imd020_out => crc_imd020_out,
      crc_imd032_out => crc_imd032_out,
      crc_imd033_out => crc_imd033_out,
      crc_imd059_out => crc_imd059_out,
      crc_imd060_out => crc_imd060_out,
      \crc_imd[2]_i_3__0_0\ => myCrc_n_48,
      \crc_imd[6]_i_3__0_0\ => myCrc_n_42,
      \crc_imd_reg[0]\ => myCrc_n_41,
      \crc_imd_reg[0]_0\ => myCrc_n_36,
      \crc_imd_reg[10]\(1 downto 0) => AXIS_tkeep(3 downto 2),
      \crc_imd_reg[11]\ => myCrc_n_50,
      \crc_imd_reg[13]\ => myCrc_n_46,
      \crc_imd_reg[14]\ => myRxtx_n_158,
      \crc_imd_reg[15]\(7) => myRxtx_n_26,
      \crc_imd_reg[15]\(6) => myRxtx_n_27,
      \crc_imd_reg[15]\(5) => myRxtx_n_28,
      \crc_imd_reg[15]\(4) => myRxtx_n_29,
      \crc_imd_reg[15]\(3) => myRxtx_n_30,
      \crc_imd_reg[15]\(2) => myRxtx_n_31,
      \crc_imd_reg[15]\(1) => myRxtx_n_32,
      \crc_imd_reg[15]\(0) => myRxtx_n_33,
      \crc_imd_reg[15]_0\ => myCrc_n_51,
      \crc_imd_reg[15]_1\ => myCrc_n_53,
      \crc_imd_reg[1]\(5) => myRxtx_n_132,
      \crc_imd_reg[1]\(4) => myRxtx_n_133,
      \crc_imd_reg[1]\(3) => myRxtx_n_134,
      \crc_imd_reg[1]\(2) => myRxtx_n_135,
      \crc_imd_reg[1]\(1) => myRxtx_n_136,
      \crc_imd_reg[1]\(0) => myRxtx_n_137,
      \crc_imd_reg[2]\ => myCrc_n_37,
      \crc_imd_reg[2]_0\ => myCrc_n_32,
      \crc_imd_reg[2]_1\ => myCrc_n_0,
      \crc_imd_reg[2]_2\ => myCrc_n_55,
      \crc_imd_reg[2]_3\ => myCrc_n_34,
      \crc_imd_reg[4]\ => myCrc_n_54,
      \crc_imd_reg[6]\ => myCrc_n_47,
      \crc_imd_reg[7]\(7) => myRxtx_n_18,
      \crc_imd_reg[7]\(6) => myRxtx_n_19,
      \crc_imd_reg[7]\(5) => myRxtx_n_20,
      \crc_imd_reg[7]\(4) => myRxtx_n_21,
      \crc_imd_reg[7]\(3) => myRxtx_n_22,
      \crc_imd_reg[7]\(2) => myRxtx_n_23,
      \crc_imd_reg[7]\(1) => myRxtx_n_24,
      \crc_imd_reg[7]\(0) => myRxtx_n_25,
      \crc_imd_reg[8]\ => myCrc_n_35,
      \crc_imd_reg[8]_0\ => myCrc_n_49,
      \crc_imd_reg[9]\ => myCrc_n_43,
      \crc_imd_reg[9]_0\ => myCrc_n_44,
      \ixRetbufCrc_reg[1]\(0) => myRxtx_n_221,
      \ixRetbufCrc_reg[2]\(0) => myRxtx_n_222,
      \ixRetbufCrc_reg[2]_0\(0) => myRxtx_n_223,
      \ixRetbufCrc_reg[2]_1\(0) => myRxtx_n_224,
      \ixRetbufCrc_reg[2]_2\(0) => myRxtx_n_225,
      \ixRetbufCrc_reg[2]_3\(0) => myRxtx_n_227,
      \ixRetbufCrc_reg[5]\(0) => myRxtx_n_219,
      \ixRetbufCrc_reg[5]_0\(0) => myRxtx_n_267,
      \ixRetbufCrc_reg[5]_1\(0) => myRxtx_n_326,
      \lastAXIS_tkeep_reg[3]\ => \ixRetbufCrc[2]_i_2_n_0\,
      \lastAXIS_tkeep_reg[3]_0\ => \stateOp_next[3]_i_2_n_0\,
      \lastAXIS_tkeep_reg[3]_1\ => \resid[0]_i_2__0_n_0\,
      lenRet1 => lenRet1,
      \len_reg[15]\(7 downto 0) => \opbuf_reg[5]_47\(7 downto 0),
      \len_reg[7]\(7 downto 0) => \opbuf_reg[6]_46\(7 downto 0),
      \opbuf_reg[0][7]\(7) => myRxtx_n_268,
      \opbuf_reg[0][7]\(6) => myRxtx_n_269,
      \opbuf_reg[0][7]\(5) => myRxtx_n_270,
      \opbuf_reg[0][7]\(4) => myRxtx_n_271,
      \opbuf_reg[0][7]\(3) => myRxtx_n_272,
      \opbuf_reg[0][7]\(2) => myRxtx_n_273,
      \opbuf_reg[0][7]\(1) => myRxtx_n_274,
      \opbuf_reg[0][7]\(0) => myRxtx_n_275,
      \opbuf_reg[1][0]\ => \opbuf[1][7]_i_3_n_0\,
      \opbuf_reg[1][0]_0\ => \opbuf[1][7]_i_4_n_0\,
      \opbuf_reg[1][7]\(7) => myRxtx_n_316,
      \opbuf_reg[1][7]\(6) => myRxtx_n_317,
      \opbuf_reg[1][7]\(5) => myRxtx_n_318,
      \opbuf_reg[1][7]\(4) => myRxtx_n_319,
      \opbuf_reg[1][7]\(3) => myRxtx_n_320,
      \opbuf_reg[1][7]\(2) => myRxtx_n_321,
      \opbuf_reg[1][7]\(1) => myRxtx_n_322,
      \opbuf_reg[1][7]\(0) => myRxtx_n_323,
      \opbuf_reg[2][7]\(7) => myRxtx_n_328,
      \opbuf_reg[2][7]\(6) => myRxtx_n_329,
      \opbuf_reg[2][7]\(5) => myRxtx_n_330,
      \opbuf_reg[2][7]\(4) => myRxtx_n_331,
      \opbuf_reg[2][7]\(3) => myRxtx_n_332,
      \opbuf_reg[2][7]\(2) => myRxtx_n_333,
      \opbuf_reg[2][7]\(1) => myRxtx_n_334,
      \opbuf_reg[2][7]\(0) => myRxtx_n_335,
      \opbuf_reg[5][7]\(15) => myRxtx_n_276,
      \opbuf_reg[5][7]\(14) => myRxtx_n_277,
      \opbuf_reg[5][7]\(13) => myRxtx_n_278,
      \opbuf_reg[5][7]\(12) => myRxtx_n_279,
      \opbuf_reg[5][7]\(11) => myRxtx_n_280,
      \opbuf_reg[5][7]\(10) => myRxtx_n_281,
      \opbuf_reg[5][7]\(9) => myRxtx_n_282,
      \opbuf_reg[5][7]\(8) => myRxtx_n_283,
      \opbuf_reg[5][7]\(7) => myRxtx_n_284,
      \opbuf_reg[5][7]\(6) => myRxtx_n_285,
      \opbuf_reg[5][7]\(5) => myRxtx_n_286,
      \opbuf_reg[5][7]\(4) => myRxtx_n_287,
      \opbuf_reg[5][7]\(3) => myRxtx_n_288,
      \opbuf_reg[5][7]\(2) => myRxtx_n_289,
      \opbuf_reg[5][7]\(1) => myRxtx_n_290,
      \opbuf_reg[5][7]\(0) => myRxtx_n_291,
      \opbuf_reg[6][0]\ => \opbuf[6][7]_i_3_n_0\,
      \opbuf_reg[6][0]_0\ => \opbuf[6][7]_i_4_n_0\,
      \out\(24) => myRxtx_n_351,
      \out\(23) => myRxtx_n_352,
      \out\(22) => myRxtx_n_353,
      \out\(21) => myRxtx_n_354,
      \out\(20) => myRxtx_n_355,
      \out\(19) => myRxtx_n_356,
      \out\(18) => myRxtx_n_357,
      \out\(17) => myRxtx_n_358,
      \out\(16) => myRxtx_n_359,
      \out\(15) => myRxtx_n_360,
      \out\(14) => myRxtx_n_361,
      \out\(13) => myRxtx_n_362,
      \out\(12) => myRxtx_n_363,
      \out\(11) => myRxtx_n_364,
      \out\(10) => myRxtx_n_365,
      \out\(9) => myRxtx_n_366,
      \out\(8) => myRxtx_n_367,
      \out\(7) => myRxtx_n_368,
      \out\(6) => myRxtx_n_369,
      \out\(5) => myRxtx_n_370,
      \out\(4) => myRxtx_n_371,
      \out\(3) => myRxtx_n_372,
      \out\(2) => myRxtx_n_373,
      \out\(1) => myRxtx_n_374,
      \out\(0) => myRxtx_n_375,
      p_10_out(0) => p_10_out(0),
      p_24_in => p_24_in,
      \pollbuf_reg[0][7]\(7) => \tixVController_reg_n_0_[7]\,
      \pollbuf_reg[0][7]\(6) => \tixVController_reg_n_0_[6]\,
      \pollbuf_reg[0][7]\(5) => \tixVController_reg_n_0_[5]\,
      \pollbuf_reg[0][7]\(4) => \tixVController_reg_n_0_[4]\,
      \pollbuf_reg[0][7]\(3) => \tixVController_reg_n_0_[3]\,
      \pollbuf_reg[0][7]\(2) => \tixVController_reg_n_0_[2]\,
      \pollbuf_reg[0][7]\(1) => \tixVController_reg_n_0_[1]\,
      \pollbuf_reg[0][7]\(0) => \tixVController_reg_n_0_[0]\,
      \pollbuf_reg[1][7]\(7) => \tixVCommand_reg_n_0_[7]\,
      \pollbuf_reg[1][7]\(6) => \tixVCommand_reg_n_0_[6]\,
      \pollbuf_reg[1][7]\(5) => \tixVCommand_reg_n_0_[5]\,
      \pollbuf_reg[1][7]\(4) => \tixVCommand_reg_n_0_[4]\,
      \pollbuf_reg[1][7]\(3) => \tixVCommand_reg_n_0_[3]\,
      \pollbuf_reg[1][7]\(2) => \tixVCommand_reg_n_0_[2]\,
      \pollbuf_reg[1][7]\(1) => \tixVCommand_reg_n_0_[1]\,
      \pollbuf_reg[1][7]\(0) => \tixVCommand_reg_n_0_[0]\,
      \pollbuf_reg[4][7]\(15) => myCrc_n_11,
      \pollbuf_reg[4][7]\(14) => myCrc_n_12,
      \pollbuf_reg[4][7]\(13) => myCrc_n_13,
      \pollbuf_reg[4][7]\(12) => myCrc_n_14,
      \pollbuf_reg[4][7]\(11) => myCrc_n_15,
      \pollbuf_reg[4][7]\(10) => myCrc_n_16,
      \pollbuf_reg[4][7]\(9) => myCrc_n_17,
      \pollbuf_reg[4][7]\(8) => myCrc_n_18,
      \pollbuf_reg[4][7]\(7) => myCrc_n_19,
      \pollbuf_reg[4][7]\(6) => myCrc_n_20,
      \pollbuf_reg[4][7]\(5) => myCrc_n_21,
      \pollbuf_reg[4][7]\(4) => myCrc_n_22,
      \pollbuf_reg[4][7]\(3) => myCrc_n_23,
      \pollbuf_reg[4][7]\(2) => myCrc_n_24,
      \pollbuf_reg[4][7]\(1) => myCrc_n_25,
      \pollbuf_reg[4][7]\(0) => myCrc_n_26,
      recvAXIS_tdata(8 downto 7) => rxAXIS_tdata(15 downto 14),
      recvAXIS_tdata(6 downto 5) => rxAXIS_tdata(11 downto 10),
      recvAXIS_tdata(4) => rxAXIS_tdata(8),
      recvAXIS_tdata(3 downto 1) => rxAXIS_tdata(5 downto 3),
      recvAXIS_tdata(0) => rxAXIS_tdata(0),
      \recvAXIS_tdata_sig_reg[12]_0\ => myRxtx_n_162,
      \recvAXIS_tdata_sig_reg[13]_0\ => myRxtx_n_164,
      \recvAXIS_tdata_sig_reg[13]_1\ => myRxtx_n_172,
      \recvAXIS_tdata_sig_reg[15]_0\(7) => myRxtx_n_292,
      \recvAXIS_tdata_sig_reg[15]_0\(6) => myRxtx_n_293,
      \recvAXIS_tdata_sig_reg[15]_0\(5) => myRxtx_n_294,
      \recvAXIS_tdata_sig_reg[15]_0\(4) => myRxtx_n_295,
      \recvAXIS_tdata_sig_reg[15]_0\(3) => myRxtx_n_296,
      \recvAXIS_tdata_sig_reg[15]_0\(2) => myRxtx_n_297,
      \recvAXIS_tdata_sig_reg[15]_0\(1) => myRxtx_n_298,
      \recvAXIS_tdata_sig_reg[15]_0\(0) => myRxtx_n_299,
      \recvAXIS_tdata_sig_reg[15]_1\(7 downto 0) => \opbuf[1]_56\(7 downto 0),
      \recvAXIS_tdata_sig_reg[21]_0\ => myRxtx_n_143,
      \recvAXIS_tdata_sig_reg[21]_1\ => myRxtx_n_174,
      \recvAXIS_tdata_sig_reg[23]_0\ => myRxtx_n_170,
      \recvAXIS_tdata_sig_reg[23]_1\(7) => myRxtx_n_300,
      \recvAXIS_tdata_sig_reg[23]_1\(6) => myRxtx_n_301,
      \recvAXIS_tdata_sig_reg[23]_1\(5) => myRxtx_n_302,
      \recvAXIS_tdata_sig_reg[23]_1\(4) => myRxtx_n_303,
      \recvAXIS_tdata_sig_reg[23]_1\(3) => myRxtx_n_304,
      \recvAXIS_tdata_sig_reg[23]_1\(2) => myRxtx_n_305,
      \recvAXIS_tdata_sig_reg[23]_1\(1) => myRxtx_n_306,
      \recvAXIS_tdata_sig_reg[23]_1\(0) => myRxtx_n_307,
      \recvAXIS_tdata_sig_reg[23]_2\(7) => myRxtx_n_308,
      \recvAXIS_tdata_sig_reg[23]_2\(6) => myRxtx_n_309,
      \recvAXIS_tdata_sig_reg[23]_2\(5) => myRxtx_n_310,
      \recvAXIS_tdata_sig_reg[23]_2\(4) => myRxtx_n_311,
      \recvAXIS_tdata_sig_reg[23]_2\(3) => myRxtx_n_312,
      \recvAXIS_tdata_sig_reg[23]_2\(2) => myRxtx_n_313,
      \recvAXIS_tdata_sig_reg[23]_2\(1) => myRxtx_n_314,
      \recvAXIS_tdata_sig_reg[23]_2\(0) => myRxtx_n_315,
      \recvAXIS_tdata_sig_reg[2]_0\ => myRxtx_n_171,
      \recvAXIS_tdata_sig_reg[5]_0\ => myRxtx_n_168,
      \recvAXIS_tdata_sig_reg[7]_0\ => myRxtx_n_141,
      recvAXIS_tlast => recvAXIS_tlast,
      recvAXIS_tlast_sig_reg_0 => myRxtx_n_138,
      \recvAXIS_tlast_sig_reg_i_3__0_0\(2) => \txlen_reg_n_0_[3]\,
      \recvAXIS_tlast_sig_reg_i_3__0_0\(1) => \txlen_reg_n_0_[1]\,
      \recvAXIS_tlast_sig_reg_i_3__0_0\(0) => \txlen_reg_n_0_[0]\,
      \resid_reg[0]\(0) => myRxtx_n_43,
      \resid_reg[0]_0\(3) => myRxtx_n_215,
      \resid_reg[0]_0\(2) => myRxtx_n_216,
      \resid_reg[0]_0\(1) => myRxtx_n_217,
      \resid_reg[0]_0\(0) => myRxtx_n_218,
      \resid_reg[0]_1\(0) => myRxtx_n_220,
      \resid_reg[0]_2\(0) => myRxtx_n_226,
      \resid_reg[0]_3\(0) => myRxtx_n_228,
      \retbuf_reg[14][4]\ => \retbuf[2][7]_i_3__0_n_0\,
      \retbuf_reg[14][4]_0\ => \retbuf[2][7]_i_4_n_0\,
      \retbuf_reg[1][0]\ => myCrc_n_144,
      \retbuf_reg[1][2]\ => myCrc_n_145,
      \retbuf_reg[1][4]\ => myCrc_n_146,
      \retbuf_reg[1][5]\ => myCrc_n_147,
      \retbuf_reg[1][6]\ => myCrc_n_148,
      \retbuf_reg[1][7]\(15 downto 8) => \retbuf_reg[1][7]_0\(31 downto 24),
      \retbuf_reg[1][7]\(7 downto 0) => \retbuf_reg[1][7]_0\(7 downto 0),
      \retbuf_reg[1][7]_0\ => \retbuf[1][7]_i_3__0_n_0\,
      \retbuf_reg[2][7]\ => \retbuf[2][7]_i_5__0_n_0\,
      \retbuf_reg[36][7]\(2) => ixRetbufCrc(5),
      \retbuf_reg[36][7]\(1 downto 0) => ixRetbufCrc(2 downto 1),
      \retbuf_reg[36][7]_0\ => \retbuf[0][7]_i_3__0_n_0\,
      \retbuf_reg[39][0]\ => \retbuf[39][7]_i_2__0_n_0\,
      \retbuf_reg[4][4]\ => myCrc_n_150,
      \retbuf_reg[4][5]\ => myCrc_n_151,
      \retbuf_reg[4][6]\ => myCrc_n_152,
      \retbuf_reg[4][7]\ => \retbuf[4][7]_i_3__0_n_0\,
      \retbuf_reg[5][5]\ => \retbuf[0][6]_i_3_n_0\,
      \retbuf_reg[5][5]_0\ => \retbuf[0][7]_i_4__0_n_0\,
      \retbuf_reg[5][5]_1\ => myCrc_n_149,
      \retbuf_reg[5][7]\(7 downto 0) => \retbuf_reg[5][7]_0\(7 downto 0),
      \retbuf_reg[5][7]_0\ => \retbuf[5][7]_i_3__0_n_0\,
      rpuAXIL_araddr(1 downto 0) => rpuAXIL_araddr(1 downto 0),
      rpuAXIL_arvalid => rpuAXIL_arvalid,
      rpuAXIL_awaddr(1 downto 0) => rpuAXIL_awaddr(1 downto 0),
      rpuAXIL_awvalid => rpuAXIL_awvalid,
      rpuAXIL_bready => rpuAXIL_bready,
      rpuAXIL_rdata(31 downto 0) => rpuAXIL_rdata(31 downto 0),
      rpuAXIL_rready => rpuAXIL_rready,
      rpuAXIL_rvalid => rpuAXIL_rvalid,
      rpuAXIL_wdata(31 downto 0) => rpuAXIL_wdata(31 downto 0),
      rpuAXIL_wstrb(3 downto 0) => rpuAXIL_wstrb(3 downto 0),
      rpuAXIL_wvalid => rpuAXIL_wvalid,
      rxAXIS_tvalid => rxAXIS_tvalid,
      rxlen(0) => rxlen(1),
      \rxlen_reg[1]\ => myRxtx_n_131,
      \rxlen_reg[1]_0\ => \rxlen[1]_i_3_n_0\,
      \scoreMin_reg[7]\(7) => myRxtx_n_190,
      \scoreMin_reg[7]\(6) => myRxtx_n_191,
      \scoreMin_reg[7]\(5) => myRxtx_n_192,
      \scoreMin_reg[7]\(4) => myRxtx_n_193,
      \scoreMin_reg[7]\(3) => myRxtx_n_194,
      \scoreMin_reg[7]\(2) => myRxtx_n_195,
      \scoreMin_reg[7]\(1) => myRxtx_n_196,
      \scoreMin_reg[7]\(0) => myRxtx_n_197,
      \sendAXIL_rdata_reg[0]_0\(0) => \stateOp_reg[0]_0\(0),
      \sendAXIL_rdata_reg[31]_0\(31) => \txAXIS_tdata_reg_n_0_[31]\,
      \sendAXIL_rdata_reg[31]_0\(30) => \txAXIS_tdata_reg_n_0_[30]\,
      \sendAXIL_rdata_reg[31]_0\(29) => \txAXIS_tdata_reg_n_0_[29]\,
      \sendAXIL_rdata_reg[31]_0\(28) => \txAXIS_tdata_reg_n_0_[28]\,
      \sendAXIL_rdata_reg[31]_0\(27) => \txAXIS_tdata_reg_n_0_[27]\,
      \sendAXIL_rdata_reg[31]_0\(26) => \txAXIS_tdata_reg_n_0_[26]\,
      \sendAXIL_rdata_reg[31]_0\(25) => \txAXIS_tdata_reg_n_0_[25]\,
      \sendAXIL_rdata_reg[31]_0\(24) => \txAXIS_tdata_reg_n_0_[24]\,
      \sendAXIL_rdata_reg[31]_0\(23) => \txAXIS_tdata_reg_n_0_[23]\,
      \sendAXIL_rdata_reg[31]_0\(22) => \txAXIS_tdata_reg_n_0_[22]\,
      \sendAXIL_rdata_reg[31]_0\(21) => \txAXIS_tdata_reg_n_0_[21]\,
      \sendAXIL_rdata_reg[31]_0\(20) => \txAXIS_tdata_reg_n_0_[20]\,
      \sendAXIL_rdata_reg[31]_0\(19) => \txAXIS_tdata_reg_n_0_[19]\,
      \sendAXIL_rdata_reg[31]_0\(18) => \txAXIS_tdata_reg_n_0_[18]\,
      \sendAXIL_rdata_reg[31]_0\(17) => \txAXIS_tdata_reg_n_0_[17]\,
      \sendAXIL_rdata_reg[31]_0\(16) => \txAXIS_tdata_reg_n_0_[16]\,
      \sendAXIL_rdata_reg[31]_0\(15) => \txAXIS_tdata_reg_n_0_[15]\,
      \sendAXIL_rdata_reg[31]_0\(14) => \txAXIS_tdata_reg_n_0_[14]\,
      \sendAXIL_rdata_reg[31]_0\(13) => \txAXIS_tdata_reg_n_0_[13]\,
      \sendAXIL_rdata_reg[31]_0\(12) => \txAXIS_tdata_reg_n_0_[12]\,
      \sendAXIL_rdata_reg[31]_0\(11) => \txAXIS_tdata_reg_n_0_[11]\,
      \sendAXIL_rdata_reg[31]_0\(10) => \txAXIS_tdata_reg_n_0_[10]\,
      \sendAXIL_rdata_reg[31]_0\(9) => \txAXIS_tdata_reg_n_0_[9]\,
      \sendAXIL_rdata_reg[31]_0\(8) => \txAXIS_tdata_reg_n_0_[8]\,
      \sendAXIL_rdata_reg[31]_0\(7) => \txAXIS_tdata_reg_n_0_[7]\,
      \sendAXIL_rdata_reg[31]_0\(6) => \txAXIS_tdata_reg_n_0_[6]\,
      \sendAXIL_rdata_reg[31]_0\(5) => \txAXIS_tdata_reg_n_0_[5]\,
      \sendAXIL_rdata_reg[31]_0\(4) => \txAXIS_tdata_reg_n_0_[4]\,
      \sendAXIL_rdata_reg[31]_0\(3) => \txAXIS_tdata_reg_n_0_[3]\,
      \sendAXIL_rdata_reg[31]_0\(2) => \txAXIS_tdata_reg_n_0_[2]\,
      \sendAXIL_rdata_reg[31]_0\(1) => \txAXIS_tdata_reg_n_0_[1]\,
      \sendAXIL_rdata_reg[31]_0\(0) => \txAXIS_tdata_reg_n_0_[0]\,
      \stateOp_next_reg[0]\ => \stateOp_next[0]_i_2_n_0\,
      \stateOp_next_reg[1]\ => \stateOp_next[2]_i_3_n_0\,
      \stateOp_next_reg[2]\(0) => \len_reg_n_0_[1]\,
      \stateOp_next_reg[2]_0\ => \stateOp_next[2]_i_2_n_0\,
      \stateOp_next_reg[4]\ => \stateOp_next[4]_i_3__0_n_0\,
      stateOp_reg => myRxtx_n_142,
      \stateOp_reg[0]\ => myRxtx_n_44,
      \stateOp_reg[0]_0\(3) => myRxtx_n_48,
      \stateOp_reg[0]_0\(2) => myRxtx_n_49,
      \stateOp_reg[0]_0\(1) => myRxtx_n_50,
      \stateOp_reg[0]_0\(0) => myRxtx_n_51,
      \stateOp_reg[0]_1\(0) => myRxtx_n_57,
      \stateOp_reg[0]_10\(1) => myXferto_n_0,
      \stateOp_reg[0]_10\(0) => myXferto_n_1,
      \stateOp_reg[0]_11\(1) => myWordto_n_0,
      \stateOp_reg[0]_11\(0) => myWordto_n_1,
      \stateOp_reg[0]_12\ => myWordto_n_2,
      \stateOp_reg[0]_13\ => \stateOp[0]_i_7__0_n_0\,
      \stateOp_reg[0]_2\ => myRxtx_n_130,
      \stateOp_reg[0]_3\ => myRxtx_n_214,
      \stateOp_reg[0]_4\ => \stateOp[4]_i_3_n_0\,
      \stateOp_reg[0]_5\ => \stateOp[4]_i_4__0_n_0\,
      \stateOp_reg[0]_6\ => \stateOp[4]_i_6__0_n_0\,
      \stateOp_reg[0]_7\ => \stateOp[4]_i_15_n_0\,
      \stateOp_reg[0]_8\ => myCrc_n_137,
      \stateOp_reg[0]_9\ => \stateOp[0]_i_5__0_n_0\,
      \stateOp_reg[1]\ => myRxtx_n_8,
      \stateOp_reg[1]_0\(4) => myRxtx_n_125,
      \stateOp_reg[1]_0\(3) => myRxtx_n_126,
      \stateOp_reg[1]_0\(2) => myRxtx_n_127,
      \stateOp_reg[1]_0\(1) => myRxtx_n_128,
      \stateOp_reg[1]_0\(0) => myRxtx_n_129,
      \stateOp_reg[1]_1\(0) => myRxtx_n_179,
      \stateOp_reg[1]_2\(4) => myRxtx_n_181,
      \stateOp_reg[1]_2\(3) => myRxtx_n_182,
      \stateOp_reg[1]_2\(2) => myRxtx_n_183,
      \stateOp_reg[1]_2\(1) => myRxtx_n_184,
      \stateOp_reg[1]_2\(0) => myRxtx_n_185,
      \stateOp_reg[1]_3\(29) => myRxtx_n_229,
      \stateOp_reg[1]_3\(28) => myRxtx_n_230,
      \stateOp_reg[1]_3\(27) => myRxtx_n_231,
      \stateOp_reg[1]_3\(26) => myRxtx_n_232,
      \stateOp_reg[1]_3\(25) => myRxtx_n_233,
      \stateOp_reg[1]_3\(24) => myRxtx_n_234,
      \stateOp_reg[1]_3\(23) => myRxtx_n_235,
      \stateOp_reg[1]_3\(22) => myRxtx_n_236,
      \stateOp_reg[1]_3\(21) => myRxtx_n_237,
      \stateOp_reg[1]_3\(20) => myRxtx_n_238,
      \stateOp_reg[1]_3\(19) => myRxtx_n_239,
      \stateOp_reg[1]_3\(18) => myRxtx_n_240,
      \stateOp_reg[1]_3\(17) => myRxtx_n_241,
      \stateOp_reg[1]_3\(16) => myRxtx_n_242,
      \stateOp_reg[1]_3\(15) => myRxtx_n_243,
      \stateOp_reg[1]_3\(14) => myRxtx_n_244,
      \stateOp_reg[1]_3\(13) => myRxtx_n_245,
      \stateOp_reg[1]_3\(12) => myRxtx_n_246,
      \stateOp_reg[1]_3\(11) => myRxtx_n_247,
      \stateOp_reg[1]_3\(10) => myRxtx_n_248,
      \stateOp_reg[1]_3\(9) => myRxtx_n_249,
      \stateOp_reg[1]_3\(8) => myRxtx_n_250,
      \stateOp_reg[1]_3\(7) => myRxtx_n_251,
      \stateOp_reg[1]_3\(6) => myRxtx_n_252,
      \stateOp_reg[1]_3\(5) => myRxtx_n_253,
      \stateOp_reg[1]_3\(4) => myRxtx_n_254,
      \stateOp_reg[1]_3\(3) => myRxtx_n_255,
      \stateOp_reg[1]_3\(2) => myRxtx_n_256,
      \stateOp_reg[1]_3\(1) => myRxtx_n_257,
      \stateOp_reg[1]_3\(0) => myRxtx_n_258,
      \stateOp_reg[1]_4\(0) => \opbuf[0]1\,
      \stateOp_reg[1]_5\ => myRxtx_n_347,
      \stateOp_reg[1]_6\ => \stateOp[1]_i_3__3_n_0\,
      \stateOp_reg[1]_7\ => \stateOp[1]_i_4__4_n_0\,
      \stateOp_reg[2]\(2) => myRxtx_n_52,
      \stateOp_reg[2]\(1) => myRxtx_n_53,
      \stateOp_reg[2]\(0) => wordcntLast(0),
      \stateOp_reg[2]_0\(0) => myRxtx_n_55,
      \stateOp_reg[2]_1\ => myRxtx_n_91,
      \stateOp_reg[2]_2\(0) => myRxtx_n_178,
      \stateOp_reg[2]_3\ => myCrc_n_134,
      \stateOp_reg[2]_4\ => \stateOp[2]_i_4__1_n_0\,
      \stateOp_reg[3]\(0) => myRxtx_n_180,
      \stateOp_reg[3]_0\(0) => \pollbuf[5]_54\,
      \stateOp_reg[3]_1\(0) => \pollbuf[3]_55\,
      \stateOp_reg[3]_2\(0) => myRxtx_n_327,
      \stateOp_reg[3]_3\ => \stateOp[3]_i_3__0_n_0\,
      \stateOp_reg[3]_4\ => \stateOp[3]_i_6__0_n_0\,
      \stateOp_reg[3]_5\ => \stateOp[3]_i_7__0_n_0\,
      \stateOp_reg[3]_6\ => \stateOp[3]_i_9_n_0\,
      \stateOp_reg[4]\(0) => myRxtx_n_344,
      \stateOp_reg[4]_0\(0) => wordcntLast(1),
      \stateOp_reg[4]_1\ => \stateOp[4]_i_9_n_0\,
      \stateOp_reg[4]_2\ => myCrc_n_136,
      stateOp_reg_0 => myRxtx_n_145,
      stateOp_reg_1 => myRxtx_n_165,
      stateOp_reg_2 => myRxtx_n_166,
      stateOp_reg_3 => myRxtx_n_167,
      stateOp_reg_4 => myCrc_n_45,
      \stateSend_reg[0]_0\ => myRxtx_n_348,
      \tixVBuffer_reg[7]\(7) => \opbuf_reg_n_0_[0][7]\,
      \tixVBuffer_reg[7]\(6) => \opbuf_reg_n_0_[0][6]\,
      \tixVBuffer_reg[7]\(5) => \opbuf_reg_n_0_[0][5]\,
      \tixVBuffer_reg[7]\(4) => \opbuf_reg_n_0_[0][4]\,
      \tixVBuffer_reg[7]\(3) => \opbuf_reg_n_0_[0][3]\,
      \tixVBuffer_reg[7]\(2) => \opbuf_reg_n_0_[0][2]\,
      \tixVBuffer_reg[7]\(1) => \opbuf_reg_n_0_[0][1]\,
      \tixVBuffer_reg[7]\(0) => \opbuf_reg_n_0_[0][0]\,
      \tixVBufxfop_reg[7]\(7) => \opbuf_reg_n_0_[2][7]\,
      \tixVBufxfop_reg[7]\(6) => \opbuf_reg_n_0_[2][6]\,
      \tixVBufxfop_reg[7]\(5) => \opbuf_reg_n_0_[2][5]\,
      \tixVBufxfop_reg[7]\(4) => \opbuf_reg_n_0_[2][4]\,
      \tixVBufxfop_reg[7]\(3) => \opbuf_reg_n_0_[2][3]\,
      \tixVBufxfop_reg[7]\(2) => \opbuf_reg_n_0_[2][2]\,
      \tixVBufxfop_reg[7]\(1) => \opbuf_reg_n_0_[2][1]\,
      \tixVBufxfop_reg[7]\(0) => \opbuf_reg_n_0_[2][0]\,
      \tixVCommand_reg[1]\(1) => myRxtx_n_186,
      \tixVCommand_reg[1]\(0) => myRxtx_n_187,
      \tixVCommand_reg[1]_0\(1) => myRxtx_n_188,
      \tixVCommand_reg[1]_0\(0) => myRxtx_n_189,
      \tixVCommand_reg[7]\(7) => myRxtx_n_259,
      \tixVCommand_reg[7]\(6) => myRxtx_n_260,
      \tixVCommand_reg[7]\(5) => myRxtx_n_261,
      \tixVCommand_reg[7]\(4) => myRxtx_n_262,
      \tixVCommand_reg[7]\(3) => myRxtx_n_263,
      \tixVCommand_reg[7]\(2) => myRxtx_n_264,
      \tixVCommand_reg[7]\(1) => myRxtx_n_265,
      \tixVCommand_reg[7]\(0) => myRxtx_n_266,
      \tixVController_reg[0]\(2) => myRxtx_n_45,
      \tixVController_reg[0]\(1) => myRxtx_n_46,
      \tixVController_reg[0]\(0) => myRxtx_n_47,
      \tixVController_reg[0]_0\ => myRxtx_n_58,
      \tixVController_reg[1]\ => myRxtx_n_59,
      \tixVController_reg[7]\(7) => myRxtx_n_35,
      \tixVController_reg[7]\(6) => myRxtx_n_36,
      \tixVController_reg[7]\(5) => myRxtx_n_37,
      \tixVController_reg[7]\(4) => myRxtx_n_38,
      \tixVController_reg[7]\(3) => myRxtx_n_39,
      \tixVController_reg[7]\(2) => myRxtx_n_40,
      \tixVController_reg[7]\(1) => myRxtx_n_41,
      \tixVController_reg[7]\(0) => myRxtx_n_42,
      \tixVController_reg[7]_0\(7 downto 0) => \opbuf_reg[1]_45\(7 downto 0),
      \tkst_reg[31]\(7) => myRxtx_n_206,
      \tkst_reg[31]\(6) => myRxtx_n_207,
      \tkst_reg[31]\(5) => myRxtx_n_208,
      \tkst_reg[31]\(4) => myRxtx_n_209,
      \tkst_reg[31]\(3) => myRxtx_n_210,
      \tkst_reg[31]\(2) => myRxtx_n_211,
      \tkst_reg[31]\(1) => myRxtx_n_212,
      \tkst_reg[31]\(0) => myRxtx_n_213,
      \tkst_reg[7]\(7) => myRxtx_n_198,
      \tkst_reg[7]\(6) => myRxtx_n_199,
      \tkst_reg[7]\(5) => myRxtx_n_200,
      \tkst_reg[7]\(4) => myRxtx_n_201,
      \tkst_reg[7]\(3) => myRxtx_n_202,
      \tkst_reg[7]\(2) => myRxtx_n_203,
      \tkst_reg[7]\(1) => myRxtx_n_204,
      \tkst_reg[7]\(0) => myRxtx_n_205,
      \txAXIS_tdata_reg[0]\ => \txAXIS_tdata[0]_i_2__0_n_0\,
      \txAXIS_tdata_reg[0]_0\ => \txAXIS_tdata[6]_i_2__0_n_0\,
      \txAXIS_tdata_reg[0]_1\ => myCrc_n_153,
      \txAXIS_tdata_reg[0]_2\ => \txAXIS_tdata[6]_i_5__0_n_0\,
      \txAXIS_tdata_reg[10]\ => myCrc_n_142,
      \txAXIS_tdata_reg[10]_0\ => \txAXIS_tdata[10]_i_3__0_n_0\,
      \txAXIS_tdata_reg[10]_1\ => \txAXIS_tdata[10]_i_4__0_n_0\,
      \txAXIS_tdata_reg[11]\ => myRxtx_n_161,
      \txAXIS_tdata_reg[11]_0\ => myRxtx_n_173,
      \txAXIS_tdata_reg[11]_1\ => \txAXIS_tdata[11]_i_2__0_n_0\,
      \txAXIS_tdata_reg[11]_2\ => \txAXIS_tdata_reg[11]_i_3_n_0\,
      \txAXIS_tdata_reg[11]_3\ => myCrc_n_30,
      \txAXIS_tdata_reg[12]\ => \txAXIS_tdata[12]_i_2__0_n_0\,
      \txAXIS_tdata_reg[12]_0\ => \txAXIS_tdata[12]_i_3__0_n_0\,
      \txAXIS_tdata_reg[12]_1\ => myCrc_n_168,
      \txAXIS_tdata_reg[13]\ => myCrc_n_169,
      \txAXIS_tdata_reg[13]_0\ => \txAXIS_tdata[13]_i_3__0_n_0\,
      \txAXIS_tdata_reg[13]_1\ => \txAXIS_tdata_reg[13]_i_4_n_0\,
      \txAXIS_tdata_reg[14]\ => myRxtx_n_144,
      \txAXIS_tdata_reg[14]_0\ => myRxtx_n_169,
      \txAXIS_tdata_reg[14]_1\ => \txAXIS_tdata[14]_i_2__0_n_0\,
      \txAXIS_tdata_reg[14]_2\ => \txAXIS_tdata_reg[14]_i_3_n_0\,
      \txAXIS_tdata_reg[14]_3\ => myCrc_n_170,
      \txAXIS_tdata_reg[15]\(1) => \resid_reg_n_0_[1]\,
      \txAXIS_tdata_reg[15]\(0) => \resid_reg_n_0_[0]\,
      \txAXIS_tdata_reg[15]_0\ => myCrc_n_171,
      \txAXIS_tdata_reg[15]_1\ => \txAXIS_tdata[15]_i_4__0_n_0\,
      \txAXIS_tdata_reg[15]_2\ => \txAXIS_tdata_reg[15]_i_5_n_0\,
      \txAXIS_tdata_reg[15]_3\ => \txAXIS_tdata[31]_i_3__0_n_0\,
      \txAXIS_tdata_reg[17]\ => \txAXIS_tdata[17]_i_2__0_n_0\,
      \txAXIS_tdata_reg[17]_0\ => \txAXIS_tdata[17]_i_3__0_n_0\,
      \txAXIS_tdata_reg[17]_1\ => \txAXIS_tdata[31]_i_7__0_n_0\,
      \txAXIS_tdata_reg[17]_2\ => \txAXIS_tdata[23]_i_5__0_n_0\,
      \txAXIS_tdata_reg[17]_3\ => myCrc_n_162,
      \txAXIS_tdata_reg[19]\ => \txAXIS_tdata[19]_i_2__0_n_0\,
      \txAXIS_tdata_reg[19]_0\ => \txAXIS_tdata[27]_i_3__0_n_0\,
      \txAXIS_tdata_reg[19]_1\ => \txAXIS_tdata[19]_i_3__0_n_0\,
      \txAXIS_tdata_reg[19]_2\ => myCrc_n_161,
      \txAXIS_tdata_reg[1]\ => myCrc_n_141,
      \txAXIS_tdata_reg[1]_0\ => \txAXIS_tdata[1]_i_3__0_n_0\,
      \txAXIS_tdata_reg[1]_1\ => \txAXIS_tdata[1]_i_4__0_n_0\,
      \txAXIS_tdata_reg[1]_2\ => \txAXIS_tdata[7]_i_7__0_n_0\,
      \txAXIS_tdata_reg[20]\ => myCrc_n_172,
      \txAXIS_tdata_reg[20]_0\ => \txAXIS_tdata[20]_i_3__0_n_0\,
      \txAXIS_tdata_reg[20]_1\ => \txAXIS_tdata[31]_i_5__0_n_0\,
      \txAXIS_tdata_reg[20]_2\ => \txAXIS_tdata[20]_i_4__0_n_0\,
      \txAXIS_tdata_reg[21]\ => \txAXIS_tdata[21]_i_2__0_n_0\,
      \txAXIS_tdata_reg[21]_0\ => \txAXIS_tdata[21]_i_3__0_n_0\,
      \txAXIS_tdata_reg[21]_1\ => myCrc_n_160,
      \txAXIS_tdata_reg[22]\ => \txAXIS_tdata[22]_i_2__0_n_0\,
      \txAXIS_tdata_reg[22]_0\ => \txAXIS_tdata[22]_i_3__0_n_0\,
      \txAXIS_tdata_reg[22]_1\ => myCrc_n_173,
      \txAXIS_tdata_reg[23]\ => \txAXIS_tdata[23]_i_3__0_n_0\,
      \txAXIS_tdata_reg[23]_0\ => \txAXIS_tdata[23]_i_4__0_n_0\,
      \txAXIS_tdata_reg[23]_1\ => myCrc_n_159,
      \txAXIS_tdata_reg[24]\ => \txAXIS_tdata[25]_i_2__0_n_0\,
      \txAXIS_tdata_reg[24]_0\ => \txAXIS_tdata_reg[24]_i_2_n_0\,
      \txAXIS_tdata_reg[24]_1\ => myCrc_n_157,
      \txAXIS_tdata_reg[25]\ => \txAXIS_tdata_reg[25]_i_3_n_0\,
      \txAXIS_tdata_reg[25]_0\ => myCrc_n_158,
      \txAXIS_tdata_reg[26]\ => myCrc_n_143,
      \txAXIS_tdata_reg[26]_0\ => \txAXIS_tdata[26]_i_3__0_n_0\,
      \txAXIS_tdata_reg[26]_1\ => \txAXIS_tdata[26]_i_4__0_n_0\,
      \txAXIS_tdata_reg[26]_2\ => \txAXIS_tdata[26]_i_5__0_n_0\,
      \txAXIS_tdata_reg[27]\ => \txAXIS_tdata[27]_i_2__0_n_0\,
      \txAXIS_tdata_reg[27]_0\ => \txAXIS_tdata[27]_i_4__0_n_0\,
      \txAXIS_tdata_reg[27]_1\ => myCrc_n_163,
      \txAXIS_tdata_reg[28]\ => \txAXIS_tdata[28]_i_2__0_n_0\,
      \txAXIS_tdata_reg[28]_0\ => \txAXIS_tdata[28]_i_3__0_n_0\,
      \txAXIS_tdata_reg[28]_1\ => myCrc_n_164,
      \txAXIS_tdata_reg[29]\ => myCrc_n_165,
      \txAXIS_tdata_reg[29]_0\ => \txAXIS_tdata[29]_i_3__0_n_0\,
      \txAXIS_tdata_reg[2]\ => \txAXIS_tdata[2]_i_2__0_n_0\,
      \txAXIS_tdata_reg[2]_0\ => myCrc_n_154,
      \txAXIS_tdata_reg[30]\(11 downto 10) => AXIS_tdata(30 downto 29),
      \txAXIS_tdata_reg[30]\(9 downto 7) => AXIS_tdata(23 downto 21),
      \txAXIS_tdata_reg[30]\(6 downto 4) => AXIS_tdata(15 downto 13),
      \txAXIS_tdata_reg[30]\(3) => AXIS_tdata(6),
      \txAXIS_tdata_reg[30]\(2) => AXIS_tdata(3),
      \txAXIS_tdata_reg[30]\(1 downto 0) => AXIS_tdata(1 downto 0),
      \txAXIS_tdata_reg[30]_0\ => \txAXIS_tdata[30]_i_2__0_n_0\,
      \txAXIS_tdata_reg[30]_1\ => \txAXIS_tdata[30]_i_3__0_n_0\,
      \txAXIS_tdata_reg[30]_2\ => myCrc_n_166,
      \txAXIS_tdata_reg[31]\ => myRxtx_n_163,
      \txAXIS_tdata_reg[31]_0\ => \txAXIS_tdata[31]_i_4__0_n_0\,
      \txAXIS_tdata_reg[31]_1\ => \txAXIS_tdata[31]_i_6__0_n_0\,
      \txAXIS_tdata_reg[31]_2\ => myCrc_n_167,
      \txAXIS_tdata_reg[3]\ => myCrc_n_140,
      \txAXIS_tdata_reg[3]_0\ => \txAXIS_tdata[3]_i_3__0_n_0\,
      \txAXIS_tdata_reg[3]_1\ => \txAXIS_tdata[3]_i_4__0_n_0\,
      \txAXIS_tdata_reg[4]\ => \txAXIS_tdata[4]_i_2__0_n_0\,
      \txAXIS_tdata_reg[4]_0\ => myCrc_n_155,
      \txAXIS_tdata_reg[5]\ => myCrc_n_139,
      \txAXIS_tdata_reg[5]_0\ => \txAXIS_tdata[5]_i_3__0_n_0\,
      \txAXIS_tdata_reg[5]_1\ => \txAXIS_tdata[5]_i_4_n_0\,
      \txAXIS_tdata_reg[6]\ => \txAXIS_tdata[6]_i_3__0_n_0\,
      \txAXIS_tdata_reg[6]_0\ => myCrc_n_156,
      \txAXIS_tdata_reg[7]\ => myRxtx_n_175,
      \txAXIS_tdata_reg[7]_0\ => myCrc_n_135,
      \txAXIS_tdata_reg[7]_1\ => \stateOp[3]_i_5__0_n_0\,
      \txAXIS_tdata_reg[7]_2\ => myCrc_n_138,
      \txAXIS_tdata_reg[7]_3\ => \txAXIS_tdata[7]_i_5__0_n_0\,
      \txAXIS_tdata_reg[7]_4\ => \txAXIS_tdata[7]_i_6__0_n_0\,
      \txAXIS_tdata_reg[8]\ => \txAXIS_tdata[8]_i_2__0_n_0\,
      \txAXIS_tdata_reg[8]_0\ => \txAXIS_tdata[8]_i_3__0_n_0\,
      \txAXIS_tdata_reg[8]_1\ => myCrc_n_28,
      \txAXIS_tdata_reg[9]\ => \txAXIS_tdata[9]_i_2__0_n_0\,
      \txAXIS_tdata_reg[9]_0\ => \txAXIS_tdata_reg[9]_i_3_n_0\,
      \txAXIS_tdata_reg[9]_1\ => myCrc_n_29,
      txlast1(29 downto 0) => txlast1(30 downto 1),
      \txlen_reg[0]\ => \wordcntLast[0]_i_2__0_n_0\,
      \wordcntLast_reg[1]\ => \wordcntLast[1]_i_2_n_0\,
      \wordcnt_reg[0]_0\(0) => \opbuf_reg[0]51_in\(5),
      \wordcnt_reg[0]_1\ => \wordcnt[30]_i_4_n_0\,
      \wordcnt_reg[30]_0\(30) => myRxtx_n_60,
      \wordcnt_reg[30]_0\(29) => myRxtx_n_61,
      \wordcnt_reg[30]_0\(28) => myRxtx_n_62,
      \wordcnt_reg[30]_0\(27) => myRxtx_n_63,
      \wordcnt_reg[30]_0\(26) => myRxtx_n_64,
      \wordcnt_reg[30]_0\(25) => myRxtx_n_65,
      \wordcnt_reg[30]_0\(24) => myRxtx_n_66,
      \wordcnt_reg[30]_0\(23) => myRxtx_n_67,
      \wordcnt_reg[30]_0\(22) => myRxtx_n_68,
      \wordcnt_reg[30]_0\(21) => myRxtx_n_69,
      \wordcnt_reg[30]_0\(20) => myRxtx_n_70,
      \wordcnt_reg[30]_0\(19) => myRxtx_n_71,
      \wordcnt_reg[30]_0\(18) => myRxtx_n_72,
      \wordcnt_reg[30]_0\(17) => myRxtx_n_73,
      \wordcnt_reg[30]_0\(16) => myRxtx_n_74,
      \wordcnt_reg[30]_0\(15) => myRxtx_n_75,
      \wordcnt_reg[30]_0\(14) => myRxtx_n_76,
      \wordcnt_reg[30]_0\(13) => myRxtx_n_77,
      \wordcnt_reg[30]_0\(12) => myRxtx_n_78,
      \wordcnt_reg[30]_0\(11) => myRxtx_n_79,
      \wordcnt_reg[30]_0\(10) => myRxtx_n_80,
      \wordcnt_reg[30]_0\(9) => myRxtx_n_81,
      \wordcnt_reg[30]_0\(8) => myRxtx_n_82,
      \wordcnt_reg[30]_0\(7) => myRxtx_n_83,
      \wordcnt_reg[30]_0\(6) => myRxtx_n_84,
      \wordcnt_reg[30]_0\(5) => myRxtx_n_85,
      \wordcnt_reg[30]_0\(4) => myRxtx_n_86,
      \wordcnt_reg[30]_0\(3) => myRxtx_n_87,
      \wordcnt_reg[30]_0\(2) => myRxtx_n_88,
      \wordcnt_reg[30]_0\(1) => myRxtx_n_89,
      \wordcnt_reg[30]_0\(0) => myRxtx_n_90
    );
myWordto: entity work.design_1_Vsp_core_0_0_Timeout_v1_0
     port map (
      Q(1) => myWordto_n_0,
      Q(0) => myWordto_n_1,
      aclk_sig => aclk_sig,
      \stateOp[1]_i_3__1\(3 downto 2) => \^q\(4 downto 3),
      \stateOp[1]_i_3__1\(1 downto 0) => \^q\(1 downto 0),
      \stateOp_reg[0]_0\ => myRxtx_n_348,
      \stateOp_reg[1]_0\ => myWordto_n_2,
      \stateOp_reg[1]_1\(0) => \stateOp_reg[0]_0\(0),
      tkclk => tkclk
    );
myXferto: entity work.\design_1_Vsp_core_0_0_Timeout_v1_0__parameterized1\
     port map (
      Q(1) => myXferto_n_0,
      Q(0) => myXferto_n_1,
      aclk_sig => aclk_sig,
      \stateOp_reg[0]_0\(0) => \stateOp_reg[0]_0\(0),
      \stateOp_reg[0]_1\ => myRxtx_n_347,
      tkclk => tkclk
    );
\opbuf[1][7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF7FFFFFFE"
    )
        port map (
      I0 => \opbuf[1][7]_i_24_n_0\,
      I1 => \opbuf[1][7]_i_25_n_0\,
      I2 => \opbuf[1][7]_i_26_n_0\,
      I3 => \opbuf[1][7]_i_27_n_0\,
      I4 => \opbuf[1][7]_i_28_n_0\,
      I5 => \opbuf[1][7]_i_29_n_0\,
      O => \opbuf[1][7]_i_10_n_0\
    );
\opbuf[1][7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(8),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(11),
      O => \opbuf[1][7]_i_11_n_0\
    );
\opbuf[1][7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(10),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(13),
      O => \opbuf[1][7]_i_12_n_0\
    );
\opbuf[1][7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(9),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(12),
      O => \opbuf[1][7]_i_13_n_0\
    );
\opbuf[1][7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(12),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(15),
      O => \opbuf[1][7]_i_14_n_0\
    );
\opbuf[1][7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(11),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(14),
      O => \opbuf[1][7]_i_15_n_0\
    );
\opbuf[1][7]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFE"
    )
        port map (
      I0 => \opbuf[6][7]_i_14_n_0\,
      I1 => \opbuf[1][7]_i_14_n_0\,
      I2 => \opbuf[6][7]_i_13_n_0\,
      I3 => \opbuf[1][7]_i_24_n_0\,
      I4 => \opbuf[6][7]_i_15_n_0\,
      O => \opbuf[1][7]_i_16_n_0\
    );
\opbuf[1][7]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(11),
      I1 => \opbuf_reg[0]3\(8),
      I2 => \opbuf_reg[0]51_in\(10),
      I3 => \wordcnt_reg_n_0_[26]\,
      I4 => \opbuf_reg[0]3\(7),
      O => \opbuf[1][7]_i_18_n_0\
    );
\opbuf[1][7]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(25),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(28),
      O => \opbuf[1][7]_i_19_n_0\
    );
\opbuf[1][7]_i_20\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(24),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(27),
      O => \opbuf[1][7]_i_20_n_0\
    );
\opbuf[1][7]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(27),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(30),
      O => \opbuf[1][7]_i_21_n_0\
    );
\opbuf[1][7]_i_22\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(26),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(29),
      O => \opbuf[1][7]_i_22_n_0\
    );
\opbuf[1][7]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(16),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(19),
      O => \opbuf[1][7]_i_24_n_0\
    );
\opbuf[1][7]_i_25\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(18),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(21),
      O => \opbuf[1][7]_i_25_n_0\
    );
\opbuf[1][7]_i_26\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(17),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(20),
      O => \opbuf[1][7]_i_26_n_0\
    );
\opbuf[1][7]_i_27\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(20),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(23),
      O => \opbuf[1][7]_i_27_n_0\
    );
\opbuf[1][7]_i_28\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(19),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(22),
      O => \opbuf[1][7]_i_28_n_0\
    );
\opbuf[1][7]_i_29\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFE"
    )
        port map (
      I0 => \opbuf[6][7]_i_17_n_0\,
      I1 => \opbuf[1][7]_i_20_n_0\,
      I2 => \opbuf[1][7]_i_40_n_0\,
      I3 => \opbuf[6][7]_i_11_n_0\,
      I4 => \opbuf[1][7]_i_27_n_0\,
      O => \opbuf[1][7]_i_29_n_0\
    );
\opbuf[1][7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \opbuf[1][7]_i_5_n_0\,
      I1 => \opbuf[1][7]_i_6_n_0\,
      I2 => \opbuf[1][7]_i_7_n_0\,
      I3 => \opbuf[1][7]_i_8_n_0\,
      I4 => \opbuf[1][7]_i_9_n_0\,
      I5 => \opbuf[1][7]_i_10_n_0\,
      O => \opbuf[1][7]_i_3_n_0\
    );
\opbuf[1][7]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1D"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(5),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]5\(5),
      O => \opbuf[1][7]_i_30_n_0\
    );
\opbuf[1][7]_i_31\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(13),
      I1 => \opbuf_reg[0]5\(13),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[1][7]_i_31_n_0\
    );
\opbuf[1][7]_i_32\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(12),
      I1 => \opbuf_reg[0]5\(12),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[1][7]_i_32_n_0\
    );
\opbuf[1][7]_i_33\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(11),
      I1 => \opbuf_reg[0]5\(11),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[1][7]_i_33_n_0\
    );
\opbuf[1][7]_i_34\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(10),
      I1 => \opbuf_reg[0]5\(10),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[1][7]_i_34_n_0\
    );
\opbuf[1][7]_i_35\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(9),
      I1 => \opbuf_reg[0]5\(9),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[1][7]_i_35_n_0\
    );
\opbuf[1][7]_i_36\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1D"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(8),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]5\(8),
      O => \opbuf[1][7]_i_36_n_0\
    );
\opbuf[1][7]_i_37\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(7),
      I1 => \opbuf_reg[0]5\(7),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[1][7]_i_37_n_0\
    );
\opbuf[1][7]_i_38\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1D"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(6),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]5\(6),
      O => \opbuf[1][7]_i_38_n_0\
    );
\opbuf[1][7]_i_39\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1D"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(30),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]5\(30),
      O => \opbuf[1][7]_i_39_n_0\
    );
\opbuf[1][7]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(2),
      O => \opbuf[1][7]_i_4_n_0\
    );
\opbuf[1][7]_i_40\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(21),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(24),
      O => \opbuf[1][7]_i_40_n_0\
    );
\opbuf[1][7]_i_43\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(19),
      O => \opbuf[1][7]_i_43_n_0\
    );
\opbuf[1][7]_i_44\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(18),
      O => \opbuf[1][7]_i_44_n_0\
    );
\opbuf[1][7]_i_45\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(17),
      O => \opbuf[1][7]_i_45_n_0\
    );
\opbuf[1][7]_i_46\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(16),
      O => \opbuf[1][7]_i_46_n_0\
    );
\opbuf[1][7]_i_47\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(15),
      O => \opbuf[1][7]_i_47_n_0\
    );
\opbuf[1][7]_i_48\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(14),
      O => \opbuf[1][7]_i_48_n_0\
    );
\opbuf[1][7]_i_49\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(13),
      O => \opbuf[1][7]_i_49_n_0\
    );
\opbuf[1][7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF7FFFFFFE"
    )
        port map (
      I0 => \opbuf[1][7]_i_11_n_0\,
      I1 => \opbuf[1][7]_i_12_n_0\,
      I2 => \opbuf[1][7]_i_13_n_0\,
      I3 => \opbuf[1][7]_i_14_n_0\,
      I4 => \opbuf[1][7]_i_15_n_0\,
      I5 => \opbuf[1][7]_i_16_n_0\,
      O => \opbuf[1][7]_i_5_n_0\
    );
\opbuf[1][7]_i_50\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(12),
      O => \opbuf[1][7]_i_50_n_0\
    );
\opbuf[1][7]_i_51\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(30),
      O => \opbuf[1][7]_i_51_n_0\
    );
\opbuf[1][7]_i_52\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(29),
      O => \opbuf[1][7]_i_52_n_0\
    );
\opbuf[1][7]_i_53\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(28),
      O => \opbuf[1][7]_i_53_n_0\
    );
\opbuf[1][7]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(6),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(9),
      O => \opbuf[1][7]_i_6_n_0\
    );
\opbuf[1][7]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(8),
      I1 => \opbuf_reg[0]3\(5),
      I2 => \opbuf_reg[0]51_in\(7),
      I3 => \wordcnt_reg_n_0_[26]\,
      I4 => \opbuf_reg[0]3\(4),
      O => \opbuf[1][7]_i_7_n_0\
    );
\opbuf[1][7]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFB8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(3),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(6),
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \opbuf[1][7]_i_18_n_0\,
      O => \opbuf[1][7]_i_8_n_0\
    );
\opbuf[1][7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFE7FFFFFFEFFFE"
    )
        port map (
      I0 => \opbuf[1][7]_i_19_n_0\,
      I1 => \opbuf[1][7]_i_20_n_0\,
      I2 => \opbuf[1][7]_i_21_n_0\,
      I3 => \opbuf[1][7]_i_22_n_0\,
      I4 => \opbuf_reg[1][7]_i_23_n_6\,
      I5 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[1][7]_i_9_n_0\
    );
\opbuf[6][7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEEFAFFFA"
    )
        port map (
      I0 => \opbuf[1][7]_i_22_n_0\,
      I1 => \opbuf_reg[0]3\(25),
      I2 => \opbuf_reg[0]51_in\(28),
      I3 => \wordcnt_reg_n_0_[26]\,
      I4 => \opbuf_reg[1][7]_i_23_n_6\,
      I5 => \opbuf[1][7]_i_21_n_0\,
      O => \opbuf[6][7]_i_10_n_0\
    );
\opbuf[6][7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(22),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(25),
      O => \opbuf[6][7]_i_11_n_0\
    );
\opbuf[6][7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(15),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(18),
      O => \opbuf[6][7]_i_13_n_0\
    );
\opbuf[6][7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(13),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(16),
      O => \opbuf[6][7]_i_14_n_0\
    );
\opbuf[6][7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(14),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(17),
      O => \opbuf[6][7]_i_15_n_0\
    );
\opbuf[6][7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]3\(23),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(26),
      O => \opbuf[6][7]_i_17_n_0\
    );
\opbuf[6][7]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(29),
      I1 => \opbuf_reg[0]5\(29),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_18_n_0\
    );
\opbuf[6][7]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(28),
      I1 => \opbuf_reg[0]5\(28),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_19_n_0\
    );
\opbuf[6][7]_i_20\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(27),
      I1 => \opbuf_reg[0]5\(27),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_20_n_0\
    );
\opbuf[6][7]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(26),
      I1 => \opbuf_reg[0]5\(26),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_21_n_0\
    );
\opbuf[6][7]_i_22\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(25),
      I1 => \opbuf_reg[0]5\(25),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_22_n_0\
    );
\opbuf[6][7]_i_23\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(24),
      I1 => \opbuf_reg[0]5\(24),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_23_n_0\
    );
\opbuf[6][7]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(23),
      I1 => \opbuf_reg[0]5\(23),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_24_n_0\
    );
\opbuf[6][7]_i_25\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(22),
      I1 => \opbuf_reg[0]5\(22),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_25_n_0\
    );
\opbuf[6][7]_i_26\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(21),
      I1 => \opbuf_reg[0]5\(21),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_26_n_0\
    );
\opbuf[6][7]_i_27\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(20),
      I1 => \opbuf_reg[0]5\(20),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_27_n_0\
    );
\opbuf[6][7]_i_28\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(19),
      I1 => \opbuf_reg[0]5\(19),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_28_n_0\
    );
\opbuf[6][7]_i_29\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(18),
      I1 => \opbuf_reg[0]5\(18),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_29_n_0\
    );
\opbuf[6][7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(4),
      O => \opbuf[6][7]_i_3_n_0\
    );
\opbuf[6][7]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(17),
      I1 => \opbuf_reg[0]5\(17),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_30_n_0\
    );
\opbuf[6][7]_i_31\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(16),
      I1 => \opbuf_reg[0]5\(16),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_31_n_0\
    );
\opbuf[6][7]_i_32\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(15),
      I1 => \opbuf_reg[0]5\(15),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_32_n_0\
    );
\opbuf[6][7]_i_33\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(14),
      I1 => \opbuf_reg[0]5\(14),
      I2 => \wordcnt_reg_n_0_[26]\,
      O => \opbuf[6][7]_i_33_n_0\
    );
\opbuf[6][7]_i_35\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(27),
      O => \opbuf[6][7]_i_35_n_0\
    );
\opbuf[6][7]_i_36\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(26),
      O => \opbuf[6][7]_i_36_n_0\
    );
\opbuf[6][7]_i_37\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(25),
      O => \opbuf[6][7]_i_37_n_0\
    );
\opbuf[6][7]_i_38\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(24),
      O => \opbuf[6][7]_i_38_n_0\
    );
\opbuf[6][7]_i_39\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(23),
      O => \opbuf[6][7]_i_39_n_0\
    );
\opbuf[6][7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \opbuf[6][7]_i_5_n_0\,
      I1 => \opbuf[6][7]_i_6_n_0\,
      I2 => \opbuf[6][7]_i_7_n_0\,
      I3 => \opbuf[6][7]_i_8_n_0\,
      I4 => \opbuf[6][7]_i_9_n_0\,
      I5 => \opbuf[6][7]_i_10_n_0\,
      O => \opbuf[6][7]_i_4_n_0\
    );
\opbuf[6][7]_i_40\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(22),
      O => \opbuf[6][7]_i_40_n_0\
    );
\opbuf[6][7]_i_41\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(21),
      O => \opbuf[6][7]_i_41_n_0\
    );
\opbuf[6][7]_i_42\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(20),
      O => \opbuf[6][7]_i_42_n_0\
    );
\opbuf[6][7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEFEA"
    )
        port map (
      I0 => \opbuf[6][7]_i_11_n_0\,
      I1 => \opbuf_reg[0]3\(21),
      I2 => \wordcnt_reg_n_0_[26]\,
      I3 => \opbuf_reg[0]51_in\(24),
      I4 => \opbuf[1][7]_i_12_n_0\,
      I5 => \opbuf[1][7]_i_13_n_0\,
      O => \opbuf[6][7]_i_5_n_0\
    );
\opbuf[6][7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEFEA"
    )
        port map (
      I0 => \opbuf[1][7]_i_27_n_0\,
      I1 => \opbuf_reg[0]3\(19),
      I2 => \wordcnt_reg_n_0_[26]\,
      I3 => \opbuf_reg[0]51_in\(22),
      I4 => \opbuf[1][7]_i_14_n_0\,
      I5 => \opbuf[1][7]_i_15_n_0\,
      O => \opbuf[6][7]_i_6_n_0\
    );
\opbuf[6][7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCFFFFFFFCFAFAF"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(9),
      I1 => \opbuf_reg[0]3\(6),
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \opbuf_reg[0]3\(3),
      I4 => \wordcnt_reg_n_0_[26]\,
      I5 => \opbuf_reg[0]51_in\(6),
      O => \opbuf[6][7]_i_7_n_0\
    );
\opbuf[6][7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \opbuf[6][7]_i_13_n_0\,
      I1 => \opbuf[1][7]_i_24_n_0\,
      I2 => \opbuf[1][7]_i_7_n_0\,
      I3 => \opbuf[1][7]_i_18_n_0\,
      I4 => \opbuf[6][7]_i_14_n_0\,
      I5 => \opbuf[6][7]_i_15_n_0\,
      O => \opbuf[6][7]_i_8_n_0\
    );
\opbuf[6][7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEFEA"
    )
        port map (
      I0 => \opbuf[1][7]_i_25_n_0\,
      I1 => \opbuf_reg[0]3\(17),
      I2 => \wordcnt_reg_n_0_[26]\,
      I3 => \opbuf_reg[0]51_in\(20),
      I4 => \opbuf[1][7]_i_20_n_0\,
      I5 => \opbuf[6][7]_i_17_n_0\,
      O => \opbuf[6][7]_i_9_n_0\
    );
\opbuf_reg[0][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_7,
      Q => \opbuf_reg_n_0_[0][0]\
    );
\opbuf_reg[0][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_6,
      Q => \opbuf_reg_n_0_[0][1]\
    );
\opbuf_reg[0][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_5,
      Q => \opbuf_reg_n_0_[0][2]\
    );
\opbuf_reg[0][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_4,
      Q => \opbuf_reg_n_0_[0][3]\
    );
\opbuf_reg[0][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_3,
      Q => \opbuf_reg_n_0_[0][4]\
    );
\opbuf_reg[0][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_2,
      Q => \opbuf_reg_n_0_[0][5]\
    );
\opbuf_reg[0][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_1,
      Q => \opbuf_reg_n_0_[0][6]\
    );
\opbuf_reg[0][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_0,
      Q => \opbuf_reg_n_0_[0][7]\
    );
\opbuf_reg[1][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => \opbuf[1]_56\(0),
      Q => \opbuf_reg[1]_45\(0)
    );
\opbuf_reg[1][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => \opbuf[1]_56\(1),
      Q => \opbuf_reg[1]_45\(1)
    );
\opbuf_reg[1][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => \opbuf[1]_56\(2),
      Q => \opbuf_reg[1]_45\(2)
    );
\opbuf_reg[1][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => \opbuf[1]_56\(3),
      Q => \opbuf_reg[1]_45\(3)
    );
\opbuf_reg[1][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => \opbuf[1]_56\(4),
      Q => \opbuf_reg[1]_45\(4)
    );
\opbuf_reg[1][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => \opbuf[1]_56\(5),
      Q => \opbuf_reg[1]_45\(5)
    );
\opbuf_reg[1][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => \opbuf[1]_56\(6),
      Q => \opbuf_reg[1]_45\(6)
    );
\opbuf_reg[1][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => \opbuf[1]_56\(7),
      Q => \opbuf_reg[1]_45\(7)
    );
\opbuf_reg[1][7]_i_17\: unisim.vcomponents.CARRY8
     port map (
      CI => \opbuf[1][7]_i_30_n_0\,
      CI_TOP => '0',
      CO(7) => \opbuf_reg[1][7]_i_17_n_0\,
      CO(6) => \opbuf_reg[1][7]_i_17_n_1\,
      CO(5) => \opbuf_reg[1][7]_i_17_n_2\,
      CO(4) => \opbuf_reg[1][7]_i_17_n_3\,
      CO(3) => \opbuf_reg[1][7]_i_17_n_4\,
      CO(2) => \opbuf_reg[1][7]_i_17_n_5\,
      CO(1) => \opbuf_reg[1][7]_i_17_n_6\,
      CO(0) => \opbuf_reg[1][7]_i_17_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \opbuf_reg[0]3\(10 downto 3),
      S(7) => \opbuf[1][7]_i_31_n_0\,
      S(6) => \opbuf[1][7]_i_32_n_0\,
      S(5) => \opbuf[1][7]_i_33_n_0\,
      S(4) => \opbuf[1][7]_i_34_n_0\,
      S(3) => \opbuf[1][7]_i_35_n_0\,
      S(2) => \opbuf[1][7]_i_36_n_0\,
      S(1) => \opbuf[1][7]_i_37_n_0\,
      S(0) => \opbuf[1][7]_i_38_n_0\
    );
\opbuf_reg[1][7]_i_23\: unisim.vcomponents.CARRY8
     port map (
      CI => \opbuf_reg[6][7]_i_12_n_0\,
      CI_TOP => '0',
      CO(7 downto 2) => \NLW_opbuf_reg[1][7]_i_23_CO_UNCONNECTED\(7 downto 2),
      CO(1) => \opbuf_reg[1][7]_i_23_n_6\,
      CO(0) => \NLW_opbuf_reg[1][7]_i_23_CO_UNCONNECTED\(0),
      DI(7 downto 0) => B"00000000",
      O(7 downto 1) => \NLW_opbuf_reg[1][7]_i_23_O_UNCONNECTED\(7 downto 1),
      O(0) => \opbuf_reg[0]3\(27),
      S(7 downto 1) => B"0000001",
      S(0) => \opbuf[1][7]_i_39_n_0\
    );
\opbuf_reg[1][7]_i_41\: unisim.vcomponents.CARRY8
     port map (
      CI => \txAXIS_tdata_reg[31]_i_12_n_0\,
      CI_TOP => '0',
      CO(7) => \opbuf_reg[1][7]_i_41_n_0\,
      CO(6) => \opbuf_reg[1][7]_i_41_n_1\,
      CO(5) => \opbuf_reg[1][7]_i_41_n_2\,
      CO(4) => \opbuf_reg[1][7]_i_41_n_3\,
      CO(3) => \opbuf_reg[1][7]_i_41_n_4\,
      CO(2) => \opbuf_reg[1][7]_i_41_n_5\,
      CO(1) => \opbuf_reg[1][7]_i_41_n_6\,
      CO(0) => \opbuf_reg[1][7]_i_41_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \opbuf_reg[0]5\(19 downto 12),
      S(7) => \opbuf[1][7]_i_43_n_0\,
      S(6) => \opbuf[1][7]_i_44_n_0\,
      S(5) => \opbuf[1][7]_i_45_n_0\,
      S(4) => \opbuf[1][7]_i_46_n_0\,
      S(3) => \opbuf[1][7]_i_47_n_0\,
      S(2) => \opbuf[1][7]_i_48_n_0\,
      S(1) => \opbuf[1][7]_i_49_n_0\,
      S(0) => \opbuf[1][7]_i_50_n_0\
    );
\opbuf_reg[1][7]_i_42\: unisim.vcomponents.CARRY8
     port map (
      CI => \opbuf_reg[6][7]_i_34_n_0\,
      CI_TOP => '0',
      CO(7 downto 2) => \NLW_opbuf_reg[1][7]_i_42_CO_UNCONNECTED\(7 downto 2),
      CO(1) => \opbuf_reg[1][7]_i_42_n_6\,
      CO(0) => \opbuf_reg[1][7]_i_42_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 3) => \NLW_opbuf_reg[1][7]_i_42_O_UNCONNECTED\(7 downto 3),
      O(2 downto 0) => \opbuf_reg[0]5\(30 downto 28),
      S(7 downto 3) => B"00000",
      S(2) => \opbuf[1][7]_i_51_n_0\,
      S(1) => \opbuf[1][7]_i_52_n_0\,
      S(0) => \opbuf[1][7]_i_53_n_0\
    );
\opbuf_reg[2][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_315,
      Q => \opbuf_reg_n_0_[2][0]\
    );
\opbuf_reg[2][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_314,
      Q => \opbuf_reg_n_0_[2][1]\
    );
\opbuf_reg[2][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_313,
      Q => \opbuf_reg_n_0_[2][2]\
    );
\opbuf_reg[2][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_312,
      Q => \opbuf_reg_n_0_[2][3]\
    );
\opbuf_reg[2][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_311,
      Q => \opbuf_reg_n_0_[2][4]\
    );
\opbuf_reg[2][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_310,
      Q => \opbuf_reg_n_0_[2][5]\
    );
\opbuf_reg[2][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_309,
      Q => \opbuf_reg_n_0_[2][6]\
    );
\opbuf_reg[2][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_57,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_308,
      Q => \opbuf_reg_n_0_[2][7]\
    );
\opbuf_reg[5][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_299,
      Q => \opbuf_reg[5]_47\(0)
    );
\opbuf_reg[5][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_298,
      Q => \opbuf_reg[5]_47\(1)
    );
\opbuf_reg[5][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_297,
      Q => \opbuf_reg[5]_47\(2)
    );
\opbuf_reg[5][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_296,
      Q => \opbuf_reg[5]_47\(3)
    );
\opbuf_reg[5][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_295,
      Q => \opbuf_reg[5]_47\(4)
    );
\opbuf_reg[5][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_294,
      Q => \opbuf_reg[5]_47\(5)
    );
\opbuf_reg[5][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_293,
      Q => \opbuf_reg[5]_47\(6)
    );
\opbuf_reg[5][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_292,
      Q => \opbuf_reg[5]_47\(7)
    );
\opbuf_reg[6][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_307,
      Q => \opbuf_reg[6]_46\(0)
    );
\opbuf_reg[6][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_306,
      Q => \opbuf_reg[6]_46\(1)
    );
\opbuf_reg[6][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_305,
      Q => \opbuf_reg[6]_46\(2)
    );
\opbuf_reg[6][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_304,
      Q => \opbuf_reg[6]_46\(3)
    );
\opbuf_reg[6][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_303,
      Q => \opbuf_reg[6]_46\(4)
    );
\opbuf_reg[6][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_302,
      Q => \opbuf_reg[6]_46\(5)
    );
\opbuf_reg[6][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_301,
      Q => \opbuf_reg[6]_46\(6)
    );
\opbuf_reg[6][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_55,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_300,
      Q => \opbuf_reg[6]_46\(7)
    );
\opbuf_reg[6][7]_i_12\: unisim.vcomponents.CARRY8
     port map (
      CI => \opbuf_reg[6][7]_i_16_n_0\,
      CI_TOP => '0',
      CO(7) => \opbuf_reg[6][7]_i_12_n_0\,
      CO(6) => \opbuf_reg[6][7]_i_12_n_1\,
      CO(5) => \opbuf_reg[6][7]_i_12_n_2\,
      CO(4) => \opbuf_reg[6][7]_i_12_n_3\,
      CO(3) => \opbuf_reg[6][7]_i_12_n_4\,
      CO(2) => \opbuf_reg[6][7]_i_12_n_5\,
      CO(1) => \opbuf_reg[6][7]_i_12_n_6\,
      CO(0) => \opbuf_reg[6][7]_i_12_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \opbuf_reg[0]3\(26 downto 19),
      S(7) => \opbuf[6][7]_i_18_n_0\,
      S(6) => \opbuf[6][7]_i_19_n_0\,
      S(5) => \opbuf[6][7]_i_20_n_0\,
      S(4) => \opbuf[6][7]_i_21_n_0\,
      S(3) => \opbuf[6][7]_i_22_n_0\,
      S(2) => \opbuf[6][7]_i_23_n_0\,
      S(1) => \opbuf[6][7]_i_24_n_0\,
      S(0) => \opbuf[6][7]_i_25_n_0\
    );
\opbuf_reg[6][7]_i_16\: unisim.vcomponents.CARRY8
     port map (
      CI => \opbuf_reg[1][7]_i_17_n_0\,
      CI_TOP => '0',
      CO(7) => \opbuf_reg[6][7]_i_16_n_0\,
      CO(6) => \opbuf_reg[6][7]_i_16_n_1\,
      CO(5) => \opbuf_reg[6][7]_i_16_n_2\,
      CO(4) => \opbuf_reg[6][7]_i_16_n_3\,
      CO(3) => \opbuf_reg[6][7]_i_16_n_4\,
      CO(2) => \opbuf_reg[6][7]_i_16_n_5\,
      CO(1) => \opbuf_reg[6][7]_i_16_n_6\,
      CO(0) => \opbuf_reg[6][7]_i_16_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \opbuf_reg[0]3\(18 downto 11),
      S(7) => \opbuf[6][7]_i_26_n_0\,
      S(6) => \opbuf[6][7]_i_27_n_0\,
      S(5) => \opbuf[6][7]_i_28_n_0\,
      S(4) => \opbuf[6][7]_i_29_n_0\,
      S(3) => \opbuf[6][7]_i_30_n_0\,
      S(2) => \opbuf[6][7]_i_31_n_0\,
      S(1) => \opbuf[6][7]_i_32_n_0\,
      S(0) => \opbuf[6][7]_i_33_n_0\
    );
\opbuf_reg[6][7]_i_34\: unisim.vcomponents.CARRY8
     port map (
      CI => \opbuf_reg[1][7]_i_41_n_0\,
      CI_TOP => '0',
      CO(7) => \opbuf_reg[6][7]_i_34_n_0\,
      CO(6) => \opbuf_reg[6][7]_i_34_n_1\,
      CO(5) => \opbuf_reg[6][7]_i_34_n_2\,
      CO(4) => \opbuf_reg[6][7]_i_34_n_3\,
      CO(3) => \opbuf_reg[6][7]_i_34_n_4\,
      CO(2) => \opbuf_reg[6][7]_i_34_n_5\,
      CO(1) => \opbuf_reg[6][7]_i_34_n_6\,
      CO(0) => \opbuf_reg[6][7]_i_34_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \opbuf_reg[0]5\(27 downto 20),
      S(7) => \opbuf[6][7]_i_35_n_0\,
      S(6) => \opbuf[6][7]_i_36_n_0\,
      S(5) => \opbuf[6][7]_i_37_n_0\,
      S(4) => \opbuf[6][7]_i_38_n_0\,
      S(3) => \opbuf[6][7]_i_39_n_0\,
      S(2) => \opbuf[6][7]_i_40_n_0\,
      S(1) => \opbuf[6][7]_i_41_n_0\,
      S(0) => \opbuf[6][7]_i_42_n_0\
    );
\pollbuf_reg[0][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_42,
      Q => \pollbuf_reg[0]_49\(0)
    );
\pollbuf_reg[0][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_41,
      Q => \pollbuf_reg[0]_49\(1)
    );
\pollbuf_reg[0][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_40,
      Q => \pollbuf_reg[0]_49\(2)
    );
\pollbuf_reg[0][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_39,
      Q => \pollbuf_reg[0]_49\(3)
    );
\pollbuf_reg[0][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_38,
      Q => \pollbuf_reg[0]_49\(4)
    );
\pollbuf_reg[0][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_37,
      Q => \pollbuf_reg[0]_49\(5)
    );
\pollbuf_reg[0][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_36,
      Q => \pollbuf_reg[0]_49\(6)
    );
\pollbuf_reg[0][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_35,
      Q => \pollbuf_reg[0]_49\(7)
    );
\pollbuf_reg[1][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_266,
      Q => \pollbuf_reg[1]_50\(0)
    );
\pollbuf_reg[1][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_265,
      Q => \pollbuf_reg[1]_50\(1)
    );
\pollbuf_reg[1][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_264,
      Q => \pollbuf_reg[1]_50\(2)
    );
\pollbuf_reg[1][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_263,
      Q => \pollbuf_reg[1]_50\(3)
    );
\pollbuf_reg[1][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_262,
      Q => \pollbuf_reg[1]_50\(4)
    );
\pollbuf_reg[1][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_261,
      Q => \pollbuf_reg[1]_50\(5)
    );
\pollbuf_reg[1][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_260,
      Q => \pollbuf_reg[1]_50\(6)
    );
\pollbuf_reg[1][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_259,
      Q => \pollbuf_reg[1]_50\(7)
    );
\pollbuf_reg[3][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_47,
      Q => \pollbuf_reg[3]_51\(1)
    );
\pollbuf_reg[3][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_46,
      Q => \pollbuf_reg[3]_51\(2)
    );
\pollbuf_reg[3][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[3]_55\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_45,
      Q => \pollbuf_reg[3]_51\(5)
    );
\pollbuf_reg[4][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_33,
      Q => \pollbuf_reg[4]_52\(0)
    );
\pollbuf_reg[4][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_32,
      Q => \pollbuf_reg[4]_52\(1)
    );
\pollbuf_reg[4][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_31,
      Q => \pollbuf_reg[4]_52\(2)
    );
\pollbuf_reg[4][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_30,
      Q => \pollbuf_reg[4]_52\(3)
    );
\pollbuf_reg[4][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_29,
      Q => \pollbuf_reg[4]_52\(4)
    );
\pollbuf_reg[4][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_28,
      Q => \pollbuf_reg[4]_52\(5)
    );
\pollbuf_reg[4][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_27,
      Q => \pollbuf_reg[4]_52\(6)
    );
\pollbuf_reg[4][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_26,
      Q => \pollbuf_reg[4]_52\(7)
    );
\pollbuf_reg[5][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_25,
      Q => \pollbuf_reg[5]_53\(0)
    );
\pollbuf_reg[5][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_24,
      Q => \pollbuf_reg[5]_53\(1)
    );
\pollbuf_reg[5][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_23,
      Q => \pollbuf_reg[5]_53\(2)
    );
\pollbuf_reg[5][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_22,
      Q => \pollbuf_reg[5]_53\(3)
    );
\pollbuf_reg[5][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_21,
      Q => \pollbuf_reg[5]_53\(4)
    );
\pollbuf_reg[5][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_20,
      Q => \pollbuf_reg[5]_53\(5)
    );
\pollbuf_reg[5][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_19,
      Q => \pollbuf_reg[5]_53\(6)
    );
\pollbuf_reg[5][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \pollbuf[5]_54\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_18,
      Q => \pollbuf_reg[5]_53\(7)
    );
\resid[0]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(0),
      I2 => \^q\(3),
      I3 => \^q\(1),
      I4 => \^q\(2),
      O => \resid[0]_i_2__0_n_0\
    );
\resid_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_344,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_189,
      Q => \resid_reg_n_0_[0]\
    );
\resid_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_344,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_188,
      Q => \resid_reg_n_0_[1]\
    );
\retbuf[0][4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[1]\,
      I2 => \stateOp[4]_i_17_n_0\,
      I3 => \tixVController_reg_n_0_[2]\,
      O => \retbuf[0][4]_i_2_n_0\
    );
\retbuf[0][6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \resid_reg_n_0_[0]\,
      I1 => \resid_reg_n_0_[1]\,
      O => \retbuf[0][6]_i_2_n_0\
    );
\retbuf[0][6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000040"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \retbuf[0][4]_i_2_n_0\,
      O => \retbuf[0][6]_i_3_n_0\
    );
\retbuf[0][7]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000200"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(3),
      I2 => \resid_reg_n_0_[1]\,
      I3 => \^q\(4),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => \retbuf[0][7]_i_3__0_n_0\
    );
\retbuf[0][7]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \retbuf[0][7]_i_4__0_n_0\
    );
\retbuf[1][7]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"010101FF"
    )
        port map (
      I0 => ixRetbufCrc(1),
      I1 => ixRetbufCrc(5),
      I2 => ixRetbufCrc(2),
      I3 => \resid_reg_n_0_[1]\,
      I4 => \resid_reg_n_0_[0]\,
      O => \retbuf[1][7]_i_3__0_n_0\
    );
\retbuf[2][7]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEFFFFF"
    )
        port map (
      I0 => \stateOp[4]_i_17_n_0\,
      I1 => \tixVController_reg_n_0_[0]\,
      I2 => \retbuf[2][7]_i_6__0_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \^q\(2),
      O => \retbuf[2][7]_i_3__0_n_0\
    );
\retbuf[2][7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFD"
    )
        port map (
      I0 => \tixVController_reg_n_0_[1]\,
      I1 => \stateOp_next[3]_i_3_n_0\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \tixVCommand_reg_n_0_[1]\,
      I4 => \tixVCommand_reg_n_0_[0]\,
      O => \retbuf[2][7]_i_4_n_0\
    );
\retbuf[2][7]_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[0]\,
      I1 => \tixVCommand_reg_n_0_[1]\,
      I2 => \stateOp_next[3]_i_3_n_0\,
      O => \retbuf[2][7]_i_5__0_n_0\
    );
\retbuf[2][7]_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(4),
      O => \retbuf[2][7]_i_6__0_n_0\
    );
\retbuf[33][7]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => ixRetbufCrc(1),
      I1 => ixRetbufCrc(5),
      I2 => ixRetbufCrc(2),
      O => \retbuf[33][7]_i_3__0_n_0\
    );
\retbuf[36][7]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"404040FF"
    )
        port map (
      I0 => ixRetbufCrc(2),
      I1 => ixRetbufCrc(5),
      I2 => ixRetbufCrc(1),
      I3 => \resid_reg_n_0_[1]\,
      I4 => \resid_reg_n_0_[0]\,
      O => \retbuf[36][7]_i_3__0_n_0\
    );
\retbuf[37][7]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1F111111"
    )
        port map (
      I0 => \resid_reg_n_0_[1]\,
      I1 => \resid_reg_n_0_[0]\,
      I2 => ixRetbufCrc(1),
      I3 => ixRetbufCrc(2),
      I4 => ixRetbufCrc(5),
      O => \retbuf[37][7]_i_3__0_n_0\
    );
\retbuf[39][7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEFFFFFFFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \resid_reg_n_0_[0]\,
      I3 => \resid_reg_n_0_[1]\,
      I4 => \^q\(0),
      I5 => \^q\(4),
      O => \retbuf[39][7]_i_2__0_n_0\
    );
\retbuf[4][7]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"040404FF"
    )
        port map (
      I0 => ixRetbufCrc(5),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(2),
      I3 => \resid_reg_n_0_[1]\,
      I4 => \resid_reg_n_0_[0]\,
      O => \retbuf[4][7]_i_3__0_n_0\
    );
\retbuf[5][7]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"101010FF"
    )
        port map (
      I0 => ixRetbufCrc(1),
      I1 => ixRetbufCrc(5),
      I2 => ixRetbufCrc(2),
      I3 => \resid_reg_n_0_[1]\,
      I4 => \resid_reg_n_0_[0]\,
      O => \retbuf[5][7]_i_3__0_n_0\
    );
\retbuf[8][5]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => ixRetbufCrc(2),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(5),
      O => \retbuf[8][5]_i_2__0_n_0\
    );
\retbuf[8][7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"404040FF"
    )
        port map (
      I0 => ixRetbufCrc(5),
      I1 => ixRetbufCrc(1),
      I2 => ixRetbufCrc(2),
      I3 => \resid_reg_n_0_[1]\,
      I4 => \resid_reg_n_0_[0]\,
      O => \retbuf[8][7]_i_3_n_0\
    );
\retbuf_reg[0][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_228,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_10,
      Q => \retbuf_reg_n_0_[0][0]\
    );
\retbuf_reg[0][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_228,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_9,
      Q => \retbuf_reg_n_0_[0][1]\
    );
\retbuf_reg[0][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_228,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_8,
      Q => \retbuf_reg_n_0_[0][2]\
    );
\retbuf_reg[0][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_228,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_7,
      Q => \retbuf_reg_n_0_[0][3]\
    );
\retbuf_reg[0][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_228,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_6,
      Q => \retbuf_reg_n_0_[0][4]\
    );
\retbuf_reg[0][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_228,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_5,
      Q => \retbuf_reg_n_0_[0][5]\
    );
\retbuf_reg[0][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_228,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_4,
      Q => \retbuf_reg_n_0_[0][6]\
    );
\retbuf_reg[0][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_228,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_3,
      Q => \retbuf_reg_n_0_[0][7]\
    );
\retbuf_reg[11][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_58,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_130,
      Q => \retbuf_reg_n_0_[11][0]\
    );
\retbuf_reg[11][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_58,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_129,
      Q => \retbuf_reg_n_0_[11][1]\
    );
\retbuf_reg[11][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_58,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_8,
      Q => \retbuf_reg_n_0_[11][2]\
    );
\retbuf_reg[11][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_58,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_27,
      Q => \retbuf_reg_n_0_[11][3]\
    );
\retbuf_reg[11][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_58,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_133,
      Q => \retbuf_reg_n_0_[11][4]\
    );
\retbuf_reg[11][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_58,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_127,
      Q => \retbuf_reg_n_0_[11][5]\
    );
\retbuf_reg[11][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_58,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_132,
      Q => \retbuf_reg_n_0_[11][6]\
    );
\retbuf_reg[11][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_58,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_3,
      Q => \retbuf_reg_n_0_[11][7]\
    );
\retbuf_reg[14][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_58,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_128,
      Q => \retbuf_reg_n_0_[14][4]\
    );
\retbuf_reg[15][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_58,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_124,
      Q => \retbuf_reg_n_0_[15][1]\
    );
\retbuf_reg[15][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_58,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_125,
      Q => \retbuf_reg_n_0_[15][2]\
    );
\retbuf_reg[15][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_58,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_131,
      Q => \retbuf_reg_n_0_[15][3]\
    );
\retbuf_reg[1][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_227,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_213,
      Q => \retbuf_reg_n_0_[1][0]\
    );
\retbuf_reg[1][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_227,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_212,
      Q => \retbuf_reg_n_0_[1][1]\
    );
\retbuf_reg[1][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_227,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_211,
      Q => \retbuf_reg_n_0_[1][2]\
    );
\retbuf_reg[1][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_227,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_210,
      Q => \retbuf_reg_n_0_[1][3]\
    );
\retbuf_reg[1][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_227,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_209,
      Q => \retbuf_reg_n_0_[1][4]\
    );
\retbuf_reg[1][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_227,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_208,
      Q => \retbuf_reg_n_0_[1][5]\
    );
\retbuf_reg[1][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_227,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_207,
      Q => \retbuf_reg_n_0_[1][6]\
    );
\retbuf_reg[1][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_227,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_206,
      Q => \retbuf_reg_n_0_[1][7]\
    );
\retbuf_reg[23][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_58,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_126,
      Q => \retbuf_reg_n_0_[23][6]\
    );
\retbuf_reg[2][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_64,
      Q => \retbuf_reg_n_0_[2][0]\
    );
\retbuf_reg[2][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_63,
      Q => \retbuf_reg_n_0_[2][1]\
    );
\retbuf_reg[2][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_62,
      Q => \retbuf_reg_n_0_[2][2]\
    );
\retbuf_reg[2][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_61,
      Q => \retbuf_reg_n_0_[2][3]\
    );
\retbuf_reg[2][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_60,
      Q => \retbuf_reg_n_0_[2][4]\
    );
\retbuf_reg[2][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_59,
      Q => \retbuf_reg_n_0_[2][5]\
    );
\retbuf_reg[2][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_58,
      Q => \retbuf_reg_n_0_[2][6]\
    );
\retbuf_reg[2][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_57,
      Q => \retbuf_reg_n_0_[2][7]\
    );
\retbuf_reg[31][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_58,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_115,
      Q => \retbuf_reg_n_0_[31][0]\
    );
\retbuf_reg[32][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_220,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_130,
      Q => \retbuf_reg_n_0_[32][0]\
    );
\retbuf_reg[32][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_220,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_129,
      Q => \retbuf_reg_n_0_[32][1]\
    );
\retbuf_reg[32][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_220,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_8,
      Q => \retbuf_reg_n_0_[32][2]\
    );
\retbuf_reg[32][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_220,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_27,
      Q => \retbuf_reg_n_0_[32][3]\
    );
\retbuf_reg[32][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_220,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_128,
      Q => \retbuf_reg_n_0_[32][4]\
    );
\retbuf_reg[32][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_220,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_127,
      Q => \retbuf_reg_n_0_[32][5]\
    );
\retbuf_reg[32][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_220,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_126,
      Q => \retbuf_reg_n_0_[32][6]\
    );
\retbuf_reg[32][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_220,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_3,
      Q => \retbuf_reg_n_0_[32][7]\
    );
\retbuf_reg[33][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_222,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_106,
      Q => \retbuf_reg_n_0_[33][0]\
    );
\retbuf_reg[33][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_222,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_105,
      Q => \retbuf_reg_n_0_[33][1]\
    );
\retbuf_reg[33][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_222,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_104,
      Q => \retbuf_reg_n_0_[33][2]\
    );
\retbuf_reg[33][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_222,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_103,
      Q => \retbuf_reg_n_0_[33][3]\
    );
\retbuf_reg[33][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_222,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_102,
      Q => \retbuf_reg_n_0_[33][4]\
    );
\retbuf_reg[33][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_222,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_101,
      Q => \retbuf_reg_n_0_[33][5]\
    );
\retbuf_reg[33][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_222,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_100,
      Q => \retbuf_reg_n_0_[33][6]\
    );
\retbuf_reg[33][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_222,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_99,
      Q => \retbuf_reg_n_0_[33][7]\
    );
\retbuf_reg[35][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_221,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_130,
      Q => \retbuf_reg_n_0_[35][0]\
    );
\retbuf_reg[35][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_221,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_129,
      Q => \retbuf_reg_n_0_[35][1]\
    );
\retbuf_reg[35][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_221,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_8,
      Q => \retbuf_reg_n_0_[35][2]\
    );
\retbuf_reg[35][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_221,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_27,
      Q => \retbuf_reg_n_0_[35][3]\
    );
\retbuf_reg[35][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_221,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_133,
      Q => \retbuf_reg_n_0_[35][4]\
    );
\retbuf_reg[35][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_221,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_127,
      Q => \retbuf_reg_n_0_[35][5]\
    );
\retbuf_reg[35][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_221,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_132,
      Q => \retbuf_reg_n_0_[35][6]\
    );
\retbuf_reg[35][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_221,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_3,
      Q => \retbuf_reg_n_0_[35][7]\
    );
\retbuf_reg[36][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_43,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_98,
      Q => \retbuf_reg_n_0_[36][0]\
    );
\retbuf_reg[36][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_43,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_97,
      Q => \retbuf_reg_n_0_[36][1]\
    );
\retbuf_reg[36][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_43,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_96,
      Q => \retbuf_reg_n_0_[36][2]\
    );
\retbuf_reg[36][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_43,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_95,
      Q => \retbuf_reg_n_0_[36][3]\
    );
\retbuf_reg[36][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_43,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_94,
      Q => \retbuf_reg_n_0_[36][4]\
    );
\retbuf_reg[36][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_43,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_93,
      Q => \retbuf_reg_n_0_[36][5]\
    );
\retbuf_reg[36][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_43,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_92,
      Q => \retbuf_reg_n_0_[36][6]\
    );
\retbuf_reg[36][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_43,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_91,
      Q => \retbuf_reg_n_0_[36][7]\
    );
\retbuf_reg[37][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_267,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_90,
      Q => \retbuf_reg_n_0_[37][0]\
    );
\retbuf_reg[37][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_267,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_89,
      Q => \retbuf_reg_n_0_[37][1]\
    );
\retbuf_reg[37][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_267,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_88,
      Q => \retbuf_reg_n_0_[37][2]\
    );
\retbuf_reg[37][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_267,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_87,
      Q => \retbuf_reg_n_0_[37][3]\
    );
\retbuf_reg[37][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_267,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_86,
      Q => \retbuf_reg_n_0_[37][4]\
    );
\retbuf_reg[37][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_267,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_85,
      Q => \retbuf_reg_n_0_[37][5]\
    );
\retbuf_reg[37][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_267,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_84,
      Q => \retbuf_reg_n_0_[37][6]\
    );
\retbuf_reg[37][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_267,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_83,
      Q => \retbuf_reg_n_0_[37][7]\
    );
\retbuf_reg[38][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \opbuf[0]1\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_123,
      Q => \retbuf_reg_n_0_[38][0]\
    );
\retbuf_reg[38][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \opbuf[0]1\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_122,
      Q => \retbuf_reg_n_0_[38][1]\
    );
\retbuf_reg[38][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \opbuf[0]1\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_121,
      Q => \retbuf_reg_n_0_[38][2]\
    );
\retbuf_reg[38][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \opbuf[0]1\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_120,
      Q => \retbuf_reg_n_0_[38][3]\
    );
\retbuf_reg[38][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \opbuf[0]1\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_119,
      Q => \retbuf_reg_n_0_[38][4]\
    );
\retbuf_reg[38][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \opbuf[0]1\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_118,
      Q => \retbuf_reg_n_0_[38][5]\
    );
\retbuf_reg[38][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \opbuf[0]1\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_117,
      Q => \retbuf_reg_n_0_[38][6]\
    );
\retbuf_reg[38][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \opbuf[0]1\,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_116,
      Q => \retbuf_reg_n_0_[38][7]\
    );
\retbuf_reg[39][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_326,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_123,
      Q => \retbuf_reg_n_0_[39][0]\
    );
\retbuf_reg[39][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_326,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_122,
      Q => \retbuf_reg_n_0_[39][1]\
    );
\retbuf_reg[39][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_326,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_121,
      Q => \retbuf_reg_n_0_[39][2]\
    );
\retbuf_reg[39][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_326,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_120,
      Q => \retbuf_reg_n_0_[39][3]\
    );
\retbuf_reg[39][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_326,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_119,
      Q => \retbuf_reg_n_0_[39][4]\
    );
\retbuf_reg[39][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_326,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_118,
      Q => \retbuf_reg_n_0_[39][5]\
    );
\retbuf_reg[39][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_326,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_117,
      Q => \retbuf_reg_n_0_[39][6]\
    );
\retbuf_reg[39][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_326,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_116,
      Q => \retbuf_reg_n_0_[39][7]\
    );
\retbuf_reg[3][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_226,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_72,
      Q => \retbuf_reg_n_0_[3][0]\
    );
\retbuf_reg[3][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_226,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_71,
      Q => \retbuf_reg_n_0_[3][1]\
    );
\retbuf_reg[3][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_226,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_70,
      Q => \retbuf_reg_n_0_[3][2]\
    );
\retbuf_reg[3][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_226,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_69,
      Q => \retbuf_reg_n_0_[3][3]\
    );
\retbuf_reg[3][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_226,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_68,
      Q => \retbuf_reg_n_0_[3][4]\
    );
\retbuf_reg[3][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_226,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_67,
      Q => \retbuf_reg_n_0_[3][5]\
    );
\retbuf_reg[3][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_226,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_66,
      Q => \retbuf_reg_n_0_[3][6]\
    );
\retbuf_reg[3][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_226,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_65,
      Q => \retbuf_reg_n_0_[3][7]\
    );
\retbuf_reg[4][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_225,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_205,
      Q => \retbuf_reg_n_0_[4][0]\
    );
\retbuf_reg[4][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_225,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_204,
      Q => \retbuf_reg_n_0_[4][1]\
    );
\retbuf_reg[4][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_225,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_203,
      Q => \retbuf_reg_n_0_[4][2]\
    );
\retbuf_reg[4][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_225,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_202,
      Q => \retbuf_reg_n_0_[4][3]\
    );
\retbuf_reg[4][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_225,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_201,
      Q => \retbuf_reg_n_0_[4][4]\
    );
\retbuf_reg[4][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_225,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_200,
      Q => \retbuf_reg_n_0_[4][5]\
    );
\retbuf_reg[4][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_225,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_199,
      Q => \retbuf_reg_n_0_[4][6]\
    );
\retbuf_reg[4][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_225,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_198,
      Q => \retbuf_reg_n_0_[4][7]\
    );
\retbuf_reg[5][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_224,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_197,
      Q => \retbuf_reg_n_0_[5][0]\
    );
\retbuf_reg[5][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_224,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_196,
      Q => \retbuf_reg_n_0_[5][1]\
    );
\retbuf_reg[5][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_224,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_195,
      Q => \retbuf_reg_n_0_[5][2]\
    );
\retbuf_reg[5][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_224,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_194,
      Q => \retbuf_reg_n_0_[5][3]\
    );
\retbuf_reg[5][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_224,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_193,
      Q => \retbuf_reg_n_0_[5][4]\
    );
\retbuf_reg[5][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_224,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_192,
      Q => \retbuf_reg_n_0_[5][5]\
    );
\retbuf_reg[5][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_224,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_191,
      Q => \retbuf_reg_n_0_[5][6]\
    );
\retbuf_reg[5][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_224,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_190,
      Q => \retbuf_reg_n_0_[5][7]\
    );
\retbuf_reg[6][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_80,
      Q => \retbuf_reg_n_0_[6][0]\
    );
\retbuf_reg[6][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_79,
      Q => \retbuf_reg_n_0_[6][1]\
    );
\retbuf_reg[6][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_78,
      Q => \retbuf_reg_n_0_[6][2]\
    );
\retbuf_reg[6][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_77,
      Q => \retbuf_reg_n_0_[6][3]\
    );
\retbuf_reg[6][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_76,
      Q => \retbuf_reg_n_0_[6][4]\
    );
\retbuf_reg[6][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_75,
      Q => \retbuf_reg_n_0_[6][5]\
    );
\retbuf_reg[6][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_74,
      Q => \retbuf_reg_n_0_[6][6]\
    );
\retbuf_reg[6][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_59,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_73,
      Q => \retbuf_reg_n_0_[6][7]\
    );
\retbuf_reg[7][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_219,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_130,
      Q => \retbuf_reg[7]_48\(0)
    );
\retbuf_reg[7][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_219,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_129,
      Q => \retbuf_reg[7]_48\(1)
    );
\retbuf_reg[7][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_219,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_8,
      Q => \retbuf_reg[7]_48\(2)
    );
\retbuf_reg[7][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_219,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_27,
      Q => \retbuf_reg[7]_48\(3)
    );
\retbuf_reg[7][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_219,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_133,
      Q => \retbuf_reg[7]_48\(4)
    );
\retbuf_reg[7][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_219,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_127,
      Q => \retbuf_reg[7]_48\(5)
    );
\retbuf_reg[7][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_219,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_132,
      Q => \retbuf_reg[7]_48\(6)
    );
\retbuf_reg[7][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_219,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_3,
      Q => \retbuf_reg[7]_48\(7)
    );
\retbuf_reg[8][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_223,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_114,
      Q => \retbuf_reg_n_0_[8][0]\
    );
\retbuf_reg[8][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_223,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_113,
      Q => \retbuf_reg_n_0_[8][1]\
    );
\retbuf_reg[8][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_223,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_112,
      Q => \retbuf_reg_n_0_[8][2]\
    );
\retbuf_reg[8][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_223,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_111,
      Q => \retbuf_reg_n_0_[8][3]\
    );
\retbuf_reg[8][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_223,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_110,
      Q => \retbuf_reg_n_0_[8][4]\
    );
\retbuf_reg[8][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_223,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_109,
      Q => \retbuf_reg_n_0_[8][5]\
    );
\retbuf_reg[8][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_223,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_108,
      Q => \retbuf_reg_n_0_[8][6]\
    );
\retbuf_reg[8][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_223,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_107,
      Q => \retbuf_reg_n_0_[8][7]\
    );
\rxlen[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01000082"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => \^q\(3),
      O => \rxlen[1]_i_3_n_0\
    );
\rxlen_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_131,
      Q => rxlen(1)
    );
\stateOp[0]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FC07CC0"
    )
        port map (
      I0 => \stateOp_reg[4]_i_5_n_5\,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => crcAXIS_tlast_sig_reg_n_0,
      O => \stateOp[0]_i_5__0_n_0\
    );
\stateOp[0]_i_7__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => crcAXIS_tlast_sig_reg_n_0,
      O => \stateOp[0]_i_7__0_n_0\
    );
\stateOp[1]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFAAAABFBFBAAABF"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      I5 => stateOp_next(1),
      O => \stateOp[1]_i_3__3_n_0\
    );
\stateOp[1]_i_4__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      O => \stateOp[1]_i_4__4_n_0\
    );
\stateOp[2]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF9391FFFFFFFF"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => crcAXIS_tlast_sig_reg_n_0,
      I4 => \^q\(3),
      I5 => \^q\(4),
      O => \stateOp[2]_i_4__1_n_0\
    );
\stateOp[2]_i_6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[5]\,
      I1 => \tixVBuffer_reg_n_0_[4]\,
      I2 => \tixVBuffer_reg_n_0_[6]\,
      I3 => \tixVBuffer_reg_n_0_[7]\,
      O => \stateOp[2]_i_6__0_n_0\
    );
\stateOp[3]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FF000000CB00"
    )
        port map (
      I0 => crcAXIS_tlast_sig_reg_n_0,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(4),
      I4 => \^q\(3),
      I5 => \^q\(2),
      O => \stateOp[3]_i_3__0_n_0\
    );
\stateOp[3]_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      O => \stateOp[3]_i_5__0_n_0\
    );
\stateOp[3]_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(2),
      O => \stateOp[3]_i_6__0_n_0\
    );
\stateOp[3]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF1FFF00001FFF"
    )
        port map (
      I0 => stateOp_next(3),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \^q\(3),
      I5 => \^q\(4),
      O => \stateOp[3]_i_7__0_n_0\
    );
\stateOp[3]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(4),
      I3 => \^q\(1),
      O => \stateOp[3]_i_9_n_0\
    );
\stateOp[4]_i_12\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[30]\,
      O => \stateOp[4]_i_12_n_0\
    );
\stateOp[4]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \wordcnt_reg_n_0_[28]\,
      I1 => \wordcnt_reg_n_0_[29]\,
      I2 => \wordcnt_reg_n_0_[27]\,
      O => \stateOp[4]_i_13_n_0\
    );
\stateOp[4]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(30),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(29),
      O => \stateOp[4]_i_14_n_0\
    );
\stateOp[4]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00B7FDB6"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \stateOp[4]_i_15_n_0\
    );
\stateOp[4]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[0]\,
      I1 => \tixVCommand_reg_n_0_[1]\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \stateOp_next[3]_i_3_n_0\,
      O => \stateOp[4]_i_16_n_0\
    );
\stateOp[4]_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \tixVController_reg_n_0_[3]\,
      I1 => \tixVController_reg_n_0_[4]\,
      I2 => \tixVController_reg_n_0_[5]\,
      I3 => \tixVController_reg_n_0_[7]\,
      I4 => \tixVController_reg_n_0_[6]\,
      O => \stateOp[4]_i_17_n_0\
    );
\stateOp[4]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \stateOp_next[4]_i_4__0_n_0\,
      I1 => \stateOp_next[3]_i_2_n_0\,
      O => \stateOp[4]_i_18_n_0\
    );
\stateOp[4]_i_20\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(26),
      I1 => \opbuf_reg[0]51_in\(28),
      I2 => \opbuf_reg[0]51_in\(27),
      O => \stateOp[4]_i_20_n_0\
    );
\stateOp[4]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(24),
      I1 => \opbuf_reg[0]51_in\(25),
      I2 => \opbuf_reg[0]51_in\(23),
      O => \stateOp[4]_i_21_n_0\
    );
\stateOp[4]_i_22\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(20),
      I1 => \opbuf_reg[0]51_in\(22),
      I2 => \opbuf_reg[0]51_in\(21),
      O => \stateOp[4]_i_22_n_0\
    );
\stateOp[4]_i_23\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(17),
      I1 => \opbuf_reg[0]51_in\(19),
      I2 => \opbuf_reg[0]51_in\(18),
      O => \stateOp[4]_i_23_n_0\
    );
\stateOp[4]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(14),
      I1 => \opbuf_reg[0]51_in\(16),
      I2 => \opbuf_reg[0]51_in\(15),
      O => \stateOp[4]_i_24_n_0\
    );
\stateOp[4]_i_25\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(12),
      I1 => \opbuf_reg[0]51_in\(13),
      I2 => \opbuf_reg[0]51_in\(11),
      O => \stateOp[4]_i_25_n_0\
    );
\stateOp[4]_i_26\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1001"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(10),
      I1 => \opbuf_reg[0]51_in\(9),
      I2 => \wordcntLast_reg_n_0_[3]\,
      I3 => \opbuf_reg[0]51_in\(8),
      O => \stateOp[4]_i_26_n_0\
    );
\stateOp[4]_i_27\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"09000009"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(6),
      I1 => \wordcntLast_reg_n_0_[1]\,
      I2 => \opbuf_reg[0]51_in\(7),
      I3 => \wordcntLast_reg_n_0_[0]\,
      I4 => \opbuf_reg[0]51_in\(5),
      O => \stateOp[4]_i_27_n_0\
    );
\stateOp[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1008C400"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \^q\(4),
      O => \stateOp[4]_i_3_n_0\
    );
\stateOp[4]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01FF37BE"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \^q\(0),
      O => \stateOp[4]_i_4__0_n_0\
    );
\stateOp[4]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055555155"
    )
        port map (
      I0 => \stateOp[4]_i_15_n_0\,
      I1 => \stateOp[4]_i_16_n_0\,
      I2 => \tixVController_reg_n_0_[1]\,
      I3 => \tixVController_reg_n_0_[0]\,
      I4 => \stateOp[4]_i_17_n_0\,
      I5 => \stateOp[4]_i_18_n_0\,
      O => \stateOp[4]_i_6__0_n_0\
    );
\stateOp[4]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000500840004008"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => stateOp_next(4),
      O => \stateOp[4]_i_9_n_0\
    );
\stateOp_next[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateOp_next[4]_i_3__0_n_0\,
      I1 => \stateOp_next[2]_i_3_n_0\,
      O => \stateOp_next[0]_i_2_n_0\
    );
\stateOp_next[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => \stateOp_next[2]_i_4_n_0\,
      I1 => \len_reg_n_0_[14]\,
      I2 => \tixVBuffer_reg_n_0_[1]\,
      I3 => \tixVBuffer_reg_n_0_[0]\,
      I4 => \len_reg_n_0_[12]\,
      I5 => \stateOp_next[2]_i_5_n_0\,
      O => \stateOp_next[2]_i_2_n_0\
    );
\stateOp_next[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => \stateOp_next[2]_i_6_n_0\,
      I1 => \stateOp_next[2]_i_7_n_0\,
      I2 => tixVBufxfop(0),
      I3 => tixVBufxfop(3),
      I4 => tixVBufxfop(6),
      I5 => tixVBufxfop(7),
      O => \stateOp_next[2]_i_3_n_0\
    );
\stateOp_next[2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \tixVBuffer_reg_n_0_[3]\,
      I1 => \tixVBuffer_reg_n_0_[2]\,
      I2 => \len_reg_n_0_[6]\,
      I3 => \len_reg_n_0_[7]\,
      O => \stateOp_next[2]_i_4_n_0\
    );
\stateOp_next[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \stateOp_next[2]_i_8_n_0\,
      I1 => \len_reg_n_0_[10]\,
      I2 => \len_reg_n_0_[9]\,
      I3 => \len_reg_n_0_[2]\,
      I4 => \stateOp_next[2]_i_9_n_0\,
      I5 => \stateOp[2]_i_6__0_n_0\,
      O => \stateOp_next[2]_i_5_n_0\
    );
\stateOp_next[2]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \stateOp[2]_i_6__0_n_0\,
      I1 => \tixVBuffer_reg_n_0_[0]\,
      I2 => \tixVBuffer_reg_n_0_[1]\,
      I3 => \tixVBuffer_reg_n_0_[2]\,
      I4 => \tixVBuffer_reg_n_0_[3]\,
      O => \stateOp_next[2]_i_6_n_0\
    );
\stateOp_next[2]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => tixVBufxfop(1),
      I1 => tixVBufxfop(2),
      I2 => tixVBufxfop(5),
      I3 => tixVBufxfop(4),
      O => \stateOp_next[2]_i_7_n_0\
    );
\stateOp_next[2]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \len_reg_n_0_[13]\,
      I1 => \len_reg_n_0_[15]\,
      I2 => \len_reg_n_0_[8]\,
      I3 => \len_reg_n_0_[11]\,
      O => \stateOp_next[2]_i_8_n_0\
    );
\stateOp_next[2]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \len_reg_n_0_[5]\,
      I1 => \len_reg_n_0_[0]\,
      I2 => \len_reg_n_0_[4]\,
      I3 => \len_reg_n_0_[3]\,
      O => \stateOp_next[2]_i_9_n_0\
    );
\stateOp_next[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000002000000"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[1]\,
      I1 => \stateOp_next[3]_i_3_n_0\,
      I2 => \stateOp_next[3]_i_4_n_0\,
      I3 => \tixVCommand_reg_n_0_[0]\,
      I4 => \tixVController_reg_n_0_[3]\,
      I5 => \stateOp_next[3]_i_5_n_0\,
      O => \stateOp_next[3]_i_2_n_0\
    );
\stateOp_next[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[2]\,
      I1 => \tixVCommand_reg_n_0_[5]\,
      I2 => \tixVCommand_reg_n_0_[6]\,
      I3 => \tixVCommand_reg_n_0_[7]\,
      I4 => \tixVCommand_reg_n_0_[3]\,
      I5 => \tixVCommand_reg_n_0_[4]\,
      O => \stateOp_next[3]_i_3_n_0\
    );
\stateOp_next[3]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \tixVController_reg_n_0_[0]\,
      I1 => \tixVController_reg_n_0_[2]\,
      I2 => \tixVController_reg_n_0_[1]\,
      O => \stateOp_next[3]_i_4_n_0\
    );
\stateOp_next[3]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \tixVController_reg_n_0_[6]\,
      I1 => \tixVController_reg_n_0_[7]\,
      I2 => \tixVController_reg_n_0_[5]\,
      I3 => \tixVController_reg_n_0_[4]\,
      O => \stateOp_next[3]_i_5_n_0\
    );
\stateOp_next[4]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DEDEDEDEDEDEDEDF"
    )
        port map (
      I0 => \stateOp_next[3]_i_2_n_0\,
      I1 => \stateOp_next[2]_i_2_n_0\,
      I2 => \len_reg_n_0_[1]\,
      I3 => \stateOp_next[4]_i_4__0_n_0\,
      I4 => \ixRetbufCrc[2]_i_2_n_0\,
      I5 => lenRet1,
      O => \stateOp_next[4]_i_3__0_n_0\
    );
\stateOp_next[4]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \stateOp_next[4]_i_5__0_n_0\,
      I1 => \tixVCommand_reg_n_0_[0]\,
      I2 => \tixVCommand_reg_n_0_[1]\,
      I3 => \stateOp_next[4]_i_6__0_n_0\,
      O => \stateOp_next[4]_i_4__0_n_0\
    );
\stateOp_next[4]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \stateOp[4]_i_17_n_0\,
      I1 => \tixVController_reg_n_0_[1]\,
      I2 => \tixVController_reg_n_0_[2]\,
      I3 => \tixVController_reg_n_0_[0]\,
      O => \stateOp_next[4]_i_5__0_n_0\
    );
\stateOp_next[4]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \tixVCommand_reg_n_0_[4]\,
      I1 => \tixVCommand_reg_n_0_[3]\,
      I2 => \tixVCommand_reg_n_0_[7]\,
      I3 => \tixVCommand_reg_n_0_[6]\,
      I4 => \tixVCommand_reg_n_0_[5]\,
      O => \stateOp_next[4]_i_6__0_n_0\
    );
\stateOp_next_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_327,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_129,
      Q => stateOp_next(0)
    );
\stateOp_next_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_327,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_128,
      Q => stateOp_next(1)
    );
\stateOp_next_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_327,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_127,
      Q => stateOp_next(2)
    );
\stateOp_next_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_327,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_126,
      Q => stateOp_next(3)
    );
\stateOp_next_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_327,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_125,
      Q => stateOp_next(4)
    );
\stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_178,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_185,
      Q => \^q\(0)
    );
\stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_178,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_184,
      Q => \^q\(1)
    );
\stateOp_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_178,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_183,
      Q => \^q\(2)
    );
\stateOp_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_178,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_182,
      Q => \^q\(3)
    );
\stateOp_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_178,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_181,
      Q => \^q\(4)
    );
\stateOp_reg[4]_i_11\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \stateOp_reg[4]_i_11_n_0\,
      CO(6) => \stateOp_reg[4]_i_11_n_1\,
      CO(5) => \stateOp_reg[4]_i_11_n_2\,
      CO(4) => \stateOp_reg[4]_i_11_n_3\,
      CO(3) => \stateOp_reg[4]_i_11_n_4\,
      CO(2) => \stateOp_reg[4]_i_11_n_5\,
      CO(1) => \stateOp_reg[4]_i_11_n_6\,
      CO(0) => \stateOp_reg[4]_i_11_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_stateOp_reg[4]_i_11_O_UNCONNECTED\(7 downto 0),
      S(7) => \stateOp[4]_i_20_n_0\,
      S(6) => \stateOp[4]_i_21_n_0\,
      S(5) => \stateOp[4]_i_22_n_0\,
      S(4) => \stateOp[4]_i_23_n_0\,
      S(3) => \stateOp[4]_i_24_n_0\,
      S(2) => \stateOp[4]_i_25_n_0\,
      S(1) => \stateOp[4]_i_26_n_0\,
      S(0) => \stateOp[4]_i_27_n_0\
    );
\stateOp_reg[4]_i_5\: unisim.vcomponents.CARRY8
     port map (
      CI => \stateOp_reg[4]_i_11_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_stateOp_reg[4]_i_5_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \stateOp_reg[4]_i_5_n_5\,
      CO(1) => \stateOp_reg[4]_i_5_n_6\,
      CO(0) => \stateOp_reg[4]_i_5_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_stateOp_reg[4]_i_5_O_UNCONNECTED\(7 downto 0),
      S(7 downto 3) => B"00000",
      S(2) => \stateOp[4]_i_12_n_0\,
      S(1) => \stateOp[4]_i_13_n_0\,
      S(0) => \stateOp[4]_i_14_n_0\
    );
\tixVBuffer_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_275,
      Q => \tixVBuffer_reg_n_0_[0]\
    );
\tixVBuffer_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_274,
      Q => \tixVBuffer_reg_n_0_[1]\
    );
\tixVBuffer_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_273,
      Q => \tixVBuffer_reg_n_0_[2]\
    );
\tixVBuffer_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_272,
      Q => \tixVBuffer_reg_n_0_[3]\
    );
\tixVBuffer_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_271,
      Q => \tixVBuffer_reg_n_0_[4]\
    );
\tixVBuffer_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_270,
      Q => \tixVBuffer_reg_n_0_[5]\
    );
\tixVBuffer_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_269,
      Q => \tixVBuffer_reg_n_0_[6]\
    );
\tixVBuffer_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_268,
      Q => \tixVBuffer_reg_n_0_[7]\
    );
\tixVBufxfop_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_335,
      Q => tixVBufxfop(0)
    );
\tixVBufxfop_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_334,
      Q => tixVBufxfop(1)
    );
\tixVBufxfop_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_333,
      Q => tixVBufxfop(2)
    );
\tixVBufxfop_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_332,
      Q => tixVBufxfop(3)
    );
\tixVBufxfop_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_331,
      Q => tixVBufxfop(4)
    );
\tixVBufxfop_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_330,
      Q => tixVBufxfop(5)
    );
\tixVBufxfop_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_329,
      Q => tixVBufxfop(6)
    );
\tixVBufxfop_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_2,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_328,
      Q => tixVBufxfop(7)
    );
\tixVCommand_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_335,
      Q => \tixVCommand_reg_n_0_[0]\
    );
\tixVCommand_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_334,
      Q => \tixVCommand_reg_n_0_[1]\
    );
\tixVCommand_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_333,
      Q => \tixVCommand_reg_n_0_[2]\
    );
\tixVCommand_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_332,
      Q => \tixVCommand_reg_n_0_[3]\
    );
\tixVCommand_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_331,
      Q => \tixVCommand_reg_n_0_[4]\
    );
\tixVCommand_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_330,
      Q => \tixVCommand_reg_n_0_[5]\
    );
\tixVCommand_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_329,
      Q => \tixVCommand_reg_n_0_[6]\
    );
\tixVCommand_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_328,
      Q => \tixVCommand_reg_n_0_[7]\
    );
\tixVController[7]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \tixVController[7]_i_5__0_n_0\,
      I1 => \tixVController[7]_i_6__0_n_0\,
      I2 => \tixVController[7]_i_7_n_0\,
      I3 => \opbuf_reg_n_0_[2][7]\,
      I4 => \opbuf_reg_n_0_[0][6]\,
      I5 => \opbuf_reg_n_0_[2][2]\,
      O => \tixVController[7]_i_4__0_n_0\
    );
\tixVController[7]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \opbuf_reg_n_0_[2][6]\,
      I1 => \opbuf_reg_n_0_[2][3]\,
      I2 => \opbuf_reg_n_0_[0][0]\,
      I3 => \opbuf_reg_n_0_[2][5]\,
      O => \tixVController[7]_i_5__0_n_0\
    );
\tixVController[7]_i_6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \opbuf_reg_n_0_[0][4]\,
      I1 => \opbuf_reg_n_0_[0][1]\,
      I2 => \opbuf_reg_n_0_[0][7]\,
      I3 => \opbuf_reg_n_0_[2][4]\,
      O => \tixVController[7]_i_6__0_n_0\
    );
\tixVController[7]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \opbuf_reg_n_0_[0][3]\,
      I1 => \opbuf_reg_n_0_[0][2]\,
      I2 => \opbuf_reg_n_0_[0][5]\,
      I3 => \opbuf_reg_n_0_[2][1]\,
      O => \tixVController[7]_i_7_n_0\
    );
\tixVController_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_323,
      Q => \tixVController_reg_n_0_[0]\
    );
\tixVController_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_322,
      Q => \tixVController_reg_n_0_[1]\
    );
\tixVController_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_321,
      Q => \tixVController_reg_n_0_[2]\
    );
\tixVController_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_320,
      Q => \tixVController_reg_n_0_[3]\
    );
\tixVController_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_319,
      Q => \tixVController_reg_n_0_[4]\
    );
\tixVController_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_318,
      Q => \tixVController_reg_n_0_[5]\
    );
\tixVController_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_317,
      Q => \tixVController_reg_n_0_[6]\
    );
\tixVController_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tixVCommand,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_316,
      Q => \tixVController_reg_n_0_[7]\
    );
\txAXIS_tdata[0]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8BBB8B88"
    )
        port map (
      I0 => \txAXIS_tdata[0]_i_4__0_n_0\,
      I1 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I2 => \retbuf_reg_n_0_[31][0]\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \txAXIS_tdata[0]_i_5_n_0\,
      O => \txAXIS_tdata[0]_i_2__0_n_0\
    );
\txAXIS_tdata[0]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1015DFD5"
    )
        port map (
      I0 => \retbuf_reg_n_0_[32][0]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \retbuf_reg_n_0_[36][0]\,
      O => \txAXIS_tdata[0]_i_4__0_n_0\
    );
\txAXIS_tdata[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[31][0]\,
      I1 => \retbuf_reg_n_0_[8][0]\,
      I2 => \txAXIS_tdata[31]_i_11_n_0\,
      I3 => \retbuf_reg_n_0_[4][0]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][0]\,
      O => \txAXIS_tdata[0]_i_5_n_0\
    );
\txAXIS_tdata[10]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"888AAA8A88888888"
    )
        port map (
      I0 => \txAXIS_tdata[26]_i_4__0_n_0\,
      I1 => \txAXIS_tdata[10]_i_6__0_n_0\,
      I2 => \retbuf_reg_n_0_[15][2]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[11][2]\,
      I5 => \txAXIS_tdata[31]_i_10__0_n_0\,
      O => \txAXIS_tdata[10]_i_3__0_n_0\
    );
\txAXIS_tdata[10]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000002A2AAAA02A2"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I1 => \retbuf_reg_n_0_[33][2]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \retbuf_reg_n_0_[37][2]\,
      I4 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][2]\,
      O => \txAXIS_tdata[10]_i_4__0_n_0\
    );
\txAXIS_tdata[10]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAABABF"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_11_n_0\,
      I1 => \retbuf_reg_n_0_[5][2]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \retbuf_reg_n_0_[1][2]\,
      I4 => \txAXIS_tdata[31]_i_10__0_n_0\,
      O => \txAXIS_tdata[10]_i_6__0_n_0\
    );
\txAXIS_tdata[11]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pollbuf_reg[5]_53\(3),
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \pollbuf_reg[1]_50\(3),
      O => \txAXIS_tdata[11]_i_2__0_n_0\
    );
\txAXIS_tdata[11]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EF89EFEF67010101"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_11_n_0\,
      I1 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I2 => \txAXIS_tdata[11]_i_7__0_n_0\,
      I3 => \retbuf_reg_n_0_[15][3]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg_n_0_[11][3]\,
      O => \txAXIS_tdata[11]_i_5__0_n_0\
    );
\txAXIS_tdata[11]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \retbuf_reg_n_0_[0][3]\,
      I1 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I2 => \retbuf_reg_n_0_[37][3]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[33][3]\,
      O => \txAXIS_tdata[11]_i_6__0_n_0\
    );
\txAXIS_tdata[11]_i_7__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \retbuf_reg_n_0_[5][3]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[1][3]\,
      O => \txAXIS_tdata[11]_i_7__0_n_0\
    );
\txAXIS_tdata[12]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1D"
    )
        port map (
      I0 => \pollbuf_reg[1]_50\(4),
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \pollbuf_reg[5]_53\(4),
      O => \txAXIS_tdata[12]_i_2__0_n_0\
    );
\txAXIS_tdata[12]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505FCFCF505FC0C0"
    )
        port map (
      I0 => \retbuf_reg_n_0_[0][4]\,
      I1 => \txAXIS_tdata[12]_i_5__0_n_0\,
      I2 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I3 => \retbuf_reg_n_0_[14][4]\,
      I4 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I5 => \txAXIS_tdata[12]_i_6__0_n_0\,
      O => \txAXIS_tdata[12]_i_3__0_n_0\
    );
\txAXIS_tdata[12]_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \retbuf_reg_n_0_[37][4]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[33][4]\,
      O => \txAXIS_tdata[12]_i_5__0_n_0\
    );
\txAXIS_tdata[12]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"47444777"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][4]\,
      I1 => \txAXIS_tdata[31]_i_11_n_0\,
      I2 => \retbuf_reg_n_0_[5][4]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[1][4]\,
      O => \txAXIS_tdata[12]_i_6__0_n_0\
    );
\txAXIS_tdata[13]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pollbuf_reg[5]_53\(5),
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \pollbuf_reg[1]_50\(5),
      O => \txAXIS_tdata[13]_i_3__0_n_0\
    );
\txAXIS_tdata[13]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFB8000000B8"
    )
        port map (
      I0 => \retbuf_reg_n_0_[5][5]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[1][5]\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \txAXIS_tdata[31]_i_11_n_0\,
      I5 => \retbuf_reg_n_0_[11][5]\,
      O => \txAXIS_tdata[13]_i_5__0_n_0\
    );
\txAXIS_tdata[13]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \retbuf_reg_n_0_[0][5]\,
      I1 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I2 => \retbuf_reg_n_0_[37][5]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[33][5]\,
      O => \txAXIS_tdata[13]_i_6__0_n_0\
    );
\txAXIS_tdata[14]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1D"
    )
        port map (
      I0 => \pollbuf_reg[1]_50\(6),
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \pollbuf_reg[5]_53\(6),
      O => \txAXIS_tdata[14]_i_2__0_n_0\
    );
\txAXIS_tdata[14]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C0022223FFFEEEE"
    )
        port map (
      I0 => \txAXIS_tdata[14]_i_7__0_n_0\,
      I1 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I2 => \retbuf_reg_n_0_[23][6]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \txAXIS_tdata[31]_i_11_n_0\,
      I5 => \retbuf_reg_n_0_[11][6]\,
      O => \txAXIS_tdata[14]_i_5__0_n_0\
    );
\txAXIS_tdata[14]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"47444777"
    )
        port map (
      I0 => \retbuf_reg_n_0_[0][6]\,
      I1 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I2 => \retbuf_reg_n_0_[37][6]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[33][6]\,
      O => \txAXIS_tdata[14]_i_6__0_n_0\
    );
\txAXIS_tdata[14]_i_7__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \retbuf_reg_n_0_[5][6]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[1][6]\,
      O => \txAXIS_tdata[14]_i_7__0_n_0\
    );
\txAXIS_tdata[15]_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pollbuf_reg[5]_53\(7),
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \pollbuf_reg[1]_50\(7),
      O => \txAXIS_tdata[15]_i_4__0_n_0\
    );
\txAXIS_tdata[15]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFB8000000B8"
    )
        port map (
      I0 => \retbuf_reg_n_0_[5][7]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[1][7]\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \txAXIS_tdata[31]_i_11_n_0\,
      I5 => \retbuf_reg_n_0_[11][7]\,
      O => \txAXIS_tdata[15]_i_6__0_n_0\
    );
\txAXIS_tdata[15]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \retbuf_reg_n_0_[0][7]\,
      I1 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I2 => \retbuf_reg_n_0_[37][7]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[33][7]\,
      O => \txAXIS_tdata[15]_i_7__0_n_0\
    );
\txAXIS_tdata[16]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFEA00EA"
    )
        port map (
      I0 => \txAXIS_tdata[16]_i_3__0_n_0\,
      I1 => \txAXIS_tdata[31]_i_11_n_0\,
      I2 => \retbuf_reg_n_0_[11][0]\,
      I3 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I4 => \txAXIS_tdata[16]_i_4__0_n_0\,
      I5 => \txAXIS_tdata[31]_i_7__0_n_0\,
      O => \txAXIS_tdata[16]_i_2__0_n_0\
    );
\txAXIS_tdata[16]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000FFB8B8"
    )
        port map (
      I0 => \retbuf_reg_n_0_[6][0]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[2][0]\,
      I3 => \txAXIS_tdata[16]_i_5__0_n_0\,
      I4 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I5 => \txAXIS_tdata[31]_i_11_n_0\,
      O => \txAXIS_tdata[16]_i_3__0_n_0\
    );
\txAXIS_tdata[16]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \retbuf_reg_n_0_[0][0]\,
      I1 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I2 => \retbuf_reg_n_0_[38][0]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[31][0]\,
      O => \txAXIS_tdata[16]_i_4__0_n_0\
    );
\txAXIS_tdata[16]_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \retbuf_reg_n_0_[31][0]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[11][0]\,
      O => \txAXIS_tdata[16]_i_5__0_n_0\
    );
\txAXIS_tdata[17]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFDDD111D1"
    )
        port map (
      I0 => \txAXIS_tdata[17]_i_5__0_n_0\,
      I1 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I2 => \retbuf_reg_n_0_[11][1]\,
      I3 => \txAXIS_tdata[31]_i_11_n_0\,
      I4 => \retbuf_reg_n_0_[15][1]\,
      I5 => \txAXIS_tdata[31]_i_5__0_n_0\,
      O => \txAXIS_tdata[17]_i_2__0_n_0\
    );
\txAXIS_tdata[17]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000002A2AAAA02A2"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I1 => \retbuf_reg_n_0_[11][1]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \retbuf_reg_n_0_[38][1]\,
      I4 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][1]\,
      O => \txAXIS_tdata[17]_i_3__0_n_0\
    );
\txAXIS_tdata[17]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F000FFF55335533"
    )
        port map (
      I0 => \retbuf_reg_n_0_[6][1]\,
      I1 => \retbuf_reg_n_0_[2][1]\,
      I2 => \retbuf_reg_n_0_[15][1]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[11][1]\,
      I5 => \txAXIS_tdata[31]_i_11_n_0\,
      O => \txAXIS_tdata[17]_i_5__0_n_0\
    );
\txAXIS_tdata[18]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000015155550151"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_7__0_n_0\,
      I1 => \txAXIS_tdata[18]_i_3__0_n_0\,
      I2 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I3 => \txAXIS_tdata[18]_i_4__0_n_0\,
      I4 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I5 => \txAXIS_tdata[18]_i_5__0_n_0\,
      O => \txAXIS_tdata[18]_i_2__0_n_0\
    );
\txAXIS_tdata[18]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"47444777"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][2]\,
      I1 => \txAXIS_tdata[31]_i_11_n_0\,
      I2 => \retbuf_reg_n_0_[6][2]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[2][2]\,
      O => \txAXIS_tdata[18]_i_3__0_n_0\
    );
\txAXIS_tdata[18]_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \retbuf_reg_n_0_[15][2]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[11][2]\,
      O => \txAXIS_tdata[18]_i_4__0_n_0\
    );
\txAXIS_tdata[18]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0047FF47"
    )
        port map (
      I0 => \retbuf_reg_n_0_[38][2]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[11][2]\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \retbuf_reg_n_0_[0][2]\,
      O => \txAXIS_tdata[18]_i_5__0_n_0\
    );
\txAXIS_tdata[19]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555540400005404"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I1 => \retbuf_reg_n_0_[2][3]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \retbuf_reg_n_0_[6][3]\,
      I4 => \txAXIS_tdata[31]_i_11_n_0\,
      I5 => \retbuf_reg_n_0_[11][3]\,
      O => \txAXIS_tdata[19]_i_2__0_n_0\
    );
\txAXIS_tdata[19]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000002A2AAAA02A2"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I1 => \retbuf_reg_n_0_[15][3]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \retbuf_reg_n_0_[38][3]\,
      I4 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][3]\,
      O => \txAXIS_tdata[19]_i_3__0_n_0\
    );
\txAXIS_tdata[1]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF8D008D"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I1 => \retbuf_reg_n_0_[11][1]\,
      I2 => \txAXIS_tdata[1]_i_5__0_n_0\,
      I3 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I4 => \txAXIS_tdata[1]_i_6_n_0\,
      I5 => \^q\(1),
      O => \txAXIS_tdata[1]_i_3__0_n_0\
    );
\txAXIS_tdata[1]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEDFDDDFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \txAXIS_tdata[7]_i_10_n_0\,
      I2 => \pollbuf_reg[4]_52\(1),
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \pollbuf_reg[0]_49\(1),
      I5 => \^q\(4),
      O => \txAXIS_tdata[1]_i_4__0_n_0\
    );
\txAXIS_tdata[1]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][1]\,
      I1 => \retbuf_reg_n_0_[8][1]\,
      I2 => \txAXIS_tdata[31]_i_11_n_0\,
      I3 => \retbuf_reg_n_0_[4][1]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][1]\,
      O => \txAXIS_tdata[1]_i_5__0_n_0\
    );
\txAXIS_tdata[1]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \retbuf_reg_n_0_[36][1]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[32][1]\,
      O => \txAXIS_tdata[1]_i_6_n_0\
    );
\txAXIS_tdata[20]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"12B7757F12B7202A"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I1 => \retbuf_reg_n_0_[14][4]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \retbuf_reg_n_0_[11][4]\,
      I4 => \txAXIS_tdata[31]_i_11_n_0\,
      I5 => \txAXIS_tdata[20]_i_5__0_n_0\,
      O => \txAXIS_tdata[20]_i_3__0_n_0\
    );
\txAXIS_tdata[20]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"47444777"
    )
        port map (
      I0 => \retbuf_reg_n_0_[0][4]\,
      I1 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I2 => \retbuf_reg_n_0_[38][4]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[11][4]\,
      O => \txAXIS_tdata[20]_i_4__0_n_0\
    );
\txAXIS_tdata[20]_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \retbuf_reg_n_0_[6][4]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[2][4]\,
      O => \txAXIS_tdata[20]_i_5__0_n_0\
    );
\txAXIS_tdata[21]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEAEAEAEFEAE"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I1 => \retbuf_reg_n_0_[11][5]\,
      I2 => \txAXIS_tdata[28]_i_5__0_n_0\,
      I3 => \retbuf_reg_n_0_[2][5]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg_n_0_[6][5]\,
      O => \txAXIS_tdata[21]_i_2__0_n_0\
    );
\txAXIS_tdata[21]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000002A2AAAA02A2"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I1 => \retbuf_reg_n_0_[11][5]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \retbuf_reg_n_0_[38][5]\,
      I4 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][5]\,
      O => \txAXIS_tdata[21]_i_3__0_n_0\
    );
\txAXIS_tdata[22]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB8B8FF00"
    )
        port map (
      I0 => \retbuf_reg_n_0_[6][6]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[2][6]\,
      I3 => \retbuf_reg_n_0_[11][6]\,
      I4 => \txAXIS_tdata[28]_i_5__0_n_0\,
      I5 => \txAXIS_tdata[31]_i_5__0_n_0\,
      O => \txAXIS_tdata[22]_i_2__0_n_0\
    );
\txAXIS_tdata[22]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404C4040404C4C4C"
    )
        port map (
      I0 => \retbuf_reg_n_0_[0][6]\,
      I1 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I2 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I3 => \retbuf_reg_n_0_[38][6]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg_n_0_[23][6]\,
      O => \txAXIS_tdata[22]_i_3__0_n_0\
    );
\txAXIS_tdata[23]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEAEAEAEFEAE"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I1 => \retbuf_reg_n_0_[11][7]\,
      I2 => \txAXIS_tdata[28]_i_5__0_n_0\,
      I3 => \retbuf_reg_n_0_[2][7]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg_n_0_[6][7]\,
      O => \txAXIS_tdata[23]_i_3__0_n_0\
    );
\txAXIS_tdata[23]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000002A2AAAA02A2"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I1 => \retbuf_reg_n_0_[11][7]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \retbuf_reg_n_0_[38][7]\,
      I4 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][7]\,
      O => \txAXIS_tdata[23]_i_4__0_n_0\
    );
\txAXIS_tdata[23]_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^q\(1),
      I1 => \resid_reg_n_0_[1]\,
      O => \txAXIS_tdata[23]_i_5__0_n_0\
    );
\txAXIS_tdata[24]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"400070F0400F7FFF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[31][0]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I3 => \txAXIS_tdata[31]_i_11_n_0\,
      I4 => \retbuf_reg_n_0_[11][0]\,
      I5 => \txAXIS_tdata[24]_i_6__0_n_0\,
      O => \txAXIS_tdata[24]_i_4__0_n_0\
    );
\txAXIS_tdata[24]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0047FF47"
    )
        port map (
      I0 => \retbuf_reg_n_0_[39][0]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[35][0]\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \retbuf_reg_n_0_[0][0]\,
      O => \txAXIS_tdata[24]_i_5__0_n_0\
    );
\txAXIS_tdata[24]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C00A0000C00ACCAA"
    )
        port map (
      I0 => \retbuf_reg_n_0_[3][0]\,
      I1 => \retbuf_reg[7]_48\(0),
      I2 => \opbuf_reg[0]5\(6),
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \wordcnt_reg_n_0_[26]\,
      I5 => \opbuf_reg[0]51_in\(6),
      O => \txAXIS_tdata[24]_i_6__0_n_0\
    );
\txAXIS_tdata[25]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I1 => \pollbuf_reg[3]_51\(1),
      O => \txAXIS_tdata[25]_i_2__0_n_0\
    );
\txAXIS_tdata[25]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400AEEE4E444EEE"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I1 => \txAXIS_tdata[25]_i_7__0_n_0\,
      I2 => \retbuf_reg_n_0_[15][1]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[11][1]\,
      I5 => \txAXIS_tdata[31]_i_11_n_0\,
      O => \txAXIS_tdata[25]_i_5__0_n_0\
    );
\txAXIS_tdata[25]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0047FF47"
    )
        port map (
      I0 => \retbuf_reg_n_0_[39][1]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[35][1]\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \retbuf_reg_n_0_[0][1]\,
      O => \txAXIS_tdata[25]_i_6__0_n_0\
    );
\txAXIS_tdata[25]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7474B8FFFFFFB8FF"
    )
        port map (
      I0 => \opbuf_reg[0]5\(6),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(6),
      I3 => \retbuf_reg_n_0_[3][1]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg[7]_48\(1),
      O => \txAXIS_tdata[25]_i_7__0_n_0\
    );
\txAXIS_tdata[26]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFB800B8"
    )
        port map (
      I0 => \retbuf_reg[7]_48\(2),
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[3][2]\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \retbuf_reg_n_0_[11][2]\,
      I5 => \txAXIS_tdata[31]_i_11_n_0\,
      O => \txAXIS_tdata[26]_i_3__0_n_0\
    );
\txAXIS_tdata[26]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000757F"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_11_n_0\,
      I1 => \retbuf_reg_n_0_[15][2]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \retbuf_reg_n_0_[11][2]\,
      I4 => \txAXIS_tdata[31]_i_5__0_n_0\,
      O => \txAXIS_tdata[26]_i_4__0_n_0\
    );
\txAXIS_tdata[26]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000002A2AAAA02A2"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I1 => \retbuf_reg_n_0_[35][2]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \retbuf_reg_n_0_[39][2]\,
      I4 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][2]\,
      O => \txAXIS_tdata[26]_i_5__0_n_0\
    );
\txAXIS_tdata[27]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000FFB8B8"
    )
        port map (
      I0 => \retbuf_reg[7]_48\(3),
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[3][3]\,
      I3 => \txAXIS_tdata[27]_i_6__0_n_0\,
      I4 => \txAXIS_tdata[31]_i_11_n_0\,
      I5 => \txAXIS_tdata[31]_i_10__0_n_0\,
      O => \txAXIS_tdata[27]_i_2__0_n_0\
    );
\txAXIS_tdata[27]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFFFEAAAAAAAAAAA"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I1 => \retbuf_reg_n_0_[15][3]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \txAXIS_tdata[31]_i_11_n_0\,
      I4 => \retbuf_reg_n_0_[11][3]\,
      I5 => \txAXIS_tdata[31]_i_10__0_n_0\,
      O => \txAXIS_tdata[27]_i_3__0_n_0\
    );
\txAXIS_tdata[27]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000002A2AAAA02A2"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I1 => \retbuf_reg_n_0_[35][3]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \retbuf_reg_n_0_[39][3]\,
      I4 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][3]\,
      O => \txAXIS_tdata[27]_i_4__0_n_0\
    );
\txAXIS_tdata[27]_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \retbuf_reg_n_0_[15][3]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[11][3]\,
      O => \txAXIS_tdata[27]_i_6__0_n_0\
    );
\txAXIS_tdata[28]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB8B8FF00"
    )
        port map (
      I0 => \retbuf_reg[7]_48\(4),
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[3][4]\,
      I3 => \retbuf_reg_n_0_[11][4]\,
      I4 => \txAXIS_tdata[28]_i_5__0_n_0\,
      I5 => \txAXIS_tdata[31]_i_5__0_n_0\,
      O => \txAXIS_tdata[28]_i_2__0_n_0\
    );
\txAXIS_tdata[28]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF474700000000"
    )
        port map (
      I0 => \retbuf_reg_n_0_[39][4]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[35][4]\,
      I3 => \retbuf_reg_n_0_[0][4]\,
      I4 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I5 => \txAXIS_tdata[31]_i_5__0_n_0\,
      O => \txAXIS_tdata[28]_i_3__0_n_0\
    );
\txAXIS_tdata[28]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C0030000C0035555"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(7),
      I1 => \opbuf_reg[0]5\(7),
      I2 => \opbuf_reg[0]5\(6),
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \wordcnt_reg_n_0_[26]\,
      I5 => \opbuf_reg[0]51_in\(6),
      O => \txAXIS_tdata[28]_i_5__0_n_0\
    );
\txAXIS_tdata[29]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800B800B8FFB800"
    )
        port map (
      I0 => \txAXIS_tdata[29]_i_4__0_n_0\,
      I1 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I2 => \txAXIS_tdata[29]_i_5__0_n_0\,
      I3 => \^q\(4),
      I4 => \pollbuf_reg[3]_51\(5),
      I5 => \txAXIS_tdata[31]_i_9__0_n_0\,
      O => \txAXIS_tdata[29]_i_3__0_n_0\
    );
\txAXIS_tdata[29]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \retbuf_reg_n_0_[0][5]\,
      I1 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I2 => \retbuf_reg_n_0_[39][5]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[35][5]\,
      O => \txAXIS_tdata[29]_i_4__0_n_0\
    );
\txAXIS_tdata[29]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFB8000000B8"
    )
        port map (
      I0 => \retbuf_reg[7]_48\(5),
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[3][5]\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \txAXIS_tdata[31]_i_11_n_0\,
      I5 => \retbuf_reg_n_0_[11][5]\,
      O => \txAXIS_tdata[29]_i_5__0_n_0\
    );
\txAXIS_tdata[2]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8BBB8B88"
    )
        port map (
      I0 => \txAXIS_tdata[2]_i_4__0_n_0\,
      I1 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I2 => \retbuf_reg_n_0_[11][2]\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \txAXIS_tdata[2]_i_5__0_n_0\,
      O => \txAXIS_tdata[2]_i_2__0_n_0\
    );
\txAXIS_tdata[2]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1015DFD5"
    )
        port map (
      I0 => \retbuf_reg_n_0_[32][2]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \retbuf_reg_n_0_[36][2]\,
      O => \txAXIS_tdata[2]_i_4__0_n_0\
    );
\txAXIS_tdata[2]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][2]\,
      I1 => \retbuf_reg_n_0_[8][2]\,
      I2 => \txAXIS_tdata[31]_i_11_n_0\,
      I3 => \retbuf_reg_n_0_[4][2]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][2]\,
      O => \txAXIS_tdata[2]_i_5__0_n_0\
    );
\txAXIS_tdata[30]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEAEAAAA"
    )
        port map (
      I0 => \txAXIS_tdata[30]_i_5__0_n_0\,
      I1 => \retbuf_reg_n_0_[11][6]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \retbuf_reg_n_0_[23][6]\,
      I4 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I5 => \txAXIS_tdata[31]_i_5__0_n_0\,
      O => \txAXIS_tdata[30]_i_2__0_n_0\
    );
\txAXIS_tdata[30]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404C4040404C4C4C"
    )
        port map (
      I0 => \retbuf_reg_n_0_[0][6]\,
      I1 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I2 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I3 => \retbuf_reg_n_0_[39][6]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg_n_0_[35][6]\,
      O => \txAXIS_tdata[30]_i_3__0_n_0\
    );
\txAXIS_tdata[30]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00B8B8"
    )
        port map (
      I0 => \retbuf_reg[7]_48\(6),
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[3][6]\,
      I3 => \retbuf_reg_n_0_[11][6]\,
      I4 => \txAXIS_tdata[31]_i_11_n_0\,
      I5 => \txAXIS_tdata[31]_i_10__0_n_0\,
      O => \txAXIS_tdata[30]_i_5__0_n_0\
    );
\txAXIS_tdata[31]_i_10__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55CC5ACC"
    )
        port map (
      I0 => \opbuf_reg[0]5\(7),
      I1 => \opbuf_reg[0]51_in\(7),
      I2 => \opbuf_reg[0]5\(6),
      I3 => \wordcnt_reg_n_0_[26]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      O => \txAXIS_tdata[31]_i_10__0_n_0\
    );
\txAXIS_tdata[31]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2EE2"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(6),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \opbuf_reg[0]5\(6),
      O => \txAXIS_tdata[31]_i_11_n_0\
    );
\txAXIS_tdata[31]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]5\(6),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(6),
      O => \txAXIS_tdata[31]_i_13_n_0\
    );
\txAXIS_tdata[31]_i_14\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(5),
      O => \txAXIS_tdata[31]_i_14_n_0\
    );
\txAXIS_tdata[31]_i_15\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(11),
      O => \txAXIS_tdata[31]_i_15_n_0\
    );
\txAXIS_tdata[31]_i_16\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(10),
      O => \txAXIS_tdata[31]_i_16_n_0\
    );
\txAXIS_tdata[31]_i_17\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(9),
      O => \txAXIS_tdata[31]_i_17_n_0\
    );
\txAXIS_tdata[31]_i_18\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(8),
      O => \txAXIS_tdata[31]_i_18_n_0\
    );
\txAXIS_tdata[31]_i_19\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(7),
      O => \txAXIS_tdata[31]_i_19_n_0\
    );
\txAXIS_tdata[31]_i_20\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \opbuf_reg[0]51_in\(6),
      O => \txAXIS_tdata[31]_i_20_n_0\
    );
\txAXIS_tdata[31]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEEF"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(4),
      I3 => \^q\(3),
      O => \txAXIS_tdata[31]_i_3__0_n_0\
    );
\txAXIS_tdata[31]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFB8000000B8"
    )
        port map (
      I0 => \retbuf_reg[7]_48\(7),
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[3][7]\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \txAXIS_tdata[31]_i_11_n_0\,
      I5 => \retbuf_reg_n_0_[11][7]\,
      O => \txAXIS_tdata[31]_i_4__0_n_0\
    );
\txAXIS_tdata[31]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01FFFEFF0100FE00"
    )
        port map (
      I0 => \opbuf_reg[0]5\(7),
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \txAXIS_tdata[31]_i_13_n_0\,
      I3 => \wordcnt_reg_n_0_[26]\,
      I4 => \opbuf_reg[0]5\(8),
      I5 => \opbuf_reg[0]51_in\(8),
      O => \txAXIS_tdata[31]_i_5__0_n_0\
    );
\txAXIS_tdata[31]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \retbuf_reg_n_0_[0][7]\,
      I1 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I2 => \retbuf_reg_n_0_[39][7]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[35][7]\,
      O => \txAXIS_tdata[31]_i_6__0_n_0\
    );
\txAXIS_tdata[31]_i_7__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(4),
      O => \txAXIS_tdata[31]_i_7__0_n_0\
    );
\txAXIS_tdata[31]_i_9__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \opbuf_reg[0]5\(5),
      I1 => \wordcnt_reg_n_0_[26]\,
      I2 => \opbuf_reg[0]51_in\(5),
      O => \txAXIS_tdata[31]_i_9__0_n_0\
    );
\txAXIS_tdata[3]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8BBB8B88"
    )
        port map (
      I0 => \txAXIS_tdata[3]_i_5__0_n_0\,
      I1 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I2 => \retbuf_reg_n_0_[11][3]\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \txAXIS_tdata[3]_i_6_n_0\,
      O => \txAXIS_tdata[3]_i_3__0_n_0\
    );
\txAXIS_tdata[3]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEDFDDDFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \txAXIS_tdata[7]_i_10_n_0\,
      I2 => \pollbuf_reg[4]_52\(3),
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \pollbuf_reg[0]_49\(3),
      I5 => \^q\(4),
      O => \txAXIS_tdata[3]_i_4__0_n_0\
    );
\txAXIS_tdata[3]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1015DFD5"
    )
        port map (
      I0 => \retbuf_reg_n_0_[32][3]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \retbuf_reg_n_0_[36][3]\,
      O => \txAXIS_tdata[3]_i_5__0_n_0\
    );
\txAXIS_tdata[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][3]\,
      I1 => \retbuf_reg_n_0_[8][3]\,
      I2 => \txAXIS_tdata[31]_i_11_n_0\,
      I3 => \retbuf_reg_n_0_[4][3]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][3]\,
      O => \txAXIS_tdata[3]_i_6_n_0\
    );
\txAXIS_tdata[4]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBB888B8"
    )
        port map (
      I0 => \txAXIS_tdata[4]_i_4__0_n_0\,
      I1 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I2 => \txAXIS_tdata[4]_i_5__0_n_0\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \txAXIS_tdata[4]_i_6__0_n_0\,
      O => \txAXIS_tdata[4]_i_2__0_n_0\
    );
\txAXIS_tdata[4]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1015DFD5"
    )
        port map (
      I0 => \retbuf_reg_n_0_[32][4]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \retbuf_reg_n_0_[36][4]\,
      O => \txAXIS_tdata[4]_i_4__0_n_0\
    );
\txAXIS_tdata[4]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[14][4]\,
      I1 => \retbuf_reg_n_0_[8][4]\,
      I2 => \txAXIS_tdata[31]_i_11_n_0\,
      I3 => \retbuf_reg_n_0_[4][4]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][4]\,
      O => \txAXIS_tdata[4]_i_5__0_n_0\
    );
\txAXIS_tdata[4]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04005400F7FF57FF"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][4]\,
      I1 => \opbuf_reg[0]51_in\(6),
      I2 => \wordcnt_reg_n_0_[26]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \opbuf_reg[0]5\(6),
      I5 => \retbuf_reg_n_0_[14][4]\,
      O => \txAXIS_tdata[4]_i_6__0_n_0\
    );
\txAXIS_tdata[5]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8BBB8B88"
    )
        port map (
      I0 => \txAXIS_tdata[5]_i_5__0_n_0\,
      I1 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I2 => \retbuf_reg_n_0_[11][5]\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \txAXIS_tdata[5]_i_6__0_n_0\,
      O => \txAXIS_tdata[5]_i_3__0_n_0\
    );
\txAXIS_tdata[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEDFDDDFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \txAXIS_tdata[7]_i_10_n_0\,
      I2 => \pollbuf_reg[4]_52\(5),
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \pollbuf_reg[0]_49\(5),
      I5 => \^q\(4),
      O => \txAXIS_tdata[5]_i_4_n_0\
    );
\txAXIS_tdata[5]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1015DFD5"
    )
        port map (
      I0 => \retbuf_reg_n_0_[32][5]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \retbuf_reg_n_0_[36][5]\,
      O => \txAXIS_tdata[5]_i_5__0_n_0\
    );
\txAXIS_tdata[5]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][5]\,
      I1 => \retbuf_reg_n_0_[8][5]\,
      I2 => \txAXIS_tdata[31]_i_11_n_0\,
      I3 => \retbuf_reg_n_0_[4][5]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][5]\,
      O => \txAXIS_tdata[5]_i_6__0_n_0\
    );
\txAXIS_tdata[6]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      O => \txAXIS_tdata[6]_i_2__0_n_0\
    );
\txAXIS_tdata[6]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \txAXIS_tdata[6]_i_6_n_0\,
      I1 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I2 => \txAXIS_tdata[6]_i_7_n_0\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \txAXIS_tdata[6]_i_8__0_n_0\,
      O => \txAXIS_tdata[6]_i_3__0_n_0\
    );
\txAXIS_tdata[6]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0200003C"
    )
        port map (
      I0 => \stateOp_next[0]_i_2_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => \txAXIS_tdata[6]_i_5__0_n_0\
    );
\txAXIS_tdata[6]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEA202A"
    )
        port map (
      I0 => \retbuf_reg_n_0_[32][6]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \retbuf_reg_n_0_[36][6]\,
      O => \txAXIS_tdata[6]_i_6_n_0\
    );
\txAXIS_tdata[6]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFFABFF0800A800"
    )
        port map (
      I0 => \retbuf_reg_n_0_[23][6]\,
      I1 => \opbuf_reg[0]51_in\(6),
      I2 => \wordcnt_reg_n_0_[26]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \opbuf_reg[0]5\(6),
      I5 => \retbuf_reg_n_0_[11][6]\,
      O => \txAXIS_tdata[6]_i_7_n_0\
    );
\txAXIS_tdata[6]_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][6]\,
      I1 => \retbuf_reg_n_0_[8][6]\,
      I2 => \txAXIS_tdata[31]_i_11_n_0\,
      I3 => \retbuf_reg_n_0_[4][6]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][6]\,
      O => \txAXIS_tdata[6]_i_8__0_n_0\
    );
\txAXIS_tdata[7]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      O => \txAXIS_tdata[7]_i_10_n_0\
    );
\txAXIS_tdata[7]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8BBB8B88"
    )
        port map (
      I0 => \txAXIS_tdata[7]_i_8__0_n_0\,
      I1 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I2 => \retbuf_reg_n_0_[11][7]\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \txAXIS_tdata[7]_i_9_n_0\,
      O => \txAXIS_tdata[7]_i_5__0_n_0\
    );
\txAXIS_tdata[7]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEDFDDDFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \txAXIS_tdata[7]_i_10_n_0\,
      I2 => \pollbuf_reg[4]_52\(7),
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \pollbuf_reg[0]_49\(7),
      I5 => \^q\(4),
      O => \txAXIS_tdata[7]_i_6__0_n_0\
    );
\txAXIS_tdata[7]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFFFFFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(4),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => \^q\(1),
      I5 => \stateOp_next[0]_i_2_n_0\,
      O => \txAXIS_tdata[7]_i_7__0_n_0\
    );
\txAXIS_tdata[7]_i_8__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1015DFD5"
    )
        port map (
      I0 => \retbuf_reg_n_0_[32][7]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I3 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I4 => \retbuf_reg_n_0_[36][7]\,
      O => \txAXIS_tdata[7]_i_8__0_n_0\
    );
\txAXIS_tdata[7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][7]\,
      I1 => \retbuf_reg_n_0_[8][7]\,
      I2 => \txAXIS_tdata[31]_i_11_n_0\,
      I3 => \retbuf_reg_n_0_[4][7]\,
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg_n_0_[0][7]\,
      O => \txAXIS_tdata[7]_i_9_n_0\
    );
\txAXIS_tdata[8]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pollbuf_reg[5]_53\(0),
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \pollbuf_reg[1]_50\(0),
      O => \txAXIS_tdata[8]_i_2__0_n_0\
    );
\txAXIS_tdata[8]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \retbuf_reg_n_0_[0][0]\,
      I1 => \txAXIS_tdata[8]_i_5__0_n_0\,
      I2 => \txAXIS_tdata[31]_i_5__0_n_0\,
      I3 => \txAXIS_tdata[8]_i_6__0_n_0\,
      I4 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I5 => \txAXIS_tdata[8]_i_7__0_n_0\,
      O => \txAXIS_tdata[8]_i_3__0_n_0\
    );
\txAXIS_tdata[8]_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \retbuf_reg_n_0_[37][0]\,
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \retbuf_reg_n_0_[33][0]\,
      O => \txAXIS_tdata[8]_i_5__0_n_0\
    );
\txAXIS_tdata[8]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEFEFFFFA2020000"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][0]\,
      I1 => \opbuf_reg[0]51_in\(6),
      I2 => \wordcnt_reg_n_0_[26]\,
      I3 => \opbuf_reg[0]5\(6),
      I4 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I5 => \retbuf_reg_n_0_[31][0]\,
      O => \txAXIS_tdata[8]_i_6__0_n_0\
    );
\txAXIS_tdata[8]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \retbuf_reg_n_0_[11][0]\,
      I1 => \txAXIS_tdata[31]_i_11_n_0\,
      I2 => \retbuf_reg_n_0_[5][0]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[1][0]\,
      O => \txAXIS_tdata[8]_i_7__0_n_0\
    );
\txAXIS_tdata[9]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pollbuf_reg[5]_53\(1),
      I1 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I2 => \pollbuf_reg[1]_50\(1),
      O => \txAXIS_tdata[9]_i_2__0_n_0\
    );
\txAXIS_tdata[9]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFD5FF55CFC0AA00"
    )
        port map (
      I0 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I1 => \retbuf_reg_n_0_[15][1]\,
      I2 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I3 => \retbuf_reg_n_0_[11][1]\,
      I4 => \txAXIS_tdata[31]_i_11_n_0\,
      I5 => \txAXIS_tdata[9]_i_7__0_n_0\,
      O => \txAXIS_tdata[9]_i_5__0_n_0\
    );
\txAXIS_tdata[9]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \retbuf_reg_n_0_[0][1]\,
      I1 => \txAXIS_tdata[31]_i_10__0_n_0\,
      I2 => \retbuf_reg_n_0_[37][1]\,
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \retbuf_reg_n_0_[33][1]\,
      O => \txAXIS_tdata[9]_i_6__0_n_0\
    );
\txAXIS_tdata[9]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C00A0000C00ACCAA"
    )
        port map (
      I0 => \retbuf_reg_n_0_[1][1]\,
      I1 => \retbuf_reg_n_0_[5][1]\,
      I2 => \opbuf_reg[0]5\(6),
      I3 => \txAXIS_tdata[31]_i_9__0_n_0\,
      I4 => \wordcnt_reg_n_0_[26]\,
      I5 => \opbuf_reg[0]51_in\(6),
      O => \txAXIS_tdata[9]_i_7__0_n_0\
    );
\txAXIS_tdata_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_218,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_258,
      Q => \txAXIS_tdata_reg_n_0_[0]\
    );
\txAXIS_tdata_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_217,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_248,
      Q => \txAXIS_tdata_reg_n_0_[10]\
    );
\txAXIS_tdata_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_217,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_247,
      Q => \txAXIS_tdata_reg_n_0_[11]\
    );
\txAXIS_tdata_reg[11]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txAXIS_tdata[11]_i_5__0_n_0\,
      I1 => \txAXIS_tdata[11]_i_6__0_n_0\,
      O => \txAXIS_tdata_reg[11]_i_3_n_0\,
      S => \txAXIS_tdata[31]_i_5__0_n_0\
    );
\txAXIS_tdata_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_217,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_246,
      Q => \txAXIS_tdata_reg_n_0_[12]\
    );
\txAXIS_tdata_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_217,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_245,
      Q => \txAXIS_tdata_reg_n_0_[13]\
    );
\txAXIS_tdata_reg[13]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txAXIS_tdata[13]_i_5__0_n_0\,
      I1 => \txAXIS_tdata[13]_i_6__0_n_0\,
      O => \txAXIS_tdata_reg[13]_i_4_n_0\,
      S => \txAXIS_tdata[31]_i_5__0_n_0\
    );
\txAXIS_tdata_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_217,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_244,
      Q => \txAXIS_tdata_reg_n_0_[14]\
    );
\txAXIS_tdata_reg[14]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txAXIS_tdata[14]_i_5__0_n_0\,
      I1 => \txAXIS_tdata[14]_i_6__0_n_0\,
      O => \txAXIS_tdata_reg[14]_i_3_n_0\,
      S => \txAXIS_tdata[31]_i_5__0_n_0\
    );
\txAXIS_tdata_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_217,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_243,
      Q => \txAXIS_tdata_reg_n_0_[15]\
    );
\txAXIS_tdata_reg[15]_i_5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txAXIS_tdata[15]_i_6__0_n_0\,
      I1 => \txAXIS_tdata[15]_i_7__0_n_0\,
      O => \txAXIS_tdata_reg[15]_i_5_n_0\,
      S => \txAXIS_tdata[31]_i_5__0_n_0\
    );
\txAXIS_tdata_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_216,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_82,
      Q => \txAXIS_tdata_reg_n_0_[16]\
    );
\txAXIS_tdata_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_216,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_242,
      Q => \txAXIS_tdata_reg_n_0_[17]\
    );
\txAXIS_tdata_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_216,
      CLR => \stateOp_reg[0]_0\(0),
      D => myCrc_n_81,
      Q => \txAXIS_tdata_reg_n_0_[18]\
    );
\txAXIS_tdata_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_216,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_241,
      Q => \txAXIS_tdata_reg_n_0_[19]\
    );
\txAXIS_tdata_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_218,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_257,
      Q => \txAXIS_tdata_reg_n_0_[1]\
    );
\txAXIS_tdata_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_216,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_240,
      Q => \txAXIS_tdata_reg_n_0_[20]\
    );
\txAXIS_tdata_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_216,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_239,
      Q => \txAXIS_tdata_reg_n_0_[21]\
    );
\txAXIS_tdata_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_216,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_238,
      Q => \txAXIS_tdata_reg_n_0_[22]\
    );
\txAXIS_tdata_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_216,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_237,
      Q => \txAXIS_tdata_reg_n_0_[23]\
    );
\txAXIS_tdata_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_215,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_236,
      Q => \txAXIS_tdata_reg_n_0_[24]\
    );
\txAXIS_tdata_reg[24]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txAXIS_tdata[24]_i_4__0_n_0\,
      I1 => \txAXIS_tdata[24]_i_5__0_n_0\,
      O => \txAXIS_tdata_reg[24]_i_2_n_0\,
      S => \txAXIS_tdata[31]_i_5__0_n_0\
    );
\txAXIS_tdata_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_215,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_235,
      Q => \txAXIS_tdata_reg_n_0_[25]\
    );
\txAXIS_tdata_reg[25]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txAXIS_tdata[25]_i_5__0_n_0\,
      I1 => \txAXIS_tdata[25]_i_6__0_n_0\,
      O => \txAXIS_tdata_reg[25]_i_3_n_0\,
      S => \txAXIS_tdata[31]_i_5__0_n_0\
    );
\txAXIS_tdata_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_215,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_234,
      Q => \txAXIS_tdata_reg_n_0_[26]\
    );
\txAXIS_tdata_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_215,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_233,
      Q => \txAXIS_tdata_reg_n_0_[27]\
    );
\txAXIS_tdata_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_215,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_232,
      Q => \txAXIS_tdata_reg_n_0_[28]\
    );
\txAXIS_tdata_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_215,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_231,
      Q => \txAXIS_tdata_reg_n_0_[29]\
    );
\txAXIS_tdata_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_218,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_256,
      Q => \txAXIS_tdata_reg_n_0_[2]\
    );
\txAXIS_tdata_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_215,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_230,
      Q => \txAXIS_tdata_reg_n_0_[30]\
    );
\txAXIS_tdata_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_215,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_229,
      Q => \txAXIS_tdata_reg_n_0_[31]\
    );
\txAXIS_tdata_reg[31]_i_12\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \txAXIS_tdata_reg[31]_i_12_n_0\,
      CO(6) => \txAXIS_tdata_reg[31]_i_12_n_1\,
      CO(5) => \txAXIS_tdata_reg[31]_i_12_n_2\,
      CO(4) => \txAXIS_tdata_reg[31]_i_12_n_3\,
      CO(3) => \txAXIS_tdata_reg[31]_i_12_n_4\,
      CO(2) => \txAXIS_tdata_reg[31]_i_12_n_5\,
      CO(1) => \txAXIS_tdata_reg[31]_i_12_n_6\,
      CO(0) => \txAXIS_tdata_reg[31]_i_12_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \txAXIS_tdata[31]_i_14_n_0\,
      DI(0) => '0',
      O(7 downto 1) => \opbuf_reg[0]5\(11 downto 5),
      O(0) => \NLW_txAXIS_tdata_reg[31]_i_12_O_UNCONNECTED\(0),
      S(7) => \txAXIS_tdata[31]_i_15_n_0\,
      S(6) => \txAXIS_tdata[31]_i_16_n_0\,
      S(5) => \txAXIS_tdata[31]_i_17_n_0\,
      S(4) => \txAXIS_tdata[31]_i_18_n_0\,
      S(3) => \txAXIS_tdata[31]_i_19_n_0\,
      S(2) => \txAXIS_tdata[31]_i_20_n_0\,
      S(1) => \opbuf_reg[0]51_in\(5),
      S(0) => '0'
    );
\txAXIS_tdata_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_218,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_255,
      Q => \txAXIS_tdata_reg_n_0_[3]\
    );
\txAXIS_tdata_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_218,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_254,
      Q => \txAXIS_tdata_reg_n_0_[4]\
    );
\txAXIS_tdata_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_218,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_253,
      Q => \txAXIS_tdata_reg_n_0_[5]\
    );
\txAXIS_tdata_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_218,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_252,
      Q => \txAXIS_tdata_reg_n_0_[6]\
    );
\txAXIS_tdata_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_218,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_251,
      Q => \txAXIS_tdata_reg_n_0_[7]\
    );
\txAXIS_tdata_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_217,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_250,
      Q => \txAXIS_tdata_reg_n_0_[8]\
    );
\txAXIS_tdata_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myRxtx_n_217,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_249,
      Q => \txAXIS_tdata_reg_n_0_[9]\
    );
\txAXIS_tdata_reg[9]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txAXIS_tdata[9]_i_5__0_n_0\,
      I1 => \txAXIS_tdata[9]_i_6__0_n_0\,
      O => \txAXIS_tdata_reg[9]_i_3_n_0\,
      S => \txAXIS_tdata[31]_i_5__0_n_0\
    );
\txlen_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[0]_0\(0),
      D => wordcntLast(0),
      Q => \txlen_reg_n_0_[0]\
    );
\txlen_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_53,
      Q => \txlen_reg_n_0_[1]\
    );
\txlen_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myCrc_n_1,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_52,
      Q => \txlen_reg_n_0_[3]\
    );
\wordcntCrcLast_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_375,
      Q => wordcntCrcLast(0)
    );
\wordcntCrcLast_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_365,
      Q => wordcntCrcLast(10)
    );
\wordcntCrcLast_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_364,
      Q => wordcntCrcLast(11)
    );
\wordcntCrcLast_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_363,
      Q => wordcntCrcLast(12)
    );
\wordcntCrcLast_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_362,
      Q => wordcntCrcLast(13)
    );
\wordcntCrcLast_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_361,
      Q => wordcntCrcLast(14)
    );
\wordcntCrcLast_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_360,
      Q => wordcntCrcLast(15)
    );
\wordcntCrcLast_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_359,
      Q => wordcntCrcLast(16)
    );
\wordcntCrcLast_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_358,
      Q => wordcntCrcLast(17)
    );
\wordcntCrcLast_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_357,
      Q => wordcntCrcLast(18)
    );
\wordcntCrcLast_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_356,
      Q => wordcntCrcLast(19)
    );
\wordcntCrcLast_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_374,
      Q => wordcntCrcLast(1)
    );
\wordcntCrcLast_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_355,
      Q => wordcntCrcLast(20)
    );
\wordcntCrcLast_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_354,
      Q => wordcntCrcLast(21)
    );
\wordcntCrcLast_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_353,
      Q => wordcntCrcLast(22)
    );
\wordcntCrcLast_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_352,
      Q => wordcntCrcLast(23)
    );
\wordcntCrcLast_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_351,
      Q => wordcntCrcLast(24)
    );
\wordcntCrcLast_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_373,
      Q => wordcntCrcLast(2)
    );
\wordcntCrcLast_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_372,
      Q => wordcntCrcLast(3)
    );
\wordcntCrcLast_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_371,
      Q => wordcntCrcLast(4)
    );
\wordcntCrcLast_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_370,
      Q => wordcntCrcLast(5)
    );
\wordcntCrcLast_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_369,
      Q => wordcntCrcLast(6)
    );
\wordcntCrcLast_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_368,
      Q => wordcntCrcLast(7)
    );
\wordcntCrcLast_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_367,
      Q => wordcntCrcLast(8)
    );
\wordcntCrcLast_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_34,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_366,
      Q => wordcntCrcLast(9)
    );
\wordcntLast[0]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10200000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => \wordcntLast[0]_i_2__0_n_0\
    );
\wordcntLast[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      O => \wordcntLast[1]_i_2_n_0\
    );
\wordcntLast_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_91,
      CLR => \stateOp_reg[0]_0\(0),
      D => wordcntLast(0),
      Q => \wordcntLast_reg_n_0_[0]\
    );
\wordcntLast_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_91,
      CLR => \stateOp_reg[0]_0\(0),
      D => wordcntLast(1),
      Q => \wordcntLast_reg_n_0_[1]\
    );
\wordcntLast_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_91,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_52,
      Q => \wordcntLast_reg_n_0_[3]\
    );
\wordcnt[30]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(2),
      O => \wordcnt[30]_i_4_n_0\
    );
\wordcnt[30]_i_7__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      O => \wordcnt[30]_i_7__0_n_0\
    );
\wordcnt_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_90,
      Q => \opbuf_reg[0]51_in\(5)
    );
\wordcnt_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_80,
      Q => \opbuf_reg[0]51_in\(15)
    );
\wordcnt_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_79,
      Q => \opbuf_reg[0]51_in\(16)
    );
\wordcnt_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_78,
      Q => \opbuf_reg[0]51_in\(17)
    );
\wordcnt_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_77,
      Q => \opbuf_reg[0]51_in\(18)
    );
\wordcnt_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_76,
      Q => \opbuf_reg[0]51_in\(19)
    );
\wordcnt_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_75,
      Q => \opbuf_reg[0]51_in\(20)
    );
\wordcnt_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_74,
      Q => \opbuf_reg[0]51_in\(21)
    );
\wordcnt_reg[16]_i_2__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[8]_i_2__0_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[16]_i_2__0_n_0\,
      CO(6) => \wordcnt_reg[16]_i_2__0_n_1\,
      CO(5) => \wordcnt_reg[16]_i_2__0_n_2\,
      CO(4) => \wordcnt_reg[16]_i_2__0_n_3\,
      CO(3) => \wordcnt_reg[16]_i_2__0_n_4\,
      CO(2) => \wordcnt_reg[16]_i_2__0_n_5\,
      CO(1) => \wordcnt_reg[16]_i_2__0_n_6\,
      CO(0) => \wordcnt_reg[16]_i_2__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => txlast1(16 downto 9),
      S(7 downto 0) => \opbuf_reg[0]51_in\(21 downto 14)
    );
\wordcnt_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_73,
      Q => \opbuf_reg[0]51_in\(22)
    );
\wordcnt_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_72,
      Q => \opbuf_reg[0]51_in\(23)
    );
\wordcnt_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_71,
      Q => \opbuf_reg[0]51_in\(24)
    );
\wordcnt_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_89,
      Q => \opbuf_reg[0]51_in\(6)
    );
\wordcnt_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_70,
      Q => \opbuf_reg[0]51_in\(25)
    );
\wordcnt_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_69,
      Q => \opbuf_reg[0]51_in\(26)
    );
\wordcnt_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_68,
      Q => \opbuf_reg[0]51_in\(27)
    );
\wordcnt_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_67,
      Q => \opbuf_reg[0]51_in\(28)
    );
\wordcnt_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_66,
      Q => \opbuf_reg[0]51_in\(29)
    );
\wordcnt_reg[24]_i_2__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[16]_i_2__0_n_0\,
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[24]_i_2__0_n_0\,
      CO(6) => \wordcnt_reg[24]_i_2__0_n_1\,
      CO(5) => \wordcnt_reg[24]_i_2__0_n_2\,
      CO(4) => \wordcnt_reg[24]_i_2__0_n_3\,
      CO(3) => \wordcnt_reg[24]_i_2__0_n_4\,
      CO(2) => \wordcnt_reg[24]_i_2__0_n_5\,
      CO(1) => \wordcnt_reg[24]_i_2__0_n_6\,
      CO(0) => \wordcnt_reg[24]_i_2__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => txlast1(24 downto 17),
      S(7 downto 0) => \opbuf_reg[0]51_in\(29 downto 22)
    );
\wordcnt_reg[25]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_65,
      Q => \opbuf_reg[0]51_in\(30)
    );
\wordcnt_reg[26]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_64,
      Q => \wordcnt_reg_n_0_[26]\
    );
\wordcnt_reg[27]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_63,
      Q => \wordcnt_reg_n_0_[27]\
    );
\wordcnt_reg[28]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_62,
      Q => \wordcnt_reg_n_0_[28]\
    );
\wordcnt_reg[29]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_61,
      Q => \wordcnt_reg_n_0_[29]\
    );
\wordcnt_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_88,
      Q => \opbuf_reg[0]51_in\(7)
    );
\wordcnt_reg[30]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_60,
      Q => \wordcnt_reg_n_0_[30]\
    );
\wordcnt_reg[30]_i_6\: unisim.vcomponents.CARRY8
     port map (
      CI => \wordcnt_reg[24]_i_2__0_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_wordcnt_reg[30]_i_6_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \wordcnt_reg[30]_i_6_n_3\,
      CO(3) => \wordcnt_reg[30]_i_6_n_4\,
      CO(2) => \wordcnt_reg[30]_i_6_n_5\,
      CO(1) => \wordcnt_reg[30]_i_6_n_6\,
      CO(0) => \wordcnt_reg[30]_i_6_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 6) => \NLW_wordcnt_reg[30]_i_6_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => txlast1(30 downto 25),
      S(7 downto 6) => B"00",
      S(5) => \wordcnt_reg_n_0_[30]\,
      S(4) => \wordcnt_reg_n_0_[29]\,
      S(3) => \wordcnt_reg_n_0_[28]\,
      S(2) => \wordcnt_reg_n_0_[27]\,
      S(1) => \wordcnt_reg_n_0_[26]\,
      S(0) => \opbuf_reg[0]51_in\(30)
    );
\wordcnt_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_87,
      Q => \opbuf_reg[0]51_in\(8)
    );
\wordcnt_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_86,
      Q => \opbuf_reg[0]51_in\(9)
    );
\wordcnt_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_85,
      Q => \opbuf_reg[0]51_in\(10)
    );
\wordcnt_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_84,
      Q => \opbuf_reg[0]51_in\(11)
    );
\wordcnt_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_83,
      Q => \opbuf_reg[0]51_in\(12)
    );
\wordcnt_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_82,
      Q => \opbuf_reg[0]51_in\(13)
    );
\wordcnt_reg[8]_i_2__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \opbuf_reg[0]51_in\(5),
      CI_TOP => '0',
      CO(7) => \wordcnt_reg[8]_i_2__0_n_0\,
      CO(6) => \wordcnt_reg[8]_i_2__0_n_1\,
      CO(5) => \wordcnt_reg[8]_i_2__0_n_2\,
      CO(4) => \wordcnt_reg[8]_i_2__0_n_3\,
      CO(3) => \wordcnt_reg[8]_i_2__0_n_4\,
      CO(2) => \wordcnt_reg[8]_i_2__0_n_5\,
      CO(1) => \wordcnt_reg[8]_i_2__0_n_6\,
      CO(0) => \wordcnt_reg[8]_i_2__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => txlast1(8 downto 1),
      S(7 downto 0) => \opbuf_reg[0]51_in\(13 downto 6)
    );
\wordcnt_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myRxtx_n_179,
      CLR => \stateOp_reg[0]_0\(0),
      D => myRxtx_n_81,
      Q => \opbuf_reg[0]51_in\(14)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_crossbar_sasd is
  port (
    m_axi_araddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 );
    aresetn : in STD_LOGIC;
    aclk : in STD_LOGIC;
    s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
    m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_crossbar_sasd : entity is "axi_crossbar_v2_1_34_crossbar_sasd";
end design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_crossbar_sasd;

architecture STRUCTURE of design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_crossbar_sasd is
  signal aa_grant_rnw : STD_LOGIC;
  signal addr_arbiter_inst_n_13 : STD_LOGIC;
  signal addr_arbiter_inst_n_14 : STD_LOGIC;
  signal addr_arbiter_inst_n_27 : STD_LOGIC;
  signal addr_arbiter_inst_n_3 : STD_LOGIC;
  signal addr_arbiter_inst_n_8 : STD_LOGIC;
  signal aresetn_d : STD_LOGIC;
  signal m_atarget_enc : STD_LOGIC_VECTOR ( 0 to 0 );
  signal m_atarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m_atarget_hot0 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m_ready_d0 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal m_ready_d0_0 : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal m_ready_d_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal m_valid_i : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal reg_slice_r_n_1 : STD_LOGIC;
  signal reg_slice_r_n_34 : STD_LOGIC;
  signal reset : STD_LOGIC;
  signal sr_rvalid : STD_LOGIC;
begin
addr_arbiter_inst: entity work.design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_addr_arbiter_sasd
     port map (
      D(1 downto 0) => m_ready_d0(1 downto 0),
      E(0) => p_1_in,
      Q(1 downto 0) => m_atarget_hot(1 downto 0),
      SR(0) => reset,
      aa_grant_rnw => aa_grant_rnw,
      aclk => aclk,
      aresetn_d => aresetn_d,
      aresetn_d_reg(0) => addr_arbiter_inst_n_3,
      aresetn_d_reg_0(0) => addr_arbiter_inst_n_14,
      \gen_no_arbiter.grant_rnw_reg_0\ => addr_arbiter_inst_n_8,
      \gen_no_arbiter.grant_rnw_reg_1\ => addr_arbiter_inst_n_13,
      \gen_no_arbiter.m_amesg_i_reg[13]_0\(6) => addr_arbiter_inst_n_27,
      \gen_no_arbiter.m_amesg_i_reg[13]_0\(5) => m_axi_araddr(0),
      \gen_no_arbiter.m_amesg_i_reg[13]_0\(4 downto 0) => m_axi_araddr(5 downto 1),
      \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\(1 downto 0) => m_atarget_hot0(1 downto 0),
      m_atarget_enc(0) => m_atarget_enc(0),
      m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
      m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
      m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
      m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
      m_axi_bready(1 downto 0) => m_axi_bready(1 downto 0),
      m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0),
      m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
      m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
      m_ready_d0(1 downto 0) => m_ready_d0_0(2 downto 1),
      \m_ready_d_reg[0]\ => reg_slice_r_n_1,
      \m_ready_d_reg[0]_0\(0) => reg_slice_r_n_34,
      \m_ready_d_reg[1]\(1 downto 0) => m_ready_d(1 downto 0),
      \m_ready_d_reg[2]\(2 downto 0) => m_ready_d_1(2 downto 0),
      m_valid_i => m_valid_i,
      s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
      s_axi_arready(0) => s_axi_arready(0),
      s_axi_arvalid(0) => s_axi_arvalid(0),
      s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
      s_axi_awready(0) => s_axi_awready(0),
      s_axi_awvalid(0) => s_axi_awvalid(0),
      s_axi_bready(0) => s_axi_bready(0),
      s_axi_bvalid(0) => s_axi_bvalid(0),
      s_axi_rready(0) => s_axi_rready(0),
      s_axi_rvalid(0) => s_axi_rvalid(0),
      s_axi_wready(0) => s_axi_wready(0),
      s_axi_wvalid(0) => s_axi_wvalid(0),
      sr_rvalid => sr_rvalid
    );
aresetn_d_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => aresetn,
      Q => aresetn_d,
      R => '0'
    );
\m_atarget_enc_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => addr_arbiter_inst_n_27,
      Q => m_atarget_enc(0),
      R => reset
    );
\m_atarget_hot_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => m_atarget_hot0(0),
      Q => m_atarget_hot(0),
      R => reset
    );
\m_atarget_hot_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => m_atarget_hot0(1),
      Q => m_atarget_hot(1),
      R => reset
    );
reg_slice_r: entity work.design_1_Vsp_core_0_0_axi_register_slice_v2_1_33_axic_register_slice
     port map (
      E(0) => p_1_in,
      Q(0) => m_ready_d(0),
      SR(0) => reset,
      aa_grant_rnw => aa_grant_rnw,
      aclk => aclk,
      m_atarget_enc(0) => m_atarget_enc(0),
      m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
      m_axi_rready(1 downto 0) => m_axi_rready(1 downto 0),
      m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0),
      \m_payload_i_reg[34]_0\(32 downto 1) => s_axi_rdata(31 downto 0),
      \m_payload_i_reg[34]_0\(0) => reg_slice_r_n_34,
      m_valid_i => m_valid_i,
      m_valid_i_reg_0 => reg_slice_r_n_1,
      rd_req_reg(1 downto 0) => m_atarget_hot(1 downto 0),
      s_axi_rready(0) => s_axi_rready(0),
      s_ready_i_reg_0 => addr_arbiter_inst_n_8,
      sr_rvalid => sr_rvalid
    );
splitter_ar: entity work.\design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_splitter__parameterized0\
     port map (
      D(1 downto 0) => m_ready_d0(1 downto 0),
      Q(1 downto 0) => m_ready_d(1 downto 0),
      SR(0) => addr_arbiter_inst_n_3,
      aclk => aclk
    );
splitter_aw: entity work.design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_splitter
     port map (
      D(1 downto 0) => m_ready_d0_0(2 downto 1),
      Q(2 downto 0) => m_ready_d_1(2 downto 0),
      SR(0) => addr_arbiter_inst_n_14,
      aclk => aclk,
      m_atarget_enc(0) => m_atarget_enc(0),
      m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0),
      \m_ready_d_reg[0]_0\ => addr_arbiter_inst_n_13,
      s_axi_bready(0) => s_axi_bready(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_axis_dwidth_converter_v1_1_32_axis_dwidth_converter is
  port (
    \state_reg[0]\ : out STD_LOGIC;
    \state_reg[1]\ : out STD_LOGIC;
    m_axis_tlast : out STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 );
    m_axis_tid : out STD_LOGIC_VECTOR ( 5 downto 0 );
    m_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axis_tvalid : in STD_LOGIC;
    s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    aclk : in STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
    s_axis_tlast : in STD_LOGIC;
    s_axis_tid : in STD_LOGIC_VECTOR ( 5 downto 0 );
    s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
    aresetn : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_axis_dwidth_converter_v1_1_32_axis_dwidth_converter : entity is "axis_dwidth_converter_v1_1_32_axis_dwidth_converter";
end design_1_Vsp_core_0_0_axis_dwidth_converter_v1_1_32_axis_dwidth_converter;

architecture STRUCTURE of design_1_Vsp_core_0_0_axis_dwidth_converter_v1_1_32_axis_dwidth_converter is
  signal areset_r : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
begin
areset_r_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => aresetn,
      O => p_0_in
    );
areset_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk,
      CE => '1',
      D => p_0_in,
      Q => areset_r,
      R => '0'
    );
\gen_downsizer_conversion.axisc_downsizer_0\: entity work.design_1_Vsp_core_0_0_axis_dwidth_converter_v1_1_32_axisc_downsizer
     port map (
      E(0) => \state_reg[0]\,
      aclk => aclk,
      areset_r => areset_r,
      m_axis_tdata(23 downto 0) => m_axis_tdata(23 downto 0),
      m_axis_tid(5 downto 0) => m_axis_tid(5 downto 0),
      m_axis_tlast => m_axis_tlast,
      m_axis_tuser(0) => m_axis_tuser(0),
      s_axis_tdata(47 downto 0) => s_axis_tdata(47 downto 0),
      s_axis_tid(5 downto 0) => s_axis_tid(5 downto 0),
      s_axis_tkeep(0) => s_axis_tkeep(0),
      s_axis_tlast => s_axis_tlast,
      s_axis_tuser(0) => s_axis_tuser(0),
      s_axis_tvalid => s_axis_tvalid,
      \state_reg[1]_0\ => \state_reg[1]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_bs_top is
  port (
    fifo_wr_clk_0 : out STD_LOGIC;
    rx_bs0_rx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs0_tx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    fifo_empty_2 : out STD_LOGIC;
    rx_bs2_rx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs2_tx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    data_to_fabric_data_rxp0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fifo_empty_4 : out STD_LOGIC;
    rx_bs4_rx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs4_tx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    data_to_fabric_data_rxp1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fifo_empty_6 : out STD_LOGIC;
    rx_bs6_rx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs6_tx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    data_to_fabric_data_rxp2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fifo_empty_8 : out STD_LOGIC;
    rx_bs8_rx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs8_tx_bit_ctrl_out : out STD_LOGIC_VECTOR ( 39 downto 0 );
    data_to_fabric_data_rxp3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    data_to_bs_out : in STD_LOGIC_VECTOR ( 4 downto 0 );
    fifo_rd_clk_0 : in STD_LOGIC;
    rx_bs_rst_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    rx_bs_rst_dly_ext_in : in STD_LOGIC_VECTOR ( 4 downto 0 );
    rx_bs0_rx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs0_tx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    fifo_rd_en_2 : in STD_LOGIC;
    rx_bs2_rx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs2_tx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    fifo_rd_en_4 : in STD_LOGIC;
    rx_bs4_rx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs4_tx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    fifo_rd_en_6 : in STD_LOGIC;
    rx_bs6_rx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs6_tx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    fifo_rd_en_8 : in STD_LOGIC;
    rx_bs8_rx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 );
    rx_bs8_tx_bit_ctrl_in : in STD_LOGIC_VECTOR ( 39 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_bs_top : entity is "high_speed_selectio_wiz_v3_6_10_bs_top";
end design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_bs_top;

architecture STRUCTURE of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_bs_top is
begin
u_rx_bs: entity work.design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_rx_bs
     port map (
      data_to_bs_out(4 downto 0) => data_to_bs_out(4 downto 0),
      data_to_fabric_data_rxp0(7 downto 0) => data_to_fabric_data_rxp0(7 downto 0),
      data_to_fabric_data_rxp1(7 downto 0) => data_to_fabric_data_rxp1(7 downto 0),
      data_to_fabric_data_rxp2(7 downto 0) => data_to_fabric_data_rxp2(7 downto 0),
      data_to_fabric_data_rxp3(7 downto 0) => data_to_fabric_data_rxp3(7 downto 0),
      fifo_empty_2 => fifo_empty_2,
      fifo_empty_4 => fifo_empty_4,
      fifo_empty_6 => fifo_empty_6,
      fifo_empty_8 => fifo_empty_8,
      fifo_rd_clk_0 => fifo_rd_clk_0,
      fifo_rd_en_2 => fifo_rd_en_2,
      fifo_rd_en_4 => fifo_rd_en_4,
      fifo_rd_en_6 => fifo_rd_en_6,
      fifo_rd_en_8 => fifo_rd_en_8,
      fifo_wr_clk_0 => fifo_wr_clk_0,
      rx_bs0_rx_bit_ctrl_in(39 downto 0) => rx_bs0_rx_bit_ctrl_in(39 downto 0),
      rx_bs0_rx_bit_ctrl_out(39 downto 0) => rx_bs0_rx_bit_ctrl_out(39 downto 0),
      rx_bs0_tx_bit_ctrl_in(39 downto 0) => rx_bs0_tx_bit_ctrl_in(39 downto 0),
      rx_bs0_tx_bit_ctrl_out(39 downto 0) => rx_bs0_tx_bit_ctrl_out(39 downto 0),
      rx_bs2_rx_bit_ctrl_in(39 downto 0) => rx_bs2_rx_bit_ctrl_in(39 downto 0),
      rx_bs2_rx_bit_ctrl_out(39 downto 0) => rx_bs2_rx_bit_ctrl_out(39 downto 0),
      rx_bs2_tx_bit_ctrl_in(39 downto 0) => rx_bs2_tx_bit_ctrl_in(39 downto 0),
      rx_bs2_tx_bit_ctrl_out(39 downto 0) => rx_bs2_tx_bit_ctrl_out(39 downto 0),
      rx_bs4_rx_bit_ctrl_in(39 downto 0) => rx_bs4_rx_bit_ctrl_in(39 downto 0),
      rx_bs4_rx_bit_ctrl_out(39 downto 0) => rx_bs4_rx_bit_ctrl_out(39 downto 0),
      rx_bs4_tx_bit_ctrl_in(39 downto 0) => rx_bs4_tx_bit_ctrl_in(39 downto 0),
      rx_bs4_tx_bit_ctrl_out(39 downto 0) => rx_bs4_tx_bit_ctrl_out(39 downto 0),
      rx_bs6_rx_bit_ctrl_in(39 downto 0) => rx_bs6_rx_bit_ctrl_in(39 downto 0),
      rx_bs6_rx_bit_ctrl_out(39 downto 0) => rx_bs6_rx_bit_ctrl_out(39 downto 0),
      rx_bs6_tx_bit_ctrl_in(39 downto 0) => rx_bs6_tx_bit_ctrl_in(39 downto 0),
      rx_bs6_tx_bit_ctrl_out(39 downto 0) => rx_bs6_tx_bit_ctrl_out(39 downto 0),
      rx_bs8_rx_bit_ctrl_in(39 downto 0) => rx_bs8_rx_bit_ctrl_in(39 downto 0),
      rx_bs8_rx_bit_ctrl_out(39 downto 0) => rx_bs8_rx_bit_ctrl_out(39 downto 0),
      rx_bs8_tx_bit_ctrl_in(39 downto 0) => rx_bs8_tx_bit_ctrl_in(39 downto 0),
      rx_bs8_tx_bit_ctrl_out(39 downto 0) => rx_bs8_tx_bit_ctrl_out(39 downto 0),
      rx_bs_rst_dly_ext_in(4 downto 0) => rx_bs_rst_dly_ext_in(4 downto 0),
      rx_bs_rst_in(4 downto 0) => rx_bs_rst_in(4 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_rst_scheme is
  port (
    \out\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \bs_rst_int_r_reg[8]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \GEN_RIU_NOT_FROM_PLL.bs_dly_rst_reg_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    pll0_clkoutphy_en_in : out STD_LOGIC;
    pll0_rst_in : out STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.rst_seq_done_reg_0\ : out STD_LOGIC;
    n1_en_vtc_in : out STD_LOGIC;
    pll0_locked_out : in STD_LOGIC;
    rst : in STD_LOGIC;
    bs_rst_dphy_in : in STD_LOGIC;
    in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    riu_clk : in STD_LOGIC;
    CLK : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\ : in STD_LOGIC;
    n1_vtc_rdy_out : in STD_LOGIC;
    n0_vtc_rdy_out : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_rst_scheme : entity is "high_speed_selectio_wiz_v3_6_10_rst_scheme";
end design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_rst_scheme;

architecture STRUCTURE of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_rst_scheme is
  signal \GEN_RIU_NOT_FROM_PLL.bs_dly_rst_i_3_n_0\ : STD_LOGIC;
  signal \^gen_riu_not_from_pll.bs_dly_rst_reg_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_2_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_3_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.hssio_state[0]_i_3_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_1_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_2_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_3_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_4_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_5_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_3_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_4_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_5_n_0\ : STD_LOGIC;
  signal \^gen_riu_not_from_pll.rst_seq_done_reg_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_i_2_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_2_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_5_n_0\ : STD_LOGIC;
  signal \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_8_n_0\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal all_bsc_dly_rdy : STD_LOGIC;
  signal bs_dly_rst : STD_LOGIC;
  signal bs_dly_rst_r : STD_LOGIC_VECTOR ( 51 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of bs_dly_rst_r : signal is "true";
  signal bs_rst_dphy_sync : STD_LOGIC;
  signal bs_rst_int_r : STD_LOGIC_VECTOR ( 51 downto 0 );
  attribute RTL_KEEP of bs_rst_int_r : signal is "true";
  signal bs_rst_r : STD_LOGIC_VECTOR ( 51 downto 0 );
  attribute RTL_KEEP of bs_rst_r : signal is "true";
  signal bsc_en_vtc : STD_LOGIC;
  signal bsc_en_vtc_1 : STD_LOGIC;
  signal hssio_state : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \hssio_state_inferred__3/i___0_n_0\ : STD_LOGIC;
  signal \hssio_state_inferred__3/i___1_n_0\ : STD_LOGIC;
  signal \hssio_state_inferred__3/i___2_n_0\ : STD_LOGIC;
  signal \hssio_state_inferred__3/i___3_n_0\ : STD_LOGIC;
  signal \hssio_state_inferred__3/i__n_0\ : STD_LOGIC;
  signal locked : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal p_0_in_0 : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \^pll0_clkoutphy_en_in\ : STD_LOGIC;
  signal \pll0_fab_clk_cntr[6]_i_3_n_0\ : STD_LOGIC;
  signal \pll0_fab_clk_cntr[6]_i_4_n_0\ : STD_LOGIC;
  signal pll0_fab_clk_cntr_reg : STD_LOGIC_VECTOR ( 6 to 6 );
  signal \pll0_fab_clk_cntr_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^pll0_rst_in\ : STD_LOGIC;
  signal rst_in_sync : STD_LOGIC;
  signal rst_seq_done : STD_LOGIC;
  signal sync_cell_dly_rdy_inst_n_1 : STD_LOGIC;
  signal sync_cell_pll0lock_inst_n_10 : STD_LOGIC;
  signal sync_cell_pll0lock_inst_n_11 : STD_LOGIC;
  signal sync_cell_pll0lock_inst_n_7 : STD_LOGIC;
  signal sync_cell_pll0lock_inst_n_8 : STD_LOGIC;
  signal sync_cell_pll0lock_inst_n_9 : STD_LOGIC;
  signal sync_cell_start_fab_cntr_pll0_inst_n_0 : STD_LOGIC;
  signal sync_cell_wait_pll0_fab_timeout_inst_n_2 : STD_LOGIC;
  signal sync_cell_wait_pll0_fab_timeout_inst_n_3 : STD_LOGIC;
  signal sync_cell_wait_pll0_fab_timeout_inst_n_4 : STD_LOGIC;
  signal timeout_cntr : STD_LOGIC;
  signal \timeout_cntr[0]_i_3_n_0\ : STD_LOGIC;
  signal \timeout_cntr[0]_i_4_n_0\ : STD_LOGIC;
  signal \timeout_cntr[0]_i_5_n_0\ : STD_LOGIC;
  signal \timeout_cntr[0]_i_6_n_0\ : STD_LOGIC;
  signal timeout_cntr_reg : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal \timeout_cntr_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_10\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_11\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_12\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_13\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_14\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_15\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_4\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_5\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_6\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_7\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_8\ : STD_LOGIC;
  signal \timeout_cntr_reg[0]_i_2_n_9\ : STD_LOGIC;
  signal \timeout_cntr_reg[16]_i_1_n_12\ : STD_LOGIC;
  signal \timeout_cntr_reg[16]_i_1_n_13\ : STD_LOGIC;
  signal \timeout_cntr_reg[16]_i_1_n_14\ : STD_LOGIC;
  signal \timeout_cntr_reg[16]_i_1_n_15\ : STD_LOGIC;
  signal \timeout_cntr_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \timeout_cntr_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \timeout_cntr_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_10\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_11\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_12\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_13\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_14\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_15\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_8\ : STD_LOGIC;
  signal \timeout_cntr_reg[8]_i_1_n_9\ : STD_LOGIC;
  signal timeout_cntr_rst : STD_LOGIC;
  signal wait_pll0_x_fab_clk_timeout : STD_LOGIC;
  signal wait_pll0_x_fab_clk_timeout_sync : STD_LOGIC;
  signal wait_pll_lock_timeout_i_1_n_0 : STD_LOGIC;
  signal wait_pll_lock_timeout_i_2_n_0 : STD_LOGIC;
  signal wait_pll_lock_timeout_i_3_n_0 : STD_LOGIC;
  signal wait_pll_lock_timeout_i_4_n_0 : STD_LOGIC;
  signal wait_pll_lock_timeout_i_5_n_0 : STD_LOGIC;
  signal wait_pll_lock_timeout_i_6_n_0 : STD_LOGIC;
  signal wait_pll_lock_timeout_i_7_n_0 : STD_LOGIC;
  signal wait_pll_lock_timeout_i_8_n_0 : STD_LOGIC;
  signal wait_pll_lock_timeout_i_9_n_0 : STD_LOGIC;
  signal wait_pll_lock_timeout_reg_n_0 : STD_LOGIC;
  signal \NLW_timeout_cntr_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_timeout_cntr_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \GEN_RIU_NOT_FROM_PLL.hssio_state[0]_i_3\ : label is "soft_lutpair3";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[0]\ : label is "WAIT_FOR_PLL_LOCK:000000100,WAIT_FOR_BSC_VTC_RDY:010000000,ASSERT_BSC_EN_VTC:001000000,DEASSERT_PLL_RESET:000000010,ASSERT_PLL_CLKOUTPHYEN:000010000,ASSERT_ALL_RESETS:000000001,WAIT_FOR_BSC_DLY_RDY:000100000,DEASSERT_BS_RESETS:000001000,RESET_SEQ_DONE:100000000";
  attribute FSM_ENCODED_STATES of \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[1]\ : label is "WAIT_FOR_PLL_LOCK:000000100,WAIT_FOR_BSC_VTC_RDY:010000000,ASSERT_BSC_EN_VTC:001000000,DEASSERT_PLL_RESET:000000010,ASSERT_PLL_CLKOUTPHYEN:000010000,ASSERT_ALL_RESETS:000000001,WAIT_FOR_BSC_DLY_RDY:000100000,DEASSERT_BS_RESETS:000001000,RESET_SEQ_DONE:100000000";
  attribute FSM_ENCODED_STATES of \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[2]\ : label is "WAIT_FOR_PLL_LOCK:000000100,WAIT_FOR_BSC_VTC_RDY:010000000,ASSERT_BSC_EN_VTC:001000000,DEASSERT_PLL_RESET:000000010,ASSERT_PLL_CLKOUTPHYEN:000010000,ASSERT_ALL_RESETS:000000001,WAIT_FOR_BSC_DLY_RDY:000100000,DEASSERT_BS_RESETS:000001000,RESET_SEQ_DONE:100000000";
  attribute FSM_ENCODED_STATES of \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[3]\ : label is "WAIT_FOR_PLL_LOCK:000000100,WAIT_FOR_BSC_VTC_RDY:010000000,ASSERT_BSC_EN_VTC:001000000,DEASSERT_PLL_RESET:000000010,ASSERT_PLL_CLKOUTPHYEN:000010000,ASSERT_ALL_RESETS:000000001,WAIT_FOR_BSC_DLY_RDY:000100000,DEASSERT_BS_RESETS:000001000,RESET_SEQ_DONE:100000000";
  attribute FSM_ENCODED_STATES of \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[4]\ : label is "WAIT_FOR_PLL_LOCK:000000100,WAIT_FOR_BSC_VTC_RDY:010000000,ASSERT_BSC_EN_VTC:001000000,DEASSERT_PLL_RESET:000000010,ASSERT_PLL_CLKOUTPHYEN:000010000,ASSERT_ALL_RESETS:000000001,WAIT_FOR_BSC_DLY_RDY:000100000,DEASSERT_BS_RESETS:000001000,RESET_SEQ_DONE:100000000";
  attribute FSM_ENCODED_STATES of \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[5]\ : label is "WAIT_FOR_PLL_LOCK:000000100,WAIT_FOR_BSC_VTC_RDY:010000000,ASSERT_BSC_EN_VTC:001000000,DEASSERT_PLL_RESET:000000010,ASSERT_PLL_CLKOUTPHYEN:000010000,ASSERT_ALL_RESETS:000000001,WAIT_FOR_BSC_DLY_RDY:000100000,DEASSERT_BS_RESETS:000001000,RESET_SEQ_DONE:100000000";
  attribute FSM_ENCODED_STATES of \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[6]\ : label is "WAIT_FOR_PLL_LOCK:000000100,WAIT_FOR_BSC_VTC_RDY:010000000,ASSERT_BSC_EN_VTC:001000000,DEASSERT_PLL_RESET:000000010,ASSERT_PLL_CLKOUTPHYEN:000010000,ASSERT_ALL_RESETS:000000001,WAIT_FOR_BSC_DLY_RDY:000100000,DEASSERT_BS_RESETS:000001000,RESET_SEQ_DONE:100000000";
  attribute FSM_ENCODED_STATES of \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[7]\ : label is "WAIT_FOR_PLL_LOCK:000000100,WAIT_FOR_BSC_VTC_RDY:010000000,ASSERT_BSC_EN_VTC:001000000,DEASSERT_PLL_RESET:000000010,ASSERT_PLL_CLKOUTPHYEN:000010000,ASSERT_ALL_RESETS:000000001,WAIT_FOR_BSC_DLY_RDY:000100000,DEASSERT_BS_RESETS:000001000,RESET_SEQ_DONE:100000000";
  attribute FSM_ENCODED_STATES of \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[8]\ : label is "WAIT_FOR_PLL_LOCK:000000100,WAIT_FOR_BSC_VTC_RDY:010000000,ASSERT_BSC_EN_VTC:001000000,DEASSERT_PLL_RESET:000000010,ASSERT_PLL_CLKOUTPHYEN:000010000,ASSERT_ALL_RESETS:000000001,WAIT_FOR_BSC_DLY_RDY:000100000,DEASSERT_BS_RESETS:000001000,RESET_SEQ_DONE:100000000";
  attribute SOFT_HLUTNM of \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_2\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_5\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_4\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_5\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_2\ : label is "soft_lutpair6";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \bs_rst_gen[0].bs_rst_r_reg[0]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[10].bs_dly_rst_r_reg[10]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[10].bs_rst_r_reg[10]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[11].bs_dly_rst_r_reg[11]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[11].bs_rst_r_reg[11]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[12].bs_dly_rst_r_reg[12]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[12].bs_rst_r_reg[12]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[13].bs_dly_rst_r_reg[13]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[13].bs_rst_r_reg[13]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[14].bs_dly_rst_r_reg[14]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[14].bs_rst_r_reg[14]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[15].bs_dly_rst_r_reg[15]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[15].bs_rst_r_reg[15]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[16].bs_dly_rst_r_reg[16]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[16].bs_rst_r_reg[16]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[17].bs_dly_rst_r_reg[17]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[17].bs_rst_r_reg[17]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[18].bs_dly_rst_r_reg[18]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[18].bs_rst_r_reg[18]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[19].bs_dly_rst_r_reg[19]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[19].bs_rst_r_reg[19]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[1].bs_dly_rst_r_reg[1]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[1].bs_rst_r_reg[1]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[20].bs_dly_rst_r_reg[20]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[20].bs_rst_r_reg[20]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[21].bs_dly_rst_r_reg[21]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[21].bs_rst_r_reg[21]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[22].bs_dly_rst_r_reg[22]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[22].bs_rst_r_reg[22]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[23].bs_dly_rst_r_reg[23]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[23].bs_rst_r_reg[23]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[24].bs_dly_rst_r_reg[24]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[24].bs_rst_r_reg[24]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[25].bs_dly_rst_r_reg[25]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[25].bs_rst_r_reg[25]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[26].bs_dly_rst_r_reg[26]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[26].bs_rst_r_reg[26]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[27].bs_dly_rst_r_reg[27]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[27].bs_rst_r_reg[27]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[28].bs_dly_rst_r_reg[28]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[28].bs_rst_r_reg[28]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[29].bs_dly_rst_r_reg[29]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[29].bs_rst_r_reg[29]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[2].bs_dly_rst_r_reg[2]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[2].bs_rst_r_reg[2]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[30].bs_dly_rst_r_reg[30]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[30].bs_rst_r_reg[30]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[31].bs_dly_rst_r_reg[31]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[31].bs_rst_r_reg[31]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[32].bs_dly_rst_r_reg[32]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[32].bs_rst_r_reg[32]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[33].bs_dly_rst_r_reg[33]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[33].bs_rst_r_reg[33]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[34].bs_dly_rst_r_reg[34]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[34].bs_rst_r_reg[34]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[35].bs_dly_rst_r_reg[35]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[35].bs_rst_r_reg[35]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[36].bs_dly_rst_r_reg[36]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[36].bs_rst_r_reg[36]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[37].bs_dly_rst_r_reg[37]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[37].bs_rst_r_reg[37]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[38].bs_dly_rst_r_reg[38]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[38].bs_rst_r_reg[38]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[39].bs_dly_rst_r_reg[39]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[39].bs_rst_r_reg[39]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[3].bs_dly_rst_r_reg[3]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[3].bs_rst_r_reg[3]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[40].bs_dly_rst_r_reg[40]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[40].bs_rst_r_reg[40]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[41].bs_dly_rst_r_reg[41]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[41].bs_rst_r_reg[41]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[42].bs_dly_rst_r_reg[42]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[42].bs_rst_r_reg[42]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[43].bs_dly_rst_r_reg[43]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[43].bs_rst_r_reg[43]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[44].bs_dly_rst_r_reg[44]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[44].bs_rst_r_reg[44]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[45].bs_dly_rst_r_reg[45]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[45].bs_rst_r_reg[45]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[46].bs_dly_rst_r_reg[46]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[46].bs_rst_r_reg[46]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[47].bs_dly_rst_r_reg[47]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[47].bs_rst_r_reg[47]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[48].bs_dly_rst_r_reg[48]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[48].bs_rst_r_reg[48]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[49].bs_dly_rst_r_reg[49]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[49].bs_rst_r_reg[49]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[4].bs_dly_rst_r_reg[4]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[4].bs_rst_r_reg[4]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[50].bs_dly_rst_r_reg[50]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[50].bs_rst_r_reg[50]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[51].bs_dly_rst_r_reg[51]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[51].bs_rst_r_reg[51]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[5].bs_dly_rst_r_reg[5]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[5].bs_rst_r_reg[5]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[6].bs_dly_rst_r_reg[6]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[6].bs_rst_r_reg[6]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[7].bs_dly_rst_r_reg[7]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[7].bs_rst_r_reg[7]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[8].bs_dly_rst_r_reg[8]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[8].bs_rst_r_reg[8]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[9].bs_dly_rst_r_reg[9]\ : label is "no";
  attribute equivalent_register_removal of \bs_rst_gen[9].bs_rst_r_reg[9]\ : label is "no";
  attribute KEEP : string;
  attribute KEEP of \bs_rst_int_r_reg[0]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[10]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[11]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[12]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[13]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[14]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[15]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[16]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[17]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[18]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[19]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[1]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[20]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[21]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[22]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[23]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[24]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[25]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[26]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[27]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[28]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[29]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[2]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[30]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[31]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[32]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[33]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[34]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[35]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[36]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[37]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[38]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[39]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[3]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[40]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[41]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[42]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[43]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[44]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[45]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[46]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[47]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[48]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[49]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[4]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[50]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[51]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[5]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[6]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[7]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[8]\ : label is "yes";
  attribute KEEP of \bs_rst_int_r_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM of \hssio_state_inferred__3/i_\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \hssio_state_inferred__3/i___0\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \hssio_state_inferred__3/i___1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \hssio_state_inferred__3/i___2\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \pll0_fab_clk_cntr[0]_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \pll0_fab_clk_cntr[1]_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \pll0_fab_clk_cntr[2]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \pll0_fab_clk_cntr[3]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \pll0_fab_clk_cntr[4]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \pll0_fab_clk_cntr[6]_i_4\ : label is "soft_lutpair4";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \timeout_cntr_reg[0]_i_2\ : label is 16;
  attribute ADDER_THRESHOLD of \timeout_cntr_reg[16]_i_1\ : label is 16;
  attribute ADDER_THRESHOLD of \timeout_cntr_reg[8]_i_1\ : label is 16;
  attribute SOFT_HLUTNM of wait_pll_lock_timeout_i_4 : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of wait_pll_lock_timeout_i_9 : label is "soft_lutpair9";
begin
  \GEN_RIU_NOT_FROM_PLL.bs_dly_rst_reg_0\ <= \^gen_riu_not_from_pll.bs_dly_rst_reg_0\;
  \GEN_RIU_NOT_FROM_PLL.rst_seq_done_reg_0\ <= \^gen_riu_not_from_pll.rst_seq_done_reg_0\;
  Q(0) <= \^q\(0);
  \bs_rst_int_r_reg[8]_0\(4) <= bs_rst_int_r(8);
  \bs_rst_int_r_reg[8]_0\(3) <= bs_rst_int_r(6);
  \bs_rst_int_r_reg[8]_0\(2) <= bs_rst_int_r(4);
  \bs_rst_int_r_reg[8]_0\(1) <= bs_rst_int_r(2);
  \bs_rst_int_r_reg[8]_0\(0) <= bs_rst_int_r(0);
  \out\(4) <= bs_dly_rst_r(8);
  \out\(3) <= bs_dly_rst_r(6);
  \out\(2) <= bs_dly_rst_r(4);
  \out\(1) <= bs_dly_rst_r(2);
  \out\(0) <= bs_dly_rst_r(0);
  pll0_clkoutphy_en_in <= \^pll0_clkoutphy_en_in\;
  pll0_rst_in <= \^pll0_rst_in\;
\BITSLICE_CTRL[0].bs_ctrl_inst_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^gen_riu_not_from_pll.rst_seq_done_reg_0\,
      I1 => bsc_en_vtc,
      O => n1_en_vtc_in
    );
\GEN_RIU_NOT_FROM_PLL.bs_dly_rst_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
        port map (
      I0 => \^q\(0),
      I1 => hssio_state(5),
      I2 => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_4_n_0\,
      I3 => hssio_state(0),
      I4 => hssio_state(3),
      I5 => hssio_state(8),
      O => bs_dly_rst
    );
\GEN_RIU_NOT_FROM_PLL.bs_dly_rst_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^q\(0),
      I1 => hssio_state(5),
      I2 => hssio_state(1),
      I3 => bsc_en_vtc_1,
      I4 => hssio_state(4),
      I5 => hssio_state(2),
      O => \GEN_RIU_NOT_FROM_PLL.bs_dly_rst_i_3_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.bs_dly_rst_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => sync_cell_pll0lock_inst_n_11,
      Q => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      S => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => hssio_state(1),
      I1 => bsc_en_vtc_1,
      I2 => hssio_state(4),
      I3 => hssio_state(2),
      I4 => hssio_state(8),
      I5 => hssio_state(3),
      O => \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_2_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => hssio_state(5),
      I1 => \^q\(0),
      O => \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_3_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => sync_cell_pll0lock_inst_n_9,
      Q => bsc_en_vtc,
      R => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^q\(0),
      I1 => hssio_state(5),
      I2 => hssio_state(8),
      I3 => hssio_state(3),
      O => \GEN_RIU_NOT_FROM_PLL.hssio_state[0]_i_3_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \hssio_state_inferred__3/i___3_n_0\,
      I1 => hssio_state(0),
      O => p_0_in_0(1)
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => p_0_in_0(0),
      Q => hssio_state(0),
      S => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => p_0_in_0(1),
      Q => hssio_state(1),
      R => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => p_0_in_0(2),
      Q => hssio_state(2),
      R => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => p_0_in_0(3),
      Q => hssio_state(3),
      R => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => p_0_in_0(4),
      Q => hssio_state(4),
      R => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => p_0_in_0(5),
      Q => hssio_state(5),
      R => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => p_0_in_0(6),
      Q => bsc_en_vtc_1,
      R => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => p_0_in_0(7),
      Q => \^q\(0),
      R => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.hssio_state_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => p_0_in_0(8),
      Q => hssio_state(8),
      R => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.pll0_clkoutphy_en_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => sync_cell_wait_pll0_fab_timeout_inst_n_3,
      Q => \^pll0_clkoutphy_en_in\,
      R => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.pll0_rst_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFFFFFEFEFF00"
    )
        port map (
      I0 => \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_2_n_0\,
      I1 => hssio_state(0),
      I2 => \GEN_RIU_NOT_FROM_PLL.hssio_state[0]_i_3_n_0\,
      I3 => \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_3_n_0\,
      I4 => hssio_state(1),
      I5 => \^pll0_rst_in\,
      O => \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_1_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.pll0_rst_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => bsc_en_vtc_1,
      I1 => hssio_state(4),
      I2 => hssio_state(2),
      O => \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_2_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.pll0_rst_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFEFEF9"
    )
        port map (
      I0 => \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_4_n_0\,
      I1 => \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_3_n_0\,
      I2 => \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_5_n_0\,
      I3 => hssio_state(2),
      I4 => bsc_en_vtc_1,
      I5 => hssio_state(4),
      O => \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_3_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.pll0_rst_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => hssio_state(3),
      I1 => hssio_state(8),
      O => \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_4_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.pll0_rst_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
        port map (
      I0 => hssio_state(8),
      I1 => hssio_state(3),
      I2 => hssio_state(0),
      I3 => hssio_state(5),
      I4 => \^q\(0),
      O => \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_5_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.pll0_rst_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => \GEN_RIU_NOT_FROM_PLL.pll0_rst_i_1_n_0\,
      Q => \^pll0_rst_in\,
      S => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \^q\(0),
      I1 => hssio_state(5),
      I2 => hssio_state(3),
      I3 => hssio_state(8),
      I4 => hssio_state(0),
      I5 => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_4_n_0\,
      O => rst_seq_done
    );
\GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFEFFEB"
    )
        port map (
      I0 => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_2_n_0\,
      I1 => hssio_state(8),
      I2 => hssio_state(3),
      I3 => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_5_n_0\,
      I4 => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_4_n_0\,
      I5 => \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_3_n_0\,
      O => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_3_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => hssio_state(2),
      I1 => hssio_state(4),
      I2 => bsc_en_vtc_1,
      I3 => hssio_state(1),
      O => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_4_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \^q\(0),
      I1 => hssio_state(5),
      I2 => hssio_state(0),
      O => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_5_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.rst_seq_done_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => sync_cell_pll0lock_inst_n_10,
      Q => \^gen_riu_not_from_pll.rst_seq_done_reg_0\,
      R => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => hssio_state(5),
      I1 => \^q\(0),
      I2 => hssio_state(0),
      I3 => hssio_state(3),
      I4 => hssio_state(8),
      I5 => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_4_n_0\,
      O => \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_i_2_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => sync_cell_wait_pll0_fab_timeout_inst_n_4,
      Q => \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg_n_0\,
      R => rst_in_sync
    );
\GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEE8"
    )
        port map (
      I0 => hssio_state(1),
      I1 => hssio_state(4),
      I2 => bsc_en_vtc_1,
      I3 => hssio_state(2),
      O => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_2_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFEA"
    )
        port map (
      I0 => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_8_n_0\,
      I1 => \^q\(0),
      I2 => hssio_state(5),
      I3 => hssio_state(0),
      I4 => hssio_state(1),
      I5 => hssio_state(8),
      O => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_5_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFEFE01"
    )
        port map (
      I0 => \^q\(0),
      I1 => hssio_state(5),
      I2 => hssio_state(3),
      I3 => hssio_state(4),
      I4 => bsc_en_vtc_1,
      I5 => hssio_state(2),
      O => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_8_n_0\
    );
\GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => sync_cell_pll0lock_inst_n_8,
      Q => timeout_cntr_rst,
      S => rst_in_sync
    );
\bs_rst_gen[0].bs_dly_rst_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(0),
      R => '0'
    );
\bs_rst_gen[0].bs_rst_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(0),
      R => '0'
    );
\bs_rst_gen[10].bs_dly_rst_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(10),
      R => '0'
    );
\bs_rst_gen[10].bs_rst_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(10),
      R => '0'
    );
\bs_rst_gen[11].bs_dly_rst_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(11),
      R => '0'
    );
\bs_rst_gen[11].bs_rst_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(11),
      R => '0'
    );
\bs_rst_gen[12].bs_dly_rst_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(12),
      R => '0'
    );
\bs_rst_gen[12].bs_rst_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(12),
      R => '0'
    );
\bs_rst_gen[13].bs_dly_rst_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(13),
      R => '0'
    );
\bs_rst_gen[13].bs_rst_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(13),
      R => '0'
    );
\bs_rst_gen[14].bs_dly_rst_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(14),
      R => '0'
    );
\bs_rst_gen[14].bs_rst_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(14),
      R => '0'
    );
\bs_rst_gen[15].bs_dly_rst_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(15),
      R => '0'
    );
\bs_rst_gen[15].bs_rst_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(15),
      R => '0'
    );
\bs_rst_gen[16].bs_dly_rst_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(16),
      R => '0'
    );
\bs_rst_gen[16].bs_rst_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(16),
      R => '0'
    );
\bs_rst_gen[17].bs_dly_rst_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(17),
      R => '0'
    );
\bs_rst_gen[17].bs_rst_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(17),
      R => '0'
    );
\bs_rst_gen[18].bs_dly_rst_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(18),
      R => '0'
    );
\bs_rst_gen[18].bs_rst_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(18),
      R => '0'
    );
\bs_rst_gen[19].bs_dly_rst_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(19),
      R => '0'
    );
\bs_rst_gen[19].bs_rst_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(19),
      R => '0'
    );
\bs_rst_gen[1].bs_dly_rst_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(1),
      R => '0'
    );
\bs_rst_gen[1].bs_rst_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(1),
      R => '0'
    );
\bs_rst_gen[20].bs_dly_rst_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(20),
      R => '0'
    );
\bs_rst_gen[20].bs_rst_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(20),
      R => '0'
    );
\bs_rst_gen[21].bs_dly_rst_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(21),
      R => '0'
    );
\bs_rst_gen[21].bs_rst_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(21),
      R => '0'
    );
\bs_rst_gen[22].bs_dly_rst_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(22),
      R => '0'
    );
\bs_rst_gen[22].bs_rst_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(22),
      R => '0'
    );
\bs_rst_gen[23].bs_dly_rst_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(23),
      R => '0'
    );
\bs_rst_gen[23].bs_rst_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(23),
      R => '0'
    );
\bs_rst_gen[24].bs_dly_rst_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(24),
      R => '0'
    );
\bs_rst_gen[24].bs_rst_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(24),
      R => '0'
    );
\bs_rst_gen[25].bs_dly_rst_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(25),
      R => '0'
    );
\bs_rst_gen[25].bs_rst_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(25),
      R => '0'
    );
\bs_rst_gen[26].bs_dly_rst_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(26),
      R => '0'
    );
\bs_rst_gen[26].bs_rst_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(26),
      R => '0'
    );
\bs_rst_gen[27].bs_dly_rst_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(27),
      R => '0'
    );
\bs_rst_gen[27].bs_rst_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(27),
      R => '0'
    );
\bs_rst_gen[28].bs_dly_rst_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(28),
      R => '0'
    );
\bs_rst_gen[28].bs_rst_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(28),
      R => '0'
    );
\bs_rst_gen[29].bs_dly_rst_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(29),
      R => '0'
    );
\bs_rst_gen[29].bs_rst_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(29),
      R => '0'
    );
\bs_rst_gen[2].bs_dly_rst_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(2),
      R => '0'
    );
\bs_rst_gen[2].bs_rst_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(2),
      R => '0'
    );
\bs_rst_gen[30].bs_dly_rst_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(30),
      R => '0'
    );
\bs_rst_gen[30].bs_rst_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(30),
      R => '0'
    );
\bs_rst_gen[31].bs_dly_rst_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(31),
      R => '0'
    );
\bs_rst_gen[31].bs_rst_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(31),
      R => '0'
    );
\bs_rst_gen[32].bs_dly_rst_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(32),
      R => '0'
    );
\bs_rst_gen[32].bs_rst_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(32),
      R => '0'
    );
\bs_rst_gen[33].bs_dly_rst_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(33),
      R => '0'
    );
\bs_rst_gen[33].bs_rst_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(33),
      R => '0'
    );
\bs_rst_gen[34].bs_dly_rst_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(34),
      R => '0'
    );
\bs_rst_gen[34].bs_rst_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(34),
      R => '0'
    );
\bs_rst_gen[35].bs_dly_rst_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(35),
      R => '0'
    );
\bs_rst_gen[35].bs_rst_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(35),
      R => '0'
    );
\bs_rst_gen[36].bs_dly_rst_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(36),
      R => '0'
    );
\bs_rst_gen[36].bs_rst_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(36),
      R => '0'
    );
\bs_rst_gen[37].bs_dly_rst_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(37),
      R => '0'
    );
\bs_rst_gen[37].bs_rst_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(37),
      R => '0'
    );
\bs_rst_gen[38].bs_dly_rst_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(38),
      R => '0'
    );
\bs_rst_gen[38].bs_rst_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(38),
      R => '0'
    );
\bs_rst_gen[39].bs_dly_rst_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(39),
      R => '0'
    );
\bs_rst_gen[39].bs_rst_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(39),
      R => '0'
    );
\bs_rst_gen[3].bs_dly_rst_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(3),
      R => '0'
    );
\bs_rst_gen[3].bs_rst_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(3),
      R => '0'
    );
\bs_rst_gen[40].bs_dly_rst_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(40),
      R => '0'
    );
\bs_rst_gen[40].bs_rst_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(40),
      R => '0'
    );
\bs_rst_gen[41].bs_dly_rst_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(41),
      R => '0'
    );
\bs_rst_gen[41].bs_rst_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(41),
      R => '0'
    );
\bs_rst_gen[42].bs_dly_rst_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(42),
      R => '0'
    );
\bs_rst_gen[42].bs_rst_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(42),
      R => '0'
    );
\bs_rst_gen[43].bs_dly_rst_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(43),
      R => '0'
    );
\bs_rst_gen[43].bs_rst_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(43),
      R => '0'
    );
\bs_rst_gen[44].bs_dly_rst_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(44),
      R => '0'
    );
\bs_rst_gen[44].bs_rst_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(44),
      R => '0'
    );
\bs_rst_gen[45].bs_dly_rst_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(45),
      R => '0'
    );
\bs_rst_gen[45].bs_rst_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(45),
      R => '0'
    );
\bs_rst_gen[46].bs_dly_rst_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(46),
      R => '0'
    );
\bs_rst_gen[46].bs_rst_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(46),
      R => '0'
    );
\bs_rst_gen[47].bs_dly_rst_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(47),
      R => '0'
    );
\bs_rst_gen[47].bs_rst_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(47),
      R => '0'
    );
\bs_rst_gen[48].bs_dly_rst_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(48),
      R => '0'
    );
\bs_rst_gen[48].bs_rst_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(48),
      R => '0'
    );
\bs_rst_gen[49].bs_dly_rst_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(49),
      R => '0'
    );
\bs_rst_gen[49].bs_rst_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(49),
      R => '0'
    );
\bs_rst_gen[4].bs_dly_rst_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(4),
      R => '0'
    );
\bs_rst_gen[4].bs_rst_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(4),
      R => '0'
    );
\bs_rst_gen[50].bs_dly_rst_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(50),
      R => '0'
    );
\bs_rst_gen[50].bs_rst_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(50),
      R => '0'
    );
\bs_rst_gen[51].bs_dly_rst_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(51),
      R => '0'
    );
\bs_rst_gen[51].bs_rst_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(51),
      R => '0'
    );
\bs_rst_gen[5].bs_dly_rst_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(5),
      R => '0'
    );
\bs_rst_gen[5].bs_rst_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(5),
      R => '0'
    );
\bs_rst_gen[6].bs_dly_rst_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(6),
      R => '0'
    );
\bs_rst_gen[6].bs_rst_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(6),
      R => '0'
    );
\bs_rst_gen[7].bs_dly_rst_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(7),
      R => '0'
    );
\bs_rst_gen[7].bs_rst_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(7),
      R => '0'
    );
\bs_rst_gen[8].bs_dly_rst_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(8),
      R => '0'
    );
\bs_rst_gen[8].bs_rst_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(8),
      R => '0'
    );
\bs_rst_gen[9].bs_dly_rst_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_dly_rst_r(9),
      R => '0'
    );
\bs_rst_gen[9].bs_rst_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      Q => bs_rst_r(9),
      R => '0'
    );
\bs_rst_int_r_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(0),
      Q => bs_rst_int_r(0),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[10]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(10),
      Q => bs_rst_int_r(10),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[11]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(11),
      Q => bs_rst_int_r(11),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[12]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(12),
      Q => bs_rst_int_r(12),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[13]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(13),
      Q => bs_rst_int_r(13),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[14]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(14),
      Q => bs_rst_int_r(14),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[15]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(15),
      Q => bs_rst_int_r(15),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[16]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(16),
      Q => bs_rst_int_r(16),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[17]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(17),
      Q => bs_rst_int_r(17),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[18]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(18),
      Q => bs_rst_int_r(18),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[19]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(19),
      Q => bs_rst_int_r(19),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(1),
      Q => bs_rst_int_r(1),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[20]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(20),
      Q => bs_rst_int_r(20),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[21]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(21),
      Q => bs_rst_int_r(21),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[22]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(22),
      Q => bs_rst_int_r(22),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[23]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(23),
      Q => bs_rst_int_r(23),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[24]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(24),
      Q => bs_rst_int_r(24),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[25]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(25),
      Q => bs_rst_int_r(25),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[26]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(26),
      Q => bs_rst_int_r(26),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[27]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(27),
      Q => bs_rst_int_r(27),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[28]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(28),
      Q => bs_rst_int_r(28),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[29]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(29),
      Q => bs_rst_int_r(29),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(2),
      Q => bs_rst_int_r(2),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[30]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(30),
      Q => bs_rst_int_r(30),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[31]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(31),
      Q => bs_rst_int_r(31),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[32]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(32),
      Q => bs_rst_int_r(32),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[33]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(33),
      Q => bs_rst_int_r(33),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[34]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(34),
      Q => bs_rst_int_r(34),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[35]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(35),
      Q => bs_rst_int_r(35),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[36]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(36),
      Q => bs_rst_int_r(36),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[37]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(37),
      Q => bs_rst_int_r(37),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[38]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(38),
      Q => bs_rst_int_r(38),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[39]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(39),
      Q => bs_rst_int_r(39),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(3),
      Q => bs_rst_int_r(3),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[40]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(40),
      Q => bs_rst_int_r(40),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[41]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(41),
      Q => bs_rst_int_r(41),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[42]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(42),
      Q => bs_rst_int_r(42),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[43]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(43),
      Q => bs_rst_int_r(43),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[44]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(44),
      Q => bs_rst_int_r(44),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[45]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(45),
      Q => bs_rst_int_r(45),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[46]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(46),
      Q => bs_rst_int_r(46),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[47]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(47),
      Q => bs_rst_int_r(47),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[48]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(48),
      Q => bs_rst_int_r(48),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[49]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(49),
      Q => bs_rst_int_r(49),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[4]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(4),
      Q => bs_rst_int_r(4),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[50]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(50),
      Q => bs_rst_int_r(50),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[51]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(51),
      Q => bs_rst_int_r(51),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[5]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(5),
      Q => bs_rst_int_r(5),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[6]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(6),
      Q => bs_rst_int_r(6),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(7),
      Q => bs_rst_int_r(7),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[8]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(8),
      Q => bs_rst_int_r(8),
      S => bs_rst_dphy_sync
    );
\bs_rst_int_r_reg[9]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => bs_rst_r(9),
      Q => bs_rst_int_r(9),
      S => bs_rst_dphy_sync
    );
\hssio_state_inferred__3/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0116"
    )
        port map (
      I0 => hssio_state(0),
      I1 => hssio_state(1),
      I2 => hssio_state(2),
      I3 => hssio_state(3),
      O => \hssio_state_inferred__3/i__n_0\
    );
\hssio_state_inferred__3/i___0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEE8"
    )
        port map (
      I0 => hssio_state(0),
      I1 => hssio_state(1),
      I2 => hssio_state(2),
      I3 => hssio_state(3),
      O => \hssio_state_inferred__3/i___0_n_0\
    );
\hssio_state_inferred__3/i___1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010116"
    )
        port map (
      I0 => hssio_state(4),
      I1 => hssio_state(5),
      I2 => bsc_en_vtc_1,
      I3 => \^q\(0),
      I4 => hssio_state(8),
      O => \hssio_state_inferred__3/i___1_n_0\
    );
\hssio_state_inferred__3/i___2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFEE8"
    )
        port map (
      I0 => hssio_state(4),
      I1 => hssio_state(5),
      I2 => bsc_en_vtc_1,
      I3 => \^q\(0),
      I4 => hssio_state(8),
      O => \hssio_state_inferred__3/i___2_n_0\
    );
\hssio_state_inferred__3/i___3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0012"
    )
        port map (
      I0 => \hssio_state_inferred__3/i__n_0\,
      I1 => \hssio_state_inferred__3/i___0_n_0\,
      I2 => \hssio_state_inferred__3/i___1_n_0\,
      I3 => \hssio_state_inferred__3/i___2_n_0\,
      O => \hssio_state_inferred__3/i___3_n_0\
    );
\pll0_fab_clk_cntr[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \pll0_fab_clk_cntr_reg__0\(0),
      O => p_0_in(0)
    );
\pll0_fab_clk_cntr[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \pll0_fab_clk_cntr_reg__0\(0),
      I1 => \pll0_fab_clk_cntr_reg__0\(1),
      O => p_0_in(1)
    );
\pll0_fab_clk_cntr[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \pll0_fab_clk_cntr_reg__0\(0),
      I1 => \pll0_fab_clk_cntr_reg__0\(1),
      I2 => \pll0_fab_clk_cntr_reg__0\(2),
      O => p_0_in(2)
    );
\pll0_fab_clk_cntr[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \pll0_fab_clk_cntr_reg__0\(1),
      I1 => \pll0_fab_clk_cntr_reg__0\(0),
      I2 => \pll0_fab_clk_cntr_reg__0\(2),
      I3 => \pll0_fab_clk_cntr_reg__0\(3),
      O => p_0_in(3)
    );
\pll0_fab_clk_cntr[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \pll0_fab_clk_cntr_reg__0\(2),
      I1 => \pll0_fab_clk_cntr_reg__0\(0),
      I2 => \pll0_fab_clk_cntr_reg__0\(1),
      I3 => \pll0_fab_clk_cntr_reg__0\(3),
      I4 => \pll0_fab_clk_cntr_reg__0\(4),
      O => p_0_in(4)
    );
\pll0_fab_clk_cntr[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \pll0_fab_clk_cntr_reg__0\(3),
      I1 => \pll0_fab_clk_cntr_reg__0\(1),
      I2 => \pll0_fab_clk_cntr_reg__0\(0),
      I3 => \pll0_fab_clk_cntr_reg__0\(2),
      I4 => \pll0_fab_clk_cntr_reg__0\(4),
      I5 => \pll0_fab_clk_cntr_reg__0\(5),
      O => p_0_in(5)
    );
\pll0_fab_clk_cntr[6]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \pll0_fab_clk_cntr[6]_i_4_n_0\,
      I1 => \pll0_fab_clk_cntr_reg__0\(5),
      I2 => pll0_fab_clk_cntr_reg(6),
      O => p_0_in(6)
    );
\pll0_fab_clk_cntr[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \pll0_fab_clk_cntr_reg__0\(3),
      I1 => \pll0_fab_clk_cntr_reg__0\(2),
      I2 => \pll0_fab_clk_cntr_reg__0\(5),
      I3 => \pll0_fab_clk_cntr_reg__0\(4),
      I4 => \pll0_fab_clk_cntr_reg__0\(1),
      I5 => \pll0_fab_clk_cntr_reg__0\(0),
      O => \pll0_fab_clk_cntr[6]_i_3_n_0\
    );
\pll0_fab_clk_cntr[6]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \pll0_fab_clk_cntr_reg__0\(4),
      I1 => \pll0_fab_clk_cntr_reg__0\(2),
      I2 => \pll0_fab_clk_cntr_reg__0\(0),
      I3 => \pll0_fab_clk_cntr_reg__0\(1),
      I4 => \pll0_fab_clk_cntr_reg__0\(3),
      O => \pll0_fab_clk_cntr[6]_i_4_n_0\
    );
\pll0_fab_clk_cntr_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_0_in(0),
      Q => \pll0_fab_clk_cntr_reg__0\(0),
      R => sync_cell_start_fab_cntr_pll0_inst_n_0
    );
\pll0_fab_clk_cntr_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_0_in(1),
      Q => \pll0_fab_clk_cntr_reg__0\(1),
      R => sync_cell_start_fab_cntr_pll0_inst_n_0
    );
\pll0_fab_clk_cntr_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_0_in(2),
      Q => \pll0_fab_clk_cntr_reg__0\(2),
      R => sync_cell_start_fab_cntr_pll0_inst_n_0
    );
\pll0_fab_clk_cntr_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_0_in(3),
      Q => \pll0_fab_clk_cntr_reg__0\(3),
      R => sync_cell_start_fab_cntr_pll0_inst_n_0
    );
\pll0_fab_clk_cntr_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_0_in(4),
      Q => \pll0_fab_clk_cntr_reg__0\(4),
      R => sync_cell_start_fab_cntr_pll0_inst_n_0
    );
\pll0_fab_clk_cntr_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_0_in(5),
      Q => \pll0_fab_clk_cntr_reg__0\(5),
      R => sync_cell_start_fab_cntr_pll0_inst_n_0
    );
\pll0_fab_clk_cntr_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_0_in(6),
      Q => pll0_fab_clk_cntr_reg(6),
      R => sync_cell_start_fab_cntr_pll0_inst_n_0
    );
sync_cell_bs_rst_dphy_inst: entity work.design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_217
     port map (
      SS(0) => bs_rst_dphy_sync,
      bs_rst_dphy_in => bs_rst_dphy_in,
      riu_clk => riu_clk
    );
sync_cell_dly_rdy_inst: entity work.design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_218
     port map (
      D(0) => p_0_in_0(6),
      \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[6]\ => locked,
      \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[6]_0\ => \hssio_state_inferred__3/i___3_n_0\,
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg\ => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\,
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\ => \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_3_n_0\,
      Q(2) => bsc_en_vtc_1,
      Q(1) => hssio_state(5),
      Q(0) => hssio_state(3),
      in0(0) => in0(0),
      \out\ => all_bsc_dly_rdy,
      riu_clk => riu_clk,
      \sync_flop_1_reg[0]_0\ => sync_cell_dly_rdy_inst_n_1
    );
sync_cell_mult_intf_lock_inst: entity work.design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_219
     port map (
      riu_clk => riu_clk
    );
sync_cell_pll0lock_inst: entity work.design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_220
     port map (
      D(5 downto 4) => p_0_in_0(8 downto 7),
      D(3 downto 1) => p_0_in_0(4 downto 2),
      D(0) => p_0_in_0(0),
      \GEN_RIU_NOT_FROM_PLL.bs_dly_rst_reg\ => \GEN_RIU_NOT_FROM_PLL.bs_dly_rst_i_3_n_0\,
      \GEN_RIU_NOT_FROM_PLL.bs_dly_rst_reg_0\ => \^gen_riu_not_from_pll.bs_dly_rst_reg_0\,
      \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_reg\ => \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_2_n_0\,
      \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_reg_0\ => \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_3_n_0\,
      \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[0]\ => \GEN_RIU_NOT_FROM_PLL.hssio_state[0]_i_3_n_0\,
      \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[2]\ => wait_pll_lock_timeout_reg_n_0,
      \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[3]\ => \hssio_state_inferred__3/i___3_n_0\,
      \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[4]\ => wait_pll0_x_fab_clk_timeout_sync,
      \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[6]\ => sync_cell_pll0lock_inst_n_9,
      \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[7]\ => all_bsc_dly_rdy,
      \GEN_RIU_NOT_FROM_PLL.rst_seq_done_reg\ => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_3_n_0\,
      \GEN_RIU_NOT_FROM_PLL.rst_seq_done_reg_0\ => \^gen_riu_not_from_pll.rst_seq_done_reg_0\,
      \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg\ => wait_pll_lock_timeout_i_3_n_0,
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg\ => sync_cell_pll0lock_inst_n_8,
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\ => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_1\,
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_1\ => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_5_n_0\,
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_2\ => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_2_n_0\,
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_3\ => sync_cell_wait_pll0_fab_timeout_inst_n_2,
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_4\ => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_i_5_n_0\,
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_5\ => sync_cell_dly_rdy_inst_n_1,
      Q(8) => hssio_state(8),
      Q(7) => \^q\(0),
      Q(6) => bsc_en_vtc_1,
      Q(5 downto 0) => hssio_state(5 downto 0),
      bs_dly_rst => bs_dly_rst,
      bsc_en_vtc => bsc_en_vtc,
      n0_vtc_rdy_out => n0_vtc_rdy_out,
      n1_vtc_rdy_out => n1_vtc_rdy_out,
      \out\ => locked,
      pll0_locked_out => pll0_locked_out,
      riu_clk => riu_clk,
      rst_seq_done => rst_seq_done,
      \sync_flop_1_reg[0]_0\ => sync_cell_pll0lock_inst_n_7,
      \sync_flop_1_reg[0]_1\ => sync_cell_pll0lock_inst_n_10,
      \sync_flop_1_reg[0]_2\ => sync_cell_pll0lock_inst_n_11,
      timeout_cntr_rst => timeout_cntr_rst
    );
sync_cell_rst_inst: entity work.design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_221
     port map (
      \out\ => rst_in_sync,
      riu_clk => riu_clk,
      rst => rst
    );
sync_cell_start_fab_cntr_pll0_inst: entity work.design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_222
     port map (
      CLK => CLK,
      Q(0) => pll0_fab_clk_cntr_reg(6),
      SR(0) => sync_cell_start_fab_cntr_pll0_inst_n_0,
      in0(0) => \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg_n_0\,
      \pll0_fab_clk_cntr_reg[0]\ => \pll0_fab_clk_cntr[6]_i_3_n_0\
    );
sync_cell_wait_pll0_fab_timeout_inst: entity work.design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell_223
     port map (
      D(0) => p_0_in_0(5),
      \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[3]\ => sync_cell_wait_pll0_fab_timeout_inst_n_2,
      \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[4]\ => sync_cell_wait_pll0_fab_timeout_inst_n_4,
      \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[5]\ => \hssio_state_inferred__3/i___3_n_0\,
      \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[5]_0\ => all_bsc_dly_rdy,
      \GEN_RIU_NOT_FROM_PLL.pll0_clkoutphy_en_reg\ => locked,
      \GEN_RIU_NOT_FROM_PLL.pll0_clkoutphy_en_reg_0\ => wait_pll_lock_timeout_i_3_n_0,
      \GEN_RIU_NOT_FROM_PLL.pll0_clkoutphy_en_reg_1\ => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_3_n_0\,
      \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg\ => \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_i_2_n_0\,
      \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg_0\ => sync_cell_pll0lock_inst_n_7,
      \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg_1\(0) => \GEN_RIU_NOT_FROM_PLL.start_fab_clk_cntr_reg_n_0\,
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg\ => \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_3_n_0\,
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\ => \GEN_RIU_NOT_FROM_PLL.rst_seq_done_i_4_n_0\,
      Q(5) => hssio_state(8),
      Q(4) => bsc_en_vtc_1,
      Q(3 downto 0) => hssio_state(5 downto 2),
      in0(0) => wait_pll0_x_fab_clk_timeout,
      \out\ => wait_pll0_x_fab_clk_timeout_sync,
      pll0_clkoutphy_en_in => \^pll0_clkoutphy_en_in\,
      riu_clk => riu_clk,
      \sync_flop_1_reg[0]_0\ => sync_cell_wait_pll0_fab_timeout_inst_n_3
    );
\timeout_cntr[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => timeout_cntr_reg(0),
      I1 => timeout_cntr_reg(1),
      I2 => \timeout_cntr[0]_i_3_n_0\,
      I3 => \timeout_cntr[0]_i_4_n_0\,
      I4 => \timeout_cntr[0]_i_5_n_0\,
      O => timeout_cntr
    );
\timeout_cntr[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFD"
    )
        port map (
      I0 => timeout_cntr_reg(6),
      I1 => timeout_cntr_reg(7),
      I2 => timeout_cntr_reg(4),
      I3 => timeout_cntr_reg(5),
      I4 => timeout_cntr_reg(3),
      I5 => timeout_cntr_reg(2),
      O => \timeout_cntr[0]_i_3_n_0\
    );
\timeout_cntr[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => timeout_cntr_reg(18),
      I1 => timeout_cntr_reg(19),
      I2 => timeout_cntr_reg(16),
      I3 => timeout_cntr_reg(17),
      I4 => timeout_cntr_reg(15),
      I5 => timeout_cntr_reg(14),
      O => \timeout_cntr[0]_i_4_n_0\
    );
\timeout_cntr[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => timeout_cntr_reg(12),
      I1 => timeout_cntr_reg(13),
      I2 => timeout_cntr_reg(10),
      I3 => timeout_cntr_reg(11),
      I4 => timeout_cntr_reg(8),
      I5 => timeout_cntr_reg(9),
      O => \timeout_cntr[0]_i_5_n_0\
    );
\timeout_cntr[0]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => timeout_cntr_reg(0),
      O => \timeout_cntr[0]_i_6_n_0\
    );
\timeout_cntr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[0]_i_2_n_15\,
      Q => timeout_cntr_reg(0),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[0]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \timeout_cntr_reg[0]_i_2_n_0\,
      CO(6) => \timeout_cntr_reg[0]_i_2_n_1\,
      CO(5) => \timeout_cntr_reg[0]_i_2_n_2\,
      CO(4) => \timeout_cntr_reg[0]_i_2_n_3\,
      CO(3) => \timeout_cntr_reg[0]_i_2_n_4\,
      CO(2) => \timeout_cntr_reg[0]_i_2_n_5\,
      CO(1) => \timeout_cntr_reg[0]_i_2_n_6\,
      CO(0) => \timeout_cntr_reg[0]_i_2_n_7\,
      DI(7 downto 0) => B"00000001",
      O(7) => \timeout_cntr_reg[0]_i_2_n_8\,
      O(6) => \timeout_cntr_reg[0]_i_2_n_9\,
      O(5) => \timeout_cntr_reg[0]_i_2_n_10\,
      O(4) => \timeout_cntr_reg[0]_i_2_n_11\,
      O(3) => \timeout_cntr_reg[0]_i_2_n_12\,
      O(2) => \timeout_cntr_reg[0]_i_2_n_13\,
      O(1) => \timeout_cntr_reg[0]_i_2_n_14\,
      O(0) => \timeout_cntr_reg[0]_i_2_n_15\,
      S(7 downto 1) => timeout_cntr_reg(7 downto 1),
      S(0) => \timeout_cntr[0]_i_6_n_0\
    );
\timeout_cntr_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[8]_i_1_n_13\,
      Q => timeout_cntr_reg(10),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[8]_i_1_n_12\,
      Q => timeout_cntr_reg(11),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[8]_i_1_n_11\,
      Q => timeout_cntr_reg(12),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[8]_i_1_n_10\,
      Q => timeout_cntr_reg(13),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[8]_i_1_n_9\,
      Q => timeout_cntr_reg(14),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[8]_i_1_n_8\,
      Q => timeout_cntr_reg(15),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[16]_i_1_n_15\,
      Q => timeout_cntr_reg(16),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[16]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \timeout_cntr_reg[8]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_timeout_cntr_reg[16]_i_1_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \timeout_cntr_reg[16]_i_1_n_5\,
      CO(1) => \timeout_cntr_reg[16]_i_1_n_6\,
      CO(0) => \timeout_cntr_reg[16]_i_1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 4) => \NLW_timeout_cntr_reg[16]_i_1_O_UNCONNECTED\(7 downto 4),
      O(3) => \timeout_cntr_reg[16]_i_1_n_12\,
      O(2) => \timeout_cntr_reg[16]_i_1_n_13\,
      O(1) => \timeout_cntr_reg[16]_i_1_n_14\,
      O(0) => \timeout_cntr_reg[16]_i_1_n_15\,
      S(7 downto 4) => B"0000",
      S(3 downto 0) => timeout_cntr_reg(19 downto 16)
    );
\timeout_cntr_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[16]_i_1_n_14\,
      Q => timeout_cntr_reg(17),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[16]_i_1_n_13\,
      Q => timeout_cntr_reg(18),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[16]_i_1_n_12\,
      Q => timeout_cntr_reg(19),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[0]_i_2_n_14\,
      Q => timeout_cntr_reg(1),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[0]_i_2_n_13\,
      Q => timeout_cntr_reg(2),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[0]_i_2_n_12\,
      Q => timeout_cntr_reg(3),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[0]_i_2_n_11\,
      Q => timeout_cntr_reg(4),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[0]_i_2_n_10\,
      Q => timeout_cntr_reg(5),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[0]_i_2_n_9\,
      Q => timeout_cntr_reg(6),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[0]_i_2_n_8\,
      Q => timeout_cntr_reg(7),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[8]_i_1_n_15\,
      Q => timeout_cntr_reg(8),
      R => timeout_cntr_rst
    );
\timeout_cntr_reg[8]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \timeout_cntr_reg[0]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \timeout_cntr_reg[8]_i_1_n_0\,
      CO(6) => \timeout_cntr_reg[8]_i_1_n_1\,
      CO(5) => \timeout_cntr_reg[8]_i_1_n_2\,
      CO(4) => \timeout_cntr_reg[8]_i_1_n_3\,
      CO(3) => \timeout_cntr_reg[8]_i_1_n_4\,
      CO(2) => \timeout_cntr_reg[8]_i_1_n_5\,
      CO(1) => \timeout_cntr_reg[8]_i_1_n_6\,
      CO(0) => \timeout_cntr_reg[8]_i_1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \timeout_cntr_reg[8]_i_1_n_8\,
      O(6) => \timeout_cntr_reg[8]_i_1_n_9\,
      O(5) => \timeout_cntr_reg[8]_i_1_n_10\,
      O(4) => \timeout_cntr_reg[8]_i_1_n_11\,
      O(3) => \timeout_cntr_reg[8]_i_1_n_12\,
      O(2) => \timeout_cntr_reg[8]_i_1_n_13\,
      O(1) => \timeout_cntr_reg[8]_i_1_n_14\,
      O(0) => \timeout_cntr_reg[8]_i_1_n_15\,
      S(7 downto 0) => timeout_cntr_reg(15 downto 8)
    );
\timeout_cntr_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => timeout_cntr,
      D => \timeout_cntr_reg[8]_i_1_n_14\,
      Q => timeout_cntr_reg(9),
      R => timeout_cntr_rst
    );
wait_pll0_x_fab_clk_timeout_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pll0_fab_clk_cntr_reg(6),
      Q => wait_pll0_x_fab_clk_timeout,
      R => '0'
    );
wait_pll_lock_timeout_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000002222E222"
    )
        port map (
      I0 => wait_pll_lock_timeout_reg_n_0,
      I1 => wait_pll_lock_timeout_i_2_n_0,
      I2 => wait_pll_lock_timeout_i_3_n_0,
      I3 => hssio_state(2),
      I4 => wait_pll_lock_timeout_i_4_n_0,
      I5 => timeout_cntr_rst,
      O => wait_pll_lock_timeout_i_1_n_0
    );
wait_pll_lock_timeout_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000800080000000"
    )
        port map (
      I0 => wait_pll_lock_timeout_i_5_n_0,
      I1 => wait_pll_lock_timeout_i_6_n_0,
      I2 => wait_pll_lock_timeout_i_7_n_0,
      I3 => wait_pll_lock_timeout_i_8_n_0,
      I4 => \GEN_RIU_NOT_FROM_PLL.bsc_en_vtc_i_2_n_0\,
      I5 => wait_pll_lock_timeout_i_9_n_0,
      O => wait_pll_lock_timeout_i_2_n_0
    );
wait_pll_lock_timeout_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => hssio_state(0),
      I1 => \^q\(0),
      I2 => hssio_state(5),
      I3 => hssio_state(8),
      I4 => hssio_state(3),
      I5 => hssio_state(1),
      O => wait_pll_lock_timeout_i_3_n_0
    );
wait_pll_lock_timeout_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => hssio_state(4),
      I1 => bsc_en_vtc_1,
      O => wait_pll_lock_timeout_i_4_n_0
    );
wait_pll_lock_timeout_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => timeout_cntr_reg(0),
      I1 => timeout_cntr_reg(1),
      O => wait_pll_lock_timeout_i_5_n_0
    );
wait_pll_lock_timeout_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080000000000000"
    )
        port map (
      I0 => timeout_cntr_reg(16),
      I1 => timeout_cntr_reg(17),
      I2 => timeout_cntr_reg(14),
      I3 => timeout_cntr_reg(15),
      I4 => timeout_cntr_reg(19),
      I5 => timeout_cntr_reg(18),
      O => wait_pll_lock_timeout_i_6_n_0
    );
wait_pll_lock_timeout_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => timeout_cntr_reg(4),
      I1 => timeout_cntr_reg(5),
      I2 => timeout_cntr_reg(2),
      I3 => timeout_cntr_reg(3),
      I4 => timeout_cntr_reg(7),
      I5 => timeout_cntr_reg(6),
      O => wait_pll_lock_timeout_i_7_n_0
    );
wait_pll_lock_timeout_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => timeout_cntr_reg(10),
      I1 => timeout_cntr_reg(11),
      I2 => timeout_cntr_reg(9),
      I3 => timeout_cntr_reg(8),
      I4 => timeout_cntr_reg(13),
      I5 => timeout_cntr_reg(12),
      O => wait_pll_lock_timeout_i_8_n_0
    );
wait_pll_lock_timeout_i_9: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EB"
    )
        port map (
      I0 => hssio_state(0),
      I1 => \^q\(0),
      I2 => hssio_state(5),
      O => wait_pll_lock_timeout_i_9_n_0
    );
wait_pll_lock_timeout_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => riu_clk,
      CE => '1',
      D => wait_pll_lock_timeout_i_1_n_0,
      Q => wait_pll_lock_timeout_reg_n_0,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_lpf is
  port (
    lpf_int : out STD_LOGIC;
    slowest_sync_clk : in STD_LOGIC;
    ext_reset_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_lpf : entity is "lpf";
end design_1_Vsp_core_0_0_lpf;

architecture STRUCTURE of design_1_Vsp_core_0_0_lpf is
  signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
  signal Q : STD_LOGIC;
  signal exr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
  signal lpf_exr : STD_LOGIC;
  signal lpf_int0 : STD_LOGIC;
  signal p_1_in4_in : STD_LOGIC;
  signal p_2_in3_in : STD_LOGIC;
  signal p_3_in6_in : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of POR_SRL_I : label is "VCC:CE";
  attribute box_type : string;
  attribute box_type of POR_SRL_I : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of POR_SRL_I : label is "\U0/myCamif/myMipirx /inst/i_0/r_sync/U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.design_1_Vsp_core_0_0_cdc_sync
     port map (
      exr_lpf(0) => exr_lpf(0),
      ext_reset_in => ext_reset_in,
      lpf_exr => lpf_exr,
      lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
      p_1_in4_in => p_1_in4_in,
      p_2_in3_in => p_2_in3_in,
      scndry_out => p_3_in6_in,
      slowest_sync_clk => slowest_sync_clk
    );
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => p_3_in6_in,
      Q => p_2_in3_in,
      R => '0'
    );
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => p_2_in3_in,
      Q => p_1_in4_in,
      R => '0'
    );
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => p_1_in4_in,
      Q => exr_lpf(0),
      R => '0'
    );
POR_SRL_I: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"FFFF"
    )
        port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => '1',
      CLK => slowest_sync_clk,
      D => '0',
      Q => Q
    );
lpf_exr_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
      Q => lpf_exr,
      R => '0'
    );
lpf_int_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => lpf_exr,
      I1 => Q,
      O => lpf_int0
    );
lpf_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => lpf_int0,
      Q => lpf_int,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_sequence_psr is
  port (
    Pr_out : out STD_LOGIC;
    lpf_int : in STD_LOGIC;
    slowest_sync_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_sequence_psr : entity is "sequence_psr";
end design_1_Vsp_core_0_0_sequence_psr;

architecture STRUCTURE of design_1_Vsp_core_0_0_sequence_psr is
  signal Core_i_1_n_0 : STD_LOGIC;
  signal MB_out : STD_LOGIC;
  signal \^pr_out\ : STD_LOGIC;
  signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
  signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
  signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
  signal from_sys_i_1_n_0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \pr_dec0__0\ : STD_LOGIC;
  signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
  signal \pr_dec_reg_n_0_[1]\ : STD_LOGIC;
  signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
  signal pr_i_1_n_0 : STD_LOGIC;
  signal seq_clr : STD_LOGIC;
  signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal seq_cnt_en : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair183";
  attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair182";
  attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair184";
  attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair183";
  attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair182";
  attribute SOFT_HLUTNM of \pr_dec[2]_i_1\ : label is "soft_lutpair184";
begin
  Pr_out <= \^pr_out\;
Core_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MB_out,
      I1 => p_0_in,
      O => Core_i_1_n_0
    );
Core_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => Core_i_1_n_0,
      Q => MB_out,
      S => lpf_int
    );
SEQ_COUNTER: entity work.design_1_Vsp_core_0_0_upcnt_n
     port map (
      Q(5 downto 0) => seq_cnt(5 downto 0),
      seq_clr => seq_clr,
      seq_cnt_en => seq_cnt_en,
      slowest_sync_clk => slowest_sync_clk
    );
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9000"
    )
        port map (
      I0 => seq_cnt_en,
      I1 => seq_cnt(4),
      I2 => seq_cnt(5),
      I3 => seq_cnt(3),
      O => \core_dec[0]_i_1_n_0\
    );
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pr_dec_reg_n_0_[1]\,
      I1 => \core_dec_reg_n_0_[0]\,
      O => \core_dec[2]_i_1_n_0\
    );
\core_dec_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => \core_dec[0]_i_1_n_0\,
      Q => \core_dec_reg_n_0_[0]\,
      R => '0'
    );
\core_dec_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => \core_dec[2]_i_1_n_0\,
      Q => p_0_in,
      R => '0'
    );
from_sys_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => MB_out,
      I1 => seq_cnt_en,
      O => from_sys_i_1_n_0
    );
from_sys_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => from_sys_i_1_n_0,
      Q => seq_cnt_en,
      S => lpf_int
    );
pr_dec0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0018"
    )
        port map (
      I0 => seq_cnt_en,
      I1 => seq_cnt(0),
      I2 => seq_cnt(2),
      I3 => seq_cnt(1),
      O => \pr_dec0__0\
    );
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1080"
    )
        port map (
      I0 => seq_cnt_en,
      I1 => seq_cnt(5),
      I2 => seq_cnt(3),
      I3 => seq_cnt(4),
      O => p_3_out(0)
    );
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \pr_dec_reg_n_0_[1]\,
      I1 => \pr_dec_reg_n_0_[0]\,
      O => p_3_out(2)
    );
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => p_3_out(0),
      Q => \pr_dec_reg_n_0_[0]\,
      R => '0'
    );
\pr_dec_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => \pr_dec0__0\,
      Q => \pr_dec_reg_n_0_[1]\,
      R => '0'
    );
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => p_3_out(2),
      Q => \pr_dec_reg_n_0_[2]\,
      R => '0'
    );
pr_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^pr_out\,
      I1 => \pr_dec_reg_n_0_[2]\,
      O => pr_i_1_n_0
    );
pr_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => pr_i_1_n_0,
      Q => \^pr_out\,
      S => lpf_int
    );
seq_clr_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => '1',
      Q => seq_clr,
      R => lpf_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_cdc_handshake is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of design_1_Vsp_core_0_0_xpm_cdc_handshake : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_handshake : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_handshake : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_cdc_handshake : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of design_1_Vsp_core_0_0_xpm_cdc_handshake : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_handshake : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of design_1_Vsp_core_0_0_xpm_cdc_handshake : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of design_1_Vsp_core_0_0_xpm_cdc_handshake : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of design_1_Vsp_core_0_0_xpm_cdc_handshake : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of design_1_Vsp_core_0_0_xpm_cdc_handshake : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of design_1_Vsp_core_0_0_xpm_cdc_handshake : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of design_1_Vsp_core_0_0_xpm_cdc_handshake : entity is "HANDSHAKE";
end design_1_Vsp_core_0_0_xpm_cdc_handshake;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_cdc_handshake is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__220\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__219\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\ : entity is 2;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized0\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[1]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(1 downto 0) <= dest_hsdata_ff(1 downto 0);
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(0),
      Q => dest_hsdata_ff(0),
      R => '0'
    );
\dest_hsdata_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(1),
      Q => dest_hsdata_ff(1),
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_sendd_ff,
      O => p_0_in
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(0),
      Q => src_hsdata_ff(0),
      R => '0'
    );
\src_hsdata_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(1),
      Q => src_hsdata_ff(1),
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__148\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__147\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 25 downto 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 25 downto 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\ : entity is 26;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__parameterized1\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC_VECTOR ( 25 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC_VECTOR ( 25 downto 0 );
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[10]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[10]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[11]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[11]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[12]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[12]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[13]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[13]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[14]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[14]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[15]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[15]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[16]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[16]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[17]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[17]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[18]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[18]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[19]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[19]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[1]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[20]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[20]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[21]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[21]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[22]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[22]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[23]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[23]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[24]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[24]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[25]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[25]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[2]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[3]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[3]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[4]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[4]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[5]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[5]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[6]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[6]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[7]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[7]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[8]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[8]\ : label is "HANDSHAKE";
  attribute KEEP of \dest_hsdata_ff_reg[9]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[9]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(25 downto 0) <= dest_hsdata_ff(25 downto 0);
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(0),
      Q => dest_hsdata_ff(0),
      R => '0'
    );
\dest_hsdata_ff_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(10),
      Q => dest_hsdata_ff(10),
      R => '0'
    );
\dest_hsdata_ff_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(11),
      Q => dest_hsdata_ff(11),
      R => '0'
    );
\dest_hsdata_ff_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(12),
      Q => dest_hsdata_ff(12),
      R => '0'
    );
\dest_hsdata_ff_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(13),
      Q => dest_hsdata_ff(13),
      R => '0'
    );
\dest_hsdata_ff_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(14),
      Q => dest_hsdata_ff(14),
      R => '0'
    );
\dest_hsdata_ff_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(15),
      Q => dest_hsdata_ff(15),
      R => '0'
    );
\dest_hsdata_ff_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(16),
      Q => dest_hsdata_ff(16),
      R => '0'
    );
\dest_hsdata_ff_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(17),
      Q => dest_hsdata_ff(17),
      R => '0'
    );
\dest_hsdata_ff_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(18),
      Q => dest_hsdata_ff(18),
      R => '0'
    );
\dest_hsdata_ff_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(19),
      Q => dest_hsdata_ff(19),
      R => '0'
    );
\dest_hsdata_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(1),
      Q => dest_hsdata_ff(1),
      R => '0'
    );
\dest_hsdata_ff_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(20),
      Q => dest_hsdata_ff(20),
      R => '0'
    );
\dest_hsdata_ff_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(21),
      Q => dest_hsdata_ff(21),
      R => '0'
    );
\dest_hsdata_ff_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(22),
      Q => dest_hsdata_ff(22),
      R => '0'
    );
\dest_hsdata_ff_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(23),
      Q => dest_hsdata_ff(23),
      R => '0'
    );
\dest_hsdata_ff_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(24),
      Q => dest_hsdata_ff(24),
      R => '0'
    );
\dest_hsdata_ff_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(25),
      Q => dest_hsdata_ff(25),
      R => '0'
    );
\dest_hsdata_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(2),
      Q => dest_hsdata_ff(2),
      R => '0'
    );
\dest_hsdata_ff_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(3),
      Q => dest_hsdata_ff(3),
      R => '0'
    );
\dest_hsdata_ff_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(4),
      Q => dest_hsdata_ff(4),
      R => '0'
    );
\dest_hsdata_ff_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(5),
      Q => dest_hsdata_ff(5),
      R => '0'
    );
\dest_hsdata_ff_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(6),
      Q => dest_hsdata_ff(6),
      R => '0'
    );
\dest_hsdata_ff_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(7),
      Q => dest_hsdata_ff(7),
      R => '0'
    );
\dest_hsdata_ff_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(8),
      Q => dest_hsdata_ff(8),
      R => '0'
    );
\dest_hsdata_ff_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff(9),
      Q => dest_hsdata_ff(9),
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[25]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => src_sendd_ff,
      O => p_0_in
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(0),
      Q => src_hsdata_ff(0),
      R => '0'
    );
\src_hsdata_ff_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(10),
      Q => src_hsdata_ff(10),
      R => '0'
    );
\src_hsdata_ff_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(11),
      Q => src_hsdata_ff(11),
      R => '0'
    );
\src_hsdata_ff_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(12),
      Q => src_hsdata_ff(12),
      R => '0'
    );
\src_hsdata_ff_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(13),
      Q => src_hsdata_ff(13),
      R => '0'
    );
\src_hsdata_ff_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(14),
      Q => src_hsdata_ff(14),
      R => '0'
    );
\src_hsdata_ff_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(15),
      Q => src_hsdata_ff(15),
      R => '0'
    );
\src_hsdata_ff_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(16),
      Q => src_hsdata_ff(16),
      R => '0'
    );
\src_hsdata_ff_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(17),
      Q => src_hsdata_ff(17),
      R => '0'
    );
\src_hsdata_ff_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(18),
      Q => src_hsdata_ff(18),
      R => '0'
    );
\src_hsdata_ff_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(19),
      Q => src_hsdata_ff(19),
      R => '0'
    );
\src_hsdata_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(1),
      Q => src_hsdata_ff(1),
      R => '0'
    );
\src_hsdata_ff_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(20),
      Q => src_hsdata_ff(20),
      R => '0'
    );
\src_hsdata_ff_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(21),
      Q => src_hsdata_ff(21),
      R => '0'
    );
\src_hsdata_ff_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(22),
      Q => src_hsdata_ff(22),
      R => '0'
    );
\src_hsdata_ff_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(23),
      Q => src_hsdata_ff(23),
      R => '0'
    );
\src_hsdata_ff_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(24),
      Q => src_hsdata_ff(24),
      R => '0'
    );
\src_hsdata_ff_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(25),
      Q => src_hsdata_ff(25),
      R => '0'
    );
\src_hsdata_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(2),
      Q => src_hsdata_ff(2),
      R => '0'
    );
\src_hsdata_ff_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(3),
      Q => src_hsdata_ff(3),
      R => '0'
    );
\src_hsdata_ff_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(4),
      Q => src_hsdata_ff(4),
      R => '0'
    );
\src_hsdata_ff_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(5),
      Q => src_hsdata_ff(5),
      R => '0'
    );
\src_hsdata_ff_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(6),
      Q => src_hsdata_ff(6),
      R => '0'
    );
\src_hsdata_ff_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(7),
      Q => src_hsdata_ff(7),
      R => '0'
    );
\src_hsdata_ff_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(8),
      Q => src_hsdata_ff(8),
      R => '0'
    );
\src_hsdata_ff_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => p_0_in,
      D => src_in(9),
      Q => src_hsdata_ff(9),
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__133\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__132\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__1\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__238\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__237\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__10\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__202\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__201\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__11\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__200\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__199\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__12\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__236\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__235\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__13\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__198\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__197\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__14\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__196\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__195\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__15\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__194\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__193\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__16\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__192\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__191\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__17\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__190\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__189\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__18\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__188\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__187\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__19\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__186\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__185\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__2\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__218\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__217\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__20\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__184\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__183\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__21\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__182\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__181\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__22\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__180\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__179\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__23\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__234\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__233\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__24\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__178\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__177\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__25\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__176\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__175\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__26\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__174\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__173\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__27\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__172\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__171\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__28\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__170\
     port map (
      dest_clk => src_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__169\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__29\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__168\
     port map (
      dest_clk => src_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__167\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__3\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__216\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__215\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__30\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__166\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__165\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__31\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__164\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__163\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__32\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__162\
     port map (
      dest_clk => src_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__161\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__33\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__160\
     port map (
      dest_clk => src_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__159\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__34\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__232\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__231\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__35\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__158\
     port map (
      dest_clk => src_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__157\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__36\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__156\
     port map (
      dest_clk => src_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__155\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__37\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__154\
     port map (
      dest_clk => src_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__153\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__38\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__152\
     port map (
      dest_clk => src_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__151\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__39\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__150\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__149\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__4\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__214\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__213\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__40\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__230\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__229\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__41\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__228\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__227\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__42\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__226\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__225\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__43\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__224\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__223\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__44\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__222\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__221\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__5\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__212\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__211\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__6\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__210\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__209\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__7\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__208\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__207\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__8\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__206\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__205\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    src_send : in STD_LOGIC;
    src_rcv : out STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    dest_req : out STD_LOGIC;
    dest_ack : in STD_LOGIC
  );
  attribute DEST_EXT_HSK : integer;
  attribute DEST_EXT_HSK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\ : entity is 0;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\ : entity is "xpm_cdc_handshake";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\ : entity is 0;
  attribute SRC_SYNC_FF : integer;
  attribute SRC_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\ : entity is 3;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\ : entity is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\ : entity is "HANDSHAKE";
end \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_handshake__xdcDup__9\ is
  signal dest_hsdata_en : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
  signal dest_hsdata_ff : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
  attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
  signal dest_req_ff : STD_LOGIC;
  signal dest_req_nxt : STD_LOGIC;
  signal src_hsdata_ff : STD_LOGIC;
  signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
  signal src_sendd_ff : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
  attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
  attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_dest2src_inst : label is "true";
  attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
  attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
  attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_src2dest_inst : label is "true";
begin
  dest_out(0) <= dest_hsdata_ff;
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => dest_hsdata_en,
      D => src_hsdata_ff,
      Q => dest_hsdata_ff,
      R => '0'
    );
dest_req_ext_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_req_nxt,
      I1 => dest_req_ff,
      O => dest_hsdata_en
    );
dest_req_ext_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_hsdata_en,
      Q => dest_req,
      R => '0'
    );
dest_req_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_req_nxt,
      Q => dest_req_ff,
      R => '0'
    );
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => src_hsdata_ff,
      I1 => src_sendd_ff,
      I2 => src_in(0),
      O => \src_hsdata_ff[0]_i_1_n_0\
    );
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => \src_hsdata_ff[0]_i_1_n_0\,
      Q => src_hsdata_ff,
      R => '0'
    );
src_sendd_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_send,
      Q => src_sendd_ff,
      R => '0'
    );
xpm_cdc_single_dest2src_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__204\
     port map (
      dest_clk => dest_clk,
      dest_out => src_rcv,
      src_clk => '0',
      src_in => dest_req_ff
    );
xpm_cdc_single_src2dest_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__203\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_req_nxt,
      src_clk => '0',
      src_in => src_sendd_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_cdc_pulse is
  port (
    src_clk : in STD_LOGIC;
    src_pulse : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    src_rst : in STD_LOGIC;
    dest_rst : in STD_LOGIC;
    dest_pulse : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_pulse : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of design_1_Vsp_core_0_0_xpm_cdc_pulse : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_cdc_pulse : entity is "xpm_cdc_pulse";
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of design_1_Vsp_core_0_0_xpm_cdc_pulse : entity is 0;
  attribute RST_USED : integer;
  attribute RST_USED of design_1_Vsp_core_0_0_xpm_cdc_pulse : entity is 1;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of design_1_Vsp_core_0_0_xpm_cdc_pulse : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of design_1_Vsp_core_0_0_xpm_cdc_pulse : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of design_1_Vsp_core_0_0_xpm_cdc_pulse : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of design_1_Vsp_core_0_0_xpm_cdc_pulse : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of design_1_Vsp_core_0_0_xpm_cdc_pulse : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of design_1_Vsp_core_0_0_xpm_cdc_pulse : entity is "PULSE";
end design_1_Vsp_core_0_0_xpm_cdc_pulse;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_cdc_pulse is
  signal dest_event_ff : STD_LOGIC;
  signal dest_event_ff_i_1_n_0 : STD_LOGIC;
  signal dest_sync_out : STD_LOGIC;
  signal src_in_ff : STD_LOGIC;
  signal src_level_ff : STD_LOGIC;
  signal src_level_nxt : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of dest_event_ff_i_1 : label is "soft_lutpair228";
  attribute SOFT_HLUTNM of dest_pulse_INST_0 : label is "soft_lutpair228";
  attribute DEST_SYNC_FF of xpm_cdc_single_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_inst : label is 0;
  attribute VERSION of xpm_cdc_single_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_inst : label is "true";
begin
dest_event_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_sync_out,
      I1 => dest_rst,
      O => dest_event_ff_i_1_n_0
    );
dest_event_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_event_ff_i_1_n_0,
      Q => dest_event_ff,
      R => '0'
    );
dest_pulse_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9A"
    )
        port map (
      I0 => dest_event_ff,
      I1 => dest_rst,
      I2 => dest_sync_out,
      O => dest_pulse
    );
src_in_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_pulse,
      Q => src_in_ff,
      R => src_rst
    );
src_level_ff_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => src_in_ff,
      I1 => src_pulse,
      I2 => src_level_ff,
      O => src_level_nxt
    );
src_level_ff_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => src_clk,
      CE => '1',
      D => src_level_nxt,
      Q => src_level_ff,
      R => src_rst
    );
xpm_cdc_single_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__134\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_sync_out,
      src_clk => '0',
      src_in => src_level_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__1\ is
  port (
    src_clk : in STD_LOGIC;
    src_pulse : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    src_rst : in STD_LOGIC;
    dest_rst : in STD_LOGIC;
    dest_pulse : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__1\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__1\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__1\ : entity is "xpm_cdc_pulse";
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__1\ : entity is 0;
  attribute RST_USED : integer;
  attribute RST_USED of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__1\ : entity is 1;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__1\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__1\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__1\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__1\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__1\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__1\ : entity is "PULSE";
end \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__1\ is
  signal dest_event_ff : STD_LOGIC;
  signal dest_event_ff_i_1_n_0 : STD_LOGIC;
  signal dest_sync_out : STD_LOGIC;
  signal src_in_ff : STD_LOGIC;
  signal src_level_ff : STD_LOGIC;
  signal src_level_nxt : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of dest_event_ff_i_1 : label is "soft_lutpair185";
  attribute SOFT_HLUTNM of dest_pulse_INST_0 : label is "soft_lutpair185";
  attribute DEST_SYNC_FF of xpm_cdc_single_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_inst : label is 0;
  attribute VERSION of xpm_cdc_single_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_inst : label is "true";
begin
dest_event_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_sync_out,
      I1 => dest_rst,
      O => dest_event_ff_i_1_n_0
    );
dest_event_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_event_ff_i_1_n_0,
      Q => dest_event_ff,
      R => '0'
    );
dest_pulse_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9A"
    )
        port map (
      I0 => dest_event_ff,
      I1 => dest_rst,
      I2 => dest_sync_out,
      O => dest_pulse
    );
src_in_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_pulse,
      Q => src_in_ff,
      R => src_rst
    );
src_level_ff_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => src_in_ff,
      I1 => src_pulse,
      I2 => src_level_ff,
      O => src_level_nxt
    );
src_level_ff_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => src_clk,
      CE => '1',
      D => src_level_nxt,
      Q => src_level_ff,
      R => src_rst
    );
xpm_cdc_single_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__146\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_sync_out,
      src_clk => '0',
      src_in => src_level_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__2\ is
  port (
    src_clk : in STD_LOGIC;
    src_pulse : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    src_rst : in STD_LOGIC;
    dest_rst : in STD_LOGIC;
    dest_pulse : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__2\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__2\ : entity is "xpm_cdc_pulse";
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__2\ : entity is 0;
  attribute RST_USED : integer;
  attribute RST_USED of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__2\ : entity is 1;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__2\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__2\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__2\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__2\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__2\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__2\ : entity is "PULSE";
end \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__2\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__2\ is
  signal dest_event_ff : STD_LOGIC;
  signal dest_event_ff_i_1_n_0 : STD_LOGIC;
  signal dest_sync_out : STD_LOGIC;
  signal src_in_ff : STD_LOGIC;
  signal src_level_ff : STD_LOGIC;
  signal src_level_nxt : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of dest_event_ff_i_1 : label is "soft_lutpair225";
  attribute SOFT_HLUTNM of dest_pulse_INST_0 : label is "soft_lutpair225";
  attribute DEST_SYNC_FF of xpm_cdc_single_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_inst : label is 0;
  attribute VERSION of xpm_cdc_single_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_inst : label is "true";
begin
dest_event_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_sync_out,
      I1 => dest_rst,
      O => dest_event_ff_i_1_n_0
    );
dest_event_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_event_ff_i_1_n_0,
      Q => dest_event_ff,
      R => '0'
    );
dest_pulse_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9A"
    )
        port map (
      I0 => dest_event_ff,
      I1 => dest_rst,
      I2 => dest_sync_out,
      O => dest_pulse
    );
src_in_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_pulse,
      Q => src_in_ff,
      R => src_rst
    );
src_level_ff_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => src_in_ff,
      I1 => src_pulse,
      I2 => src_level_ff,
      O => src_level_nxt
    );
src_level_ff_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => src_clk,
      CE => '1',
      D => src_level_nxt,
      Q => src_level_ff,
      R => src_rst
    );
xpm_cdc_single_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__137\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_sync_out,
      src_clk => '0',
      src_in => src_level_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__3\ is
  port (
    src_clk : in STD_LOGIC;
    src_pulse : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    src_rst : in STD_LOGIC;
    dest_rst : in STD_LOGIC;
    dest_pulse : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__3\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__3\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__3\ : entity is "xpm_cdc_pulse";
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__3\ : entity is 0;
  attribute RST_USED : integer;
  attribute RST_USED of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__3\ : entity is 1;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__3\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__3\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__3\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__3\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__3\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__3\ : entity is "PULSE";
end \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__3\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__3\ is
  signal dest_event_ff : STD_LOGIC;
  signal dest_event_ff_i_1_n_0 : STD_LOGIC;
  signal dest_sync_out : STD_LOGIC;
  signal src_in_ff : STD_LOGIC;
  signal src_level_ff : STD_LOGIC;
  signal src_level_nxt : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of dest_event_ff_i_1 : label is "soft_lutpair226";
  attribute SOFT_HLUTNM of dest_pulse_INST_0 : label is "soft_lutpair226";
  attribute DEST_SYNC_FF of xpm_cdc_single_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_inst : label is 0;
  attribute VERSION of xpm_cdc_single_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_inst : label is "true";
begin
dest_event_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_sync_out,
      I1 => dest_rst,
      O => dest_event_ff_i_1_n_0
    );
dest_event_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_event_ff_i_1_n_0,
      Q => dest_event_ff,
      R => '0'
    );
dest_pulse_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9A"
    )
        port map (
      I0 => dest_event_ff,
      I1 => dest_rst,
      I2 => dest_sync_out,
      O => dest_pulse
    );
src_in_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_pulse,
      Q => src_in_ff,
      R => src_rst
    );
src_level_ff_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => src_in_ff,
      I1 => src_pulse,
      I2 => src_level_ff,
      O => src_level_nxt
    );
src_level_ff_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => src_clk,
      CE => '1',
      D => src_level_nxt,
      Q => src_level_ff,
      R => src_rst
    );
xpm_cdc_single_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__136\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_sync_out,
      src_clk => '0',
      src_in => src_level_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__4\ is
  port (
    src_clk : in STD_LOGIC;
    src_pulse : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    src_rst : in STD_LOGIC;
    dest_rst : in STD_LOGIC;
    dest_pulse : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__4\ : entity is 3;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__4\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__4\ : entity is "xpm_cdc_pulse";
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__4\ : entity is 0;
  attribute RST_USED : integer;
  attribute RST_USED of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__4\ : entity is 1;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__4\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__4\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__4\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__4\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__4\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__4\ : entity is "PULSE";
end \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_cdc_pulse__xdcDup__4\ is
  signal dest_event_ff : STD_LOGIC;
  signal dest_event_ff_i_1_n_0 : STD_LOGIC;
  signal dest_sync_out : STD_LOGIC;
  signal src_in_ff : STD_LOGIC;
  signal src_level_ff : STD_LOGIC;
  signal src_level_nxt : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of dest_event_ff_i_1 : label is "soft_lutpair227";
  attribute SOFT_HLUTNM of dest_pulse_INST_0 : label is "soft_lutpair227";
  attribute DEST_SYNC_FF of xpm_cdc_single_inst : label is 3;
  attribute INIT_SYNC_FF of xpm_cdc_single_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_cdc_single_inst : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xpm_cdc_single_inst : label is 0;
  attribute VERSION of xpm_cdc_single_inst : label is 0;
  attribute XPM_CDC of xpm_cdc_single_inst : label is "SINGLE";
  attribute XPM_MODULE of xpm_cdc_single_inst : label is "TRUE";
  attribute is_du_within_envelope of xpm_cdc_single_inst : label is "true";
begin
dest_event_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dest_sync_out,
      I1 => dest_rst,
      O => dest_event_ff_i_1_n_0
    );
dest_event_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => dest_event_ff_i_1_n_0,
      Q => dest_event_ff,
      R => '0'
    );
dest_pulse_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9A"
    )
        port map (
      I0 => dest_event_ff,
      I1 => dest_rst,
      I2 => dest_sync_out,
      O => dest_pulse
    );
src_in_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => src_clk,
      CE => '1',
      D => src_pulse,
      Q => src_in_ff,
      R => src_rst
    );
src_level_ff_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => src_in_ff,
      I1 => src_pulse,
      I2 => src_level_ff,
      O => src_level_nxt
    );
src_level_ff_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => src_clk,
      CE => '1',
      D => src_level_nxt,
      Q => src_level_ff,
      R => src_rst
    );
xpm_cdc_single_inst: entity work.\design_1_Vsp_core_0_0_xpm_cdc_single__135\
     port map (
      dest_clk => dest_clk,
      dest_out => dest_sync_out,
      src_clk => '0',
      src_in => src_level_ff
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_base is
  port (
    sleep : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 11 downto 0 );
    full : out STD_LOGIC;
    full_n : out STD_LOGIC;
    prog_full : out STD_LOGIC;
    wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    overflow : out STD_LOGIC;
    wr_rst_busy : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    rd_clk : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
    empty : out STD_LOGIC;
    prog_empty : out STD_LOGIC;
    rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    underflow : out STD_LOGIC;
    rd_rst_busy : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    data_valid : out STD_LOGIC;
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC
  );
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 0;
  attribute CDC_DEST_SYNC_FF : integer;
  attribute CDC_DEST_SYNC_FF of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 2;
  attribute COMMON_CLOCK : integer;
  attribute COMMON_CLOCK of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 1;
  attribute DOUT_RESET_VALUE : string;
  attribute DOUT_RESET_VALUE of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "0";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 0;
  attribute ENABLE_ECC : integer;
  attribute ENABLE_ECC of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 0;
  attribute EN_ADV_FEATURE : string;
  attribute EN_ADV_FEATURE of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "16'b0000011100000111";
  attribute EN_AE : string;
  attribute EN_AE of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "1'b0";
  attribute EN_AF : string;
  attribute EN_AF of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "1'b0";
  attribute EN_DVLD : string;
  attribute EN_DVLD of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "1'b0";
  attribute EN_OF : string;
  attribute EN_OF of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "1'b1";
  attribute EN_PE : string;
  attribute EN_PE of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "1'b1";
  attribute EN_PF : string;
  attribute EN_PF of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "1'b1";
  attribute EN_RDC : string;
  attribute EN_RDC of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "1'b1";
  attribute EN_SIM_ASSERT_ERR : string;
  attribute EN_SIM_ASSERT_ERR of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "warning";
  attribute EN_UF : string;
  attribute EN_UF of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "1'b1";
  attribute EN_WACK : string;
  attribute EN_WACK of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "1'b0";
  attribute EN_WDC : string;
  attribute EN_WDC of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "1'b1";
  attribute FG_EQ_ASYM_DOUT : string;
  attribute FG_EQ_ASYM_DOUT of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "1'b0";
  attribute FIFO_MEMORY_TYPE : integer;
  attribute FIFO_MEMORY_TYPE of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 1;
  attribute FIFO_MEM_TYPE : integer;
  attribute FIFO_MEM_TYPE of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 1;
  attribute FIFO_READ_DEPTH : integer;
  attribute FIFO_READ_DEPTH of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 16;
  attribute FIFO_READ_LATENCY : integer;
  attribute FIFO_READ_LATENCY of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 1;
  attribute FIFO_SIZE : integer;
  attribute FIFO_SIZE of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 192;
  attribute FIFO_WRITE_DEPTH : integer;
  attribute FIFO_WRITE_DEPTH of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 16;
  attribute FULL_RESET_VALUE : integer;
  attribute FULL_RESET_VALUE of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 0;
  attribute FULL_RST_VAL : string;
  attribute FULL_RST_VAL of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "xpm_fifo_base";
  attribute PE_THRESH_ADJ : integer;
  attribute PE_THRESH_ADJ of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 3;
  attribute PE_THRESH_MAX : integer;
  attribute PE_THRESH_MAX of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 11;
  attribute PE_THRESH_MIN : integer;
  attribute PE_THRESH_MIN of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 5;
  attribute PF_THRESH_ADJ : integer;
  attribute PF_THRESH_ADJ of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 9;
  attribute PF_THRESH_MAX : integer;
  attribute PF_THRESH_MAX of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 11;
  attribute PF_THRESH_MIN : integer;
  attribute PF_THRESH_MIN of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 5;
  attribute PROG_EMPTY_THRESH : integer;
  attribute PROG_EMPTY_THRESH of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 5;
  attribute PROG_FULL_THRESH : integer;
  attribute PROG_FULL_THRESH of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 11;
  attribute RD_DATA_COUNT_WIDTH : integer;
  attribute RD_DATA_COUNT_WIDTH of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 5;
  attribute RD_DC_WIDTH_EXT : integer;
  attribute RD_DC_WIDTH_EXT of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 5;
  attribute RD_LATENCY : integer;
  attribute RD_LATENCY of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 2;
  attribute RD_MODE : integer;
  attribute RD_MODE of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 1;
  attribute RD_PNTR_WIDTH : integer;
  attribute RD_PNTR_WIDTH of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 4;
  attribute READ_DATA_WIDTH : integer;
  attribute READ_DATA_WIDTH of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 12;
  attribute READ_MODE : integer;
  attribute READ_MODE of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 1;
  attribute READ_MODE_LL : integer;
  attribute READ_MODE_LL of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 1;
  attribute RELATED_CLOCKS : integer;
  attribute RELATED_CLOCKS of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 0;
  attribute REMOVE_WR_RD_PROT_LOGIC : integer;
  attribute REMOVE_WR_RD_PROT_LOGIC of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 0;
  attribute USE_ADV_FEATURES : string;
  attribute USE_ADV_FEATURES of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "0707";
  attribute VERSION : integer;
  attribute VERSION of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 0;
  attribute WIDTH_RATIO : integer;
  attribute WIDTH_RATIO of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 1;
  attribute WRITE_DATA_WIDTH : integer;
  attribute WRITE_DATA_WIDTH of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 12;
  attribute WR_DATA_COUNT_WIDTH : integer;
  attribute WR_DATA_COUNT_WIDTH of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 5;
  attribute WR_DC_WIDTH_EXT : integer;
  attribute WR_DC_WIDTH_EXT of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 5;
  attribute WR_DEPTH_LOG : integer;
  attribute WR_DEPTH_LOG of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 4;
  attribute WR_PNTR_WIDTH : integer;
  attribute WR_PNTR_WIDTH of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 4;
  attribute WR_RD_RATIO : integer;
  attribute WR_RD_RATIO of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 0;
  attribute WR_WIDTH_LOG : integer;
  attribute WR_WIDTH_LOG of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 4;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "TRUE";
  attribute both_stages_valid : integer;
  attribute both_stages_valid of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 3;
  attribute invalid : integer;
  attribute invalid of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 0;
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of design_1_Vsp_core_0_0_xpm_fifo_base : entity is "soft";
  attribute stage1_valid : integer;
  attribute stage1_valid of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 2;
  attribute stage2_valid : integer;
  attribute stage2_valid of design_1_Vsp_core_0_0_xpm_fifo_base : entity is 1;
end design_1_Vsp_core_0_0_xpm_fifo_base;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_base is
  signal \<const0>\ : STD_LOGIC;
  signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^empty\ : STD_LOGIC;
  signal empty_fwft_i0 : STD_LOGIC;
  signal \gen_fwft.ram_regout_en\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\ : STD_LOGIC;
  signal leaving_empty0 : STD_LOGIC;
  signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ram_empty_i : STD_LOGIC;
  signal ram_empty_i0 : STD_LOGIC;
  signal ram_full_i0 : STD_LOGIC;
  signal ram_wr_en_pf : STD_LOGIC;
  signal rd_pntr_ext : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rdp_inst_n_2 : STD_LOGIC;
  signal rdpp1_inst_n_0 : STD_LOGIC;
  signal rdpp1_inst_n_1 : STD_LOGIC;
  signal rdpp1_inst_n_2 : STD_LOGIC;
  signal rdpp1_inst_n_3 : STD_LOGIC;
  signal rst_d1 : STD_LOGIC;
  signal wr_pntr_ext : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wrpp1_inst_n_0 : STD_LOGIC;
  signal wrpp1_inst_n_1 : STD_LOGIC;
  signal wrpp1_inst_n_2 : STD_LOGIC;
  signal wrpp1_inst_n_3 : STD_LOGIC;
  signal xpm_fifo_rst_inst_n_1 : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair283";
  attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\ : label is "soft_lutpair283";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
  attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
  attribute SOFT_HLUTNM of \gen_fwft.empty_fwft_i_i_1\ : label is "soft_lutpair282";
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \gen_sdpram.xpm_memory_base_inst\ : label is "[7:0]";
  attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute KEEP_HIERARCHY of \gen_sdpram.xpm_memory_base_inst\ : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 192;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_ECC_MODE : string;
  attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 16;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
  attribute P_MEMORY_PRIMITIVE : string;
  attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \gen_sdpram.xpm_memory_base_inst\ : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
  attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute SOFT_HLUTNM of \gen_sdpram.xpm_memory_base_inst_i_3\ : label is "soft_lutpair282";
begin
  almost_empty <= \<const0>\;
  almost_full <= \<const0>\;
  data_valid <= \<const0>\;
  dbiterr <= \<const0>\;
  empty <= \^empty\;
  full <= \<const0>\;
  full_n <= \<const0>\;
  overflow <= \<const0>\;
  prog_empty <= \<const0>\;
  prog_full <= \<const0>\;
  rd_data_count(4) <= \<const0>\;
  rd_data_count(3) <= \<const0>\;
  rd_data_count(2) <= \<const0>\;
  rd_data_count(1) <= \<const0>\;
  rd_data_count(0) <= \<const0>\;
  rd_rst_busy <= \<const0>\;
  sbiterr <= \<const0>\;
  underflow <= \<const0>\;
  wr_ack <= \<const0>\;
  wr_data_count(4) <= \<const0>\;
  wr_data_count(3) <= \<const0>\;
  wr_data_count(2) <= \<const0>\;
  wr_data_count(1) <= \<const0>\;
  wr_data_count(0) <= \<const0>\;
  wr_rst_busy <= \<const0>\;
\FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A85"
    )
        port map (
      I0 => curr_fwft_state(0),
      I1 => rd_en,
      I2 => curr_fwft_state(1),
      I3 => ram_empty_i,
      O => \next_fwft_state__0\(0)
    );
\FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7C"
    )
        port map (
      I0 => rd_en,
      I1 => curr_fwft_state(1),
      I2 => curr_fwft_state(0),
      O => \next_fwft_state__0\(1)
    );
\FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \next_fwft_state__0\(0),
      Q => curr_fwft_state(0),
      R => xpm_fifo_rst_inst_n_1
    );
\FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \next_fwft_state__0\(1),
      Q => curr_fwft_state(1),
      R => xpm_fifo_rst_inst_n_1
    );
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F380"
    )
        port map (
      I0 => rd_en,
      I1 => curr_fwft_state(0),
      I2 => curr_fwft_state(1),
      I3 => \^empty\,
      O => empty_fwft_i0
    );
\gen_fwft.empty_fwft_i_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => empty_fwft_i0,
      Q => \^empty\,
      S => xpm_fifo_rst_inst_n_1
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => ram_full_i0,
      Q => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\,
      R => xpm_fifo_rst_inst_n_1
    );
\gen_pntr_flags_cc.ram_empty_i_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => ram_empty_i0,
      Q => ram_empty_i,
      S => xpm_fifo_rst_inst_n_1
    );
\gen_sdpram.xpm_memory_base_inst\: entity work.design_1_Vsp_core_0_0_xpm_memory_base
     port map (
      addra(3 downto 0) => wr_pntr_ext(3 downto 0),
      addrb(3 downto 0) => rd_pntr_ext(3 downto 0),
      clka => wr_clk,
      clkb => '0',
      dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\,
      dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\,
      dina(11 downto 0) => din(11 downto 0),
      dinb(11 downto 0) => B"000000000000",
      douta(11 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(11 downto 0),
      doutb(11 downto 0) => dout(11 downto 0),
      ena => ram_wr_en_pf,
      enb => rdp_inst_n_2,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => \gen_fwft.ram_regout_en\,
      rsta => '0',
      rstb => xpm_fifo_rst_inst_n_1,
      sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\,
      sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\,
      sleep => '0',
      wea(0) => '0',
      web(0) => '0'
    );
\gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"62"
    )
        port map (
      I0 => curr_fwft_state(0),
      I1 => curr_fwft_state(1),
      I2 => rd_en,
      O => \gen_fwft.ram_regout_en\
    );
rdp_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_148\
     port map (
      E(0) => ram_wr_en_pf,
      Q(3 downto 0) => rd_pntr_ext(3 downto 0),
      \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
      \count_value_i_reg[3]_0\(0) => xpm_fifo_rst_inst_n_1,
      enb => rdp_inst_n_2,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\ => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(3 downto 0) => wr_pntr_ext(3 downto 0),
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(3) => wrpp1_inst_n_0,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(2) => wrpp1_inst_n_1,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(1) => wrpp1_inst_n_2,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(0) => wrpp1_inst_n_3,
      leaving_empty0 => leaving_empty0,
      ram_empty_i => ram_empty_i,
      ram_full_i0 => ram_full_i0,
      rd_en => rd_en,
      wr_clk => wr_clk
    );
rdpp1_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_149\
     port map (
      E(0) => rdp_inst_n_2,
      Q(3) => rdpp1_inst_n_0,
      Q(2) => rdpp1_inst_n_1,
      Q(1) => rdpp1_inst_n_2,
      Q(0) => rdpp1_inst_n_3,
      \count_value_i_reg[1]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
      \count_value_i_reg[1]_1\(0) => xpm_fifo_rst_inst_n_1,
      rd_en => rd_en,
      wr_clk => wr_clk
    );
rst_d1_inst: entity work.design_1_Vsp_core_0_0_xpm_fifo_reg_bit_150
     port map (
      Q(0) => xpm_fifo_rst_inst_n_1,
      rst_d1 => rst_d1,
      wr_clk => wr_clk
    );
wrp_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_151\
     port map (
      E(0) => ram_wr_en_pf,
      Q(3 downto 0) => wr_pntr_ext(3 downto 0),
      \count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_1,
      enb => rdp_inst_n_2,
      \gen_pntr_flags_cc.ram_empty_i_reg\(3) => rdpp1_inst_n_0,
      \gen_pntr_flags_cc.ram_empty_i_reg\(2) => rdpp1_inst_n_1,
      \gen_pntr_flags_cc.ram_empty_i_reg\(1) => rdpp1_inst_n_2,
      \gen_pntr_flags_cc.ram_empty_i_reg\(0) => rdpp1_inst_n_3,
      leaving_empty0 => leaving_empty0,
      ram_empty_i => ram_empty_i,
      ram_empty_i0 => ram_empty_i0,
      wr_clk => wr_clk
    );
wrpp1_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_152\
     port map (
      E(0) => ram_wr_en_pf,
      Q(3) => wrpp1_inst_n_0,
      Q(2) => wrpp1_inst_n_1,
      Q(1) => wrpp1_inst_n_2,
      Q(0) => wrpp1_inst_n_3,
      \count_value_i_reg[1]_0\(0) => xpm_fifo_rst_inst_n_1,
      wr_clk => wr_clk
    );
xpm_fifo_rst_inst: entity work.design_1_Vsp_core_0_0_xpm_fifo_rst_153
     port map (
      E(0) => ram_wr_en_pf,
      Q(0) => xpm_fifo_rst_inst_n_1,
      \count_value_i_reg[3]\ => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\,
      rst => rst,
      rst_d1 => rst_d1,
      wr_clk => wr_clk,
      wr_en => wr_en
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_base__4\ is
  port (
    sleep : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 11 downto 0 );
    full : out STD_LOGIC;
    full_n : out STD_LOGIC;
    prog_full : out STD_LOGIC;
    wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    overflow : out STD_LOGIC;
    wr_rst_busy : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    rd_clk : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
    empty : out STD_LOGIC;
    prog_empty : out STD_LOGIC;
    rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    underflow : out STD_LOGIC;
    rd_rst_busy : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    data_valid : out STD_LOGIC;
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC
  );
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 0;
  attribute CDC_DEST_SYNC_FF : integer;
  attribute CDC_DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 2;
  attribute COMMON_CLOCK : integer;
  attribute COMMON_CLOCK of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 1;
  attribute DOUT_RESET_VALUE : string;
  attribute DOUT_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "0";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 0;
  attribute ENABLE_ECC : integer;
  attribute ENABLE_ECC of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 0;
  attribute EN_ADV_FEATURE : string;
  attribute EN_ADV_FEATURE of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "16'b0000011100000111";
  attribute EN_AE : string;
  attribute EN_AE of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "1'b0";
  attribute EN_AF : string;
  attribute EN_AF of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "1'b0";
  attribute EN_DVLD : string;
  attribute EN_DVLD of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "1'b0";
  attribute EN_OF : string;
  attribute EN_OF of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "1'b1";
  attribute EN_PE : string;
  attribute EN_PE of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "1'b1";
  attribute EN_PF : string;
  attribute EN_PF of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "1'b1";
  attribute EN_RDC : string;
  attribute EN_RDC of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "1'b1";
  attribute EN_SIM_ASSERT_ERR : string;
  attribute EN_SIM_ASSERT_ERR of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "warning";
  attribute EN_UF : string;
  attribute EN_UF of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "1'b1";
  attribute EN_WACK : string;
  attribute EN_WACK of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "1'b0";
  attribute EN_WDC : string;
  attribute EN_WDC of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "1'b1";
  attribute FG_EQ_ASYM_DOUT : string;
  attribute FG_EQ_ASYM_DOUT of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "1'b0";
  attribute FIFO_MEMORY_TYPE : integer;
  attribute FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 1;
  attribute FIFO_MEM_TYPE : integer;
  attribute FIFO_MEM_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 1;
  attribute FIFO_READ_DEPTH : integer;
  attribute FIFO_READ_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 16;
  attribute FIFO_READ_LATENCY : integer;
  attribute FIFO_READ_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 1;
  attribute FIFO_SIZE : integer;
  attribute FIFO_SIZE of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 192;
  attribute FIFO_WRITE_DEPTH : integer;
  attribute FIFO_WRITE_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 16;
  attribute FULL_RESET_VALUE : integer;
  attribute FULL_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 0;
  attribute FULL_RST_VAL : string;
  attribute FULL_RST_VAL of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "xpm_fifo_base";
  attribute PE_THRESH_ADJ : integer;
  attribute PE_THRESH_ADJ of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 3;
  attribute PE_THRESH_MAX : integer;
  attribute PE_THRESH_MAX of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 11;
  attribute PE_THRESH_MIN : integer;
  attribute PE_THRESH_MIN of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 5;
  attribute PF_THRESH_ADJ : integer;
  attribute PF_THRESH_ADJ of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 9;
  attribute PF_THRESH_MAX : integer;
  attribute PF_THRESH_MAX of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 11;
  attribute PF_THRESH_MIN : integer;
  attribute PF_THRESH_MIN of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 5;
  attribute PROG_EMPTY_THRESH : integer;
  attribute PROG_EMPTY_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 5;
  attribute PROG_FULL_THRESH : integer;
  attribute PROG_FULL_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 11;
  attribute RD_DATA_COUNT_WIDTH : integer;
  attribute RD_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 5;
  attribute RD_DC_WIDTH_EXT : integer;
  attribute RD_DC_WIDTH_EXT of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 5;
  attribute RD_LATENCY : integer;
  attribute RD_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 2;
  attribute RD_MODE : integer;
  attribute RD_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 1;
  attribute RD_PNTR_WIDTH : integer;
  attribute RD_PNTR_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 4;
  attribute READ_DATA_WIDTH : integer;
  attribute READ_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 12;
  attribute READ_MODE : integer;
  attribute READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 1;
  attribute READ_MODE_LL : integer;
  attribute READ_MODE_LL of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 1;
  attribute RELATED_CLOCKS : integer;
  attribute RELATED_CLOCKS of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 0;
  attribute REMOVE_WR_RD_PROT_LOGIC : integer;
  attribute REMOVE_WR_RD_PROT_LOGIC of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 0;
  attribute USE_ADV_FEATURES : string;
  attribute USE_ADV_FEATURES of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "0707";
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 0;
  attribute WIDTH_RATIO : integer;
  attribute WIDTH_RATIO of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 1;
  attribute WRITE_DATA_WIDTH : integer;
  attribute WRITE_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 12;
  attribute WR_DATA_COUNT_WIDTH : integer;
  attribute WR_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 5;
  attribute WR_DC_WIDTH_EXT : integer;
  attribute WR_DC_WIDTH_EXT of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 5;
  attribute WR_DEPTH_LOG : integer;
  attribute WR_DEPTH_LOG of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 4;
  attribute WR_PNTR_WIDTH : integer;
  attribute WR_PNTR_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 4;
  attribute WR_RD_RATIO : integer;
  attribute WR_RD_RATIO of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 0;
  attribute WR_WIDTH_LOG : integer;
  attribute WR_WIDTH_LOG of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 4;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "TRUE";
  attribute both_stages_valid : integer;
  attribute both_stages_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 3;
  attribute invalid : integer;
  attribute invalid of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 0;
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is "soft";
  attribute stage1_valid : integer;
  attribute stage1_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 2;
  attribute stage2_valid : integer;
  attribute stage2_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ : entity is 1;
end \design_1_Vsp_core_0_0_xpm_fifo_base__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_base__4\ is
  signal \<const0>\ : STD_LOGIC;
  signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^empty\ : STD_LOGIC;
  signal empty_fwft_i0 : STD_LOGIC;
  signal \gen_fwft.ram_regout_en\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\ : STD_LOGIC;
  signal leaving_empty0 : STD_LOGIC;
  signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ram_empty_i : STD_LOGIC;
  signal ram_empty_i0 : STD_LOGIC;
  signal ram_full_i0 : STD_LOGIC;
  signal ram_wr_en_pf : STD_LOGIC;
  signal rd_pntr_ext : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rdp_inst_n_2 : STD_LOGIC;
  signal rdpp1_inst_n_0 : STD_LOGIC;
  signal rdpp1_inst_n_1 : STD_LOGIC;
  signal rdpp1_inst_n_2 : STD_LOGIC;
  signal rdpp1_inst_n_3 : STD_LOGIC;
  signal rst_d1 : STD_LOGIC;
  signal wr_pntr_ext : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wrpp1_inst_n_0 : STD_LOGIC;
  signal wrpp1_inst_n_1 : STD_LOGIC;
  signal wrpp1_inst_n_2 : STD_LOGIC;
  signal wrpp1_inst_n_3 : STD_LOGIC;
  signal xpm_fifo_rst_inst_n_1 : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair318";
  attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\ : label is "soft_lutpair318";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
  attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
  attribute SOFT_HLUTNM of \gen_fwft.empty_fwft_i_i_1\ : label is "soft_lutpair317";
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \gen_sdpram.xpm_memory_base_inst\ : label is "[7:0]";
  attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute KEEP_HIERARCHY of \gen_sdpram.xpm_memory_base_inst\ : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 192;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_ECC_MODE : string;
  attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 16;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
  attribute P_MEMORY_PRIMITIVE : string;
  attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \gen_sdpram.xpm_memory_base_inst\ : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
  attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute SOFT_HLUTNM of \gen_sdpram.xpm_memory_base_inst_i_3\ : label is "soft_lutpair317";
begin
  almost_empty <= \<const0>\;
  almost_full <= \<const0>\;
  data_valid <= \<const0>\;
  dbiterr <= \<const0>\;
  empty <= \^empty\;
  full <= \<const0>\;
  full_n <= \<const0>\;
  overflow <= \<const0>\;
  prog_empty <= \<const0>\;
  prog_full <= \<const0>\;
  rd_data_count(4) <= \<const0>\;
  rd_data_count(3) <= \<const0>\;
  rd_data_count(2) <= \<const0>\;
  rd_data_count(1) <= \<const0>\;
  rd_data_count(0) <= \<const0>\;
  rd_rst_busy <= \<const0>\;
  sbiterr <= \<const0>\;
  underflow <= \<const0>\;
  wr_ack <= \<const0>\;
  wr_data_count(4) <= \<const0>\;
  wr_data_count(3) <= \<const0>\;
  wr_data_count(2) <= \<const0>\;
  wr_data_count(1) <= \<const0>\;
  wr_data_count(0) <= \<const0>\;
  wr_rst_busy <= \<const0>\;
\FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A85"
    )
        port map (
      I0 => curr_fwft_state(0),
      I1 => rd_en,
      I2 => curr_fwft_state(1),
      I3 => ram_empty_i,
      O => \next_fwft_state__0\(0)
    );
\FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7C"
    )
        port map (
      I0 => rd_en,
      I1 => curr_fwft_state(1),
      I2 => curr_fwft_state(0),
      O => \next_fwft_state__0\(1)
    );
\FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \next_fwft_state__0\(0),
      Q => curr_fwft_state(0),
      R => xpm_fifo_rst_inst_n_1
    );
\FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \next_fwft_state__0\(1),
      Q => curr_fwft_state(1),
      R => xpm_fifo_rst_inst_n_1
    );
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F380"
    )
        port map (
      I0 => rd_en,
      I1 => curr_fwft_state(0),
      I2 => curr_fwft_state(1),
      I3 => \^empty\,
      O => empty_fwft_i0
    );
\gen_fwft.empty_fwft_i_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => empty_fwft_i0,
      Q => \^empty\,
      S => xpm_fifo_rst_inst_n_1
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => ram_full_i0,
      Q => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\,
      R => xpm_fifo_rst_inst_n_1
    );
\gen_pntr_flags_cc.ram_empty_i_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => ram_empty_i0,
      Q => ram_empty_i,
      S => xpm_fifo_rst_inst_n_1
    );
\gen_sdpram.xpm_memory_base_inst\: entity work.\design_1_Vsp_core_0_0_xpm_memory_base__4\
     port map (
      addra(3 downto 0) => wr_pntr_ext(3 downto 0),
      addrb(3 downto 0) => rd_pntr_ext(3 downto 0),
      clka => rd_clk,
      clkb => '0',
      dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\,
      dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\,
      dina(11 downto 0) => din(11 downto 0),
      dinb(11 downto 0) => B"000000000000",
      douta(11 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(11 downto 0),
      doutb(11 downto 0) => dout(11 downto 0),
      ena => ram_wr_en_pf,
      enb => rdp_inst_n_2,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => \gen_fwft.ram_regout_en\,
      rsta => '0',
      rstb => xpm_fifo_rst_inst_n_1,
      sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\,
      sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\,
      sleep => '0',
      wea(0) => '0',
      web(0) => '0'
    );
\gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"62"
    )
        port map (
      I0 => curr_fwft_state(0),
      I1 => curr_fwft_state(1),
      I2 => rd_en,
      O => \gen_fwft.ram_regout_en\
    );
rdp_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0\
     port map (
      E(0) => ram_wr_en_pf,
      Q(3 downto 0) => rd_pntr_ext(3 downto 0),
      \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
      \count_value_i_reg[3]_0\(0) => xpm_fifo_rst_inst_n_1,
      enb => rdp_inst_n_2,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\ => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(3 downto 0) => wr_pntr_ext(3 downto 0),
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(3) => wrpp1_inst_n_0,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(2) => wrpp1_inst_n_1,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(1) => wrpp1_inst_n_2,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(0) => wrpp1_inst_n_3,
      leaving_empty0 => leaving_empty0,
      ram_empty_i => ram_empty_i,
      ram_full_i0 => ram_full_i0,
      rd_clk => rd_clk,
      rd_en => rd_en
    );
rdpp1_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1\
     port map (
      E(0) => rdp_inst_n_2,
      Q(3) => rdpp1_inst_n_0,
      Q(2) => rdpp1_inst_n_1,
      Q(1) => rdpp1_inst_n_2,
      Q(0) => rdpp1_inst_n_3,
      \count_value_i_reg[1]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
      \count_value_i_reg[1]_1\(0) => xpm_fifo_rst_inst_n_1,
      rd_clk => rd_clk,
      rd_en => rd_en
    );
rst_d1_inst: entity work.design_1_Vsp_core_0_0_xpm_fifo_reg_bit_132
     port map (
      Q(0) => xpm_fifo_rst_inst_n_1,
      rd_clk => rd_clk,
      rst_d1 => rst_d1
    );
wrp_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_133\
     port map (
      E(0) => ram_wr_en_pf,
      Q(3 downto 0) => wr_pntr_ext(3 downto 0),
      \count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_1,
      enb => rdp_inst_n_2,
      \gen_pntr_flags_cc.ram_empty_i_reg\(3) => rdpp1_inst_n_0,
      \gen_pntr_flags_cc.ram_empty_i_reg\(2) => rdpp1_inst_n_1,
      \gen_pntr_flags_cc.ram_empty_i_reg\(1) => rdpp1_inst_n_2,
      \gen_pntr_flags_cc.ram_empty_i_reg\(0) => rdpp1_inst_n_3,
      leaving_empty0 => leaving_empty0,
      ram_empty_i => ram_empty_i,
      ram_empty_i0 => ram_empty_i0,
      rd_clk => rd_clk
    );
wrpp1_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_134\
     port map (
      E(0) => ram_wr_en_pf,
      Q(3) => wrpp1_inst_n_0,
      Q(2) => wrpp1_inst_n_1,
      Q(1) => wrpp1_inst_n_2,
      Q(0) => wrpp1_inst_n_3,
      \count_value_i_reg[1]_0\(0) => xpm_fifo_rst_inst_n_1,
      rd_clk => rd_clk
    );
xpm_fifo_rst_inst: entity work.design_1_Vsp_core_0_0_xpm_fifo_rst_135
     port map (
      E(0) => ram_wr_en_pf,
      Q(0) => xpm_fifo_rst_inst_n_1,
      \count_value_i_reg[3]\ => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\,
      rd_clk => rd_clk,
      rst => rst,
      rst_d1 => rst_d1,
      wr_en => wr_en
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_base__5\ is
  port (
    sleep : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 11 downto 0 );
    full : out STD_LOGIC;
    full_n : out STD_LOGIC;
    prog_full : out STD_LOGIC;
    wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    overflow : out STD_LOGIC;
    wr_rst_busy : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    rd_clk : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
    empty : out STD_LOGIC;
    prog_empty : out STD_LOGIC;
    rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    underflow : out STD_LOGIC;
    rd_rst_busy : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    data_valid : out STD_LOGIC;
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC
  );
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 0;
  attribute CDC_DEST_SYNC_FF : integer;
  attribute CDC_DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 2;
  attribute COMMON_CLOCK : integer;
  attribute COMMON_CLOCK of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 1;
  attribute DOUT_RESET_VALUE : string;
  attribute DOUT_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "0";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 0;
  attribute ENABLE_ECC : integer;
  attribute ENABLE_ECC of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 0;
  attribute EN_ADV_FEATURE : string;
  attribute EN_ADV_FEATURE of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "16'b0000011100000111";
  attribute EN_AE : string;
  attribute EN_AE of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "1'b0";
  attribute EN_AF : string;
  attribute EN_AF of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "1'b0";
  attribute EN_DVLD : string;
  attribute EN_DVLD of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "1'b0";
  attribute EN_OF : string;
  attribute EN_OF of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "1'b1";
  attribute EN_PE : string;
  attribute EN_PE of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "1'b1";
  attribute EN_PF : string;
  attribute EN_PF of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "1'b1";
  attribute EN_RDC : string;
  attribute EN_RDC of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "1'b1";
  attribute EN_SIM_ASSERT_ERR : string;
  attribute EN_SIM_ASSERT_ERR of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "warning";
  attribute EN_UF : string;
  attribute EN_UF of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "1'b1";
  attribute EN_WACK : string;
  attribute EN_WACK of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "1'b0";
  attribute EN_WDC : string;
  attribute EN_WDC of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "1'b1";
  attribute FG_EQ_ASYM_DOUT : string;
  attribute FG_EQ_ASYM_DOUT of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "1'b0";
  attribute FIFO_MEMORY_TYPE : integer;
  attribute FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 1;
  attribute FIFO_MEM_TYPE : integer;
  attribute FIFO_MEM_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 1;
  attribute FIFO_READ_DEPTH : integer;
  attribute FIFO_READ_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 16;
  attribute FIFO_READ_LATENCY : integer;
  attribute FIFO_READ_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 1;
  attribute FIFO_SIZE : integer;
  attribute FIFO_SIZE of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 192;
  attribute FIFO_WRITE_DEPTH : integer;
  attribute FIFO_WRITE_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 16;
  attribute FULL_RESET_VALUE : integer;
  attribute FULL_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 0;
  attribute FULL_RST_VAL : string;
  attribute FULL_RST_VAL of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "xpm_fifo_base";
  attribute PE_THRESH_ADJ : integer;
  attribute PE_THRESH_ADJ of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 3;
  attribute PE_THRESH_MAX : integer;
  attribute PE_THRESH_MAX of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 11;
  attribute PE_THRESH_MIN : integer;
  attribute PE_THRESH_MIN of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 5;
  attribute PF_THRESH_ADJ : integer;
  attribute PF_THRESH_ADJ of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 9;
  attribute PF_THRESH_MAX : integer;
  attribute PF_THRESH_MAX of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 11;
  attribute PF_THRESH_MIN : integer;
  attribute PF_THRESH_MIN of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 5;
  attribute PROG_EMPTY_THRESH : integer;
  attribute PROG_EMPTY_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 5;
  attribute PROG_FULL_THRESH : integer;
  attribute PROG_FULL_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 11;
  attribute RD_DATA_COUNT_WIDTH : integer;
  attribute RD_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 5;
  attribute RD_DC_WIDTH_EXT : integer;
  attribute RD_DC_WIDTH_EXT of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 5;
  attribute RD_LATENCY : integer;
  attribute RD_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 2;
  attribute RD_MODE : integer;
  attribute RD_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 1;
  attribute RD_PNTR_WIDTH : integer;
  attribute RD_PNTR_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 4;
  attribute READ_DATA_WIDTH : integer;
  attribute READ_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 12;
  attribute READ_MODE : integer;
  attribute READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 1;
  attribute READ_MODE_LL : integer;
  attribute READ_MODE_LL of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 1;
  attribute RELATED_CLOCKS : integer;
  attribute RELATED_CLOCKS of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 0;
  attribute REMOVE_WR_RD_PROT_LOGIC : integer;
  attribute REMOVE_WR_RD_PROT_LOGIC of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 0;
  attribute USE_ADV_FEATURES : string;
  attribute USE_ADV_FEATURES of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "0707";
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 0;
  attribute WIDTH_RATIO : integer;
  attribute WIDTH_RATIO of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 1;
  attribute WRITE_DATA_WIDTH : integer;
  attribute WRITE_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 12;
  attribute WR_DATA_COUNT_WIDTH : integer;
  attribute WR_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 5;
  attribute WR_DC_WIDTH_EXT : integer;
  attribute WR_DC_WIDTH_EXT of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 5;
  attribute WR_DEPTH_LOG : integer;
  attribute WR_DEPTH_LOG of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 4;
  attribute WR_PNTR_WIDTH : integer;
  attribute WR_PNTR_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 4;
  attribute WR_RD_RATIO : integer;
  attribute WR_RD_RATIO of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 0;
  attribute WR_WIDTH_LOG : integer;
  attribute WR_WIDTH_LOG of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 4;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "TRUE";
  attribute both_stages_valid : integer;
  attribute both_stages_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 3;
  attribute invalid : integer;
  attribute invalid of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 0;
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is "soft";
  attribute stage1_valid : integer;
  attribute stage1_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 2;
  attribute stage2_valid : integer;
  attribute stage2_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ : entity is 1;
end \design_1_Vsp_core_0_0_xpm_fifo_base__5\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_base__5\ is
  signal \<const0>\ : STD_LOGIC;
  signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^empty\ : STD_LOGIC;
  signal empty_fwft_i0 : STD_LOGIC;
  signal \gen_fwft.ram_regout_en\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\ : STD_LOGIC;
  signal leaving_empty0 : STD_LOGIC;
  signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ram_empty_i : STD_LOGIC;
  signal ram_empty_i0 : STD_LOGIC;
  signal ram_full_i0 : STD_LOGIC;
  signal ram_wr_en_pf : STD_LOGIC;
  signal rd_pntr_ext : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rdp_inst_n_2 : STD_LOGIC;
  signal rdpp1_inst_n_0 : STD_LOGIC;
  signal rdpp1_inst_n_1 : STD_LOGIC;
  signal rdpp1_inst_n_2 : STD_LOGIC;
  signal rdpp1_inst_n_3 : STD_LOGIC;
  signal rst_d1 : STD_LOGIC;
  signal wr_pntr_ext : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wrpp1_inst_n_0 : STD_LOGIC;
  signal wrpp1_inst_n_1 : STD_LOGIC;
  signal wrpp1_inst_n_2 : STD_LOGIC;
  signal wrpp1_inst_n_3 : STD_LOGIC;
  signal xpm_fifo_rst_inst_n_1 : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair303";
  attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\ : label is "soft_lutpair303";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
  attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
  attribute SOFT_HLUTNM of \gen_fwft.empty_fwft_i_i_1\ : label is "soft_lutpair302";
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \gen_sdpram.xpm_memory_base_inst\ : label is "[7:0]";
  attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute KEEP_HIERARCHY of \gen_sdpram.xpm_memory_base_inst\ : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 192;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_ECC_MODE : string;
  attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 16;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
  attribute P_MEMORY_PRIMITIVE : string;
  attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \gen_sdpram.xpm_memory_base_inst\ : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
  attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute SOFT_HLUTNM of \gen_sdpram.xpm_memory_base_inst_i_3\ : label is "soft_lutpair302";
begin
  almost_empty <= \<const0>\;
  almost_full <= \<const0>\;
  data_valid <= \<const0>\;
  dbiterr <= \<const0>\;
  empty <= \^empty\;
  full <= \<const0>\;
  full_n <= \<const0>\;
  overflow <= \<const0>\;
  prog_empty <= \<const0>\;
  prog_full <= \<const0>\;
  rd_data_count(4) <= \<const0>\;
  rd_data_count(3) <= \<const0>\;
  rd_data_count(2) <= \<const0>\;
  rd_data_count(1) <= \<const0>\;
  rd_data_count(0) <= \<const0>\;
  rd_rst_busy <= \<const0>\;
  sbiterr <= \<const0>\;
  underflow <= \<const0>\;
  wr_ack <= \<const0>\;
  wr_data_count(4) <= \<const0>\;
  wr_data_count(3) <= \<const0>\;
  wr_data_count(2) <= \<const0>\;
  wr_data_count(1) <= \<const0>\;
  wr_data_count(0) <= \<const0>\;
  wr_rst_busy <= \<const0>\;
\FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A85"
    )
        port map (
      I0 => curr_fwft_state(0),
      I1 => rd_en,
      I2 => curr_fwft_state(1),
      I3 => ram_empty_i,
      O => \next_fwft_state__0\(0)
    );
\FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7C"
    )
        port map (
      I0 => rd_en,
      I1 => curr_fwft_state(1),
      I2 => curr_fwft_state(0),
      O => \next_fwft_state__0\(1)
    );
\FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \next_fwft_state__0\(0),
      Q => curr_fwft_state(0),
      R => xpm_fifo_rst_inst_n_1
    );
\FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \next_fwft_state__0\(1),
      Q => curr_fwft_state(1),
      R => xpm_fifo_rst_inst_n_1
    );
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F380"
    )
        port map (
      I0 => rd_en,
      I1 => curr_fwft_state(0),
      I2 => curr_fwft_state(1),
      I3 => \^empty\,
      O => empty_fwft_i0
    );
\gen_fwft.empty_fwft_i_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => empty_fwft_i0,
      Q => \^empty\,
      S => xpm_fifo_rst_inst_n_1
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => ram_full_i0,
      Q => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\,
      R => xpm_fifo_rst_inst_n_1
    );
\gen_pntr_flags_cc.ram_empty_i_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => ram_empty_i0,
      Q => ram_empty_i,
      S => xpm_fifo_rst_inst_n_1
    );
\gen_sdpram.xpm_memory_base_inst\: entity work.\design_1_Vsp_core_0_0_xpm_memory_base__5\
     port map (
      addra(3 downto 0) => wr_pntr_ext(3 downto 0),
      addrb(3 downto 0) => rd_pntr_ext(3 downto 0),
      clka => rd_clk,
      clkb => '0',
      dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\,
      dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\,
      dina(11 downto 0) => din(11 downto 0),
      dinb(11 downto 0) => B"000000000000",
      douta(11 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(11 downto 0),
      doutb(11 downto 0) => dout(11 downto 0),
      ena => ram_wr_en_pf,
      enb => rdp_inst_n_2,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => \gen_fwft.ram_regout_en\,
      rsta => '0',
      rstb => xpm_fifo_rst_inst_n_1,
      sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\,
      sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\,
      sleep => '0',
      wea(0) => '0',
      web(0) => '0'
    );
\gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"62"
    )
        port map (
      I0 => curr_fwft_state(0),
      I1 => curr_fwft_state(1),
      I2 => rd_en,
      O => \gen_fwft.ram_regout_en\
    );
rdp_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_136\
     port map (
      E(0) => ram_wr_en_pf,
      Q(3 downto 0) => rd_pntr_ext(3 downto 0),
      \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
      \count_value_i_reg[3]_0\(0) => xpm_fifo_rst_inst_n_1,
      enb => rdp_inst_n_2,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\ => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(3 downto 0) => wr_pntr_ext(3 downto 0),
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(3) => wrpp1_inst_n_0,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(2) => wrpp1_inst_n_1,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(1) => wrpp1_inst_n_2,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(0) => wrpp1_inst_n_3,
      leaving_empty0 => leaving_empty0,
      ram_empty_i => ram_empty_i,
      ram_full_i0 => ram_full_i0,
      rd_clk => rd_clk,
      rd_en => rd_en
    );
rdpp1_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_137\
     port map (
      E(0) => rdp_inst_n_2,
      Q(3) => rdpp1_inst_n_0,
      Q(2) => rdpp1_inst_n_1,
      Q(1) => rdpp1_inst_n_2,
      Q(0) => rdpp1_inst_n_3,
      \count_value_i_reg[1]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
      \count_value_i_reg[1]_1\(0) => xpm_fifo_rst_inst_n_1,
      rd_clk => rd_clk,
      rd_en => rd_en
    );
rst_d1_inst: entity work.design_1_Vsp_core_0_0_xpm_fifo_reg_bit_138
     port map (
      Q(0) => xpm_fifo_rst_inst_n_1,
      rd_clk => rd_clk,
      rst_d1 => rst_d1
    );
wrp_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_139\
     port map (
      E(0) => ram_wr_en_pf,
      Q(3 downto 0) => wr_pntr_ext(3 downto 0),
      \count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_1,
      enb => rdp_inst_n_2,
      \gen_pntr_flags_cc.ram_empty_i_reg\(3) => rdpp1_inst_n_0,
      \gen_pntr_flags_cc.ram_empty_i_reg\(2) => rdpp1_inst_n_1,
      \gen_pntr_flags_cc.ram_empty_i_reg\(1) => rdpp1_inst_n_2,
      \gen_pntr_flags_cc.ram_empty_i_reg\(0) => rdpp1_inst_n_3,
      leaving_empty0 => leaving_empty0,
      ram_empty_i => ram_empty_i,
      ram_empty_i0 => ram_empty_i0,
      rd_clk => rd_clk
    );
wrpp1_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_140\
     port map (
      E(0) => ram_wr_en_pf,
      Q(3) => wrpp1_inst_n_0,
      Q(2) => wrpp1_inst_n_1,
      Q(1) => wrpp1_inst_n_2,
      Q(0) => wrpp1_inst_n_3,
      \count_value_i_reg[1]_0\(0) => xpm_fifo_rst_inst_n_1,
      rd_clk => rd_clk
    );
xpm_fifo_rst_inst: entity work.design_1_Vsp_core_0_0_xpm_fifo_rst_141
     port map (
      E(0) => ram_wr_en_pf,
      Q(0) => xpm_fifo_rst_inst_n_1,
      \count_value_i_reg[3]\ => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\,
      rd_clk => rd_clk,
      rst => rst,
      rst_d1 => rst_d1,
      wr_en => wr_en
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_base__6\ is
  port (
    sleep : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 11 downto 0 );
    full : out STD_LOGIC;
    full_n : out STD_LOGIC;
    prog_full : out STD_LOGIC;
    wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    overflow : out STD_LOGIC;
    wr_rst_busy : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    rd_clk : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
    empty : out STD_LOGIC;
    prog_empty : out STD_LOGIC;
    rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    underflow : out STD_LOGIC;
    rd_rst_busy : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    data_valid : out STD_LOGIC;
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC
  );
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 0;
  attribute CDC_DEST_SYNC_FF : integer;
  attribute CDC_DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 2;
  attribute COMMON_CLOCK : integer;
  attribute COMMON_CLOCK of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 1;
  attribute DOUT_RESET_VALUE : string;
  attribute DOUT_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "0";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 0;
  attribute ENABLE_ECC : integer;
  attribute ENABLE_ECC of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 0;
  attribute EN_ADV_FEATURE : string;
  attribute EN_ADV_FEATURE of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "16'b0000011100000111";
  attribute EN_AE : string;
  attribute EN_AE of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "1'b0";
  attribute EN_AF : string;
  attribute EN_AF of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "1'b0";
  attribute EN_DVLD : string;
  attribute EN_DVLD of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "1'b0";
  attribute EN_OF : string;
  attribute EN_OF of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "1'b1";
  attribute EN_PE : string;
  attribute EN_PE of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "1'b1";
  attribute EN_PF : string;
  attribute EN_PF of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "1'b1";
  attribute EN_RDC : string;
  attribute EN_RDC of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "1'b1";
  attribute EN_SIM_ASSERT_ERR : string;
  attribute EN_SIM_ASSERT_ERR of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "warning";
  attribute EN_UF : string;
  attribute EN_UF of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "1'b1";
  attribute EN_WACK : string;
  attribute EN_WACK of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "1'b0";
  attribute EN_WDC : string;
  attribute EN_WDC of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "1'b1";
  attribute FG_EQ_ASYM_DOUT : string;
  attribute FG_EQ_ASYM_DOUT of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "1'b0";
  attribute FIFO_MEMORY_TYPE : integer;
  attribute FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 1;
  attribute FIFO_MEM_TYPE : integer;
  attribute FIFO_MEM_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 1;
  attribute FIFO_READ_DEPTH : integer;
  attribute FIFO_READ_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 16;
  attribute FIFO_READ_LATENCY : integer;
  attribute FIFO_READ_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 1;
  attribute FIFO_SIZE : integer;
  attribute FIFO_SIZE of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 192;
  attribute FIFO_WRITE_DEPTH : integer;
  attribute FIFO_WRITE_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 16;
  attribute FULL_RESET_VALUE : integer;
  attribute FULL_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 0;
  attribute FULL_RST_VAL : string;
  attribute FULL_RST_VAL of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "xpm_fifo_base";
  attribute PE_THRESH_ADJ : integer;
  attribute PE_THRESH_ADJ of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 3;
  attribute PE_THRESH_MAX : integer;
  attribute PE_THRESH_MAX of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 11;
  attribute PE_THRESH_MIN : integer;
  attribute PE_THRESH_MIN of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 5;
  attribute PF_THRESH_ADJ : integer;
  attribute PF_THRESH_ADJ of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 9;
  attribute PF_THRESH_MAX : integer;
  attribute PF_THRESH_MAX of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 11;
  attribute PF_THRESH_MIN : integer;
  attribute PF_THRESH_MIN of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 5;
  attribute PROG_EMPTY_THRESH : integer;
  attribute PROG_EMPTY_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 5;
  attribute PROG_FULL_THRESH : integer;
  attribute PROG_FULL_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 11;
  attribute RD_DATA_COUNT_WIDTH : integer;
  attribute RD_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 5;
  attribute RD_DC_WIDTH_EXT : integer;
  attribute RD_DC_WIDTH_EXT of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 5;
  attribute RD_LATENCY : integer;
  attribute RD_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 2;
  attribute RD_MODE : integer;
  attribute RD_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 1;
  attribute RD_PNTR_WIDTH : integer;
  attribute RD_PNTR_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 4;
  attribute READ_DATA_WIDTH : integer;
  attribute READ_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 12;
  attribute READ_MODE : integer;
  attribute READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 1;
  attribute READ_MODE_LL : integer;
  attribute READ_MODE_LL of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 1;
  attribute RELATED_CLOCKS : integer;
  attribute RELATED_CLOCKS of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 0;
  attribute REMOVE_WR_RD_PROT_LOGIC : integer;
  attribute REMOVE_WR_RD_PROT_LOGIC of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 0;
  attribute USE_ADV_FEATURES : string;
  attribute USE_ADV_FEATURES of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "0707";
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 0;
  attribute WIDTH_RATIO : integer;
  attribute WIDTH_RATIO of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 1;
  attribute WRITE_DATA_WIDTH : integer;
  attribute WRITE_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 12;
  attribute WR_DATA_COUNT_WIDTH : integer;
  attribute WR_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 5;
  attribute WR_DC_WIDTH_EXT : integer;
  attribute WR_DC_WIDTH_EXT of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 5;
  attribute WR_DEPTH_LOG : integer;
  attribute WR_DEPTH_LOG of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 4;
  attribute WR_PNTR_WIDTH : integer;
  attribute WR_PNTR_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 4;
  attribute WR_RD_RATIO : integer;
  attribute WR_RD_RATIO of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 0;
  attribute WR_WIDTH_LOG : integer;
  attribute WR_WIDTH_LOG of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 4;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "TRUE";
  attribute both_stages_valid : integer;
  attribute both_stages_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 3;
  attribute invalid : integer;
  attribute invalid of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 0;
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is "soft";
  attribute stage1_valid : integer;
  attribute stage1_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 2;
  attribute stage2_valid : integer;
  attribute stage2_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ : entity is 1;
end \design_1_Vsp_core_0_0_xpm_fifo_base__6\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_base__6\ is
  signal \<const0>\ : STD_LOGIC;
  signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^empty\ : STD_LOGIC;
  signal empty_fwft_i0 : STD_LOGIC;
  signal \gen_fwft.ram_regout_en\ : STD_LOGIC;
  signal \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\ : STD_LOGIC;
  signal leaving_empty0 : STD_LOGIC;
  signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ram_empty_i : STD_LOGIC;
  signal ram_empty_i0 : STD_LOGIC;
  signal ram_full_i0 : STD_LOGIC;
  signal ram_wr_en_pf : STD_LOGIC;
  signal rd_pntr_ext : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rdp_inst_n_2 : STD_LOGIC;
  signal rdpp1_inst_n_0 : STD_LOGIC;
  signal rdpp1_inst_n_1 : STD_LOGIC;
  signal rdpp1_inst_n_2 : STD_LOGIC;
  signal rdpp1_inst_n_3 : STD_LOGIC;
  signal rst_d1 : STD_LOGIC;
  signal wr_pntr_ext : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wrpp1_inst_n_0 : STD_LOGIC;
  signal wrpp1_inst_n_1 : STD_LOGIC;
  signal wrpp1_inst_n_2 : STD_LOGIC;
  signal wrpp1_inst_n_3 : STD_LOGIC;
  signal xpm_fifo_rst_inst_n_1 : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair293";
  attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\ : label is "soft_lutpair293";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
  attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
  attribute SOFT_HLUTNM of \gen_fwft.empty_fwft_i_i_1\ : label is "soft_lutpair292";
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \gen_sdpram.xpm_memory_base_inst\ : label is "[7:0]";
  attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute KEEP_HIERARCHY of \gen_sdpram.xpm_memory_base_inst\ : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 192;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_ECC_MODE : string;
  attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 16;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
  attribute P_MEMORY_PRIMITIVE : string;
  attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \gen_sdpram.xpm_memory_base_inst\ : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
  attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 12;
  attribute SOFT_HLUTNM of \gen_sdpram.xpm_memory_base_inst_i_3\ : label is "soft_lutpair292";
begin
  almost_empty <= \<const0>\;
  almost_full <= \<const0>\;
  data_valid <= \<const0>\;
  dbiterr <= \<const0>\;
  empty <= \^empty\;
  full <= \<const0>\;
  full_n <= \<const0>\;
  overflow <= \<const0>\;
  prog_empty <= \<const0>\;
  prog_full <= \<const0>\;
  rd_data_count(4) <= \<const0>\;
  rd_data_count(3) <= \<const0>\;
  rd_data_count(2) <= \<const0>\;
  rd_data_count(1) <= \<const0>\;
  rd_data_count(0) <= \<const0>\;
  rd_rst_busy <= \<const0>\;
  sbiterr <= \<const0>\;
  underflow <= \<const0>\;
  wr_ack <= \<const0>\;
  wr_data_count(4) <= \<const0>\;
  wr_data_count(3) <= \<const0>\;
  wr_data_count(2) <= \<const0>\;
  wr_data_count(1) <= \<const0>\;
  wr_data_count(0) <= \<const0>\;
  wr_rst_busy <= \<const0>\;
\FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A85"
    )
        port map (
      I0 => curr_fwft_state(0),
      I1 => rd_en,
      I2 => curr_fwft_state(1),
      I3 => ram_empty_i,
      O => \next_fwft_state__0\(0)
    );
\FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7C"
    )
        port map (
      I0 => rd_en,
      I1 => curr_fwft_state(1),
      I2 => curr_fwft_state(0),
      O => \next_fwft_state__0\(1)
    );
\FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \next_fwft_state__0\(0),
      Q => curr_fwft_state(0),
      R => xpm_fifo_rst_inst_n_1
    );
\FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \next_fwft_state__0\(1),
      Q => curr_fwft_state(1),
      R => xpm_fifo_rst_inst_n_1
    );
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F380"
    )
        port map (
      I0 => rd_en,
      I1 => curr_fwft_state(0),
      I2 => curr_fwft_state(1),
      I3 => \^empty\,
      O => empty_fwft_i0
    );
\gen_fwft.empty_fwft_i_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => empty_fwft_i0,
      Q => \^empty\,
      S => xpm_fifo_rst_inst_n_1
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => ram_full_i0,
      Q => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\,
      R => xpm_fifo_rst_inst_n_1
    );
\gen_pntr_flags_cc.ram_empty_i_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => ram_empty_i0,
      Q => ram_empty_i,
      S => xpm_fifo_rst_inst_n_1
    );
\gen_sdpram.xpm_memory_base_inst\: entity work.\design_1_Vsp_core_0_0_xpm_memory_base__6\
     port map (
      addra(3 downto 0) => wr_pntr_ext(3 downto 0),
      addrb(3 downto 0) => rd_pntr_ext(3 downto 0),
      clka => rd_clk,
      clkb => '0',
      dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\,
      dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\,
      dina(11 downto 0) => din(11 downto 0),
      dinb(11 downto 0) => B"000000000000",
      douta(11 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(11 downto 0),
      doutb(11 downto 0) => dout(11 downto 0),
      ena => ram_wr_en_pf,
      enb => rdp_inst_n_2,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => \gen_fwft.ram_regout_en\,
      rsta => '0',
      rstb => xpm_fifo_rst_inst_n_1,
      sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\,
      sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\,
      sleep => '0',
      wea(0) => '0',
      web(0) => '0'
    );
\gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"62"
    )
        port map (
      I0 => curr_fwft_state(0),
      I1 => curr_fwft_state(1),
      I2 => rd_en,
      O => \gen_fwft.ram_regout_en\
    );
rdp_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_142\
     port map (
      E(0) => ram_wr_en_pf,
      Q(3 downto 0) => rd_pntr_ext(3 downto 0),
      \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
      \count_value_i_reg[3]_0\(0) => xpm_fifo_rst_inst_n_1,
      enb => rdp_inst_n_2,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\ => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_0\(3 downto 0) => wr_pntr_ext(3 downto 0),
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(3) => wrpp1_inst_n_0,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(2) => wrpp1_inst_n_1,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(1) => wrpp1_inst_n_2,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_1\(0) => wrpp1_inst_n_3,
      leaving_empty0 => leaving_empty0,
      ram_empty_i => ram_empty_i,
      ram_full_i0 => ram_full_i0,
      rd_clk => rd_clk,
      rd_en => rd_en
    );
rdpp1_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_143\
     port map (
      E(0) => rdp_inst_n_2,
      Q(3) => rdpp1_inst_n_0,
      Q(2) => rdpp1_inst_n_1,
      Q(1) => rdpp1_inst_n_2,
      Q(0) => rdpp1_inst_n_3,
      \count_value_i_reg[1]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
      \count_value_i_reg[1]_1\(0) => xpm_fifo_rst_inst_n_1,
      rd_clk => rd_clk,
      rd_en => rd_en
    );
rst_d1_inst: entity work.design_1_Vsp_core_0_0_xpm_fifo_reg_bit_144
     port map (
      Q(0) => xpm_fifo_rst_inst_n_1,
      rd_clk => rd_clk,
      rst_d1 => rst_d1
    );
wrp_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized0_145\
     port map (
      E(0) => ram_wr_en_pf,
      Q(3 downto 0) => wr_pntr_ext(3 downto 0),
      \count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_1,
      enb => rdp_inst_n_2,
      \gen_pntr_flags_cc.ram_empty_i_reg\(3) => rdpp1_inst_n_0,
      \gen_pntr_flags_cc.ram_empty_i_reg\(2) => rdpp1_inst_n_1,
      \gen_pntr_flags_cc.ram_empty_i_reg\(1) => rdpp1_inst_n_2,
      \gen_pntr_flags_cc.ram_empty_i_reg\(0) => rdpp1_inst_n_3,
      leaving_empty0 => leaving_empty0,
      ram_empty_i => ram_empty_i,
      ram_empty_i0 => ram_empty_i0,
      rd_clk => rd_clk
    );
wrpp1_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized1_146\
     port map (
      E(0) => ram_wr_en_pf,
      Q(3) => wrpp1_inst_n_0,
      Q(2) => wrpp1_inst_n_1,
      Q(1) => wrpp1_inst_n_2,
      Q(0) => wrpp1_inst_n_3,
      \count_value_i_reg[1]_0\(0) => xpm_fifo_rst_inst_n_1,
      rd_clk => rd_clk
    );
xpm_fifo_rst_inst: entity work.design_1_Vsp_core_0_0_xpm_fifo_rst_147
     port map (
      E(0) => ram_wr_en_pf,
      Q(0) => xpm_fifo_rst_inst_n_1,
      \count_value_i_reg[3]\ => \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg_n_0\,
      rd_clk => rd_clk,
      rst => rst,
      rst_d1 => rst_d1,
      wr_en => wr_en
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ is
  port (
    sleep : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 67 downto 0 );
    full : out STD_LOGIC;
    full_n : out STD_LOGIC;
    prog_full : out STD_LOGIC;
    wr_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
    overflow : out STD_LOGIC;
    wr_rst_busy : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    rd_clk : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 67 downto 0 );
    empty : out STD_LOGIC;
    prog_empty : out STD_LOGIC;
    rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
    underflow : out STD_LOGIC;
    rd_rst_busy : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    data_valid : out STD_LOGIC;
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC
  );
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 0;
  attribute CDC_DEST_SYNC_FF : integer;
  attribute CDC_DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 2;
  attribute COMMON_CLOCK : integer;
  attribute COMMON_CLOCK of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 1;
  attribute DOUT_RESET_VALUE : string;
  attribute DOUT_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "0";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 0;
  attribute ENABLE_ECC : integer;
  attribute ENABLE_ECC of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 0;
  attribute EN_ADV_FEATURE : string;
  attribute EN_ADV_FEATURE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "16'b0000111100001111";
  attribute EN_AE : string;
  attribute EN_AE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "1'b1";
  attribute EN_AF : string;
  attribute EN_AF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "1'b1";
  attribute EN_DVLD : string;
  attribute EN_DVLD of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "1'b0";
  attribute EN_OF : string;
  attribute EN_OF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "1'b1";
  attribute EN_PE : string;
  attribute EN_PE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "1'b1";
  attribute EN_PF : string;
  attribute EN_PF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "1'b1";
  attribute EN_RDC : string;
  attribute EN_RDC of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "1'b1";
  attribute EN_SIM_ASSERT_ERR : string;
  attribute EN_SIM_ASSERT_ERR of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "warning";
  attribute EN_UF : string;
  attribute EN_UF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "1'b1";
  attribute EN_WACK : string;
  attribute EN_WACK of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "1'b0";
  attribute EN_WDC : string;
  attribute EN_WDC of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "1'b1";
  attribute FG_EQ_ASYM_DOUT : string;
  attribute FG_EQ_ASYM_DOUT of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "1'b0";
  attribute FIFO_MEMORY_TYPE : integer;
  attribute FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 2;
  attribute FIFO_MEM_TYPE : integer;
  attribute FIFO_MEM_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 2;
  attribute FIFO_READ_DEPTH : integer;
  attribute FIFO_READ_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 2048;
  attribute FIFO_READ_LATENCY : integer;
  attribute FIFO_READ_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 1;
  attribute FIFO_SIZE : integer;
  attribute FIFO_SIZE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 139264;
  attribute FIFO_WRITE_DEPTH : integer;
  attribute FIFO_WRITE_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 2048;
  attribute FULL_RESET_VALUE : integer;
  attribute FULL_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 0;
  attribute FULL_RST_VAL : string;
  attribute FULL_RST_VAL of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "xpm_fifo_base";
  attribute PE_THRESH_ADJ : integer;
  attribute PE_THRESH_ADJ of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 8;
  attribute PE_THRESH_MAX : integer;
  attribute PE_THRESH_MAX of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 2043;
  attribute PE_THRESH_MIN : integer;
  attribute PE_THRESH_MIN of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 5;
  attribute PF_THRESH_ADJ : integer;
  attribute PF_THRESH_ADJ of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 2041;
  attribute PF_THRESH_MAX : integer;
  attribute PF_THRESH_MAX of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 2043;
  attribute PF_THRESH_MIN : integer;
  attribute PF_THRESH_MIN of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 5;
  attribute PROG_EMPTY_THRESH : integer;
  attribute PROG_EMPTY_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 10;
  attribute PROG_FULL_THRESH : integer;
  attribute PROG_FULL_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 2043;
  attribute RD_DATA_COUNT_WIDTH : integer;
  attribute RD_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 1;
  attribute RD_DC_WIDTH_EXT : integer;
  attribute RD_DC_WIDTH_EXT of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 12;
  attribute RD_LATENCY : integer;
  attribute RD_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 2;
  attribute RD_MODE : integer;
  attribute RD_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 1;
  attribute RD_PNTR_WIDTH : integer;
  attribute RD_PNTR_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 11;
  attribute READ_DATA_WIDTH : integer;
  attribute READ_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 68;
  attribute READ_MODE : integer;
  attribute READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 1;
  attribute READ_MODE_LL : integer;
  attribute READ_MODE_LL of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 1;
  attribute RELATED_CLOCKS : integer;
  attribute RELATED_CLOCKS of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 0;
  attribute REMOVE_WR_RD_PROT_LOGIC : integer;
  attribute REMOVE_WR_RD_PROT_LOGIC of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 0;
  attribute USE_ADV_FEATURES : string;
  attribute USE_ADV_FEATURES of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "0f0f";
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 0;
  attribute WIDTH_RATIO : integer;
  attribute WIDTH_RATIO of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 1;
  attribute WRITE_DATA_WIDTH : integer;
  attribute WRITE_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 68;
  attribute WR_DATA_COUNT_WIDTH : integer;
  attribute WR_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 1;
  attribute WR_DC_WIDTH_EXT : integer;
  attribute WR_DC_WIDTH_EXT of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 12;
  attribute WR_DEPTH_LOG : integer;
  attribute WR_DEPTH_LOG of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 11;
  attribute WR_PNTR_WIDTH : integer;
  attribute WR_PNTR_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 11;
  attribute WR_RD_RATIO : integer;
  attribute WR_RD_RATIO of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 0;
  attribute WR_WIDTH_LOG : integer;
  attribute WR_WIDTH_LOG of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 7;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "TRUE";
  attribute both_stages_valid : integer;
  attribute both_stages_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 3;
  attribute invalid : integer;
  attribute invalid of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 0;
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is "soft";
  attribute stage1_valid : integer;
  attribute stage1_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 2;
  attribute stage2_valid : integer;
  attribute stage2_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ : entity is 1;
end \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^almost_full\ : STD_LOGIC;
  signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^empty\ : STD_LOGIC;
  signal empty_fwft_i0 : STD_LOGIC;
  signal \^full\ : STD_LOGIC;
  signal \gen_fwft.ram_regout_en\ : STD_LOGIC;
  signal leaving_empty0 : STD_LOGIC;
  signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ram_empty_i : STD_LOGIC;
  signal ram_empty_i0 : STD_LOGIC;
  signal ram_full_i0 : STD_LOGIC;
  signal ram_wr_en_pf : STD_LOGIC;
  signal rd_pntr_ext : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal rdp_inst_n_0 : STD_LOGIC;
  signal rdpp1_inst_n_0 : STD_LOGIC;
  signal rdpp1_inst_n_1 : STD_LOGIC;
  signal rdpp1_inst_n_10 : STD_LOGIC;
  signal rdpp1_inst_n_11 : STD_LOGIC;
  signal rdpp1_inst_n_2 : STD_LOGIC;
  signal rdpp1_inst_n_3 : STD_LOGIC;
  signal rdpp1_inst_n_4 : STD_LOGIC;
  signal rdpp1_inst_n_5 : STD_LOGIC;
  signal rdpp1_inst_n_6 : STD_LOGIC;
  signal rdpp1_inst_n_7 : STD_LOGIC;
  signal rdpp1_inst_n_8 : STD_LOGIC;
  signal rdpp1_inst_n_9 : STD_LOGIC;
  signal rst_d1 : STD_LOGIC;
  signal rst_d1_inst_n_1 : STD_LOGIC;
  signal wr_pntr_ext : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal wrpp1_inst_n_0 : STD_LOGIC;
  signal wrpp1_inst_n_1 : STD_LOGIC;
  signal wrpp1_inst_n_10 : STD_LOGIC;
  signal wrpp1_inst_n_2 : STD_LOGIC;
  signal wrpp1_inst_n_3 : STD_LOGIC;
  signal wrpp1_inst_n_4 : STD_LOGIC;
  signal wrpp1_inst_n_5 : STD_LOGIC;
  signal wrpp1_inst_n_6 : STD_LOGIC;
  signal wrpp1_inst_n_7 : STD_LOGIC;
  signal wrpp1_inst_n_8 : STD_LOGIC;
  signal wrpp1_inst_n_9 : STD_LOGIC;
  signal wrpp2_inst_n_0 : STD_LOGIC;
  signal wrpp2_inst_n_1 : STD_LOGIC;
  signal wrpp2_inst_n_10 : STD_LOGIC;
  signal wrpp2_inst_n_2 : STD_LOGIC;
  signal wrpp2_inst_n_3 : STD_LOGIC;
  signal wrpp2_inst_n_4 : STD_LOGIC;
  signal wrpp2_inst_n_5 : STD_LOGIC;
  signal wrpp2_inst_n_6 : STD_LOGIC;
  signal wrpp2_inst_n_7 : STD_LOGIC;
  signal wrpp2_inst_n_8 : STD_LOGIC;
  signal wrpp2_inst_n_9 : STD_LOGIC;
  signal xpm_fifo_rst_inst_n_0 : STD_LOGIC;
  signal xpm_fifo_rst_inst_n_2 : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 67 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair336";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
  attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 11;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 11;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \gen_sdpram.xpm_memory_base_inst\ : label is "[7:0]";
  attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute KEEP_HIERARCHY of \gen_sdpram.xpm_memory_base_inst\ : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute \MEM.ADDRESS_SPACE\ : boolean;
  attribute \MEM.ADDRESS_SPACE\ of \gen_sdpram.xpm_memory_base_inst\ : label is std.standard.true;
  attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer;
  attribute \MEM.ADDRESS_SPACE_BEGIN\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer;
  attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer;
  attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 67;
  attribute \MEM.ADDRESS_SPACE_END\ : integer;
  attribute \MEM.ADDRESS_SPACE_END\ of \gen_sdpram.xpm_memory_base_inst\ : label is 2047;
  attribute \MEM.CORE_MEMORY_WIDTH\ : integer;
  attribute \MEM.CORE_MEMORY_WIDTH\ of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 139264;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_ECC_MODE : string;
  attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 2048;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
  attribute P_MEMORY_PRIMITIVE : string;
  attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "block";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 11;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 11;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 11;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 11;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \gen_sdpram.xpm_memory_base_inst\ : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
  attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 68;
  attribute SOFT_HLUTNM of \gen_sdpram.xpm_memory_base_inst_i_3\ : label is "soft_lutpair336";
begin
  almost_empty <= \<const0>\;
  almost_full <= \^almost_full\;
  data_valid <= \<const0>\;
  dbiterr <= \<const0>\;
  empty <= \^empty\;
  full <= \^full\;
  full_n <= \<const0>\;
  overflow <= \<const0>\;
  prog_empty <= \<const0>\;
  prog_full <= \<const0>\;
  rd_data_count(0) <= \<const0>\;
  rd_rst_busy <= \<const0>\;
  sbiterr <= \<const0>\;
  underflow <= \<const0>\;
  wr_ack <= \<const0>\;
  wr_data_count(0) <= \<const0>\;
  wr_rst_busy <= \<const0>\;
\FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A85"
    )
        port map (
      I0 => curr_fwft_state(0),
      I1 => rd_en,
      I2 => curr_fwft_state(1),
      I3 => ram_empty_i,
      O => \next_fwft_state__0\(0)
    );
\FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7C"
    )
        port map (
      I0 => rd_en,
      I1 => curr_fwft_state(1),
      I2 => curr_fwft_state(0),
      O => \next_fwft_state__0\(1)
    );
\FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \next_fwft_state__0\(0),
      Q => curr_fwft_state(0),
      R => xpm_fifo_rst_inst_n_2
    );
\FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \next_fwft_state__0\(1),
      Q => curr_fwft_state(1),
      R => xpm_fifo_rst_inst_n_2
    );
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F380"
    )
        port map (
      I0 => rd_en,
      I1 => curr_fwft_state(0),
      I2 => curr_fwft_state(1),
      I3 => \^empty\,
      O => empty_fwft_i0
    );
\gen_fwft.empty_fwft_i_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => empty_fwft_i0,
      Q => \^empty\,
      S => xpm_fifo_rst_inst_n_2
    );
\gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => rdp_inst_n_0,
      Q => \^almost_full\,
      R => '0'
    );
\gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => ram_full_i0,
      Q => \^full\,
      R => xpm_fifo_rst_inst_n_2
    );
\gen_pntr_flags_cc.ram_empty_i_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => ram_empty_i0,
      Q => ram_empty_i,
      S => xpm_fifo_rst_inst_n_2
    );
\gen_sdpram.xpm_memory_base_inst\: entity work.\design_1_Vsp_core_0_0_xpm_memory_base__parameterized0\
     port map (
      addra(10 downto 0) => wr_pntr_ext(10 downto 0),
      addrb(10 downto 0) => rd_pntr_ext(10 downto 0),
      clka => rd_clk,
      clkb => '0',
      dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\,
      dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\,
      dina(67 downto 0) => din(67 downto 0),
      dinb(67 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000",
      douta(67 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(67 downto 0),
      doutb(67 downto 0) => dout(67 downto 0),
      ena => '0',
      enb => rdpp1_inst_n_11,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => \gen_fwft.ram_regout_en\,
      rsta => '0',
      rstb => xpm_fifo_rst_inst_n_2,
      sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\,
      sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\,
      sleep => '0',
      wea(0) => ram_wr_en_pf,
      web(0) => '0'
    );
\gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"62"
    )
        port map (
      I0 => curr_fwft_state(0),
      I1 => curr_fwft_state(1),
      I2 => rd_en,
      O => \gen_fwft.ram_regout_en\
    );
rdp_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized5\
     port map (
      Q(10 downto 0) => rd_pntr_ext(10 downto 0),
      almost_full => \^almost_full\,
      \count_value_i_reg[0]_0\ => rdpp1_inst_n_11,
      \count_value_i_reg[10]_0\(0) => xpm_fifo_rst_inst_n_2,
      \count_value_i_reg[1]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
      \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(10) => wrpp2_inst_n_0,
      \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(9) => wrpp2_inst_n_1,
      \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(8) => wrpp2_inst_n_2,
      \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(7) => wrpp2_inst_n_3,
      \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(6) => wrpp2_inst_n_4,
      \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(5) => wrpp2_inst_n_5,
      \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(4) => wrpp2_inst_n_6,
      \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(3) => wrpp2_inst_n_7,
      \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(2) => wrpp2_inst_n_8,
      \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(1) => wrpp2_inst_n_9,
      \gen_pntr_flags_cc.gaf_cc.ram_afull_i_i_3_0\(0) => wrpp2_inst_n_10,
      \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg\ => rdp_inst_n_0,
      \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_0\ => xpm_fifo_rst_inst_n_0,
      \gen_pntr_flags_cc.gaf_cc.ram_afull_i_reg_1\ => rst_d1_inst_n_1,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(10) => wrpp1_inst_n_0,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(9) => wrpp1_inst_n_1,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(8) => wrpp1_inst_n_2,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(7) => wrpp1_inst_n_3,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(6) => wrpp1_inst_n_4,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(5) => wrpp1_inst_n_5,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(4) => wrpp1_inst_n_6,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(3) => wrpp1_inst_n_7,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(2) => wrpp1_inst_n_8,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(1) => wrpp1_inst_n_9,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_2_0\(0) => wrpp1_inst_n_10,
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_i_3_0\(10 downto 0) => wr_pntr_ext(10 downto 0),
      \gen_pntr_flags_cc.ngen_full_rst_val.ram_full_i_reg\ => \^full\,
      leaving_empty0 => leaving_empty0,
      ram_empty_i => ram_empty_i,
      ram_full_i0 => ram_full_i0,
      ram_wr_en_pf => ram_wr_en_pf,
      rd_clk => rd_clk,
      rd_en => rd_en,
      rst => rst
    );
rdpp1_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized6\
     port map (
      \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ => rdpp1_inst_n_11,
      Q(10) => rdpp1_inst_n_0,
      Q(9) => rdpp1_inst_n_1,
      Q(8) => rdpp1_inst_n_2,
      Q(7) => rdpp1_inst_n_3,
      Q(6) => rdpp1_inst_n_4,
      Q(5) => rdpp1_inst_n_5,
      Q(4) => rdpp1_inst_n_6,
      Q(3) => rdpp1_inst_n_7,
      Q(2) => rdpp1_inst_n_8,
      Q(1) => rdpp1_inst_n_9,
      Q(0) => rdpp1_inst_n_10,
      \count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
      \count_value_i_reg[1]_0\(0) => xpm_fifo_rst_inst_n_2,
      ram_empty_i => ram_empty_i,
      rd_clk => rd_clk,
      rd_en => rd_en
    );
rst_d1_inst: entity work.design_1_Vsp_core_0_0_xpm_fifo_reg_bit_129
     port map (
      Q(0) => xpm_fifo_rst_inst_n_2,
      d_out_int_reg_0 => rst_d1_inst_n_1,
      rd_clk => rd_clk,
      rst => rst,
      rst_d1 => rst_d1
    );
wrp_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized5_130\
     port map (
      Q(10 downto 0) => wr_pntr_ext(10 downto 0),
      \count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_2,
      \count_value_i_reg[5]_0\ => \^full\,
      \gen_pntr_flags_cc.ram_empty_i_reg\ => rdpp1_inst_n_11,
      \gen_pntr_flags_cc.ram_empty_i_reg_0\(10) => rdpp1_inst_n_0,
      \gen_pntr_flags_cc.ram_empty_i_reg_0\(9) => rdpp1_inst_n_1,
      \gen_pntr_flags_cc.ram_empty_i_reg_0\(8) => rdpp1_inst_n_2,
      \gen_pntr_flags_cc.ram_empty_i_reg_0\(7) => rdpp1_inst_n_3,
      \gen_pntr_flags_cc.ram_empty_i_reg_0\(6) => rdpp1_inst_n_4,
      \gen_pntr_flags_cc.ram_empty_i_reg_0\(5) => rdpp1_inst_n_5,
      \gen_pntr_flags_cc.ram_empty_i_reg_0\(4) => rdpp1_inst_n_6,
      \gen_pntr_flags_cc.ram_empty_i_reg_0\(3) => rdpp1_inst_n_7,
      \gen_pntr_flags_cc.ram_empty_i_reg_0\(2) => rdpp1_inst_n_8,
      \gen_pntr_flags_cc.ram_empty_i_reg_0\(1) => rdpp1_inst_n_9,
      \gen_pntr_flags_cc.ram_empty_i_reg_0\(0) => rdpp1_inst_n_10,
      leaving_empty0 => leaving_empty0,
      ram_empty_i => ram_empty_i,
      ram_empty_i0 => ram_empty_i0,
      ram_wr_en_pf => ram_wr_en_pf,
      rd_clk => rd_clk,
      rst_d1 => rst_d1,
      wr_en => wr_en
    );
wrpp1_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized6_131\
     port map (
      Q(10) => wrpp1_inst_n_0,
      Q(9) => wrpp1_inst_n_1,
      Q(8) => wrpp1_inst_n_2,
      Q(7) => wrpp1_inst_n_3,
      Q(6) => wrpp1_inst_n_4,
      Q(5) => wrpp1_inst_n_5,
      Q(4) => wrpp1_inst_n_6,
      Q(3) => wrpp1_inst_n_7,
      Q(2) => wrpp1_inst_n_8,
      Q(1) => wrpp1_inst_n_9,
      Q(0) => wrpp1_inst_n_10,
      \count_value_i_reg[1]_0\(0) => xpm_fifo_rst_inst_n_2,
      \count_value_i_reg[5]_0\ => \^full\,
      ram_wr_en_pf => ram_wr_en_pf,
      rd_clk => rd_clk,
      rst_d1 => rst_d1,
      wr_en => wr_en
    );
wrpp2_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized4\
     port map (
      Q(10) => wrpp2_inst_n_0,
      Q(9) => wrpp2_inst_n_1,
      Q(8) => wrpp2_inst_n_2,
      Q(7) => wrpp2_inst_n_3,
      Q(6) => wrpp2_inst_n_4,
      Q(5) => wrpp2_inst_n_5,
      Q(4) => wrpp2_inst_n_6,
      Q(3) => wrpp2_inst_n_7,
      Q(2) => wrpp2_inst_n_8,
      Q(1) => wrpp2_inst_n_9,
      Q(0) => wrpp2_inst_n_10,
      \count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_2,
      \count_value_i_reg[5]_0\ => \^full\,
      ram_wr_en_pf => ram_wr_en_pf,
      rd_clk => rd_clk,
      rst_d1 => rst_d1,
      wr_en => wr_en
    );
xpm_fifo_rst_inst: entity work.design_1_Vsp_core_0_0_xpm_fifo_rst
     port map (
      Q(1 downto 0) => curr_fwft_state(1 downto 0),
      \count_value_i_reg[10]\ => \^full\,
      \gen_pntr_flags_cc.ram_empty_i_reg\ => xpm_fifo_rst_inst_n_0,
      \gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\(0) => xpm_fifo_rst_inst_n_2,
      ram_empty_i => ram_empty_i,
      ram_wr_en_pf => ram_wr_en_pf,
      rd_clk => rd_clk,
      rd_en => rd_en,
      rst => rst,
      rst_d1 => rst_d1,
      wr_en => wr_en
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_rst__parameterized0\ is
  port (
    \gen_rst_ic.fifo_rd_rst_ic_reg_0\ : out STD_LOGIC;
    wrst_busy : out STD_LOGIC;
    overflow_i0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    wr_rst_busy : out STD_LOGIC;
    underflow_i0 : out STD_LOGIC;
    rd_clk : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    rst : in STD_LOGIC;
    \gof.overflow_i_reg\ : in STD_LOGIC;
    rst_d1 : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    \guf.underflow_i_reg\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_rst__parameterized0\ : entity is "xpm_fifo_rst";
end \design_1_Vsp_core_0_0_xpm_fifo_rst__parameterized0\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_rst__parameterized0\ is
  signal \/i__n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : signal is "yes";
  signal \gen_rst_ic.curr_rrst_state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP of \gen_rst_ic.curr_rrst_state\ : signal is "yes";
  signal \gen_rst_ic.fifo_rd_rst_i__0\ : STD_LOGIC;
  signal \^gen_rst_ic.fifo_rd_rst_ic_reg_0\ : STD_LOGIC;
  signal \gen_rst_ic.fifo_rd_rst_wr_i\ : STD_LOGIC;
  signal \gen_rst_ic.fifo_wr_rst_ic\ : STD_LOGIC;
  signal \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\ : STD_LOGIC;
  signal \gen_rst_ic.fifo_wr_rst_ic_i_2_n_0\ : STD_LOGIC;
  signal \gen_rst_ic.fifo_wr_rst_rd\ : STD_LOGIC;
  signal \gen_rst_ic.next_rrst_state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \gen_rst_ic.rst_seq_reentered_i_1_n_0\ : STD_LOGIC;
  signal \gen_rst_ic.rst_seq_reentered_i_2_n_0\ : STD_LOGIC;
  signal \gen_rst_ic.rst_seq_reentered_reg_n_0\ : STD_LOGIC;
  signal \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\ : STD_LOGIC;
  signal \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC;
  signal \^wrst_busy\ : STD_LOGIC;
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
  attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
  attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
  attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
  attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "RRST_IDLE:00,RRST_IN:01,RRST_OUT:10,RRST_EXIT:11";
  attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "RRST_IDLE:00,RRST_IN:01,RRST_OUT:10,RRST_EXIT:11";
  attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "yes";
  attribute DEF_VAL : string;
  attribute DEF_VAL of \gen_rst_ic.rrst_wr_inst\ : label is "1'b0";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 2;
  attribute INIT : string;
  attribute INIT of \gen_rst_ic.rrst_wr_inst\ : label is "0";
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 1;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \gen_rst_ic.rrst_wr_inst\ : label is 0;
  attribute VERSION : integer;
  attribute VERSION of \gen_rst_ic.rrst_wr_inst\ : label is 0;
  attribute XPM_CDC : string;
  attribute XPM_CDC of \gen_rst_ic.rrst_wr_inst\ : label is "SYNC_RST";
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \gen_rst_ic.rrst_wr_inst\ : label is "TRUE";
  attribute DEF_VAL of \gen_rst_ic.wrst_rd_inst\ : label is "1'b0";
  attribute DEST_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 2;
  attribute INIT of \gen_rst_ic.wrst_rd_inst\ : label is "0";
  attribute INIT_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 1;
  attribute SIM_ASSERT_CHK of \gen_rst_ic.wrst_rd_inst\ : label is 0;
  attribute VERSION of \gen_rst_ic.wrst_rd_inst\ : label is 0;
  attribute XPM_CDC of \gen_rst_ic.wrst_rd_inst\ : label is "SYNC_RST";
  attribute XPM_MODULE of \gen_rst_ic.wrst_rd_inst\ : label is "TRUE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gof.overflow_i_i_1\ : label is "soft_lutpair431";
  attribute SOFT_HLUTNM of wr_rst_busy_INST_0 : label is "soft_lutpair431";
begin
  \gen_rst_ic.fifo_rd_rst_ic_reg_0\ <= \^gen_rst_ic.fifo_rd_rst_ic_reg_0\;
  wrst_busy <= \^wrst_busy\;
\/i_\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010116"
    )
        port map (
      I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
      O => \/i__n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555555555555FFD5"
    )
        port map (
      I0 => \/i__n_0\,
      I1 => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I4 => p_0_in,
      I5 => rst,
      O => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F800F800FF00F800"
    )
        port map (
      I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_3_n_0\,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
      I3 => \/i__n_0\,
      I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      I5 => \gen_rst_ic.fifo_rd_rst_wr_i\,
      O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in,
      I1 => rst,
      O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_3_n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000100010000000"
    )
        port map (
      I0 => p_0_in,
      I1 => rst,
      I2 => \/i__n_0\,
      I3 => \gen_rst_ic.fifo_rd_rst_wr_i\,
      I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      I5 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      O => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => \/i__n_0\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      I2 => \gen_rst_ic.fifo_rd_rst_wr_i\,
      I3 => rst,
      I4 => p_0_in,
      O => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => \/i__n_0\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      I2 => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
      I3 => rst,
      I4 => p_0_in,
      O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\,
      Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      R => '0'
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\,
      Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      R => '0'
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\,
      Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      R => '0'
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\,
      Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      R => '0'
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\,
      Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
      R => '0'
    );
\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_rst_ic.curr_rrst_state\(0),
      I1 => \gen_rst_ic.curr_rrst_state\(1),
      O => \gen_rst_ic.next_rrst_state\(1)
    );
\FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_rst_ic.next_rrst_state\(0),
      Q => \gen_rst_ic.curr_rrst_state\(0),
      R => '0'
    );
\FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_rst_ic.next_rrst_state\(1),
      Q => \gen_rst_ic.curr_rrst_state\(1),
      R => '0'
    );
\__0/i_\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \gen_rst_ic.fifo_wr_rst_rd\,
      I1 => \gen_rst_ic.curr_rrst_state\(1),
      I2 => \gen_rst_ic.curr_rrst_state\(0),
      O => \gen_rst_ic.next_rrst_state\(0)
    );
\gen_rst_ic.fifo_rd_rst_i\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"3E"
    )
        port map (
      I0 => \gen_rst_ic.fifo_wr_rst_rd\,
      I1 => \gen_rst_ic.curr_rrst_state\(1),
      I2 => \gen_rst_ic.curr_rrst_state\(0),
      O => \gen_rst_ic.fifo_rd_rst_i__0\
    );
\gen_rst_ic.fifo_rd_rst_ic_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_rst_ic.fifo_rd_rst_i__0\,
      Q => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\,
      R => '0'
    );
\gen_rst_ic.fifo_wr_rst_ic_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF8FFFFFFF80000"
    )
        port map (
      I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
      I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      I4 => \gen_rst_ic.fifo_wr_rst_ic_i_2_n_0\,
      I5 => \gen_rst_ic.fifo_wr_rst_ic\,
      O => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\
    );
\gen_rst_ic.fifo_wr_rst_ic_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010116"
    )
        port map (
      I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      O => \gen_rst_ic.fifo_wr_rst_ic_i_2_n_0\
    );
\gen_rst_ic.fifo_wr_rst_ic_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\,
      Q => \gen_rst_ic.fifo_wr_rst_ic\,
      R => '0'
    );
\gen_rst_ic.rrst_wr_inst\: entity work.\design_1_Vsp_core_0_0_xpm_cdc_sync_rst__5\
     port map (
      dest_clk => wr_clk,
      dest_rst => \gen_rst_ic.fifo_rd_rst_wr_i\,
      src_rst => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\
    );
\gen_rst_ic.rst_seq_reentered_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAAE"
    )
        port map (
      I0 => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
      I2 => \gen_rst_ic.rst_seq_reentered_i_2_n_0\,
      I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      I5 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\,
      O => \gen_rst_ic.rst_seq_reentered_i_1_n_0\
    );
\gen_rst_ic.rst_seq_reentered_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      O => \gen_rst_ic.rst_seq_reentered_i_2_n_0\
    );
\gen_rst_ic.rst_seq_reentered_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \gen_rst_ic.rst_seq_reentered_i_1_n_0\,
      Q => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
      R => '0'
    );
\gen_rst_ic.wr_rst_busy_ic_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFFEF00"
    )
        port map (
      I0 => rst,
      I1 => p_0_in,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I3 => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\,
      I4 => \^wrst_busy\,
      O => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\
    );
\gen_rst_ic.wr_rst_busy_ic_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000116"
    )
        port map (
      I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
      O => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\
    );
\gen_rst_ic.wr_rst_busy_ic_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\,
      Q => \^wrst_busy\,
      R => '0'
    );
\gen_rst_ic.wrst_rd_inst\: entity work.\design_1_Vsp_core_0_0_xpm_cdc_sync_rst__4\
     port map (
      dest_clk => rd_clk,
      dest_rst => \gen_rst_ic.fifo_wr_rst_rd\,
      src_rst => \gen_rst_ic.fifo_wr_rst_ic\
    );
\gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => wr_en,
      I1 => \gof.overflow_i_reg\,
      I2 => \^wrst_busy\,
      I3 => rst_d1,
      O => E(0)
    );
\gof.overflow_i_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE00"
    )
        port map (
      I0 => \gof.overflow_i_reg\,
      I1 => \^wrst_busy\,
      I2 => rst_d1,
      I3 => wr_en,
      O => overflow_i0
    );
\guf.underflow_i_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\,
      I1 => rd_en,
      I2 => \guf.underflow_i_reg\,
      O => underflow_i0
    );
\power_on_rst_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => '0',
      Q => \power_on_rst_reg_n_0_[0]\,
      R => '0'
    );
\power_on_rst_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \power_on_rst_reg_n_0_[0]\,
      Q => p_0_in,
      R => '0'
    );
wr_rst_busy_INST_0: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^wrst_busy\,
      I1 => rst_d1,
      O => wr_rst_busy
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_rst__parameterized0__xdcDup__1\ is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    wrst_busy : out STD_LOGIC;
    overflow_i0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    wr_rst_busy : out STD_LOGIC;
    underflow_i0 : out STD_LOGIC;
    rd_clk : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    rst : in STD_LOGIC;
    \gof.overflow_i_reg\ : in STD_LOGIC;
    rst_d1 : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    \guf.underflow_i_reg\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_rst__parameterized0__xdcDup__1\ : entity is "xpm_fifo_rst";
end \design_1_Vsp_core_0_0_xpm_fifo_rst__parameterized0__xdcDup__1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_rst__parameterized0__xdcDup__1\ is
  signal \/i__n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : signal is "yes";
  signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \gen_rst_ic.curr_rrst_state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP of \gen_rst_ic.curr_rrst_state\ : signal is "yes";
  signal \gen_rst_ic.fifo_rd_rst_i__0\ : STD_LOGIC;
  signal \gen_rst_ic.fifo_rd_rst_wr_i\ : STD_LOGIC;
  signal \gen_rst_ic.fifo_wr_rst_ic\ : STD_LOGIC;
  signal \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\ : STD_LOGIC;
  signal \gen_rst_ic.fifo_wr_rst_ic_i_2_n_0\ : STD_LOGIC;
  signal \gen_rst_ic.fifo_wr_rst_rd\ : STD_LOGIC;
  signal \gen_rst_ic.next_rrst_state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \gen_rst_ic.rst_seq_reentered_i_1_n_0\ : STD_LOGIC;
  signal \gen_rst_ic.rst_seq_reentered_i_2_n_0\ : STD_LOGIC;
  signal \gen_rst_ic.rst_seq_reentered_reg_n_0\ : STD_LOGIC;
  signal \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\ : STD_LOGIC;
  signal \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC;
  signal \^wrst_busy\ : STD_LOGIC;
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
  attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
  attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
  attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
  attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "RRST_IDLE:00,RRST_IN:01,RRST_OUT:10,RRST_EXIT:11";
  attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "yes";
  attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "RRST_IDLE:00,RRST_IN:01,RRST_OUT:10,RRST_EXIT:11";
  attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "yes";
  attribute DEF_VAL : string;
  attribute DEF_VAL of \gen_rst_ic.rrst_wr_inst\ : label is "1'b0";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 2;
  attribute INIT : string;
  attribute INIT of \gen_rst_ic.rrst_wr_inst\ : label is "0";
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 1;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \gen_rst_ic.rrst_wr_inst\ : label is 0;
  attribute VERSION : integer;
  attribute VERSION of \gen_rst_ic.rrst_wr_inst\ : label is 0;
  attribute XPM_CDC : string;
  attribute XPM_CDC of \gen_rst_ic.rrst_wr_inst\ : label is "SYNC_RST";
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \gen_rst_ic.rrst_wr_inst\ : label is "TRUE";
  attribute DEF_VAL of \gen_rst_ic.wrst_rd_inst\ : label is "1'b0";
  attribute DEST_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 2;
  attribute INIT of \gen_rst_ic.wrst_rd_inst\ : label is "0";
  attribute INIT_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 1;
  attribute SIM_ASSERT_CHK of \gen_rst_ic.wrst_rd_inst\ : label is 0;
  attribute VERSION of \gen_rst_ic.wrst_rd_inst\ : label is 0;
  attribute XPM_CDC of \gen_rst_ic.wrst_rd_inst\ : label is "SYNC_RST";
  attribute XPM_MODULE of \gen_rst_ic.wrst_rd_inst\ : label is "TRUE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gof.overflow_i_i_1\ : label is "soft_lutpair248";
  attribute SOFT_HLUTNM of wr_rst_busy_INST_0 : label is "soft_lutpair248";
begin
  SR(0) <= \^sr\(0);
  wrst_busy <= \^wrst_busy\;
\/i_\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010116"
    )
        port map (
      I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
      O => \/i__n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555555555555FFD5"
    )
        port map (
      I0 => \/i__n_0\,
      I1 => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I4 => p_0_in,
      I5 => rst,
      O => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F800F800FF00F800"
    )
        port map (
      I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_3_n_0\,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
      I3 => \/i__n_0\,
      I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      I5 => \gen_rst_ic.fifo_rd_rst_wr_i\,
      O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in,
      I1 => rst,
      O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_3_n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000100010000000"
    )
        port map (
      I0 => p_0_in,
      I1 => rst,
      I2 => \/i__n_0\,
      I3 => \gen_rst_ic.fifo_rd_rst_wr_i\,
      I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      I5 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      O => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => \/i__n_0\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      I2 => \gen_rst_ic.fifo_rd_rst_wr_i\,
      I3 => rst,
      I4 => p_0_in,
      O => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => \/i__n_0\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      I2 => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
      I3 => rst,
      I4 => p_0_in,
      O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\,
      Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      R => '0'
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\,
      Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      R => '0'
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\,
      Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      R => '0'
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\,
      Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      R => '0'
    );
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\,
      Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
      R => '0'
    );
\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \gen_rst_ic.curr_rrst_state\(0),
      I1 => \gen_rst_ic.curr_rrst_state\(1),
      O => \gen_rst_ic.next_rrst_state\(1)
    );
\FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_rst_ic.next_rrst_state\(0),
      Q => \gen_rst_ic.curr_rrst_state\(0),
      R => '0'
    );
\FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_rst_ic.next_rrst_state\(1),
      Q => \gen_rst_ic.curr_rrst_state\(1),
      R => '0'
    );
\__0/i_\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \gen_rst_ic.fifo_wr_rst_rd\,
      I1 => \gen_rst_ic.curr_rrst_state\(1),
      I2 => \gen_rst_ic.curr_rrst_state\(0),
      O => \gen_rst_ic.next_rrst_state\(0)
    );
\gen_rst_ic.fifo_rd_rst_i\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"3E"
    )
        port map (
      I0 => \gen_rst_ic.fifo_wr_rst_rd\,
      I1 => \gen_rst_ic.curr_rrst_state\(1),
      I2 => \gen_rst_ic.curr_rrst_state\(0),
      O => \gen_rst_ic.fifo_rd_rst_i__0\
    );
\gen_rst_ic.fifo_rd_rst_ic_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_rst_ic.fifo_rd_rst_i__0\,
      Q => \^sr\(0),
      R => '0'
    );
\gen_rst_ic.fifo_wr_rst_ic_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF8FFFFFFF80000"
    )
        port map (
      I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
      I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      I4 => \gen_rst_ic.fifo_wr_rst_ic_i_2_n_0\,
      I5 => \gen_rst_ic.fifo_wr_rst_ic\,
      O => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\
    );
\gen_rst_ic.fifo_wr_rst_ic_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010116"
    )
        port map (
      I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      O => \gen_rst_ic.fifo_wr_rst_ic_i_2_n_0\
    );
\gen_rst_ic.fifo_wr_rst_ic_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\,
      Q => \gen_rst_ic.fifo_wr_rst_ic\,
      R => '0'
    );
\gen_rst_ic.rrst_wr_inst\: entity work.design_1_Vsp_core_0_0_xpm_cdc_sync_rst
     port map (
      dest_clk => wr_clk,
      dest_rst => \gen_rst_ic.fifo_rd_rst_wr_i\,
      src_rst => \^sr\(0)
    );
\gen_rst_ic.rst_seq_reentered_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAAE"
    )
        port map (
      I0 => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
      I2 => \gen_rst_ic.rst_seq_reentered_i_2_n_0\,
      I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      I5 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\,
      O => \gen_rst_ic.rst_seq_reentered_i_1_n_0\
    );
\gen_rst_ic.rst_seq_reentered_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      O => \gen_rst_ic.rst_seq_reentered_i_2_n_0\
    );
\gen_rst_ic.rst_seq_reentered_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \gen_rst_ic.rst_seq_reentered_i_1_n_0\,
      Q => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
      R => '0'
    );
\gen_rst_ic.wr_rst_busy_ic_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFFEF00"
    )
        port map (
      I0 => rst,
      I1 => p_0_in,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I3 => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\,
      I4 => \^wrst_busy\,
      O => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\
    );
\gen_rst_ic.wr_rst_busy_ic_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000116"
    )
        port map (
      I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
      I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
      I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
      I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
      I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
      O => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\
    );
\gen_rst_ic.wr_rst_busy_ic_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\,
      Q => \^wrst_busy\,
      R => '0'
    );
\gen_rst_ic.wrst_rd_inst\: entity work.\design_1_Vsp_core_0_0_xpm_cdc_sync_rst__6\
     port map (
      dest_clk => rd_clk,
      dest_rst => \gen_rst_ic.fifo_wr_rst_rd\,
      src_rst => \gen_rst_ic.fifo_wr_rst_ic\
    );
\gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => wr_en,
      I1 => \gof.overflow_i_reg\,
      I2 => \^wrst_busy\,
      I3 => rst_d1,
      O => E(0)
    );
\gof.overflow_i_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE00"
    )
        port map (
      I0 => \gof.overflow_i_reg\,
      I1 => \^wrst_busy\,
      I2 => rst_d1,
      I3 => wr_en,
      O => overflow_i0
    );
\guf.underflow_i_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => \^sr\(0),
      I1 => rd_en,
      I2 => \guf.underflow_i_reg\,
      O => underflow_i0
    );
\power_on_rst_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => '0',
      Q => \power_on_rst_reg_n_0_[0]\,
      R => '0'
    );
\power_on_rst_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => \power_on_rst_reg_n_0_[0]\,
      Q => p_0_in,
      R => '0'
    );
wr_rst_busy_INST_0: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^wrst_busy\,
      I1 => rst_d1,
      O => wr_rst_busy
    );
end STRUCTURE;
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`protect begin_protected
`protect version = 1
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`protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_axi_crossbar is
  port (
    m_axi_araddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 );
    aresetn : in STD_LOGIC;
    aclk : in STD_LOGIC;
    s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
    m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_axi_crossbar : entity is "axi_crossbar_v2_1_34_axi_crossbar";
end design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_axi_crossbar;

architecture STRUCTURE of design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_axi_crossbar is
begin
\gen_sasd.crossbar_sasd_0\: entity work.design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_crossbar_sasd
     port map (
      aclk => aclk,
      aresetn => aresetn,
      m_axi_araddr(5 downto 0) => m_axi_araddr(5 downto 0),
      m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
      m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
      m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
      m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
      m_axi_bready(1 downto 0) => m_axi_bready(1 downto 0),
      m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0),
      m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
      m_axi_rready(1 downto 0) => m_axi_rready(1 downto 0),
      m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0),
      m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
      m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
      s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
      s_axi_arready(0) => s_axi_arready(0),
      s_axi_arvalid(0) => s_axi_arvalid(0),
      s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
      s_axi_awready(0) => s_axi_awready(0),
      s_axi_awvalid(0) => s_axi_awvalid(0),
      s_axi_bready(0) => s_axi_bready(0),
      s_axi_bvalid(0) => s_axi_bvalid(0),
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      s_axi_rready(0) => s_axi_rready(0),
      s_axi_rvalid(0) => s_axi_rvalid(0),
      s_axi_wready(0) => s_axi_wready(0),
      s_axi_wvalid(0) => s_axi_wvalid(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_vfb_0_0_axis_converter is
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    s_axis_tvalid : in STD_LOGIC;
    s_axis_tready : out STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_tlast : in STD_LOGIC;
    s_axis_tid : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axis_tdest : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axis_tuser : in STD_LOGIC_VECTOR ( 151 downto 0 );
    m_axis_tvalid : out STD_LOGIC;
    m_axis_tready : in STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axis_tlast : out STD_LOGIC;
    m_axis_tid : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axis_tdest : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axis_tuser : out STD_LOGIC_VECTOR ( 75 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_Vsp_core_0_0_bd_7289_vfb_0_0_axis_converter : entity is "bd_7289_vfb_0_0_axis_converter,axis_dwidth_converter_v1_1_32_axis_dwidth_converter,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_vfb_0_0_axis_converter : entity is "bd_7289_vfb_0_0_axis_converter";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_bd_7289_vfb_0_0_axis_converter : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of design_1_Vsp_core_0_0_bd_7289_vfb_0_0_axis_converter : entity is "axis_dwidth_converter_v1_1_32_axis_dwidth_converter,Vivado 2024.2";
end design_1_Vsp_core_0_0_bd_7289_vfb_0_0_axis_converter;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_vfb_0_0_axis_converter is
  signal \<const0>\ : STD_LOGIC;
  signal \^m_axis_tdata\ : STD_LOGIC_VECTOR ( 27 downto 0 );
  signal \^m_axis_tid\ : STD_LOGIC_VECTOR ( 9 downto 4 );
  signal \^m_axis_tuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute x_interface_info : string;
  attribute x_interface_info of aclk : signal is "xilinx.com:signal:clock:1.0 CLKIF CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of aclk : signal is "slave";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of aclk : signal is "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXIS:M_AXIS, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
  attribute x_interface_info of aresetn : signal is "xilinx.com:signal:reset:1.0 RSTIF RST";
  attribute x_interface_mode of aresetn : signal is "slave";
  attribute x_interface_parameter of aresetn : signal is "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute x_interface_info of m_axis_tlast : signal is "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
  attribute x_interface_info of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
  attribute x_interface_info of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
  attribute x_interface_mode of m_axis_tvalid : signal is "master";
  attribute x_interface_parameter of m_axis_tvalid : signal is "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
  attribute x_interface_info of s_axis_tlast : signal is "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
  attribute x_interface_info of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
  attribute x_interface_info of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
  attribute x_interface_mode of s_axis_tvalid : signal is "slave";
  attribute x_interface_parameter of s_axis_tvalid : signal is "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
  attribute x_interface_info of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
  attribute x_interface_info of m_axis_tdest : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDEST";
  attribute x_interface_info of m_axis_tid : signal is "xilinx.com:interface:axis:1.0 M_AXIS TID";
  attribute x_interface_info of m_axis_tkeep : signal is "xilinx.com:interface:axis:1.0 M_AXIS TKEEP";
  attribute x_interface_info of m_axis_tuser : signal is "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
  attribute x_interface_info of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
  attribute x_interface_info of s_axis_tdest : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDEST";
  attribute x_interface_info of s_axis_tid : signal is "xilinx.com:interface:axis:1.0 S_AXIS TID";
  attribute x_interface_info of s_axis_tkeep : signal is "xilinx.com:interface:axis:1.0 S_AXIS TKEEP";
  attribute x_interface_info of s_axis_tuser : signal is "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
begin
  m_axis_tdata(31) <= \<const0>\;
  m_axis_tdata(30) <= \<const0>\;
  m_axis_tdata(29) <= \<const0>\;
  m_axis_tdata(28) <= \<const0>\;
  m_axis_tdata(27 downto 16) <= \^m_axis_tdata\(27 downto 16);
  m_axis_tdata(15) <= \<const0>\;
  m_axis_tdata(14) <= \<const0>\;
  m_axis_tdata(13) <= \<const0>\;
  m_axis_tdata(12) <= \<const0>\;
  m_axis_tdata(11 downto 0) <= \^m_axis_tdata\(11 downto 0);
  m_axis_tdest(31) <= \<const0>\;
  m_axis_tdest(30) <= \<const0>\;
  m_axis_tdest(29) <= \<const0>\;
  m_axis_tdest(28) <= \<const0>\;
  m_axis_tdest(27) <= \<const0>\;
  m_axis_tdest(26) <= \<const0>\;
  m_axis_tdest(25) <= \<const0>\;
  m_axis_tdest(24) <= \<const0>\;
  m_axis_tdest(23) <= \<const0>\;
  m_axis_tdest(22) <= \<const0>\;
  m_axis_tdest(21) <= \<const0>\;
  m_axis_tdest(20) <= \<const0>\;
  m_axis_tdest(19) <= \<const0>\;
  m_axis_tdest(18) <= \<const0>\;
  m_axis_tdest(17) <= \<const0>\;
  m_axis_tdest(16) <= \<const0>\;
  m_axis_tdest(15) <= \<const0>\;
  m_axis_tdest(14) <= \<const0>\;
  m_axis_tdest(13) <= \<const0>\;
  m_axis_tdest(12) <= \<const0>\;
  m_axis_tdest(11) <= \<const0>\;
  m_axis_tdest(10) <= \<const0>\;
  m_axis_tdest(9) <= \<const0>\;
  m_axis_tdest(8) <= \<const0>\;
  m_axis_tdest(7) <= \<const0>\;
  m_axis_tdest(6) <= \<const0>\;
  m_axis_tdest(5) <= \<const0>\;
  m_axis_tdest(4) <= \<const0>\;
  m_axis_tdest(3) <= \<const0>\;
  m_axis_tdest(2) <= \<const0>\;
  m_axis_tdest(1) <= \<const0>\;
  m_axis_tdest(0) <= \<const0>\;
  m_axis_tid(31) <= \<const0>\;
  m_axis_tid(30) <= \<const0>\;
  m_axis_tid(29) <= \<const0>\;
  m_axis_tid(28) <= \<const0>\;
  m_axis_tid(27) <= \<const0>\;
  m_axis_tid(26) <= \<const0>\;
  m_axis_tid(25) <= \<const0>\;
  m_axis_tid(24) <= \<const0>\;
  m_axis_tid(23) <= \<const0>\;
  m_axis_tid(22) <= \<const0>\;
  m_axis_tid(21) <= \<const0>\;
  m_axis_tid(20) <= \<const0>\;
  m_axis_tid(19) <= \<const0>\;
  m_axis_tid(18) <= \<const0>\;
  m_axis_tid(17) <= \<const0>\;
  m_axis_tid(16) <= \<const0>\;
  m_axis_tid(15) <= \<const0>\;
  m_axis_tid(14) <= \<const0>\;
  m_axis_tid(13) <= \<const0>\;
  m_axis_tid(12) <= \<const0>\;
  m_axis_tid(11) <= \<const0>\;
  m_axis_tid(10) <= \<const0>\;
  m_axis_tid(9 downto 4) <= \^m_axis_tid\(9 downto 4);
  m_axis_tid(3) <= \<const0>\;
  m_axis_tid(2) <= \<const0>\;
  m_axis_tid(1) <= \<const0>\;
  m_axis_tid(0) <= \<const0>\;
  m_axis_tkeep(3) <= \<const0>\;
  m_axis_tkeep(2) <= \<const0>\;
  m_axis_tkeep(1) <= \<const0>\;
  m_axis_tkeep(0) <= \<const0>\;
  m_axis_tuser(75) <= \<const0>\;
  m_axis_tuser(74) <= \<const0>\;
  m_axis_tuser(73) <= \<const0>\;
  m_axis_tuser(72) <= \<const0>\;
  m_axis_tuser(71) <= \<const0>\;
  m_axis_tuser(70) <= \<const0>\;
  m_axis_tuser(69) <= \<const0>\;
  m_axis_tuser(68) <= \<const0>\;
  m_axis_tuser(67) <= \<const0>\;
  m_axis_tuser(66) <= \<const0>\;
  m_axis_tuser(65) <= \<const0>\;
  m_axis_tuser(64) <= \<const0>\;
  m_axis_tuser(63) <= \<const0>\;
  m_axis_tuser(62) <= \<const0>\;
  m_axis_tuser(61) <= \<const0>\;
  m_axis_tuser(60) <= \<const0>\;
  m_axis_tuser(59) <= \<const0>\;
  m_axis_tuser(58) <= \<const0>\;
  m_axis_tuser(57) <= \<const0>\;
  m_axis_tuser(56) <= \<const0>\;
  m_axis_tuser(55) <= \<const0>\;
  m_axis_tuser(54) <= \<const0>\;
  m_axis_tuser(53) <= \<const0>\;
  m_axis_tuser(52) <= \<const0>\;
  m_axis_tuser(51) <= \<const0>\;
  m_axis_tuser(50) <= \<const0>\;
  m_axis_tuser(49) <= \<const0>\;
  m_axis_tuser(48) <= \<const0>\;
  m_axis_tuser(47) <= \<const0>\;
  m_axis_tuser(46) <= \<const0>\;
  m_axis_tuser(45) <= \<const0>\;
  m_axis_tuser(44) <= \<const0>\;
  m_axis_tuser(43) <= \<const0>\;
  m_axis_tuser(42) <= \<const0>\;
  m_axis_tuser(41) <= \<const0>\;
  m_axis_tuser(40) <= \<const0>\;
  m_axis_tuser(39) <= \<const0>\;
  m_axis_tuser(38) <= \<const0>\;
  m_axis_tuser(37) <= \<const0>\;
  m_axis_tuser(36) <= \<const0>\;
  m_axis_tuser(35) <= \<const0>\;
  m_axis_tuser(34) <= \<const0>\;
  m_axis_tuser(33) <= \<const0>\;
  m_axis_tuser(32) <= \<const0>\;
  m_axis_tuser(31) <= \<const0>\;
  m_axis_tuser(30) <= \<const0>\;
  m_axis_tuser(29) <= \<const0>\;
  m_axis_tuser(28) <= \<const0>\;
  m_axis_tuser(27) <= \<const0>\;
  m_axis_tuser(26) <= \<const0>\;
  m_axis_tuser(25) <= \<const0>\;
  m_axis_tuser(24) <= \<const0>\;
  m_axis_tuser(23) <= \<const0>\;
  m_axis_tuser(22) <= \<const0>\;
  m_axis_tuser(21) <= \<const0>\;
  m_axis_tuser(20) <= \<const0>\;
  m_axis_tuser(19) <= \<const0>\;
  m_axis_tuser(18) <= \<const0>\;
  m_axis_tuser(17) <= \<const0>\;
  m_axis_tuser(16) <= \<const0>\;
  m_axis_tuser(15) <= \<const0>\;
  m_axis_tuser(14) <= \<const0>\;
  m_axis_tuser(13) <= \<const0>\;
  m_axis_tuser(12) <= \<const0>\;
  m_axis_tuser(11) <= \<const0>\;
  m_axis_tuser(10) <= \<const0>\;
  m_axis_tuser(9) <= \<const0>\;
  m_axis_tuser(8) <= \<const0>\;
  m_axis_tuser(7) <= \<const0>\;
  m_axis_tuser(6) <= \<const0>\;
  m_axis_tuser(5) <= \<const0>\;
  m_axis_tuser(4) <= \<const0>\;
  m_axis_tuser(3) <= \<const0>\;
  m_axis_tuser(2) <= \<const0>\;
  m_axis_tuser(1) <= \<const0>\;
  m_axis_tuser(0) <= \^m_axis_tuser\(0);
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
inst: entity work.design_1_Vsp_core_0_0_axis_dwidth_converter_v1_1_32_axis_dwidth_converter
     port map (
      aclk => aclk,
      aresetn => aresetn,
      m_axis_tdata(23 downto 12) => \^m_axis_tdata\(27 downto 16),
      m_axis_tdata(11 downto 0) => \^m_axis_tdata\(11 downto 0),
      m_axis_tid(5 downto 0) => \^m_axis_tid\(9 downto 4),
      m_axis_tlast => m_axis_tlast,
      m_axis_tuser(0) => \^m_axis_tuser\(0),
      s_axis_tdata(47 downto 36) => s_axis_tdata(59 downto 48),
      s_axis_tdata(35 downto 24) => s_axis_tdata(43 downto 32),
      s_axis_tdata(23 downto 12) => s_axis_tdata(27 downto 16),
      s_axis_tdata(11 downto 0) => s_axis_tdata(11 downto 0),
      s_axis_tid(5 downto 0) => s_axis_tid(9 downto 4),
      s_axis_tkeep(0) => s_axis_tkeep(7),
      s_axis_tlast => s_axis_tlast,
      s_axis_tuser(0) => s_axis_tuser(19),
      s_axis_tvalid => s_axis_tvalid,
      \state_reg[0]\ => s_axis_tready,
      \state_reg[1]\ => m_axis_tvalid
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_clk_rst_top is
  port (
    \out\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \bs_rst_int_r_reg[8]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    pll0_clkout0_out : out STD_LOGIC;
    bsctrl_rst : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    rst_seq_done3 : out STD_LOGIC;
    n1_en_vtc_in : out STD_LOGIC;
    pll0_clkoutphy_out : out STD_LOGIC;
    rst : in STD_LOGIC;
    bs_rst_dphy_in : in STD_LOGIC;
    in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    riu_clk : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg\ : in STD_LOGIC;
    n1_vtc_rdy_out : in STD_LOGIC;
    n0_vtc_rdy_out : in STD_LOGIC;
    \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_clk_rst_top : entity is "high_speed_selectio_wiz_v3_6_10_clk_rst_top";
end design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_clk_rst_top;

architecture STRUCTURE of design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_clk_rst_top is
  signal clk_scheme_inst_n_1 : STD_LOGIC;
  signal \^pll0_clkout0_out\ : STD_LOGIC;
  signal pll0_clkoutphy_en : STD_LOGIC;
  signal pll1_rst : STD_LOGIC;
begin
  pll0_clkout0_out <= \^pll0_clkout0_out\;
clk_scheme_inst: entity work.design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_clk_scheme
     port map (
      pll0_clkout0_out => \^pll0_clkout0_out\,
      pll0_clkoutphy_en_in => pll0_clkoutphy_en,
      pll0_clkoutphy_out => pll0_clkoutphy_out,
      pll0_locked_out => clk_scheme_inst_n_1,
      pll0_rst_in => pll1_rst,
      riu_clk => riu_clk
    );
rst_scheme_inst: entity work.design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_rst_scheme
     port map (
      CLK => \^pll0_clkout0_out\,
      \GEN_RIU_NOT_FROM_PLL.bs_dly_rst_reg_0\ => bsctrl_rst,
      \GEN_RIU_NOT_FROM_PLL.rst_seq_done_reg_0\ => rst_seq_done3,
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\ => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg\,
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_1\ => \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\,
      Q(0) => Q(0),
      bs_rst_dphy_in => bs_rst_dphy_in,
      \bs_rst_int_r_reg[8]_0\(4 downto 0) => \bs_rst_int_r_reg[8]\(4 downto 0),
      in0(0) => in0(0),
      n0_vtc_rdy_out => n0_vtc_rdy_out,
      n1_en_vtc_in => n1_en_vtc_in,
      n1_vtc_rdy_out => n1_vtc_rdy_out,
      \out\(4 downto 0) => \out\(4 downto 0),
      pll0_clkoutphy_en_in => pll0_clkoutphy_en,
      pll0_locked_out => clk_scheme_inst_n_1,
      pll0_rst_in => pll1_rst,
      riu_clk => riu_clk,
      rst => rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_proc_sys_reset is
  port (
    slowest_sync_clk : in STD_LOGIC;
    ext_reset_in : in STD_LOGIC;
    aux_reset_in : in STD_LOGIC;
    mb_debug_sys_rst : in STD_LOGIC;
    dcm_locked : in STD_LOGIC;
    mb_reset : out STD_LOGIC;
    bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
    peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
    interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
    peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute C_AUX_RESET_HIGH : string;
  attribute C_AUX_RESET_HIGH of design_1_Vsp_core_0_0_proc_sys_reset : entity is "1'b0";
  attribute C_AUX_RST_WIDTH : integer;
  attribute C_AUX_RST_WIDTH of design_1_Vsp_core_0_0_proc_sys_reset : entity is 4;
  attribute C_EXT_RESET_HIGH : string;
  attribute C_EXT_RESET_HIGH of design_1_Vsp_core_0_0_proc_sys_reset : entity is "1'b0";
  attribute C_EXT_RST_WIDTH : integer;
  attribute C_EXT_RST_WIDTH of design_1_Vsp_core_0_0_proc_sys_reset : entity is 4;
  attribute C_FAMILY : string;
  attribute C_FAMILY of design_1_Vsp_core_0_0_proc_sys_reset : entity is "zynquplus";
  attribute C_NUM_BUS_RST : integer;
  attribute C_NUM_BUS_RST of design_1_Vsp_core_0_0_proc_sys_reset : entity is 1;
  attribute C_NUM_INTERCONNECT_ARESETN : integer;
  attribute C_NUM_INTERCONNECT_ARESETN of design_1_Vsp_core_0_0_proc_sys_reset : entity is 1;
  attribute C_NUM_PERP_ARESETN : integer;
  attribute C_NUM_PERP_ARESETN of design_1_Vsp_core_0_0_proc_sys_reset : entity is 1;
  attribute C_NUM_PERP_RST : integer;
  attribute C_NUM_PERP_RST of design_1_Vsp_core_0_0_proc_sys_reset : entity is 1;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_proc_sys_reset : entity is "proc_sys_reset";
end design_1_Vsp_core_0_0_proc_sys_reset;

architecture STRUCTURE of design_1_Vsp_core_0_0_proc_sys_reset is
  signal \<const0>\ : STD_LOGIC;
  signal Pr_out : STD_LOGIC;
  signal lpf_int : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE";
begin
  bus_struct_reset(0) <= \<const0>\;
  interconnect_aresetn(0) <= \<const0>\;
  mb_reset <= \<const0>\;
  peripheral_aresetn(0) <= \<const0>\;
EXT_LPF: entity work.design_1_Vsp_core_0_0_lpf
     port map (
      ext_reset_in => ext_reset_in,
      lpf_int => lpf_int,
      slowest_sync_clk => slowest_sync_clk
    );
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => slowest_sync_clk,
      CE => '1',
      D => Pr_out,
      Q => peripheral_reset(0),
      R => '0'
    );
SEQ: entity work.design_1_Vsp_core_0_0_sequence_psr
     port map (
      Pr_out => Pr_out,
      lpf_int => lpf_int,
      slowest_sync_clk => slowest_sync_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ is
  port (
    sleep : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 25 downto 0 );
    full : out STD_LOGIC;
    full_n : out STD_LOGIC;
    prog_full : out STD_LOGIC;
    wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    overflow : out STD_LOGIC;
    wr_rst_busy : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    rd_clk : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 25 downto 0 );
    empty : out STD_LOGIC;
    prog_empty : out STD_LOGIC;
    rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    underflow : out STD_LOGIC;
    rd_rst_busy : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    data_valid : out STD_LOGIC;
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC
  );
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute CDC_DEST_SYNC_FF : integer;
  attribute CDC_DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 2;
  attribute COMMON_CLOCK : integer;
  attribute COMMON_CLOCK of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute DOUT_RESET_VALUE : string;
  attribute DOUT_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "0";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute ENABLE_ECC : integer;
  attribute ENABLE_ECC of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute EN_ADV_FEATURE : string;
  attribute EN_ADV_FEATURE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "16'b0000011100000111";
  attribute EN_AE : string;
  attribute EN_AE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "1'b0";
  attribute EN_AF : string;
  attribute EN_AF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "1'b0";
  attribute EN_DVLD : string;
  attribute EN_DVLD of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "1'b0";
  attribute EN_OF : string;
  attribute EN_OF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "1'b1";
  attribute EN_PE : string;
  attribute EN_PE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "1'b1";
  attribute EN_PF : string;
  attribute EN_PF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "1'b1";
  attribute EN_RDC : string;
  attribute EN_RDC of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "1'b1";
  attribute EN_SIM_ASSERT_ERR : string;
  attribute EN_SIM_ASSERT_ERR of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "warning";
  attribute EN_UF : string;
  attribute EN_UF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "1'b1";
  attribute EN_WACK : string;
  attribute EN_WACK of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "1'b0";
  attribute EN_WDC : string;
  attribute EN_WDC of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "1'b1";
  attribute FG_EQ_ASYM_DOUT : string;
  attribute FG_EQ_ASYM_DOUT of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "1'b0";
  attribute FIFO_MEMORY_TYPE : integer;
  attribute FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 1;
  attribute FIFO_MEM_TYPE : integer;
  attribute FIFO_MEM_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 1;
  attribute FIFO_READ_DEPTH : integer;
  attribute FIFO_READ_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 32;
  attribute FIFO_READ_LATENCY : integer;
  attribute FIFO_READ_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 1;
  attribute FIFO_SIZE : integer;
  attribute FIFO_SIZE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 832;
  attribute FIFO_WRITE_DEPTH : integer;
  attribute FIFO_WRITE_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 32;
  attribute FULL_RESET_VALUE : integer;
  attribute FULL_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute FULL_RST_VAL : string;
  attribute FULL_RST_VAL of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "xpm_fifo_base";
  attribute PE_THRESH_ADJ : integer;
  attribute PE_THRESH_ADJ of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 10;
  attribute PE_THRESH_MAX : integer;
  attribute PE_THRESH_MAX of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 29;
  attribute PE_THRESH_MIN : integer;
  attribute PE_THRESH_MIN of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 3;
  attribute PF_THRESH_ADJ : integer;
  attribute PF_THRESH_ADJ of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 29;
  attribute PF_THRESH_MAX : integer;
  attribute PF_THRESH_MAX of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 29;
  attribute PF_THRESH_MIN : integer;
  attribute PF_THRESH_MIN of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 5;
  attribute PROG_EMPTY_THRESH : integer;
  attribute PROG_EMPTY_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 10;
  attribute PROG_FULL_THRESH : integer;
  attribute PROG_FULL_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 29;
  attribute RD_DATA_COUNT_WIDTH : integer;
  attribute RD_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 5;
  attribute RD_DC_WIDTH_EXT : integer;
  attribute RD_DC_WIDTH_EXT of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 6;
  attribute RD_LATENCY : integer;
  attribute RD_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 1;
  attribute RD_MODE : integer;
  attribute RD_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute RD_PNTR_WIDTH : integer;
  attribute RD_PNTR_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 5;
  attribute READ_DATA_WIDTH : integer;
  attribute READ_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 26;
  attribute READ_MODE : integer;
  attribute READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute READ_MODE_LL : integer;
  attribute READ_MODE_LL of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute RELATED_CLOCKS : integer;
  attribute RELATED_CLOCKS of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute REMOVE_WR_RD_PROT_LOGIC : integer;
  attribute REMOVE_WR_RD_PROT_LOGIC of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute USE_ADV_FEATURES : string;
  attribute USE_ADV_FEATURES of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "0707";
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute WIDTH_RATIO : integer;
  attribute WIDTH_RATIO of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 1;
  attribute WRITE_DATA_WIDTH : integer;
  attribute WRITE_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 26;
  attribute WR_DATA_COUNT_WIDTH : integer;
  attribute WR_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 5;
  attribute WR_DC_WIDTH_EXT : integer;
  attribute WR_DC_WIDTH_EXT of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 6;
  attribute WR_DEPTH_LOG : integer;
  attribute WR_DEPTH_LOG of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 5;
  attribute WR_PNTR_WIDTH : integer;
  attribute WR_PNTR_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 5;
  attribute WR_RD_RATIO : integer;
  attribute WR_RD_RATIO of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute WR_WIDTH_LOG : integer;
  attribute WR_WIDTH_LOG of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 5;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "TRUE";
  attribute both_stages_valid : integer;
  attribute both_stages_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 3;
  attribute invalid : integer;
  attribute invalid of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 0;
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is "soft";
  attribute stage1_valid : integer;
  attribute stage1_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 2;
  attribute stage2_valid : integer;
  attribute stage2_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ : entity is 1;
end \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\ is
  signal \<const0>\ : STD_LOGIC;
  signal diff_pntr_pe : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal diff_pntr_pf_q : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal diff_pntr_pf_q0 : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \^empty\ : STD_LOGIC;
  signal empty_i0 : STD_LOGIC;
  signal \^full\ : STD_LOGIC;
  signal \gen_cdc_pntr.rpw_gray_reg_dc_n_0\ : STD_LOGIC;
  signal \gen_cdc_pntr.rpw_gray_reg_dc_n_1\ : STD_LOGIC;
  signal \gen_cdc_pntr.rpw_gray_reg_dc_n_2\ : STD_LOGIC;
  signal \gen_cdc_pntr.rpw_gray_reg_dc_n_3\ : STD_LOGIC;
  signal \gen_cdc_pntr.rpw_gray_reg_dc_n_4\ : STD_LOGIC;
  signal \gen_cdc_pntr.rpw_gray_reg_dc_n_5\ : STD_LOGIC;
  signal \gen_cdc_pntr.wpr_gray_reg_n_4\ : STD_LOGIC;
  signal \gen_cdc_pntr.wpr_gray_reg_n_5\ : STD_LOGIC;
  signal \gen_cdc_pntr.wpr_gray_reg_n_6\ : STD_LOGIC;
  signal \gen_cdc_pntr.wpr_gray_reg_n_7\ : STD_LOGIC;
  signal \gen_cdc_pntr.wpr_gray_reg_n_8\ : STD_LOGIC;
  signal \gen_cdc_pntr.wpr_gray_reg_n_9\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\ : STD_LOGIC;
  signal \grdc.diff_wr_rd_pntr_rdc0_out\ : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal \gwdc.diff_wr_rd_pntr1_out\ : STD_LOGIC_VECTOR ( 5 downto 1 );
  signal overflow_i0 : STD_LOGIC;
  signal \^prog_empty\ : STD_LOGIC;
  signal \^prog_full\ : STD_LOGIC;
  signal ram_full_i0 : STD_LOGIC;
  signal ram_rd_en_i : STD_LOGIC;
  signal rd_pntr_ext : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rd_pntr_wr : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal rd_pntr_wr_cdc : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal rd_pntr_wr_cdc_dc : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^rd_rst_busy\ : STD_LOGIC;
  signal rdp_inst_n_10 : STD_LOGIC;
  signal rdp_inst_n_8 : STD_LOGIC;
  signal rdp_inst_n_9 : STD_LOGIC;
  signal rst_d1 : STD_LOGIC;
  signal rst_d1_inst_n_1 : STD_LOGIC;
  signal underflow_i0 : STD_LOGIC;
  signal wr_pntr_ext : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal wr_pntr_plus1_pf : STD_LOGIC_VECTOR ( 5 downto 4 );
  signal wr_pntr_plus1_pf_carry : STD_LOGIC;
  signal wr_pntr_rd_cdc : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal wr_pntr_rd_cdc_dc : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal wrpp1_inst_n_0 : STD_LOGIC;
  signal wrpp2_inst_n_0 : STD_LOGIC;
  signal wrpp2_inst_n_1 : STD_LOGIC;
  signal wrpp2_inst_n_2 : STD_LOGIC;
  signal wrst_busy : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 25 downto 0 );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 1;
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
  attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
  attribute SIM_LOSSLESS_GRAY_CHK : integer;
  attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
  attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 6;
  attribute XPM_CDC : string;
  attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "GRAY";
  attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "TRUE";
  attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 2;
  attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 1;
  attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
  attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
  attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
  attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
  attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 5;
  attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "GRAY";
  attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "TRUE";
  attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 2;
  attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 1;
  attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
  attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
  attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
  attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
  attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 6;
  attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "GRAY";
  attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "TRUE";
  attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 2;
  attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 1;
  attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
  attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
  attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
  attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
  attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 5;
  attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "GRAY";
  attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "TRUE";
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 26;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 26;
  attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \gen_sdpram.xpm_memory_base_inst\ : label is "[7:0]";
  attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute KEEP_HIERARCHY of \gen_sdpram.xpm_memory_base_inst\ : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 832;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_ECC_MODE : string;
  attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
  attribute P_MEMORY_PRIMITIVE : string;
  attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 26;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 26;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 26;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 26;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 26;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 26;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 26;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \gen_sdpram.xpm_memory_base_inst\ : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 26;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 26;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
  attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 26;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 26;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 28;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 28;
begin
  almost_empty <= \<const0>\;
  almost_full <= \<const0>\;
  data_valid <= \<const0>\;
  dbiterr <= \<const0>\;
  empty <= \^empty\;
  full <= \^full\;
  full_n <= \<const0>\;
  prog_empty <= \^prog_empty\;
  prog_full <= \^prog_full\;
  rd_rst_busy <= \^rd_rst_busy\;
  sbiterr <= \<const0>\;
  wr_ack <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_cdc_pntr.rd_pntr_cdc_dc_inst\: entity work.\design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0\
     port map (
      dest_clk => wr_clk,
      dest_out_bin(5 downto 0) => rd_pntr_wr_cdc_dc(5 downto 0),
      src_clk => rd_clk,
      src_in_bin(5 downto 0) => rd_pntr_ext(5 downto 0)
    );
\gen_cdc_pntr.rd_pntr_cdc_inst\: entity work.design_1_Vsp_core_0_0_xpm_cdc_gray
     port map (
      dest_clk => wr_clk,
      dest_out_bin(4 downto 0) => rd_pntr_wr_cdc(4 downto 0),
      src_clk => rd_clk,
      src_in_bin(4 downto 0) => rd_pntr_ext(4 downto 0)
    );
\gen_cdc_pntr.rpw_gray_reg\: entity work.design_1_Vsp_core_0_0_xpm_fifo_reg_vec_154
     port map (
      D(4 downto 0) => rd_pntr_wr_cdc(4 downto 0),
      E(0) => wr_pntr_plus1_pf_carry,
      Q(4 downto 0) => rd_pntr_wr(4 downto 0),
      \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\ => wrpp1_inst_n_0,
      \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_0\ => wrpp2_inst_n_0,
      \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_1\(1) => wrpp2_inst_n_1,
      \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_1\(0) => wrpp2_inst_n_2,
      \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_2\(1 downto 0) => wr_pntr_plus1_pf(5 downto 4),
      ram_full_i0 => ram_full_i0,
      wr_clk => wr_clk,
      wrst_busy => wrst_busy
    );
\gen_cdc_pntr.rpw_gray_reg_dc\: entity work.\design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_155\
     port map (
      D(5 downto 0) => rd_pntr_wr_cdc_dc(5 downto 0),
      Q(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\,
      Q(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\,
      Q(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\,
      Q(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\,
      Q(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\,
      Q(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\,
      wr_clk => wr_clk,
      wrst_busy => wrst_busy
    );
\gen_cdc_pntr.wpr_gray_reg\: entity work.design_1_Vsp_core_0_0_xpm_fifo_reg_vec_156
     port map (
      D(3 downto 1) => diff_pntr_pe(4 downto 2),
      D(0) => diff_pntr_pe(0),
      Q(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\,
      Q(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\,
      Q(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\,
      Q(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\,
      Q(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\,
      SR(0) => \^rd_rst_busy\,
      \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\ => \^empty\,
      \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\ => rdp_inst_n_10,
      \gen_pf_ic_rc.ram_empty_i_reg\(4 downto 0) => rd_pntr_ext(4 downto 0),
      rd_clk => rd_clk,
      rd_en => rd_en,
      \reg_out_i_reg[3]_0\ => \gen_cdc_pntr.wpr_gray_reg_n_9\,
      \reg_out_i_reg[4]_0\(4 downto 0) => wr_pntr_rd_cdc(4 downto 0)
    );
\gen_cdc_pntr.wpr_gray_reg_dc\: entity work.\design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_157\
     port map (
      D(4 downto 0) => \grdc.diff_wr_rd_pntr_rdc0_out\(5 downto 1),
      Q(5 downto 0) => rd_pntr_ext(5 downto 0),
      SR(0) => \^rd_rst_busy\,
      rd_clk => rd_clk,
      \reg_out_i_reg[5]_0\(5 downto 0) => wr_pntr_rd_cdc_dc(5 downto 0)
    );
\gen_cdc_pntr.wr_pntr_cdc_dc_inst\: entity work.\design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__6\
     port map (
      dest_clk => rd_clk,
      dest_out_bin(5 downto 0) => wr_pntr_rd_cdc_dc(5 downto 0),
      src_clk => wr_clk,
      src_in_bin(5 downto 0) => wr_pntr_ext(5 downto 0)
    );
\gen_cdc_pntr.wr_pntr_cdc_inst\: entity work.\design_1_Vsp_core_0_0_xpm_cdc_gray__6\
     port map (
      dest_clk => rd_clk,
      dest_out_bin(4 downto 0) => wr_pntr_rd_cdc(4 downto 0),
      src_clk => wr_clk,
      src_in_bin(4 downto 0) => wr_pntr_ext(4 downto 0)
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => diff_pntr_pe(0),
      Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\,
      R => \^rd_rst_busy\
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => diff_pntr_pe(1),
      Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\,
      R => \^rd_rst_busy\
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => diff_pntr_pe(2),
      Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\,
      R => \^rd_rst_busy\
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => diff_pntr_pe(3),
      Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\,
      R => \^rd_rst_busy\
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => diff_pntr_pe(4),
      Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\,
      R => \^rd_rst_busy\
    );
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^prog_empty\,
      I1 => \^empty\,
      I2 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\,
      O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\
    );
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000557F"
    )
        port map (
      I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\,
      I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\,
      I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\,
      I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\,
      I4 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\,
      O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\
    );
\gen_pf_ic_rc.gpe_ic.prog_empty_i_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\,
      Q => \^prog_empty\,
      S => \^rd_rst_busy\
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => diff_pntr_pf_q0(1),
      Q => diff_pntr_pf_q(1),
      R => wrst_busy
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => diff_pntr_pf_q0(2),
      Q => diff_pntr_pf_q(2),
      R => wrst_busy
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => diff_pntr_pf_q0(3),
      Q => diff_pntr_pf_q(3),
      R => wrst_busy
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => diff_pntr_pf_q0(4),
      Q => diff_pntr_pf_q(4),
      R => wrst_busy
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => diff_pntr_pf_q0(5),
      Q => diff_pntr_pf_q(5),
      R => wrst_busy
    );
\gen_pf_ic_rc.gpf_ic.prog_full_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => rst_d1_inst_n_1,
      Q => \^prog_full\,
      R => '0'
    );
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => ram_full_i0,
      Q => \^full\,
      R => wrst_busy
    );
\gen_pf_ic_rc.ram_empty_i_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => empty_i0,
      Q => \^empty\,
      S => \^rd_rst_busy\
    );
\gen_sdpram.xpm_memory_base_inst\: entity work.\design_1_Vsp_core_0_0_xpm_memory_base__parameterized1\
     port map (
      addra(4 downto 0) => wr_pntr_ext(4 downto 0),
      addrb(4 downto 0) => rd_pntr_ext(4 downto 0),
      clka => wr_clk,
      clkb => rd_clk,
      dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\,
      dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\,
      dina(25 downto 0) => din(25 downto 0),
      dinb(25 downto 0) => B"00000000000000000000000000",
      douta(25 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(25 downto 0),
      doutb(25 downto 0) => dout(25 downto 0),
      ena => wr_pntr_plus1_pf_carry,
      enb => ram_rd_en_i,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => \^rd_rst_busy\,
      sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\,
      sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\,
      sleep => '0',
      wea(0) => '0',
      web(0) => '0'
    );
\gof.overflow_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => overflow_i0,
      Q => overflow,
      R => '0'
    );
\grdc.rd_data_count_i_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => rd_clk,
      CE => '1',
      D => \grdc.diff_wr_rd_pntr_rdc0_out\(1),
      Q => rd_data_count(0),
      R => \^rd_rst_busy\
    );
\grdc.rd_data_count_i_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => rd_clk,
      CE => '1',
      D => \grdc.diff_wr_rd_pntr_rdc0_out\(2),
      Q => rd_data_count(1),
      R => \^rd_rst_busy\
    );
\grdc.rd_data_count_i_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => rd_clk,
      CE => '1',
      D => \grdc.diff_wr_rd_pntr_rdc0_out\(3),
      Q => rd_data_count(2),
      R => \^rd_rst_busy\
    );
\grdc.rd_data_count_i_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => rd_clk,
      CE => '1',
      D => \grdc.diff_wr_rd_pntr_rdc0_out\(4),
      Q => rd_data_count(3),
      R => \^rd_rst_busy\
    );
\grdc.rd_data_count_i_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rd_clk,
      CE => '1',
      D => \grdc.diff_wr_rd_pntr_rdc0_out\(5),
      Q => rd_data_count(4),
      R => \^rd_rst_busy\
    );
\guf.underflow_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => underflow_i0,
      Q => underflow,
      R => '0'
    );
\gwdc.wr_data_count_i_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => wr_clk,
      CE => '1',
      D => \gwdc.diff_wr_rd_pntr1_out\(1),
      Q => wr_data_count(0),
      R => wrst_busy
    );
\gwdc.wr_data_count_i_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => wr_clk,
      CE => '1',
      D => \gwdc.diff_wr_rd_pntr1_out\(2),
      Q => wr_data_count(1),
      R => wrst_busy
    );
\gwdc.wr_data_count_i_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => wr_clk,
      CE => '1',
      D => \gwdc.diff_wr_rd_pntr1_out\(3),
      Q => wr_data_count(2),
      R => wrst_busy
    );
\gwdc.wr_data_count_i_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => wr_clk,
      CE => '1',
      D => \gwdc.diff_wr_rd_pntr1_out\(4),
      Q => wr_data_count(3),
      R => wrst_busy
    );
\gwdc.wr_data_count_i_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wr_clk,
      CE => '1',
      D => \gwdc.diff_wr_rd_pntr1_out\(5),
      Q => wr_data_count(4),
      R => wrst_busy
    );
rdp_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_158\
     port map (
      D(0) => diff_pntr_pe(1),
      E(0) => ram_rd_en_i,
      Q(5 downto 0) => rd_pntr_ext(5 downto 0),
      SR(0) => \^rd_rst_busy\,
      \count_value_i_reg[2]_0\ => rdp_inst_n_9,
      \count_value_i_reg[4]_0\ => rdp_inst_n_10,
      \count_value_i_reg[5]_0\ => \^empty\,
      \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(3) => \gen_cdc_pntr.wpr_gray_reg_n_4\,
      \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\,
      \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\,
      \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\,
      \gen_pf_ic_rc.ram_empty_i_reg\ => rdp_inst_n_8,
      rd_clk => rd_clk,
      rd_en => rd_en
    );
rdpp1_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_159\
     port map (
      E(0) => ram_rd_en_i,
      Q(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\,
      Q(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\,
      Q(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\,
      Q(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\,
      Q(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\,
      SR(0) => \^rd_rst_busy\,
      \count_value_i_reg[4]_0\ => rdp_inst_n_8,
      empty_i0 => empty_i0,
      \gen_pf_ic_rc.ram_empty_i_reg\ => \gen_cdc_pntr.wpr_gray_reg_n_9\,
      \gen_pf_ic_rc.ram_empty_i_reg_0\ => rdp_inst_n_9,
      \gen_pf_ic_rc.ram_empty_i_reg_1\ => \^empty\,
      rd_clk => rd_clk,
      rd_en => rd_en
    );
rst_d1_inst: entity work.design_1_Vsp_core_0_0_xpm_fifo_reg_bit_160
     port map (
      Q(4 downto 0) => diff_pntr_pf_q(5 downto 1),
      d_out_int_reg_0 => rst_d1_inst_n_1,
      \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ => \^full\,
      prog_full => \^prog_full\,
      rst => rst,
      rst_d1 => rst_d1,
      wr_clk => wr_clk,
      wrst_busy => wrst_busy
    );
wrp_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_161\
     port map (
      D(4 downto 0) => \gwdc.diff_wr_rd_pntr1_out\(5 downto 1),
      E(0) => wr_pntr_plus1_pf_carry,
      Q(5 downto 0) => wr_pntr_ext(5 downto 0),
      \count_value_i_reg[5]_0\ => \^full\,
      \gwdc.wr_data_count_i_reg[5]\(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\,
      \gwdc.wr_data_count_i_reg[5]\(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\,
      \gwdc.wr_data_count_i_reg[5]\(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\,
      \gwdc.wr_data_count_i_reg[5]\(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\,
      \gwdc.wr_data_count_i_reg[5]\(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\,
      \gwdc.wr_data_count_i_reg[5]\(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\,
      rst_d1 => rst_d1,
      wr_clk => wr_clk,
      wr_en => wr_en,
      wrst_busy => wrst_busy
    );
wrpp1_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_162\
     port map (
      D(4 downto 0) => diff_pntr_pf_q0(5 downto 1),
      E(0) => wr_pntr_plus1_pf_carry,
      Q(1 downto 0) => wr_pntr_plus1_pf(5 downto 4),
      \count_value_i_reg[2]_0\ => wrpp1_inst_n_0,
      \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(4 downto 0) => rd_pntr_wr(4 downto 0),
      wr_clk => wr_clk,
      wrst_busy => wrst_busy
    );
wrpp2_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized9_163\
     port map (
      E(0) => wr_pntr_plus1_pf_carry,
      Q(2 downto 0) => rd_pntr_wr(2 downto 0),
      \count_value_i_reg[2]_0\ => wrpp2_inst_n_0,
      \count_value_i_reg[4]_0\(1) => wrpp2_inst_n_1,
      \count_value_i_reg[4]_0\(0) => wrpp2_inst_n_2,
      wr_clk => wr_clk,
      wrst_busy => wrst_busy
    );
xpm_fifo_rst_inst: entity work.\design_1_Vsp_core_0_0_xpm_fifo_rst__parameterized0__xdcDup__1\
     port map (
      E(0) => wr_pntr_plus1_pf_carry,
      SR(0) => \^rd_rst_busy\,
      \gof.overflow_i_reg\ => \^full\,
      \guf.underflow_i_reg\ => \^empty\,
      overflow_i0 => overflow_i0,
      rd_clk => rd_clk,
      rd_en => rd_en,
      rst => rst,
      rst_d1 => rst_d1,
      underflow_i0 => underflow_i0,
      wr_clk => wr_clk,
      wr_en => wr_en,
      wr_rst_busy => wr_rst_busy,
      wrst_busy => wrst_busy
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ is
  port (
    sleep : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 41 downto 0 );
    full : out STD_LOGIC;
    full_n : out STD_LOGIC;
    prog_full : out STD_LOGIC;
    wr_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
    overflow : out STD_LOGIC;
    wr_rst_busy : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    rd_clk : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 41 downto 0 );
    empty : out STD_LOGIC;
    prog_empty : out STD_LOGIC;
    rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
    underflow : out STD_LOGIC;
    rd_rst_busy : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    data_valid : out STD_LOGIC;
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC
  );
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute CDC_DEST_SYNC_FF : integer;
  attribute CDC_DEST_SYNC_FF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 2;
  attribute COMMON_CLOCK : integer;
  attribute COMMON_CLOCK of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute DOUT_RESET_VALUE : string;
  attribute DOUT_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "0";
  attribute ECC_MODE : integer;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute ENABLE_ECC : integer;
  attribute ENABLE_ECC of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute EN_ADV_FEATURE : string;
  attribute EN_ADV_FEATURE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "16'b0000011100000111";
  attribute EN_AE : string;
  attribute EN_AE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "1'b0";
  attribute EN_AF : string;
  attribute EN_AF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "1'b0";
  attribute EN_DVLD : string;
  attribute EN_DVLD of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "1'b0";
  attribute EN_OF : string;
  attribute EN_OF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "1'b1";
  attribute EN_PE : string;
  attribute EN_PE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "1'b1";
  attribute EN_PF : string;
  attribute EN_PF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "1'b1";
  attribute EN_RDC : string;
  attribute EN_RDC of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "1'b1";
  attribute EN_SIM_ASSERT_ERR : string;
  attribute EN_SIM_ASSERT_ERR of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "warning";
  attribute EN_UF : string;
  attribute EN_UF of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "1'b1";
  attribute EN_WACK : string;
  attribute EN_WACK of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "1'b0";
  attribute EN_WDC : string;
  attribute EN_WDC of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "1'b1";
  attribute FG_EQ_ASYM_DOUT : string;
  attribute FG_EQ_ASYM_DOUT of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "1'b0";
  attribute FIFO_MEMORY_TYPE : integer;
  attribute FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 1;
  attribute FIFO_MEM_TYPE : integer;
  attribute FIFO_MEM_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 1;
  attribute FIFO_READ_DEPTH : integer;
  attribute FIFO_READ_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 32;
  attribute FIFO_READ_LATENCY : integer;
  attribute FIFO_READ_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 1;
  attribute FIFO_SIZE : integer;
  attribute FIFO_SIZE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 1344;
  attribute FIFO_WRITE_DEPTH : integer;
  attribute FIFO_WRITE_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 32;
  attribute FULL_RESET_VALUE : integer;
  attribute FULL_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute FULL_RST_VAL : string;
  attribute FULL_RST_VAL of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "1'b0";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "xpm_fifo_base";
  attribute PE_THRESH_ADJ : integer;
  attribute PE_THRESH_ADJ of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 10;
  attribute PE_THRESH_MAX : integer;
  attribute PE_THRESH_MAX of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 29;
  attribute PE_THRESH_MIN : integer;
  attribute PE_THRESH_MIN of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 3;
  attribute PF_THRESH_ADJ : integer;
  attribute PF_THRESH_ADJ of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 10;
  attribute PF_THRESH_MAX : integer;
  attribute PF_THRESH_MAX of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 29;
  attribute PF_THRESH_MIN : integer;
  attribute PF_THRESH_MIN of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 5;
  attribute PROG_EMPTY_THRESH : integer;
  attribute PROG_EMPTY_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 10;
  attribute PROG_FULL_THRESH : integer;
  attribute PROG_FULL_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 10;
  attribute RD_DATA_COUNT_WIDTH : integer;
  attribute RD_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 1;
  attribute RD_DC_WIDTH_EXT : integer;
  attribute RD_DC_WIDTH_EXT of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 6;
  attribute RD_LATENCY : integer;
  attribute RD_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 1;
  attribute RD_MODE : integer;
  attribute RD_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute RD_PNTR_WIDTH : integer;
  attribute RD_PNTR_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 5;
  attribute READ_DATA_WIDTH : integer;
  attribute READ_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 42;
  attribute READ_MODE : integer;
  attribute READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute READ_MODE_LL : integer;
  attribute READ_MODE_LL of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute RELATED_CLOCKS : integer;
  attribute RELATED_CLOCKS of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute REMOVE_WR_RD_PROT_LOGIC : integer;
  attribute REMOVE_WR_RD_PROT_LOGIC of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute USE_ADV_FEATURES : string;
  attribute USE_ADV_FEATURES of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "0707";
  attribute VERSION : integer;
  attribute VERSION of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute WIDTH_RATIO : integer;
  attribute WIDTH_RATIO of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 1;
  attribute WRITE_DATA_WIDTH : integer;
  attribute WRITE_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 42;
  attribute WR_DATA_COUNT_WIDTH : integer;
  attribute WR_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 1;
  attribute WR_DC_WIDTH_EXT : integer;
  attribute WR_DC_WIDTH_EXT of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 6;
  attribute WR_DEPTH_LOG : integer;
  attribute WR_DEPTH_LOG of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 5;
  attribute WR_PNTR_WIDTH : integer;
  attribute WR_PNTR_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 5;
  attribute WR_RD_RATIO : integer;
  attribute WR_RD_RATIO of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute WR_WIDTH_LOG : integer;
  attribute WR_WIDTH_LOG of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 6;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "TRUE";
  attribute both_stages_valid : integer;
  attribute both_stages_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 3;
  attribute invalid : integer;
  attribute invalid of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 0;
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is "soft";
  attribute stage1_valid : integer;
  attribute stage1_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 2;
  attribute stage2_valid : integer;
  attribute stage2_valid of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ : entity is 1;
end \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\ is
  signal \<const0>\ : STD_LOGIC;
  signal diff_pntr_pe : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal diff_pntr_pf_q : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal diff_pntr_pf_q0 : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal \^empty\ : STD_LOGIC;
  signal empty_i0 : STD_LOGIC;
  signal \^full\ : STD_LOGIC;
  signal \gen_cdc_pntr.rpw_gray_reg_dc_n_0\ : STD_LOGIC;
  signal \gen_cdc_pntr.rpw_gray_reg_dc_n_1\ : STD_LOGIC;
  signal \gen_cdc_pntr.rpw_gray_reg_dc_n_2\ : STD_LOGIC;
  signal \gen_cdc_pntr.rpw_gray_reg_dc_n_3\ : STD_LOGIC;
  signal \gen_cdc_pntr.rpw_gray_reg_dc_n_4\ : STD_LOGIC;
  signal \gen_cdc_pntr.rpw_gray_reg_dc_n_5\ : STD_LOGIC;
  signal \gen_cdc_pntr.wpr_gray_reg_n_4\ : STD_LOGIC;
  signal \gen_cdc_pntr.wpr_gray_reg_n_5\ : STD_LOGIC;
  signal \gen_cdc_pntr.wpr_gray_reg_n_6\ : STD_LOGIC;
  signal \gen_cdc_pntr.wpr_gray_reg_n_7\ : STD_LOGIC;
  signal \gen_cdc_pntr.wpr_gray_reg_n_8\ : STD_LOGIC;
  signal \gen_cdc_pntr.wpr_gray_reg_n_9\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\ : STD_LOGIC;
  signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\ : STD_LOGIC;
  signal \grdc.diff_wr_rd_pntr_rdc0_out\ : STD_LOGIC_VECTOR ( 5 to 5 );
  signal \gwdc.diff_wr_rd_pntr1_out\ : STD_LOGIC_VECTOR ( 5 to 5 );
  signal overflow_i0 : STD_LOGIC;
  signal \^prog_empty\ : STD_LOGIC;
  signal \^prog_full\ : STD_LOGIC;
  signal ram_full_i0 : STD_LOGIC;
  signal ram_rd_en_i : STD_LOGIC;
  signal rd_pntr_ext : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rd_pntr_wr : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal rd_pntr_wr_cdc : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal rd_pntr_wr_cdc_dc : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^rd_rst_busy\ : STD_LOGIC;
  signal rdp_inst_n_10 : STD_LOGIC;
  signal rdp_inst_n_8 : STD_LOGIC;
  signal rdp_inst_n_9 : STD_LOGIC;
  signal rst_d1 : STD_LOGIC;
  signal rst_d1_inst_n_1 : STD_LOGIC;
  signal underflow_i0 : STD_LOGIC;
  signal wr_pntr_ext : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal wr_pntr_plus1_pf : STD_LOGIC_VECTOR ( 5 downto 4 );
  signal wr_pntr_plus1_pf_carry : STD_LOGIC;
  signal wr_pntr_rd_cdc : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal wr_pntr_rd_cdc_dc : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal wrpp1_inst_n_0 : STD_LOGIC;
  signal wrpp2_inst_n_0 : STD_LOGIC;
  signal wrpp2_inst_n_1 : STD_LOGIC;
  signal wrpp2_inst_n_2 : STD_LOGIC;
  signal wrst_busy : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 41 downto 0 );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 1;
  attribute REG_OUTPUT : integer;
  attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
  attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
  attribute SIM_LOSSLESS_GRAY_CHK : integer;
  attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
  attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
  attribute WIDTH : integer;
  attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 6;
  attribute XPM_CDC : string;
  attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "GRAY";
  attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "TRUE";
  attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 2;
  attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 1;
  attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
  attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
  attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
  attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
  attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 5;
  attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "GRAY";
  attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "TRUE";
  attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 2;
  attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 1;
  attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
  attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
  attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
  attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
  attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 6;
  attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "GRAY";
  attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "TRUE";
  attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 2;
  attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 1;
  attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
  attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
  attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
  attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
  attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 5;
  attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "GRAY";
  attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "TRUE";
  attribute ADDR_WIDTH_A : integer;
  attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
  attribute ADDR_WIDTH_B : integer;
  attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
  attribute AUTO_SLEEP_TIME : integer;
  attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute BYTE_WRITE_WIDTH_A : integer;
  attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 42;
  attribute BYTE_WRITE_WIDTH_B : integer;
  attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 42;
  attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute CLOCKING_MODE : integer;
  attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute ECC_BIT_RANGE : string;
  attribute ECC_BIT_RANGE of \gen_sdpram.xpm_memory_base_inst\ : label is "[7:0]";
  attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute ECC_TYPE : string;
  attribute ECC_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is "NONE";
  attribute IGNORE_INIT_SYNTH : integer;
  attribute IGNORE_INIT_SYNTH of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute KEEP_HIERARCHY of \gen_sdpram.xpm_memory_base_inst\ : label is "soft";
  attribute MAX_NUM_CHAR : integer;
  attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute MEMORY_INIT_FILE : string;
  attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none";
  attribute MEMORY_INIT_PARAM : string;
  attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is "";
  attribute MEMORY_OPTIMIZATION : string;
  attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true";
  attribute MEMORY_PRIMITIVE : integer;
  attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute MEMORY_SIZE : integer;
  attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 1344;
  attribute MEMORY_TYPE : integer;
  attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute MESSAGE_CONTROL : integer;
  attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute NUM_CHAR_LOC : integer;
  attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_ECC_MODE : string;
  attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc";
  attribute P_ENABLE_BYTE_WRITE_A : integer;
  attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_ENABLE_BYTE_WRITE_B : integer;
  attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_MAX_DEPTH_DATA : integer;
  attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 32;
  attribute P_MEMORY_OPT : string;
  attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
  attribute P_MEMORY_PRIMITIVE : string;
  attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "distributed";
  attribute P_MIN_WIDTH_DATA : integer;
  attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 42;
  attribute P_MIN_WIDTH_DATA_A : integer;
  attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 42;
  attribute P_MIN_WIDTH_DATA_B : integer;
  attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 42;
  attribute P_MIN_WIDTH_DATA_ECC : integer;
  attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 42;
  attribute P_MIN_WIDTH_DATA_LDW : integer;
  attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
  attribute P_MIN_WIDTH_DATA_SHFT : integer;
  attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 42;
  attribute P_NUM_COLS_WRITE_A : integer;
  attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_COLS_WRITE_B : integer;
  attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_READ_A : integer;
  attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_READ_B : integer;
  attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_WRITE_A : integer;
  attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_NUM_ROWS_WRITE_B : integer;
  attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute P_SDP_WRITE_MODE : string;
  attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
  attribute P_WIDTH_ADDR_LSB_READ_A : integer;
  attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_READ_B : integer;
  attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
  attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute P_WIDTH_ADDR_READ_A : integer;
  attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
  attribute P_WIDTH_ADDR_READ_B : integer;
  attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
  attribute P_WIDTH_ADDR_WRITE_A : integer;
  attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
  attribute P_WIDTH_ADDR_WRITE_B : integer;
  attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
  attribute P_WIDTH_COL_WRITE_A : integer;
  attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 42;
  attribute P_WIDTH_COL_WRITE_B : integer;
  attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 42;
  attribute RAM_DECOMP : string;
  attribute RAM_DECOMP of \gen_sdpram.xpm_memory_base_inst\ : label is "auto";
  attribute READ_DATA_WIDTH_A : integer;
  attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 42;
  attribute READ_DATA_WIDTH_B : integer;
  attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 42;
  attribute READ_LATENCY_A : integer;
  attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute READ_LATENCY_B : integer;
  attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute READ_RESET_VALUE_A : string;
  attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
  attribute READ_RESET_VALUE_B : string;
  attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
  attribute RST_MODE_A : string;
  attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
  attribute RST_MODE_B : string;
  attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
  attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_EMBEDDED_CONSTRAINT : integer;
  attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute USE_MEM_INIT : integer;
  attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute USE_MEM_INIT_MMI : integer;
  attribute USE_MEM_INIT_MMI of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
  attribute WRITE_DATA_WIDTH_A : integer;
  attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 42;
  attribute WRITE_DATA_WIDTH_B : integer;
  attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 42;
  attribute WRITE_MODE_A : integer;
  attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
  attribute WRITE_MODE_B : integer;
  attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute WRITE_PROTECT : integer;
  attribute WRITE_PROTECT of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
  attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE";
  attribute rsta_loop_iter : integer;
  attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
  attribute rstb_loop_iter : integer;
  attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
begin
  almost_empty <= \<const0>\;
  almost_full <= \<const0>\;
  data_valid <= \<const0>\;
  dbiterr <= \<const0>\;
  empty <= \^empty\;
  full <= \^full\;
  full_n <= \<const0>\;
  prog_empty <= \^prog_empty\;
  prog_full <= \^prog_full\;
  rd_rst_busy <= \^rd_rst_busy\;
  sbiterr <= \<const0>\;
  wr_ack <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gen_cdc_pntr.rd_pntr_cdc_dc_inst\: entity work.\design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__5\
     port map (
      dest_clk => wr_clk,
      dest_out_bin(5 downto 0) => rd_pntr_wr_cdc_dc(5 downto 0),
      src_clk => rd_clk,
      src_in_bin(5 downto 0) => rd_pntr_ext(5 downto 0)
    );
\gen_cdc_pntr.rd_pntr_cdc_inst\: entity work.\design_1_Vsp_core_0_0_xpm_cdc_gray__5\
     port map (
      dest_clk => wr_clk,
      dest_out_bin(4 downto 0) => rd_pntr_wr_cdc(4 downto 0),
      src_clk => rd_clk,
      src_in_bin(4 downto 0) => rd_pntr_ext(4 downto 0)
    );
\gen_cdc_pntr.rpw_gray_reg\: entity work.design_1_Vsp_core_0_0_xpm_fifo_reg_vec
     port map (
      D(4 downto 0) => rd_pntr_wr_cdc(4 downto 0),
      E(0) => wr_pntr_plus1_pf_carry,
      Q(4 downto 0) => rd_pntr_wr(4 downto 0),
      \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\ => wrpp1_inst_n_0,
      \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_0\ => wrpp2_inst_n_0,
      \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_1\(1) => wrpp2_inst_n_1,
      \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_1\(0) => wrpp2_inst_n_2,
      \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_2\(1 downto 0) => wr_pntr_plus1_pf(5 downto 4),
      ram_full_i0 => ram_full_i0,
      wr_clk => wr_clk,
      wrst_busy => wrst_busy
    );
\gen_cdc_pntr.rpw_gray_reg_dc\: entity work.\design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0\
     port map (
      D(5 downto 0) => rd_pntr_wr_cdc_dc(5 downto 0),
      Q(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\,
      Q(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\,
      Q(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\,
      Q(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\,
      Q(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\,
      Q(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\,
      wr_clk => wr_clk,
      wrst_busy => wrst_busy
    );
\gen_cdc_pntr.wpr_gray_reg\: entity work.design_1_Vsp_core_0_0_xpm_fifo_reg_vec_125
     port map (
      D(3 downto 1) => diff_pntr_pe(4 downto 2),
      D(0) => diff_pntr_pe(0),
      Q(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\,
      Q(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\,
      Q(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\,
      Q(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\,
      Q(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\,
      \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\ => \^empty\,
      \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\ => rdp_inst_n_10,
      \gen_pf_ic_rc.ram_empty_i_reg\(4 downto 0) => rd_pntr_ext(4 downto 0),
      rd_clk => rd_clk,
      rd_en => rd_en,
      \reg_out_i_reg[0]_0\ => \^rd_rst_busy\,
      \reg_out_i_reg[3]_0\ => \gen_cdc_pntr.wpr_gray_reg_n_9\,
      \reg_out_i_reg[4]_0\(4 downto 0) => wr_pntr_rd_cdc(4 downto 0)
    );
\gen_cdc_pntr.wpr_gray_reg_dc\: entity work.\design_1_Vsp_core_0_0_xpm_fifo_reg_vec__parameterized0_126\
     port map (
      D(5 downto 0) => wr_pntr_rd_cdc_dc(5 downto 0),
      O(0) => \grdc.diff_wr_rd_pntr_rdc0_out\(5),
      Q(5 downto 0) => rd_pntr_ext(5 downto 0),
      rd_clk => rd_clk,
      \reg_out_i_reg[0]_0\ => \^rd_rst_busy\
    );
\gen_cdc_pntr.wr_pntr_cdc_dc_inst\: entity work.\design_1_Vsp_core_0_0_xpm_cdc_gray__parameterized0__4\
     port map (
      dest_clk => rd_clk,
      dest_out_bin(5 downto 0) => wr_pntr_rd_cdc_dc(5 downto 0),
      src_clk => wr_clk,
      src_in_bin(5 downto 0) => wr_pntr_ext(5 downto 0)
    );
\gen_cdc_pntr.wr_pntr_cdc_inst\: entity work.\design_1_Vsp_core_0_0_xpm_cdc_gray__4\
     port map (
      dest_clk => rd_clk,
      dest_out_bin(4 downto 0) => wr_pntr_rd_cdc(4 downto 0),
      src_clk => wr_clk,
      src_in_bin(4 downto 0) => wr_pntr_ext(4 downto 0)
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => diff_pntr_pe(0),
      Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\,
      R => \^rd_rst_busy\
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => diff_pntr_pe(1),
      Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\,
      R => \^rd_rst_busy\
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => diff_pntr_pe(2),
      Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\,
      R => \^rd_rst_busy\
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => diff_pntr_pe(3),
      Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\,
      R => \^rd_rst_busy\
    );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => diff_pntr_pe(4),
      Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\,
      R => \^rd_rst_busy\
    );
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^prog_empty\,
      I1 => \^empty\,
      I2 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\,
      O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\
    );
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000557F"
    )
        port map (
      I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\,
      I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\,
      I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\,
      I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\,
      I4 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\,
      O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\
    );
\gen_pf_ic_rc.gpe_ic.prog_empty_i_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\,
      Q => \^prog_empty\,
      S => \^rd_rst_busy\
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => diff_pntr_pf_q0(2),
      Q => diff_pntr_pf_q(2),
      R => wrst_busy
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => diff_pntr_pf_q0(3),
      Q => diff_pntr_pf_q(3),
      R => wrst_busy
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => diff_pntr_pf_q0(4),
      Q => diff_pntr_pf_q(4),
      R => wrst_busy
    );
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => diff_pntr_pf_q0(5),
      Q => diff_pntr_pf_q(5),
      R => wrst_busy
    );
\gen_pf_ic_rc.gpf_ic.prog_full_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => rst_d1_inst_n_1,
      Q => \^prog_full\,
      R => '0'
    );
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => ram_full_i0,
      Q => \^full\,
      R => wrst_busy
    );
\gen_pf_ic_rc.ram_empty_i_reg\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => empty_i0,
      Q => \^empty\,
      S => \^rd_rst_busy\
    );
\gen_sdpram.xpm_memory_base_inst\: entity work.\design_1_Vsp_core_0_0_xpm_memory_base__parameterized2\
     port map (
      addra(4 downto 0) => wr_pntr_ext(4 downto 0),
      addrb(4 downto 0) => rd_pntr_ext(4 downto 0),
      clka => wr_clk,
      clkb => rd_clk,
      dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\,
      dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\,
      dina(41 downto 0) => din(41 downto 0),
      dinb(41 downto 0) => B"000000000000000000000000000000000000000000",
      douta(41 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(41 downto 0),
      doutb(41 downto 0) => dout(41 downto 0),
      ena => wr_pntr_plus1_pf_carry,
      enb => ram_rd_en_i,
      injectdbiterra => '0',
      injectdbiterrb => '0',
      injectsbiterra => '0',
      injectsbiterrb => '0',
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rstb => \^rd_rst_busy\,
      sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\,
      sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\,
      sleep => '0',
      wea(0) => '0',
      web(0) => '0'
    );
\gof.overflow_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => wr_clk,
      CE => '1',
      D => overflow_i0,
      Q => overflow,
      R => '0'
    );
\grdc.rd_data_count_i_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => rd_clk,
      CE => '1',
      D => \grdc.diff_wr_rd_pntr_rdc0_out\(5),
      Q => rd_data_count(0),
      R => \^rd_rst_busy\
    );
\guf.underflow_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rd_clk,
      CE => '1',
      D => underflow_i0,
      Q => underflow,
      R => '0'
    );
\gwdc.wr_data_count_i_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => wr_clk,
      CE => '1',
      D => \gwdc.diff_wr_rd_pntr1_out\(5),
      Q => wr_data_count(0),
      R => wrst_busy
    );
rdp_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7\
     port map (
      D(0) => diff_pntr_pe(1),
      E(0) => ram_rd_en_i,
      Q(5 downto 0) => rd_pntr_ext(5 downto 0),
      \count_value_i_reg[2]_0\ => rdp_inst_n_9,
      \count_value_i_reg[4]_0\ => rdp_inst_n_10,
      \count_value_i_reg[5]_0\ => \^empty\,
      \count_value_i_reg[5]_1\ => \^rd_rst_busy\,
      \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(3) => \gen_cdc_pntr.wpr_gray_reg_n_4\,
      \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\,
      \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\,
      \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\,
      \gen_pf_ic_rc.ram_empty_i_reg\ => rdp_inst_n_8,
      rd_clk => rd_clk,
      rd_en => rd_en
    );
rdpp1_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8\
     port map (
      E(0) => ram_rd_en_i,
      Q(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\,
      Q(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\,
      Q(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\,
      Q(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\,
      Q(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\,
      \count_value_i_reg[0]_0\ => \^rd_rst_busy\,
      \count_value_i_reg[4]_0\ => rdp_inst_n_8,
      empty_i0 => empty_i0,
      \gen_pf_ic_rc.ram_empty_i_reg\ => \gen_cdc_pntr.wpr_gray_reg_n_9\,
      \gen_pf_ic_rc.ram_empty_i_reg_0\ => rdp_inst_n_9,
      \gen_pf_ic_rc.ram_empty_i_reg_1\ => \^empty\,
      rd_clk => rd_clk,
      rd_en => rd_en
    );
rst_d1_inst: entity work.design_1_Vsp_core_0_0_xpm_fifo_reg_bit
     port map (
      Q(3 downto 0) => diff_pntr_pf_q(5 downto 2),
      d_out_int_reg_0 => rst_d1_inst_n_1,
      \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ => \^full\,
      prog_full => \^prog_full\,
      rst => rst,
      rst_d1 => rst_d1,
      wr_clk => wr_clk,
      wrst_busy => wrst_busy
    );
wrp_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized7_127\
     port map (
      E(0) => wr_pntr_plus1_pf_carry,
      O(0) => \gwdc.diff_wr_rd_pntr1_out\(5),
      Q(5 downto 0) => wr_pntr_ext(5 downto 0),
      \count_value_i_reg[5]_0\ => \^full\,
      \gwdc.wr_data_count_i_reg[5]\(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\,
      \gwdc.wr_data_count_i_reg[5]\(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\,
      \gwdc.wr_data_count_i_reg[5]\(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\,
      \gwdc.wr_data_count_i_reg[5]\(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\,
      \gwdc.wr_data_count_i_reg[5]\(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\,
      \gwdc.wr_data_count_i_reg[5]\(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\,
      rst_d1 => rst_d1,
      wr_clk => wr_clk,
      wr_en => wr_en,
      wrst_busy => wrst_busy
    );
wrpp1_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized8_128\
     port map (
      D(3 downto 0) => diff_pntr_pf_q0(5 downto 2),
      E(0) => wr_pntr_plus1_pf_carry,
      Q(1 downto 0) => wr_pntr_plus1_pf(5 downto 4),
      \count_value_i_reg[2]_0\ => wrpp1_inst_n_0,
      \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\(4 downto 0) => rd_pntr_wr(4 downto 0),
      wr_clk => wr_clk,
      wrst_busy => wrst_busy
    );
wrpp2_inst: entity work.\design_1_Vsp_core_0_0_xpm_counter_updn__parameterized9\
     port map (
      E(0) => wr_pntr_plus1_pf_carry,
      Q(2 downto 0) => rd_pntr_wr(2 downto 0),
      \count_value_i_reg[2]_0\ => wrpp2_inst_n_0,
      \count_value_i_reg[4]_0\(1) => wrpp2_inst_n_1,
      \count_value_i_reg[4]_0\(0) => wrpp2_inst_n_2,
      wr_clk => wr_clk,
      wrst_busy => wrst_busy
    );
xpm_fifo_rst_inst: entity work.\design_1_Vsp_core_0_0_xpm_fifo_rst__parameterized0\
     port map (
      E(0) => wr_pntr_plus1_pf_carry,
      \gen_rst_ic.fifo_rd_rst_ic_reg_0\ => \^rd_rst_busy\,
      \gof.overflow_i_reg\ => \^full\,
      \guf.underflow_i_reg\ => \^empty\,
      overflow_i0 => overflow_i0,
      rd_clk => rd_clk,
      rd_en => rd_en,
      rst => rst,
      rst_d1 => rst_d1,
      underflow_i0 => underflow_i0,
      wr_clk => wr_clk,
      wr_en => wr_en,
      wr_rst_busy => wr_rst_busy,
      wrst_busy => wrst_busy
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_sync is
  port (
    sleep : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 11 downto 0 );
    full : out STD_LOGIC;
    prog_full : out STD_LOGIC;
    wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    overflow : out STD_LOGIC;
    wr_rst_busy : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
    empty : out STD_LOGIC;
    prog_empty : out STD_LOGIC;
    rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    underflow : out STD_LOGIC;
    rd_rst_busy : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    data_valid : out STD_LOGIC;
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC
  );
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 0;
  attribute DOUT_RESET_VALUE : string;
  attribute DOUT_RESET_VALUE of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is "0";
  attribute ECC_MODE : string;
  attribute ECC_MODE of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is "no_ecc";
  attribute EN_ADV_FEATURE_SYNC : string;
  attribute EN_ADV_FEATURE_SYNC of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is "16'b0000011100000111";
  attribute EN_SIM_ASSERT_ERR : string;
  attribute EN_SIM_ASSERT_ERR of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is "warning";
  attribute FIFO_MEMORY_TYPE : string;
  attribute FIFO_MEMORY_TYPE of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is "distributed";
  attribute FIFO_READ_LATENCY : integer;
  attribute FIFO_READ_LATENCY of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 1;
  attribute FIFO_WRITE_DEPTH : integer;
  attribute FIFO_WRITE_DEPTH of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 16;
  attribute FULL_RESET_VALUE : integer;
  attribute FULL_RESET_VALUE of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is "xpm_fifo_sync";
  attribute PROG_EMPTY_THRESH : integer;
  attribute PROG_EMPTY_THRESH of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 5;
  attribute PROG_FULL_THRESH : integer;
  attribute PROG_FULL_THRESH of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 11;
  attribute P_COMMON_CLOCK : integer;
  attribute P_COMMON_CLOCK of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 1;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 0;
  attribute P_FIFO_MEMORY_TYPE : integer;
  attribute P_FIFO_MEMORY_TYPE of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 1;
  attribute P_READ_MODE : integer;
  attribute P_READ_MODE of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 2;
  attribute RD_DATA_COUNT_WIDTH : integer;
  attribute RD_DATA_COUNT_WIDTH of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 5;
  attribute READ_DATA_WIDTH : integer;
  attribute READ_DATA_WIDTH of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 12;
  attribute READ_MODE : string;
  attribute READ_MODE of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is "fwft";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 0;
  attribute USE_ADV_FEATURES : string;
  attribute USE_ADV_FEATURES of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is "0707";
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 0;
  attribute WRITE_DATA_WIDTH : integer;
  attribute WRITE_DATA_WIDTH of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 12;
  attribute WR_DATA_COUNT_WIDTH : integer;
  attribute WR_DATA_COUNT_WIDTH of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is 5;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of design_1_Vsp_core_0_0_xpm_fifo_sync : entity is "soft";
end design_1_Vsp_core_0_0_xpm_fifo_sync;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_sync is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_full_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_full_n_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute CASCADE_HEIGHT of xpm_fifo_base_inst : label is 0;
  attribute CDC_DEST_SYNC_FF : integer;
  attribute CDC_DEST_SYNC_FF of xpm_fifo_base_inst : label is 2;
  attribute COMMON_CLOCK : integer;
  attribute COMMON_CLOCK of xpm_fifo_base_inst : label is 1;
  attribute DOUT_RESET_VALUE of xpm_fifo_base_inst : label is "0";
  attribute ECC_MODE_integer : integer;
  attribute ECC_MODE_integer of xpm_fifo_base_inst : label is 0;
  attribute ENABLE_ECC : integer;
  attribute ENABLE_ECC of xpm_fifo_base_inst : label is 0;
  attribute EN_ADV_FEATURE : string;
  attribute EN_ADV_FEATURE of xpm_fifo_base_inst : label is "16'b0000011100000111";
  attribute EN_AE : string;
  attribute EN_AE of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_AF : string;
  attribute EN_AF of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_DVLD : string;
  attribute EN_DVLD of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_OF : string;
  attribute EN_OF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_PE : string;
  attribute EN_PE of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_PF : string;
  attribute EN_PF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_RDC : string;
  attribute EN_RDC of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_SIM_ASSERT_ERR of xpm_fifo_base_inst : label is "warning";
  attribute EN_UF : string;
  attribute EN_UF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_WACK : string;
  attribute EN_WACK of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_WDC : string;
  attribute EN_WDC of xpm_fifo_base_inst : label is "1'b1";
  attribute FG_EQ_ASYM_DOUT : string;
  attribute FG_EQ_ASYM_DOUT of xpm_fifo_base_inst : label is "1'b0";
  attribute FIFO_MEMORY_TYPE_integer : integer;
  attribute FIFO_MEMORY_TYPE_integer of xpm_fifo_base_inst : label is 1;
  attribute FIFO_MEM_TYPE : integer;
  attribute FIFO_MEM_TYPE of xpm_fifo_base_inst : label is 1;
  attribute FIFO_READ_DEPTH : integer;
  attribute FIFO_READ_DEPTH of xpm_fifo_base_inst : label is 16;
  attribute FIFO_READ_LATENCY of xpm_fifo_base_inst : label is 1;
  attribute FIFO_SIZE : integer;
  attribute FIFO_SIZE of xpm_fifo_base_inst : label is 192;
  attribute FIFO_WRITE_DEPTH of xpm_fifo_base_inst : label is 16;
  attribute FULL_RESET_VALUE of xpm_fifo_base_inst : label is 0;
  attribute FULL_RST_VAL : string;
  attribute FULL_RST_VAL of xpm_fifo_base_inst : label is "1'b0";
  attribute KEEP_HIERARCHY of xpm_fifo_base_inst : label is "soft";
  attribute PE_THRESH_ADJ : integer;
  attribute PE_THRESH_ADJ of xpm_fifo_base_inst : label is 3;
  attribute PE_THRESH_MAX : integer;
  attribute PE_THRESH_MAX of xpm_fifo_base_inst : label is 11;
  attribute PE_THRESH_MIN : integer;
  attribute PE_THRESH_MIN of xpm_fifo_base_inst : label is 5;
  attribute PF_THRESH_ADJ : integer;
  attribute PF_THRESH_ADJ of xpm_fifo_base_inst : label is 9;
  attribute PF_THRESH_MAX : integer;
  attribute PF_THRESH_MAX of xpm_fifo_base_inst : label is 11;
  attribute PF_THRESH_MIN : integer;
  attribute PF_THRESH_MIN of xpm_fifo_base_inst : label is 5;
  attribute PROG_EMPTY_THRESH of xpm_fifo_base_inst : label is 5;
  attribute PROG_FULL_THRESH of xpm_fifo_base_inst : label is 11;
  attribute RD_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 5;
  attribute RD_DC_WIDTH_EXT : integer;
  attribute RD_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 5;
  attribute RD_LATENCY : integer;
  attribute RD_LATENCY of xpm_fifo_base_inst : label is 2;
  attribute RD_MODE : integer;
  attribute RD_MODE of xpm_fifo_base_inst : label is 1;
  attribute RD_PNTR_WIDTH : integer;
  attribute RD_PNTR_WIDTH of xpm_fifo_base_inst : label is 4;
  attribute READ_DATA_WIDTH of xpm_fifo_base_inst : label is 12;
  attribute READ_MODE_integer : integer;
  attribute READ_MODE_integer of xpm_fifo_base_inst : label is 1;
  attribute READ_MODE_LL : integer;
  attribute READ_MODE_LL of xpm_fifo_base_inst : label is 1;
  attribute RELATED_CLOCKS : integer;
  attribute RELATED_CLOCKS of xpm_fifo_base_inst : label is 0;
  attribute REMOVE_WR_RD_PROT_LOGIC : integer;
  attribute REMOVE_WR_RD_PROT_LOGIC of xpm_fifo_base_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_fifo_base_inst : label is 0;
  attribute USE_ADV_FEATURES of xpm_fifo_base_inst : label is "0707";
  attribute VERSION : integer;
  attribute VERSION of xpm_fifo_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_fifo_base_inst : label is 0;
  attribute WIDTH_RATIO : integer;
  attribute WIDTH_RATIO of xpm_fifo_base_inst : label is 1;
  attribute WRITE_DATA_WIDTH of xpm_fifo_base_inst : label is 12;
  attribute WR_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 5;
  attribute WR_DC_WIDTH_EXT : integer;
  attribute WR_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 5;
  attribute WR_DEPTH_LOG : integer;
  attribute WR_DEPTH_LOG of xpm_fifo_base_inst : label is 4;
  attribute WR_PNTR_WIDTH : integer;
  attribute WR_PNTR_WIDTH of xpm_fifo_base_inst : label is 4;
  attribute WR_RD_RATIO : integer;
  attribute WR_RD_RATIO of xpm_fifo_base_inst : label is 0;
  attribute WR_WIDTH_LOG : integer;
  attribute WR_WIDTH_LOG of xpm_fifo_base_inst : label is 4;
  attribute XPM_MODULE of xpm_fifo_base_inst : label is "TRUE";
  attribute both_stages_valid : integer;
  attribute both_stages_valid of xpm_fifo_base_inst : label is 3;
  attribute invalid : integer;
  attribute invalid of xpm_fifo_base_inst : label is 0;
  attribute stage1_valid : integer;
  attribute stage1_valid of xpm_fifo_base_inst : label is 2;
  attribute stage2_valid : integer;
  attribute stage2_valid of xpm_fifo_base_inst : label is 1;
begin
  almost_empty <= \<const0>\;
  almost_full <= \<const0>\;
  data_valid <= \<const0>\;
  dbiterr <= \<const0>\;
  full <= \<const0>\;
  overflow <= \<const0>\;
  prog_empty <= \<const0>\;
  prog_full <= \<const0>\;
  rd_data_count(4) <= \<const0>\;
  rd_data_count(3) <= \<const0>\;
  rd_data_count(2) <= \<const0>\;
  rd_data_count(1) <= \<const0>\;
  rd_data_count(0) <= \<const0>\;
  rd_rst_busy <= \<const0>\;
  sbiterr <= \<const0>\;
  underflow <= \<const0>\;
  wr_ack <= \<const0>\;
  wr_data_count(4) <= \<const0>\;
  wr_data_count(3) <= \<const0>\;
  wr_data_count(2) <= \<const0>\;
  wr_data_count(1) <= \<const0>\;
  wr_data_count(0) <= \<const0>\;
  wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_fifo_base_inst: entity work.design_1_Vsp_core_0_0_xpm_fifo_base
     port map (
      almost_empty => NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED,
      almost_full => NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED,
      data_valid => NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED,
      dbiterr => NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED,
      din(11 downto 0) => din(11 downto 0),
      dout(11 downto 0) => dout(11 downto 0),
      empty => empty,
      full => NLW_xpm_fifo_base_inst_full_UNCONNECTED,
      full_n => NLW_xpm_fifo_base_inst_full_n_UNCONNECTED,
      injectdbiterr => '0',
      injectsbiterr => '0',
      overflow => NLW_xpm_fifo_base_inst_overflow_UNCONNECTED,
      prog_empty => NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED,
      prog_full => NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED,
      rd_clk => '0',
      rd_data_count(4 downto 0) => NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED(4 downto 0),
      rd_en => rd_en,
      rd_rst_busy => NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED,
      rst => rst,
      sbiterr => NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED,
      sleep => '0',
      underflow => NLW_xpm_fifo_base_inst_underflow_UNCONNECTED,
      wr_ack => NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED,
      wr_clk => wr_clk,
      wr_data_count(4 downto 0) => NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED(4 downto 0),
      wr_en => wr_en,
      wr_rst_busy => NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ is
  port (
    sleep : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 11 downto 0 );
    full : out STD_LOGIC;
    prog_full : out STD_LOGIC;
    wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    overflow : out STD_LOGIC;
    wr_rst_busy : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
    empty : out STD_LOGIC;
    prog_empty : out STD_LOGIC;
    rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    underflow : out STD_LOGIC;
    rd_rst_busy : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    data_valid : out STD_LOGIC;
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC
  );
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 0;
  attribute DOUT_RESET_VALUE : string;
  attribute DOUT_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is "0";
  attribute ECC_MODE : string;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is "no_ecc";
  attribute EN_ADV_FEATURE_SYNC : string;
  attribute EN_ADV_FEATURE_SYNC of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is "16'b0000011100000111";
  attribute EN_SIM_ASSERT_ERR : string;
  attribute EN_SIM_ASSERT_ERR of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is "warning";
  attribute FIFO_MEMORY_TYPE : string;
  attribute FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is "distributed";
  attribute FIFO_READ_LATENCY : integer;
  attribute FIFO_READ_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 1;
  attribute FIFO_WRITE_DEPTH : integer;
  attribute FIFO_WRITE_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 16;
  attribute FULL_RESET_VALUE : integer;
  attribute FULL_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is "xpm_fifo_sync";
  attribute PROG_EMPTY_THRESH : integer;
  attribute PROG_EMPTY_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 5;
  attribute PROG_FULL_THRESH : integer;
  attribute PROG_FULL_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 11;
  attribute P_COMMON_CLOCK : integer;
  attribute P_COMMON_CLOCK of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 1;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 0;
  attribute P_FIFO_MEMORY_TYPE : integer;
  attribute P_FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 1;
  attribute P_READ_MODE : integer;
  attribute P_READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 2;
  attribute RD_DATA_COUNT_WIDTH : integer;
  attribute RD_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 5;
  attribute READ_DATA_WIDTH : integer;
  attribute READ_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 12;
  attribute READ_MODE : string;
  attribute READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is "fwft";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 0;
  attribute USE_ADV_FEATURES : string;
  attribute USE_ADV_FEATURES of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is "0707";
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 0;
  attribute WRITE_DATA_WIDTH : integer;
  attribute WRITE_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 12;
  attribute WR_DATA_COUNT_WIDTH : integer;
  attribute WR_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is 5;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ : entity is "soft";
end \design_1_Vsp_core_0_0_xpm_fifo_sync__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_sync__4\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_full_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_full_n_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute CASCADE_HEIGHT of xpm_fifo_base_inst : label is 0;
  attribute CDC_DEST_SYNC_FF : integer;
  attribute CDC_DEST_SYNC_FF of xpm_fifo_base_inst : label is 2;
  attribute COMMON_CLOCK : integer;
  attribute COMMON_CLOCK of xpm_fifo_base_inst : label is 1;
  attribute DOUT_RESET_VALUE of xpm_fifo_base_inst : label is "0";
  attribute ECC_MODE_integer : integer;
  attribute ECC_MODE_integer of xpm_fifo_base_inst : label is 0;
  attribute ENABLE_ECC : integer;
  attribute ENABLE_ECC of xpm_fifo_base_inst : label is 0;
  attribute EN_ADV_FEATURE : string;
  attribute EN_ADV_FEATURE of xpm_fifo_base_inst : label is "16'b0000011100000111";
  attribute EN_AE : string;
  attribute EN_AE of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_AF : string;
  attribute EN_AF of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_DVLD : string;
  attribute EN_DVLD of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_OF : string;
  attribute EN_OF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_PE : string;
  attribute EN_PE of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_PF : string;
  attribute EN_PF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_RDC : string;
  attribute EN_RDC of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_SIM_ASSERT_ERR of xpm_fifo_base_inst : label is "warning";
  attribute EN_UF : string;
  attribute EN_UF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_WACK : string;
  attribute EN_WACK of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_WDC : string;
  attribute EN_WDC of xpm_fifo_base_inst : label is "1'b1";
  attribute FG_EQ_ASYM_DOUT : string;
  attribute FG_EQ_ASYM_DOUT of xpm_fifo_base_inst : label is "1'b0";
  attribute FIFO_MEMORY_TYPE_integer : integer;
  attribute FIFO_MEMORY_TYPE_integer of xpm_fifo_base_inst : label is 1;
  attribute FIFO_MEM_TYPE : integer;
  attribute FIFO_MEM_TYPE of xpm_fifo_base_inst : label is 1;
  attribute FIFO_READ_DEPTH : integer;
  attribute FIFO_READ_DEPTH of xpm_fifo_base_inst : label is 16;
  attribute FIFO_READ_LATENCY of xpm_fifo_base_inst : label is 1;
  attribute FIFO_SIZE : integer;
  attribute FIFO_SIZE of xpm_fifo_base_inst : label is 192;
  attribute FIFO_WRITE_DEPTH of xpm_fifo_base_inst : label is 16;
  attribute FULL_RESET_VALUE of xpm_fifo_base_inst : label is 0;
  attribute FULL_RST_VAL : string;
  attribute FULL_RST_VAL of xpm_fifo_base_inst : label is "1'b0";
  attribute KEEP_HIERARCHY of xpm_fifo_base_inst : label is "soft";
  attribute PE_THRESH_ADJ : integer;
  attribute PE_THRESH_ADJ of xpm_fifo_base_inst : label is 3;
  attribute PE_THRESH_MAX : integer;
  attribute PE_THRESH_MAX of xpm_fifo_base_inst : label is 11;
  attribute PE_THRESH_MIN : integer;
  attribute PE_THRESH_MIN of xpm_fifo_base_inst : label is 5;
  attribute PF_THRESH_ADJ : integer;
  attribute PF_THRESH_ADJ of xpm_fifo_base_inst : label is 9;
  attribute PF_THRESH_MAX : integer;
  attribute PF_THRESH_MAX of xpm_fifo_base_inst : label is 11;
  attribute PF_THRESH_MIN : integer;
  attribute PF_THRESH_MIN of xpm_fifo_base_inst : label is 5;
  attribute PROG_EMPTY_THRESH of xpm_fifo_base_inst : label is 5;
  attribute PROG_FULL_THRESH of xpm_fifo_base_inst : label is 11;
  attribute RD_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 5;
  attribute RD_DC_WIDTH_EXT : integer;
  attribute RD_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 5;
  attribute RD_LATENCY : integer;
  attribute RD_LATENCY of xpm_fifo_base_inst : label is 2;
  attribute RD_MODE : integer;
  attribute RD_MODE of xpm_fifo_base_inst : label is 1;
  attribute RD_PNTR_WIDTH : integer;
  attribute RD_PNTR_WIDTH of xpm_fifo_base_inst : label is 4;
  attribute READ_DATA_WIDTH of xpm_fifo_base_inst : label is 12;
  attribute READ_MODE_integer : integer;
  attribute READ_MODE_integer of xpm_fifo_base_inst : label is 1;
  attribute READ_MODE_LL : integer;
  attribute READ_MODE_LL of xpm_fifo_base_inst : label is 1;
  attribute RELATED_CLOCKS : integer;
  attribute RELATED_CLOCKS of xpm_fifo_base_inst : label is 0;
  attribute REMOVE_WR_RD_PROT_LOGIC : integer;
  attribute REMOVE_WR_RD_PROT_LOGIC of xpm_fifo_base_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_fifo_base_inst : label is 0;
  attribute USE_ADV_FEATURES of xpm_fifo_base_inst : label is "0707";
  attribute VERSION : integer;
  attribute VERSION of xpm_fifo_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_fifo_base_inst : label is 0;
  attribute WIDTH_RATIO : integer;
  attribute WIDTH_RATIO of xpm_fifo_base_inst : label is 1;
  attribute WRITE_DATA_WIDTH of xpm_fifo_base_inst : label is 12;
  attribute WR_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 5;
  attribute WR_DC_WIDTH_EXT : integer;
  attribute WR_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 5;
  attribute WR_DEPTH_LOG : integer;
  attribute WR_DEPTH_LOG of xpm_fifo_base_inst : label is 4;
  attribute WR_PNTR_WIDTH : integer;
  attribute WR_PNTR_WIDTH of xpm_fifo_base_inst : label is 4;
  attribute WR_RD_RATIO : integer;
  attribute WR_RD_RATIO of xpm_fifo_base_inst : label is 0;
  attribute WR_WIDTH_LOG : integer;
  attribute WR_WIDTH_LOG of xpm_fifo_base_inst : label is 4;
  attribute XPM_MODULE of xpm_fifo_base_inst : label is "TRUE";
  attribute both_stages_valid : integer;
  attribute both_stages_valid of xpm_fifo_base_inst : label is 3;
  attribute invalid : integer;
  attribute invalid of xpm_fifo_base_inst : label is 0;
  attribute stage1_valid : integer;
  attribute stage1_valid of xpm_fifo_base_inst : label is 2;
  attribute stage2_valid : integer;
  attribute stage2_valid of xpm_fifo_base_inst : label is 1;
begin
  almost_empty <= \<const0>\;
  almost_full <= \<const0>\;
  data_valid <= \<const0>\;
  dbiterr <= \<const0>\;
  full <= \<const0>\;
  overflow <= \<const0>\;
  prog_empty <= \<const0>\;
  prog_full <= \<const0>\;
  rd_data_count(4) <= \<const0>\;
  rd_data_count(3) <= \<const0>\;
  rd_data_count(2) <= \<const0>\;
  rd_data_count(1) <= \<const0>\;
  rd_data_count(0) <= \<const0>\;
  rd_rst_busy <= \<const0>\;
  sbiterr <= \<const0>\;
  underflow <= \<const0>\;
  wr_ack <= \<const0>\;
  wr_data_count(4) <= \<const0>\;
  wr_data_count(3) <= \<const0>\;
  wr_data_count(2) <= \<const0>\;
  wr_data_count(1) <= \<const0>\;
  wr_data_count(0) <= \<const0>\;
  wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_fifo_base_inst: entity work.\design_1_Vsp_core_0_0_xpm_fifo_base__4\
     port map (
      almost_empty => NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED,
      almost_full => NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED,
      data_valid => NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED,
      dbiterr => NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED,
      din(11 downto 0) => din(11 downto 0),
      dout(11 downto 0) => dout(11 downto 0),
      empty => empty,
      full => NLW_xpm_fifo_base_inst_full_UNCONNECTED,
      full_n => NLW_xpm_fifo_base_inst_full_n_UNCONNECTED,
      injectdbiterr => '0',
      injectsbiterr => '0',
      overflow => NLW_xpm_fifo_base_inst_overflow_UNCONNECTED,
      prog_empty => NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED,
      prog_full => NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED,
      rd_clk => wr_clk,
      rd_data_count(4 downto 0) => NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED(4 downto 0),
      rd_en => rd_en,
      rd_rst_busy => NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED,
      rst => rst,
      sbiterr => NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED,
      sleep => '0',
      underflow => NLW_xpm_fifo_base_inst_underflow_UNCONNECTED,
      wr_ack => NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED,
      wr_clk => '0',
      wr_data_count(4 downto 0) => NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED(4 downto 0),
      wr_en => wr_en,
      wr_rst_busy => NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ is
  port (
    sleep : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 11 downto 0 );
    full : out STD_LOGIC;
    prog_full : out STD_LOGIC;
    wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    overflow : out STD_LOGIC;
    wr_rst_busy : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
    empty : out STD_LOGIC;
    prog_empty : out STD_LOGIC;
    rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    underflow : out STD_LOGIC;
    rd_rst_busy : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    data_valid : out STD_LOGIC;
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC
  );
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 0;
  attribute DOUT_RESET_VALUE : string;
  attribute DOUT_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is "0";
  attribute ECC_MODE : string;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is "no_ecc";
  attribute EN_ADV_FEATURE_SYNC : string;
  attribute EN_ADV_FEATURE_SYNC of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is "16'b0000011100000111";
  attribute EN_SIM_ASSERT_ERR : string;
  attribute EN_SIM_ASSERT_ERR of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is "warning";
  attribute FIFO_MEMORY_TYPE : string;
  attribute FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is "distributed";
  attribute FIFO_READ_LATENCY : integer;
  attribute FIFO_READ_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 1;
  attribute FIFO_WRITE_DEPTH : integer;
  attribute FIFO_WRITE_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 16;
  attribute FULL_RESET_VALUE : integer;
  attribute FULL_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is "xpm_fifo_sync";
  attribute PROG_EMPTY_THRESH : integer;
  attribute PROG_EMPTY_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 5;
  attribute PROG_FULL_THRESH : integer;
  attribute PROG_FULL_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 11;
  attribute P_COMMON_CLOCK : integer;
  attribute P_COMMON_CLOCK of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 1;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 0;
  attribute P_FIFO_MEMORY_TYPE : integer;
  attribute P_FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 1;
  attribute P_READ_MODE : integer;
  attribute P_READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 2;
  attribute RD_DATA_COUNT_WIDTH : integer;
  attribute RD_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 5;
  attribute READ_DATA_WIDTH : integer;
  attribute READ_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 12;
  attribute READ_MODE : string;
  attribute READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is "fwft";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 0;
  attribute USE_ADV_FEATURES : string;
  attribute USE_ADV_FEATURES of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is "0707";
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 0;
  attribute WRITE_DATA_WIDTH : integer;
  attribute WRITE_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 12;
  attribute WR_DATA_COUNT_WIDTH : integer;
  attribute WR_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is 5;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ : entity is "soft";
end \design_1_Vsp_core_0_0_xpm_fifo_sync__5\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_sync__5\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_full_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_full_n_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute CASCADE_HEIGHT of xpm_fifo_base_inst : label is 0;
  attribute CDC_DEST_SYNC_FF : integer;
  attribute CDC_DEST_SYNC_FF of xpm_fifo_base_inst : label is 2;
  attribute COMMON_CLOCK : integer;
  attribute COMMON_CLOCK of xpm_fifo_base_inst : label is 1;
  attribute DOUT_RESET_VALUE of xpm_fifo_base_inst : label is "0";
  attribute ECC_MODE_integer : integer;
  attribute ECC_MODE_integer of xpm_fifo_base_inst : label is 0;
  attribute ENABLE_ECC : integer;
  attribute ENABLE_ECC of xpm_fifo_base_inst : label is 0;
  attribute EN_ADV_FEATURE : string;
  attribute EN_ADV_FEATURE of xpm_fifo_base_inst : label is "16'b0000011100000111";
  attribute EN_AE : string;
  attribute EN_AE of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_AF : string;
  attribute EN_AF of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_DVLD : string;
  attribute EN_DVLD of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_OF : string;
  attribute EN_OF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_PE : string;
  attribute EN_PE of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_PF : string;
  attribute EN_PF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_RDC : string;
  attribute EN_RDC of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_SIM_ASSERT_ERR of xpm_fifo_base_inst : label is "warning";
  attribute EN_UF : string;
  attribute EN_UF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_WACK : string;
  attribute EN_WACK of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_WDC : string;
  attribute EN_WDC of xpm_fifo_base_inst : label is "1'b1";
  attribute FG_EQ_ASYM_DOUT : string;
  attribute FG_EQ_ASYM_DOUT of xpm_fifo_base_inst : label is "1'b0";
  attribute FIFO_MEMORY_TYPE_integer : integer;
  attribute FIFO_MEMORY_TYPE_integer of xpm_fifo_base_inst : label is 1;
  attribute FIFO_MEM_TYPE : integer;
  attribute FIFO_MEM_TYPE of xpm_fifo_base_inst : label is 1;
  attribute FIFO_READ_DEPTH : integer;
  attribute FIFO_READ_DEPTH of xpm_fifo_base_inst : label is 16;
  attribute FIFO_READ_LATENCY of xpm_fifo_base_inst : label is 1;
  attribute FIFO_SIZE : integer;
  attribute FIFO_SIZE of xpm_fifo_base_inst : label is 192;
  attribute FIFO_WRITE_DEPTH of xpm_fifo_base_inst : label is 16;
  attribute FULL_RESET_VALUE of xpm_fifo_base_inst : label is 0;
  attribute FULL_RST_VAL : string;
  attribute FULL_RST_VAL of xpm_fifo_base_inst : label is "1'b0";
  attribute KEEP_HIERARCHY of xpm_fifo_base_inst : label is "soft";
  attribute PE_THRESH_ADJ : integer;
  attribute PE_THRESH_ADJ of xpm_fifo_base_inst : label is 3;
  attribute PE_THRESH_MAX : integer;
  attribute PE_THRESH_MAX of xpm_fifo_base_inst : label is 11;
  attribute PE_THRESH_MIN : integer;
  attribute PE_THRESH_MIN of xpm_fifo_base_inst : label is 5;
  attribute PF_THRESH_ADJ : integer;
  attribute PF_THRESH_ADJ of xpm_fifo_base_inst : label is 9;
  attribute PF_THRESH_MAX : integer;
  attribute PF_THRESH_MAX of xpm_fifo_base_inst : label is 11;
  attribute PF_THRESH_MIN : integer;
  attribute PF_THRESH_MIN of xpm_fifo_base_inst : label is 5;
  attribute PROG_EMPTY_THRESH of xpm_fifo_base_inst : label is 5;
  attribute PROG_FULL_THRESH of xpm_fifo_base_inst : label is 11;
  attribute RD_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 5;
  attribute RD_DC_WIDTH_EXT : integer;
  attribute RD_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 5;
  attribute RD_LATENCY : integer;
  attribute RD_LATENCY of xpm_fifo_base_inst : label is 2;
  attribute RD_MODE : integer;
  attribute RD_MODE of xpm_fifo_base_inst : label is 1;
  attribute RD_PNTR_WIDTH : integer;
  attribute RD_PNTR_WIDTH of xpm_fifo_base_inst : label is 4;
  attribute READ_DATA_WIDTH of xpm_fifo_base_inst : label is 12;
  attribute READ_MODE_integer : integer;
  attribute READ_MODE_integer of xpm_fifo_base_inst : label is 1;
  attribute READ_MODE_LL : integer;
  attribute READ_MODE_LL of xpm_fifo_base_inst : label is 1;
  attribute RELATED_CLOCKS : integer;
  attribute RELATED_CLOCKS of xpm_fifo_base_inst : label is 0;
  attribute REMOVE_WR_RD_PROT_LOGIC : integer;
  attribute REMOVE_WR_RD_PROT_LOGIC of xpm_fifo_base_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_fifo_base_inst : label is 0;
  attribute USE_ADV_FEATURES of xpm_fifo_base_inst : label is "0707";
  attribute VERSION : integer;
  attribute VERSION of xpm_fifo_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_fifo_base_inst : label is 0;
  attribute WIDTH_RATIO : integer;
  attribute WIDTH_RATIO of xpm_fifo_base_inst : label is 1;
  attribute WRITE_DATA_WIDTH of xpm_fifo_base_inst : label is 12;
  attribute WR_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 5;
  attribute WR_DC_WIDTH_EXT : integer;
  attribute WR_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 5;
  attribute WR_DEPTH_LOG : integer;
  attribute WR_DEPTH_LOG of xpm_fifo_base_inst : label is 4;
  attribute WR_PNTR_WIDTH : integer;
  attribute WR_PNTR_WIDTH of xpm_fifo_base_inst : label is 4;
  attribute WR_RD_RATIO : integer;
  attribute WR_RD_RATIO of xpm_fifo_base_inst : label is 0;
  attribute WR_WIDTH_LOG : integer;
  attribute WR_WIDTH_LOG of xpm_fifo_base_inst : label is 4;
  attribute XPM_MODULE of xpm_fifo_base_inst : label is "TRUE";
  attribute both_stages_valid : integer;
  attribute both_stages_valid of xpm_fifo_base_inst : label is 3;
  attribute invalid : integer;
  attribute invalid of xpm_fifo_base_inst : label is 0;
  attribute stage1_valid : integer;
  attribute stage1_valid of xpm_fifo_base_inst : label is 2;
  attribute stage2_valid : integer;
  attribute stage2_valid of xpm_fifo_base_inst : label is 1;
begin
  almost_empty <= \<const0>\;
  almost_full <= \<const0>\;
  data_valid <= \<const0>\;
  dbiterr <= \<const0>\;
  full <= \<const0>\;
  overflow <= \<const0>\;
  prog_empty <= \<const0>\;
  prog_full <= \<const0>\;
  rd_data_count(4) <= \<const0>\;
  rd_data_count(3) <= \<const0>\;
  rd_data_count(2) <= \<const0>\;
  rd_data_count(1) <= \<const0>\;
  rd_data_count(0) <= \<const0>\;
  rd_rst_busy <= \<const0>\;
  sbiterr <= \<const0>\;
  underflow <= \<const0>\;
  wr_ack <= \<const0>\;
  wr_data_count(4) <= \<const0>\;
  wr_data_count(3) <= \<const0>\;
  wr_data_count(2) <= \<const0>\;
  wr_data_count(1) <= \<const0>\;
  wr_data_count(0) <= \<const0>\;
  wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_fifo_base_inst: entity work.\design_1_Vsp_core_0_0_xpm_fifo_base__5\
     port map (
      almost_empty => NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED,
      almost_full => NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED,
      data_valid => NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED,
      dbiterr => NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED,
      din(11 downto 0) => din(11 downto 0),
      dout(11 downto 0) => dout(11 downto 0),
      empty => empty,
      full => NLW_xpm_fifo_base_inst_full_UNCONNECTED,
      full_n => NLW_xpm_fifo_base_inst_full_n_UNCONNECTED,
      injectdbiterr => '0',
      injectsbiterr => '0',
      overflow => NLW_xpm_fifo_base_inst_overflow_UNCONNECTED,
      prog_empty => NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED,
      prog_full => NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED,
      rd_clk => wr_clk,
      rd_data_count(4 downto 0) => NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED(4 downto 0),
      rd_en => rd_en,
      rd_rst_busy => NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED,
      rst => rst,
      sbiterr => NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED,
      sleep => '0',
      underflow => NLW_xpm_fifo_base_inst_underflow_UNCONNECTED,
      wr_ack => NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED,
      wr_clk => '0',
      wr_data_count(4 downto 0) => NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED(4 downto 0),
      wr_en => wr_en,
      wr_rst_busy => NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ is
  port (
    sleep : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 11 downto 0 );
    full : out STD_LOGIC;
    prog_full : out STD_LOGIC;
    wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    overflow : out STD_LOGIC;
    wr_rst_busy : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
    empty : out STD_LOGIC;
    prog_empty : out STD_LOGIC;
    rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    underflow : out STD_LOGIC;
    rd_rst_busy : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    data_valid : out STD_LOGIC;
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC
  );
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 0;
  attribute DOUT_RESET_VALUE : string;
  attribute DOUT_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is "0";
  attribute ECC_MODE : string;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is "no_ecc";
  attribute EN_ADV_FEATURE_SYNC : string;
  attribute EN_ADV_FEATURE_SYNC of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is "16'b0000011100000111";
  attribute EN_SIM_ASSERT_ERR : string;
  attribute EN_SIM_ASSERT_ERR of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is "warning";
  attribute FIFO_MEMORY_TYPE : string;
  attribute FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is "distributed";
  attribute FIFO_READ_LATENCY : integer;
  attribute FIFO_READ_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 1;
  attribute FIFO_WRITE_DEPTH : integer;
  attribute FIFO_WRITE_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 16;
  attribute FULL_RESET_VALUE : integer;
  attribute FULL_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is "xpm_fifo_sync";
  attribute PROG_EMPTY_THRESH : integer;
  attribute PROG_EMPTY_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 5;
  attribute PROG_FULL_THRESH : integer;
  attribute PROG_FULL_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 11;
  attribute P_COMMON_CLOCK : integer;
  attribute P_COMMON_CLOCK of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 1;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 0;
  attribute P_FIFO_MEMORY_TYPE : integer;
  attribute P_FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 1;
  attribute P_READ_MODE : integer;
  attribute P_READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 2;
  attribute RD_DATA_COUNT_WIDTH : integer;
  attribute RD_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 5;
  attribute READ_DATA_WIDTH : integer;
  attribute READ_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 12;
  attribute READ_MODE : string;
  attribute READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is "fwft";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 0;
  attribute USE_ADV_FEATURES : string;
  attribute USE_ADV_FEATURES of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is "0707";
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 0;
  attribute WRITE_DATA_WIDTH : integer;
  attribute WRITE_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 12;
  attribute WR_DATA_COUNT_WIDTH : integer;
  attribute WR_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is 5;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ : entity is "soft";
end \design_1_Vsp_core_0_0_xpm_fifo_sync__6\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_sync__6\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_full_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_full_n_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute CASCADE_HEIGHT of xpm_fifo_base_inst : label is 0;
  attribute CDC_DEST_SYNC_FF : integer;
  attribute CDC_DEST_SYNC_FF of xpm_fifo_base_inst : label is 2;
  attribute COMMON_CLOCK : integer;
  attribute COMMON_CLOCK of xpm_fifo_base_inst : label is 1;
  attribute DOUT_RESET_VALUE of xpm_fifo_base_inst : label is "0";
  attribute ECC_MODE_integer : integer;
  attribute ECC_MODE_integer of xpm_fifo_base_inst : label is 0;
  attribute ENABLE_ECC : integer;
  attribute ENABLE_ECC of xpm_fifo_base_inst : label is 0;
  attribute EN_ADV_FEATURE : string;
  attribute EN_ADV_FEATURE of xpm_fifo_base_inst : label is "16'b0000011100000111";
  attribute EN_AE : string;
  attribute EN_AE of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_AF : string;
  attribute EN_AF of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_DVLD : string;
  attribute EN_DVLD of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_OF : string;
  attribute EN_OF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_PE : string;
  attribute EN_PE of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_PF : string;
  attribute EN_PF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_RDC : string;
  attribute EN_RDC of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_SIM_ASSERT_ERR of xpm_fifo_base_inst : label is "warning";
  attribute EN_UF : string;
  attribute EN_UF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_WACK : string;
  attribute EN_WACK of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_WDC : string;
  attribute EN_WDC of xpm_fifo_base_inst : label is "1'b1";
  attribute FG_EQ_ASYM_DOUT : string;
  attribute FG_EQ_ASYM_DOUT of xpm_fifo_base_inst : label is "1'b0";
  attribute FIFO_MEMORY_TYPE_integer : integer;
  attribute FIFO_MEMORY_TYPE_integer of xpm_fifo_base_inst : label is 1;
  attribute FIFO_MEM_TYPE : integer;
  attribute FIFO_MEM_TYPE of xpm_fifo_base_inst : label is 1;
  attribute FIFO_READ_DEPTH : integer;
  attribute FIFO_READ_DEPTH of xpm_fifo_base_inst : label is 16;
  attribute FIFO_READ_LATENCY of xpm_fifo_base_inst : label is 1;
  attribute FIFO_SIZE : integer;
  attribute FIFO_SIZE of xpm_fifo_base_inst : label is 192;
  attribute FIFO_WRITE_DEPTH of xpm_fifo_base_inst : label is 16;
  attribute FULL_RESET_VALUE of xpm_fifo_base_inst : label is 0;
  attribute FULL_RST_VAL : string;
  attribute FULL_RST_VAL of xpm_fifo_base_inst : label is "1'b0";
  attribute KEEP_HIERARCHY of xpm_fifo_base_inst : label is "soft";
  attribute PE_THRESH_ADJ : integer;
  attribute PE_THRESH_ADJ of xpm_fifo_base_inst : label is 3;
  attribute PE_THRESH_MAX : integer;
  attribute PE_THRESH_MAX of xpm_fifo_base_inst : label is 11;
  attribute PE_THRESH_MIN : integer;
  attribute PE_THRESH_MIN of xpm_fifo_base_inst : label is 5;
  attribute PF_THRESH_ADJ : integer;
  attribute PF_THRESH_ADJ of xpm_fifo_base_inst : label is 9;
  attribute PF_THRESH_MAX : integer;
  attribute PF_THRESH_MAX of xpm_fifo_base_inst : label is 11;
  attribute PF_THRESH_MIN : integer;
  attribute PF_THRESH_MIN of xpm_fifo_base_inst : label is 5;
  attribute PROG_EMPTY_THRESH of xpm_fifo_base_inst : label is 5;
  attribute PROG_FULL_THRESH of xpm_fifo_base_inst : label is 11;
  attribute RD_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 5;
  attribute RD_DC_WIDTH_EXT : integer;
  attribute RD_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 5;
  attribute RD_LATENCY : integer;
  attribute RD_LATENCY of xpm_fifo_base_inst : label is 2;
  attribute RD_MODE : integer;
  attribute RD_MODE of xpm_fifo_base_inst : label is 1;
  attribute RD_PNTR_WIDTH : integer;
  attribute RD_PNTR_WIDTH of xpm_fifo_base_inst : label is 4;
  attribute READ_DATA_WIDTH of xpm_fifo_base_inst : label is 12;
  attribute READ_MODE_integer : integer;
  attribute READ_MODE_integer of xpm_fifo_base_inst : label is 1;
  attribute READ_MODE_LL : integer;
  attribute READ_MODE_LL of xpm_fifo_base_inst : label is 1;
  attribute RELATED_CLOCKS : integer;
  attribute RELATED_CLOCKS of xpm_fifo_base_inst : label is 0;
  attribute REMOVE_WR_RD_PROT_LOGIC : integer;
  attribute REMOVE_WR_RD_PROT_LOGIC of xpm_fifo_base_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_fifo_base_inst : label is 0;
  attribute USE_ADV_FEATURES of xpm_fifo_base_inst : label is "0707";
  attribute VERSION : integer;
  attribute VERSION of xpm_fifo_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_fifo_base_inst : label is 0;
  attribute WIDTH_RATIO : integer;
  attribute WIDTH_RATIO of xpm_fifo_base_inst : label is 1;
  attribute WRITE_DATA_WIDTH of xpm_fifo_base_inst : label is 12;
  attribute WR_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 5;
  attribute WR_DC_WIDTH_EXT : integer;
  attribute WR_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 5;
  attribute WR_DEPTH_LOG : integer;
  attribute WR_DEPTH_LOG of xpm_fifo_base_inst : label is 4;
  attribute WR_PNTR_WIDTH : integer;
  attribute WR_PNTR_WIDTH of xpm_fifo_base_inst : label is 4;
  attribute WR_RD_RATIO : integer;
  attribute WR_RD_RATIO of xpm_fifo_base_inst : label is 0;
  attribute WR_WIDTH_LOG : integer;
  attribute WR_WIDTH_LOG of xpm_fifo_base_inst : label is 4;
  attribute XPM_MODULE of xpm_fifo_base_inst : label is "TRUE";
  attribute both_stages_valid : integer;
  attribute both_stages_valid of xpm_fifo_base_inst : label is 3;
  attribute invalid : integer;
  attribute invalid of xpm_fifo_base_inst : label is 0;
  attribute stage1_valid : integer;
  attribute stage1_valid of xpm_fifo_base_inst : label is 2;
  attribute stage2_valid : integer;
  attribute stage2_valid of xpm_fifo_base_inst : label is 1;
begin
  almost_empty <= \<const0>\;
  almost_full <= \<const0>\;
  data_valid <= \<const0>\;
  dbiterr <= \<const0>\;
  full <= \<const0>\;
  overflow <= \<const0>\;
  prog_empty <= \<const0>\;
  prog_full <= \<const0>\;
  rd_data_count(4) <= \<const0>\;
  rd_data_count(3) <= \<const0>\;
  rd_data_count(2) <= \<const0>\;
  rd_data_count(1) <= \<const0>\;
  rd_data_count(0) <= \<const0>\;
  rd_rst_busy <= \<const0>\;
  sbiterr <= \<const0>\;
  underflow <= \<const0>\;
  wr_ack <= \<const0>\;
  wr_data_count(4) <= \<const0>\;
  wr_data_count(3) <= \<const0>\;
  wr_data_count(2) <= \<const0>\;
  wr_data_count(1) <= \<const0>\;
  wr_data_count(0) <= \<const0>\;
  wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_fifo_base_inst: entity work.\design_1_Vsp_core_0_0_xpm_fifo_base__6\
     port map (
      almost_empty => NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED,
      almost_full => NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED,
      data_valid => NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED,
      dbiterr => NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED,
      din(11 downto 0) => din(11 downto 0),
      dout(11 downto 0) => dout(11 downto 0),
      empty => empty,
      full => NLW_xpm_fifo_base_inst_full_UNCONNECTED,
      full_n => NLW_xpm_fifo_base_inst_full_n_UNCONNECTED,
      injectdbiterr => '0',
      injectsbiterr => '0',
      overflow => NLW_xpm_fifo_base_inst_overflow_UNCONNECTED,
      prog_empty => NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED,
      prog_full => NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED,
      rd_clk => wr_clk,
      rd_data_count(4 downto 0) => NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED(4 downto 0),
      rd_en => rd_en,
      rd_rst_busy => NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED,
      rst => rst,
      sbiterr => NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED,
      sleep => '0',
      underflow => NLW_xpm_fifo_base_inst_underflow_UNCONNECTED,
      wr_ack => NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED,
      wr_clk => '0',
      wr_data_count(4 downto 0) => NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED(4 downto 0),
      wr_en => wr_en,
      wr_rst_busy => NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ is
  port (
    sleep : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 67 downto 0 );
    full : out STD_LOGIC;
    prog_full : out STD_LOGIC;
    wr_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
    overflow : out STD_LOGIC;
    wr_rst_busy : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 67 downto 0 );
    empty : out STD_LOGIC;
    prog_empty : out STD_LOGIC;
    rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
    underflow : out STD_LOGIC;
    rd_rst_busy : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    data_valid : out STD_LOGIC;
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC
  );
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 0;
  attribute DOUT_RESET_VALUE : string;
  attribute DOUT_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is "0";
  attribute ECC_MODE : string;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is "no_ecc";
  attribute EN_ADV_FEATURE_SYNC : string;
  attribute EN_ADV_FEATURE_SYNC of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is "16'b0000111100001111";
  attribute EN_SIM_ASSERT_ERR : string;
  attribute EN_SIM_ASSERT_ERR of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is "warning";
  attribute FIFO_MEMORY_TYPE : string;
  attribute FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is "block";
  attribute FIFO_READ_LATENCY : integer;
  attribute FIFO_READ_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 1;
  attribute FIFO_WRITE_DEPTH : integer;
  attribute FIFO_WRITE_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 2048;
  attribute FULL_RESET_VALUE : integer;
  attribute FULL_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is "xpm_fifo_sync";
  attribute PROG_EMPTY_THRESH : integer;
  attribute PROG_EMPTY_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 10;
  attribute PROG_FULL_THRESH : integer;
  attribute PROG_FULL_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 2043;
  attribute P_COMMON_CLOCK : integer;
  attribute P_COMMON_CLOCK of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 1;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 0;
  attribute P_FIFO_MEMORY_TYPE : integer;
  attribute P_FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 2;
  attribute P_READ_MODE : integer;
  attribute P_READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 1;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 2;
  attribute RD_DATA_COUNT_WIDTH : integer;
  attribute RD_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 1;
  attribute READ_DATA_WIDTH : integer;
  attribute READ_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 68;
  attribute READ_MODE : string;
  attribute READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is "fwft";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 0;
  attribute USE_ADV_FEATURES : string;
  attribute USE_ADV_FEATURES of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is "0f0f";
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 0;
  attribute WRITE_DATA_WIDTH : integer;
  attribute WRITE_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 68;
  attribute WR_DATA_COUNT_WIDTH : integer;
  attribute WR_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ : entity is "soft";
end \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_sync__parameterized0\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_full_n_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute CASCADE_HEIGHT of xpm_fifo_base_inst : label is 0;
  attribute CDC_DEST_SYNC_FF : integer;
  attribute CDC_DEST_SYNC_FF of xpm_fifo_base_inst : label is 2;
  attribute COMMON_CLOCK : integer;
  attribute COMMON_CLOCK of xpm_fifo_base_inst : label is 1;
  attribute DOUT_RESET_VALUE of xpm_fifo_base_inst : label is "0";
  attribute ECC_MODE_integer : integer;
  attribute ECC_MODE_integer of xpm_fifo_base_inst : label is 0;
  attribute ENABLE_ECC : integer;
  attribute ENABLE_ECC of xpm_fifo_base_inst : label is 0;
  attribute EN_ADV_FEATURE : string;
  attribute EN_ADV_FEATURE of xpm_fifo_base_inst : label is "16'b0000111100001111";
  attribute EN_AE : string;
  attribute EN_AE of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_AF : string;
  attribute EN_AF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_DVLD : string;
  attribute EN_DVLD of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_OF : string;
  attribute EN_OF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_PE : string;
  attribute EN_PE of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_PF : string;
  attribute EN_PF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_RDC : string;
  attribute EN_RDC of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_SIM_ASSERT_ERR of xpm_fifo_base_inst : label is "warning";
  attribute EN_UF : string;
  attribute EN_UF of xpm_fifo_base_inst : label is "1'b1";
  attribute EN_WACK : string;
  attribute EN_WACK of xpm_fifo_base_inst : label is "1'b0";
  attribute EN_WDC : string;
  attribute EN_WDC of xpm_fifo_base_inst : label is "1'b1";
  attribute FG_EQ_ASYM_DOUT : string;
  attribute FG_EQ_ASYM_DOUT of xpm_fifo_base_inst : label is "1'b0";
  attribute FIFO_MEMORY_TYPE_integer : integer;
  attribute FIFO_MEMORY_TYPE_integer of xpm_fifo_base_inst : label is 2;
  attribute FIFO_MEM_TYPE : integer;
  attribute FIFO_MEM_TYPE of xpm_fifo_base_inst : label is 2;
  attribute FIFO_READ_DEPTH : integer;
  attribute FIFO_READ_DEPTH of xpm_fifo_base_inst : label is 2048;
  attribute FIFO_READ_LATENCY of xpm_fifo_base_inst : label is 1;
  attribute FIFO_SIZE : integer;
  attribute FIFO_SIZE of xpm_fifo_base_inst : label is 139264;
  attribute FIFO_WRITE_DEPTH of xpm_fifo_base_inst : label is 2048;
  attribute FULL_RESET_VALUE of xpm_fifo_base_inst : label is 0;
  attribute FULL_RST_VAL : string;
  attribute FULL_RST_VAL of xpm_fifo_base_inst : label is "1'b0";
  attribute KEEP_HIERARCHY of xpm_fifo_base_inst : label is "soft";
  attribute PE_THRESH_ADJ : integer;
  attribute PE_THRESH_ADJ of xpm_fifo_base_inst : label is 8;
  attribute PE_THRESH_MAX : integer;
  attribute PE_THRESH_MAX of xpm_fifo_base_inst : label is 2043;
  attribute PE_THRESH_MIN : integer;
  attribute PE_THRESH_MIN of xpm_fifo_base_inst : label is 5;
  attribute PF_THRESH_ADJ : integer;
  attribute PF_THRESH_ADJ of xpm_fifo_base_inst : label is 2041;
  attribute PF_THRESH_MAX : integer;
  attribute PF_THRESH_MAX of xpm_fifo_base_inst : label is 2043;
  attribute PF_THRESH_MIN : integer;
  attribute PF_THRESH_MIN of xpm_fifo_base_inst : label is 5;
  attribute PROG_EMPTY_THRESH of xpm_fifo_base_inst : label is 10;
  attribute PROG_FULL_THRESH of xpm_fifo_base_inst : label is 2043;
  attribute RD_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 1;
  attribute RD_DC_WIDTH_EXT : integer;
  attribute RD_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 12;
  attribute RD_LATENCY : integer;
  attribute RD_LATENCY of xpm_fifo_base_inst : label is 2;
  attribute RD_MODE : integer;
  attribute RD_MODE of xpm_fifo_base_inst : label is 1;
  attribute RD_PNTR_WIDTH : integer;
  attribute RD_PNTR_WIDTH of xpm_fifo_base_inst : label is 11;
  attribute READ_DATA_WIDTH of xpm_fifo_base_inst : label is 68;
  attribute READ_MODE_integer : integer;
  attribute READ_MODE_integer of xpm_fifo_base_inst : label is 1;
  attribute READ_MODE_LL : integer;
  attribute READ_MODE_LL of xpm_fifo_base_inst : label is 1;
  attribute RELATED_CLOCKS : integer;
  attribute RELATED_CLOCKS of xpm_fifo_base_inst : label is 0;
  attribute REMOVE_WR_RD_PROT_LOGIC : integer;
  attribute REMOVE_WR_RD_PROT_LOGIC of xpm_fifo_base_inst : label is 0;
  attribute SIM_ASSERT_CHK of xpm_fifo_base_inst : label is 0;
  attribute USE_ADV_FEATURES of xpm_fifo_base_inst : label is "0f0f";
  attribute VERSION : integer;
  attribute VERSION of xpm_fifo_base_inst : label is 0;
  attribute WAKEUP_TIME of xpm_fifo_base_inst : label is 0;
  attribute WIDTH_RATIO : integer;
  attribute WIDTH_RATIO of xpm_fifo_base_inst : label is 1;
  attribute WRITE_DATA_WIDTH of xpm_fifo_base_inst : label is 68;
  attribute WR_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 1;
  attribute WR_DC_WIDTH_EXT : integer;
  attribute WR_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 12;
  attribute WR_DEPTH_LOG : integer;
  attribute WR_DEPTH_LOG of xpm_fifo_base_inst : label is 11;
  attribute WR_PNTR_WIDTH : integer;
  attribute WR_PNTR_WIDTH of xpm_fifo_base_inst : label is 11;
  attribute WR_RD_RATIO : integer;
  attribute WR_RD_RATIO of xpm_fifo_base_inst : label is 0;
  attribute WR_WIDTH_LOG : integer;
  attribute WR_WIDTH_LOG of xpm_fifo_base_inst : label is 7;
  attribute XPM_MODULE of xpm_fifo_base_inst : label is "TRUE";
  attribute both_stages_valid : integer;
  attribute both_stages_valid of xpm_fifo_base_inst : label is 3;
  attribute invalid : integer;
  attribute invalid of xpm_fifo_base_inst : label is 0;
  attribute stage1_valid : integer;
  attribute stage1_valid of xpm_fifo_base_inst : label is 2;
  attribute stage2_valid : integer;
  attribute stage2_valid of xpm_fifo_base_inst : label is 1;
begin
  almost_empty <= \<const0>\;
  data_valid <= \<const0>\;
  dbiterr <= \<const0>\;
  overflow <= \<const0>\;
  prog_empty <= \<const0>\;
  prog_full <= \<const0>\;
  rd_data_count(0) <= \<const0>\;
  rd_rst_busy <= \<const0>\;
  sbiterr <= \<const0>\;
  underflow <= \<const0>\;
  wr_ack <= \<const0>\;
  wr_data_count(0) <= \<const0>\;
  wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
xpm_fifo_base_inst: entity work.\design_1_Vsp_core_0_0_xpm_fifo_base__parameterized0\
     port map (
      almost_empty => NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED,
      almost_full => almost_full,
      data_valid => NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED,
      dbiterr => NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED,
      din(67 downto 0) => din(67 downto 0),
      dout(67 downto 0) => dout(67 downto 0),
      empty => empty,
      full => full,
      full_n => NLW_xpm_fifo_base_inst_full_n_UNCONNECTED,
      injectdbiterr => '0',
      injectsbiterr => '0',
      overflow => NLW_xpm_fifo_base_inst_overflow_UNCONNECTED,
      prog_empty => NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED,
      prog_full => NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED,
      rd_clk => wr_clk,
      rd_data_count(0) => NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED(0),
      rd_en => rd_en,
      rd_rst_busy => NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED,
      rst => rst,
      sbiterr => NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED,
      sleep => '0',
      underflow => NLW_xpm_fifo_base_inst_underflow_UNCONNECTED,
      wr_ack => NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED,
      wr_clk => '0',
      wr_data_count(0) => NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED(0),
      wr_en => wr_en,
      wr_rst_busy => NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED
    );
end STRUCTURE;
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`protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256400)
`protect data_block
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`protect end_protected
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2024.2"
`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
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`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
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`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_hssio_wiz_top is
  port (
    lp_rx_o_n : out STD_LOGIC_VECTOR ( 4 downto 0 );
    lp_rx_o_p : out STD_LOGIC_VECTOR ( 4 downto 0 );
    fifo_wr_clk_0 : out STD_LOGIC;
    fifo_empty_2 : out STD_LOGIC;
    data_to_fabric_data_rxp0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fifo_empty_4 : out STD_LOGIC;
    data_to_fabric_data_rxp1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fifo_empty_6 : out STD_LOGIC;
    data_to_fabric_data_rxp2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fifo_empty_8 : out STD_LOGIC;
    data_to_fabric_data_rxp3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    rst_seq_done : out STD_LOGIC;
    hs_rx_disable : in STD_LOGIC_VECTOR ( 4 downto 0 );
    clk_rxp : in STD_LOGIC;
    clk_rxn : in STD_LOGIC;
    data_rxp0 : in STD_LOGIC;
    data_rxn0 : in STD_LOGIC;
    data_rxp1 : in STD_LOGIC;
    data_rxn1 : in STD_LOGIC;
    data_rxp2 : in STD_LOGIC;
    data_rxn2 : in STD_LOGIC;
    data_rxp3 : in STD_LOGIC;
    data_rxn3 : in STD_LOGIC;
    fifo_rd_clk_0 : in STD_LOGIC;
    fifo_rd_en_2 : in STD_LOGIC;
    fifo_rd_en_4 : in STD_LOGIC;
    fifo_rd_en_6 : in STD_LOGIC;
    fifo_rd_en_8 : in STD_LOGIC;
    riu_clk : in STD_LOGIC;
    rst : in STD_LOGIC;
    bs_rst_dphy_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_hssio_wiz_top : entity is "bd_7289_phy_0_hssio_rx_hssio_wiz_top";
end design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_hssio_wiz_top;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_hssio_wiz_top is
  signal all_bsc_dly_rdy_in : STD_LOGIC;
  signal bs_ctrl_top_inst_n_0 : STD_LOGIC;
  signal bs_ctrl_top_inst_n_1 : STD_LOGIC;
  signal bs_ctrl_top_inst_n_2 : STD_LOGIC;
  signal bs_ctrl_top_inst_n_3 : STD_LOGIC;
  signal bs_rst : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal bsctrl_rst : STD_LOGIC;
  signal clk_rst_top_inst_n_10 : STD_LOGIC;
  signal clk_rst_top_inst_n_15 : STD_LOGIC;
  signal core_rdy : STD_LOGIC;
  signal core_rdy_r : STD_LOGIC_VECTOR ( 51 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of core_rdy_r : signal is "true";
  signal data_to_bs : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal n0_en_vtc : STD_LOGIC;
  signal n0_rx_bit_ctrl_in0 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_rx_bit_ctrl_in2 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_rx_bit_ctrl_in4 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_rx_bit_ctrl_out0 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_rx_bit_ctrl_out2 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_rx_bit_ctrl_out4 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_tbyte_d : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute RTL_KEEP of n0_tbyte_d : signal is "true";
  signal n0_tx_bit_ctrl_in0 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_tx_bit_ctrl_in2 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_tx_bit_ctrl_in4 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_tx_bit_ctrl_out0 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_tx_bit_ctrl_out2 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n0_tx_bit_ctrl_out4 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_rx_bit_ctrl_in0 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_rx_bit_ctrl_in2 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_rx_bit_ctrl_out0 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_rx_bit_ctrl_out2 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_tbyte_d : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute RTL_KEEP of n1_tbyte_d : signal is "true";
  signal n1_tx_bit_ctrl_in0 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_tx_bit_ctrl_in2 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_tx_bit_ctrl_out0 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n1_tx_bit_ctrl_out2 : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal n2_tbyte_d : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute RTL_KEEP of n2_tbyte_d : signal is "true";
  signal n3_tbyte_d : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute RTL_KEEP of n3_tbyte_d : signal is "true";
  signal n4_tbyte_d : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute RTL_KEEP of n4_tbyte_d : signal is "true";
  signal n5_tbyte_d : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute RTL_KEEP of n5_tbyte_d : signal is "true";
  signal n6_tbyte_d : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute RTL_KEEP of n6_tbyte_d : signal is "true";
  signal n7_tbyte_d : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute RTL_KEEP of n7_tbyte_d : signal is "true";
  signal rst_dly : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \rst_scheme_inst/hssio_state\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal rst_seq_done1 : STD_LOGIC;
  attribute RTL_KEEP of rst_seq_done1 : signal is "true";
  signal rst_seq_done2 : STD_LOGIC;
  attribute RTL_KEEP of rst_seq_done2 : signal is "true";
  signal rst_seq_done3 : STD_LOGIC;
  attribute RTL_KEEP of rst_seq_done3 : signal is "true";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \CORE_RDY_GEN[10].core_rdy_r_reg[10]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[11].core_rdy_r_reg[11]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[12].core_rdy_r_reg[12]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[13].core_rdy_r_reg[13]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[14].core_rdy_r_reg[14]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[15].core_rdy_r_reg[15]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[16].core_rdy_r_reg[16]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[17].core_rdy_r_reg[17]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[18].core_rdy_r_reg[18]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[19].core_rdy_r_reg[19]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[1].core_rdy_r_reg[1]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[20].core_rdy_r_reg[20]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[21].core_rdy_r_reg[21]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[22].core_rdy_r_reg[22]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[23].core_rdy_r_reg[23]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[24].core_rdy_r_reg[24]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[25].core_rdy_r_reg[25]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[26].core_rdy_r_reg[26]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[27].core_rdy_r_reg[27]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[28].core_rdy_r_reg[28]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[29].core_rdy_r_reg[29]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[2].core_rdy_r_reg[2]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[30].core_rdy_r_reg[30]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[31].core_rdy_r_reg[31]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[32].core_rdy_r_reg[32]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[33].core_rdy_r_reg[33]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[34].core_rdy_r_reg[34]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[35].core_rdy_r_reg[35]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[36].core_rdy_r_reg[36]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[37].core_rdy_r_reg[37]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[38].core_rdy_r_reg[38]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[39].core_rdy_r_reg[39]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[3].core_rdy_r_reg[3]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[40].core_rdy_r_reg[40]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[41].core_rdy_r_reg[41]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[42].core_rdy_r_reg[42]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[43].core_rdy_r_reg[43]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[44].core_rdy_r_reg[44]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[45].core_rdy_r_reg[45]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[46].core_rdy_r_reg[46]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[47].core_rdy_r_reg[47]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[48].core_rdy_r_reg[48]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[49].core_rdy_r_reg[49]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[4].core_rdy_r_reg[4]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[50].core_rdy_r_reg[50]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[51].core_rdy_r_reg[51]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[5].core_rdy_r_reg[5]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[6].core_rdy_r_reg[6]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[7].core_rdy_r_reg[7]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[8].core_rdy_r_reg[8]\ : label is "no";
  attribute equivalent_register_removal of \CORE_RDY_GEN[9].core_rdy_r_reg[9]\ : label is "no";
  attribute KEEP : string;
  attribute KEEP of \GEN_NIB0_TBYTE.n0_tbyte_d_reg[0]\ : label is "yes";
  attribute KEEP of \GEN_NIB0_TBYTE.n0_tbyte_d_reg[1]\ : label is "yes";
  attribute KEEP of \GEN_NIB0_TBYTE.n0_tbyte_d_reg[2]\ : label is "yes";
  attribute KEEP of \GEN_NIB0_TBYTE.n0_tbyte_d_reg[3]\ : label is "yes";
  attribute KEEP of \GEN_NIB1_TBYTE.n1_tbyte_d_reg[0]\ : label is "yes";
  attribute KEEP of \GEN_NIB1_TBYTE.n1_tbyte_d_reg[1]\ : label is "yes";
  attribute KEEP of \GEN_NIB1_TBYTE.n1_tbyte_d_reg[2]\ : label is "yes";
  attribute KEEP of \GEN_NIB1_TBYTE.n1_tbyte_d_reg[3]\ : label is "yes";
  attribute KEEP of \GEN_NIB2_TBYTE.n2_tbyte_d_reg[0]\ : label is "yes";
  attribute KEEP of \GEN_NIB2_TBYTE.n2_tbyte_d_reg[1]\ : label is "yes";
  attribute KEEP of \GEN_NIB2_TBYTE.n2_tbyte_d_reg[2]\ : label is "yes";
  attribute KEEP of \GEN_NIB2_TBYTE.n2_tbyte_d_reg[3]\ : label is "yes";
  attribute KEEP of \GEN_NIB3_TBYTE.n3_tbyte_d_reg[0]\ : label is "yes";
  attribute KEEP of \GEN_NIB3_TBYTE.n3_tbyte_d_reg[1]\ : label is "yes";
  attribute KEEP of \GEN_NIB3_TBYTE.n3_tbyte_d_reg[2]\ : label is "yes";
  attribute KEEP of \GEN_NIB3_TBYTE.n3_tbyte_d_reg[3]\ : label is "yes";
  attribute KEEP of \GEN_NIB4_TBYTE.n4_tbyte_d_reg[0]\ : label is "yes";
  attribute KEEP of \GEN_NIB4_TBYTE.n4_tbyte_d_reg[1]\ : label is "yes";
  attribute KEEP of \GEN_NIB4_TBYTE.n4_tbyte_d_reg[2]\ : label is "yes";
  attribute KEEP of \GEN_NIB4_TBYTE.n4_tbyte_d_reg[3]\ : label is "yes";
  attribute KEEP of \GEN_NIB5_TBYTE.n5_tbyte_d_reg[0]\ : label is "yes";
  attribute KEEP of \GEN_NIB5_TBYTE.n5_tbyte_d_reg[1]\ : label is "yes";
  attribute KEEP of \GEN_NIB5_TBYTE.n5_tbyte_d_reg[2]\ : label is "yes";
  attribute KEEP of \GEN_NIB5_TBYTE.n5_tbyte_d_reg[3]\ : label is "yes";
  attribute KEEP of \GEN_NIB6_TBYTE.n6_tbyte_d_reg[0]\ : label is "yes";
  attribute KEEP of \GEN_NIB6_TBYTE.n6_tbyte_d_reg[1]\ : label is "yes";
  attribute KEEP of \GEN_NIB6_TBYTE.n6_tbyte_d_reg[2]\ : label is "yes";
  attribute KEEP of \GEN_NIB6_TBYTE.n6_tbyte_d_reg[3]\ : label is "yes";
  attribute KEEP of \GEN_NIB7_TBYTE.n7_tbyte_d_reg[0]\ : label is "yes";
  attribute KEEP of \GEN_NIB7_TBYTE.n7_tbyte_d_reg[1]\ : label is "yes";
  attribute KEEP of \GEN_NIB7_TBYTE.n7_tbyte_d_reg[2]\ : label is "yes";
  attribute KEEP of \GEN_NIB7_TBYTE.n7_tbyte_d_reg[3]\ : label is "yes";
begin
  rst_seq_done <= rst_seq_done3;
\CORE_RDY_GEN[0].core_rdy_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(0),
      R => '0'
    );
\CORE_RDY_GEN[10].core_rdy_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(10),
      R => '0'
    );
\CORE_RDY_GEN[11].core_rdy_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(11),
      R => '0'
    );
\CORE_RDY_GEN[12].core_rdy_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(12),
      R => '0'
    );
\CORE_RDY_GEN[13].core_rdy_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(13),
      R => '0'
    );
\CORE_RDY_GEN[14].core_rdy_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(14),
      R => '0'
    );
\CORE_RDY_GEN[15].core_rdy_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(15),
      R => '0'
    );
\CORE_RDY_GEN[16].core_rdy_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(16),
      R => '0'
    );
\CORE_RDY_GEN[17].core_rdy_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(17),
      R => '0'
    );
\CORE_RDY_GEN[18].core_rdy_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(18),
      R => '0'
    );
\CORE_RDY_GEN[19].core_rdy_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(19),
      R => '0'
    );
\CORE_RDY_GEN[1].core_rdy_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(1),
      R => '0'
    );
\CORE_RDY_GEN[20].core_rdy_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(20),
      R => '0'
    );
\CORE_RDY_GEN[21].core_rdy_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(21),
      R => '0'
    );
\CORE_RDY_GEN[22].core_rdy_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(22),
      R => '0'
    );
\CORE_RDY_GEN[23].core_rdy_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(23),
      R => '0'
    );
\CORE_RDY_GEN[24].core_rdy_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(24),
      R => '0'
    );
\CORE_RDY_GEN[25].core_rdy_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(25),
      R => '0'
    );
\CORE_RDY_GEN[26].core_rdy_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(26),
      R => '0'
    );
\CORE_RDY_GEN[27].core_rdy_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(27),
      R => '0'
    );
\CORE_RDY_GEN[28].core_rdy_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(28),
      R => '0'
    );
\CORE_RDY_GEN[29].core_rdy_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(29),
      R => '0'
    );
\CORE_RDY_GEN[2].core_rdy_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(2),
      R => '0'
    );
\CORE_RDY_GEN[30].core_rdy_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(30),
      R => '0'
    );
\CORE_RDY_GEN[31].core_rdy_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(31),
      R => '0'
    );
\CORE_RDY_GEN[32].core_rdy_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(32),
      R => '0'
    );
\CORE_RDY_GEN[33].core_rdy_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(33),
      R => '0'
    );
\CORE_RDY_GEN[34].core_rdy_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(34),
      R => '0'
    );
\CORE_RDY_GEN[35].core_rdy_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(35),
      R => '0'
    );
\CORE_RDY_GEN[36].core_rdy_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(36),
      R => '0'
    );
\CORE_RDY_GEN[37].core_rdy_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(37),
      R => '0'
    );
\CORE_RDY_GEN[38].core_rdy_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(38),
      R => '0'
    );
\CORE_RDY_GEN[39].core_rdy_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(39),
      R => '0'
    );
\CORE_RDY_GEN[3].core_rdy_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(3),
      R => '0'
    );
\CORE_RDY_GEN[40].core_rdy_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(40),
      R => '0'
    );
\CORE_RDY_GEN[41].core_rdy_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(41),
      R => '0'
    );
\CORE_RDY_GEN[42].core_rdy_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(42),
      R => '0'
    );
\CORE_RDY_GEN[43].core_rdy_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(43),
      R => '0'
    );
\CORE_RDY_GEN[44].core_rdy_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(44),
      R => '0'
    );
\CORE_RDY_GEN[45].core_rdy_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(45),
      R => '0'
    );
\CORE_RDY_GEN[46].core_rdy_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(46),
      R => '0'
    );
\CORE_RDY_GEN[47].core_rdy_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(47),
      R => '0'
    );
\CORE_RDY_GEN[48].core_rdy_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(48),
      R => '0'
    );
\CORE_RDY_GEN[49].core_rdy_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(49),
      R => '0'
    );
\CORE_RDY_GEN[4].core_rdy_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(4),
      R => '0'
    );
\CORE_RDY_GEN[50].core_rdy_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(50),
      R => '0'
    );
\CORE_RDY_GEN[51].core_rdy_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(51),
      R => '0'
    );
\CORE_RDY_GEN[5].core_rdy_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(5),
      R => '0'
    );
\CORE_RDY_GEN[6].core_rdy_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(6),
      R => '0'
    );
\CORE_RDY_GEN[7].core_rdy_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(7),
      R => '0'
    );
\CORE_RDY_GEN[8].core_rdy_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(8),
      R => '0'
    );
\CORE_RDY_GEN[9].core_rdy_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => riu_clk,
      CE => '1',
      D => core_rdy,
      Q => core_rdy_r(9),
      R => '0'
    );
\GEN_NIB0_TBYTE.n0_tbyte_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n0_tbyte_d(0),
      R => '0'
    );
\GEN_NIB0_TBYTE.n0_tbyte_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n0_tbyte_d(1),
      R => '0'
    );
\GEN_NIB0_TBYTE.n0_tbyte_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n0_tbyte_d(2),
      R => '0'
    );
\GEN_NIB0_TBYTE.n0_tbyte_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n0_tbyte_d(3),
      R => '0'
    );
\GEN_NIB1_TBYTE.n1_tbyte_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n1_tbyte_d(0),
      R => '0'
    );
\GEN_NIB1_TBYTE.n1_tbyte_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n1_tbyte_d(1),
      R => '0'
    );
\GEN_NIB1_TBYTE.n1_tbyte_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n1_tbyte_d(2),
      R => '0'
    );
\GEN_NIB1_TBYTE.n1_tbyte_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n1_tbyte_d(3),
      R => '0'
    );
\GEN_NIB2_TBYTE.n2_tbyte_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n2_tbyte_d(0),
      R => '0'
    );
\GEN_NIB2_TBYTE.n2_tbyte_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n2_tbyte_d(1),
      R => '0'
    );
\GEN_NIB2_TBYTE.n2_tbyte_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n2_tbyte_d(2),
      R => '0'
    );
\GEN_NIB2_TBYTE.n2_tbyte_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n2_tbyte_d(3),
      R => '0'
    );
\GEN_NIB3_TBYTE.n3_tbyte_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n3_tbyte_d(0),
      R => '0'
    );
\GEN_NIB3_TBYTE.n3_tbyte_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n3_tbyte_d(1),
      R => '0'
    );
\GEN_NIB3_TBYTE.n3_tbyte_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n3_tbyte_d(2),
      R => '0'
    );
\GEN_NIB3_TBYTE.n3_tbyte_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n3_tbyte_d(3),
      R => '0'
    );
\GEN_NIB4_TBYTE.n4_tbyte_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n4_tbyte_d(0),
      R => '0'
    );
\GEN_NIB4_TBYTE.n4_tbyte_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n4_tbyte_d(1),
      R => '0'
    );
\GEN_NIB4_TBYTE.n4_tbyte_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n4_tbyte_d(2),
      R => '0'
    );
\GEN_NIB4_TBYTE.n4_tbyte_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n4_tbyte_d(3),
      R => '0'
    );
\GEN_NIB5_TBYTE.n5_tbyte_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n5_tbyte_d(0),
      R => '0'
    );
\GEN_NIB5_TBYTE.n5_tbyte_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n5_tbyte_d(1),
      R => '0'
    );
\GEN_NIB5_TBYTE.n5_tbyte_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n5_tbyte_d(2),
      R => '0'
    );
\GEN_NIB5_TBYTE.n5_tbyte_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n5_tbyte_d(3),
      R => '0'
    );
\GEN_NIB6_TBYTE.n6_tbyte_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n6_tbyte_d(0),
      R => '0'
    );
\GEN_NIB6_TBYTE.n6_tbyte_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n6_tbyte_d(1),
      R => '0'
    );
\GEN_NIB6_TBYTE.n6_tbyte_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n6_tbyte_d(2),
      R => '0'
    );
\GEN_NIB6_TBYTE.n6_tbyte_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n6_tbyte_d(3),
      R => '0'
    );
\GEN_NIB7_TBYTE.n7_tbyte_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n7_tbyte_d(0),
      R => '0'
    );
\GEN_NIB7_TBYTE.n7_tbyte_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n7_tbyte_d(1),
      R => '0'
    );
\GEN_NIB7_TBYTE.n7_tbyte_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n7_tbyte_d(2),
      R => '0'
    );
\GEN_NIB7_TBYTE.n7_tbyte_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk_rst_top_inst_n_10,
      CE => '1',
      D => '0',
      Q => n7_tbyte_d(3),
      R => '0'
    );
bs_ctrl_top_inst: entity work.design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_bs_ctrl_top
     port map (
      \BITSLICE_CTRL[1].bs_ctrl_inst_0\ => bs_ctrl_top_inst_n_0,
      \GEN_RIU_NOT_FROM_PLL.hssio_state_reg[7]\ => bs_ctrl_top_inst_n_3,
      Q(0) => \rst_scheme_inst/hssio_state\(7),
      bsctrl_rst => bsctrl_rst,
      core_rdy => core_rdy,
      in0(0) => all_bsc_dly_rdy_in,
      n0_rx_bit_ctrl_out0(39 downto 0) => n0_rx_bit_ctrl_out0(39 downto 0),
      n0_rx_bit_ctrl_out2(39 downto 0) => n0_rx_bit_ctrl_out2(39 downto 0),
      n0_rx_bit_ctrl_out4(39 downto 0) => n0_rx_bit_ctrl_out4(39 downto 0),
      n0_tbyte_in(3 downto 0) => n0_tbyte_d(3 downto 0),
      n0_tx_bit_ctrl_out0(39 downto 0) => n0_tx_bit_ctrl_out0(39 downto 0),
      n0_tx_bit_ctrl_out2(39 downto 0) => n0_tx_bit_ctrl_out2(39 downto 0),
      n0_tx_bit_ctrl_out4(39 downto 0) => n0_tx_bit_ctrl_out4(39 downto 0),
      n0_vtc_rdy_out => bs_ctrl_top_inst_n_2,
      n1_en_vtc_in => n0_en_vtc,
      n1_rx_bit_ctrl_out0(39 downto 0) => n1_rx_bit_ctrl_out0(39 downto 0),
      n1_rx_bit_ctrl_out2(39 downto 0) => n1_rx_bit_ctrl_out2(39 downto 0),
      n1_tbyte_in(3 downto 0) => n1_tbyte_d(3 downto 0),
      n1_tx_bit_ctrl_out0(39 downto 0) => n1_tx_bit_ctrl_out0(39 downto 0),
      n1_tx_bit_ctrl_out2(39 downto 0) => n1_tx_bit_ctrl_out2(39 downto 0),
      n1_vtc_rdy_out => bs_ctrl_top_inst_n_1,
      pll0_clkoutphy_out => clk_rst_top_inst_n_15,
      riu_clk => riu_clk,
      rx_bs0_rx_bit_ctrl_out(39 downto 0) => n0_rx_bit_ctrl_in0(39 downto 0),
      rx_bs0_tx_bit_ctrl_out(39 downto 0) => n0_tx_bit_ctrl_in0(39 downto 0),
      rx_bs2_rx_bit_ctrl_out(39 downto 0) => n0_rx_bit_ctrl_in2(39 downto 0),
      rx_bs2_tx_bit_ctrl_out(39 downto 0) => n0_tx_bit_ctrl_in2(39 downto 0),
      rx_bs4_rx_bit_ctrl_out(39 downto 0) => n0_rx_bit_ctrl_in4(39 downto 0),
      rx_bs4_tx_bit_ctrl_out(39 downto 0) => n0_tx_bit_ctrl_in4(39 downto 0),
      rx_bs6_rx_bit_ctrl_out(39 downto 0) => n1_rx_bit_ctrl_in0(39 downto 0),
      rx_bs6_tx_bit_ctrl_out(39 downto 0) => n1_tx_bit_ctrl_in0(39 downto 0),
      rx_bs8_rx_bit_ctrl_out(39 downto 0) => n1_rx_bit_ctrl_in2(39 downto 0),
      rx_bs8_tx_bit_ctrl_out(39 downto 0) => n1_tx_bit_ctrl_in2(39 downto 0)
    );
bs_top_inst: entity work.design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_bs_top
     port map (
      data_to_bs_out(4) => data_to_bs(8),
      data_to_bs_out(3) => data_to_bs(6),
      data_to_bs_out(2) => data_to_bs(4),
      data_to_bs_out(1) => data_to_bs(2),
      data_to_bs_out(0) => data_to_bs(0),
      data_to_fabric_data_rxp0(7 downto 0) => data_to_fabric_data_rxp0(7 downto 0),
      data_to_fabric_data_rxp1(7 downto 0) => data_to_fabric_data_rxp1(7 downto 0),
      data_to_fabric_data_rxp2(7 downto 0) => data_to_fabric_data_rxp2(7 downto 0),
      data_to_fabric_data_rxp3(7 downto 0) => data_to_fabric_data_rxp3(7 downto 0),
      fifo_empty_2 => fifo_empty_2,
      fifo_empty_4 => fifo_empty_4,
      fifo_empty_6 => fifo_empty_6,
      fifo_empty_8 => fifo_empty_8,
      fifo_rd_clk_0 => fifo_rd_clk_0,
      fifo_rd_en_2 => fifo_rd_en_2,
      fifo_rd_en_4 => fifo_rd_en_4,
      fifo_rd_en_6 => fifo_rd_en_6,
      fifo_rd_en_8 => fifo_rd_en_8,
      fifo_wr_clk_0 => fifo_wr_clk_0,
      rx_bs0_rx_bit_ctrl_in(39 downto 0) => n0_rx_bit_ctrl_out0(39 downto 0),
      rx_bs0_rx_bit_ctrl_out(39 downto 0) => n0_rx_bit_ctrl_in0(39 downto 0),
      rx_bs0_tx_bit_ctrl_in(39 downto 0) => n0_tx_bit_ctrl_out0(39 downto 0),
      rx_bs0_tx_bit_ctrl_out(39 downto 0) => n0_tx_bit_ctrl_in0(39 downto 0),
      rx_bs2_rx_bit_ctrl_in(39 downto 0) => n0_rx_bit_ctrl_out2(39 downto 0),
      rx_bs2_rx_bit_ctrl_out(39 downto 0) => n0_rx_bit_ctrl_in2(39 downto 0),
      rx_bs2_tx_bit_ctrl_in(39 downto 0) => n0_tx_bit_ctrl_out2(39 downto 0),
      rx_bs2_tx_bit_ctrl_out(39 downto 0) => n0_tx_bit_ctrl_in2(39 downto 0),
      rx_bs4_rx_bit_ctrl_in(39 downto 0) => n0_rx_bit_ctrl_out4(39 downto 0),
      rx_bs4_rx_bit_ctrl_out(39 downto 0) => n0_rx_bit_ctrl_in4(39 downto 0),
      rx_bs4_tx_bit_ctrl_in(39 downto 0) => n0_tx_bit_ctrl_out4(39 downto 0),
      rx_bs4_tx_bit_ctrl_out(39 downto 0) => n0_tx_bit_ctrl_in4(39 downto 0),
      rx_bs6_rx_bit_ctrl_in(39 downto 0) => n1_rx_bit_ctrl_out0(39 downto 0),
      rx_bs6_rx_bit_ctrl_out(39 downto 0) => n1_rx_bit_ctrl_in0(39 downto 0),
      rx_bs6_tx_bit_ctrl_in(39 downto 0) => n1_tx_bit_ctrl_out0(39 downto 0),
      rx_bs6_tx_bit_ctrl_out(39 downto 0) => n1_tx_bit_ctrl_in0(39 downto 0),
      rx_bs8_rx_bit_ctrl_in(39 downto 0) => n1_rx_bit_ctrl_out2(39 downto 0),
      rx_bs8_rx_bit_ctrl_out(39 downto 0) => n1_rx_bit_ctrl_in2(39 downto 0),
      rx_bs8_tx_bit_ctrl_in(39 downto 0) => n1_tx_bit_ctrl_out2(39 downto 0),
      rx_bs8_tx_bit_ctrl_out(39 downto 0) => n1_tx_bit_ctrl_in2(39 downto 0),
      rx_bs_rst_dly_ext_in(4) => rst_dly(8),
      rx_bs_rst_dly_ext_in(3) => rst_dly(6),
      rx_bs_rst_dly_ext_in(2) => rst_dly(4),
      rx_bs_rst_dly_ext_in(1) => rst_dly(2),
      rx_bs_rst_dly_ext_in(0) => rst_dly(0),
      rx_bs_rst_in(4) => bs_rst(8),
      rx_bs_rst_in(3) => bs_rst(6),
      rx_bs_rst_in(2) => bs_rst(4),
      rx_bs_rst_in(1) => bs_rst(2),
      rx_bs_rst_in(0) => bs_rst(0)
    );
clk_rst_top_inst: entity work.design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_clk_rst_top
     port map (
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg\ => bs_ctrl_top_inst_n_0,
      \GEN_RIU_NOT_FROM_PLL.timeout_cntr_rst_reg_0\ => bs_ctrl_top_inst_n_3,
      Q(0) => \rst_scheme_inst/hssio_state\(7),
      bs_rst_dphy_in => bs_rst_dphy_in,
      \bs_rst_int_r_reg[8]\(4) => bs_rst(8),
      \bs_rst_int_r_reg[8]\(3) => bs_rst(6),
      \bs_rst_int_r_reg[8]\(2) => bs_rst(4),
      \bs_rst_int_r_reg[8]\(1) => bs_rst(2),
      \bs_rst_int_r_reg[8]\(0) => bs_rst(0),
      bsctrl_rst => bsctrl_rst,
      in0(0) => all_bsc_dly_rdy_in,
      n0_vtc_rdy_out => bs_ctrl_top_inst_n_2,
      n1_en_vtc_in => n0_en_vtc,
      n1_vtc_rdy_out => bs_ctrl_top_inst_n_1,
      \out\(4) => rst_dly(8),
      \out\(3) => rst_dly(6),
      \out\(2) => rst_dly(4),
      \out\(1) => rst_dly(2),
      \out\(0) => rst_dly(0),
      pll0_clkout0_out => clk_rst_top_inst_n_10,
      pll0_clkoutphy_out => clk_rst_top_inst_n_15,
      riu_clk => riu_clk,
      rst => rst,
      rst_seq_done3 => rst_seq_done3
    );
iobuf_top_inst: entity work.design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_mipi_iobuf_rx
     port map (
      data_from_pins(9) => data_rxn3,
      data_from_pins(8) => data_rxp3,
      data_from_pins(7) => data_rxn2,
      data_from_pins(6) => data_rxp2,
      data_from_pins(5) => data_rxn1,
      data_from_pins(4) => data_rxp1,
      data_from_pins(3) => data_rxn0,
      data_from_pins(2) => data_rxp0,
      data_from_pins(1) => clk_rxn,
      data_from_pins(0) => clk_rxp,
      data_to_bs_out(4) => data_to_bs(8),
      data_to_bs_out(3) => data_to_bs(6),
      data_to_bs_out(2) => data_to_bs(4),
      data_to_bs_out(1) => data_to_bs(2),
      data_to_bs_out(0) => data_to_bs(0),
      hs_rx_disable(4 downto 0) => hs_rx_disable(4 downto 0),
      lp_rx_o_n(4 downto 0) => lp_rx_o_n(4 downto 0),
      lp_rx_o_p(4 downto 0) => lp_rx_o_p(4 downto 0)
    );
rst_seq_done1_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rst_seq_done3,
      O => rst_seq_done1
    );
rst_seq_done2_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rst_seq_done3,
      O => rst_seq_done2
    );
sync_cell_rst_seq_pll0_inst: entity work.design_1_Vsp_core_0_0_high_speed_selectio_wiz_v3_6_10_sync_cell
     port map (
      CLK => clk_rst_top_inst_n_10,
      \out\ => rst_seq_done1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_r_sync_0 is
  port (
    slowest_sync_clk : in STD_LOGIC;
    ext_reset_in : in STD_LOGIC;
    aux_reset_in : in STD_LOGIC;
    mb_debug_sys_rst : in STD_LOGIC;
    dcm_locked : in STD_LOGIC;
    mb_reset : out STD_LOGIC;
    bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
    peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
    interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
    peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_Vsp_core_0_0_bd_7289_r_sync_0 : entity is "bd_7289_r_sync_0,proc_sys_reset,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_r_sync_0 : entity is "bd_7289_r_sync_0";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_bd_7289_r_sync_0 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of design_1_Vsp_core_0_0_bd_7289_r_sync_0 : entity is "proc_sys_reset,Vivado 2024.2";
end design_1_Vsp_core_0_0_bd_7289_r_sync_0;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_r_sync_0 is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_mb_reset_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_peripheral_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute C_AUX_RESET_HIGH : string;
  attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
  attribute C_AUX_RST_WIDTH : integer;
  attribute C_AUX_RST_WIDTH of U0 : label is 4;
  attribute C_EXT_RESET_HIGH : string;
  attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
  attribute C_EXT_RST_WIDTH : integer;
  attribute C_EXT_RST_WIDTH of U0 : label is 4;
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_NUM_BUS_RST : integer;
  attribute C_NUM_BUS_RST of U0 : label is 1;
  attribute C_NUM_INTERCONNECT_ARESETN : integer;
  attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
  attribute C_NUM_PERP_ARESETN : integer;
  attribute C_NUM_PERP_ARESETN of U0 : label is 1;
  attribute C_NUM_PERP_RST : integer;
  attribute C_NUM_PERP_RST of U0 : label is 1;
  attribute x_interface_info : string;
  attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
  attribute x_interface_mode : string;
  attribute x_interface_mode of aux_reset_in : signal is "slave aux_reset";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST";
  attribute x_interface_mode of ext_reset_in : signal is "slave ext_reset";
  attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST";
  attribute x_interface_mode of mb_debug_sys_rst : signal is "slave dbg_reset";
  attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
  attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
  attribute x_interface_mode of mb_reset : signal is "master mb_rst";
  attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
  attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
  attribute x_interface_mode of slowest_sync_clk : signal is "slave clock";
  attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_7289_dphy_clk_200M, INSERT_VIP 0";
  attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
  attribute x_interface_mode of bus_struct_reset : signal is "master bus_struct_reset";
  attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
  attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
  attribute x_interface_mode of interconnect_aresetn : signal is "master interconnect_low_rst";
  attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
  attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
  attribute x_interface_mode of peripheral_aresetn : signal is "master peripheral_low_rst";
  attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
  attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
  attribute x_interface_mode of peripheral_reset : signal is "master peripheral_high_rst";
  attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
begin
  bus_struct_reset(0) <= \<const0>\;
  interconnect_aresetn(0) <= \<const0>\;
  mb_reset <= \<const0>\;
  peripheral_aresetn(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.design_1_Vsp_core_0_0_proc_sys_reset
     port map (
      aux_reset_in => '1',
      bus_struct_reset(0) => NLW_U0_bus_struct_reset_UNCONNECTED(0),
      dcm_locked => '1',
      ext_reset_in => ext_reset_in,
      interconnect_aresetn(0) => NLW_U0_interconnect_aresetn_UNCONNECTED(0),
      mb_debug_sys_rst => '0',
      mb_reset => NLW_U0_mb_reset_UNCONNECTED,
      peripheral_aresetn(0) => NLW_U0_peripheral_aresetn_UNCONNECTED(0),
      peripheral_reset(0) => peripheral_reset(0),
      slowest_sync_clk => slowest_sync_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_vfb_0_0_axis_dconverter is
  port (
    s_axis_tready : out STD_LOGIC;
    m_axis_tvalid : out STD_LOGIC;
    \r1_data_reg[19]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_tlast : out STD_LOGIC;
    m_axis_tid : out STD_LOGIC_VECTOR ( 5 downto 0 );
    D : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \state_reg[1]\ : out STD_LOGIC;
    \state_reg[0]\ : out STD_LOGIC;
    \state_reg[1]_0\ : out STD_LOGIC;
    \state_reg[1]_1\ : out STD_LOGIC;
    vfb_clk : in STD_LOGIC;
    vfb_arstn : in STD_LOGIC;
    s_fifo_tv : in STD_LOGIC;
    \r0_data_reg[59]\ : in STD_LOGIC_VECTOR ( 47 downto 0 );
    s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axis_tlast : in STD_LOGIC;
    \r0_id_reg[9]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
    \vfb_data_reg[4]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \vfb_data_reg[23]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    vfb_sof119_out : in STD_LOGIC;
    cur_dtype_udef : in STD_LOGIC;
    \sband_tu_r[0]_i_2\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_vfb_0_0_axis_dconverter : entity is "bd_7289_vfb_0_0_axis_dconverter";
end design_1_Vsp_core_0_0_bd_7289_vfb_0_0_axis_dconverter;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_vfb_0_0_axis_dconverter is
  signal m_axis_tdata : STD_LOGIC_VECTOR ( 27 downto 4 );
  signal m_axis_tuser : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^m_axis_tvalid\ : STD_LOGIC;
  signal \^s_axis_tready\ : STD_LOGIC;
  signal \^state_reg[1]\ : STD_LOGIC;
  signal \vfb_data[23]_i_4_n_0\ : STD_LOGIC;
  signal NLW_axis_conv_inst_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 12 );
  signal NLW_axis_conv_inst_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_axis_conv_inst_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_axis_conv_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_axis_conv_inst_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 75 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \TUSR0.vfb_sof[69]_i_5\ : label is "soft_lutpair544";
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of axis_conv_inst : label is "bd_7289_vfb_0_0_axis_converter,axis_dwidth_converter_v1_1_32_axis_dwidth_converter,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of axis_conv_inst : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of axis_conv_inst : label is "axis_dwidth_converter_v1_1_32_axis_dwidth_converter,Vivado 2024.2";
  attribute SOFT_HLUTNM of \buf_valid[1]_i_3\ : label is "soft_lutpair545";
  attribute SOFT_HLUTNM of \vfb_data[23]_i_4\ : label is "soft_lutpair544";
  attribute SOFT_HLUTNM of \vfb_sof[0]_i_3\ : label is "soft_lutpair545";
begin
  m_axis_tvalid <= \^m_axis_tvalid\;
  s_axis_tready <= \^s_axis_tready\;
  \state_reg[1]\ <= \^state_reg[1]\;
\REQ_BUFFER_RAW12.buff_tv_i_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^s_axis_tready\,
      I1 => s_fifo_tv,
      O => \state_reg[0]\
    );
\TUSR0.vfb_sof[69]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => vfb_arstn,
      I1 => \^m_axis_tvalid\,
      O => \^state_reg[1]\
    );
axis_conv_inst: entity work.design_1_Vsp_core_0_0_bd_7289_vfb_0_0_axis_converter
     port map (
      aclk => vfb_clk,
      aresetn => vfb_arstn,
      m_axis_tdata(31 downto 28) => NLW_axis_conv_inst_m_axis_tdata_UNCONNECTED(31 downto 28),
      m_axis_tdata(27 downto 20) => m_axis_tdata(27 downto 20),
      m_axis_tdata(19 downto 16) => \r1_data_reg[19]\(7 downto 4),
      m_axis_tdata(15 downto 12) => NLW_axis_conv_inst_m_axis_tdata_UNCONNECTED(15 downto 12),
      m_axis_tdata(11 downto 4) => m_axis_tdata(11 downto 4),
      m_axis_tdata(3 downto 0) => \r1_data_reg[19]\(3 downto 0),
      m_axis_tdest(31 downto 0) => NLW_axis_conv_inst_m_axis_tdest_UNCONNECTED(31 downto 0),
      m_axis_tid(31 downto 10) => NLW_axis_conv_inst_m_axis_tid_UNCONNECTED(31 downto 10),
      m_axis_tid(9 downto 4) => m_axis_tid(5 downto 0),
      m_axis_tid(3 downto 0) => NLW_axis_conv_inst_m_axis_tid_UNCONNECTED(3 downto 0),
      m_axis_tkeep(3 downto 0) => NLW_axis_conv_inst_m_axis_tkeep_UNCONNECTED(3 downto 0),
      m_axis_tlast => m_axis_tlast,
      m_axis_tready => '1',
      m_axis_tuser(75 downto 1) => NLW_axis_conv_inst_m_axis_tuser_UNCONNECTED(75 downto 1),
      m_axis_tuser(0) => m_axis_tuser(0),
      m_axis_tvalid => \^m_axis_tvalid\,
      s_axis_tdata(63 downto 60) => B"0000",
      s_axis_tdata(59 downto 48) => \r0_data_reg[59]\(47 downto 36),
      s_axis_tdata(47 downto 44) => B"0000",
      s_axis_tdata(43 downto 32) => \r0_data_reg[59]\(35 downto 24),
      s_axis_tdata(31 downto 28) => B"0000",
      s_axis_tdata(27 downto 16) => \r0_data_reg[59]\(23 downto 12),
      s_axis_tdata(15 downto 12) => B"0000",
      s_axis_tdata(11 downto 0) => \r0_data_reg[59]\(11 downto 0),
      s_axis_tdest(31 downto 0) => B"00000000000000000000000000000000",
      s_axis_tid(31 downto 10) => B"0000000000000000000000",
      s_axis_tid(9 downto 4) => \r0_id_reg[9]\(5 downto 0),
      s_axis_tid(3 downto 0) => B"0000",
      s_axis_tkeep(7) => s_axis_tkeep(0),
      s_axis_tkeep(6 downto 0) => B"0000000",
      s_axis_tlast => s_axis_tlast,
      s_axis_tready => \^s_axis_tready\,
      s_axis_tuser(151 downto 20) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axis_tuser(19) => s_axis_tuser(0),
      s_axis_tuser(18 downto 0) => B"0000000000000000000",
      s_axis_tvalid => s_fifo_tv
    );
\buf_valid[1]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^m_axis_tvalid\,
      I1 => cur_dtype_udef,
      I2 => \sband_tu_r[0]_i_2\,
      O => \state_reg[1]_0\
    );
\vfb_data[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(6),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(6),
      I4 => m_axis_tdata(10),
      I5 => \^state_reg[1]\,
      O => D(6)
    );
\vfb_data[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(7),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(7),
      I4 => m_axis_tdata(11),
      I5 => \^state_reg[1]\,
      O => D(7)
    );
\vfb_data[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(8),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(8),
      I4 => m_axis_tdata(20),
      I5 => \^state_reg[1]\,
      O => D(8)
    );
\vfb_data[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(9),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(9),
      I4 => m_axis_tdata(21),
      I5 => \^state_reg[1]\,
      O => D(9)
    );
\vfb_data[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(10),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(10),
      I4 => m_axis_tdata(22),
      I5 => \^state_reg[1]\,
      O => D(10)
    );
\vfb_data[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(11),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(11),
      I4 => m_axis_tdata(23),
      I5 => \^state_reg[1]\,
      O => D(11)
    );
\vfb_data[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(12),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(12),
      I4 => m_axis_tdata(24),
      I5 => \^state_reg[1]\,
      O => D(12)
    );
\vfb_data[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(13),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(13),
      I4 => m_axis_tdata(25),
      I5 => \^state_reg[1]\,
      O => D(13)
    );
\vfb_data[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(14),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(14),
      I4 => m_axis_tdata(26),
      I5 => \^state_reg[1]\,
      O => D(14)
    );
\vfb_data[23]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(15),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(15),
      I4 => m_axis_tdata(27),
      I5 => \^state_reg[1]\,
      O => D(15)
    );
\vfb_data[23]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \^m_axis_tvalid\,
      I1 => vfb_arstn,
      I2 => vfb_sof119_out,
      O => \vfb_data[23]_i_4_n_0\
    );
\vfb_data[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(0),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(0),
      I4 => m_axis_tdata(4),
      I5 => \^state_reg[1]\,
      O => D(0)
    );
\vfb_data[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(1),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(1),
      I4 => m_axis_tdata(5),
      I5 => \^state_reg[1]\,
      O => D(1)
    );
\vfb_data[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(2),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(2),
      I4 => m_axis_tdata(6),
      I5 => \^state_reg[1]\,
      O => D(2)
    );
\vfb_data[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(3),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(3),
      I4 => m_axis_tdata(7),
      I5 => \^state_reg[1]\,
      O => D(3)
    );
\vfb_data[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(4),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(4),
      I4 => m_axis_tdata(8),
      I5 => \^state_reg[1]\,
      O => D(4)
    );
\vfb_data[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \vfb_data_reg[4]\,
      I1 => Q(5),
      I2 => \vfb_data[23]_i_4_n_0\,
      I3 => \vfb_data_reg[23]\(5),
      I4 => m_axis_tdata(9),
      I5 => \^state_reg[1]\,
      O => D(5)
    );
\vfb_sof[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => m_axis_tuser(0),
      I1 => \^m_axis_tvalid\,
      O => \state_reg[1]_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_xbar_0 is
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
    s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
    s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axi_awaddr : out STD_LOGIC_VECTOR ( 25 downto 0 );
    m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
    m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_araddr : out STD_LOGIC_VECTOR ( 25 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
    m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_Vsp_core_0_0_bd_7289_xbar_0 : entity is "bd_7289_xbar_0,axi_crossbar_v2_1_34_axi_crossbar,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_xbar_0 : entity is "bd_7289_xbar_0";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_bd_7289_xbar_0 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of design_1_Vsp_core_0_0_bd_7289_xbar_0 : entity is "axi_crossbar_v2_1_34_axi_crossbar,Vivado 2024.2";
end design_1_Vsp_core_0_0_bd_7289_xbar_0;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_xbar_0 is
  signal \<const0>\ : STD_LOGIC;
  signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  attribute x_interface_info : string;
  attribute x_interface_info of aclk : signal is "xilinx.com:signal:clock:1.0 CLKIF CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of aclk : signal is "slave";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of aclk : signal is "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_7289_lite_aclk, INSERT_VIP 0";
  attribute x_interface_info of aresetn : signal is "xilinx.com:signal:reset:1.0 RSTIF RST";
  attribute x_interface_mode of aresetn : signal is "slave";
  attribute x_interface_parameter of aresetn : signal is "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT";
  attribute x_interface_info of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [12:0] [12:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [12:0] [25:13]";
  attribute x_interface_info of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]";
  attribute x_interface_info of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]";
  attribute x_interface_info of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]";
  attribute x_interface_info of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [12:0] [12:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [12:0] [25:13]";
  attribute x_interface_mode of m_axi_awaddr : signal is "master M01_AXI";
  attribute x_interface_parameter of m_axi_awaddr : signal is "XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 13, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN bd_7289_lite_aclk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute x_interface_info of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]";
  attribute x_interface_info of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]";
  attribute x_interface_info of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]";
  attribute x_interface_info of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]";
  attribute x_interface_info of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]";
  attribute x_interface_info of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]";
  attribute x_interface_info of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]";
  attribute x_interface_info of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]";
  attribute x_interface_info of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]";
  attribute x_interface_info of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]";
  attribute x_interface_info of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]";
  attribute x_interface_info of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]";
  attribute x_interface_info of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]";
  attribute x_interface_info of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]";
  attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
  attribute x_interface_info of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
  attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
  attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
  attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
  attribute x_interface_mode of s_axi_awaddr : signal is "slave";
  attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 13, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN bd_7289_lite_aclk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute x_interface_info of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
  attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
  attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
  attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
  attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
  attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
  attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
  attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
  attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
  attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
  attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
  attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
  attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
  attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
begin
  \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
  m_axi_araddr(25) <= \<const0>\;
  m_axi_araddr(24) <= \<const0>\;
  m_axi_araddr(23) <= \<const0>\;
  m_axi_araddr(22) <= \<const0>\;
  m_axi_araddr(21) <= \<const0>\;
  m_axi_araddr(20) <= \<const0>\;
  m_axi_araddr(19 downto 15) <= \^m_axi_araddr\(6 downto 2);
  m_axi_araddr(14) <= \<const0>\;
  m_axi_araddr(13) <= \<const0>\;
  m_axi_araddr(12) <= \<const0>\;
  m_axi_araddr(11) <= \<const0>\;
  m_axi_araddr(10) <= \<const0>\;
  m_axi_araddr(9) <= \<const0>\;
  m_axi_araddr(8) <= \<const0>\;
  m_axi_araddr(7 downto 2) <= \^m_axi_araddr\(7 downto 2);
  m_axi_araddr(1) <= \<const0>\;
  m_axi_araddr(0) <= \<const0>\;
  m_axi_arprot(5) <= \<const0>\;
  m_axi_arprot(4) <= \<const0>\;
  m_axi_arprot(3) <= \<const0>\;
  m_axi_arprot(2) <= \<const0>\;
  m_axi_arprot(1) <= \<const0>\;
  m_axi_arprot(0) <= \<const0>\;
  m_axi_awaddr(25) <= \<const0>\;
  m_axi_awaddr(24) <= \<const0>\;
  m_axi_awaddr(23) <= \<const0>\;
  m_axi_awaddr(22) <= \<const0>\;
  m_axi_awaddr(21) <= \<const0>\;
  m_axi_awaddr(20) <= \<const0>\;
  m_axi_awaddr(19 downto 15) <= \^m_axi_araddr\(6 downto 2);
  m_axi_awaddr(14) <= \<const0>\;
  m_axi_awaddr(13) <= \<const0>\;
  m_axi_awaddr(12) <= \<const0>\;
  m_axi_awaddr(11) <= \<const0>\;
  m_axi_awaddr(10) <= \<const0>\;
  m_axi_awaddr(9) <= \<const0>\;
  m_axi_awaddr(8) <= \<const0>\;
  m_axi_awaddr(7 downto 2) <= \^m_axi_araddr\(7 downto 2);
  m_axi_awaddr(1) <= \<const0>\;
  m_axi_awaddr(0) <= \<const0>\;
  m_axi_awprot(5) <= \<const0>\;
  m_axi_awprot(4) <= \<const0>\;
  m_axi_awprot(3) <= \<const0>\;
  m_axi_awprot(2) <= \<const0>\;
  m_axi_awprot(1) <= \<const0>\;
  m_axi_awprot(0) <= \<const0>\;
  m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
  m_axi_wdata(31 downto 27) <= \^s_axi_wdata\(31 downto 27);
  m_axi_wdata(26) <= \<const0>\;
  m_axi_wdata(25) <= \<const0>\;
  m_axi_wdata(24) <= \<const0>\;
  m_axi_wdata(23 downto 0) <= \^s_axi_wdata\(23 downto 0);
  m_axi_wstrb(7) <= \<const0>\;
  m_axi_wstrb(6) <= \<const0>\;
  m_axi_wstrb(5) <= \<const0>\;
  m_axi_wstrb(4) <= \<const0>\;
  m_axi_wstrb(3) <= \<const0>\;
  m_axi_wstrb(2) <= \<const0>\;
  m_axi_wstrb(1) <= \<const0>\;
  m_axi_wstrb(0) <= \<const0>\;
  s_axi_bresp(1) <= \<const0>\;
  s_axi_bresp(0) <= \<const0>\;
  s_axi_rresp(1) <= \<const0>\;
  s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
inst: entity work.design_1_Vsp_core_0_0_axi_crossbar_v2_1_34_axi_crossbar
     port map (
      aclk => aclk,
      aresetn => aresetn,
      m_axi_araddr(5 downto 1) => \^m_axi_araddr\(6 downto 2),
      m_axi_araddr(0) => \^m_axi_araddr\(7),
      m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
      m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
      m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
      m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
      m_axi_bready(1 downto 0) => m_axi_bready(1 downto 0),
      m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0),
      m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
      m_axi_rready(1 downto 0) => m_axi_rready(1 downto 0),
      m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0),
      m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
      m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
      s_axi_araddr(6) => s_axi_araddr(12),
      s_axi_araddr(5 downto 0) => s_axi_araddr(7 downto 2),
      s_axi_arready(0) => s_axi_arready(0),
      s_axi_arvalid(0) => s_axi_arvalid(0),
      s_axi_awaddr(6) => s_axi_awaddr(12),
      s_axi_awaddr(5 downto 0) => s_axi_awaddr(7 downto 2),
      s_axi_awready(0) => s_axi_awready(0),
      s_axi_awvalid(0) => s_axi_awvalid(0),
      s_axi_bready(0) => s_axi_bready(0),
      s_axi_bvalid(0) => s_axi_bvalid(0),
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      s_axi_rready(0) => s_axi_rready(0),
      s_axi_rvalid(0) => s_axi_rvalid(0),
      s_axi_wready(0) => s_axi_wready(0),
      s_axi_wvalid(0) => s_axi_wvalid(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_xpm_fifo_async is
  port (
    sleep : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 25 downto 0 );
    full : out STD_LOGIC;
    prog_full : out STD_LOGIC;
    wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    overflow : out STD_LOGIC;
    wr_rst_busy : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    rd_clk : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 25 downto 0 );
    empty : out STD_LOGIC;
    prog_empty : out STD_LOGIC;
    rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
    underflow : out STD_LOGIC;
    rd_rst_busy : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    data_valid : out STD_LOGIC;
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC
  );
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 0;
  attribute CDC_SYNC_STAGES : integer;
  attribute CDC_SYNC_STAGES of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 2;
  attribute DOUT_RESET_VALUE : string;
  attribute DOUT_RESET_VALUE of design_1_Vsp_core_0_0_xpm_fifo_async : entity is "0";
  attribute ECC_MODE : string;
  attribute ECC_MODE of design_1_Vsp_core_0_0_xpm_fifo_async : entity is "no_ecc";
  attribute EN_ADV_FEATURE_ASYNC : string;
  attribute EN_ADV_FEATURE_ASYNC of design_1_Vsp_core_0_0_xpm_fifo_async : entity is "16'b0000011100000111";
  attribute EN_SIM_ASSERT_ERR : string;
  attribute EN_SIM_ASSERT_ERR of design_1_Vsp_core_0_0_xpm_fifo_async : entity is "warning";
  attribute FIFO_MEMORY_TYPE : string;
  attribute FIFO_MEMORY_TYPE of design_1_Vsp_core_0_0_xpm_fifo_async : entity is "distributed";
  attribute FIFO_READ_LATENCY : integer;
  attribute FIFO_READ_LATENCY of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 1;
  attribute FIFO_WRITE_DEPTH : integer;
  attribute FIFO_WRITE_DEPTH of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 32;
  attribute FULL_RESET_VALUE : integer;
  attribute FULL_RESET_VALUE of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_xpm_fifo_async : entity is "xpm_fifo_async";
  attribute PROG_EMPTY_THRESH : integer;
  attribute PROG_EMPTY_THRESH of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 10;
  attribute PROG_FULL_THRESH : integer;
  attribute PROG_FULL_THRESH of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 29;
  attribute P_COMMON_CLOCK : integer;
  attribute P_COMMON_CLOCK of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 0;
  attribute P_FIFO_MEMORY_TYPE : integer;
  attribute P_FIFO_MEMORY_TYPE of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 1;
  attribute P_READ_MODE : integer;
  attribute P_READ_MODE of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 0;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 2;
  attribute RD_DATA_COUNT_WIDTH : integer;
  attribute RD_DATA_COUNT_WIDTH of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 5;
  attribute READ_DATA_WIDTH : integer;
  attribute READ_DATA_WIDTH of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 26;
  attribute READ_MODE : string;
  attribute READ_MODE of design_1_Vsp_core_0_0_xpm_fifo_async : entity is "std";
  attribute RELATED_CLOCKS : integer;
  attribute RELATED_CLOCKS of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 0;
  attribute USE_ADV_FEATURES : string;
  attribute USE_ADV_FEATURES of design_1_Vsp_core_0_0_xpm_fifo_async : entity is "0707";
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 0;
  attribute WRITE_DATA_WIDTH : integer;
  attribute WRITE_DATA_WIDTH of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 26;
  attribute WR_DATA_COUNT_WIDTH : integer;
  attribute WR_DATA_COUNT_WIDTH of design_1_Vsp_core_0_0_xpm_fifo_async : entity is 5;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of design_1_Vsp_core_0_0_xpm_fifo_async : entity is "TRUE";
  attribute dont_touch : string;
  attribute dont_touch of design_1_Vsp_core_0_0_xpm_fifo_async : entity is "true";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of design_1_Vsp_core_0_0_xpm_fifo_async : entity is "true";
end design_1_Vsp_core_0_0_xpm_fifo_async;

architecture STRUCTURE of design_1_Vsp_core_0_0_xpm_fifo_async is
  signal \<const0>\ : STD_LOGIC;
  signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED\ : STD_LOGIC;
  attribute CASCADE_HEIGHT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute CDC_DEST_SYNC_FF : integer;
  attribute CDC_DEST_SYNC_FF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2;
  attribute COMMON_CLOCK : integer;
  attribute COMMON_CLOCK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute DOUT_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0";
  attribute ECC_MODE_integer : integer;
  attribute ECC_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute ENABLE_ECC : integer;
  attribute ENABLE_ECC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute EN_ADV_FEATURE : string;
  attribute EN_ADV_FEATURE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "16'b0000011100000111";
  attribute EN_AE : string;
  attribute EN_AE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
  attribute EN_AF : string;
  attribute EN_AF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
  attribute EN_DVLD : string;
  attribute EN_DVLD of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
  attribute EN_OF : string;
  attribute EN_OF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
  attribute EN_PE : string;
  attribute EN_PE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
  attribute EN_PF : string;
  attribute EN_PF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
  attribute EN_RDC : string;
  attribute EN_RDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
  attribute EN_SIM_ASSERT_ERR of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "warning";
  attribute EN_UF : string;
  attribute EN_UF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
  attribute EN_WACK : string;
  attribute EN_WACK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
  attribute EN_WDC : string;
  attribute EN_WDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
  attribute FG_EQ_ASYM_DOUT : string;
  attribute FG_EQ_ASYM_DOUT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
  attribute FIFO_MEMORY_TYPE_integer : integer;
  attribute FIFO_MEMORY_TYPE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
  attribute FIFO_MEM_TYPE : integer;
  attribute FIFO_MEM_TYPE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
  attribute FIFO_READ_DEPTH : integer;
  attribute FIFO_READ_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 32;
  attribute FIFO_READ_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
  attribute FIFO_SIZE : integer;
  attribute FIFO_SIZE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 832;
  attribute FIFO_WRITE_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 32;
  attribute FULL_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute FULL_RST_VAL : string;
  attribute FULL_RST_VAL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "soft";
  attribute PE_THRESH_ADJ : integer;
  attribute PE_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10;
  attribute PE_THRESH_MAX : integer;
  attribute PE_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 29;
  attribute PE_THRESH_MIN : integer;
  attribute PE_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3;
  attribute PF_THRESH_ADJ : integer;
  attribute PF_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 29;
  attribute PF_THRESH_MAX : integer;
  attribute PF_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 29;
  attribute PF_THRESH_MIN : integer;
  attribute PF_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5;
  attribute PROG_EMPTY_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10;
  attribute PROG_FULL_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 29;
  attribute RD_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5;
  attribute RD_DC_WIDTH_EXT : integer;
  attribute RD_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 6;
  attribute RD_LATENCY : integer;
  attribute RD_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
  attribute RD_MODE : integer;
  attribute RD_MODE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute RD_PNTR_WIDTH : integer;
  attribute RD_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5;
  attribute READ_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 26;
  attribute READ_MODE_integer : integer;
  attribute READ_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute READ_MODE_LL : integer;
  attribute READ_MODE_LL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute RELATED_CLOCKS of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute REMOVE_WR_RD_PROT_LOGIC : integer;
  attribute REMOVE_WR_RD_PROT_LOGIC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute SIM_ASSERT_CHK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute USE_ADV_FEATURES of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0707";
  attribute VERSION : integer;
  attribute VERSION of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute WAKEUP_TIME of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute WIDTH_RATIO : integer;
  attribute WIDTH_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
  attribute WRITE_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 26;
  attribute WR_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5;
  attribute WR_DC_WIDTH_EXT : integer;
  attribute WR_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 6;
  attribute WR_DEPTH_LOG : integer;
  attribute WR_DEPTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5;
  attribute WR_PNTR_WIDTH : integer;
  attribute WR_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5;
  attribute WR_RD_RATIO : integer;
  attribute WR_RD_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute WR_WIDTH_LOG : integer;
  attribute WR_WIDTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5;
  attribute XPM_MODULE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "TRUE";
  attribute both_stages_valid : integer;
  attribute both_stages_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3;
  attribute invalid : integer;
  attribute invalid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute stage1_valid : integer;
  attribute stage1_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2;
  attribute stage2_valid : integer;
  attribute stage2_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
begin
  almost_empty <= \<const0>\;
  almost_full <= \<const0>\;
  data_valid <= \<const0>\;
  dbiterr <= \<const0>\;
  sbiterr <= \<const0>\;
  wr_ack <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gnuram_async_fifo.xpm_fifo_base_inst\: entity work.\design_1_Vsp_core_0_0_xpm_fifo_base__parameterized1\
     port map (
      almost_empty => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED\,
      almost_full => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED\,
      data_valid => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED\,
      dbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\,
      din(25 downto 0) => din(25 downto 0),
      dout(25 downto 0) => dout(25 downto 0),
      empty => empty,
      full => full,
      full_n => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\,
      injectdbiterr => '0',
      injectsbiterr => '0',
      overflow => overflow,
      prog_empty => prog_empty,
      prog_full => prog_full,
      rd_clk => rd_clk,
      rd_data_count(4 downto 0) => rd_data_count(4 downto 0),
      rd_en => rd_en,
      rd_rst_busy => rd_rst_busy,
      rst => rst,
      sbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\,
      sleep => '0',
      underflow => underflow,
      wr_ack => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED\,
      wr_clk => wr_clk,
      wr_data_count(4 downto 0) => wr_data_count(4 downto 0),
      wr_en => wr_en,
      wr_rst_busy => wr_rst_busy
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ is
  port (
    sleep : in STD_LOGIC;
    rst : in STD_LOGIC;
    wr_clk : in STD_LOGIC;
    wr_en : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 41 downto 0 );
    full : out STD_LOGIC;
    prog_full : out STD_LOGIC;
    wr_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
    overflow : out STD_LOGIC;
    wr_rst_busy : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    rd_clk : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 41 downto 0 );
    empty : out STD_LOGIC;
    prog_empty : out STD_LOGIC;
    rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
    underflow : out STD_LOGIC;
    rd_rst_busy : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    data_valid : out STD_LOGIC;
    injectsbiterr : in STD_LOGIC;
    injectdbiterr : in STD_LOGIC;
    sbiterr : out STD_LOGIC;
    dbiterr : out STD_LOGIC
  );
  attribute CASCADE_HEIGHT : integer;
  attribute CASCADE_HEIGHT of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 0;
  attribute CDC_SYNC_STAGES : integer;
  attribute CDC_SYNC_STAGES of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 2;
  attribute DOUT_RESET_VALUE : string;
  attribute DOUT_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is "0";
  attribute ECC_MODE : string;
  attribute ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is "no_ecc";
  attribute EN_ADV_FEATURE_ASYNC : string;
  attribute EN_ADV_FEATURE_ASYNC of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is "16'b0000011100000111";
  attribute EN_SIM_ASSERT_ERR : string;
  attribute EN_SIM_ASSERT_ERR of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is "warning";
  attribute FIFO_MEMORY_TYPE : string;
  attribute FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is "distributed";
  attribute FIFO_READ_LATENCY : integer;
  attribute FIFO_READ_LATENCY of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 1;
  attribute FIFO_WRITE_DEPTH : integer;
  attribute FIFO_WRITE_DEPTH of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 32;
  attribute FULL_RESET_VALUE : integer;
  attribute FULL_RESET_VALUE of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is "xpm_fifo_async";
  attribute PROG_EMPTY_THRESH : integer;
  attribute PROG_EMPTY_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 10;
  attribute PROG_FULL_THRESH : integer;
  attribute PROG_FULL_THRESH of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 10;
  attribute P_COMMON_CLOCK : integer;
  attribute P_COMMON_CLOCK of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 0;
  attribute P_ECC_MODE : integer;
  attribute P_ECC_MODE of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 0;
  attribute P_FIFO_MEMORY_TYPE : integer;
  attribute P_FIFO_MEMORY_TYPE of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 1;
  attribute P_READ_MODE : integer;
  attribute P_READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 0;
  attribute P_WAKEUP_TIME : integer;
  attribute P_WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 2;
  attribute RD_DATA_COUNT_WIDTH : integer;
  attribute RD_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 1;
  attribute READ_DATA_WIDTH : integer;
  attribute READ_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 42;
  attribute READ_MODE : string;
  attribute READ_MODE of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is "std";
  attribute RELATED_CLOCKS : integer;
  attribute RELATED_CLOCKS of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 0;
  attribute USE_ADV_FEATURES : string;
  attribute USE_ADV_FEATURES of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is "0707";
  attribute WAKEUP_TIME : integer;
  attribute WAKEUP_TIME of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 0;
  attribute WRITE_DATA_WIDTH : integer;
  attribute WRITE_DATA_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 42;
  attribute WR_DATA_COUNT_WIDTH : integer;
  attribute WR_DATA_COUNT_WIDTH of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is 1;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is "TRUE";
  attribute dont_touch : string;
  attribute dont_touch of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is "true";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ : entity is "true";
end \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_xpm_fifo_async__parameterized0\ is
  signal \<const0>\ : STD_LOGIC;
  signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED\ : STD_LOGIC;
  attribute CASCADE_HEIGHT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute CDC_DEST_SYNC_FF : integer;
  attribute CDC_DEST_SYNC_FF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2;
  attribute COMMON_CLOCK : integer;
  attribute COMMON_CLOCK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute DOUT_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0";
  attribute ECC_MODE_integer : integer;
  attribute ECC_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute ENABLE_ECC : integer;
  attribute ENABLE_ECC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute EN_ADV_FEATURE : string;
  attribute EN_ADV_FEATURE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "16'b0000011100000111";
  attribute EN_AE : string;
  attribute EN_AE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
  attribute EN_AF : string;
  attribute EN_AF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
  attribute EN_DVLD : string;
  attribute EN_DVLD of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
  attribute EN_OF : string;
  attribute EN_OF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
  attribute EN_PE : string;
  attribute EN_PE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
  attribute EN_PF : string;
  attribute EN_PF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
  attribute EN_RDC : string;
  attribute EN_RDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
  attribute EN_SIM_ASSERT_ERR of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "warning";
  attribute EN_UF : string;
  attribute EN_UF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
  attribute EN_WACK : string;
  attribute EN_WACK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
  attribute EN_WDC : string;
  attribute EN_WDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
  attribute FG_EQ_ASYM_DOUT : string;
  attribute FG_EQ_ASYM_DOUT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
  attribute FIFO_MEMORY_TYPE_integer : integer;
  attribute FIFO_MEMORY_TYPE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
  attribute FIFO_MEM_TYPE : integer;
  attribute FIFO_MEM_TYPE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
  attribute FIFO_READ_DEPTH : integer;
  attribute FIFO_READ_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 32;
  attribute FIFO_READ_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
  attribute FIFO_SIZE : integer;
  attribute FIFO_SIZE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1344;
  attribute FIFO_WRITE_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 32;
  attribute FULL_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute FULL_RST_VAL : string;
  attribute FULL_RST_VAL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "soft";
  attribute PE_THRESH_ADJ : integer;
  attribute PE_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10;
  attribute PE_THRESH_MAX : integer;
  attribute PE_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 29;
  attribute PE_THRESH_MIN : integer;
  attribute PE_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3;
  attribute PF_THRESH_ADJ : integer;
  attribute PF_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10;
  attribute PF_THRESH_MAX : integer;
  attribute PF_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 29;
  attribute PF_THRESH_MIN : integer;
  attribute PF_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5;
  attribute PROG_EMPTY_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10;
  attribute PROG_FULL_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10;
  attribute RD_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
  attribute RD_DC_WIDTH_EXT : integer;
  attribute RD_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 6;
  attribute RD_LATENCY : integer;
  attribute RD_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
  attribute RD_MODE : integer;
  attribute RD_MODE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute RD_PNTR_WIDTH : integer;
  attribute RD_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5;
  attribute READ_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 42;
  attribute READ_MODE_integer : integer;
  attribute READ_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute READ_MODE_LL : integer;
  attribute READ_MODE_LL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute RELATED_CLOCKS of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute REMOVE_WR_RD_PROT_LOGIC : integer;
  attribute REMOVE_WR_RD_PROT_LOGIC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute SIM_ASSERT_CHK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute USE_ADV_FEATURES of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0707";
  attribute VERSION : integer;
  attribute VERSION of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute WAKEUP_TIME of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute WIDTH_RATIO : integer;
  attribute WIDTH_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
  attribute WRITE_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 42;
  attribute WR_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
  attribute WR_DC_WIDTH_EXT : integer;
  attribute WR_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 6;
  attribute WR_DEPTH_LOG : integer;
  attribute WR_DEPTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5;
  attribute WR_PNTR_WIDTH : integer;
  attribute WR_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5;
  attribute WR_RD_RATIO : integer;
  attribute WR_RD_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute WR_WIDTH_LOG : integer;
  attribute WR_WIDTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 6;
  attribute XPM_MODULE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "TRUE";
  attribute both_stages_valid : integer;
  attribute both_stages_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3;
  attribute invalid : integer;
  attribute invalid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
  attribute stage1_valid : integer;
  attribute stage1_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2;
  attribute stage2_valid : integer;
  attribute stage2_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
begin
  almost_empty <= \<const0>\;
  almost_full <= \<const0>\;
  data_valid <= \<const0>\;
  dbiterr <= \<const0>\;
  sbiterr <= \<const0>\;
  wr_ack <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\gnuram_async_fifo.xpm_fifo_base_inst\: entity work.\design_1_Vsp_core_0_0_xpm_fifo_base__parameterized2\
     port map (
      almost_empty => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED\,
      almost_full => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED\,
      data_valid => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED\,
      dbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\,
      din(41 downto 0) => din(41 downto 0),
      dout(41 downto 0) => dout(41 downto 0),
      empty => empty,
      full => full,
      full_n => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\,
      injectdbiterr => '0',
      injectsbiterr => '0',
      overflow => overflow,
      prog_empty => prog_empty,
      prog_full => prog_full,
      rd_clk => rd_clk,
      rd_data_count(0) => rd_data_count(0),
      rd_en => rd_en,
      rd_rst_busy => rd_rst_busy,
      rst => rst,
      sbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\,
      sleep => '0',
      underflow => underflow,
      wr_ack => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED\,
      wr_clk => wr_clk,
      wr_data_count(0) => wr_data_count(0),
      wr_en => wr_en,
      wr_rst_busy => wr_rst_busy
    );
end STRUCTURE;
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`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2024.2"
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`protect key_block
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`protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
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`protect key_block
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`protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
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`protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26224)
`protect data_block
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 is
  port (
    daddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
    dclk : in STD_LOGIC;
    den : in STD_LOGIC;
    di : in STD_LOGIC_VECTOR ( 15 downto 0 );
    dwe : in STD_LOGIC;
    do_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    drdy : out STD_LOGIC;
    clk_p : in STD_LOGIC;
    clk_n : in STD_LOGIC;
    clk : in STD_LOGIC;
    riu_clk : in STD_LOGIC;
    app_clk : in STD_LOGIC;
    bs_rst_dphy_in : in STD_LOGIC;
    rst_seq_done : out STD_LOGIC;
    pll0_clkout0 : out STD_LOGIC;
    pll0_locked : out STD_LOGIC;
    pll0_clkout1 : out STD_LOGIC;
    pll1_clkout0 : out STD_LOGIC;
    pll1_locked : out STD_LOGIC;
    intf_rdy : out STD_LOGIC;
    multi_intf_lock_in : in STD_LOGIC;
    shared_pll0_clkout0_in : in STD_LOGIC;
    shared_pll1_clkout0_in : in STD_LOGIC;
    shared_pll0_clkoutphy_in : in STD_LOGIC;
    shared_pll1_clkoutphy_in : in STD_LOGIC;
    shared_pll0_locked_in : in STD_LOGIC;
    shared_pll1_locked_in : in STD_LOGIC;
    shared_pll0_clkoutphy_out : out STD_LOGIC;
    shared_pll1_clkoutphy_out : out STD_LOGIC;
    clk_from_ibuf : out STD_LOGIC;
    lptx_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
    lptx_i_p : in STD_LOGIC_VECTOR ( 4 downto 0 );
    lptx_i_n : in STD_LOGIC_VECTOR ( 4 downto 0 );
    hs_rx_disable : in STD_LOGIC_VECTOR ( 4 downto 0 );
    lp_rx_disable : in STD_LOGIC_VECTOR ( 4 downto 0 );
    lp_rx_o_p : out STD_LOGIC_VECTOR ( 4 downto 0 );
    lp_rx_o_n : out STD_LOGIC_VECTOR ( 4 downto 0 );
    dly_rdy_bsc0 : out STD_LOGIC;
    vtc_rdy_bsc0 : out STD_LOGIC;
    en_vtc_bsc0 : in STD_LOGIC;
    phy_rden_bsc0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dly_rdy_bsc1 : out STD_LOGIC;
    vtc_rdy_bsc1 : out STD_LOGIC;
    en_vtc_bsc1 : in STD_LOGIC;
    phy_rden_bsc1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dly_rdy_bsc2 : out STD_LOGIC;
    vtc_rdy_bsc2 : out STD_LOGIC;
    en_vtc_bsc2 : in STD_LOGIC;
    phy_rden_bsc2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dly_rdy_bsc3 : out STD_LOGIC;
    vtc_rdy_bsc3 : out STD_LOGIC;
    en_vtc_bsc3 : in STD_LOGIC;
    phy_rden_bsc3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dly_rdy_bsc4 : out STD_LOGIC;
    vtc_rdy_bsc4 : out STD_LOGIC;
    en_vtc_bsc4 : in STD_LOGIC;
    phy_rden_bsc4 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dly_rdy_bsc5 : out STD_LOGIC;
    vtc_rdy_bsc5 : out STD_LOGIC;
    en_vtc_bsc5 : in STD_LOGIC;
    phy_rden_bsc5 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dly_rdy_bsc6 : out STD_LOGIC;
    vtc_rdy_bsc6 : out STD_LOGIC;
    en_vtc_bsc6 : in STD_LOGIC;
    phy_rden_bsc6 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    dly_rdy_bsc7 : out STD_LOGIC;
    vtc_rdy_bsc7 : out STD_LOGIC;
    en_vtc_bsc7 : in STD_LOGIC;
    phy_rden_bsc7 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    riu_addr_bg0 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    riu_nibble_sel_bg0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    riu_wr_data_bg0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_wr_en_bg0 : in STD_LOGIC;
    riu_rd_data_bg0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_valid_bg0 : out STD_LOGIC;
    riu_addr_bg0_bs0 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    riu_nibble_sel_bg0_bs0 : in STD_LOGIC;
    riu_wr_data_bg0_bs0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_wr_en_bg0_bs0 : in STD_LOGIC;
    riu_rd_data_bg0_bs0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_valid_bg0_bs0 : out STD_LOGIC;
    riu_addr_bg0_bs1 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    riu_nibble_sel_bg0_bs1 : in STD_LOGIC;
    riu_wr_data_bg0_bs1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_wr_en_bg0_bs1 : in STD_LOGIC;
    riu_rd_data_bg0_bs1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_valid_bg0_bs1 : out STD_LOGIC;
    riu_addr_bg1 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    riu_nibble_sel_bg1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    riu_wr_data_bg1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_wr_en_bg1 : in STD_LOGIC;
    riu_rd_data_bg1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_valid_bg1 : out STD_LOGIC;
    riu_addr_bg1_bs2 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    riu_nibble_sel_bg1_bs2 : in STD_LOGIC;
    riu_wr_data_bg1_bs2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_wr_en_bg1_bs2 : in STD_LOGIC;
    riu_rd_data_bg1_bs2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_valid_bg1_bs2 : out STD_LOGIC;
    riu_addr_bg1_bs3 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    riu_nibble_sel_bg1_bs3 : in STD_LOGIC;
    riu_wr_data_bg1_bs3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_wr_en_bg1_bs3 : in STD_LOGIC;
    riu_rd_data_bg1_bs3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_valid_bg1_bs3 : out STD_LOGIC;
    riu_addr_bg2 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    riu_nibble_sel_bg2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    riu_wr_data_bg2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_wr_en_bg2 : in STD_LOGIC;
    riu_rd_data_bg2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_valid_bg2 : out STD_LOGIC;
    riu_addr_bg2_bs4 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    riu_nibble_sel_bg2_bs4 : in STD_LOGIC;
    riu_wr_data_bg2_bs4 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_wr_en_bg2_bs4 : in STD_LOGIC;
    riu_rd_data_bg2_bs4 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_valid_bg2_bs4 : out STD_LOGIC;
    riu_addr_bg2_bs5 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    riu_nibble_sel_bg2_bs5 : in STD_LOGIC;
    riu_wr_data_bg2_bs5 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_wr_en_bg2_bs5 : in STD_LOGIC;
    riu_rd_data_bg2_bs5 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_valid_bg2_bs5 : out STD_LOGIC;
    riu_addr_bg3 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    riu_nibble_sel_bg3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    riu_wr_data_bg3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_wr_en_bg3 : in STD_LOGIC;
    riu_rd_data_bg3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_valid_bg3 : out STD_LOGIC;
    riu_addr_bg3_bs6 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    riu_nibble_sel_bg3_bs6 : in STD_LOGIC;
    riu_wr_data_bg3_bs6 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_wr_en_bg3_bs6 : in STD_LOGIC;
    riu_rd_data_bg3_bs6 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_valid_bg3_bs6 : out STD_LOGIC;
    riu_addr_bg3_bs7 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    riu_nibble_sel_bg3_bs7 : in STD_LOGIC;
    riu_wr_data_bg3_bs7 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_wr_en_bg3_bs7 : in STD_LOGIC;
    riu_rd_data_bg3_bs7 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    riu_valid_bg3_bs7 : out STD_LOGIC;
    tx_clk : in STD_LOGIC;
    rx_clk : in STD_LOGIC;
    bidir_tx_clk : in STD_LOGIC;
    bidir_rx_clk : in STD_LOGIC;
    bidir_tx_bs_tri_clk : in STD_LOGIC;
    bg0_pin0_nc : in STD_LOGIC;
    bg0_pin6_nc : in STD_LOGIC;
    bg1_pin0_nc : in STD_LOGIC;
    bg1_pin6_nc : in STD_LOGIC;
    bg2_pin0_nc : in STD_LOGIC;
    bg2_pin6_nc : in STD_LOGIC;
    bg3_pin0_nc : in STD_LOGIC;
    bg3_pin6_nc : in STD_LOGIC;
    start_bitslip : in STD_LOGIC;
    rx_bitslip_sync_done : out STD_LOGIC;
    rxtx_bitslip_sync_done : out STD_LOGIC;
    clk_rxp : in STD_LOGIC;
    data_to_fabric_clk_rxp : out STD_LOGIC_VECTOR ( 7 downto 0 );
    tri_t_0 : in STD_LOGIC;
    tx_cntvaluein_0 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_0 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_0 : in STD_LOGIC;
    tx_en_vtc_0 : in STD_LOGIC;
    tx_inc_0 : in STD_LOGIC;
    tx_load_0 : in STD_LOGIC;
    rx_cntvalueout_0 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_0 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_0 : in STD_LOGIC;
    rx_en_vtc_0 : in STD_LOGIC;
    rx_inc_0 : in STD_LOGIC;
    rx_load_0 : in STD_LOGIC;
    rx_cntvalueout_ext_0 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_0 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_0 : in STD_LOGIC;
    rx_en_vtc_ext_0 : in STD_LOGIC;
    rx_inc_ext_0 : in STD_LOGIC;
    rx_load_ext_0 : in STD_LOGIC;
    fifo_empty_0 : out STD_LOGIC;
    fifo_rd_clk_0 : in STD_LOGIC;
    fifo_rd_en_0 : in STD_LOGIC;
    bitslip_error_0 : out STD_LOGIC;
    clk_rxn : in STD_LOGIC;
    data_to_fabric_clk_rxn : out STD_LOGIC_VECTOR ( 7 downto 0 );
    tri_t_1 : in STD_LOGIC;
    tx_cntvaluein_1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_1 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_1 : in STD_LOGIC;
    tx_en_vtc_1 : in STD_LOGIC;
    tx_inc_1 : in STD_LOGIC;
    tx_load_1 : in STD_LOGIC;
    rx_cntvalueout_1 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_1 : in STD_LOGIC;
    rx_en_vtc_1 : in STD_LOGIC;
    rx_inc_1 : in STD_LOGIC;
    rx_load_1 : in STD_LOGIC;
    rx_cntvalueout_ext_1 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_1 : in STD_LOGIC;
    rx_en_vtc_ext_1 : in STD_LOGIC;
    rx_inc_ext_1 : in STD_LOGIC;
    rx_load_ext_1 : in STD_LOGIC;
    fifo_empty_1 : out STD_LOGIC;
    fifo_rd_clk_1 : in STD_LOGIC;
    fifo_rd_en_1 : in STD_LOGIC;
    bitslip_error_1 : out STD_LOGIC;
    data_rxp0 : in STD_LOGIC;
    data_to_fabric_data_rxp0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    tri_t_2 : in STD_LOGIC;
    tx_cntvaluein_2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_2 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_2 : in STD_LOGIC;
    tx_en_vtc_2 : in STD_LOGIC;
    tx_inc_2 : in STD_LOGIC;
    tx_load_2 : in STD_LOGIC;
    rx_cntvalueout_2 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_2 : in STD_LOGIC;
    rx_en_vtc_2 : in STD_LOGIC;
    rx_inc_2 : in STD_LOGIC;
    rx_load_2 : in STD_LOGIC;
    rx_cntvalueout_ext_2 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_2 : in STD_LOGIC;
    rx_en_vtc_ext_2 : in STD_LOGIC;
    rx_inc_ext_2 : in STD_LOGIC;
    rx_load_ext_2 : in STD_LOGIC;
    fifo_empty_2 : out STD_LOGIC;
    fifo_rd_clk_2 : in STD_LOGIC;
    fifo_rd_en_2 : in STD_LOGIC;
    bitslip_error_2 : out STD_LOGIC;
    data_rxn0 : in STD_LOGIC;
    data_to_fabric_data_rxn0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    tri_t_3 : in STD_LOGIC;
    tx_cntvaluein_3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_3 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_3 : in STD_LOGIC;
    tx_en_vtc_3 : in STD_LOGIC;
    tx_inc_3 : in STD_LOGIC;
    tx_load_3 : in STD_LOGIC;
    rx_cntvalueout_3 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_3 : in STD_LOGIC;
    rx_en_vtc_3 : in STD_LOGIC;
    rx_inc_3 : in STD_LOGIC;
    rx_load_3 : in STD_LOGIC;
    rx_cntvalueout_ext_3 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_3 : in STD_LOGIC;
    rx_en_vtc_ext_3 : in STD_LOGIC;
    rx_inc_ext_3 : in STD_LOGIC;
    rx_load_ext_3 : in STD_LOGIC;
    fifo_empty_3 : out STD_LOGIC;
    fifo_rd_clk_3 : in STD_LOGIC;
    fifo_rd_en_3 : in STD_LOGIC;
    bitslip_error_3 : out STD_LOGIC;
    data_rxp1 : in STD_LOGIC;
    data_to_fabric_data_rxp1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    tri_t_4 : in STD_LOGIC;
    tx_cntvaluein_4 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_4 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_4 : in STD_LOGIC;
    tx_en_vtc_4 : in STD_LOGIC;
    tx_inc_4 : in STD_LOGIC;
    tx_load_4 : in STD_LOGIC;
    rx_cntvalueout_4 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_4 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_4 : in STD_LOGIC;
    rx_en_vtc_4 : in STD_LOGIC;
    rx_inc_4 : in STD_LOGIC;
    rx_load_4 : in STD_LOGIC;
    rx_cntvalueout_ext_4 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_4 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_4 : in STD_LOGIC;
    rx_en_vtc_ext_4 : in STD_LOGIC;
    rx_inc_ext_4 : in STD_LOGIC;
    rx_load_ext_4 : in STD_LOGIC;
    fifo_empty_4 : out STD_LOGIC;
    fifo_rd_clk_4 : in STD_LOGIC;
    fifo_rd_en_4 : in STD_LOGIC;
    bitslip_error_4 : out STD_LOGIC;
    data_rxn1 : in STD_LOGIC;
    data_to_fabric_data_rxn1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    tri_t_5 : in STD_LOGIC;
    tx_cntvaluein_5 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_5 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_5 : in STD_LOGIC;
    tx_en_vtc_5 : in STD_LOGIC;
    tx_inc_5 : in STD_LOGIC;
    tx_load_5 : in STD_LOGIC;
    rx_cntvalueout_5 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_5 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_5 : in STD_LOGIC;
    rx_en_vtc_5 : in STD_LOGIC;
    rx_inc_5 : in STD_LOGIC;
    rx_load_5 : in STD_LOGIC;
    rx_cntvalueout_ext_5 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_5 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_5 : in STD_LOGIC;
    rx_en_vtc_ext_5 : in STD_LOGIC;
    rx_inc_ext_5 : in STD_LOGIC;
    rx_load_ext_5 : in STD_LOGIC;
    fifo_empty_5 : out STD_LOGIC;
    fifo_rd_clk_5 : in STD_LOGIC;
    fifo_rd_en_5 : in STD_LOGIC;
    bitslip_error_5 : out STD_LOGIC;
    data_rxp2 : in STD_LOGIC;
    data_to_fabric_data_rxp2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    tri_t_6 : in STD_LOGIC;
    tx_cntvaluein_6 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_6 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_6 : in STD_LOGIC;
    tx_en_vtc_6 : in STD_LOGIC;
    tx_inc_6 : in STD_LOGIC;
    tx_load_6 : in STD_LOGIC;
    rx_cntvalueout_6 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_6 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_6 : in STD_LOGIC;
    rx_en_vtc_6 : in STD_LOGIC;
    rx_inc_6 : in STD_LOGIC;
    rx_load_6 : in STD_LOGIC;
    rx_cntvalueout_ext_6 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_6 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_6 : in STD_LOGIC;
    rx_en_vtc_ext_6 : in STD_LOGIC;
    rx_inc_ext_6 : in STD_LOGIC;
    rx_load_ext_6 : in STD_LOGIC;
    fifo_empty_6 : out STD_LOGIC;
    fifo_rd_clk_6 : in STD_LOGIC;
    fifo_rd_en_6 : in STD_LOGIC;
    bitslip_error_6 : out STD_LOGIC;
    data_rxn2 : in STD_LOGIC;
    data_to_fabric_data_rxn2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    tri_t_7 : in STD_LOGIC;
    tx_cntvaluein_7 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_7 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_7 : in STD_LOGIC;
    tx_en_vtc_7 : in STD_LOGIC;
    tx_inc_7 : in STD_LOGIC;
    tx_load_7 : in STD_LOGIC;
    rx_cntvalueout_7 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_7 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_7 : in STD_LOGIC;
    rx_en_vtc_7 : in STD_LOGIC;
    rx_inc_7 : in STD_LOGIC;
    rx_load_7 : in STD_LOGIC;
    rx_cntvalueout_ext_7 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_7 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_7 : in STD_LOGIC;
    rx_en_vtc_ext_7 : in STD_LOGIC;
    rx_inc_ext_7 : in STD_LOGIC;
    rx_load_ext_7 : in STD_LOGIC;
    fifo_empty_7 : out STD_LOGIC;
    fifo_rd_clk_7 : in STD_LOGIC;
    fifo_rd_en_7 : in STD_LOGIC;
    bitslip_error_7 : out STD_LOGIC;
    data_rxp3 : in STD_LOGIC;
    data_to_fabric_data_rxp3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    tri_t_8 : in STD_LOGIC;
    tx_cntvaluein_8 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_8 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_8 : in STD_LOGIC;
    tx_en_vtc_8 : in STD_LOGIC;
    tx_inc_8 : in STD_LOGIC;
    tx_load_8 : in STD_LOGIC;
    rx_cntvalueout_8 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_8 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_8 : in STD_LOGIC;
    rx_en_vtc_8 : in STD_LOGIC;
    rx_inc_8 : in STD_LOGIC;
    rx_load_8 : in STD_LOGIC;
    rx_cntvalueout_ext_8 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_8 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_8 : in STD_LOGIC;
    rx_en_vtc_ext_8 : in STD_LOGIC;
    rx_inc_ext_8 : in STD_LOGIC;
    rx_load_ext_8 : in STD_LOGIC;
    fifo_empty_8 : out STD_LOGIC;
    fifo_rd_clk_8 : in STD_LOGIC;
    fifo_rd_en_8 : in STD_LOGIC;
    bitslip_error_8 : out STD_LOGIC;
    data_rxn3 : in STD_LOGIC;
    data_to_fabric_data_rxn3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    tri_t_9 : in STD_LOGIC;
    tx_cntvaluein_9 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_9 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_9 : in STD_LOGIC;
    tx_en_vtc_9 : in STD_LOGIC;
    tx_inc_9 : in STD_LOGIC;
    tx_load_9 : in STD_LOGIC;
    rx_cntvalueout_9 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_9 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_9 : in STD_LOGIC;
    rx_en_vtc_9 : in STD_LOGIC;
    rx_inc_9 : in STD_LOGIC;
    rx_load_9 : in STD_LOGIC;
    rx_cntvalueout_ext_9 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_9 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_9 : in STD_LOGIC;
    rx_en_vtc_ext_9 : in STD_LOGIC;
    rx_inc_ext_9 : in STD_LOGIC;
    rx_load_ext_9 : in STD_LOGIC;
    fifo_empty_9 : out STD_LOGIC;
    fifo_rd_clk_9 : in STD_LOGIC;
    fifo_rd_en_9 : in STD_LOGIC;
    bitslip_error_9 : out STD_LOGIC;
    tri_t_10 : in STD_LOGIC;
    tx_cntvaluein_10 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_10 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_10 : in STD_LOGIC;
    tx_en_vtc_10 : in STD_LOGIC;
    tx_inc_10 : in STD_LOGIC;
    tx_load_10 : in STD_LOGIC;
    rx_cntvalueout_10 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_10 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_10 : in STD_LOGIC;
    rx_en_vtc_10 : in STD_LOGIC;
    rx_inc_10 : in STD_LOGIC;
    rx_load_10 : in STD_LOGIC;
    rx_cntvalueout_ext_10 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_10 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_10 : in STD_LOGIC;
    rx_en_vtc_ext_10 : in STD_LOGIC;
    rx_inc_ext_10 : in STD_LOGIC;
    rx_load_ext_10 : in STD_LOGIC;
    fifo_empty_10 : out STD_LOGIC;
    fifo_rd_clk_10 : in STD_LOGIC;
    fifo_rd_en_10 : in STD_LOGIC;
    bitslip_error_10 : out STD_LOGIC;
    tri_t_11 : in STD_LOGIC;
    tx_cntvaluein_11 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_11 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_11 : in STD_LOGIC;
    tx_en_vtc_11 : in STD_LOGIC;
    tx_inc_11 : in STD_LOGIC;
    tx_load_11 : in STD_LOGIC;
    rx_cntvalueout_11 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_11 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_11 : in STD_LOGIC;
    rx_en_vtc_11 : in STD_LOGIC;
    rx_inc_11 : in STD_LOGIC;
    rx_load_11 : in STD_LOGIC;
    rx_cntvalueout_ext_11 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_11 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_11 : in STD_LOGIC;
    rx_en_vtc_ext_11 : in STD_LOGIC;
    rx_inc_ext_11 : in STD_LOGIC;
    rx_load_ext_11 : in STD_LOGIC;
    fifo_empty_11 : out STD_LOGIC;
    fifo_rd_clk_11 : in STD_LOGIC;
    fifo_rd_en_11 : in STD_LOGIC;
    bitslip_error_11 : out STD_LOGIC;
    tri_t_12 : in STD_LOGIC;
    tx_cntvaluein_12 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_12 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_12 : in STD_LOGIC;
    tx_en_vtc_12 : in STD_LOGIC;
    tx_inc_12 : in STD_LOGIC;
    tx_load_12 : in STD_LOGIC;
    rx_cntvalueout_12 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_12 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_12 : in STD_LOGIC;
    rx_en_vtc_12 : in STD_LOGIC;
    rx_inc_12 : in STD_LOGIC;
    rx_load_12 : in STD_LOGIC;
    rx_cntvalueout_ext_12 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_12 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_12 : in STD_LOGIC;
    rx_en_vtc_ext_12 : in STD_LOGIC;
    rx_inc_ext_12 : in STD_LOGIC;
    rx_load_ext_12 : in STD_LOGIC;
    fifo_empty_12 : out STD_LOGIC;
    fifo_rd_clk_12 : in STD_LOGIC;
    fifo_rd_en_12 : in STD_LOGIC;
    bitslip_error_12 : out STD_LOGIC;
    tri_t_13 : in STD_LOGIC;
    tx_cntvaluein_13 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_13 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_13 : in STD_LOGIC;
    tx_en_vtc_13 : in STD_LOGIC;
    tx_inc_13 : in STD_LOGIC;
    tx_load_13 : in STD_LOGIC;
    rx_cntvalueout_13 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_13 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_13 : in STD_LOGIC;
    rx_en_vtc_13 : in STD_LOGIC;
    rx_inc_13 : in STD_LOGIC;
    rx_load_13 : in STD_LOGIC;
    rx_cntvalueout_ext_13 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_13 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_13 : in STD_LOGIC;
    rx_en_vtc_ext_13 : in STD_LOGIC;
    rx_inc_ext_13 : in STD_LOGIC;
    rx_load_ext_13 : in STD_LOGIC;
    fifo_empty_13 : out STD_LOGIC;
    fifo_rd_clk_13 : in STD_LOGIC;
    fifo_rd_en_13 : in STD_LOGIC;
    bitslip_error_13 : out STD_LOGIC;
    tri_t_14 : in STD_LOGIC;
    tx_cntvaluein_14 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_14 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_14 : in STD_LOGIC;
    tx_en_vtc_14 : in STD_LOGIC;
    tx_inc_14 : in STD_LOGIC;
    tx_load_14 : in STD_LOGIC;
    rx_cntvalueout_14 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_14 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_14 : in STD_LOGIC;
    rx_en_vtc_14 : in STD_LOGIC;
    rx_inc_14 : in STD_LOGIC;
    rx_load_14 : in STD_LOGIC;
    rx_cntvalueout_ext_14 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_14 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_14 : in STD_LOGIC;
    rx_en_vtc_ext_14 : in STD_LOGIC;
    rx_inc_ext_14 : in STD_LOGIC;
    rx_load_ext_14 : in STD_LOGIC;
    fifo_empty_14 : out STD_LOGIC;
    fifo_rd_clk_14 : in STD_LOGIC;
    fifo_rd_en_14 : in STD_LOGIC;
    bitslip_error_14 : out STD_LOGIC;
    tri_t_15 : in STD_LOGIC;
    tx_cntvaluein_15 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_15 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_15 : in STD_LOGIC;
    tx_en_vtc_15 : in STD_LOGIC;
    tx_inc_15 : in STD_LOGIC;
    tx_load_15 : in STD_LOGIC;
    rx_cntvalueout_15 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_15 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_15 : in STD_LOGIC;
    rx_en_vtc_15 : in STD_LOGIC;
    rx_inc_15 : in STD_LOGIC;
    rx_load_15 : in STD_LOGIC;
    rx_cntvalueout_ext_15 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_15 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_15 : in STD_LOGIC;
    rx_en_vtc_ext_15 : in STD_LOGIC;
    rx_inc_ext_15 : in STD_LOGIC;
    rx_load_ext_15 : in STD_LOGIC;
    fifo_empty_15 : out STD_LOGIC;
    fifo_rd_clk_15 : in STD_LOGIC;
    fifo_rd_en_15 : in STD_LOGIC;
    bitslip_error_15 : out STD_LOGIC;
    tri_t_16 : in STD_LOGIC;
    tx_cntvaluein_16 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_16 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_16 : in STD_LOGIC;
    tx_en_vtc_16 : in STD_LOGIC;
    tx_inc_16 : in STD_LOGIC;
    tx_load_16 : in STD_LOGIC;
    rx_cntvalueout_16 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_16 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_16 : in STD_LOGIC;
    rx_en_vtc_16 : in STD_LOGIC;
    rx_inc_16 : in STD_LOGIC;
    rx_load_16 : in STD_LOGIC;
    rx_cntvalueout_ext_16 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_16 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_16 : in STD_LOGIC;
    rx_en_vtc_ext_16 : in STD_LOGIC;
    rx_inc_ext_16 : in STD_LOGIC;
    rx_load_ext_16 : in STD_LOGIC;
    fifo_empty_16 : out STD_LOGIC;
    fifo_rd_clk_16 : in STD_LOGIC;
    fifo_rd_en_16 : in STD_LOGIC;
    bitslip_error_16 : out STD_LOGIC;
    tri_t_17 : in STD_LOGIC;
    tx_cntvaluein_17 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_17 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_17 : in STD_LOGIC;
    tx_en_vtc_17 : in STD_LOGIC;
    tx_inc_17 : in STD_LOGIC;
    tx_load_17 : in STD_LOGIC;
    rx_cntvalueout_17 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_17 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_17 : in STD_LOGIC;
    rx_en_vtc_17 : in STD_LOGIC;
    rx_inc_17 : in STD_LOGIC;
    rx_load_17 : in STD_LOGIC;
    rx_cntvalueout_ext_17 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_17 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_17 : in STD_LOGIC;
    rx_en_vtc_ext_17 : in STD_LOGIC;
    rx_inc_ext_17 : in STD_LOGIC;
    rx_load_ext_17 : in STD_LOGIC;
    fifo_empty_17 : out STD_LOGIC;
    fifo_rd_clk_17 : in STD_LOGIC;
    fifo_rd_en_17 : in STD_LOGIC;
    bitslip_error_17 : out STD_LOGIC;
    tri_t_18 : in STD_LOGIC;
    tx_cntvaluein_18 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_18 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_18 : in STD_LOGIC;
    tx_en_vtc_18 : in STD_LOGIC;
    tx_inc_18 : in STD_LOGIC;
    tx_load_18 : in STD_LOGIC;
    rx_cntvalueout_18 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_18 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_18 : in STD_LOGIC;
    rx_en_vtc_18 : in STD_LOGIC;
    rx_inc_18 : in STD_LOGIC;
    rx_load_18 : in STD_LOGIC;
    rx_cntvalueout_ext_18 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_18 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_18 : in STD_LOGIC;
    rx_en_vtc_ext_18 : in STD_LOGIC;
    rx_inc_ext_18 : in STD_LOGIC;
    rx_load_ext_18 : in STD_LOGIC;
    fifo_empty_18 : out STD_LOGIC;
    fifo_rd_clk_18 : in STD_LOGIC;
    fifo_rd_en_18 : in STD_LOGIC;
    bitslip_error_18 : out STD_LOGIC;
    tri_t_19 : in STD_LOGIC;
    tx_cntvaluein_19 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_19 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_19 : in STD_LOGIC;
    tx_en_vtc_19 : in STD_LOGIC;
    tx_inc_19 : in STD_LOGIC;
    tx_load_19 : in STD_LOGIC;
    rx_cntvalueout_19 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_19 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_19 : in STD_LOGIC;
    rx_en_vtc_19 : in STD_LOGIC;
    rx_inc_19 : in STD_LOGIC;
    rx_load_19 : in STD_LOGIC;
    rx_cntvalueout_ext_19 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_19 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_19 : in STD_LOGIC;
    rx_en_vtc_ext_19 : in STD_LOGIC;
    rx_inc_ext_19 : in STD_LOGIC;
    rx_load_ext_19 : in STD_LOGIC;
    fifo_empty_19 : out STD_LOGIC;
    fifo_rd_clk_19 : in STD_LOGIC;
    fifo_rd_en_19 : in STD_LOGIC;
    bitslip_error_19 : out STD_LOGIC;
    tri_t_20 : in STD_LOGIC;
    tx_cntvaluein_20 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_20 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_20 : in STD_LOGIC;
    tx_en_vtc_20 : in STD_LOGIC;
    tx_inc_20 : in STD_LOGIC;
    tx_load_20 : in STD_LOGIC;
    rx_cntvalueout_20 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_20 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_20 : in STD_LOGIC;
    rx_en_vtc_20 : in STD_LOGIC;
    rx_inc_20 : in STD_LOGIC;
    rx_load_20 : in STD_LOGIC;
    rx_cntvalueout_ext_20 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_20 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_20 : in STD_LOGIC;
    rx_en_vtc_ext_20 : in STD_LOGIC;
    rx_inc_ext_20 : in STD_LOGIC;
    rx_load_ext_20 : in STD_LOGIC;
    fifo_empty_20 : out STD_LOGIC;
    fifo_rd_clk_20 : in STD_LOGIC;
    fifo_rd_en_20 : in STD_LOGIC;
    bitslip_error_20 : out STD_LOGIC;
    tri_t_21 : in STD_LOGIC;
    tx_cntvaluein_21 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_21 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_21 : in STD_LOGIC;
    tx_en_vtc_21 : in STD_LOGIC;
    tx_inc_21 : in STD_LOGIC;
    tx_load_21 : in STD_LOGIC;
    rx_cntvalueout_21 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_21 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_21 : in STD_LOGIC;
    rx_en_vtc_21 : in STD_LOGIC;
    rx_inc_21 : in STD_LOGIC;
    rx_load_21 : in STD_LOGIC;
    rx_cntvalueout_ext_21 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_21 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_21 : in STD_LOGIC;
    rx_en_vtc_ext_21 : in STD_LOGIC;
    rx_inc_ext_21 : in STD_LOGIC;
    rx_load_ext_21 : in STD_LOGIC;
    fifo_empty_21 : out STD_LOGIC;
    fifo_rd_clk_21 : in STD_LOGIC;
    fifo_rd_en_21 : in STD_LOGIC;
    bitslip_error_21 : out STD_LOGIC;
    tri_t_22 : in STD_LOGIC;
    tx_cntvaluein_22 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_22 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_22 : in STD_LOGIC;
    tx_en_vtc_22 : in STD_LOGIC;
    tx_inc_22 : in STD_LOGIC;
    tx_load_22 : in STD_LOGIC;
    rx_cntvalueout_22 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_22 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_22 : in STD_LOGIC;
    rx_en_vtc_22 : in STD_LOGIC;
    rx_inc_22 : in STD_LOGIC;
    rx_load_22 : in STD_LOGIC;
    rx_cntvalueout_ext_22 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_22 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_22 : in STD_LOGIC;
    rx_en_vtc_ext_22 : in STD_LOGIC;
    rx_inc_ext_22 : in STD_LOGIC;
    rx_load_ext_22 : in STD_LOGIC;
    fifo_empty_22 : out STD_LOGIC;
    fifo_rd_clk_22 : in STD_LOGIC;
    fifo_rd_en_22 : in STD_LOGIC;
    bitslip_error_22 : out STD_LOGIC;
    tri_t_23 : in STD_LOGIC;
    tx_cntvaluein_23 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_23 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_23 : in STD_LOGIC;
    tx_en_vtc_23 : in STD_LOGIC;
    tx_inc_23 : in STD_LOGIC;
    tx_load_23 : in STD_LOGIC;
    rx_cntvalueout_23 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_23 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_23 : in STD_LOGIC;
    rx_en_vtc_23 : in STD_LOGIC;
    rx_inc_23 : in STD_LOGIC;
    rx_load_23 : in STD_LOGIC;
    rx_cntvalueout_ext_23 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_23 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_23 : in STD_LOGIC;
    rx_en_vtc_ext_23 : in STD_LOGIC;
    rx_inc_ext_23 : in STD_LOGIC;
    rx_load_ext_23 : in STD_LOGIC;
    fifo_empty_23 : out STD_LOGIC;
    fifo_rd_clk_23 : in STD_LOGIC;
    fifo_rd_en_23 : in STD_LOGIC;
    bitslip_error_23 : out STD_LOGIC;
    tri_t_24 : in STD_LOGIC;
    tx_cntvaluein_24 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_24 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_24 : in STD_LOGIC;
    tx_en_vtc_24 : in STD_LOGIC;
    tx_inc_24 : in STD_LOGIC;
    tx_load_24 : in STD_LOGIC;
    rx_cntvalueout_24 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_24 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_24 : in STD_LOGIC;
    rx_en_vtc_24 : in STD_LOGIC;
    rx_inc_24 : in STD_LOGIC;
    rx_load_24 : in STD_LOGIC;
    rx_cntvalueout_ext_24 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_24 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_24 : in STD_LOGIC;
    rx_en_vtc_ext_24 : in STD_LOGIC;
    rx_inc_ext_24 : in STD_LOGIC;
    rx_load_ext_24 : in STD_LOGIC;
    fifo_empty_24 : out STD_LOGIC;
    fifo_rd_clk_24 : in STD_LOGIC;
    fifo_rd_en_24 : in STD_LOGIC;
    bitslip_error_24 : out STD_LOGIC;
    tri_t_25 : in STD_LOGIC;
    tx_cntvaluein_25 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_25 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_25 : in STD_LOGIC;
    tx_en_vtc_25 : in STD_LOGIC;
    tx_inc_25 : in STD_LOGIC;
    tx_load_25 : in STD_LOGIC;
    rx_cntvalueout_25 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_25 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_25 : in STD_LOGIC;
    rx_en_vtc_25 : in STD_LOGIC;
    rx_inc_25 : in STD_LOGIC;
    rx_load_25 : in STD_LOGIC;
    rx_cntvalueout_ext_25 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_25 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_25 : in STD_LOGIC;
    rx_en_vtc_ext_25 : in STD_LOGIC;
    rx_inc_ext_25 : in STD_LOGIC;
    rx_load_ext_25 : in STD_LOGIC;
    fifo_empty_25 : out STD_LOGIC;
    fifo_rd_clk_25 : in STD_LOGIC;
    fifo_rd_en_25 : in STD_LOGIC;
    bitslip_error_25 : out STD_LOGIC;
    tri_t_26 : in STD_LOGIC;
    tx_cntvaluein_26 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_26 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_26 : in STD_LOGIC;
    tx_en_vtc_26 : in STD_LOGIC;
    tx_inc_26 : in STD_LOGIC;
    tx_load_26 : in STD_LOGIC;
    rx_cntvalueout_26 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_26 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_26 : in STD_LOGIC;
    rx_en_vtc_26 : in STD_LOGIC;
    rx_inc_26 : in STD_LOGIC;
    rx_load_26 : in STD_LOGIC;
    rx_cntvalueout_ext_26 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_26 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_26 : in STD_LOGIC;
    rx_en_vtc_ext_26 : in STD_LOGIC;
    rx_inc_ext_26 : in STD_LOGIC;
    rx_load_ext_26 : in STD_LOGIC;
    fifo_empty_26 : out STD_LOGIC;
    fifo_rd_clk_26 : in STD_LOGIC;
    fifo_rd_en_26 : in STD_LOGIC;
    bitslip_error_26 : out STD_LOGIC;
    tri_t_27 : in STD_LOGIC;
    tx_cntvaluein_27 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_27 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_27 : in STD_LOGIC;
    tx_en_vtc_27 : in STD_LOGIC;
    tx_inc_27 : in STD_LOGIC;
    tx_load_27 : in STD_LOGIC;
    rx_cntvalueout_27 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_27 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_27 : in STD_LOGIC;
    rx_en_vtc_27 : in STD_LOGIC;
    rx_inc_27 : in STD_LOGIC;
    rx_load_27 : in STD_LOGIC;
    rx_cntvalueout_ext_27 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_27 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_27 : in STD_LOGIC;
    rx_en_vtc_ext_27 : in STD_LOGIC;
    rx_inc_ext_27 : in STD_LOGIC;
    rx_load_ext_27 : in STD_LOGIC;
    fifo_empty_27 : out STD_LOGIC;
    fifo_rd_clk_27 : in STD_LOGIC;
    fifo_rd_en_27 : in STD_LOGIC;
    bitslip_error_27 : out STD_LOGIC;
    tri_t_28 : in STD_LOGIC;
    tx_cntvaluein_28 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_28 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_28 : in STD_LOGIC;
    tx_en_vtc_28 : in STD_LOGIC;
    tx_inc_28 : in STD_LOGIC;
    tx_load_28 : in STD_LOGIC;
    rx_cntvalueout_28 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_28 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_28 : in STD_LOGIC;
    rx_en_vtc_28 : in STD_LOGIC;
    rx_inc_28 : in STD_LOGIC;
    rx_load_28 : in STD_LOGIC;
    rx_cntvalueout_ext_28 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_28 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_28 : in STD_LOGIC;
    rx_en_vtc_ext_28 : in STD_LOGIC;
    rx_inc_ext_28 : in STD_LOGIC;
    rx_load_ext_28 : in STD_LOGIC;
    fifo_empty_28 : out STD_LOGIC;
    fifo_rd_clk_28 : in STD_LOGIC;
    fifo_rd_en_28 : in STD_LOGIC;
    bitslip_error_28 : out STD_LOGIC;
    tri_t_29 : in STD_LOGIC;
    tx_cntvaluein_29 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_29 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_29 : in STD_LOGIC;
    tx_en_vtc_29 : in STD_LOGIC;
    tx_inc_29 : in STD_LOGIC;
    tx_load_29 : in STD_LOGIC;
    rx_cntvalueout_29 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_29 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_29 : in STD_LOGIC;
    rx_en_vtc_29 : in STD_LOGIC;
    rx_inc_29 : in STD_LOGIC;
    rx_load_29 : in STD_LOGIC;
    rx_cntvalueout_ext_29 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_29 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_29 : in STD_LOGIC;
    rx_en_vtc_ext_29 : in STD_LOGIC;
    rx_inc_ext_29 : in STD_LOGIC;
    rx_load_ext_29 : in STD_LOGIC;
    fifo_empty_29 : out STD_LOGIC;
    fifo_rd_clk_29 : in STD_LOGIC;
    fifo_rd_en_29 : in STD_LOGIC;
    bitslip_error_29 : out STD_LOGIC;
    tri_t_30 : in STD_LOGIC;
    tx_cntvaluein_30 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_30 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_30 : in STD_LOGIC;
    tx_en_vtc_30 : in STD_LOGIC;
    tx_inc_30 : in STD_LOGIC;
    tx_load_30 : in STD_LOGIC;
    rx_cntvalueout_30 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_30 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_30 : in STD_LOGIC;
    rx_en_vtc_30 : in STD_LOGIC;
    rx_inc_30 : in STD_LOGIC;
    rx_load_30 : in STD_LOGIC;
    rx_cntvalueout_ext_30 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_30 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_30 : in STD_LOGIC;
    rx_en_vtc_ext_30 : in STD_LOGIC;
    rx_inc_ext_30 : in STD_LOGIC;
    rx_load_ext_30 : in STD_LOGIC;
    fifo_empty_30 : out STD_LOGIC;
    fifo_rd_clk_30 : in STD_LOGIC;
    fifo_rd_en_30 : in STD_LOGIC;
    bitslip_error_30 : out STD_LOGIC;
    tri_t_31 : in STD_LOGIC;
    tx_cntvaluein_31 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_31 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_31 : in STD_LOGIC;
    tx_en_vtc_31 : in STD_LOGIC;
    tx_inc_31 : in STD_LOGIC;
    tx_load_31 : in STD_LOGIC;
    rx_cntvalueout_31 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_31 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_31 : in STD_LOGIC;
    rx_en_vtc_31 : in STD_LOGIC;
    rx_inc_31 : in STD_LOGIC;
    rx_load_31 : in STD_LOGIC;
    rx_cntvalueout_ext_31 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_31 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_31 : in STD_LOGIC;
    rx_en_vtc_ext_31 : in STD_LOGIC;
    rx_inc_ext_31 : in STD_LOGIC;
    rx_load_ext_31 : in STD_LOGIC;
    fifo_empty_31 : out STD_LOGIC;
    fifo_rd_clk_31 : in STD_LOGIC;
    fifo_rd_en_31 : in STD_LOGIC;
    bitslip_error_31 : out STD_LOGIC;
    tri_t_32 : in STD_LOGIC;
    tx_cntvaluein_32 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_32 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_32 : in STD_LOGIC;
    tx_en_vtc_32 : in STD_LOGIC;
    tx_inc_32 : in STD_LOGIC;
    tx_load_32 : in STD_LOGIC;
    rx_cntvalueout_32 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_32 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_32 : in STD_LOGIC;
    rx_en_vtc_32 : in STD_LOGIC;
    rx_inc_32 : in STD_LOGIC;
    rx_load_32 : in STD_LOGIC;
    rx_cntvalueout_ext_32 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_32 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_32 : in STD_LOGIC;
    rx_en_vtc_ext_32 : in STD_LOGIC;
    rx_inc_ext_32 : in STD_LOGIC;
    rx_load_ext_32 : in STD_LOGIC;
    fifo_empty_32 : out STD_LOGIC;
    fifo_rd_clk_32 : in STD_LOGIC;
    fifo_rd_en_32 : in STD_LOGIC;
    bitslip_error_32 : out STD_LOGIC;
    tri_t_33 : in STD_LOGIC;
    tx_cntvaluein_33 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_33 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_33 : in STD_LOGIC;
    tx_en_vtc_33 : in STD_LOGIC;
    tx_inc_33 : in STD_LOGIC;
    tx_load_33 : in STD_LOGIC;
    rx_cntvalueout_33 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_33 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_33 : in STD_LOGIC;
    rx_en_vtc_33 : in STD_LOGIC;
    rx_inc_33 : in STD_LOGIC;
    rx_load_33 : in STD_LOGIC;
    rx_cntvalueout_ext_33 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_33 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_33 : in STD_LOGIC;
    rx_en_vtc_ext_33 : in STD_LOGIC;
    rx_inc_ext_33 : in STD_LOGIC;
    rx_load_ext_33 : in STD_LOGIC;
    fifo_empty_33 : out STD_LOGIC;
    fifo_rd_clk_33 : in STD_LOGIC;
    fifo_rd_en_33 : in STD_LOGIC;
    bitslip_error_33 : out STD_LOGIC;
    tri_t_34 : in STD_LOGIC;
    tx_cntvaluein_34 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_34 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_34 : in STD_LOGIC;
    tx_en_vtc_34 : in STD_LOGIC;
    tx_inc_34 : in STD_LOGIC;
    tx_load_34 : in STD_LOGIC;
    rx_cntvalueout_34 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_34 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_34 : in STD_LOGIC;
    rx_en_vtc_34 : in STD_LOGIC;
    rx_inc_34 : in STD_LOGIC;
    rx_load_34 : in STD_LOGIC;
    rx_cntvalueout_ext_34 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_34 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_34 : in STD_LOGIC;
    rx_en_vtc_ext_34 : in STD_LOGIC;
    rx_inc_ext_34 : in STD_LOGIC;
    rx_load_ext_34 : in STD_LOGIC;
    fifo_empty_34 : out STD_LOGIC;
    fifo_rd_clk_34 : in STD_LOGIC;
    fifo_rd_en_34 : in STD_LOGIC;
    bitslip_error_34 : out STD_LOGIC;
    tri_t_35 : in STD_LOGIC;
    tx_cntvaluein_35 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_35 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_35 : in STD_LOGIC;
    tx_en_vtc_35 : in STD_LOGIC;
    tx_inc_35 : in STD_LOGIC;
    tx_load_35 : in STD_LOGIC;
    rx_cntvalueout_35 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_35 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_35 : in STD_LOGIC;
    rx_en_vtc_35 : in STD_LOGIC;
    rx_inc_35 : in STD_LOGIC;
    rx_load_35 : in STD_LOGIC;
    rx_cntvalueout_ext_35 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_35 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_35 : in STD_LOGIC;
    rx_en_vtc_ext_35 : in STD_LOGIC;
    rx_inc_ext_35 : in STD_LOGIC;
    rx_load_ext_35 : in STD_LOGIC;
    fifo_empty_35 : out STD_LOGIC;
    fifo_rd_clk_35 : in STD_LOGIC;
    fifo_rd_en_35 : in STD_LOGIC;
    bitslip_error_35 : out STD_LOGIC;
    tri_t_36 : in STD_LOGIC;
    tx_cntvaluein_36 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_36 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_36 : in STD_LOGIC;
    tx_en_vtc_36 : in STD_LOGIC;
    tx_inc_36 : in STD_LOGIC;
    tx_load_36 : in STD_LOGIC;
    rx_cntvalueout_36 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_36 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_36 : in STD_LOGIC;
    rx_en_vtc_36 : in STD_LOGIC;
    rx_inc_36 : in STD_LOGIC;
    rx_load_36 : in STD_LOGIC;
    rx_cntvalueout_ext_36 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_36 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_36 : in STD_LOGIC;
    rx_en_vtc_ext_36 : in STD_LOGIC;
    rx_inc_ext_36 : in STD_LOGIC;
    rx_load_ext_36 : in STD_LOGIC;
    fifo_empty_36 : out STD_LOGIC;
    fifo_rd_clk_36 : in STD_LOGIC;
    fifo_rd_en_36 : in STD_LOGIC;
    bitslip_error_36 : out STD_LOGIC;
    tri_t_37 : in STD_LOGIC;
    tx_cntvaluein_37 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_37 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_37 : in STD_LOGIC;
    tx_en_vtc_37 : in STD_LOGIC;
    tx_inc_37 : in STD_LOGIC;
    tx_load_37 : in STD_LOGIC;
    rx_cntvalueout_37 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_37 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_37 : in STD_LOGIC;
    rx_en_vtc_37 : in STD_LOGIC;
    rx_inc_37 : in STD_LOGIC;
    rx_load_37 : in STD_LOGIC;
    rx_cntvalueout_ext_37 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_37 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_37 : in STD_LOGIC;
    rx_en_vtc_ext_37 : in STD_LOGIC;
    rx_inc_ext_37 : in STD_LOGIC;
    rx_load_ext_37 : in STD_LOGIC;
    fifo_empty_37 : out STD_LOGIC;
    fifo_rd_clk_37 : in STD_LOGIC;
    fifo_rd_en_37 : in STD_LOGIC;
    bitslip_error_37 : out STD_LOGIC;
    tri_t_38 : in STD_LOGIC;
    tx_cntvaluein_38 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_38 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_38 : in STD_LOGIC;
    tx_en_vtc_38 : in STD_LOGIC;
    tx_inc_38 : in STD_LOGIC;
    tx_load_38 : in STD_LOGIC;
    rx_cntvalueout_38 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_38 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_38 : in STD_LOGIC;
    rx_en_vtc_38 : in STD_LOGIC;
    rx_inc_38 : in STD_LOGIC;
    rx_load_38 : in STD_LOGIC;
    rx_cntvalueout_ext_38 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_38 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_38 : in STD_LOGIC;
    rx_en_vtc_ext_38 : in STD_LOGIC;
    rx_inc_ext_38 : in STD_LOGIC;
    rx_load_ext_38 : in STD_LOGIC;
    fifo_empty_38 : out STD_LOGIC;
    fifo_rd_clk_38 : in STD_LOGIC;
    fifo_rd_en_38 : in STD_LOGIC;
    bitslip_error_38 : out STD_LOGIC;
    tri_t_39 : in STD_LOGIC;
    tx_cntvaluein_39 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_39 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_39 : in STD_LOGIC;
    tx_en_vtc_39 : in STD_LOGIC;
    tx_inc_39 : in STD_LOGIC;
    tx_load_39 : in STD_LOGIC;
    rx_cntvalueout_39 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_39 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_39 : in STD_LOGIC;
    rx_en_vtc_39 : in STD_LOGIC;
    rx_inc_39 : in STD_LOGIC;
    rx_load_39 : in STD_LOGIC;
    rx_cntvalueout_ext_39 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_39 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_39 : in STD_LOGIC;
    rx_en_vtc_ext_39 : in STD_LOGIC;
    rx_inc_ext_39 : in STD_LOGIC;
    rx_load_ext_39 : in STD_LOGIC;
    fifo_empty_39 : out STD_LOGIC;
    fifo_rd_clk_39 : in STD_LOGIC;
    fifo_rd_en_39 : in STD_LOGIC;
    bitslip_error_39 : out STD_LOGIC;
    tri_t_40 : in STD_LOGIC;
    tx_cntvaluein_40 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_40 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_40 : in STD_LOGIC;
    tx_en_vtc_40 : in STD_LOGIC;
    tx_inc_40 : in STD_LOGIC;
    tx_load_40 : in STD_LOGIC;
    rx_cntvalueout_40 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_40 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_40 : in STD_LOGIC;
    rx_en_vtc_40 : in STD_LOGIC;
    rx_inc_40 : in STD_LOGIC;
    rx_load_40 : in STD_LOGIC;
    rx_cntvalueout_ext_40 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_40 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_40 : in STD_LOGIC;
    rx_en_vtc_ext_40 : in STD_LOGIC;
    rx_inc_ext_40 : in STD_LOGIC;
    rx_load_ext_40 : in STD_LOGIC;
    fifo_empty_40 : out STD_LOGIC;
    fifo_rd_clk_40 : in STD_LOGIC;
    fifo_rd_en_40 : in STD_LOGIC;
    bitslip_error_40 : out STD_LOGIC;
    tri_t_41 : in STD_LOGIC;
    tx_cntvaluein_41 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_41 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_41 : in STD_LOGIC;
    tx_en_vtc_41 : in STD_LOGIC;
    tx_inc_41 : in STD_LOGIC;
    tx_load_41 : in STD_LOGIC;
    rx_cntvalueout_41 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_41 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_41 : in STD_LOGIC;
    rx_en_vtc_41 : in STD_LOGIC;
    rx_inc_41 : in STD_LOGIC;
    rx_load_41 : in STD_LOGIC;
    rx_cntvalueout_ext_41 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_41 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_41 : in STD_LOGIC;
    rx_en_vtc_ext_41 : in STD_LOGIC;
    rx_inc_ext_41 : in STD_LOGIC;
    rx_load_ext_41 : in STD_LOGIC;
    fifo_empty_41 : out STD_LOGIC;
    fifo_rd_clk_41 : in STD_LOGIC;
    fifo_rd_en_41 : in STD_LOGIC;
    bitslip_error_41 : out STD_LOGIC;
    tri_t_42 : in STD_LOGIC;
    tx_cntvaluein_42 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_42 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_42 : in STD_LOGIC;
    tx_en_vtc_42 : in STD_LOGIC;
    tx_inc_42 : in STD_LOGIC;
    tx_load_42 : in STD_LOGIC;
    rx_cntvalueout_42 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_42 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_42 : in STD_LOGIC;
    rx_en_vtc_42 : in STD_LOGIC;
    rx_inc_42 : in STD_LOGIC;
    rx_load_42 : in STD_LOGIC;
    rx_cntvalueout_ext_42 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_42 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_42 : in STD_LOGIC;
    rx_en_vtc_ext_42 : in STD_LOGIC;
    rx_inc_ext_42 : in STD_LOGIC;
    rx_load_ext_42 : in STD_LOGIC;
    fifo_empty_42 : out STD_LOGIC;
    fifo_rd_clk_42 : in STD_LOGIC;
    fifo_rd_en_42 : in STD_LOGIC;
    bitslip_error_42 : out STD_LOGIC;
    tri_t_43 : in STD_LOGIC;
    tx_cntvaluein_43 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_43 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_43 : in STD_LOGIC;
    tx_en_vtc_43 : in STD_LOGIC;
    tx_inc_43 : in STD_LOGIC;
    tx_load_43 : in STD_LOGIC;
    rx_cntvalueout_43 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_43 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_43 : in STD_LOGIC;
    rx_en_vtc_43 : in STD_LOGIC;
    rx_inc_43 : in STD_LOGIC;
    rx_load_43 : in STD_LOGIC;
    rx_cntvalueout_ext_43 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_43 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_43 : in STD_LOGIC;
    rx_en_vtc_ext_43 : in STD_LOGIC;
    rx_inc_ext_43 : in STD_LOGIC;
    rx_load_ext_43 : in STD_LOGIC;
    fifo_empty_43 : out STD_LOGIC;
    fifo_rd_clk_43 : in STD_LOGIC;
    fifo_rd_en_43 : in STD_LOGIC;
    bitslip_error_43 : out STD_LOGIC;
    tri_t_44 : in STD_LOGIC;
    tx_cntvaluein_44 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_44 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_44 : in STD_LOGIC;
    tx_en_vtc_44 : in STD_LOGIC;
    tx_inc_44 : in STD_LOGIC;
    tx_load_44 : in STD_LOGIC;
    rx_cntvalueout_44 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_44 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_44 : in STD_LOGIC;
    rx_en_vtc_44 : in STD_LOGIC;
    rx_inc_44 : in STD_LOGIC;
    rx_load_44 : in STD_LOGIC;
    rx_cntvalueout_ext_44 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_44 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_44 : in STD_LOGIC;
    rx_en_vtc_ext_44 : in STD_LOGIC;
    rx_inc_ext_44 : in STD_LOGIC;
    rx_load_ext_44 : in STD_LOGIC;
    fifo_empty_44 : out STD_LOGIC;
    fifo_rd_clk_44 : in STD_LOGIC;
    fifo_rd_en_44 : in STD_LOGIC;
    bitslip_error_44 : out STD_LOGIC;
    tri_t_45 : in STD_LOGIC;
    tx_cntvaluein_45 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_45 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_45 : in STD_LOGIC;
    tx_en_vtc_45 : in STD_LOGIC;
    tx_inc_45 : in STD_LOGIC;
    tx_load_45 : in STD_LOGIC;
    rx_cntvalueout_45 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_45 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_45 : in STD_LOGIC;
    rx_en_vtc_45 : in STD_LOGIC;
    rx_inc_45 : in STD_LOGIC;
    rx_load_45 : in STD_LOGIC;
    rx_cntvalueout_ext_45 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_45 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_45 : in STD_LOGIC;
    rx_en_vtc_ext_45 : in STD_LOGIC;
    rx_inc_ext_45 : in STD_LOGIC;
    rx_load_ext_45 : in STD_LOGIC;
    fifo_empty_45 : out STD_LOGIC;
    fifo_rd_clk_45 : in STD_LOGIC;
    fifo_rd_en_45 : in STD_LOGIC;
    bitslip_error_45 : out STD_LOGIC;
    tri_t_46 : in STD_LOGIC;
    tx_cntvaluein_46 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_46 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_46 : in STD_LOGIC;
    tx_en_vtc_46 : in STD_LOGIC;
    tx_inc_46 : in STD_LOGIC;
    tx_load_46 : in STD_LOGIC;
    rx_cntvalueout_46 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_46 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_46 : in STD_LOGIC;
    rx_en_vtc_46 : in STD_LOGIC;
    rx_inc_46 : in STD_LOGIC;
    rx_load_46 : in STD_LOGIC;
    rx_cntvalueout_ext_46 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_46 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_46 : in STD_LOGIC;
    rx_en_vtc_ext_46 : in STD_LOGIC;
    rx_inc_ext_46 : in STD_LOGIC;
    rx_load_ext_46 : in STD_LOGIC;
    fifo_empty_46 : out STD_LOGIC;
    fifo_rd_clk_46 : in STD_LOGIC;
    fifo_rd_en_46 : in STD_LOGIC;
    bitslip_error_46 : out STD_LOGIC;
    tri_t_47 : in STD_LOGIC;
    tx_cntvaluein_47 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_47 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_47 : in STD_LOGIC;
    tx_en_vtc_47 : in STD_LOGIC;
    tx_inc_47 : in STD_LOGIC;
    tx_load_47 : in STD_LOGIC;
    rx_cntvalueout_47 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_47 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_47 : in STD_LOGIC;
    rx_en_vtc_47 : in STD_LOGIC;
    rx_inc_47 : in STD_LOGIC;
    rx_load_47 : in STD_LOGIC;
    rx_cntvalueout_ext_47 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_47 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_47 : in STD_LOGIC;
    rx_en_vtc_ext_47 : in STD_LOGIC;
    rx_inc_ext_47 : in STD_LOGIC;
    rx_load_ext_47 : in STD_LOGIC;
    fifo_empty_47 : out STD_LOGIC;
    fifo_rd_clk_47 : in STD_LOGIC;
    fifo_rd_en_47 : in STD_LOGIC;
    bitslip_error_47 : out STD_LOGIC;
    tri_t_48 : in STD_LOGIC;
    tx_cntvaluein_48 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_48 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_48 : in STD_LOGIC;
    tx_en_vtc_48 : in STD_LOGIC;
    tx_inc_48 : in STD_LOGIC;
    tx_load_48 : in STD_LOGIC;
    rx_cntvalueout_48 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_48 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_48 : in STD_LOGIC;
    rx_en_vtc_48 : in STD_LOGIC;
    rx_inc_48 : in STD_LOGIC;
    rx_load_48 : in STD_LOGIC;
    rx_cntvalueout_ext_48 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_48 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_48 : in STD_LOGIC;
    rx_en_vtc_ext_48 : in STD_LOGIC;
    rx_inc_ext_48 : in STD_LOGIC;
    rx_load_ext_48 : in STD_LOGIC;
    fifo_empty_48 : out STD_LOGIC;
    fifo_rd_clk_48 : in STD_LOGIC;
    fifo_rd_en_48 : in STD_LOGIC;
    bitslip_error_48 : out STD_LOGIC;
    tri_t_49 : in STD_LOGIC;
    tx_cntvaluein_49 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_49 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_49 : in STD_LOGIC;
    tx_en_vtc_49 : in STD_LOGIC;
    tx_inc_49 : in STD_LOGIC;
    tx_load_49 : in STD_LOGIC;
    rx_cntvalueout_49 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_49 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_49 : in STD_LOGIC;
    rx_en_vtc_49 : in STD_LOGIC;
    rx_inc_49 : in STD_LOGIC;
    rx_load_49 : in STD_LOGIC;
    rx_cntvalueout_ext_49 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_49 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_49 : in STD_LOGIC;
    rx_en_vtc_ext_49 : in STD_LOGIC;
    rx_inc_ext_49 : in STD_LOGIC;
    rx_load_ext_49 : in STD_LOGIC;
    fifo_empty_49 : out STD_LOGIC;
    fifo_rd_clk_49 : in STD_LOGIC;
    fifo_rd_en_49 : in STD_LOGIC;
    bitslip_error_49 : out STD_LOGIC;
    tri_t_50 : in STD_LOGIC;
    tx_cntvaluein_50 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_50 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_50 : in STD_LOGIC;
    tx_en_vtc_50 : in STD_LOGIC;
    tx_inc_50 : in STD_LOGIC;
    tx_load_50 : in STD_LOGIC;
    rx_cntvalueout_50 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_50 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_50 : in STD_LOGIC;
    rx_en_vtc_50 : in STD_LOGIC;
    rx_inc_50 : in STD_LOGIC;
    rx_load_50 : in STD_LOGIC;
    rx_cntvalueout_ext_50 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_50 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_50 : in STD_LOGIC;
    rx_en_vtc_ext_50 : in STD_LOGIC;
    rx_inc_ext_50 : in STD_LOGIC;
    rx_load_ext_50 : in STD_LOGIC;
    fifo_empty_50 : out STD_LOGIC;
    fifo_rd_clk_50 : in STD_LOGIC;
    fifo_rd_en_50 : in STD_LOGIC;
    bitslip_error_50 : out STD_LOGIC;
    tri_t_51 : in STD_LOGIC;
    tx_cntvaluein_51 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_cntvalueout_51 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    tx_ce_51 : in STD_LOGIC;
    tx_en_vtc_51 : in STD_LOGIC;
    tx_inc_51 : in STD_LOGIC;
    tx_load_51 : in STD_LOGIC;
    rx_cntvalueout_51 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_51 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_51 : in STD_LOGIC;
    rx_en_vtc_51 : in STD_LOGIC;
    rx_inc_51 : in STD_LOGIC;
    rx_load_51 : in STD_LOGIC;
    rx_cntvalueout_ext_51 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_cntvaluein_ext_51 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rx_ce_ext_51 : in STD_LOGIC;
    rx_en_vtc_ext_51 : in STD_LOGIC;
    rx_inc_ext_51 : in STD_LOGIC;
    rx_load_ext_51 : in STD_LOGIC;
    fifo_empty_51 : out STD_LOGIC;
    fifo_rd_clk_51 : in STD_LOGIC;
    fifo_rd_en_51 : in STD_LOGIC;
    bitslip_error_51 : out STD_LOGIC;
    fifo_wr_clk_0 : out STD_LOGIC;
    fifo_wr_clk_6 : out STD_LOGIC;
    fifo_wr_clk_13 : out STD_LOGIC;
    fifo_wr_clk_19 : out STD_LOGIC;
    fifo_wr_clk_26 : out STD_LOGIC;
    fifo_wr_clk_32 : out STD_LOGIC;
    fifo_wr_clk_39 : out STD_LOGIC;
    fifo_wr_clk_45 : out STD_LOGIC;
    tri_tbyte0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    bidir_tx_bs_tri_cntvalueout0 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_cntvaluein0 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_en_vtc0 : in STD_LOGIC;
    bidir_tx_bs_tri_ce0 : in STD_LOGIC;
    bidir_tx_bs_tri_inc0 : in STD_LOGIC;
    bidir_tx_bs_tri_load0 : in STD_LOGIC;
    tri_tbyte1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    bidir_tx_bs_tri_cntvalueout1 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_cntvaluein1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_en_vtc1 : in STD_LOGIC;
    bidir_tx_bs_tri_ce1 : in STD_LOGIC;
    bidir_tx_bs_tri_inc1 : in STD_LOGIC;
    bidir_tx_bs_tri_load1 : in STD_LOGIC;
    tri_tbyte2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    bidir_tx_bs_tri_cntvalueout2 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_cntvaluein2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_en_vtc2 : in STD_LOGIC;
    bidir_tx_bs_tri_ce2 : in STD_LOGIC;
    bidir_tx_bs_tri_inc2 : in STD_LOGIC;
    bidir_tx_bs_tri_load2 : in STD_LOGIC;
    tri_tbyte3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    bidir_tx_bs_tri_cntvalueout3 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_cntvaluein3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_en_vtc3 : in STD_LOGIC;
    bidir_tx_bs_tri_ce3 : in STD_LOGIC;
    bidir_tx_bs_tri_inc3 : in STD_LOGIC;
    bidir_tx_bs_tri_load3 : in STD_LOGIC;
    tri_tbyte4 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    bidir_tx_bs_tri_cntvalueout4 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_cntvaluein4 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_en_vtc4 : in STD_LOGIC;
    bidir_tx_bs_tri_ce4 : in STD_LOGIC;
    bidir_tx_bs_tri_inc4 : in STD_LOGIC;
    bidir_tx_bs_tri_load4 : in STD_LOGIC;
    tri_tbyte5 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    bidir_tx_bs_tri_cntvalueout5 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_cntvaluein5 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_en_vtc5 : in STD_LOGIC;
    bidir_tx_bs_tri_ce5 : in STD_LOGIC;
    bidir_tx_bs_tri_inc5 : in STD_LOGIC;
    bidir_tx_bs_tri_load5 : in STD_LOGIC;
    tri_tbyte6 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    bidir_tx_bs_tri_cntvalueout6 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_cntvaluein6 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_en_vtc6 : in STD_LOGIC;
    bidir_tx_bs_tri_ce6 : in STD_LOGIC;
    bidir_tx_bs_tri_inc6 : in STD_LOGIC;
    bidir_tx_bs_tri_load6 : in STD_LOGIC;
    tri_tbyte7 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    bidir_tx_bs_tri_cntvalueout7 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_cntvaluein7 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    bidir_tx_bs_tri_en_vtc7 : in STD_LOGIC;
    bidir_tx_bs_tri_ce7 : in STD_LOGIC;
    bidir_tx_bs_tri_inc7 : in STD_LOGIC;
    bidir_tx_bs_tri_load7 : in STD_LOGIC;
    fifo_rd_data_valid : out STD_LOGIC;
    rst : in STD_LOGIC
  );
  attribute C_ALL_EN_PIN_INFO : string;
  attribute C_ALL_EN_PIN_INFO of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "0 {nibble 0 dir RX sig_type DIFF data_strb Strobe data_strb_org Strobe sig_name clk_rxp loc T3} 1 {nibble 0 dir RX sig_type DIFF data_strb Strobe data_strb_org Strobe sig_name clk_rxn loc T2} 2 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp0 loc P3} 3 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn0 loc R3} 4 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp1 loc U2} 5 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn1 loc U1} 6 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp2 loc R4} 7 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn2 loc T4} 8 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp3 loc R1} 9 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn3 loc T1}";
  attribute C_ALL_RX_EN : string;
  attribute C_ALL_RX_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "52'b0000000000000000000000000000000000000000001111111111";
  attribute C_BANK : integer;
  attribute C_BANK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 65;
  attribute C_BIDIR_BITSLICE_EN : string;
  attribute C_BIDIR_BITSLICE_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "52'b0000000000000000000000000000000000000000000000000000";
  attribute C_BIDIR_FIFO_SYNC_MODE : string;
  attribute C_BIDIR_FIFO_SYNC_MODE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "FALSE";
  attribute C_BIDIR_IS_RX_CLK_INVERTED : string;
  attribute C_BIDIR_IS_RX_CLK_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_BIDIR_IS_RX_RST_DLY_INVERTED : string;
  attribute C_BIDIR_IS_RX_RST_DLY_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_BIDIR_IS_RX_RST_INVERTED : string;
  attribute C_BIDIR_IS_RX_RST_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_BIDIR_IS_TX_CLK_INVERTED : string;
  attribute C_BIDIR_IS_TX_CLK_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_BIDIR_IS_TX_RST_DLY_INVERTED : string;
  attribute C_BIDIR_IS_TX_RST_DLY_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_BIDIR_IS_TX_RST_INVERTED : string;
  attribute C_BIDIR_IS_TX_RST_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_BIDIR_RX_DELAY_FORMAT : string;
  attribute C_BIDIR_RX_DELAY_FORMAT of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "TIME";
  attribute C_BIDIR_TX_DELAY_FORMAT : string;
  attribute C_BIDIR_TX_DELAY_FORMAT of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "TIME";
  attribute C_BITSLIP_MODE : string;
  attribute C_BITSLIP_MODE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "SLIP_PER_BIT";
  attribute C_BITSLIP_VAL : string;
  attribute C_BITSLIP_VAL of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "8'b00101100";
  attribute C_BS0_INFO : string;
  attribute C_BS0_INFO of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "0 {name bg0_pin0_nc loc T3} 1 {name bg0_pin6_nc loc R4} 2 {name bg1_pin0_nc loc N2} 3 {name bg1_pin6_nc loc M5} 4 {name bg2_pin0_nc loc J3} 5 {name bg2_pin6_nc loc J5} 6 {name bg3_pin0_nc loc G1} 7 {name bg3_pin6_nc loc D3}";
  attribute C_BSC_CTRL_CLK : string;
  attribute C_BSC_CTRL_CLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "EXTERNAL";
  attribute C_BSC_EN_DYN_ODLY_MODE : string;
  attribute C_BSC_EN_DYN_ODLY_MODE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "FALSE";
  attribute C_BSC_IDLY_VT_TRACK : string;
  attribute C_BSC_IDLY_VT_TRACK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "TRUE";
  attribute C_BSC_ODLY_VT_TRACK : string;
  attribute C_BSC_ODLY_VT_TRACK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "TRUE";
  attribute C_BSC_QDLY_VT_TRACK : string;
  attribute C_BSC_QDLY_VT_TRACK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "TRUE";
  attribute C_BSC_READ_IDLE_COUNT : string;
  attribute C_BSC_READ_IDLE_COUNT of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "6'b000000";
  attribute C_BSC_REFCLK_SRC : string;
  attribute C_BSC_REFCLK_SRC of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "PLLCLK";
  attribute C_BSC_ROUNDING_FACTOR : integer;
  attribute C_BSC_ROUNDING_FACTOR of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 16;
  attribute C_BSC_RXGATE_EXTEND : string;
  attribute C_BSC_RXGATE_EXTEND of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "FALSE";
  attribute C_BSC_RX_GATING : string;
  attribute C_BSC_RX_GATING of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "DISABLE";
  attribute C_BSC_SELF_CALIBRATE : string;
  attribute C_BSC_SELF_CALIBRATE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "ENABLE";
  attribute C_BSC_SIM_SPEEDUP : string;
  attribute C_BSC_SIM_SPEEDUP of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "FAST";
  attribute C_BS_INIT_VAL : string;
  attribute C_BS_INIT_VAL of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "52'b0000000000000000000000000000000000000000000000000000";
  attribute C_CLKIN_DIFF_EN : integer;
  attribute C_CLKIN_DIFF_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_CLKIN_PERIOD : string;
  attribute C_CLKIN_PERIOD of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "5.000000";
  attribute C_CLK_FWD : integer;
  attribute C_CLK_FWD of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_CLK_FWD_BITSLICE_NO : integer;
  attribute C_CLK_FWD_BITSLICE_NO of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_CLK_FWD_ENABLE : string;
  attribute C_CLK_FWD_ENABLE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "52'b0000000000000000000000000000000000000000000000000000";
  attribute C_CLK_FWD_PHASE : integer;
  attribute C_CLK_FWD_PHASE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_CLK_SIG_TYPE : string;
  attribute C_CLK_SIG_TYPE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "SINGLE";
  attribute C_CLOCK_TRI : integer;
  attribute C_CLOCK_TRI of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 1;
  attribute C_DATA_PIN_EN : integer;
  attribute C_DATA_PIN_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 5;
  attribute C_DATA_TRI : integer;
  attribute C_DATA_TRI of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 1;
  attribute C_DEVICE : string;
  attribute C_DEVICE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "xczu1cg";
  attribute C_DEVICE_FAMILY : string;
  attribute C_DEVICE_FAMILY of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "zynquplus";
  attribute C_DIFFERENTIAL_IO_STD : string;
  attribute C_DIFFERENTIAL_IO_STD of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "MIPI_DPHY_DCI";
  attribute C_DIFFERENTIAL_IO_TERMINATION : string;
  attribute C_DIFFERENTIAL_IO_TERMINATION of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "TERM_100";
  attribute C_DIFF_EN : string;
  attribute C_DIFF_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "52'b0000000000000000000000000000000000000000001111111111";
  attribute C_DIV_MODE : string;
  attribute C_DIV_MODE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "DIV4";
  attribute C_ENABLE_BITSLIP : integer;
  attribute C_ENABLE_BITSLIP of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_ENABLE_DATA_BITSLIP : integer;
  attribute C_ENABLE_DATA_BITSLIP of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_ENABLE_N_PINS : integer;
  attribute C_ENABLE_N_PINS of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 1;
  attribute C_ENABLE_PLL0_PLLOUT1 : integer;
  attribute C_ENABLE_PLL0_PLLOUT1 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_ENABLE_PLL0_PLLOUTFB : integer;
  attribute C_ENABLE_PLL0_PLLOUTFB of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_ENABLE_RIU_INTERFACE : integer;
  attribute C_ENABLE_RIU_INTERFACE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_ENABLE_RIU_SPLIT : integer;
  attribute C_ENABLE_RIU_SPLIT of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_ENABLE_TX_TRI : integer;
  attribute C_ENABLE_TX_TRI of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_EN_BIDIR : integer;
  attribute C_EN_BIDIR of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_EN_BSC0 : integer;
  attribute C_EN_BSC0 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 1;
  attribute C_EN_BSC1 : integer;
  attribute C_EN_BSC1 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 1;
  attribute C_EN_BSC2 : integer;
  attribute C_EN_BSC2 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_EN_BSC3 : integer;
  attribute C_EN_BSC3 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_EN_BSC4 : integer;
  attribute C_EN_BSC4 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_EN_BSC5 : integer;
  attribute C_EN_BSC5 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_EN_BSC6 : integer;
  attribute C_EN_BSC6 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_EN_BSC7 : integer;
  attribute C_EN_BSC7 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_EN_MULTI_INTF_PORTS : integer;
  attribute C_EN_MULTI_INTF_PORTS of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_EN_RIU_OR0 : string;
  attribute C_EN_RIU_OR0 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "TRUE";
  attribute C_EN_RIU_OR1 : string;
  attribute C_EN_RIU_OR1 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "FALSE";
  attribute C_EN_RIU_OR2 : string;
  attribute C_EN_RIU_OR2 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "FALSE";
  attribute C_EN_RIU_OR3 : string;
  attribute C_EN_RIU_OR3 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "FALSE";
  attribute C_EN_RX : integer;
  attribute C_EN_RX of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 1;
  attribute C_EN_TX : integer;
  attribute C_EN_TX of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_EN_VTC : integer;
  attribute C_EN_VTC of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_EXDES_BANK : string;
  attribute C_EXDES_BANK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "";
  attribute C_EX_CLK_FREQ : string;
  attribute C_EX_CLK_FREQ of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "200.000000";
  attribute C_EX_INST_GEN : integer;
  attribute C_EX_INST_GEN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_FIFO_SYNC_MODE : integer;
  attribute C_FIFO_SYNC_MODE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 1;
  attribute C_GC_LOC : string;
  attribute C_GC_LOC of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "21 {name IO_L11P_T1U_N8_GC_65 loc L2} 23 {name IO_L12P_T1U_N10_GC_65 loc L4} 28 {name IO_L14P_T2L_N2_GC_65 loc K4}";
  attribute C_INCLK_LOC : string;
  attribute C_INCLK_LOC of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "NONE";
  attribute C_INCLK_PIN : integer;
  attribute C_INCLK_PIN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 100;
  attribute C_INV_RX_CLK : string;
  attribute C_INV_RX_CLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "8'b00000000";
  attribute C_NIB0_BS0_EN : integer;
  attribute C_NIB0_BS0_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIB0_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB0_EN_CLK_TO_EXT_NORTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB0_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB0_EN_CLK_TO_EXT_SOUTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB0_EN_OTHER_NCLK : string;
  attribute C_NIB0_EN_OTHER_NCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB0_EN_OTHER_PCLK : string;
  attribute C_NIB0_EN_OTHER_PCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB1_BS0_EN : integer;
  attribute C_NIB1_BS0_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIB1_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB1_EN_CLK_TO_EXT_NORTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB1_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB1_EN_CLK_TO_EXT_SOUTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB1_EN_OTHER_NCLK : string;
  attribute C_NIB1_EN_OTHER_NCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b1";
  attribute C_NIB1_EN_OTHER_PCLK : string;
  attribute C_NIB1_EN_OTHER_PCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b1";
  attribute C_NIB2_BS0_EN : integer;
  attribute C_NIB2_BS0_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIB2_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB2_EN_CLK_TO_EXT_NORTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB2_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB2_EN_CLK_TO_EXT_SOUTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB2_EN_OTHER_NCLK : string;
  attribute C_NIB2_EN_OTHER_NCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB2_EN_OTHER_PCLK : string;
  attribute C_NIB2_EN_OTHER_PCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB3_BS0_EN : integer;
  attribute C_NIB3_BS0_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIB3_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB3_EN_CLK_TO_EXT_NORTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB3_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB3_EN_CLK_TO_EXT_SOUTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB3_EN_OTHER_NCLK : string;
  attribute C_NIB3_EN_OTHER_NCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB3_EN_OTHER_PCLK : string;
  attribute C_NIB3_EN_OTHER_PCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB4_BS0_EN : integer;
  attribute C_NIB4_BS0_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIB4_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB4_EN_CLK_TO_EXT_NORTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB4_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB4_EN_CLK_TO_EXT_SOUTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB4_EN_OTHER_NCLK : string;
  attribute C_NIB4_EN_OTHER_NCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB4_EN_OTHER_PCLK : string;
  attribute C_NIB4_EN_OTHER_PCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB5_BS0_EN : integer;
  attribute C_NIB5_BS0_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIB5_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB5_EN_CLK_TO_EXT_NORTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB5_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB5_EN_CLK_TO_EXT_SOUTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB5_EN_OTHER_NCLK : string;
  attribute C_NIB5_EN_OTHER_NCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB5_EN_OTHER_PCLK : string;
  attribute C_NIB5_EN_OTHER_PCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB6_BS0_EN : integer;
  attribute C_NIB6_BS0_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIB6_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB6_EN_CLK_TO_EXT_NORTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB6_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB6_EN_CLK_TO_EXT_SOUTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB6_EN_OTHER_NCLK : string;
  attribute C_NIB6_EN_OTHER_NCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB6_EN_OTHER_PCLK : string;
  attribute C_NIB6_EN_OTHER_PCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB7_BS0_EN : integer;
  attribute C_NIB7_BS0_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIB7_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB7_EN_CLK_TO_EXT_NORTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB7_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB7_EN_CLK_TO_EXT_SOUTH of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB7_EN_OTHER_NCLK : string;
  attribute C_NIB7_EN_OTHER_NCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIB7_EN_OTHER_PCLK : string;
  attribute C_NIB7_EN_OTHER_PCLK of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_NIBBLE0_TRI : integer;
  attribute C_NIBBLE0_TRI of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIBBLE1_TRI : integer;
  attribute C_NIBBLE1_TRI of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIBBLE2_TRI : integer;
  attribute C_NIBBLE2_TRI of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIBBLE3_TRI : integer;
  attribute C_NIBBLE3_TRI of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIBBLE4_TRI : integer;
  attribute C_NIBBLE4_TRI of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIBBLE5_TRI : integer;
  attribute C_NIBBLE5_TRI of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIBBLE6_TRI : integer;
  attribute C_NIBBLE6_TRI of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_NIBBLE7_TRI : integer;
  attribute C_NIBBLE7_TRI of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_PIN_INFO : string;
  attribute C_PIN_INFO of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "0 {nibble 0 dir RX sig_type DIFF data_strb Strobe data_strb_org Strobe sig_name clk_rxp loc T3} 1 {nibble 0 dir RX sig_type DIFF data_strb Strobe data_strb_org Strobe sig_name clk_rxn loc T2} 2 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp0 loc P3} 3 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn0 loc R3} 4 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp1 loc U2} 5 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn1 loc U1} 6 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp2 loc R4} 7 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn2 loc T4} 8 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp3 loc R1} 9 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn3 loc T1}";
  attribute C_PLL0_CLK0_PHASE : string;
  attribute C_PLL0_CLK0_PHASE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "0.000000";
  attribute C_PLL0_CLK1_PHASE : string;
  attribute C_PLL0_CLK1_PHASE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "0.000000";
  attribute C_PLL0_CLKFBOUT_MULT : integer;
  attribute C_PLL0_CLKFBOUT_MULT of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 15;
  attribute C_PLL0_CLKOUT1_DIVIDE : integer;
  attribute C_PLL0_CLKOUT1_DIVIDE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 1;
  attribute C_PLL0_CLKOUTPHY_MODE : string;
  attribute C_PLL0_CLKOUTPHY_MODE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "VCO";
  attribute C_PLL0_CLK_SOURCE : string;
  attribute C_PLL0_CLK_SOURCE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "BUFG_TO_PLL";
  attribute C_PLL0_DIVCLK_DIVIDE : integer;
  attribute C_PLL0_DIVCLK_DIVIDE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 2;
  attribute C_PLL0_DIV_FACTOR : string;
  attribute C_PLL0_DIV_FACTOR of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1.000000";
  attribute C_PLL0_FIFO_WRITE_CLK_EN : integer;
  attribute C_PLL0_FIFO_WRITE_CLK_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 1;
  attribute C_PLL0_MMCM_CLKFBOUT_MULT_F : string;
  attribute C_PLL0_MMCM_CLKFBOUT_MULT_F of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "7.875000";
  attribute C_PLL0_MMCM_CLKOUT0_DIVIDE_F : string;
  attribute C_PLL0_MMCM_CLKOUT0_DIVIDE_F of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "7.875000";
  attribute C_PLL0_MMCM_DIVCLK_DIVIDE : integer;
  attribute C_PLL0_MMCM_DIVCLK_DIVIDE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 1;
  attribute C_PLL0_RX_EXTERNAL_CLK_TO_DATA : integer;
  attribute C_PLL0_RX_EXTERNAL_CLK_TO_DATA of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 3;
  attribute C_PLL1_CLK0_PHASE : string;
  attribute C_PLL1_CLK0_PHASE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "0.000000";
  attribute C_PLL1_CLK1_PHASE : string;
  attribute C_PLL1_CLK1_PHASE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "0.000000";
  attribute C_PLL1_CLKFBOUT_MULT : integer;
  attribute C_PLL1_CLKFBOUT_MULT of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 15;
  attribute C_PLL1_CLKOUTPHY_MODE : string;
  attribute C_PLL1_CLKOUTPHY_MODE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "VCO";
  attribute C_PLL1_DIVCLK_DIVIDE : integer;
  attribute C_PLL1_DIVCLK_DIVIDE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 2;
  attribute C_PLL1_DIV_FACTOR : string;
  attribute C_PLL1_DIV_FACTOR of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1.000000";
  attribute C_PLL_SHARING : integer;
  attribute C_PLL_SHARING of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_PLL_VCOMIN : string;
  attribute C_PLL_VCOMIN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "750.000000";
  attribute C_REC_IN_FREQ : string;
  attribute C_REC_IN_FREQ of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "93.750";
  attribute C_RX_BITSLICE0_EN : string;
  attribute C_RX_BITSLICE0_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "8'b00000000";
  attribute C_RX_BITSLICE_EN : string;
  attribute C_RX_BITSLICE_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "52'b0000000000000000000000000000000000000000001111111111";
  attribute C_RX_DELAY_CASCADE : integer;
  attribute C_RX_DELAY_CASCADE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_RX_DELAY_FORMAT : string;
  attribute C_RX_DELAY_FORMAT of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "TIME";
  attribute C_RX_DELAY_TYPE : string;
  attribute C_RX_DELAY_TYPE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE0 : string;
  attribute C_RX_DELAY_TYPE0 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE1 : string;
  attribute C_RX_DELAY_TYPE1 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE10 : string;
  attribute C_RX_DELAY_TYPE10 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE11 : string;
  attribute C_RX_DELAY_TYPE11 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE12 : string;
  attribute C_RX_DELAY_TYPE12 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE13 : string;
  attribute C_RX_DELAY_TYPE13 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE14 : string;
  attribute C_RX_DELAY_TYPE14 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE15 : string;
  attribute C_RX_DELAY_TYPE15 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE16 : string;
  attribute C_RX_DELAY_TYPE16 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE17 : string;
  attribute C_RX_DELAY_TYPE17 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE18 : string;
  attribute C_RX_DELAY_TYPE18 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE19 : string;
  attribute C_RX_DELAY_TYPE19 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE2 : string;
  attribute C_RX_DELAY_TYPE2 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE20 : string;
  attribute C_RX_DELAY_TYPE20 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE21 : string;
  attribute C_RX_DELAY_TYPE21 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE22 : string;
  attribute C_RX_DELAY_TYPE22 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE23 : string;
  attribute C_RX_DELAY_TYPE23 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE24 : string;
  attribute C_RX_DELAY_TYPE24 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE25 : string;
  attribute C_RX_DELAY_TYPE25 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE26 : string;
  attribute C_RX_DELAY_TYPE26 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE27 : string;
  attribute C_RX_DELAY_TYPE27 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE28 : string;
  attribute C_RX_DELAY_TYPE28 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE29 : string;
  attribute C_RX_DELAY_TYPE29 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE3 : string;
  attribute C_RX_DELAY_TYPE3 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE30 : string;
  attribute C_RX_DELAY_TYPE30 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE31 : string;
  attribute C_RX_DELAY_TYPE31 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE32 : string;
  attribute C_RX_DELAY_TYPE32 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE33 : string;
  attribute C_RX_DELAY_TYPE33 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE34 : string;
  attribute C_RX_DELAY_TYPE34 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE35 : string;
  attribute C_RX_DELAY_TYPE35 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE36 : string;
  attribute C_RX_DELAY_TYPE36 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE37 : string;
  attribute C_RX_DELAY_TYPE37 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE38 : string;
  attribute C_RX_DELAY_TYPE38 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE39 : string;
  attribute C_RX_DELAY_TYPE39 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE4 : string;
  attribute C_RX_DELAY_TYPE4 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE40 : string;
  attribute C_RX_DELAY_TYPE40 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE41 : string;
  attribute C_RX_DELAY_TYPE41 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE42 : string;
  attribute C_RX_DELAY_TYPE42 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE43 : string;
  attribute C_RX_DELAY_TYPE43 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE44 : string;
  attribute C_RX_DELAY_TYPE44 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE45 : string;
  attribute C_RX_DELAY_TYPE45 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE46 : string;
  attribute C_RX_DELAY_TYPE46 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE47 : string;
  attribute C_RX_DELAY_TYPE47 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE48 : string;
  attribute C_RX_DELAY_TYPE48 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE49 : string;
  attribute C_RX_DELAY_TYPE49 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE5 : string;
  attribute C_RX_DELAY_TYPE5 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE50 : string;
  attribute C_RX_DELAY_TYPE50 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE51 : string;
  attribute C_RX_DELAY_TYPE51 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE6 : string;
  attribute C_RX_DELAY_TYPE6 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE7 : string;
  attribute C_RX_DELAY_TYPE7 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE8 : string;
  attribute C_RX_DELAY_TYPE8 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_TYPE9 : string;
  attribute C_RX_DELAY_TYPE9 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_RX_DELAY_VALUE : string;
  attribute C_RX_DELAY_VALUE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE0 : string;
  attribute C_RX_DELAY_VALUE0 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE1 : string;
  attribute C_RX_DELAY_VALUE1 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE10 : string;
  attribute C_RX_DELAY_VALUE10 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE11 : string;
  attribute C_RX_DELAY_VALUE11 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE12 : string;
  attribute C_RX_DELAY_VALUE12 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE13 : string;
  attribute C_RX_DELAY_VALUE13 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE14 : string;
  attribute C_RX_DELAY_VALUE14 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE15 : string;
  attribute C_RX_DELAY_VALUE15 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE16 : string;
  attribute C_RX_DELAY_VALUE16 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE17 : string;
  attribute C_RX_DELAY_VALUE17 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE18 : string;
  attribute C_RX_DELAY_VALUE18 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE19 : string;
  attribute C_RX_DELAY_VALUE19 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE2 : string;
  attribute C_RX_DELAY_VALUE2 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE20 : string;
  attribute C_RX_DELAY_VALUE20 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE21 : string;
  attribute C_RX_DELAY_VALUE21 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE22 : string;
  attribute C_RX_DELAY_VALUE22 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE23 : string;
  attribute C_RX_DELAY_VALUE23 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE24 : string;
  attribute C_RX_DELAY_VALUE24 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE25 : string;
  attribute C_RX_DELAY_VALUE25 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE26 : string;
  attribute C_RX_DELAY_VALUE26 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE27 : string;
  attribute C_RX_DELAY_VALUE27 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE28 : string;
  attribute C_RX_DELAY_VALUE28 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE29 : string;
  attribute C_RX_DELAY_VALUE29 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE3 : string;
  attribute C_RX_DELAY_VALUE3 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE30 : string;
  attribute C_RX_DELAY_VALUE30 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE31 : string;
  attribute C_RX_DELAY_VALUE31 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE32 : string;
  attribute C_RX_DELAY_VALUE32 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE33 : string;
  attribute C_RX_DELAY_VALUE33 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE34 : string;
  attribute C_RX_DELAY_VALUE34 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE35 : string;
  attribute C_RX_DELAY_VALUE35 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE36 : string;
  attribute C_RX_DELAY_VALUE36 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE37 : string;
  attribute C_RX_DELAY_VALUE37 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE38 : string;
  attribute C_RX_DELAY_VALUE38 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE39 : string;
  attribute C_RX_DELAY_VALUE39 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE4 : string;
  attribute C_RX_DELAY_VALUE4 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE40 : string;
  attribute C_RX_DELAY_VALUE40 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE41 : string;
  attribute C_RX_DELAY_VALUE41 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE42 : string;
  attribute C_RX_DELAY_VALUE42 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE43 : string;
  attribute C_RX_DELAY_VALUE43 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE44 : string;
  attribute C_RX_DELAY_VALUE44 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE45 : string;
  attribute C_RX_DELAY_VALUE45 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE46 : string;
  attribute C_RX_DELAY_VALUE46 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE47 : string;
  attribute C_RX_DELAY_VALUE47 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE48 : string;
  attribute C_RX_DELAY_VALUE48 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE49 : string;
  attribute C_RX_DELAY_VALUE49 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE5 : string;
  attribute C_RX_DELAY_VALUE5 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE50 : string;
  attribute C_RX_DELAY_VALUE50 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE51 : string;
  attribute C_RX_DELAY_VALUE51 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE6 : string;
  attribute C_RX_DELAY_VALUE6 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE7 : string;
  attribute C_RX_DELAY_VALUE7 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE8 : string;
  attribute C_RX_DELAY_VALUE8 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE9 : string;
  attribute C_RX_DELAY_VALUE9 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT0 : string;
  attribute C_RX_DELAY_VALUE_EXT0 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT1 : string;
  attribute C_RX_DELAY_VALUE_EXT1 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT10 : string;
  attribute C_RX_DELAY_VALUE_EXT10 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT11 : string;
  attribute C_RX_DELAY_VALUE_EXT11 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT12 : string;
  attribute C_RX_DELAY_VALUE_EXT12 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT13 : string;
  attribute C_RX_DELAY_VALUE_EXT13 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT14 : string;
  attribute C_RX_DELAY_VALUE_EXT14 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT15 : string;
  attribute C_RX_DELAY_VALUE_EXT15 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT16 : string;
  attribute C_RX_DELAY_VALUE_EXT16 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT17 : string;
  attribute C_RX_DELAY_VALUE_EXT17 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT18 : string;
  attribute C_RX_DELAY_VALUE_EXT18 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT19 : string;
  attribute C_RX_DELAY_VALUE_EXT19 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT2 : string;
  attribute C_RX_DELAY_VALUE_EXT2 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT20 : string;
  attribute C_RX_DELAY_VALUE_EXT20 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT21 : string;
  attribute C_RX_DELAY_VALUE_EXT21 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT22 : string;
  attribute C_RX_DELAY_VALUE_EXT22 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT23 : string;
  attribute C_RX_DELAY_VALUE_EXT23 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT24 : string;
  attribute C_RX_DELAY_VALUE_EXT24 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT25 : string;
  attribute C_RX_DELAY_VALUE_EXT25 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT26 : string;
  attribute C_RX_DELAY_VALUE_EXT26 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT27 : string;
  attribute C_RX_DELAY_VALUE_EXT27 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT28 : string;
  attribute C_RX_DELAY_VALUE_EXT28 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT29 : string;
  attribute C_RX_DELAY_VALUE_EXT29 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT3 : string;
  attribute C_RX_DELAY_VALUE_EXT3 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT30 : string;
  attribute C_RX_DELAY_VALUE_EXT30 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT31 : string;
  attribute C_RX_DELAY_VALUE_EXT31 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT32 : string;
  attribute C_RX_DELAY_VALUE_EXT32 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT33 : string;
  attribute C_RX_DELAY_VALUE_EXT33 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT34 : string;
  attribute C_RX_DELAY_VALUE_EXT34 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT35 : string;
  attribute C_RX_DELAY_VALUE_EXT35 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT36 : string;
  attribute C_RX_DELAY_VALUE_EXT36 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT37 : string;
  attribute C_RX_DELAY_VALUE_EXT37 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT38 : string;
  attribute C_RX_DELAY_VALUE_EXT38 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT39 : string;
  attribute C_RX_DELAY_VALUE_EXT39 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT4 : string;
  attribute C_RX_DELAY_VALUE_EXT4 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT40 : string;
  attribute C_RX_DELAY_VALUE_EXT40 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT41 : string;
  attribute C_RX_DELAY_VALUE_EXT41 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT42 : string;
  attribute C_RX_DELAY_VALUE_EXT42 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT43 : string;
  attribute C_RX_DELAY_VALUE_EXT43 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT44 : string;
  attribute C_RX_DELAY_VALUE_EXT44 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT45 : string;
  attribute C_RX_DELAY_VALUE_EXT45 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT46 : string;
  attribute C_RX_DELAY_VALUE_EXT46 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT47 : string;
  attribute C_RX_DELAY_VALUE_EXT47 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT48 : string;
  attribute C_RX_DELAY_VALUE_EXT48 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT49 : string;
  attribute C_RX_DELAY_VALUE_EXT49 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT5 : string;
  attribute C_RX_DELAY_VALUE_EXT5 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT50 : string;
  attribute C_RX_DELAY_VALUE_EXT50 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT51 : string;
  attribute C_RX_DELAY_VALUE_EXT51 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT6 : string;
  attribute C_RX_DELAY_VALUE_EXT6 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT7 : string;
  attribute C_RX_DELAY_VALUE_EXT7 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT8 : string;
  attribute C_RX_DELAY_VALUE_EXT8 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT9 : string;
  attribute C_RX_DELAY_VALUE_EXT9 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_RX_EQUALIZATION_D : string;
  attribute C_RX_EQUALIZATION_D of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "EQ_NONE";
  attribute C_RX_EQUALIZATION_S : string;
  attribute C_RX_EQUALIZATION_S of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "NONE";
  attribute C_RX_FIFO_SYNC_MODE : string;
  attribute C_RX_FIFO_SYNC_MODE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "FALSE";
  attribute C_RX_IS_CLK_EXT_INVERTED : string;
  attribute C_RX_IS_CLK_EXT_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_RX_IS_CLK_INVERTED : string;
  attribute C_RX_IS_CLK_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_RX_IS_RST_DLY_EXT_INVERTED : string;
  attribute C_RX_IS_RST_DLY_EXT_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_RX_IS_RST_DLY_INVERTED : string;
  attribute C_RX_IS_RST_DLY_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_RX_IS_RST_INVERTED : string;
  attribute C_RX_IS_RST_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_RX_PIN_EN : string;
  attribute C_RX_PIN_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "52'b0000000000000000000000000000000000000000000101010101";
  attribute C_RX_REFCLK_FREQ : string;
  attribute C_RX_REFCLK_FREQ of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1500.000000";
  attribute C_RX_STROBE_EN : string;
  attribute C_RX_STROBE_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "16'b0000000000000011";
  attribute C_SERIALIZATION_FACTOR : integer;
  attribute C_SERIALIZATION_FACTOR of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 8;
  attribute C_SERIAL_MODE : string;
  attribute C_SERIAL_MODE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "FALSE";
  attribute C_SIM_DEVICE : string;
  attribute C_SIM_DEVICE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "ULTRASCALE_PLUS_ES1";
  attribute C_SIM_VERSION : string;
  attribute C_SIM_VERSION of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2.000000";
  attribute C_SINGLE_ENDED_IO_STD : string;
  attribute C_SINGLE_ENDED_IO_STD of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "NONE";
  attribute C_SINGLE_ENDED_IO_TERMINATION : string;
  attribute C_SINGLE_ENDED_IO_TERMINATION of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "NONE";
  attribute C_STRB_INFO : string;
  attribute C_STRB_INFO of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "9 99 9 9 9 9 9 9 9 9 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99";
  attribute C_TEMPLATE : integer;
  attribute C_TEMPLATE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 2;
  attribute C_TX_BITSLICE_EN : string;
  attribute C_TX_BITSLICE_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "52'b0000000000000000000000000000000000000000000000000000";
  attribute C_TX_DATA_PHASE : integer;
  attribute C_TX_DATA_PHASE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_TX_DELAY_FORMAT : string;
  attribute C_TX_DELAY_FORMAT of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "TIME";
  attribute C_TX_DELAY_TYPE : integer;
  attribute C_TX_DELAY_TYPE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is 0;
  attribute C_TX_DELAY_TYPE0 : string;
  attribute C_TX_DELAY_TYPE0 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE1 : string;
  attribute C_TX_DELAY_TYPE1 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE10 : string;
  attribute C_TX_DELAY_TYPE10 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE11 : string;
  attribute C_TX_DELAY_TYPE11 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE12 : string;
  attribute C_TX_DELAY_TYPE12 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE13 : string;
  attribute C_TX_DELAY_TYPE13 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE14 : string;
  attribute C_TX_DELAY_TYPE14 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE15 : string;
  attribute C_TX_DELAY_TYPE15 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE16 : string;
  attribute C_TX_DELAY_TYPE16 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE17 : string;
  attribute C_TX_DELAY_TYPE17 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE18 : string;
  attribute C_TX_DELAY_TYPE18 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE19 : string;
  attribute C_TX_DELAY_TYPE19 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE2 : string;
  attribute C_TX_DELAY_TYPE2 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE20 : string;
  attribute C_TX_DELAY_TYPE20 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE21 : string;
  attribute C_TX_DELAY_TYPE21 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE22 : string;
  attribute C_TX_DELAY_TYPE22 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE23 : string;
  attribute C_TX_DELAY_TYPE23 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE24 : string;
  attribute C_TX_DELAY_TYPE24 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE25 : string;
  attribute C_TX_DELAY_TYPE25 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE26 : string;
  attribute C_TX_DELAY_TYPE26 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE27 : string;
  attribute C_TX_DELAY_TYPE27 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE28 : string;
  attribute C_TX_DELAY_TYPE28 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE29 : string;
  attribute C_TX_DELAY_TYPE29 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE3 : string;
  attribute C_TX_DELAY_TYPE3 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE30 : string;
  attribute C_TX_DELAY_TYPE30 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE31 : string;
  attribute C_TX_DELAY_TYPE31 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE32 : string;
  attribute C_TX_DELAY_TYPE32 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE33 : string;
  attribute C_TX_DELAY_TYPE33 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE34 : string;
  attribute C_TX_DELAY_TYPE34 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE35 : string;
  attribute C_TX_DELAY_TYPE35 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE36 : string;
  attribute C_TX_DELAY_TYPE36 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE37 : string;
  attribute C_TX_DELAY_TYPE37 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE38 : string;
  attribute C_TX_DELAY_TYPE38 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE39 : string;
  attribute C_TX_DELAY_TYPE39 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE4 : string;
  attribute C_TX_DELAY_TYPE4 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE40 : string;
  attribute C_TX_DELAY_TYPE40 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE41 : string;
  attribute C_TX_DELAY_TYPE41 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE42 : string;
  attribute C_TX_DELAY_TYPE42 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE43 : string;
  attribute C_TX_DELAY_TYPE43 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE44 : string;
  attribute C_TX_DELAY_TYPE44 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE45 : string;
  attribute C_TX_DELAY_TYPE45 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE46 : string;
  attribute C_TX_DELAY_TYPE46 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE47 : string;
  attribute C_TX_DELAY_TYPE47 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE48 : string;
  attribute C_TX_DELAY_TYPE48 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE49 : string;
  attribute C_TX_DELAY_TYPE49 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE5 : string;
  attribute C_TX_DELAY_TYPE5 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE50 : string;
  attribute C_TX_DELAY_TYPE50 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE51 : string;
  attribute C_TX_DELAY_TYPE51 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE6 : string;
  attribute C_TX_DELAY_TYPE6 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE7 : string;
  attribute C_TX_DELAY_TYPE7 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE8 : string;
  attribute C_TX_DELAY_TYPE8 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_TYPE9 : string;
  attribute C_TX_DELAY_TYPE9 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "2'b00";
  attribute C_TX_DELAY_VALUE : string;
  attribute C_TX_DELAY_VALUE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE0 : string;
  attribute C_TX_DELAY_VALUE0 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE1 : string;
  attribute C_TX_DELAY_VALUE1 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE10 : string;
  attribute C_TX_DELAY_VALUE10 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE11 : string;
  attribute C_TX_DELAY_VALUE11 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE12 : string;
  attribute C_TX_DELAY_VALUE12 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE13 : string;
  attribute C_TX_DELAY_VALUE13 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE14 : string;
  attribute C_TX_DELAY_VALUE14 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE15 : string;
  attribute C_TX_DELAY_VALUE15 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE16 : string;
  attribute C_TX_DELAY_VALUE16 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE17 : string;
  attribute C_TX_DELAY_VALUE17 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE18 : string;
  attribute C_TX_DELAY_VALUE18 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE19 : string;
  attribute C_TX_DELAY_VALUE19 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE2 : string;
  attribute C_TX_DELAY_VALUE2 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE20 : string;
  attribute C_TX_DELAY_VALUE20 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE21 : string;
  attribute C_TX_DELAY_VALUE21 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE22 : string;
  attribute C_TX_DELAY_VALUE22 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE23 : string;
  attribute C_TX_DELAY_VALUE23 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE24 : string;
  attribute C_TX_DELAY_VALUE24 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE25 : string;
  attribute C_TX_DELAY_VALUE25 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE26 : string;
  attribute C_TX_DELAY_VALUE26 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE27 : string;
  attribute C_TX_DELAY_VALUE27 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE28 : string;
  attribute C_TX_DELAY_VALUE28 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE29 : string;
  attribute C_TX_DELAY_VALUE29 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE3 : string;
  attribute C_TX_DELAY_VALUE3 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE30 : string;
  attribute C_TX_DELAY_VALUE30 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE31 : string;
  attribute C_TX_DELAY_VALUE31 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE32 : string;
  attribute C_TX_DELAY_VALUE32 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE33 : string;
  attribute C_TX_DELAY_VALUE33 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE34 : string;
  attribute C_TX_DELAY_VALUE34 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE35 : string;
  attribute C_TX_DELAY_VALUE35 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE36 : string;
  attribute C_TX_DELAY_VALUE36 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE37 : string;
  attribute C_TX_DELAY_VALUE37 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE38 : string;
  attribute C_TX_DELAY_VALUE38 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE39 : string;
  attribute C_TX_DELAY_VALUE39 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE4 : string;
  attribute C_TX_DELAY_VALUE4 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE40 : string;
  attribute C_TX_DELAY_VALUE40 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE41 : string;
  attribute C_TX_DELAY_VALUE41 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE42 : string;
  attribute C_TX_DELAY_VALUE42 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE43 : string;
  attribute C_TX_DELAY_VALUE43 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE44 : string;
  attribute C_TX_DELAY_VALUE44 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE45 : string;
  attribute C_TX_DELAY_VALUE45 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE46 : string;
  attribute C_TX_DELAY_VALUE46 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE47 : string;
  attribute C_TX_DELAY_VALUE47 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE48 : string;
  attribute C_TX_DELAY_VALUE48 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE49 : string;
  attribute C_TX_DELAY_VALUE49 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE5 : string;
  attribute C_TX_DELAY_VALUE5 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE50 : string;
  attribute C_TX_DELAY_VALUE50 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE51 : string;
  attribute C_TX_DELAY_VALUE51 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE6 : string;
  attribute C_TX_DELAY_VALUE6 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE7 : string;
  attribute C_TX_DELAY_VALUE7 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE8 : string;
  attribute C_TX_DELAY_VALUE8 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DELAY_VALUE9 : string;
  attribute C_TX_DELAY_VALUE9 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "12'b000000000000";
  attribute C_TX_DRIVE_D : string;
  attribute C_TX_DRIVE_D of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "NONE";
  attribute C_TX_DRIVE_S : string;
  attribute C_TX_DRIVE_S of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "NONE";
  attribute C_TX_IS_CLK_INVERTED : string;
  attribute C_TX_IS_CLK_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_TX_IS_RST_DLY_INVERTED : string;
  attribute C_TX_IS_RST_DLY_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_TX_IS_RST_INVERTED : string;
  attribute C_TX_IS_RST_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_TX_NATIVE_ODELAY_BYPASS : string;
  attribute C_TX_NATIVE_ODELAY_BYPASS of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "FALSE";
  attribute C_TX_PRE_EMPHASIS_D : string;
  attribute C_TX_PRE_EMPHASIS_D of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "NONE";
  attribute C_TX_PRE_EMPHASIS_S : string;
  attribute C_TX_PRE_EMPHASIS_S of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "NONE";
  attribute C_TX_REFCLK_FREQ : string;
  attribute C_TX_REFCLK_FREQ of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1500.000000";
  attribute C_TX_SLEW_D : string;
  attribute C_TX_SLEW_D of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "NONE";
  attribute C_TX_SLEW_S : string;
  attribute C_TX_SLEW_S of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "NONE";
  attribute C_TX_TRI_DELAY_FORMAT : string;
  attribute C_TX_TRI_DELAY_FORMAT of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "TIME";
  attribute C_TX_TRI_INIT : string;
  attribute C_TX_TRI_INIT of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b1";
  attribute C_TX_TRI_IS_CLK_INVERTED : string;
  attribute C_TX_TRI_IS_CLK_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_TX_TRI_IS_RST_DLY_INVERTED : string;
  attribute C_TX_TRI_IS_RST_DLY_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_TX_TRI_IS_RST_INVERTED : string;
  attribute C_TX_TRI_IS_RST_INVERTED of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "1'b0";
  attribute C_TX_TRI_NATIVE_ODELAY_BYPASS : string;
  attribute C_TX_TRI_NATIVE_ODELAY_BYPASS of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "FALSE";
  attribute C_TX_TRI_OUTPUT_PHASE_90 : string;
  attribute C_TX_TRI_OUTPUT_PHASE_90 of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "FALSE";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10";
  attribute TX_BITSLICE_TRI_EN : string;
  attribute TX_BITSLICE_TRI_EN of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "8'b00000000";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 : entity is "yes";
end design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10 is
  signal \<const0>\ : STD_LOGIC;
begin
  bidir_tx_bs_tri_cntvalueout0(8) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout0(7) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout0(6) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout0(5) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout0(4) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout0(3) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout0(2) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout0(1) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout0(0) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout1(8) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout1(7) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout1(6) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout1(5) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout1(4) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout1(3) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout1(2) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout1(1) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout1(0) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout2(8) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout2(7) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout2(6) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout2(5) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout2(4) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout2(3) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout2(2) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout2(1) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout2(0) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout3(8) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout3(7) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout3(6) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout3(5) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout3(4) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout3(3) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout3(2) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout3(1) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout3(0) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout4(8) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout4(7) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout4(6) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout4(5) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout4(4) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout4(3) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout4(2) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout4(1) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout4(0) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout5(8) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout5(7) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout5(6) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout5(5) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout5(4) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout5(3) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout5(2) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout5(1) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout5(0) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout6(8) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout6(7) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout6(6) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout6(5) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout6(4) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout6(3) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout6(2) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout6(1) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout6(0) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout7(8) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout7(7) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout7(6) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout7(5) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout7(4) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout7(3) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout7(2) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout7(1) <= \<const0>\;
  bidir_tx_bs_tri_cntvalueout7(0) <= \<const0>\;
  bitslip_error_0 <= \<const0>\;
  bitslip_error_1 <= \<const0>\;
  bitslip_error_10 <= \<const0>\;
  bitslip_error_11 <= \<const0>\;
  bitslip_error_12 <= \<const0>\;
  bitslip_error_13 <= \<const0>\;
  bitslip_error_14 <= \<const0>\;
  bitslip_error_15 <= \<const0>\;
  bitslip_error_16 <= \<const0>\;
  bitslip_error_17 <= \<const0>\;
  bitslip_error_18 <= \<const0>\;
  bitslip_error_19 <= \<const0>\;
  bitslip_error_2 <= \<const0>\;
  bitslip_error_20 <= \<const0>\;
  bitslip_error_21 <= \<const0>\;
  bitslip_error_22 <= \<const0>\;
  bitslip_error_23 <= \<const0>\;
  bitslip_error_24 <= \<const0>\;
  bitslip_error_25 <= \<const0>\;
  bitslip_error_26 <= \<const0>\;
  bitslip_error_27 <= \<const0>\;
  bitslip_error_28 <= \<const0>\;
  bitslip_error_29 <= \<const0>\;
  bitslip_error_3 <= \<const0>\;
  bitslip_error_30 <= \<const0>\;
  bitslip_error_31 <= \<const0>\;
  bitslip_error_32 <= \<const0>\;
  bitslip_error_33 <= \<const0>\;
  bitslip_error_34 <= \<const0>\;
  bitslip_error_35 <= \<const0>\;
  bitslip_error_36 <= \<const0>\;
  bitslip_error_37 <= \<const0>\;
  bitslip_error_38 <= \<const0>\;
  bitslip_error_39 <= \<const0>\;
  bitslip_error_4 <= \<const0>\;
  bitslip_error_40 <= \<const0>\;
  bitslip_error_41 <= \<const0>\;
  bitslip_error_42 <= \<const0>\;
  bitslip_error_43 <= \<const0>\;
  bitslip_error_44 <= \<const0>\;
  bitslip_error_45 <= \<const0>\;
  bitslip_error_46 <= \<const0>\;
  bitslip_error_47 <= \<const0>\;
  bitslip_error_48 <= \<const0>\;
  bitslip_error_49 <= \<const0>\;
  bitslip_error_5 <= \<const0>\;
  bitslip_error_50 <= \<const0>\;
  bitslip_error_51 <= \<const0>\;
  bitslip_error_6 <= \<const0>\;
  bitslip_error_7 <= \<const0>\;
  bitslip_error_8 <= \<const0>\;
  bitslip_error_9 <= \<const0>\;
  clk_from_ibuf <= \<const0>\;
  data_to_fabric_clk_rxn(7) <= \<const0>\;
  data_to_fabric_clk_rxn(6) <= \<const0>\;
  data_to_fabric_clk_rxn(5) <= \<const0>\;
  data_to_fabric_clk_rxn(4) <= \<const0>\;
  data_to_fabric_clk_rxn(3) <= \<const0>\;
  data_to_fabric_clk_rxn(2) <= \<const0>\;
  data_to_fabric_clk_rxn(1) <= \<const0>\;
  data_to_fabric_clk_rxn(0) <= \<const0>\;
  data_to_fabric_clk_rxp(7) <= \<const0>\;
  data_to_fabric_clk_rxp(6) <= \<const0>\;
  data_to_fabric_clk_rxp(5) <= \<const0>\;
  data_to_fabric_clk_rxp(4) <= \<const0>\;
  data_to_fabric_clk_rxp(3) <= \<const0>\;
  data_to_fabric_clk_rxp(2) <= \<const0>\;
  data_to_fabric_clk_rxp(1) <= \<const0>\;
  data_to_fabric_clk_rxp(0) <= \<const0>\;
  data_to_fabric_data_rxn0(7) <= \<const0>\;
  data_to_fabric_data_rxn0(6) <= \<const0>\;
  data_to_fabric_data_rxn0(5) <= \<const0>\;
  data_to_fabric_data_rxn0(4) <= \<const0>\;
  data_to_fabric_data_rxn0(3) <= \<const0>\;
  data_to_fabric_data_rxn0(2) <= \<const0>\;
  data_to_fabric_data_rxn0(1) <= \<const0>\;
  data_to_fabric_data_rxn0(0) <= \<const0>\;
  data_to_fabric_data_rxn1(7) <= \<const0>\;
  data_to_fabric_data_rxn1(6) <= \<const0>\;
  data_to_fabric_data_rxn1(5) <= \<const0>\;
  data_to_fabric_data_rxn1(4) <= \<const0>\;
  data_to_fabric_data_rxn1(3) <= \<const0>\;
  data_to_fabric_data_rxn1(2) <= \<const0>\;
  data_to_fabric_data_rxn1(1) <= \<const0>\;
  data_to_fabric_data_rxn1(0) <= \<const0>\;
  data_to_fabric_data_rxn2(7) <= \<const0>\;
  data_to_fabric_data_rxn2(6) <= \<const0>\;
  data_to_fabric_data_rxn2(5) <= \<const0>\;
  data_to_fabric_data_rxn2(4) <= \<const0>\;
  data_to_fabric_data_rxn2(3) <= \<const0>\;
  data_to_fabric_data_rxn2(2) <= \<const0>\;
  data_to_fabric_data_rxn2(1) <= \<const0>\;
  data_to_fabric_data_rxn2(0) <= \<const0>\;
  data_to_fabric_data_rxn3(7) <= \<const0>\;
  data_to_fabric_data_rxn3(6) <= \<const0>\;
  data_to_fabric_data_rxn3(5) <= \<const0>\;
  data_to_fabric_data_rxn3(4) <= \<const0>\;
  data_to_fabric_data_rxn3(3) <= \<const0>\;
  data_to_fabric_data_rxn3(2) <= \<const0>\;
  data_to_fabric_data_rxn3(1) <= \<const0>\;
  data_to_fabric_data_rxn3(0) <= \<const0>\;
  dly_rdy_bsc0 <= \<const0>\;
  dly_rdy_bsc1 <= \<const0>\;
  dly_rdy_bsc2 <= \<const0>\;
  dly_rdy_bsc3 <= \<const0>\;
  dly_rdy_bsc4 <= \<const0>\;
  dly_rdy_bsc5 <= \<const0>\;
  dly_rdy_bsc6 <= \<const0>\;
  dly_rdy_bsc7 <= \<const0>\;
  do_out(15) <= \<const0>\;
  do_out(14) <= \<const0>\;
  do_out(13) <= \<const0>\;
  do_out(12) <= \<const0>\;
  do_out(11) <= \<const0>\;
  do_out(10) <= \<const0>\;
  do_out(9) <= \<const0>\;
  do_out(8) <= \<const0>\;
  do_out(7) <= \<const0>\;
  do_out(6) <= \<const0>\;
  do_out(5) <= \<const0>\;
  do_out(4) <= \<const0>\;
  do_out(3) <= \<const0>\;
  do_out(2) <= \<const0>\;
  do_out(1) <= \<const0>\;
  do_out(0) <= \<const0>\;
  drdy <= \<const0>\;
  fifo_empty_0 <= \<const0>\;
  fifo_empty_1 <= \<const0>\;
  fifo_empty_10 <= \<const0>\;
  fifo_empty_11 <= \<const0>\;
  fifo_empty_12 <= \<const0>\;
  fifo_empty_13 <= \<const0>\;
  fifo_empty_14 <= \<const0>\;
  fifo_empty_15 <= \<const0>\;
  fifo_empty_16 <= \<const0>\;
  fifo_empty_17 <= \<const0>\;
  fifo_empty_18 <= \<const0>\;
  fifo_empty_19 <= \<const0>\;
  fifo_empty_20 <= \<const0>\;
  fifo_empty_21 <= \<const0>\;
  fifo_empty_22 <= \<const0>\;
  fifo_empty_23 <= \<const0>\;
  fifo_empty_24 <= \<const0>\;
  fifo_empty_25 <= \<const0>\;
  fifo_empty_26 <= \<const0>\;
  fifo_empty_27 <= \<const0>\;
  fifo_empty_28 <= \<const0>\;
  fifo_empty_29 <= \<const0>\;
  fifo_empty_3 <= \<const0>\;
  fifo_empty_30 <= \<const0>\;
  fifo_empty_31 <= \<const0>\;
  fifo_empty_32 <= \<const0>\;
  fifo_empty_33 <= \<const0>\;
  fifo_empty_34 <= \<const0>\;
  fifo_empty_35 <= \<const0>\;
  fifo_empty_36 <= \<const0>\;
  fifo_empty_37 <= \<const0>\;
  fifo_empty_38 <= \<const0>\;
  fifo_empty_39 <= \<const0>\;
  fifo_empty_40 <= \<const0>\;
  fifo_empty_41 <= \<const0>\;
  fifo_empty_42 <= \<const0>\;
  fifo_empty_43 <= \<const0>\;
  fifo_empty_44 <= \<const0>\;
  fifo_empty_45 <= \<const0>\;
  fifo_empty_46 <= \<const0>\;
  fifo_empty_47 <= \<const0>\;
  fifo_empty_48 <= \<const0>\;
  fifo_empty_49 <= \<const0>\;
  fifo_empty_5 <= \<const0>\;
  fifo_empty_50 <= \<const0>\;
  fifo_empty_51 <= \<const0>\;
  fifo_empty_7 <= \<const0>\;
  fifo_empty_9 <= \<const0>\;
  fifo_rd_data_valid <= \<const0>\;
  fifo_wr_clk_13 <= \<const0>\;
  fifo_wr_clk_19 <= \<const0>\;
  fifo_wr_clk_26 <= \<const0>\;
  fifo_wr_clk_32 <= \<const0>\;
  fifo_wr_clk_39 <= \<const0>\;
  fifo_wr_clk_45 <= \<const0>\;
  fifo_wr_clk_6 <= \<const0>\;
  intf_rdy <= \<const0>\;
  pll0_clkout0 <= \<const0>\;
  pll0_clkout1 <= \<const0>\;
  pll0_locked <= \<const0>\;
  pll1_clkout0 <= \<const0>\;
  pll1_locked <= \<const0>\;
  riu_rd_data_bg0(15) <= \<const0>\;
  riu_rd_data_bg0(14) <= \<const0>\;
  riu_rd_data_bg0(13) <= \<const0>\;
  riu_rd_data_bg0(12) <= \<const0>\;
  riu_rd_data_bg0(11) <= \<const0>\;
  riu_rd_data_bg0(10) <= \<const0>\;
  riu_rd_data_bg0(9) <= \<const0>\;
  riu_rd_data_bg0(8) <= \<const0>\;
  riu_rd_data_bg0(7) <= \<const0>\;
  riu_rd_data_bg0(6) <= \<const0>\;
  riu_rd_data_bg0(5) <= \<const0>\;
  riu_rd_data_bg0(4) <= \<const0>\;
  riu_rd_data_bg0(3) <= \<const0>\;
  riu_rd_data_bg0(2) <= \<const0>\;
  riu_rd_data_bg0(1) <= \<const0>\;
  riu_rd_data_bg0(0) <= \<const0>\;
  riu_rd_data_bg0_bs0(15) <= \<const0>\;
  riu_rd_data_bg0_bs0(14) <= \<const0>\;
  riu_rd_data_bg0_bs0(13) <= \<const0>\;
  riu_rd_data_bg0_bs0(12) <= \<const0>\;
  riu_rd_data_bg0_bs0(11) <= \<const0>\;
  riu_rd_data_bg0_bs0(10) <= \<const0>\;
  riu_rd_data_bg0_bs0(9) <= \<const0>\;
  riu_rd_data_bg0_bs0(8) <= \<const0>\;
  riu_rd_data_bg0_bs0(7) <= \<const0>\;
  riu_rd_data_bg0_bs0(6) <= \<const0>\;
  riu_rd_data_bg0_bs0(5) <= \<const0>\;
  riu_rd_data_bg0_bs0(4) <= \<const0>\;
  riu_rd_data_bg0_bs0(3) <= \<const0>\;
  riu_rd_data_bg0_bs0(2) <= \<const0>\;
  riu_rd_data_bg0_bs0(1) <= \<const0>\;
  riu_rd_data_bg0_bs0(0) <= \<const0>\;
  riu_rd_data_bg0_bs1(15) <= \<const0>\;
  riu_rd_data_bg0_bs1(14) <= \<const0>\;
  riu_rd_data_bg0_bs1(13) <= \<const0>\;
  riu_rd_data_bg0_bs1(12) <= \<const0>\;
  riu_rd_data_bg0_bs1(11) <= \<const0>\;
  riu_rd_data_bg0_bs1(10) <= \<const0>\;
  riu_rd_data_bg0_bs1(9) <= \<const0>\;
  riu_rd_data_bg0_bs1(8) <= \<const0>\;
  riu_rd_data_bg0_bs1(7) <= \<const0>\;
  riu_rd_data_bg0_bs1(6) <= \<const0>\;
  riu_rd_data_bg0_bs1(5) <= \<const0>\;
  riu_rd_data_bg0_bs1(4) <= \<const0>\;
  riu_rd_data_bg0_bs1(3) <= \<const0>\;
  riu_rd_data_bg0_bs1(2) <= \<const0>\;
  riu_rd_data_bg0_bs1(1) <= \<const0>\;
  riu_rd_data_bg0_bs1(0) <= \<const0>\;
  riu_rd_data_bg1(15) <= \<const0>\;
  riu_rd_data_bg1(14) <= \<const0>\;
  riu_rd_data_bg1(13) <= \<const0>\;
  riu_rd_data_bg1(12) <= \<const0>\;
  riu_rd_data_bg1(11) <= \<const0>\;
  riu_rd_data_bg1(10) <= \<const0>\;
  riu_rd_data_bg1(9) <= \<const0>\;
  riu_rd_data_bg1(8) <= \<const0>\;
  riu_rd_data_bg1(7) <= \<const0>\;
  riu_rd_data_bg1(6) <= \<const0>\;
  riu_rd_data_bg1(5) <= \<const0>\;
  riu_rd_data_bg1(4) <= \<const0>\;
  riu_rd_data_bg1(3) <= \<const0>\;
  riu_rd_data_bg1(2) <= \<const0>\;
  riu_rd_data_bg1(1) <= \<const0>\;
  riu_rd_data_bg1(0) <= \<const0>\;
  riu_rd_data_bg1_bs2(15) <= \<const0>\;
  riu_rd_data_bg1_bs2(14) <= \<const0>\;
  riu_rd_data_bg1_bs2(13) <= \<const0>\;
  riu_rd_data_bg1_bs2(12) <= \<const0>\;
  riu_rd_data_bg1_bs2(11) <= \<const0>\;
  riu_rd_data_bg1_bs2(10) <= \<const0>\;
  riu_rd_data_bg1_bs2(9) <= \<const0>\;
  riu_rd_data_bg1_bs2(8) <= \<const0>\;
  riu_rd_data_bg1_bs2(7) <= \<const0>\;
  riu_rd_data_bg1_bs2(6) <= \<const0>\;
  riu_rd_data_bg1_bs2(5) <= \<const0>\;
  riu_rd_data_bg1_bs2(4) <= \<const0>\;
  riu_rd_data_bg1_bs2(3) <= \<const0>\;
  riu_rd_data_bg1_bs2(2) <= \<const0>\;
  riu_rd_data_bg1_bs2(1) <= \<const0>\;
  riu_rd_data_bg1_bs2(0) <= \<const0>\;
  riu_rd_data_bg1_bs3(15) <= \<const0>\;
  riu_rd_data_bg1_bs3(14) <= \<const0>\;
  riu_rd_data_bg1_bs3(13) <= \<const0>\;
  riu_rd_data_bg1_bs3(12) <= \<const0>\;
  riu_rd_data_bg1_bs3(11) <= \<const0>\;
  riu_rd_data_bg1_bs3(10) <= \<const0>\;
  riu_rd_data_bg1_bs3(9) <= \<const0>\;
  riu_rd_data_bg1_bs3(8) <= \<const0>\;
  riu_rd_data_bg1_bs3(7) <= \<const0>\;
  riu_rd_data_bg1_bs3(6) <= \<const0>\;
  riu_rd_data_bg1_bs3(5) <= \<const0>\;
  riu_rd_data_bg1_bs3(4) <= \<const0>\;
  riu_rd_data_bg1_bs3(3) <= \<const0>\;
  riu_rd_data_bg1_bs3(2) <= \<const0>\;
  riu_rd_data_bg1_bs3(1) <= \<const0>\;
  riu_rd_data_bg1_bs3(0) <= \<const0>\;
  riu_rd_data_bg2(15) <= \<const0>\;
  riu_rd_data_bg2(14) <= \<const0>\;
  riu_rd_data_bg2(13) <= \<const0>\;
  riu_rd_data_bg2(12) <= \<const0>\;
  riu_rd_data_bg2(11) <= \<const0>\;
  riu_rd_data_bg2(10) <= \<const0>\;
  riu_rd_data_bg2(9) <= \<const0>\;
  riu_rd_data_bg2(8) <= \<const0>\;
  riu_rd_data_bg2(7) <= \<const0>\;
  riu_rd_data_bg2(6) <= \<const0>\;
  riu_rd_data_bg2(5) <= \<const0>\;
  riu_rd_data_bg2(4) <= \<const0>\;
  riu_rd_data_bg2(3) <= \<const0>\;
  riu_rd_data_bg2(2) <= \<const0>\;
  riu_rd_data_bg2(1) <= \<const0>\;
  riu_rd_data_bg2(0) <= \<const0>\;
  riu_rd_data_bg2_bs4(15) <= \<const0>\;
  riu_rd_data_bg2_bs4(14) <= \<const0>\;
  riu_rd_data_bg2_bs4(13) <= \<const0>\;
  riu_rd_data_bg2_bs4(12) <= \<const0>\;
  riu_rd_data_bg2_bs4(11) <= \<const0>\;
  riu_rd_data_bg2_bs4(10) <= \<const0>\;
  riu_rd_data_bg2_bs4(9) <= \<const0>\;
  riu_rd_data_bg2_bs4(8) <= \<const0>\;
  riu_rd_data_bg2_bs4(7) <= \<const0>\;
  riu_rd_data_bg2_bs4(6) <= \<const0>\;
  riu_rd_data_bg2_bs4(5) <= \<const0>\;
  riu_rd_data_bg2_bs4(4) <= \<const0>\;
  riu_rd_data_bg2_bs4(3) <= \<const0>\;
  riu_rd_data_bg2_bs4(2) <= \<const0>\;
  riu_rd_data_bg2_bs4(1) <= \<const0>\;
  riu_rd_data_bg2_bs4(0) <= \<const0>\;
  riu_rd_data_bg2_bs5(15) <= \<const0>\;
  riu_rd_data_bg2_bs5(14) <= \<const0>\;
  riu_rd_data_bg2_bs5(13) <= \<const0>\;
  riu_rd_data_bg2_bs5(12) <= \<const0>\;
  riu_rd_data_bg2_bs5(11) <= \<const0>\;
  riu_rd_data_bg2_bs5(10) <= \<const0>\;
  riu_rd_data_bg2_bs5(9) <= \<const0>\;
  riu_rd_data_bg2_bs5(8) <= \<const0>\;
  riu_rd_data_bg2_bs5(7) <= \<const0>\;
  riu_rd_data_bg2_bs5(6) <= \<const0>\;
  riu_rd_data_bg2_bs5(5) <= \<const0>\;
  riu_rd_data_bg2_bs5(4) <= \<const0>\;
  riu_rd_data_bg2_bs5(3) <= \<const0>\;
  riu_rd_data_bg2_bs5(2) <= \<const0>\;
  riu_rd_data_bg2_bs5(1) <= \<const0>\;
  riu_rd_data_bg2_bs5(0) <= \<const0>\;
  riu_rd_data_bg3(15) <= \<const0>\;
  riu_rd_data_bg3(14) <= \<const0>\;
  riu_rd_data_bg3(13) <= \<const0>\;
  riu_rd_data_bg3(12) <= \<const0>\;
  riu_rd_data_bg3(11) <= \<const0>\;
  riu_rd_data_bg3(10) <= \<const0>\;
  riu_rd_data_bg3(9) <= \<const0>\;
  riu_rd_data_bg3(8) <= \<const0>\;
  riu_rd_data_bg3(7) <= \<const0>\;
  riu_rd_data_bg3(6) <= \<const0>\;
  riu_rd_data_bg3(5) <= \<const0>\;
  riu_rd_data_bg3(4) <= \<const0>\;
  riu_rd_data_bg3(3) <= \<const0>\;
  riu_rd_data_bg3(2) <= \<const0>\;
  riu_rd_data_bg3(1) <= \<const0>\;
  riu_rd_data_bg3(0) <= \<const0>\;
  riu_rd_data_bg3_bs6(15) <= \<const0>\;
  riu_rd_data_bg3_bs6(14) <= \<const0>\;
  riu_rd_data_bg3_bs6(13) <= \<const0>\;
  riu_rd_data_bg3_bs6(12) <= \<const0>\;
  riu_rd_data_bg3_bs6(11) <= \<const0>\;
  riu_rd_data_bg3_bs6(10) <= \<const0>\;
  riu_rd_data_bg3_bs6(9) <= \<const0>\;
  riu_rd_data_bg3_bs6(8) <= \<const0>\;
  riu_rd_data_bg3_bs6(7) <= \<const0>\;
  riu_rd_data_bg3_bs6(6) <= \<const0>\;
  riu_rd_data_bg3_bs6(5) <= \<const0>\;
  riu_rd_data_bg3_bs6(4) <= \<const0>\;
  riu_rd_data_bg3_bs6(3) <= \<const0>\;
  riu_rd_data_bg3_bs6(2) <= \<const0>\;
  riu_rd_data_bg3_bs6(1) <= \<const0>\;
  riu_rd_data_bg3_bs6(0) <= \<const0>\;
  riu_rd_data_bg3_bs7(15) <= \<const0>\;
  riu_rd_data_bg3_bs7(14) <= \<const0>\;
  riu_rd_data_bg3_bs7(13) <= \<const0>\;
  riu_rd_data_bg3_bs7(12) <= \<const0>\;
  riu_rd_data_bg3_bs7(11) <= \<const0>\;
  riu_rd_data_bg3_bs7(10) <= \<const0>\;
  riu_rd_data_bg3_bs7(9) <= \<const0>\;
  riu_rd_data_bg3_bs7(8) <= \<const0>\;
  riu_rd_data_bg3_bs7(7) <= \<const0>\;
  riu_rd_data_bg3_bs7(6) <= \<const0>\;
  riu_rd_data_bg3_bs7(5) <= \<const0>\;
  riu_rd_data_bg3_bs7(4) <= \<const0>\;
  riu_rd_data_bg3_bs7(3) <= \<const0>\;
  riu_rd_data_bg3_bs7(2) <= \<const0>\;
  riu_rd_data_bg3_bs7(1) <= \<const0>\;
  riu_rd_data_bg3_bs7(0) <= \<const0>\;
  riu_valid_bg0 <= \<const0>\;
  riu_valid_bg0_bs0 <= \<const0>\;
  riu_valid_bg0_bs1 <= \<const0>\;
  riu_valid_bg1 <= \<const0>\;
  riu_valid_bg1_bs2 <= \<const0>\;
  riu_valid_bg1_bs3 <= \<const0>\;
  riu_valid_bg2 <= \<const0>\;
  riu_valid_bg2_bs4 <= \<const0>\;
  riu_valid_bg2_bs5 <= \<const0>\;
  riu_valid_bg3 <= \<const0>\;
  riu_valid_bg3_bs6 <= \<const0>\;
  riu_valid_bg3_bs7 <= \<const0>\;
  rx_bitslip_sync_done <= \<const0>\;
  rx_cntvalueout_0(8) <= \<const0>\;
  rx_cntvalueout_0(7) <= \<const0>\;
  rx_cntvalueout_0(6) <= \<const0>\;
  rx_cntvalueout_0(5) <= \<const0>\;
  rx_cntvalueout_0(4) <= \<const0>\;
  rx_cntvalueout_0(3) <= \<const0>\;
  rx_cntvalueout_0(2) <= \<const0>\;
  rx_cntvalueout_0(1) <= \<const0>\;
  rx_cntvalueout_0(0) <= \<const0>\;
  rx_cntvalueout_1(8) <= \<const0>\;
  rx_cntvalueout_1(7) <= \<const0>\;
  rx_cntvalueout_1(6) <= \<const0>\;
  rx_cntvalueout_1(5) <= \<const0>\;
  rx_cntvalueout_1(4) <= \<const0>\;
  rx_cntvalueout_1(3) <= \<const0>\;
  rx_cntvalueout_1(2) <= \<const0>\;
  rx_cntvalueout_1(1) <= \<const0>\;
  rx_cntvalueout_1(0) <= \<const0>\;
  rx_cntvalueout_10(8) <= \<const0>\;
  rx_cntvalueout_10(7) <= \<const0>\;
  rx_cntvalueout_10(6) <= \<const0>\;
  rx_cntvalueout_10(5) <= \<const0>\;
  rx_cntvalueout_10(4) <= \<const0>\;
  rx_cntvalueout_10(3) <= \<const0>\;
  rx_cntvalueout_10(2) <= \<const0>\;
  rx_cntvalueout_10(1) <= \<const0>\;
  rx_cntvalueout_10(0) <= \<const0>\;
  rx_cntvalueout_11(8) <= \<const0>\;
  rx_cntvalueout_11(7) <= \<const0>\;
  rx_cntvalueout_11(6) <= \<const0>\;
  rx_cntvalueout_11(5) <= \<const0>\;
  rx_cntvalueout_11(4) <= \<const0>\;
  rx_cntvalueout_11(3) <= \<const0>\;
  rx_cntvalueout_11(2) <= \<const0>\;
  rx_cntvalueout_11(1) <= \<const0>\;
  rx_cntvalueout_11(0) <= \<const0>\;
  rx_cntvalueout_12(8) <= \<const0>\;
  rx_cntvalueout_12(7) <= \<const0>\;
  rx_cntvalueout_12(6) <= \<const0>\;
  rx_cntvalueout_12(5) <= \<const0>\;
  rx_cntvalueout_12(4) <= \<const0>\;
  rx_cntvalueout_12(3) <= \<const0>\;
  rx_cntvalueout_12(2) <= \<const0>\;
  rx_cntvalueout_12(1) <= \<const0>\;
  rx_cntvalueout_12(0) <= \<const0>\;
  rx_cntvalueout_13(8) <= \<const0>\;
  rx_cntvalueout_13(7) <= \<const0>\;
  rx_cntvalueout_13(6) <= \<const0>\;
  rx_cntvalueout_13(5) <= \<const0>\;
  rx_cntvalueout_13(4) <= \<const0>\;
  rx_cntvalueout_13(3) <= \<const0>\;
  rx_cntvalueout_13(2) <= \<const0>\;
  rx_cntvalueout_13(1) <= \<const0>\;
  rx_cntvalueout_13(0) <= \<const0>\;
  rx_cntvalueout_14(8) <= \<const0>\;
  rx_cntvalueout_14(7) <= \<const0>\;
  rx_cntvalueout_14(6) <= \<const0>\;
  rx_cntvalueout_14(5) <= \<const0>\;
  rx_cntvalueout_14(4) <= \<const0>\;
  rx_cntvalueout_14(3) <= \<const0>\;
  rx_cntvalueout_14(2) <= \<const0>\;
  rx_cntvalueout_14(1) <= \<const0>\;
  rx_cntvalueout_14(0) <= \<const0>\;
  rx_cntvalueout_15(8) <= \<const0>\;
  rx_cntvalueout_15(7) <= \<const0>\;
  rx_cntvalueout_15(6) <= \<const0>\;
  rx_cntvalueout_15(5) <= \<const0>\;
  rx_cntvalueout_15(4) <= \<const0>\;
  rx_cntvalueout_15(3) <= \<const0>\;
  rx_cntvalueout_15(2) <= \<const0>\;
  rx_cntvalueout_15(1) <= \<const0>\;
  rx_cntvalueout_15(0) <= \<const0>\;
  rx_cntvalueout_16(8) <= \<const0>\;
  rx_cntvalueout_16(7) <= \<const0>\;
  rx_cntvalueout_16(6) <= \<const0>\;
  rx_cntvalueout_16(5) <= \<const0>\;
  rx_cntvalueout_16(4) <= \<const0>\;
  rx_cntvalueout_16(3) <= \<const0>\;
  rx_cntvalueout_16(2) <= \<const0>\;
  rx_cntvalueout_16(1) <= \<const0>\;
  rx_cntvalueout_16(0) <= \<const0>\;
  rx_cntvalueout_17(8) <= \<const0>\;
  rx_cntvalueout_17(7) <= \<const0>\;
  rx_cntvalueout_17(6) <= \<const0>\;
  rx_cntvalueout_17(5) <= \<const0>\;
  rx_cntvalueout_17(4) <= \<const0>\;
  rx_cntvalueout_17(3) <= \<const0>\;
  rx_cntvalueout_17(2) <= \<const0>\;
  rx_cntvalueout_17(1) <= \<const0>\;
  rx_cntvalueout_17(0) <= \<const0>\;
  rx_cntvalueout_18(8) <= \<const0>\;
  rx_cntvalueout_18(7) <= \<const0>\;
  rx_cntvalueout_18(6) <= \<const0>\;
  rx_cntvalueout_18(5) <= \<const0>\;
  rx_cntvalueout_18(4) <= \<const0>\;
  rx_cntvalueout_18(3) <= \<const0>\;
  rx_cntvalueout_18(2) <= \<const0>\;
  rx_cntvalueout_18(1) <= \<const0>\;
  rx_cntvalueout_18(0) <= \<const0>\;
  rx_cntvalueout_19(8) <= \<const0>\;
  rx_cntvalueout_19(7) <= \<const0>\;
  rx_cntvalueout_19(6) <= \<const0>\;
  rx_cntvalueout_19(5) <= \<const0>\;
  rx_cntvalueout_19(4) <= \<const0>\;
  rx_cntvalueout_19(3) <= \<const0>\;
  rx_cntvalueout_19(2) <= \<const0>\;
  rx_cntvalueout_19(1) <= \<const0>\;
  rx_cntvalueout_19(0) <= \<const0>\;
  rx_cntvalueout_2(8) <= \<const0>\;
  rx_cntvalueout_2(7) <= \<const0>\;
  rx_cntvalueout_2(6) <= \<const0>\;
  rx_cntvalueout_2(5) <= \<const0>\;
  rx_cntvalueout_2(4) <= \<const0>\;
  rx_cntvalueout_2(3) <= \<const0>\;
  rx_cntvalueout_2(2) <= \<const0>\;
  rx_cntvalueout_2(1) <= \<const0>\;
  rx_cntvalueout_2(0) <= \<const0>\;
  rx_cntvalueout_20(8) <= \<const0>\;
  rx_cntvalueout_20(7) <= \<const0>\;
  rx_cntvalueout_20(6) <= \<const0>\;
  rx_cntvalueout_20(5) <= \<const0>\;
  rx_cntvalueout_20(4) <= \<const0>\;
  rx_cntvalueout_20(3) <= \<const0>\;
  rx_cntvalueout_20(2) <= \<const0>\;
  rx_cntvalueout_20(1) <= \<const0>\;
  rx_cntvalueout_20(0) <= \<const0>\;
  rx_cntvalueout_21(8) <= \<const0>\;
  rx_cntvalueout_21(7) <= \<const0>\;
  rx_cntvalueout_21(6) <= \<const0>\;
  rx_cntvalueout_21(5) <= \<const0>\;
  rx_cntvalueout_21(4) <= \<const0>\;
  rx_cntvalueout_21(3) <= \<const0>\;
  rx_cntvalueout_21(2) <= \<const0>\;
  rx_cntvalueout_21(1) <= \<const0>\;
  rx_cntvalueout_21(0) <= \<const0>\;
  rx_cntvalueout_22(8) <= \<const0>\;
  rx_cntvalueout_22(7) <= \<const0>\;
  rx_cntvalueout_22(6) <= \<const0>\;
  rx_cntvalueout_22(5) <= \<const0>\;
  rx_cntvalueout_22(4) <= \<const0>\;
  rx_cntvalueout_22(3) <= \<const0>\;
  rx_cntvalueout_22(2) <= \<const0>\;
  rx_cntvalueout_22(1) <= \<const0>\;
  rx_cntvalueout_22(0) <= \<const0>\;
  rx_cntvalueout_23(8) <= \<const0>\;
  rx_cntvalueout_23(7) <= \<const0>\;
  rx_cntvalueout_23(6) <= \<const0>\;
  rx_cntvalueout_23(5) <= \<const0>\;
  rx_cntvalueout_23(4) <= \<const0>\;
  rx_cntvalueout_23(3) <= \<const0>\;
  rx_cntvalueout_23(2) <= \<const0>\;
  rx_cntvalueout_23(1) <= \<const0>\;
  rx_cntvalueout_23(0) <= \<const0>\;
  rx_cntvalueout_24(8) <= \<const0>\;
  rx_cntvalueout_24(7) <= \<const0>\;
  rx_cntvalueout_24(6) <= \<const0>\;
  rx_cntvalueout_24(5) <= \<const0>\;
  rx_cntvalueout_24(4) <= \<const0>\;
  rx_cntvalueout_24(3) <= \<const0>\;
  rx_cntvalueout_24(2) <= \<const0>\;
  rx_cntvalueout_24(1) <= \<const0>\;
  rx_cntvalueout_24(0) <= \<const0>\;
  rx_cntvalueout_25(8) <= \<const0>\;
  rx_cntvalueout_25(7) <= \<const0>\;
  rx_cntvalueout_25(6) <= \<const0>\;
  rx_cntvalueout_25(5) <= \<const0>\;
  rx_cntvalueout_25(4) <= \<const0>\;
  rx_cntvalueout_25(3) <= \<const0>\;
  rx_cntvalueout_25(2) <= \<const0>\;
  rx_cntvalueout_25(1) <= \<const0>\;
  rx_cntvalueout_25(0) <= \<const0>\;
  rx_cntvalueout_26(8) <= \<const0>\;
  rx_cntvalueout_26(7) <= \<const0>\;
  rx_cntvalueout_26(6) <= \<const0>\;
  rx_cntvalueout_26(5) <= \<const0>\;
  rx_cntvalueout_26(4) <= \<const0>\;
  rx_cntvalueout_26(3) <= \<const0>\;
  rx_cntvalueout_26(2) <= \<const0>\;
  rx_cntvalueout_26(1) <= \<const0>\;
  rx_cntvalueout_26(0) <= \<const0>\;
  rx_cntvalueout_27(8) <= \<const0>\;
  rx_cntvalueout_27(7) <= \<const0>\;
  rx_cntvalueout_27(6) <= \<const0>\;
  rx_cntvalueout_27(5) <= \<const0>\;
  rx_cntvalueout_27(4) <= \<const0>\;
  rx_cntvalueout_27(3) <= \<const0>\;
  rx_cntvalueout_27(2) <= \<const0>\;
  rx_cntvalueout_27(1) <= \<const0>\;
  rx_cntvalueout_27(0) <= \<const0>\;
  rx_cntvalueout_28(8) <= \<const0>\;
  rx_cntvalueout_28(7) <= \<const0>\;
  rx_cntvalueout_28(6) <= \<const0>\;
  rx_cntvalueout_28(5) <= \<const0>\;
  rx_cntvalueout_28(4) <= \<const0>\;
  rx_cntvalueout_28(3) <= \<const0>\;
  rx_cntvalueout_28(2) <= \<const0>\;
  rx_cntvalueout_28(1) <= \<const0>\;
  rx_cntvalueout_28(0) <= \<const0>\;
  rx_cntvalueout_29(8) <= \<const0>\;
  rx_cntvalueout_29(7) <= \<const0>\;
  rx_cntvalueout_29(6) <= \<const0>\;
  rx_cntvalueout_29(5) <= \<const0>\;
  rx_cntvalueout_29(4) <= \<const0>\;
  rx_cntvalueout_29(3) <= \<const0>\;
  rx_cntvalueout_29(2) <= \<const0>\;
  rx_cntvalueout_29(1) <= \<const0>\;
  rx_cntvalueout_29(0) <= \<const0>\;
  rx_cntvalueout_3(8) <= \<const0>\;
  rx_cntvalueout_3(7) <= \<const0>\;
  rx_cntvalueout_3(6) <= \<const0>\;
  rx_cntvalueout_3(5) <= \<const0>\;
  rx_cntvalueout_3(4) <= \<const0>\;
  rx_cntvalueout_3(3) <= \<const0>\;
  rx_cntvalueout_3(2) <= \<const0>\;
  rx_cntvalueout_3(1) <= \<const0>\;
  rx_cntvalueout_3(0) <= \<const0>\;
  rx_cntvalueout_30(8) <= \<const0>\;
  rx_cntvalueout_30(7) <= \<const0>\;
  rx_cntvalueout_30(6) <= \<const0>\;
  rx_cntvalueout_30(5) <= \<const0>\;
  rx_cntvalueout_30(4) <= \<const0>\;
  rx_cntvalueout_30(3) <= \<const0>\;
  rx_cntvalueout_30(2) <= \<const0>\;
  rx_cntvalueout_30(1) <= \<const0>\;
  rx_cntvalueout_30(0) <= \<const0>\;
  rx_cntvalueout_31(8) <= \<const0>\;
  rx_cntvalueout_31(7) <= \<const0>\;
  rx_cntvalueout_31(6) <= \<const0>\;
  rx_cntvalueout_31(5) <= \<const0>\;
  rx_cntvalueout_31(4) <= \<const0>\;
  rx_cntvalueout_31(3) <= \<const0>\;
  rx_cntvalueout_31(2) <= \<const0>\;
  rx_cntvalueout_31(1) <= \<const0>\;
  rx_cntvalueout_31(0) <= \<const0>\;
  rx_cntvalueout_32(8) <= \<const0>\;
  rx_cntvalueout_32(7) <= \<const0>\;
  rx_cntvalueout_32(6) <= \<const0>\;
  rx_cntvalueout_32(5) <= \<const0>\;
  rx_cntvalueout_32(4) <= \<const0>\;
  rx_cntvalueout_32(3) <= \<const0>\;
  rx_cntvalueout_32(2) <= \<const0>\;
  rx_cntvalueout_32(1) <= \<const0>\;
  rx_cntvalueout_32(0) <= \<const0>\;
  rx_cntvalueout_33(8) <= \<const0>\;
  rx_cntvalueout_33(7) <= \<const0>\;
  rx_cntvalueout_33(6) <= \<const0>\;
  rx_cntvalueout_33(5) <= \<const0>\;
  rx_cntvalueout_33(4) <= \<const0>\;
  rx_cntvalueout_33(3) <= \<const0>\;
  rx_cntvalueout_33(2) <= \<const0>\;
  rx_cntvalueout_33(1) <= \<const0>\;
  rx_cntvalueout_33(0) <= \<const0>\;
  rx_cntvalueout_34(8) <= \<const0>\;
  rx_cntvalueout_34(7) <= \<const0>\;
  rx_cntvalueout_34(6) <= \<const0>\;
  rx_cntvalueout_34(5) <= \<const0>\;
  rx_cntvalueout_34(4) <= \<const0>\;
  rx_cntvalueout_34(3) <= \<const0>\;
  rx_cntvalueout_34(2) <= \<const0>\;
  rx_cntvalueout_34(1) <= \<const0>\;
  rx_cntvalueout_34(0) <= \<const0>\;
  rx_cntvalueout_35(8) <= \<const0>\;
  rx_cntvalueout_35(7) <= \<const0>\;
  rx_cntvalueout_35(6) <= \<const0>\;
  rx_cntvalueout_35(5) <= \<const0>\;
  rx_cntvalueout_35(4) <= \<const0>\;
  rx_cntvalueout_35(3) <= \<const0>\;
  rx_cntvalueout_35(2) <= \<const0>\;
  rx_cntvalueout_35(1) <= \<const0>\;
  rx_cntvalueout_35(0) <= \<const0>\;
  rx_cntvalueout_36(8) <= \<const0>\;
  rx_cntvalueout_36(7) <= \<const0>\;
  rx_cntvalueout_36(6) <= \<const0>\;
  rx_cntvalueout_36(5) <= \<const0>\;
  rx_cntvalueout_36(4) <= \<const0>\;
  rx_cntvalueout_36(3) <= \<const0>\;
  rx_cntvalueout_36(2) <= \<const0>\;
  rx_cntvalueout_36(1) <= \<const0>\;
  rx_cntvalueout_36(0) <= \<const0>\;
  rx_cntvalueout_37(8) <= \<const0>\;
  rx_cntvalueout_37(7) <= \<const0>\;
  rx_cntvalueout_37(6) <= \<const0>\;
  rx_cntvalueout_37(5) <= \<const0>\;
  rx_cntvalueout_37(4) <= \<const0>\;
  rx_cntvalueout_37(3) <= \<const0>\;
  rx_cntvalueout_37(2) <= \<const0>\;
  rx_cntvalueout_37(1) <= \<const0>\;
  rx_cntvalueout_37(0) <= \<const0>\;
  rx_cntvalueout_38(8) <= \<const0>\;
  rx_cntvalueout_38(7) <= \<const0>\;
  rx_cntvalueout_38(6) <= \<const0>\;
  rx_cntvalueout_38(5) <= \<const0>\;
  rx_cntvalueout_38(4) <= \<const0>\;
  rx_cntvalueout_38(3) <= \<const0>\;
  rx_cntvalueout_38(2) <= \<const0>\;
  rx_cntvalueout_38(1) <= \<const0>\;
  rx_cntvalueout_38(0) <= \<const0>\;
  rx_cntvalueout_39(8) <= \<const0>\;
  rx_cntvalueout_39(7) <= \<const0>\;
  rx_cntvalueout_39(6) <= \<const0>\;
  rx_cntvalueout_39(5) <= \<const0>\;
  rx_cntvalueout_39(4) <= \<const0>\;
  rx_cntvalueout_39(3) <= \<const0>\;
  rx_cntvalueout_39(2) <= \<const0>\;
  rx_cntvalueout_39(1) <= \<const0>\;
  rx_cntvalueout_39(0) <= \<const0>\;
  rx_cntvalueout_4(8) <= \<const0>\;
  rx_cntvalueout_4(7) <= \<const0>\;
  rx_cntvalueout_4(6) <= \<const0>\;
  rx_cntvalueout_4(5) <= \<const0>\;
  rx_cntvalueout_4(4) <= \<const0>\;
  rx_cntvalueout_4(3) <= \<const0>\;
  rx_cntvalueout_4(2) <= \<const0>\;
  rx_cntvalueout_4(1) <= \<const0>\;
  rx_cntvalueout_4(0) <= \<const0>\;
  rx_cntvalueout_40(8) <= \<const0>\;
  rx_cntvalueout_40(7) <= \<const0>\;
  rx_cntvalueout_40(6) <= \<const0>\;
  rx_cntvalueout_40(5) <= \<const0>\;
  rx_cntvalueout_40(4) <= \<const0>\;
  rx_cntvalueout_40(3) <= \<const0>\;
  rx_cntvalueout_40(2) <= \<const0>\;
  rx_cntvalueout_40(1) <= \<const0>\;
  rx_cntvalueout_40(0) <= \<const0>\;
  rx_cntvalueout_41(8) <= \<const0>\;
  rx_cntvalueout_41(7) <= \<const0>\;
  rx_cntvalueout_41(6) <= \<const0>\;
  rx_cntvalueout_41(5) <= \<const0>\;
  rx_cntvalueout_41(4) <= \<const0>\;
  rx_cntvalueout_41(3) <= \<const0>\;
  rx_cntvalueout_41(2) <= \<const0>\;
  rx_cntvalueout_41(1) <= \<const0>\;
  rx_cntvalueout_41(0) <= \<const0>\;
  rx_cntvalueout_42(8) <= \<const0>\;
  rx_cntvalueout_42(7) <= \<const0>\;
  rx_cntvalueout_42(6) <= \<const0>\;
  rx_cntvalueout_42(5) <= \<const0>\;
  rx_cntvalueout_42(4) <= \<const0>\;
  rx_cntvalueout_42(3) <= \<const0>\;
  rx_cntvalueout_42(2) <= \<const0>\;
  rx_cntvalueout_42(1) <= \<const0>\;
  rx_cntvalueout_42(0) <= \<const0>\;
  rx_cntvalueout_43(8) <= \<const0>\;
  rx_cntvalueout_43(7) <= \<const0>\;
  rx_cntvalueout_43(6) <= \<const0>\;
  rx_cntvalueout_43(5) <= \<const0>\;
  rx_cntvalueout_43(4) <= \<const0>\;
  rx_cntvalueout_43(3) <= \<const0>\;
  rx_cntvalueout_43(2) <= \<const0>\;
  rx_cntvalueout_43(1) <= \<const0>\;
  rx_cntvalueout_43(0) <= \<const0>\;
  rx_cntvalueout_44(8) <= \<const0>\;
  rx_cntvalueout_44(7) <= \<const0>\;
  rx_cntvalueout_44(6) <= \<const0>\;
  rx_cntvalueout_44(5) <= \<const0>\;
  rx_cntvalueout_44(4) <= \<const0>\;
  rx_cntvalueout_44(3) <= \<const0>\;
  rx_cntvalueout_44(2) <= \<const0>\;
  rx_cntvalueout_44(1) <= \<const0>\;
  rx_cntvalueout_44(0) <= \<const0>\;
  rx_cntvalueout_45(8) <= \<const0>\;
  rx_cntvalueout_45(7) <= \<const0>\;
  rx_cntvalueout_45(6) <= \<const0>\;
  rx_cntvalueout_45(5) <= \<const0>\;
  rx_cntvalueout_45(4) <= \<const0>\;
  rx_cntvalueout_45(3) <= \<const0>\;
  rx_cntvalueout_45(2) <= \<const0>\;
  rx_cntvalueout_45(1) <= \<const0>\;
  rx_cntvalueout_45(0) <= \<const0>\;
  rx_cntvalueout_46(8) <= \<const0>\;
  rx_cntvalueout_46(7) <= \<const0>\;
  rx_cntvalueout_46(6) <= \<const0>\;
  rx_cntvalueout_46(5) <= \<const0>\;
  rx_cntvalueout_46(4) <= \<const0>\;
  rx_cntvalueout_46(3) <= \<const0>\;
  rx_cntvalueout_46(2) <= \<const0>\;
  rx_cntvalueout_46(1) <= \<const0>\;
  rx_cntvalueout_46(0) <= \<const0>\;
  rx_cntvalueout_47(8) <= \<const0>\;
  rx_cntvalueout_47(7) <= \<const0>\;
  rx_cntvalueout_47(6) <= \<const0>\;
  rx_cntvalueout_47(5) <= \<const0>\;
  rx_cntvalueout_47(4) <= \<const0>\;
  rx_cntvalueout_47(3) <= \<const0>\;
  rx_cntvalueout_47(2) <= \<const0>\;
  rx_cntvalueout_47(1) <= \<const0>\;
  rx_cntvalueout_47(0) <= \<const0>\;
  rx_cntvalueout_48(8) <= \<const0>\;
  rx_cntvalueout_48(7) <= \<const0>\;
  rx_cntvalueout_48(6) <= \<const0>\;
  rx_cntvalueout_48(5) <= \<const0>\;
  rx_cntvalueout_48(4) <= \<const0>\;
  rx_cntvalueout_48(3) <= \<const0>\;
  rx_cntvalueout_48(2) <= \<const0>\;
  rx_cntvalueout_48(1) <= \<const0>\;
  rx_cntvalueout_48(0) <= \<const0>\;
  rx_cntvalueout_49(8) <= \<const0>\;
  rx_cntvalueout_49(7) <= \<const0>\;
  rx_cntvalueout_49(6) <= \<const0>\;
  rx_cntvalueout_49(5) <= \<const0>\;
  rx_cntvalueout_49(4) <= \<const0>\;
  rx_cntvalueout_49(3) <= \<const0>\;
  rx_cntvalueout_49(2) <= \<const0>\;
  rx_cntvalueout_49(1) <= \<const0>\;
  rx_cntvalueout_49(0) <= \<const0>\;
  rx_cntvalueout_5(8) <= \<const0>\;
  rx_cntvalueout_5(7) <= \<const0>\;
  rx_cntvalueout_5(6) <= \<const0>\;
  rx_cntvalueout_5(5) <= \<const0>\;
  rx_cntvalueout_5(4) <= \<const0>\;
  rx_cntvalueout_5(3) <= \<const0>\;
  rx_cntvalueout_5(2) <= \<const0>\;
  rx_cntvalueout_5(1) <= \<const0>\;
  rx_cntvalueout_5(0) <= \<const0>\;
  rx_cntvalueout_50(8) <= \<const0>\;
  rx_cntvalueout_50(7) <= \<const0>\;
  rx_cntvalueout_50(6) <= \<const0>\;
  rx_cntvalueout_50(5) <= \<const0>\;
  rx_cntvalueout_50(4) <= \<const0>\;
  rx_cntvalueout_50(3) <= \<const0>\;
  rx_cntvalueout_50(2) <= \<const0>\;
  rx_cntvalueout_50(1) <= \<const0>\;
  rx_cntvalueout_50(0) <= \<const0>\;
  rx_cntvalueout_51(8) <= \<const0>\;
  rx_cntvalueout_51(7) <= \<const0>\;
  rx_cntvalueout_51(6) <= \<const0>\;
  rx_cntvalueout_51(5) <= \<const0>\;
  rx_cntvalueout_51(4) <= \<const0>\;
  rx_cntvalueout_51(3) <= \<const0>\;
  rx_cntvalueout_51(2) <= \<const0>\;
  rx_cntvalueout_51(1) <= \<const0>\;
  rx_cntvalueout_51(0) <= \<const0>\;
  rx_cntvalueout_6(8) <= \<const0>\;
  rx_cntvalueout_6(7) <= \<const0>\;
  rx_cntvalueout_6(6) <= \<const0>\;
  rx_cntvalueout_6(5) <= \<const0>\;
  rx_cntvalueout_6(4) <= \<const0>\;
  rx_cntvalueout_6(3) <= \<const0>\;
  rx_cntvalueout_6(2) <= \<const0>\;
  rx_cntvalueout_6(1) <= \<const0>\;
  rx_cntvalueout_6(0) <= \<const0>\;
  rx_cntvalueout_7(8) <= \<const0>\;
  rx_cntvalueout_7(7) <= \<const0>\;
  rx_cntvalueout_7(6) <= \<const0>\;
  rx_cntvalueout_7(5) <= \<const0>\;
  rx_cntvalueout_7(4) <= \<const0>\;
  rx_cntvalueout_7(3) <= \<const0>\;
  rx_cntvalueout_7(2) <= \<const0>\;
  rx_cntvalueout_7(1) <= \<const0>\;
  rx_cntvalueout_7(0) <= \<const0>\;
  rx_cntvalueout_8(8) <= \<const0>\;
  rx_cntvalueout_8(7) <= \<const0>\;
  rx_cntvalueout_8(6) <= \<const0>\;
  rx_cntvalueout_8(5) <= \<const0>\;
  rx_cntvalueout_8(4) <= \<const0>\;
  rx_cntvalueout_8(3) <= \<const0>\;
  rx_cntvalueout_8(2) <= \<const0>\;
  rx_cntvalueout_8(1) <= \<const0>\;
  rx_cntvalueout_8(0) <= \<const0>\;
  rx_cntvalueout_9(8) <= \<const0>\;
  rx_cntvalueout_9(7) <= \<const0>\;
  rx_cntvalueout_9(6) <= \<const0>\;
  rx_cntvalueout_9(5) <= \<const0>\;
  rx_cntvalueout_9(4) <= \<const0>\;
  rx_cntvalueout_9(3) <= \<const0>\;
  rx_cntvalueout_9(2) <= \<const0>\;
  rx_cntvalueout_9(1) <= \<const0>\;
  rx_cntvalueout_9(0) <= \<const0>\;
  rx_cntvalueout_ext_0(8) <= \<const0>\;
  rx_cntvalueout_ext_0(7) <= \<const0>\;
  rx_cntvalueout_ext_0(6) <= \<const0>\;
  rx_cntvalueout_ext_0(5) <= \<const0>\;
  rx_cntvalueout_ext_0(4) <= \<const0>\;
  rx_cntvalueout_ext_0(3) <= \<const0>\;
  rx_cntvalueout_ext_0(2) <= \<const0>\;
  rx_cntvalueout_ext_0(1) <= \<const0>\;
  rx_cntvalueout_ext_0(0) <= \<const0>\;
  rx_cntvalueout_ext_1(8) <= \<const0>\;
  rx_cntvalueout_ext_1(7) <= \<const0>\;
  rx_cntvalueout_ext_1(6) <= \<const0>\;
  rx_cntvalueout_ext_1(5) <= \<const0>\;
  rx_cntvalueout_ext_1(4) <= \<const0>\;
  rx_cntvalueout_ext_1(3) <= \<const0>\;
  rx_cntvalueout_ext_1(2) <= \<const0>\;
  rx_cntvalueout_ext_1(1) <= \<const0>\;
  rx_cntvalueout_ext_1(0) <= \<const0>\;
  rx_cntvalueout_ext_10(8) <= \<const0>\;
  rx_cntvalueout_ext_10(7) <= \<const0>\;
  rx_cntvalueout_ext_10(6) <= \<const0>\;
  rx_cntvalueout_ext_10(5) <= \<const0>\;
  rx_cntvalueout_ext_10(4) <= \<const0>\;
  rx_cntvalueout_ext_10(3) <= \<const0>\;
  rx_cntvalueout_ext_10(2) <= \<const0>\;
  rx_cntvalueout_ext_10(1) <= \<const0>\;
  rx_cntvalueout_ext_10(0) <= \<const0>\;
  rx_cntvalueout_ext_11(8) <= \<const0>\;
  rx_cntvalueout_ext_11(7) <= \<const0>\;
  rx_cntvalueout_ext_11(6) <= \<const0>\;
  rx_cntvalueout_ext_11(5) <= \<const0>\;
  rx_cntvalueout_ext_11(4) <= \<const0>\;
  rx_cntvalueout_ext_11(3) <= \<const0>\;
  rx_cntvalueout_ext_11(2) <= \<const0>\;
  rx_cntvalueout_ext_11(1) <= \<const0>\;
  rx_cntvalueout_ext_11(0) <= \<const0>\;
  rx_cntvalueout_ext_12(8) <= \<const0>\;
  rx_cntvalueout_ext_12(7) <= \<const0>\;
  rx_cntvalueout_ext_12(6) <= \<const0>\;
  rx_cntvalueout_ext_12(5) <= \<const0>\;
  rx_cntvalueout_ext_12(4) <= \<const0>\;
  rx_cntvalueout_ext_12(3) <= \<const0>\;
  rx_cntvalueout_ext_12(2) <= \<const0>\;
  rx_cntvalueout_ext_12(1) <= \<const0>\;
  rx_cntvalueout_ext_12(0) <= \<const0>\;
  rx_cntvalueout_ext_13(8) <= \<const0>\;
  rx_cntvalueout_ext_13(7) <= \<const0>\;
  rx_cntvalueout_ext_13(6) <= \<const0>\;
  rx_cntvalueout_ext_13(5) <= \<const0>\;
  rx_cntvalueout_ext_13(4) <= \<const0>\;
  rx_cntvalueout_ext_13(3) <= \<const0>\;
  rx_cntvalueout_ext_13(2) <= \<const0>\;
  rx_cntvalueout_ext_13(1) <= \<const0>\;
  rx_cntvalueout_ext_13(0) <= \<const0>\;
  rx_cntvalueout_ext_14(8) <= \<const0>\;
  rx_cntvalueout_ext_14(7) <= \<const0>\;
  rx_cntvalueout_ext_14(6) <= \<const0>\;
  rx_cntvalueout_ext_14(5) <= \<const0>\;
  rx_cntvalueout_ext_14(4) <= \<const0>\;
  rx_cntvalueout_ext_14(3) <= \<const0>\;
  rx_cntvalueout_ext_14(2) <= \<const0>\;
  rx_cntvalueout_ext_14(1) <= \<const0>\;
  rx_cntvalueout_ext_14(0) <= \<const0>\;
  rx_cntvalueout_ext_15(8) <= \<const0>\;
  rx_cntvalueout_ext_15(7) <= \<const0>\;
  rx_cntvalueout_ext_15(6) <= \<const0>\;
  rx_cntvalueout_ext_15(5) <= \<const0>\;
  rx_cntvalueout_ext_15(4) <= \<const0>\;
  rx_cntvalueout_ext_15(3) <= \<const0>\;
  rx_cntvalueout_ext_15(2) <= \<const0>\;
  rx_cntvalueout_ext_15(1) <= \<const0>\;
  rx_cntvalueout_ext_15(0) <= \<const0>\;
  rx_cntvalueout_ext_16(8) <= \<const0>\;
  rx_cntvalueout_ext_16(7) <= \<const0>\;
  rx_cntvalueout_ext_16(6) <= \<const0>\;
  rx_cntvalueout_ext_16(5) <= \<const0>\;
  rx_cntvalueout_ext_16(4) <= \<const0>\;
  rx_cntvalueout_ext_16(3) <= \<const0>\;
  rx_cntvalueout_ext_16(2) <= \<const0>\;
  rx_cntvalueout_ext_16(1) <= \<const0>\;
  rx_cntvalueout_ext_16(0) <= \<const0>\;
  rx_cntvalueout_ext_17(8) <= \<const0>\;
  rx_cntvalueout_ext_17(7) <= \<const0>\;
  rx_cntvalueout_ext_17(6) <= \<const0>\;
  rx_cntvalueout_ext_17(5) <= \<const0>\;
  rx_cntvalueout_ext_17(4) <= \<const0>\;
  rx_cntvalueout_ext_17(3) <= \<const0>\;
  rx_cntvalueout_ext_17(2) <= \<const0>\;
  rx_cntvalueout_ext_17(1) <= \<const0>\;
  rx_cntvalueout_ext_17(0) <= \<const0>\;
  rx_cntvalueout_ext_18(8) <= \<const0>\;
  rx_cntvalueout_ext_18(7) <= \<const0>\;
  rx_cntvalueout_ext_18(6) <= \<const0>\;
  rx_cntvalueout_ext_18(5) <= \<const0>\;
  rx_cntvalueout_ext_18(4) <= \<const0>\;
  rx_cntvalueout_ext_18(3) <= \<const0>\;
  rx_cntvalueout_ext_18(2) <= \<const0>\;
  rx_cntvalueout_ext_18(1) <= \<const0>\;
  rx_cntvalueout_ext_18(0) <= \<const0>\;
  rx_cntvalueout_ext_19(8) <= \<const0>\;
  rx_cntvalueout_ext_19(7) <= \<const0>\;
  rx_cntvalueout_ext_19(6) <= \<const0>\;
  rx_cntvalueout_ext_19(5) <= \<const0>\;
  rx_cntvalueout_ext_19(4) <= \<const0>\;
  rx_cntvalueout_ext_19(3) <= \<const0>\;
  rx_cntvalueout_ext_19(2) <= \<const0>\;
  rx_cntvalueout_ext_19(1) <= \<const0>\;
  rx_cntvalueout_ext_19(0) <= \<const0>\;
  rx_cntvalueout_ext_2(8) <= \<const0>\;
  rx_cntvalueout_ext_2(7) <= \<const0>\;
  rx_cntvalueout_ext_2(6) <= \<const0>\;
  rx_cntvalueout_ext_2(5) <= \<const0>\;
  rx_cntvalueout_ext_2(4) <= \<const0>\;
  rx_cntvalueout_ext_2(3) <= \<const0>\;
  rx_cntvalueout_ext_2(2) <= \<const0>\;
  rx_cntvalueout_ext_2(1) <= \<const0>\;
  rx_cntvalueout_ext_2(0) <= \<const0>\;
  rx_cntvalueout_ext_20(8) <= \<const0>\;
  rx_cntvalueout_ext_20(7) <= \<const0>\;
  rx_cntvalueout_ext_20(6) <= \<const0>\;
  rx_cntvalueout_ext_20(5) <= \<const0>\;
  rx_cntvalueout_ext_20(4) <= \<const0>\;
  rx_cntvalueout_ext_20(3) <= \<const0>\;
  rx_cntvalueout_ext_20(2) <= \<const0>\;
  rx_cntvalueout_ext_20(1) <= \<const0>\;
  rx_cntvalueout_ext_20(0) <= \<const0>\;
  rx_cntvalueout_ext_21(8) <= \<const0>\;
  rx_cntvalueout_ext_21(7) <= \<const0>\;
  rx_cntvalueout_ext_21(6) <= \<const0>\;
  rx_cntvalueout_ext_21(5) <= \<const0>\;
  rx_cntvalueout_ext_21(4) <= \<const0>\;
  rx_cntvalueout_ext_21(3) <= \<const0>\;
  rx_cntvalueout_ext_21(2) <= \<const0>\;
  rx_cntvalueout_ext_21(1) <= \<const0>\;
  rx_cntvalueout_ext_21(0) <= \<const0>\;
  rx_cntvalueout_ext_22(8) <= \<const0>\;
  rx_cntvalueout_ext_22(7) <= \<const0>\;
  rx_cntvalueout_ext_22(6) <= \<const0>\;
  rx_cntvalueout_ext_22(5) <= \<const0>\;
  rx_cntvalueout_ext_22(4) <= \<const0>\;
  rx_cntvalueout_ext_22(3) <= \<const0>\;
  rx_cntvalueout_ext_22(2) <= \<const0>\;
  rx_cntvalueout_ext_22(1) <= \<const0>\;
  rx_cntvalueout_ext_22(0) <= \<const0>\;
  rx_cntvalueout_ext_23(8) <= \<const0>\;
  rx_cntvalueout_ext_23(7) <= \<const0>\;
  rx_cntvalueout_ext_23(6) <= \<const0>\;
  rx_cntvalueout_ext_23(5) <= \<const0>\;
  rx_cntvalueout_ext_23(4) <= \<const0>\;
  rx_cntvalueout_ext_23(3) <= \<const0>\;
  rx_cntvalueout_ext_23(2) <= \<const0>\;
  rx_cntvalueout_ext_23(1) <= \<const0>\;
  rx_cntvalueout_ext_23(0) <= \<const0>\;
  rx_cntvalueout_ext_24(8) <= \<const0>\;
  rx_cntvalueout_ext_24(7) <= \<const0>\;
  rx_cntvalueout_ext_24(6) <= \<const0>\;
  rx_cntvalueout_ext_24(5) <= \<const0>\;
  rx_cntvalueout_ext_24(4) <= \<const0>\;
  rx_cntvalueout_ext_24(3) <= \<const0>\;
  rx_cntvalueout_ext_24(2) <= \<const0>\;
  rx_cntvalueout_ext_24(1) <= \<const0>\;
  rx_cntvalueout_ext_24(0) <= \<const0>\;
  rx_cntvalueout_ext_25(8) <= \<const0>\;
  rx_cntvalueout_ext_25(7) <= \<const0>\;
  rx_cntvalueout_ext_25(6) <= \<const0>\;
  rx_cntvalueout_ext_25(5) <= \<const0>\;
  rx_cntvalueout_ext_25(4) <= \<const0>\;
  rx_cntvalueout_ext_25(3) <= \<const0>\;
  rx_cntvalueout_ext_25(2) <= \<const0>\;
  rx_cntvalueout_ext_25(1) <= \<const0>\;
  rx_cntvalueout_ext_25(0) <= \<const0>\;
  rx_cntvalueout_ext_26(8) <= \<const0>\;
  rx_cntvalueout_ext_26(7) <= \<const0>\;
  rx_cntvalueout_ext_26(6) <= \<const0>\;
  rx_cntvalueout_ext_26(5) <= \<const0>\;
  rx_cntvalueout_ext_26(4) <= \<const0>\;
  rx_cntvalueout_ext_26(3) <= \<const0>\;
  rx_cntvalueout_ext_26(2) <= \<const0>\;
  rx_cntvalueout_ext_26(1) <= \<const0>\;
  rx_cntvalueout_ext_26(0) <= \<const0>\;
  rx_cntvalueout_ext_27(8) <= \<const0>\;
  rx_cntvalueout_ext_27(7) <= \<const0>\;
  rx_cntvalueout_ext_27(6) <= \<const0>\;
  rx_cntvalueout_ext_27(5) <= \<const0>\;
  rx_cntvalueout_ext_27(4) <= \<const0>\;
  rx_cntvalueout_ext_27(3) <= \<const0>\;
  rx_cntvalueout_ext_27(2) <= \<const0>\;
  rx_cntvalueout_ext_27(1) <= \<const0>\;
  rx_cntvalueout_ext_27(0) <= \<const0>\;
  rx_cntvalueout_ext_28(8) <= \<const0>\;
  rx_cntvalueout_ext_28(7) <= \<const0>\;
  rx_cntvalueout_ext_28(6) <= \<const0>\;
  rx_cntvalueout_ext_28(5) <= \<const0>\;
  rx_cntvalueout_ext_28(4) <= \<const0>\;
  rx_cntvalueout_ext_28(3) <= \<const0>\;
  rx_cntvalueout_ext_28(2) <= \<const0>\;
  rx_cntvalueout_ext_28(1) <= \<const0>\;
  rx_cntvalueout_ext_28(0) <= \<const0>\;
  rx_cntvalueout_ext_29(8) <= \<const0>\;
  rx_cntvalueout_ext_29(7) <= \<const0>\;
  rx_cntvalueout_ext_29(6) <= \<const0>\;
  rx_cntvalueout_ext_29(5) <= \<const0>\;
  rx_cntvalueout_ext_29(4) <= \<const0>\;
  rx_cntvalueout_ext_29(3) <= \<const0>\;
  rx_cntvalueout_ext_29(2) <= \<const0>\;
  rx_cntvalueout_ext_29(1) <= \<const0>\;
  rx_cntvalueout_ext_29(0) <= \<const0>\;
  rx_cntvalueout_ext_3(8) <= \<const0>\;
  rx_cntvalueout_ext_3(7) <= \<const0>\;
  rx_cntvalueout_ext_3(6) <= \<const0>\;
  rx_cntvalueout_ext_3(5) <= \<const0>\;
  rx_cntvalueout_ext_3(4) <= \<const0>\;
  rx_cntvalueout_ext_3(3) <= \<const0>\;
  rx_cntvalueout_ext_3(2) <= \<const0>\;
  rx_cntvalueout_ext_3(1) <= \<const0>\;
  rx_cntvalueout_ext_3(0) <= \<const0>\;
  rx_cntvalueout_ext_30(8) <= \<const0>\;
  rx_cntvalueout_ext_30(7) <= \<const0>\;
  rx_cntvalueout_ext_30(6) <= \<const0>\;
  rx_cntvalueout_ext_30(5) <= \<const0>\;
  rx_cntvalueout_ext_30(4) <= \<const0>\;
  rx_cntvalueout_ext_30(3) <= \<const0>\;
  rx_cntvalueout_ext_30(2) <= \<const0>\;
  rx_cntvalueout_ext_30(1) <= \<const0>\;
  rx_cntvalueout_ext_30(0) <= \<const0>\;
  rx_cntvalueout_ext_31(8) <= \<const0>\;
  rx_cntvalueout_ext_31(7) <= \<const0>\;
  rx_cntvalueout_ext_31(6) <= \<const0>\;
  rx_cntvalueout_ext_31(5) <= \<const0>\;
  rx_cntvalueout_ext_31(4) <= \<const0>\;
  rx_cntvalueout_ext_31(3) <= \<const0>\;
  rx_cntvalueout_ext_31(2) <= \<const0>\;
  rx_cntvalueout_ext_31(1) <= \<const0>\;
  rx_cntvalueout_ext_31(0) <= \<const0>\;
  rx_cntvalueout_ext_32(8) <= \<const0>\;
  rx_cntvalueout_ext_32(7) <= \<const0>\;
  rx_cntvalueout_ext_32(6) <= \<const0>\;
  rx_cntvalueout_ext_32(5) <= \<const0>\;
  rx_cntvalueout_ext_32(4) <= \<const0>\;
  rx_cntvalueout_ext_32(3) <= \<const0>\;
  rx_cntvalueout_ext_32(2) <= \<const0>\;
  rx_cntvalueout_ext_32(1) <= \<const0>\;
  rx_cntvalueout_ext_32(0) <= \<const0>\;
  rx_cntvalueout_ext_33(8) <= \<const0>\;
  rx_cntvalueout_ext_33(7) <= \<const0>\;
  rx_cntvalueout_ext_33(6) <= \<const0>\;
  rx_cntvalueout_ext_33(5) <= \<const0>\;
  rx_cntvalueout_ext_33(4) <= \<const0>\;
  rx_cntvalueout_ext_33(3) <= \<const0>\;
  rx_cntvalueout_ext_33(2) <= \<const0>\;
  rx_cntvalueout_ext_33(1) <= \<const0>\;
  rx_cntvalueout_ext_33(0) <= \<const0>\;
  rx_cntvalueout_ext_34(8) <= \<const0>\;
  rx_cntvalueout_ext_34(7) <= \<const0>\;
  rx_cntvalueout_ext_34(6) <= \<const0>\;
  rx_cntvalueout_ext_34(5) <= \<const0>\;
  rx_cntvalueout_ext_34(4) <= \<const0>\;
  rx_cntvalueout_ext_34(3) <= \<const0>\;
  rx_cntvalueout_ext_34(2) <= \<const0>\;
  rx_cntvalueout_ext_34(1) <= \<const0>\;
  rx_cntvalueout_ext_34(0) <= \<const0>\;
  rx_cntvalueout_ext_35(8) <= \<const0>\;
  rx_cntvalueout_ext_35(7) <= \<const0>\;
  rx_cntvalueout_ext_35(6) <= \<const0>\;
  rx_cntvalueout_ext_35(5) <= \<const0>\;
  rx_cntvalueout_ext_35(4) <= \<const0>\;
  rx_cntvalueout_ext_35(3) <= \<const0>\;
  rx_cntvalueout_ext_35(2) <= \<const0>\;
  rx_cntvalueout_ext_35(1) <= \<const0>\;
  rx_cntvalueout_ext_35(0) <= \<const0>\;
  rx_cntvalueout_ext_36(8) <= \<const0>\;
  rx_cntvalueout_ext_36(7) <= \<const0>\;
  rx_cntvalueout_ext_36(6) <= \<const0>\;
  rx_cntvalueout_ext_36(5) <= \<const0>\;
  rx_cntvalueout_ext_36(4) <= \<const0>\;
  rx_cntvalueout_ext_36(3) <= \<const0>\;
  rx_cntvalueout_ext_36(2) <= \<const0>\;
  rx_cntvalueout_ext_36(1) <= \<const0>\;
  rx_cntvalueout_ext_36(0) <= \<const0>\;
  rx_cntvalueout_ext_37(8) <= \<const0>\;
  rx_cntvalueout_ext_37(7) <= \<const0>\;
  rx_cntvalueout_ext_37(6) <= \<const0>\;
  rx_cntvalueout_ext_37(5) <= \<const0>\;
  rx_cntvalueout_ext_37(4) <= \<const0>\;
  rx_cntvalueout_ext_37(3) <= \<const0>\;
  rx_cntvalueout_ext_37(2) <= \<const0>\;
  rx_cntvalueout_ext_37(1) <= \<const0>\;
  rx_cntvalueout_ext_37(0) <= \<const0>\;
  rx_cntvalueout_ext_38(8) <= \<const0>\;
  rx_cntvalueout_ext_38(7) <= \<const0>\;
  rx_cntvalueout_ext_38(6) <= \<const0>\;
  rx_cntvalueout_ext_38(5) <= \<const0>\;
  rx_cntvalueout_ext_38(4) <= \<const0>\;
  rx_cntvalueout_ext_38(3) <= \<const0>\;
  rx_cntvalueout_ext_38(2) <= \<const0>\;
  rx_cntvalueout_ext_38(1) <= \<const0>\;
  rx_cntvalueout_ext_38(0) <= \<const0>\;
  rx_cntvalueout_ext_39(8) <= \<const0>\;
  rx_cntvalueout_ext_39(7) <= \<const0>\;
  rx_cntvalueout_ext_39(6) <= \<const0>\;
  rx_cntvalueout_ext_39(5) <= \<const0>\;
  rx_cntvalueout_ext_39(4) <= \<const0>\;
  rx_cntvalueout_ext_39(3) <= \<const0>\;
  rx_cntvalueout_ext_39(2) <= \<const0>\;
  rx_cntvalueout_ext_39(1) <= \<const0>\;
  rx_cntvalueout_ext_39(0) <= \<const0>\;
  rx_cntvalueout_ext_4(8) <= \<const0>\;
  rx_cntvalueout_ext_4(7) <= \<const0>\;
  rx_cntvalueout_ext_4(6) <= \<const0>\;
  rx_cntvalueout_ext_4(5) <= \<const0>\;
  rx_cntvalueout_ext_4(4) <= \<const0>\;
  rx_cntvalueout_ext_4(3) <= \<const0>\;
  rx_cntvalueout_ext_4(2) <= \<const0>\;
  rx_cntvalueout_ext_4(1) <= \<const0>\;
  rx_cntvalueout_ext_4(0) <= \<const0>\;
  rx_cntvalueout_ext_40(8) <= \<const0>\;
  rx_cntvalueout_ext_40(7) <= \<const0>\;
  rx_cntvalueout_ext_40(6) <= \<const0>\;
  rx_cntvalueout_ext_40(5) <= \<const0>\;
  rx_cntvalueout_ext_40(4) <= \<const0>\;
  rx_cntvalueout_ext_40(3) <= \<const0>\;
  rx_cntvalueout_ext_40(2) <= \<const0>\;
  rx_cntvalueout_ext_40(1) <= \<const0>\;
  rx_cntvalueout_ext_40(0) <= \<const0>\;
  rx_cntvalueout_ext_41(8) <= \<const0>\;
  rx_cntvalueout_ext_41(7) <= \<const0>\;
  rx_cntvalueout_ext_41(6) <= \<const0>\;
  rx_cntvalueout_ext_41(5) <= \<const0>\;
  rx_cntvalueout_ext_41(4) <= \<const0>\;
  rx_cntvalueout_ext_41(3) <= \<const0>\;
  rx_cntvalueout_ext_41(2) <= \<const0>\;
  rx_cntvalueout_ext_41(1) <= \<const0>\;
  rx_cntvalueout_ext_41(0) <= \<const0>\;
  rx_cntvalueout_ext_42(8) <= \<const0>\;
  rx_cntvalueout_ext_42(7) <= \<const0>\;
  rx_cntvalueout_ext_42(6) <= \<const0>\;
  rx_cntvalueout_ext_42(5) <= \<const0>\;
  rx_cntvalueout_ext_42(4) <= \<const0>\;
  rx_cntvalueout_ext_42(3) <= \<const0>\;
  rx_cntvalueout_ext_42(2) <= \<const0>\;
  rx_cntvalueout_ext_42(1) <= \<const0>\;
  rx_cntvalueout_ext_42(0) <= \<const0>\;
  rx_cntvalueout_ext_43(8) <= \<const0>\;
  rx_cntvalueout_ext_43(7) <= \<const0>\;
  rx_cntvalueout_ext_43(6) <= \<const0>\;
  rx_cntvalueout_ext_43(5) <= \<const0>\;
  rx_cntvalueout_ext_43(4) <= \<const0>\;
  rx_cntvalueout_ext_43(3) <= \<const0>\;
  rx_cntvalueout_ext_43(2) <= \<const0>\;
  rx_cntvalueout_ext_43(1) <= \<const0>\;
  rx_cntvalueout_ext_43(0) <= \<const0>\;
  rx_cntvalueout_ext_44(8) <= \<const0>\;
  rx_cntvalueout_ext_44(7) <= \<const0>\;
  rx_cntvalueout_ext_44(6) <= \<const0>\;
  rx_cntvalueout_ext_44(5) <= \<const0>\;
  rx_cntvalueout_ext_44(4) <= \<const0>\;
  rx_cntvalueout_ext_44(3) <= \<const0>\;
  rx_cntvalueout_ext_44(2) <= \<const0>\;
  rx_cntvalueout_ext_44(1) <= \<const0>\;
  rx_cntvalueout_ext_44(0) <= \<const0>\;
  rx_cntvalueout_ext_45(8) <= \<const0>\;
  rx_cntvalueout_ext_45(7) <= \<const0>\;
  rx_cntvalueout_ext_45(6) <= \<const0>\;
  rx_cntvalueout_ext_45(5) <= \<const0>\;
  rx_cntvalueout_ext_45(4) <= \<const0>\;
  rx_cntvalueout_ext_45(3) <= \<const0>\;
  rx_cntvalueout_ext_45(2) <= \<const0>\;
  rx_cntvalueout_ext_45(1) <= \<const0>\;
  rx_cntvalueout_ext_45(0) <= \<const0>\;
  rx_cntvalueout_ext_46(8) <= \<const0>\;
  rx_cntvalueout_ext_46(7) <= \<const0>\;
  rx_cntvalueout_ext_46(6) <= \<const0>\;
  rx_cntvalueout_ext_46(5) <= \<const0>\;
  rx_cntvalueout_ext_46(4) <= \<const0>\;
  rx_cntvalueout_ext_46(3) <= \<const0>\;
  rx_cntvalueout_ext_46(2) <= \<const0>\;
  rx_cntvalueout_ext_46(1) <= \<const0>\;
  rx_cntvalueout_ext_46(0) <= \<const0>\;
  rx_cntvalueout_ext_47(8) <= \<const0>\;
  rx_cntvalueout_ext_47(7) <= \<const0>\;
  rx_cntvalueout_ext_47(6) <= \<const0>\;
  rx_cntvalueout_ext_47(5) <= \<const0>\;
  rx_cntvalueout_ext_47(4) <= \<const0>\;
  rx_cntvalueout_ext_47(3) <= \<const0>\;
  rx_cntvalueout_ext_47(2) <= \<const0>\;
  rx_cntvalueout_ext_47(1) <= \<const0>\;
  rx_cntvalueout_ext_47(0) <= \<const0>\;
  rx_cntvalueout_ext_48(8) <= \<const0>\;
  rx_cntvalueout_ext_48(7) <= \<const0>\;
  rx_cntvalueout_ext_48(6) <= \<const0>\;
  rx_cntvalueout_ext_48(5) <= \<const0>\;
  rx_cntvalueout_ext_48(4) <= \<const0>\;
  rx_cntvalueout_ext_48(3) <= \<const0>\;
  rx_cntvalueout_ext_48(2) <= \<const0>\;
  rx_cntvalueout_ext_48(1) <= \<const0>\;
  rx_cntvalueout_ext_48(0) <= \<const0>\;
  rx_cntvalueout_ext_49(8) <= \<const0>\;
  rx_cntvalueout_ext_49(7) <= \<const0>\;
  rx_cntvalueout_ext_49(6) <= \<const0>\;
  rx_cntvalueout_ext_49(5) <= \<const0>\;
  rx_cntvalueout_ext_49(4) <= \<const0>\;
  rx_cntvalueout_ext_49(3) <= \<const0>\;
  rx_cntvalueout_ext_49(2) <= \<const0>\;
  rx_cntvalueout_ext_49(1) <= \<const0>\;
  rx_cntvalueout_ext_49(0) <= \<const0>\;
  rx_cntvalueout_ext_5(8) <= \<const0>\;
  rx_cntvalueout_ext_5(7) <= \<const0>\;
  rx_cntvalueout_ext_5(6) <= \<const0>\;
  rx_cntvalueout_ext_5(5) <= \<const0>\;
  rx_cntvalueout_ext_5(4) <= \<const0>\;
  rx_cntvalueout_ext_5(3) <= \<const0>\;
  rx_cntvalueout_ext_5(2) <= \<const0>\;
  rx_cntvalueout_ext_5(1) <= \<const0>\;
  rx_cntvalueout_ext_5(0) <= \<const0>\;
  rx_cntvalueout_ext_50(8) <= \<const0>\;
  rx_cntvalueout_ext_50(7) <= \<const0>\;
  rx_cntvalueout_ext_50(6) <= \<const0>\;
  rx_cntvalueout_ext_50(5) <= \<const0>\;
  rx_cntvalueout_ext_50(4) <= \<const0>\;
  rx_cntvalueout_ext_50(3) <= \<const0>\;
  rx_cntvalueout_ext_50(2) <= \<const0>\;
  rx_cntvalueout_ext_50(1) <= \<const0>\;
  rx_cntvalueout_ext_50(0) <= \<const0>\;
  rx_cntvalueout_ext_51(8) <= \<const0>\;
  rx_cntvalueout_ext_51(7) <= \<const0>\;
  rx_cntvalueout_ext_51(6) <= \<const0>\;
  rx_cntvalueout_ext_51(5) <= \<const0>\;
  rx_cntvalueout_ext_51(4) <= \<const0>\;
  rx_cntvalueout_ext_51(3) <= \<const0>\;
  rx_cntvalueout_ext_51(2) <= \<const0>\;
  rx_cntvalueout_ext_51(1) <= \<const0>\;
  rx_cntvalueout_ext_51(0) <= \<const0>\;
  rx_cntvalueout_ext_6(8) <= \<const0>\;
  rx_cntvalueout_ext_6(7) <= \<const0>\;
  rx_cntvalueout_ext_6(6) <= \<const0>\;
  rx_cntvalueout_ext_6(5) <= \<const0>\;
  rx_cntvalueout_ext_6(4) <= \<const0>\;
  rx_cntvalueout_ext_6(3) <= \<const0>\;
  rx_cntvalueout_ext_6(2) <= \<const0>\;
  rx_cntvalueout_ext_6(1) <= \<const0>\;
  rx_cntvalueout_ext_6(0) <= \<const0>\;
  rx_cntvalueout_ext_7(8) <= \<const0>\;
  rx_cntvalueout_ext_7(7) <= \<const0>\;
  rx_cntvalueout_ext_7(6) <= \<const0>\;
  rx_cntvalueout_ext_7(5) <= \<const0>\;
  rx_cntvalueout_ext_7(4) <= \<const0>\;
  rx_cntvalueout_ext_7(3) <= \<const0>\;
  rx_cntvalueout_ext_7(2) <= \<const0>\;
  rx_cntvalueout_ext_7(1) <= \<const0>\;
  rx_cntvalueout_ext_7(0) <= \<const0>\;
  rx_cntvalueout_ext_8(8) <= \<const0>\;
  rx_cntvalueout_ext_8(7) <= \<const0>\;
  rx_cntvalueout_ext_8(6) <= \<const0>\;
  rx_cntvalueout_ext_8(5) <= \<const0>\;
  rx_cntvalueout_ext_8(4) <= \<const0>\;
  rx_cntvalueout_ext_8(3) <= \<const0>\;
  rx_cntvalueout_ext_8(2) <= \<const0>\;
  rx_cntvalueout_ext_8(1) <= \<const0>\;
  rx_cntvalueout_ext_8(0) <= \<const0>\;
  rx_cntvalueout_ext_9(8) <= \<const0>\;
  rx_cntvalueout_ext_9(7) <= \<const0>\;
  rx_cntvalueout_ext_9(6) <= \<const0>\;
  rx_cntvalueout_ext_9(5) <= \<const0>\;
  rx_cntvalueout_ext_9(4) <= \<const0>\;
  rx_cntvalueout_ext_9(3) <= \<const0>\;
  rx_cntvalueout_ext_9(2) <= \<const0>\;
  rx_cntvalueout_ext_9(1) <= \<const0>\;
  rx_cntvalueout_ext_9(0) <= \<const0>\;
  rxtx_bitslip_sync_done <= \<const0>\;
  shared_pll0_clkoutphy_out <= \<const0>\;
  shared_pll1_clkoutphy_out <= \<const0>\;
  tx_cntvalueout_0(8) <= \<const0>\;
  tx_cntvalueout_0(7) <= \<const0>\;
  tx_cntvalueout_0(6) <= \<const0>\;
  tx_cntvalueout_0(5) <= \<const0>\;
  tx_cntvalueout_0(4) <= \<const0>\;
  tx_cntvalueout_0(3) <= \<const0>\;
  tx_cntvalueout_0(2) <= \<const0>\;
  tx_cntvalueout_0(1) <= \<const0>\;
  tx_cntvalueout_0(0) <= \<const0>\;
  tx_cntvalueout_1(8) <= \<const0>\;
  tx_cntvalueout_1(7) <= \<const0>\;
  tx_cntvalueout_1(6) <= \<const0>\;
  tx_cntvalueout_1(5) <= \<const0>\;
  tx_cntvalueout_1(4) <= \<const0>\;
  tx_cntvalueout_1(3) <= \<const0>\;
  tx_cntvalueout_1(2) <= \<const0>\;
  tx_cntvalueout_1(1) <= \<const0>\;
  tx_cntvalueout_1(0) <= \<const0>\;
  tx_cntvalueout_10(8) <= \<const0>\;
  tx_cntvalueout_10(7) <= \<const0>\;
  tx_cntvalueout_10(6) <= \<const0>\;
  tx_cntvalueout_10(5) <= \<const0>\;
  tx_cntvalueout_10(4) <= \<const0>\;
  tx_cntvalueout_10(3) <= \<const0>\;
  tx_cntvalueout_10(2) <= \<const0>\;
  tx_cntvalueout_10(1) <= \<const0>\;
  tx_cntvalueout_10(0) <= \<const0>\;
  tx_cntvalueout_11(8) <= \<const0>\;
  tx_cntvalueout_11(7) <= \<const0>\;
  tx_cntvalueout_11(6) <= \<const0>\;
  tx_cntvalueout_11(5) <= \<const0>\;
  tx_cntvalueout_11(4) <= \<const0>\;
  tx_cntvalueout_11(3) <= \<const0>\;
  tx_cntvalueout_11(2) <= \<const0>\;
  tx_cntvalueout_11(1) <= \<const0>\;
  tx_cntvalueout_11(0) <= \<const0>\;
  tx_cntvalueout_12(8) <= \<const0>\;
  tx_cntvalueout_12(7) <= \<const0>\;
  tx_cntvalueout_12(6) <= \<const0>\;
  tx_cntvalueout_12(5) <= \<const0>\;
  tx_cntvalueout_12(4) <= \<const0>\;
  tx_cntvalueout_12(3) <= \<const0>\;
  tx_cntvalueout_12(2) <= \<const0>\;
  tx_cntvalueout_12(1) <= \<const0>\;
  tx_cntvalueout_12(0) <= \<const0>\;
  tx_cntvalueout_13(8) <= \<const0>\;
  tx_cntvalueout_13(7) <= \<const0>\;
  tx_cntvalueout_13(6) <= \<const0>\;
  tx_cntvalueout_13(5) <= \<const0>\;
  tx_cntvalueout_13(4) <= \<const0>\;
  tx_cntvalueout_13(3) <= \<const0>\;
  tx_cntvalueout_13(2) <= \<const0>\;
  tx_cntvalueout_13(1) <= \<const0>\;
  tx_cntvalueout_13(0) <= \<const0>\;
  tx_cntvalueout_14(8) <= \<const0>\;
  tx_cntvalueout_14(7) <= \<const0>\;
  tx_cntvalueout_14(6) <= \<const0>\;
  tx_cntvalueout_14(5) <= \<const0>\;
  tx_cntvalueout_14(4) <= \<const0>\;
  tx_cntvalueout_14(3) <= \<const0>\;
  tx_cntvalueout_14(2) <= \<const0>\;
  tx_cntvalueout_14(1) <= \<const0>\;
  tx_cntvalueout_14(0) <= \<const0>\;
  tx_cntvalueout_15(8) <= \<const0>\;
  tx_cntvalueout_15(7) <= \<const0>\;
  tx_cntvalueout_15(6) <= \<const0>\;
  tx_cntvalueout_15(5) <= \<const0>\;
  tx_cntvalueout_15(4) <= \<const0>\;
  tx_cntvalueout_15(3) <= \<const0>\;
  tx_cntvalueout_15(2) <= \<const0>\;
  tx_cntvalueout_15(1) <= \<const0>\;
  tx_cntvalueout_15(0) <= \<const0>\;
  tx_cntvalueout_16(8) <= \<const0>\;
  tx_cntvalueout_16(7) <= \<const0>\;
  tx_cntvalueout_16(6) <= \<const0>\;
  tx_cntvalueout_16(5) <= \<const0>\;
  tx_cntvalueout_16(4) <= \<const0>\;
  tx_cntvalueout_16(3) <= \<const0>\;
  tx_cntvalueout_16(2) <= \<const0>\;
  tx_cntvalueout_16(1) <= \<const0>\;
  tx_cntvalueout_16(0) <= \<const0>\;
  tx_cntvalueout_17(8) <= \<const0>\;
  tx_cntvalueout_17(7) <= \<const0>\;
  tx_cntvalueout_17(6) <= \<const0>\;
  tx_cntvalueout_17(5) <= \<const0>\;
  tx_cntvalueout_17(4) <= \<const0>\;
  tx_cntvalueout_17(3) <= \<const0>\;
  tx_cntvalueout_17(2) <= \<const0>\;
  tx_cntvalueout_17(1) <= \<const0>\;
  tx_cntvalueout_17(0) <= \<const0>\;
  tx_cntvalueout_18(8) <= \<const0>\;
  tx_cntvalueout_18(7) <= \<const0>\;
  tx_cntvalueout_18(6) <= \<const0>\;
  tx_cntvalueout_18(5) <= \<const0>\;
  tx_cntvalueout_18(4) <= \<const0>\;
  tx_cntvalueout_18(3) <= \<const0>\;
  tx_cntvalueout_18(2) <= \<const0>\;
  tx_cntvalueout_18(1) <= \<const0>\;
  tx_cntvalueout_18(0) <= \<const0>\;
  tx_cntvalueout_19(8) <= \<const0>\;
  tx_cntvalueout_19(7) <= \<const0>\;
  tx_cntvalueout_19(6) <= \<const0>\;
  tx_cntvalueout_19(5) <= \<const0>\;
  tx_cntvalueout_19(4) <= \<const0>\;
  tx_cntvalueout_19(3) <= \<const0>\;
  tx_cntvalueout_19(2) <= \<const0>\;
  tx_cntvalueout_19(1) <= \<const0>\;
  tx_cntvalueout_19(0) <= \<const0>\;
  tx_cntvalueout_2(8) <= \<const0>\;
  tx_cntvalueout_2(7) <= \<const0>\;
  tx_cntvalueout_2(6) <= \<const0>\;
  tx_cntvalueout_2(5) <= \<const0>\;
  tx_cntvalueout_2(4) <= \<const0>\;
  tx_cntvalueout_2(3) <= \<const0>\;
  tx_cntvalueout_2(2) <= \<const0>\;
  tx_cntvalueout_2(1) <= \<const0>\;
  tx_cntvalueout_2(0) <= \<const0>\;
  tx_cntvalueout_20(8) <= \<const0>\;
  tx_cntvalueout_20(7) <= \<const0>\;
  tx_cntvalueout_20(6) <= \<const0>\;
  tx_cntvalueout_20(5) <= \<const0>\;
  tx_cntvalueout_20(4) <= \<const0>\;
  tx_cntvalueout_20(3) <= \<const0>\;
  tx_cntvalueout_20(2) <= \<const0>\;
  tx_cntvalueout_20(1) <= \<const0>\;
  tx_cntvalueout_20(0) <= \<const0>\;
  tx_cntvalueout_21(8) <= \<const0>\;
  tx_cntvalueout_21(7) <= \<const0>\;
  tx_cntvalueout_21(6) <= \<const0>\;
  tx_cntvalueout_21(5) <= \<const0>\;
  tx_cntvalueout_21(4) <= \<const0>\;
  tx_cntvalueout_21(3) <= \<const0>\;
  tx_cntvalueout_21(2) <= \<const0>\;
  tx_cntvalueout_21(1) <= \<const0>\;
  tx_cntvalueout_21(0) <= \<const0>\;
  tx_cntvalueout_22(8) <= \<const0>\;
  tx_cntvalueout_22(7) <= \<const0>\;
  tx_cntvalueout_22(6) <= \<const0>\;
  tx_cntvalueout_22(5) <= \<const0>\;
  tx_cntvalueout_22(4) <= \<const0>\;
  tx_cntvalueout_22(3) <= \<const0>\;
  tx_cntvalueout_22(2) <= \<const0>\;
  tx_cntvalueout_22(1) <= \<const0>\;
  tx_cntvalueout_22(0) <= \<const0>\;
  tx_cntvalueout_23(8) <= \<const0>\;
  tx_cntvalueout_23(7) <= \<const0>\;
  tx_cntvalueout_23(6) <= \<const0>\;
  tx_cntvalueout_23(5) <= \<const0>\;
  tx_cntvalueout_23(4) <= \<const0>\;
  tx_cntvalueout_23(3) <= \<const0>\;
  tx_cntvalueout_23(2) <= \<const0>\;
  tx_cntvalueout_23(1) <= \<const0>\;
  tx_cntvalueout_23(0) <= \<const0>\;
  tx_cntvalueout_24(8) <= \<const0>\;
  tx_cntvalueout_24(7) <= \<const0>\;
  tx_cntvalueout_24(6) <= \<const0>\;
  tx_cntvalueout_24(5) <= \<const0>\;
  tx_cntvalueout_24(4) <= \<const0>\;
  tx_cntvalueout_24(3) <= \<const0>\;
  tx_cntvalueout_24(2) <= \<const0>\;
  tx_cntvalueout_24(1) <= \<const0>\;
  tx_cntvalueout_24(0) <= \<const0>\;
  tx_cntvalueout_25(8) <= \<const0>\;
  tx_cntvalueout_25(7) <= \<const0>\;
  tx_cntvalueout_25(6) <= \<const0>\;
  tx_cntvalueout_25(5) <= \<const0>\;
  tx_cntvalueout_25(4) <= \<const0>\;
  tx_cntvalueout_25(3) <= \<const0>\;
  tx_cntvalueout_25(2) <= \<const0>\;
  tx_cntvalueout_25(1) <= \<const0>\;
  tx_cntvalueout_25(0) <= \<const0>\;
  tx_cntvalueout_26(8) <= \<const0>\;
  tx_cntvalueout_26(7) <= \<const0>\;
  tx_cntvalueout_26(6) <= \<const0>\;
  tx_cntvalueout_26(5) <= \<const0>\;
  tx_cntvalueout_26(4) <= \<const0>\;
  tx_cntvalueout_26(3) <= \<const0>\;
  tx_cntvalueout_26(2) <= \<const0>\;
  tx_cntvalueout_26(1) <= \<const0>\;
  tx_cntvalueout_26(0) <= \<const0>\;
  tx_cntvalueout_27(8) <= \<const0>\;
  tx_cntvalueout_27(7) <= \<const0>\;
  tx_cntvalueout_27(6) <= \<const0>\;
  tx_cntvalueout_27(5) <= \<const0>\;
  tx_cntvalueout_27(4) <= \<const0>\;
  tx_cntvalueout_27(3) <= \<const0>\;
  tx_cntvalueout_27(2) <= \<const0>\;
  tx_cntvalueout_27(1) <= \<const0>\;
  tx_cntvalueout_27(0) <= \<const0>\;
  tx_cntvalueout_28(8) <= \<const0>\;
  tx_cntvalueout_28(7) <= \<const0>\;
  tx_cntvalueout_28(6) <= \<const0>\;
  tx_cntvalueout_28(5) <= \<const0>\;
  tx_cntvalueout_28(4) <= \<const0>\;
  tx_cntvalueout_28(3) <= \<const0>\;
  tx_cntvalueout_28(2) <= \<const0>\;
  tx_cntvalueout_28(1) <= \<const0>\;
  tx_cntvalueout_28(0) <= \<const0>\;
  tx_cntvalueout_29(8) <= \<const0>\;
  tx_cntvalueout_29(7) <= \<const0>\;
  tx_cntvalueout_29(6) <= \<const0>\;
  tx_cntvalueout_29(5) <= \<const0>\;
  tx_cntvalueout_29(4) <= \<const0>\;
  tx_cntvalueout_29(3) <= \<const0>\;
  tx_cntvalueout_29(2) <= \<const0>\;
  tx_cntvalueout_29(1) <= \<const0>\;
  tx_cntvalueout_29(0) <= \<const0>\;
  tx_cntvalueout_3(8) <= \<const0>\;
  tx_cntvalueout_3(7) <= \<const0>\;
  tx_cntvalueout_3(6) <= \<const0>\;
  tx_cntvalueout_3(5) <= \<const0>\;
  tx_cntvalueout_3(4) <= \<const0>\;
  tx_cntvalueout_3(3) <= \<const0>\;
  tx_cntvalueout_3(2) <= \<const0>\;
  tx_cntvalueout_3(1) <= \<const0>\;
  tx_cntvalueout_3(0) <= \<const0>\;
  tx_cntvalueout_30(8) <= \<const0>\;
  tx_cntvalueout_30(7) <= \<const0>\;
  tx_cntvalueout_30(6) <= \<const0>\;
  tx_cntvalueout_30(5) <= \<const0>\;
  tx_cntvalueout_30(4) <= \<const0>\;
  tx_cntvalueout_30(3) <= \<const0>\;
  tx_cntvalueout_30(2) <= \<const0>\;
  tx_cntvalueout_30(1) <= \<const0>\;
  tx_cntvalueout_30(0) <= \<const0>\;
  tx_cntvalueout_31(8) <= \<const0>\;
  tx_cntvalueout_31(7) <= \<const0>\;
  tx_cntvalueout_31(6) <= \<const0>\;
  tx_cntvalueout_31(5) <= \<const0>\;
  tx_cntvalueout_31(4) <= \<const0>\;
  tx_cntvalueout_31(3) <= \<const0>\;
  tx_cntvalueout_31(2) <= \<const0>\;
  tx_cntvalueout_31(1) <= \<const0>\;
  tx_cntvalueout_31(0) <= \<const0>\;
  tx_cntvalueout_32(8) <= \<const0>\;
  tx_cntvalueout_32(7) <= \<const0>\;
  tx_cntvalueout_32(6) <= \<const0>\;
  tx_cntvalueout_32(5) <= \<const0>\;
  tx_cntvalueout_32(4) <= \<const0>\;
  tx_cntvalueout_32(3) <= \<const0>\;
  tx_cntvalueout_32(2) <= \<const0>\;
  tx_cntvalueout_32(1) <= \<const0>\;
  tx_cntvalueout_32(0) <= \<const0>\;
  tx_cntvalueout_33(8) <= \<const0>\;
  tx_cntvalueout_33(7) <= \<const0>\;
  tx_cntvalueout_33(6) <= \<const0>\;
  tx_cntvalueout_33(5) <= \<const0>\;
  tx_cntvalueout_33(4) <= \<const0>\;
  tx_cntvalueout_33(3) <= \<const0>\;
  tx_cntvalueout_33(2) <= \<const0>\;
  tx_cntvalueout_33(1) <= \<const0>\;
  tx_cntvalueout_33(0) <= \<const0>\;
  tx_cntvalueout_34(8) <= \<const0>\;
  tx_cntvalueout_34(7) <= \<const0>\;
  tx_cntvalueout_34(6) <= \<const0>\;
  tx_cntvalueout_34(5) <= \<const0>\;
  tx_cntvalueout_34(4) <= \<const0>\;
  tx_cntvalueout_34(3) <= \<const0>\;
  tx_cntvalueout_34(2) <= \<const0>\;
  tx_cntvalueout_34(1) <= \<const0>\;
  tx_cntvalueout_34(0) <= \<const0>\;
  tx_cntvalueout_35(8) <= \<const0>\;
  tx_cntvalueout_35(7) <= \<const0>\;
  tx_cntvalueout_35(6) <= \<const0>\;
  tx_cntvalueout_35(5) <= \<const0>\;
  tx_cntvalueout_35(4) <= \<const0>\;
  tx_cntvalueout_35(3) <= \<const0>\;
  tx_cntvalueout_35(2) <= \<const0>\;
  tx_cntvalueout_35(1) <= \<const0>\;
  tx_cntvalueout_35(0) <= \<const0>\;
  tx_cntvalueout_36(8) <= \<const0>\;
  tx_cntvalueout_36(7) <= \<const0>\;
  tx_cntvalueout_36(6) <= \<const0>\;
  tx_cntvalueout_36(5) <= \<const0>\;
  tx_cntvalueout_36(4) <= \<const0>\;
  tx_cntvalueout_36(3) <= \<const0>\;
  tx_cntvalueout_36(2) <= \<const0>\;
  tx_cntvalueout_36(1) <= \<const0>\;
  tx_cntvalueout_36(0) <= \<const0>\;
  tx_cntvalueout_37(8) <= \<const0>\;
  tx_cntvalueout_37(7) <= \<const0>\;
  tx_cntvalueout_37(6) <= \<const0>\;
  tx_cntvalueout_37(5) <= \<const0>\;
  tx_cntvalueout_37(4) <= \<const0>\;
  tx_cntvalueout_37(3) <= \<const0>\;
  tx_cntvalueout_37(2) <= \<const0>\;
  tx_cntvalueout_37(1) <= \<const0>\;
  tx_cntvalueout_37(0) <= \<const0>\;
  tx_cntvalueout_38(8) <= \<const0>\;
  tx_cntvalueout_38(7) <= \<const0>\;
  tx_cntvalueout_38(6) <= \<const0>\;
  tx_cntvalueout_38(5) <= \<const0>\;
  tx_cntvalueout_38(4) <= \<const0>\;
  tx_cntvalueout_38(3) <= \<const0>\;
  tx_cntvalueout_38(2) <= \<const0>\;
  tx_cntvalueout_38(1) <= \<const0>\;
  tx_cntvalueout_38(0) <= \<const0>\;
  tx_cntvalueout_39(8) <= \<const0>\;
  tx_cntvalueout_39(7) <= \<const0>\;
  tx_cntvalueout_39(6) <= \<const0>\;
  tx_cntvalueout_39(5) <= \<const0>\;
  tx_cntvalueout_39(4) <= \<const0>\;
  tx_cntvalueout_39(3) <= \<const0>\;
  tx_cntvalueout_39(2) <= \<const0>\;
  tx_cntvalueout_39(1) <= \<const0>\;
  tx_cntvalueout_39(0) <= \<const0>\;
  tx_cntvalueout_4(8) <= \<const0>\;
  tx_cntvalueout_4(7) <= \<const0>\;
  tx_cntvalueout_4(6) <= \<const0>\;
  tx_cntvalueout_4(5) <= \<const0>\;
  tx_cntvalueout_4(4) <= \<const0>\;
  tx_cntvalueout_4(3) <= \<const0>\;
  tx_cntvalueout_4(2) <= \<const0>\;
  tx_cntvalueout_4(1) <= \<const0>\;
  tx_cntvalueout_4(0) <= \<const0>\;
  tx_cntvalueout_40(8) <= \<const0>\;
  tx_cntvalueout_40(7) <= \<const0>\;
  tx_cntvalueout_40(6) <= \<const0>\;
  tx_cntvalueout_40(5) <= \<const0>\;
  tx_cntvalueout_40(4) <= \<const0>\;
  tx_cntvalueout_40(3) <= \<const0>\;
  tx_cntvalueout_40(2) <= \<const0>\;
  tx_cntvalueout_40(1) <= \<const0>\;
  tx_cntvalueout_40(0) <= \<const0>\;
  tx_cntvalueout_41(8) <= \<const0>\;
  tx_cntvalueout_41(7) <= \<const0>\;
  tx_cntvalueout_41(6) <= \<const0>\;
  tx_cntvalueout_41(5) <= \<const0>\;
  tx_cntvalueout_41(4) <= \<const0>\;
  tx_cntvalueout_41(3) <= \<const0>\;
  tx_cntvalueout_41(2) <= \<const0>\;
  tx_cntvalueout_41(1) <= \<const0>\;
  tx_cntvalueout_41(0) <= \<const0>\;
  tx_cntvalueout_42(8) <= \<const0>\;
  tx_cntvalueout_42(7) <= \<const0>\;
  tx_cntvalueout_42(6) <= \<const0>\;
  tx_cntvalueout_42(5) <= \<const0>\;
  tx_cntvalueout_42(4) <= \<const0>\;
  tx_cntvalueout_42(3) <= \<const0>\;
  tx_cntvalueout_42(2) <= \<const0>\;
  tx_cntvalueout_42(1) <= \<const0>\;
  tx_cntvalueout_42(0) <= \<const0>\;
  tx_cntvalueout_43(8) <= \<const0>\;
  tx_cntvalueout_43(7) <= \<const0>\;
  tx_cntvalueout_43(6) <= \<const0>\;
  tx_cntvalueout_43(5) <= \<const0>\;
  tx_cntvalueout_43(4) <= \<const0>\;
  tx_cntvalueout_43(3) <= \<const0>\;
  tx_cntvalueout_43(2) <= \<const0>\;
  tx_cntvalueout_43(1) <= \<const0>\;
  tx_cntvalueout_43(0) <= \<const0>\;
  tx_cntvalueout_44(8) <= \<const0>\;
  tx_cntvalueout_44(7) <= \<const0>\;
  tx_cntvalueout_44(6) <= \<const0>\;
  tx_cntvalueout_44(5) <= \<const0>\;
  tx_cntvalueout_44(4) <= \<const0>\;
  tx_cntvalueout_44(3) <= \<const0>\;
  tx_cntvalueout_44(2) <= \<const0>\;
  tx_cntvalueout_44(1) <= \<const0>\;
  tx_cntvalueout_44(0) <= \<const0>\;
  tx_cntvalueout_45(8) <= \<const0>\;
  tx_cntvalueout_45(7) <= \<const0>\;
  tx_cntvalueout_45(6) <= \<const0>\;
  tx_cntvalueout_45(5) <= \<const0>\;
  tx_cntvalueout_45(4) <= \<const0>\;
  tx_cntvalueout_45(3) <= \<const0>\;
  tx_cntvalueout_45(2) <= \<const0>\;
  tx_cntvalueout_45(1) <= \<const0>\;
  tx_cntvalueout_45(0) <= \<const0>\;
  tx_cntvalueout_46(8) <= \<const0>\;
  tx_cntvalueout_46(7) <= \<const0>\;
  tx_cntvalueout_46(6) <= \<const0>\;
  tx_cntvalueout_46(5) <= \<const0>\;
  tx_cntvalueout_46(4) <= \<const0>\;
  tx_cntvalueout_46(3) <= \<const0>\;
  tx_cntvalueout_46(2) <= \<const0>\;
  tx_cntvalueout_46(1) <= \<const0>\;
  tx_cntvalueout_46(0) <= \<const0>\;
  tx_cntvalueout_47(8) <= \<const0>\;
  tx_cntvalueout_47(7) <= \<const0>\;
  tx_cntvalueout_47(6) <= \<const0>\;
  tx_cntvalueout_47(5) <= \<const0>\;
  tx_cntvalueout_47(4) <= \<const0>\;
  tx_cntvalueout_47(3) <= \<const0>\;
  tx_cntvalueout_47(2) <= \<const0>\;
  tx_cntvalueout_47(1) <= \<const0>\;
  tx_cntvalueout_47(0) <= \<const0>\;
  tx_cntvalueout_48(8) <= \<const0>\;
  tx_cntvalueout_48(7) <= \<const0>\;
  tx_cntvalueout_48(6) <= \<const0>\;
  tx_cntvalueout_48(5) <= \<const0>\;
  tx_cntvalueout_48(4) <= \<const0>\;
  tx_cntvalueout_48(3) <= \<const0>\;
  tx_cntvalueout_48(2) <= \<const0>\;
  tx_cntvalueout_48(1) <= \<const0>\;
  tx_cntvalueout_48(0) <= \<const0>\;
  tx_cntvalueout_49(8) <= \<const0>\;
  tx_cntvalueout_49(7) <= \<const0>\;
  tx_cntvalueout_49(6) <= \<const0>\;
  tx_cntvalueout_49(5) <= \<const0>\;
  tx_cntvalueout_49(4) <= \<const0>\;
  tx_cntvalueout_49(3) <= \<const0>\;
  tx_cntvalueout_49(2) <= \<const0>\;
  tx_cntvalueout_49(1) <= \<const0>\;
  tx_cntvalueout_49(0) <= \<const0>\;
  tx_cntvalueout_5(8) <= \<const0>\;
  tx_cntvalueout_5(7) <= \<const0>\;
  tx_cntvalueout_5(6) <= \<const0>\;
  tx_cntvalueout_5(5) <= \<const0>\;
  tx_cntvalueout_5(4) <= \<const0>\;
  tx_cntvalueout_5(3) <= \<const0>\;
  tx_cntvalueout_5(2) <= \<const0>\;
  tx_cntvalueout_5(1) <= \<const0>\;
  tx_cntvalueout_5(0) <= \<const0>\;
  tx_cntvalueout_50(8) <= \<const0>\;
  tx_cntvalueout_50(7) <= \<const0>\;
  tx_cntvalueout_50(6) <= \<const0>\;
  tx_cntvalueout_50(5) <= \<const0>\;
  tx_cntvalueout_50(4) <= \<const0>\;
  tx_cntvalueout_50(3) <= \<const0>\;
  tx_cntvalueout_50(2) <= \<const0>\;
  tx_cntvalueout_50(1) <= \<const0>\;
  tx_cntvalueout_50(0) <= \<const0>\;
  tx_cntvalueout_51(8) <= \<const0>\;
  tx_cntvalueout_51(7) <= \<const0>\;
  tx_cntvalueout_51(6) <= \<const0>\;
  tx_cntvalueout_51(5) <= \<const0>\;
  tx_cntvalueout_51(4) <= \<const0>\;
  tx_cntvalueout_51(3) <= \<const0>\;
  tx_cntvalueout_51(2) <= \<const0>\;
  tx_cntvalueout_51(1) <= \<const0>\;
  tx_cntvalueout_51(0) <= \<const0>\;
  tx_cntvalueout_6(8) <= \<const0>\;
  tx_cntvalueout_6(7) <= \<const0>\;
  tx_cntvalueout_6(6) <= \<const0>\;
  tx_cntvalueout_6(5) <= \<const0>\;
  tx_cntvalueout_6(4) <= \<const0>\;
  tx_cntvalueout_6(3) <= \<const0>\;
  tx_cntvalueout_6(2) <= \<const0>\;
  tx_cntvalueout_6(1) <= \<const0>\;
  tx_cntvalueout_6(0) <= \<const0>\;
  tx_cntvalueout_7(8) <= \<const0>\;
  tx_cntvalueout_7(7) <= \<const0>\;
  tx_cntvalueout_7(6) <= \<const0>\;
  tx_cntvalueout_7(5) <= \<const0>\;
  tx_cntvalueout_7(4) <= \<const0>\;
  tx_cntvalueout_7(3) <= \<const0>\;
  tx_cntvalueout_7(2) <= \<const0>\;
  tx_cntvalueout_7(1) <= \<const0>\;
  tx_cntvalueout_7(0) <= \<const0>\;
  tx_cntvalueout_8(8) <= \<const0>\;
  tx_cntvalueout_8(7) <= \<const0>\;
  tx_cntvalueout_8(6) <= \<const0>\;
  tx_cntvalueout_8(5) <= \<const0>\;
  tx_cntvalueout_8(4) <= \<const0>\;
  tx_cntvalueout_8(3) <= \<const0>\;
  tx_cntvalueout_8(2) <= \<const0>\;
  tx_cntvalueout_8(1) <= \<const0>\;
  tx_cntvalueout_8(0) <= \<const0>\;
  tx_cntvalueout_9(8) <= \<const0>\;
  tx_cntvalueout_9(7) <= \<const0>\;
  tx_cntvalueout_9(6) <= \<const0>\;
  tx_cntvalueout_9(5) <= \<const0>\;
  tx_cntvalueout_9(4) <= \<const0>\;
  tx_cntvalueout_9(3) <= \<const0>\;
  tx_cntvalueout_9(2) <= \<const0>\;
  tx_cntvalueout_9(1) <= \<const0>\;
  tx_cntvalueout_9(0) <= \<const0>\;
  vtc_rdy_bsc0 <= \<const0>\;
  vtc_rdy_bsc1 <= \<const0>\;
  vtc_rdy_bsc2 <= \<const0>\;
  vtc_rdy_bsc3 <= \<const0>\;
  vtc_rdy_bsc4 <= \<const0>\;
  vtc_rdy_bsc5 <= \<const0>\;
  vtc_rdy_bsc6 <= \<const0>\;
  vtc_rdy_bsc7 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
top_inst: entity work.design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_hssio_wiz_top
     port map (
      bs_rst_dphy_in => bs_rst_dphy_in,
      clk_rxn => clk_rxn,
      clk_rxp => clk_rxp,
      data_rxn0 => data_rxn0,
      data_rxn1 => data_rxn1,
      data_rxn2 => data_rxn2,
      data_rxn3 => data_rxn3,
      data_rxp0 => data_rxp0,
      data_rxp1 => data_rxp1,
      data_rxp2 => data_rxp2,
      data_rxp3 => data_rxp3,
      data_to_fabric_data_rxp0(7 downto 0) => data_to_fabric_data_rxp0(7 downto 0),
      data_to_fabric_data_rxp1(7 downto 0) => data_to_fabric_data_rxp1(7 downto 0),
      data_to_fabric_data_rxp2(7 downto 0) => data_to_fabric_data_rxp2(7 downto 0),
      data_to_fabric_data_rxp3(7 downto 0) => data_to_fabric_data_rxp3(7 downto 0),
      fifo_empty_2 => fifo_empty_2,
      fifo_empty_4 => fifo_empty_4,
      fifo_empty_6 => fifo_empty_6,
      fifo_empty_8 => fifo_empty_8,
      fifo_rd_clk_0 => fifo_rd_clk_0,
      fifo_rd_en_2 => fifo_rd_en_2,
      fifo_rd_en_4 => fifo_rd_en_4,
      fifo_rd_en_6 => fifo_rd_en_6,
      fifo_rd_en_8 => fifo_rd_en_8,
      fifo_wr_clk_0 => fifo_wr_clk_0,
      hs_rx_disable(4 downto 0) => hs_rx_disable(4 downto 0),
      lp_rx_o_n(4 downto 0) => lp_rx_o_n(4 downto 0),
      lp_rx_o_p(4 downto 0) => lp_rx_o_p(4 downto 0),
      riu_clk => riu_clk,
      rst => rst,
      rst_seq_done => rst_seq_done
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_vfb_0_0_core is
  port (
    vfb_valid_reg : out STD_LOGIC;
    vfb_eol_reg : out STD_LOGIC;
    vfb_sof : out STD_LOGIC_VECTOR ( 6 downto 0 );
    vfb_data : out STD_LOGIC_VECTOR ( 23 downto 0 );
    s_axis_tready : out STD_LOGIC;
    vfb_arstn : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 80 downto 0 );
    s_axis_tvalid : in STD_LOGIC;
    vfb_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_vfb_0_0_core : entity is "bd_7289_vfb_0_0_core";
end design_1_Vsp_core_0_0_bd_7289_vfb_0_0_core;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_vfb_0_0_core is
  signal \VFB_MIN.reorder_n_2\ : STD_LOGIC;
  signal \VFB_MIN.reorder_n_31\ : STD_LOGIC;
  signal \VFB_MIN.reorder_n_34\ : STD_LOGIC;
  signal \VFB_MIN.reorder_n_35\ : STD_LOGIC;
  signal \VFB_MIN.reorder_n_84\ : STD_LOGIC;
  signal axis_dconverter_n_1 : STD_LOGIC;
  signal axis_dconverter_n_17 : STD_LOGIC;
  signal axis_dconverter_n_18 : STD_LOGIC;
  signal axis_dconverter_n_19 : STD_LOGIC;
  signal axis_dconverter_n_20 : STD_LOGIC;
  signal axis_dconverter_n_21 : STD_LOGIC;
  signal axis_dconverter_n_22 : STD_LOGIC;
  signal axis_dconverter_n_23 : STD_LOGIC;
  signal axis_dconverter_n_24 : STD_LOGIC;
  signal axis_dconverter_n_25 : STD_LOGIC;
  signal axis_dconverter_n_26 : STD_LOGIC;
  signal axis_dconverter_n_27 : STD_LOGIC;
  signal axis_dconverter_n_28 : STD_LOGIC;
  signal axis_dconverter_n_29 : STD_LOGIC;
  signal axis_dconverter_n_30 : STD_LOGIC;
  signal axis_dconverter_n_31 : STD_LOGIC;
  signal axis_dconverter_n_32 : STD_LOGIC;
  signal axis_dconverter_n_33 : STD_LOGIC;
  signal axis_dconverter_n_34 : STD_LOGIC;
  signal axis_dconverter_n_35 : STD_LOGIC;
  signal axis_dconverter_n_36 : STD_LOGIC;
  signal cur_dtype_udef : STD_LOGIC;
  signal m_axis_tdata : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal m_axis_tid : STD_LOGIC_VECTOR ( 9 downto 4 );
  signal m_axis_tlast : STD_LOGIC;
  signal op_inf_n_14 : STD_LOGIC;
  signal op_inf_n_15 : STD_LOGIC;
  signal op_inf_n_16 : STD_LOGIC;
  signal op_inf_n_17 : STD_LOGIC;
  signal op_inf_n_18 : STD_LOGIC;
  signal op_inf_n_19 : STD_LOGIC;
  signal op_inf_n_20 : STD_LOGIC;
  signal op_inf_n_21 : STD_LOGIC;
  signal op_inf_n_22 : STD_LOGIC;
  signal op_inf_n_23 : STD_LOGIC;
  signal op_inf_n_24 : STD_LOGIC;
  signal op_inf_n_25 : STD_LOGIC;
  signal op_inf_n_26 : STD_LOGIC;
  signal op_inf_n_27 : STD_LOGIC;
  signal op_inf_n_28 : STD_LOGIC;
  signal op_inf_n_29 : STD_LOGIC;
  signal op_inf_n_30 : STD_LOGIC;
  signal op_inf_n_31 : STD_LOGIC;
  signal op_inf_n_32 : STD_LOGIC;
  signal op_inf_n_33 : STD_LOGIC;
  signal op_inf_n_34 : STD_LOGIC;
  signal op_inf_n_35 : STD_LOGIC;
  signal op_inf_n_36 : STD_LOGIC;
  signal op_inf_n_37 : STD_LOGIC;
  signal op_inf_n_38 : STD_LOGIC;
  signal op_inf_n_39 : STD_LOGIC;
  signal op_inf_n_4 : STD_LOGIC;
  signal op_inf_n_40 : STD_LOGIC;
  signal op_inf_n_41 : STD_LOGIC;
  signal op_inf_n_42 : STD_LOGIC;
  signal op_inf_n_43 : STD_LOGIC;
  signal op_inf_n_44 : STD_LOGIC;
  signal op_inf_n_45 : STD_LOGIC;
  signal op_inf_n_46 : STD_LOGIC;
  signal op_inf_n_47 : STD_LOGIC;
  signal op_inf_n_48 : STD_LOGIC;
  signal op_inf_n_49 : STD_LOGIC;
  signal op_inf_n_50 : STD_LOGIC;
  signal op_inf_n_51 : STD_LOGIC;
  signal op_inf_n_52 : STD_LOGIC;
  signal op_inf_n_53 : STD_LOGIC;
  signal op_inf_n_54 : STD_LOGIC;
  signal op_inf_n_55 : STD_LOGIC;
  signal op_inf_n_56 : STD_LOGIC;
  signal op_inf_n_57 : STD_LOGIC;
  signal op_inf_n_58 : STD_LOGIC;
  signal op_inf_n_59 : STD_LOGIC;
  signal op_inf_n_6 : STD_LOGIC;
  signal op_inf_n_60 : STD_LOGIC;
  signal op_inf_n_61 : STD_LOGIC;
  signal op_inf_n_7 : STD_LOGIC;
  signal s_fifo_td : STD_LOGIC_VECTOR ( 59 downto 0 );
  signal s_fifo_tid : STD_LOGIC_VECTOR ( 9 downto 4 );
  signal s_fifo_tk : STD_LOGIC_VECTOR ( 7 to 7 );
  signal s_fifo_tl : STD_LOGIC;
  signal s_fifo_tr : STD_LOGIC;
  signal s_fifo_tu : STD_LOGIC_VECTOR ( 76 to 76 );
  signal s_fifo_tv : STD_LOGIC;
  signal sband_td : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal sband_td_r : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal sband_tk : STD_LOGIC_VECTOR ( 2 to 2 );
  signal sband_tl : STD_LOGIC;
  signal sband_ts : STD_LOGIC_VECTOR ( 9 downto 4 );
  signal sband_tu : STD_LOGIC_VECTOR ( 0 to 0 );
  signal sband_tu_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^vfb_eol_reg\ : STD_LOGIC;
  signal vfb_sof015_out : STD_LOGIC;
  signal vfb_sof119_out : STD_LOGIC;
  signal \^vfb_valid_reg\ : STD_LOGIC;
begin
  vfb_eol_reg <= \^vfb_eol_reg\;
  vfb_valid_reg <= \^vfb_valid_reg\;
\VFB_MIN.reorder\: entity work.design_1_Vsp_core_0_0_vfb_v1_0_27_reorder
     port map (
      D(80 downto 0) => D(80 downto 0),
      E(0) => \^vfb_valid_reg\,
      Q(22 downto 7) => sband_td(15 downto 0),
      Q(6) => sband_tk(2),
      Q(5 downto 0) => sband_ts(9 downto 4),
      \REQ_BUFFER_RAW12.buff_tv_i_reg_0\ => axis_dconverter_n_34,
      SR(0) => \VFB_MIN.reorder_n_2\,
      \buf_data_reg[0][106]_0\(1) => \VFB_MIN.reorder_n_34\,
      \buf_data_reg[0][106]_0\(0) => \VFB_MIN.reorder_n_35\,
      \buf_data_reg[0][171]_0\(47 downto 0) => sband_td_r(47 downto 0),
      \buf_valid_reg[1]_0\ => s_axis_tready,
      \buf_valid_reg[1]_1\ => axis_dconverter_n_35,
      cur_dtype_udef => cur_dtype_udef,
      m_axis_tvalid => axis_dconverter_n_1,
      s_axis_tkeep(0) => s_fifo_tk(7),
      s_axis_tlast => s_fifo_tl,
      s_axis_tready => s_fifo_tr,
      s_axis_tuser(0) => s_fifo_tu(76),
      s_axis_tvalid => s_axis_tvalid,
      \s_fifo_td_reg[59]_0\(47 downto 36) => s_fifo_td(59 downto 48),
      \s_fifo_td_reg[59]_0\(35 downto 24) => s_fifo_td(43 downto 32),
      \s_fifo_td_reg[59]_0\(23 downto 12) => s_fifo_td(27 downto 16),
      \s_fifo_td_reg[59]_0\(11 downto 0) => s_fifo_td(11 downto 0),
      \s_fifo_tid_reg[9]_0\(5 downto 0) => s_fifo_tid(9 downto 4),
      s_fifo_tv => s_fifo_tv,
      \sband_td_r_reg[31]\(31) => op_inf_n_14,
      \sband_td_r_reg[31]\(30) => op_inf_n_15,
      \sband_td_r_reg[31]\(29) => op_inf_n_16,
      \sband_td_r_reg[31]\(28) => op_inf_n_17,
      \sband_td_r_reg[31]\(27) => op_inf_n_18,
      \sband_td_r_reg[31]\(26) => op_inf_n_19,
      \sband_td_r_reg[31]\(25) => op_inf_n_20,
      \sband_td_r_reg[31]\(24) => op_inf_n_21,
      \sband_td_r_reg[31]\(23) => op_inf_n_22,
      \sband_td_r_reg[31]\(22) => op_inf_n_23,
      \sband_td_r_reg[31]\(21) => op_inf_n_24,
      \sband_td_r_reg[31]\(20) => op_inf_n_25,
      \sband_td_r_reg[31]\(19) => op_inf_n_26,
      \sband_td_r_reg[31]\(18) => op_inf_n_27,
      \sband_td_r_reg[31]\(17) => op_inf_n_28,
      \sband_td_r_reg[31]\(16) => op_inf_n_29,
      \sband_td_r_reg[31]\(15) => op_inf_n_30,
      \sband_td_r_reg[31]\(14) => op_inf_n_31,
      \sband_td_r_reg[31]\(13) => op_inf_n_32,
      \sband_td_r_reg[31]\(12) => op_inf_n_33,
      \sband_td_r_reg[31]\(11) => op_inf_n_34,
      \sband_td_r_reg[31]\(10) => op_inf_n_35,
      \sband_td_r_reg[31]\(9) => op_inf_n_36,
      \sband_td_r_reg[31]\(8) => op_inf_n_37,
      \sband_td_r_reg[31]\(7) => op_inf_n_38,
      \sband_td_r_reg[31]\(6) => op_inf_n_39,
      \sband_td_r_reg[31]\(5) => op_inf_n_40,
      \sband_td_r_reg[31]\(4) => op_inf_n_41,
      \sband_td_r_reg[31]\(3) => op_inf_n_42,
      \sband_td_r_reg[31]\(2) => op_inf_n_43,
      \sband_td_r_reg[31]\(1) => op_inf_n_44,
      \sband_td_r_reg[31]\(0) => op_inf_n_45,
      \sband_tk_r_reg[2]\(0) => op_inf_n_7,
      sband_tl => sband_tl,
      sband_tl_r_reg => op_inf_n_6,
      sband_tl_r_reg_0 => \^vfb_eol_reg\,
      sband_tu(0) => sband_tu(0),
      sband_tu_r(0) => sband_tu_r(0),
      \state_reg[1]\ => \VFB_MIN.reorder_n_31\,
      \state_reg[1]_0\ => \VFB_MIN.reorder_n_84\,
      vfb_arstn => vfb_arstn,
      vfb_clk => vfb_clk,
      vfb_sof015_out => vfb_sof015_out,
      vfb_sof119_out => vfb_sof119_out,
      \vfb_sof_reg[0]\ => op_inf_n_4
    );
axis_dconverter: entity work.design_1_Vsp_core_0_0_bd_7289_vfb_0_0_axis_dconverter
     port map (
      D(15) => axis_dconverter_n_17,
      D(14) => axis_dconverter_n_18,
      D(13) => axis_dconverter_n_19,
      D(12) => axis_dconverter_n_20,
      D(11) => axis_dconverter_n_21,
      D(10) => axis_dconverter_n_22,
      D(9) => axis_dconverter_n_23,
      D(8) => axis_dconverter_n_24,
      D(7) => axis_dconverter_n_25,
      D(6) => axis_dconverter_n_26,
      D(5) => axis_dconverter_n_27,
      D(4) => axis_dconverter_n_28,
      D(3) => axis_dconverter_n_29,
      D(2) => axis_dconverter_n_30,
      D(1) => axis_dconverter_n_31,
      D(0) => axis_dconverter_n_32,
      Q(15) => op_inf_n_46,
      Q(14) => op_inf_n_47,
      Q(13) => op_inf_n_48,
      Q(12) => op_inf_n_49,
      Q(11) => op_inf_n_50,
      Q(10) => op_inf_n_51,
      Q(9) => op_inf_n_52,
      Q(8) => op_inf_n_53,
      Q(7) => op_inf_n_54,
      Q(6) => op_inf_n_55,
      Q(5) => op_inf_n_56,
      Q(4) => op_inf_n_57,
      Q(3) => op_inf_n_58,
      Q(2) => op_inf_n_59,
      Q(1) => op_inf_n_60,
      Q(0) => op_inf_n_61,
      cur_dtype_udef => cur_dtype_udef,
      m_axis_tid(5 downto 0) => m_axis_tid(9 downto 4),
      m_axis_tlast => m_axis_tlast,
      m_axis_tvalid => axis_dconverter_n_1,
      \r0_data_reg[59]\(47 downto 36) => s_fifo_td(59 downto 48),
      \r0_data_reg[59]\(35 downto 24) => s_fifo_td(43 downto 32),
      \r0_data_reg[59]\(23 downto 12) => s_fifo_td(27 downto 16),
      \r0_data_reg[59]\(11 downto 0) => s_fifo_td(11 downto 0),
      \r0_id_reg[9]\(5 downto 0) => s_fifo_tid(9 downto 4),
      \r1_data_reg[19]\(7 downto 4) => m_axis_tdata(19 downto 16),
      \r1_data_reg[19]\(3 downto 0) => m_axis_tdata(3 downto 0),
      s_axis_tkeep(0) => s_fifo_tk(7),
      s_axis_tlast => s_fifo_tl,
      s_axis_tready => s_fifo_tr,
      s_axis_tuser(0) => s_fifo_tu(76),
      s_fifo_tv => s_fifo_tv,
      \sband_tu_r[0]_i_2\ => \^vfb_eol_reg\,
      \state_reg[0]\ => axis_dconverter_n_34,
      \state_reg[1]\ => axis_dconverter_n_33,
      \state_reg[1]_0\ => axis_dconverter_n_35,
      \state_reg[1]_1\ => axis_dconverter_n_36,
      vfb_arstn => vfb_arstn,
      vfb_clk => vfb_clk,
      \vfb_data_reg[23]\(15 downto 0) => sband_td(15 downto 0),
      \vfb_data_reg[4]\ => \VFB_MIN.reorder_n_84\,
      vfb_sof119_out => vfb_sof119_out
    );
op_inf: entity work.design_1_Vsp_core_0_0_vfb_v1_0_27_op_inf
     port map (
      D(1) => \VFB_MIN.reorder_n_34\,
      D(0) => \VFB_MIN.reorder_n_35\,
      E(0) => \^vfb_valid_reg\,
      Q(6) => sband_tk(2),
      Q(5 downto 0) => sband_ts(9 downto 4),
      SR(0) => \VFB_MIN.reorder_n_2\,
      \TUSR0.vfb_sof_reg[64]_0\ => axis_dconverter_n_33,
      m_axis_tid(5 downto 0) => m_axis_tid(9 downto 4),
      m_axis_tlast => m_axis_tlast,
      m_axis_tvalid => axis_dconverter_n_1,
      \sband_td_r_reg[47]_0\(47) => op_inf_n_14,
      \sband_td_r_reg[47]_0\(46) => op_inf_n_15,
      \sband_td_r_reg[47]_0\(45) => op_inf_n_16,
      \sband_td_r_reg[47]_0\(44) => op_inf_n_17,
      \sband_td_r_reg[47]_0\(43) => op_inf_n_18,
      \sband_td_r_reg[47]_0\(42) => op_inf_n_19,
      \sband_td_r_reg[47]_0\(41) => op_inf_n_20,
      \sband_td_r_reg[47]_0\(40) => op_inf_n_21,
      \sband_td_r_reg[47]_0\(39) => op_inf_n_22,
      \sband_td_r_reg[47]_0\(38) => op_inf_n_23,
      \sband_td_r_reg[47]_0\(37) => op_inf_n_24,
      \sband_td_r_reg[47]_0\(36) => op_inf_n_25,
      \sband_td_r_reg[47]_0\(35) => op_inf_n_26,
      \sband_td_r_reg[47]_0\(34) => op_inf_n_27,
      \sband_td_r_reg[47]_0\(33) => op_inf_n_28,
      \sband_td_r_reg[47]_0\(32) => op_inf_n_29,
      \sband_td_r_reg[47]_0\(31) => op_inf_n_30,
      \sband_td_r_reg[47]_0\(30) => op_inf_n_31,
      \sband_td_r_reg[47]_0\(29) => op_inf_n_32,
      \sband_td_r_reg[47]_0\(28) => op_inf_n_33,
      \sband_td_r_reg[47]_0\(27) => op_inf_n_34,
      \sband_td_r_reg[47]_0\(26) => op_inf_n_35,
      \sband_td_r_reg[47]_0\(25) => op_inf_n_36,
      \sband_td_r_reg[47]_0\(24) => op_inf_n_37,
      \sband_td_r_reg[47]_0\(23) => op_inf_n_38,
      \sband_td_r_reg[47]_0\(22) => op_inf_n_39,
      \sband_td_r_reg[47]_0\(21) => op_inf_n_40,
      \sband_td_r_reg[47]_0\(20) => op_inf_n_41,
      \sband_td_r_reg[47]_0\(19) => op_inf_n_42,
      \sband_td_r_reg[47]_0\(18) => op_inf_n_43,
      \sband_td_r_reg[47]_0\(17) => op_inf_n_44,
      \sband_td_r_reg[47]_0\(16) => op_inf_n_45,
      \sband_td_r_reg[47]_0\(15) => op_inf_n_46,
      \sband_td_r_reg[47]_0\(14) => op_inf_n_47,
      \sband_td_r_reg[47]_0\(13) => op_inf_n_48,
      \sband_td_r_reg[47]_0\(12) => op_inf_n_49,
      \sband_td_r_reg[47]_0\(11) => op_inf_n_50,
      \sband_td_r_reg[47]_0\(10) => op_inf_n_51,
      \sband_td_r_reg[47]_0\(9) => op_inf_n_52,
      \sband_td_r_reg[47]_0\(8) => op_inf_n_53,
      \sband_td_r_reg[47]_0\(7) => op_inf_n_54,
      \sband_td_r_reg[47]_0\(6) => op_inf_n_55,
      \sband_td_r_reg[47]_0\(5) => op_inf_n_56,
      \sband_td_r_reg[47]_0\(4) => op_inf_n_57,
      \sband_td_r_reg[47]_0\(3) => op_inf_n_58,
      \sband_td_r_reg[47]_0\(2) => op_inf_n_59,
      \sband_td_r_reg[47]_0\(1) => op_inf_n_60,
      \sband_td_r_reg[47]_0\(0) => op_inf_n_61,
      \sband_td_r_reg[47]_1\(47 downto 0) => sband_td_r(47 downto 0),
      \sband_tk_r_reg[4]_0\(0) => op_inf_n_7,
      sband_tl => sband_tl,
      sband_tu(0) => sband_tu(0),
      sband_tu_r(0) => sband_tu_r(0),
      vfb_arstn => vfb_arstn,
      vfb_clk => vfb_clk,
      \vfb_cnt_reg[3]_0\ => op_inf_n_6,
      vfb_data(23 downto 0) => vfb_data(23 downto 0),
      \vfb_data_reg[15]_0\(7 downto 4) => m_axis_tdata(19 downto 16),
      \vfb_data_reg[15]_0\(3 downto 0) => m_axis_tdata(3 downto 0),
      \vfb_data_reg[23]_0\(15) => axis_dconverter_n_17,
      \vfb_data_reg[23]_0\(14) => axis_dconverter_n_18,
      \vfb_data_reg[23]_0\(13) => axis_dconverter_n_19,
      \vfb_data_reg[23]_0\(12) => axis_dconverter_n_20,
      \vfb_data_reg[23]_0\(11) => axis_dconverter_n_21,
      \vfb_data_reg[23]_0\(10) => axis_dconverter_n_22,
      \vfb_data_reg[23]_0\(9) => axis_dconverter_n_23,
      \vfb_data_reg[23]_0\(8) => axis_dconverter_n_24,
      \vfb_data_reg[23]_0\(7) => axis_dconverter_n_25,
      \vfb_data_reg[23]_0\(6) => axis_dconverter_n_26,
      \vfb_data_reg[23]_0\(5) => axis_dconverter_n_27,
      \vfb_data_reg[23]_0\(4) => axis_dconverter_n_28,
      \vfb_data_reg[23]_0\(3) => axis_dconverter_n_29,
      \vfb_data_reg[23]_0\(2) => axis_dconverter_n_30,
      \vfb_data_reg[23]_0\(1) => axis_dconverter_n_31,
      \vfb_data_reg[23]_0\(0) => axis_dconverter_n_32,
      vfb_eol_reg_0 => \^vfb_eol_reg\,
      vfb_sof(5 downto 0) => vfb_sof(6 downto 1),
      vfb_sof015_out => vfb_sof015_out,
      vfb_sof119_out => vfb_sof119_out,
      \vfb_sof_reg[0]_0\ => vfb_sof(0),
      \vfb_sof_reg[0]_1\ => \VFB_MIN.reorder_n_31\,
      \vfb_sof_reg[0]_2\ => axis_dconverter_n_36,
      vfb_valid_reg_0 => op_inf_n_4
    );
end STRUCTURE;
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`protect key_block
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`protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 62928)
`protect data_block
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`protect begin_protected
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`protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx is
  port (
    hs_rx_disable : in STD_LOGIC_VECTOR ( 4 downto 0 );
    lp_rx_disable : in STD_LOGIC_VECTOR ( 4 downto 0 );
    lp_rx_o_p : out STD_LOGIC_VECTOR ( 4 downto 0 );
    lp_rx_o_n : out STD_LOGIC_VECTOR ( 4 downto 0 );
    fifo_rd_clk_0 : in STD_LOGIC;
    fifo_rd_clk_1 : in STD_LOGIC;
    fifo_rd_clk_2 : in STD_LOGIC;
    fifo_rd_clk_3 : in STD_LOGIC;
    fifo_rd_clk_4 : in STD_LOGIC;
    fifo_rd_clk_5 : in STD_LOGIC;
    fifo_rd_clk_6 : in STD_LOGIC;
    fifo_rd_clk_7 : in STD_LOGIC;
    fifo_rd_clk_8 : in STD_LOGIC;
    fifo_rd_clk_9 : in STD_LOGIC;
    fifo_rd_en_0 : in STD_LOGIC;
    fifo_rd_en_1 : in STD_LOGIC;
    fifo_rd_en_2 : in STD_LOGIC;
    fifo_rd_en_3 : in STD_LOGIC;
    fifo_rd_en_4 : in STD_LOGIC;
    fifo_rd_en_5 : in STD_LOGIC;
    fifo_rd_en_6 : in STD_LOGIC;
    fifo_rd_en_7 : in STD_LOGIC;
    fifo_rd_en_8 : in STD_LOGIC;
    fifo_rd_en_9 : in STD_LOGIC;
    fifo_empty_0 : out STD_LOGIC;
    fifo_empty_1 : out STD_LOGIC;
    fifo_empty_2 : out STD_LOGIC;
    fifo_empty_3 : out STD_LOGIC;
    fifo_empty_4 : out STD_LOGIC;
    fifo_empty_5 : out STD_LOGIC;
    fifo_empty_6 : out STD_LOGIC;
    fifo_empty_7 : out STD_LOGIC;
    fifo_empty_8 : out STD_LOGIC;
    fifo_empty_9 : out STD_LOGIC;
    fifo_wr_clk_0 : out STD_LOGIC;
    vtc_rdy_bsc0 : out STD_LOGIC;
    en_vtc_bsc0 : in STD_LOGIC;
    vtc_rdy_bsc1 : out STD_LOGIC;
    en_vtc_bsc1 : in STD_LOGIC;
    dly_rdy_bsc0 : out STD_LOGIC;
    dly_rdy_bsc1 : out STD_LOGIC;
    rst_seq_done : out STD_LOGIC;
    shared_pll0_clkoutphy_out : out STD_LOGIC;
    pll0_clkout0 : out STD_LOGIC;
    rst : in STD_LOGIC;
    bs_rst_dphy_in : in STD_LOGIC;
    clk : in STD_LOGIC;
    riu_clk : in STD_LOGIC;
    pll0_locked : out STD_LOGIC;
    clk_rxp : in STD_LOGIC;
    data_to_fabric_clk_rxp : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clk_rxn : in STD_LOGIC;
    data_to_fabric_clk_rxn : out STD_LOGIC_VECTOR ( 7 downto 0 );
    data_rxp0 : in STD_LOGIC;
    data_to_fabric_data_rxp0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    data_rxn0 : in STD_LOGIC;
    data_to_fabric_data_rxn0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    data_rxp1 : in STD_LOGIC;
    data_to_fabric_data_rxp1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    data_rxn1 : in STD_LOGIC;
    data_to_fabric_data_rxn1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    data_rxp2 : in STD_LOGIC;
    data_to_fabric_data_rxp2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    data_rxn2 : in STD_LOGIC;
    data_to_fabric_data_rxn2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    data_rxp3 : in STD_LOGIC;
    data_to_fabric_data_rxp3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    data_rxn3 : in STD_LOGIC;
    data_to_fabric_data_rxn3 : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx : entity is "bd_7289_phy_0_hssio_rx,bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx : entity is "bd_7289_phy_0_hssio_rx";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx : entity is "bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10,Vivado 2024.2";
end design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_inst_bitslip_error_0_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_1_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_10_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_11_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_12_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_13_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_14_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_15_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_16_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_17_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_18_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_19_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_2_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_20_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_21_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_22_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_23_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_24_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_25_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_26_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_27_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_28_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_29_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_3_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_30_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_31_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_32_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_33_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_34_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_35_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_36_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_37_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_38_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_39_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_4_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_40_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_41_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_42_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_43_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_44_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_45_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_46_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_47_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_48_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_49_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_5_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_50_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_51_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_6_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_7_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_8_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bitslip_error_9_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_clk_from_ibuf_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dly_rdy_bsc0_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dly_rdy_bsc1_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dly_rdy_bsc2_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dly_rdy_bsc3_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dly_rdy_bsc4_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dly_rdy_bsc5_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dly_rdy_bsc6_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dly_rdy_bsc7_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_drdy_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_0_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_1_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_10_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_11_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_12_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_13_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_14_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_15_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_16_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_17_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_18_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_19_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_20_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_21_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_22_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_23_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_24_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_25_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_26_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_27_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_28_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_29_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_3_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_30_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_31_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_32_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_33_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_34_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_35_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_36_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_37_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_38_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_39_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_40_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_41_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_42_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_43_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_44_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_45_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_46_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_47_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_48_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_49_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_5_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_50_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_51_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_7_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_empty_9_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_rd_data_valid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_wr_clk_13_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_wr_clk_19_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_wr_clk_26_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_wr_clk_32_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_wr_clk_39_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_wr_clk_45_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_fifo_wr_clk_6_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_intf_rdy_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pll0_clkout0_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pll0_clkout1_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pll0_locked_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pll1_clkout0_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pll1_locked_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_riu_valid_bg0_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_riu_valid_bg0_bs0_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_riu_valid_bg0_bs1_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_riu_valid_bg1_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_riu_valid_bg1_bs2_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_riu_valid_bg1_bs3_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_riu_valid_bg2_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_riu_valid_bg2_bs4_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_riu_valid_bg2_bs5_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_riu_valid_bg3_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_riu_valid_bg3_bs6_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_riu_valid_bg3_bs7_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_rx_bitslip_sync_done_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_rxtx_bitslip_sync_done_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_shared_pll0_clkoutphy_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_shared_pll1_clkoutphy_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_vtc_rdy_bsc0_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_vtc_rdy_bsc1_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_vtc_rdy_bsc2_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_vtc_rdy_bsc3_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_vtc_rdy_bsc4_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_vtc_rdy_bsc5_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_vtc_rdy_bsc6_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_vtc_rdy_bsc7_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_bidir_tx_bs_tri_cntvalueout0_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_bidir_tx_bs_tri_cntvalueout1_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_bidir_tx_bs_tri_cntvalueout2_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_bidir_tx_bs_tri_cntvalueout3_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_bidir_tx_bs_tri_cntvalueout4_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_bidir_tx_bs_tri_cntvalueout5_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_bidir_tx_bs_tri_cntvalueout6_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_bidir_tx_bs_tri_cntvalueout7_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_data_to_fabric_clk_rxn_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_data_to_fabric_clk_rxp_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_data_to_fabric_data_rxn0_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_data_to_fabric_data_rxn1_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_data_to_fabric_data_rxn2_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_data_to_fabric_data_rxn3_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_do_out_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_riu_rd_data_bg0_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_riu_rd_data_bg0_bs0_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_riu_rd_data_bg0_bs1_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_riu_rd_data_bg1_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_riu_rd_data_bg1_bs2_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_riu_rd_data_bg1_bs3_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_riu_rd_data_bg2_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_riu_rd_data_bg2_bs4_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_riu_rd_data_bg2_bs5_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_riu_rd_data_bg3_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_riu_rd_data_bg3_bs6_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_riu_rd_data_bg3_bs7_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_rx_cntvalueout_0_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_1_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_10_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_11_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_12_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_13_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_14_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_15_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_16_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_17_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_18_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_19_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_2_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_20_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_21_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_22_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_23_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_24_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_25_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_26_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_27_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_28_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_29_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_3_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_30_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_31_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_32_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_33_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_34_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_35_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_36_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_37_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_38_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_39_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_4_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_40_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_41_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_42_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_43_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_44_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_45_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_46_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_47_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_48_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_49_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_5_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_50_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_51_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_6_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_7_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_8_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_9_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_0_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_1_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_10_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_11_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_12_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_13_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_14_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_15_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_16_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_17_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_18_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_19_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_2_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_20_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_21_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_22_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_23_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_24_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_25_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_26_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_27_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_28_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_29_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_3_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_30_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_31_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_32_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_33_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_34_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_35_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_36_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_37_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_38_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_39_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_4_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_40_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_41_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_42_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_43_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_44_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_45_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_46_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_47_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_48_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_49_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_5_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_50_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_51_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_6_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_7_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_8_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_rx_cntvalueout_ext_9_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_0_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_1_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_10_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_11_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_12_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_13_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_14_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_15_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_16_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_17_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_18_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_19_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_2_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_20_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_21_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_22_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_23_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_24_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_25_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_26_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_27_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_28_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_29_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_3_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_30_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_31_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_32_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_33_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_34_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_35_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_36_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_37_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_38_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_39_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_4_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_40_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_41_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_42_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_43_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_44_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_45_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_46_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_47_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_48_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_49_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_5_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_50_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_51_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_6_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_7_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_8_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_tx_cntvalueout_9_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute C_ALL_EN_PIN_INFO : string;
  attribute C_ALL_EN_PIN_INFO of inst : label is "0 {nibble 0 dir RX sig_type DIFF data_strb Strobe data_strb_org Strobe sig_name clk_rxp loc T3} 1 {nibble 0 dir RX sig_type DIFF data_strb Strobe data_strb_org Strobe sig_name clk_rxn loc T2} 2 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp0 loc P3} 3 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn0 loc R3} 4 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp1 loc U2} 5 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn1 loc U1} 6 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp2 loc R4} 7 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn2 loc T4} 8 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp3 loc R1} 9 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn3 loc T1}";
  attribute C_ALL_RX_EN : string;
  attribute C_ALL_RX_EN of inst : label is "52'b0000000000000000000000000000000000000000001111111111";
  attribute C_BANK : integer;
  attribute C_BANK of inst : label is 65;
  attribute C_BIDIR_BITSLICE_EN : string;
  attribute C_BIDIR_BITSLICE_EN of inst : label is "52'b0000000000000000000000000000000000000000000000000000";
  attribute C_BIDIR_FIFO_SYNC_MODE : string;
  attribute C_BIDIR_FIFO_SYNC_MODE of inst : label is "FALSE";
  attribute C_BIDIR_IS_RX_CLK_INVERTED : string;
  attribute C_BIDIR_IS_RX_CLK_INVERTED of inst : label is "1'b0";
  attribute C_BIDIR_IS_RX_RST_DLY_INVERTED : string;
  attribute C_BIDIR_IS_RX_RST_DLY_INVERTED of inst : label is "1'b0";
  attribute C_BIDIR_IS_RX_RST_INVERTED : string;
  attribute C_BIDIR_IS_RX_RST_INVERTED of inst : label is "1'b0";
  attribute C_BIDIR_IS_TX_CLK_INVERTED : string;
  attribute C_BIDIR_IS_TX_CLK_INVERTED of inst : label is "1'b0";
  attribute C_BIDIR_IS_TX_RST_DLY_INVERTED : string;
  attribute C_BIDIR_IS_TX_RST_DLY_INVERTED of inst : label is "1'b0";
  attribute C_BIDIR_IS_TX_RST_INVERTED : string;
  attribute C_BIDIR_IS_TX_RST_INVERTED of inst : label is "1'b0";
  attribute C_BIDIR_RX_DELAY_FORMAT : string;
  attribute C_BIDIR_RX_DELAY_FORMAT of inst : label is "TIME";
  attribute C_BIDIR_TX_DELAY_FORMAT : string;
  attribute C_BIDIR_TX_DELAY_FORMAT of inst : label is "TIME";
  attribute C_BITSLIP_MODE : string;
  attribute C_BITSLIP_MODE of inst : label is "SLIP_PER_BIT";
  attribute C_BITSLIP_VAL : string;
  attribute C_BITSLIP_VAL of inst : label is "8'b00101100";
  attribute C_BS0_INFO : string;
  attribute C_BS0_INFO of inst : label is "0 {name bg0_pin0_nc loc T3} 1 {name bg0_pin6_nc loc R4} 2 {name bg1_pin0_nc loc N2} 3 {name bg1_pin6_nc loc M5} 4 {name bg2_pin0_nc loc J3} 5 {name bg2_pin6_nc loc J5} 6 {name bg3_pin0_nc loc G1} 7 {name bg3_pin6_nc loc D3}";
  attribute C_BSC_CTRL_CLK : string;
  attribute C_BSC_CTRL_CLK of inst : label is "EXTERNAL";
  attribute C_BSC_EN_DYN_ODLY_MODE : string;
  attribute C_BSC_EN_DYN_ODLY_MODE of inst : label is "FALSE";
  attribute C_BSC_IDLY_VT_TRACK : string;
  attribute C_BSC_IDLY_VT_TRACK of inst : label is "TRUE";
  attribute C_BSC_ODLY_VT_TRACK : string;
  attribute C_BSC_ODLY_VT_TRACK of inst : label is "TRUE";
  attribute C_BSC_QDLY_VT_TRACK : string;
  attribute C_BSC_QDLY_VT_TRACK of inst : label is "TRUE";
  attribute C_BSC_READ_IDLE_COUNT : string;
  attribute C_BSC_READ_IDLE_COUNT of inst : label is "6'b000000";
  attribute C_BSC_REFCLK_SRC : string;
  attribute C_BSC_REFCLK_SRC of inst : label is "PLLCLK";
  attribute C_BSC_ROUNDING_FACTOR : integer;
  attribute C_BSC_ROUNDING_FACTOR of inst : label is 16;
  attribute C_BSC_RXGATE_EXTEND : string;
  attribute C_BSC_RXGATE_EXTEND of inst : label is "FALSE";
  attribute C_BSC_RX_GATING : string;
  attribute C_BSC_RX_GATING of inst : label is "DISABLE";
  attribute C_BSC_SELF_CALIBRATE : string;
  attribute C_BSC_SELF_CALIBRATE of inst : label is "ENABLE";
  attribute C_BSC_SIM_SPEEDUP : string;
  attribute C_BSC_SIM_SPEEDUP of inst : label is "FAST";
  attribute C_BS_INIT_VAL : string;
  attribute C_BS_INIT_VAL of inst : label is "52'b0000000000000000000000000000000000000000000000000000";
  attribute C_CLKIN_DIFF_EN : integer;
  attribute C_CLKIN_DIFF_EN of inst : label is 0;
  attribute C_CLKIN_PERIOD : string;
  attribute C_CLKIN_PERIOD of inst : label is "5.000000";
  attribute C_CLK_FWD : integer;
  attribute C_CLK_FWD of inst : label is 0;
  attribute C_CLK_FWD_BITSLICE_NO : integer;
  attribute C_CLK_FWD_BITSLICE_NO of inst : label is 0;
  attribute C_CLK_FWD_ENABLE : string;
  attribute C_CLK_FWD_ENABLE of inst : label is "52'b0000000000000000000000000000000000000000000000000000";
  attribute C_CLK_FWD_PHASE : integer;
  attribute C_CLK_FWD_PHASE of inst : label is 0;
  attribute C_CLK_SIG_TYPE : string;
  attribute C_CLK_SIG_TYPE of inst : label is "SINGLE";
  attribute C_CLOCK_TRI : integer;
  attribute C_CLOCK_TRI of inst : label is 1;
  attribute C_DATA_PIN_EN : integer;
  attribute C_DATA_PIN_EN of inst : label is 5;
  attribute C_DATA_TRI : integer;
  attribute C_DATA_TRI of inst : label is 1;
  attribute C_DEVICE : string;
  attribute C_DEVICE of inst : label is "xczu1cg";
  attribute C_DEVICE_FAMILY : string;
  attribute C_DEVICE_FAMILY of inst : label is "zynquplus";
  attribute C_DIFFERENTIAL_IO_STD : string;
  attribute C_DIFFERENTIAL_IO_STD of inst : label is "MIPI_DPHY_DCI";
  attribute C_DIFFERENTIAL_IO_TERMINATION : string;
  attribute C_DIFFERENTIAL_IO_TERMINATION of inst : label is "TERM_100";
  attribute C_DIFF_EN : string;
  attribute C_DIFF_EN of inst : label is "52'b0000000000000000000000000000000000000000001111111111";
  attribute C_DIV_MODE : string;
  attribute C_DIV_MODE of inst : label is "DIV4";
  attribute C_ENABLE_BITSLIP : integer;
  attribute C_ENABLE_BITSLIP of inst : label is 0;
  attribute C_ENABLE_DATA_BITSLIP : integer;
  attribute C_ENABLE_DATA_BITSLIP of inst : label is 0;
  attribute C_ENABLE_N_PINS : integer;
  attribute C_ENABLE_N_PINS of inst : label is 1;
  attribute C_ENABLE_PLL0_PLLOUT1 : integer;
  attribute C_ENABLE_PLL0_PLLOUT1 of inst : label is 0;
  attribute C_ENABLE_PLL0_PLLOUTFB : integer;
  attribute C_ENABLE_PLL0_PLLOUTFB of inst : label is 0;
  attribute C_ENABLE_RIU_INTERFACE : integer;
  attribute C_ENABLE_RIU_INTERFACE of inst : label is 0;
  attribute C_ENABLE_RIU_SPLIT : integer;
  attribute C_ENABLE_RIU_SPLIT of inst : label is 0;
  attribute C_ENABLE_TX_TRI : integer;
  attribute C_ENABLE_TX_TRI of inst : label is 0;
  attribute C_EN_BIDIR : integer;
  attribute C_EN_BIDIR of inst : label is 0;
  attribute C_EN_BSC0 : integer;
  attribute C_EN_BSC0 of inst : label is 1;
  attribute C_EN_BSC1 : integer;
  attribute C_EN_BSC1 of inst : label is 1;
  attribute C_EN_BSC2 : integer;
  attribute C_EN_BSC2 of inst : label is 0;
  attribute C_EN_BSC3 : integer;
  attribute C_EN_BSC3 of inst : label is 0;
  attribute C_EN_BSC4 : integer;
  attribute C_EN_BSC4 of inst : label is 0;
  attribute C_EN_BSC5 : integer;
  attribute C_EN_BSC5 of inst : label is 0;
  attribute C_EN_BSC6 : integer;
  attribute C_EN_BSC6 of inst : label is 0;
  attribute C_EN_BSC7 : integer;
  attribute C_EN_BSC7 of inst : label is 0;
  attribute C_EN_MULTI_INTF_PORTS : integer;
  attribute C_EN_MULTI_INTF_PORTS of inst : label is 0;
  attribute C_EN_RIU_OR0 : string;
  attribute C_EN_RIU_OR0 of inst : label is "TRUE";
  attribute C_EN_RIU_OR1 : string;
  attribute C_EN_RIU_OR1 of inst : label is "FALSE";
  attribute C_EN_RIU_OR2 : string;
  attribute C_EN_RIU_OR2 of inst : label is "FALSE";
  attribute C_EN_RIU_OR3 : string;
  attribute C_EN_RIU_OR3 of inst : label is "FALSE";
  attribute C_EN_RX : integer;
  attribute C_EN_RX of inst : label is 1;
  attribute C_EN_TX : integer;
  attribute C_EN_TX of inst : label is 0;
  attribute C_EN_VTC : integer;
  attribute C_EN_VTC of inst : label is 0;
  attribute C_EXDES_BANK : string;
  attribute C_EXDES_BANK of inst : label is "";
  attribute C_EX_CLK_FREQ : string;
  attribute C_EX_CLK_FREQ of inst : label is "200.000000";
  attribute C_EX_INST_GEN : integer;
  attribute C_EX_INST_GEN of inst : label is 0;
  attribute C_FIFO_SYNC_MODE : integer;
  attribute C_FIFO_SYNC_MODE of inst : label is 1;
  attribute C_GC_LOC : string;
  attribute C_GC_LOC of inst : label is "21 {name IO_L11P_T1U_N8_GC_65 loc L2} 23 {name IO_L12P_T1U_N10_GC_65 loc L4} 28 {name IO_L14P_T2L_N2_GC_65 loc K4}";
  attribute C_INCLK_LOC : string;
  attribute C_INCLK_LOC of inst : label is "NONE";
  attribute C_INCLK_PIN : integer;
  attribute C_INCLK_PIN of inst : label is 100;
  attribute C_INV_RX_CLK : string;
  attribute C_INV_RX_CLK of inst : label is "8'b00000000";
  attribute C_NIB0_BS0_EN : integer;
  attribute C_NIB0_BS0_EN of inst : label is 0;
  attribute C_NIB0_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB0_EN_CLK_TO_EXT_NORTH of inst : label is "1'b0";
  attribute C_NIB0_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB0_EN_CLK_TO_EXT_SOUTH of inst : label is "1'b0";
  attribute C_NIB0_EN_OTHER_NCLK : string;
  attribute C_NIB0_EN_OTHER_NCLK of inst : label is "1'b0";
  attribute C_NIB0_EN_OTHER_PCLK : string;
  attribute C_NIB0_EN_OTHER_PCLK of inst : label is "1'b0";
  attribute C_NIB1_BS0_EN : integer;
  attribute C_NIB1_BS0_EN of inst : label is 0;
  attribute C_NIB1_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB1_EN_CLK_TO_EXT_NORTH of inst : label is "1'b0";
  attribute C_NIB1_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB1_EN_CLK_TO_EXT_SOUTH of inst : label is "1'b0";
  attribute C_NIB1_EN_OTHER_NCLK : string;
  attribute C_NIB1_EN_OTHER_NCLK of inst : label is "1'b1";
  attribute C_NIB1_EN_OTHER_PCLK : string;
  attribute C_NIB1_EN_OTHER_PCLK of inst : label is "1'b1";
  attribute C_NIB2_BS0_EN : integer;
  attribute C_NIB2_BS0_EN of inst : label is 0;
  attribute C_NIB2_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB2_EN_CLK_TO_EXT_NORTH of inst : label is "1'b0";
  attribute C_NIB2_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB2_EN_CLK_TO_EXT_SOUTH of inst : label is "1'b0";
  attribute C_NIB2_EN_OTHER_NCLK : string;
  attribute C_NIB2_EN_OTHER_NCLK of inst : label is "1'b0";
  attribute C_NIB2_EN_OTHER_PCLK : string;
  attribute C_NIB2_EN_OTHER_PCLK of inst : label is "1'b0";
  attribute C_NIB3_BS0_EN : integer;
  attribute C_NIB3_BS0_EN of inst : label is 0;
  attribute C_NIB3_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB3_EN_CLK_TO_EXT_NORTH of inst : label is "1'b0";
  attribute C_NIB3_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB3_EN_CLK_TO_EXT_SOUTH of inst : label is "1'b0";
  attribute C_NIB3_EN_OTHER_NCLK : string;
  attribute C_NIB3_EN_OTHER_NCLK of inst : label is "1'b0";
  attribute C_NIB3_EN_OTHER_PCLK : string;
  attribute C_NIB3_EN_OTHER_PCLK of inst : label is "1'b0";
  attribute C_NIB4_BS0_EN : integer;
  attribute C_NIB4_BS0_EN of inst : label is 0;
  attribute C_NIB4_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB4_EN_CLK_TO_EXT_NORTH of inst : label is "1'b0";
  attribute C_NIB4_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB4_EN_CLK_TO_EXT_SOUTH of inst : label is "1'b0";
  attribute C_NIB4_EN_OTHER_NCLK : string;
  attribute C_NIB4_EN_OTHER_NCLK of inst : label is "1'b0";
  attribute C_NIB4_EN_OTHER_PCLK : string;
  attribute C_NIB4_EN_OTHER_PCLK of inst : label is "1'b0";
  attribute C_NIB5_BS0_EN : integer;
  attribute C_NIB5_BS0_EN of inst : label is 0;
  attribute C_NIB5_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB5_EN_CLK_TO_EXT_NORTH of inst : label is "1'b0";
  attribute C_NIB5_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB5_EN_CLK_TO_EXT_SOUTH of inst : label is "1'b0";
  attribute C_NIB5_EN_OTHER_NCLK : string;
  attribute C_NIB5_EN_OTHER_NCLK of inst : label is "1'b0";
  attribute C_NIB5_EN_OTHER_PCLK : string;
  attribute C_NIB5_EN_OTHER_PCLK of inst : label is "1'b0";
  attribute C_NIB6_BS0_EN : integer;
  attribute C_NIB6_BS0_EN of inst : label is 0;
  attribute C_NIB6_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB6_EN_CLK_TO_EXT_NORTH of inst : label is "1'b0";
  attribute C_NIB6_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB6_EN_CLK_TO_EXT_SOUTH of inst : label is "1'b0";
  attribute C_NIB6_EN_OTHER_NCLK : string;
  attribute C_NIB6_EN_OTHER_NCLK of inst : label is "1'b0";
  attribute C_NIB6_EN_OTHER_PCLK : string;
  attribute C_NIB6_EN_OTHER_PCLK of inst : label is "1'b0";
  attribute C_NIB7_BS0_EN : integer;
  attribute C_NIB7_BS0_EN of inst : label is 0;
  attribute C_NIB7_EN_CLK_TO_EXT_NORTH : string;
  attribute C_NIB7_EN_CLK_TO_EXT_NORTH of inst : label is "1'b0";
  attribute C_NIB7_EN_CLK_TO_EXT_SOUTH : string;
  attribute C_NIB7_EN_CLK_TO_EXT_SOUTH of inst : label is "1'b0";
  attribute C_NIB7_EN_OTHER_NCLK : string;
  attribute C_NIB7_EN_OTHER_NCLK of inst : label is "1'b0";
  attribute C_NIB7_EN_OTHER_PCLK : string;
  attribute C_NIB7_EN_OTHER_PCLK of inst : label is "1'b0";
  attribute C_NIBBLE0_TRI : integer;
  attribute C_NIBBLE0_TRI of inst : label is 0;
  attribute C_NIBBLE1_TRI : integer;
  attribute C_NIBBLE1_TRI of inst : label is 0;
  attribute C_NIBBLE2_TRI : integer;
  attribute C_NIBBLE2_TRI of inst : label is 0;
  attribute C_NIBBLE3_TRI : integer;
  attribute C_NIBBLE3_TRI of inst : label is 0;
  attribute C_NIBBLE4_TRI : integer;
  attribute C_NIBBLE4_TRI of inst : label is 0;
  attribute C_NIBBLE5_TRI : integer;
  attribute C_NIBBLE5_TRI of inst : label is 0;
  attribute C_NIBBLE6_TRI : integer;
  attribute C_NIBBLE6_TRI of inst : label is 0;
  attribute C_NIBBLE7_TRI : integer;
  attribute C_NIBBLE7_TRI of inst : label is 0;
  attribute C_PIN_INFO : string;
  attribute C_PIN_INFO of inst : label is "0 {nibble 0 dir RX sig_type DIFF data_strb Strobe data_strb_org Strobe sig_name clk_rxp loc T3} 1 {nibble 0 dir RX sig_type DIFF data_strb Strobe data_strb_org Strobe sig_name clk_rxn loc T2} 2 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp0 loc P3} 3 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn0 loc R3} 4 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp1 loc U2} 5 {nibble 0 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn1 loc U1} 6 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp2 loc R4} 7 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn2 loc T4} 8 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxp3 loc R1} 9 {nibble 1 dir RX sig_type DIFF data_strb Data data_strb_org Data sig_name data_rxn3 loc T1}";
  attribute C_PLL0_CLK0_PHASE : string;
  attribute C_PLL0_CLK0_PHASE of inst : label is "0.000000";
  attribute C_PLL0_CLK1_PHASE : string;
  attribute C_PLL0_CLK1_PHASE of inst : label is "0.000000";
  attribute C_PLL0_CLKFBOUT_MULT : integer;
  attribute C_PLL0_CLKFBOUT_MULT of inst : label is 15;
  attribute C_PLL0_CLKOUT1_DIVIDE : integer;
  attribute C_PLL0_CLKOUT1_DIVIDE of inst : label is 1;
  attribute C_PLL0_CLKOUTPHY_MODE : string;
  attribute C_PLL0_CLKOUTPHY_MODE of inst : label is "VCO";
  attribute C_PLL0_CLK_SOURCE : string;
  attribute C_PLL0_CLK_SOURCE of inst : label is "BUFG_TO_PLL";
  attribute C_PLL0_DIVCLK_DIVIDE : integer;
  attribute C_PLL0_DIVCLK_DIVIDE of inst : label is 2;
  attribute C_PLL0_DIV_FACTOR : string;
  attribute C_PLL0_DIV_FACTOR of inst : label is "1.000000";
  attribute C_PLL0_FIFO_WRITE_CLK_EN : integer;
  attribute C_PLL0_FIFO_WRITE_CLK_EN of inst : label is 1;
  attribute C_PLL0_MMCM_CLKFBOUT_MULT_F : string;
  attribute C_PLL0_MMCM_CLKFBOUT_MULT_F of inst : label is "7.875000";
  attribute C_PLL0_MMCM_CLKOUT0_DIVIDE_F : string;
  attribute C_PLL0_MMCM_CLKOUT0_DIVIDE_F of inst : label is "7.875000";
  attribute C_PLL0_MMCM_DIVCLK_DIVIDE : integer;
  attribute C_PLL0_MMCM_DIVCLK_DIVIDE of inst : label is 1;
  attribute C_PLL0_RX_EXTERNAL_CLK_TO_DATA : integer;
  attribute C_PLL0_RX_EXTERNAL_CLK_TO_DATA of inst : label is 3;
  attribute C_PLL1_CLK0_PHASE : string;
  attribute C_PLL1_CLK0_PHASE of inst : label is "0.000000";
  attribute C_PLL1_CLK1_PHASE : string;
  attribute C_PLL1_CLK1_PHASE of inst : label is "0.000000";
  attribute C_PLL1_CLKFBOUT_MULT : integer;
  attribute C_PLL1_CLKFBOUT_MULT of inst : label is 15;
  attribute C_PLL1_CLKOUTPHY_MODE : string;
  attribute C_PLL1_CLKOUTPHY_MODE of inst : label is "VCO";
  attribute C_PLL1_DIVCLK_DIVIDE : integer;
  attribute C_PLL1_DIVCLK_DIVIDE of inst : label is 2;
  attribute C_PLL1_DIV_FACTOR : string;
  attribute C_PLL1_DIV_FACTOR of inst : label is "1.000000";
  attribute C_PLL_SHARING : integer;
  attribute C_PLL_SHARING of inst : label is 0;
  attribute C_PLL_VCOMIN : string;
  attribute C_PLL_VCOMIN of inst : label is "750.000000";
  attribute C_REC_IN_FREQ : string;
  attribute C_REC_IN_FREQ of inst : label is "93.750";
  attribute C_RX_BITSLICE0_EN : string;
  attribute C_RX_BITSLICE0_EN of inst : label is "8'b00000000";
  attribute C_RX_BITSLICE_EN : string;
  attribute C_RX_BITSLICE_EN of inst : label is "52'b0000000000000000000000000000000000000000001111111111";
  attribute C_RX_DELAY_CASCADE : integer;
  attribute C_RX_DELAY_CASCADE of inst : label is 0;
  attribute C_RX_DELAY_FORMAT : string;
  attribute C_RX_DELAY_FORMAT of inst : label is "TIME";
  attribute C_RX_DELAY_TYPE : string;
  attribute C_RX_DELAY_TYPE of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE0 : string;
  attribute C_RX_DELAY_TYPE0 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE1 : string;
  attribute C_RX_DELAY_TYPE1 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE10 : string;
  attribute C_RX_DELAY_TYPE10 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE11 : string;
  attribute C_RX_DELAY_TYPE11 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE12 : string;
  attribute C_RX_DELAY_TYPE12 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE13 : string;
  attribute C_RX_DELAY_TYPE13 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE14 : string;
  attribute C_RX_DELAY_TYPE14 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE15 : string;
  attribute C_RX_DELAY_TYPE15 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE16 : string;
  attribute C_RX_DELAY_TYPE16 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE17 : string;
  attribute C_RX_DELAY_TYPE17 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE18 : string;
  attribute C_RX_DELAY_TYPE18 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE19 : string;
  attribute C_RX_DELAY_TYPE19 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE2 : string;
  attribute C_RX_DELAY_TYPE2 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE20 : string;
  attribute C_RX_DELAY_TYPE20 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE21 : string;
  attribute C_RX_DELAY_TYPE21 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE22 : string;
  attribute C_RX_DELAY_TYPE22 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE23 : string;
  attribute C_RX_DELAY_TYPE23 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE24 : string;
  attribute C_RX_DELAY_TYPE24 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE25 : string;
  attribute C_RX_DELAY_TYPE25 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE26 : string;
  attribute C_RX_DELAY_TYPE26 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE27 : string;
  attribute C_RX_DELAY_TYPE27 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE28 : string;
  attribute C_RX_DELAY_TYPE28 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE29 : string;
  attribute C_RX_DELAY_TYPE29 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE3 : string;
  attribute C_RX_DELAY_TYPE3 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE30 : string;
  attribute C_RX_DELAY_TYPE30 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE31 : string;
  attribute C_RX_DELAY_TYPE31 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE32 : string;
  attribute C_RX_DELAY_TYPE32 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE33 : string;
  attribute C_RX_DELAY_TYPE33 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE34 : string;
  attribute C_RX_DELAY_TYPE34 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE35 : string;
  attribute C_RX_DELAY_TYPE35 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE36 : string;
  attribute C_RX_DELAY_TYPE36 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE37 : string;
  attribute C_RX_DELAY_TYPE37 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE38 : string;
  attribute C_RX_DELAY_TYPE38 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE39 : string;
  attribute C_RX_DELAY_TYPE39 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE4 : string;
  attribute C_RX_DELAY_TYPE4 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE40 : string;
  attribute C_RX_DELAY_TYPE40 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE41 : string;
  attribute C_RX_DELAY_TYPE41 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE42 : string;
  attribute C_RX_DELAY_TYPE42 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE43 : string;
  attribute C_RX_DELAY_TYPE43 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE44 : string;
  attribute C_RX_DELAY_TYPE44 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE45 : string;
  attribute C_RX_DELAY_TYPE45 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE46 : string;
  attribute C_RX_DELAY_TYPE46 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE47 : string;
  attribute C_RX_DELAY_TYPE47 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE48 : string;
  attribute C_RX_DELAY_TYPE48 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE49 : string;
  attribute C_RX_DELAY_TYPE49 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE5 : string;
  attribute C_RX_DELAY_TYPE5 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE50 : string;
  attribute C_RX_DELAY_TYPE50 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE51 : string;
  attribute C_RX_DELAY_TYPE51 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE6 : string;
  attribute C_RX_DELAY_TYPE6 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE7 : string;
  attribute C_RX_DELAY_TYPE7 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE8 : string;
  attribute C_RX_DELAY_TYPE8 of inst : label is "2'b00";
  attribute C_RX_DELAY_TYPE9 : string;
  attribute C_RX_DELAY_TYPE9 of inst : label is "2'b00";
  attribute C_RX_DELAY_VALUE : string;
  attribute C_RX_DELAY_VALUE of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE0 : string;
  attribute C_RX_DELAY_VALUE0 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE1 : string;
  attribute C_RX_DELAY_VALUE1 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE10 : string;
  attribute C_RX_DELAY_VALUE10 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE11 : string;
  attribute C_RX_DELAY_VALUE11 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE12 : string;
  attribute C_RX_DELAY_VALUE12 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE13 : string;
  attribute C_RX_DELAY_VALUE13 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE14 : string;
  attribute C_RX_DELAY_VALUE14 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE15 : string;
  attribute C_RX_DELAY_VALUE15 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE16 : string;
  attribute C_RX_DELAY_VALUE16 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE17 : string;
  attribute C_RX_DELAY_VALUE17 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE18 : string;
  attribute C_RX_DELAY_VALUE18 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE19 : string;
  attribute C_RX_DELAY_VALUE19 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE2 : string;
  attribute C_RX_DELAY_VALUE2 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE20 : string;
  attribute C_RX_DELAY_VALUE20 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE21 : string;
  attribute C_RX_DELAY_VALUE21 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE22 : string;
  attribute C_RX_DELAY_VALUE22 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE23 : string;
  attribute C_RX_DELAY_VALUE23 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE24 : string;
  attribute C_RX_DELAY_VALUE24 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE25 : string;
  attribute C_RX_DELAY_VALUE25 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE26 : string;
  attribute C_RX_DELAY_VALUE26 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE27 : string;
  attribute C_RX_DELAY_VALUE27 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE28 : string;
  attribute C_RX_DELAY_VALUE28 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE29 : string;
  attribute C_RX_DELAY_VALUE29 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE3 : string;
  attribute C_RX_DELAY_VALUE3 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE30 : string;
  attribute C_RX_DELAY_VALUE30 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE31 : string;
  attribute C_RX_DELAY_VALUE31 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE32 : string;
  attribute C_RX_DELAY_VALUE32 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE33 : string;
  attribute C_RX_DELAY_VALUE33 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE34 : string;
  attribute C_RX_DELAY_VALUE34 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE35 : string;
  attribute C_RX_DELAY_VALUE35 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE36 : string;
  attribute C_RX_DELAY_VALUE36 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE37 : string;
  attribute C_RX_DELAY_VALUE37 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE38 : string;
  attribute C_RX_DELAY_VALUE38 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE39 : string;
  attribute C_RX_DELAY_VALUE39 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE4 : string;
  attribute C_RX_DELAY_VALUE4 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE40 : string;
  attribute C_RX_DELAY_VALUE40 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE41 : string;
  attribute C_RX_DELAY_VALUE41 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE42 : string;
  attribute C_RX_DELAY_VALUE42 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE43 : string;
  attribute C_RX_DELAY_VALUE43 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE44 : string;
  attribute C_RX_DELAY_VALUE44 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE45 : string;
  attribute C_RX_DELAY_VALUE45 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE46 : string;
  attribute C_RX_DELAY_VALUE46 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE47 : string;
  attribute C_RX_DELAY_VALUE47 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE48 : string;
  attribute C_RX_DELAY_VALUE48 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE49 : string;
  attribute C_RX_DELAY_VALUE49 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE5 : string;
  attribute C_RX_DELAY_VALUE5 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE50 : string;
  attribute C_RX_DELAY_VALUE50 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE51 : string;
  attribute C_RX_DELAY_VALUE51 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE6 : string;
  attribute C_RX_DELAY_VALUE6 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE7 : string;
  attribute C_RX_DELAY_VALUE7 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE8 : string;
  attribute C_RX_DELAY_VALUE8 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE9 : string;
  attribute C_RX_DELAY_VALUE9 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT0 : string;
  attribute C_RX_DELAY_VALUE_EXT0 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT1 : string;
  attribute C_RX_DELAY_VALUE_EXT1 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT10 : string;
  attribute C_RX_DELAY_VALUE_EXT10 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT11 : string;
  attribute C_RX_DELAY_VALUE_EXT11 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT12 : string;
  attribute C_RX_DELAY_VALUE_EXT12 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT13 : string;
  attribute C_RX_DELAY_VALUE_EXT13 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT14 : string;
  attribute C_RX_DELAY_VALUE_EXT14 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT15 : string;
  attribute C_RX_DELAY_VALUE_EXT15 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT16 : string;
  attribute C_RX_DELAY_VALUE_EXT16 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT17 : string;
  attribute C_RX_DELAY_VALUE_EXT17 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT18 : string;
  attribute C_RX_DELAY_VALUE_EXT18 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT19 : string;
  attribute C_RX_DELAY_VALUE_EXT19 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT2 : string;
  attribute C_RX_DELAY_VALUE_EXT2 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT20 : string;
  attribute C_RX_DELAY_VALUE_EXT20 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT21 : string;
  attribute C_RX_DELAY_VALUE_EXT21 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT22 : string;
  attribute C_RX_DELAY_VALUE_EXT22 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT23 : string;
  attribute C_RX_DELAY_VALUE_EXT23 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT24 : string;
  attribute C_RX_DELAY_VALUE_EXT24 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT25 : string;
  attribute C_RX_DELAY_VALUE_EXT25 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT26 : string;
  attribute C_RX_DELAY_VALUE_EXT26 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT27 : string;
  attribute C_RX_DELAY_VALUE_EXT27 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT28 : string;
  attribute C_RX_DELAY_VALUE_EXT28 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT29 : string;
  attribute C_RX_DELAY_VALUE_EXT29 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT3 : string;
  attribute C_RX_DELAY_VALUE_EXT3 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT30 : string;
  attribute C_RX_DELAY_VALUE_EXT30 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT31 : string;
  attribute C_RX_DELAY_VALUE_EXT31 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT32 : string;
  attribute C_RX_DELAY_VALUE_EXT32 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT33 : string;
  attribute C_RX_DELAY_VALUE_EXT33 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT34 : string;
  attribute C_RX_DELAY_VALUE_EXT34 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT35 : string;
  attribute C_RX_DELAY_VALUE_EXT35 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT36 : string;
  attribute C_RX_DELAY_VALUE_EXT36 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT37 : string;
  attribute C_RX_DELAY_VALUE_EXT37 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT38 : string;
  attribute C_RX_DELAY_VALUE_EXT38 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT39 : string;
  attribute C_RX_DELAY_VALUE_EXT39 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT4 : string;
  attribute C_RX_DELAY_VALUE_EXT4 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT40 : string;
  attribute C_RX_DELAY_VALUE_EXT40 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT41 : string;
  attribute C_RX_DELAY_VALUE_EXT41 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT42 : string;
  attribute C_RX_DELAY_VALUE_EXT42 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT43 : string;
  attribute C_RX_DELAY_VALUE_EXT43 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT44 : string;
  attribute C_RX_DELAY_VALUE_EXT44 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT45 : string;
  attribute C_RX_DELAY_VALUE_EXT45 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT46 : string;
  attribute C_RX_DELAY_VALUE_EXT46 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT47 : string;
  attribute C_RX_DELAY_VALUE_EXT47 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT48 : string;
  attribute C_RX_DELAY_VALUE_EXT48 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT49 : string;
  attribute C_RX_DELAY_VALUE_EXT49 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT5 : string;
  attribute C_RX_DELAY_VALUE_EXT5 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT50 : string;
  attribute C_RX_DELAY_VALUE_EXT50 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT51 : string;
  attribute C_RX_DELAY_VALUE_EXT51 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT6 : string;
  attribute C_RX_DELAY_VALUE_EXT6 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT7 : string;
  attribute C_RX_DELAY_VALUE_EXT7 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT8 : string;
  attribute C_RX_DELAY_VALUE_EXT8 of inst : label is "12'b000000000000";
  attribute C_RX_DELAY_VALUE_EXT9 : string;
  attribute C_RX_DELAY_VALUE_EXT9 of inst : label is "12'b000000000000";
  attribute C_RX_EQUALIZATION_D : string;
  attribute C_RX_EQUALIZATION_D of inst : label is "EQ_NONE";
  attribute C_RX_EQUALIZATION_S : string;
  attribute C_RX_EQUALIZATION_S of inst : label is "NONE";
  attribute C_RX_FIFO_SYNC_MODE : string;
  attribute C_RX_FIFO_SYNC_MODE of inst : label is "FALSE";
  attribute C_RX_IS_CLK_EXT_INVERTED : string;
  attribute C_RX_IS_CLK_EXT_INVERTED of inst : label is "1'b0";
  attribute C_RX_IS_CLK_INVERTED : string;
  attribute C_RX_IS_CLK_INVERTED of inst : label is "1'b0";
  attribute C_RX_IS_RST_DLY_EXT_INVERTED : string;
  attribute C_RX_IS_RST_DLY_EXT_INVERTED of inst : label is "1'b0";
  attribute C_RX_IS_RST_DLY_INVERTED : string;
  attribute C_RX_IS_RST_DLY_INVERTED of inst : label is "1'b0";
  attribute C_RX_IS_RST_INVERTED : string;
  attribute C_RX_IS_RST_INVERTED of inst : label is "1'b0";
  attribute C_RX_PIN_EN : string;
  attribute C_RX_PIN_EN of inst : label is "52'b0000000000000000000000000000000000000000000101010101";
  attribute C_RX_REFCLK_FREQ : string;
  attribute C_RX_REFCLK_FREQ of inst : label is "1500.000000";
  attribute C_RX_STROBE_EN : string;
  attribute C_RX_STROBE_EN of inst : label is "16'b0000000000000011";
  attribute C_SERIALIZATION_FACTOR : integer;
  attribute C_SERIALIZATION_FACTOR of inst : label is 8;
  attribute C_SERIAL_MODE : string;
  attribute C_SERIAL_MODE of inst : label is "FALSE";
  attribute C_SIM_DEVICE : string;
  attribute C_SIM_DEVICE of inst : label is "ULTRASCALE_PLUS_ES1";
  attribute C_SIM_VERSION : string;
  attribute C_SIM_VERSION of inst : label is "2.000000";
  attribute C_SINGLE_ENDED_IO_STD : string;
  attribute C_SINGLE_ENDED_IO_STD of inst : label is "NONE";
  attribute C_SINGLE_ENDED_IO_TERMINATION : string;
  attribute C_SINGLE_ENDED_IO_TERMINATION of inst : label is "NONE";
  attribute C_STRB_INFO : string;
  attribute C_STRB_INFO of inst : label is "9 99 9 9 9 9 9 9 9 9 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99";
  attribute C_TEMPLATE : integer;
  attribute C_TEMPLATE of inst : label is 2;
  attribute C_TX_BITSLICE_EN : string;
  attribute C_TX_BITSLICE_EN of inst : label is "52'b0000000000000000000000000000000000000000000000000000";
  attribute C_TX_DATA_PHASE : integer;
  attribute C_TX_DATA_PHASE of inst : label is 0;
  attribute C_TX_DELAY_FORMAT : string;
  attribute C_TX_DELAY_FORMAT of inst : label is "TIME";
  attribute C_TX_DELAY_TYPE : integer;
  attribute C_TX_DELAY_TYPE of inst : label is 0;
  attribute C_TX_DELAY_TYPE0 : string;
  attribute C_TX_DELAY_TYPE0 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE1 : string;
  attribute C_TX_DELAY_TYPE1 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE10 : string;
  attribute C_TX_DELAY_TYPE10 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE11 : string;
  attribute C_TX_DELAY_TYPE11 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE12 : string;
  attribute C_TX_DELAY_TYPE12 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE13 : string;
  attribute C_TX_DELAY_TYPE13 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE14 : string;
  attribute C_TX_DELAY_TYPE14 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE15 : string;
  attribute C_TX_DELAY_TYPE15 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE16 : string;
  attribute C_TX_DELAY_TYPE16 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE17 : string;
  attribute C_TX_DELAY_TYPE17 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE18 : string;
  attribute C_TX_DELAY_TYPE18 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE19 : string;
  attribute C_TX_DELAY_TYPE19 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE2 : string;
  attribute C_TX_DELAY_TYPE2 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE20 : string;
  attribute C_TX_DELAY_TYPE20 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE21 : string;
  attribute C_TX_DELAY_TYPE21 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE22 : string;
  attribute C_TX_DELAY_TYPE22 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE23 : string;
  attribute C_TX_DELAY_TYPE23 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE24 : string;
  attribute C_TX_DELAY_TYPE24 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE25 : string;
  attribute C_TX_DELAY_TYPE25 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE26 : string;
  attribute C_TX_DELAY_TYPE26 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE27 : string;
  attribute C_TX_DELAY_TYPE27 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE28 : string;
  attribute C_TX_DELAY_TYPE28 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE29 : string;
  attribute C_TX_DELAY_TYPE29 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE3 : string;
  attribute C_TX_DELAY_TYPE3 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE30 : string;
  attribute C_TX_DELAY_TYPE30 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE31 : string;
  attribute C_TX_DELAY_TYPE31 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE32 : string;
  attribute C_TX_DELAY_TYPE32 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE33 : string;
  attribute C_TX_DELAY_TYPE33 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE34 : string;
  attribute C_TX_DELAY_TYPE34 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE35 : string;
  attribute C_TX_DELAY_TYPE35 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE36 : string;
  attribute C_TX_DELAY_TYPE36 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE37 : string;
  attribute C_TX_DELAY_TYPE37 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE38 : string;
  attribute C_TX_DELAY_TYPE38 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE39 : string;
  attribute C_TX_DELAY_TYPE39 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE4 : string;
  attribute C_TX_DELAY_TYPE4 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE40 : string;
  attribute C_TX_DELAY_TYPE40 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE41 : string;
  attribute C_TX_DELAY_TYPE41 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE42 : string;
  attribute C_TX_DELAY_TYPE42 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE43 : string;
  attribute C_TX_DELAY_TYPE43 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE44 : string;
  attribute C_TX_DELAY_TYPE44 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE45 : string;
  attribute C_TX_DELAY_TYPE45 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE46 : string;
  attribute C_TX_DELAY_TYPE46 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE47 : string;
  attribute C_TX_DELAY_TYPE47 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE48 : string;
  attribute C_TX_DELAY_TYPE48 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE49 : string;
  attribute C_TX_DELAY_TYPE49 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE5 : string;
  attribute C_TX_DELAY_TYPE5 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE50 : string;
  attribute C_TX_DELAY_TYPE50 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE51 : string;
  attribute C_TX_DELAY_TYPE51 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE6 : string;
  attribute C_TX_DELAY_TYPE6 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE7 : string;
  attribute C_TX_DELAY_TYPE7 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE8 : string;
  attribute C_TX_DELAY_TYPE8 of inst : label is "2'b00";
  attribute C_TX_DELAY_TYPE9 : string;
  attribute C_TX_DELAY_TYPE9 of inst : label is "2'b00";
  attribute C_TX_DELAY_VALUE : string;
  attribute C_TX_DELAY_VALUE of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE0 : string;
  attribute C_TX_DELAY_VALUE0 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE1 : string;
  attribute C_TX_DELAY_VALUE1 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE10 : string;
  attribute C_TX_DELAY_VALUE10 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE11 : string;
  attribute C_TX_DELAY_VALUE11 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE12 : string;
  attribute C_TX_DELAY_VALUE12 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE13 : string;
  attribute C_TX_DELAY_VALUE13 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE14 : string;
  attribute C_TX_DELAY_VALUE14 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE15 : string;
  attribute C_TX_DELAY_VALUE15 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE16 : string;
  attribute C_TX_DELAY_VALUE16 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE17 : string;
  attribute C_TX_DELAY_VALUE17 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE18 : string;
  attribute C_TX_DELAY_VALUE18 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE19 : string;
  attribute C_TX_DELAY_VALUE19 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE2 : string;
  attribute C_TX_DELAY_VALUE2 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE20 : string;
  attribute C_TX_DELAY_VALUE20 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE21 : string;
  attribute C_TX_DELAY_VALUE21 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE22 : string;
  attribute C_TX_DELAY_VALUE22 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE23 : string;
  attribute C_TX_DELAY_VALUE23 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE24 : string;
  attribute C_TX_DELAY_VALUE24 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE25 : string;
  attribute C_TX_DELAY_VALUE25 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE26 : string;
  attribute C_TX_DELAY_VALUE26 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE27 : string;
  attribute C_TX_DELAY_VALUE27 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE28 : string;
  attribute C_TX_DELAY_VALUE28 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE29 : string;
  attribute C_TX_DELAY_VALUE29 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE3 : string;
  attribute C_TX_DELAY_VALUE3 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE30 : string;
  attribute C_TX_DELAY_VALUE30 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE31 : string;
  attribute C_TX_DELAY_VALUE31 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE32 : string;
  attribute C_TX_DELAY_VALUE32 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE33 : string;
  attribute C_TX_DELAY_VALUE33 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE34 : string;
  attribute C_TX_DELAY_VALUE34 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE35 : string;
  attribute C_TX_DELAY_VALUE35 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE36 : string;
  attribute C_TX_DELAY_VALUE36 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE37 : string;
  attribute C_TX_DELAY_VALUE37 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE38 : string;
  attribute C_TX_DELAY_VALUE38 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE39 : string;
  attribute C_TX_DELAY_VALUE39 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE4 : string;
  attribute C_TX_DELAY_VALUE4 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE40 : string;
  attribute C_TX_DELAY_VALUE40 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE41 : string;
  attribute C_TX_DELAY_VALUE41 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE42 : string;
  attribute C_TX_DELAY_VALUE42 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE43 : string;
  attribute C_TX_DELAY_VALUE43 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE44 : string;
  attribute C_TX_DELAY_VALUE44 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE45 : string;
  attribute C_TX_DELAY_VALUE45 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE46 : string;
  attribute C_TX_DELAY_VALUE46 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE47 : string;
  attribute C_TX_DELAY_VALUE47 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE48 : string;
  attribute C_TX_DELAY_VALUE48 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE49 : string;
  attribute C_TX_DELAY_VALUE49 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE5 : string;
  attribute C_TX_DELAY_VALUE5 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE50 : string;
  attribute C_TX_DELAY_VALUE50 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE51 : string;
  attribute C_TX_DELAY_VALUE51 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE6 : string;
  attribute C_TX_DELAY_VALUE6 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE7 : string;
  attribute C_TX_DELAY_VALUE7 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE8 : string;
  attribute C_TX_DELAY_VALUE8 of inst : label is "12'b000000000000";
  attribute C_TX_DELAY_VALUE9 : string;
  attribute C_TX_DELAY_VALUE9 of inst : label is "12'b000000000000";
  attribute C_TX_DRIVE_D : string;
  attribute C_TX_DRIVE_D of inst : label is "NONE";
  attribute C_TX_DRIVE_S : string;
  attribute C_TX_DRIVE_S of inst : label is "NONE";
  attribute C_TX_IS_CLK_INVERTED : string;
  attribute C_TX_IS_CLK_INVERTED of inst : label is "1'b0";
  attribute C_TX_IS_RST_DLY_INVERTED : string;
  attribute C_TX_IS_RST_DLY_INVERTED of inst : label is "1'b0";
  attribute C_TX_IS_RST_INVERTED : string;
  attribute C_TX_IS_RST_INVERTED of inst : label is "1'b0";
  attribute C_TX_NATIVE_ODELAY_BYPASS : string;
  attribute C_TX_NATIVE_ODELAY_BYPASS of inst : label is "FALSE";
  attribute C_TX_PRE_EMPHASIS_D : string;
  attribute C_TX_PRE_EMPHASIS_D of inst : label is "NONE";
  attribute C_TX_PRE_EMPHASIS_S : string;
  attribute C_TX_PRE_EMPHASIS_S of inst : label is "NONE";
  attribute C_TX_REFCLK_FREQ : string;
  attribute C_TX_REFCLK_FREQ of inst : label is "1500.000000";
  attribute C_TX_SLEW_D : string;
  attribute C_TX_SLEW_D of inst : label is "NONE";
  attribute C_TX_SLEW_S : string;
  attribute C_TX_SLEW_S of inst : label is "NONE";
  attribute C_TX_TRI_DELAY_FORMAT : string;
  attribute C_TX_TRI_DELAY_FORMAT of inst : label is "TIME";
  attribute C_TX_TRI_INIT : string;
  attribute C_TX_TRI_INIT of inst : label is "1'b1";
  attribute C_TX_TRI_IS_CLK_INVERTED : string;
  attribute C_TX_TRI_IS_CLK_INVERTED of inst : label is "1'b0";
  attribute C_TX_TRI_IS_RST_DLY_INVERTED : string;
  attribute C_TX_TRI_IS_RST_DLY_INVERTED of inst : label is "1'b0";
  attribute C_TX_TRI_IS_RST_INVERTED : string;
  attribute C_TX_TRI_IS_RST_INVERTED of inst : label is "1'b0";
  attribute C_TX_TRI_NATIVE_ODELAY_BYPASS : string;
  attribute C_TX_TRI_NATIVE_ODELAY_BYPASS of inst : label is "FALSE";
  attribute C_TX_TRI_OUTPUT_PHASE_90 : string;
  attribute C_TX_TRI_OUTPUT_PHASE_90 of inst : label is "FALSE";
  attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
  attribute TX_BITSLICE_TRI_EN : string;
  attribute TX_BITSLICE_TRI_EN of inst : label is "8'b00000000";
  attribute x_interface_info : string;
  attribute x_interface_info of clk : signal is "xilinx.com:signal:clock:1.0 clock_CLK CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clk : signal is "slave";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clk : signal is "XIL_INTERFACENAME clock_CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
  attribute x_interface_info of clk_rxn : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_data_rx:1.0 xiphy_rx_pins pin1";
  attribute x_interface_info of clk_rxp : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_data_rx:1.0 xiphy_rx_pins pin0";
  attribute x_interface_mode of clk_rxp : signal is "slave";
  attribute x_interface_info of data_rxn0 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_data_rx:1.0 xiphy_rx_pins pin3";
  attribute x_interface_info of data_rxn1 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_data_rx:1.0 xiphy_rx_pins pin5";
  attribute x_interface_info of data_rxn2 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_data_rx:1.0 xiphy_rx_pins pin7";
  attribute x_interface_info of data_rxn3 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_data_rx:1.0 xiphy_rx_pins pin9";
  attribute x_interface_info of data_rxp0 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_data_rx:1.0 xiphy_rx_pins pin2";
  attribute x_interface_info of data_rxp1 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_data_rx:1.0 xiphy_rx_pins pin4";
  attribute x_interface_info of data_rxp2 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_data_rx:1.0 xiphy_rx_pins pin6";
  attribute x_interface_info of data_rxp3 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_data_rx:1.0 xiphy_rx_pins pin8";
  attribute x_interface_info of dly_rdy_bsc0 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL dly_rdy_bsc0";
  attribute x_interface_info of dly_rdy_bsc1 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL dly_rdy_bsc1";
  attribute x_interface_info of en_vtc_bsc0 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL en_vtc_bsc0";
  attribute x_interface_info of en_vtc_bsc1 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL en_vtc_bsc1";
  attribute x_interface_info of fifo_empty_0 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_empty_0";
  attribute x_interface_info of fifo_empty_1 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_empty_1";
  attribute x_interface_info of fifo_empty_2 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_empty_2";
  attribute x_interface_info of fifo_empty_3 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_empty_3";
  attribute x_interface_info of fifo_empty_4 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_empty_4";
  attribute x_interface_info of fifo_empty_5 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_empty_5";
  attribute x_interface_info of fifo_empty_6 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_empty_6";
  attribute x_interface_info of fifo_empty_7 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_empty_7";
  attribute x_interface_info of fifo_empty_8 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_empty_8";
  attribute x_interface_info of fifo_empty_9 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_empty_9";
  attribute x_interface_info of fifo_rd_clk_0 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_clk_0";
  attribute x_interface_mode of fifo_rd_clk_0 : signal is "master";
  attribute x_interface_info of fifo_rd_clk_1 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_clk_1";
  attribute x_interface_info of fifo_rd_clk_2 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_clk_2";
  attribute x_interface_info of fifo_rd_clk_3 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_clk_3";
  attribute x_interface_info of fifo_rd_clk_4 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_clk_4";
  attribute x_interface_info of fifo_rd_clk_5 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_clk_5";
  attribute x_interface_info of fifo_rd_clk_6 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_clk_6";
  attribute x_interface_info of fifo_rd_clk_7 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_clk_7";
  attribute x_interface_info of fifo_rd_clk_8 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_clk_8";
  attribute x_interface_info of fifo_rd_clk_9 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_clk_9";
  attribute x_interface_info of fifo_rd_en_0 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_en_0";
  attribute x_interface_info of fifo_rd_en_1 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_en_1";
  attribute x_interface_info of fifo_rd_en_2 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_en_2";
  attribute x_interface_info of fifo_rd_en_3 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_en_3";
  attribute x_interface_info of fifo_rd_en_4 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_en_4";
  attribute x_interface_info of fifo_rd_en_5 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_en_5";
  attribute x_interface_info of fifo_rd_en_6 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_en_6";
  attribute x_interface_info of fifo_rd_en_7 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_en_7";
  attribute x_interface_info of fifo_rd_en_8 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_en_8";
  attribute x_interface_info of fifo_rd_en_9 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_rd_en_9";
  attribute x_interface_info of fifo_wr_clk_0 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL fifo_wr_clk_0";
  attribute x_interface_info of pll0_clkout0 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL pll0_clkout0";
  attribute x_interface_info of pll0_locked : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL pll0_locked";
  attribute x_interface_info of riu_clk : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL riu_clk";
  attribute x_interface_info of rst : signal is "xilinx.com:signal:reset:1.0 reset_rst RST";
  attribute x_interface_mode of rst : signal is "slave";
  attribute x_interface_parameter of rst : signal is "XIL_INTERFACENAME reset_rst, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
  attribute x_interface_info of rst_seq_done : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL rst_seq_done";
  attribute x_interface_info of vtc_rdy_bsc0 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL vtc_rdy_bsc0";
  attribute x_interface_info of vtc_rdy_bsc1 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ctrl:1.0 HSSIO_CTRL vtc_rdy_bsc1";
  attribute x_interface_info of data_to_fabric_clk_rxn : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ip_to_pins:1.0 data_to_fabric ip_to_pins_1";
  attribute x_interface_info of data_to_fabric_clk_rxp : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ip_to_pins:1.0 data_to_fabric ip_to_pins_0";
  attribute x_interface_mode of data_to_fabric_clk_rxp : signal is "master";
  attribute x_interface_info of data_to_fabric_data_rxn0 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ip_to_pins:1.0 data_to_fabric ip_to_pins_3";
  attribute x_interface_info of data_to_fabric_data_rxn1 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ip_to_pins:1.0 data_to_fabric ip_to_pins_5";
  attribute x_interface_info of data_to_fabric_data_rxn2 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ip_to_pins:1.0 data_to_fabric ip_to_pins_7";
  attribute x_interface_info of data_to_fabric_data_rxn3 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ip_to_pins:1.0 data_to_fabric ip_to_pins_9";
  attribute x_interface_info of data_to_fabric_data_rxp0 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ip_to_pins:1.0 data_to_fabric ip_to_pins_2";
  attribute x_interface_info of data_to_fabric_data_rxp1 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ip_to_pins:1.0 data_to_fabric ip_to_pins_4";
  attribute x_interface_info of data_to_fabric_data_rxp2 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ip_to_pins:1.0 data_to_fabric ip_to_pins_6";
  attribute x_interface_info of data_to_fabric_data_rxp3 : signal is "xilinx.com:display_high_speed_selectio_wiz:hssio_ip_to_pins:1.0 data_to_fabric ip_to_pins_8";
begin
  data_to_fabric_clk_rxn(7) <= \<const0>\;
  data_to_fabric_clk_rxn(6) <= \<const0>\;
  data_to_fabric_clk_rxn(5) <= \<const0>\;
  data_to_fabric_clk_rxn(4) <= \<const0>\;
  data_to_fabric_clk_rxn(3) <= \<const0>\;
  data_to_fabric_clk_rxn(2) <= \<const0>\;
  data_to_fabric_clk_rxn(1) <= \<const0>\;
  data_to_fabric_clk_rxn(0) <= \<const0>\;
  data_to_fabric_clk_rxp(7) <= \<const0>\;
  data_to_fabric_clk_rxp(6) <= \<const0>\;
  data_to_fabric_clk_rxp(5) <= \<const0>\;
  data_to_fabric_clk_rxp(4) <= \<const0>\;
  data_to_fabric_clk_rxp(3) <= \<const0>\;
  data_to_fabric_clk_rxp(2) <= \<const0>\;
  data_to_fabric_clk_rxp(1) <= \<const0>\;
  data_to_fabric_clk_rxp(0) <= \<const0>\;
  data_to_fabric_data_rxn0(7) <= \<const0>\;
  data_to_fabric_data_rxn0(6) <= \<const0>\;
  data_to_fabric_data_rxn0(5) <= \<const0>\;
  data_to_fabric_data_rxn0(4) <= \<const0>\;
  data_to_fabric_data_rxn0(3) <= \<const0>\;
  data_to_fabric_data_rxn0(2) <= \<const0>\;
  data_to_fabric_data_rxn0(1) <= \<const0>\;
  data_to_fabric_data_rxn0(0) <= \<const0>\;
  data_to_fabric_data_rxn1(7) <= \<const0>\;
  data_to_fabric_data_rxn1(6) <= \<const0>\;
  data_to_fabric_data_rxn1(5) <= \<const0>\;
  data_to_fabric_data_rxn1(4) <= \<const0>\;
  data_to_fabric_data_rxn1(3) <= \<const0>\;
  data_to_fabric_data_rxn1(2) <= \<const0>\;
  data_to_fabric_data_rxn1(1) <= \<const0>\;
  data_to_fabric_data_rxn1(0) <= \<const0>\;
  data_to_fabric_data_rxn2(7) <= \<const0>\;
  data_to_fabric_data_rxn2(6) <= \<const0>\;
  data_to_fabric_data_rxn2(5) <= \<const0>\;
  data_to_fabric_data_rxn2(4) <= \<const0>\;
  data_to_fabric_data_rxn2(3) <= \<const0>\;
  data_to_fabric_data_rxn2(2) <= \<const0>\;
  data_to_fabric_data_rxn2(1) <= \<const0>\;
  data_to_fabric_data_rxn2(0) <= \<const0>\;
  data_to_fabric_data_rxn3(7) <= \<const0>\;
  data_to_fabric_data_rxn3(6) <= \<const0>\;
  data_to_fabric_data_rxn3(5) <= \<const0>\;
  data_to_fabric_data_rxn3(4) <= \<const0>\;
  data_to_fabric_data_rxn3(3) <= \<const0>\;
  data_to_fabric_data_rxn3(2) <= \<const0>\;
  data_to_fabric_data_rxn3(1) <= \<const0>\;
  data_to_fabric_data_rxn3(0) <= \<const0>\;
  dly_rdy_bsc0 <= \<const0>\;
  dly_rdy_bsc1 <= \<const0>\;
  fifo_empty_0 <= \<const0>\;
  fifo_empty_1 <= \<const0>\;
  fifo_empty_3 <= \<const0>\;
  fifo_empty_5 <= \<const0>\;
  fifo_empty_7 <= \<const0>\;
  fifo_empty_9 <= \<const0>\;
  pll0_clkout0 <= \<const0>\;
  pll0_locked <= \<const0>\;
  shared_pll0_clkoutphy_out <= \<const0>\;
  vtc_rdy_bsc0 <= \<const0>\;
  vtc_rdy_bsc1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
inst: entity work.design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10
     port map (
      app_clk => '0',
      bg0_pin0_nc => '0',
      bg0_pin6_nc => '0',
      bg1_pin0_nc => '0',
      bg1_pin6_nc => '0',
      bg2_pin0_nc => '0',
      bg2_pin6_nc => '0',
      bg3_pin0_nc => '0',
      bg3_pin6_nc => '0',
      bidir_rx_clk => '0',
      bidir_tx_bs_tri_ce0 => '0',
      bidir_tx_bs_tri_ce1 => '0',
      bidir_tx_bs_tri_ce2 => '0',
      bidir_tx_bs_tri_ce3 => '0',
      bidir_tx_bs_tri_ce4 => '0',
      bidir_tx_bs_tri_ce5 => '0',
      bidir_tx_bs_tri_ce6 => '0',
      bidir_tx_bs_tri_ce7 => '0',
      bidir_tx_bs_tri_clk => '0',
      bidir_tx_bs_tri_cntvaluein0(8 downto 0) => B"000000000",
      bidir_tx_bs_tri_cntvaluein1(8 downto 0) => B"000000000",
      bidir_tx_bs_tri_cntvaluein2(8 downto 0) => B"000000000",
      bidir_tx_bs_tri_cntvaluein3(8 downto 0) => B"000000000",
      bidir_tx_bs_tri_cntvaluein4(8 downto 0) => B"000000000",
      bidir_tx_bs_tri_cntvaluein5(8 downto 0) => B"000000000",
      bidir_tx_bs_tri_cntvaluein6(8 downto 0) => B"000000000",
      bidir_tx_bs_tri_cntvaluein7(8 downto 0) => B"000000000",
      bidir_tx_bs_tri_cntvalueout0(8 downto 0) => NLW_inst_bidir_tx_bs_tri_cntvalueout0_UNCONNECTED(8 downto 0),
      bidir_tx_bs_tri_cntvalueout1(8 downto 0) => NLW_inst_bidir_tx_bs_tri_cntvalueout1_UNCONNECTED(8 downto 0),
      bidir_tx_bs_tri_cntvalueout2(8 downto 0) => NLW_inst_bidir_tx_bs_tri_cntvalueout2_UNCONNECTED(8 downto 0),
      bidir_tx_bs_tri_cntvalueout3(8 downto 0) => NLW_inst_bidir_tx_bs_tri_cntvalueout3_UNCONNECTED(8 downto 0),
      bidir_tx_bs_tri_cntvalueout4(8 downto 0) => NLW_inst_bidir_tx_bs_tri_cntvalueout4_UNCONNECTED(8 downto 0),
      bidir_tx_bs_tri_cntvalueout5(8 downto 0) => NLW_inst_bidir_tx_bs_tri_cntvalueout5_UNCONNECTED(8 downto 0),
      bidir_tx_bs_tri_cntvalueout6(8 downto 0) => NLW_inst_bidir_tx_bs_tri_cntvalueout6_UNCONNECTED(8 downto 0),
      bidir_tx_bs_tri_cntvalueout7(8 downto 0) => NLW_inst_bidir_tx_bs_tri_cntvalueout7_UNCONNECTED(8 downto 0),
      bidir_tx_bs_tri_en_vtc0 => '0',
      bidir_tx_bs_tri_en_vtc1 => '0',
      bidir_tx_bs_tri_en_vtc2 => '0',
      bidir_tx_bs_tri_en_vtc3 => '0',
      bidir_tx_bs_tri_en_vtc4 => '0',
      bidir_tx_bs_tri_en_vtc5 => '0',
      bidir_tx_bs_tri_en_vtc6 => '0',
      bidir_tx_bs_tri_en_vtc7 => '0',
      bidir_tx_bs_tri_inc0 => '0',
      bidir_tx_bs_tri_inc1 => '0',
      bidir_tx_bs_tri_inc2 => '0',
      bidir_tx_bs_tri_inc3 => '0',
      bidir_tx_bs_tri_inc4 => '0',
      bidir_tx_bs_tri_inc5 => '0',
      bidir_tx_bs_tri_inc6 => '0',
      bidir_tx_bs_tri_inc7 => '0',
      bidir_tx_bs_tri_load0 => '0',
      bidir_tx_bs_tri_load1 => '0',
      bidir_tx_bs_tri_load2 => '0',
      bidir_tx_bs_tri_load3 => '0',
      bidir_tx_bs_tri_load4 => '0',
      bidir_tx_bs_tri_load5 => '0',
      bidir_tx_bs_tri_load6 => '0',
      bidir_tx_bs_tri_load7 => '0',
      bidir_tx_clk => '0',
      bitslip_error_0 => NLW_inst_bitslip_error_0_UNCONNECTED,
      bitslip_error_1 => NLW_inst_bitslip_error_1_UNCONNECTED,
      bitslip_error_10 => NLW_inst_bitslip_error_10_UNCONNECTED,
      bitslip_error_11 => NLW_inst_bitslip_error_11_UNCONNECTED,
      bitslip_error_12 => NLW_inst_bitslip_error_12_UNCONNECTED,
      bitslip_error_13 => NLW_inst_bitslip_error_13_UNCONNECTED,
      bitslip_error_14 => NLW_inst_bitslip_error_14_UNCONNECTED,
      bitslip_error_15 => NLW_inst_bitslip_error_15_UNCONNECTED,
      bitslip_error_16 => NLW_inst_bitslip_error_16_UNCONNECTED,
      bitslip_error_17 => NLW_inst_bitslip_error_17_UNCONNECTED,
      bitslip_error_18 => NLW_inst_bitslip_error_18_UNCONNECTED,
      bitslip_error_19 => NLW_inst_bitslip_error_19_UNCONNECTED,
      bitslip_error_2 => NLW_inst_bitslip_error_2_UNCONNECTED,
      bitslip_error_20 => NLW_inst_bitslip_error_20_UNCONNECTED,
      bitslip_error_21 => NLW_inst_bitslip_error_21_UNCONNECTED,
      bitslip_error_22 => NLW_inst_bitslip_error_22_UNCONNECTED,
      bitslip_error_23 => NLW_inst_bitslip_error_23_UNCONNECTED,
      bitslip_error_24 => NLW_inst_bitslip_error_24_UNCONNECTED,
      bitslip_error_25 => NLW_inst_bitslip_error_25_UNCONNECTED,
      bitslip_error_26 => NLW_inst_bitslip_error_26_UNCONNECTED,
      bitslip_error_27 => NLW_inst_bitslip_error_27_UNCONNECTED,
      bitslip_error_28 => NLW_inst_bitslip_error_28_UNCONNECTED,
      bitslip_error_29 => NLW_inst_bitslip_error_29_UNCONNECTED,
      bitslip_error_3 => NLW_inst_bitslip_error_3_UNCONNECTED,
      bitslip_error_30 => NLW_inst_bitslip_error_30_UNCONNECTED,
      bitslip_error_31 => NLW_inst_bitslip_error_31_UNCONNECTED,
      bitslip_error_32 => NLW_inst_bitslip_error_32_UNCONNECTED,
      bitslip_error_33 => NLW_inst_bitslip_error_33_UNCONNECTED,
      bitslip_error_34 => NLW_inst_bitslip_error_34_UNCONNECTED,
      bitslip_error_35 => NLW_inst_bitslip_error_35_UNCONNECTED,
      bitslip_error_36 => NLW_inst_bitslip_error_36_UNCONNECTED,
      bitslip_error_37 => NLW_inst_bitslip_error_37_UNCONNECTED,
      bitslip_error_38 => NLW_inst_bitslip_error_38_UNCONNECTED,
      bitslip_error_39 => NLW_inst_bitslip_error_39_UNCONNECTED,
      bitslip_error_4 => NLW_inst_bitslip_error_4_UNCONNECTED,
      bitslip_error_40 => NLW_inst_bitslip_error_40_UNCONNECTED,
      bitslip_error_41 => NLW_inst_bitslip_error_41_UNCONNECTED,
      bitslip_error_42 => NLW_inst_bitslip_error_42_UNCONNECTED,
      bitslip_error_43 => NLW_inst_bitslip_error_43_UNCONNECTED,
      bitslip_error_44 => NLW_inst_bitslip_error_44_UNCONNECTED,
      bitslip_error_45 => NLW_inst_bitslip_error_45_UNCONNECTED,
      bitslip_error_46 => NLW_inst_bitslip_error_46_UNCONNECTED,
      bitslip_error_47 => NLW_inst_bitslip_error_47_UNCONNECTED,
      bitslip_error_48 => NLW_inst_bitslip_error_48_UNCONNECTED,
      bitslip_error_49 => NLW_inst_bitslip_error_49_UNCONNECTED,
      bitslip_error_5 => NLW_inst_bitslip_error_5_UNCONNECTED,
      bitslip_error_50 => NLW_inst_bitslip_error_50_UNCONNECTED,
      bitslip_error_51 => NLW_inst_bitslip_error_51_UNCONNECTED,
      bitslip_error_6 => NLW_inst_bitslip_error_6_UNCONNECTED,
      bitslip_error_7 => NLW_inst_bitslip_error_7_UNCONNECTED,
      bitslip_error_8 => NLW_inst_bitslip_error_8_UNCONNECTED,
      bitslip_error_9 => NLW_inst_bitslip_error_9_UNCONNECTED,
      bs_rst_dphy_in => bs_rst_dphy_in,
      clk => '0',
      clk_from_ibuf => NLW_inst_clk_from_ibuf_UNCONNECTED,
      clk_n => '0',
      clk_p => '0',
      clk_rxn => clk_rxn,
      clk_rxp => clk_rxp,
      daddr(6 downto 0) => B"0000000",
      data_rxn0 => data_rxn0,
      data_rxn1 => data_rxn1,
      data_rxn2 => data_rxn2,
      data_rxn3 => data_rxn3,
      data_rxp0 => data_rxp0,
      data_rxp1 => data_rxp1,
      data_rxp2 => data_rxp2,
      data_rxp3 => data_rxp3,
      data_to_fabric_clk_rxn(7 downto 0) => NLW_inst_data_to_fabric_clk_rxn_UNCONNECTED(7 downto 0),
      data_to_fabric_clk_rxp(7 downto 0) => NLW_inst_data_to_fabric_clk_rxp_UNCONNECTED(7 downto 0),
      data_to_fabric_data_rxn0(7 downto 0) => NLW_inst_data_to_fabric_data_rxn0_UNCONNECTED(7 downto 0),
      data_to_fabric_data_rxn1(7 downto 0) => NLW_inst_data_to_fabric_data_rxn1_UNCONNECTED(7 downto 0),
      data_to_fabric_data_rxn2(7 downto 0) => NLW_inst_data_to_fabric_data_rxn2_UNCONNECTED(7 downto 0),
      data_to_fabric_data_rxn3(7 downto 0) => NLW_inst_data_to_fabric_data_rxn3_UNCONNECTED(7 downto 0),
      data_to_fabric_data_rxp0(7 downto 0) => data_to_fabric_data_rxp0(7 downto 0),
      data_to_fabric_data_rxp1(7 downto 0) => data_to_fabric_data_rxp1(7 downto 0),
      data_to_fabric_data_rxp2(7 downto 0) => data_to_fabric_data_rxp2(7 downto 0),
      data_to_fabric_data_rxp3(7 downto 0) => data_to_fabric_data_rxp3(7 downto 0),
      dclk => '0',
      den => '0',
      di(15 downto 0) => B"0000000000000000",
      dly_rdy_bsc0 => NLW_inst_dly_rdy_bsc0_UNCONNECTED,
      dly_rdy_bsc1 => NLW_inst_dly_rdy_bsc1_UNCONNECTED,
      dly_rdy_bsc2 => NLW_inst_dly_rdy_bsc2_UNCONNECTED,
      dly_rdy_bsc3 => NLW_inst_dly_rdy_bsc3_UNCONNECTED,
      dly_rdy_bsc4 => NLW_inst_dly_rdy_bsc4_UNCONNECTED,
      dly_rdy_bsc5 => NLW_inst_dly_rdy_bsc5_UNCONNECTED,
      dly_rdy_bsc6 => NLW_inst_dly_rdy_bsc6_UNCONNECTED,
      dly_rdy_bsc7 => NLW_inst_dly_rdy_bsc7_UNCONNECTED,
      do_out(15 downto 0) => NLW_inst_do_out_UNCONNECTED(15 downto 0),
      drdy => NLW_inst_drdy_UNCONNECTED,
      dwe => '0',
      en_vtc_bsc0 => '1',
      en_vtc_bsc1 => '1',
      en_vtc_bsc2 => '0',
      en_vtc_bsc3 => '0',
      en_vtc_bsc4 => '0',
      en_vtc_bsc5 => '0',
      en_vtc_bsc6 => '0',
      en_vtc_bsc7 => '0',
      fifo_empty_0 => NLW_inst_fifo_empty_0_UNCONNECTED,
      fifo_empty_1 => NLW_inst_fifo_empty_1_UNCONNECTED,
      fifo_empty_10 => NLW_inst_fifo_empty_10_UNCONNECTED,
      fifo_empty_11 => NLW_inst_fifo_empty_11_UNCONNECTED,
      fifo_empty_12 => NLW_inst_fifo_empty_12_UNCONNECTED,
      fifo_empty_13 => NLW_inst_fifo_empty_13_UNCONNECTED,
      fifo_empty_14 => NLW_inst_fifo_empty_14_UNCONNECTED,
      fifo_empty_15 => NLW_inst_fifo_empty_15_UNCONNECTED,
      fifo_empty_16 => NLW_inst_fifo_empty_16_UNCONNECTED,
      fifo_empty_17 => NLW_inst_fifo_empty_17_UNCONNECTED,
      fifo_empty_18 => NLW_inst_fifo_empty_18_UNCONNECTED,
      fifo_empty_19 => NLW_inst_fifo_empty_19_UNCONNECTED,
      fifo_empty_2 => fifo_empty_2,
      fifo_empty_20 => NLW_inst_fifo_empty_20_UNCONNECTED,
      fifo_empty_21 => NLW_inst_fifo_empty_21_UNCONNECTED,
      fifo_empty_22 => NLW_inst_fifo_empty_22_UNCONNECTED,
      fifo_empty_23 => NLW_inst_fifo_empty_23_UNCONNECTED,
      fifo_empty_24 => NLW_inst_fifo_empty_24_UNCONNECTED,
      fifo_empty_25 => NLW_inst_fifo_empty_25_UNCONNECTED,
      fifo_empty_26 => NLW_inst_fifo_empty_26_UNCONNECTED,
      fifo_empty_27 => NLW_inst_fifo_empty_27_UNCONNECTED,
      fifo_empty_28 => NLW_inst_fifo_empty_28_UNCONNECTED,
      fifo_empty_29 => NLW_inst_fifo_empty_29_UNCONNECTED,
      fifo_empty_3 => NLW_inst_fifo_empty_3_UNCONNECTED,
      fifo_empty_30 => NLW_inst_fifo_empty_30_UNCONNECTED,
      fifo_empty_31 => NLW_inst_fifo_empty_31_UNCONNECTED,
      fifo_empty_32 => NLW_inst_fifo_empty_32_UNCONNECTED,
      fifo_empty_33 => NLW_inst_fifo_empty_33_UNCONNECTED,
      fifo_empty_34 => NLW_inst_fifo_empty_34_UNCONNECTED,
      fifo_empty_35 => NLW_inst_fifo_empty_35_UNCONNECTED,
      fifo_empty_36 => NLW_inst_fifo_empty_36_UNCONNECTED,
      fifo_empty_37 => NLW_inst_fifo_empty_37_UNCONNECTED,
      fifo_empty_38 => NLW_inst_fifo_empty_38_UNCONNECTED,
      fifo_empty_39 => NLW_inst_fifo_empty_39_UNCONNECTED,
      fifo_empty_4 => fifo_empty_4,
      fifo_empty_40 => NLW_inst_fifo_empty_40_UNCONNECTED,
      fifo_empty_41 => NLW_inst_fifo_empty_41_UNCONNECTED,
      fifo_empty_42 => NLW_inst_fifo_empty_42_UNCONNECTED,
      fifo_empty_43 => NLW_inst_fifo_empty_43_UNCONNECTED,
      fifo_empty_44 => NLW_inst_fifo_empty_44_UNCONNECTED,
      fifo_empty_45 => NLW_inst_fifo_empty_45_UNCONNECTED,
      fifo_empty_46 => NLW_inst_fifo_empty_46_UNCONNECTED,
      fifo_empty_47 => NLW_inst_fifo_empty_47_UNCONNECTED,
      fifo_empty_48 => NLW_inst_fifo_empty_48_UNCONNECTED,
      fifo_empty_49 => NLW_inst_fifo_empty_49_UNCONNECTED,
      fifo_empty_5 => NLW_inst_fifo_empty_5_UNCONNECTED,
      fifo_empty_50 => NLW_inst_fifo_empty_50_UNCONNECTED,
      fifo_empty_51 => NLW_inst_fifo_empty_51_UNCONNECTED,
      fifo_empty_6 => fifo_empty_6,
      fifo_empty_7 => NLW_inst_fifo_empty_7_UNCONNECTED,
      fifo_empty_8 => fifo_empty_8,
      fifo_empty_9 => NLW_inst_fifo_empty_9_UNCONNECTED,
      fifo_rd_clk_0 => fifo_rd_clk_0,
      fifo_rd_clk_1 => '0',
      fifo_rd_clk_10 => '0',
      fifo_rd_clk_11 => '0',
      fifo_rd_clk_12 => '0',
      fifo_rd_clk_13 => '0',
      fifo_rd_clk_14 => '0',
      fifo_rd_clk_15 => '0',
      fifo_rd_clk_16 => '0',
      fifo_rd_clk_17 => '0',
      fifo_rd_clk_18 => '0',
      fifo_rd_clk_19 => '0',
      fifo_rd_clk_2 => '0',
      fifo_rd_clk_20 => '0',
      fifo_rd_clk_21 => '0',
      fifo_rd_clk_22 => '0',
      fifo_rd_clk_23 => '0',
      fifo_rd_clk_24 => '0',
      fifo_rd_clk_25 => '0',
      fifo_rd_clk_26 => '0',
      fifo_rd_clk_27 => '0',
      fifo_rd_clk_28 => '0',
      fifo_rd_clk_29 => '0',
      fifo_rd_clk_3 => '0',
      fifo_rd_clk_30 => '0',
      fifo_rd_clk_31 => '0',
      fifo_rd_clk_32 => '0',
      fifo_rd_clk_33 => '0',
      fifo_rd_clk_34 => '0',
      fifo_rd_clk_35 => '0',
      fifo_rd_clk_36 => '0',
      fifo_rd_clk_37 => '0',
      fifo_rd_clk_38 => '0',
      fifo_rd_clk_39 => '0',
      fifo_rd_clk_4 => '0',
      fifo_rd_clk_40 => '0',
      fifo_rd_clk_41 => '0',
      fifo_rd_clk_42 => '0',
      fifo_rd_clk_43 => '0',
      fifo_rd_clk_44 => '0',
      fifo_rd_clk_45 => '0',
      fifo_rd_clk_46 => '0',
      fifo_rd_clk_47 => '0',
      fifo_rd_clk_48 => '0',
      fifo_rd_clk_49 => '0',
      fifo_rd_clk_5 => '0',
      fifo_rd_clk_50 => '0',
      fifo_rd_clk_51 => '0',
      fifo_rd_clk_6 => '0',
      fifo_rd_clk_7 => '0',
      fifo_rd_clk_8 => '0',
      fifo_rd_clk_9 => '0',
      fifo_rd_data_valid => NLW_inst_fifo_rd_data_valid_UNCONNECTED,
      fifo_rd_en_0 => '1',
      fifo_rd_en_1 => '0',
      fifo_rd_en_10 => '0',
      fifo_rd_en_11 => '0',
      fifo_rd_en_12 => '0',
      fifo_rd_en_13 => '0',
      fifo_rd_en_14 => '0',
      fifo_rd_en_15 => '0',
      fifo_rd_en_16 => '0',
      fifo_rd_en_17 => '0',
      fifo_rd_en_18 => '0',
      fifo_rd_en_19 => '0',
      fifo_rd_en_2 => fifo_rd_en_2,
      fifo_rd_en_20 => '0',
      fifo_rd_en_21 => '0',
      fifo_rd_en_22 => '0',
      fifo_rd_en_23 => '0',
      fifo_rd_en_24 => '0',
      fifo_rd_en_25 => '0',
      fifo_rd_en_26 => '0',
      fifo_rd_en_27 => '0',
      fifo_rd_en_28 => '0',
      fifo_rd_en_29 => '0',
      fifo_rd_en_3 => '0',
      fifo_rd_en_30 => '0',
      fifo_rd_en_31 => '0',
      fifo_rd_en_32 => '0',
      fifo_rd_en_33 => '0',
      fifo_rd_en_34 => '0',
      fifo_rd_en_35 => '0',
      fifo_rd_en_36 => '0',
      fifo_rd_en_37 => '0',
      fifo_rd_en_38 => '0',
      fifo_rd_en_39 => '0',
      fifo_rd_en_4 => fifo_rd_en_4,
      fifo_rd_en_40 => '0',
      fifo_rd_en_41 => '0',
      fifo_rd_en_42 => '0',
      fifo_rd_en_43 => '0',
      fifo_rd_en_44 => '0',
      fifo_rd_en_45 => '0',
      fifo_rd_en_46 => '0',
      fifo_rd_en_47 => '0',
      fifo_rd_en_48 => '0',
      fifo_rd_en_49 => '0',
      fifo_rd_en_5 => '0',
      fifo_rd_en_50 => '0',
      fifo_rd_en_51 => '0',
      fifo_rd_en_6 => fifo_rd_en_6,
      fifo_rd_en_7 => '0',
      fifo_rd_en_8 => fifo_rd_en_8,
      fifo_rd_en_9 => '0',
      fifo_wr_clk_0 => fifo_wr_clk_0,
      fifo_wr_clk_13 => NLW_inst_fifo_wr_clk_13_UNCONNECTED,
      fifo_wr_clk_19 => NLW_inst_fifo_wr_clk_19_UNCONNECTED,
      fifo_wr_clk_26 => NLW_inst_fifo_wr_clk_26_UNCONNECTED,
      fifo_wr_clk_32 => NLW_inst_fifo_wr_clk_32_UNCONNECTED,
      fifo_wr_clk_39 => NLW_inst_fifo_wr_clk_39_UNCONNECTED,
      fifo_wr_clk_45 => NLW_inst_fifo_wr_clk_45_UNCONNECTED,
      fifo_wr_clk_6 => NLW_inst_fifo_wr_clk_6_UNCONNECTED,
      hs_rx_disable(4 downto 0) => hs_rx_disable(4 downto 0),
      intf_rdy => NLW_inst_intf_rdy_UNCONNECTED,
      lp_rx_disable(4 downto 0) => B"00000",
      lp_rx_o_n(4 downto 0) => lp_rx_o_n(4 downto 0),
      lp_rx_o_p(4 downto 0) => lp_rx_o_p(4 downto 0),
      lptx_i_n(4 downto 0) => B"00000",
      lptx_i_p(4 downto 0) => B"00000",
      lptx_t(4 downto 0) => B"00000",
      multi_intf_lock_in => '0',
      phy_rden_bsc0(3 downto 0) => B"0000",
      phy_rden_bsc1(3 downto 0) => B"0000",
      phy_rden_bsc2(3 downto 0) => B"0000",
      phy_rden_bsc3(3 downto 0) => B"0000",
      phy_rden_bsc4(3 downto 0) => B"0000",
      phy_rden_bsc5(3 downto 0) => B"0000",
      phy_rden_bsc6(3 downto 0) => B"0000",
      phy_rden_bsc7(3 downto 0) => B"0000",
      pll0_clkout0 => NLW_inst_pll0_clkout0_UNCONNECTED,
      pll0_clkout1 => NLW_inst_pll0_clkout1_UNCONNECTED,
      pll0_locked => NLW_inst_pll0_locked_UNCONNECTED,
      pll1_clkout0 => NLW_inst_pll1_clkout0_UNCONNECTED,
      pll1_locked => NLW_inst_pll1_locked_UNCONNECTED,
      riu_addr_bg0(5 downto 0) => B"000000",
      riu_addr_bg0_bs0(5 downto 0) => B"000000",
      riu_addr_bg0_bs1(5 downto 0) => B"000000",
      riu_addr_bg1(5 downto 0) => B"000000",
      riu_addr_bg1_bs2(5 downto 0) => B"000000",
      riu_addr_bg1_bs3(5 downto 0) => B"000000",
      riu_addr_bg2(5 downto 0) => B"000000",
      riu_addr_bg2_bs4(5 downto 0) => B"000000",
      riu_addr_bg2_bs5(5 downto 0) => B"000000",
      riu_addr_bg3(5 downto 0) => B"000000",
      riu_addr_bg3_bs6(5 downto 0) => B"000000",
      riu_addr_bg3_bs7(5 downto 0) => B"000000",
      riu_clk => riu_clk,
      riu_nibble_sel_bg0(1 downto 0) => B"00",
      riu_nibble_sel_bg0_bs0 => '0',
      riu_nibble_sel_bg0_bs1 => '0',
      riu_nibble_sel_bg1(1 downto 0) => B"00",
      riu_nibble_sel_bg1_bs2 => '0',
      riu_nibble_sel_bg1_bs3 => '0',
      riu_nibble_sel_bg2(1 downto 0) => B"00",
      riu_nibble_sel_bg2_bs4 => '0',
      riu_nibble_sel_bg2_bs5 => '0',
      riu_nibble_sel_bg3(1 downto 0) => B"00",
      riu_nibble_sel_bg3_bs6 => '0',
      riu_nibble_sel_bg3_bs7 => '0',
      riu_rd_data_bg0(15 downto 0) => NLW_inst_riu_rd_data_bg0_UNCONNECTED(15 downto 0),
      riu_rd_data_bg0_bs0(15 downto 0) => NLW_inst_riu_rd_data_bg0_bs0_UNCONNECTED(15 downto 0),
      riu_rd_data_bg0_bs1(15 downto 0) => NLW_inst_riu_rd_data_bg0_bs1_UNCONNECTED(15 downto 0),
      riu_rd_data_bg1(15 downto 0) => NLW_inst_riu_rd_data_bg1_UNCONNECTED(15 downto 0),
      riu_rd_data_bg1_bs2(15 downto 0) => NLW_inst_riu_rd_data_bg1_bs2_UNCONNECTED(15 downto 0),
      riu_rd_data_bg1_bs3(15 downto 0) => NLW_inst_riu_rd_data_bg1_bs3_UNCONNECTED(15 downto 0),
      riu_rd_data_bg2(15 downto 0) => NLW_inst_riu_rd_data_bg2_UNCONNECTED(15 downto 0),
      riu_rd_data_bg2_bs4(15 downto 0) => NLW_inst_riu_rd_data_bg2_bs4_UNCONNECTED(15 downto 0),
      riu_rd_data_bg2_bs5(15 downto 0) => NLW_inst_riu_rd_data_bg2_bs5_UNCONNECTED(15 downto 0),
      riu_rd_data_bg3(15 downto 0) => NLW_inst_riu_rd_data_bg3_UNCONNECTED(15 downto 0),
      riu_rd_data_bg3_bs6(15 downto 0) => NLW_inst_riu_rd_data_bg3_bs6_UNCONNECTED(15 downto 0),
      riu_rd_data_bg3_bs7(15 downto 0) => NLW_inst_riu_rd_data_bg3_bs7_UNCONNECTED(15 downto 0),
      riu_valid_bg0 => NLW_inst_riu_valid_bg0_UNCONNECTED,
      riu_valid_bg0_bs0 => NLW_inst_riu_valid_bg0_bs0_UNCONNECTED,
      riu_valid_bg0_bs1 => NLW_inst_riu_valid_bg0_bs1_UNCONNECTED,
      riu_valid_bg1 => NLW_inst_riu_valid_bg1_UNCONNECTED,
      riu_valid_bg1_bs2 => NLW_inst_riu_valid_bg1_bs2_UNCONNECTED,
      riu_valid_bg1_bs3 => NLW_inst_riu_valid_bg1_bs3_UNCONNECTED,
      riu_valid_bg2 => NLW_inst_riu_valid_bg2_UNCONNECTED,
      riu_valid_bg2_bs4 => NLW_inst_riu_valid_bg2_bs4_UNCONNECTED,
      riu_valid_bg2_bs5 => NLW_inst_riu_valid_bg2_bs5_UNCONNECTED,
      riu_valid_bg3 => NLW_inst_riu_valid_bg3_UNCONNECTED,
      riu_valid_bg3_bs6 => NLW_inst_riu_valid_bg3_bs6_UNCONNECTED,
      riu_valid_bg3_bs7 => NLW_inst_riu_valid_bg3_bs7_UNCONNECTED,
      riu_wr_data_bg0(15 downto 0) => B"0000000000000000",
      riu_wr_data_bg0_bs0(15 downto 0) => B"0000000000000000",
      riu_wr_data_bg0_bs1(15 downto 0) => B"0000000000000000",
      riu_wr_data_bg1(15 downto 0) => B"0000000000000000",
      riu_wr_data_bg1_bs2(15 downto 0) => B"0000000000000000",
      riu_wr_data_bg1_bs3(15 downto 0) => B"0000000000000000",
      riu_wr_data_bg2(15 downto 0) => B"0000000000000000",
      riu_wr_data_bg2_bs4(15 downto 0) => B"0000000000000000",
      riu_wr_data_bg2_bs5(15 downto 0) => B"0000000000000000",
      riu_wr_data_bg3(15 downto 0) => B"0000000000000000",
      riu_wr_data_bg3_bs6(15 downto 0) => B"0000000000000000",
      riu_wr_data_bg3_bs7(15 downto 0) => B"0000000000000000",
      riu_wr_en_bg0 => '0',
      riu_wr_en_bg0_bs0 => '0',
      riu_wr_en_bg0_bs1 => '0',
      riu_wr_en_bg1 => '0',
      riu_wr_en_bg1_bs2 => '0',
      riu_wr_en_bg1_bs3 => '0',
      riu_wr_en_bg2 => '0',
      riu_wr_en_bg2_bs4 => '0',
      riu_wr_en_bg2_bs5 => '0',
      riu_wr_en_bg3 => '0',
      riu_wr_en_bg3_bs6 => '0',
      riu_wr_en_bg3_bs7 => '0',
      rst => rst,
      rst_seq_done => rst_seq_done,
      rx_bitslip_sync_done => NLW_inst_rx_bitslip_sync_done_UNCONNECTED,
      rx_ce_0 => '0',
      rx_ce_1 => '0',
      rx_ce_10 => '0',
      rx_ce_11 => '0',
      rx_ce_12 => '0',
      rx_ce_13 => '0',
      rx_ce_14 => '0',
      rx_ce_15 => '0',
      rx_ce_16 => '0',
      rx_ce_17 => '0',
      rx_ce_18 => '0',
      rx_ce_19 => '0',
      rx_ce_2 => '0',
      rx_ce_20 => '0',
      rx_ce_21 => '0',
      rx_ce_22 => '0',
      rx_ce_23 => '0',
      rx_ce_24 => '0',
      rx_ce_25 => '0',
      rx_ce_26 => '0',
      rx_ce_27 => '0',
      rx_ce_28 => '0',
      rx_ce_29 => '0',
      rx_ce_3 => '0',
      rx_ce_30 => '0',
      rx_ce_31 => '0',
      rx_ce_32 => '0',
      rx_ce_33 => '0',
      rx_ce_34 => '0',
      rx_ce_35 => '0',
      rx_ce_36 => '0',
      rx_ce_37 => '0',
      rx_ce_38 => '0',
      rx_ce_39 => '0',
      rx_ce_4 => '0',
      rx_ce_40 => '0',
      rx_ce_41 => '0',
      rx_ce_42 => '0',
      rx_ce_43 => '0',
      rx_ce_44 => '0',
      rx_ce_45 => '0',
      rx_ce_46 => '0',
      rx_ce_47 => '0',
      rx_ce_48 => '0',
      rx_ce_49 => '0',
      rx_ce_5 => '0',
      rx_ce_50 => '0',
      rx_ce_51 => '0',
      rx_ce_6 => '0',
      rx_ce_7 => '0',
      rx_ce_8 => '0',
      rx_ce_9 => '0',
      rx_ce_ext_0 => '0',
      rx_ce_ext_1 => '0',
      rx_ce_ext_10 => '0',
      rx_ce_ext_11 => '0',
      rx_ce_ext_12 => '0',
      rx_ce_ext_13 => '0',
      rx_ce_ext_14 => '0',
      rx_ce_ext_15 => '0',
      rx_ce_ext_16 => '0',
      rx_ce_ext_17 => '0',
      rx_ce_ext_18 => '0',
      rx_ce_ext_19 => '0',
      rx_ce_ext_2 => '0',
      rx_ce_ext_20 => '0',
      rx_ce_ext_21 => '0',
      rx_ce_ext_22 => '0',
      rx_ce_ext_23 => '0',
      rx_ce_ext_24 => '0',
      rx_ce_ext_25 => '0',
      rx_ce_ext_26 => '0',
      rx_ce_ext_27 => '0',
      rx_ce_ext_28 => '0',
      rx_ce_ext_29 => '0',
      rx_ce_ext_3 => '0',
      rx_ce_ext_30 => '0',
      rx_ce_ext_31 => '0',
      rx_ce_ext_32 => '0',
      rx_ce_ext_33 => '0',
      rx_ce_ext_34 => '0',
      rx_ce_ext_35 => '0',
      rx_ce_ext_36 => '0',
      rx_ce_ext_37 => '0',
      rx_ce_ext_38 => '0',
      rx_ce_ext_39 => '0',
      rx_ce_ext_4 => '0',
      rx_ce_ext_40 => '0',
      rx_ce_ext_41 => '0',
      rx_ce_ext_42 => '0',
      rx_ce_ext_43 => '0',
      rx_ce_ext_44 => '0',
      rx_ce_ext_45 => '0',
      rx_ce_ext_46 => '0',
      rx_ce_ext_47 => '0',
      rx_ce_ext_48 => '0',
      rx_ce_ext_49 => '0',
      rx_ce_ext_5 => '0',
      rx_ce_ext_50 => '0',
      rx_ce_ext_51 => '0',
      rx_ce_ext_6 => '0',
      rx_ce_ext_7 => '0',
      rx_ce_ext_8 => '0',
      rx_ce_ext_9 => '0',
      rx_clk => '0',
      rx_cntvaluein_0(8 downto 0) => B"000000000",
      rx_cntvaluein_1(8 downto 0) => B"000000000",
      rx_cntvaluein_10(8 downto 0) => B"000000000",
      rx_cntvaluein_11(8 downto 0) => B"000000000",
      rx_cntvaluein_12(8 downto 0) => B"000000000",
      rx_cntvaluein_13(8 downto 0) => B"000000000",
      rx_cntvaluein_14(8 downto 0) => B"000000000",
      rx_cntvaluein_15(8 downto 0) => B"000000000",
      rx_cntvaluein_16(8 downto 0) => B"000000000",
      rx_cntvaluein_17(8 downto 0) => B"000000000",
      rx_cntvaluein_18(8 downto 0) => B"000000000",
      rx_cntvaluein_19(8 downto 0) => B"000000000",
      rx_cntvaluein_2(8 downto 0) => B"000000000",
      rx_cntvaluein_20(8 downto 0) => B"000000000",
      rx_cntvaluein_21(8 downto 0) => B"000000000",
      rx_cntvaluein_22(8 downto 0) => B"000000000",
      rx_cntvaluein_23(8 downto 0) => B"000000000",
      rx_cntvaluein_24(8 downto 0) => B"000000000",
      rx_cntvaluein_25(8 downto 0) => B"000000000",
      rx_cntvaluein_26(8 downto 0) => B"000000000",
      rx_cntvaluein_27(8 downto 0) => B"000000000",
      rx_cntvaluein_28(8 downto 0) => B"000000000",
      rx_cntvaluein_29(8 downto 0) => B"000000000",
      rx_cntvaluein_3(8 downto 0) => B"000000000",
      rx_cntvaluein_30(8 downto 0) => B"000000000",
      rx_cntvaluein_31(8 downto 0) => B"000000000",
      rx_cntvaluein_32(8 downto 0) => B"000000000",
      rx_cntvaluein_33(8 downto 0) => B"000000000",
      rx_cntvaluein_34(8 downto 0) => B"000000000",
      rx_cntvaluein_35(8 downto 0) => B"000000000",
      rx_cntvaluein_36(8 downto 0) => B"000000000",
      rx_cntvaluein_37(8 downto 0) => B"000000000",
      rx_cntvaluein_38(8 downto 0) => B"000000000",
      rx_cntvaluein_39(8 downto 0) => B"000000000",
      rx_cntvaluein_4(8 downto 0) => B"000000000",
      rx_cntvaluein_40(8 downto 0) => B"000000000",
      rx_cntvaluein_41(8 downto 0) => B"000000000",
      rx_cntvaluein_42(8 downto 0) => B"000000000",
      rx_cntvaluein_43(8 downto 0) => B"000000000",
      rx_cntvaluein_44(8 downto 0) => B"000000000",
      rx_cntvaluein_45(8 downto 0) => B"000000000",
      rx_cntvaluein_46(8 downto 0) => B"000000000",
      rx_cntvaluein_47(8 downto 0) => B"000000000",
      rx_cntvaluein_48(8 downto 0) => B"000000000",
      rx_cntvaluein_49(8 downto 0) => B"000000000",
      rx_cntvaluein_5(8 downto 0) => B"000000000",
      rx_cntvaluein_50(8 downto 0) => B"000000000",
      rx_cntvaluein_51(8 downto 0) => B"000000000",
      rx_cntvaluein_6(8 downto 0) => B"000000000",
      rx_cntvaluein_7(8 downto 0) => B"000000000",
      rx_cntvaluein_8(8 downto 0) => B"000000000",
      rx_cntvaluein_9(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_0(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_1(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_10(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_11(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_12(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_13(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_14(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_15(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_16(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_17(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_18(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_19(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_2(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_20(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_21(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_22(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_23(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_24(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_25(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_26(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_27(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_28(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_29(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_3(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_30(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_31(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_32(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_33(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_34(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_35(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_36(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_37(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_38(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_39(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_4(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_40(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_41(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_42(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_43(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_44(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_45(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_46(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_47(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_48(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_49(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_5(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_50(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_51(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_6(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_7(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_8(8 downto 0) => B"000000000",
      rx_cntvaluein_ext_9(8 downto 0) => B"000000000",
      rx_cntvalueout_0(8 downto 0) => NLW_inst_rx_cntvalueout_0_UNCONNECTED(8 downto 0),
      rx_cntvalueout_1(8 downto 0) => NLW_inst_rx_cntvalueout_1_UNCONNECTED(8 downto 0),
      rx_cntvalueout_10(8 downto 0) => NLW_inst_rx_cntvalueout_10_UNCONNECTED(8 downto 0),
      rx_cntvalueout_11(8 downto 0) => NLW_inst_rx_cntvalueout_11_UNCONNECTED(8 downto 0),
      rx_cntvalueout_12(8 downto 0) => NLW_inst_rx_cntvalueout_12_UNCONNECTED(8 downto 0),
      rx_cntvalueout_13(8 downto 0) => NLW_inst_rx_cntvalueout_13_UNCONNECTED(8 downto 0),
      rx_cntvalueout_14(8 downto 0) => NLW_inst_rx_cntvalueout_14_UNCONNECTED(8 downto 0),
      rx_cntvalueout_15(8 downto 0) => NLW_inst_rx_cntvalueout_15_UNCONNECTED(8 downto 0),
      rx_cntvalueout_16(8 downto 0) => NLW_inst_rx_cntvalueout_16_UNCONNECTED(8 downto 0),
      rx_cntvalueout_17(8 downto 0) => NLW_inst_rx_cntvalueout_17_UNCONNECTED(8 downto 0),
      rx_cntvalueout_18(8 downto 0) => NLW_inst_rx_cntvalueout_18_UNCONNECTED(8 downto 0),
      rx_cntvalueout_19(8 downto 0) => NLW_inst_rx_cntvalueout_19_UNCONNECTED(8 downto 0),
      rx_cntvalueout_2(8 downto 0) => NLW_inst_rx_cntvalueout_2_UNCONNECTED(8 downto 0),
      rx_cntvalueout_20(8 downto 0) => NLW_inst_rx_cntvalueout_20_UNCONNECTED(8 downto 0),
      rx_cntvalueout_21(8 downto 0) => NLW_inst_rx_cntvalueout_21_UNCONNECTED(8 downto 0),
      rx_cntvalueout_22(8 downto 0) => NLW_inst_rx_cntvalueout_22_UNCONNECTED(8 downto 0),
      rx_cntvalueout_23(8 downto 0) => NLW_inst_rx_cntvalueout_23_UNCONNECTED(8 downto 0),
      rx_cntvalueout_24(8 downto 0) => NLW_inst_rx_cntvalueout_24_UNCONNECTED(8 downto 0),
      rx_cntvalueout_25(8 downto 0) => NLW_inst_rx_cntvalueout_25_UNCONNECTED(8 downto 0),
      rx_cntvalueout_26(8 downto 0) => NLW_inst_rx_cntvalueout_26_UNCONNECTED(8 downto 0),
      rx_cntvalueout_27(8 downto 0) => NLW_inst_rx_cntvalueout_27_UNCONNECTED(8 downto 0),
      rx_cntvalueout_28(8 downto 0) => NLW_inst_rx_cntvalueout_28_UNCONNECTED(8 downto 0),
      rx_cntvalueout_29(8 downto 0) => NLW_inst_rx_cntvalueout_29_UNCONNECTED(8 downto 0),
      rx_cntvalueout_3(8 downto 0) => NLW_inst_rx_cntvalueout_3_UNCONNECTED(8 downto 0),
      rx_cntvalueout_30(8 downto 0) => NLW_inst_rx_cntvalueout_30_UNCONNECTED(8 downto 0),
      rx_cntvalueout_31(8 downto 0) => NLW_inst_rx_cntvalueout_31_UNCONNECTED(8 downto 0),
      rx_cntvalueout_32(8 downto 0) => NLW_inst_rx_cntvalueout_32_UNCONNECTED(8 downto 0),
      rx_cntvalueout_33(8 downto 0) => NLW_inst_rx_cntvalueout_33_UNCONNECTED(8 downto 0),
      rx_cntvalueout_34(8 downto 0) => NLW_inst_rx_cntvalueout_34_UNCONNECTED(8 downto 0),
      rx_cntvalueout_35(8 downto 0) => NLW_inst_rx_cntvalueout_35_UNCONNECTED(8 downto 0),
      rx_cntvalueout_36(8 downto 0) => NLW_inst_rx_cntvalueout_36_UNCONNECTED(8 downto 0),
      rx_cntvalueout_37(8 downto 0) => NLW_inst_rx_cntvalueout_37_UNCONNECTED(8 downto 0),
      rx_cntvalueout_38(8 downto 0) => NLW_inst_rx_cntvalueout_38_UNCONNECTED(8 downto 0),
      rx_cntvalueout_39(8 downto 0) => NLW_inst_rx_cntvalueout_39_UNCONNECTED(8 downto 0),
      rx_cntvalueout_4(8 downto 0) => NLW_inst_rx_cntvalueout_4_UNCONNECTED(8 downto 0),
      rx_cntvalueout_40(8 downto 0) => NLW_inst_rx_cntvalueout_40_UNCONNECTED(8 downto 0),
      rx_cntvalueout_41(8 downto 0) => NLW_inst_rx_cntvalueout_41_UNCONNECTED(8 downto 0),
      rx_cntvalueout_42(8 downto 0) => NLW_inst_rx_cntvalueout_42_UNCONNECTED(8 downto 0),
      rx_cntvalueout_43(8 downto 0) => NLW_inst_rx_cntvalueout_43_UNCONNECTED(8 downto 0),
      rx_cntvalueout_44(8 downto 0) => NLW_inst_rx_cntvalueout_44_UNCONNECTED(8 downto 0),
      rx_cntvalueout_45(8 downto 0) => NLW_inst_rx_cntvalueout_45_UNCONNECTED(8 downto 0),
      rx_cntvalueout_46(8 downto 0) => NLW_inst_rx_cntvalueout_46_UNCONNECTED(8 downto 0),
      rx_cntvalueout_47(8 downto 0) => NLW_inst_rx_cntvalueout_47_UNCONNECTED(8 downto 0),
      rx_cntvalueout_48(8 downto 0) => NLW_inst_rx_cntvalueout_48_UNCONNECTED(8 downto 0),
      rx_cntvalueout_49(8 downto 0) => NLW_inst_rx_cntvalueout_49_UNCONNECTED(8 downto 0),
      rx_cntvalueout_5(8 downto 0) => NLW_inst_rx_cntvalueout_5_UNCONNECTED(8 downto 0),
      rx_cntvalueout_50(8 downto 0) => NLW_inst_rx_cntvalueout_50_UNCONNECTED(8 downto 0),
      rx_cntvalueout_51(8 downto 0) => NLW_inst_rx_cntvalueout_51_UNCONNECTED(8 downto 0),
      rx_cntvalueout_6(8 downto 0) => NLW_inst_rx_cntvalueout_6_UNCONNECTED(8 downto 0),
      rx_cntvalueout_7(8 downto 0) => NLW_inst_rx_cntvalueout_7_UNCONNECTED(8 downto 0),
      rx_cntvalueout_8(8 downto 0) => NLW_inst_rx_cntvalueout_8_UNCONNECTED(8 downto 0),
      rx_cntvalueout_9(8 downto 0) => NLW_inst_rx_cntvalueout_9_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_0(8 downto 0) => NLW_inst_rx_cntvalueout_ext_0_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_1(8 downto 0) => NLW_inst_rx_cntvalueout_ext_1_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_10(8 downto 0) => NLW_inst_rx_cntvalueout_ext_10_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_11(8 downto 0) => NLW_inst_rx_cntvalueout_ext_11_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_12(8 downto 0) => NLW_inst_rx_cntvalueout_ext_12_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_13(8 downto 0) => NLW_inst_rx_cntvalueout_ext_13_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_14(8 downto 0) => NLW_inst_rx_cntvalueout_ext_14_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_15(8 downto 0) => NLW_inst_rx_cntvalueout_ext_15_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_16(8 downto 0) => NLW_inst_rx_cntvalueout_ext_16_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_17(8 downto 0) => NLW_inst_rx_cntvalueout_ext_17_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_18(8 downto 0) => NLW_inst_rx_cntvalueout_ext_18_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_19(8 downto 0) => NLW_inst_rx_cntvalueout_ext_19_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_2(8 downto 0) => NLW_inst_rx_cntvalueout_ext_2_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_20(8 downto 0) => NLW_inst_rx_cntvalueout_ext_20_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_21(8 downto 0) => NLW_inst_rx_cntvalueout_ext_21_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_22(8 downto 0) => NLW_inst_rx_cntvalueout_ext_22_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_23(8 downto 0) => NLW_inst_rx_cntvalueout_ext_23_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_24(8 downto 0) => NLW_inst_rx_cntvalueout_ext_24_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_25(8 downto 0) => NLW_inst_rx_cntvalueout_ext_25_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_26(8 downto 0) => NLW_inst_rx_cntvalueout_ext_26_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_27(8 downto 0) => NLW_inst_rx_cntvalueout_ext_27_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_28(8 downto 0) => NLW_inst_rx_cntvalueout_ext_28_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_29(8 downto 0) => NLW_inst_rx_cntvalueout_ext_29_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_3(8 downto 0) => NLW_inst_rx_cntvalueout_ext_3_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_30(8 downto 0) => NLW_inst_rx_cntvalueout_ext_30_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_31(8 downto 0) => NLW_inst_rx_cntvalueout_ext_31_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_32(8 downto 0) => NLW_inst_rx_cntvalueout_ext_32_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_33(8 downto 0) => NLW_inst_rx_cntvalueout_ext_33_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_34(8 downto 0) => NLW_inst_rx_cntvalueout_ext_34_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_35(8 downto 0) => NLW_inst_rx_cntvalueout_ext_35_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_36(8 downto 0) => NLW_inst_rx_cntvalueout_ext_36_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_37(8 downto 0) => NLW_inst_rx_cntvalueout_ext_37_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_38(8 downto 0) => NLW_inst_rx_cntvalueout_ext_38_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_39(8 downto 0) => NLW_inst_rx_cntvalueout_ext_39_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_4(8 downto 0) => NLW_inst_rx_cntvalueout_ext_4_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_40(8 downto 0) => NLW_inst_rx_cntvalueout_ext_40_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_41(8 downto 0) => NLW_inst_rx_cntvalueout_ext_41_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_42(8 downto 0) => NLW_inst_rx_cntvalueout_ext_42_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_43(8 downto 0) => NLW_inst_rx_cntvalueout_ext_43_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_44(8 downto 0) => NLW_inst_rx_cntvalueout_ext_44_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_45(8 downto 0) => NLW_inst_rx_cntvalueout_ext_45_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_46(8 downto 0) => NLW_inst_rx_cntvalueout_ext_46_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_47(8 downto 0) => NLW_inst_rx_cntvalueout_ext_47_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_48(8 downto 0) => NLW_inst_rx_cntvalueout_ext_48_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_49(8 downto 0) => NLW_inst_rx_cntvalueout_ext_49_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_5(8 downto 0) => NLW_inst_rx_cntvalueout_ext_5_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_50(8 downto 0) => NLW_inst_rx_cntvalueout_ext_50_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_51(8 downto 0) => NLW_inst_rx_cntvalueout_ext_51_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_6(8 downto 0) => NLW_inst_rx_cntvalueout_ext_6_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_7(8 downto 0) => NLW_inst_rx_cntvalueout_ext_7_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_8(8 downto 0) => NLW_inst_rx_cntvalueout_ext_8_UNCONNECTED(8 downto 0),
      rx_cntvalueout_ext_9(8 downto 0) => NLW_inst_rx_cntvalueout_ext_9_UNCONNECTED(8 downto 0),
      rx_en_vtc_0 => '0',
      rx_en_vtc_1 => '0',
      rx_en_vtc_10 => '0',
      rx_en_vtc_11 => '0',
      rx_en_vtc_12 => '0',
      rx_en_vtc_13 => '0',
      rx_en_vtc_14 => '0',
      rx_en_vtc_15 => '0',
      rx_en_vtc_16 => '0',
      rx_en_vtc_17 => '0',
      rx_en_vtc_18 => '0',
      rx_en_vtc_19 => '0',
      rx_en_vtc_2 => '0',
      rx_en_vtc_20 => '0',
      rx_en_vtc_21 => '0',
      rx_en_vtc_22 => '0',
      rx_en_vtc_23 => '0',
      rx_en_vtc_24 => '0',
      rx_en_vtc_25 => '0',
      rx_en_vtc_26 => '0',
      rx_en_vtc_27 => '0',
      rx_en_vtc_28 => '0',
      rx_en_vtc_29 => '0',
      rx_en_vtc_3 => '0',
      rx_en_vtc_30 => '0',
      rx_en_vtc_31 => '0',
      rx_en_vtc_32 => '0',
      rx_en_vtc_33 => '0',
      rx_en_vtc_34 => '0',
      rx_en_vtc_35 => '0',
      rx_en_vtc_36 => '0',
      rx_en_vtc_37 => '0',
      rx_en_vtc_38 => '0',
      rx_en_vtc_39 => '0',
      rx_en_vtc_4 => '0',
      rx_en_vtc_40 => '0',
      rx_en_vtc_41 => '0',
      rx_en_vtc_42 => '0',
      rx_en_vtc_43 => '0',
      rx_en_vtc_44 => '0',
      rx_en_vtc_45 => '0',
      rx_en_vtc_46 => '0',
      rx_en_vtc_47 => '0',
      rx_en_vtc_48 => '0',
      rx_en_vtc_49 => '0',
      rx_en_vtc_5 => '0',
      rx_en_vtc_50 => '0',
      rx_en_vtc_51 => '0',
      rx_en_vtc_6 => '0',
      rx_en_vtc_7 => '0',
      rx_en_vtc_8 => '0',
      rx_en_vtc_9 => '0',
      rx_en_vtc_ext_0 => '0',
      rx_en_vtc_ext_1 => '0',
      rx_en_vtc_ext_10 => '0',
      rx_en_vtc_ext_11 => '0',
      rx_en_vtc_ext_12 => '0',
      rx_en_vtc_ext_13 => '0',
      rx_en_vtc_ext_14 => '0',
      rx_en_vtc_ext_15 => '0',
      rx_en_vtc_ext_16 => '0',
      rx_en_vtc_ext_17 => '0',
      rx_en_vtc_ext_18 => '0',
      rx_en_vtc_ext_19 => '0',
      rx_en_vtc_ext_2 => '0',
      rx_en_vtc_ext_20 => '0',
      rx_en_vtc_ext_21 => '0',
      rx_en_vtc_ext_22 => '0',
      rx_en_vtc_ext_23 => '0',
      rx_en_vtc_ext_24 => '0',
      rx_en_vtc_ext_25 => '0',
      rx_en_vtc_ext_26 => '0',
      rx_en_vtc_ext_27 => '0',
      rx_en_vtc_ext_28 => '0',
      rx_en_vtc_ext_29 => '0',
      rx_en_vtc_ext_3 => '0',
      rx_en_vtc_ext_30 => '0',
      rx_en_vtc_ext_31 => '0',
      rx_en_vtc_ext_32 => '0',
      rx_en_vtc_ext_33 => '0',
      rx_en_vtc_ext_34 => '0',
      rx_en_vtc_ext_35 => '0',
      rx_en_vtc_ext_36 => '0',
      rx_en_vtc_ext_37 => '0',
      rx_en_vtc_ext_38 => '0',
      rx_en_vtc_ext_39 => '0',
      rx_en_vtc_ext_4 => '0',
      rx_en_vtc_ext_40 => '0',
      rx_en_vtc_ext_41 => '0',
      rx_en_vtc_ext_42 => '0',
      rx_en_vtc_ext_43 => '0',
      rx_en_vtc_ext_44 => '0',
      rx_en_vtc_ext_45 => '0',
      rx_en_vtc_ext_46 => '0',
      rx_en_vtc_ext_47 => '0',
      rx_en_vtc_ext_48 => '0',
      rx_en_vtc_ext_49 => '0',
      rx_en_vtc_ext_5 => '0',
      rx_en_vtc_ext_50 => '0',
      rx_en_vtc_ext_51 => '0',
      rx_en_vtc_ext_6 => '0',
      rx_en_vtc_ext_7 => '0',
      rx_en_vtc_ext_8 => '0',
      rx_en_vtc_ext_9 => '0',
      rx_inc_0 => '0',
      rx_inc_1 => '0',
      rx_inc_10 => '0',
      rx_inc_11 => '0',
      rx_inc_12 => '0',
      rx_inc_13 => '0',
      rx_inc_14 => '0',
      rx_inc_15 => '0',
      rx_inc_16 => '0',
      rx_inc_17 => '0',
      rx_inc_18 => '0',
      rx_inc_19 => '0',
      rx_inc_2 => '0',
      rx_inc_20 => '0',
      rx_inc_21 => '0',
      rx_inc_22 => '0',
      rx_inc_23 => '0',
      rx_inc_24 => '0',
      rx_inc_25 => '0',
      rx_inc_26 => '0',
      rx_inc_27 => '0',
      rx_inc_28 => '0',
      rx_inc_29 => '0',
      rx_inc_3 => '0',
      rx_inc_30 => '0',
      rx_inc_31 => '0',
      rx_inc_32 => '0',
      rx_inc_33 => '0',
      rx_inc_34 => '0',
      rx_inc_35 => '0',
      rx_inc_36 => '0',
      rx_inc_37 => '0',
      rx_inc_38 => '0',
      rx_inc_39 => '0',
      rx_inc_4 => '0',
      rx_inc_40 => '0',
      rx_inc_41 => '0',
      rx_inc_42 => '0',
      rx_inc_43 => '0',
      rx_inc_44 => '0',
      rx_inc_45 => '0',
      rx_inc_46 => '0',
      rx_inc_47 => '0',
      rx_inc_48 => '0',
      rx_inc_49 => '0',
      rx_inc_5 => '0',
      rx_inc_50 => '0',
      rx_inc_51 => '0',
      rx_inc_6 => '0',
      rx_inc_7 => '0',
      rx_inc_8 => '0',
      rx_inc_9 => '0',
      rx_inc_ext_0 => '0',
      rx_inc_ext_1 => '0',
      rx_inc_ext_10 => '0',
      rx_inc_ext_11 => '0',
      rx_inc_ext_12 => '0',
      rx_inc_ext_13 => '0',
      rx_inc_ext_14 => '0',
      rx_inc_ext_15 => '0',
      rx_inc_ext_16 => '0',
      rx_inc_ext_17 => '0',
      rx_inc_ext_18 => '0',
      rx_inc_ext_19 => '0',
      rx_inc_ext_2 => '0',
      rx_inc_ext_20 => '0',
      rx_inc_ext_21 => '0',
      rx_inc_ext_22 => '0',
      rx_inc_ext_23 => '0',
      rx_inc_ext_24 => '0',
      rx_inc_ext_25 => '0',
      rx_inc_ext_26 => '0',
      rx_inc_ext_27 => '0',
      rx_inc_ext_28 => '0',
      rx_inc_ext_29 => '0',
      rx_inc_ext_3 => '0',
      rx_inc_ext_30 => '0',
      rx_inc_ext_31 => '0',
      rx_inc_ext_32 => '0',
      rx_inc_ext_33 => '0',
      rx_inc_ext_34 => '0',
      rx_inc_ext_35 => '0',
      rx_inc_ext_36 => '0',
      rx_inc_ext_37 => '0',
      rx_inc_ext_38 => '0',
      rx_inc_ext_39 => '0',
      rx_inc_ext_4 => '0',
      rx_inc_ext_40 => '0',
      rx_inc_ext_41 => '0',
      rx_inc_ext_42 => '0',
      rx_inc_ext_43 => '0',
      rx_inc_ext_44 => '0',
      rx_inc_ext_45 => '0',
      rx_inc_ext_46 => '0',
      rx_inc_ext_47 => '0',
      rx_inc_ext_48 => '0',
      rx_inc_ext_49 => '0',
      rx_inc_ext_5 => '0',
      rx_inc_ext_50 => '0',
      rx_inc_ext_51 => '0',
      rx_inc_ext_6 => '0',
      rx_inc_ext_7 => '0',
      rx_inc_ext_8 => '0',
      rx_inc_ext_9 => '0',
      rx_load_0 => '0',
      rx_load_1 => '0',
      rx_load_10 => '0',
      rx_load_11 => '0',
      rx_load_12 => '0',
      rx_load_13 => '0',
      rx_load_14 => '0',
      rx_load_15 => '0',
      rx_load_16 => '0',
      rx_load_17 => '0',
      rx_load_18 => '0',
      rx_load_19 => '0',
      rx_load_2 => '0',
      rx_load_20 => '0',
      rx_load_21 => '0',
      rx_load_22 => '0',
      rx_load_23 => '0',
      rx_load_24 => '0',
      rx_load_25 => '0',
      rx_load_26 => '0',
      rx_load_27 => '0',
      rx_load_28 => '0',
      rx_load_29 => '0',
      rx_load_3 => '0',
      rx_load_30 => '0',
      rx_load_31 => '0',
      rx_load_32 => '0',
      rx_load_33 => '0',
      rx_load_34 => '0',
      rx_load_35 => '0',
      rx_load_36 => '0',
      rx_load_37 => '0',
      rx_load_38 => '0',
      rx_load_39 => '0',
      rx_load_4 => '0',
      rx_load_40 => '0',
      rx_load_41 => '0',
      rx_load_42 => '0',
      rx_load_43 => '0',
      rx_load_44 => '0',
      rx_load_45 => '0',
      rx_load_46 => '0',
      rx_load_47 => '0',
      rx_load_48 => '0',
      rx_load_49 => '0',
      rx_load_5 => '0',
      rx_load_50 => '0',
      rx_load_51 => '0',
      rx_load_6 => '0',
      rx_load_7 => '0',
      rx_load_8 => '0',
      rx_load_9 => '0',
      rx_load_ext_0 => '0',
      rx_load_ext_1 => '0',
      rx_load_ext_10 => '0',
      rx_load_ext_11 => '0',
      rx_load_ext_12 => '0',
      rx_load_ext_13 => '0',
      rx_load_ext_14 => '0',
      rx_load_ext_15 => '0',
      rx_load_ext_16 => '0',
      rx_load_ext_17 => '0',
      rx_load_ext_18 => '0',
      rx_load_ext_19 => '0',
      rx_load_ext_2 => '0',
      rx_load_ext_20 => '0',
      rx_load_ext_21 => '0',
      rx_load_ext_22 => '0',
      rx_load_ext_23 => '0',
      rx_load_ext_24 => '0',
      rx_load_ext_25 => '0',
      rx_load_ext_26 => '0',
      rx_load_ext_27 => '0',
      rx_load_ext_28 => '0',
      rx_load_ext_29 => '0',
      rx_load_ext_3 => '0',
      rx_load_ext_30 => '0',
      rx_load_ext_31 => '0',
      rx_load_ext_32 => '0',
      rx_load_ext_33 => '0',
      rx_load_ext_34 => '0',
      rx_load_ext_35 => '0',
      rx_load_ext_36 => '0',
      rx_load_ext_37 => '0',
      rx_load_ext_38 => '0',
      rx_load_ext_39 => '0',
      rx_load_ext_4 => '0',
      rx_load_ext_40 => '0',
      rx_load_ext_41 => '0',
      rx_load_ext_42 => '0',
      rx_load_ext_43 => '0',
      rx_load_ext_44 => '0',
      rx_load_ext_45 => '0',
      rx_load_ext_46 => '0',
      rx_load_ext_47 => '0',
      rx_load_ext_48 => '0',
      rx_load_ext_49 => '0',
      rx_load_ext_5 => '0',
      rx_load_ext_50 => '0',
      rx_load_ext_51 => '0',
      rx_load_ext_6 => '0',
      rx_load_ext_7 => '0',
      rx_load_ext_8 => '0',
      rx_load_ext_9 => '0',
      rxtx_bitslip_sync_done => NLW_inst_rxtx_bitslip_sync_done_UNCONNECTED,
      shared_pll0_clkout0_in => '0',
      shared_pll0_clkoutphy_in => '0',
      shared_pll0_clkoutphy_out => NLW_inst_shared_pll0_clkoutphy_out_UNCONNECTED,
      shared_pll0_locked_in => '0',
      shared_pll1_clkout0_in => '0',
      shared_pll1_clkoutphy_in => '0',
      shared_pll1_clkoutphy_out => NLW_inst_shared_pll1_clkoutphy_out_UNCONNECTED,
      shared_pll1_locked_in => '0',
      start_bitslip => '0',
      tri_t_0 => '0',
      tri_t_1 => '0',
      tri_t_10 => '0',
      tri_t_11 => '0',
      tri_t_12 => '0',
      tri_t_13 => '0',
      tri_t_14 => '0',
      tri_t_15 => '0',
      tri_t_16 => '0',
      tri_t_17 => '0',
      tri_t_18 => '0',
      tri_t_19 => '0',
      tri_t_2 => '0',
      tri_t_20 => '0',
      tri_t_21 => '0',
      tri_t_22 => '0',
      tri_t_23 => '0',
      tri_t_24 => '0',
      tri_t_25 => '0',
      tri_t_26 => '0',
      tri_t_27 => '0',
      tri_t_28 => '0',
      tri_t_29 => '0',
      tri_t_3 => '0',
      tri_t_30 => '0',
      tri_t_31 => '0',
      tri_t_32 => '0',
      tri_t_33 => '0',
      tri_t_34 => '0',
      tri_t_35 => '0',
      tri_t_36 => '0',
      tri_t_37 => '0',
      tri_t_38 => '0',
      tri_t_39 => '0',
      tri_t_4 => '0',
      tri_t_40 => '0',
      tri_t_41 => '0',
      tri_t_42 => '0',
      tri_t_43 => '0',
      tri_t_44 => '0',
      tri_t_45 => '0',
      tri_t_46 => '0',
      tri_t_47 => '0',
      tri_t_48 => '0',
      tri_t_49 => '0',
      tri_t_5 => '0',
      tri_t_50 => '0',
      tri_t_51 => '0',
      tri_t_6 => '0',
      tri_t_7 => '0',
      tri_t_8 => '0',
      tri_t_9 => '0',
      tri_tbyte0(3 downto 0) => B"0000",
      tri_tbyte1(3 downto 0) => B"0000",
      tri_tbyte2(3 downto 0) => B"0000",
      tri_tbyte3(3 downto 0) => B"0000",
      tri_tbyte4(3 downto 0) => B"0000",
      tri_tbyte5(3 downto 0) => B"0000",
      tri_tbyte6(3 downto 0) => B"0000",
      tri_tbyte7(3 downto 0) => B"0000",
      tx_ce_0 => '0',
      tx_ce_1 => '0',
      tx_ce_10 => '0',
      tx_ce_11 => '0',
      tx_ce_12 => '0',
      tx_ce_13 => '0',
      tx_ce_14 => '0',
      tx_ce_15 => '0',
      tx_ce_16 => '0',
      tx_ce_17 => '0',
      tx_ce_18 => '0',
      tx_ce_19 => '0',
      tx_ce_2 => '0',
      tx_ce_20 => '0',
      tx_ce_21 => '0',
      tx_ce_22 => '0',
      tx_ce_23 => '0',
      tx_ce_24 => '0',
      tx_ce_25 => '0',
      tx_ce_26 => '0',
      tx_ce_27 => '0',
      tx_ce_28 => '0',
      tx_ce_29 => '0',
      tx_ce_3 => '0',
      tx_ce_30 => '0',
      tx_ce_31 => '0',
      tx_ce_32 => '0',
      tx_ce_33 => '0',
      tx_ce_34 => '0',
      tx_ce_35 => '0',
      tx_ce_36 => '0',
      tx_ce_37 => '0',
      tx_ce_38 => '0',
      tx_ce_39 => '0',
      tx_ce_4 => '0',
      tx_ce_40 => '0',
      tx_ce_41 => '0',
      tx_ce_42 => '0',
      tx_ce_43 => '0',
      tx_ce_44 => '0',
      tx_ce_45 => '0',
      tx_ce_46 => '0',
      tx_ce_47 => '0',
      tx_ce_48 => '0',
      tx_ce_49 => '0',
      tx_ce_5 => '0',
      tx_ce_50 => '0',
      tx_ce_51 => '0',
      tx_ce_6 => '0',
      tx_ce_7 => '0',
      tx_ce_8 => '0',
      tx_ce_9 => '0',
      tx_clk => '0',
      tx_cntvaluein_0(8 downto 0) => B"000000000",
      tx_cntvaluein_1(8 downto 0) => B"000000000",
      tx_cntvaluein_10(8 downto 0) => B"000000000",
      tx_cntvaluein_11(8 downto 0) => B"000000000",
      tx_cntvaluein_12(8 downto 0) => B"000000000",
      tx_cntvaluein_13(8 downto 0) => B"000000000",
      tx_cntvaluein_14(8 downto 0) => B"000000000",
      tx_cntvaluein_15(8 downto 0) => B"000000000",
      tx_cntvaluein_16(8 downto 0) => B"000000000",
      tx_cntvaluein_17(8 downto 0) => B"000000000",
      tx_cntvaluein_18(8 downto 0) => B"000000000",
      tx_cntvaluein_19(8 downto 0) => B"000000000",
      tx_cntvaluein_2(8 downto 0) => B"000000000",
      tx_cntvaluein_20(8 downto 0) => B"000000000",
      tx_cntvaluein_21(8 downto 0) => B"000000000",
      tx_cntvaluein_22(8 downto 0) => B"000000000",
      tx_cntvaluein_23(8 downto 0) => B"000000000",
      tx_cntvaluein_24(8 downto 0) => B"000000000",
      tx_cntvaluein_25(8 downto 0) => B"000000000",
      tx_cntvaluein_26(8 downto 0) => B"000000000",
      tx_cntvaluein_27(8 downto 0) => B"000000000",
      tx_cntvaluein_28(8 downto 0) => B"000000000",
      tx_cntvaluein_29(8 downto 0) => B"000000000",
      tx_cntvaluein_3(8 downto 0) => B"000000000",
      tx_cntvaluein_30(8 downto 0) => B"000000000",
      tx_cntvaluein_31(8 downto 0) => B"000000000",
      tx_cntvaluein_32(8 downto 0) => B"000000000",
      tx_cntvaluein_33(8 downto 0) => B"000000000",
      tx_cntvaluein_34(8 downto 0) => B"000000000",
      tx_cntvaluein_35(8 downto 0) => B"000000000",
      tx_cntvaluein_36(8 downto 0) => B"000000000",
      tx_cntvaluein_37(8 downto 0) => B"000000000",
      tx_cntvaluein_38(8 downto 0) => B"000000000",
      tx_cntvaluein_39(8 downto 0) => B"000000000",
      tx_cntvaluein_4(8 downto 0) => B"000000000",
      tx_cntvaluein_40(8 downto 0) => B"000000000",
      tx_cntvaluein_41(8 downto 0) => B"000000000",
      tx_cntvaluein_42(8 downto 0) => B"000000000",
      tx_cntvaluein_43(8 downto 0) => B"000000000",
      tx_cntvaluein_44(8 downto 0) => B"000000000",
      tx_cntvaluein_45(8 downto 0) => B"000000000",
      tx_cntvaluein_46(8 downto 0) => B"000000000",
      tx_cntvaluein_47(8 downto 0) => B"000000000",
      tx_cntvaluein_48(8 downto 0) => B"000000000",
      tx_cntvaluein_49(8 downto 0) => B"000000000",
      tx_cntvaluein_5(8 downto 0) => B"000000000",
      tx_cntvaluein_50(8 downto 0) => B"000000000",
      tx_cntvaluein_51(8 downto 0) => B"000000000",
      tx_cntvaluein_6(8 downto 0) => B"000000000",
      tx_cntvaluein_7(8 downto 0) => B"000000000",
      tx_cntvaluein_8(8 downto 0) => B"000000000",
      tx_cntvaluein_9(8 downto 0) => B"000000000",
      tx_cntvalueout_0(8 downto 0) => NLW_inst_tx_cntvalueout_0_UNCONNECTED(8 downto 0),
      tx_cntvalueout_1(8 downto 0) => NLW_inst_tx_cntvalueout_1_UNCONNECTED(8 downto 0),
      tx_cntvalueout_10(8 downto 0) => NLW_inst_tx_cntvalueout_10_UNCONNECTED(8 downto 0),
      tx_cntvalueout_11(8 downto 0) => NLW_inst_tx_cntvalueout_11_UNCONNECTED(8 downto 0),
      tx_cntvalueout_12(8 downto 0) => NLW_inst_tx_cntvalueout_12_UNCONNECTED(8 downto 0),
      tx_cntvalueout_13(8 downto 0) => NLW_inst_tx_cntvalueout_13_UNCONNECTED(8 downto 0),
      tx_cntvalueout_14(8 downto 0) => NLW_inst_tx_cntvalueout_14_UNCONNECTED(8 downto 0),
      tx_cntvalueout_15(8 downto 0) => NLW_inst_tx_cntvalueout_15_UNCONNECTED(8 downto 0),
      tx_cntvalueout_16(8 downto 0) => NLW_inst_tx_cntvalueout_16_UNCONNECTED(8 downto 0),
      tx_cntvalueout_17(8 downto 0) => NLW_inst_tx_cntvalueout_17_UNCONNECTED(8 downto 0),
      tx_cntvalueout_18(8 downto 0) => NLW_inst_tx_cntvalueout_18_UNCONNECTED(8 downto 0),
      tx_cntvalueout_19(8 downto 0) => NLW_inst_tx_cntvalueout_19_UNCONNECTED(8 downto 0),
      tx_cntvalueout_2(8 downto 0) => NLW_inst_tx_cntvalueout_2_UNCONNECTED(8 downto 0),
      tx_cntvalueout_20(8 downto 0) => NLW_inst_tx_cntvalueout_20_UNCONNECTED(8 downto 0),
      tx_cntvalueout_21(8 downto 0) => NLW_inst_tx_cntvalueout_21_UNCONNECTED(8 downto 0),
      tx_cntvalueout_22(8 downto 0) => NLW_inst_tx_cntvalueout_22_UNCONNECTED(8 downto 0),
      tx_cntvalueout_23(8 downto 0) => NLW_inst_tx_cntvalueout_23_UNCONNECTED(8 downto 0),
      tx_cntvalueout_24(8 downto 0) => NLW_inst_tx_cntvalueout_24_UNCONNECTED(8 downto 0),
      tx_cntvalueout_25(8 downto 0) => NLW_inst_tx_cntvalueout_25_UNCONNECTED(8 downto 0),
      tx_cntvalueout_26(8 downto 0) => NLW_inst_tx_cntvalueout_26_UNCONNECTED(8 downto 0),
      tx_cntvalueout_27(8 downto 0) => NLW_inst_tx_cntvalueout_27_UNCONNECTED(8 downto 0),
      tx_cntvalueout_28(8 downto 0) => NLW_inst_tx_cntvalueout_28_UNCONNECTED(8 downto 0),
      tx_cntvalueout_29(8 downto 0) => NLW_inst_tx_cntvalueout_29_UNCONNECTED(8 downto 0),
      tx_cntvalueout_3(8 downto 0) => NLW_inst_tx_cntvalueout_3_UNCONNECTED(8 downto 0),
      tx_cntvalueout_30(8 downto 0) => NLW_inst_tx_cntvalueout_30_UNCONNECTED(8 downto 0),
      tx_cntvalueout_31(8 downto 0) => NLW_inst_tx_cntvalueout_31_UNCONNECTED(8 downto 0),
      tx_cntvalueout_32(8 downto 0) => NLW_inst_tx_cntvalueout_32_UNCONNECTED(8 downto 0),
      tx_cntvalueout_33(8 downto 0) => NLW_inst_tx_cntvalueout_33_UNCONNECTED(8 downto 0),
      tx_cntvalueout_34(8 downto 0) => NLW_inst_tx_cntvalueout_34_UNCONNECTED(8 downto 0),
      tx_cntvalueout_35(8 downto 0) => NLW_inst_tx_cntvalueout_35_UNCONNECTED(8 downto 0),
      tx_cntvalueout_36(8 downto 0) => NLW_inst_tx_cntvalueout_36_UNCONNECTED(8 downto 0),
      tx_cntvalueout_37(8 downto 0) => NLW_inst_tx_cntvalueout_37_UNCONNECTED(8 downto 0),
      tx_cntvalueout_38(8 downto 0) => NLW_inst_tx_cntvalueout_38_UNCONNECTED(8 downto 0),
      tx_cntvalueout_39(8 downto 0) => NLW_inst_tx_cntvalueout_39_UNCONNECTED(8 downto 0),
      tx_cntvalueout_4(8 downto 0) => NLW_inst_tx_cntvalueout_4_UNCONNECTED(8 downto 0),
      tx_cntvalueout_40(8 downto 0) => NLW_inst_tx_cntvalueout_40_UNCONNECTED(8 downto 0),
      tx_cntvalueout_41(8 downto 0) => NLW_inst_tx_cntvalueout_41_UNCONNECTED(8 downto 0),
      tx_cntvalueout_42(8 downto 0) => NLW_inst_tx_cntvalueout_42_UNCONNECTED(8 downto 0),
      tx_cntvalueout_43(8 downto 0) => NLW_inst_tx_cntvalueout_43_UNCONNECTED(8 downto 0),
      tx_cntvalueout_44(8 downto 0) => NLW_inst_tx_cntvalueout_44_UNCONNECTED(8 downto 0),
      tx_cntvalueout_45(8 downto 0) => NLW_inst_tx_cntvalueout_45_UNCONNECTED(8 downto 0),
      tx_cntvalueout_46(8 downto 0) => NLW_inst_tx_cntvalueout_46_UNCONNECTED(8 downto 0),
      tx_cntvalueout_47(8 downto 0) => NLW_inst_tx_cntvalueout_47_UNCONNECTED(8 downto 0),
      tx_cntvalueout_48(8 downto 0) => NLW_inst_tx_cntvalueout_48_UNCONNECTED(8 downto 0),
      tx_cntvalueout_49(8 downto 0) => NLW_inst_tx_cntvalueout_49_UNCONNECTED(8 downto 0),
      tx_cntvalueout_5(8 downto 0) => NLW_inst_tx_cntvalueout_5_UNCONNECTED(8 downto 0),
      tx_cntvalueout_50(8 downto 0) => NLW_inst_tx_cntvalueout_50_UNCONNECTED(8 downto 0),
      tx_cntvalueout_51(8 downto 0) => NLW_inst_tx_cntvalueout_51_UNCONNECTED(8 downto 0),
      tx_cntvalueout_6(8 downto 0) => NLW_inst_tx_cntvalueout_6_UNCONNECTED(8 downto 0),
      tx_cntvalueout_7(8 downto 0) => NLW_inst_tx_cntvalueout_7_UNCONNECTED(8 downto 0),
      tx_cntvalueout_8(8 downto 0) => NLW_inst_tx_cntvalueout_8_UNCONNECTED(8 downto 0),
      tx_cntvalueout_9(8 downto 0) => NLW_inst_tx_cntvalueout_9_UNCONNECTED(8 downto 0),
      tx_en_vtc_0 => '0',
      tx_en_vtc_1 => '0',
      tx_en_vtc_10 => '0',
      tx_en_vtc_11 => '0',
      tx_en_vtc_12 => '0',
      tx_en_vtc_13 => '0',
      tx_en_vtc_14 => '0',
      tx_en_vtc_15 => '0',
      tx_en_vtc_16 => '0',
      tx_en_vtc_17 => '0',
      tx_en_vtc_18 => '0',
      tx_en_vtc_19 => '0',
      tx_en_vtc_2 => '0',
      tx_en_vtc_20 => '0',
      tx_en_vtc_21 => '0',
      tx_en_vtc_22 => '0',
      tx_en_vtc_23 => '0',
      tx_en_vtc_24 => '0',
      tx_en_vtc_25 => '0',
      tx_en_vtc_26 => '0',
      tx_en_vtc_27 => '0',
      tx_en_vtc_28 => '0',
      tx_en_vtc_29 => '0',
      tx_en_vtc_3 => '0',
      tx_en_vtc_30 => '0',
      tx_en_vtc_31 => '0',
      tx_en_vtc_32 => '0',
      tx_en_vtc_33 => '0',
      tx_en_vtc_34 => '0',
      tx_en_vtc_35 => '0',
      tx_en_vtc_36 => '0',
      tx_en_vtc_37 => '0',
      tx_en_vtc_38 => '0',
      tx_en_vtc_39 => '0',
      tx_en_vtc_4 => '0',
      tx_en_vtc_40 => '0',
      tx_en_vtc_41 => '0',
      tx_en_vtc_42 => '0',
      tx_en_vtc_43 => '0',
      tx_en_vtc_44 => '0',
      tx_en_vtc_45 => '0',
      tx_en_vtc_46 => '0',
      tx_en_vtc_47 => '0',
      tx_en_vtc_48 => '0',
      tx_en_vtc_49 => '0',
      tx_en_vtc_5 => '0',
      tx_en_vtc_50 => '0',
      tx_en_vtc_51 => '0',
      tx_en_vtc_6 => '0',
      tx_en_vtc_7 => '0',
      tx_en_vtc_8 => '0',
      tx_en_vtc_9 => '0',
      tx_inc_0 => '0',
      tx_inc_1 => '0',
      tx_inc_10 => '0',
      tx_inc_11 => '0',
      tx_inc_12 => '0',
      tx_inc_13 => '0',
      tx_inc_14 => '0',
      tx_inc_15 => '0',
      tx_inc_16 => '0',
      tx_inc_17 => '0',
      tx_inc_18 => '0',
      tx_inc_19 => '0',
      tx_inc_2 => '0',
      tx_inc_20 => '0',
      tx_inc_21 => '0',
      tx_inc_22 => '0',
      tx_inc_23 => '0',
      tx_inc_24 => '0',
      tx_inc_25 => '0',
      tx_inc_26 => '0',
      tx_inc_27 => '0',
      tx_inc_28 => '0',
      tx_inc_29 => '0',
      tx_inc_3 => '0',
      tx_inc_30 => '0',
      tx_inc_31 => '0',
      tx_inc_32 => '0',
      tx_inc_33 => '0',
      tx_inc_34 => '0',
      tx_inc_35 => '0',
      tx_inc_36 => '0',
      tx_inc_37 => '0',
      tx_inc_38 => '0',
      tx_inc_39 => '0',
      tx_inc_4 => '0',
      tx_inc_40 => '0',
      tx_inc_41 => '0',
      tx_inc_42 => '0',
      tx_inc_43 => '0',
      tx_inc_44 => '0',
      tx_inc_45 => '0',
      tx_inc_46 => '0',
      tx_inc_47 => '0',
      tx_inc_48 => '0',
      tx_inc_49 => '0',
      tx_inc_5 => '0',
      tx_inc_50 => '0',
      tx_inc_51 => '0',
      tx_inc_6 => '0',
      tx_inc_7 => '0',
      tx_inc_8 => '0',
      tx_inc_9 => '0',
      tx_load_0 => '0',
      tx_load_1 => '0',
      tx_load_10 => '0',
      tx_load_11 => '0',
      tx_load_12 => '0',
      tx_load_13 => '0',
      tx_load_14 => '0',
      tx_load_15 => '0',
      tx_load_16 => '0',
      tx_load_17 => '0',
      tx_load_18 => '0',
      tx_load_19 => '0',
      tx_load_2 => '0',
      tx_load_20 => '0',
      tx_load_21 => '0',
      tx_load_22 => '0',
      tx_load_23 => '0',
      tx_load_24 => '0',
      tx_load_25 => '0',
      tx_load_26 => '0',
      tx_load_27 => '0',
      tx_load_28 => '0',
      tx_load_29 => '0',
      tx_load_3 => '0',
      tx_load_30 => '0',
      tx_load_31 => '0',
      tx_load_32 => '0',
      tx_load_33 => '0',
      tx_load_34 => '0',
      tx_load_35 => '0',
      tx_load_36 => '0',
      tx_load_37 => '0',
      tx_load_38 => '0',
      tx_load_39 => '0',
      tx_load_4 => '0',
      tx_load_40 => '0',
      tx_load_41 => '0',
      tx_load_42 => '0',
      tx_load_43 => '0',
      tx_load_44 => '0',
      tx_load_45 => '0',
      tx_load_46 => '0',
      tx_load_47 => '0',
      tx_load_48 => '0',
      tx_load_49 => '0',
      tx_load_5 => '0',
      tx_load_50 => '0',
      tx_load_51 => '0',
      tx_load_6 => '0',
      tx_load_7 => '0',
      tx_load_8 => '0',
      tx_load_9 => '0',
      vtc_rdy_bsc0 => NLW_inst_vtc_rdy_bsc0_UNCONNECTED,
      vtc_rdy_bsc1 => NLW_inst_vtc_rdy_bsc1_UNCONNECTED,
      vtc_rdy_bsc2 => NLW_inst_vtc_rdy_bsc2_UNCONNECTED,
      vtc_rdy_bsc3 => NLW_inst_vtc_rdy_bsc3_UNCONNECTED,
      vtc_rdy_bsc4 => NLW_inst_vtc_rdy_bsc4_UNCONNECTED,
      vtc_rdy_bsc5 => NLW_inst_vtc_rdy_bsc5_UNCONNECTED,
      vtc_rdy_bsc6 => NLW_inst_vtc_rdy_bsc6_UNCONNECTED,
      vtc_rdy_bsc7 => NLW_inst_vtc_rdy_bsc7_UNCONNECTED
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_vfb_0_0 is
  port (
    s_axis_aclk : in STD_LOGIC;
    s_axis_aresetn : in STD_LOGIC;
    s_axis_tready : out STD_LOGIC;
    s_axis_tvalid : in STD_LOGIC;
    s_axis_tlast : in STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_tuser : in STD_LOGIC_VECTOR ( 95 downto 0 );
    s_axis_tdest : in STD_LOGIC_VECTOR ( 3 downto 0 );
    mdt_tv : out STD_LOGIC;
    mdt_tr : out STD_LOGIC;
    sdt_tv : out STD_LOGIC;
    sdt_tr : out STD_LOGIC;
    vfb_tv : out STD_LOGIC;
    vfb_tr : out STD_LOGIC;
    vfb_arstn : in STD_LOGIC;
    vfb_clk : in STD_LOGIC;
    vfb_ready : in STD_LOGIC;
    core_men_vfb : in STD_LOGIC;
    vfb_full : out STD_LOGIC;
    vfb_wc_full : out STD_LOGIC;
    core_men_ack_vfb : out STD_LOGIC;
    vfb_valid : out STD_LOGIC;
    vfb_eol : out STD_LOGIC;
    vfb_sof : out STD_LOGIC_VECTOR ( 95 downto 0 );
    vfb_vcdt : out STD_LOGIC_VECTOR ( 9 downto 0 );
    vfb_data : out STD_LOGIC_VECTOR ( 23 downto 0 )
  );
  attribute AXIS_TDATA_WIDTH : integer;
  attribute AXIS_TDATA_WIDTH of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 64;
  attribute AXIS_TDEST_WIDTH : integer;
  attribute AXIS_TDEST_WIDTH of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 4;
  attribute AXIS_TUSER_WIDTH : integer;
  attribute AXIS_TUSER_WIDTH of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 96;
  attribute C_HS_LINE_RATE : integer;
  attribute C_HS_LINE_RATE of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 1188;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is "bd_7289_vfb_0_0";
  attribute VFB_4PXL_W : integer;
  attribute VFB_4PXL_W of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 48;
  attribute VFB_BYPASS_WC : integer;
  attribute VFB_BYPASS_WC of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 0;
  attribute VFB_DATA_TYPE : integer;
  attribute VFB_DATA_TYPE of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 44;
  attribute VFB_DCONV_OWIDTH : integer;
  attribute VFB_DCONV_OWIDTH of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 32;
  attribute VFB_EN_VCX : integer;
  attribute VFB_EN_VCX of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 0;
  attribute VFB_FIFO_DEPTH : integer;
  attribute VFB_FIFO_DEPTH of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 2048;
  attribute VFB_FIFO_WIDTH : integer;
  attribute VFB_FIFO_WIDTH of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 64;
  attribute VFB_FILTER_VC : integer;
  attribute VFB_FILTER_VC of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 0;
  attribute VFB_OP_DWIDTH : integer;
  attribute VFB_OP_DWIDTH of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 24;
  attribute VFB_OP_PIXELS : integer;
  attribute VFB_OP_PIXELS of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 2;
  attribute VFB_PXL_W : integer;
  attribute VFB_PXL_W of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 12;
  attribute VFB_PXL_W_BB : integer;
  attribute VFB_PXL_W_BB of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 16;
  attribute VFB_REQ_BUFFER : integer;
  attribute VFB_REQ_BUFFER of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 1;
  attribute VFB_REQ_REORDER : integer;
  attribute VFB_REQ_REORDER of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 1;
  attribute VFB_TU_WIDTH : integer;
  attribute VFB_TU_WIDTH of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 96;
  attribute VFB_VC : integer;
  attribute VFB_VC of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is 0;
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 : entity is "yes";
end design_1_Vsp_core_0_0_bd_7289_vfb_0_0;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_vfb_0_0 is
  signal \<const0>\ : STD_LOGIC;
  signal \^vfb_sof\ : STD_LOGIC_VECTOR ( 69 downto 0 );
begin
  core_men_ack_vfb <= \<const0>\;
  mdt_tr <= \<const0>\;
  mdt_tv <= \<const0>\;
  sdt_tr <= \<const0>\;
  sdt_tv <= \<const0>\;
  vfb_full <= \<const0>\;
  vfb_sof(95) <= \<const0>\;
  vfb_sof(94) <= \<const0>\;
  vfb_sof(93) <= \<const0>\;
  vfb_sof(92) <= \<const0>\;
  vfb_sof(91) <= \<const0>\;
  vfb_sof(90) <= \<const0>\;
  vfb_sof(89) <= \<const0>\;
  vfb_sof(88) <= \<const0>\;
  vfb_sof(87) <= \<const0>\;
  vfb_sof(86) <= \<const0>\;
  vfb_sof(85) <= \<const0>\;
  vfb_sof(84) <= \<const0>\;
  vfb_sof(83) <= \<const0>\;
  vfb_sof(82) <= \<const0>\;
  vfb_sof(81) <= \<const0>\;
  vfb_sof(80) <= \<const0>\;
  vfb_sof(79) <= \<const0>\;
  vfb_sof(78) <= \<const0>\;
  vfb_sof(77) <= \<const0>\;
  vfb_sof(76) <= \<const0>\;
  vfb_sof(75) <= \<const0>\;
  vfb_sof(74) <= \<const0>\;
  vfb_sof(73) <= \<const0>\;
  vfb_sof(72) <= \<const0>\;
  vfb_sof(71) <= \<const0>\;
  vfb_sof(70) <= \<const0>\;
  vfb_sof(69 downto 64) <= \^vfb_sof\(69 downto 64);
  vfb_sof(63) <= \<const0>\;
  vfb_sof(62) <= \<const0>\;
  vfb_sof(61) <= \<const0>\;
  vfb_sof(60) <= \<const0>\;
  vfb_sof(59) <= \<const0>\;
  vfb_sof(58) <= \<const0>\;
  vfb_sof(57) <= \<const0>\;
  vfb_sof(56) <= \<const0>\;
  vfb_sof(55) <= \<const0>\;
  vfb_sof(54) <= \<const0>\;
  vfb_sof(53) <= \<const0>\;
  vfb_sof(52) <= \<const0>\;
  vfb_sof(51) <= \<const0>\;
  vfb_sof(50) <= \<const0>\;
  vfb_sof(49) <= \<const0>\;
  vfb_sof(48) <= \<const0>\;
  vfb_sof(47) <= \<const0>\;
  vfb_sof(46) <= \<const0>\;
  vfb_sof(45) <= \<const0>\;
  vfb_sof(44) <= \<const0>\;
  vfb_sof(43) <= \<const0>\;
  vfb_sof(42) <= \<const0>\;
  vfb_sof(41) <= \<const0>\;
  vfb_sof(40) <= \<const0>\;
  vfb_sof(39) <= \<const0>\;
  vfb_sof(38) <= \<const0>\;
  vfb_sof(37) <= \<const0>\;
  vfb_sof(36) <= \<const0>\;
  vfb_sof(35) <= \<const0>\;
  vfb_sof(34) <= \<const0>\;
  vfb_sof(33) <= \<const0>\;
  vfb_sof(32) <= \<const0>\;
  vfb_sof(31) <= \<const0>\;
  vfb_sof(30) <= \<const0>\;
  vfb_sof(29) <= \<const0>\;
  vfb_sof(28) <= \<const0>\;
  vfb_sof(27) <= \<const0>\;
  vfb_sof(26) <= \<const0>\;
  vfb_sof(25) <= \<const0>\;
  vfb_sof(24) <= \<const0>\;
  vfb_sof(23) <= \<const0>\;
  vfb_sof(22) <= \<const0>\;
  vfb_sof(21) <= \<const0>\;
  vfb_sof(20) <= \<const0>\;
  vfb_sof(19) <= \<const0>\;
  vfb_sof(18) <= \<const0>\;
  vfb_sof(17) <= \<const0>\;
  vfb_sof(16) <= \<const0>\;
  vfb_sof(15) <= \<const0>\;
  vfb_sof(14) <= \<const0>\;
  vfb_sof(13) <= \<const0>\;
  vfb_sof(12) <= \<const0>\;
  vfb_sof(11) <= \<const0>\;
  vfb_sof(10) <= \<const0>\;
  vfb_sof(9) <= \<const0>\;
  vfb_sof(8) <= \<const0>\;
  vfb_sof(7) <= \<const0>\;
  vfb_sof(6) <= \<const0>\;
  vfb_sof(5) <= \<const0>\;
  vfb_sof(4) <= \<const0>\;
  vfb_sof(3) <= \<const0>\;
  vfb_sof(2) <= \<const0>\;
  vfb_sof(1) <= \<const0>\;
  vfb_sof(0) <= \^vfb_sof\(0);
  vfb_tr <= \<const0>\;
  vfb_tv <= \<const0>\;
  vfb_vcdt(9) <= \<const0>\;
  vfb_vcdt(8) <= \<const0>\;
  vfb_vcdt(7) <= \<const0>\;
  vfb_vcdt(6) <= \<const0>\;
  vfb_vcdt(5) <= \<const0>\;
  vfb_vcdt(4) <= \<const0>\;
  vfb_vcdt(3) <= \<const0>\;
  vfb_vcdt(2) <= \<const0>\;
  vfb_vcdt(1) <= \<const0>\;
  vfb_vcdt(0) <= \<const0>\;
  vfb_wc_full <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
inst: entity work.design_1_Vsp_core_0_0_bd_7289_vfb_0_0_core
     port map (
      D(80) => s_axis_tlast,
      D(79 downto 16) => s_axis_tdata(63 downto 0),
      D(15 downto 8) => s_axis_tkeep(7 downto 0),
      D(7 downto 2) => s_axis_tuser(69 downto 64),
      D(1 downto 0) => s_axis_tuser(1 downto 0),
      s_axis_tready => s_axis_tready,
      s_axis_tvalid => s_axis_tvalid,
      vfb_arstn => vfb_arstn,
      vfb_clk => vfb_clk,
      vfb_data(23 downto 0) => vfb_data(23 downto 0),
      vfb_eol_reg => vfb_eol,
      vfb_sof(6 downto 1) => \^vfb_sof\(69 downto 64),
      vfb_sof(0) => \^vfb_sof\(0),
      vfb_valid_reg => vfb_valid
    );
end STRUCTURE;
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2024.2"
`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
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`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
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`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Xilinx", key_keyname="xilinxt_2023_11", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=384)
`protect key_block
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`protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 354688)
`protect data_block
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`protect end_protected
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2024.2"
`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
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`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Xilinx", key_keyname="xilinxt_2023_11", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=384)
`protect key_block
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`protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 442912)
`protect data_block
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a32b64 is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a32b64 : entity is "Dpbram_xlnx_size2kB_a32b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a32b64 : entity is "Dpbram_xlnx_size2kB_a32b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a32b64 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a32b64 : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a32b64;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a32b64 is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 9;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 8;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     8.000303 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size2kB_a32b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 512;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 256;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 32;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 512;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 256;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 32;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9
     port map (
      addra(8 downto 0) => addra(8 downto 0),
      addrb(7 downto 0) => addrb(7 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(31) => dina(31),
      dina(30 downto 27) => B"0000",
      dina(26 downto 16) => dina(26 downto 16),
      dina(15 downto 11) => B"00000",
      dina(10 downto 0) => dina(10 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(31 downto 0) => NLW_U0_douta_UNCONNECTED(31 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(7 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(7 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(7 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(7 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a64b64 is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 63 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a64b64 : entity is "Dpbram_xlnx_size2kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a64b64 : entity is "Dpbram_xlnx_size2kB_a64b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a64b64 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a64b64 : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a64b64;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a64b64 is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 59 downto 0 );
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 60 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 8;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 8;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     8.476303 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size2kB_a64b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 256;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 256;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 64;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 256;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 256;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 64;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
  doutb(63) <= \<const0>\;
  doutb(62) <= \<const0>\;
  doutb(61) <= \<const0>\;
  doutb(60) <= \<const0>\;
  doutb(59 downto 0) <= \^doutb\(59 downto 0);
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized5\
     port map (
      addra(7 downto 0) => addra(7 downto 0),
      addrb(7 downto 0) => addrb(7 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(63 downto 60) => B"0000",
      dina(59 downto 0) => dina(59 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_U0_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 60) => NLW_U0_doutb_UNCONNECTED(63 downto 60),
      doutb(59 downto 0) => \^doutb\(59 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(7 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(7 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(7 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(7 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8 is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8 : entity is "Dpbram_xlnx_size2kB_a8b8,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8 : entity is "Dpbram_xlnx_size2kB_a8b8";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8 : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8 is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 11;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 11;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "1";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "0";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     2.05356 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size2kB_a8b8.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 2048;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 2048;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 8;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 8;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 2048;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 2048;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 8;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 8;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized1\
     port map (
      addra(10 downto 0) => addra(10 downto 0),
      addrb(10 downto 0) => addrb(10 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(7 downto 0) => dina(7 downto 0),
      dinb(7 downto 0) => B"00000000",
      douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0),
      doutb(7 downto 0) => doutb(7 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0),
      s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(7 downto 0) => B"00000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__5\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__5\ : entity is "Dpbram_xlnx_size2kB_a8b8,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__5\ : entity is "Dpbram_xlnx_size2kB_a8b8";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__5\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__5\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__5\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__5\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 11;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 11;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "1";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "0";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     2.05356 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size2kB_a8b8.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 2048;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 2048;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 8;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 8;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 2048;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 2048;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 8;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 8;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized1__5\
     port map (
      addra(10 downto 0) => addra(10 downto 0),
      addrb(10 downto 0) => addrb(10 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(7 downto 0) => dina(7 downto 0),
      dinb(7 downto 0) => B"00000000",
      douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0),
      doutb(7 downto 0) => doutb(7 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0),
      s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(7 downto 0) => B"00000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__6\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__6\ : entity is "Dpbram_xlnx_size2kB_a8b8,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__6\ : entity is "Dpbram_xlnx_size2kB_a8b8";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__6\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__6\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__6\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__6\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 11;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 11;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "1";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "0";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     2.05356 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size2kB_a8b8.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 2048;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 2048;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 8;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 8;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 2048;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 2048;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 8;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 8;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized1__6\
     port map (
      addra(10 downto 0) => addra(10 downto 0),
      addrb(10 downto 0) => addrb(10 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(7 downto 0) => dina(7 downto 0),
      dinb(7 downto 0) => B"00000000",
      douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0),
      doutb(7 downto 0) => doutb(7 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0),
      s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(7 downto 0) => B"00000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__7\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__7\ : entity is "Dpbram_xlnx_size2kB_a8b8,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__7\ : entity is "Dpbram_xlnx_size2kB_a8b8";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__7\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__7\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__7\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__7\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 11;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 11;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "1";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "0";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     2.05356 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size2kB_a8b8.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 2048;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 2048;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 8;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 8;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 2048;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 2048;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 8;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 8;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized1__7\
     port map (
      addra(10 downto 0) => addra(10 downto 0),
      addrb(10 downto 0) => addrb(10 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(7 downto 0) => dina(7 downto 0),
      dinb(7 downto 0) => B"00000000",
      douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0),
      doutb(7 downto 0) => doutb(7 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0),
      s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(7 downto 0) => B"00000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__8\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__8\ : entity is "Dpbram_xlnx_size2kB_a8b8,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__8\ : entity is "Dpbram_xlnx_size2kB_a8b8";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__8\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__8\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__8\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__8\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 11;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 11;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "1";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "0";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     2.05356 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size2kB_a8b8.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 2048;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 2048;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 8;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 8;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 2048;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 2048;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 8;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 8;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized1__8\
     port map (
      addra(10 downto 0) => addra(10 downto 0),
      addrb(10 downto 0) => addrb(10 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(7 downto 0) => dina(7 downto 0),
      dinb(7 downto 0) => B"00000000",
      douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0),
      doutb(7 downto 0) => doutb(7 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0),
      s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(7 downto 0) => B"00000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64 is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64 : entity is "Dpbram_xlnx_size38kB_a8b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64 : entity is "Dpbram_xlnx_size38kB_a8b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64 : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64 is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 16;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 13;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "10";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     26.47852 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size38kB_a8b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 38912;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 4864;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 8;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 38912;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 4864;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 8;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized7\
     port map (
      addra(15 downto 0) => B"0000000000000000",
      addrb(12 downto 0) => addrb(12 downto 0),
      clka => '0',
      clkb => clkb,
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(7 downto 0) => B"00000000",
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => '0',
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(12 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(12 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(12 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(12 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(7 downto 0) => B"00000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64__2\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64__2\ : entity is "Dpbram_xlnx_size38kB_a8b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64__2\ : entity is "Dpbram_xlnx_size38kB_a8b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64__2\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64__2\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64__2\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64__2\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 16;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 13;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "10";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     26.47852 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size38kB_a8b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 38912;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 4864;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 8;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 38912;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 4864;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 8;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized7__2\
     port map (
      addra(15 downto 0) => addra(15 downto 0),
      addrb(12 downto 0) => addrb(12 downto 0),
      clka => '0',
      clkb => clkb,
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(7 downto 0) => dina(7 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(12 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(12 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(12 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(12 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(7 downto 0) => B"00000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64 is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64 : entity is "Dpbram_xlnx_size4kB_a32b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64 : entity is "Dpbram_xlnx_size4kB_a32b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64 : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64 is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 10;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     8.000303 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size4kB_a32b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 1024;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 32;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 1024;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 32;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized3\
     port map (
      addra(9 downto 0) => addra(9 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(31 downto 30) => dina(31 downto 30),
      dina(29 downto 22) => B"00000000",
      dina(21 downto 0) => dina(21 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(31 downto 0) => NLW_U0_douta_UNCONNECTED(31 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__4\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__4\ : entity is "Dpbram_xlnx_size4kB_a32b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__4\ : entity is "Dpbram_xlnx_size4kB_a32b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__4\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__4\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__4\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 10;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     8.000303 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size4kB_a32b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 1024;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 32;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 1024;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 32;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized3__4\
     port map (
      addra(9 downto 0) => addra(9 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => clkb,
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(31 downto 30) => dina(31 downto 30),
      dina(29 downto 25) => B"00000",
      dina(24 downto 0) => dina(24 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(31 downto 0) => NLW_U0_douta_UNCONNECTED(31 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__5\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__5\ : entity is "Dpbram_xlnx_size4kB_a32b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__5\ : entity is "Dpbram_xlnx_size4kB_a32b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__5\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__5\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__5\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__5\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 10;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     8.000303 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size4kB_a32b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 1024;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 32;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 1024;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 32;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized3__5\
     port map (
      addra(9 downto 0) => addra(9 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(31 downto 0) => dina(31 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(31 downto 0) => NLW_U0_douta_UNCONNECTED(31 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__6\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__6\ : entity is "Dpbram_xlnx_size4kB_a32b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__6\ : entity is "Dpbram_xlnx_size4kB_a32b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__6\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__6\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__6\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__6\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 10;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     8.000303 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size4kB_a32b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 1024;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 32;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 1024;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 32;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized3__6\
     port map (
      addra(9 downto 0) => addra(9 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(31 downto 0) => dina(31 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(31 downto 0) => NLW_U0_douta_UNCONNECTED(31 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64 is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 63 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64 : entity is "Dpbram_xlnx_size4kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64 : entity is "Dpbram_xlnx_size4kB_a64b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64 : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64 is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 9;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     8.476303 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size4kB_a64b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 512;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 64;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 512;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 64;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized17\
     port map (
      addra(8 downto 0) => addra(8 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(63 downto 0) => dina(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_U0_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__5\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 63 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__5\ : entity is "Dpbram_xlnx_size4kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__5\ : entity is "Dpbram_xlnx_size4kB_a64b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__5\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__5\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__5\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__5\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 9;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     8.476303 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size4kB_a64b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 512;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 64;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 512;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 64;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized17__5\
     port map (
      addra(8 downto 0) => addra(8 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(63 downto 0) => dina(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_U0_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__6\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 63 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__6\ : entity is "Dpbram_xlnx_size4kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__6\ : entity is "Dpbram_xlnx_size4kB_a64b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__6\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__6\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__6\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__6\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 9;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     8.476303 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size4kB_a64b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 512;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 64;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 512;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 64;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized17__6\
     port map (
      addra(8 downto 0) => addra(8 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(63 downto 0) => dina(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_U0_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__7\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 63 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__7\ : entity is "Dpbram_xlnx_size4kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__7\ : entity is "Dpbram_xlnx_size4kB_a64b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__7\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__7\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__7\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__7\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 9;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     8.476303 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size4kB_a64b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 512;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 64;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 512;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 64;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized17__7\
     port map (
      addra(8 downto 0) => addra(8 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(63 downto 0) => dina(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_U0_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__8\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 63 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__8\ : entity is "Dpbram_xlnx_size4kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__8\ : entity is "Dpbram_xlnx_size4kB_a64b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__8\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__8\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__8\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__8\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 9;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     8.476303 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size4kB_a64b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 512;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 64;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 512;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 64;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized17__8\
     port map (
      addra(8 downto 0) => addra(8 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(63 downto 0) => dina(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_U0_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64 is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 63 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64 : entity is "Dpbram_xlnx_size6kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64 : entity is "Dpbram_xlnx_size6kB_a64b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64 : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64 is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 10;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 10;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     8.476303 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size6kB_a64b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 768;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 768;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 64;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 768;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 768;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 64;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized15\
     port map (
      addra(9 downto 0) => addra(9 downto 0),
      addrb(9 downto 0) => addrb(9 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(63 downto 0) => dina(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_U0_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__3\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 63 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__3\ : entity is "Dpbram_xlnx_size6kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__3\ : entity is "Dpbram_xlnx_size6kB_a64b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__3\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__3\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__3\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__3\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 10;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 10;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     8.476303 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size6kB_a64b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 768;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 768;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 64;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 768;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 768;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 64;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized15__3\
     port map (
      addra(9 downto 0) => addra(9 downto 0),
      addrb(9 downto 0) => addrb(9 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(63 downto 0) => dina(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_U0_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__4\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 63 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__4\ : entity is "Dpbram_xlnx_size6kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__4\ : entity is "Dpbram_xlnx_size6kB_a64b64";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__4\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__4\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__4\ is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 10;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 10;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     8.476303 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size6kB_a64b64.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 768;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 768;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 64;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 768;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 768;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 64;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
  douta(63) <= \<const0>\;
  douta(62) <= \<const0>\;
  douta(61) <= \<const0>\;
  douta(60) <= \<const0>\;
  douta(59) <= \<const0>\;
  douta(58) <= \<const0>\;
  douta(57) <= \<const0>\;
  douta(56) <= \<const0>\;
  douta(55) <= \<const0>\;
  douta(54) <= \<const0>\;
  douta(53) <= \<const0>\;
  douta(52) <= \<const0>\;
  douta(51) <= \<const0>\;
  douta(50) <= \<const0>\;
  douta(49) <= \<const0>\;
  douta(48) <= \<const0>\;
  douta(47) <= \<const0>\;
  douta(46) <= \<const0>\;
  douta(45) <= \<const0>\;
  douta(44) <= \<const0>\;
  douta(43) <= \<const0>\;
  douta(42) <= \<const0>\;
  douta(41) <= \<const0>\;
  douta(40) <= \<const0>\;
  douta(39) <= \<const0>\;
  douta(38) <= \<const0>\;
  douta(37) <= \<const0>\;
  douta(36) <= \<const0>\;
  douta(35) <= \<const0>\;
  douta(34) <= \<const0>\;
  douta(33) <= \<const0>\;
  douta(32) <= \<const0>\;
  douta(31) <= \<const0>\;
  douta(30) <= \<const0>\;
  douta(29) <= \<const0>\;
  douta(28) <= \<const0>\;
  douta(27) <= \<const0>\;
  douta(26) <= \<const0>\;
  douta(25) <= \<const0>\;
  douta(24) <= \<const0>\;
  douta(23) <= \<const0>\;
  douta(22) <= \<const0>\;
  douta(21) <= \<const0>\;
  douta(20) <= \<const0>\;
  douta(19) <= \<const0>\;
  douta(18) <= \<const0>\;
  douta(17) <= \<const0>\;
  douta(16) <= \<const0>\;
  douta(15) <= \<const0>\;
  douta(14) <= \<const0>\;
  douta(13) <= \<const0>\;
  douta(12) <= \<const0>\;
  douta(11) <= \<const0>\;
  douta(10) <= \<const0>\;
  douta(9) <= \<const0>\;
  douta(8) <= \<const0>\;
  douta(7) <= \<const0>\;
  douta(6) <= \<const0>\;
  douta(5) <= \<const0>\;
  douta(4) <= \<const0>\;
  douta(3) <= \<const0>\;
  douta(2) <= \<const0>\;
  douta(1) <= \<const0>\;
  douta(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized15__4\
     port map (
      addra(9 downto 0) => addra(9 downto 0),
      addrb(9 downto 0) => addrb(9 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(63 downto 0) => dina(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_U0_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128 is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 127 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 127 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128 : entity is "Dpbram_xlnx_size8kB_a32b128,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128 : entity is "Dpbram_xlnx_size8kB_a32b128";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128 : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128 is
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 11;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "4";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     15.524607 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size8kB_a32b128.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 2048;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 32;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 128;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 2048;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 32;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 128;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized9\
     port map (
      addra(10 downto 0) => addra(10 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => clkb,
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(31 downto 0) => dina(31 downto 0),
      dinb(127 downto 0) => dinb(127 downto 0),
      douta(31 downto 0) => douta(31 downto 0),
      doutb(127 downto 0) => doutb(127 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(127 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(127 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => wea(0),
      web(0) => web(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128__2\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dinb : in STD_LOGIC_VECTOR ( 127 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 127 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128__2\ : entity is "Dpbram_xlnx_size8kB_a32b128,blk_mem_gen_v8_4_9,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128__2\ : entity is "Dpbram_xlnx_size8kB_a32b128";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of \design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128__2\ : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128__2\ : entity is "blk_mem_gen_v8_4_9,Vivado 2024.2";
end \design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128__2\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128__2\ is
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 11;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 0;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "4";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     15.524607 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynquplus";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "Dpbram_xlnx_size8kB_a32b128.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 2;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 2048;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 32;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 128;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 2048;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 32;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 128;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynquplus";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute x_interface_info : string;
  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clka : signal is "slave BRAM_PORTA";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute x_interface_mode of clkb : signal is "slave BRAM_PORTB";
  attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_ADDRESS_MODE BYTE_ADDRESS, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute x_interface_info of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
  attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
  attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
begin
U0: entity work.\design_1_Vsp_core_0_0_blk_mem_gen_v8_4_9__parameterized9__2\
     port map (
      addra(10 downto 0) => addra(10 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => clkb,
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(31 downto 0) => dina(31 downto 0),
      dinb(127 downto 0) => dinb(127 downto 0),
      douta(31 downto 0) => douta(31 downto 0),
      doutb(127 downto 0) => doutb(127 downto 0),
      eccpipece => '0',
      ena => ena,
      enb => enb,
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '1',
      regceb => '1',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(127 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(127 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => wea(0),
      web(0) => web(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_phy_0_support is
  port (
    rxbyteclkhs : out STD_LOGIC;
    dl0_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl0_rxvalidhs : out STD_LOGIC;
    dl0_rxactivehs : out STD_LOGIC;
    dl0_rxsynchs : out STD_LOGIC;
    dl0_stopstate : out STD_LOGIC;
    dl0_errsoths : out STD_LOGIC;
    dl0_errsotsynchs : out STD_LOGIC;
    dl1_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl1_rxvalidhs : out STD_LOGIC;
    dl1_rxactivehs : out STD_LOGIC;
    dl1_rxsynchs : out STD_LOGIC;
    dl1_stopstate : out STD_LOGIC;
    dl1_errsoths : out STD_LOGIC;
    dl1_errsotsynchs : out STD_LOGIC;
    dl2_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl2_rxvalidhs : out STD_LOGIC;
    dl2_rxactivehs : out STD_LOGIC;
    dl2_rxsynchs : out STD_LOGIC;
    dl2_stopstate : out STD_LOGIC;
    dl2_errsoths : out STD_LOGIC;
    dl2_errsotsynchs : out STD_LOGIC;
    dl3_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl3_rxvalidhs : out STD_LOGIC;
    dl3_rxactivehs : out STD_LOGIC;
    dl3_rxsynchs : out STD_LOGIC;
    dl3_stopstate : out STD_LOGIC;
    dl3_errsoths : out STD_LOGIC;
    dl3_errsotsynchs : out STD_LOGIC;
    cl_stopstate : out STD_LOGIC;
    s_axi_awready : out STD_LOGIC;
    s_axi_arready : out STD_LOGIC;
    s_axi_wready : out STD_LOGIC;
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rvalid : out STD_LOGIC;
    s_axi_bvalid : out STD_LOGIC;
    clk_rxp : in STD_LOGIC;
    clk_rxn : in STD_LOGIC;
    data_rxp : in STD_LOGIC_VECTOR ( 3 downto 0 );
    data_rxn : in STD_LOGIC_VECTOR ( 3 downto 0 );
    core_rst : in STD_LOGIC;
    core_clk : in STD_LOGIC;
    cl_enable : in STD_LOGIC;
    s_axi_aresetn : in STD_LOGIC;
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
    s_axi_awvalid : in STD_LOGIC;
    s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
    s_axi_arvalid : in STD_LOGIC;
    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_wvalid : in STD_LOGIC;
    s_axi_rready : in STD_LOGIC;
    s_axi_bready : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_phy_0_support : entity is "bd_7289_phy_0_support";
end design_1_Vsp_core_0_0_bd_7289_phy_0_support;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_phy_0_support is
  signal bit_slc_rst_w : STD_LOGIC;
  signal cl_enable_sync : STD_LOGIC;
  signal core_ref_clk_w : STD_LOGIC;
  signal core_rst_coreclk_sync : STD_LOGIC;
  signal div4_clk_t : STD_LOGIC;
  signal dphy_en_w : STD_LOGIC;
  signal dphy_srst_w : STD_LOGIC;
  signal phy_rdy_out : STD_LOGIC;
  signal phy_reset_w : STD_LOGIC;
  signal rx_cl_disable_ibuf_w : STD_LOGIC;
  signal rx_dl0_disable_ibuf_w : STD_LOGIC;
  signal rx_dl0_fifo_empty_w : STD_LOGIC;
  signal rx_dl0_hs_dp_w : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rx_dl0_lp_dn_w : STD_LOGIC;
  signal rx_dl0_lp_dp_w : STD_LOGIC;
  signal rx_dl1_disable_ibuf_w : STD_LOGIC;
  signal rx_dl1_fifo_empty_w : STD_LOGIC;
  signal rx_dl1_hs_dp_w : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rx_dl1_lp_dn_w : STD_LOGIC;
  signal rx_dl1_lp_dp_w : STD_LOGIC;
  signal rx_dl2_disable_ibuf_w : STD_LOGIC;
  signal rx_dl2_fifo_empty_w : STD_LOGIC;
  signal rx_dl2_hs_dp_w : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rx_dl2_lp_dn_w : STD_LOGIC;
  signal rx_dl2_lp_dp_w : STD_LOGIC;
  signal rx_dl3_disable_ibuf_w : STD_LOGIC;
  signal rx_dl3_fifo_empty_w : STD_LOGIC;
  signal rx_dl3_hs_dp_w : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rx_dl3_lp_dn_w : STD_LOGIC;
  signal rx_dl3_lp_dp_w : STD_LOGIC;
  signal \^rxbyteclkhs\ : STD_LOGIC;
  signal \slave_rx.bd_7289_phy_0_rx_hssio_i_i_1_n_0\ : STD_LOGIC;
  signal \slave_rx.bd_7289_phy_0_rx_hssio_i_i_2_n_0\ : STD_LOGIC;
  signal \slave_rx.bd_7289_phy_0_rx_hssio_i_i_3_n_0\ : STD_LOGIC;
  signal \slave_rx.bd_7289_phy_0_rx_hssio_i_i_4_n_0\ : STD_LOGIC;
  signal \slave_rx.bd_7289_phy_0_rx_hssio_i_n_4\ : STD_LOGIC;
  signal \slave_rx.bd_7289_phy_0_rx_hssio_i_n_9\ : STD_LOGIC;
  signal \slave_rx.u_rx_rst_logic_n_6\ : STD_LOGIC;
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_dly_rdy_bsc0_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_dly_rdy_bsc1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_fifo_empty_0_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_fifo_empty_1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_fifo_empty_3_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_fifo_empty_5_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_fifo_empty_7_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_fifo_empty_9_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_pll0_clkout0_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_pll0_locked_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_shared_pll0_clkoutphy_out_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_vtc_rdy_bsc0_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_vtc_rdy_bsc1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_data_to_fabric_clk_rxn_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_data_to_fabric_clk_rxp_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_data_to_fabric_data_rxn0_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_data_to_fabric_data_rxn1_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_data_to_fabric_data_rxn2_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_data_to_fabric_data_rxn3_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.cl_enable_sync_support_i_prmry_ack_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.cl_enable_sync_support_i_scndry_vect_out_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_calib_status_l0_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_calib_status_l1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_calib_status_l2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_calib_status_l3_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_cl_rxclkactivehs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_cl_rxulpsclknot_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_cl_ulpsactivenot_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl0_errcontrol_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl0_erresc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl0_errsyncesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl0_rxclkesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl0_rxlpdtesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl0_rxskewcalhs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl0_rxulpsesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl0_rxvalidesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl0_ulpsactivenot_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl1_errcontrol_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl1_erresc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl1_errsyncesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl1_rxclkesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl1_rxlpdtesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl1_rxskewcalhs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl1_rxulpsesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl1_rxvalidesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl1_ulpsactivenot_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl2_errcontrol_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl2_erresc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl2_errsyncesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl2_rxclkesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl2_rxlpdtesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl2_rxskewcalhs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl2_rxulpsesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl2_rxvalidesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl2_ulpsactivenot_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl3_errcontrol_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl3_erresc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl3_errsyncesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl3_rxclkesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl3_rxlpdtesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl3_rxskewcalhs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl3_rxulpsesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl3_rxvalidesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl3_ulpsactivenot_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_errcontrol_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_erresc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_errsoths_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_errsotsynchs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_errsyncesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_rxactivehs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_rxclkesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_rxlpdtesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_rxskewcalhs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_rxsynchs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_rxulpsesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_rxvalidesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_rxvalidhs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_stopstate_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_ulpsactivenot_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_errcontrol_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_erresc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_errsoths_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_errsotsynchs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_errsyncesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_rxactivehs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_rxclkesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_rxlpdtesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_rxskewcalhs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_rxsynchs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_rxulpsesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_rxvalidesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_rxvalidhs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_stopstate_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_ulpsactivenot_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_errcontrol_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_erresc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_errsoths_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_errsotsynchs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_errsyncesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_rxactivehs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_rxclkesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_rxlpdtesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_rxskewcalhs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_rxsynchs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_rxulpsesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_rxvalidesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_rxvalidhs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_stopstate_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_ulpsactivenot_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_errcontrol_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_erresc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_errsoths_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_errsotsynchs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_errsyncesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_rxactivehs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_rxclkesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_rxlpdtesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_rxskewcalhs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_rxsynchs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_rxulpsesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_rxvalidesc_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_rxvalidhs_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_stopstate_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_ulpsactivenot_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_idelay_load_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_init_done_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_phy_rst_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_reg_cal_start_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_nibble_sel_l0_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_nibble_sel_l1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_nibble_sel_l2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_nibble_sel_l3_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_wr_en_l0_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_wr_en_l1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_wr_en_l2_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_wr_en_l3_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_cl_en_hs_lpn_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_cl_fifo_rd_clk_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_cl_fifo_rd_en_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl0_en_hs_lpn_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl0_fifo_rd_clk_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl0_fifo_rd_en_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl1_en_hs_lpn_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl1_fifo_rd_clk_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl1_fifo_rd_en_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl2_en_hs_lpn_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl2_fifo_rd_clk_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl2_fifo_rd_en_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl3_en_hs_lpn_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl3_fifo_rd_clk_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl3_fifo_rd_en_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl4_disable_ibuf_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl4_en_hs_lpn_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl4_fifo_rd_clk_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl4_fifo_rd_en_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl5_disable_ibuf_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl5_en_hs_lpn_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl5_fifo_rd_clk_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl5_fifo_rd_en_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl6_disable_ibuf_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl6_en_hs_lpn_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl6_fifo_rd_clk_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl6_fifo_rd_en_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl7_disable_ibuf_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl7_en_hs_lpn_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl7_fifo_rd_clk_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_rx_dl7_fifo_rd_en_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_sys_rst_byteclk_out_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.dphy_rx_fab_top_alt_skew_calb_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl0_rxdataesc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl0_rxtriggeresc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl1_rxdataesc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl1_rxtriggeresc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl2_rxdataesc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl2_rxtriggeresc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl3_rxdataesc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl3_rxtriggeresc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_rxdataesc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_rxdatahs_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl4_rxtriggeresc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_rxdataesc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_rxdatahs_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl5_rxtriggeresc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_rxdataesc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_rxdatahs_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl6_rxtriggeresc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_rxdataesc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_rxdatahs_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_dl7_rxtriggeresc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_idelay_tap_value_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_init_periodic_skew_calb_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_addr_l0_UNCONNECTED\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_addr_l1_UNCONNECTED\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_addr_l2_UNCONNECTED\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_addr_l3_UNCONNECTED\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_wr_data_l0_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_wr_data_l1_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_wr_data_l2_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_riu_wr_data_l3_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_s_axi_bresp_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_s_axi_rresp_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_tap_comp_res_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_slave_rx.dphy_rx_fab_top_tap_val_dyn_out_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_slave_rx.u_rx_rst_logic_mmcm_rst_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.u_rx_rst_logic_system_rst_byteclk_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.u_rx_rst_logic_system_rst_div4clk_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.u_rx_rst_logic_system_rst_escclk_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_slave_rx.u_rx_rst_logic_txpll_rst_UNCONNECTED\ : STD_LOGIC;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \slave_rx.bd_7289_phy_0_rx_hssio_i\ : label is "bd_7289_phy_0_hssio_rx,bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of \slave_rx.bd_7289_phy_0_rx_hssio_i\ : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of \slave_rx.bd_7289_phy_0_rx_hssio_i\ : label is "bd_7289_phy_0_hssio_rx_high_speed_selectio_wiz_v3_6_10,Vivado 2024.2";
  attribute DowngradeIPIdentifiedWarnings of \slave_rx.cl_enable_sync_support_i\ : label is "yes";
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of \slave_rx.cl_enable_sync_support_i\ : label is "soft";
  attribute c_cdc_type : string;
  attribute c_cdc_type of \slave_rx.cl_enable_sync_support_i\ : label is "2'b01";
  attribute c_flop_input : string;
  attribute c_flop_input of \slave_rx.cl_enable_sync_support_i\ : label is "1'b0";
  attribute c_mtbf_stages : integer;
  attribute c_mtbf_stages of \slave_rx.cl_enable_sync_support_i\ : label is 3;
  attribute c_reset_state : string;
  attribute c_reset_state of \slave_rx.cl_enable_sync_support_i\ : label is "1'b1";
  attribute c_single_bit : string;
  attribute c_single_bit of \slave_rx.cl_enable_sync_support_i\ : label is "1'b1";
  attribute c_vector_width : string;
  attribute c_vector_width of \slave_rx.cl_enable_sync_support_i\ : label is "8'b00000010";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of \slave_rx.cl_enable_sync_support_i\ : label is "true";
  attribute BYTE_UI : integer;
  attribute BYTE_UI of \slave_rx.dphy_rx_fab_top\ : label is 6;
  attribute CL_ACTIVE_BYTE_UI : integer;
  attribute CL_ACTIVE_BYTE_UI of \slave_rx.dphy_rx_fab_top\ : label is 1;
  attribute C_CAL_MODE : string;
  attribute C_CAL_MODE of \slave_rx.dphy_rx_fab_top\ : label is "FIXED";
  attribute C_CLK_PREPARE_VAL : integer;
  attribute C_CLK_PREPARE_VAL of \slave_rx.dphy_rx_fab_top\ : label is 40;
  attribute C_CLK_SETTLE_VAL : integer;
  attribute C_CLK_SETTLE_VAL of \slave_rx.dphy_rx_fab_top\ : label is 95;
  attribute C_CLK_TERMEN_VAL : integer;
  attribute C_CLK_TERMEN_VAL of \slave_rx.dphy_rx_fab_top\ : label is 38;
  attribute C_CLK_ZERO_VAL : integer;
  attribute C_CLK_ZERO_VAL of \slave_rx.dphy_rx_fab_top\ : label is 205;
  attribute C_COMP_CYCLES : integer;
  attribute C_COMP_CYCLES of \slave_rx.dphy_rx_fab_top\ : label is 5;
  attribute C_DPHY_LANES : integer;
  attribute C_DPHY_LANES of \slave_rx.dphy_rx_fab_top\ : label is 4;
  attribute C_DPHY_MODE : string;
  attribute C_DPHY_MODE of \slave_rx.dphy_rx_fab_top\ : label is "SLAVE";
  attribute C_D_TERMEN_VAL : integer;
  attribute C_D_TERMEN_VAL of \slave_rx.dphy_rx_fab_top\ : label is 35;
  attribute C_EN_DEBUG_REGS : integer;
  attribute C_EN_DEBUG_REGS of \slave_rx.dphy_rx_fab_top\ : label is 0;
  attribute C_EN_EXT_TAP : integer;
  attribute C_EN_EXT_TAP of \slave_rx.dphy_rx_fab_top\ : label is 0;
  attribute C_EN_REGISTER : integer;
  attribute C_EN_REGISTER of \slave_rx.dphy_rx_fab_top\ : label is 1;
  attribute C_EN_TIMEOUT_REGS : integer;
  attribute C_EN_TIMEOUT_REGS of \slave_rx.dphy_rx_fab_top\ : label is 0;
  attribute C_EN_ULPS_WAKEUP_CNT : string;
  attribute C_EN_ULPS_WAKEUP_CNT of \slave_rx.dphy_rx_fab_top\ : label is "FALSE";
  attribute C_ESC_TIMEOUT : integer;
  attribute C_ESC_TIMEOUT of \slave_rx.dphy_rx_fab_top\ : label is 25600;
  attribute C_HS_LINE_RATE : integer;
  attribute C_HS_LINE_RATE of \slave_rx.dphy_rx_fab_top\ : label is 1188;
  attribute C_HS_RX_TIMEOUT : integer;
  attribute C_HS_RX_TIMEOUT of \slave_rx.dphy_rx_fab_top\ : label is 65541;
  attribute C_HS_SETTLE_VAL : integer;
  attribute C_HS_SETTLE_VAL of \slave_rx.dphy_rx_fab_top\ : label is 143;
  attribute C_HS_SKIP_VAL : integer;
  attribute C_HS_SKIP_VAL of \slave_rx.dphy_rx_fab_top\ : label is 40;
  attribute C_IDLY_TAP : integer;
  attribute C_IDLY_TAP of \slave_rx.dphy_rx_fab_top\ : label is 0;
  attribute C_INIT : integer;
  attribute C_INIT of \slave_rx.dphy_rx_fab_top\ : label is 100000;
  attribute C_IO_ADDR : string;
  attribute C_IO_ADDR of \slave_rx.dphy_rx_fab_top\ : label is "8'b00010100";
  attribute C_IS_7SERIES : string;
  attribute C_IS_7SERIES of \slave_rx.dphy_rx_fab_top\ : label is "FALSE";
  attribute C_LPX_PERIOD : integer;
  attribute C_LPX_PERIOD of \slave_rx.dphy_rx_fab_top\ : label is 50;
  attribute C_NO_INCR_TAPS : integer;
  attribute C_NO_INCR_TAPS of \slave_rx.dphy_rx_fab_top\ : label is 2;
  attribute C_RCVE_ALT_DESKEW_SEQ : string;
  attribute C_RCVE_ALT_DESKEW_SEQ of \slave_rx.dphy_rx_fab_top\ : label is "false";
  attribute C_RCVE_DESKEW_SEQ : string;
  attribute C_RCVE_DESKEW_SEQ of \slave_rx.dphy_rx_fab_top\ : label is "false";
  attribute C_STABLE_CLK_PERIOD : string;
  attribute C_STABLE_CLK_PERIOD of \slave_rx.dphy_rx_fab_top\ : label is "5.000000";
  attribute C_UI_IN_TAPS : integer;
  attribute C_UI_IN_TAPS of \slave_rx.dphy_rx_fab_top\ : label is 64;
  attribute C_WAKEUP : integer;
  attribute C_WAKEUP of \slave_rx.dphy_rx_fab_top\ : label is 1000;
  attribute DPHY_PRESET : string;
  attribute DPHY_PRESET of \slave_rx.dphy_rx_fab_top\ : label is "CSI2RX_XLNX";
  attribute DowngradeIPIdentifiedWarnings of \slave_rx.dphy_rx_fab_top\ : label is "yes";
  attribute INIT_TIMEOUT_L : integer;
  attribute INIT_TIMEOUT_L of \slave_rx.dphy_rx_fab_top\ : label is 19998;
  attribute KEEP_HIERARCHY of \slave_rx.dphy_rx_fab_top\ : label is "soft";
  attribute LPX_PERIOD_MIN : integer;
  attribute LPX_PERIOD_MIN of \slave_rx.dphy_rx_fab_top\ : label is 25;
  attribute LP_STATE_CNT : integer;
  attribute LP_STATE_CNT of \slave_rx.dphy_rx_fab_top\ : label is 2;
  attribute MTBF_SYNC_STAGES : integer;
  attribute MTBF_SYNC_STAGES of \slave_rx.dphy_rx_fab_top\ : label is 3;
  attribute RESET_PULSE_EXTN : string;
  attribute RESET_PULSE_EXTN of \slave_rx.dphy_rx_fab_top\ : label is "4'b0001";
  attribute SETTLE_TIMEOUT_L : integer;
  attribute SETTLE_TIMEOUT_L of \slave_rx.dphy_rx_fab_top\ : label is 24;
  attribute SUPPORT_LEVEL : integer;
  attribute SUPPORT_LEVEL of \slave_rx.dphy_rx_fab_top\ : label is 1;
  attribute UI10_VAL : integer;
  attribute UI10_VAL of \slave_rx.dphy_rx_fab_top\ : label is 8;
  attribute UI_VAL : integer;
  attribute UI_VAL of \slave_rx.dphy_rx_fab_top\ : label is 841;
  attribute is_du_within_envelope of \slave_rx.dphy_rx_fab_top\ : label is "true";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \slave_rx.rxbyteclkhs_buf\ : label is "BUFG";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \slave_rx.rxbyteclkhs_buf\ : label is "VCC:CE";
  attribute box_type : string;
  attribute box_type of \slave_rx.rxbyteclkhs_buf\ : label is "PRIMITIVE";
  attribute KEEP_HIERARCHY of \slave_rx.u_core_rst_coreclk_sync_rx_i\ : label is "soft";
  attribute c_init_val : string;
  attribute c_init_val of \slave_rx.u_core_rst_coreclk_sync_rx_i\ : label is "1'b1";
  attribute c_mtbf_stages_string : string;
  attribute c_mtbf_stages_string of \slave_rx.u_core_rst_coreclk_sync_rx_i\ : label is "5'b00010";
  attribute is_du_within_envelope of \slave_rx.u_core_rst_coreclk_sync_rx_i\ : label is "true";
  attribute ASSERT_ALL_RESETS : string;
  attribute ASSERT_ALL_RESETS of \slave_rx.u_rx_rst_logic\ : label is "3'b001";
  attribute DPHY_PRESET of \slave_rx.u_rx_rst_logic\ : label is "CSI2RX_XLNX";
  attribute DowngradeIPIdentifiedWarnings of \slave_rx.u_rx_rst_logic\ : label is "yes";
  attribute KEEP_HIERARCHY of \slave_rx.u_rx_rst_logic\ : label is "soft";
  attribute MMCM_USED : string;
  attribute MMCM_USED of \slave_rx.u_rx_rst_logic\ : label is "TRUE";
  attribute MTBF_SYNC_STAGES of \slave_rx.u_rx_rst_logic\ : label is 3;
  attribute RELEASE_MMCM_RESET : string;
  attribute RELEASE_MMCM_RESET of \slave_rx.u_rx_rst_logic\ : label is "3'b010";
  attribute RELEASE_TXPLL_RESET : string;
  attribute RELEASE_TXPLL_RESET of \slave_rx.u_rx_rst_logic\ : label is "3'b011";
  attribute RESET_FSM_DONE : string;
  attribute RESET_FSM_DONE of \slave_rx.u_rx_rst_logic\ : label is "3'b101";
  attribute RST_BEGIN : string;
  attribute RST_BEGIN of \slave_rx.u_rx_rst_logic\ : label is "3'b000";
  attribute STABLE_CLK_PERIOD : string;
  attribute STABLE_CLK_PERIOD of \slave_rx.u_rx_rst_logic\ : label is "5.000000";
  attribute TIME_OUT : integer;
  attribute TIME_OUT of \slave_rx.u_rx_rst_logic\ : label is 40000;
  attribute TXPLL_USED : string;
  attribute TXPLL_USED of \slave_rx.u_rx_rst_logic\ : label is "FALSE";
  attribute WAIT_FOR_ENABLE : string;
  attribute WAIT_FOR_ENABLE of \slave_rx.u_rx_rst_logic\ : label is "3'b100";
  attribute WATCHDOG_TIMEOUT : integer;
  attribute WATCHDOG_TIMEOUT of \slave_rx.u_rx_rst_logic\ : label is 200000;
  attribute is_du_within_envelope of \slave_rx.u_rx_rst_logic\ : label is "true";
begin
  rxbyteclkhs <= \^rxbyteclkhs\;
\slave_rx.bd_7289_phy_0_rx_hssio_i\: entity work.design_1_Vsp_core_0_0_bd_7289_phy_0_hssio_rx
     port map (
      bs_rst_dphy_in => bit_slc_rst_w,
      clk => '0',
      clk_rxn => clk_rxn,
      clk_rxp => clk_rxp,
      data_rxn0 => data_rxn(0),
      data_rxn1 => data_rxn(1),
      data_rxn2 => data_rxn(2),
      data_rxn3 => data_rxn(3),
      data_rxp0 => data_rxp(0),
      data_rxp1 => data_rxp(1),
      data_rxp2 => data_rxp(2),
      data_rxp3 => data_rxp(3),
      data_to_fabric_clk_rxn(7 downto 0) => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_data_to_fabric_clk_rxn_UNCONNECTED\(7 downto 0),
      data_to_fabric_clk_rxp(7 downto 0) => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_data_to_fabric_clk_rxp_UNCONNECTED\(7 downto 0),
      data_to_fabric_data_rxn0(7 downto 0) => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_data_to_fabric_data_rxn0_UNCONNECTED\(7 downto 0),
      data_to_fabric_data_rxn1(7 downto 0) => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_data_to_fabric_data_rxn1_UNCONNECTED\(7 downto 0),
      data_to_fabric_data_rxn2(7 downto 0) => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_data_to_fabric_data_rxn2_UNCONNECTED\(7 downto 0),
      data_to_fabric_data_rxn3(7 downto 0) => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_data_to_fabric_data_rxn3_UNCONNECTED\(7 downto 0),
      data_to_fabric_data_rxp0(7 downto 0) => rx_dl0_hs_dp_w(7 downto 0),
      data_to_fabric_data_rxp1(7 downto 0) => rx_dl1_hs_dp_w(7 downto 0),
      data_to_fabric_data_rxp2(7 downto 0) => rx_dl2_hs_dp_w(7 downto 0),
      data_to_fabric_data_rxp3(7 downto 0) => rx_dl3_hs_dp_w(7 downto 0),
      dly_rdy_bsc0 => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_dly_rdy_bsc0_UNCONNECTED\,
      dly_rdy_bsc1 => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_dly_rdy_bsc1_UNCONNECTED\,
      en_vtc_bsc0 => '1',
      en_vtc_bsc1 => '1',
      fifo_empty_0 => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_fifo_empty_0_UNCONNECTED\,
      fifo_empty_1 => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_fifo_empty_1_UNCONNECTED\,
      fifo_empty_2 => rx_dl0_fifo_empty_w,
      fifo_empty_3 => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_fifo_empty_3_UNCONNECTED\,
      fifo_empty_4 => rx_dl1_fifo_empty_w,
      fifo_empty_5 => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_fifo_empty_5_UNCONNECTED\,
      fifo_empty_6 => rx_dl2_fifo_empty_w,
      fifo_empty_7 => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_fifo_empty_7_UNCONNECTED\,
      fifo_empty_8 => rx_dl3_fifo_empty_w,
      fifo_empty_9 => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_fifo_empty_9_UNCONNECTED\,
      fifo_rd_clk_0 => \^rxbyteclkhs\,
      fifo_rd_clk_1 => '0',
      fifo_rd_clk_2 => '0',
      fifo_rd_clk_3 => '0',
      fifo_rd_clk_4 => '0',
      fifo_rd_clk_5 => '0',
      fifo_rd_clk_6 => '0',
      fifo_rd_clk_7 => '0',
      fifo_rd_clk_8 => '0',
      fifo_rd_clk_9 => '0',
      fifo_rd_en_0 => '1',
      fifo_rd_en_1 => '1',
      fifo_rd_en_2 => \slave_rx.bd_7289_phy_0_rx_hssio_i_i_1_n_0\,
      fifo_rd_en_3 => '0',
      fifo_rd_en_4 => \slave_rx.bd_7289_phy_0_rx_hssio_i_i_2_n_0\,
      fifo_rd_en_5 => '0',
      fifo_rd_en_6 => \slave_rx.bd_7289_phy_0_rx_hssio_i_i_3_n_0\,
      fifo_rd_en_7 => '0',
      fifo_rd_en_8 => \slave_rx.bd_7289_phy_0_rx_hssio_i_i_4_n_0\,
      fifo_rd_en_9 => '0',
      fifo_wr_clk_0 => div4_clk_t,
      hs_rx_disable(4) => rx_dl3_disable_ibuf_w,
      hs_rx_disable(3) => rx_dl2_disable_ibuf_w,
      hs_rx_disable(2) => rx_dl1_disable_ibuf_w,
      hs_rx_disable(1) => rx_dl0_disable_ibuf_w,
      hs_rx_disable(0) => rx_cl_disable_ibuf_w,
      lp_rx_disable(4 downto 0) => B"00000",
      lp_rx_o_n(4) => rx_dl3_lp_dn_w,
      lp_rx_o_n(3) => rx_dl2_lp_dn_w,
      lp_rx_o_n(2) => rx_dl1_lp_dn_w,
      lp_rx_o_n(1) => rx_dl0_lp_dn_w,
      lp_rx_o_n(0) => \slave_rx.bd_7289_phy_0_rx_hssio_i_n_9\,
      lp_rx_o_p(4) => rx_dl3_lp_dp_w,
      lp_rx_o_p(3) => rx_dl2_lp_dp_w,
      lp_rx_o_p(2) => rx_dl1_lp_dp_w,
      lp_rx_o_p(1) => rx_dl0_lp_dp_w,
      lp_rx_o_p(0) => \slave_rx.bd_7289_phy_0_rx_hssio_i_n_4\,
      pll0_clkout0 => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_pll0_clkout0_UNCONNECTED\,
      pll0_locked => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_pll0_locked_UNCONNECTED\,
      riu_clk => core_ref_clk_w,
      rst => phy_reset_w,
      rst_seq_done => phy_rdy_out,
      shared_pll0_clkoutphy_out => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_shared_pll0_clkoutphy_out_UNCONNECTED\,
      vtc_rdy_bsc0 => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_vtc_rdy_bsc0_UNCONNECTED\,
      vtc_rdy_bsc1 => \NLW_slave_rx.bd_7289_phy_0_rx_hssio_i_vtc_rdy_bsc1_UNCONNECTED\
    );
\slave_rx.bd_7289_phy_0_rx_hssio_i_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rx_dl0_fifo_empty_w,
      O => \slave_rx.bd_7289_phy_0_rx_hssio_i_i_1_n_0\
    );
\slave_rx.bd_7289_phy_0_rx_hssio_i_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rx_dl1_fifo_empty_w,
      O => \slave_rx.bd_7289_phy_0_rx_hssio_i_i_2_n_0\
    );
\slave_rx.bd_7289_phy_0_rx_hssio_i_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rx_dl2_fifo_empty_w,
      O => \slave_rx.bd_7289_phy_0_rx_hssio_i_i_3_n_0\
    );
\slave_rx.bd_7289_phy_0_rx_hssio_i_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rx_dl3_fifo_empty_w,
      O => \slave_rx.bd_7289_phy_0_rx_hssio_i_i_4_n_0\
    );
\slave_rx.cl_enable_sync_support_i\: entity work.design_1_Vsp_core_0_0_mipi_dphy_v4_3_13_rx_sync_cell
     port map (
      prmry_ack => \NLW_slave_rx.cl_enable_sync_support_i_prmry_ack_UNCONNECTED\,
      prmry_aclk => '0',
      prmry_in => cl_enable,
      prmry_rst_n => '1',
      prmry_vect_in(1 downto 0) => B"00",
      scndry_aclk => core_clk,
      scndry_out => cl_enable_sync,
      scndry_rst_n => '1',
      scndry_vect_out(1 downto 0) => \NLW_slave_rx.cl_enable_sync_support_i_scndry_vect_out_UNCONNECTED\(1 downto 0)
    );
\slave_rx.dphy_rx_fab_top\: entity work.design_1_Vsp_core_0_0_mipi_dphy_v4_3_13_rx_fab_top
     port map (
      alt_skew_calb(3 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_alt_skew_calb_UNCONNECTED\(3 downto 0),
      bit_slc_rst => bit_slc_rst_w,
      cal_done => '0',
      cal_pass => '0',
      calib_status_l0 => \NLW_slave_rx.dphy_rx_fab_top_calib_status_l0_UNCONNECTED\,
      calib_status_l1 => \NLW_slave_rx.dphy_rx_fab_top_calib_status_l1_UNCONNECTED\,
      calib_status_l2 => \NLW_slave_rx.dphy_rx_fab_top_calib_status_l2_UNCONNECTED\,
      calib_status_l3 => \NLW_slave_rx.dphy_rx_fab_top_calib_status_l3_UNCONNECTED\,
      cl_enable => cl_enable_sync,
      cl_rxclkactivehs => \NLW_slave_rx.dphy_rx_fab_top_cl_rxclkactivehs_UNCONNECTED\,
      cl_rxulpsclknot => \NLW_slave_rx.dphy_rx_fab_top_cl_rxulpsclknot_UNCONNECTED\,
      cl_stopstate => cl_stopstate,
      cl_ulpsactivenot => \NLW_slave_rx.dphy_rx_fab_top_cl_ulpsactivenot_UNCONNECTED\,
      clk_200m => '0',
      core_clk => core_clk,
      core_ref_clk => core_ref_clk_w,
      core_rst => core_rst_coreclk_sync,
      dl0_enable => '0',
      dl0_errcontrol => \NLW_slave_rx.dphy_rx_fab_top_dl0_errcontrol_UNCONNECTED\,
      dl0_erresc => \NLW_slave_rx.dphy_rx_fab_top_dl0_erresc_UNCONNECTED\,
      dl0_errsoths => dl0_errsoths,
      dl0_errsotsynchs => dl0_errsotsynchs,
      dl0_errsyncesc => \NLW_slave_rx.dphy_rx_fab_top_dl0_errsyncesc_UNCONNECTED\,
      dl0_forcerxmode => '0',
      dl0_rxactivehs => dl0_rxactivehs,
      dl0_rxclkesc => \NLW_slave_rx.dphy_rx_fab_top_dl0_rxclkesc_UNCONNECTED\,
      dl0_rxdataesc(7 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl0_rxdataesc_UNCONNECTED\(7 downto 0),
      dl0_rxdatahs(7 downto 0) => dl0_rxdatahs(7 downto 0),
      dl0_rxlpdtesc => \NLW_slave_rx.dphy_rx_fab_top_dl0_rxlpdtesc_UNCONNECTED\,
      dl0_rxskewcalhs => \NLW_slave_rx.dphy_rx_fab_top_dl0_rxskewcalhs_UNCONNECTED\,
      dl0_rxsynchs => dl0_rxsynchs,
      dl0_rxtriggeresc(3 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl0_rxtriggeresc_UNCONNECTED\(3 downto 0),
      dl0_rxulpsesc => \NLW_slave_rx.dphy_rx_fab_top_dl0_rxulpsesc_UNCONNECTED\,
      dl0_rxvalidesc => \NLW_slave_rx.dphy_rx_fab_top_dl0_rxvalidesc_UNCONNECTED\,
      dl0_rxvalidhs => dl0_rxvalidhs,
      dl0_stopstate => dl0_stopstate,
      dl0_ulpsactivenot => \NLW_slave_rx.dphy_rx_fab_top_dl0_ulpsactivenot_UNCONNECTED\,
      dl1_enable => '0',
      dl1_errcontrol => \NLW_slave_rx.dphy_rx_fab_top_dl1_errcontrol_UNCONNECTED\,
      dl1_erresc => \NLW_slave_rx.dphy_rx_fab_top_dl1_erresc_UNCONNECTED\,
      dl1_errsoths => dl1_errsoths,
      dl1_errsotsynchs => dl1_errsotsynchs,
      dl1_errsyncesc => \NLW_slave_rx.dphy_rx_fab_top_dl1_errsyncesc_UNCONNECTED\,
      dl1_forcerxmode => '0',
      dl1_rxactivehs => dl1_rxactivehs,
      dl1_rxclkesc => \NLW_slave_rx.dphy_rx_fab_top_dl1_rxclkesc_UNCONNECTED\,
      dl1_rxdataesc(7 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl1_rxdataesc_UNCONNECTED\(7 downto 0),
      dl1_rxdatahs(7 downto 0) => dl1_rxdatahs(7 downto 0),
      dl1_rxlpdtesc => \NLW_slave_rx.dphy_rx_fab_top_dl1_rxlpdtesc_UNCONNECTED\,
      dl1_rxskewcalhs => \NLW_slave_rx.dphy_rx_fab_top_dl1_rxskewcalhs_UNCONNECTED\,
      dl1_rxsynchs => dl1_rxsynchs,
      dl1_rxtriggeresc(3 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl1_rxtriggeresc_UNCONNECTED\(3 downto 0),
      dl1_rxulpsesc => \NLW_slave_rx.dphy_rx_fab_top_dl1_rxulpsesc_UNCONNECTED\,
      dl1_rxvalidesc => \NLW_slave_rx.dphy_rx_fab_top_dl1_rxvalidesc_UNCONNECTED\,
      dl1_rxvalidhs => dl1_rxvalidhs,
      dl1_stopstate => dl1_stopstate,
      dl1_ulpsactivenot => \NLW_slave_rx.dphy_rx_fab_top_dl1_ulpsactivenot_UNCONNECTED\,
      dl2_enable => '0',
      dl2_errcontrol => \NLW_slave_rx.dphy_rx_fab_top_dl2_errcontrol_UNCONNECTED\,
      dl2_erresc => \NLW_slave_rx.dphy_rx_fab_top_dl2_erresc_UNCONNECTED\,
      dl2_errsoths => dl2_errsoths,
      dl2_errsotsynchs => dl2_errsotsynchs,
      dl2_errsyncesc => \NLW_slave_rx.dphy_rx_fab_top_dl2_errsyncesc_UNCONNECTED\,
      dl2_forcerxmode => '0',
      dl2_rxactivehs => dl2_rxactivehs,
      dl2_rxclkesc => \NLW_slave_rx.dphy_rx_fab_top_dl2_rxclkesc_UNCONNECTED\,
      dl2_rxdataesc(7 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl2_rxdataesc_UNCONNECTED\(7 downto 0),
      dl2_rxdatahs(7 downto 0) => dl2_rxdatahs(7 downto 0),
      dl2_rxlpdtesc => \NLW_slave_rx.dphy_rx_fab_top_dl2_rxlpdtesc_UNCONNECTED\,
      dl2_rxskewcalhs => \NLW_slave_rx.dphy_rx_fab_top_dl2_rxskewcalhs_UNCONNECTED\,
      dl2_rxsynchs => dl2_rxsynchs,
      dl2_rxtriggeresc(3 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl2_rxtriggeresc_UNCONNECTED\(3 downto 0),
      dl2_rxulpsesc => \NLW_slave_rx.dphy_rx_fab_top_dl2_rxulpsesc_UNCONNECTED\,
      dl2_rxvalidesc => \NLW_slave_rx.dphy_rx_fab_top_dl2_rxvalidesc_UNCONNECTED\,
      dl2_rxvalidhs => dl2_rxvalidhs,
      dl2_stopstate => dl2_stopstate,
      dl2_ulpsactivenot => \NLW_slave_rx.dphy_rx_fab_top_dl2_ulpsactivenot_UNCONNECTED\,
      dl3_enable => '0',
      dl3_errcontrol => \NLW_slave_rx.dphy_rx_fab_top_dl3_errcontrol_UNCONNECTED\,
      dl3_erresc => \NLW_slave_rx.dphy_rx_fab_top_dl3_erresc_UNCONNECTED\,
      dl3_errsoths => dl3_errsoths,
      dl3_errsotsynchs => dl3_errsotsynchs,
      dl3_errsyncesc => \NLW_slave_rx.dphy_rx_fab_top_dl3_errsyncesc_UNCONNECTED\,
      dl3_forcerxmode => '0',
      dl3_rxactivehs => dl3_rxactivehs,
      dl3_rxclkesc => \NLW_slave_rx.dphy_rx_fab_top_dl3_rxclkesc_UNCONNECTED\,
      dl3_rxdataesc(7 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl3_rxdataesc_UNCONNECTED\(7 downto 0),
      dl3_rxdatahs(7 downto 0) => dl3_rxdatahs(7 downto 0),
      dl3_rxlpdtesc => \NLW_slave_rx.dphy_rx_fab_top_dl3_rxlpdtesc_UNCONNECTED\,
      dl3_rxskewcalhs => \NLW_slave_rx.dphy_rx_fab_top_dl3_rxskewcalhs_UNCONNECTED\,
      dl3_rxsynchs => dl3_rxsynchs,
      dl3_rxtriggeresc(3 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl3_rxtriggeresc_UNCONNECTED\(3 downto 0),
      dl3_rxulpsesc => \NLW_slave_rx.dphy_rx_fab_top_dl3_rxulpsesc_UNCONNECTED\,
      dl3_rxvalidesc => \NLW_slave_rx.dphy_rx_fab_top_dl3_rxvalidesc_UNCONNECTED\,
      dl3_rxvalidhs => dl3_rxvalidhs,
      dl3_stopstate => dl3_stopstate,
      dl3_ulpsactivenot => \NLW_slave_rx.dphy_rx_fab_top_dl3_ulpsactivenot_UNCONNECTED\,
      dl4_enable => '0',
      dl4_errcontrol => \NLW_slave_rx.dphy_rx_fab_top_dl4_errcontrol_UNCONNECTED\,
      dl4_erresc => \NLW_slave_rx.dphy_rx_fab_top_dl4_erresc_UNCONNECTED\,
      dl4_errsoths => \NLW_slave_rx.dphy_rx_fab_top_dl4_errsoths_UNCONNECTED\,
      dl4_errsotsynchs => \NLW_slave_rx.dphy_rx_fab_top_dl4_errsotsynchs_UNCONNECTED\,
      dl4_errsyncesc => \NLW_slave_rx.dphy_rx_fab_top_dl4_errsyncesc_UNCONNECTED\,
      dl4_forcerxmode => '0',
      dl4_rxactivehs => \NLW_slave_rx.dphy_rx_fab_top_dl4_rxactivehs_UNCONNECTED\,
      dl4_rxclkesc => \NLW_slave_rx.dphy_rx_fab_top_dl4_rxclkesc_UNCONNECTED\,
      dl4_rxdataesc(7 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl4_rxdataesc_UNCONNECTED\(7 downto 0),
      dl4_rxdatahs(7 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl4_rxdatahs_UNCONNECTED\(7 downto 0),
      dl4_rxlpdtesc => \NLW_slave_rx.dphy_rx_fab_top_dl4_rxlpdtesc_UNCONNECTED\,
      dl4_rxskewcalhs => \NLW_slave_rx.dphy_rx_fab_top_dl4_rxskewcalhs_UNCONNECTED\,
      dl4_rxsynchs => \NLW_slave_rx.dphy_rx_fab_top_dl4_rxsynchs_UNCONNECTED\,
      dl4_rxtriggeresc(3 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl4_rxtriggeresc_UNCONNECTED\(3 downto 0),
      dl4_rxulpsesc => \NLW_slave_rx.dphy_rx_fab_top_dl4_rxulpsesc_UNCONNECTED\,
      dl4_rxvalidesc => \NLW_slave_rx.dphy_rx_fab_top_dl4_rxvalidesc_UNCONNECTED\,
      dl4_rxvalidhs => \NLW_slave_rx.dphy_rx_fab_top_dl4_rxvalidhs_UNCONNECTED\,
      dl4_stopstate => \NLW_slave_rx.dphy_rx_fab_top_dl4_stopstate_UNCONNECTED\,
      dl4_ulpsactivenot => \NLW_slave_rx.dphy_rx_fab_top_dl4_ulpsactivenot_UNCONNECTED\,
      dl5_enable => '0',
      dl5_errcontrol => \NLW_slave_rx.dphy_rx_fab_top_dl5_errcontrol_UNCONNECTED\,
      dl5_erresc => \NLW_slave_rx.dphy_rx_fab_top_dl5_erresc_UNCONNECTED\,
      dl5_errsoths => \NLW_slave_rx.dphy_rx_fab_top_dl5_errsoths_UNCONNECTED\,
      dl5_errsotsynchs => \NLW_slave_rx.dphy_rx_fab_top_dl5_errsotsynchs_UNCONNECTED\,
      dl5_errsyncesc => \NLW_slave_rx.dphy_rx_fab_top_dl5_errsyncesc_UNCONNECTED\,
      dl5_forcerxmode => '0',
      dl5_rxactivehs => \NLW_slave_rx.dphy_rx_fab_top_dl5_rxactivehs_UNCONNECTED\,
      dl5_rxclkesc => \NLW_slave_rx.dphy_rx_fab_top_dl5_rxclkesc_UNCONNECTED\,
      dl5_rxdataesc(7 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl5_rxdataesc_UNCONNECTED\(7 downto 0),
      dl5_rxdatahs(7 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl5_rxdatahs_UNCONNECTED\(7 downto 0),
      dl5_rxlpdtesc => \NLW_slave_rx.dphy_rx_fab_top_dl5_rxlpdtesc_UNCONNECTED\,
      dl5_rxskewcalhs => \NLW_slave_rx.dphy_rx_fab_top_dl5_rxskewcalhs_UNCONNECTED\,
      dl5_rxsynchs => \NLW_slave_rx.dphy_rx_fab_top_dl5_rxsynchs_UNCONNECTED\,
      dl5_rxtriggeresc(3 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl5_rxtriggeresc_UNCONNECTED\(3 downto 0),
      dl5_rxulpsesc => \NLW_slave_rx.dphy_rx_fab_top_dl5_rxulpsesc_UNCONNECTED\,
      dl5_rxvalidesc => \NLW_slave_rx.dphy_rx_fab_top_dl5_rxvalidesc_UNCONNECTED\,
      dl5_rxvalidhs => \NLW_slave_rx.dphy_rx_fab_top_dl5_rxvalidhs_UNCONNECTED\,
      dl5_stopstate => \NLW_slave_rx.dphy_rx_fab_top_dl5_stopstate_UNCONNECTED\,
      dl5_ulpsactivenot => \NLW_slave_rx.dphy_rx_fab_top_dl5_ulpsactivenot_UNCONNECTED\,
      dl6_enable => '0',
      dl6_errcontrol => \NLW_slave_rx.dphy_rx_fab_top_dl6_errcontrol_UNCONNECTED\,
      dl6_erresc => \NLW_slave_rx.dphy_rx_fab_top_dl6_erresc_UNCONNECTED\,
      dl6_errsoths => \NLW_slave_rx.dphy_rx_fab_top_dl6_errsoths_UNCONNECTED\,
      dl6_errsotsynchs => \NLW_slave_rx.dphy_rx_fab_top_dl6_errsotsynchs_UNCONNECTED\,
      dl6_errsyncesc => \NLW_slave_rx.dphy_rx_fab_top_dl6_errsyncesc_UNCONNECTED\,
      dl6_forcerxmode => '0',
      dl6_rxactivehs => \NLW_slave_rx.dphy_rx_fab_top_dl6_rxactivehs_UNCONNECTED\,
      dl6_rxclkesc => \NLW_slave_rx.dphy_rx_fab_top_dl6_rxclkesc_UNCONNECTED\,
      dl6_rxdataesc(7 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl6_rxdataesc_UNCONNECTED\(7 downto 0),
      dl6_rxdatahs(7 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl6_rxdatahs_UNCONNECTED\(7 downto 0),
      dl6_rxlpdtesc => \NLW_slave_rx.dphy_rx_fab_top_dl6_rxlpdtesc_UNCONNECTED\,
      dl6_rxskewcalhs => \NLW_slave_rx.dphy_rx_fab_top_dl6_rxskewcalhs_UNCONNECTED\,
      dl6_rxsynchs => \NLW_slave_rx.dphy_rx_fab_top_dl6_rxsynchs_UNCONNECTED\,
      dl6_rxtriggeresc(3 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl6_rxtriggeresc_UNCONNECTED\(3 downto 0),
      dl6_rxulpsesc => \NLW_slave_rx.dphy_rx_fab_top_dl6_rxulpsesc_UNCONNECTED\,
      dl6_rxvalidesc => \NLW_slave_rx.dphy_rx_fab_top_dl6_rxvalidesc_UNCONNECTED\,
      dl6_rxvalidhs => \NLW_slave_rx.dphy_rx_fab_top_dl6_rxvalidhs_UNCONNECTED\,
      dl6_stopstate => \NLW_slave_rx.dphy_rx_fab_top_dl6_stopstate_UNCONNECTED\,
      dl6_ulpsactivenot => \NLW_slave_rx.dphy_rx_fab_top_dl6_ulpsactivenot_UNCONNECTED\,
      dl7_enable => '0',
      dl7_errcontrol => \NLW_slave_rx.dphy_rx_fab_top_dl7_errcontrol_UNCONNECTED\,
      dl7_erresc => \NLW_slave_rx.dphy_rx_fab_top_dl7_erresc_UNCONNECTED\,
      dl7_errsoths => \NLW_slave_rx.dphy_rx_fab_top_dl7_errsoths_UNCONNECTED\,
      dl7_errsotsynchs => \NLW_slave_rx.dphy_rx_fab_top_dl7_errsotsynchs_UNCONNECTED\,
      dl7_errsyncesc => \NLW_slave_rx.dphy_rx_fab_top_dl7_errsyncesc_UNCONNECTED\,
      dl7_forcerxmode => '0',
      dl7_rxactivehs => \NLW_slave_rx.dphy_rx_fab_top_dl7_rxactivehs_UNCONNECTED\,
      dl7_rxclkesc => \NLW_slave_rx.dphy_rx_fab_top_dl7_rxclkesc_UNCONNECTED\,
      dl7_rxdataesc(7 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl7_rxdataesc_UNCONNECTED\(7 downto 0),
      dl7_rxdatahs(7 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl7_rxdatahs_UNCONNECTED\(7 downto 0),
      dl7_rxlpdtesc => \NLW_slave_rx.dphy_rx_fab_top_dl7_rxlpdtesc_UNCONNECTED\,
      dl7_rxskewcalhs => \NLW_slave_rx.dphy_rx_fab_top_dl7_rxskewcalhs_UNCONNECTED\,
      dl7_rxsynchs => \NLW_slave_rx.dphy_rx_fab_top_dl7_rxsynchs_UNCONNECTED\,
      dl7_rxtriggeresc(3 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_dl7_rxtriggeresc_UNCONNECTED\(3 downto 0),
      dl7_rxulpsesc => \NLW_slave_rx.dphy_rx_fab_top_dl7_rxulpsesc_UNCONNECTED\,
      dl7_rxvalidesc => \NLW_slave_rx.dphy_rx_fab_top_dl7_rxvalidesc_UNCONNECTED\,
      dl7_rxvalidhs => \NLW_slave_rx.dphy_rx_fab_top_dl7_rxvalidhs_UNCONNECTED\,
      dl7_stopstate => \NLW_slave_rx.dphy_rx_fab_top_dl7_stopstate_UNCONNECTED\,
      dl7_ulpsactivenot => \NLW_slave_rx.dphy_rx_fab_top_dl7_ulpsactivenot_UNCONNECTED\,
      dly_ctrl_rdy => '0',
      dphy_en_out => dphy_en_w,
      dphy_srst_out => dphy_srst_w,
      idelay_load => \NLW_slave_rx.dphy_rx_fab_top_idelay_load_UNCONNECTED\,
      idelay_ready => '0',
      idelay_tap_value(8 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_idelay_tap_value_UNCONNECTED\(8 downto 0),
      idly_tap_val(4 downto 0) => B"00000",
      init_done => \NLW_slave_rx.dphy_rx_fab_top_init_done_UNCONNECTED\,
      init_periodic_skew_calb(3 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_init_periodic_skew_calb_UNCONNECTED\(3 downto 0),
      lane0_tap(4 downto 0) => B"00000",
      lane1_tap(4 downto 0) => B"00000",
      lane2_tap(4 downto 0) => B"00000",
      lane3_tap(4 downto 0) => B"00000",
      lane4_tap(4 downto 0) => B"00000",
      lane5_tap(4 downto 0) => B"00000",
      lane6_tap(4 downto 0) => B"00000",
      lane7_tap(4 downto 0) => B"00000",
      phy_ready => phy_rdy_out,
      phy_rst => \NLW_slave_rx.dphy_rx_fab_top_phy_rst_UNCONNECTED\,
      reg_cal_start => \NLW_slave_rx.dphy_rx_fab_top_reg_cal_start_UNCONNECTED\,
      riu_addr_l0(5 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_riu_addr_l0_UNCONNECTED\(5 downto 0),
      riu_addr_l1(5 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_riu_addr_l1_UNCONNECTED\(5 downto 0),
      riu_addr_l2(5 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_riu_addr_l2_UNCONNECTED\(5 downto 0),
      riu_addr_l3(5 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_riu_addr_l3_UNCONNECTED\(5 downto 0),
      riu_nibble_sel_l0 => \NLW_slave_rx.dphy_rx_fab_top_riu_nibble_sel_l0_UNCONNECTED\,
      riu_nibble_sel_l1 => \NLW_slave_rx.dphy_rx_fab_top_riu_nibble_sel_l1_UNCONNECTED\,
      riu_nibble_sel_l2 => \NLW_slave_rx.dphy_rx_fab_top_riu_nibble_sel_l2_UNCONNECTED\,
      riu_nibble_sel_l3 => \NLW_slave_rx.dphy_rx_fab_top_riu_nibble_sel_l3_UNCONNECTED\,
      riu_rd_data_l0(15 downto 0) => B"0000000000000000",
      riu_rd_data_l1(15 downto 0) => B"0000000000000000",
      riu_rd_data_l2(15 downto 0) => B"0000000000000000",
      riu_rd_data_l3(15 downto 0) => B"0000000000000000",
      riu_valid_l0 => '0',
      riu_valid_l1 => '0',
      riu_valid_l2 => '0',
      riu_valid_l3 => '0',
      riu_wr_data_l0(15 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_riu_wr_data_l0_UNCONNECTED\(15 downto 0),
      riu_wr_data_l1(15 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_riu_wr_data_l1_UNCONNECTED\(15 downto 0),
      riu_wr_data_l2(15 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_riu_wr_data_l2_UNCONNECTED\(15 downto 0),
      riu_wr_data_l3(15 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_riu_wr_data_l3_UNCONNECTED\(15 downto 0),
      riu_wr_en_l0 => \NLW_slave_rx.dphy_rx_fab_top_riu_wr_en_l0_UNCONNECTED\,
      riu_wr_en_l1 => \NLW_slave_rx.dphy_rx_fab_top_riu_wr_en_l1_UNCONNECTED\,
      riu_wr_en_l2 => \NLW_slave_rx.dphy_rx_fab_top_riu_wr_en_l2_UNCONNECTED\,
      riu_wr_en_l3 => \NLW_slave_rx.dphy_rx_fab_top_riu_wr_en_l3_UNCONNECTED\,
      rx_cl_disable_ibuf => rx_cl_disable_ibuf_w,
      rx_cl_en_hs_lpn => \NLW_slave_rx.dphy_rx_fab_top_rx_cl_en_hs_lpn_UNCONNECTED\,
      rx_cl_fifo_empty => '0',
      rx_cl_fifo_rd_clk => \NLW_slave_rx.dphy_rx_fab_top_rx_cl_fifo_rd_clk_UNCONNECTED\,
      rx_cl_fifo_rd_en => \NLW_slave_rx.dphy_rx_fab_top_rx_cl_fifo_rd_en_UNCONNECTED\,
      rx_cl_hs_dp(7 downto 0) => B"00000000",
      rx_cl_lp_dn => \slave_rx.bd_7289_phy_0_rx_hssio_i_n_9\,
      rx_cl_lp_dp => \slave_rx.bd_7289_phy_0_rx_hssio_i_n_4\,
      rx_div4_clk => \^rxbyteclkhs\,
      rx_dl0_disable_ibuf => rx_dl0_disable_ibuf_w,
      rx_dl0_en_hs_lpn => \NLW_slave_rx.dphy_rx_fab_top_rx_dl0_en_hs_lpn_UNCONNECTED\,
      rx_dl0_fifo_empty => '0',
      rx_dl0_fifo_rd_clk => \NLW_slave_rx.dphy_rx_fab_top_rx_dl0_fifo_rd_clk_UNCONNECTED\,
      rx_dl0_fifo_rd_en => \NLW_slave_rx.dphy_rx_fab_top_rx_dl0_fifo_rd_en_UNCONNECTED\,
      rx_dl0_hs_dp(7 downto 0) => rx_dl0_hs_dp_w(7 downto 0),
      rx_dl0_lp_dn => rx_dl0_lp_dn_w,
      rx_dl0_lp_dp => rx_dl0_lp_dp_w,
      rx_dl1_disable_ibuf => rx_dl1_disable_ibuf_w,
      rx_dl1_en_hs_lpn => \NLW_slave_rx.dphy_rx_fab_top_rx_dl1_en_hs_lpn_UNCONNECTED\,
      rx_dl1_fifo_empty => '0',
      rx_dl1_fifo_rd_clk => \NLW_slave_rx.dphy_rx_fab_top_rx_dl1_fifo_rd_clk_UNCONNECTED\,
      rx_dl1_fifo_rd_en => \NLW_slave_rx.dphy_rx_fab_top_rx_dl1_fifo_rd_en_UNCONNECTED\,
      rx_dl1_hs_dp(7 downto 0) => rx_dl1_hs_dp_w(7 downto 0),
      rx_dl1_lp_dn => rx_dl1_lp_dn_w,
      rx_dl1_lp_dp => rx_dl1_lp_dp_w,
      rx_dl2_disable_ibuf => rx_dl2_disable_ibuf_w,
      rx_dl2_en_hs_lpn => \NLW_slave_rx.dphy_rx_fab_top_rx_dl2_en_hs_lpn_UNCONNECTED\,
      rx_dl2_fifo_empty => '0',
      rx_dl2_fifo_rd_clk => \NLW_slave_rx.dphy_rx_fab_top_rx_dl2_fifo_rd_clk_UNCONNECTED\,
      rx_dl2_fifo_rd_en => \NLW_slave_rx.dphy_rx_fab_top_rx_dl2_fifo_rd_en_UNCONNECTED\,
      rx_dl2_hs_dp(7 downto 0) => rx_dl2_hs_dp_w(7 downto 0),
      rx_dl2_lp_dn => rx_dl2_lp_dn_w,
      rx_dl2_lp_dp => rx_dl2_lp_dp_w,
      rx_dl3_disable_ibuf => rx_dl3_disable_ibuf_w,
      rx_dl3_en_hs_lpn => \NLW_slave_rx.dphy_rx_fab_top_rx_dl3_en_hs_lpn_UNCONNECTED\,
      rx_dl3_fifo_empty => '0',
      rx_dl3_fifo_rd_clk => \NLW_slave_rx.dphy_rx_fab_top_rx_dl3_fifo_rd_clk_UNCONNECTED\,
      rx_dl3_fifo_rd_en => \NLW_slave_rx.dphy_rx_fab_top_rx_dl3_fifo_rd_en_UNCONNECTED\,
      rx_dl3_hs_dp(7 downto 0) => rx_dl3_hs_dp_w(7 downto 0),
      rx_dl3_lp_dn => rx_dl3_lp_dn_w,
      rx_dl3_lp_dp => rx_dl3_lp_dp_w,
      rx_dl4_disable_ibuf => \NLW_slave_rx.dphy_rx_fab_top_rx_dl4_disable_ibuf_UNCONNECTED\,
      rx_dl4_en_hs_lpn => \NLW_slave_rx.dphy_rx_fab_top_rx_dl4_en_hs_lpn_UNCONNECTED\,
      rx_dl4_fifo_empty => '0',
      rx_dl4_fifo_rd_clk => \NLW_slave_rx.dphy_rx_fab_top_rx_dl4_fifo_rd_clk_UNCONNECTED\,
      rx_dl4_fifo_rd_en => \NLW_slave_rx.dphy_rx_fab_top_rx_dl4_fifo_rd_en_UNCONNECTED\,
      rx_dl4_hs_dp(7 downto 0) => B"00000000",
      rx_dl4_lp_dn => '0',
      rx_dl4_lp_dp => '0',
      rx_dl5_disable_ibuf => \NLW_slave_rx.dphy_rx_fab_top_rx_dl5_disable_ibuf_UNCONNECTED\,
      rx_dl5_en_hs_lpn => \NLW_slave_rx.dphy_rx_fab_top_rx_dl5_en_hs_lpn_UNCONNECTED\,
      rx_dl5_fifo_empty => '0',
      rx_dl5_fifo_rd_clk => \NLW_slave_rx.dphy_rx_fab_top_rx_dl5_fifo_rd_clk_UNCONNECTED\,
      rx_dl5_fifo_rd_en => \NLW_slave_rx.dphy_rx_fab_top_rx_dl5_fifo_rd_en_UNCONNECTED\,
      rx_dl5_hs_dp(7 downto 0) => B"00000000",
      rx_dl5_lp_dn => '0',
      rx_dl5_lp_dp => '0',
      rx_dl6_disable_ibuf => \NLW_slave_rx.dphy_rx_fab_top_rx_dl6_disable_ibuf_UNCONNECTED\,
      rx_dl6_en_hs_lpn => \NLW_slave_rx.dphy_rx_fab_top_rx_dl6_en_hs_lpn_UNCONNECTED\,
      rx_dl6_fifo_empty => '0',
      rx_dl6_fifo_rd_clk => \NLW_slave_rx.dphy_rx_fab_top_rx_dl6_fifo_rd_clk_UNCONNECTED\,
      rx_dl6_fifo_rd_en => \NLW_slave_rx.dphy_rx_fab_top_rx_dl6_fifo_rd_en_UNCONNECTED\,
      rx_dl6_hs_dp(7 downto 0) => B"00000000",
      rx_dl6_lp_dn => '0',
      rx_dl6_lp_dp => '0',
      rx_dl7_disable_ibuf => \NLW_slave_rx.dphy_rx_fab_top_rx_dl7_disable_ibuf_UNCONNECTED\,
      rx_dl7_en_hs_lpn => \NLW_slave_rx.dphy_rx_fab_top_rx_dl7_en_hs_lpn_UNCONNECTED\,
      rx_dl7_fifo_empty => '0',
      rx_dl7_fifo_rd_clk => \NLW_slave_rx.dphy_rx_fab_top_rx_dl7_fifo_rd_clk_UNCONNECTED\,
      rx_dl7_fifo_rd_en => \NLW_slave_rx.dphy_rx_fab_top_rx_dl7_fifo_rd_en_UNCONNECTED\,
      rx_dl7_hs_dp(7 downto 0) => B"00000000",
      rx_dl7_lp_dn => '0',
      rx_dl7_lp_dp => '0',
      s_axi_aclk => '0',
      s_axi_araddr(6 downto 2) => s_axi_araddr(4 downto 0),
      s_axi_araddr(1 downto 0) => B"00",
      s_axi_aresetn => s_axi_aresetn,
      s_axi_arready => s_axi_arready,
      s_axi_arvalid => s_axi_arvalid,
      s_axi_awaddr(6 downto 2) => s_axi_awaddr(4 downto 0),
      s_axi_awaddr(1 downto 0) => B"00",
      s_axi_awready => s_axi_awready,
      s_axi_awvalid => s_axi_awvalid,
      s_axi_bready => s_axi_bready,
      s_axi_bresp(1 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_s_axi_bresp_UNCONNECTED\(1 downto 0),
      s_axi_bvalid => s_axi_bvalid,
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      s_axi_rready => s_axi_rready,
      s_axi_rresp(1 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_s_axi_rresp_UNCONNECTED\(1 downto 0),
      s_axi_rvalid => s_axi_rvalid,
      s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
      s_axi_wready => s_axi_wready,
      s_axi_wstrb(3 downto 0) => B"0000",
      s_axi_wvalid => s_axi_wvalid,
      sys_rst_byteclk_out => \NLW_slave_rx.dphy_rx_fab_top_sys_rst_byteclk_out_UNCONNECTED\,
      system_rst_byteclk_in => '0',
      system_rst_in => \slave_rx.u_rx_rst_logic_n_6\,
      system_rst_phybyteclk_in => '0',
      tap_comp_res(7 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_tap_comp_res_UNCONNECTED\(7 downto 0),
      tap_comp_rst => '0',
      tap_val_dyn_out(63 downto 0) => \NLW_slave_rx.dphy_rx_fab_top_tap_val_dyn_out_UNCONNECTED\(63 downto 0)
    );
\slave_rx.rxbyteclkhs_buf\: unisim.vcomponents.BUFGCE
    generic map(
      CE_TYPE => "ASYNC",
      SIM_DEVICE => "ULTRASCALE_PLUS"
    )
        port map (
      CE => '1',
      I => div4_clk_t,
      O => \^rxbyteclkhs\
    );
\slave_rx.u_core_rst_coreclk_sync_rx_i\: entity work.design_1_Vsp_core_0_0_mipi_dphy_v4_3_13_rx_rst_sync
     port map (
      prmry_in => core_rst,
      scndry_aclk => core_clk,
      scndry_out => core_rst_coreclk_sync
    );
\slave_rx.u_rx_rst_logic\: entity work.design_1_Vsp_core_0_0_mipi_dphy_v4_3_13_rx_rst_logic
     port map (
      cl_enable => cl_enable_sync,
      core_clk => core_clk,
      core_rst => core_rst_coreclk_sync,
      dphyen => dphy_en_w,
      mmcm_lock => '1',
      mmcm_rst => \NLW_slave_rx.u_rx_rst_logic_mmcm_rst_UNCONNECTED\,
      phy_rdy => '1',
      phy_rst => phy_reset_w,
      srst => dphy_srst_w,
      system_rst => \slave_rx.u_rx_rst_logic_n_6\,
      system_rst_byteclk => \NLW_slave_rx.u_rx_rst_logic_system_rst_byteclk_UNCONNECTED\,
      system_rst_div4clk => \NLW_slave_rx.u_rx_rst_logic_system_rst_div4clk_UNCONNECTED\,
      system_rst_escclk => \NLW_slave_rx.u_rx_rst_logic_system_rst_escclk_UNCONNECTED\,
      txpll_lock => '1',
      txpll_rst => \NLW_slave_rx.u_rx_rst_logic_txpll_rst_UNCONNECTED\
    );
end STRUCTURE;
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_size2kB_a32b64 is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    aclk_sig : in STD_LOGIC;
    ena : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 22 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_size2kB_a32b64 : entity is "Dpbram_size2kB_a32b64";
end design_1_Vsp_core_0_0_Dpbram_size2kB_a32b64;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_size2kB_a32b64 is
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size2kB_a32b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
myMnfcore: entity work.design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a32b64
     port map (
      addra(8 downto 0) => Q(8 downto 0),
      addrb(7 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(31) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(22),
      dina(30 downto 27) => B"0000",
      dina(26 downto 16) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(21 downto 11),
      dina(15 downto 11) => B"00000",
      dina(10 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(10 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(31 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(31 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      ena => ena,
      enb => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0),
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_size2kB_a64b64 is
  port (
    D : out STD_LOGIC_VECTOR ( 51 downto 0 );
    \acc0_lcl_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    aclk_sig : in STD_LOGIC;
    ena : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 59 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \acc2_reg[19]\ : in STD_LOGIC;
    \acc0_lcl_reg[19]_i_2_0\ : in STD_LOGIC;
    \acc0_lcl_reg[19]_i_2_1\ : in STD_LOGIC;
    \acc2_lcl_reg[19]_i_2_0\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
    \acc1_lcl_reg[19]_i_2_0\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
    \acc0_lcl_reg[19]_i_2_2\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
    \dwrAccbuf_reg[15]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    DI : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \acc0_lcl_reg[7]_i_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \acc2_lcl_reg[15]_i_2_0\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
    \acc1_lcl_reg[7]_i_2_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_size2kB_a64b64 : entity is "Dpbram_size2kB_a64b64";
end design_1_Vsp_core_0_0_Dpbram_size2kB_a64b64;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_size2kB_a64b64 is
  signal acc0_lcl : STD_LOGIC_VECTOR ( 19 downto 12 );
  signal \acc0_lcl[15]_i_11_n_0\ : STD_LOGIC;
  signal \acc0_lcl[15]_i_12_n_0\ : STD_LOGIC;
  signal \acc0_lcl[15]_i_13_n_0\ : STD_LOGIC;
  signal \acc0_lcl[15]_i_14_n_0\ : STD_LOGIC;
  signal \acc0_lcl_reg[15]_i_2_n_0\ : STD_LOGIC;
  signal \acc0_lcl_reg[15]_i_2_n_1\ : STD_LOGIC;
  signal \acc0_lcl_reg[15]_i_2_n_2\ : STD_LOGIC;
  signal \acc0_lcl_reg[15]_i_2_n_3\ : STD_LOGIC;
  signal \acc0_lcl_reg[15]_i_2_n_4\ : STD_LOGIC;
  signal \acc0_lcl_reg[15]_i_2_n_5\ : STD_LOGIC;
  signal \acc0_lcl_reg[15]_i_2_n_6\ : STD_LOGIC;
  signal \acc0_lcl_reg[15]_i_2_n_7\ : STD_LOGIC;
  signal \acc0_lcl_reg[19]_i_2_n_5\ : STD_LOGIC;
  signal \acc0_lcl_reg[19]_i_2_n_6\ : STD_LOGIC;
  signal \acc0_lcl_reg[19]_i_2_n_7\ : STD_LOGIC;
  signal acc1_lcl : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal \acc1_lcl[15]_i_11_n_0\ : STD_LOGIC;
  signal \acc1_lcl[15]_i_12_n_0\ : STD_LOGIC;
  signal \acc1_lcl[15]_i_13_n_0\ : STD_LOGIC;
  signal \acc1_lcl[15]_i_14_n_0\ : STD_LOGIC;
  signal \acc1_lcl[7]_i_11_n_0\ : STD_LOGIC;
  signal \acc1_lcl[7]_i_12_n_0\ : STD_LOGIC;
  signal \acc1_lcl[7]_i_13_n_0\ : STD_LOGIC;
  signal \acc1_lcl[7]_i_14_n_0\ : STD_LOGIC;
  signal \acc1_lcl[7]_i_15_n_0\ : STD_LOGIC;
  signal \acc1_lcl[7]_i_16_n_0\ : STD_LOGIC;
  signal \acc1_lcl[7]_i_17_n_0\ : STD_LOGIC;
  signal \acc1_lcl[7]_i_18_n_0\ : STD_LOGIC;
  signal \acc1_lcl_reg[15]_i_2_n_0\ : STD_LOGIC;
  signal \acc1_lcl_reg[15]_i_2_n_1\ : STD_LOGIC;
  signal \acc1_lcl_reg[15]_i_2_n_2\ : STD_LOGIC;
  signal \acc1_lcl_reg[15]_i_2_n_3\ : STD_LOGIC;
  signal \acc1_lcl_reg[15]_i_2_n_4\ : STD_LOGIC;
  signal \acc1_lcl_reg[15]_i_2_n_5\ : STD_LOGIC;
  signal \acc1_lcl_reg[15]_i_2_n_6\ : STD_LOGIC;
  signal \acc1_lcl_reg[15]_i_2_n_7\ : STD_LOGIC;
  signal \acc1_lcl_reg[19]_i_2_n_5\ : STD_LOGIC;
  signal \acc1_lcl_reg[19]_i_2_n_6\ : STD_LOGIC;
  signal \acc1_lcl_reg[19]_i_2_n_7\ : STD_LOGIC;
  signal \acc1_lcl_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \acc1_lcl_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \acc1_lcl_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \acc1_lcl_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \acc1_lcl_reg[7]_i_2_n_4\ : STD_LOGIC;
  signal \acc1_lcl_reg[7]_i_2_n_5\ : STD_LOGIC;
  signal \acc1_lcl_reg[7]_i_2_n_6\ : STD_LOGIC;
  signal \acc1_lcl_reg[7]_i_2_n_7\ : STD_LOGIC;
  signal acc2_lcl : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal \acc2_lcl[15]_i_11_n_0\ : STD_LOGIC;
  signal \acc2_lcl[15]_i_12_n_0\ : STD_LOGIC;
  signal \acc2_lcl[15]_i_13_n_0\ : STD_LOGIC;
  signal \acc2_lcl[15]_i_14_n_0\ : STD_LOGIC;
  signal \acc2_lcl[7]_i_11_n_0\ : STD_LOGIC;
  signal \acc2_lcl[7]_i_12_n_0\ : STD_LOGIC;
  signal \acc2_lcl[7]_i_13_n_0\ : STD_LOGIC;
  signal \acc2_lcl[7]_i_14_n_0\ : STD_LOGIC;
  signal \acc2_lcl[7]_i_15_n_0\ : STD_LOGIC;
  signal \acc2_lcl[7]_i_16_n_0\ : STD_LOGIC;
  signal \acc2_lcl[7]_i_17_n_0\ : STD_LOGIC;
  signal \acc2_lcl[7]_i_18_n_0\ : STD_LOGIC;
  signal \acc2_lcl_reg[15]_i_2_n_0\ : STD_LOGIC;
  signal \acc2_lcl_reg[15]_i_2_n_1\ : STD_LOGIC;
  signal \acc2_lcl_reg[15]_i_2_n_2\ : STD_LOGIC;
  signal \acc2_lcl_reg[15]_i_2_n_3\ : STD_LOGIC;
  signal \acc2_lcl_reg[15]_i_2_n_4\ : STD_LOGIC;
  signal \acc2_lcl_reg[15]_i_2_n_5\ : STD_LOGIC;
  signal \acc2_lcl_reg[15]_i_2_n_6\ : STD_LOGIC;
  signal \acc2_lcl_reg[15]_i_2_n_7\ : STD_LOGIC;
  signal \acc2_lcl_reg[19]_i_2_n_5\ : STD_LOGIC;
  signal \acc2_lcl_reg[19]_i_2_n_6\ : STD_LOGIC;
  signal \acc2_lcl_reg[19]_i_2_n_7\ : STD_LOGIC;
  signal \acc2_lcl_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \acc2_lcl_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \acc2_lcl_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \acc2_lcl_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \acc2_lcl_reg[7]_i_2_n_4\ : STD_LOGIC;
  signal \acc2_lcl_reg[7]_i_2_n_5\ : STD_LOGIC;
  signal \acc2_lcl_reg[7]_i_2_n_6\ : STD_LOGIC;
  signal \acc2_lcl_reg[7]_i_2_n_7\ : STD_LOGIC;
  signal drdAccbufB : STD_LOGIC_VECTOR ( 59 downto 0 );
  signal dwrAccbuf : STD_LOGIC_VECTOR ( 59 downto 8 );
  signal enB : STD_LOGIC;
  signal \NLW_acc0_lcl_reg[19]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_acc0_lcl_reg[19]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_acc1_lcl_reg[19]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_acc1_lcl_reg[19]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_acc2_lcl_reg[19]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_acc2_lcl_reg[19]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_myMnfcore_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 60 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \acc0_lcl[8]_i_1\ : label is "soft_lutpair1627";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \acc0_lcl_reg[15]_i_2\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \acc0_lcl_reg[15]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}";
  attribute ADDER_THRESHOLD of \acc0_lcl_reg[19]_i_2\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS of \acc0_lcl_reg[19]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}";
  attribute ADDER_THRESHOLD of \acc1_lcl_reg[15]_i_2\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS of \acc1_lcl_reg[15]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}";
  attribute ADDER_THRESHOLD of \acc1_lcl_reg[19]_i_2\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS of \acc1_lcl_reg[19]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}";
  attribute ADDER_THRESHOLD of \acc1_lcl_reg[7]_i_2\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS of \acc1_lcl_reg[7]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}";
  attribute ADDER_THRESHOLD of \acc2_lcl_reg[15]_i_2\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS of \acc2_lcl_reg[15]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}";
  attribute ADDER_THRESHOLD of \acc2_lcl_reg[19]_i_2\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS of \acc2_lcl_reg[19]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}";
  attribute ADDER_THRESHOLD of \acc2_lcl_reg[7]_i_2\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS of \acc2_lcl_reg[7]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}";
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size2kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
  attribute SOFT_HLUTNM of \myMnfcore_i_1__1\ : label is "soft_lutpair1627";
begin
\acc0_lcl[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(10),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(2)
    );
\acc0_lcl[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(11),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(3)
    );
\acc0_lcl[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(12),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(4)
    );
\acc0_lcl[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(13),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(5)
    );
\acc0_lcl[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(14),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(6)
    );
\acc0_lcl[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(15),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(7)
    );
\acc0_lcl[15]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(12),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_2\(12),
      O => acc0_lcl(12)
    );
\acc0_lcl[15]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => DI(3),
      I1 => \acc0_lcl_reg[19]_i_2_2\(11),
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_0\,
      I4 => drdAccbufB(11),
      O => \acc0_lcl[15]_i_11_n_0\
    );
\acc0_lcl[15]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => DI(2),
      I1 => \acc0_lcl_reg[19]_i_2_2\(10),
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_0\,
      I4 => drdAccbufB(10),
      O => \acc0_lcl[15]_i_12_n_0\
    );
\acc0_lcl[15]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => DI(1),
      I1 => \acc0_lcl_reg[19]_i_2_2\(9),
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_0\,
      I4 => drdAccbufB(9),
      O => \acc0_lcl[15]_i_13_n_0\
    );
\acc0_lcl[15]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => DI(0),
      I1 => \acc0_lcl_reg[19]_i_2_2\(8),
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_0\,
      I4 => drdAccbufB(8),
      O => \acc0_lcl[15]_i_14_n_0\
    );
\acc0_lcl[15]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(15),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_2\(15),
      O => acc0_lcl(15)
    );
\acc0_lcl[15]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(14),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_2\(14),
      O => acc0_lcl(14)
    );
\acc0_lcl[15]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(13),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_2\(13),
      O => acc0_lcl(13)
    );
\acc0_lcl[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(16),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(8)
    );
\acc0_lcl[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(17),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(9)
    );
\acc0_lcl[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(18),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(10)
    );
\acc0_lcl[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(19),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(11)
    );
\acc0_lcl[19]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(19),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_2\(19),
      O => acc0_lcl(19)
    );
\acc0_lcl[19]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(18),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_2\(18),
      O => acc0_lcl(18)
    );
\acc0_lcl[19]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(17),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_2\(17),
      O => acc0_lcl(17)
    );
\acc0_lcl[19]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(16),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_2\(16),
      O => acc0_lcl(16)
    );
\acc0_lcl[7]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \acc0_lcl_reg[7]_i_2\(7),
      I1 => \acc0_lcl_reg[19]_i_2_2\(7),
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_0\,
      I4 => drdAccbufB(7),
      O => \acc0_lcl_reg[7]\(7)
    );
\acc0_lcl[7]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \acc0_lcl_reg[7]_i_2\(6),
      I1 => \acc0_lcl_reg[19]_i_2_2\(6),
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_0\,
      I4 => drdAccbufB(6),
      O => \acc0_lcl_reg[7]\(6)
    );
\acc0_lcl[7]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \acc0_lcl_reg[7]_i_2\(5),
      I1 => \acc0_lcl_reg[19]_i_2_2\(5),
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_0\,
      I4 => drdAccbufB(5),
      O => \acc0_lcl_reg[7]\(5)
    );
\acc0_lcl[7]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \acc0_lcl_reg[7]_i_2\(4),
      I1 => \acc0_lcl_reg[19]_i_2_2\(4),
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_0\,
      I4 => drdAccbufB(4),
      O => \acc0_lcl_reg[7]\(4)
    );
\acc0_lcl[7]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \acc0_lcl_reg[7]_i_2\(3),
      I1 => \acc0_lcl_reg[19]_i_2_2\(3),
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_0\,
      I4 => drdAccbufB(3),
      O => \acc0_lcl_reg[7]\(3)
    );
\acc0_lcl[7]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \acc0_lcl_reg[7]_i_2\(2),
      I1 => \acc0_lcl_reg[19]_i_2_2\(2),
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_0\,
      I4 => drdAccbufB(2),
      O => \acc0_lcl_reg[7]\(2)
    );
\acc0_lcl[7]_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \acc0_lcl_reg[7]_i_2\(1),
      I1 => \acc0_lcl_reg[19]_i_2_2\(1),
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_0\,
      I4 => drdAccbufB(1),
      O => \acc0_lcl_reg[7]\(1)
    );
\acc0_lcl[7]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55A6A6A6"
    )
        port map (
      I0 => \acc0_lcl_reg[7]_i_2\(0),
      I1 => \acc0_lcl_reg[19]_i_2_2\(0),
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc0_lcl_reg[19]_i_2_0\,
      I4 => drdAccbufB(0),
      O => \acc0_lcl_reg[7]\(0)
    );
\acc0_lcl[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(8),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(0)
    );
\acc0_lcl[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(9),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(1)
    );
\acc0_lcl_reg[15]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \dwrAccbuf_reg[15]\(0),
      CI_TOP => '0',
      CO(7) => \acc0_lcl_reg[15]_i_2_n_0\,
      CO(6) => \acc0_lcl_reg[15]_i_2_n_1\,
      CO(5) => \acc0_lcl_reg[15]_i_2_n_2\,
      CO(4) => \acc0_lcl_reg[15]_i_2_n_3\,
      CO(3) => \acc0_lcl_reg[15]_i_2_n_4\,
      CO(2) => \acc0_lcl_reg[15]_i_2_n_5\,
      CO(1) => \acc0_lcl_reg[15]_i_2_n_6\,
      CO(0) => \acc0_lcl_reg[15]_i_2_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3 downto 0) => DI(3 downto 0),
      O(7 downto 0) => dwrAccbuf(15 downto 8),
      S(7 downto 4) => acc0_lcl(15 downto 12),
      S(3) => \acc0_lcl[15]_i_11_n_0\,
      S(2) => \acc0_lcl[15]_i_12_n_0\,
      S(1) => \acc0_lcl[15]_i_13_n_0\,
      S(0) => \acc0_lcl[15]_i_14_n_0\
    );
\acc0_lcl_reg[19]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \acc0_lcl_reg[15]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_acc0_lcl_reg[19]_i_2_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \acc0_lcl_reg[19]_i_2_n_5\,
      CO(1) => \acc0_lcl_reg[19]_i_2_n_6\,
      CO(0) => \acc0_lcl_reg[19]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 4) => \NLW_acc0_lcl_reg[19]_i_2_O_UNCONNECTED\(7 downto 4),
      O(3 downto 0) => dwrAccbuf(19 downto 16),
      S(7 downto 4) => B"0000",
      S(3 downto 0) => acc0_lcl(19 downto 16)
    );
\acc1_lcl[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(20),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(12)
    );
\acc1_lcl[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(30),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(22)
    );
\acc1_lcl[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(31),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(23)
    );
\acc1_lcl[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(32),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(24)
    );
\acc1_lcl[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(33),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(25)
    );
\acc1_lcl[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(34),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(26)
    );
\acc1_lcl[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(35),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(27)
    );
\acc1_lcl[15]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(32),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(12),
      O => acc1_lcl(12)
    );
\acc1_lcl[15]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc1_lcl_reg[19]_i_2_0\(11),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(31),
      I4 => \acc2_lcl_reg[15]_i_2_0\(11),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc1_lcl[15]_i_11_n_0\
    );
\acc1_lcl[15]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc1_lcl_reg[19]_i_2_0\(10),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(30),
      I4 => \acc2_lcl_reg[15]_i_2_0\(10),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc1_lcl[15]_i_12_n_0\
    );
\acc1_lcl[15]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc1_lcl_reg[19]_i_2_0\(9),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(29),
      I4 => \acc2_lcl_reg[15]_i_2_0\(9),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc1_lcl[15]_i_13_n_0\
    );
\acc1_lcl[15]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc1_lcl_reg[19]_i_2_0\(8),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(28),
      I4 => \acc2_lcl_reg[15]_i_2_0\(8),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc1_lcl[15]_i_14_n_0\
    );
\acc1_lcl[15]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(31),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(11),
      O => acc1_lcl(11)
    );
\acc1_lcl[15]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(30),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(10),
      O => acc1_lcl(10)
    );
\acc1_lcl[15]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(29),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(9),
      O => acc1_lcl(9)
    );
\acc1_lcl[15]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(28),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(8),
      O => acc1_lcl(8)
    );
\acc1_lcl[15]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(35),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(15),
      O => acc1_lcl(15)
    );
\acc1_lcl[15]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(34),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(14),
      O => acc1_lcl(14)
    );
\acc1_lcl[15]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(33),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(13),
      O => acc1_lcl(13)
    );
\acc1_lcl[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(36),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(28)
    );
\acc1_lcl[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(37),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(29)
    );
\acc1_lcl[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(38),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(30)
    );
\acc1_lcl[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(39),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(31)
    );
\acc1_lcl[19]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(39),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(19),
      O => acc1_lcl(19)
    );
\acc1_lcl[19]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(38),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(18),
      O => acc1_lcl(18)
    );
\acc1_lcl[19]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(37),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(17),
      O => acc1_lcl(17)
    );
\acc1_lcl[19]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(36),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(16),
      O => acc1_lcl(16)
    );
\acc1_lcl[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(21),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(13)
    );
\acc1_lcl[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(22),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(14)
    );
\acc1_lcl[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(23),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(15)
    );
\acc1_lcl[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(24),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(16)
    );
\acc1_lcl[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(25),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(17)
    );
\acc1_lcl[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(26),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(18)
    );
\acc1_lcl[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(27),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(19)
    );
\acc1_lcl[7]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(20),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(0),
      O => acc1_lcl(0)
    );
\acc1_lcl[7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc1_lcl_reg[19]_i_2_0\(7),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(27),
      I4 => \acc2_lcl_reg[15]_i_2_0\(7),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc1_lcl[7]_i_11_n_0\
    );
\acc1_lcl[7]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc1_lcl_reg[19]_i_2_0\(6),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(26),
      I4 => \acc2_lcl_reg[15]_i_2_0\(6),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc1_lcl[7]_i_12_n_0\
    );
\acc1_lcl[7]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc1_lcl_reg[19]_i_2_0\(5),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(25),
      I4 => \acc2_lcl_reg[15]_i_2_0\(5),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc1_lcl[7]_i_13_n_0\
    );
\acc1_lcl[7]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc1_lcl_reg[19]_i_2_0\(4),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(24),
      I4 => \acc2_lcl_reg[15]_i_2_0\(4),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc1_lcl[7]_i_14_n_0\
    );
\acc1_lcl[7]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc1_lcl_reg[19]_i_2_0\(3),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(23),
      I4 => \acc2_lcl_reg[15]_i_2_0\(3),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc1_lcl[7]_i_15_n_0\
    );
\acc1_lcl[7]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc1_lcl_reg[19]_i_2_0\(2),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(22),
      I4 => \acc2_lcl_reg[15]_i_2_0\(2),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc1_lcl[7]_i_16_n_0\
    );
\acc1_lcl[7]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc1_lcl_reg[19]_i_2_0\(1),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(21),
      I4 => \acc2_lcl_reg[15]_i_2_0\(1),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc1_lcl[7]_i_17_n_0\
    );
\acc1_lcl[7]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc1_lcl_reg[19]_i_2_0\(0),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(20),
      I4 => \acc2_lcl_reg[15]_i_2_0\(0),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc1_lcl[7]_i_18_n_0\
    );
\acc1_lcl[7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(27),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(7),
      O => acc1_lcl(7)
    );
\acc1_lcl[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(26),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(6),
      O => acc1_lcl(6)
    );
\acc1_lcl[7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(25),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(5),
      O => acc1_lcl(5)
    );
\acc1_lcl[7]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(24),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(4),
      O => acc1_lcl(4)
    );
\acc1_lcl[7]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(23),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(3),
      O => acc1_lcl(3)
    );
\acc1_lcl[7]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(22),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(2),
      O => acc1_lcl(2)
    );
\acc1_lcl[7]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(21),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc1_lcl_reg[19]_i_2_0\(1),
      O => acc1_lcl(1)
    );
\acc1_lcl[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(28),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(20)
    );
\acc1_lcl[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(29),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(21)
    );
\acc1_lcl_reg[15]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \acc1_lcl_reg[7]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \acc1_lcl_reg[15]_i_2_n_0\,
      CO(6) => \acc1_lcl_reg[15]_i_2_n_1\,
      CO(5) => \acc1_lcl_reg[15]_i_2_n_2\,
      CO(4) => \acc1_lcl_reg[15]_i_2_n_3\,
      CO(3) => \acc1_lcl_reg[15]_i_2_n_4\,
      CO(2) => \acc1_lcl_reg[15]_i_2_n_5\,
      CO(1) => \acc1_lcl_reg[15]_i_2_n_6\,
      CO(0) => \acc1_lcl_reg[15]_i_2_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3 downto 0) => acc1_lcl(11 downto 8),
      O(7 downto 0) => dwrAccbuf(35 downto 28),
      S(7 downto 4) => acc1_lcl(15 downto 12),
      S(3) => \acc1_lcl[15]_i_11_n_0\,
      S(2) => \acc1_lcl[15]_i_12_n_0\,
      S(1) => \acc1_lcl[15]_i_13_n_0\,
      S(0) => \acc1_lcl[15]_i_14_n_0\
    );
\acc1_lcl_reg[19]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \acc1_lcl_reg[15]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_acc1_lcl_reg[19]_i_2_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \acc1_lcl_reg[19]_i_2_n_5\,
      CO(1) => \acc1_lcl_reg[19]_i_2_n_6\,
      CO(0) => \acc1_lcl_reg[19]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 4) => \NLW_acc1_lcl_reg[19]_i_2_O_UNCONNECTED\(7 downto 4),
      O(3 downto 0) => dwrAccbuf(39 downto 36),
      S(7 downto 4) => B"0000",
      S(3 downto 0) => acc1_lcl(19 downto 16)
    );
\acc1_lcl_reg[7]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \acc1_lcl_reg[7]_i_2_n_0\,
      CO(6) => \acc1_lcl_reg[7]_i_2_n_1\,
      CO(5) => \acc1_lcl_reg[7]_i_2_n_2\,
      CO(4) => \acc1_lcl_reg[7]_i_2_n_3\,
      CO(3) => \acc1_lcl_reg[7]_i_2_n_4\,
      CO(2) => \acc1_lcl_reg[7]_i_2_n_5\,
      CO(1) => \acc1_lcl_reg[7]_i_2_n_6\,
      CO(0) => \acc1_lcl_reg[7]_i_2_n_7\,
      DI(7 downto 0) => acc1_lcl(7 downto 0),
      O(7 downto 0) => dwrAccbuf(27 downto 20),
      S(7) => \acc1_lcl[7]_i_11_n_0\,
      S(6) => \acc1_lcl[7]_i_12_n_0\,
      S(5) => \acc1_lcl[7]_i_13_n_0\,
      S(4) => \acc1_lcl[7]_i_14_n_0\,
      S(3) => \acc1_lcl[7]_i_15_n_0\,
      S(2) => \acc1_lcl[7]_i_16_n_0\,
      S(1) => \acc1_lcl[7]_i_17_n_0\,
      S(0) => \acc1_lcl[7]_i_18_n_0\
    );
\acc2_lcl[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(40),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(32)
    );
\acc2_lcl[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(50),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(42)
    );
\acc2_lcl[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(51),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(43)
    );
\acc2_lcl[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(52),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(44)
    );
\acc2_lcl[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(53),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(45)
    );
\acc2_lcl[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(54),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(46)
    );
\acc2_lcl[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(55),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(47)
    );
\acc2_lcl[15]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(52),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(12),
      O => acc2_lcl(12)
    );
\acc2_lcl[15]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc2_lcl_reg[19]_i_2_0\(11),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(51),
      I4 => \acc2_lcl_reg[15]_i_2_0\(23),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc2_lcl[15]_i_11_n_0\
    );
\acc2_lcl[15]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc2_lcl_reg[19]_i_2_0\(10),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(50),
      I4 => \acc2_lcl_reg[15]_i_2_0\(22),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc2_lcl[15]_i_12_n_0\
    );
\acc2_lcl[15]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc2_lcl_reg[19]_i_2_0\(9),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(49),
      I4 => \acc2_lcl_reg[15]_i_2_0\(21),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc2_lcl[15]_i_13_n_0\
    );
\acc2_lcl[15]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc2_lcl_reg[19]_i_2_0\(8),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(48),
      I4 => \acc2_lcl_reg[15]_i_2_0\(20),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc2_lcl[15]_i_14_n_0\
    );
\acc2_lcl[15]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(51),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(11),
      O => acc2_lcl(11)
    );
\acc2_lcl[15]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(50),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(10),
      O => acc2_lcl(10)
    );
\acc2_lcl[15]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(49),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(9),
      O => acc2_lcl(9)
    );
\acc2_lcl[15]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(48),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(8),
      O => acc2_lcl(8)
    );
\acc2_lcl[15]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(55),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(15),
      O => acc2_lcl(15)
    );
\acc2_lcl[15]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(54),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(14),
      O => acc2_lcl(14)
    );
\acc2_lcl[15]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(53),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(13),
      O => acc2_lcl(13)
    );
\acc2_lcl[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(56),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(48)
    );
\acc2_lcl[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(57),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(49)
    );
\acc2_lcl[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(58),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(50)
    );
\acc2_lcl[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(59),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(51)
    );
\acc2_lcl[19]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(59),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(19),
      O => acc2_lcl(19)
    );
\acc2_lcl[19]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(58),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(18),
      O => acc2_lcl(18)
    );
\acc2_lcl[19]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(57),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(17),
      O => acc2_lcl(17)
    );
\acc2_lcl[19]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(56),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(16),
      O => acc2_lcl(16)
    );
\acc2_lcl[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(41),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(33)
    );
\acc2_lcl[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(42),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(34)
    );
\acc2_lcl[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(43),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(35)
    );
\acc2_lcl[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(44),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(36)
    );
\acc2_lcl[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(45),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(37)
    );
\acc2_lcl[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(46),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(38)
    );
\acc2_lcl[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(47),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(39)
    );
\acc2_lcl[7]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(40),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(0),
      O => acc2_lcl(0)
    );
\acc2_lcl[7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc2_lcl_reg[19]_i_2_0\(7),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(47),
      I4 => \acc2_lcl_reg[15]_i_2_0\(19),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc2_lcl[7]_i_11_n_0\
    );
\acc2_lcl[7]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc2_lcl_reg[19]_i_2_0\(6),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(46),
      I4 => \acc2_lcl_reg[15]_i_2_0\(18),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc2_lcl[7]_i_12_n_0\
    );
\acc2_lcl[7]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc2_lcl_reg[19]_i_2_0\(5),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(45),
      I4 => \acc2_lcl_reg[15]_i_2_0\(17),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc2_lcl[7]_i_13_n_0\
    );
\acc2_lcl[7]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc2_lcl_reg[19]_i_2_0\(4),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(44),
      I4 => \acc2_lcl_reg[15]_i_2_0\(16),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc2_lcl[7]_i_14_n_0\
    );
\acc2_lcl[7]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc2_lcl_reg[19]_i_2_0\(3),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(43),
      I4 => \acc2_lcl_reg[15]_i_2_0\(15),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc2_lcl[7]_i_15_n_0\
    );
\acc2_lcl[7]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc2_lcl_reg[19]_i_2_0\(2),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(42),
      I4 => \acc2_lcl_reg[15]_i_2_0\(14),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc2_lcl[7]_i_16_n_0\
    );
\acc2_lcl[7]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc2_lcl_reg[19]_i_2_0\(1),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(41),
      I4 => \acc2_lcl_reg[15]_i_2_0\(13),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc2_lcl[7]_i_17_n_0\
    );
\acc2_lcl[7]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDF222F222F222"
    )
        port map (
      I0 => \acc2_lcl_reg[19]_i_2_0\(0),
      I1 => \acc0_lcl_reg[19]_i_2_1\,
      I2 => \acc0_lcl_reg[19]_i_2_0\,
      I3 => drdAccbufB(40),
      I4 => \acc2_lcl_reg[15]_i_2_0\(12),
      I5 => \acc1_lcl_reg[7]_i_2_0\,
      O => \acc2_lcl[7]_i_18_n_0\
    );
\acc2_lcl[7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(47),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(7),
      O => acc2_lcl(7)
    );
\acc2_lcl[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(46),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(6),
      O => acc2_lcl(6)
    );
\acc2_lcl[7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(45),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(5),
      O => acc2_lcl(5)
    );
\acc2_lcl[7]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(44),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(4),
      O => acc2_lcl(4)
    );
\acc2_lcl[7]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(43),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(3),
      O => acc2_lcl(3)
    );
\acc2_lcl[7]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(42),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(2),
      O => acc2_lcl(2)
    );
\acc2_lcl[7]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drdAccbufB(41),
      I1 => \acc0_lcl_reg[19]_i_2_0\,
      I2 => \acc0_lcl_reg[19]_i_2_1\,
      I3 => \acc2_lcl_reg[19]_i_2_0\(1),
      O => acc2_lcl(1)
    );
\acc2_lcl[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(48),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(40)
    );
\acc2_lcl[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => dwrAccbuf(49),
      I1 => \acc2_reg[19]\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => D(41)
    );
\acc2_lcl_reg[15]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \acc2_lcl_reg[7]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \acc2_lcl_reg[15]_i_2_n_0\,
      CO(6) => \acc2_lcl_reg[15]_i_2_n_1\,
      CO(5) => \acc2_lcl_reg[15]_i_2_n_2\,
      CO(4) => \acc2_lcl_reg[15]_i_2_n_3\,
      CO(3) => \acc2_lcl_reg[15]_i_2_n_4\,
      CO(2) => \acc2_lcl_reg[15]_i_2_n_5\,
      CO(1) => \acc2_lcl_reg[15]_i_2_n_6\,
      CO(0) => \acc2_lcl_reg[15]_i_2_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3 downto 0) => acc2_lcl(11 downto 8),
      O(7 downto 0) => dwrAccbuf(55 downto 48),
      S(7 downto 4) => acc2_lcl(15 downto 12),
      S(3) => \acc2_lcl[15]_i_11_n_0\,
      S(2) => \acc2_lcl[15]_i_12_n_0\,
      S(1) => \acc2_lcl[15]_i_13_n_0\,
      S(0) => \acc2_lcl[15]_i_14_n_0\
    );
\acc2_lcl_reg[19]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \acc2_lcl_reg[15]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_acc2_lcl_reg[19]_i_2_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \acc2_lcl_reg[19]_i_2_n_5\,
      CO(1) => \acc2_lcl_reg[19]_i_2_n_6\,
      CO(0) => \acc2_lcl_reg[19]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 4) => \NLW_acc2_lcl_reg[19]_i_2_O_UNCONNECTED\(7 downto 4),
      O(3 downto 0) => dwrAccbuf(59 downto 56),
      S(7 downto 4) => B"0000",
      S(3 downto 0) => acc2_lcl(19 downto 16)
    );
\acc2_lcl_reg[7]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \acc2_lcl_reg[7]_i_2_n_0\,
      CO(6) => \acc2_lcl_reg[7]_i_2_n_1\,
      CO(5) => \acc2_lcl_reg[7]_i_2_n_2\,
      CO(4) => \acc2_lcl_reg[7]_i_2_n_3\,
      CO(3) => \acc2_lcl_reg[7]_i_2_n_4\,
      CO(2) => \acc2_lcl_reg[7]_i_2_n_5\,
      CO(1) => \acc2_lcl_reg[7]_i_2_n_6\,
      CO(0) => \acc2_lcl_reg[7]_i_2_n_7\,
      DI(7 downto 0) => acc2_lcl(7 downto 0),
      O(7 downto 0) => dwrAccbuf(47 downto 40),
      S(7) => \acc2_lcl[7]_i_11_n_0\,
      S(6) => \acc2_lcl[7]_i_12_n_0\,
      S(5) => \acc2_lcl[7]_i_13_n_0\,
      S(4) => \acc2_lcl[7]_i_14_n_0\,
      S(3) => \acc2_lcl[7]_i_15_n_0\,
      S(2) => \acc2_lcl[7]_i_16_n_0\,
      S(1) => \acc2_lcl[7]_i_17_n_0\,
      S(0) => \acc2_lcl[7]_i_18_n_0\
    );
myMnfcore: entity work.design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a64b64
     port map (
      addra(7 downto 0) => Q(7 downto 0),
      addrb(7 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(63 downto 60) => B"0000",
      dina(59 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(59 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 60) => NLW_myMnfcore_doutb_UNCONNECTED(63 downto 60),
      doutb(59 downto 0) => drdAccbufB(59 downto 0),
      ena => ena,
      enb => enB,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      O => enB
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8 is
  port (
    doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \fghij_reg[2]\ : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \dImd_reg[7]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \dImd_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[7]_1\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_3\ : in STD_LOGIC;
    \dImd_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8 : entity is "Dpbram_size2kB_a8b8";
end design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8 is
  signal \dImd[0]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[1]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[2]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[3]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[4]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[5]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[6]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[7]_i_2_n_0\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^fghij_reg[2]\ : STD_LOGIC;
  signal myMnfcore_i_1_n_0 : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size2kB_a8b8,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
  doutb(7 downto 0) <= \^doutb\(7 downto 0);
  \fghij_reg[2]\ <= \^fghij_reg[2]\;
\dImd[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[0]_i_2_n_0\,
      I1 => \dImd_reg[7]\(2),
      I2 => \dImd_reg[7]_0\(0),
      I3 => \dImd_reg[7]_1\,
      O => D(0)
    );
\dImd[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(0),
      I1 => \dImd_reg[7]_2\(0),
      I2 => \dImd_reg[7]\(1),
      I3 => \dImd_reg[7]_3\(0),
      I4 => \dImd_reg[7]\(0),
      I5 => \dImd_reg[7]_4\(0),
      O => \dImd[0]_i_2_n_0\
    );
\dImd[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[1]_i_2_n_0\,
      I1 => \dImd_reg[7]\(2),
      I2 => \dImd_reg[7]_0\(1),
      I3 => \dImd_reg[7]_1\,
      O => D(1)
    );
\dImd[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(1),
      I1 => \dImd_reg[7]_2\(1),
      I2 => \dImd_reg[7]\(1),
      I3 => \dImd_reg[7]_3\(1),
      I4 => \dImd_reg[7]\(0),
      I5 => \dImd_reg[7]_4\(1),
      O => \dImd[1]_i_2_n_0\
    );
\dImd[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[2]_i_2_n_0\,
      I1 => \dImd_reg[7]\(2),
      I2 => \dImd_reg[7]_0\(2),
      I3 => \dImd_reg[7]_1\,
      O => D(2)
    );
\dImd[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(2),
      I1 => \dImd_reg[7]_2\(2),
      I2 => \dImd_reg[7]\(1),
      I3 => \dImd_reg[7]_3\(2),
      I4 => \dImd_reg[7]\(0),
      I5 => \dImd_reg[7]_4\(2),
      O => \dImd[2]_i_2_n_0\
    );
\dImd[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[3]_i_2_n_0\,
      I1 => \dImd_reg[7]\(2),
      I2 => \dImd_reg[7]_0\(3),
      I3 => \dImd_reg[7]_1\,
      O => D(3)
    );
\dImd[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(3),
      I1 => \dImd_reg[7]_2\(3),
      I2 => \dImd_reg[7]\(1),
      I3 => \dImd_reg[7]_3\(3),
      I4 => \dImd_reg[7]\(0),
      I5 => \dImd_reg[7]_4\(3),
      O => \dImd[3]_i_2_n_0\
    );
\dImd[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[4]_i_2_n_0\,
      I1 => \dImd_reg[7]\(2),
      I2 => \dImd_reg[7]_0\(4),
      I3 => \dImd_reg[7]_1\,
      O => D(4)
    );
\dImd[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(4),
      I1 => \dImd_reg[7]_2\(4),
      I2 => \dImd_reg[7]\(1),
      I3 => \dImd_reg[7]_3\(4),
      I4 => \dImd_reg[7]\(0),
      I5 => \dImd_reg[7]_4\(4),
      O => \dImd[4]_i_2_n_0\
    );
\dImd[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[5]_i_2_n_0\,
      I1 => \dImd_reg[7]\(2),
      I2 => \dImd_reg[7]_0\(5),
      I3 => \dImd_reg[7]_1\,
      O => D(5)
    );
\dImd[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(5),
      I1 => \dImd_reg[7]_2\(5),
      I2 => \dImd_reg[7]\(1),
      I3 => \dImd_reg[7]_3\(5),
      I4 => \dImd_reg[7]\(0),
      I5 => \dImd_reg[7]_4\(5),
      O => \dImd[5]_i_2_n_0\
    );
\dImd[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[6]_i_2_n_0\,
      I1 => \dImd_reg[7]\(2),
      I2 => \dImd_reg[7]_0\(6),
      I3 => \dImd_reg[7]_1\,
      O => D(6)
    );
\dImd[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(6),
      I1 => \dImd_reg[7]_2\(6),
      I2 => \dImd_reg[7]\(1),
      I3 => \dImd_reg[7]_3\(6),
      I4 => \dImd_reg[7]\(0),
      I5 => \dImd_reg[7]_4\(6),
      O => \dImd[6]_i_2_n_0\
    );
\dImd[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[7]_i_2_n_0\,
      I1 => \dImd_reg[7]\(2),
      I2 => \dImd_reg[7]_0\(7),
      I3 => \dImd_reg[7]_1\,
      O => D(7)
    );
\dImd[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(7),
      I1 => \dImd_reg[7]_2\(7),
      I2 => \dImd_reg[7]\(1),
      I3 => \dImd_reg[7]_3\(7),
      I4 => \dImd_reg[7]\(0),
      I5 => \dImd_reg[7]_4\(7),
      O => \dImd[7]_i_2_n_0\
    );
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__5\
     port map (
      addra(10 downto 0) => Q(10 downto 0),
      addrb(10 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(10 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(7 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(7 downto 0),
      dinb(7 downto 0) => B"00000000",
      douta(7 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(7 downto 0),
      doutb(7 downto 0) => \^doutb\(7 downto 0),
      ena => myMnfcore_i_1_n_0,
      enb => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\,
      wea(0) => '1',
      web(0) => '0'
    );
myMnfcore_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\,
      I1 => \^fghij_reg[2]\,
      O => myMnfcore_i_1_n_0
    );
myMnfcore_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFEF"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\,
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_3\,
      I2 => \dImd_reg[7]\(2),
      I3 => \dImd_reg[7]\(1),
      I4 => \dImd_reg[7]\(0),
      O => \^fghij_reg[2]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__1\ is
  port (
    doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \dImd_reg[39]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \dImd_reg[39]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[39]_1\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_3\ : in STD_LOGIC;
    \dImd_reg[39]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[39]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[39]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__1\ : entity is "Dpbram_size2kB_a8b8";
end \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__1\ is
  signal \dImd[32]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[33]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[34]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[35]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[36]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[37]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[38]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[39]_i_6_n_0\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \myMnfcore_i_1__7_n_0\ : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size2kB_a8b8,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
  doutb(7 downto 0) <= \^doutb\(7 downto 0);
\dImd[32]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[32]_i_2_n_0\,
      I1 => \dImd_reg[39]\(2),
      I2 => \dImd_reg[39]_0\(0),
      I3 => \dImd_reg[39]_1\,
      O => D(0)
    );
\dImd[32]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(0),
      I1 => \dImd_reg[39]_2\(0),
      I2 => \dImd_reg[39]\(1),
      I3 => \dImd_reg[39]_3\(0),
      I4 => \dImd_reg[39]\(0),
      I5 => \dImd_reg[39]_4\(0),
      O => \dImd[32]_i_2_n_0\
    );
\dImd[33]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[33]_i_2_n_0\,
      I1 => \dImd_reg[39]\(2),
      I2 => \dImd_reg[39]_0\(1),
      I3 => \dImd_reg[39]_1\,
      O => D(1)
    );
\dImd[33]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(1),
      I1 => \dImd_reg[39]_2\(1),
      I2 => \dImd_reg[39]\(1),
      I3 => \dImd_reg[39]_3\(1),
      I4 => \dImd_reg[39]\(0),
      I5 => \dImd_reg[39]_4\(1),
      O => \dImd[33]_i_2_n_0\
    );
\dImd[34]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[34]_i_2_n_0\,
      I1 => \dImd_reg[39]\(2),
      I2 => \dImd_reg[39]_0\(2),
      I3 => \dImd_reg[39]_1\,
      O => D(2)
    );
\dImd[34]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(2),
      I1 => \dImd_reg[39]_2\(2),
      I2 => \dImd_reg[39]\(1),
      I3 => \dImd_reg[39]_3\(2),
      I4 => \dImd_reg[39]\(0),
      I5 => \dImd_reg[39]_4\(2),
      O => \dImd[34]_i_2_n_0\
    );
\dImd[35]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[35]_i_2_n_0\,
      I1 => \dImd_reg[39]\(2),
      I2 => \dImd_reg[39]_0\(3),
      I3 => \dImd_reg[39]_1\,
      O => D(3)
    );
\dImd[35]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(3),
      I1 => \dImd_reg[39]_2\(3),
      I2 => \dImd_reg[39]\(1),
      I3 => \dImd_reg[39]_3\(3),
      I4 => \dImd_reg[39]\(0),
      I5 => \dImd_reg[39]_4\(3),
      O => \dImd[35]_i_2_n_0\
    );
\dImd[36]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[36]_i_2_n_0\,
      I1 => \dImd_reg[39]\(2),
      I2 => \dImd_reg[39]_0\(4),
      I3 => \dImd_reg[39]_1\,
      O => D(4)
    );
\dImd[36]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(4),
      I1 => \dImd_reg[39]_2\(4),
      I2 => \dImd_reg[39]\(1),
      I3 => \dImd_reg[39]_3\(4),
      I4 => \dImd_reg[39]\(0),
      I5 => \dImd_reg[39]_4\(4),
      O => \dImd[36]_i_2_n_0\
    );
\dImd[37]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[37]_i_2_n_0\,
      I1 => \dImd_reg[39]\(2),
      I2 => \dImd_reg[39]_0\(5),
      I3 => \dImd_reg[39]_1\,
      O => D(5)
    );
\dImd[37]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(5),
      I1 => \dImd_reg[39]_2\(5),
      I2 => \dImd_reg[39]\(1),
      I3 => \dImd_reg[39]_3\(5),
      I4 => \dImd_reg[39]\(0),
      I5 => \dImd_reg[39]_4\(5),
      O => \dImd[37]_i_2_n_0\
    );
\dImd[38]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[38]_i_2_n_0\,
      I1 => \dImd_reg[39]\(2),
      I2 => \dImd_reg[39]_0\(6),
      I3 => \dImd_reg[39]_1\,
      O => D(6)
    );
\dImd[38]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(6),
      I1 => \dImd_reg[39]_2\(6),
      I2 => \dImd_reg[39]\(1),
      I3 => \dImd_reg[39]_3\(6),
      I4 => \dImd_reg[39]\(0),
      I5 => \dImd_reg[39]_4\(6),
      O => \dImd[38]_i_2_n_0\
    );
\dImd[39]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[39]_i_6_n_0\,
      I1 => \dImd_reg[39]\(2),
      I2 => \dImd_reg[39]_0\(7),
      I3 => \dImd_reg[39]_1\,
      O => D(7)
    );
\dImd[39]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(7),
      I1 => \dImd_reg[39]_2\(7),
      I2 => \dImd_reg[39]\(1),
      I3 => \dImd_reg[39]_3\(7),
      I4 => \dImd_reg[39]\(0),
      I5 => \dImd_reg[39]_4\(7),
      O => \dImd[39]_i_6_n_0\
    );
myMnfcore: entity work.design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8
     port map (
      addra(10 downto 0) => Q(10 downto 0),
      addrb(10 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(10 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(7 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(7 downto 0),
      dinb(7 downto 0) => B"00000000",
      douta(7 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(7 downto 0),
      doutb(7 downto 0) => \^doutb\(7 downto 0),
      ena => \myMnfcore_i_1__7_n_0\,
      enb => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\,
      I1 => \dImd_reg[39]\(2),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\,
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_3\,
      I4 => \dImd_reg[39]\(1),
      I5 => \dImd_reg[39]\(0),
      O => \myMnfcore_i_1__7_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__2\ is
  port (
    doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \fghij_reg[11]\ : out STD_LOGIC;
    \fghij_reg[30]\ : out STD_LOGIC;
    \fghij_reg[11]_0\ : out STD_LOGIC;
    \fghij_reg[13]\ : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\ : in STD_LOGIC_VECTOR ( 30 downto 0 );
    \dImd_reg[31]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[31]_0\ : in STD_LOGIC;
    \dImd_reg[31]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[31]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[31]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__2\ : entity is "Dpbram_size2kB_a8b8";
end \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__2\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__2\ is
  signal \dImd[24]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[25]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[26]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[27]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[28]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[29]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[30]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[31]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[39]_i_7_n_0\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^fghij_reg[11]\ : STD_LOGIC;
  signal \^fghij_reg[11]_0\ : STD_LOGIC;
  signal \^fghij_reg[13]\ : STD_LOGIC;
  signal \^fghij_reg[30]\ : STD_LOGIC;
  signal \myMnfcore_i_1__9_n_0\ : STD_LOGIC;
  signal myMnfcore_i_5_n_0 : STD_LOGIC;
  signal myMnfcore_i_6_n_0 : STD_LOGIC;
  signal myMnfcore_i_7_n_0 : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size2kB_a8b8,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
  doutb(7 downto 0) <= \^doutb\(7 downto 0);
  \fghij_reg[11]\ <= \^fghij_reg[11]\;
  \fghij_reg[11]_0\ <= \^fghij_reg[11]_0\;
  \fghij_reg[13]\ <= \^fghij_reg[13]\;
  \fghij_reg[30]\ <= \^fghij_reg[30]\;
\dImd[24]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[24]_i_2_n_0\,
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(2),
      I2 => \dImd_reg[31]\(0),
      I3 => \dImd_reg[31]_0\,
      O => D(0)
    );
\dImd[24]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(0),
      I1 => \dImd_reg[31]_1\(0),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(1),
      I3 => \dImd_reg[31]_2\(0),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(0),
      I5 => \dImd_reg[31]_3\(0),
      O => \dImd[24]_i_2_n_0\
    );
\dImd[25]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[25]_i_2_n_0\,
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(2),
      I2 => \dImd_reg[31]\(1),
      I3 => \dImd_reg[31]_0\,
      O => D(1)
    );
\dImd[25]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(1),
      I1 => \dImd_reg[31]_1\(1),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(1),
      I3 => \dImd_reg[31]_2\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(0),
      I5 => \dImd_reg[31]_3\(1),
      O => \dImd[25]_i_2_n_0\
    );
\dImd[26]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[26]_i_2_n_0\,
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(2),
      I2 => \dImd_reg[31]\(2),
      I3 => \dImd_reg[31]_0\,
      O => D(2)
    );
\dImd[26]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(2),
      I1 => \dImd_reg[31]_1\(2),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(1),
      I3 => \dImd_reg[31]_2\(2),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(0),
      I5 => \dImd_reg[31]_3\(2),
      O => \dImd[26]_i_2_n_0\
    );
\dImd[27]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[27]_i_2_n_0\,
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(2),
      I2 => \dImd_reg[31]\(3),
      I3 => \dImd_reg[31]_0\,
      O => D(3)
    );
\dImd[27]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(3),
      I1 => \dImd_reg[31]_1\(3),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(1),
      I3 => \dImd_reg[31]_2\(3),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(0),
      I5 => \dImd_reg[31]_3\(3),
      O => \dImd[27]_i_2_n_0\
    );
\dImd[28]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[28]_i_2_n_0\,
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(2),
      I2 => \dImd_reg[31]\(4),
      I3 => \dImd_reg[31]_0\,
      O => D(4)
    );
\dImd[28]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(4),
      I1 => \dImd_reg[31]_1\(4),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(1),
      I3 => \dImd_reg[31]_2\(4),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(0),
      I5 => \dImd_reg[31]_3\(4),
      O => \dImd[28]_i_2_n_0\
    );
\dImd[29]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[29]_i_2_n_0\,
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(2),
      I2 => \dImd_reg[31]\(5),
      I3 => \dImd_reg[31]_0\,
      O => D(5)
    );
\dImd[29]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(5),
      I1 => \dImd_reg[31]_1\(5),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(1),
      I3 => \dImd_reg[31]_2\(5),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(0),
      I5 => \dImd_reg[31]_3\(5),
      O => \dImd[29]_i_2_n_0\
    );
\dImd[30]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[30]_i_2_n_0\,
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(2),
      I2 => \dImd_reg[31]\(6),
      I3 => \dImd_reg[31]_0\,
      O => D(6)
    );
\dImd[30]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(6),
      I1 => \dImd_reg[31]_1\(6),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(1),
      I3 => \dImd_reg[31]_2\(6),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(0),
      I5 => \dImd_reg[31]_3\(6),
      O => \dImd[30]_i_2_n_0\
    );
\dImd[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[31]_i_2_n_0\,
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(2),
      I2 => \dImd_reg[31]\(7),
      I3 => \dImd_reg[31]_0\,
      O => D(7)
    );
\dImd[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(7),
      I1 => \dImd_reg[31]_1\(7),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(1),
      I3 => \dImd_reg[31]_2\(7),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(0),
      I5 => \dImd_reg[31]_3\(7),
      O => \dImd[31]_i_2_n_0\
    );
\dImd[39]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(11),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(10),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(20),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(19),
      I4 => \dImd[39]_i_7_n_0\,
      O => \^fghij_reg[11]_0\
    );
\dImd[39]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(4),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(5),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(23),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(7),
      O => \dImd[39]_i_7_n_0\
    );
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__8\
     port map (
      addra(10 downto 0) => Q(10 downto 0),
      addrb(10 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(10 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(7 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(7 downto 0),
      dinb(7 downto 0) => B"00000000",
      douta(7 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(7 downto 0),
      doutb(7 downto 0) => \^doutb\(7 downto 0),
      ena => \myMnfcore_i_1__9_n_0\,
      enb => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000100000"
    )
        port map (
      I0 => \^fghij_reg[11]\,
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(2),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\,
      I3 => \^fghij_reg[30]\,
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(0),
      I5 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(1),
      O => \myMnfcore_i_1__9_n_0\
    );
\myMnfcore_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^fghij_reg[11]_0\,
      I1 => \^fghij_reg[13]\,
      O => \^fghij_reg[11]\
    );
myMnfcore_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => myMnfcore_i_5_n_0,
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(30),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(29),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(24),
      I4 => myMnfcore_i_6_n_0,
      O => \^fghij_reg[30]\
    );
myMnfcore_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(13),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(12),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(6),
      I3 => myMnfcore_i_7_n_0,
      O => \^fghij_reg[13]\
    );
myMnfcore_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(28),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(27),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(25),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(26),
      O => myMnfcore_i_5_n_0
    );
myMnfcore_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(14),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(15),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(9),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(8),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(17),
      I5 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(18),
      O => myMnfcore_i_6_n_0
    );
myMnfcore_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(22),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(21),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(16),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(3),
      O => myMnfcore_i_7_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__3\ is
  port (
    doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \dImd_reg[23]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \dImd_reg[23]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[23]_1\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_3\ : in STD_LOGIC;
    \dImd_reg[23]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[23]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[23]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__3\ : entity is "Dpbram_size2kB_a8b8";
end \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__3\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__3\ is
  signal \dImd[16]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[17]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[18]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[19]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[20]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[21]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[22]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[23]_i_2_n_0\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \myMnfcore_i_1__6_n_0\ : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size2kB_a8b8,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
  doutb(7 downto 0) <= \^doutb\(7 downto 0);
\dImd[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[16]_i_2_n_0\,
      I1 => \dImd_reg[23]\(2),
      I2 => \dImd_reg[23]_0\(0),
      I3 => \dImd_reg[23]_1\,
      O => D(0)
    );
\dImd[16]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(0),
      I1 => \dImd_reg[23]_2\(0),
      I2 => \dImd_reg[23]\(1),
      I3 => \dImd_reg[23]_3\(0),
      I4 => \dImd_reg[23]\(0),
      I5 => \dImd_reg[23]_4\(0),
      O => \dImd[16]_i_2_n_0\
    );
\dImd[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[17]_i_2_n_0\,
      I1 => \dImd_reg[23]\(2),
      I2 => \dImd_reg[23]_0\(1),
      I3 => \dImd_reg[23]_1\,
      O => D(1)
    );
\dImd[17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(1),
      I1 => \dImd_reg[23]_2\(1),
      I2 => \dImd_reg[23]\(1),
      I3 => \dImd_reg[23]_3\(1),
      I4 => \dImd_reg[23]\(0),
      I5 => \dImd_reg[23]_4\(1),
      O => \dImd[17]_i_2_n_0\
    );
\dImd[18]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[18]_i_2_n_0\,
      I1 => \dImd_reg[23]\(2),
      I2 => \dImd_reg[23]_0\(2),
      I3 => \dImd_reg[23]_1\,
      O => D(2)
    );
\dImd[18]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(2),
      I1 => \dImd_reg[23]_2\(2),
      I2 => \dImd_reg[23]\(1),
      I3 => \dImd_reg[23]_3\(2),
      I4 => \dImd_reg[23]\(0),
      I5 => \dImd_reg[23]_4\(2),
      O => \dImd[18]_i_2_n_0\
    );
\dImd[19]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[19]_i_2_n_0\,
      I1 => \dImd_reg[23]\(2),
      I2 => \dImd_reg[23]_0\(3),
      I3 => \dImd_reg[23]_1\,
      O => D(3)
    );
\dImd[19]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(3),
      I1 => \dImd_reg[23]_2\(3),
      I2 => \dImd_reg[23]\(1),
      I3 => \dImd_reg[23]_3\(3),
      I4 => \dImd_reg[23]\(0),
      I5 => \dImd_reg[23]_4\(3),
      O => \dImd[19]_i_2_n_0\
    );
\dImd[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[20]_i_2_n_0\,
      I1 => \dImd_reg[23]\(2),
      I2 => \dImd_reg[23]_0\(4),
      I3 => \dImd_reg[23]_1\,
      O => D(4)
    );
\dImd[20]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(4),
      I1 => \dImd_reg[23]_2\(4),
      I2 => \dImd_reg[23]\(1),
      I3 => \dImd_reg[23]_3\(4),
      I4 => \dImd_reg[23]\(0),
      I5 => \dImd_reg[23]_4\(4),
      O => \dImd[20]_i_2_n_0\
    );
\dImd[21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[21]_i_2_n_0\,
      I1 => \dImd_reg[23]\(2),
      I2 => \dImd_reg[23]_0\(5),
      I3 => \dImd_reg[23]_1\,
      O => D(5)
    );
\dImd[21]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(5),
      I1 => \dImd_reg[23]_2\(5),
      I2 => \dImd_reg[23]\(1),
      I3 => \dImd_reg[23]_3\(5),
      I4 => \dImd_reg[23]\(0),
      I5 => \dImd_reg[23]_4\(5),
      O => \dImd[21]_i_2_n_0\
    );
\dImd[22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[22]_i_2_n_0\,
      I1 => \dImd_reg[23]\(2),
      I2 => \dImd_reg[23]_0\(6),
      I3 => \dImd_reg[23]_1\,
      O => D(6)
    );
\dImd[22]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(6),
      I1 => \dImd_reg[23]_2\(6),
      I2 => \dImd_reg[23]\(1),
      I3 => \dImd_reg[23]_3\(6),
      I4 => \dImd_reg[23]\(0),
      I5 => \dImd_reg[23]_4\(6),
      O => \dImd[22]_i_2_n_0\
    );
\dImd[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[23]_i_2_n_0\,
      I1 => \dImd_reg[23]\(2),
      I2 => \dImd_reg[23]_0\(7),
      I3 => \dImd_reg[23]_1\,
      O => D(7)
    );
\dImd[23]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(7),
      I1 => \dImd_reg[23]_2\(7),
      I2 => \dImd_reg[23]\(1),
      I3 => \dImd_reg[23]_3\(7),
      I4 => \dImd_reg[23]\(0),
      I5 => \dImd_reg[23]_4\(7),
      O => \dImd[23]_i_2_n_0\
    );
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__7\
     port map (
      addra(10 downto 0) => Q(10 downto 0),
      addrb(10 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(10 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(7 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(7 downto 0),
      dinb(7 downto 0) => B"00000000",
      douta(7 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(7 downto 0),
      doutb(7 downto 0) => \^doutb\(7 downto 0),
      ena => \myMnfcore_i_1__6_n_0\,
      enb => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000100000"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\,
      I1 => \dImd_reg[23]\(2),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\,
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_3\,
      I4 => \dImd_reg[23]\(1),
      I5 => \dImd_reg[23]\(0),
      O => \myMnfcore_i_1__6_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__4\ is
  port (
    doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \dImd_reg[15]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \dImd_reg[15]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[15]_1\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_3\ : in STD_LOGIC;
    \dImd_reg[15]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[15]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dImd_reg[15]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__4\ : entity is "Dpbram_size2kB_a8b8";
end \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__4\ is
  signal \dImd[10]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[11]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[12]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[13]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[14]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[15]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[8]_i_2_n_0\ : STD_LOGIC;
  signal \dImd[9]_i_2_n_0\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \myMnfcore_i_1__8_n_0\ : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size2kB_a8b8,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
  doutb(7 downto 0) <= \^doutb\(7 downto 0);
\dImd[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[10]_i_2_n_0\,
      I1 => \dImd_reg[15]\(2),
      I2 => \dImd_reg[15]_0\(2),
      I3 => \dImd_reg[15]_1\,
      O => D(2)
    );
\dImd[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(2),
      I1 => \dImd_reg[15]_2\(2),
      I2 => \dImd_reg[15]\(1),
      I3 => \dImd_reg[15]_3\(2),
      I4 => \dImd_reg[15]\(0),
      I5 => \dImd_reg[15]_4\(2),
      O => \dImd[10]_i_2_n_0\
    );
\dImd[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[11]_i_2_n_0\,
      I1 => \dImd_reg[15]\(2),
      I2 => \dImd_reg[15]_0\(3),
      I3 => \dImd_reg[15]_1\,
      O => D(3)
    );
\dImd[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(3),
      I1 => \dImd_reg[15]_2\(3),
      I2 => \dImd_reg[15]\(1),
      I3 => \dImd_reg[15]_3\(3),
      I4 => \dImd_reg[15]\(0),
      I5 => \dImd_reg[15]_4\(3),
      O => \dImd[11]_i_2_n_0\
    );
\dImd[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[12]_i_2_n_0\,
      I1 => \dImd_reg[15]\(2),
      I2 => \dImd_reg[15]_0\(4),
      I3 => \dImd_reg[15]_1\,
      O => D(4)
    );
\dImd[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(4),
      I1 => \dImd_reg[15]_2\(4),
      I2 => \dImd_reg[15]\(1),
      I3 => \dImd_reg[15]_3\(4),
      I4 => \dImd_reg[15]\(0),
      I5 => \dImd_reg[15]_4\(4),
      O => \dImd[12]_i_2_n_0\
    );
\dImd[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[13]_i_2_n_0\,
      I1 => \dImd_reg[15]\(2),
      I2 => \dImd_reg[15]_0\(5),
      I3 => \dImd_reg[15]_1\,
      O => D(5)
    );
\dImd[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(5),
      I1 => \dImd_reg[15]_2\(5),
      I2 => \dImd_reg[15]\(1),
      I3 => \dImd_reg[15]_3\(5),
      I4 => \dImd_reg[15]\(0),
      I5 => \dImd_reg[15]_4\(5),
      O => \dImd[13]_i_2_n_0\
    );
\dImd[14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[14]_i_2_n_0\,
      I1 => \dImd_reg[15]\(2),
      I2 => \dImd_reg[15]_0\(6),
      I3 => \dImd_reg[15]_1\,
      O => D(6)
    );
\dImd[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(6),
      I1 => \dImd_reg[15]_2\(6),
      I2 => \dImd_reg[15]\(1),
      I3 => \dImd_reg[15]_3\(6),
      I4 => \dImd_reg[15]\(0),
      I5 => \dImd_reg[15]_4\(6),
      O => \dImd[14]_i_2_n_0\
    );
\dImd[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[15]_i_2_n_0\,
      I1 => \dImd_reg[15]\(2),
      I2 => \dImd_reg[15]_0\(7),
      I3 => \dImd_reg[15]_1\,
      O => D(7)
    );
\dImd[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(7),
      I1 => \dImd_reg[15]_2\(7),
      I2 => \dImd_reg[15]\(1),
      I3 => \dImd_reg[15]_3\(7),
      I4 => \dImd_reg[15]\(0),
      I5 => \dImd_reg[15]_4\(7),
      O => \dImd[15]_i_2_n_0\
    );
\dImd[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[8]_i_2_n_0\,
      I1 => \dImd_reg[15]\(2),
      I2 => \dImd_reg[15]_0\(0),
      I3 => \dImd_reg[15]_1\,
      O => D(0)
    );
\dImd[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(0),
      I1 => \dImd_reg[15]_2\(0),
      I2 => \dImd_reg[15]\(1),
      I3 => \dImd_reg[15]_3\(0),
      I4 => \dImd_reg[15]\(0),
      I5 => \dImd_reg[15]_4\(0),
      O => \dImd[8]_i_2_n_0\
    );
\dImd[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \dImd[9]_i_2_n_0\,
      I1 => \dImd_reg[15]\(2),
      I2 => \dImd_reg[15]_0\(1),
      I3 => \dImd_reg[15]_1\,
      O => D(1)
    );
\dImd[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(1),
      I1 => \dImd_reg[15]_2\(1),
      I2 => \dImd_reg[15]\(1),
      I3 => \dImd_reg[15]_3\(1),
      I4 => \dImd_reg[15]\(0),
      I5 => \dImd_reg[15]_4\(1),
      O => \dImd[9]_i_2_n_0\
    );
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size2kB_a8b8__6\
     port map (
      addra(10 downto 0) => Q(10 downto 0),
      addrb(10 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(10 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(7 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(7 downto 0),
      dinb(7 downto 0) => B"00000000",
      douta(7 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(7 downto 0),
      doutb(7 downto 0) => \^doutb\(7 downto 0),
      ena => \myMnfcore_i_1__8_n_0\,
      enb => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000000"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\,
      I1 => \dImd_reg[15]\(2),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\,
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_3\,
      I4 => \dImd_reg[15]\(0),
      I5 => \dImd_reg[15]\(1),
      O => \myMnfcore_i_1__8_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_size38kB_a8b64 is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\ : in STD_LOGIC_VECTOR ( 12 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_size38kB_a8b64 : entity is "Dpbram_size38kB_a8b64";
end design_1_Vsp_core_0_0_Dpbram_size38kB_a8b64;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_size38kB_a8b64 is
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size38kB_a8b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
myMnfcore: entity work.design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64
     port map (
      addra(15 downto 0) => B"0000000000000000",
      addrb(12 downto 0) => \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(12 downto 0),
      clka => '0',
      clkb => aclk_sig,
      dina(7 downto 0) => B"00000000",
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(7 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(7 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      ena => '0',
      enb => Q(0),
      wea(0) => '1',
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size38kB_a8b64__xdcDup__1\ is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    aclk_sig : in STD_LOGIC;
    \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size38kB_a8b64__xdcDup__1\ : entity is "Dpbram_size38kB_a8b64";
end \design_1_Vsp_core_0_0_Dpbram_size38kB_a8b64__xdcDup__1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size38kB_a8b64__xdcDup__1\ is
  signal enA : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size38kB_a8b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size38kB_a8b64__2\
     port map (
      addra(15 downto 0) => Q(15 downto 0),
      addrb(12 downto 0) => \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(12 downto 0),
      clka => '0',
      clkb => aclk_sig,
      dina(7 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(7 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(7 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      ena => enA,
      enb => \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\(0),
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0),
      O => enA
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64 is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    aclk_sig : in STD_LOGIC;
    ena : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64 : entity is "Dpbram_size4kB_a32b64";
end design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64 is
  signal enSeqbufB : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size4kB_a32b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__5\
     port map (
      addra(9 downto 0) => Q(9 downto 0),
      addrb(8 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(31 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(31 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(31 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(31 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      ena => ena,
      enb => enSeqbufB,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => enSeqbufB
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__1\ is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    aclk_sig : in STD_LOGIC;
    ena : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__1\ : entity is "Dpbram_size4kB_a32b64";
end \design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__1\ is
  signal enSeqbufB : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size4kB_a32b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__6\
     port map (
      addra(9 downto 0) => Q(9 downto 0),
      addrb(8 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(31 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(31 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(31 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(31 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      ena => ena,
      enb => enSeqbufB,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => enSeqbufB
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__2\ is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    aclk_sig : in STD_LOGIC;
    ena : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__2\ : entity is "Dpbram_size4kB_a32b64";
end \design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__2\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__2\ is
  signal enSeqbufB : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size4kB_a32b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
myMnfcore: entity work.design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64
     port map (
      addra(9 downto 0) => Q(9 downto 0),
      addrb(8 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(31 downto 30) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(23 downto 22),
      dina(29 downto 22) => B"00000000",
      dina(21 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(21 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(31 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(31 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      ena => ena,
      enb => enSeqbufB,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => enSeqbufB
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__3\ is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    memclk : in STD_LOGIC;
    ena : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 26 downto 0 );
    aclk_sig : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__3\ : entity is "Dpbram_size4kB_a32b64";
end \design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__3\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__3\ is
  signal enSeqbufB : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size4kB_a32b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a32b64__4\
     port map (
      addra(9 downto 0) => Q(9 downto 0),
      addrb(8 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8 downto 0),
      clka => memclk,
      clkb => aclk_sig,
      dina(31 downto 30) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(26 downto 25),
      dina(29 downto 25) => B"00000",
      dina(24 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(24 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(31 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(31 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      ena => ena,
      enb => enSeqbufB,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
      O => enSeqbufB
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64 is
  port (
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    enb : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \gr4_reg[4]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gr4_reg[4]_0\ : in STD_LOGIC;
    \drdRow4bufBm1_reg[60]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gr4_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64 : entity is "Dpbram_size4kB_a64b64";
end design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64 is
  signal drdRow4bufB : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \gr4[10]_i_3_n_0\ : STD_LOGIC;
  signal \gr4[10]_i_4_n_0\ : STD_LOGIC;
  signal \gr4[10]_i_5_n_0\ : STD_LOGIC;
  signal \gr4[10]_i_6_n_0\ : STD_LOGIC;
  signal \gr4[11]_i_4_n_0\ : STD_LOGIC;
  signal \gr4[11]_i_5_n_0\ : STD_LOGIC;
  signal \gr4[11]_i_6_n_0\ : STD_LOGIC;
  signal \gr4[11]_i_7_n_0\ : STD_LOGIC;
  signal \gr4[4]_i_3_n_0\ : STD_LOGIC;
  signal \gr4[4]_i_4_n_0\ : STD_LOGIC;
  signal \gr4[4]_i_5_n_0\ : STD_LOGIC;
  signal \gr4[4]_i_6_n_0\ : STD_LOGIC;
  signal \gr4[5]_i_3_n_0\ : STD_LOGIC;
  signal \gr4[5]_i_4_n_0\ : STD_LOGIC;
  signal \gr4[5]_i_5_n_0\ : STD_LOGIC;
  signal \gr4[5]_i_6_n_0\ : STD_LOGIC;
  signal \gr4[6]_i_3_n_0\ : STD_LOGIC;
  signal \gr4[6]_i_4_n_0\ : STD_LOGIC;
  signal \gr4[6]_i_5_n_0\ : STD_LOGIC;
  signal \gr4[6]_i_6_n_0\ : STD_LOGIC;
  signal \gr4[7]_i_3_n_0\ : STD_LOGIC;
  signal \gr4[7]_i_4_n_0\ : STD_LOGIC;
  signal \gr4[7]_i_5_n_0\ : STD_LOGIC;
  signal \gr4[7]_i_6_n_0\ : STD_LOGIC;
  signal \gr4[8]_i_3_n_0\ : STD_LOGIC;
  signal \gr4[8]_i_4_n_0\ : STD_LOGIC;
  signal \gr4[8]_i_5_n_0\ : STD_LOGIC;
  signal \gr4[8]_i_6_n_0\ : STD_LOGIC;
  signal \gr4[9]_i_3_n_0\ : STD_LOGIC;
  signal \gr4[9]_i_4_n_0\ : STD_LOGIC;
  signal \gr4[9]_i_5_n_0\ : STD_LOGIC;
  signal \gr4[9]_i_6_n_0\ : STD_LOGIC;
  signal \gr4_reg[10]_i_2_n_0\ : STD_LOGIC;
  signal \gr4_reg[11]_i_3_n_0\ : STD_LOGIC;
  signal \gr4_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \gr4_reg[5]_i_2_n_0\ : STD_LOGIC;
  signal \gr4_reg[6]_i_2_n_0\ : STD_LOGIC;
  signal \gr4_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \gr4_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \gr4_reg[9]_i_2_n_0\ : STD_LOGIC;
  signal \myMnfcore_i_1__13_n_0\ : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \drdRow4bufBm1[60]_i_1\ : label is "soft_lutpair2955";
  attribute SOFT_HLUTNM of \drdRow4bufBm1[61]_i_1\ : label is "soft_lutpair2955";
  attribute SOFT_HLUTNM of \drdRow4bufBm1[62]_i_1\ : label is "soft_lutpair2956";
  attribute SOFT_HLUTNM of \drdRow4bufBm1[63]_i_2\ : label is "soft_lutpair2956";
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size4kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
\drdRow4bufBm1[60]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow4bufB(60),
      I1 => \drdRow4bufBm1_reg[60]\(1),
      I2 => \drdRow4bufBm1_reg[60]\(2),
      I3 => \drdRow4bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0)
    );
\drdRow4bufBm1[61]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow4bufB(61),
      I1 => \drdRow4bufBm1_reg[60]\(1),
      I2 => \drdRow4bufBm1_reg[60]\(2),
      I3 => \drdRow4bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1)
    );
\drdRow4bufBm1[62]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow4bufB(62),
      I1 => \drdRow4bufBm1_reg[60]\(1),
      I2 => \drdRow4bufBm1_reg[60]\(2),
      I3 => \drdRow4bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2)
    );
\drdRow4bufBm1[63]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow4bufB(63),
      I1 => \drdRow4bufBm1_reg[60]\(1),
      I2 => \drdRow4bufBm1_reg[60]\(2),
      I3 => \drdRow4bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3)
    );
\gr4[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr4_reg[10]_i_2_n_0\,
      I1 => \gr4_reg[4]\(3),
      I2 => \gr4[10]_i_3_n_0\,
      I3 => \gr4_reg[4]\(2),
      I4 => \gr4[10]_i_4_n_0\,
      I5 => \gr4_reg[4]_0\,
      O => D(6)
    );
\gr4[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(14),
      I1 => drdRow4bufB(2),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(54),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(42),
      O => \gr4[10]_i_3_n_0\
    );
\gr4[10]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(62),
      I1 => drdRow4bufB(50),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(38),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(26),
      O => \gr4[10]_i_4_n_0\
    );
\gr4[10]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(46),
      I1 => drdRow4bufB(34),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(22),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(10),
      O => \gr4[10]_i_5_n_0\
    );
\gr4[10]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(30),
      I1 => drdRow4bufB(18),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(6),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(58),
      O => \gr4[10]_i_6_n_0\
    );
\gr4[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr4_reg[11]_i_3_n_0\,
      I1 => \gr4_reg[4]\(3),
      I2 => \gr4[11]_i_4_n_0\,
      I3 => \gr4_reg[4]\(2),
      I4 => \gr4[11]_i_5_n_0\,
      I5 => \gr4_reg[4]_0\,
      O => D(7)
    );
\gr4[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(15),
      I1 => drdRow4bufB(3),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(55),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(43),
      O => \gr4[11]_i_4_n_0\
    );
\gr4[11]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(63),
      I1 => drdRow4bufB(51),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(39),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(27),
      O => \gr4[11]_i_5_n_0\
    );
\gr4[11]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(47),
      I1 => drdRow4bufB(35),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(23),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(11),
      O => \gr4[11]_i_6_n_0\
    );
\gr4[11]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(31),
      I1 => drdRow4bufB(19),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(7),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(59),
      O => \gr4[11]_i_7_n_0\
    );
\gr4[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr4_reg[4]_i_2_n_0\,
      I1 => \gr4_reg[4]\(3),
      I2 => \gr4[4]_i_3_n_0\,
      I3 => \gr4_reg[4]\(2),
      I4 => \gr4[4]_i_4_n_0\,
      I5 => \gr4_reg[4]_0\,
      O => D(0)
    );
\gr4[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(8),
      I1 => \gr4_reg[7]\(0),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(48),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(36),
      O => \gr4[4]_i_3_n_0\
    );
\gr4[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(56),
      I1 => drdRow4bufB(44),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(32),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(20),
      O => \gr4[4]_i_4_n_0\
    );
\gr4[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(40),
      I1 => drdRow4bufB(28),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(16),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(4),
      O => \gr4[4]_i_5_n_0\
    );
\gr4[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(24),
      I1 => drdRow4bufB(12),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(0),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(52),
      O => \gr4[4]_i_6_n_0\
    );
\gr4[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr4_reg[5]_i_2_n_0\,
      I1 => \gr4_reg[4]\(3),
      I2 => \gr4[5]_i_3_n_0\,
      I3 => \gr4_reg[4]\(2),
      I4 => \gr4[5]_i_4_n_0\,
      I5 => \gr4_reg[4]_0\,
      O => D(1)
    );
\gr4[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(9),
      I1 => \gr4_reg[7]\(1),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(49),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(37),
      O => \gr4[5]_i_3_n_0\
    );
\gr4[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(57),
      I1 => drdRow4bufB(45),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(33),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(21),
      O => \gr4[5]_i_4_n_0\
    );
\gr4[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(41),
      I1 => drdRow4bufB(29),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(17),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(5),
      O => \gr4[5]_i_5_n_0\
    );
\gr4[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(25),
      I1 => drdRow4bufB(13),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(1),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(53),
      O => \gr4[5]_i_6_n_0\
    );
\gr4[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr4_reg[6]_i_2_n_0\,
      I1 => \gr4_reg[4]\(3),
      I2 => \gr4[6]_i_3_n_0\,
      I3 => \gr4_reg[4]\(2),
      I4 => \gr4[6]_i_4_n_0\,
      I5 => \gr4_reg[4]_0\,
      O => D(2)
    );
\gr4[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(10),
      I1 => \gr4_reg[7]\(2),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(50),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(38),
      O => \gr4[6]_i_3_n_0\
    );
\gr4[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(58),
      I1 => drdRow4bufB(46),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(34),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(22),
      O => \gr4[6]_i_4_n_0\
    );
\gr4[6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(42),
      I1 => drdRow4bufB(30),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(18),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(6),
      O => \gr4[6]_i_5_n_0\
    );
\gr4[6]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(26),
      I1 => drdRow4bufB(14),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(2),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(54),
      O => \gr4[6]_i_6_n_0\
    );
\gr4[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr4_reg[7]_i_2_n_0\,
      I1 => \gr4_reg[4]\(3),
      I2 => \gr4[7]_i_3_n_0\,
      I3 => \gr4_reg[4]\(2),
      I4 => \gr4[7]_i_4_n_0\,
      I5 => \gr4_reg[4]_0\,
      O => D(3)
    );
\gr4[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(11),
      I1 => \gr4_reg[7]\(3),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(51),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(39),
      O => \gr4[7]_i_3_n_0\
    );
\gr4[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(59),
      I1 => drdRow4bufB(47),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(35),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(23),
      O => \gr4[7]_i_4_n_0\
    );
\gr4[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(43),
      I1 => drdRow4bufB(31),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(19),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(7),
      O => \gr4[7]_i_5_n_0\
    );
\gr4[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(27),
      I1 => drdRow4bufB(15),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(3),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(55),
      O => \gr4[7]_i_6_n_0\
    );
\gr4[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr4_reg[8]_i_2_n_0\,
      I1 => \gr4_reg[4]\(3),
      I2 => \gr4[8]_i_3_n_0\,
      I3 => \gr4_reg[4]\(2),
      I4 => \gr4[8]_i_4_n_0\,
      I5 => \gr4_reg[4]_0\,
      O => D(4)
    );
\gr4[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(12),
      I1 => drdRow4bufB(0),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(52),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(40),
      O => \gr4[8]_i_3_n_0\
    );
\gr4[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(60),
      I1 => drdRow4bufB(48),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(36),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(24),
      O => \gr4[8]_i_4_n_0\
    );
\gr4[8]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(44),
      I1 => drdRow4bufB(32),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(20),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(8),
      O => \gr4[8]_i_5_n_0\
    );
\gr4[8]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(28),
      I1 => drdRow4bufB(16),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(4),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(56),
      O => \gr4[8]_i_6_n_0\
    );
\gr4[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr4_reg[9]_i_2_n_0\,
      I1 => \gr4_reg[4]\(3),
      I2 => \gr4[9]_i_3_n_0\,
      I3 => \gr4_reg[4]\(2),
      I4 => \gr4[9]_i_4_n_0\,
      I5 => \gr4_reg[4]_0\,
      O => D(5)
    );
\gr4[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(13),
      I1 => drdRow4bufB(1),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(53),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(41),
      O => \gr4[9]_i_3_n_0\
    );
\gr4[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(61),
      I1 => drdRow4bufB(49),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(37),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(25),
      O => \gr4[9]_i_4_n_0\
    );
\gr4[9]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(45),
      I1 => drdRow4bufB(33),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(21),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(9),
      O => \gr4[9]_i_5_n_0\
    );
\gr4[9]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow4bufB(29),
      I1 => drdRow4bufB(17),
      I2 => \gr4_reg[4]\(1),
      I3 => drdRow4bufB(5),
      I4 => \gr4_reg[4]\(0),
      I5 => drdRow4bufB(57),
      O => \gr4[9]_i_6_n_0\
    );
\gr4_reg[10]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr4[10]_i_5_n_0\,
      I1 => \gr4[10]_i_6_n_0\,
      O => \gr4_reg[10]_i_2_n_0\,
      S => \gr4_reg[4]\(2)
    );
\gr4_reg[11]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr4[11]_i_6_n_0\,
      I1 => \gr4[11]_i_7_n_0\,
      O => \gr4_reg[11]_i_3_n_0\,
      S => \gr4_reg[4]\(2)
    );
\gr4_reg[4]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr4[4]_i_5_n_0\,
      I1 => \gr4[4]_i_6_n_0\,
      O => \gr4_reg[4]_i_2_n_0\,
      S => \gr4_reg[4]\(2)
    );
\gr4_reg[5]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr4[5]_i_5_n_0\,
      I1 => \gr4[5]_i_6_n_0\,
      O => \gr4_reg[5]_i_2_n_0\,
      S => \gr4_reg[4]\(2)
    );
\gr4_reg[6]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr4[6]_i_5_n_0\,
      I1 => \gr4[6]_i_6_n_0\,
      O => \gr4_reg[6]_i_2_n_0\,
      S => \gr4_reg[4]\(2)
    );
\gr4_reg[7]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr4[7]_i_5_n_0\,
      I1 => \gr4[7]_i_6_n_0\,
      O => \gr4_reg[7]_i_2_n_0\,
      S => \gr4_reg[4]\(2)
    );
\gr4_reg[8]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr4[8]_i_5_n_0\,
      I1 => \gr4[8]_i_6_n_0\,
      O => \gr4_reg[8]_i_2_n_0\,
      S => \gr4_reg[4]\(2)
    );
\gr4_reg[9]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr4[9]_i_5_n_0\,
      I1 => \gr4[9]_i_6_n_0\,
      O => \gr4_reg[9]_i_2_n_0\,
      S => \gr4_reg[4]\(2)
    );
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__5\
     port map (
      addra(8 downto 0) => Q(8 downto 0),
      addrb(8 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(8 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(63 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => drdRow4bufB(63 downto 0),
      ena => \myMnfcore_i_1__13_n_0\,
      enb => enb,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\,
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(2),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(1),
      O => \myMnfcore_i_1__13_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__1\ is
  port (
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    enb : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \gr0_reg[4]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gr0_reg[4]_0\ : in STD_LOGIC;
    \drdRow0bufBm1_reg[60]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC;
    \gr0_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__1\ : entity is "Dpbram_size4kB_a64b64";
end \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__1\ is
  signal drdRow0bufB : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \gr0[10]_i_3_n_0\ : STD_LOGIC;
  signal \gr0[10]_i_4_n_0\ : STD_LOGIC;
  signal \gr0[10]_i_5_n_0\ : STD_LOGIC;
  signal \gr0[10]_i_6_n_0\ : STD_LOGIC;
  signal \gr0[11]_i_3_n_0\ : STD_LOGIC;
  signal \gr0[11]_i_4_n_0\ : STD_LOGIC;
  signal \gr0[11]_i_5_n_0\ : STD_LOGIC;
  signal \gr0[11]_i_6_n_0\ : STD_LOGIC;
  signal \gr0[4]_i_3_n_0\ : STD_LOGIC;
  signal \gr0[4]_i_4_n_0\ : STD_LOGIC;
  signal \gr0[4]_i_5_n_0\ : STD_LOGIC;
  signal \gr0[4]_i_6_n_0\ : STD_LOGIC;
  signal \gr0[5]_i_3_n_0\ : STD_LOGIC;
  signal \gr0[5]_i_4_n_0\ : STD_LOGIC;
  signal \gr0[5]_i_5_n_0\ : STD_LOGIC;
  signal \gr0[5]_i_6_n_0\ : STD_LOGIC;
  signal \gr0[6]_i_3_n_0\ : STD_LOGIC;
  signal \gr0[6]_i_4_n_0\ : STD_LOGIC;
  signal \gr0[6]_i_5_n_0\ : STD_LOGIC;
  signal \gr0[6]_i_6_n_0\ : STD_LOGIC;
  signal \gr0[7]_i_3_n_0\ : STD_LOGIC;
  signal \gr0[7]_i_4_n_0\ : STD_LOGIC;
  signal \gr0[7]_i_5_n_0\ : STD_LOGIC;
  signal \gr0[7]_i_6_n_0\ : STD_LOGIC;
  signal \gr0[8]_i_3_n_0\ : STD_LOGIC;
  signal \gr0[8]_i_4_n_0\ : STD_LOGIC;
  signal \gr0[8]_i_5_n_0\ : STD_LOGIC;
  signal \gr0[8]_i_6_n_0\ : STD_LOGIC;
  signal \gr0[9]_i_3_n_0\ : STD_LOGIC;
  signal \gr0[9]_i_4_n_0\ : STD_LOGIC;
  signal \gr0[9]_i_5_n_0\ : STD_LOGIC;
  signal \gr0[9]_i_6_n_0\ : STD_LOGIC;
  signal \gr0_reg[10]_i_2_n_0\ : STD_LOGIC;
  signal \gr0_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \gr0_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \gr0_reg[5]_i_2_n_0\ : STD_LOGIC;
  signal \gr0_reg[6]_i_2_n_0\ : STD_LOGIC;
  signal \gr0_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \gr0_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \gr0_reg[9]_i_2_n_0\ : STD_LOGIC;
  signal \myMnfcore_i_1__14_n_0\ : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \drdRow0bufBm1[60]_i_1\ : label is "soft_lutpair2947";
  attribute SOFT_HLUTNM of \drdRow0bufBm1[61]_i_1\ : label is "soft_lutpair2947";
  attribute SOFT_HLUTNM of \drdRow0bufBm1[62]_i_1\ : label is "soft_lutpair2948";
  attribute SOFT_HLUTNM of \drdRow0bufBm1[63]_i_1\ : label is "soft_lutpair2948";
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size4kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
\drdRow0bufBm1[60]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow0bufB(60),
      I1 => \drdRow0bufBm1_reg[60]\(1),
      I2 => \drdRow0bufBm1_reg[60]\(2),
      I3 => \drdRow0bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0)
    );
\drdRow0bufBm1[61]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow0bufB(61),
      I1 => \drdRow0bufBm1_reg[60]\(1),
      I2 => \drdRow0bufBm1_reg[60]\(2),
      I3 => \drdRow0bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1)
    );
\drdRow0bufBm1[62]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow0bufB(62),
      I1 => \drdRow0bufBm1_reg[60]\(1),
      I2 => \drdRow0bufBm1_reg[60]\(2),
      I3 => \drdRow0bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2)
    );
\drdRow0bufBm1[63]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow0bufB(63),
      I1 => \drdRow0bufBm1_reg[60]\(1),
      I2 => \drdRow0bufBm1_reg[60]\(2),
      I3 => \drdRow0bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3)
    );
\gr0[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr0_reg[10]_i_2_n_0\,
      I1 => \gr0_reg[4]\(3),
      I2 => \gr0[10]_i_3_n_0\,
      I3 => \gr0_reg[4]\(2),
      I4 => \gr0[10]_i_4_n_0\,
      I5 => \gr0_reg[4]_0\,
      O => D(6)
    );
\gr0[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(14),
      I1 => drdRow0bufB(2),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(54),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(42),
      O => \gr0[10]_i_3_n_0\
    );
\gr0[10]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(62),
      I1 => drdRow0bufB(50),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(38),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(26),
      O => \gr0[10]_i_4_n_0\
    );
\gr0[10]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(46),
      I1 => drdRow0bufB(34),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(22),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(10),
      O => \gr0[10]_i_5_n_0\
    );
\gr0[10]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(30),
      I1 => drdRow0bufB(18),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(6),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(58),
      O => \gr0[10]_i_6_n_0\
    );
\gr0[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr0_reg[11]_i_2_n_0\,
      I1 => \gr0_reg[4]\(3),
      I2 => \gr0[11]_i_3_n_0\,
      I3 => \gr0_reg[4]\(2),
      I4 => \gr0[11]_i_4_n_0\,
      I5 => \gr0_reg[4]_0\,
      O => D(7)
    );
\gr0[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(15),
      I1 => drdRow0bufB(3),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(55),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(43),
      O => \gr0[11]_i_3_n_0\
    );
\gr0[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(63),
      I1 => drdRow0bufB(51),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(39),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(27),
      O => \gr0[11]_i_4_n_0\
    );
\gr0[11]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(47),
      I1 => drdRow0bufB(35),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(23),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(11),
      O => \gr0[11]_i_5_n_0\
    );
\gr0[11]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(31),
      I1 => drdRow0bufB(19),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(7),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(59),
      O => \gr0[11]_i_6_n_0\
    );
\gr0[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr0_reg[4]_i_2_n_0\,
      I1 => \gr0_reg[4]\(3),
      I2 => \gr0[4]_i_3_n_0\,
      I3 => \gr0_reg[4]\(2),
      I4 => \gr0[4]_i_4_n_0\,
      I5 => \gr0_reg[4]_0\,
      O => D(0)
    );
\gr0[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(8),
      I1 => \gr0_reg[7]\(0),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(48),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(36),
      O => \gr0[4]_i_3_n_0\
    );
\gr0[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(56),
      I1 => drdRow0bufB(44),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(32),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(20),
      O => \gr0[4]_i_4_n_0\
    );
\gr0[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(40),
      I1 => drdRow0bufB(28),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(16),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(4),
      O => \gr0[4]_i_5_n_0\
    );
\gr0[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(24),
      I1 => drdRow0bufB(12),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(0),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(52),
      O => \gr0[4]_i_6_n_0\
    );
\gr0[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr0_reg[5]_i_2_n_0\,
      I1 => \gr0_reg[4]\(3),
      I2 => \gr0[5]_i_3_n_0\,
      I3 => \gr0_reg[4]\(2),
      I4 => \gr0[5]_i_4_n_0\,
      I5 => \gr0_reg[4]_0\,
      O => D(1)
    );
\gr0[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(9),
      I1 => \gr0_reg[7]\(1),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(49),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(37),
      O => \gr0[5]_i_3_n_0\
    );
\gr0[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(57),
      I1 => drdRow0bufB(45),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(33),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(21),
      O => \gr0[5]_i_4_n_0\
    );
\gr0[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(41),
      I1 => drdRow0bufB(29),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(17),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(5),
      O => \gr0[5]_i_5_n_0\
    );
\gr0[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(25),
      I1 => drdRow0bufB(13),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(1),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(53),
      O => \gr0[5]_i_6_n_0\
    );
\gr0[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr0_reg[6]_i_2_n_0\,
      I1 => \gr0_reg[4]\(3),
      I2 => \gr0[6]_i_3_n_0\,
      I3 => \gr0_reg[4]\(2),
      I4 => \gr0[6]_i_4_n_0\,
      I5 => \gr0_reg[4]_0\,
      O => D(2)
    );
\gr0[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(10),
      I1 => \gr0_reg[7]\(2),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(50),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(38),
      O => \gr0[6]_i_3_n_0\
    );
\gr0[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(58),
      I1 => drdRow0bufB(46),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(34),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(22),
      O => \gr0[6]_i_4_n_0\
    );
\gr0[6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(42),
      I1 => drdRow0bufB(30),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(18),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(6),
      O => \gr0[6]_i_5_n_0\
    );
\gr0[6]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(26),
      I1 => drdRow0bufB(14),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(2),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(54),
      O => \gr0[6]_i_6_n_0\
    );
\gr0[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr0_reg[7]_i_2_n_0\,
      I1 => \gr0_reg[4]\(3),
      I2 => \gr0[7]_i_3_n_0\,
      I3 => \gr0_reg[4]\(2),
      I4 => \gr0[7]_i_4_n_0\,
      I5 => \gr0_reg[4]_0\,
      O => D(3)
    );
\gr0[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(11),
      I1 => \gr0_reg[7]\(3),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(51),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(39),
      O => \gr0[7]_i_3_n_0\
    );
\gr0[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(59),
      I1 => drdRow0bufB(47),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(35),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(23),
      O => \gr0[7]_i_4_n_0\
    );
\gr0[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(43),
      I1 => drdRow0bufB(31),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(19),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(7),
      O => \gr0[7]_i_5_n_0\
    );
\gr0[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(27),
      I1 => drdRow0bufB(15),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(3),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(55),
      O => \gr0[7]_i_6_n_0\
    );
\gr0[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr0_reg[8]_i_2_n_0\,
      I1 => \gr0_reg[4]\(3),
      I2 => \gr0[8]_i_3_n_0\,
      I3 => \gr0_reg[4]\(2),
      I4 => \gr0[8]_i_4_n_0\,
      I5 => \gr0_reg[4]_0\,
      O => D(4)
    );
\gr0[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(12),
      I1 => drdRow0bufB(0),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(52),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(40),
      O => \gr0[8]_i_3_n_0\
    );
\gr0[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(60),
      I1 => drdRow0bufB(48),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(36),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(24),
      O => \gr0[8]_i_4_n_0\
    );
\gr0[8]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(44),
      I1 => drdRow0bufB(32),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(20),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(8),
      O => \gr0[8]_i_5_n_0\
    );
\gr0[8]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(28),
      I1 => drdRow0bufB(16),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(4),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(56),
      O => \gr0[8]_i_6_n_0\
    );
\gr0[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr0_reg[9]_i_2_n_0\,
      I1 => \gr0_reg[4]\(3),
      I2 => \gr0[9]_i_3_n_0\,
      I3 => \gr0_reg[4]\(2),
      I4 => \gr0[9]_i_4_n_0\,
      I5 => \gr0_reg[4]_0\,
      O => D(5)
    );
\gr0[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(13),
      I1 => drdRow0bufB(1),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(53),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(41),
      O => \gr0[9]_i_3_n_0\
    );
\gr0[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(61),
      I1 => drdRow0bufB(49),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(37),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(25),
      O => \gr0[9]_i_4_n_0\
    );
\gr0[9]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(45),
      I1 => drdRow0bufB(33),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(21),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(9),
      O => \gr0[9]_i_5_n_0\
    );
\gr0[9]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow0bufB(29),
      I1 => drdRow0bufB(17),
      I2 => \gr0_reg[4]\(1),
      I3 => drdRow0bufB(5),
      I4 => \gr0_reg[4]\(0),
      I5 => drdRow0bufB(57),
      O => \gr0[9]_i_6_n_0\
    );
\gr0_reg[10]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr0[10]_i_5_n_0\,
      I1 => \gr0[10]_i_6_n_0\,
      O => \gr0_reg[10]_i_2_n_0\,
      S => \gr0_reg[4]\(2)
    );
\gr0_reg[11]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr0[11]_i_5_n_0\,
      I1 => \gr0[11]_i_6_n_0\,
      O => \gr0_reg[11]_i_2_n_0\,
      S => \gr0_reg[4]\(2)
    );
\gr0_reg[4]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr0[4]_i_5_n_0\,
      I1 => \gr0[4]_i_6_n_0\,
      O => \gr0_reg[4]_i_2_n_0\,
      S => \gr0_reg[4]\(2)
    );
\gr0_reg[5]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr0[5]_i_5_n_0\,
      I1 => \gr0[5]_i_6_n_0\,
      O => \gr0_reg[5]_i_2_n_0\,
      S => \gr0_reg[4]\(2)
    );
\gr0_reg[6]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr0[6]_i_5_n_0\,
      I1 => \gr0[6]_i_6_n_0\,
      O => \gr0_reg[6]_i_2_n_0\,
      S => \gr0_reg[4]\(2)
    );
\gr0_reg[7]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr0[7]_i_5_n_0\,
      I1 => \gr0[7]_i_6_n_0\,
      O => \gr0_reg[7]_i_2_n_0\,
      S => \gr0_reg[4]\(2)
    );
\gr0_reg[8]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr0[8]_i_5_n_0\,
      I1 => \gr0[8]_i_6_n_0\,
      O => \gr0_reg[8]_i_2_n_0\,
      S => \gr0_reg[4]\(2)
    );
\gr0_reg[9]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr0[9]_i_5_n_0\,
      I1 => \gr0[9]_i_6_n_0\,
      O => \gr0_reg[9]_i_2_n_0\,
      S => \gr0_reg[4]\(2)
    );
myMnfcore: entity work.design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64
     port map (
      addra(8 downto 0) => Q(8 downto 0),
      addrb(8 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(8 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(63 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => drdRow0bufB(63 downto 0),
      ena => \myMnfcore_i_1__14_n_0\,
      enb => enb,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(1),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\,
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(2),
      O => \myMnfcore_i_1__14_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__2\ is
  port (
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    enb : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \gr1_reg[4]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gr1_reg[4]_0\ : in STD_LOGIC;
    \drdRow1bufBm1_reg[60]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gr1_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__2\ : entity is "Dpbram_size4kB_a64b64";
end \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__2\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__2\ is
  signal drdRow1bufB : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal enA : STD_LOGIC;
  signal \gr1[10]_i_3_n_0\ : STD_LOGIC;
  signal \gr1[10]_i_4_n_0\ : STD_LOGIC;
  signal \gr1[10]_i_5_n_0\ : STD_LOGIC;
  signal \gr1[10]_i_6_n_0\ : STD_LOGIC;
  signal \gr1[11]_i_3_n_0\ : STD_LOGIC;
  signal \gr1[11]_i_4_n_0\ : STD_LOGIC;
  signal \gr1[11]_i_5_n_0\ : STD_LOGIC;
  signal \gr1[11]_i_6_n_0\ : STD_LOGIC;
  signal \gr1[4]_i_3_n_0\ : STD_LOGIC;
  signal \gr1[4]_i_4_n_0\ : STD_LOGIC;
  signal \gr1[4]_i_5_n_0\ : STD_LOGIC;
  signal \gr1[4]_i_6_n_0\ : STD_LOGIC;
  signal \gr1[5]_i_3_n_0\ : STD_LOGIC;
  signal \gr1[5]_i_4_n_0\ : STD_LOGIC;
  signal \gr1[5]_i_5_n_0\ : STD_LOGIC;
  signal \gr1[5]_i_6_n_0\ : STD_LOGIC;
  signal \gr1[6]_i_3_n_0\ : STD_LOGIC;
  signal \gr1[6]_i_4_n_0\ : STD_LOGIC;
  signal \gr1[6]_i_5_n_0\ : STD_LOGIC;
  signal \gr1[6]_i_6_n_0\ : STD_LOGIC;
  signal \gr1[7]_i_3_n_0\ : STD_LOGIC;
  signal \gr1[7]_i_4_n_0\ : STD_LOGIC;
  signal \gr1[7]_i_5_n_0\ : STD_LOGIC;
  signal \gr1[7]_i_6_n_0\ : STD_LOGIC;
  signal \gr1[8]_i_3_n_0\ : STD_LOGIC;
  signal \gr1[8]_i_4_n_0\ : STD_LOGIC;
  signal \gr1[8]_i_5_n_0\ : STD_LOGIC;
  signal \gr1[8]_i_6_n_0\ : STD_LOGIC;
  signal \gr1[9]_i_3_n_0\ : STD_LOGIC;
  signal \gr1[9]_i_4_n_0\ : STD_LOGIC;
  signal \gr1[9]_i_5_n_0\ : STD_LOGIC;
  signal \gr1[9]_i_6_n_0\ : STD_LOGIC;
  signal \gr1_reg[10]_i_2_n_0\ : STD_LOGIC;
  signal \gr1_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \gr1_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \gr1_reg[5]_i_2_n_0\ : STD_LOGIC;
  signal \gr1_reg[6]_i_2_n_0\ : STD_LOGIC;
  signal \gr1_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \gr1_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \gr1_reg[9]_i_2_n_0\ : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \drdRow1bufBm1[60]_i_1\ : label is "soft_lutpair2949";
  attribute SOFT_HLUTNM of \drdRow1bufBm1[61]_i_1\ : label is "soft_lutpair2949";
  attribute SOFT_HLUTNM of \drdRow1bufBm1[62]_i_1\ : label is "soft_lutpair2950";
  attribute SOFT_HLUTNM of \drdRow1bufBm1[63]_i_1\ : label is "soft_lutpair2950";
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size4kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
\drdRow1bufBm1[60]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow1bufB(60),
      I1 => \drdRow1bufBm1_reg[60]\(1),
      I2 => \drdRow1bufBm1_reg[60]\(2),
      I3 => \drdRow1bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0)
    );
\drdRow1bufBm1[61]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow1bufB(61),
      I1 => \drdRow1bufBm1_reg[60]\(1),
      I2 => \drdRow1bufBm1_reg[60]\(2),
      I3 => \drdRow1bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1)
    );
\drdRow1bufBm1[62]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow1bufB(62),
      I1 => \drdRow1bufBm1_reg[60]\(1),
      I2 => \drdRow1bufBm1_reg[60]\(2),
      I3 => \drdRow1bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2)
    );
\drdRow1bufBm1[63]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow1bufB(63),
      I1 => \drdRow1bufBm1_reg[60]\(1),
      I2 => \drdRow1bufBm1_reg[60]\(2),
      I3 => \drdRow1bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3)
    );
\gr1[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr1_reg[10]_i_2_n_0\,
      I1 => \gr1_reg[4]\(3),
      I2 => \gr1[10]_i_3_n_0\,
      I3 => \gr1_reg[4]\(2),
      I4 => \gr1[10]_i_4_n_0\,
      I5 => \gr1_reg[4]_0\,
      O => D(6)
    );
\gr1[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(14),
      I1 => drdRow1bufB(2),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(54),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(42),
      O => \gr1[10]_i_3_n_0\
    );
\gr1[10]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(62),
      I1 => drdRow1bufB(50),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(38),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(26),
      O => \gr1[10]_i_4_n_0\
    );
\gr1[10]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(46),
      I1 => drdRow1bufB(34),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(22),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(10),
      O => \gr1[10]_i_5_n_0\
    );
\gr1[10]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(30),
      I1 => drdRow1bufB(18),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(6),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(58),
      O => \gr1[10]_i_6_n_0\
    );
\gr1[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr1_reg[11]_i_2_n_0\,
      I1 => \gr1_reg[4]\(3),
      I2 => \gr1[11]_i_3_n_0\,
      I3 => \gr1_reg[4]\(2),
      I4 => \gr1[11]_i_4_n_0\,
      I5 => \gr1_reg[4]_0\,
      O => D(7)
    );
\gr1[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(15),
      I1 => drdRow1bufB(3),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(55),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(43),
      O => \gr1[11]_i_3_n_0\
    );
\gr1[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(63),
      I1 => drdRow1bufB(51),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(39),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(27),
      O => \gr1[11]_i_4_n_0\
    );
\gr1[11]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(47),
      I1 => drdRow1bufB(35),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(23),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(11),
      O => \gr1[11]_i_5_n_0\
    );
\gr1[11]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(31),
      I1 => drdRow1bufB(19),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(7),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(59),
      O => \gr1[11]_i_6_n_0\
    );
\gr1[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr1_reg[4]_i_2_n_0\,
      I1 => \gr1_reg[4]\(3),
      I2 => \gr1[4]_i_3_n_0\,
      I3 => \gr1_reg[4]\(2),
      I4 => \gr1[4]_i_4_n_0\,
      I5 => \gr1_reg[4]_0\,
      O => D(0)
    );
\gr1[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(8),
      I1 => \gr1_reg[7]\(0),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(48),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(36),
      O => \gr1[4]_i_3_n_0\
    );
\gr1[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(56),
      I1 => drdRow1bufB(44),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(32),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(20),
      O => \gr1[4]_i_4_n_0\
    );
\gr1[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(40),
      I1 => drdRow1bufB(28),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(16),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(4),
      O => \gr1[4]_i_5_n_0\
    );
\gr1[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(24),
      I1 => drdRow1bufB(12),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(0),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(52),
      O => \gr1[4]_i_6_n_0\
    );
\gr1[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr1_reg[5]_i_2_n_0\,
      I1 => \gr1_reg[4]\(3),
      I2 => \gr1[5]_i_3_n_0\,
      I3 => \gr1_reg[4]\(2),
      I4 => \gr1[5]_i_4_n_0\,
      I5 => \gr1_reg[4]_0\,
      O => D(1)
    );
\gr1[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(9),
      I1 => \gr1_reg[7]\(1),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(49),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(37),
      O => \gr1[5]_i_3_n_0\
    );
\gr1[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(57),
      I1 => drdRow1bufB(45),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(33),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(21),
      O => \gr1[5]_i_4_n_0\
    );
\gr1[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(41),
      I1 => drdRow1bufB(29),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(17),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(5),
      O => \gr1[5]_i_5_n_0\
    );
\gr1[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(25),
      I1 => drdRow1bufB(13),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(1),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(53),
      O => \gr1[5]_i_6_n_0\
    );
\gr1[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr1_reg[6]_i_2_n_0\,
      I1 => \gr1_reg[4]\(3),
      I2 => \gr1[6]_i_3_n_0\,
      I3 => \gr1_reg[4]\(2),
      I4 => \gr1[6]_i_4_n_0\,
      I5 => \gr1_reg[4]_0\,
      O => D(2)
    );
\gr1[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(10),
      I1 => \gr1_reg[7]\(2),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(50),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(38),
      O => \gr1[6]_i_3_n_0\
    );
\gr1[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(58),
      I1 => drdRow1bufB(46),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(34),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(22),
      O => \gr1[6]_i_4_n_0\
    );
\gr1[6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(42),
      I1 => drdRow1bufB(30),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(18),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(6),
      O => \gr1[6]_i_5_n_0\
    );
\gr1[6]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(26),
      I1 => drdRow1bufB(14),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(2),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(54),
      O => \gr1[6]_i_6_n_0\
    );
\gr1[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr1_reg[7]_i_2_n_0\,
      I1 => \gr1_reg[4]\(3),
      I2 => \gr1[7]_i_3_n_0\,
      I3 => \gr1_reg[4]\(2),
      I4 => \gr1[7]_i_4_n_0\,
      I5 => \gr1_reg[4]_0\,
      O => D(3)
    );
\gr1[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(11),
      I1 => \gr1_reg[7]\(3),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(51),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(39),
      O => \gr1[7]_i_3_n_0\
    );
\gr1[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(59),
      I1 => drdRow1bufB(47),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(35),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(23),
      O => \gr1[7]_i_4_n_0\
    );
\gr1[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(43),
      I1 => drdRow1bufB(31),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(19),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(7),
      O => \gr1[7]_i_5_n_0\
    );
\gr1[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(27),
      I1 => drdRow1bufB(15),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(3),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(55),
      O => \gr1[7]_i_6_n_0\
    );
\gr1[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr1_reg[8]_i_2_n_0\,
      I1 => \gr1_reg[4]\(3),
      I2 => \gr1[8]_i_3_n_0\,
      I3 => \gr1_reg[4]\(2),
      I4 => \gr1[8]_i_4_n_0\,
      I5 => \gr1_reg[4]_0\,
      O => D(4)
    );
\gr1[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(12),
      I1 => drdRow1bufB(0),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(52),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(40),
      O => \gr1[8]_i_3_n_0\
    );
\gr1[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(60),
      I1 => drdRow1bufB(48),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(36),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(24),
      O => \gr1[8]_i_4_n_0\
    );
\gr1[8]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(44),
      I1 => drdRow1bufB(32),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(20),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(8),
      O => \gr1[8]_i_5_n_0\
    );
\gr1[8]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(28),
      I1 => drdRow1bufB(16),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(4),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(56),
      O => \gr1[8]_i_6_n_0\
    );
\gr1[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr1_reg[9]_i_2_n_0\,
      I1 => \gr1_reg[4]\(3),
      I2 => \gr1[9]_i_3_n_0\,
      I3 => \gr1_reg[4]\(2),
      I4 => \gr1[9]_i_4_n_0\,
      I5 => \gr1_reg[4]_0\,
      O => D(5)
    );
\gr1[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(13),
      I1 => drdRow1bufB(1),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(53),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(41),
      O => \gr1[9]_i_3_n_0\
    );
\gr1[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(61),
      I1 => drdRow1bufB(49),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(37),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(25),
      O => \gr1[9]_i_4_n_0\
    );
\gr1[9]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(45),
      I1 => drdRow1bufB(33),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(21),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(9),
      O => \gr1[9]_i_5_n_0\
    );
\gr1[9]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow1bufB(29),
      I1 => drdRow1bufB(17),
      I2 => \gr1_reg[4]\(1),
      I3 => drdRow1bufB(5),
      I4 => \gr1_reg[4]\(0),
      I5 => drdRow1bufB(57),
      O => \gr1[9]_i_6_n_0\
    );
\gr1_reg[10]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr1[10]_i_5_n_0\,
      I1 => \gr1[10]_i_6_n_0\,
      O => \gr1_reg[10]_i_2_n_0\,
      S => \gr1_reg[4]\(2)
    );
\gr1_reg[11]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr1[11]_i_5_n_0\,
      I1 => \gr1[11]_i_6_n_0\,
      O => \gr1_reg[11]_i_2_n_0\,
      S => \gr1_reg[4]\(2)
    );
\gr1_reg[4]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr1[4]_i_5_n_0\,
      I1 => \gr1[4]_i_6_n_0\,
      O => \gr1_reg[4]_i_2_n_0\,
      S => \gr1_reg[4]\(2)
    );
\gr1_reg[5]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr1[5]_i_5_n_0\,
      I1 => \gr1[5]_i_6_n_0\,
      O => \gr1_reg[5]_i_2_n_0\,
      S => \gr1_reg[4]\(2)
    );
\gr1_reg[6]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr1[6]_i_5_n_0\,
      I1 => \gr1[6]_i_6_n_0\,
      O => \gr1_reg[6]_i_2_n_0\,
      S => \gr1_reg[4]\(2)
    );
\gr1_reg[7]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr1[7]_i_5_n_0\,
      I1 => \gr1[7]_i_6_n_0\,
      O => \gr1_reg[7]_i_2_n_0\,
      S => \gr1_reg[4]\(2)
    );
\gr1_reg[8]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr1[8]_i_5_n_0\,
      I1 => \gr1[8]_i_6_n_0\,
      O => \gr1_reg[8]_i_2_n_0\,
      S => \gr1_reg[4]\(2)
    );
\gr1_reg[9]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr1[9]_i_5_n_0\,
      I1 => \gr1[9]_i_6_n_0\,
      O => \gr1_reg[9]_i_2_n_0\,
      S => \gr1_reg[4]\(2)
    );
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__8\
     port map (
      addra(8 downto 0) => Q(8 downto 0),
      addrb(8 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(8 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(63 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => drdRow1bufB(63 downto 0),
      ena => enA,
      enb => enb,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(1),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\,
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(2),
      O => enA
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__3\ is
  port (
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    enb : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \gr2_reg[4]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gr2_reg[4]_0\ : in STD_LOGIC;
    \drdRow2bufBm1_reg[60]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gr2_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__3\ : entity is "Dpbram_size4kB_a64b64";
end \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__3\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__3\ is
  signal drdRow2bufB : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \gr2[10]_i_3_n_0\ : STD_LOGIC;
  signal \gr2[10]_i_4_n_0\ : STD_LOGIC;
  signal \gr2[10]_i_5_n_0\ : STD_LOGIC;
  signal \gr2[10]_i_6_n_0\ : STD_LOGIC;
  signal \gr2[11]_i_3_n_0\ : STD_LOGIC;
  signal \gr2[11]_i_4_n_0\ : STD_LOGIC;
  signal \gr2[11]_i_5_n_0\ : STD_LOGIC;
  signal \gr2[11]_i_6_n_0\ : STD_LOGIC;
  signal \gr2[4]_i_3_n_0\ : STD_LOGIC;
  signal \gr2[4]_i_4_n_0\ : STD_LOGIC;
  signal \gr2[4]_i_5_n_0\ : STD_LOGIC;
  signal \gr2[4]_i_6_n_0\ : STD_LOGIC;
  signal \gr2[5]_i_3_n_0\ : STD_LOGIC;
  signal \gr2[5]_i_4_n_0\ : STD_LOGIC;
  signal \gr2[5]_i_5_n_0\ : STD_LOGIC;
  signal \gr2[5]_i_6_n_0\ : STD_LOGIC;
  signal \gr2[6]_i_3_n_0\ : STD_LOGIC;
  signal \gr2[6]_i_4_n_0\ : STD_LOGIC;
  signal \gr2[6]_i_5_n_0\ : STD_LOGIC;
  signal \gr2[6]_i_6_n_0\ : STD_LOGIC;
  signal \gr2[7]_i_3_n_0\ : STD_LOGIC;
  signal \gr2[7]_i_4_n_0\ : STD_LOGIC;
  signal \gr2[7]_i_5_n_0\ : STD_LOGIC;
  signal \gr2[7]_i_6_n_0\ : STD_LOGIC;
  signal \gr2[8]_i_3_n_0\ : STD_LOGIC;
  signal \gr2[8]_i_4_n_0\ : STD_LOGIC;
  signal \gr2[8]_i_5_n_0\ : STD_LOGIC;
  signal \gr2[8]_i_6_n_0\ : STD_LOGIC;
  signal \gr2[9]_i_3_n_0\ : STD_LOGIC;
  signal \gr2[9]_i_4_n_0\ : STD_LOGIC;
  signal \gr2[9]_i_5_n_0\ : STD_LOGIC;
  signal \gr2[9]_i_6_n_0\ : STD_LOGIC;
  signal \gr2_reg[10]_i_2_n_0\ : STD_LOGIC;
  signal \gr2_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \gr2_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \gr2_reg[5]_i_2_n_0\ : STD_LOGIC;
  signal \gr2_reg[6]_i_2_n_0\ : STD_LOGIC;
  signal \gr2_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \gr2_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \gr2_reg[9]_i_2_n_0\ : STD_LOGIC;
  signal \myMnfcore_i_1__16_n_0\ : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \drdRow2bufBm1[60]_i_1\ : label is "soft_lutpair2951";
  attribute SOFT_HLUTNM of \drdRow2bufBm1[61]_i_1\ : label is "soft_lutpair2951";
  attribute SOFT_HLUTNM of \drdRow2bufBm1[62]_i_1\ : label is "soft_lutpair2952";
  attribute SOFT_HLUTNM of \drdRow2bufBm1[63]_i_1\ : label is "soft_lutpair2952";
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size4kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
\drdRow2bufBm1[60]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow2bufB(60),
      I1 => \drdRow2bufBm1_reg[60]\(1),
      I2 => \drdRow2bufBm1_reg[60]\(2),
      I3 => \drdRow2bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0)
    );
\drdRow2bufBm1[61]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow2bufB(61),
      I1 => \drdRow2bufBm1_reg[60]\(1),
      I2 => \drdRow2bufBm1_reg[60]\(2),
      I3 => \drdRow2bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1)
    );
\drdRow2bufBm1[62]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow2bufB(62),
      I1 => \drdRow2bufBm1_reg[60]\(1),
      I2 => \drdRow2bufBm1_reg[60]\(2),
      I3 => \drdRow2bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2)
    );
\drdRow2bufBm1[63]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow2bufB(63),
      I1 => \drdRow2bufBm1_reg[60]\(1),
      I2 => \drdRow2bufBm1_reg[60]\(2),
      I3 => \drdRow2bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3)
    );
\gr2[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr2_reg[10]_i_2_n_0\,
      I1 => \gr2_reg[4]\(3),
      I2 => \gr2[10]_i_3_n_0\,
      I3 => \gr2_reg[4]\(2),
      I4 => \gr2[10]_i_4_n_0\,
      I5 => \gr2_reg[4]_0\,
      O => D(6)
    );
\gr2[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(14),
      I1 => drdRow2bufB(2),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(54),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(42),
      O => \gr2[10]_i_3_n_0\
    );
\gr2[10]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(62),
      I1 => drdRow2bufB(50),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(38),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(26),
      O => \gr2[10]_i_4_n_0\
    );
\gr2[10]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(46),
      I1 => drdRow2bufB(34),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(22),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(10),
      O => \gr2[10]_i_5_n_0\
    );
\gr2[10]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(30),
      I1 => drdRow2bufB(18),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(6),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(58),
      O => \gr2[10]_i_6_n_0\
    );
\gr2[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr2_reg[11]_i_2_n_0\,
      I1 => \gr2_reg[4]\(3),
      I2 => \gr2[11]_i_3_n_0\,
      I3 => \gr2_reg[4]\(2),
      I4 => \gr2[11]_i_4_n_0\,
      I5 => \gr2_reg[4]_0\,
      O => D(7)
    );
\gr2[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(15),
      I1 => drdRow2bufB(3),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(55),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(43),
      O => \gr2[11]_i_3_n_0\
    );
\gr2[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(63),
      I1 => drdRow2bufB(51),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(39),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(27),
      O => \gr2[11]_i_4_n_0\
    );
\gr2[11]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(47),
      I1 => drdRow2bufB(35),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(23),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(11),
      O => \gr2[11]_i_5_n_0\
    );
\gr2[11]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(31),
      I1 => drdRow2bufB(19),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(7),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(59),
      O => \gr2[11]_i_6_n_0\
    );
\gr2[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr2_reg[4]_i_2_n_0\,
      I1 => \gr2_reg[4]\(3),
      I2 => \gr2[4]_i_3_n_0\,
      I3 => \gr2_reg[4]\(2),
      I4 => \gr2[4]_i_4_n_0\,
      I5 => \gr2_reg[4]_0\,
      O => D(0)
    );
\gr2[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(8),
      I1 => \gr2_reg[7]\(0),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(48),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(36),
      O => \gr2[4]_i_3_n_0\
    );
\gr2[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(56),
      I1 => drdRow2bufB(44),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(32),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(20),
      O => \gr2[4]_i_4_n_0\
    );
\gr2[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(40),
      I1 => drdRow2bufB(28),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(16),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(4),
      O => \gr2[4]_i_5_n_0\
    );
\gr2[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(24),
      I1 => drdRow2bufB(12),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(0),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(52),
      O => \gr2[4]_i_6_n_0\
    );
\gr2[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr2_reg[5]_i_2_n_0\,
      I1 => \gr2_reg[4]\(3),
      I2 => \gr2[5]_i_3_n_0\,
      I3 => \gr2_reg[4]\(2),
      I4 => \gr2[5]_i_4_n_0\,
      I5 => \gr2_reg[4]_0\,
      O => D(1)
    );
\gr2[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(9),
      I1 => \gr2_reg[7]\(1),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(49),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(37),
      O => \gr2[5]_i_3_n_0\
    );
\gr2[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(57),
      I1 => drdRow2bufB(45),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(33),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(21),
      O => \gr2[5]_i_4_n_0\
    );
\gr2[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(41),
      I1 => drdRow2bufB(29),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(17),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(5),
      O => \gr2[5]_i_5_n_0\
    );
\gr2[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(25),
      I1 => drdRow2bufB(13),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(1),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(53),
      O => \gr2[5]_i_6_n_0\
    );
\gr2[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr2_reg[6]_i_2_n_0\,
      I1 => \gr2_reg[4]\(3),
      I2 => \gr2[6]_i_3_n_0\,
      I3 => \gr2_reg[4]\(2),
      I4 => \gr2[6]_i_4_n_0\,
      I5 => \gr2_reg[4]_0\,
      O => D(2)
    );
\gr2[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(10),
      I1 => \gr2_reg[7]\(2),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(50),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(38),
      O => \gr2[6]_i_3_n_0\
    );
\gr2[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(58),
      I1 => drdRow2bufB(46),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(34),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(22),
      O => \gr2[6]_i_4_n_0\
    );
\gr2[6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(42),
      I1 => drdRow2bufB(30),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(18),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(6),
      O => \gr2[6]_i_5_n_0\
    );
\gr2[6]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(26),
      I1 => drdRow2bufB(14),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(2),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(54),
      O => \gr2[6]_i_6_n_0\
    );
\gr2[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr2_reg[7]_i_2_n_0\,
      I1 => \gr2_reg[4]\(3),
      I2 => \gr2[7]_i_3_n_0\,
      I3 => \gr2_reg[4]\(2),
      I4 => \gr2[7]_i_4_n_0\,
      I5 => \gr2_reg[4]_0\,
      O => D(3)
    );
\gr2[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(11),
      I1 => \gr2_reg[7]\(3),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(51),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(39),
      O => \gr2[7]_i_3_n_0\
    );
\gr2[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(59),
      I1 => drdRow2bufB(47),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(35),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(23),
      O => \gr2[7]_i_4_n_0\
    );
\gr2[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(43),
      I1 => drdRow2bufB(31),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(19),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(7),
      O => \gr2[7]_i_5_n_0\
    );
\gr2[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(27),
      I1 => drdRow2bufB(15),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(3),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(55),
      O => \gr2[7]_i_6_n_0\
    );
\gr2[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr2_reg[8]_i_2_n_0\,
      I1 => \gr2_reg[4]\(3),
      I2 => \gr2[8]_i_3_n_0\,
      I3 => \gr2_reg[4]\(2),
      I4 => \gr2[8]_i_4_n_0\,
      I5 => \gr2_reg[4]_0\,
      O => D(4)
    );
\gr2[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(12),
      I1 => drdRow2bufB(0),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(52),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(40),
      O => \gr2[8]_i_3_n_0\
    );
\gr2[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(60),
      I1 => drdRow2bufB(48),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(36),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(24),
      O => \gr2[8]_i_4_n_0\
    );
\gr2[8]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(44),
      I1 => drdRow2bufB(32),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(20),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(8),
      O => \gr2[8]_i_5_n_0\
    );
\gr2[8]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(28),
      I1 => drdRow2bufB(16),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(4),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(56),
      O => \gr2[8]_i_6_n_0\
    );
\gr2[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr2_reg[9]_i_2_n_0\,
      I1 => \gr2_reg[4]\(3),
      I2 => \gr2[9]_i_3_n_0\,
      I3 => \gr2_reg[4]\(2),
      I4 => \gr2[9]_i_4_n_0\,
      I5 => \gr2_reg[4]_0\,
      O => D(5)
    );
\gr2[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(13),
      I1 => drdRow2bufB(1),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(53),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(41),
      O => \gr2[9]_i_3_n_0\
    );
\gr2[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(61),
      I1 => drdRow2bufB(49),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(37),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(25),
      O => \gr2[9]_i_4_n_0\
    );
\gr2[9]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(45),
      I1 => drdRow2bufB(33),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(21),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(9),
      O => \gr2[9]_i_5_n_0\
    );
\gr2[9]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow2bufB(29),
      I1 => drdRow2bufB(17),
      I2 => \gr2_reg[4]\(1),
      I3 => drdRow2bufB(5),
      I4 => \gr2_reg[4]\(0),
      I5 => drdRow2bufB(57),
      O => \gr2[9]_i_6_n_0\
    );
\gr2_reg[10]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr2[10]_i_5_n_0\,
      I1 => \gr2[10]_i_6_n_0\,
      O => \gr2_reg[10]_i_2_n_0\,
      S => \gr2_reg[4]\(2)
    );
\gr2_reg[11]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr2[11]_i_5_n_0\,
      I1 => \gr2[11]_i_6_n_0\,
      O => \gr2_reg[11]_i_2_n_0\,
      S => \gr2_reg[4]\(2)
    );
\gr2_reg[4]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr2[4]_i_5_n_0\,
      I1 => \gr2[4]_i_6_n_0\,
      O => \gr2_reg[4]_i_2_n_0\,
      S => \gr2_reg[4]\(2)
    );
\gr2_reg[5]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr2[5]_i_5_n_0\,
      I1 => \gr2[5]_i_6_n_0\,
      O => \gr2_reg[5]_i_2_n_0\,
      S => \gr2_reg[4]\(2)
    );
\gr2_reg[6]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr2[6]_i_5_n_0\,
      I1 => \gr2[6]_i_6_n_0\,
      O => \gr2_reg[6]_i_2_n_0\,
      S => \gr2_reg[4]\(2)
    );
\gr2_reg[7]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr2[7]_i_5_n_0\,
      I1 => \gr2[7]_i_6_n_0\,
      O => \gr2_reg[7]_i_2_n_0\,
      S => \gr2_reg[4]\(2)
    );
\gr2_reg[8]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr2[8]_i_5_n_0\,
      I1 => \gr2[8]_i_6_n_0\,
      O => \gr2_reg[8]_i_2_n_0\,
      S => \gr2_reg[4]\(2)
    );
\gr2_reg[9]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr2[9]_i_5_n_0\,
      I1 => \gr2[9]_i_6_n_0\,
      O => \gr2_reg[9]_i_2_n_0\,
      S => \gr2_reg[4]\(2)
    );
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__7\
     port map (
      addra(8 downto 0) => Q(8 downto 0),
      addrb(8 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(8 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(63 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => drdRow2bufB(63 downto 0),
      ena => \myMnfcore_i_1__16_n_0\,
      enb => enb,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(1),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\,
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(2),
      O => \myMnfcore_i_1__16_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__4\ is
  port (
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    enb : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \gr3_reg[4]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \gr3_reg[4]_0\ : in STD_LOGIC;
    \drdRow3bufBm1_reg[60]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC;
    \gr3_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__4\ : entity is "Dpbram_size4kB_a64b64";
end \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__4\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__4\ is
  signal drdRow3bufB : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \gr3[10]_i_3_n_0\ : STD_LOGIC;
  signal \gr3[10]_i_4_n_0\ : STD_LOGIC;
  signal \gr3[10]_i_5_n_0\ : STD_LOGIC;
  signal \gr3[10]_i_6_n_0\ : STD_LOGIC;
  signal \gr3[11]_i_3_n_0\ : STD_LOGIC;
  signal \gr3[11]_i_4_n_0\ : STD_LOGIC;
  signal \gr3[11]_i_5_n_0\ : STD_LOGIC;
  signal \gr3[11]_i_6_n_0\ : STD_LOGIC;
  signal \gr3[4]_i_3_n_0\ : STD_LOGIC;
  signal \gr3[4]_i_4_n_0\ : STD_LOGIC;
  signal \gr3[4]_i_5_n_0\ : STD_LOGIC;
  signal \gr3[4]_i_6_n_0\ : STD_LOGIC;
  signal \gr3[5]_i_3_n_0\ : STD_LOGIC;
  signal \gr3[5]_i_4_n_0\ : STD_LOGIC;
  signal \gr3[5]_i_5_n_0\ : STD_LOGIC;
  signal \gr3[5]_i_6_n_0\ : STD_LOGIC;
  signal \gr3[6]_i_3_n_0\ : STD_LOGIC;
  signal \gr3[6]_i_4_n_0\ : STD_LOGIC;
  signal \gr3[6]_i_5_n_0\ : STD_LOGIC;
  signal \gr3[6]_i_6_n_0\ : STD_LOGIC;
  signal \gr3[7]_i_3_n_0\ : STD_LOGIC;
  signal \gr3[7]_i_4_n_0\ : STD_LOGIC;
  signal \gr3[7]_i_5_n_0\ : STD_LOGIC;
  signal \gr3[7]_i_6_n_0\ : STD_LOGIC;
  signal \gr3[8]_i_3_n_0\ : STD_LOGIC;
  signal \gr3[8]_i_4_n_0\ : STD_LOGIC;
  signal \gr3[8]_i_5_n_0\ : STD_LOGIC;
  signal \gr3[8]_i_6_n_0\ : STD_LOGIC;
  signal \gr3[9]_i_3_n_0\ : STD_LOGIC;
  signal \gr3[9]_i_4_n_0\ : STD_LOGIC;
  signal \gr3[9]_i_5_n_0\ : STD_LOGIC;
  signal \gr3[9]_i_6_n_0\ : STD_LOGIC;
  signal \gr3_reg[10]_i_2_n_0\ : STD_LOGIC;
  signal \gr3_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \gr3_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \gr3_reg[5]_i_2_n_0\ : STD_LOGIC;
  signal \gr3_reg[6]_i_2_n_0\ : STD_LOGIC;
  signal \gr3_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \gr3_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \gr3_reg[9]_i_2_n_0\ : STD_LOGIC;
  signal \myMnfcore_i_1__12_n_0\ : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \drdRow3bufBm1[60]_i_1\ : label is "soft_lutpair2953";
  attribute SOFT_HLUTNM of \drdRow3bufBm1[61]_i_1\ : label is "soft_lutpair2953";
  attribute SOFT_HLUTNM of \drdRow3bufBm1[62]_i_1\ : label is "soft_lutpair2954";
  attribute SOFT_HLUTNM of \drdRow3bufBm1[63]_i_1\ : label is "soft_lutpair2954";
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size4kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
begin
\drdRow3bufBm1[60]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow3bufB(60),
      I1 => \drdRow3bufBm1_reg[60]\(1),
      I2 => \drdRow3bufBm1_reg[60]\(2),
      I3 => \drdRow3bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0)
    );
\drdRow3bufBm1[61]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow3bufB(61),
      I1 => \drdRow3bufBm1_reg[60]\(1),
      I2 => \drdRow3bufBm1_reg[60]\(2),
      I3 => \drdRow3bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1)
    );
\drdRow3bufBm1[62]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow3bufB(62),
      I1 => \drdRow3bufBm1_reg[60]\(1),
      I2 => \drdRow3bufBm1_reg[60]\(2),
      I3 => \drdRow3bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2)
    );
\drdRow3bufBm1[63]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drdRow3bufB(63),
      I1 => \drdRow3bufBm1_reg[60]\(1),
      I2 => \drdRow3bufBm1_reg[60]\(2),
      I3 => \drdRow3bufBm1_reg[60]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3)
    );
\gr3[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr3_reg[10]_i_2_n_0\,
      I1 => \gr3_reg[4]\(3),
      I2 => \gr3[10]_i_3_n_0\,
      I3 => \gr3_reg[4]\(2),
      I4 => \gr3[10]_i_4_n_0\,
      I5 => \gr3_reg[4]_0\,
      O => D(6)
    );
\gr3[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(14),
      I1 => drdRow3bufB(2),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(54),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(42),
      O => \gr3[10]_i_3_n_0\
    );
\gr3[10]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(62),
      I1 => drdRow3bufB(50),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(38),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(26),
      O => \gr3[10]_i_4_n_0\
    );
\gr3[10]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(46),
      I1 => drdRow3bufB(34),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(22),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(10),
      O => \gr3[10]_i_5_n_0\
    );
\gr3[10]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(30),
      I1 => drdRow3bufB(18),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(6),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(58),
      O => \gr3[10]_i_6_n_0\
    );
\gr3[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr3_reg[11]_i_2_n_0\,
      I1 => \gr3_reg[4]\(3),
      I2 => \gr3[11]_i_3_n_0\,
      I3 => \gr3_reg[4]\(2),
      I4 => \gr3[11]_i_4_n_0\,
      I5 => \gr3_reg[4]_0\,
      O => D(7)
    );
\gr3[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(15),
      I1 => drdRow3bufB(3),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(55),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(43),
      O => \gr3[11]_i_3_n_0\
    );
\gr3[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(63),
      I1 => drdRow3bufB(51),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(39),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(27),
      O => \gr3[11]_i_4_n_0\
    );
\gr3[11]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(47),
      I1 => drdRow3bufB(35),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(23),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(11),
      O => \gr3[11]_i_5_n_0\
    );
\gr3[11]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(31),
      I1 => drdRow3bufB(19),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(7),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(59),
      O => \gr3[11]_i_6_n_0\
    );
\gr3[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr3_reg[4]_i_2_n_0\,
      I1 => \gr3_reg[4]\(3),
      I2 => \gr3[4]_i_3_n_0\,
      I3 => \gr3_reg[4]\(2),
      I4 => \gr3[4]_i_4_n_0\,
      I5 => \gr3_reg[4]_0\,
      O => D(0)
    );
\gr3[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(8),
      I1 => \gr3_reg[7]\(0),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(48),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(36),
      O => \gr3[4]_i_3_n_0\
    );
\gr3[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(56),
      I1 => drdRow3bufB(44),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(32),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(20),
      O => \gr3[4]_i_4_n_0\
    );
\gr3[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(40),
      I1 => drdRow3bufB(28),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(16),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(4),
      O => \gr3[4]_i_5_n_0\
    );
\gr3[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(24),
      I1 => drdRow3bufB(12),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(0),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(52),
      O => \gr3[4]_i_6_n_0\
    );
\gr3[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr3_reg[5]_i_2_n_0\,
      I1 => \gr3_reg[4]\(3),
      I2 => \gr3[5]_i_3_n_0\,
      I3 => \gr3_reg[4]\(2),
      I4 => \gr3[5]_i_4_n_0\,
      I5 => \gr3_reg[4]_0\,
      O => D(1)
    );
\gr3[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(9),
      I1 => \gr3_reg[7]\(1),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(49),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(37),
      O => \gr3[5]_i_3_n_0\
    );
\gr3[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(57),
      I1 => drdRow3bufB(45),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(33),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(21),
      O => \gr3[5]_i_4_n_0\
    );
\gr3[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(41),
      I1 => drdRow3bufB(29),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(17),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(5),
      O => \gr3[5]_i_5_n_0\
    );
\gr3[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(25),
      I1 => drdRow3bufB(13),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(1),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(53),
      O => \gr3[5]_i_6_n_0\
    );
\gr3[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr3_reg[6]_i_2_n_0\,
      I1 => \gr3_reg[4]\(3),
      I2 => \gr3[6]_i_3_n_0\,
      I3 => \gr3_reg[4]\(2),
      I4 => \gr3[6]_i_4_n_0\,
      I5 => \gr3_reg[4]_0\,
      O => D(2)
    );
\gr3[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(10),
      I1 => \gr3_reg[7]\(2),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(50),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(38),
      O => \gr3[6]_i_3_n_0\
    );
\gr3[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(58),
      I1 => drdRow3bufB(46),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(34),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(22),
      O => \gr3[6]_i_4_n_0\
    );
\gr3[6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(42),
      I1 => drdRow3bufB(30),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(18),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(6),
      O => \gr3[6]_i_5_n_0\
    );
\gr3[6]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(26),
      I1 => drdRow3bufB(14),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(2),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(54),
      O => \gr3[6]_i_6_n_0\
    );
\gr3[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr3_reg[7]_i_2_n_0\,
      I1 => \gr3_reg[4]\(3),
      I2 => \gr3[7]_i_3_n_0\,
      I3 => \gr3_reg[4]\(2),
      I4 => \gr3[7]_i_4_n_0\,
      I5 => \gr3_reg[4]_0\,
      O => D(3)
    );
\gr3[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(11),
      I1 => \gr3_reg[7]\(3),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(51),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(39),
      O => \gr3[7]_i_3_n_0\
    );
\gr3[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(59),
      I1 => drdRow3bufB(47),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(35),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(23),
      O => \gr3[7]_i_4_n_0\
    );
\gr3[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(43),
      I1 => drdRow3bufB(31),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(19),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(7),
      O => \gr3[7]_i_5_n_0\
    );
\gr3[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(27),
      I1 => drdRow3bufB(15),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(3),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(55),
      O => \gr3[7]_i_6_n_0\
    );
\gr3[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr3_reg[8]_i_2_n_0\,
      I1 => \gr3_reg[4]\(3),
      I2 => \gr3[8]_i_3_n_0\,
      I3 => \gr3_reg[4]\(2),
      I4 => \gr3[8]_i_4_n_0\,
      I5 => \gr3_reg[4]_0\,
      O => D(4)
    );
\gr3[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(12),
      I1 => drdRow3bufB(0),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(52),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(40),
      O => \gr3[8]_i_3_n_0\
    );
\gr3[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(60),
      I1 => drdRow3bufB(48),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(36),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(24),
      O => \gr3[8]_i_4_n_0\
    );
\gr3[8]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(44),
      I1 => drdRow3bufB(32),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(20),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(8),
      O => \gr3[8]_i_5_n_0\
    );
\gr3[8]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(28),
      I1 => drdRow3bufB(16),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(4),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(56),
      O => \gr3[8]_i_6_n_0\
    );
\gr3[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \gr3_reg[9]_i_2_n_0\,
      I1 => \gr3_reg[4]\(3),
      I2 => \gr3[9]_i_3_n_0\,
      I3 => \gr3_reg[4]\(2),
      I4 => \gr3[9]_i_4_n_0\,
      I5 => \gr3_reg[4]_0\,
      O => D(5)
    );
\gr3[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(13),
      I1 => drdRow3bufB(1),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(53),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(41),
      O => \gr3[9]_i_3_n_0\
    );
\gr3[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(61),
      I1 => drdRow3bufB(49),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(37),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(25),
      O => \gr3[9]_i_4_n_0\
    );
\gr3[9]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(45),
      I1 => drdRow3bufB(33),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(21),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(9),
      O => \gr3[9]_i_5_n_0\
    );
\gr3[9]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdRow3bufB(29),
      I1 => drdRow3bufB(17),
      I2 => \gr3_reg[4]\(1),
      I3 => drdRow3bufB(5),
      I4 => \gr3_reg[4]\(0),
      I5 => drdRow3bufB(57),
      O => \gr3[9]_i_6_n_0\
    );
\gr3_reg[10]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr3[10]_i_5_n_0\,
      I1 => \gr3[10]_i_6_n_0\,
      O => \gr3_reg[10]_i_2_n_0\,
      S => \gr3_reg[4]\(2)
    );
\gr3_reg[11]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr3[11]_i_5_n_0\,
      I1 => \gr3[11]_i_6_n_0\,
      O => \gr3_reg[11]_i_2_n_0\,
      S => \gr3_reg[4]\(2)
    );
\gr3_reg[4]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr3[4]_i_5_n_0\,
      I1 => \gr3[4]_i_6_n_0\,
      O => \gr3_reg[4]_i_2_n_0\,
      S => \gr3_reg[4]\(2)
    );
\gr3_reg[5]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr3[5]_i_5_n_0\,
      I1 => \gr3[5]_i_6_n_0\,
      O => \gr3_reg[5]_i_2_n_0\,
      S => \gr3_reg[4]\(2)
    );
\gr3_reg[6]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr3[6]_i_5_n_0\,
      I1 => \gr3[6]_i_6_n_0\,
      O => \gr3_reg[6]_i_2_n_0\,
      S => \gr3_reg[4]\(2)
    );
\gr3_reg[7]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr3[7]_i_5_n_0\,
      I1 => \gr3[7]_i_6_n_0\,
      O => \gr3_reg[7]_i_2_n_0\,
      S => \gr3_reg[4]\(2)
    );
\gr3_reg[8]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr3[8]_i_5_n_0\,
      I1 => \gr3[8]_i_6_n_0\,
      O => \gr3_reg[8]_i_2_n_0\,
      S => \gr3_reg[4]\(2)
    );
\gr3_reg[9]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr3[9]_i_5_n_0\,
      I1 => \gr3[9]_i_6_n_0\,
      O => \gr3_reg[9]_i_2_n_0\,
      S => \gr3_reg[4]\(2)
    );
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size4kB_a64b64__6\
     port map (
      addra(8 downto 0) => Q(8 downto 0),
      addrb(8 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(8 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(63 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => drdRow3bufB(63 downto 0),
      ena => \myMnfcore_i_1__12_n_0\,
      enb => enb,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(1),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\,
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(2),
      O => \myMnfcore_i_1__12_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64 is
  port (
    \qrs_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \qrs_reg[1]\ : out STD_LOGIC;
    \qrs_reg[1]_0\ : out STD_LOGIC;
    \qrs_reg[1]_1\ : out STD_LOGIC;
    \qrs_reg[2]_0\ : out STD_LOGIC;
    \qrs_reg[2]_1\ : out STD_LOGIC;
    \qrs_reg[2]_2\ : out STD_LOGIC;
    p_1_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \qrs_reg[1]_2\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \qrs_reg[1]_3\ : out STD_LOGIC;
    \qrs_reg[1]_4\ : out STD_LOGIC;
    \qrs_reg[1]_5\ : out STD_LOGIC;
    \qrs_reg[1]_6\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \FSM_sequential_stateRgbegr_reg[1]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    enEobufB : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \rgbToManyAXIS_tdata_sig_reg[7]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    p_0_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
    p_3_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gr_reg[11]_i_3_0\ : in STD_LOGIC;
    \gr_reg[11]_i_3_1\ : in STD_LOGIC;
    \gr_reg[5]_i_2_0\ : in STD_LOGIC;
    \gr_reg[5]_i_2_1\ : in STD_LOGIC;
    \gr_reg[11]_i_3_2\ : in STD_LOGIC;
    \gr_reg[5]_i_2_2\ : in STD_LOGIC;
    \gr_reg[5]_i_2_3\ : in STD_LOGIC;
    \gr_reg[5]_i_2_4\ : in STD_LOGIC;
    \gr_reg[5]_i_2_5\ : in STD_LOGIC;
    \gr_reg[11]_i_3_3\ : in STD_LOGIC;
    \drdOddbufBm1_reg[63]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    oddNotEven : in STD_LOGIC;
    enEobuf : in STD_LOGIC;
    \rgbToManyAXIS_tdata_sig_reg[7]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64 : entity is "Dpbram_size6kB_a64b64";
end design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64 is
  signal drdOddbufB : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal gr0 : STD_LOGIC_VECTOR ( 13 downto 2 );
  signal \gr[11]_i_10_n_0\ : STD_LOGIC;
  signal \gr[11]_i_11_n_0\ : STD_LOGIC;
  signal \gr[11]_i_12_n_0\ : STD_LOGIC;
  signal \gr[11]_i_13_n_0\ : STD_LOGIC;
  signal \gr[11]_i_15_n_0\ : STD_LOGIC;
  signal \gr[11]_i_17_n_0\ : STD_LOGIC;
  signal \gr[11]_i_19_n_0\ : STD_LOGIC;
  signal \gr[11]_i_20_n_0\ : STD_LOGIC;
  signal \gr[11]_i_21_n_0\ : STD_LOGIC;
  signal \gr[11]_i_22_n_0\ : STD_LOGIC;
  signal \gr[11]_i_23_n_0\ : STD_LOGIC;
  signal \gr[11]_i_24_n_0\ : STD_LOGIC;
  signal \gr[11]_i_25_n_0\ : STD_LOGIC;
  signal \gr[11]_i_26_n_0\ : STD_LOGIC;
  signal \gr[11]_i_27_n_0\ : STD_LOGIC;
  signal \gr[11]_i_28_n_0\ : STD_LOGIC;
  signal \gr[11]_i_29_n_0\ : STD_LOGIC;
  signal \gr[11]_i_30_n_0\ : STD_LOGIC;
  signal \gr[11]_i_31_n_0\ : STD_LOGIC;
  signal \gr[11]_i_4_n_0\ : STD_LOGIC;
  signal \gr[11]_i_5_n_0\ : STD_LOGIC;
  signal \gr[11]_i_6_n_0\ : STD_LOGIC;
  signal \gr[11]_i_7_n_0\ : STD_LOGIC;
  signal \gr[11]_i_8_n_0\ : STD_LOGIC;
  signal \gr[11]_i_9_n_0\ : STD_LOGIC;
  signal \gr[5]_i_10_n_0\ : STD_LOGIC;
  signal \gr[5]_i_11_n_0\ : STD_LOGIC;
  signal \gr[5]_i_12_n_0\ : STD_LOGIC;
  signal \gr[5]_i_13_n_0\ : STD_LOGIC;
  signal \gr[5]_i_14_n_0\ : STD_LOGIC;
  signal \gr[5]_i_16_n_0\ : STD_LOGIC;
  signal \gr[5]_i_17_n_0\ : STD_LOGIC;
  signal \gr[5]_i_18_n_0\ : STD_LOGIC;
  signal \gr[5]_i_19_n_0\ : STD_LOGIC;
  signal \gr[5]_i_21_n_0\ : STD_LOGIC;
  signal \gr[5]_i_22_n_0\ : STD_LOGIC;
  signal \gr[5]_i_24_n_0\ : STD_LOGIC;
  signal \gr[5]_i_27_n_0\ : STD_LOGIC;
  signal \gr[5]_i_28_n_0\ : STD_LOGIC;
  signal \gr[5]_i_29_n_0\ : STD_LOGIC;
  signal \gr[5]_i_30_n_0\ : STD_LOGIC;
  signal \gr[5]_i_31_n_0\ : STD_LOGIC;
  signal \gr[5]_i_32_n_0\ : STD_LOGIC;
  signal \gr[5]_i_33_n_0\ : STD_LOGIC;
  signal \gr[5]_i_34_n_0\ : STD_LOGIC;
  signal \gr[5]_i_35_n_0\ : STD_LOGIC;
  signal \gr[5]_i_3_n_0\ : STD_LOGIC;
  signal \gr[5]_i_4_n_0\ : STD_LOGIC;
  signal \gr[5]_i_5_n_0\ : STD_LOGIC;
  signal \gr[5]_i_6_n_0\ : STD_LOGIC;
  signal \gr[5]_i_7_n_0\ : STD_LOGIC;
  signal \gr[5]_i_8_n_0\ : STD_LOGIC;
  signal \gr[5]_i_9_n_0\ : STD_LOGIC;
  signal \gr_reg[11]_i_3_n_4\ : STD_LOGIC;
  signal \gr_reg[11]_i_3_n_5\ : STD_LOGIC;
  signal \gr_reg[11]_i_3_n_6\ : STD_LOGIC;
  signal \gr_reg[11]_i_3_n_7\ : STD_LOGIC;
  signal \gr_reg[5]_i_2_n_0\ : STD_LOGIC;
  signal \gr_reg[5]_i_2_n_1\ : STD_LOGIC;
  signal \gr_reg[5]_i_2_n_2\ : STD_LOGIC;
  signal \gr_reg[5]_i_2_n_3\ : STD_LOGIC;
  signal \gr_reg[5]_i_2_n_4\ : STD_LOGIC;
  signal \gr_reg[5]_i_2_n_5\ : STD_LOGIC;
  signal \gr_reg[5]_i_2_n_6\ : STD_LOGIC;
  signal \gr_reg[5]_i_2_n_7\ : STD_LOGIC;
  signal \myMnfcore_i_1__10_n_0\ : STD_LOGIC;
  signal \^p_1_in\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal p_2_in : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^qrs_reg[1]\ : STD_LOGIC;
  signal \^qrs_reg[1]_0\ : STD_LOGIC;
  signal \^qrs_reg[1]_1\ : STD_LOGIC;
  signal \^qrs_reg[1]_2\ : STD_LOGIC;
  signal \^qrs_reg[1]_3\ : STD_LOGIC;
  signal \^qrs_reg[1]_4\ : STD_LOGIC;
  signal \^qrs_reg[1]_5\ : STD_LOGIC;
  signal \^qrs_reg[1]_6\ : STD_LOGIC;
  signal \^qrs_reg[2]_0\ : STD_LOGIC;
  signal \^qrs_reg[2]_1\ : STD_LOGIC;
  signal \^qrs_reg[2]_2\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[0]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[0]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[10]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[10]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[11]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[11]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_39_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_40_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_41_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_42_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_43_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_44_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_45_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_46_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_47_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_48_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_49_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[1]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[1]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_28_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_29_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_30_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[2]_i_2_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[2]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[2]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[3]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[3]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[4]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[4]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[5]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[5]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[6]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[6]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[7]_i_2_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[7]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[8]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[8]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[9]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[9]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[10]_i_2_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[5]_i_2_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[6]_i_2_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[9]_i_2_n_0\ : STD_LOGIC;
  signal \NLW_gr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gr_reg[11]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_gr_reg[5]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \drdOddbufBm1[48]_i_1\ : label is "soft_lutpair2936";
  attribute SOFT_HLUTNM of \drdOddbufBm1[49]_i_1\ : label is "soft_lutpair2936";
  attribute SOFT_HLUTNM of \drdOddbufBm1[50]_i_1\ : label is "soft_lutpair2935";
  attribute SOFT_HLUTNM of \drdOddbufBm1[51]_i_1\ : label is "soft_lutpair2935";
  attribute SOFT_HLUTNM of \drdOddbufBm1[52]_i_1\ : label is "soft_lutpair2934";
  attribute SOFT_HLUTNM of \drdOddbufBm1[53]_i_1\ : label is "soft_lutpair2934";
  attribute SOFT_HLUTNM of \drdOddbufBm1[54]_i_1\ : label is "soft_lutpair2933";
  attribute SOFT_HLUTNM of \drdOddbufBm1[55]_i_1\ : label is "soft_lutpair2933";
  attribute SOFT_HLUTNM of \drdOddbufBm1[56]_i_1\ : label is "soft_lutpair2932";
  attribute SOFT_HLUTNM of \drdOddbufBm1[57]_i_1\ : label is "soft_lutpair2932";
  attribute SOFT_HLUTNM of \drdOddbufBm1[58]_i_1\ : label is "soft_lutpair2931";
  attribute SOFT_HLUTNM of \drdOddbufBm1[59]_i_1\ : label is "soft_lutpair2931";
  attribute SOFT_HLUTNM of \drdOddbufBm1[60]_i_1\ : label is "soft_lutpair2930";
  attribute SOFT_HLUTNM of \drdOddbufBm1[61]_i_1\ : label is "soft_lutpair2930";
  attribute SOFT_HLUTNM of \drdOddbufBm1[62]_i_1\ : label is "soft_lutpair2929";
  attribute SOFT_HLUTNM of \drdOddbufBm1[63]_i_1\ : label is "soft_lutpair2929";
  attribute SOFT_HLUTNM of \gr[0]_i_1\ : label is "soft_lutpair2942";
  attribute SOFT_HLUTNM of \gr[10]_i_1\ : label is "soft_lutpair2937";
  attribute SOFT_HLUTNM of \gr[11]_i_15\ : label is "soft_lutpair2920";
  attribute SOFT_HLUTNM of \gr[11]_i_17\ : label is "soft_lutpair2920";
  attribute SOFT_HLUTNM of \gr[11]_i_19\ : label is "soft_lutpair2915";
  attribute SOFT_HLUTNM of \gr[11]_i_2\ : label is "soft_lutpair2937";
  attribute SOFT_HLUTNM of \gr[11]_i_20\ : label is "soft_lutpair2913";
  attribute SOFT_HLUTNM of \gr[11]_i_21\ : label is "soft_lutpair2921";
  attribute SOFT_HLUTNM of \gr[11]_i_22\ : label is "soft_lutpair2913";
  attribute SOFT_HLUTNM of \gr[11]_i_24\ : label is "soft_lutpair2928";
  attribute SOFT_HLUTNM of \gr[11]_i_25\ : label is "soft_lutpair2928";
  attribute SOFT_HLUTNM of \gr[11]_i_27\ : label is "soft_lutpair2926";
  attribute SOFT_HLUTNM of \gr[11]_i_28\ : label is "soft_lutpair2926";
  attribute SOFT_HLUTNM of \gr[11]_i_30\ : label is "soft_lutpair2925";
  attribute SOFT_HLUTNM of \gr[11]_i_31\ : label is "soft_lutpair2925";
  attribute SOFT_HLUTNM of \gr[1]_i_1\ : label is "soft_lutpair2942";
  attribute SOFT_HLUTNM of \gr[2]_i_1\ : label is "soft_lutpair2941";
  attribute SOFT_HLUTNM of \gr[3]_i_1\ : label is "soft_lutpair2941";
  attribute SOFT_HLUTNM of \gr[4]_i_1\ : label is "soft_lutpair2940";
  attribute SOFT_HLUTNM of \gr[5]_i_1\ : label is "soft_lutpair2940";
  attribute SOFT_HLUTNM of \gr[5]_i_18\ : label is "soft_lutpair2917";
  attribute SOFT_HLUTNM of \gr[5]_i_19\ : label is "soft_lutpair2921";
  attribute SOFT_HLUTNM of \gr[5]_i_21\ : label is "soft_lutpair2917";
  attribute SOFT_HLUTNM of \gr[5]_i_22\ : label is "soft_lutpair2923";
  attribute SOFT_HLUTNM of \gr[5]_i_24\ : label is "soft_lutpair2923";
  attribute SOFT_HLUTNM of \gr[5]_i_25\ : label is "soft_lutpair2916";
  attribute SOFT_HLUTNM of \gr[5]_i_26\ : label is "soft_lutpair2919";
  attribute SOFT_HLUTNM of \gr[5]_i_30\ : label is "soft_lutpair2914";
  attribute SOFT_HLUTNM of \gr[5]_i_31\ : label is "soft_lutpair2914";
  attribute SOFT_HLUTNM of \gr[6]_i_1\ : label is "soft_lutpair2939";
  attribute SOFT_HLUTNM of \gr[7]_i_1\ : label is "soft_lutpair2939";
  attribute SOFT_HLUTNM of \gr[8]_i_1\ : label is "soft_lutpair2938";
  attribute SOFT_HLUTNM of \gr[9]_i_1\ : label is "soft_lutpair2938";
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size6kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[10]_i_1\ : label is "soft_lutpair2943";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[11]_i_1\ : label is "soft_lutpair2943";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[18]_i_40\ : label is "soft_lutpair2924";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[18]_i_41\ : label is "soft_lutpair2924";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[18]_i_43\ : label is "soft_lutpair2922";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[18]_i_44\ : label is "soft_lutpair2922";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[18]_i_46\ : label is "soft_lutpair2918";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[18]_i_47\ : label is "soft_lutpair2918";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[1]_i_1\ : label is "soft_lutpair2946";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[1]_i_2\ : label is "soft_lutpair2916";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[23]_i_29\ : label is "soft_lutpair2927";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[23]_i_30\ : label is "soft_lutpair2927";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[2]_i_1\ : label is "soft_lutpair2919";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[3]_i_1\ : label is "soft_lutpair2946";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[4]_i_1\ : label is "soft_lutpair2945";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[5]_i_1\ : label is "soft_lutpair2945";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[6]_i_1\ : label is "soft_lutpair2944";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[8]_i_1\ : label is "soft_lutpair2944";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[9]_i_1\ : label is "soft_lutpair2915";
begin
  p_1_in(1 downto 0) <= \^p_1_in\(1 downto 0);
  \qrs_reg[1]\ <= \^qrs_reg[1]\;
  \qrs_reg[1]_0\ <= \^qrs_reg[1]_0\;
  \qrs_reg[1]_1\ <= \^qrs_reg[1]_1\;
  \qrs_reg[1]_2\ <= \^qrs_reg[1]_2\;
  \qrs_reg[1]_3\ <= \^qrs_reg[1]_3\;
  \qrs_reg[1]_4\ <= \^qrs_reg[1]_4\;
  \qrs_reg[1]_5\ <= \^qrs_reg[1]_5\;
  \qrs_reg[1]_6\ <= \^qrs_reg[1]_6\;
  \qrs_reg[2]_0\ <= \^qrs_reg[2]_0\;
  \qrs_reg[2]_1\ <= \^qrs_reg[2]_1\;
  \qrs_reg[2]_2\ <= \^qrs_reg[2]_2\;
\drdOddbufBm1[48]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(48),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0)
    );
\drdOddbufBm1[49]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(49),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1)
    );
\drdOddbufBm1[50]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(50),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2)
    );
\drdOddbufBm1[51]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(51),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3)
    );
\drdOddbufBm1[52]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(52),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4)
    );
\drdOddbufBm1[53]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(53),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5)
    );
\drdOddbufBm1[54]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(54),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6)
    );
\drdOddbufBm1[55]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(55),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7)
    );
\drdOddbufBm1[56]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(56),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(8)
    );
\drdOddbufBm1[57]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(57),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(9)
    );
\drdOddbufBm1[58]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(58),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(10)
    );
\drdOddbufBm1[59]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(59),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(11)
    );
\drdOddbufBm1[60]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(60),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(12)
    );
\drdOddbufBm1[61]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(61),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(13)
    );
\drdOddbufBm1[62]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(62),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(14)
    );
\drdOddbufBm1[63]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => drdOddbufB(63),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(15)
    );
\gr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => gr0(2),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \FSM_sequential_stateRgbegr_reg[1]\(0)
    );
\gr[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => gr0(12),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \FSM_sequential_stateRgbegr_reg[1]\(10)
    );
\gr[11]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => p_0_in(11),
      I1 => \rgbToManyAXIS_tdata_sig_reg[11]_i_2_n_0\,
      I2 => \^qrs_reg[1]_2\,
      I3 => \gr[11]_i_5_n_0\,
      I4 => \gr[11]_i_15_n_0\,
      I5 => \gr_reg[11]_i_3_3\,
      O => \gr[11]_i_10_n_0\
    );
\gr[11]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D42B2BD42BD4D42B"
    )
        port map (
      I0 => p_0_in(9),
      I1 => \^qrs_reg[1]_1\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[9]_i_2_n_0\,
      I3 => \gr[11]_i_6_n_0\,
      I4 => \gr_reg[11]_i_3_2\,
      I5 => \gr[11]_i_17_n_0\,
      O => \gr[11]_i_11_n_0\
    );
\gr[11]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B24D4DB24DB2B24D"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[8]_i_2_n_0\,
      I1 => \^qrs_reg[1]\,
      I2 => p_0_in(8),
      I3 => \gr[11]_i_7_n_0\,
      I4 => \gr_reg[11]_i_3_1\,
      I5 => \gr[11]_i_19_n_0\,
      O => \gr[11]_i_12_n_0\
    );
\gr[11]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \^qrs_reg[1]\,
      I1 => p_0_in(8),
      I2 => \rgbToManyAXIS_tdata_sig_reg[8]_i_2_n_0\,
      I3 => \gr[11]_i_8_n_0\,
      I4 => \gr[11]_i_20_n_0\,
      I5 => \gr_reg[11]_i_3_0\,
      O => \gr[11]_i_13_n_0\
    );
\gr[11]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5530553F"
    )
        port map (
      I0 => \gr[11]_i_23_n_0\,
      I1 => \gr[11]_i_24_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I4 => \gr[11]_i_25_n_0\,
      O => \^qrs_reg[1]_2\
    );
\gr[11]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B2"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[10]_i_2_n_0\,
      I1 => \^qrs_reg[1]_5\,
      I2 => p_0_in(10),
      O => \gr[11]_i_15_n_0\
    );
\gr[11]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5530553F"
    )
        port map (
      I0 => \gr[11]_i_26_n_0\,
      I1 => \gr[11]_i_27_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I4 => \gr[11]_i_28_n_0\,
      O => \^qrs_reg[1]_1\
    );
\gr[11]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \^qrs_reg[1]_5\,
      I1 => p_0_in(10),
      I2 => \rgbToManyAXIS_tdata_sig_reg[10]_i_2_n_0\,
      O => \gr[11]_i_17_n_0\
    );
\gr[11]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5530553F"
    )
        port map (
      I0 => \gr[11]_i_29_n_0\,
      I1 => \gr[11]_i_30_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I4 => \gr[11]_i_31_n_0\,
      O => \^qrs_reg[1]\
    );
\gr[11]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \^qrs_reg[1]_1\,
      I1 => p_0_in(9),
      I2 => \rgbToManyAXIS_tdata_sig_reg[9]_i_2_n_0\,
      O => \gr[11]_i_19_n_0\
    );
\gr[11]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => gr0(13),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \FSM_sequential_stateRgbegr_reg[1]\(11)
    );
\gr[11]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B800FFB8"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[7]_i_2_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I2 => \rgbToManyAXIS_tdata_sig[7]_i_3_n_0\,
      I3 => p_0_in(7),
      I4 => \^qrs_reg[1]_3\,
      O => \gr[11]_i_20_n_0\
    );
\gr[11]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B2"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[6]_i_2_n_0\,
      I1 => \^qrs_reg[1]_6\,
      I2 => p_0_in(6),
      O => \gr[11]_i_21_n_0\
    );
\gr[11]_i_22\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"47B8B847"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[7]_i_2_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I2 => \rgbToManyAXIS_tdata_sig[7]_i_3_n_0\,
      I3 => \^qrs_reg[1]_3\,
      I4 => p_0_in(7),
      O => \gr[11]_i_22_n_0\
    );
\gr[11]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(63),
      I1 => drdOddbufB(39),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(15),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(55),
      O => \gr[11]_i_23_n_0\
    );
\gr[11]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(31),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(7),
      O => \gr[11]_i_24_n_0\
    );
\gr[11]_i_25\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(47),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(23),
      O => \gr[11]_i_25_n_0\
    );
\gr[11]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(61),
      I1 => drdOddbufB(37),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(13),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(53),
      O => \gr[11]_i_26_n_0\
    );
\gr[11]_i_27\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(29),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(5),
      O => \gr[11]_i_27_n_0\
    );
\gr[11]_i_28\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(45),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(21),
      O => \gr[11]_i_28_n_0\
    );
\gr[11]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(60),
      I1 => drdOddbufB(36),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(12),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(52),
      O => \gr[11]_i_29_n_0\
    );
\gr[11]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(28),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(4),
      O => \gr[11]_i_30_n_0\
    );
\gr[11]_i_31\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(44),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(20),
      O => \gr[11]_i_31_n_0\
    );
\gr[11]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69FF0069"
    )
        port map (
      I0 => p_0_in(11),
      I1 => \rgbToManyAXIS_tdata_sig_reg[11]_i_2_n_0\,
      I2 => \^qrs_reg[1]_2\,
      I3 => \gr_reg[11]_i_3_3\,
      I4 => \gr[11]_i_15_n_0\,
      O => \gr[11]_i_4_n_0\
    );
\gr[11]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"002B2BFF"
    )
        port map (
      I0 => p_0_in(9),
      I1 => \^qrs_reg[1]_1\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[9]_i_2_n_0\,
      I3 => \gr_reg[11]_i_3_2\,
      I4 => \gr[11]_i_17_n_0\,
      O => \gr[11]_i_5_n_0\
    );
\gr[11]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B200FFB2"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[8]_i_2_n_0\,
      I1 => \^qrs_reg[1]\,
      I2 => p_0_in(8),
      I3 => \gr[11]_i_19_n_0\,
      I4 => \gr_reg[11]_i_3_1\,
      O => \gr[11]_i_6_n_0\
    );
\gr[11]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6900FF69"
    )
        port map (
      I0 => \^qrs_reg[1]\,
      I1 => p_0_in(8),
      I2 => \rgbToManyAXIS_tdata_sig_reg[8]_i_2_n_0\,
      I3 => \gr[11]_i_20_n_0\,
      I4 => \gr_reg[11]_i_3_0\,
      O => \gr[11]_i_7_n_0\
    );
\gr[11]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B2"
    )
        port map (
      I0 => \gr[11]_i_21_n_0\,
      I1 => \gr_reg[5]_i_2_4\,
      I2 => \gr[11]_i_22_n_0\,
      O => \gr[11]_i_8_n_0\
    );
\gr[11]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E7718EE7"
    )
        port map (
      I0 => p_0_in(11),
      I1 => \rgbToManyAXIS_tdata_sig_reg[11]_i_2_n_0\,
      I2 => \^qrs_reg[1]_2\,
      I3 => \gr_reg[11]_i_3_3\,
      I4 => \gr[11]_i_15_n_0\,
      O => \gr[11]_i_9_n_0\
    );
\gr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => gr0(3),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \FSM_sequential_stateRgbegr_reg[1]\(1)
    );
\gr[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => gr0(4),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \FSM_sequential_stateRgbegr_reg[1]\(2)
    );
\gr[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => gr0(5),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \FSM_sequential_stateRgbegr_reg[1]\(3)
    );
\gr[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => gr0(6),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \FSM_sequential_stateRgbegr_reg[1]\(4)
    );
\gr[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => gr0(7),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \FSM_sequential_stateRgbegr_reg[1]\(5)
    );
\gr[5]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2BD4D42BD42B2BD4"
    )
        port map (
      I0 => \gr[5]_i_18_n_0\,
      I1 => \gr_reg[5]_i_2_3\,
      I2 => \gr[5]_i_19_n_0\,
      I3 => \gr[11]_i_21_n_0\,
      I4 => \gr_reg[5]_i_2_4\,
      I5 => \gr[11]_i_22_n_0\,
      O => \gr[5]_i_10_n_0\
    );
\gr[5]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \gr[5]_i_4_n_0\,
      I1 => \gr[5]_i_18_n_0\,
      I2 => \gr_reg[5]_i_2_3\,
      I3 => \gr[5]_i_19_n_0\,
      O => \gr[5]_i_11_n_0\
    );
\gr[5]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4DB2B24DB24D4DB2"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[4]_i_2_n_0\,
      I1 => \^qrs_reg[1]_0\,
      I2 => p_0_in(4),
      I3 => \gr[5]_i_5_n_0\,
      I4 => \gr_reg[5]_i_2_0\,
      I5 => \gr[5]_i_21_n_0\,
      O => \gr[5]_i_12_n_0\
    );
\gr[5]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[4]_i_2_n_0\,
      I1 => \^qrs_reg[1]_0\,
      I2 => p_0_in(4),
      I3 => \gr[5]_i_6_n_0\,
      I4 => \gr[5]_i_22_n_0\,
      I5 => \gr_reg[5]_i_2_1\,
      O => \gr[5]_i_13_n_0\
    );
\gr[5]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"718E8E718E71718E"
    )
        port map (
      I0 => p_0_in(2),
      I1 => \^p_1_in\(0),
      I2 => \rgbToManyAXIS_tdata_sig[2]_i_2_n_0\,
      I3 => \gr[5]_i_7_n_0\,
      I4 => \gr_reg[5]_i_2_5\,
      I5 => \gr[5]_i_24_n_0\,
      O => \gr[5]_i_14_n_0\
    );
\gr[5]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FFCA35CA35FF00"
    )
        port map (
      I0 => \gr[5]_i_27_n_0\,
      I1 => \gr[5]_i_28_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I3 => \gr[5]_i_9_n_0\,
      I4 => p_0_in(0),
      I5 => p_2_in(0),
      O => \gr[5]_i_16_n_0\
    );
\gr[5]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CA3535CA35CACA35"
    )
        port map (
      I0 => \gr[5]_i_27_n_0\,
      I1 => \gr[5]_i_28_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I3 => p_0_in(0),
      I4 => p_2_in(0),
      I5 => p_3_in(0),
      O => \gr[5]_i_17_n_0\
    );
\gr[5]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B2"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[5]_i_2_n_0\,
      I1 => \^qrs_reg[1]_4\,
      I2 => p_0_in(5),
      O => \gr[5]_i_18_n_0\
    );
\gr[5]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[6]_i_2_n_0\,
      I1 => \^qrs_reg[1]_6\,
      I2 => p_0_in(6),
      O => \gr[5]_i_19_n_0\
    );
\gr[5]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5530553F"
    )
        port map (
      I0 => \gr[5]_i_29_n_0\,
      I1 => \gr[5]_i_30_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I4 => \gr[5]_i_31_n_0\,
      O => \^qrs_reg[1]_0\
    );
\gr[5]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[5]_i_2_n_0\,
      I1 => \^qrs_reg[1]_4\,
      I2 => p_0_in(5),
      O => \gr[5]_i_21_n_0\
    );
\gr[5]_i_22\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[3]_i_2_n_0\,
      I1 => p_0_in(3),
      I2 => \^p_1_in\(1),
      O => \gr[5]_i_22_n_0\
    );
\gr[5]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \^p_1_in\(1),
      I1 => p_0_in(3),
      I2 => \rgbToManyAXIS_tdata_sig_reg[3]_i_2_n_0\,
      O => \gr[5]_i_24_n_0\
    );
\gr[5]_i_25\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CA"
    )
        port map (
      I0 => \gr[5]_i_34_n_0\,
      I1 => \gr[5]_i_35_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      O => \^qrs_reg[2]_1\
    );
\gr[5]_i_26\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[2]_i_2_n_0\,
      I1 => \^p_1_in\(0),
      I2 => p_0_in(2),
      O => \^qrs_reg[2]_2\
    );
\gr[5]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => drdOddbufB(20),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(12),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(36),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(12),
      O => \gr[5]_i_27_n_0\
    );
\gr[5]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => drdOddbufB(52),
      I1 => drdOddbufB(28),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(4),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(44),
      O => \gr[5]_i_28_n_0\
    );
\gr[5]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(56),
      I1 => drdOddbufB(32),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(8),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(48),
      O => \gr[5]_i_29_n_0\
    );
\gr[5]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2B"
    )
        port map (
      I0 => \gr[5]_i_18_n_0\,
      I1 => \gr_reg[5]_i_2_3\,
      I2 => \gr[5]_i_19_n_0\,
      O => \gr[5]_i_3_n_0\
    );
\gr[5]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(24),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(0),
      O => \gr[5]_i_30_n_0\
    );
\gr[5]_i_31\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(40),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(16),
      O => \gr[5]_i_31_n_0\
    );
\gr[5]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(22),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(14),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(38),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(14),
      O => \gr[5]_i_32_n_0\
    );
\gr[5]_i_33\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(54),
      I1 => drdOddbufB(30),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(6),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(46),
      O => \gr[5]_i_33_n_0\
    );
\gr[5]_i_34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => drdOddbufB(21),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(13),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(37),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(13),
      O => \gr[5]_i_34_n_0\
    );
\gr[5]_i_35\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => drdOddbufB(53),
      I1 => drdOddbufB(29),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(5),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(45),
      O => \gr[5]_i_35_n_0\
    );
\gr[5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00B2B2FF"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[4]_i_2_n_0\,
      I1 => \^qrs_reg[1]_0\,
      I2 => p_0_in(4),
      I3 => \gr_reg[5]_i_2_0\,
      I4 => \gr[5]_i_21_n_0\,
      O => \gr[5]_i_4_n_0\
    );
\gr[5]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69FF0069"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[4]_i_2_n_0\,
      I1 => \^qrs_reg[1]_0\,
      I2 => p_0_in(4),
      I3 => \gr_reg[5]_i_2_1\,
      I4 => \gr[5]_i_22_n_0\,
      O => \gr[5]_i_5_n_0\
    );
\gr[5]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF8E8E00"
    )
        port map (
      I0 => p_0_in(2),
      I1 => \^p_1_in\(0),
      I2 => \rgbToManyAXIS_tdata_sig[2]_i_2_n_0\,
      I3 => \gr_reg[5]_i_2_5\,
      I4 => \gr[5]_i_24_n_0\,
      O => \gr[5]_i_6_n_0\
    );
\gr[5]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"002B2BFF"
    )
        port map (
      I0 => p_0_in(1),
      I1 => \^qrs_reg[2]_1\,
      I2 => \^qrs_reg[2]_0\,
      I3 => \gr_reg[5]_i_2_2\,
      I4 => \^qrs_reg[2]_2\,
      O => \gr[5]_i_7_n_0\
    );
\gr[5]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2BD4D42B"
    )
        port map (
      I0 => p_0_in(1),
      I1 => \^qrs_reg[2]_1\,
      I2 => \^qrs_reg[2]_0\,
      I3 => \^qrs_reg[2]_2\,
      I4 => \gr_reg[5]_i_2_2\,
      O => \gr[5]_i_8_n_0\
    );
\gr[5]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \^qrs_reg[2]_0\,
      I1 => \^qrs_reg[2]_1\,
      I2 => p_0_in(1),
      I3 => p_3_in(1),
      O => \gr[5]_i_9_n_0\
    );
\gr[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => gr0(8),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \FSM_sequential_stateRgbegr_reg[1]\(6)
    );
\gr[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => gr0(9),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \FSM_sequential_stateRgbegr_reg[1]\(7)
    );
\gr[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => gr0(10),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \FSM_sequential_stateRgbegr_reg[1]\(8)
    );
\gr[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => gr0(11),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => \FSM_sequential_stateRgbegr_reg[1]\(9)
    );
\gr_reg[11]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \gr_reg[5]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_gr_reg[11]_i_3_CO_UNCONNECTED\(7 downto 6),
      CO(5) => gr0(13),
      CO(4) => \NLW_gr_reg[11]_i_3_CO_UNCONNECTED\(4),
      CO(3) => \gr_reg[11]_i_3_n_4\,
      CO(2) => \gr_reg[11]_i_3_n_5\,
      CO(1) => \gr_reg[11]_i_3_n_6\,
      CO(0) => \gr_reg[11]_i_3_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \gr[11]_i_4_n_0\,
      DI(3) => \gr[11]_i_5_n_0\,
      DI(2) => \gr[11]_i_6_n_0\,
      DI(1) => \gr[11]_i_7_n_0\,
      DI(0) => \gr[11]_i_8_n_0\,
      O(7 downto 5) => \NLW_gr_reg[11]_i_3_O_UNCONNECTED\(7 downto 5),
      O(4 downto 0) => gr0(12 downto 8),
      S(7 downto 5) => B"001",
      S(4) => \gr[11]_i_9_n_0\,
      S(3) => \gr[11]_i_10_n_0\,
      S(2) => \gr[11]_i_11_n_0\,
      S(1) => \gr[11]_i_12_n_0\,
      S(0) => \gr[11]_i_13_n_0\
    );
\gr_reg[5]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \gr_reg[5]_i_2_n_0\,
      CO(6) => \gr_reg[5]_i_2_n_1\,
      CO(5) => \gr_reg[5]_i_2_n_2\,
      CO(4) => \gr_reg[5]_i_2_n_3\,
      CO(3) => \gr_reg[5]_i_2_n_4\,
      CO(2) => \gr_reg[5]_i_2_n_5\,
      CO(1) => \gr_reg[5]_i_2_n_6\,
      CO(0) => \gr_reg[5]_i_2_n_7\,
      DI(7) => \gr[5]_i_3_n_0\,
      DI(6) => \gr[5]_i_4_n_0\,
      DI(5) => \gr[5]_i_5_n_0\,
      DI(4) => \gr[5]_i_6_n_0\,
      DI(3) => \gr[5]_i_7_n_0\,
      DI(2) => \gr[5]_i_8_n_0\,
      DI(1) => \gr[5]_i_9_n_0\,
      DI(0) => p_3_in(0),
      O(7 downto 2) => gr0(7 downto 2),
      O(1 downto 0) => \NLW_gr_reg[5]_i_2_O_UNCONNECTED\(1 downto 0),
      S(7) => \gr[5]_i_10_n_0\,
      S(6) => \gr[5]_i_11_n_0\,
      S(5) => \gr[5]_i_12_n_0\,
      S(4) => \gr[5]_i_13_n_0\,
      S(3) => \gr[5]_i_14_n_0\,
      S(2) => S(0),
      S(1) => \gr[5]_i_16_n_0\,
      S(0) => \gr[5]_i_17_n_0\
    );
\gr_reg[5]_i_23\: unisim.vcomponents.MUXF7
     port map (
      I0 => \gr[5]_i_32_n_0\,
      I1 => \gr[5]_i_33_n_0\,
      O => \^p_1_in\(0),
      S => \rgbToManyAXIS_tdata_sig_reg[7]\(2)
    );
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__3\
     port map (
      addra(9 downto 0) => Q(9 downto 0),
      addrb(9 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(9 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(63 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => drdOddbufB(63 downto 0),
      ena => \myMnfcore_i_1__10_n_0\,
      enb => enEobufB,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => oddNotEven,
      I1 => enEobuf,
      O => \myMnfcore_i_1__10_n_0\
    );
\rgbToManyAXIS_tdata_sig[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => p_2_in(0),
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => D(0)
    );
\rgbToManyAXIS_tdata_sig[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(8),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(0),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(24),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(0),
      O => \rgbToManyAXIS_tdata_sig[0]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(40),
      I1 => drdOddbufB(16),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(8),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(32),
      O => \rgbToManyAXIS_tdata_sig[0]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[10]_i_2_n_0\,
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => D(10)
    );
\rgbToManyAXIS_tdata_sig[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(18),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(10),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(34),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(10),
      O => \rgbToManyAXIS_tdata_sig[10]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[10]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(50),
      I1 => drdOddbufB(26),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(2),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(42),
      O => \rgbToManyAXIS_tdata_sig[10]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[11]_i_2_n_0\,
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => D(11)
    );
\rgbToManyAXIS_tdata_sig[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(19),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(11),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(35),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(11),
      O => \rgbToManyAXIS_tdata_sig[11]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(51),
      I1 => drdOddbufB(27),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(3),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(43),
      O => \rgbToManyAXIS_tdata_sig[11]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CA35"
    )
        port map (
      I0 => \gr[5]_i_27_n_0\,
      I1 => \gr[5]_i_28_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I3 => p_0_in(0),
      O => \qrs_reg[2]\(0)
    );
\rgbToManyAXIS_tdata_sig[18]_i_35\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5530553F"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[18]_i_39_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[18]_i_40_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_41_n_0\,
      O => \^qrs_reg[1]_3\
    );
\rgbToManyAXIS_tdata_sig[18]_i_36\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5530553F"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[18]_i_42_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[18]_i_43_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_44_n_0\,
      O => \^qrs_reg[1]_6\
    );
\rgbToManyAXIS_tdata_sig[18]_i_37\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5530553F"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[18]_i_45_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[18]_i_46_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_47_n_0\,
      O => \^qrs_reg[1]_4\
    );
\rgbToManyAXIS_tdata_sig[18]_i_39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(59),
      I1 => drdOddbufB(35),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(11),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(51),
      O => \rgbToManyAXIS_tdata_sig[18]_i_39_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_40\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(27),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(3),
      O => \rgbToManyAXIS_tdata_sig[18]_i_40_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_41\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(43),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(19),
      O => \rgbToManyAXIS_tdata_sig[18]_i_41_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(58),
      I1 => drdOddbufB(34),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(10),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(50),
      O => \rgbToManyAXIS_tdata_sig[18]_i_42_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_43\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(26),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(2),
      O => \rgbToManyAXIS_tdata_sig[18]_i_43_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_44\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(42),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(18),
      O => \rgbToManyAXIS_tdata_sig[18]_i_44_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(57),
      I1 => drdOddbufB(33),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(9),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(49),
      O => \rgbToManyAXIS_tdata_sig[18]_i_45_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_46\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(25),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(1),
      O => \rgbToManyAXIS_tdata_sig[18]_i_46_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_47\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(41),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(17),
      O => \rgbToManyAXIS_tdata_sig[18]_i_47_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_48\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(23),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(15),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(39),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(15),
      O => \rgbToManyAXIS_tdata_sig[18]_i_48_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_49\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(55),
      I1 => drdOddbufB(31),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(7),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(47),
      O => \rgbToManyAXIS_tdata_sig[18]_i_49_n_0\
    );
\rgbToManyAXIS_tdata_sig[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \drdOddbufBm1_reg[63]\(1),
      I1 => \drdOddbufBm1_reg[63]\(0),
      I2 => \^qrs_reg[2]_0\,
      O => D(1)
    );
\rgbToManyAXIS_tdata_sig[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CA"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[1]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[1]_i_4_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      O => \^qrs_reg[2]_0\
    );
\rgbToManyAXIS_tdata_sig[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => drdOddbufB(25),
      I1 => drdOddbufB(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(9),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(1),
      O => \rgbToManyAXIS_tdata_sig[1]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => drdOddbufB(41),
      I1 => drdOddbufB(17),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(9),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(33),
      O => \rgbToManyAXIS_tdata_sig[1]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_27\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5530553F"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[23]_i_28_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[23]_i_29_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I4 => \rgbToManyAXIS_tdata_sig[23]_i_30_n_0\,
      O => \^qrs_reg[1]_5\
    );
\rgbToManyAXIS_tdata_sig[23]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(62),
      I1 => drdOddbufB(38),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(14),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(54),
      O => \rgbToManyAXIS_tdata_sig[23]_i_28_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_29\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(30),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(6),
      O => \rgbToManyAXIS_tdata_sig[23]_i_29_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdOddbufB(46),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I2 => drdOddbufB(22),
      O => \rgbToManyAXIS_tdata_sig[23]_i_30_n_0\
    );
\rgbToManyAXIS_tdata_sig[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \drdOddbufBm1_reg[63]\(1),
      I1 => \drdOddbufBm1_reg[63]\(0),
      I2 => \rgbToManyAXIS_tdata_sig[2]_i_2_n_0\,
      O => D(2)
    );
\rgbToManyAXIS_tdata_sig[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1D"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[2]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I2 => \rgbToManyAXIS_tdata_sig[2]_i_4_n_0\,
      O => \rgbToManyAXIS_tdata_sig[2]_i_2_n_0\
    );
\rgbToManyAXIS_tdata_sig[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(10),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(2),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(26),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(2),
      O => \rgbToManyAXIS_tdata_sig[2]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(42),
      I1 => drdOddbufB(18),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(10),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(34),
      O => \rgbToManyAXIS_tdata_sig[2]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[3]_i_2_n_0\,
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => D(3)
    );
\rgbToManyAXIS_tdata_sig[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(11),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(3),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(27),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(3),
      O => \rgbToManyAXIS_tdata_sig[3]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(43),
      I1 => drdOddbufB(19),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(11),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(35),
      O => \rgbToManyAXIS_tdata_sig[3]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[4]_i_2_n_0\,
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => D(4)
    );
\rgbToManyAXIS_tdata_sig[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(12),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(4),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(28),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(4),
      O => \rgbToManyAXIS_tdata_sig[4]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(44),
      I1 => drdOddbufB(20),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(12),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(36),
      O => \rgbToManyAXIS_tdata_sig[4]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[5]_i_2_n_0\,
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => D(5)
    );
\rgbToManyAXIS_tdata_sig[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(13),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(5),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(29),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(5),
      O => \rgbToManyAXIS_tdata_sig[5]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(45),
      I1 => drdOddbufB(21),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(13),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(37),
      O => \rgbToManyAXIS_tdata_sig[5]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[6]_i_2_n_0\,
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => D(6)
    );
\rgbToManyAXIS_tdata_sig[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(14),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(6),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(30),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(6),
      O => \rgbToManyAXIS_tdata_sig[6]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(46),
      I1 => drdOddbufB(22),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(14),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(38),
      O => \rgbToManyAXIS_tdata_sig[6]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8B8B800"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[7]_i_2_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]\(2),
      I2 => \rgbToManyAXIS_tdata_sig[7]_i_3_n_0\,
      I3 => \drdOddbufBm1_reg[63]\(1),
      I4 => \drdOddbufBm1_reg[63]\(0),
      O => D(7)
    );
\rgbToManyAXIS_tdata_sig[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(47),
      I1 => drdOddbufB(23),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(15),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(39),
      O => \rgbToManyAXIS_tdata_sig[7]_i_2_n_0\
    );
\rgbToManyAXIS_tdata_sig[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(15),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(7),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(31),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(7),
      O => \rgbToManyAXIS_tdata_sig[7]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[8]_i_2_n_0\,
      I1 => \drdOddbufBm1_reg[63]\(1),
      I2 => \drdOddbufBm1_reg[63]\(0),
      O => D(8)
    );
\rgbToManyAXIS_tdata_sig[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(16),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(8),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(32),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(8),
      O => \rgbToManyAXIS_tdata_sig[8]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdOddbufB(48),
      I1 => drdOddbufB(24),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(0),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(40),
      O => \rgbToManyAXIS_tdata_sig[8]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \drdOddbufBm1_reg[63]\(1),
      I1 => \drdOddbufBm1_reg[63]\(0),
      I2 => \rgbToManyAXIS_tdata_sig_reg[9]_i_2_n_0\,
      O => D(9)
    );
\rgbToManyAXIS_tdata_sig[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505F3030505F3F3F"
    )
        port map (
      I0 => drdOddbufB(17),
      I1 => \rgbToManyAXIS_tdata_sig_reg[7]_0\(9),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(33),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(9),
      O => \rgbToManyAXIS_tdata_sig[9]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => drdOddbufB(1),
      I1 => drdOddbufB(41),
      I2 => \rgbToManyAXIS_tdata_sig_reg[7]\(1),
      I3 => drdOddbufB(49),
      I4 => \rgbToManyAXIS_tdata_sig_reg[7]\(0),
      I5 => drdOddbufB(25),
      O => \rgbToManyAXIS_tdata_sig[9]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig_reg[0]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[0]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[0]_i_4_n_0\,
      O => p_2_in(0),
      S => \rgbToManyAXIS_tdata_sig_reg[7]\(2)
    );
\rgbToManyAXIS_tdata_sig_reg[10]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[10]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[10]_i_4_n_0\,
      O => \rgbToManyAXIS_tdata_sig_reg[10]_i_2_n_0\,
      S => \rgbToManyAXIS_tdata_sig_reg[7]\(2)
    );
\rgbToManyAXIS_tdata_sig_reg[11]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[11]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[11]_i_4_n_0\,
      O => \rgbToManyAXIS_tdata_sig_reg[11]_i_2_n_0\,
      S => \rgbToManyAXIS_tdata_sig_reg[7]\(2)
    );
\rgbToManyAXIS_tdata_sig_reg[18]_i_38\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[18]_i_48_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[18]_i_49_n_0\,
      O => \^p_1_in\(1),
      S => \rgbToManyAXIS_tdata_sig_reg[7]\(2)
    );
\rgbToManyAXIS_tdata_sig_reg[3]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[3]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[3]_i_4_n_0\,
      O => \rgbToManyAXIS_tdata_sig_reg[3]_i_2_n_0\,
      S => \rgbToManyAXIS_tdata_sig_reg[7]\(2)
    );
\rgbToManyAXIS_tdata_sig_reg[4]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[4]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[4]_i_4_n_0\,
      O => \rgbToManyAXIS_tdata_sig_reg[4]_i_2_n_0\,
      S => \rgbToManyAXIS_tdata_sig_reg[7]\(2)
    );
\rgbToManyAXIS_tdata_sig_reg[5]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[5]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[5]_i_4_n_0\,
      O => \rgbToManyAXIS_tdata_sig_reg[5]_i_2_n_0\,
      S => \rgbToManyAXIS_tdata_sig_reg[7]\(2)
    );
\rgbToManyAXIS_tdata_sig_reg[6]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[6]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[6]_i_4_n_0\,
      O => \rgbToManyAXIS_tdata_sig_reg[6]_i_2_n_0\,
      S => \rgbToManyAXIS_tdata_sig_reg[7]\(2)
    );
\rgbToManyAXIS_tdata_sig_reg[8]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[8]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[8]_i_4_n_0\,
      O => \rgbToManyAXIS_tdata_sig_reg[8]_i_2_n_0\,
      S => \rgbToManyAXIS_tdata_sig_reg[7]\(2)
    );
\rgbToManyAXIS_tdata_sig_reg[9]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[9]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[9]_i_4_n_0\,
      O => \rgbToManyAXIS_tdata_sig_reg[9]_i_2_n_0\,
      S => \rgbToManyAXIS_tdata_sig_reg[7]\(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64__xdcDup__1\ is
  port (
    doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
    p_0_in : out STD_LOGIC_VECTOR ( 11 downto 0 );
    S : out STD_LOGIC_VECTOR ( 0 to 0 );
    \qrs_reg[2]\ : out STD_LOGIC;
    p_3_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \qrs_reg[1]\ : out STD_LOGIC;
    \qrs_reg[1]_0\ : out STD_LOGIC;
    \qrs_reg[1]_1\ : out STD_LOGIC;
    \qrs_reg[2]_0\ : out STD_LOGIC;
    \qrs_reg[1]_2\ : out STD_LOGIC;
    \qrs_reg[1]_3\ : out STD_LOGIC;
    \qrs_reg[1]_4\ : out STD_LOGIC;
    \qrs_reg[2]_1\ : out STD_LOGIC;
    \qrs_reg[1]_5\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 23 downto 0 );
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC;
    enEobuf : in STD_LOGIC;
    oddNotEven : in STD_LOGIC;
    \rgbToManyAXIS_tdata_sig_reg[23]_i_2_0\ : in STD_LOGIC;
    \rgbToManyAXIS_tdata_sig_reg[18]_i_2_0\ : in STD_LOGIC;
    \rgbToManyAXIS_tdata_sig_reg[23]_i_2_1\ : in STD_LOGIC;
    \gr_reg[5]_i_2\ : in STD_LOGIC;
    \rgbToManyAXIS_tdata_sig_reg[18]_i_2_1\ : in STD_LOGIC;
    \rgbToManyAXIS_tdata_sig_reg[23]_i_2_2\ : in STD_LOGIC;
    \rgbToManyAXIS_tdata_sig_reg[18]_i_2_2\ : in STD_LOGIC;
    \rgbToManyAXIS_tdata_sig_reg[23]_i_2_3\ : in STD_LOGIC;
    \rgbToManyAXIS_tdata_sig_reg[18]_i_2_3\ : in STD_LOGIC;
    \gr_reg[5]_i_2_0\ : in STD_LOGIC;
    \gr_reg[5]_i_2_1\ : in STD_LOGIC;
    enEobufB : in STD_LOGIC;
    \rgbToManyAXIS_tdata_sig_reg[28]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rgbToManyAXIS_tdata_sig[35]_i_2_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \rgbToManyAXIS_tdata_sig[18]_i_3_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \rgbToManyAXIS_tdata_sig_reg[35]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rgbToManyAXIS_tdata_sig_reg[18]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    p_1_in : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64__xdcDup__1\ : entity is "Dpbram_size6kB_a64b64";
end \design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64__xdcDup__1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64__xdcDup__1\ is
  signal \^doutb\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal drdEvenAbufB : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal enB7_out : STD_LOGIC;
  signal \myMnfcore_i_1__17_n_0\ : STD_LOGIC;
  signal \^p_0_in\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \^p_3_in\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^qrs_reg[1]\ : STD_LOGIC;
  signal \^qrs_reg[1]_0\ : STD_LOGIC;
  signal \^qrs_reg[1]_1\ : STD_LOGIC;
  signal \^qrs_reg[1]_2\ : STD_LOGIC;
  signal \^qrs_reg[1]_3\ : STD_LOGIC;
  signal \^qrs_reg[1]_4\ : STD_LOGIC;
  signal \^qrs_reg[1]_5\ : STD_LOGIC;
  signal \^qrs_reg[2]\ : STD_LOGIC;
  signal \^qrs_reg[2]_0\ : STD_LOGIC;
  signal \^qrs_reg[2]_1\ : STD_LOGIC;
  signal rgbToManyAXIS_tdata_sig0 : STD_LOGIC_VECTOR ( 12 downto 1 );
  signal \rgbToManyAXIS_tdata_sig[18]_i_11_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_12_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_13_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_14_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_15_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_16_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_17_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_19_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_20_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_21_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_22_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_23_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_24_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_25_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_26_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_27_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_28_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_29_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_30_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_31_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_32_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_33_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[18]_i_34_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_10_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_11_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_12_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_13_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_14_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_15_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_16_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_17_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_18_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_19_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_20_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_21_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_22_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_23_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_24_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_25_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_26_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_7_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_8_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[23]_i_9_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[24]_i_5_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[24]_i_6_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[24]_i_7_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[24]_i_8_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[25]_i_5_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[25]_i_6_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[25]_i_7_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[25]_i_8_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[26]_i_10_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[26]_i_11_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[26]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[26]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[26]_i_5_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[26]_i_6_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[26]_i_7_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[26]_i_8_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[26]_i_9_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[27]_i_5_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[27]_i_6_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[27]_i_7_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[27]_i_8_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[28]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[28]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[28]_i_5_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[28]_i_6_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[29]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[29]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[29]_i_5_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[29]_i_6_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[30]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[30]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[30]_i_5_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[30]_i_6_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[31]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[31]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[31]_i_5_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[31]_i_6_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[32]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[32]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[32]_i_5_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[32]_i_6_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[32]_i_7_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[33]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[33]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[33]_i_5_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[33]_i_6_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[34]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[34]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[34]_i_5_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[34]_i_6_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[35]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[35]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[35]_i_5_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig[35]_i_6_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_1\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_2\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_3\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_4\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_5\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_6\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_7\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[23]_i_2_n_5\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[23]_i_2_n_6\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[23]_i_2_n_7\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[24]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[24]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[25]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[25]_i_4_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[27]_i_3_n_0\ : STD_LOGIC;
  signal \rgbToManyAXIS_tdata_sig_reg[27]_i_4_n_0\ : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_rgbToManyAXIS_tdata_sig_reg[18]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_rgbToManyAXIS_tdata_sig_reg[23]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_rgbToManyAXIS_tdata_sig_reg[23]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size6kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \myMnfcore_i_1__17\ : label is "soft_lutpair2897";
  attribute SOFT_HLUTNM of \myMnfcore_i_2__4\ : label is "soft_lutpair2897";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[12]_i_1\ : label is "soft_lutpair2911";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[13]_i_1\ : label is "soft_lutpair2911";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[14]_i_1\ : label is "soft_lutpair2910";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[15]_i_1\ : label is "soft_lutpair2910";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[16]_i_1\ : label is "soft_lutpair2909";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[17]_i_1\ : label is "soft_lutpair2909";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[18]_i_1\ : label is "soft_lutpair2908";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[18]_i_21\ : label is "soft_lutpair2895";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[18]_i_22\ : label is "soft_lutpair2896";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[18]_i_26\ : label is "soft_lutpair2894";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[19]_i_1\ : label is "soft_lutpair2908";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[20]_i_1\ : label is "soft_lutpair2907";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[21]_i_1\ : label is "soft_lutpair2907";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[22]_i_1\ : label is "soft_lutpair2906";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[23]_i_1\ : label is "soft_lutpair2906";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[24]_i_1\ : label is "soft_lutpair2905";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[25]_i_1\ : label is "soft_lutpair2905";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[26]_i_1\ : label is "soft_lutpair2904";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[26]_i_10\ : label is "soft_lutpair2898";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[26]_i_11\ : label is "soft_lutpair2898";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[26]_i_5\ : label is "soft_lutpair2895";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[26]_i_6\ : label is "soft_lutpair2896";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[26]_i_8\ : label is "soft_lutpair2899";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[26]_i_9\ : label is "soft_lutpair2899";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[27]_i_1\ : label is "soft_lutpair2904";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[28]_i_1\ : label is "soft_lutpair2903";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[29]_i_1\ : label is "soft_lutpair2903";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[30]_i_1\ : label is "soft_lutpair2902";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[31]_i_1\ : label is "soft_lutpair2902";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[32]_i_1\ : label is "soft_lutpair2901";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[32]_i_7\ : label is "soft_lutpair2894";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[33]_i_1\ : label is "soft_lutpair2901";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[34]_i_1\ : label is "soft_lutpair2900";
  attribute SOFT_HLUTNM of \rgbToManyAXIS_tdata_sig[35]_i_1\ : label is "soft_lutpair2900";
begin
  doutb(15 downto 0) <= \^doutb\(15 downto 0);
  p_0_in(11 downto 0) <= \^p_0_in\(11 downto 0);
  p_3_in(1 downto 0) <= \^p_3_in\(1 downto 0);
  \qrs_reg[1]\ <= \^qrs_reg[1]\;
  \qrs_reg[1]_0\ <= \^qrs_reg[1]_0\;
  \qrs_reg[1]_1\ <= \^qrs_reg[1]_1\;
  \qrs_reg[1]_2\ <= \^qrs_reg[1]_2\;
  \qrs_reg[1]_3\ <= \^qrs_reg[1]_3\;
  \qrs_reg[1]_4\ <= \^qrs_reg[1]_4\;
  \qrs_reg[1]_5\ <= \^qrs_reg[1]_5\;
  \qrs_reg[2]\ <= \^qrs_reg[2]\;
  \qrs_reg[2]_0\ <= \^qrs_reg[2]_0\;
  \qrs_reg[2]_1\ <= \^qrs_reg[2]_1\;
\gr[5]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BD4242BD2BD4D42B"
    )
        port map (
      I0 => \^p_0_in\(1),
      I1 => \gr_reg[5]_i_2\,
      I2 => \gr_reg[5]_i_2_0\,
      I3 => \gr_reg[5]_i_2_1\,
      I4 => \^qrs_reg[2]\,
      I5 => \^p_3_in\(1),
      O => S(0)
    );
myMnfcore: entity work.design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64
     port map (
      addra(9 downto 0) => Q(9 downto 0),
      addrb(9 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(9 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(63 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 48) => \^doutb\(15 downto 0),
      doutb(47 downto 0) => drdEvenAbufB(47 downto 0),
      ena => \myMnfcore_i_1__17_n_0\,
      enb => enB7_out,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I1 => enEobuf,
      I2 => oddNotEven,
      O => \myMnfcore_i_1__17_n_0\
    );
\myMnfcore_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I1 => enEobufB,
      O => enB7_out
    );
\rgbToManyAXIS_tdata_sig[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rgbToManyAXIS_tdata_sig0(1),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(0)
    );
\rgbToManyAXIS_tdata_sig[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rgbToManyAXIS_tdata_sig0(2),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(1)
    );
\rgbToManyAXIS_tdata_sig[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rgbToManyAXIS_tdata_sig0(3),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(2)
    );
\rgbToManyAXIS_tdata_sig[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rgbToManyAXIS_tdata_sig0(4),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(3)
    );
\rgbToManyAXIS_tdata_sig[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rgbToManyAXIS_tdata_sig0(5),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(4)
    );
\rgbToManyAXIS_tdata_sig[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rgbToManyAXIS_tdata_sig0(6),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(5)
    );
\rgbToManyAXIS_tdata_sig[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rgbToManyAXIS_tdata_sig0(7),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(6)
    );
\rgbToManyAXIS_tdata_sig[18]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[28]_i_6_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[18]_i_33_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I3 => \rgbToManyAXIS_tdata_sig[18]_i_34_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I5 => \rgbToManyAXIS_tdata_sig[28]_i_5_n_0\,
      O => \^p_0_in\(0)
    );
\rgbToManyAXIS_tdata_sig[18]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^p_0_in\(7),
      I1 => \rgbToManyAXIS_tdata_sig_reg[18]_i_2_3\,
      O => \rgbToManyAXIS_tdata_sig[18]_i_11_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^p_0_in\(6),
      I1 => \rgbToManyAXIS_tdata_sig_reg[18]_i_2_2\,
      O => \rgbToManyAXIS_tdata_sig[18]_i_12_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^p_0_in\(5),
      I1 => \rgbToManyAXIS_tdata_sig_reg[18]_i_2_1\,
      O => \rgbToManyAXIS_tdata_sig[18]_i_13_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^p_0_in\(4),
      I1 => \rgbToManyAXIS_tdata_sig_reg[18]_i_2_0\,
      O => \rgbToManyAXIS_tdata_sig[18]_i_14_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^p_0_in\(3),
      I1 => p_1_in(1),
      O => \rgbToManyAXIS_tdata_sig[18]_i_15_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^p_0_in\(2),
      I1 => p_1_in(0),
      O => \rgbToManyAXIS_tdata_sig[18]_i_16_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^p_0_in\(1),
      I1 => \gr_reg[5]_i_2\,
      O => \rgbToManyAXIS_tdata_sig[18]_i_17_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(15),
      I1 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I2 => drdEvenAbufB(39),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I4 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(39),
      O => \rgbToManyAXIS_tdata_sig[18]_i_19_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(15),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(15),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(7),
      O => \rgbToManyAXIS_tdata_sig[18]_i_20_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(14),
      I1 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I2 => drdEvenAbufB(38),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I4 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(38),
      O => \rgbToManyAXIS_tdata_sig[18]_i_21_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_22\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(14),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(14),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(6),
      O => \rgbToManyAXIS_tdata_sig[18]_i_22_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(13),
      I1 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I2 => drdEvenAbufB(37),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I4 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(37),
      O => \rgbToManyAXIS_tdata_sig[18]_i_23_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_24\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(13),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(13),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(5),
      O => \rgbToManyAXIS_tdata_sig[18]_i_24_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(12),
      I1 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I2 => drdEvenAbufB(36),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I4 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(36),
      O => \rgbToManyAXIS_tdata_sig[18]_i_25_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(12),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(12),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(4),
      O => \rgbToManyAXIS_tdata_sig[18]_i_26_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_27\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(11),
      I1 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I2 => drdEvenAbufB(35),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I4 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(35),
      O => \rgbToManyAXIS_tdata_sig[18]_i_27_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_28\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(11),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(11),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(3),
      O => \rgbToManyAXIS_tdata_sig[18]_i_28_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_29\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(10),
      I1 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I2 => drdEvenAbufB(34),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I4 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(34),
      O => \rgbToManyAXIS_tdata_sig[18]_i_29_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[35]_i_6_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[18]_i_19_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I3 => \rgbToManyAXIS_tdata_sig[18]_i_20_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_5_n_0\,
      O => \^p_0_in\(7)
    );
\rgbToManyAXIS_tdata_sig[18]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(10),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(10),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(2),
      O => \rgbToManyAXIS_tdata_sig[18]_i_30_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_31\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(9),
      I1 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I2 => drdEvenAbufB(33),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I4 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(33),
      O => \rgbToManyAXIS_tdata_sig[18]_i_31_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_32\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(9),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(9),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(1),
      O => \rgbToManyAXIS_tdata_sig[18]_i_32_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_33\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(8),
      I1 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I2 => drdEvenAbufB(32),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I4 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(32),
      O => \rgbToManyAXIS_tdata_sig[18]_i_33_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_34\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(8),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(8),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(0),
      O => \rgbToManyAXIS_tdata_sig[18]_i_34_n_0\
    );
\rgbToManyAXIS_tdata_sig[18]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[34]_i_6_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[18]_i_21_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I3 => \rgbToManyAXIS_tdata_sig[18]_i_22_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I5 => \rgbToManyAXIS_tdata_sig[34]_i_5_n_0\,
      O => \^p_0_in\(6)
    );
\rgbToManyAXIS_tdata_sig[18]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[33]_i_6_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[18]_i_23_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I3 => \rgbToManyAXIS_tdata_sig[18]_i_24_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I5 => \rgbToManyAXIS_tdata_sig[33]_i_5_n_0\,
      O => \^p_0_in\(5)
    );
\rgbToManyAXIS_tdata_sig[18]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[32]_i_5_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[18]_i_25_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I3 => \rgbToManyAXIS_tdata_sig[18]_i_26_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I5 => \rgbToManyAXIS_tdata_sig[32]_i_6_n_0\,
      O => \^p_0_in\(4)
    );
\rgbToManyAXIS_tdata_sig[18]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[31]_i_6_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[18]_i_27_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I3 => \rgbToManyAXIS_tdata_sig[18]_i_28_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I5 => \rgbToManyAXIS_tdata_sig[31]_i_5_n_0\,
      O => \^p_0_in\(3)
    );
\rgbToManyAXIS_tdata_sig[18]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[30]_i_6_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[18]_i_29_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I3 => \rgbToManyAXIS_tdata_sig[18]_i_30_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I5 => \rgbToManyAXIS_tdata_sig[30]_i_5_n_0\,
      O => \^p_0_in\(2)
    );
\rgbToManyAXIS_tdata_sig[18]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[29]_i_6_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[18]_i_31_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I3 => \rgbToManyAXIS_tdata_sig[18]_i_32_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I5 => \rgbToManyAXIS_tdata_sig[29]_i_5_n_0\,
      O => \^p_0_in\(1)
    );
\rgbToManyAXIS_tdata_sig[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rgbToManyAXIS_tdata_sig0(8),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(7)
    );
\rgbToManyAXIS_tdata_sig[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rgbToManyAXIS_tdata_sig0(9),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(8)
    );
\rgbToManyAXIS_tdata_sig[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rgbToManyAXIS_tdata_sig0(10),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(9)
    );
\rgbToManyAXIS_tdata_sig[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rgbToManyAXIS_tdata_sig0(11),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(10)
    );
\rgbToManyAXIS_tdata_sig[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rgbToManyAXIS_tdata_sig0(12),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(11)
    );
\rgbToManyAXIS_tdata_sig[23]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^p_0_in\(8),
      I1 => \rgbToManyAXIS_tdata_sig_reg[23]_i_2_0\,
      O => \rgbToManyAXIS_tdata_sig[23]_i_10_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(3),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(51),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(27),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(27),
      O => \rgbToManyAXIS_tdata_sig[23]_i_11_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(3),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(3),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(43),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(43),
      O => \rgbToManyAXIS_tdata_sig[23]_i_12_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(19),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(19),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(11),
      O => \rgbToManyAXIS_tdata_sig[23]_i_13_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(35),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(35),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(11),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(11),
      O => \rgbToManyAXIS_tdata_sig[23]_i_14_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(2),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(50),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(26),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(26),
      O => \rgbToManyAXIS_tdata_sig[23]_i_15_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(2),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(2),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(42),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(42),
      O => \rgbToManyAXIS_tdata_sig[23]_i_16_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(18),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(18),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(10),
      O => \rgbToManyAXIS_tdata_sig[23]_i_17_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(34),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(34),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(10),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(10),
      O => \rgbToManyAXIS_tdata_sig[23]_i_18_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(1),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(49),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(25),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(25),
      O => \rgbToManyAXIS_tdata_sig[23]_i_19_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(1),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(41),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(41),
      O => \rgbToManyAXIS_tdata_sig[23]_i_20_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(17),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(17),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(9),
      O => \rgbToManyAXIS_tdata_sig[23]_i_21_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(33),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(33),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(9),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(9),
      O => \rgbToManyAXIS_tdata_sig[23]_i_22_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(0),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(48),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(24),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(24),
      O => \rgbToManyAXIS_tdata_sig[23]_i_23_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(0),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(0),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(40),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(40),
      O => \rgbToManyAXIS_tdata_sig[23]_i_24_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(16),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(16),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(8),
      O => \rgbToManyAXIS_tdata_sig[23]_i_25_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(32),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(32),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(8),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(8),
      O => \rgbToManyAXIS_tdata_sig[23]_i_26_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[23]_i_11_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[23]_i_12_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I3 => \rgbToManyAXIS_tdata_sig[23]_i_13_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I5 => \rgbToManyAXIS_tdata_sig[23]_i_14_n_0\,
      O => \^p_0_in\(11)
    );
\rgbToManyAXIS_tdata_sig[23]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[23]_i_15_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[23]_i_16_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I3 => \rgbToManyAXIS_tdata_sig[23]_i_17_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I5 => \rgbToManyAXIS_tdata_sig[23]_i_18_n_0\,
      O => \^p_0_in\(10)
    );
\rgbToManyAXIS_tdata_sig[23]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[23]_i_19_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[23]_i_20_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I3 => \rgbToManyAXIS_tdata_sig[23]_i_21_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I5 => \rgbToManyAXIS_tdata_sig[23]_i_22_n_0\,
      O => \^p_0_in\(9)
    );
\rgbToManyAXIS_tdata_sig[23]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[23]_i_23_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[23]_i_24_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I3 => \rgbToManyAXIS_tdata_sig[23]_i_25_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I5 => \rgbToManyAXIS_tdata_sig[23]_i_26_n_0\,
      O => \^p_0_in\(8)
    );
\rgbToManyAXIS_tdata_sig[23]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^p_0_in\(11),
      I1 => \rgbToManyAXIS_tdata_sig_reg[23]_i_2_3\,
      O => \rgbToManyAXIS_tdata_sig[23]_i_7_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^p_0_in\(10),
      I1 => \rgbToManyAXIS_tdata_sig_reg[23]_i_2_2\,
      O => \rgbToManyAXIS_tdata_sig[23]_i_8_n_0\
    );
\rgbToManyAXIS_tdata_sig[23]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^p_0_in\(9),
      I1 => \rgbToManyAXIS_tdata_sig_reg[23]_i_2_1\,
      O => \rgbToManyAXIS_tdata_sig[23]_i_9_n_0\
    );
\rgbToManyAXIS_tdata_sig[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^p_3_in\(0),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(12)
    );
\rgbToManyAXIS_tdata_sig[24]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(36),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(36),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(12),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(12),
      O => \rgbToManyAXIS_tdata_sig[24]_i_5_n_0\
    );
\rgbToManyAXIS_tdata_sig[24]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(20),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(20),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(12),
      O => \rgbToManyAXIS_tdata_sig[24]_i_6_n_0\
    );
\rgbToManyAXIS_tdata_sig[24]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(4),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(4),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(44),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(44),
      O => \rgbToManyAXIS_tdata_sig[24]_i_7_n_0\
    );
\rgbToManyAXIS_tdata_sig[24]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(4),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(52),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(28),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(28),
      O => \rgbToManyAXIS_tdata_sig[24]_i_8_n_0\
    );
\rgbToManyAXIS_tdata_sig[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^p_3_in\(1),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(13)
    );
\rgbToManyAXIS_tdata_sig[25]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(37),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(37),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(13),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(13),
      O => \rgbToManyAXIS_tdata_sig[25]_i_5_n_0\
    );
\rgbToManyAXIS_tdata_sig[25]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(21),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(21),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(13),
      O => \rgbToManyAXIS_tdata_sig[25]_i_6_n_0\
    );
\rgbToManyAXIS_tdata_sig[25]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(5),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(5),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(45),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(45),
      O => \rgbToManyAXIS_tdata_sig[25]_i_7_n_0\
    );
\rgbToManyAXIS_tdata_sig[25]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(5),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(53),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(29),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(29),
      O => \rgbToManyAXIS_tdata_sig[25]_i_8_n_0\
    );
\rgbToManyAXIS_tdata_sig[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      I2 => \^qrs_reg[2]\,
      O => D(14)
    );
\rgbToManyAXIS_tdata_sig[26]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^doutb\(6),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(54),
      O => \rgbToManyAXIS_tdata_sig[26]_i_10_n_0\
    );
\rgbToManyAXIS_tdata_sig[26]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdEvenAbufB(30),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(30),
      O => \rgbToManyAXIS_tdata_sig[26]_i_11_n_0\
    );
\rgbToManyAXIS_tdata_sig[26]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05F5030305F5F3F3"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[26]_i_5_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[26]_i_6_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I3 => \rgbToManyAXIS_tdata_sig[26]_i_7_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I5 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(14),
      O => \rgbToManyAXIS_tdata_sig[26]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[26]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"03F3050503F3F5F5"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[26]_i_8_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[26]_i_9_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I3 => \rgbToManyAXIS_tdata_sig[26]_i_10_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I5 => \rgbToManyAXIS_tdata_sig[26]_i_11_n_0\,
      O => \rgbToManyAXIS_tdata_sig[26]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[26]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdEvenAbufB(38),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(38),
      O => \rgbToManyAXIS_tdata_sig[26]_i_5_n_0\
    );
\rgbToManyAXIS_tdata_sig[26]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdEvenAbufB(14),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(14),
      O => \rgbToManyAXIS_tdata_sig[26]_i_6_n_0\
    );
\rgbToManyAXIS_tdata_sig[26]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdEvenAbufB(22),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(22),
      O => \rgbToManyAXIS_tdata_sig[26]_i_7_n_0\
    );
\rgbToManyAXIS_tdata_sig[26]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdEvenAbufB(46),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(46),
      O => \rgbToManyAXIS_tdata_sig[26]_i_8_n_0\
    );
\rgbToManyAXIS_tdata_sig[26]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdEvenAbufB(6),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(6),
      O => \rgbToManyAXIS_tdata_sig[26]_i_9_n_0\
    );
\rgbToManyAXIS_tdata_sig[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^qrs_reg[2]_1\,
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I2 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      O => D(15)
    );
\rgbToManyAXIS_tdata_sig[27]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(39),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(39),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(15),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(15),
      O => \rgbToManyAXIS_tdata_sig[27]_i_5_n_0\
    );
\rgbToManyAXIS_tdata_sig[27]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => drdEvenAbufB(23),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(23),
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I4 => \rgbToManyAXIS_tdata_sig[18]_i_3_0\(15),
      O => \rgbToManyAXIS_tdata_sig[27]_i_6_n_0\
    );
\rgbToManyAXIS_tdata_sig[27]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(7),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(7),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(47),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(47),
      O => \rgbToManyAXIS_tdata_sig[27]_i_7_n_0\
    );
\rgbToManyAXIS_tdata_sig[27]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(7),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(55),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(31),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(31),
      O => \rgbToManyAXIS_tdata_sig[27]_i_8_n_0\
    );
\rgbToManyAXIS_tdata_sig[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      I2 => \^qrs_reg[1]\,
      O => D(16)
    );
\rgbToManyAXIS_tdata_sig[28]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55330F0055330FFF"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[28]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[28]_i_4_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig[28]_i_5_n_0\,
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I5 => \rgbToManyAXIS_tdata_sig[28]_i_6_n_0\,
      O => \^qrs_reg[1]\
    );
\rgbToManyAXIS_tdata_sig[28]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(8),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(56),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(32),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(32),
      O => \rgbToManyAXIS_tdata_sig[28]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[28]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(8),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(8),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => \^doutb\(0),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(48),
      O => \rgbToManyAXIS_tdata_sig[28]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[28]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(24),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(24),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(0),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(0),
      O => \rgbToManyAXIS_tdata_sig[28]_i_5_n_0\
    );
\rgbToManyAXIS_tdata_sig[28]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(40),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(40),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(16),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(16),
      O => \rgbToManyAXIS_tdata_sig[28]_i_6_n_0\
    );
\rgbToManyAXIS_tdata_sig[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      I2 => \^qrs_reg[1]_0\,
      O => D(17)
    );
\rgbToManyAXIS_tdata_sig[29]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55330F0055330FFF"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[29]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[29]_i_4_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig[29]_i_5_n_0\,
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I5 => \rgbToManyAXIS_tdata_sig[29]_i_6_n_0\,
      O => \^qrs_reg[1]_0\
    );
\rgbToManyAXIS_tdata_sig[29]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(9),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(57),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(33),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(33),
      O => \rgbToManyAXIS_tdata_sig[29]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[29]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(9),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(9),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => \^doutb\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(49),
      O => \rgbToManyAXIS_tdata_sig[29]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[29]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(25),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(25),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(1),
      O => \rgbToManyAXIS_tdata_sig[29]_i_5_n_0\
    );
\rgbToManyAXIS_tdata_sig[29]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(41),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(41),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(17),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(17),
      O => \rgbToManyAXIS_tdata_sig[29]_i_6_n_0\
    );
\rgbToManyAXIS_tdata_sig[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      I2 => \^qrs_reg[1]_2\,
      O => D(18)
    );
\rgbToManyAXIS_tdata_sig[30]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55330F0055330FFF"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[30]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[30]_i_4_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig[30]_i_5_n_0\,
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I5 => \rgbToManyAXIS_tdata_sig[30]_i_6_n_0\,
      O => \^qrs_reg[1]_2\
    );
\rgbToManyAXIS_tdata_sig[30]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(10),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(58),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(34),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(34),
      O => \rgbToManyAXIS_tdata_sig[30]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[30]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(10),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(10),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => \^doutb\(2),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(50),
      O => \rgbToManyAXIS_tdata_sig[30]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[30]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(26),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(26),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(2),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(2),
      O => \rgbToManyAXIS_tdata_sig[30]_i_5_n_0\
    );
\rgbToManyAXIS_tdata_sig[30]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(42),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(42),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(18),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(18),
      O => \rgbToManyAXIS_tdata_sig[30]_i_6_n_0\
    );
\rgbToManyAXIS_tdata_sig[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      I2 => \^qrs_reg[1]_4\,
      O => D(19)
    );
\rgbToManyAXIS_tdata_sig[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55330F0055330FFF"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[31]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[31]_i_4_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig[31]_i_5_n_0\,
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I5 => \rgbToManyAXIS_tdata_sig[31]_i_6_n_0\,
      O => \^qrs_reg[1]_4\
    );
\rgbToManyAXIS_tdata_sig[31]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(11),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(59),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(35),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(35),
      O => \rgbToManyAXIS_tdata_sig[31]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[31]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(11),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(11),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => \^doutb\(3),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(51),
      O => \rgbToManyAXIS_tdata_sig[31]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[31]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(27),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(27),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(3),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(3),
      O => \rgbToManyAXIS_tdata_sig[31]_i_5_n_0\
    );
\rgbToManyAXIS_tdata_sig[31]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(43),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(43),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(19),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(19),
      O => \rgbToManyAXIS_tdata_sig[31]_i_6_n_0\
    );
\rgbToManyAXIS_tdata_sig[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      I2 => \^qrs_reg[2]_0\,
      O => D(20)
    );
\rgbToManyAXIS_tdata_sig[32]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020A0AF2F2FA0AF"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[32]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[32]_i_4_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I3 => \rgbToManyAXIS_tdata_sig[32]_i_5_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I5 => \rgbToManyAXIS_tdata_sig[32]_i_6_n_0\,
      O => \^qrs_reg[2]_0\
    );
\rgbToManyAXIS_tdata_sig[32]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00FF4747"
    )
        port map (
      I0 => \^doutb\(4),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(52),
      I3 => \rgbToManyAXIS_tdata_sig[32]_i_7_n_0\,
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I5 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      O => \rgbToManyAXIS_tdata_sig[32]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[32]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(12),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(60),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(36),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(36),
      O => \rgbToManyAXIS_tdata_sig[32]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[32]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(44),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(44),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(20),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(20),
      O => \rgbToManyAXIS_tdata_sig[32]_i_5_n_0\
    );
\rgbToManyAXIS_tdata_sig[32]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(28),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(28),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(4),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(4),
      O => \rgbToManyAXIS_tdata_sig[32]_i_6_n_0\
    );
\rgbToManyAXIS_tdata_sig[32]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdEvenAbufB(12),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(12),
      O => \rgbToManyAXIS_tdata_sig[32]_i_7_n_0\
    );
\rgbToManyAXIS_tdata_sig[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      I2 => \^qrs_reg[1]_1\,
      O => D(21)
    );
\rgbToManyAXIS_tdata_sig[33]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55330F0055330FFF"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[33]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[33]_i_4_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig[33]_i_5_n_0\,
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I5 => \rgbToManyAXIS_tdata_sig[33]_i_6_n_0\,
      O => \^qrs_reg[1]_1\
    );
\rgbToManyAXIS_tdata_sig[33]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(13),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(61),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(37),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(37),
      O => \rgbToManyAXIS_tdata_sig[33]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[33]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(13),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(13),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => \^doutb\(5),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(53),
      O => \rgbToManyAXIS_tdata_sig[33]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[33]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(29),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(29),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(5),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(5),
      O => \rgbToManyAXIS_tdata_sig[33]_i_5_n_0\
    );
\rgbToManyAXIS_tdata_sig[33]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(45),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(45),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(21),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(21),
      O => \rgbToManyAXIS_tdata_sig[33]_i_6_n_0\
    );
\rgbToManyAXIS_tdata_sig[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      I2 => \^qrs_reg[1]_3\,
      O => D(22)
    );
\rgbToManyAXIS_tdata_sig[34]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55330F0055330FFF"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[34]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[34]_i_4_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig[34]_i_5_n_0\,
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I5 => \rgbToManyAXIS_tdata_sig[34]_i_6_n_0\,
      O => \^qrs_reg[1]_3\
    );
\rgbToManyAXIS_tdata_sig[34]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(14),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(62),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(38),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(38),
      O => \rgbToManyAXIS_tdata_sig[34]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[34]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(14),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(14),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => \^doutb\(6),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(54),
      O => \rgbToManyAXIS_tdata_sig[34]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[34]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(30),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(30),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(6),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(6),
      O => \rgbToManyAXIS_tdata_sig[34]_i_5_n_0\
    );
\rgbToManyAXIS_tdata_sig[34]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(46),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(46),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(22),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(22),
      O => \rgbToManyAXIS_tdata_sig[34]_i_6_n_0\
    );
\rgbToManyAXIS_tdata_sig[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[35]\(1),
      I1 => \rgbToManyAXIS_tdata_sig_reg[35]\(0),
      I2 => \^qrs_reg[1]_5\,
      O => D(23)
    );
\rgbToManyAXIS_tdata_sig[35]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55330F0055330FFF"
    )
        port map (
      I0 => \rgbToManyAXIS_tdata_sig[35]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_4_n_0\,
      I2 => \rgbToManyAXIS_tdata_sig[35]_i_5_n_0\,
      I3 => \rgbToManyAXIS_tdata_sig_reg[28]\(1),
      I4 => \rgbToManyAXIS_tdata_sig_reg[28]\(2),
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_6_n_0\,
      O => \^qrs_reg[1]_5\
    );
\rgbToManyAXIS_tdata_sig[35]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \^doutb\(15),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(63),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(39),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(39),
      O => \rgbToManyAXIS_tdata_sig[35]_i_3_n_0\
    );
\rgbToManyAXIS_tdata_sig[35]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(15),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(15),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => \^doutb\(7),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(55),
      O => \rgbToManyAXIS_tdata_sig[35]_i_4_n_0\
    );
\rgbToManyAXIS_tdata_sig[35]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(31),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(31),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(7),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(7),
      O => \rgbToManyAXIS_tdata_sig[35]_i_5_n_0\
    );
\rgbToManyAXIS_tdata_sig[35]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => drdEvenAbufB(47),
      I1 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(47),
      I2 => \rgbToManyAXIS_tdata_sig_reg[28]\(0),
      I3 => drdEvenAbufB(23),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I5 => \rgbToManyAXIS_tdata_sig[35]_i_2_0\(23),
      O => \rgbToManyAXIS_tdata_sig[35]_i_6_n_0\
    );
\rgbToManyAXIS_tdata_sig_reg[18]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_0\,
      CO(6) => \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_1\,
      CO(5) => \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_2\,
      CO(4) => \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_3\,
      CO(3) => \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_4\,
      CO(2) => \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_5\,
      CO(1) => \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_6\,
      CO(0) => \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_7\,
      DI(7 downto 0) => \^p_0_in\(7 downto 0),
      O(7 downto 1) => rgbToManyAXIS_tdata_sig0(7 downto 1),
      O(0) => \NLW_rgbToManyAXIS_tdata_sig_reg[18]_i_2_O_UNCONNECTED\(0),
      S(7) => \rgbToManyAXIS_tdata_sig[18]_i_11_n_0\,
      S(6) => \rgbToManyAXIS_tdata_sig[18]_i_12_n_0\,
      S(5) => \rgbToManyAXIS_tdata_sig[18]_i_13_n_0\,
      S(4) => \rgbToManyAXIS_tdata_sig[18]_i_14_n_0\,
      S(3) => \rgbToManyAXIS_tdata_sig[18]_i_15_n_0\,
      S(2) => \rgbToManyAXIS_tdata_sig[18]_i_16_n_0\,
      S(1) => \rgbToManyAXIS_tdata_sig[18]_i_17_n_0\,
      S(0) => \rgbToManyAXIS_tdata_sig_reg[18]\(0)
    );
\rgbToManyAXIS_tdata_sig_reg[23]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \rgbToManyAXIS_tdata_sig_reg[18]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_rgbToManyAXIS_tdata_sig_reg[23]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => rgbToManyAXIS_tdata_sig0(12),
      CO(3) => \NLW_rgbToManyAXIS_tdata_sig_reg[23]_i_2_CO_UNCONNECTED\(3),
      CO(2) => \rgbToManyAXIS_tdata_sig_reg[23]_i_2_n_5\,
      CO(1) => \rgbToManyAXIS_tdata_sig_reg[23]_i_2_n_6\,
      CO(0) => \rgbToManyAXIS_tdata_sig_reg[23]_i_2_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3 downto 0) => \^p_0_in\(11 downto 8),
      O(7 downto 4) => \NLW_rgbToManyAXIS_tdata_sig_reg[23]_i_2_O_UNCONNECTED\(7 downto 4),
      O(3 downto 0) => rgbToManyAXIS_tdata_sig0(11 downto 8),
      S(7 downto 4) => B"0001",
      S(3) => \rgbToManyAXIS_tdata_sig[23]_i_7_n_0\,
      S(2) => \rgbToManyAXIS_tdata_sig[23]_i_8_n_0\,
      S(1) => \rgbToManyAXIS_tdata_sig[23]_i_9_n_0\,
      S(0) => \rgbToManyAXIS_tdata_sig[23]_i_10_n_0\
    );
\rgbToManyAXIS_tdata_sig_reg[24]_i_2\: unisim.vcomponents.MUXF8
     port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[24]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig_reg[24]_i_4_n_0\,
      O => \^p_3_in\(0),
      S => \rgbToManyAXIS_tdata_sig_reg[28]\(2)
    );
\rgbToManyAXIS_tdata_sig_reg[24]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[24]_i_5_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[24]_i_6_n_0\,
      O => \rgbToManyAXIS_tdata_sig_reg[24]_i_3_n_0\,
      S => \rgbToManyAXIS_tdata_sig_reg[28]\(1)
    );
\rgbToManyAXIS_tdata_sig_reg[24]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[24]_i_7_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[24]_i_8_n_0\,
      O => \rgbToManyAXIS_tdata_sig_reg[24]_i_4_n_0\,
      S => \rgbToManyAXIS_tdata_sig_reg[28]\(1)
    );
\rgbToManyAXIS_tdata_sig_reg[25]_i_2\: unisim.vcomponents.MUXF8
     port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[25]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig_reg[25]_i_4_n_0\,
      O => \^p_3_in\(1),
      S => \rgbToManyAXIS_tdata_sig_reg[28]\(2)
    );
\rgbToManyAXIS_tdata_sig_reg[25]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[25]_i_5_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[25]_i_6_n_0\,
      O => \rgbToManyAXIS_tdata_sig_reg[25]_i_3_n_0\,
      S => \rgbToManyAXIS_tdata_sig_reg[28]\(1)
    );
\rgbToManyAXIS_tdata_sig_reg[25]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[25]_i_7_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[25]_i_8_n_0\,
      O => \rgbToManyAXIS_tdata_sig_reg[25]_i_4_n_0\,
      S => \rgbToManyAXIS_tdata_sig_reg[28]\(1)
    );
\rgbToManyAXIS_tdata_sig_reg[26]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[26]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[26]_i_4_n_0\,
      O => \^qrs_reg[2]\,
      S => \rgbToManyAXIS_tdata_sig_reg[28]\(2)
    );
\rgbToManyAXIS_tdata_sig_reg[27]_i_2\: unisim.vcomponents.MUXF8
     port map (
      I0 => \rgbToManyAXIS_tdata_sig_reg[27]_i_3_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig_reg[27]_i_4_n_0\,
      O => \^qrs_reg[2]_1\,
      S => \rgbToManyAXIS_tdata_sig_reg[28]\(2)
    );
\rgbToManyAXIS_tdata_sig_reg[27]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[27]_i_5_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[27]_i_6_n_0\,
      O => \rgbToManyAXIS_tdata_sig_reg[27]_i_3_n_0\,
      S => \rgbToManyAXIS_tdata_sig_reg[28]\(1)
    );
\rgbToManyAXIS_tdata_sig_reg[27]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rgbToManyAXIS_tdata_sig[27]_i_7_n_0\,
      I1 => \rgbToManyAXIS_tdata_sig[27]_i_8_n_0\,
      O => \rgbToManyAXIS_tdata_sig_reg[27]_i_4_n_0\,
      S => \rgbToManyAXIS_tdata_sig_reg[28]\(1)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64__xdcDup__2\ is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    D : out STD_LOGIC_VECTOR ( 15 downto 0 );
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC;
    enEobuf : in STD_LOGIC;
    oddNotEven : in STD_LOGIC;
    enEobufB : in STD_LOGIC;
    \drdEvenbufBm1_reg[63]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \drdEvenbufBm1_reg[63]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64__xdcDup__2\ : entity is "Dpbram_size6kB_a64b64";
end \design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64__xdcDup__2\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64__xdcDup__2\ is
  signal \^doutb\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal enA6_out : STD_LOGIC;
  signal enB : STD_LOGIC;
  signal NLW_myMnfcore_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size6kB_a64b64,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \myMnfcore_i_1__11\ : label is "soft_lutpair2912";
  attribute SOFT_HLUTNM of \myMnfcore_i_2__3\ : label is "soft_lutpair2912";
begin
  doutb(63 downto 0) <= \^doutb\(63 downto 0);
\drdEvenbufBm1[48]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(48),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(0),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(0)
    );
\drdEvenbufBm1[49]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(49),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(1),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(1)
    );
\drdEvenbufBm1[50]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(50),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(2),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(2)
    );
\drdEvenbufBm1[51]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(51),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(3),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(3)
    );
\drdEvenbufBm1[52]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(52),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(4),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(4)
    );
\drdEvenbufBm1[53]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(53),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(5),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(5)
    );
\drdEvenbufBm1[54]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(54),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(6),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(6)
    );
\drdEvenbufBm1[55]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(55),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(7),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(7)
    );
\drdEvenbufBm1[56]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(56),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(8),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(8)
    );
\drdEvenbufBm1[57]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(57),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(9),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(9)
    );
\drdEvenbufBm1[58]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(58),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(10),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(10)
    );
\drdEvenbufBm1[59]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(59),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(11),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(11)
    );
\drdEvenbufBm1[60]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(60),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(12),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(12)
    );
\drdEvenbufBm1[61]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(61),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(13),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(13)
    );
\drdEvenbufBm1[62]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(62),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(14),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(14)
    );
\drdEvenbufBm1[63]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => \^doutb\(63),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I2 => \drdEvenbufBm1_reg[63]\(15),
      I3 => \drdEvenbufBm1_reg[63]_0\(1),
      I4 => \drdEvenbufBm1_reg[63]_0\(0),
      O => D(15)
    );
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size6kB_a64b64__4\
     port map (
      addra(9 downto 0) => Q(9 downto 0),
      addrb(9 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(9 downto 0),
      clka => aclk_sig,
      clkb => '0',
      dina(63 downto 0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_myMnfcore_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => \^doutb\(63 downto 0),
      ena => enA6_out,
      enb => enB,
      wea(0) => '1',
      web(0) => '0'
    );
\myMnfcore_i_1__11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      I1 => enEobuf,
      I2 => oddNotEven,
      O => enA6_out
    );
\myMnfcore_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => enEobufB,
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\,
      O => enB
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Dpbram_size8kB_a32b128 is
  port (
    douta : out STD_LOGIC_VECTOR ( 27 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 127 downto 0 );
    web : out STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : out STD_LOGIC_VECTOR ( 8 downto 0 );
    D : out STD_LOGIC_VECTOR ( 24 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
    memclk : in STD_LOGIC;
    ddrAXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    \dwrRowbuf_reg[9]\ : in STD_LOGIC;
    \dwrRowbuf_reg[9]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[9]_1\ : in STD_LOGIC;
    \dwrRowbuf_reg[9]_2\ : in STD_LOGIC;
    \dwrRowbuf_reg[9]_3\ : in STD_LOGIC;
    \dwrRowbuf_reg[10]\ : in STD_LOGIC;
    \dwrRowbuf_reg[10]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[11]\ : in STD_LOGIC;
    \dwrRowbuf_reg[11]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[12]\ : in STD_LOGIC;
    \dwrRowbuf_reg[12]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[13]\ : in STD_LOGIC;
    \dwrRowbuf_reg[13]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[14]\ : in STD_LOGIC;
    \dwrRowbuf_reg[14]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[15]\ : in STD_LOGIC;
    \dwrRowbuf_reg[31]\ : in STD_LOGIC_VECTOR ( 29 downto 0 );
    \dwrRowbuf_reg[8]\ : in STD_LOGIC;
    \dwrRowbuf_reg[8]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[2]\ : in STD_LOGIC;
    \dwrRowbuf_reg[2]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[2]_1\ : in STD_LOGIC;
    \dwrRowbuf_reg[16]\ : in STD_LOGIC;
    \dwrRowbuf_reg[16]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[16]_1\ : in STD_LOGIC;
    \dwrRowbuf_reg[17]\ : in STD_LOGIC;
    \dwrRowbuf_reg[17]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[18]\ : in STD_LOGIC;
    \dwrRowbuf_reg[18]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[19]\ : in STD_LOGIC;
    \dwrRowbuf_reg[19]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[20]\ : in STD_LOGIC;
    \dwrRowbuf_reg[20]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[21]\ : in STD_LOGIC;
    \dwrRowbuf_reg[21]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[22]\ : in STD_LOGIC;
    \dwrRowbuf_reg[22]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[23]\ : in STD_LOGIC;
    \dwrRowbuf_reg[25]\ : in STD_LOGIC;
    \dwrRowbuf_reg[24]\ : in STD_LOGIC;
    \dwrRowbuf_reg[25]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[26]\ : in STD_LOGIC;
    \dwrRowbuf_reg[27]\ : in STD_LOGIC;
    \dwrRowbuf_reg[27]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[27]_1\ : in STD_LOGIC;
    \dwrRowbuf_reg[28]\ : in STD_LOGIC;
    \dwrRowbuf_reg[28]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[29]\ : in STD_LOGIC;
    \dwrRowbuf_reg[29]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[30]\ : in STD_LOGIC;
    \dwrRowbuf_reg[30]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[31]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[9]_4\ : in STD_LOGIC;
    \dwrRowbuf_reg[24]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[24]_1\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_5\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_9\ : in STD_LOGIC;
    enRowbufBEgrstr : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_10\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_11\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    liveBNotA_memclk : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_13\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Dpbram_size8kB_a32b128 : entity is "Dpbram_size8kB_a32b128";
end design_1_Vsp_core_0_0_Dpbram_size8kB_a32b128;

architecture STRUCTURE of design_1_Vsp_core_0_0_Dpbram_size8kB_a32b128 is
  signal \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\ : STD_LOGIC;
  signal \^device_8series.no_bmm_info.true_dp.simple_prim36.ram_0\ : STD_LOGIC;
  signal \^device_8series.no_bmm_info.true_dp.simple_prim36.ram_2\ : STD_LOGIC;
  signal \^device_8series.no_bmm_info.true_dp.simple_prim36.ram_3\ : STD_LOGIC;
  signal \^addrb\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \^douta\ : STD_LOGIC_VECTOR ( 27 downto 0 );
  signal drdRowBbuf : STD_LOGIC_VECTOR ( 31 downto 15 );
  signal \dwrRowbuf[31]_i_10_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_11_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_12_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_13_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_14_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_15_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_16_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_17_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_6_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_7_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_8_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_9_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[4]_i_5_n_0\ : STD_LOGIC;
  signal enA : STD_LOGIC;
  signal enB : STD_LOGIC;
  signal myMnfcore_i_10_n_0 : STD_LOGIC;
  signal myMnfcore_i_11_n_0 : STD_LOGIC;
  signal myMnfcore_i_12_n_0 : STD_LOGIC;
  signal \myMnfcore_i_2__2_n_0\ : STD_LOGIC;
  signal \myMnfcore_i_3__0_n_0\ : STD_LOGIC;
  signal \myMnfcore_i_4__0_n_0\ : STD_LOGIC;
  signal \myMnfcore_i_5__0_n_0\ : STD_LOGIC;
  signal \myMnfcore_i_6__0_n_0\ : STD_LOGIC;
  signal \myMnfcore_i_7__0_n_0\ : STD_LOGIC;
  signal myMnfcore_i_8_n_0 : STD_LOGIC;
  signal myMnfcore_i_9_n_0 : STD_LOGIC;
  signal \^web\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size8kB_a32b128,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of myMnfcore_i_10 : label is "soft_lutpair1710";
  attribute SOFT_HLUTNM of myMnfcore_i_11 : label is "soft_lutpair1710";
  attribute SOFT_HLUTNM of \myMnfcore_i_2__2\ : label is "soft_lutpair1706";
  attribute SOFT_HLUTNM of \myMnfcore_i_3__0\ : label is "soft_lutpair1706";
  attribute SOFT_HLUTNM of \myMnfcore_i_4__0\ : label is "soft_lutpair1707";
  attribute SOFT_HLUTNM of \myMnfcore_i_5__0\ : label is "soft_lutpair1707";
  attribute SOFT_HLUTNM of \myMnfcore_i_6__0\ : label is "soft_lutpair1708";
  attribute SOFT_HLUTNM of \myMnfcore_i_7__0\ : label is "soft_lutpair1708";
  attribute SOFT_HLUTNM of myMnfcore_i_8 : label is "soft_lutpair1709";
  attribute SOFT_HLUTNM of myMnfcore_i_9 : label is "soft_lutpair1709";
begin
  \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ <= \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\;
  \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ <= \^device_8series.no_bmm_info.true_dp.simple_prim36.ram_0\;
  \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ <= \^device_8series.no_bmm_info.true_dp.simple_prim36.ram_2\;
  \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ <= \^device_8series.no_bmm_info.true_dp.simple_prim36.ram_3\;
  addrb(8 downto 0) <= \^addrb\(8 downto 0);
  douta(27 downto 0) <= \^douta\(27 downto 0);
  web(0) <= \^web\(0);
\dwrRowbuf[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[9]_1\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[10]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[10]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(3)
    );
\dwrRowbuf[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[10]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[11]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[11]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(4)
    );
\dwrRowbuf[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[11]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[12]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[12]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(5)
    );
\dwrRowbuf[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[12]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[13]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[13]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(6)
    );
\dwrRowbuf[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[13]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[14]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[14]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(7)
    );
\dwrRowbuf[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[15]\,
      I1 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I2 => drdRowBbuf(15),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I4 => \dwrRowbuf_reg[31]\(14),
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(8)
    );
\dwrRowbuf[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF27002700000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[9]_0\,
      I1 => \dwrRowbuf_reg[16]\,
      I2 => \dwrRowbuf_reg[16]_0\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[16]_1\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(9)
    );
\dwrRowbuf[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFD100D100000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[16]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[17]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[17]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(10)
    );
\dwrRowbuf[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[17]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[18]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[18]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(11)
    );
\dwrRowbuf[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[18]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[19]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[19]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(12)
    );
\dwrRowbuf[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[19]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[20]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[20]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(13)
    );
\dwrRowbuf[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[20]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[21]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[21]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(14)
    );
\dwrRowbuf[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[21]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[22]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[22]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(15)
    );
\dwrRowbuf[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[23]\,
      I1 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I2 => drdRowBbuf(23),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I4 => \dwrRowbuf_reg[31]\(21),
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(16)
    );
\dwrRowbuf[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"888AAA8A00022202"
    )
        port map (
      I0 => \dwrRowbuf_reg[9]_3\,
      I1 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I2 => \dwrRowbuf_reg[24]_0\,
      I3 => \dwrRowbuf_reg[9]_0\,
      I4 => \dwrRowbuf_reg[24]\,
      I5 => \dwrRowbuf_reg[24]_1\,
      O => D(17)
    );
\dwrRowbuf[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF27002700000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[9]_0\,
      I1 => \dwrRowbuf_reg[25]\,
      I2 => \dwrRowbuf_reg[24]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[25]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(18)
    );
\dwrRowbuf[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[26]\,
      I1 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I2 => drdRowBbuf(26),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I4 => \dwrRowbuf_reg[31]\(24),
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(19)
    );
\dwrRowbuf[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[27]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[27]_0\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[27]_1\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(20)
    );
\dwrRowbuf[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[27]_0\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[28]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[28]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(21)
    );
\dwrRowbuf[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[28]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[29]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[29]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(22)
    );
\dwrRowbuf[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF96009600000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[2]\,
      I1 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram_0\,
      I2 => \dwrRowbuf_reg[2]_0\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[2]_1\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(0)
    );
\dwrRowbuf[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8A80202A"
    )
        port map (
      I0 => \dwrRowbuf_reg[9]_4\,
      I1 => \dwrRowbuf_reg[31]\(2),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I3 => \^douta\(2),
      I4 => \dwrRowbuf[4]_i_5_n_0\,
      O => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram_0\
    );
\dwrRowbuf[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[29]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[30]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[30]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(23)
    );
\dwrRowbuf[31]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000054040000"
    )
        port map (
      I0 => \dwrRowbuf[31]_i_15_n_0\,
      I1 => \^douta\(15),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I3 => \dwrRowbuf_reg[31]\(15),
      I4 => \dwrRowbuf_reg[17]_0\,
      I5 => \dwrRowbuf[31]_i_16_n_0\,
      O => \dwrRowbuf[31]_i_10_n_0\
    );
\dwrRowbuf[31]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"335FFF5F"
    )
        port map (
      I0 => \^douta\(13),
      I1 => \dwrRowbuf_reg[31]\(12),
      I2 => \^douta\(8),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I4 => \dwrRowbuf_reg[31]\(7),
      O => \dwrRowbuf[31]_i_11_n_0\
    );
\dwrRowbuf[31]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"335FFF5F"
    )
        port map (
      I0 => drdRowBbuf(15),
      I1 => \dwrRowbuf_reg[31]\(14),
      I2 => \^douta\(12),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I4 => \dwrRowbuf_reg[31]\(11),
      O => \dwrRowbuf[31]_i_12_n_0\
    );
\dwrRowbuf[31]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"335FFF5F"
    )
        port map (
      I0 => \^douta\(22),
      I1 => \dwrRowbuf_reg[31]\(22),
      I2 => \^douta\(26),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I4 => \dwrRowbuf_reg[31]\(27),
      O => \dwrRowbuf[31]_i_13_n_0\
    );
\dwrRowbuf[31]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"335FFF5F"
    )
        port map (
      I0 => drdRowBbuf(31),
      I1 => \dwrRowbuf_reg[31]\(29),
      I2 => \^douta\(24),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I4 => \dwrRowbuf_reg[31]\(25),
      O => \dwrRowbuf[31]_i_14_n_0\
    );
\dwrRowbuf[31]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"335FFF5F"
    )
        port map (
      I0 => \^douta\(18),
      I1 => \dwrRowbuf_reg[31]\(17),
      I2 => \^douta\(17),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I4 => \dwrRowbuf_reg[31]\(16),
      O => \dwrRowbuf[31]_i_15_n_0\
    );
\dwrRowbuf[31]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF47CF77FF"
    )
        port map (
      I0 => \dwrRowbuf_reg[31]\(21),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => drdRowBbuf(23),
      I3 => \dwrRowbuf_reg[31]\(20),
      I4 => \^douta\(21),
      I5 => \dwrRowbuf[31]_i_17_n_0\,
      O => \dwrRowbuf[31]_i_16_n_0\
    );
\dwrRowbuf[31]_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"335FFF5F"
    )
        port map (
      I0 => \^douta\(19),
      I1 => \dwrRowbuf_reg[31]\(18),
      I2 => \^douta\(20),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I4 => \dwrRowbuf_reg[31]\(19),
      O => \dwrRowbuf[31]_i_17_n_0\
    );
\dwrRowbuf[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[31]_0\,
      I1 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I2 => drdRowBbuf(31),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I4 => \dwrRowbuf_reg[31]\(29),
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(24)
    );
\dwrRowbuf[31]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DD0D0000"
    )
        port map (
      I0 => \dwrRowbuf[31]_i_6_n_0\,
      I1 => \dwrRowbuf[31]_i_7_n_0\,
      I2 => \dwrRowbuf[31]_i_8_n_0\,
      I3 => \dwrRowbuf[31]_i_9_n_0\,
      I4 => \dwrRowbuf_reg[9]_4\,
      I5 => \dwrRowbuf[31]_i_10_n_0\,
      O => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\
    );
\dwrRowbuf[31]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000B8308800"
    )
        port map (
      I0 => \dwrRowbuf_reg[31]\(8),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \^douta\(9),
      I3 => \dwrRowbuf_reg[31]\(13),
      I4 => \^douta\(14),
      I5 => \dwrRowbuf[31]_i_11_n_0\,
      O => \dwrRowbuf[31]_i_6_n_0\
    );
\dwrRowbuf[31]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF47CF77FF"
    )
        port map (
      I0 => \dwrRowbuf_reg[31]\(9),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \^douta\(10),
      I3 => \dwrRowbuf_reg[31]\(10),
      I4 => \^douta\(11),
      I5 => \dwrRowbuf[31]_i_12_n_0\,
      O => \dwrRowbuf[31]_i_7_n_0\
    );
\dwrRowbuf[31]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000B8308800"
    )
        port map (
      I0 => \dwrRowbuf_reg[31]\(26),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \^douta\(25),
      I3 => \dwrRowbuf_reg[31]\(23),
      I4 => \^douta\(23),
      I5 => \dwrRowbuf[31]_i_13_n_0\,
      O => \dwrRowbuf[31]_i_8_n_0\
    );
\dwrRowbuf[31]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF47CF77FF"
    )
        port map (
      I0 => \dwrRowbuf_reg[31]\(28),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \^douta\(27),
      I3 => \dwrRowbuf_reg[31]\(24),
      I4 => drdRowBbuf(26),
      I5 => \dwrRowbuf[31]_i_14_n_0\,
      O => \dwrRowbuf[31]_i_9_n_0\
    );
\dwrRowbuf[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444500000005000"
    )
        port map (
      I0 => \dwrRowbuf[4]_i_5_n_0\,
      I1 => \dwrRowbuf_reg[31]\(2),
      I2 => \^douta\(2),
      I3 => \^douta\(3),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I5 => \dwrRowbuf_reg[31]\(3),
      O => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram_3\
    );
\dwrRowbuf[4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00053305"
    )
        port map (
      I0 => \^douta\(1),
      I1 => \dwrRowbuf_reg[31]\(1),
      I2 => \^douta\(0),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I4 => \dwrRowbuf_reg[31]\(0),
      O => \dwrRowbuf[4]_i_5_n_0\
    );
\dwrRowbuf[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A0C0000000C000"
    )
        port map (
      I0 => \dwrRowbuf_reg[31]\(4),
      I1 => \^douta\(4),
      I2 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram_3\,
      I3 => \^douta\(5),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I5 => \dwrRowbuf_reg[31]\(5),
      O => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram_2\
    );
\dwrRowbuf[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"202A8A80"
    )
        port map (
      I0 => \dwrRowbuf_reg[9]_4\,
      I1 => \dwrRowbuf_reg[31]\(6),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I3 => \^douta\(6),
      I4 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram_2\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\
    );
\dwrRowbuf[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[8]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[9]\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[8]_0\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(1)
    );
\dwrRowbuf[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[9]\,
      I1 => \dwrRowbuf_reg[9]_0\,
      I2 => \dwrRowbuf_reg[9]_1\,
      I3 => \^device_8series.no_bmm_info.true_dp.simple_prim36.ram\,
      I4 => \dwrRowbuf_reg[9]_2\,
      I5 => \dwrRowbuf_reg[9]_3\,
      O => D(2)
    );
myMnfcore: entity work.\design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128__2\
     port map (
      addra(10) => \myMnfcore_i_2__2_n_0\,
      addra(9) => \myMnfcore_i_3__0_n_0\,
      addra(8) => \myMnfcore_i_4__0_n_0\,
      addra(7) => \myMnfcore_i_5__0_n_0\,
      addra(6) => \myMnfcore_i_6__0_n_0\,
      addra(5) => \myMnfcore_i_7__0_n_0\,
      addra(4) => myMnfcore_i_8_n_0,
      addra(3) => myMnfcore_i_9_n_0,
      addra(2) => myMnfcore_i_10_n_0,
      addra(1) => myMnfcore_i_11_n_0,
      addra(0) => myMnfcore_i_12_n_0,
      addrb(8 downto 0) => \^addrb\(8 downto 0),
      clka => aclk_sig,
      clkb => memclk,
      dina(31 downto 0) => Q(31 downto 0),
      dinb(127 downto 0) => ddrAXI_rdata(127 downto 0),
      douta(31) => drdRowBbuf(31),
      douta(30 downto 27) => \^douta\(27 downto 24),
      douta(26) => drdRowBbuf(26),
      douta(25 downto 24) => \^douta\(23 downto 22),
      douta(23) => drdRowBbuf(23),
      douta(22 downto 16) => \^douta\(21 downto 15),
      douta(15) => drdRowBbuf(15),
      douta(14 downto 0) => \^douta\(14 downto 0),
      doutb(127 downto 0) => doutb(127 downto 0),
      ena => enA,
      enb => enB,
      wea(0) => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      web(0) => \^web\(0)
    );
myMnfcore_i_10: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\(2),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\(2),
      O => myMnfcore_i_10_n_0
    );
myMnfcore_i_11: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\(1),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\(1),
      O => myMnfcore_i_11_n_0
    );
myMnfcore_i_12: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\(0),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\(0),
      O => myMnfcore_i_12_n_0
    );
\myMnfcore_i_13__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000088F88888"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_9\,
      I1 => enRowbufBEgrstr,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_10\,
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_11\(0),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_11\(1),
      I5 => liveBNotA_memclk,
      O => enB
    );
myMnfcore_i_15: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(3),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(1),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(2),
      O => \^web\(0)
    );
myMnfcore_i_16: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAC0CC00"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(8),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_13\(8),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(0),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(2),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(1),
      I5 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(3),
      O => \^addrb\(8)
    );
myMnfcore_i_17: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAC0CC00"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(7),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_13\(7),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(0),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(2),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(1),
      I5 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(3),
      O => \^addrb\(7)
    );
myMnfcore_i_18: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAC0CC00"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(6),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_13\(6),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(0),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(2),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(1),
      I5 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(3),
      O => \^addrb\(6)
    );
myMnfcore_i_19: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAC0CC00"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(5),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_13\(5),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(0),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(2),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(1),
      I5 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(3),
      O => \^addrb\(5)
    );
\myMnfcore_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8BB8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_5\,
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_6\(0),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_6\(1),
      O => enA
    );
myMnfcore_i_20: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAC0CC00"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(4),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_13\(4),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(0),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(2),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(1),
      I5 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(3),
      O => \^addrb\(4)
    );
myMnfcore_i_21: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAC0CC00"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(3),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_13\(3),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(0),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(2),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(1),
      I5 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(3),
      O => \^addrb\(3)
    );
myMnfcore_i_22: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAC0CC00"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(2),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_13\(2),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(0),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(2),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(1),
      I5 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(3),
      O => \^addrb\(2)
    );
myMnfcore_i_23: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAC0CC00"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(1),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_13\(1),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(0),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(2),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(1),
      I5 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(3),
      O => \^addrb\(1)
    );
myMnfcore_i_24: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAC0CC00"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(0),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_13\(0),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(0),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(2),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(1),
      I5 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(3),
      O => \^addrb\(0)
    );
\myMnfcore_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\(10),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\(10),
      O => \myMnfcore_i_2__2_n_0\
    );
\myMnfcore_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\(9),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\(9),
      O => \myMnfcore_i_3__0_n_0\
    );
\myMnfcore_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\(8),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\(8),
      O => \myMnfcore_i_4__0_n_0\
    );
\myMnfcore_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\(7),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\(7),
      O => \myMnfcore_i_5__0_n_0\
    );
\myMnfcore_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\(6),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\(6),
      O => \myMnfcore_i_6__0_n_0\
    );
\myMnfcore_i_7__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\(5),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\(5),
      O => \myMnfcore_i_7__0_n_0\
    );
myMnfcore_i_8: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\(4),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\(4),
      O => myMnfcore_i_8_n_0
    );
myMnfcore_i_9: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\(3),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\(3),
      O => myMnfcore_i_9_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_Vsp_core_0_0_Dpbram_size8kB_a32b128__xdcDup__1\ is
  port (
    douta : out STD_LOGIC_VECTOR ( 29 downto 0 );
    D : out STD_LOGIC_VECTOR ( 6 downto 0 );
    \stateSwap_reg[0]\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_5\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_6\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_9\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_10\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_11\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_13\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_15\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_16\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_17\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_18\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_19\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_20\ : out STD_LOGIC;
    \stateSwap_reg[2]\ : out STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\ : out STD_LOGIC_VECTOR ( 127 downto 0 );
    aclk_sig : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
    memclk : in STD_LOGIC;
    web : in STD_LOGIC_VECTOR ( 0 to 0 );
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    ddrAXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    \dwrRowbuf_reg[1]\ : in STD_LOGIC;
    \dwrRowbuf_reg[1]_0\ : in STD_LOGIC;
    \dwrRowbuf_reg[1]_1\ : in STD_LOGIC;
    \dwrRowbuf_reg[0]\ : in STD_LOGIC;
    \dwrRowbuf_reg[4]\ : in STD_LOGIC;
    \dwrRowbuf_reg[6]\ : in STD_LOGIC;
    \dwrRowbuf_reg[0]_0\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_22\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\ : in STD_LOGIC;
    \dwrRowbuf_reg[7]\ : in STD_LOGIC;
    \dwrRowbuf_reg[30]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
    \dwrRowbuf_reg[3]\ : in STD_LOGIC;
    \dwrRowbuf_reg[3]_0\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_24\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_25\ : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_26\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_27\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    enRowbufBEgrstr : in STD_LOGIC;
    \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_28\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    liveBNotA_memclk : in STD_LOGIC;
    \egrfifo_reg[0][0]\ : in STD_LOGIC;
    doutb : in STD_LOGIC_VECTOR ( 127 downto 0 );
    \egrfifo_reg[0][0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_Vsp_core_0_0_Dpbram_size8kB_a32b128__xdcDup__1\ : entity is "Dpbram_size8kB_a32b128";
end \design_1_Vsp_core_0_0_Dpbram_size8kB_a32b128__xdcDup__1\;

architecture STRUCTURE of \design_1_Vsp_core_0_0_Dpbram_size8kB_a32b128__xdcDup__1\ is
  signal aA : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \^douta\ : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal drdA : STD_LOGIC_VECTOR ( 17 downto 7 );
  signal drdB : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal \dwrRowbuf[0]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[1]_i_3_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[1]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[1]_i_5_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[3]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[3]_i_3_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[3]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[4]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[4]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[5]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[5]_i_3_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[5]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[6]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[7]_i_3_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[7]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[7]_i_5_n_0\ : STD_LOGIC;
  signal enA2 : STD_LOGIC;
  signal enA8_out : STD_LOGIC;
  signal enB19_out : STD_LOGIC;
  signal \^stateswap_reg[0]\ : STD_LOGIC;
  signal \^stateswap_reg[2]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \dwrRowbuf[0]_i_2\ : label is "soft_lutpair1684";
  attribute SOFT_HLUTNM of \dwrRowbuf[10]_i_3\ : label is "soft_lutpair1691";
  attribute SOFT_HLUTNM of \dwrRowbuf[11]_i_3\ : label is "soft_lutpair1691";
  attribute SOFT_HLUTNM of \dwrRowbuf[12]_i_3\ : label is "soft_lutpair1690";
  attribute SOFT_HLUTNM of \dwrRowbuf[13]_i_3\ : label is "soft_lutpair1692";
  attribute SOFT_HLUTNM of \dwrRowbuf[14]_i_4\ : label is "soft_lutpair1693";
  attribute SOFT_HLUTNM of \dwrRowbuf[16]_i_3\ : label is "soft_lutpair1690";
  attribute SOFT_HLUTNM of \dwrRowbuf[17]_i_3\ : label is "soft_lutpair1689";
  attribute SOFT_HLUTNM of \dwrRowbuf[18]_i_3\ : label is "soft_lutpair1688";
  attribute SOFT_HLUTNM of \dwrRowbuf[19]_i_3\ : label is "soft_lutpair1689";
  attribute SOFT_HLUTNM of \dwrRowbuf[1]_i_4\ : label is "soft_lutpair1684";
  attribute SOFT_HLUTNM of \dwrRowbuf[1]_i_5\ : label is "soft_lutpair1699";
  attribute SOFT_HLUTNM of \dwrRowbuf[20]_i_3\ : label is "soft_lutpair1687";
  attribute SOFT_HLUTNM of \dwrRowbuf[21]_i_3\ : label is "soft_lutpair1687";
  attribute SOFT_HLUTNM of \dwrRowbuf[22]_i_4\ : label is "soft_lutpair1688";
  attribute SOFT_HLUTNM of \dwrRowbuf[24]_i_3\ : label is "soft_lutpair1695";
  attribute SOFT_HLUTNM of \dwrRowbuf[25]_i_4\ : label is "soft_lutpair1696";
  attribute SOFT_HLUTNM of \dwrRowbuf[27]_i_3\ : label is "soft_lutpair1694";
  attribute SOFT_HLUTNM of \dwrRowbuf[28]_i_3\ : label is "soft_lutpair1696";
  attribute SOFT_HLUTNM of \dwrRowbuf[29]_i_3\ : label is "soft_lutpair1695";
  attribute SOFT_HLUTNM of \dwrRowbuf[2]_i_5\ : label is "soft_lutpair1700";
  attribute SOFT_HLUTNM of \dwrRowbuf[30]_i_5\ : label is "soft_lutpair1694";
  attribute SOFT_HLUTNM of \dwrRowbuf[3]_i_2\ : label is "soft_lutpair1699";
  attribute SOFT_HLUTNM of \dwrRowbuf[4]_i_2\ : label is "soft_lutpair1698";
  attribute SOFT_HLUTNM of \dwrRowbuf[5]_i_2\ : label is "soft_lutpair1698";
  attribute SOFT_HLUTNM of \dwrRowbuf[6]_i_2\ : label is "soft_lutpair1697";
  attribute SOFT_HLUTNM of \dwrRowbuf[7]_i_5\ : label is "soft_lutpair1697";
  attribute SOFT_HLUTNM of \dwrRowbuf[8]_i_3\ : label is "soft_lutpair1692";
  attribute SOFT_HLUTNM of \dwrRowbuf[9]_i_3\ : label is "soft_lutpair1693";
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMnfcore : label is "Dpbram_xlnx_size8kB_a32b128,blk_mem_gen_v8_4_9,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMnfcore : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMnfcore : label is "blk_mem_gen_v8_4_9,Vivado 2024.2";
  attribute SOFT_HLUTNM of \myMnfcore_i_10__0\ : label is "soft_lutpair1704";
  attribute SOFT_HLUTNM of \myMnfcore_i_11__0\ : label is "soft_lutpair1704";
  attribute SOFT_HLUTNM of \myMnfcore_i_12__0\ : label is "soft_lutpair1705";
  attribute SOFT_HLUTNM of myMnfcore_i_13 : label is "soft_lutpair1705";
  attribute SOFT_HLUTNM of \myMnfcore_i_1__4\ : label is "soft_lutpair1686";
  attribute SOFT_HLUTNM of myMnfcore_i_25 : label is "soft_lutpair1685";
  attribute SOFT_HLUTNM of myMnfcore_i_26 : label is "soft_lutpair1685";
  attribute SOFT_HLUTNM of \myMnfcore_i_2__1\ : label is "soft_lutpair1686";
  attribute SOFT_HLUTNM of \myMnfcore_i_3__1\ : label is "soft_lutpair1700";
  attribute SOFT_HLUTNM of \myMnfcore_i_4__1\ : label is "soft_lutpair1701";
  attribute SOFT_HLUTNM of \myMnfcore_i_5__1\ : label is "soft_lutpair1701";
  attribute SOFT_HLUTNM of \myMnfcore_i_6__1\ : label is "soft_lutpair1702";
  attribute SOFT_HLUTNM of \myMnfcore_i_7__1\ : label is "soft_lutpair1702";
  attribute SOFT_HLUTNM of \myMnfcore_i_8__0\ : label is "soft_lutpair1703";
  attribute SOFT_HLUTNM of \myMnfcore_i_9__0\ : label is "soft_lutpair1703";
begin
  douta(29 downto 0) <= \^douta\(29 downto 0);
  \stateSwap_reg[0]\ <= \^stateswap_reg[0]\;
  \stateSwap_reg[2]\ <= \^stateswap_reg[2]\;
\dwrRowbuf[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAB40000"
    )
        port map (
      I0 => \dwrRowbuf[0]_i_2_n_0\,
      I1 => \dwrRowbuf_reg[0]\,
      I2 => \dwrRowbuf_reg[0]_0\,
      I3 => \dwrRowbuf_reg[1]_0\,
      I4 => \dwrRowbuf_reg[1]_1\,
      O => D(0)
    );
\dwrRowbuf[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(0),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(0),
      O => \dwrRowbuf[0]_i_2_n_0\
    );
\dwrRowbuf[10]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(9),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(10),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\
    );
\dwrRowbuf[11]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(10),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(11),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_9\
    );
\dwrRowbuf[12]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(11),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(12),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\
    );
\dwrRowbuf[13]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(12),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(13),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_11\
    );
\dwrRowbuf[14]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(13),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(14),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_13\
    );
\dwrRowbuf[16]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(15),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(15),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_6\
    );
\dwrRowbuf[17]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdA(17),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(16),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_5\
    );
\dwrRowbuf[18]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(16),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(17),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\
    );
\dwrRowbuf[19]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(17),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(18),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\
    );
\dwrRowbuf[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF69006900000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[1]\,
      I1 => \dwrRowbuf[1]_i_3_n_0\,
      I2 => \dwrRowbuf[1]_i_4_n_0\,
      I3 => \dwrRowbuf_reg[1]_0\,
      I4 => \dwrRowbuf[1]_i_5_n_0\,
      I5 => \dwrRowbuf_reg[1]_1\,
      O => D(1)
    );
\dwrRowbuf[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A802A20808A202A"
    )
        port map (
      I0 => \dwrRowbuf_reg[0]\,
      I1 => \^douta\(0),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I3 => \dwrRowbuf_reg[30]\(0),
      I4 => \^douta\(1),
      I5 => \dwrRowbuf_reg[30]\(1),
      O => \dwrRowbuf[1]_i_3_n_0\
    );
\dwrRowbuf[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08000888"
    )
        port map (
      I0 => \dwrRowbuf_reg[0]_0\,
      I1 => \dwrRowbuf_reg[0]\,
      I2 => \^douta\(0),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I4 => \dwrRowbuf_reg[30]\(0),
      O => \dwrRowbuf[1]_i_4_n_0\
    );
\dwrRowbuf[1]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(1),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(1),
      O => \dwrRowbuf[1]_i_5_n_0\
    );
\dwrRowbuf[20]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(18),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(19),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\
    );
\dwrRowbuf[21]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(19),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(20),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\
    );
\dwrRowbuf[22]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(20),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(21),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\
    );
\dwrRowbuf[24]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(22),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(22),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_17\
    );
\dwrRowbuf[25]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(23),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(23),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_19\
    );
\dwrRowbuf[27]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(25),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(24),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\
    );
\dwrRowbuf[28]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(26),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(25),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_18\
    );
\dwrRowbuf[29]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(27),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(26),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_16\
    );
\dwrRowbuf[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBF37BB"
    )
        port map (
      I0 => \dwrRowbuf[0]_i_2_n_0\,
      I1 => \dwrRowbuf_reg[0]\,
      I2 => \dwrRowbuf_reg[0]_0\,
      I3 => \dwrRowbuf[1]_i_5_n_0\,
      I4 => \dwrRowbuf_reg[1]\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\
    );
\dwrRowbuf[2]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(2),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(2),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_20\
    );
\dwrRowbuf[30]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(28),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(27),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_15\
    );
\dwrRowbuf[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCD72800000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[0]\,
      I1 => \dwrRowbuf[3]_i_2_n_0\,
      I2 => \dwrRowbuf[3]_i_3_n_0\,
      I3 => \dwrRowbuf[3]_i_4_n_0\,
      I4 => \dwrRowbuf_reg[1]_0\,
      I5 => \dwrRowbuf_reg[1]_1\,
      O => D(2)
    );
\dwrRowbuf[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(3),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(3),
      O => \dwrRowbuf[3]_i_2_n_0\
    );
\dwrRowbuf[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCC0AAAACCC0A0A0"
    )
        port map (
      I0 => \dwrRowbuf_reg[30]\(2),
      I1 => \^douta\(2),
      I2 => \dwrRowbuf[0]_i_2_n_0\,
      I3 => \^douta\(1),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I5 => \dwrRowbuf_reg[30]\(1),
      O => \dwrRowbuf[3]_i_3_n_0\
    );
\dwrRowbuf[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F00FF0F2F002F00"
    )
        port map (
      I0 => \dwrRowbuf[1]_i_3_n_0\,
      I1 => \dwrRowbuf_reg[1]\,
      I2 => \dwrRowbuf_reg[3]\,
      I3 => \dwrRowbuf_reg[3]_0\,
      I4 => \dwrRowbuf[1]_i_5_n_0\,
      I5 => \dwrRowbuf[1]_i_4_n_0\,
      O => \dwrRowbuf[3]_i_4_n_0\
    );
\dwrRowbuf[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCD72800000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[0]\,
      I1 => \dwrRowbuf[4]_i_2_n_0\,
      I2 => \dwrRowbuf_reg[4]\,
      I3 => \dwrRowbuf[4]_i_4_n_0\,
      I4 => \dwrRowbuf_reg[1]_0\,
      I5 => \dwrRowbuf_reg[1]_1\,
      O => D(3)
    );
\dwrRowbuf[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(4),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(4),
      O => \dwrRowbuf[4]_i_2_n_0\
    );
\dwrRowbuf[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2228882800000000"
    )
        port map (
      I0 => \dwrRowbuf[3]_i_4_n_0\,
      I1 => \dwrRowbuf[3]_i_3_n_0\,
      I2 => \dwrRowbuf_reg[30]\(3),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I4 => \^douta\(3),
      I5 => \dwrRowbuf_reg[0]\,
      O => \dwrRowbuf[4]_i_4_n_0\
    );
\dwrRowbuf[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCD72800000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[0]\,
      I1 => \dwrRowbuf[5]_i_2_n_0\,
      I2 => \dwrRowbuf[5]_i_3_n_0\,
      I3 => \dwrRowbuf[5]_i_4_n_0\,
      I4 => \dwrRowbuf_reg[1]_0\,
      I5 => \dwrRowbuf_reg[1]_1\,
      O => D(4)
    );
\dwrRowbuf[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(5),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(5),
      O => \dwrRowbuf[5]_i_2_n_0\
    );
\dwrRowbuf[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A0C0000000C000"
    )
        port map (
      I0 => \^douta\(3),
      I1 => \dwrRowbuf_reg[30]\(3),
      I2 => \dwrRowbuf[3]_i_3_n_0\,
      I3 => \dwrRowbuf_reg[30]\(4),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I5 => \^douta\(4),
      O => \dwrRowbuf[5]_i_3_n_0\
    );
\dwrRowbuf[5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28000000"
    )
        port map (
      I0 => \dwrRowbuf[3]_i_4_n_0\,
      I1 => \dwrRowbuf[3]_i_2_n_0\,
      I2 => \dwrRowbuf[3]_i_3_n_0\,
      I3 => \dwrRowbuf[4]_i_2_n_0\,
      I4 => \dwrRowbuf_reg[0]\,
      O => \dwrRowbuf[5]_i_4_n_0\
    );
\dwrRowbuf[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCD72800000000"
    )
        port map (
      I0 => \dwrRowbuf_reg[0]\,
      I1 => \dwrRowbuf[6]_i_2_n_0\,
      I2 => \dwrRowbuf_reg[6]\,
      I3 => \dwrRowbuf[7]_i_3_n_0\,
      I4 => \dwrRowbuf_reg[1]_0\,
      I5 => \dwrRowbuf_reg[1]_1\,
      O => D(5)
    );
\dwrRowbuf[6]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(6),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(6),
      O => \dwrRowbuf[6]_i_2_n_0\
    );
\dwrRowbuf[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00780000007800"
    )
        port map (
      I0 => \dwrRowbuf_reg[7]\,
      I1 => \dwrRowbuf[7]_i_3_n_0\,
      I2 => \dwrRowbuf[7]_i_4_n_0\,
      I3 => \dwrRowbuf_reg[1]_1\,
      I4 => \dwrRowbuf_reg[1]_0\,
      I5 => \dwrRowbuf[7]_i_5_n_0\,
      O => D(6)
    );
\dwrRowbuf[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880000000000000"
    )
        port map (
      I0 => \dwrRowbuf[3]_i_4_n_0\,
      I1 => \dwrRowbuf[4]_i_2_n_0\,
      I2 => \dwrRowbuf[3]_i_3_n_0\,
      I3 => \dwrRowbuf[3]_i_2_n_0\,
      I4 => \dwrRowbuf[5]_i_2_n_0\,
      I5 => \dwrRowbuf_reg[0]\,
      O => \dwrRowbuf[7]_i_3_n_0\
    );
\dwrRowbuf[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"202A8A808A808A80"
    )
        port map (
      I0 => \dwrRowbuf_reg[0]\,
      I1 => drdA(7),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I3 => \dwrRowbuf_reg[30]\(7),
      I4 => \dwrRowbuf_reg[6]\,
      I5 => \dwrRowbuf[6]_i_2_n_0\,
      O => \dwrRowbuf[7]_i_4_n_0\
    );
\dwrRowbuf[7]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => drdA(7),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(7),
      O => \dwrRowbuf[7]_i_5_n_0\
    );
\dwrRowbuf[8]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(7),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(8),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_10\
    );
\dwrRowbuf[9]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^douta\(8),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \dwrRowbuf_reg[30]\(9),
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\
    );
\egrfifo[2][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(0),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(0),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(0)
    );
\egrfifo[2][100]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(100),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(100),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(100)
    );
\egrfifo[2][101]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(101),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(101),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(101)
    );
\egrfifo[2][102]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(102),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(102),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(102)
    );
\egrfifo[2][103]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(103),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(103),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(103)
    );
\egrfifo[2][104]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(104),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(104),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(104)
    );
\egrfifo[2][105]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(105),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(105),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(105)
    );
\egrfifo[2][106]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(106),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(106),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(106)
    );
\egrfifo[2][107]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(107),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(107),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(107)
    );
\egrfifo[2][108]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(108),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(108),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(108)
    );
\egrfifo[2][109]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(109),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(109),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(109)
    );
\egrfifo[2][10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(10),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(10),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(10)
    );
\egrfifo[2][110]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(110),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(110),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(110)
    );
\egrfifo[2][111]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(111),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(111),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(111)
    );
\egrfifo[2][112]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(112),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(112),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(112)
    );
\egrfifo[2][113]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(113),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(113),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(113)
    );
\egrfifo[2][114]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(114),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(114),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(114)
    );
\egrfifo[2][115]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(115),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(115),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(115)
    );
\egrfifo[2][116]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(116),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(116),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(116)
    );
\egrfifo[2][117]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(117),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(117),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(117)
    );
\egrfifo[2][118]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(118),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(118),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(118)
    );
\egrfifo[2][119]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(119),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(119),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(119)
    );
\egrfifo[2][11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(11),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(11),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(11)
    );
\egrfifo[2][120]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(120),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(120),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(120)
    );
\egrfifo[2][121]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(121),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(121),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(121)
    );
\egrfifo[2][122]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(122),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(122),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(122)
    );
\egrfifo[2][123]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(123),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(123),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(123)
    );
\egrfifo[2][124]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(124),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(124),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(124)
    );
\egrfifo[2][125]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(125),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(125),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(125)
    );
\egrfifo[2][126]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(126),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(126),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(126)
    );
\egrfifo[2][127]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(127),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(127),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(127)
    );
\egrfifo[2][12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(12),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(12),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(12)
    );
\egrfifo[2][13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(13),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(13),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(13)
    );
\egrfifo[2][14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(14),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(14),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(14)
    );
\egrfifo[2][15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(15),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(15),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(15)
    );
\egrfifo[2][16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(16),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(16),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(16)
    );
\egrfifo[2][17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(17),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(17),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(17)
    );
\egrfifo[2][18]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(18),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(18),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(18)
    );
\egrfifo[2][19]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(19),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(19),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(19)
    );
\egrfifo[2][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(1),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(1),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(1)
    );
\egrfifo[2][20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(20),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(20),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(20)
    );
\egrfifo[2][21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(21),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(21),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(21)
    );
\egrfifo[2][22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(22),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(22),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(22)
    );
\egrfifo[2][23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(23),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(23),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(23)
    );
\egrfifo[2][24]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(24),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(24),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(24)
    );
\egrfifo[2][25]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(25),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(25),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(25)
    );
\egrfifo[2][26]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(26),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(26),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(26)
    );
\egrfifo[2][27]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(27),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(27),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(27)
    );
\egrfifo[2][28]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(28),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(28),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(28)
    );
\egrfifo[2][29]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(29),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(29),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(29)
    );
\egrfifo[2][2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(2),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(2),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(2)
    );
\egrfifo[2][30]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(30),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(30),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(30)
    );
\egrfifo[2][31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(31),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(31),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(31)
    );
\egrfifo[2][32]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(32),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(32),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(32)
    );
\egrfifo[2][33]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(33),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(33),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(33)
    );
\egrfifo[2][34]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(34),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(34),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(34)
    );
\egrfifo[2][35]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(35),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(35),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(35)
    );
\egrfifo[2][36]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(36),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(36),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(36)
    );
\egrfifo[2][37]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(37),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(37),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(37)
    );
\egrfifo[2][38]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(38),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(38),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(38)
    );
\egrfifo[2][39]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(39),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(39),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(39)
    );
\egrfifo[2][3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(3),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(3),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(3)
    );
\egrfifo[2][40]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(40),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(40),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(40)
    );
\egrfifo[2][41]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(41),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(41),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(41)
    );
\egrfifo[2][42]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(42),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(42),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(42)
    );
\egrfifo[2][43]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(43),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(43),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(43)
    );
\egrfifo[2][44]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(44),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(44),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(44)
    );
\egrfifo[2][45]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(45),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(45),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(45)
    );
\egrfifo[2][46]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(46),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(46),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(46)
    );
\egrfifo[2][47]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(47),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(47),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(47)
    );
\egrfifo[2][48]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(48),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(48),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(48)
    );
\egrfifo[2][49]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(49),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(49),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(49)
    );
\egrfifo[2][4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(4),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(4),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(4)
    );
\egrfifo[2][50]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(50),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(50),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(50)
    );
\egrfifo[2][51]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(51),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(51),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(51)
    );
\egrfifo[2][52]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(52),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(52),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(52)
    );
\egrfifo[2][53]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(53),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(53),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(53)
    );
\egrfifo[2][54]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(54),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(54),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(54)
    );
\egrfifo[2][55]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(55),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(55),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(55)
    );
\egrfifo[2][56]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(56),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(56),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(56)
    );
\egrfifo[2][57]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(57),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(57),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(57)
    );
\egrfifo[2][58]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(58),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(58),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(58)
    );
\egrfifo[2][59]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(59),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(59),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(59)
    );
\egrfifo[2][5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(5),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(5),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(5)
    );
\egrfifo[2][60]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(60),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(60),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(60)
    );
\egrfifo[2][61]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(61),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(61),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(61)
    );
\egrfifo[2][62]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(62),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(62),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(62)
    );
\egrfifo[2][63]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(63),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(63),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(63)
    );
\egrfifo[2][64]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(64),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(64),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(64)
    );
\egrfifo[2][65]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(65),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(65),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(65)
    );
\egrfifo[2][66]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(66),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(66),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(66)
    );
\egrfifo[2][67]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(67),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(67),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(67)
    );
\egrfifo[2][68]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(68),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(68),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(68)
    );
\egrfifo[2][69]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(69),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(69),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(69)
    );
\egrfifo[2][6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(6),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(6),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(6)
    );
\egrfifo[2][70]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(70),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(70),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(70)
    );
\egrfifo[2][71]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(71),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(71),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(71)
    );
\egrfifo[2][72]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(72),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(72),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(72)
    );
\egrfifo[2][73]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(73),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(73),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(73)
    );
\egrfifo[2][74]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(74),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(74),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(74)
    );
\egrfifo[2][75]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(75),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(75),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(75)
    );
\egrfifo[2][76]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(76),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(76),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(76)
    );
\egrfifo[2][77]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(77),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(77),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(77)
    );
\egrfifo[2][78]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(78),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(78),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(78)
    );
\egrfifo[2][79]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(79),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(79),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(79)
    );
\egrfifo[2][7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(7),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(7),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(7)
    );
\egrfifo[2][80]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(80),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(80),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(80)
    );
\egrfifo[2][81]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(81),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(81),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(81)
    );
\egrfifo[2][82]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(82),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(82),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(82)
    );
\egrfifo[2][83]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(83),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(83),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(83)
    );
\egrfifo[2][84]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(84),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(84),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(84)
    );
\egrfifo[2][85]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(85),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(85),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(85)
    );
\egrfifo[2][86]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(86),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(86),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(86)
    );
\egrfifo[2][87]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(87),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(87),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(87)
    );
\egrfifo[2][88]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(88),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(88),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(88)
    );
\egrfifo[2][89]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(89),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(89),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(89)
    );
\egrfifo[2][8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(8),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(8),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(8)
    );
\egrfifo[2][90]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(90),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(90),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(90)
    );
\egrfifo[2][91]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(91),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(91),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(91)
    );
\egrfifo[2][92]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(92),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(92),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(92)
    );
\egrfifo[2][93]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(93),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(93),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(93)
    );
\egrfifo[2][94]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(94),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(94),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(94)
    );
\egrfifo[2][95]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(95),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(95),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(95)
    );
\egrfifo[2][96]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(96),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(96),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(96)
    );
\egrfifo[2][97]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(97),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(97),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(97)
    );
\egrfifo[2][98]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(98),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(98),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(98)
    );
\egrfifo[2][99]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(99),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(99),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(99)
    );
\egrfifo[2][9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => drdB(9),
      I1 => \egrfifo_reg[0][0]\,
      I2 => doutb(9),
      I3 => \egrfifo_reg[0][0]_0\,
      O => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(9)
    );
myMnfcore: entity work.design_1_Vsp_core_0_0_Dpbram_xlnx_size8kB_a32b128
     port map (
      addra(10 downto 0) => aA(10 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => aclk_sig,
      clkb => memclk,
      dina(31 downto 0) => Q(31 downto 0),
      dinb(127 downto 0) => ddrAXI_rdata(127 downto 0),
      douta(31 downto 18) => \^douta\(29 downto 16),
      douta(17) => drdA(17),
      douta(16 downto 8) => \^douta\(15 downto 7),
      douta(7) => drdA(7),
      douta(6 downto 0) => \^douta\(6 downto 0),
      doutb(127 downto 0) => drdB(127 downto 0),
      ena => enA8_out,
      enb => enB19_out,
      wea(0) => enA2,
      web(0) => web(0)
    );
\myMnfcore_i_10__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_26\(3),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_27\(3),
      O => aA(3)
    );
\myMnfcore_i_11__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_26\(2),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_27\(2),
      O => aA(2)
    );
\myMnfcore_i_12__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_26\(1),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_27\(1),
      O => aA(1)
    );
myMnfcore_i_13: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_26\(0),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_27\(0),
      O => aA(0)
    );
myMnfcore_i_14: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88F8888800000000"
    )
        port map (
      I0 => \^stateswap_reg[0]\,
      I1 => enRowbufBEgrstr,
      I2 => \^stateswap_reg[2]\,
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_28\(0),
      I4 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_28\(1),
      I5 => liveBNotA_memclk,
      O => enB19_out
    );
\myMnfcore_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6F60"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_24\(0),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_24\(1),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_25\,
      O => enA8_out
    );
myMnfcore_i_25: unisim.vcomponents.LUT4
    generic map(
      INIT => X"002C"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_22\(0),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_22\(2),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_22\(1),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_22\(3),
      O => \^stateswap_reg[0]\
    );
myMnfcore_i_26: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF9D"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_22\(2),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_22\(1),
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_22\(0),
      I3 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_22\(3),
      O => \^stateswap_reg[2]\
    );
\myMnfcore_i_2__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      O => enA2
    );
\myMnfcore_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_26\(10),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_27\(10),
      O => aA(10)
    );
\myMnfcore_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_26\(9),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_27\(9),
      O => aA(9)
    );
\myMnfcore_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_26\(8),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_27\(8),
      O => aA(8)
    );
\myMnfcore_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_26\(7),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_27\(7),
      O => aA(7)
    );
\myMnfcore_i_7__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_26\(6),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_27\(6),
      O => aA(6)
    );
\myMnfcore_i_8__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_26\(5),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_27\(5),
      O => aA(5)
    );
\myMnfcore_i_9__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_26\(4),
      I1 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\,
      I2 => \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_27\(4),
      O => aA(4)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_phy_0_c1 is
  port (
    rxbyteclkhs : out STD_LOGIC;
    dl0_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl0_rxvalidhs : out STD_LOGIC;
    dl0_rxactivehs : out STD_LOGIC;
    dl0_rxsynchs : out STD_LOGIC;
    dl0_stopstate : out STD_LOGIC;
    dl0_errsoths : out STD_LOGIC;
    dl0_errsotsynchs : out STD_LOGIC;
    dl1_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl1_rxvalidhs : out STD_LOGIC;
    dl1_rxactivehs : out STD_LOGIC;
    dl1_rxsynchs : out STD_LOGIC;
    dl1_stopstate : out STD_LOGIC;
    dl1_errsoths : out STD_LOGIC;
    dl1_errsotsynchs : out STD_LOGIC;
    dl2_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl2_rxvalidhs : out STD_LOGIC;
    dl2_rxactivehs : out STD_LOGIC;
    dl2_rxsynchs : out STD_LOGIC;
    dl2_stopstate : out STD_LOGIC;
    dl2_errsoths : out STD_LOGIC;
    dl2_errsotsynchs : out STD_LOGIC;
    dl3_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl3_rxvalidhs : out STD_LOGIC;
    dl3_rxactivehs : out STD_LOGIC;
    dl3_rxsynchs : out STD_LOGIC;
    dl3_stopstate : out STD_LOGIC;
    dl3_errsoths : out STD_LOGIC;
    dl3_errsotsynchs : out STD_LOGIC;
    cl_stopstate : out STD_LOGIC;
    s_axi_awready : out STD_LOGIC;
    s_axi_arready : out STD_LOGIC;
    s_axi_wready : out STD_LOGIC;
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rvalid : out STD_LOGIC;
    s_axi_bvalid : out STD_LOGIC;
    clk_rxp : in STD_LOGIC;
    clk_rxn : in STD_LOGIC;
    data_rxp : in STD_LOGIC_VECTOR ( 3 downto 0 );
    data_rxn : in STD_LOGIC_VECTOR ( 3 downto 0 );
    core_rst : in STD_LOGIC;
    core_clk : in STD_LOGIC;
    cl_enable : in STD_LOGIC;
    s_axi_aresetn : in STD_LOGIC;
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
    s_axi_awvalid : in STD_LOGIC;
    s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
    s_axi_arvalid : in STD_LOGIC;
    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_wvalid : in STD_LOGIC;
    s_axi_rready : in STD_LOGIC;
    s_axi_bready : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_phy_0_c1 : entity is "bd_7289_phy_0_c1";
end design_1_Vsp_core_0_0_bd_7289_phy_0_c1;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_phy_0_c1 is
begin
bd_7289_phy_0_rx_support_i: entity work.design_1_Vsp_core_0_0_bd_7289_phy_0_support
     port map (
      cl_enable => cl_enable,
      cl_stopstate => cl_stopstate,
      clk_rxn => clk_rxn,
      clk_rxp => clk_rxp,
      core_clk => core_clk,
      core_rst => core_rst,
      data_rxn(3 downto 0) => data_rxn(3 downto 0),
      data_rxp(3 downto 0) => data_rxp(3 downto 0),
      dl0_errsoths => dl0_errsoths,
      dl0_errsotsynchs => dl0_errsotsynchs,
      dl0_rxactivehs => dl0_rxactivehs,
      dl0_rxdatahs(7 downto 0) => dl0_rxdatahs(7 downto 0),
      dl0_rxsynchs => dl0_rxsynchs,
      dl0_rxvalidhs => dl0_rxvalidhs,
      dl0_stopstate => dl0_stopstate,
      dl1_errsoths => dl1_errsoths,
      dl1_errsotsynchs => dl1_errsotsynchs,
      dl1_rxactivehs => dl1_rxactivehs,
      dl1_rxdatahs(7 downto 0) => dl1_rxdatahs(7 downto 0),
      dl1_rxsynchs => dl1_rxsynchs,
      dl1_rxvalidhs => dl1_rxvalidhs,
      dl1_stopstate => dl1_stopstate,
      dl2_errsoths => dl2_errsoths,
      dl2_errsotsynchs => dl2_errsotsynchs,
      dl2_rxactivehs => dl2_rxactivehs,
      dl2_rxdatahs(7 downto 0) => dl2_rxdatahs(7 downto 0),
      dl2_rxsynchs => dl2_rxsynchs,
      dl2_rxvalidhs => dl2_rxvalidhs,
      dl2_stopstate => dl2_stopstate,
      dl3_errsoths => dl3_errsoths,
      dl3_errsotsynchs => dl3_errsotsynchs,
      dl3_rxactivehs => dl3_rxactivehs,
      dl3_rxdatahs(7 downto 0) => dl3_rxdatahs(7 downto 0),
      dl3_rxsynchs => dl3_rxsynchs,
      dl3_rxvalidhs => dl3_rxvalidhs,
      dl3_stopstate => dl3_stopstate,
      rxbyteclkhs => rxbyteclkhs,
      s_axi_araddr(4 downto 0) => s_axi_araddr(4 downto 0),
      s_axi_aresetn => s_axi_aresetn,
      s_axi_arready => s_axi_arready,
      s_axi_arvalid => s_axi_arvalid,
      s_axi_awaddr(4 downto 0) => s_axi_awaddr(4 downto 0),
      s_axi_awready => s_axi_awready,
      s_axi_awvalid => s_axi_awvalid,
      s_axi_bready => s_axi_bready,
      s_axi_bvalid => s_axi_bvalid,
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      s_axi_rready => s_axi_rready,
      s_axi_rvalid => s_axi_rvalid,
      s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
      s_axi_wready => s_axi_wready,
      s_axi_wvalid => s_axi_wvalid
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_rx_0 is
  port (
    core_clk : in STD_LOGIC;
    s_axi_aclk : in STD_LOGIC;
    s_axi_aresetn : in STD_LOGIC;
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_awvalid : in STD_LOGIC;
    s_axi_awready : out STD_LOGIC;
    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_wvalid : in STD_LOGIC;
    s_axi_wready : out STD_LOGIC;
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : out STD_LOGIC;
    s_axi_bready : in STD_LOGIC;
    s_axi_araddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_arvalid : in STD_LOGIC;
    s_axi_arready : out STD_LOGIC;
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rvalid : out STD_LOGIC;
    s_axi_rready : in STD_LOGIC;
    cl_stopstate : in STD_LOGIC;
    cl_enable : out STD_LOGIC;
    cl_rxulpsclknot : in STD_LOGIC;
    vfb_full : in STD_LOGIC;
    vfb_wc_full : in STD_LOGIC;
    core_men_ack_vfb : in STD_LOGIC;
    core_men_vfb : out STD_LOGIC;
    dl0_rxbyteclkhs : in STD_LOGIC;
    dl0_rxdatahs : in STD_LOGIC_VECTOR ( 7 downto 0 );
    dl0_rxvalidhs : in STD_LOGIC;
    dl0_rxactivehs : in STD_LOGIC;
    dl0_rxsynchs : in STD_LOGIC;
    dl0_stopstate : in STD_LOGIC;
    dl0_shutdown : out STD_LOGIC;
    dl0_rxulpmesc : in STD_LOGIC;
    dl0_errsoths : in STD_LOGIC;
    dl0_errsotsynchs : in STD_LOGIC;
    dl0_erresc : in STD_LOGIC;
    dl0_errcontrol : in STD_LOGIC;
    dl1_rxbyteclkhs : in STD_LOGIC;
    dl1_rxdatahs : in STD_LOGIC_VECTOR ( 7 downto 0 );
    dl1_rxvalidhs : in STD_LOGIC;
    dl1_rxactivehs : in STD_LOGIC;
    dl1_rxsynchs : in STD_LOGIC;
    dl1_stopstate : in STD_LOGIC;
    dl1_shutdown : out STD_LOGIC;
    dl1_rxulpmesc : in STD_LOGIC;
    dl1_errsoths : in STD_LOGIC;
    dl1_errsotsynchs : in STD_LOGIC;
    dl1_erresc : in STD_LOGIC;
    dl1_errcontrol : in STD_LOGIC;
    dl2_rxbyteclkhs : in STD_LOGIC;
    dl2_rxdatahs : in STD_LOGIC_VECTOR ( 7 downto 0 );
    dl2_rxvalidhs : in STD_LOGIC;
    dl2_rxactivehs : in STD_LOGIC;
    dl2_rxsynchs : in STD_LOGIC;
    dl2_stopstate : in STD_LOGIC;
    dl2_shutdown : out STD_LOGIC;
    dl2_rxulpmesc : in STD_LOGIC;
    dl2_errsoths : in STD_LOGIC;
    dl2_errsotsynchs : in STD_LOGIC;
    dl2_erresc : in STD_LOGIC;
    dl2_errcontrol : in STD_LOGIC;
    dl3_rxbyteclkhs : in STD_LOGIC;
    dl3_rxdatahs : in STD_LOGIC_VECTOR ( 7 downto 0 );
    dl3_rxvalidhs : in STD_LOGIC;
    dl3_rxactivehs : in STD_LOGIC;
    dl3_rxsynchs : in STD_LOGIC;
    dl3_stopstate : in STD_LOGIC;
    dl3_shutdown : out STD_LOGIC;
    dl3_rxulpmesc : in STD_LOGIC;
    dl3_errsoths : in STD_LOGIC;
    dl3_errsotsynchs : in STD_LOGIC;
    dl3_erresc : in STD_LOGIC;
    dl3_errcontrol : in STD_LOGIC;
    video_aclk : in STD_LOGIC;
    m_axis_aclk : in STD_LOGIC;
    m_axis_aresetn : in STD_LOGIC;
    m_axis_tready : in STD_LOGIC;
    m_axis_tvalid : out STD_LOGIC;
    m_axis_tlast : out STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_tuser : out STD_LOGIC_VECTOR ( 95 downto 0 );
    m_axis_tdest : out STD_LOGIC_VECTOR ( 3 downto 0 );
    mdt_tv : in STD_LOGIC;
    mdt_tr : in STD_LOGIC;
    sdt_tv : in STD_LOGIC;
    sdt_tr : in STD_LOGIC;
    vfb_tv : in STD_LOGIC;
    vfb_tr : in STD_LOGIC;
    interrupt : out STD_LOGIC;
    frame_rcvd_pulse_out : out STD_LOGIC
  );
  attribute AXIS_FIFO_DCNT_WIDTH : integer;
  attribute AXIS_FIFO_DCNT_WIDTH of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 11;
  attribute AXIS_FIFO_DEPTH : integer;
  attribute AXIS_FIFO_DEPTH of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 2048;
  attribute AXIS_TDATA_WIDTH : integer;
  attribute AXIS_TDATA_WIDTH of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 64;
  attribute AXIS_TDEST_WIDTH : integer;
  attribute AXIS_TDEST_WIDTH of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 4;
  attribute AXIS_TUSER_WIDTH : integer;
  attribute AXIS_TUSER_WIDTH of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 96;
  attribute CMN_INC_VFB : string;
  attribute CMN_INC_VFB of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is "true";
  attribute CSI_EN_VC_SUPPORT : integer;
  attribute CSI_EN_VC_SUPPORT of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 1;
  attribute CSI_FIXED_VC : integer;
  attribute CSI_FIXED_VC of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 0;
  attribute CSI_INV_SHUTDOWN : integer;
  attribute CSI_INV_SHUTDOWN of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 1;
  attribute CSI_LANES : integer;
  attribute CSI_LANES of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 4;
  attribute CSI_OFFLOAD_NONIMAGE : integer;
  attribute CSI_OFFLOAD_NONIMAGE of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 0;
  attribute CSI_VC_OFF_0 : integer;
  attribute CSI_VC_OFF_0 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 1;
  attribute CSI_VC_OFF_1 : integer;
  attribute CSI_VC_OFF_1 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 2;
  attribute CSI_VC_OFF_10 : integer;
  attribute CSI_VC_OFF_10 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 11;
  attribute CSI_VC_OFF_11 : integer;
  attribute CSI_VC_OFF_11 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 12;
  attribute CSI_VC_OFF_12 : integer;
  attribute CSI_VC_OFF_12 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 13;
  attribute CSI_VC_OFF_13 : integer;
  attribute CSI_VC_OFF_13 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 14;
  attribute CSI_VC_OFF_14 : integer;
  attribute CSI_VC_OFF_14 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 15;
  attribute CSI_VC_OFF_2 : integer;
  attribute CSI_VC_OFF_2 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 3;
  attribute CSI_VC_OFF_3 : integer;
  attribute CSI_VC_OFF_3 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 4;
  attribute CSI_VC_OFF_4 : integer;
  attribute CSI_VC_OFF_4 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 5;
  attribute CSI_VC_OFF_5 : integer;
  attribute CSI_VC_OFF_5 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 6;
  attribute CSI_VC_OFF_6 : integer;
  attribute CSI_VC_OFF_6 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 7;
  attribute CSI_VC_OFF_7 : integer;
  attribute CSI_VC_OFF_7 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 8;
  attribute CSI_VC_OFF_8 : integer;
  attribute CSI_VC_OFF_8 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 9;
  attribute CSI_VC_OFF_9 : integer;
  attribute CSI_VC_OFF_9 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 10;
  attribute C_CSI2RX_DBG : integer;
  attribute C_CSI2RX_DBG of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 0;
  attribute C_CSI_FILTER_USERDATATYPE : integer;
  attribute C_CSI_FILTER_USERDATATYPE of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 0;
  attribute C_CSI_OPT1_REGS : integer;
  attribute C_CSI_OPT1_REGS of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 0;
  attribute C_CSI_OPT2_CRC : integer;
  attribute C_CSI_OPT2_CRC of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 0;
  attribute C_CSI_OPT3_FIXEDLANES : integer;
  attribute C_CSI_OPT3_FIXEDLANES of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 1;
  attribute C_DISABLE_LITE : integer;
  attribute C_DISABLE_LITE of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 0;
  attribute C_EN_CSI_V2_0 : string;
  attribute C_EN_CSI_V2_0 of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is "false";
  attribute C_EN_VCX : string;
  attribute C_EN_VCX of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is "false";
  attribute C_FAMILY : string;
  attribute C_FAMILY of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is "zynquplus";
  attribute C_HS_LINE_RATE : integer;
  attribute C_HS_LINE_RATE of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 1188;
  attribute C_MIPI_SLV_INT : integer;
  attribute C_MIPI_SLV_INT of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 0;
  attribute C_RCVE_DESKEW_SEQ : string;
  attribute C_RCVE_DESKEW_SEQ of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is "false";
  attribute C_SPRT_ISP_BRIDGE : integer;
  attribute C_SPRT_ISP_BRIDGE of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 0;
  attribute C_S_AXI_ADDR_WIDTH : integer;
  attribute C_S_AXI_ADDR_WIDTH of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 8;
  attribute C_S_AXI_DATA_WIDTH : integer;
  attribute C_S_AXI_DATA_WIDTH of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is 32;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is "bd_7289_rx_0";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_bd_7289_rx_0 : entity is "yes";
end design_1_Vsp_core_0_0_bd_7289_rx_0;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_rx_0 is
  signal \<const0>\ : STD_LOGIC;
  signal \^m_axis_tuser\ : STD_LOGIC_VECTOR ( 69 downto 0 );
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_cl_stopstate_intr_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_core_men_vfb_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_crc_status_intr_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_disable_in_progress_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl0_shutdown_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl0_stopstate_intr_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl1_shutdown_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl1_stopstate_intr_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl2_shutdown_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl2_stopstate_intr_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl3_shutdown_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl3_stopstate_intr_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_errsoths_intr_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_errsotsynchs_intr_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_frame_rcvd_pulse_out_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_header_valid_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_interrupt_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_linebuffer_full_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_eni_tlast_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_eni_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_ecc_status_intr_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_header_data_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_eni_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_eni_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_eni_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_eni_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 95 downto 0 );
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 95 downto 2 );
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute AXIS_FIFO_DCNT_WIDTH of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 11;
  attribute AXIS_FIFO_DEPTH of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 2048;
  attribute AXIS_TDATA_WIDTH of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 64;
  attribute AXIS_TDEST_WIDTH of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 4;
  attribute AXIS_TUSER_WIDTH of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 96;
  attribute CMN_INC_VFB of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is "true";
  attribute CSI_EN_VC_SUPPORT of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 1;
  attribute CSI_FIXED_VC of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 0;
  attribute CSI_INV_SHUTDOWN of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 1;
  attribute CSI_LANES of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 4;
  attribute CSI_OFFLOAD_NONIMAGE of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 0;
  attribute CSI_VC_OFF_0 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 1;
  attribute CSI_VC_OFF_1 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 2;
  attribute CSI_VC_OFF_10 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 11;
  attribute CSI_VC_OFF_11 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 12;
  attribute CSI_VC_OFF_12 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 13;
  attribute CSI_VC_OFF_13 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 14;
  attribute CSI_VC_OFF_14 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 15;
  attribute CSI_VC_OFF_2 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 3;
  attribute CSI_VC_OFF_3 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 4;
  attribute CSI_VC_OFF_4 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 5;
  attribute CSI_VC_OFF_5 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 6;
  attribute CSI_VC_OFF_6 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 7;
  attribute CSI_VC_OFF_7 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 8;
  attribute CSI_VC_OFF_8 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 9;
  attribute CSI_VC_OFF_9 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 10;
  attribute C_CSI2RX_DBG of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 0;
  attribute C_CSI_FILTER_USERDATATYPE of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 0;
  attribute C_CSI_OPT1_REGS of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 0;
  attribute C_CSI_OPT2_CRC of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 0;
  attribute C_CSI_OPT3_FIXEDLANES of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 1;
  attribute C_DISABLE_LITE of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 0;
  attribute C_EN_CSI_V2_0 of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is "false";
  attribute C_EN_VCX of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is "false";
  attribute C_FAMILY of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is "zynquplus";
  attribute C_HS_LINE_RATE of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 1188;
  attribute C_IS_EVAL : integer;
  attribute C_IS_EVAL of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 0;
  attribute C_MIPI_SLV_INT of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 0;
  attribute C_RCVE_DESKEW_SEQ of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is "false";
  attribute C_RX_PHY : integer;
  attribute C_RX_PHY of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 0;
  attribute C_SPRT_ISP_BRIDGE_string : string;
  attribute C_SPRT_ISP_BRIDGE_string of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is "false";
  attribute C_S_AXI_ADDR_WIDTH of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 8;
  attribute C_S_AXI_DATA_WIDTH of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 32;
  attribute DowngradeIPIdentifiedWarnings of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is "yes";
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is "soft";
  attribute VC_H : integer;
  attribute VC_H of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 4;
  attribute VC_L : integer;
  attribute VC_L of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 0;
  attribute VC_NUMS : integer;
  attribute VC_NUMS of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 4;
  attribute VFB_FIFO : integer;
  attribute VFB_FIFO of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is 16;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of mipi_csi2_rx_ctrl_v1_0_11_top_dut : label is "true";
begin
  core_men_vfb <= \<const0>\;
  dl0_shutdown <= \<const0>\;
  dl1_shutdown <= \<const0>\;
  dl2_shutdown <= \<const0>\;
  dl3_shutdown <= \<const0>\;
  frame_rcvd_pulse_out <= \<const0>\;
  interrupt <= \<const0>\;
  m_axis_tdest(3) <= \<const0>\;
  m_axis_tdest(2) <= \<const0>\;
  m_axis_tdest(1) <= \<const0>\;
  m_axis_tdest(0) <= \<const0>\;
  m_axis_tuser(95) <= \<const0>\;
  m_axis_tuser(94) <= \<const0>\;
  m_axis_tuser(93) <= \<const0>\;
  m_axis_tuser(92) <= \<const0>\;
  m_axis_tuser(91) <= \<const0>\;
  m_axis_tuser(90) <= \<const0>\;
  m_axis_tuser(89) <= \<const0>\;
  m_axis_tuser(88) <= \<const0>\;
  m_axis_tuser(87) <= \<const0>\;
  m_axis_tuser(86) <= \<const0>\;
  m_axis_tuser(85) <= \<const0>\;
  m_axis_tuser(84) <= \<const0>\;
  m_axis_tuser(83) <= \<const0>\;
  m_axis_tuser(82) <= \<const0>\;
  m_axis_tuser(81) <= \<const0>\;
  m_axis_tuser(80) <= \<const0>\;
  m_axis_tuser(79) <= \<const0>\;
  m_axis_tuser(78) <= \<const0>\;
  m_axis_tuser(77) <= \<const0>\;
  m_axis_tuser(76) <= \<const0>\;
  m_axis_tuser(75) <= \<const0>\;
  m_axis_tuser(74) <= \<const0>\;
  m_axis_tuser(73) <= \<const0>\;
  m_axis_tuser(72) <= \<const0>\;
  m_axis_tuser(71) <= \<const0>\;
  m_axis_tuser(70) <= \<const0>\;
  m_axis_tuser(69 downto 64) <= \^m_axis_tuser\(69 downto 64);
  m_axis_tuser(63) <= \<const0>\;
  m_axis_tuser(62) <= \<const0>\;
  m_axis_tuser(61) <= \<const0>\;
  m_axis_tuser(60) <= \<const0>\;
  m_axis_tuser(59) <= \<const0>\;
  m_axis_tuser(58) <= \<const0>\;
  m_axis_tuser(57) <= \<const0>\;
  m_axis_tuser(56) <= \<const0>\;
  m_axis_tuser(55) <= \<const0>\;
  m_axis_tuser(54) <= \<const0>\;
  m_axis_tuser(53) <= \<const0>\;
  m_axis_tuser(52) <= \<const0>\;
  m_axis_tuser(51) <= \<const0>\;
  m_axis_tuser(50) <= \<const0>\;
  m_axis_tuser(49) <= \<const0>\;
  m_axis_tuser(48) <= \<const0>\;
  m_axis_tuser(47) <= \<const0>\;
  m_axis_tuser(46) <= \<const0>\;
  m_axis_tuser(45) <= \<const0>\;
  m_axis_tuser(44) <= \<const0>\;
  m_axis_tuser(43) <= \<const0>\;
  m_axis_tuser(42) <= \<const0>\;
  m_axis_tuser(41) <= \<const0>\;
  m_axis_tuser(40) <= \<const0>\;
  m_axis_tuser(39) <= \<const0>\;
  m_axis_tuser(38) <= \<const0>\;
  m_axis_tuser(37) <= \<const0>\;
  m_axis_tuser(36) <= \<const0>\;
  m_axis_tuser(35) <= \<const0>\;
  m_axis_tuser(34) <= \<const0>\;
  m_axis_tuser(33) <= \<const0>\;
  m_axis_tuser(32) <= \<const0>\;
  m_axis_tuser(31) <= \<const0>\;
  m_axis_tuser(30) <= \<const0>\;
  m_axis_tuser(29) <= \<const0>\;
  m_axis_tuser(28) <= \<const0>\;
  m_axis_tuser(27) <= \<const0>\;
  m_axis_tuser(26) <= \<const0>\;
  m_axis_tuser(25) <= \<const0>\;
  m_axis_tuser(24) <= \<const0>\;
  m_axis_tuser(23) <= \<const0>\;
  m_axis_tuser(22) <= \<const0>\;
  m_axis_tuser(21) <= \<const0>\;
  m_axis_tuser(20) <= \<const0>\;
  m_axis_tuser(19) <= \<const0>\;
  m_axis_tuser(18) <= \<const0>\;
  m_axis_tuser(17) <= \<const0>\;
  m_axis_tuser(16) <= \<const0>\;
  m_axis_tuser(15) <= \<const0>\;
  m_axis_tuser(14) <= \<const0>\;
  m_axis_tuser(13) <= \<const0>\;
  m_axis_tuser(12) <= \<const0>\;
  m_axis_tuser(11) <= \<const0>\;
  m_axis_tuser(10) <= \<const0>\;
  m_axis_tuser(9) <= \<const0>\;
  m_axis_tuser(8) <= \<const0>\;
  m_axis_tuser(7) <= \<const0>\;
  m_axis_tuser(6) <= \<const0>\;
  m_axis_tuser(5) <= \<const0>\;
  m_axis_tuser(4) <= \<const0>\;
  m_axis_tuser(3) <= \<const0>\;
  m_axis_tuser(2) <= \<const0>\;
  m_axis_tuser(1 downto 0) <= \^m_axis_tuser\(1 downto 0);
  s_axi_bresp(1) <= \<const0>\;
  s_axi_bresp(0) <= \<const0>\;
  s_axi_rresp(1) <= \<const0>\;
  s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
mipi_csi2_rx_ctrl_v1_0_11_top_dut: entity work.design_1_Vsp_core_0_0_mipi_csi2_rx_ctrl_v1_0_11_top
     port map (
      active_lanes(1 downto 0) => B"00",
      cl_enable => cl_enable,
      cl_rxulpsclknot => cl_rxulpsclknot,
      cl_stopstate => cl_stopstate,
      cl_stopstate_intr => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_cl_stopstate_intr_UNCONNECTED,
      core_clk => '0',
      core_enable => '0',
      core_men_ack_vfb => '1',
      core_men_vfb => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_core_men_vfb_UNCONNECTED,
      crc_status_intr => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_crc_status_intr_UNCONNECTED,
      disable_in_progress => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_disable_in_progress_UNCONNECTED,
      dl0_errcontrol => '0',
      dl0_erresc => '0',
      dl0_errsoths => dl0_errsoths,
      dl0_errsotsynchs => dl0_errsotsynchs,
      dl0_rxactivehs => dl0_rxactivehs,
      dl0_rxbyteclkhs => dl0_rxbyteclkhs,
      dl0_rxdatahs(7 downto 0) => dl0_rxdatahs(7 downto 0),
      dl0_rxskewcalhs => '0',
      dl0_rxsynchs => dl0_rxsynchs,
      dl0_rxulpmesc => '0',
      dl0_rxvalidhs => dl0_rxvalidhs,
      dl0_shutdown => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl0_shutdown_UNCONNECTED,
      dl0_stopstate => dl0_stopstate,
      dl0_stopstate_intr => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl0_stopstate_intr_UNCONNECTED,
      dl1_errcontrol => '0',
      dl1_erresc => '0',
      dl1_errsoths => dl1_errsoths,
      dl1_errsotsynchs => dl1_errsotsynchs,
      dl1_rxactivehs => dl1_rxactivehs,
      dl1_rxbyteclkhs => '0',
      dl1_rxdatahs(7 downto 0) => dl1_rxdatahs(7 downto 0),
      dl1_rxskewcalhs => '0',
      dl1_rxsynchs => dl1_rxsynchs,
      dl1_rxulpmesc => '0',
      dl1_rxvalidhs => dl1_rxvalidhs,
      dl1_shutdown => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl1_shutdown_UNCONNECTED,
      dl1_stopstate => dl1_stopstate,
      dl1_stopstate_intr => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl1_stopstate_intr_UNCONNECTED,
      dl2_errcontrol => '0',
      dl2_erresc => '0',
      dl2_errsoths => dl2_errsoths,
      dl2_errsotsynchs => dl2_errsotsynchs,
      dl2_rxactivehs => dl2_rxactivehs,
      dl2_rxbyteclkhs => '0',
      dl2_rxdatahs(7 downto 0) => dl2_rxdatahs(7 downto 0),
      dl2_rxskewcalhs => '0',
      dl2_rxsynchs => dl2_rxsynchs,
      dl2_rxulpmesc => '0',
      dl2_rxvalidhs => dl2_rxvalidhs,
      dl2_shutdown => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl2_shutdown_UNCONNECTED,
      dl2_stopstate => dl2_stopstate,
      dl2_stopstate_intr => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl2_stopstate_intr_UNCONNECTED,
      dl3_errcontrol => '0',
      dl3_erresc => '0',
      dl3_errsoths => dl3_errsoths,
      dl3_errsotsynchs => dl3_errsotsynchs,
      dl3_rxactivehs => dl3_rxactivehs,
      dl3_rxbyteclkhs => '0',
      dl3_rxdatahs(7 downto 0) => dl3_rxdatahs(7 downto 0),
      dl3_rxskewcalhs => '0',
      dl3_rxsynchs => dl3_rxsynchs,
      dl3_rxulpmesc => '0',
      dl3_rxvalidhs => dl3_rxvalidhs,
      dl3_shutdown => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl3_shutdown_UNCONNECTED,
      dl3_stopstate => dl3_stopstate,
      dl3_stopstate_intr => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_dl3_stopstate_intr_UNCONNECTED,
      ecc_status_intr(1 downto 0) => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_ecc_status_intr_UNCONNECTED(1 downto 0),
      errsoths_intr => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_errsoths_intr_UNCONNECTED,
      errsotsynchs_intr => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_errsotsynchs_intr_UNCONNECTED,
      frame_rcvd_pulse_out => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_frame_rcvd_pulse_out_UNCONNECTED,
      header_data(31 downto 0) => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_header_data_UNCONNECTED(31 downto 0),
      header_valid => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_header_valid_UNCONNECTED,
      interrupt => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_interrupt_UNCONNECTED,
      linebuffer_full => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_linebuffer_full_UNCONNECTED,
      m_axis_aclk => '0',
      m_axis_aresetn => '0',
      m_axis_eni_tdata(63 downto 0) => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_eni_tdata_UNCONNECTED(63 downto 0),
      m_axis_eni_tdest(3 downto 0) => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_eni_tdest_UNCONNECTED(3 downto 0),
      m_axis_eni_tkeep(7 downto 0) => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_eni_tkeep_UNCONNECTED(7 downto 0),
      m_axis_eni_tlast => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_eni_tlast_UNCONNECTED,
      m_axis_eni_tready => '0',
      m_axis_eni_tuser(95 downto 0) => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_eni_tuser_UNCONNECTED(95 downto 0),
      m_axis_eni_tvalid => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_eni_tvalid_UNCONNECTED,
      m_axis_tdata(63 downto 0) => m_axis_tdata(63 downto 0),
      m_axis_tdest(3 downto 0) => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_tdest_UNCONNECTED(3 downto 0),
      m_axis_tkeep(7 downto 0) => m_axis_tkeep(7 downto 0),
      m_axis_tlast => m_axis_tlast,
      m_axis_tready => m_axis_tready,
      m_axis_tuser(95 downto 70) => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_tuser_UNCONNECTED(95 downto 70),
      m_axis_tuser(69 downto 64) => \^m_axis_tuser\(69 downto 64),
      m_axis_tuser(63 downto 2) => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_m_axis_tuser_UNCONNECTED(63 downto 2),
      m_axis_tuser(1 downto 0) => \^m_axis_tuser\(1 downto 0),
      m_axis_tvalid => m_axis_tvalid,
      mdt_tr => '0',
      mdt_tv => '0',
      s_axi_aclk => s_axi_aclk,
      s_axi_araddr(7 downto 2) => s_axi_araddr(7 downto 2),
      s_axi_araddr(1 downto 0) => B"00",
      s_axi_aresetn => s_axi_aresetn,
      s_axi_arready => s_axi_arready,
      s_axi_arvalid => s_axi_arvalid,
      s_axi_awaddr(7 downto 2) => s_axi_awaddr(7 downto 2),
      s_axi_awaddr(1 downto 0) => B"00",
      s_axi_awready => s_axi_awready,
      s_axi_awvalid => s_axi_awvalid,
      s_axi_bready => s_axi_bready,
      s_axi_bresp(1 downto 0) => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => s_axi_bvalid,
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      s_axi_rready => s_axi_rready,
      s_axi_rresp(1 downto 0) => NLW_mipi_csi2_rx_ctrl_v1_0_11_top_dut_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => s_axi_rvalid,
      s_axi_wdata(31 downto 27) => s_axi_wdata(31 downto 27),
      s_axi_wdata(26 downto 24) => B"000",
      s_axi_wdata(23 downto 0) => s_axi_wdata(23 downto 0),
      s_axi_wready => s_axi_wready,
      s_axi_wstrb(3 downto 0) => B"0000",
      s_axi_wvalid => s_axi_wvalid,
      sdt_tr => '0',
      sdt_tv => '0',
      vfb_full => '0',
      vfb_tr => '0',
      vfb_tv => '0',
      vfb_wc_full => '0',
      video_aclk => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Corner is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    ackInvCornerSet : out STD_LOGIC;
    ackInvCornerUnlock : out STD_LOGIC;
    ackInvCornerAcquire : out STD_LOGIC;
    ackInvCornerConfig : out STD_LOGIC;
    rng_reg_0 : out STD_LOGIC;
    rng_reg_1 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \col_lcl_reg[10]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \tixVState_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateOp_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \tixVState_reg[1]_1\ : out STD_LOGIC;
    \row_lcl_reg[1]_0\ : out STD_LOGIC;
    \FSM_onehot_stateCoobufB_reg[5]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \tkst_reg[31]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \scoreMin_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \scoreMax_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ackCoobufCornerToHostif : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    ackInvSet_sig : in STD_LOGIC;
    linNotLog_reg_0 : in STD_LOGIC;
    ackInvUnlock_sig0_in : in STD_LOGIC;
    hdrNotFix : in STD_LOGIC;
    rng_reg_2 : in STD_LOGIC;
    grayVideoinToManyAXIS_tdata : in STD_LOGIC_VECTOR ( 39 downto 0 );
    \aImdbufB_reg[0]_0\ : in STD_LOGIC;
    \tkst_reg[0]_0\ : in STD_LOGIC;
    enCoobuf_reg_0 : in STD_LOGIC;
    \capt_reg[2]\ : in STD_LOGIC;
    \capt_reg[1]\ : in STD_LOGIC;
    \stateOp_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    vsync_last_reg_0 : in STD_LOGIC;
    \tixVState_reg[1]_2\ : in STD_LOGIC;
    \stateCorner_reg[1]_0\ : in STD_LOGIC;
    grayVideoinToManyAXIS_tlast : in STD_LOGIC;
    grayVideoinToManyAXIS_tvalid : in STD_LOGIC;
    \col_lcl_reg[0]__0_0\ : in STD_LOGIC;
    NColRaw : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \col_lcl[10]__0_i_3_0\ : in STD_LOGIC;
    \col_lcl[10]__0_i_5_0\ : in STD_LOGIC;
    \col_lcl[10]__0_i_3_1\ : in STD_LOGIC;
    \col_lcl[10]__0_i_3_2\ : in STD_LOGIC;
    NRowRaw : in STD_LOGIC_VECTOR ( 2 downto 0 );
    reqInvAcquire : in STD_LOGIC;
    reqInvCornerConfig : in STD_LOGIC;
    \tixVState_reg[1]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \tixVState_reg[1]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \tkst_reg[31]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \dy_reg[44]_0\ : in STD_LOGIC_VECTOR ( 44 downto 0 );
    \col1_reg[10]_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \thd_reg[7]_0\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
    \row1_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \col0_reg[10]_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    coobufCornerToHostifAXIS_tready : in STD_LOGIC;
    dneCoobufCornerToHostif : in STD_LOGIC;
    reqCoobufCornerToHostif : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Corner : entity is "Corner";
end design_1_Vsp_core_0_0_Corner;

architecture STRUCTURE of design_1_Vsp_core_0_0_Corner is
  signal A : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal ARG : STD_LOGIC_VECTOR ( 37 downto 19 );
  signal B : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \FSM_onehot_stateCoobufB[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateCoobufB[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateCoobufB[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateCoobufB[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateCoobufB[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateCoobufB[5]_i_3_n_0\ : STD_LOGIC;
  signal \^fsm_onehot_statecoobufb_reg[5]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \FSM_onehot_stateCoobufB_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_stateCoobufB_reg_n_0_[2]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal RESIZE : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal RESIZE0_in : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal aCoobufB : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \aCoobufB[0]_i_1_n_0\ : STD_LOGIC;
  signal \aCoobufB[5]_i_2_n_0\ : STD_LOGIC;
  signal \aCoobufB_reg_n_0_[0]\ : STD_LOGIC;
  signal \aCoobufB_reg_n_0_[1]\ : STD_LOGIC;
  signal \aCoobufB_reg_n_0_[2]\ : STD_LOGIC;
  signal \aCoobufB_reg_n_0_[3]\ : STD_LOGIC;
  signal \aCoobufB_reg_n_0_[4]\ : STD_LOGIC;
  signal \aCoobufB_reg_n_0_[5]\ : STD_LOGIC;
  signal \aCoobufB_reg_n_0_[6]\ : STD_LOGIC;
  signal \aCoobufB_reg_n_0_[7]\ : STD_LOGIC;
  signal \aCoobuf[3]_i_1_n_0\ : STD_LOGIC;
  signal \aCoobuf[5]_i_2_n_0\ : STD_LOGIC;
  signal \aCoobuf[8]_i_3_n_0\ : STD_LOGIC;
  signal aCoobuf_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal aImdbufB : STD_LOGIC;
  signal \aImdbufB[0]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbufB[10]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbufB[10]_i_2_n_0\ : STD_LOGIC;
  signal \aImdbufB[1]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbufB[2]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbufB[3]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbufB[4]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbufB[4]_i_2_n_0\ : STD_LOGIC;
  signal \aImdbufB[5]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbufB[5]_i_2_n_0\ : STD_LOGIC;
  signal \aImdbufB[6]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbufB[7]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbufB[8]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbufB[8]_i_2_n_0\ : STD_LOGIC;
  signal \aImdbufB[9]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbufB_reg_n_0_[0]\ : STD_LOGIC;
  signal \aImdbufB_reg_n_0_[10]\ : STD_LOGIC;
  signal \aImdbufB_reg_n_0_[1]\ : STD_LOGIC;
  signal \aImdbufB_reg_n_0_[2]\ : STD_LOGIC;
  signal \aImdbufB_reg_n_0_[3]\ : STD_LOGIC;
  signal \aImdbufB_reg_n_0_[4]\ : STD_LOGIC;
  signal \aImdbufB_reg_n_0_[5]\ : STD_LOGIC;
  signal \aImdbufB_reg_n_0_[6]\ : STD_LOGIC;
  signal \aImdbufB_reg_n_0_[7]\ : STD_LOGIC;
  signal \aImdbufB_reg_n_0_[8]\ : STD_LOGIC;
  signal \aImdbufB_reg_n_0_[9]\ : STD_LOGIC;
  signal \aImdbuf[0]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbuf[10]_i_2_n_0\ : STD_LOGIC;
  signal \aImdbuf[10]_i_3_n_0\ : STD_LOGIC;
  signal \aImdbuf[10]_i_4_n_0\ : STD_LOGIC;
  signal \aImdbuf[10]_i_5_n_0\ : STD_LOGIC;
  signal \aImdbuf[10]_i_6_n_0\ : STD_LOGIC;
  signal \aImdbuf[10]_i_7_n_0\ : STD_LOGIC;
  signal \aImdbuf[10]_i_8_n_0\ : STD_LOGIC;
  signal \aImdbuf[1]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbuf[2]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbuf[3]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbuf[4]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbuf[4]_i_2_n_0\ : STD_LOGIC;
  signal \aImdbuf[5]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbuf[5]_i_2_n_0\ : STD_LOGIC;
  signal \aImdbuf[6]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbuf[7]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbuf[8]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbuf[8]_i_2_n_0\ : STD_LOGIC;
  signal \aImdbuf[9]_i_1_n_0\ : STD_LOGIC;
  signal \aImdbuf_reg_n_0_[0]\ : STD_LOGIC;
  signal \aImdbuf_reg_n_0_[10]\ : STD_LOGIC;
  signal \aImdbuf_reg_n_0_[1]\ : STD_LOGIC;
  signal \aImdbuf_reg_n_0_[2]\ : STD_LOGIC;
  signal \aImdbuf_reg_n_0_[3]\ : STD_LOGIC;
  signal \aImdbuf_reg_n_0_[4]\ : STD_LOGIC;
  signal \aImdbuf_reg_n_0_[5]\ : STD_LOGIC;
  signal \aImdbuf_reg_n_0_[6]\ : STD_LOGIC;
  signal \aImdbuf_reg_n_0_[7]\ : STD_LOGIC;
  signal \aImdbuf_reg_n_0_[8]\ : STD_LOGIC;
  signal \aImdbuf_reg_n_0_[9]\ : STD_LOGIC;
  signal \abcde[0]_i_1_n_0\ : STD_LOGIC;
  signal \abcde[1]_i_1_n_0\ : STD_LOGIC;
  signal \abcde[2]_i_1_n_0\ : STD_LOGIC;
  signal \abcde[2]_i_2_n_0\ : STD_LOGIC;
  signal \abcde__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal ackInvAcquire_sig : STD_LOGIC;
  signal ackInvConfig_sig : STD_LOGIC;
  signal ceMaxsel_i_1_n_0 : STD_LOGIC;
  signal ceMaxsel_i_2_n_0 : STD_LOGIC;
  signal ceMaxsel_reg_n_0 : STD_LOGIC;
  signal ceScore : STD_LOGIC;
  signal ceScore15_out : STD_LOGIC;
  signal col0 : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal col1 : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \col_lcl[0]__0_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[0]_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_10_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_11_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_12_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_14_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_16_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_17_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_2_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_3_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_4_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_5_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_6_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_8_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_9_n_0\ : STD_LOGIC;
  signal \col_lcl[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[10]_i_2_n_0\ : STD_LOGIC;
  signal \col_lcl[10]_i_3_n_0\ : STD_LOGIC;
  signal \col_lcl[10]_i_4_n_0\ : STD_LOGIC;
  signal \col_lcl[10]_i_5_n_0\ : STD_LOGIC;
  signal \col_lcl[1]__0_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[1]_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[2]__0_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[2]_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[3]__0_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[3]_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[4]__0_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[4]__0_i_2_n_0\ : STD_LOGIC;
  signal \col_lcl[4]_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[5]__0_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[5]__0_i_2_n_0\ : STD_LOGIC;
  signal \col_lcl[5]_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \col_lcl[6]__0_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[6]_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[7]__0_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[7]_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[8]__0_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[8]__0_i_2_n_0\ : STD_LOGIC;
  signal \col_lcl[8]__0_i_3_n_0\ : STD_LOGIC;
  signal \col_lcl[8]__0_i_4_n_0\ : STD_LOGIC;
  signal \col_lcl[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[9]__0_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[9]__0_i_2_n_0\ : STD_LOGIC;
  signal \col_lcl[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[9]_i_2__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[0]__0_n_0\ : STD_LOGIC;
  signal \^col_lcl_reg[10]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \col_lcl_reg[10]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[1]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[2]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[3]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[4]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[5]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[6]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[7]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[8]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[9]__0_n_0\ : STD_LOGIC;
  signal colmax_lcl : STD_LOGIC;
  signal \colmax_lcl[0]_i_1_n_0\ : STD_LOGIC;
  signal \colmax_lcl[1]_i_1_n_0\ : STD_LOGIC;
  signal \colmax_lcl[2]_i_2_n_0\ : STD_LOGIC;
  signal \colmax_lcl_reg_n_0_[0]\ : STD_LOGIC;
  signal \colmax_lcl_reg_n_0_[1]\ : STD_LOGIC;
  signal \colmax_lcl_reg_n_0_[2]\ : STD_LOGIC;
  signal colsumX : STD_LOGIC_VECTOR ( 41 downto 21 );
  signal colsumX4p1 : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal \colsumX4p1[0]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[10]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[11]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[12]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[13]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[14]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[16]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[17]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[18]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[19]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[1]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[20]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[2]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[3]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[4]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[5]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[6]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[8]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p1[9]_i_1_n_0\ : STD_LOGIC;
  signal colsumX4p2 : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal \colsumX4p2[0]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[10]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[11]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[12]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[13]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[14]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[16]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[17]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[18]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[19]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[1]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[20]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[2]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[3]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[4]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[5]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[6]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[8]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX4p2[9]_i_1_n_0\ : STD_LOGIC;
  signal colsumXA0 : STD_LOGIC_VECTOR ( 17 downto 2 );
  signal colsumXA00_in : STD_LOGIC_VECTOR ( 17 downto 2 );
  signal \colsumXA[0]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[10]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[11]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[12]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[13]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[14]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[16]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[17]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXA[17]_i_11_n_0\ : STD_LOGIC;
  signal \colsumXA[17]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[17]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXA[17]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXA[17]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXA[17]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXA[17]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXA[17]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXA[17]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXA[18]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[19]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[1]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[20]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[21]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[22]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[23]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[24]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[25]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[26]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[27]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[28]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXA[28]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[28]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXA[28]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXA[28]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXA[28]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXA[28]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXA[28]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXA[28]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXA[29]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[2]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[30]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[31]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[32]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[33]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[34]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[35]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[36]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXA[36]_i_11_n_0\ : STD_LOGIC;
  signal \colsumXA[36]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[36]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXA[36]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXA[36]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXA[36]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXA[36]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXA[36]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXA[36]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXA[37]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[3]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[4]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[5]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[6]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[8]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[9]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXA[9]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXA[9]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXA[9]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXA[9]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXA[9]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXA[9]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXA[9]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXA[9]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXA_reg[17]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXA_reg[17]_i_2_n_1\ : STD_LOGIC;
  signal \colsumXA_reg[17]_i_2_n_2\ : STD_LOGIC;
  signal \colsumXA_reg[17]_i_2_n_3\ : STD_LOGIC;
  signal \colsumXA_reg[17]_i_2_n_4\ : STD_LOGIC;
  signal \colsumXA_reg[17]_i_2_n_5\ : STD_LOGIC;
  signal \colsumXA_reg[17]_i_2_n_6\ : STD_LOGIC;
  signal \colsumXA_reg[17]_i_2_n_7\ : STD_LOGIC;
  signal \colsumXA_reg[18]_i_2_n_7\ : STD_LOGIC;
  signal \colsumXA_reg[28]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXA_reg[28]_i_2_n_1\ : STD_LOGIC;
  signal \colsumXA_reg[28]_i_2_n_2\ : STD_LOGIC;
  signal \colsumXA_reg[28]_i_2_n_3\ : STD_LOGIC;
  signal \colsumXA_reg[28]_i_2_n_4\ : STD_LOGIC;
  signal \colsumXA_reg[28]_i_2_n_5\ : STD_LOGIC;
  signal \colsumXA_reg[28]_i_2_n_6\ : STD_LOGIC;
  signal \colsumXA_reg[28]_i_2_n_7\ : STD_LOGIC;
  signal \colsumXA_reg[36]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXA_reg[36]_i_2_n_1\ : STD_LOGIC;
  signal \colsumXA_reg[36]_i_2_n_2\ : STD_LOGIC;
  signal \colsumXA_reg[36]_i_2_n_3\ : STD_LOGIC;
  signal \colsumXA_reg[36]_i_2_n_4\ : STD_LOGIC;
  signal \colsumXA_reg[36]_i_2_n_5\ : STD_LOGIC;
  signal \colsumXA_reg[36]_i_2_n_6\ : STD_LOGIC;
  signal \colsumXA_reg[36]_i_2_n_7\ : STD_LOGIC;
  signal \colsumXA_reg[37]_i_2_n_7\ : STD_LOGIC;
  signal \colsumXA_reg[9]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXA_reg[9]_i_2_n_1\ : STD_LOGIC;
  signal \colsumXA_reg[9]_i_2_n_2\ : STD_LOGIC;
  signal \colsumXA_reg[9]_i_2_n_3\ : STD_LOGIC;
  signal \colsumXA_reg[9]_i_2_n_4\ : STD_LOGIC;
  signal \colsumXA_reg[9]_i_2_n_5\ : STD_LOGIC;
  signal \colsumXA_reg[9]_i_2_n_6\ : STD_LOGIC;
  signal \colsumXA_reg[9]_i_2_n_7\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[0]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[10]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[11]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[12]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[13]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[14]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[15]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[16]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[17]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[18]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[1]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[2]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[3]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[4]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[5]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[6]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[7]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[8]\ : STD_LOGIC;
  signal \colsumXA_reg_n_0_[9]\ : STD_LOGIC;
  signal colsumXB : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal \colsumXB[15]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_11_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_12_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_13_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_14_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_15_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_16_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_17_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXB[15]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXB[19]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXB[19]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXB[19]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXB[19]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXB[19]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXB[19]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXB[19]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_11_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_12_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_13_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_14_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_15_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_16_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_17_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXB[7]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \colsumXB_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \colsumXB_reg[19]_i_1_n_12\ : STD_LOGIC;
  signal \colsumXB_reg[19]_i_1_n_13\ : STD_LOGIC;
  signal \colsumXB_reg[19]_i_1_n_14\ : STD_LOGIC;
  signal \colsumXB_reg[19]_i_1_n_15\ : STD_LOGIC;
  signal \colsumXB_reg[19]_i_1_n_5\ : STD_LOGIC;
  signal \colsumXB_reg[19]_i_1_n_6\ : STD_LOGIC;
  signal \colsumXB_reg[19]_i_1_n_7\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \colsumXB_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal \colsumXC[15]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_11_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_12_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_13_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_14_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_15_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_16_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_17_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXC[15]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXC[20]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXC[20]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXC[20]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXC[20]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXC[20]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXC[20]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXC[20]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXC[20]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXC[20]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_11_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_12_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_13_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_14_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_15_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_16_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXC[7]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \colsumXC_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \colsumXC_reg[20]_i_1_n_11\ : STD_LOGIC;
  signal \colsumXC_reg[20]_i_1_n_12\ : STD_LOGIC;
  signal \colsumXC_reg[20]_i_1_n_13\ : STD_LOGIC;
  signal \colsumXC_reg[20]_i_1_n_14\ : STD_LOGIC;
  signal \colsumXC_reg[20]_i_1_n_15\ : STD_LOGIC;
  signal \colsumXC_reg[20]_i_1_n_4\ : STD_LOGIC;
  signal \colsumXC_reg[20]_i_1_n_5\ : STD_LOGIC;
  signal \colsumXC_reg[20]_i_1_n_6\ : STD_LOGIC;
  signal \colsumXC_reg[20]_i_1_n_7\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \colsumXC_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal colsumXY4p1 : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal \colsumXY4p1[0]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[10]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[11]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[12]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[13]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[14]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[16]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[17]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[18]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[19]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[1]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[20]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[2]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[3]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[4]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[5]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[6]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[8]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p1[9]_i_1_n_0\ : STD_LOGIC;
  signal colsumXY4p2 : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal \colsumXY4p2[0]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[10]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[11]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[12]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[13]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[14]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[16]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[17]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[18]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[19]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[1]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[20]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[2]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[3]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[4]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[5]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[6]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[8]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY4p2[9]_i_1_n_0\ : STD_LOGIC;
  signal colsumXYA : STD_LOGIC_VECTOR ( 37 downto 0 );
  signal colsumXYA0 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal colsumXYA00_in : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \colsumXYA[0]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[10]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[11]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[12]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[13]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[14]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[15]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXYA[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[15]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXYA[15]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXYA[15]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXYA[15]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXYA[15]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXYA[15]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXYA[15]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXYA[16]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[17]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[18]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[18]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXYA[18]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXYA[18]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXYA[19]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[1]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[20]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[21]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[22]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[23]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[24]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[25]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[26]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXYA[26]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[26]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXYA[26]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXYA[26]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXYA[26]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXYA[26]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXYA[26]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXYA[26]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXYA[27]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[28]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[29]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[2]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[30]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[31]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[32]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[33]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[34]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXYA[34]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[34]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXYA[34]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXYA[34]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXYA[34]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXYA[34]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXYA[34]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXYA[34]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXYA[35]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[36]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[37]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[37]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXYA[37]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXYA[37]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXYA[3]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[4]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[5]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[6]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[7]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXYA[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[7]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXYA[7]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXYA[7]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXYA[7]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXYA[7]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXYA[7]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXYA[7]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXYA[8]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA[9]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYA_reg[15]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXYA_reg[15]_i_2_n_1\ : STD_LOGIC;
  signal \colsumXYA_reg[15]_i_2_n_2\ : STD_LOGIC;
  signal \colsumXYA_reg[15]_i_2_n_3\ : STD_LOGIC;
  signal \colsumXYA_reg[15]_i_2_n_4\ : STD_LOGIC;
  signal \colsumXYA_reg[15]_i_2_n_5\ : STD_LOGIC;
  signal \colsumXYA_reg[15]_i_2_n_6\ : STD_LOGIC;
  signal \colsumXYA_reg[15]_i_2_n_7\ : STD_LOGIC;
  signal \colsumXYA_reg[18]_i_2_n_5\ : STD_LOGIC;
  signal \colsumXYA_reg[18]_i_2_n_7\ : STD_LOGIC;
  signal \colsumXYA_reg[26]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXYA_reg[26]_i_2_n_1\ : STD_LOGIC;
  signal \colsumXYA_reg[26]_i_2_n_2\ : STD_LOGIC;
  signal \colsumXYA_reg[26]_i_2_n_3\ : STD_LOGIC;
  signal \colsumXYA_reg[26]_i_2_n_4\ : STD_LOGIC;
  signal \colsumXYA_reg[26]_i_2_n_5\ : STD_LOGIC;
  signal \colsumXYA_reg[26]_i_2_n_6\ : STD_LOGIC;
  signal \colsumXYA_reg[26]_i_2_n_7\ : STD_LOGIC;
  signal \colsumXYA_reg[34]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXYA_reg[34]_i_2_n_1\ : STD_LOGIC;
  signal \colsumXYA_reg[34]_i_2_n_2\ : STD_LOGIC;
  signal \colsumXYA_reg[34]_i_2_n_3\ : STD_LOGIC;
  signal \colsumXYA_reg[34]_i_2_n_4\ : STD_LOGIC;
  signal \colsumXYA_reg[34]_i_2_n_5\ : STD_LOGIC;
  signal \colsumXYA_reg[34]_i_2_n_6\ : STD_LOGIC;
  signal \colsumXYA_reg[34]_i_2_n_7\ : STD_LOGIC;
  signal \colsumXYA_reg[37]_i_2_n_5\ : STD_LOGIC;
  signal \colsumXYA_reg[37]_i_2_n_7\ : STD_LOGIC;
  signal \colsumXYA_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXYA_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \colsumXYA_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \colsumXYA_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \colsumXYA_reg[7]_i_2_n_4\ : STD_LOGIC;
  signal \colsumXYA_reg[7]_i_2_n_5\ : STD_LOGIC;
  signal \colsumXYA_reg[7]_i_2_n_6\ : STD_LOGIC;
  signal \colsumXYA_reg[7]_i_2_n_7\ : STD_LOGIC;
  signal colsumXYB : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal \colsumXYB[15]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_11_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_12_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_13_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_14_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_15_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_16_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_17_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXYB[15]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXYB[19]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXYB[19]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXYB[19]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXYB[19]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXYB[19]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXYB[19]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXYB[19]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_11_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_12_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_13_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_14_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_15_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_16_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_17_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXYB[7]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \colsumXYB_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \colsumXYB_reg[19]_i_1_n_12\ : STD_LOGIC;
  signal \colsumXYB_reg[19]_i_1_n_13\ : STD_LOGIC;
  signal \colsumXYB_reg[19]_i_1_n_14\ : STD_LOGIC;
  signal \colsumXYB_reg[19]_i_1_n_15\ : STD_LOGIC;
  signal \colsumXYB_reg[19]_i_1_n_5\ : STD_LOGIC;
  signal \colsumXYB_reg[19]_i_1_n_6\ : STD_LOGIC;
  signal \colsumXYB_reg[19]_i_1_n_7\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \colsumXYB_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal colsumXYC : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal \colsumXYC[15]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_11_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_12_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_13_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_14_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_15_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_16_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_17_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXYC[15]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXYC[20]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXYC[20]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXYC[20]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXYC[20]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXYC[20]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXYC[20]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXYC[20]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXYC[20]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXYC[20]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_10_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_11_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_12_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_13_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_14_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_15_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_16_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_17_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_2_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_3_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_4_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_5_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_6_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_7_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_8_n_0\ : STD_LOGIC;
  signal \colsumXYC[7]_i_9_n_0\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \colsumXYC_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \colsumXYC_reg[20]_i_1_n_11\ : STD_LOGIC;
  signal \colsumXYC_reg[20]_i_1_n_12\ : STD_LOGIC;
  signal \colsumXYC_reg[20]_i_1_n_13\ : STD_LOGIC;
  signal \colsumXYC_reg[20]_i_1_n_14\ : STD_LOGIC;
  signal \colsumXYC_reg[20]_i_1_n_15\ : STD_LOGIC;
  signal \colsumXYC_reg[20]_i_1_n_4\ : STD_LOGIC;
  signal \colsumXYC_reg[20]_i_1_n_5\ : STD_LOGIC;
  signal \colsumXYC_reg[20]_i_1_n_6\ : STD_LOGIC;
  signal \colsumXYC_reg[20]_i_1_n_7\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \colsumXYC_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal \colsumXY[100]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[101]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[102]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[103]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[104]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[21]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[22]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[23]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[24]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[25]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[26]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[27]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[28]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[29]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[30]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[31]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[32]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[33]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[34]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[35]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[36]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[37]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[38]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[39]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[40]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[41]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[84]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[85]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[86]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[87]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[88]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[89]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[90]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[91]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[92]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[93]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[94]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[95]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[96]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[97]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[98]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY[99]_i_1_n_0\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[0]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[100]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[101]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[102]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[103]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[104]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[10]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[11]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[12]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[13]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[14]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[15]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[16]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[17]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[18]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[19]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[1]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[20]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[21]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[22]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[23]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[24]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[25]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[26]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[27]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[28]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[29]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[2]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[30]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[31]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[32]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[33]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[34]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[35]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[36]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[37]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[38]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[39]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[3]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[40]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[41]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[42]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[43]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[44]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[45]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[46]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[47]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[48]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[49]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[4]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[50]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[51]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[52]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[53]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[54]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[55]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[56]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[57]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[58]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[59]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[5]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[60]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[61]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[62]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[63]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[64]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[65]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[66]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[67]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[68]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[69]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[6]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[70]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[71]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[72]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[73]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[74]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[75]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[76]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[77]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[78]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[79]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[7]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[80]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[81]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[82]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[83]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[84]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[85]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[86]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[87]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[88]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[89]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[8]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[90]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[91]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[92]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[93]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[94]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[95]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[96]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[97]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[98]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[99]\ : STD_LOGIC;
  signal \colsumXY_reg_n_0_[9]\ : STD_LOGIC;
  signal \colsumX[100]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[101]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[102]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[103]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[104]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[104]_i_2_n_0\ : STD_LOGIC;
  signal \colsumX[20]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[21]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[22]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[23]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[24]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[25]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[26]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[27]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[28]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[29]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[30]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[31]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[32]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[33]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[34]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[35]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[36]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[37]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[38]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[39]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[40]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[41]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[41]_i_2_n_0\ : STD_LOGIC;
  signal \colsumX[62]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[83]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[84]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[85]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[86]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[87]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[88]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[89]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[90]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[91]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[92]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[93]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[94]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[95]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[96]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[97]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[98]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX[99]_i_1_n_0\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[0]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[100]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[101]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[102]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[103]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[104]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[10]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[11]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[12]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[13]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[14]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[15]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[16]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[17]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[18]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[19]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[1]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[20]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[21]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[22]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[23]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[24]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[25]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[26]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[27]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[28]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[29]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[2]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[30]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[31]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[32]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[33]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[34]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[35]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[36]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[37]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[38]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[39]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[3]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[40]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[41]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[42]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[43]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[44]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[45]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[46]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[47]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[48]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[49]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[4]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[50]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[51]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[52]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[53]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[54]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[55]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[56]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[57]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[58]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[59]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[5]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[60]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[61]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[62]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[63]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[64]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[65]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[66]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[67]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[68]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[69]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[6]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[70]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[71]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[72]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[73]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[74]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[75]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[76]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[77]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[78]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[79]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[7]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[80]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[81]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[82]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[83]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[84]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[85]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[86]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[87]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[88]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[89]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[8]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[90]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[91]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[92]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[93]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[94]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[95]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[96]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[97]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[98]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[99]\ : STD_LOGIC;
  signal \colsumX_reg_n_0_[9]\ : STD_LOGIC;
  signal colsumY : STD_LOGIC_VECTOR ( 41 downto 21 );
  signal colsumY4p1 : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal \colsumY4p1[0]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[10]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[11]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[12]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[13]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[14]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[16]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[17]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[18]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[19]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[1]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[20]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[2]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[3]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[4]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[5]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[6]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[8]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p1[9]_i_1_n_0\ : STD_LOGIC;
  signal colsumY4p2 : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal \colsumY4p2[0]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[10]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[11]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[12]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[13]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[14]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[16]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[17]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[18]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[19]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[1]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[20]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[2]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[3]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[4]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[5]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[6]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[8]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY4p2[9]_i_1_n_0\ : STD_LOGIC;
  signal colsumYA : STD_LOGIC_VECTOR ( 37 downto 0 );
  signal colsumYA0 : STD_LOGIC_VECTOR ( 17 downto 2 );
  signal colsumYA00_in : STD_LOGIC_VECTOR ( 17 downto 2 );
  signal \colsumYA[0]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[10]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[11]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[12]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[13]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[14]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[16]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[17]_i_10_n_0\ : STD_LOGIC;
  signal \colsumYA[17]_i_11_n_0\ : STD_LOGIC;
  signal \colsumYA[17]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[17]_i_3_n_0\ : STD_LOGIC;
  signal \colsumYA[17]_i_4_n_0\ : STD_LOGIC;
  signal \colsumYA[17]_i_5_n_0\ : STD_LOGIC;
  signal \colsumYA[17]_i_6_n_0\ : STD_LOGIC;
  signal \colsumYA[17]_i_7_n_0\ : STD_LOGIC;
  signal \colsumYA[17]_i_8_n_0\ : STD_LOGIC;
  signal \colsumYA[17]_i_9_n_0\ : STD_LOGIC;
  signal \colsumYA[18]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[19]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[1]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[20]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[21]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[22]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[23]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[24]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[25]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[26]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[27]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[28]_i_10_n_0\ : STD_LOGIC;
  signal \colsumYA[28]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[28]_i_3_n_0\ : STD_LOGIC;
  signal \colsumYA[28]_i_4_n_0\ : STD_LOGIC;
  signal \colsumYA[28]_i_5_n_0\ : STD_LOGIC;
  signal \colsumYA[28]_i_6_n_0\ : STD_LOGIC;
  signal \colsumYA[28]_i_7_n_0\ : STD_LOGIC;
  signal \colsumYA[28]_i_8_n_0\ : STD_LOGIC;
  signal \colsumYA[28]_i_9_n_0\ : STD_LOGIC;
  signal \colsumYA[29]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[2]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[30]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[31]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[32]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[33]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[34]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[35]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[36]_i_10_n_0\ : STD_LOGIC;
  signal \colsumYA[36]_i_11_n_0\ : STD_LOGIC;
  signal \colsumYA[36]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[36]_i_3_n_0\ : STD_LOGIC;
  signal \colsumYA[36]_i_4_n_0\ : STD_LOGIC;
  signal \colsumYA[36]_i_5_n_0\ : STD_LOGIC;
  signal \colsumYA[36]_i_6_n_0\ : STD_LOGIC;
  signal \colsumYA[36]_i_7_n_0\ : STD_LOGIC;
  signal \colsumYA[36]_i_8_n_0\ : STD_LOGIC;
  signal \colsumYA[36]_i_9_n_0\ : STD_LOGIC;
  signal \colsumYA[37]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[3]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[4]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[5]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[6]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[8]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[9]_i_10_n_0\ : STD_LOGIC;
  signal \colsumYA[9]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYA[9]_i_3_n_0\ : STD_LOGIC;
  signal \colsumYA[9]_i_4_n_0\ : STD_LOGIC;
  signal \colsumYA[9]_i_5_n_0\ : STD_LOGIC;
  signal \colsumYA[9]_i_6_n_0\ : STD_LOGIC;
  signal \colsumYA[9]_i_7_n_0\ : STD_LOGIC;
  signal \colsumYA[9]_i_8_n_0\ : STD_LOGIC;
  signal \colsumYA[9]_i_9_n_0\ : STD_LOGIC;
  signal \colsumYA_reg[17]_i_2_n_0\ : STD_LOGIC;
  signal \colsumYA_reg[17]_i_2_n_1\ : STD_LOGIC;
  signal \colsumYA_reg[17]_i_2_n_2\ : STD_LOGIC;
  signal \colsumYA_reg[17]_i_2_n_3\ : STD_LOGIC;
  signal \colsumYA_reg[17]_i_2_n_4\ : STD_LOGIC;
  signal \colsumYA_reg[17]_i_2_n_5\ : STD_LOGIC;
  signal \colsumYA_reg[17]_i_2_n_6\ : STD_LOGIC;
  signal \colsumYA_reg[17]_i_2_n_7\ : STD_LOGIC;
  signal \colsumYA_reg[18]_i_2_n_7\ : STD_LOGIC;
  signal \colsumYA_reg[28]_i_2_n_0\ : STD_LOGIC;
  signal \colsumYA_reg[28]_i_2_n_1\ : STD_LOGIC;
  signal \colsumYA_reg[28]_i_2_n_2\ : STD_LOGIC;
  signal \colsumYA_reg[28]_i_2_n_3\ : STD_LOGIC;
  signal \colsumYA_reg[28]_i_2_n_4\ : STD_LOGIC;
  signal \colsumYA_reg[28]_i_2_n_5\ : STD_LOGIC;
  signal \colsumYA_reg[28]_i_2_n_6\ : STD_LOGIC;
  signal \colsumYA_reg[28]_i_2_n_7\ : STD_LOGIC;
  signal \colsumYA_reg[36]_i_2_n_0\ : STD_LOGIC;
  signal \colsumYA_reg[36]_i_2_n_1\ : STD_LOGIC;
  signal \colsumYA_reg[36]_i_2_n_2\ : STD_LOGIC;
  signal \colsumYA_reg[36]_i_2_n_3\ : STD_LOGIC;
  signal \colsumYA_reg[36]_i_2_n_4\ : STD_LOGIC;
  signal \colsumYA_reg[36]_i_2_n_5\ : STD_LOGIC;
  signal \colsumYA_reg[36]_i_2_n_6\ : STD_LOGIC;
  signal \colsumYA_reg[36]_i_2_n_7\ : STD_LOGIC;
  signal \colsumYA_reg[37]_i_2_n_7\ : STD_LOGIC;
  signal \colsumYA_reg[9]_i_2_n_0\ : STD_LOGIC;
  signal \colsumYA_reg[9]_i_2_n_1\ : STD_LOGIC;
  signal \colsumYA_reg[9]_i_2_n_2\ : STD_LOGIC;
  signal \colsumYA_reg[9]_i_2_n_3\ : STD_LOGIC;
  signal \colsumYA_reg[9]_i_2_n_4\ : STD_LOGIC;
  signal \colsumYA_reg[9]_i_2_n_5\ : STD_LOGIC;
  signal \colsumYA_reg[9]_i_2_n_6\ : STD_LOGIC;
  signal \colsumYA_reg[9]_i_2_n_7\ : STD_LOGIC;
  signal colsumYB : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal \colsumYB[15]_i_10_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_11_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_12_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_13_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_14_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_15_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_16_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_17_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_2_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_3_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_4_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_5_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_6_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_7_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_8_n_0\ : STD_LOGIC;
  signal \colsumYB[15]_i_9_n_0\ : STD_LOGIC;
  signal \colsumYB[19]_i_2_n_0\ : STD_LOGIC;
  signal \colsumYB[19]_i_3_n_0\ : STD_LOGIC;
  signal \colsumYB[19]_i_4_n_0\ : STD_LOGIC;
  signal \colsumYB[19]_i_5_n_0\ : STD_LOGIC;
  signal \colsumYB[19]_i_6_n_0\ : STD_LOGIC;
  signal \colsumYB[19]_i_7_n_0\ : STD_LOGIC;
  signal \colsumYB[19]_i_8_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_10_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_11_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_12_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_13_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_14_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_15_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_16_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_17_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_2_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_3_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_4_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_5_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_6_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_7_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_8_n_0\ : STD_LOGIC;
  signal \colsumYB[7]_i_9_n_0\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \colsumYB_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \colsumYB_reg[19]_i_1_n_12\ : STD_LOGIC;
  signal \colsumYB_reg[19]_i_1_n_13\ : STD_LOGIC;
  signal \colsumYB_reg[19]_i_1_n_14\ : STD_LOGIC;
  signal \colsumYB_reg[19]_i_1_n_15\ : STD_LOGIC;
  signal \colsumYB_reg[19]_i_1_n_5\ : STD_LOGIC;
  signal \colsumYB_reg[19]_i_1_n_6\ : STD_LOGIC;
  signal \colsumYB_reg[19]_i_1_n_7\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \colsumYB_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal \colsumYC[15]_i_10_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_11_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_12_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_13_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_14_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_15_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_16_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_17_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_2_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_3_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_4_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_5_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_6_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_7_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_8_n_0\ : STD_LOGIC;
  signal \colsumYC[15]_i_9_n_0\ : STD_LOGIC;
  signal \colsumYC[20]_i_10_n_0\ : STD_LOGIC;
  signal \colsumYC[20]_i_2_n_0\ : STD_LOGIC;
  signal \colsumYC[20]_i_3_n_0\ : STD_LOGIC;
  signal \colsumYC[20]_i_4_n_0\ : STD_LOGIC;
  signal \colsumYC[20]_i_5_n_0\ : STD_LOGIC;
  signal \colsumYC[20]_i_6_n_0\ : STD_LOGIC;
  signal \colsumYC[20]_i_7_n_0\ : STD_LOGIC;
  signal \colsumYC[20]_i_8_n_0\ : STD_LOGIC;
  signal \colsumYC[20]_i_9_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_10_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_11_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_12_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_13_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_14_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_15_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_16_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_2_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_3_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_4_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_5_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_6_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_7_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_8_n_0\ : STD_LOGIC;
  signal \colsumYC[7]_i_9_n_0\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \colsumYC_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \colsumYC_reg[20]_i_1_n_11\ : STD_LOGIC;
  signal \colsumYC_reg[20]_i_1_n_12\ : STD_LOGIC;
  signal \colsumYC_reg[20]_i_1_n_13\ : STD_LOGIC;
  signal \colsumYC_reg[20]_i_1_n_14\ : STD_LOGIC;
  signal \colsumYC_reg[20]_i_1_n_15\ : STD_LOGIC;
  signal \colsumYC_reg[20]_i_1_n_4\ : STD_LOGIC;
  signal \colsumYC_reg[20]_i_1_n_5\ : STD_LOGIC;
  signal \colsumYC_reg[20]_i_1_n_6\ : STD_LOGIC;
  signal \colsumYC_reg[20]_i_1_n_7\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \colsumYC_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal \colsumY[100]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[101]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[102]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[103]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[104]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[21]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[22]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[23]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[24]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[25]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[26]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[27]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[28]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[29]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[30]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[31]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[32]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[33]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[34]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[35]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[36]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[37]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[38]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[39]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[40]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[41]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[84]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[85]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[86]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[87]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[88]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[89]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[90]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[91]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[92]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[93]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[94]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[95]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[96]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[97]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[98]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY[99]_i_1_n_0\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[0]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[100]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[101]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[102]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[103]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[104]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[10]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[11]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[12]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[13]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[14]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[15]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[16]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[17]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[18]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[19]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[1]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[20]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[21]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[22]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[23]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[24]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[25]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[26]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[27]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[28]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[29]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[2]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[30]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[31]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[32]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[33]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[34]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[35]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[36]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[37]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[38]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[39]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[3]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[40]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[41]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[42]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[43]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[44]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[45]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[46]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[47]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[48]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[49]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[4]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[50]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[51]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[52]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[53]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[54]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[55]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[56]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[57]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[58]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[59]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[5]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[60]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[61]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[62]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[63]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[64]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[65]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[66]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[67]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[68]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[69]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[6]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[70]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[71]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[72]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[73]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[74]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[75]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[76]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[77]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[78]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[79]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[7]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[80]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[81]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[82]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[83]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[84]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[85]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[86]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[87]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[88]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[89]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[8]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[90]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[91]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[92]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[93]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[94]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[95]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[96]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[97]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[98]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[99]\ : STD_LOGIC;
  signal \colsumY_reg_n_0_[9]\ : STD_LOGIC;
  signal \dIgrm1[0]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[10]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[11]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[12]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[13]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[14]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[15]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[16]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[17]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[18]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[19]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[1]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[20]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[21]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[22]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[23]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[24]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[25]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[26]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[27]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[28]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[29]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[2]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[30]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[31]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[32]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[33]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[34]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[35]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[36]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[37]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[38]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[39]_i_2_n_0\ : STD_LOGIC;
  signal \dIgrm1[3]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[4]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[5]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[6]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[7]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[8]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1[9]_i_1_n_0\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[0]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[10]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[11]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[12]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[13]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[14]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[15]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[16]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[17]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[18]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[19]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[1]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[20]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[21]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[22]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[23]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[24]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[25]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[26]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[27]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[28]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[29]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[2]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[30]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[31]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[32]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[33]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[34]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[35]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[36]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[37]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[38]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[39]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[3]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[4]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[5]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[6]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[7]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[8]\ : STD_LOGIC;
  signal \dIgrm1_reg_n_0_[9]\ : STD_LOGIC;
  signal \dImd[39]_i_1_n_0\ : STD_LOGIC;
  signal \dImd[39]_i_3_n_0\ : STD_LOGIC;
  signal \dImd[39]_i_5_n_0\ : STD_LOGIC;
  signal \dImd_reg_n_0_[0]\ : STD_LOGIC;
  signal \dImd_reg_n_0_[1]\ : STD_LOGIC;
  signal \dImd_reg_n_0_[2]\ : STD_LOGIC;
  signal \dImd_reg_n_0_[3]\ : STD_LOGIC;
  signal \dImd_reg_n_0_[4]\ : STD_LOGIC;
  signal \dImd_reg_n_0_[5]\ : STD_LOGIC;
  signal \dImd_reg_n_0_[6]\ : STD_LOGIC;
  signal \dImd_reg_n_0_[7]\ : STD_LOGIC;
  signal data0 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal data1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal data2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal data3 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal diffI_II : STD_LOGIC_VECTOR ( 46 downto 0 );
  signal \diffI_II[15]_i_10_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_11_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_12_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_13_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_14_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_15_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_16_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_17_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_2_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_3_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_4_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_5_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_6_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_7_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_8_n_0\ : STD_LOGIC;
  signal \diffI_II[15]_i_9_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_10_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_11_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_12_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_13_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_14_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_15_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_16_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_17_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_2_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_3_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_4_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_5_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_6_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_7_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_8_n_0\ : STD_LOGIC;
  signal \diffI_II[23]_i_9_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_10_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_11_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_12_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_13_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_14_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_15_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_16_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_17_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_2_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_3_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_4_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_5_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_6_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_7_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_8_n_0\ : STD_LOGIC;
  signal \diffI_II[31]_i_9_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_10_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_11_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_12_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_13_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_14_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_15_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_16_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_17_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_2_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_3_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_4_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_5_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_6_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_7_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_8_n_0\ : STD_LOGIC;
  signal \diffI_II[39]_i_9_n_0\ : STD_LOGIC;
  signal \diffI_II[46]_i_10_n_0\ : STD_LOGIC;
  signal \diffI_II[46]_i_11_n_0\ : STD_LOGIC;
  signal \diffI_II[46]_i_12_n_0\ : STD_LOGIC;
  signal \diffI_II[46]_i_13_n_0\ : STD_LOGIC;
  signal \diffI_II[46]_i_14_n_0\ : STD_LOGIC;
  signal \diffI_II[46]_i_2_n_0\ : STD_LOGIC;
  signal \diffI_II[46]_i_3_n_0\ : STD_LOGIC;
  signal \diffI_II[46]_i_4_n_0\ : STD_LOGIC;
  signal \diffI_II[46]_i_5_n_0\ : STD_LOGIC;
  signal \diffI_II[46]_i_6_n_0\ : STD_LOGIC;
  signal \diffI_II[46]_i_7_n_0\ : STD_LOGIC;
  signal \diffI_II[46]_i_8_n_0\ : STD_LOGIC;
  signal \diffI_II[46]_i_9_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_10_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_11_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_12_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_13_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_14_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_15_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_16_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_17_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_2_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_3_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_4_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_5_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_6_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_7_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_8_n_0\ : STD_LOGIC;
  signal \diffI_II[7]_i_9_n_0\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \diffI_II_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_1\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_10\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_11\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_12\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_13\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_14\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_15\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_2\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_3\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_4\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_5\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_6\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_7\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_8\ : STD_LOGIC;
  signal \diffI_II_reg[23]_i_1_n_9\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_1\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_10\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_11\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_12\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_13\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_14\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_15\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_2\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_3\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_4\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_5\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_6\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_7\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_8\ : STD_LOGIC;
  signal \diffI_II_reg[31]_i_1_n_9\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_1\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_10\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_11\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_12\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_13\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_14\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_15\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_2\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_3\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_4\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_5\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_6\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_7\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_8\ : STD_LOGIC;
  signal \diffI_II_reg[39]_i_1_n_9\ : STD_LOGIC;
  signal \diffI_II_reg[46]_i_1_n_10\ : STD_LOGIC;
  signal \diffI_II_reg[46]_i_1_n_11\ : STD_LOGIC;
  signal \diffI_II_reg[46]_i_1_n_12\ : STD_LOGIC;
  signal \diffI_II_reg[46]_i_1_n_13\ : STD_LOGIC;
  signal \diffI_II_reg[46]_i_1_n_14\ : STD_LOGIC;
  signal \diffI_II_reg[46]_i_1_n_15\ : STD_LOGIC;
  signal \diffI_II_reg[46]_i_1_n_2\ : STD_LOGIC;
  signal \diffI_II_reg[46]_i_1_n_3\ : STD_LOGIC;
  signal \diffI_II_reg[46]_i_1_n_4\ : STD_LOGIC;
  signal \diffI_II_reg[46]_i_1_n_5\ : STD_LOGIC;
  signal \diffI_II_reg[46]_i_1_n_6\ : STD_LOGIC;
  signal \diffI_II_reg[46]_i_1_n_7\ : STD_LOGIC;
  signal \diffI_II_reg[46]_i_1_n_9\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \diffI_II_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal diffI_IIp1 : STD_LOGIC_VECTOR ( 46 downto 0 );
  signal \diffI_IIp1[0]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[10]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[11]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[12]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[13]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[14]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[15]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[16]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[17]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[18]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[19]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[1]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[20]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[21]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[22]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[23]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[24]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[25]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[26]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[27]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[28]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[29]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[2]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[30]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[31]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[32]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[33]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[34]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[35]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[36]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[37]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[38]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[39]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[3]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[40]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[41]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[42]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[43]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[44]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[45]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[46]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[4]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[5]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[6]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[7]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[8]_i_1_n_0\ : STD_LOGIC;
  signal \diffI_IIp1[9]_i_1_n_0\ : STD_LOGIC;
  signal drdImd0bufB : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal drdImd1bufB : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal drdImd2bufB : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal drdImd3bufB : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal drdImd4bufB : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \dwrCoobuf[0]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[10]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[16]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[17]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[18]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[19]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[1]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[20]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[21]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[22]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[23]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[24]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[25]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[26]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[2]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_100_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_101_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_103_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_104_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_105_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_106_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_107_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_108_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_109_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_110_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_12_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_13_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_16_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_18_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_19_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_20_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_21_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_22_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_23_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_24_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_25_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_26_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_27_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_28_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_29_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_2_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_30_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_31_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_32_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_33_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_34_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_35_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_36_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_37_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_38_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_39_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_3_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_40_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_41_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_42_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_43_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_44_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_45_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_46_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_47_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_48_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_49_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_4_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_50_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_51_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_52_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_53_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_54_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_55_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_56_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_57_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_58_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_59_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_5_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_60_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_61_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_62_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_63_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_64_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_65_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_66_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_68_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_69_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_6_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_70_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_71_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_72_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_73_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_74_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_75_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_76_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_77_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_78_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_79_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_7_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_80_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_81_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_82_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_83_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_84_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_85_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_86_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_87_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_88_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_89_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_90_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_91_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_92_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_93_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_94_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_95_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_96_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_97_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_98_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[31]_i_99_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[3]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[4]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[5]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[6]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[7]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[8]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf[9]_i_1_n_0\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_102_n_5\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_102_n_6\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_102_n_7\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_10_n_3\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_10_n_4\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_10_n_5\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_10_n_6\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_10_n_7\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_11_n_3\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_11_n_4\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_11_n_5\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_11_n_6\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_11_n_7\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_14_n_5\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_14_n_6\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_14_n_7\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_15_n_5\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_15_n_6\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_15_n_7\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_17_n_5\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_17_n_6\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_17_n_7\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_67_n_5\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_67_n_6\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_67_n_7\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_8_n_3\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_8_n_4\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_8_n_5\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_8_n_6\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_8_n_7\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_9_n_3\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_9_n_4\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_9_n_5\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_9_n_6\ : STD_LOGIC;
  signal \dwrCoobuf_reg[31]_i_9_n_7\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[0]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[10]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[16]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[17]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[18]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[19]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[1]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[20]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[21]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[22]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[23]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[24]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[25]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[26]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[2]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[31]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[3]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[4]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[5]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[6]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[7]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[8]\ : STD_LOGIC;
  signal \dwrCoobuf_reg_n_0_[9]\ : STD_LOGIC;
  signal \dx[0]_i_1_n_0\ : STD_LOGIC;
  signal \dx[10]_i_1_n_0\ : STD_LOGIC;
  signal \dx[11]_i_1_n_0\ : STD_LOGIC;
  signal \dx[11]_i_2_n_0\ : STD_LOGIC;
  signal \dx[12]_i_1_n_0\ : STD_LOGIC;
  signal \dx[13]_i_1_n_0\ : STD_LOGIC;
  signal \dx[13]_i_2_n_0\ : STD_LOGIC;
  signal \dx[14]_i_1_n_0\ : STD_LOGIC;
  signal \dx[15]_i_1_n_0\ : STD_LOGIC;
  signal \dx[15]_i_2_n_0\ : STD_LOGIC;
  signal \dx[16]_i_1_n_0\ : STD_LOGIC;
  signal \dx[17]_i_1_n_0\ : STD_LOGIC;
  signal \dx[17]_i_2_n_0\ : STD_LOGIC;
  signal \dx[18]_i_1_n_0\ : STD_LOGIC;
  signal \dx[19]_i_1_n_0\ : STD_LOGIC;
  signal \dx[1]_i_1_n_0\ : STD_LOGIC;
  signal \dx[20]_i_1_n_0\ : STD_LOGIC;
  signal \dx[20]_i_2_n_0\ : STD_LOGIC;
  signal \dx[21]_i_1_n_0\ : STD_LOGIC;
  signal \dx[22]_i_1_n_0\ : STD_LOGIC;
  signal \dx[22]_i_2_n_0\ : STD_LOGIC;
  signal \dx[23]_i_1_n_0\ : STD_LOGIC;
  signal \dx[24]_i_1_n_0\ : STD_LOGIC;
  signal \dx[24]_i_2_n_0\ : STD_LOGIC;
  signal \dx[25]_i_1_n_0\ : STD_LOGIC;
  signal \dx[26]_i_1_n_0\ : STD_LOGIC;
  signal \dx[26]_i_2_n_0\ : STD_LOGIC;
  signal \dx[27]_i_1_n_0\ : STD_LOGIC;
  signal \dx[28]_i_1_n_0\ : STD_LOGIC;
  signal \dx[29]_i_1_n_0\ : STD_LOGIC;
  signal \dx[29]_i_2_n_0\ : STD_LOGIC;
  signal \dx[2]_i_1_n_0\ : STD_LOGIC;
  signal \dx[2]_i_2_n_0\ : STD_LOGIC;
  signal \dx[30]_i_1_n_0\ : STD_LOGIC;
  signal \dx[31]_i_1_n_0\ : STD_LOGIC;
  signal \dx[31]_i_2_n_0\ : STD_LOGIC;
  signal \dx[32]_i_1_n_0\ : STD_LOGIC;
  signal \dx[33]_i_1_n_0\ : STD_LOGIC;
  signal \dx[33]_i_2_n_0\ : STD_LOGIC;
  signal \dx[34]_i_1_n_0\ : STD_LOGIC;
  signal \dx[35]_i_1_n_0\ : STD_LOGIC;
  signal \dx[35]_i_2_n_0\ : STD_LOGIC;
  signal \dx[36]_i_1_n_0\ : STD_LOGIC;
  signal \dx[37]_i_1_n_0\ : STD_LOGIC;
  signal \dx[38]_i_1_n_0\ : STD_LOGIC;
  signal \dx[38]_i_2_n_0\ : STD_LOGIC;
  signal \dx[39]_i_1_n_0\ : STD_LOGIC;
  signal \dx[3]_i_1_n_0\ : STD_LOGIC;
  signal \dx[40]_i_1_n_0\ : STD_LOGIC;
  signal \dx[40]_i_2_n_0\ : STD_LOGIC;
  signal \dx[41]_i_1_n_0\ : STD_LOGIC;
  signal \dx[42]_i_1_n_0\ : STD_LOGIC;
  signal \dx[42]_i_2_n_0\ : STD_LOGIC;
  signal \dx[43]_i_1_n_0\ : STD_LOGIC;
  signal \dx[44]_i_1_n_0\ : STD_LOGIC;
  signal \dx[44]_i_2_n_0\ : STD_LOGIC;
  signal \dx[4]_i_1_n_0\ : STD_LOGIC;
  signal \dx[4]_i_2_n_0\ : STD_LOGIC;
  signal \dx[5]_i_1_n_0\ : STD_LOGIC;
  signal \dx[6]_i_1_n_0\ : STD_LOGIC;
  signal \dx[6]_i_2_n_0\ : STD_LOGIC;
  signal \dx[7]_i_1_n_0\ : STD_LOGIC;
  signal \dx[8]_i_1_n_0\ : STD_LOGIC;
  signal \dx[8]_i_2_n_0\ : STD_LOGIC;
  signal \dx[9]_i_1_n_0\ : STD_LOGIC;
  signal \dx_reg_n_0_[0]\ : STD_LOGIC;
  signal \dx_reg_n_0_[18]\ : STD_LOGIC;
  signal \dx_reg_n_0_[19]\ : STD_LOGIC;
  signal \dx_reg_n_0_[1]\ : STD_LOGIC;
  signal \dx_reg_n_0_[20]\ : STD_LOGIC;
  signal \dx_reg_n_0_[21]\ : STD_LOGIC;
  signal \dx_reg_n_0_[22]\ : STD_LOGIC;
  signal \dx_reg_n_0_[23]\ : STD_LOGIC;
  signal \dx_reg_n_0_[24]\ : STD_LOGIC;
  signal \dx_reg_n_0_[25]\ : STD_LOGIC;
  signal \dx_reg_n_0_[26]\ : STD_LOGIC;
  signal \dx_reg_n_0_[27]\ : STD_LOGIC;
  signal \dx_reg_n_0_[28]\ : STD_LOGIC;
  signal \dx_reg_n_0_[29]\ : STD_LOGIC;
  signal \dx_reg_n_0_[2]\ : STD_LOGIC;
  signal \dx_reg_n_0_[30]\ : STD_LOGIC;
  signal \dx_reg_n_0_[31]\ : STD_LOGIC;
  signal \dx_reg_n_0_[32]\ : STD_LOGIC;
  signal \dx_reg_n_0_[33]\ : STD_LOGIC;
  signal \dx_reg_n_0_[34]\ : STD_LOGIC;
  signal \dx_reg_n_0_[35]\ : STD_LOGIC;
  signal \dx_reg_n_0_[36]\ : STD_LOGIC;
  signal \dx_reg_n_0_[37]\ : STD_LOGIC;
  signal \dx_reg_n_0_[38]\ : STD_LOGIC;
  signal \dx_reg_n_0_[39]\ : STD_LOGIC;
  signal \dx_reg_n_0_[3]\ : STD_LOGIC;
  signal \dx_reg_n_0_[40]\ : STD_LOGIC;
  signal \dx_reg_n_0_[41]\ : STD_LOGIC;
  signal \dx_reg_n_0_[42]\ : STD_LOGIC;
  signal \dx_reg_n_0_[43]\ : STD_LOGIC;
  signal \dx_reg_n_0_[44]\ : STD_LOGIC;
  signal \dx_reg_n_0_[4]\ : STD_LOGIC;
  signal \dx_reg_n_0_[5]\ : STD_LOGIC;
  signal \dx_reg_n_0_[6]\ : STD_LOGIC;
  signal \dx_reg_n_0_[7]\ : STD_LOGIC;
  signal \dx_reg_n_0_[8]\ : STD_LOGIC;
  signal dy : STD_LOGIC;
  signal \dy_reg_n_0_[0]\ : STD_LOGIC;
  signal \dy_reg_n_0_[18]\ : STD_LOGIC;
  signal \dy_reg_n_0_[19]\ : STD_LOGIC;
  signal \dy_reg_n_0_[1]\ : STD_LOGIC;
  signal \dy_reg_n_0_[20]\ : STD_LOGIC;
  signal \dy_reg_n_0_[21]\ : STD_LOGIC;
  signal \dy_reg_n_0_[22]\ : STD_LOGIC;
  signal \dy_reg_n_0_[23]\ : STD_LOGIC;
  signal \dy_reg_n_0_[24]\ : STD_LOGIC;
  signal \dy_reg_n_0_[25]\ : STD_LOGIC;
  signal \dy_reg_n_0_[26]\ : STD_LOGIC;
  signal \dy_reg_n_0_[27]\ : STD_LOGIC;
  signal \dy_reg_n_0_[28]\ : STD_LOGIC;
  signal \dy_reg_n_0_[29]\ : STD_LOGIC;
  signal \dy_reg_n_0_[2]\ : STD_LOGIC;
  signal \dy_reg_n_0_[30]\ : STD_LOGIC;
  signal \dy_reg_n_0_[31]\ : STD_LOGIC;
  signal \dy_reg_n_0_[32]\ : STD_LOGIC;
  signal \dy_reg_n_0_[33]\ : STD_LOGIC;
  signal \dy_reg_n_0_[34]\ : STD_LOGIC;
  signal \dy_reg_n_0_[35]\ : STD_LOGIC;
  signal \dy_reg_n_0_[36]\ : STD_LOGIC;
  signal \dy_reg_n_0_[37]\ : STD_LOGIC;
  signal \dy_reg_n_0_[38]\ : STD_LOGIC;
  signal \dy_reg_n_0_[39]\ : STD_LOGIC;
  signal \dy_reg_n_0_[3]\ : STD_LOGIC;
  signal \dy_reg_n_0_[40]\ : STD_LOGIC;
  signal \dy_reg_n_0_[41]\ : STD_LOGIC;
  signal \dy_reg_n_0_[42]\ : STD_LOGIC;
  signal \dy_reg_n_0_[43]\ : STD_LOGIC;
  signal \dy_reg_n_0_[44]\ : STD_LOGIC;
  signal \dy_reg_n_0_[4]\ : STD_LOGIC;
  signal \dy_reg_n_0_[5]\ : STD_LOGIC;
  signal \dy_reg_n_0_[6]\ : STD_LOGIC;
  signal \dy_reg_n_0_[7]\ : STD_LOGIC;
  signal \dy_reg_n_0_[8]\ : STD_LOGIC;
  signal enCoobufB : STD_LOGIC;
  signal enCoobuf_i_1_n_0 : STD_LOGIC;
  signal enCoobuf_reg_n_0 : STD_LOGIC;
  signal enImdbuf_i_1_n_0 : STD_LOGIC;
  signal enImdbuf_reg_n_0 : STD_LOGIC;
  signal fghij : STD_LOGIC_VECTOR ( 30 downto 0 );
  signal fghij0 : STD_LOGIC_VECTOR ( 30 downto 1 );
  signal \fghij[0]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[10]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[11]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[12]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[13]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[14]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[15]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[16]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[17]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[18]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[19]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[1]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[20]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[21]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[22]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[23]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[24]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[25]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[26]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[27]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[28]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[29]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[2]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[30]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[30]_i_2_n_0\ : STD_LOGIC;
  signal \fghij[3]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[4]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[5]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[6]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[7]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[8]_i_1_n_0\ : STD_LOGIC;
  signal \fghij[9]_i_1_n_0\ : STD_LOGIC;
  signal \fghij_reg[16]_i_2_n_0\ : STD_LOGIC;
  signal \fghij_reg[16]_i_2_n_1\ : STD_LOGIC;
  signal \fghij_reg[16]_i_2_n_2\ : STD_LOGIC;
  signal \fghij_reg[16]_i_2_n_3\ : STD_LOGIC;
  signal \fghij_reg[16]_i_2_n_4\ : STD_LOGIC;
  signal \fghij_reg[16]_i_2_n_5\ : STD_LOGIC;
  signal \fghij_reg[16]_i_2_n_6\ : STD_LOGIC;
  signal \fghij_reg[16]_i_2_n_7\ : STD_LOGIC;
  signal \fghij_reg[24]_i_2_n_0\ : STD_LOGIC;
  signal \fghij_reg[24]_i_2_n_1\ : STD_LOGIC;
  signal \fghij_reg[24]_i_2_n_2\ : STD_LOGIC;
  signal \fghij_reg[24]_i_2_n_3\ : STD_LOGIC;
  signal \fghij_reg[24]_i_2_n_4\ : STD_LOGIC;
  signal \fghij_reg[24]_i_2_n_5\ : STD_LOGIC;
  signal \fghij_reg[24]_i_2_n_6\ : STD_LOGIC;
  signal \fghij_reg[24]_i_2_n_7\ : STD_LOGIC;
  signal \fghij_reg[30]_i_3_n_3\ : STD_LOGIC;
  signal \fghij_reg[30]_i_3_n_4\ : STD_LOGIC;
  signal \fghij_reg[30]_i_3_n_5\ : STD_LOGIC;
  signal \fghij_reg[30]_i_3_n_6\ : STD_LOGIC;
  signal \fghij_reg[30]_i_3_n_7\ : STD_LOGIC;
  signal \fghij_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \fghij_reg[8]_i_2_n_1\ : STD_LOGIC;
  signal \fghij_reg[8]_i_2_n_2\ : STD_LOGIC;
  signal \fghij_reg[8]_i_2_n_3\ : STD_LOGIC;
  signal \fghij_reg[8]_i_2_n_4\ : STD_LOGIC;
  signal \fghij_reg[8]_i_2_n_5\ : STD_LOGIC;
  signal \fghij_reg[8]_i_2_n_6\ : STD_LOGIC;
  signal \fghij_reg[8]_i_2_n_7\ : STD_LOGIC;
  signal flag1 : STD_LOGIC;
  signal flag2 : STD_LOGIC;
  signal flag234_in : STD_LOGIC;
  signal flag238_in : STD_LOGIC;
  signal flag241_in : STD_LOGIC;
  signal flag3 : STD_LOGIC;
  signal flag4 : STD_LOGIC;
  signal flag5 : STD_LOGIC;
  signal flag52_in : STD_LOGIC;
  signal \i[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \i[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \i[1]_i_2_n_0\ : STD_LOGIC;
  signal \i[1]_i_3_n_0\ : STD_LOGIC;
  signal \i__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ixMax : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \ixMax[2]_i_10_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_11_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_12_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_13_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_14_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_15_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_16_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_17_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_18_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_19_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_20_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_21_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_22_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_23_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_24_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_25_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_26_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_27_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_28_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_29_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_2_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_30_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_31_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_32_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_33_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_34_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_35_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_36_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_37_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_38_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_39_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_3_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_40_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_41_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_42_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_43_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_44_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_45_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_46_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_47_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_48_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_49_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_4_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_50_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_51_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_52_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_53_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_54_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_55_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_56_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_57_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_58_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_59_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_5_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_60_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_61_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_62_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_63_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_64_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_6_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_7_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_8_n_0\ : STD_LOGIC;
  signal \ixMax[2]_i_9_n_0\ : STD_LOGIC;
  signal \ixMax_reg_n_0_[0]\ : STD_LOGIC;
  signal \ixMax_reg_n_0_[1]\ : STD_LOGIC;
  signal \ixMax_reg_n_0_[2]\ : STD_LOGIC;
  signal lat : STD_LOGIC_VECTOR ( 4 to 4 );
  signal \lat[4]_i_1_n_0\ : STD_LOGIC;
  signal linNotLog_reg_n_0 : STD_LOGIC;
  signal \maximds[0][7]_i_1_n_0\ : STD_LOGIC;
  signal \maximds[0]_40\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \maximds[1][7]_i_1_n_0\ : STD_LOGIC;
  signal \maximds[2][7]_i_1_n_0\ : STD_LOGIC;
  signal \maximds[3][7]_i_1_n_0\ : STD_LOGIC;
  signal \maximds[4][0]_i_2_n_0\ : STD_LOGIC;
  signal \maximds[4][1]_i_2_n_0\ : STD_LOGIC;
  signal \maximds[4][2]_i_2_n_0\ : STD_LOGIC;
  signal \maximds[4][3]_i_2_n_0\ : STD_LOGIC;
  signal \maximds[4][4]_i_2_n_0\ : STD_LOGIC;
  signal \maximds[4][5]_i_2_n_0\ : STD_LOGIC;
  signal \maximds[4][6]_i_2_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_10_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_11_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_12_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_13_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_14_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_15_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_16_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_17_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_18_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_19_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_1_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_20_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_21_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_22_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_23_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_24_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_25_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_26_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_27_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_28_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_29_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_30_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_31_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_32_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_33_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_34_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_35_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_36_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_37_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_38_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_39_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_3_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_40_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_41_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_42_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_43_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_44_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_45_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_46_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_47_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_48_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_49_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_4_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_50_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_51_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_52_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_53_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_54_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_55_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_56_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_57_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_58_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_59_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_5_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_60_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_61_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_62_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_63_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_64_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_65_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_66_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_67_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_68_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_69_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_6_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_7_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_8_n_0\ : STD_LOGIC;
  signal \maximds[4][7]_i_9_n_0\ : STD_LOGIC;
  signal \maximds_reg_n_0_[0][0]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[0][1]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[0][2]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[0][3]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[0][4]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[0][5]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[0][6]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[0][7]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[1][0]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[1][1]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[1][2]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[1][3]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[1][4]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[1][5]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[1][6]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[1][7]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[2][0]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[2][1]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[2][2]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[2][3]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[2][4]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[2][5]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[2][6]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[2][7]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[3][0]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[3][1]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[3][2]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[3][3]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[3][4]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[3][5]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[3][6]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[3][7]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[4][0]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[4][1]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[4][2]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[4][3]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[4][4]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[4][5]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[4][6]\ : STD_LOGIC;
  signal \maximds_reg_n_0_[4][7]\ : STD_LOGIC;
  signal \maximdsm1_reg[0]0\ : STD_LOGIC;
  signal \maximdsm1_reg[0]_36\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \maximdsm1_reg[1]_35\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \maximdsm1_reg[2]_39\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \maximdsm1_reg[3]_38\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \maximdsm1_reg[4]_37\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal msb : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal msb0 : STD_LOGIC;
  signal \msb[0]_i_10_n_0\ : STD_LOGIC;
  signal \msb[0]_i_11_n_0\ : STD_LOGIC;
  signal \msb[0]_i_12_n_0\ : STD_LOGIC;
  signal \msb[0]_i_13_n_0\ : STD_LOGIC;
  signal \msb[0]_i_1_n_0\ : STD_LOGIC;
  signal \msb[0]_i_2_n_0\ : STD_LOGIC;
  signal \msb[0]_i_3_n_0\ : STD_LOGIC;
  signal \msb[0]_i_4_n_0\ : STD_LOGIC;
  signal \msb[0]_i_5_n_0\ : STD_LOGIC;
  signal \msb[0]_i_6_n_0\ : STD_LOGIC;
  signal \msb[0]_i_7_n_0\ : STD_LOGIC;
  signal \msb[0]_i_8_n_0\ : STD_LOGIC;
  signal \msb[0]_i_9_n_0\ : STD_LOGIC;
  signal \msb[1]_i_10_n_0\ : STD_LOGIC;
  signal \msb[1]_i_11_n_0\ : STD_LOGIC;
  signal \msb[1]_i_12_n_0\ : STD_LOGIC;
  signal \msb[1]_i_13_n_0\ : STD_LOGIC;
  signal \msb[1]_i_1_n_0\ : STD_LOGIC;
  signal \msb[1]_i_2_n_0\ : STD_LOGIC;
  signal \msb[1]_i_3_n_0\ : STD_LOGIC;
  signal \msb[1]_i_4_n_0\ : STD_LOGIC;
  signal \msb[1]_i_5_n_0\ : STD_LOGIC;
  signal \msb[1]_i_6_n_0\ : STD_LOGIC;
  signal \msb[1]_i_7_n_0\ : STD_LOGIC;
  signal \msb[1]_i_8_n_0\ : STD_LOGIC;
  signal \msb[1]_i_9_n_0\ : STD_LOGIC;
  signal \msb[2]_i_10_n_0\ : STD_LOGIC;
  signal \msb[2]_i_11_n_0\ : STD_LOGIC;
  signal \msb[2]_i_12_n_0\ : STD_LOGIC;
  signal \msb[2]_i_13_n_0\ : STD_LOGIC;
  signal \msb[2]_i_14_n_0\ : STD_LOGIC;
  signal \msb[2]_i_1_n_0\ : STD_LOGIC;
  signal \msb[2]_i_2_n_0\ : STD_LOGIC;
  signal \msb[2]_i_3_n_0\ : STD_LOGIC;
  signal \msb[2]_i_4_n_0\ : STD_LOGIC;
  signal \msb[2]_i_5_n_0\ : STD_LOGIC;
  signal \msb[2]_i_6_n_0\ : STD_LOGIC;
  signal \msb[2]_i_7_n_0\ : STD_LOGIC;
  signal \msb[2]_i_8_n_0\ : STD_LOGIC;
  signal \msb[2]_i_9_n_0\ : STD_LOGIC;
  signal \msb[3]_i_10_n_0\ : STD_LOGIC;
  signal \msb[3]_i_11_n_0\ : STD_LOGIC;
  signal \msb[3]_i_12_n_0\ : STD_LOGIC;
  signal \msb[3]_i_13_n_0\ : STD_LOGIC;
  signal \msb[3]_i_1_n_0\ : STD_LOGIC;
  signal \msb[3]_i_2_n_0\ : STD_LOGIC;
  signal \msb[3]_i_3_n_0\ : STD_LOGIC;
  signal \msb[3]_i_4_n_0\ : STD_LOGIC;
  signal \msb[3]_i_5_n_0\ : STD_LOGIC;
  signal \msb[3]_i_6_n_0\ : STD_LOGIC;
  signal \msb[3]_i_7_n_0\ : STD_LOGIC;
  signal \msb[3]_i_8_n_0\ : STD_LOGIC;
  signal \msb[3]_i_9_n_0\ : STD_LOGIC;
  signal \msb[4]_i_1_n_0\ : STD_LOGIC;
  signal \msb[4]_i_2_n_0\ : STD_LOGIC;
  signal \msb[4]_i_3_n_0\ : STD_LOGIC;
  signal \msb[4]_i_4_n_0\ : STD_LOGIC;
  signal \msb[4]_i_5_n_0\ : STD_LOGIC;
  signal \msb[5]_i_2_n_0\ : STD_LOGIC;
  signal \msb[5]_i_3_n_0\ : STD_LOGIC;
  signal \msb[5]_i_4_n_0\ : STD_LOGIC;
  signal \msb[5]_i_5_n_0\ : STD_LOGIC;
  signal myImd0buf_n_10 : STD_LOGIC;
  signal myImd0buf_n_11 : STD_LOGIC;
  signal myImd0buf_n_12 : STD_LOGIC;
  signal myImd0buf_n_13 : STD_LOGIC;
  signal myImd0buf_n_14 : STD_LOGIC;
  signal myImd0buf_n_15 : STD_LOGIC;
  signal myImd0buf_n_8 : STD_LOGIC;
  signal myImd0buf_n_9 : STD_LOGIC;
  signal myImd1buf_n_10 : STD_LOGIC;
  signal myImd1buf_n_11 : STD_LOGIC;
  signal myImd1buf_n_12 : STD_LOGIC;
  signal myImd1buf_n_13 : STD_LOGIC;
  signal myImd1buf_n_14 : STD_LOGIC;
  signal myImd1buf_n_15 : STD_LOGIC;
  signal myImd1buf_n_16 : STD_LOGIC;
  signal myImd1buf_n_17 : STD_LOGIC;
  signal myImd1buf_n_18 : STD_LOGIC;
  signal myImd1buf_n_19 : STD_LOGIC;
  signal myImd1buf_n_8 : STD_LOGIC;
  signal myImd1buf_n_9 : STD_LOGIC;
  signal myImd2buf_n_10 : STD_LOGIC;
  signal myImd2buf_n_11 : STD_LOGIC;
  signal myImd2buf_n_12 : STD_LOGIC;
  signal myImd2buf_n_13 : STD_LOGIC;
  signal myImd2buf_n_14 : STD_LOGIC;
  signal myImd2buf_n_15 : STD_LOGIC;
  signal myImd2buf_n_8 : STD_LOGIC;
  signal myImd2buf_n_9 : STD_LOGIC;
  signal myImd3buf_n_10 : STD_LOGIC;
  signal myImd3buf_n_11 : STD_LOGIC;
  signal myImd3buf_n_12 : STD_LOGIC;
  signal myImd3buf_n_13 : STD_LOGIC;
  signal myImd3buf_n_14 : STD_LOGIC;
  signal myImd3buf_n_15 : STD_LOGIC;
  signal myImd3buf_n_8 : STD_LOGIC;
  signal myImd3buf_n_9 : STD_LOGIC;
  signal myImd4buf_n_10 : STD_LOGIC;
  signal myImd4buf_n_11 : STD_LOGIC;
  signal myImd4buf_n_12 : STD_LOGIC;
  signal myImd4buf_n_13 : STD_LOGIC;
  signal myImd4buf_n_14 : STD_LOGIC;
  signal myImd4buf_n_15 : STD_LOGIC;
  signal myImd4buf_n_16 : STD_LOGIC;
  signal myImd4buf_n_8 : STD_LOGIC;
  signal myImd4buf_n_9 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal p_0_out : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal postNotLive_i_1_n_0 : STD_LOGIC;
  signal postNotLive_reg_n_0 : STD_LOGIC;
  signal \postcol_lcl[0]_i_1_n_0\ : STD_LOGIC;
  signal \postcol_lcl[10]_i_1_n_0\ : STD_LOGIC;
  signal \postcol_lcl[10]_i_2_n_0\ : STD_LOGIC;
  signal \postcol_lcl[10]_i_3_n_0\ : STD_LOGIC;
  signal \postcol_lcl[10]_i_4_n_0\ : STD_LOGIC;
  signal \postcol_lcl[1]_i_1_n_0\ : STD_LOGIC;
  signal \postcol_lcl[2]_i_1_n_0\ : STD_LOGIC;
  signal \postcol_lcl[3]_i_1_n_0\ : STD_LOGIC;
  signal \postcol_lcl[4]_i_1_n_0\ : STD_LOGIC;
  signal \postcol_lcl[4]_i_2_n_0\ : STD_LOGIC;
  signal \postcol_lcl[5]_i_1_n_0\ : STD_LOGIC;
  signal \postcol_lcl[5]_i_2_n_0\ : STD_LOGIC;
  signal \postcol_lcl[6]_i_1_n_0\ : STD_LOGIC;
  signal \postcol_lcl[7]_i_1_n_0\ : STD_LOGIC;
  signal \postcol_lcl[8]_i_1_n_0\ : STD_LOGIC;
  signal \postcol_lcl[9]_i_1_n_0\ : STD_LOGIC;
  signal \postcol_lcl[9]_i_2_n_0\ : STD_LOGIC;
  signal \postcol_lcl[9]_i_3_n_0\ : STD_LOGIC;
  signal \postcol_lcl__0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \r[15]_i_10_n_0\ : STD_LOGIC;
  signal \r[15]_i_11_n_0\ : STD_LOGIC;
  signal \r[15]_i_12_n_0\ : STD_LOGIC;
  signal \r[15]_i_13_n_0\ : STD_LOGIC;
  signal \r[15]_i_14_n_0\ : STD_LOGIC;
  signal \r[15]_i_15_n_0\ : STD_LOGIC;
  signal \r[15]_i_16_n_0\ : STD_LOGIC;
  signal \r[15]_i_17_n_0\ : STD_LOGIC;
  signal \r[15]_i_2_n_0\ : STD_LOGIC;
  signal \r[15]_i_3_n_0\ : STD_LOGIC;
  signal \r[15]_i_4_n_0\ : STD_LOGIC;
  signal \r[15]_i_5_n_0\ : STD_LOGIC;
  signal \r[15]_i_6_n_0\ : STD_LOGIC;
  signal \r[15]_i_7_n_0\ : STD_LOGIC;
  signal \r[15]_i_8_n_0\ : STD_LOGIC;
  signal \r[15]_i_9_n_0\ : STD_LOGIC;
  signal \r[23]_i_10_n_0\ : STD_LOGIC;
  signal \r[23]_i_11_n_0\ : STD_LOGIC;
  signal \r[23]_i_12_n_0\ : STD_LOGIC;
  signal \r[23]_i_13_n_0\ : STD_LOGIC;
  signal \r[23]_i_14_n_0\ : STD_LOGIC;
  signal \r[23]_i_15_n_0\ : STD_LOGIC;
  signal \r[23]_i_16_n_0\ : STD_LOGIC;
  signal \r[23]_i_17_n_0\ : STD_LOGIC;
  signal \r[23]_i_2_n_0\ : STD_LOGIC;
  signal \r[23]_i_3_n_0\ : STD_LOGIC;
  signal \r[23]_i_4_n_0\ : STD_LOGIC;
  signal \r[23]_i_5_n_0\ : STD_LOGIC;
  signal \r[23]_i_6_n_0\ : STD_LOGIC;
  signal \r[23]_i_7_n_0\ : STD_LOGIC;
  signal \r[23]_i_8_n_0\ : STD_LOGIC;
  signal \r[23]_i_9_n_0\ : STD_LOGIC;
  signal \r[31]_i_10_n_0\ : STD_LOGIC;
  signal \r[31]_i_11_n_0\ : STD_LOGIC;
  signal \r[31]_i_12_n_0\ : STD_LOGIC;
  signal \r[31]_i_13_n_0\ : STD_LOGIC;
  signal \r[31]_i_14_n_0\ : STD_LOGIC;
  signal \r[31]_i_15_n_0\ : STD_LOGIC;
  signal \r[31]_i_16_n_0\ : STD_LOGIC;
  signal \r[31]_i_17_n_0\ : STD_LOGIC;
  signal \r[31]_i_2_n_0\ : STD_LOGIC;
  signal \r[31]_i_3_n_0\ : STD_LOGIC;
  signal \r[31]_i_4_n_0\ : STD_LOGIC;
  signal \r[31]_i_5_n_0\ : STD_LOGIC;
  signal \r[31]_i_6_n_0\ : STD_LOGIC;
  signal \r[31]_i_7_n_0\ : STD_LOGIC;
  signal \r[31]_i_8_n_0\ : STD_LOGIC;
  signal \r[31]_i_9_n_0\ : STD_LOGIC;
  signal \r[39]_i_10_n_0\ : STD_LOGIC;
  signal \r[39]_i_11_n_0\ : STD_LOGIC;
  signal \r[39]_i_12_n_0\ : STD_LOGIC;
  signal \r[39]_i_13_n_0\ : STD_LOGIC;
  signal \r[39]_i_14_n_0\ : STD_LOGIC;
  signal \r[39]_i_15_n_0\ : STD_LOGIC;
  signal \r[39]_i_16_n_0\ : STD_LOGIC;
  signal \r[39]_i_17_n_0\ : STD_LOGIC;
  signal \r[39]_i_2_n_0\ : STD_LOGIC;
  signal \r[39]_i_3_n_0\ : STD_LOGIC;
  signal \r[39]_i_4_n_0\ : STD_LOGIC;
  signal \r[39]_i_5_n_0\ : STD_LOGIC;
  signal \r[39]_i_6_n_0\ : STD_LOGIC;
  signal \r[39]_i_7_n_0\ : STD_LOGIC;
  signal \r[39]_i_8_n_0\ : STD_LOGIC;
  signal \r[39]_i_9_n_0\ : STD_LOGIC;
  signal \r[47]_i_10_n_0\ : STD_LOGIC;
  signal \r[47]_i_11_n_0\ : STD_LOGIC;
  signal \r[47]_i_12_n_0\ : STD_LOGIC;
  signal \r[47]_i_13_n_0\ : STD_LOGIC;
  signal \r[47]_i_14_n_0\ : STD_LOGIC;
  signal \r[47]_i_15_n_0\ : STD_LOGIC;
  signal \r[47]_i_16_n_0\ : STD_LOGIC;
  signal \r[47]_i_2_n_0\ : STD_LOGIC;
  signal \r[47]_i_3_n_0\ : STD_LOGIC;
  signal \r[47]_i_4_n_0\ : STD_LOGIC;
  signal \r[47]_i_5_n_0\ : STD_LOGIC;
  signal \r[47]_i_6_n_0\ : STD_LOGIC;
  signal \r[47]_i_7_n_0\ : STD_LOGIC;
  signal \r[47]_i_8_n_0\ : STD_LOGIC;
  signal \r[47]_i_9_n_0\ : STD_LOGIC;
  signal \r[7]_i_10_n_0\ : STD_LOGIC;
  signal \r[7]_i_11_n_0\ : STD_LOGIC;
  signal \r[7]_i_12_n_0\ : STD_LOGIC;
  signal \r[7]_i_13_n_0\ : STD_LOGIC;
  signal \r[7]_i_14_n_0\ : STD_LOGIC;
  signal \r[7]_i_15_n_0\ : STD_LOGIC;
  signal \r[7]_i_16_n_0\ : STD_LOGIC;
  signal \r[7]_i_17_n_0\ : STD_LOGIC;
  signal \r[7]_i_2_n_0\ : STD_LOGIC;
  signal \r[7]_i_3_n_0\ : STD_LOGIC;
  signal \r[7]_i_4_n_0\ : STD_LOGIC;
  signal \r[7]_i_5_n_0\ : STD_LOGIC;
  signal \r[7]_i_6_n_0\ : STD_LOGIC;
  signal \r[7]_i_7_n_0\ : STD_LOGIC;
  signal \r[7]_i_8_n_0\ : STD_LOGIC;
  signal \r[7]_i_9_n_0\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \r_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_0\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_1\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_10\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_11\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_12\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_13\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_14\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_15\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_2\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_3\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_4\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_5\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_6\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_7\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_8\ : STD_LOGIC;
  signal \r_reg[23]_i_1_n_9\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_0\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_1\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_10\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_11\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_12\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_13\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_14\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_15\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_2\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_3\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_4\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_5\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_6\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_7\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_8\ : STD_LOGIC;
  signal \r_reg[31]_i_1_n_9\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_0\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_1\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_10\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_11\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_12\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_13\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_14\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_15\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_2\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_3\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_4\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_5\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_6\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_7\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_8\ : STD_LOGIC;
  signal \r_reg[39]_i_1_n_9\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_1\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_10\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_11\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_12\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_13\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_14\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_15\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_2\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_3\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_4\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_5\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_6\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_7\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_8\ : STD_LOGIC;
  signal \r_reg[47]_i_1_n_9\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \r_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal \r_reg_n_0_[0]\ : STD_LOGIC;
  signal \r_reg_n_0_[10]\ : STD_LOGIC;
  signal \r_reg_n_0_[11]\ : STD_LOGIC;
  signal \r_reg_n_0_[12]\ : STD_LOGIC;
  signal \r_reg_n_0_[13]\ : STD_LOGIC;
  signal \r_reg_n_0_[14]\ : STD_LOGIC;
  signal \r_reg_n_0_[15]\ : STD_LOGIC;
  signal \r_reg_n_0_[16]\ : STD_LOGIC;
  signal \r_reg_n_0_[17]\ : STD_LOGIC;
  signal \r_reg_n_0_[18]\ : STD_LOGIC;
  signal \r_reg_n_0_[19]\ : STD_LOGIC;
  signal \r_reg_n_0_[1]\ : STD_LOGIC;
  signal \r_reg_n_0_[20]\ : STD_LOGIC;
  signal \r_reg_n_0_[21]\ : STD_LOGIC;
  signal \r_reg_n_0_[22]\ : STD_LOGIC;
  signal \r_reg_n_0_[23]\ : STD_LOGIC;
  signal \r_reg_n_0_[24]\ : STD_LOGIC;
  signal \r_reg_n_0_[25]\ : STD_LOGIC;
  signal \r_reg_n_0_[26]\ : STD_LOGIC;
  signal \r_reg_n_0_[27]\ : STD_LOGIC;
  signal \r_reg_n_0_[28]\ : STD_LOGIC;
  signal \r_reg_n_0_[29]\ : STD_LOGIC;
  signal \r_reg_n_0_[2]\ : STD_LOGIC;
  signal \r_reg_n_0_[30]\ : STD_LOGIC;
  signal \r_reg_n_0_[31]\ : STD_LOGIC;
  signal \r_reg_n_0_[32]\ : STD_LOGIC;
  signal \r_reg_n_0_[33]\ : STD_LOGIC;
  signal \r_reg_n_0_[34]\ : STD_LOGIC;
  signal \r_reg_n_0_[35]\ : STD_LOGIC;
  signal \r_reg_n_0_[36]\ : STD_LOGIC;
  signal \r_reg_n_0_[37]\ : STD_LOGIC;
  signal \r_reg_n_0_[38]\ : STD_LOGIC;
  signal \r_reg_n_0_[39]\ : STD_LOGIC;
  signal \r_reg_n_0_[3]\ : STD_LOGIC;
  signal \r_reg_n_0_[40]\ : STD_LOGIC;
  signal \r_reg_n_0_[41]\ : STD_LOGIC;
  signal \r_reg_n_0_[42]\ : STD_LOGIC;
  signal \r_reg_n_0_[43]\ : STD_LOGIC;
  signal \r_reg_n_0_[44]\ : STD_LOGIC;
  signal \r_reg_n_0_[45]\ : STD_LOGIC;
  signal \r_reg_n_0_[46]\ : STD_LOGIC;
  signal \r_reg_n_0_[47]\ : STD_LOGIC;
  signal \r_reg_n_0_[4]\ : STD_LOGIC;
  signal \r_reg_n_0_[5]\ : STD_LOGIC;
  signal \r_reg_n_0_[6]\ : STD_LOGIC;
  signal \r_reg_n_0_[7]\ : STD_LOGIC;
  signal \r_reg_n_0_[8]\ : STD_LOGIC;
  signal \r_reg_n_0_[9]\ : STD_LOGIC;
  signal \rexp[0]_i_10_n_0\ : STD_LOGIC;
  signal \rexp[0]_i_1_n_0\ : STD_LOGIC;
  signal \rexp[0]_i_2_n_0\ : STD_LOGIC;
  signal \rexp[0]_i_3_n_0\ : STD_LOGIC;
  signal \rexp[0]_i_4_n_0\ : STD_LOGIC;
  signal \rexp[0]_i_5_n_0\ : STD_LOGIC;
  signal \rexp[0]_i_6_n_0\ : STD_LOGIC;
  signal \rexp[0]_i_7_n_0\ : STD_LOGIC;
  signal \rexp[0]_i_8_n_0\ : STD_LOGIC;
  signal \rexp[0]_i_9_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_10_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_11_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_12_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_13_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_14_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_15_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_16_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_17_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_18_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_19_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_1_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_20_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_21_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_22_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_23_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_24_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_25_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_26_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_27_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_28_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_29_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_2_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_30_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_32_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_33_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_34_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_35_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_36_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_37_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_38_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_3_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_4_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_5_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_6_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_7_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_8_n_0\ : STD_LOGIC;
  signal \rexp[1]_i_9_n_0\ : STD_LOGIC;
  signal \rexp[2]_i_1_n_0\ : STD_LOGIC;
  signal \rexp[2]_i_2_n_0\ : STD_LOGIC;
  signal \rexp[2]_i_3_n_0\ : STD_LOGIC;
  signal \rexp[2]_i_4_n_0\ : STD_LOGIC;
  signal \rexp[2]_i_5_n_0\ : STD_LOGIC;
  signal \rexp[2]_i_6_n_0\ : STD_LOGIC;
  signal \rexp[2]_i_7_n_0\ : STD_LOGIC;
  signal \rexp[2]_i_8_n_0\ : STD_LOGIC;
  signal \rexp[2]_i_9_n_0\ : STD_LOGIC;
  signal \rexp[3]_i_1_n_0\ : STD_LOGIC;
  signal \rexp[3]_i_2_n_0\ : STD_LOGIC;
  signal \rexp[4]_i_1_n_0\ : STD_LOGIC;
  signal \rexp[4]_i_2_n_0\ : STD_LOGIC;
  signal \rexp[4]_i_3_n_0\ : STD_LOGIC;
  signal \rexp[4]_i_4_n_0\ : STD_LOGIC;
  signal \rexp[4]_i_5_n_0\ : STD_LOGIC;
  signal \rexp[4]_i_6_n_0\ : STD_LOGIC;
  signal \rexp[5]_i_1_n_0\ : STD_LOGIC;
  signal \rexp[5]_i_2_n_0\ : STD_LOGIC;
  signal \rexp[5]_i_3_n_0\ : STD_LOGIC;
  signal \rexp[5]_i_4_n_0\ : STD_LOGIC;
  signal \rexp[5]_i_5_n_0\ : STD_LOGIC;
  signal \rexp[5]_i_6_n_0\ : STD_LOGIC;
  signal \rexp[6]_i_1_n_0\ : STD_LOGIC;
  signal \rexp[6]_i_2_n_0\ : STD_LOGIC;
  signal \rexp[6]_i_3_n_0\ : STD_LOGIC;
  signal \rexp[6]_i_4_n_0\ : STD_LOGIC;
  signal \rexp[6]_i_5_n_0\ : STD_LOGIC;
  signal \rexp[6]_i_6_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_10_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_11_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_12_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_13_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_14_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_15_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_16_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_17_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_18_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_19_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_1_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_20_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_21_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_22_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_23_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_24_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_25_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_26_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_27_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_28_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_29_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_2_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_30_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_31_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_32_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_33_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_34_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_35_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_36_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_37_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_38_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_39_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_3_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_4_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_5_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_6_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_7_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_8_n_0\ : STD_LOGIC;
  signal \rexp[7]_i_9_n_0\ : STD_LOGIC;
  signal \rexp_reg[1]_i_31_n_0\ : STD_LOGIC;
  signal \rexp_reg_n_0_[0]\ : STD_LOGIC;
  signal \rexp_reg_n_0_[1]\ : STD_LOGIC;
  signal \rexp_reg_n_0_[2]\ : STD_LOGIC;
  signal \rexp_reg_n_0_[3]\ : STD_LOGIC;
  signal \rexp_reg_n_0_[4]\ : STD_LOGIC;
  signal \rexp_reg_n_0_[5]\ : STD_LOGIC;
  signal \rexp_reg_n_0_[6]\ : STD_LOGIC;
  signal \rexp_reg_n_0_[7]\ : STD_LOGIC;
  signal \^rng_reg_0\ : STD_LOGIC;
  signal \^rng_reg_1\ : STD_LOGIC;
  signal row0 : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal row1 : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \row_lcl[10]_i_1_n_0\ : STD_LOGIC;
  signal \row_lcl[10]_i_3_n_0\ : STD_LOGIC;
  signal \row_lcl[5]_i_2_n_0\ : STD_LOGIC;
  signal \row_lcl[9]_i_1_n_0\ : STD_LOGIC;
  signal \row_lcl[9]_i_2_n_0\ : STD_LOGIC;
  signal row_lcl_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rshift[0]_i_1_n_0\ : STD_LOGIC;
  signal \rshift[1]_i_1_n_0\ : STD_LOGIC;
  signal \rshift[2]_i_1_n_0\ : STD_LOGIC;
  signal \rshift[3]_i_1_n_0\ : STD_LOGIC;
  signal \rshift[4]_i_1_n_0\ : STD_LOGIC;
  signal \rshift[4]_i_2_n_0\ : STD_LOGIC;
  signal \rshift[4]_i_3_n_0\ : STD_LOGIC;
  signal \rshift[4]_i_4_n_0\ : STD_LOGIC;
  signal \rshift[5]_i_1_n_0\ : STD_LOGIC;
  signal \rshift[5]_i_2_n_0\ : STD_LOGIC;
  signal \rshift[5]_i_3_n_0\ : STD_LOGIC;
  signal \rshift[5]_i_4_n_0\ : STD_LOGIC;
  signal \rshift__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal scoreMax : STD_LOGIC;
  signal \scoreMax[0]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax[1]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax[2]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax[3]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax[4]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax[5]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax[6]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax[7]_i_1_n_0\ : STD_LOGIC;
  signal scoreMax_lcl0 : STD_LOGIC;
  signal \scoreMax_lcl[0]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[1]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[2]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[3]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[4]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[5]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[6]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[7]_i_10_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[7]_i_11_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[7]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[7]_i_2_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[7]_i_4_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[7]_i_5_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[7]_i_6_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[7]_i_7_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[7]_i_8_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl[7]_i_9_n_0\ : STD_LOGIC;
  signal \scoreMax_lcl__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \scoreMax_lcl_reg[7]_i_3_n_5\ : STD_LOGIC;
  signal \scoreMax_lcl_reg[7]_i_3_n_6\ : STD_LOGIC;
  signal \scoreMax_lcl_reg[7]_i_3_n_7\ : STD_LOGIC;
  signal \scoreMin[0]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin[1]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin[2]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin[3]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin[4]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin[5]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin[6]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin[7]_i_1_n_0\ : STD_LOGIC;
  signal scoreMin_lcl0 : STD_LOGIC;
  signal \scoreMin_lcl[0]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[1]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[2]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[3]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[4]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[5]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[6]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[7]_i_10_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[7]_i_11_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[7]_i_1_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[7]_i_2_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[7]_i_4_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[7]_i_5_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[7]_i_6_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[7]_i_7_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[7]_i_8_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl[7]_i_9_n_0\ : STD_LOGIC;
  signal \scoreMin_lcl__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \scoreMin_lcl_reg[7]_i_3_n_5\ : STD_LOGIC;
  signal \scoreMin_lcl_reg[7]_i_3_n_6\ : STD_LOGIC;
  signal \scoreMin_lcl_reg[7]_i_3_n_7\ : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal shift : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \shift[0]_i_1_n_0\ : STD_LOGIC;
  signal \shift[1]_i_1_n_0\ : STD_LOGIC;
  signal \shift[2]_i_1_n_0\ : STD_LOGIC;
  signal \shift[3]_i_1_n_0\ : STD_LOGIC;
  signal \shift[4]_i_1_n_0\ : STD_LOGIC;
  signal \shift[5]_i_2_n_0\ : STD_LOGIC;
  signal \shift_lcl[0]_i_1_n_0\ : STD_LOGIC;
  signal \shift_lcl[1]_i_1_n_0\ : STD_LOGIC;
  signal \shift_lcl[2]_i_1_n_0\ : STD_LOGIC;
  signal \shift_lcl[3]_i_1_n_0\ : STD_LOGIC;
  signal \shift_lcl[4]_i_1_n_0\ : STD_LOGIC;
  signal \shift_lcl[5]_i_1_n_0\ : STD_LOGIC;
  signal \shift_lcl[5]_i_2_n_0\ : STD_LOGIC;
  signal \shift_lcl[5]_i_3_n_0\ : STD_LOGIC;
  signal \shift_lcl[5]_i_4_n_0\ : STD_LOGIC;
  signal \shift_lcl[5]_i_5_n_0\ : STD_LOGIC;
  signal \shift_lcl[5]_i_6_n_0\ : STD_LOGIC;
  signal \shift_lcl__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal stateCorner : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \stateCorner[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateCorner[0]_i_2_n_0\ : STD_LOGIC;
  signal \stateCorner[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateCorner[1]_i_4_n_0\ : STD_LOGIC;
  signal \stateCorner[1]_i_5_n_0\ : STD_LOGIC;
  signal \stateCorner[1]_i_6_n_0\ : STD_LOGIC;
  signal \stateImdstream[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateImdstream[0]_i_2_n_0\ : STD_LOGIC;
  signal \stateImdstream[0]_i_3_n_0\ : STD_LOGIC;
  signal \stateImdstream[0]_i_4_n_0\ : STD_LOGIC;
  signal \stateImdstream[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateImdstream[1]_i_2_n_0\ : STD_LOGIC;
  signal \stateImdstream[1]_i_3_n_0\ : STD_LOGIC;
  signal \stateImdstream[1]_i_4_n_0\ : STD_LOGIC;
  signal \stateImdstream[2]_i_1_n_0\ : STD_LOGIC;
  signal \stateImdstream[2]_i_2_n_0\ : STD_LOGIC;
  signal \stateImdstream_reg_n_0_[0]\ : STD_LOGIC;
  signal \stateImdstream_reg_n_0_[1]\ : STD_LOGIC;
  signal \stateMaxsel[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateMaxsel[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateMaxsel[1]_i_2_n_0\ : STD_LOGIC;
  signal \stateMaxsel[1]_i_3_n_0\ : STD_LOGIC;
  signal \stateMaxsel_reg_n_0_[0]\ : STD_LOGIC;
  signal \stateMaxsel_reg_n_0_[1]\ : STD_LOGIC;
  signal stateOp : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^stateop_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal stateScore : STD_LOGIC;
  signal \stateScore_reg_rep__0_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__10_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__11_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__12_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__13_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__14_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__15_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__16_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__17_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__18_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__1_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__2_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__3_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__4_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__5_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__6_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__7_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__8_n_0\ : STD_LOGIC;
  signal \stateScore_reg_rep__9_n_0\ : STD_LOGIC;
  signal stateScore_reg_rep_n_0 : STD_LOGIC;
  signal sumIII : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal \sumIII[15]_i_10_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_11_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_12_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_13_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_14_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_15_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_16_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_17_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_2_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_3_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_4_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_5_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_6_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_7_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_8_n_0\ : STD_LOGIC;
  signal \sumIII[15]_i_9_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_10_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_11_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_12_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_13_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_14_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_15_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_16_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_2_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_3_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_4_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_5_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_6_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_7_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_8_n_0\ : STD_LOGIC;
  signal \sumIII[23]_i_9_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_10_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_11_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_12_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_13_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_14_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_15_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_16_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_17_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_2_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_3_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_4_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_5_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_6_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_7_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_8_n_0\ : STD_LOGIC;
  signal \sumIII[7]_i_9_n_0\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \sumIII_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_1\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_10\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_11\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_12\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_13\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_14\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_15\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_2\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_3\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_4\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_5\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_6\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_7\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_8\ : STD_LOGIC;
  signal \sumIII_reg[23]_i_1_n_9\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \sumIII_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal sumX : STD_LOGIC_VECTOR ( 22 downto 0 );
  signal sumXA : STD_LOGIC_VECTOR ( 43 downto 0 );
  signal sumXA0 : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal sumXA00_in : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal \sumXA[0]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[10]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[11]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[12]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[13]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[14]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[15]_i_10_n_0\ : STD_LOGIC;
  signal \sumXA[15]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[15]_i_3_n_0\ : STD_LOGIC;
  signal \sumXA[15]_i_4_n_0\ : STD_LOGIC;
  signal \sumXA[15]_i_5_n_0\ : STD_LOGIC;
  signal \sumXA[15]_i_6_n_0\ : STD_LOGIC;
  signal \sumXA[15]_i_7_n_0\ : STD_LOGIC;
  signal \sumXA[15]_i_8_n_0\ : STD_LOGIC;
  signal \sumXA[15]_i_9_n_0\ : STD_LOGIC;
  signal \sumXA[16]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[17]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[18]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[19]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[1]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[20]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[21]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[21]_i_3_n_0\ : STD_LOGIC;
  signal \sumXA[21]_i_4_n_0\ : STD_LOGIC;
  signal \sumXA[21]_i_5_n_0\ : STD_LOGIC;
  signal \sumXA[21]_i_6_n_0\ : STD_LOGIC;
  signal \sumXA[21]_i_7_n_0\ : STD_LOGIC;
  signal \sumXA[21]_i_8_n_0\ : STD_LOGIC;
  signal \sumXA[22]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[23]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[24]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[25]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[26]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[27]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[28]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[29]_i_10_n_0\ : STD_LOGIC;
  signal \sumXA[29]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[29]_i_3_n_0\ : STD_LOGIC;
  signal \sumXA[29]_i_4_n_0\ : STD_LOGIC;
  signal \sumXA[29]_i_5_n_0\ : STD_LOGIC;
  signal \sumXA[29]_i_6_n_0\ : STD_LOGIC;
  signal \sumXA[29]_i_7_n_0\ : STD_LOGIC;
  signal \sumXA[29]_i_8_n_0\ : STD_LOGIC;
  signal \sumXA[29]_i_9_n_0\ : STD_LOGIC;
  signal \sumXA[2]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[30]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[31]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[32]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[33]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[34]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[35]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[36]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[37]_i_10_n_0\ : STD_LOGIC;
  signal \sumXA[37]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[37]_i_3_n_0\ : STD_LOGIC;
  signal \sumXA[37]_i_4_n_0\ : STD_LOGIC;
  signal \sumXA[37]_i_5_n_0\ : STD_LOGIC;
  signal \sumXA[37]_i_6_n_0\ : STD_LOGIC;
  signal \sumXA[37]_i_7_n_0\ : STD_LOGIC;
  signal \sumXA[37]_i_8_n_0\ : STD_LOGIC;
  signal \sumXA[37]_i_9_n_0\ : STD_LOGIC;
  signal \sumXA[38]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[39]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[3]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[40]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[41]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[42]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[43]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[43]_i_3_n_0\ : STD_LOGIC;
  signal \sumXA[43]_i_4_n_0\ : STD_LOGIC;
  signal \sumXA[43]_i_5_n_0\ : STD_LOGIC;
  signal \sumXA[43]_i_6_n_0\ : STD_LOGIC;
  signal \sumXA[43]_i_7_n_0\ : STD_LOGIC;
  signal \sumXA[43]_i_8_n_0\ : STD_LOGIC;
  signal \sumXA[4]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[5]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[6]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[7]_i_10_n_0\ : STD_LOGIC;
  signal \sumXA[7]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[7]_i_3_n_0\ : STD_LOGIC;
  signal \sumXA[7]_i_4_n_0\ : STD_LOGIC;
  signal \sumXA[7]_i_5_n_0\ : STD_LOGIC;
  signal \sumXA[7]_i_6_n_0\ : STD_LOGIC;
  signal \sumXA[7]_i_7_n_0\ : STD_LOGIC;
  signal \sumXA[7]_i_8_n_0\ : STD_LOGIC;
  signal \sumXA[7]_i_9_n_0\ : STD_LOGIC;
  signal \sumXA[8]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA[9]_i_1_n_0\ : STD_LOGIC;
  signal \sumXA_reg[15]_i_2_n_0\ : STD_LOGIC;
  signal \sumXA_reg[15]_i_2_n_1\ : STD_LOGIC;
  signal \sumXA_reg[15]_i_2_n_2\ : STD_LOGIC;
  signal \sumXA_reg[15]_i_2_n_3\ : STD_LOGIC;
  signal \sumXA_reg[15]_i_2_n_4\ : STD_LOGIC;
  signal \sumXA_reg[15]_i_2_n_5\ : STD_LOGIC;
  signal \sumXA_reg[15]_i_2_n_6\ : STD_LOGIC;
  signal \sumXA_reg[15]_i_2_n_7\ : STD_LOGIC;
  signal \sumXA_reg[21]_i_2_n_2\ : STD_LOGIC;
  signal \sumXA_reg[21]_i_2_n_4\ : STD_LOGIC;
  signal \sumXA_reg[21]_i_2_n_5\ : STD_LOGIC;
  signal \sumXA_reg[21]_i_2_n_6\ : STD_LOGIC;
  signal \sumXA_reg[21]_i_2_n_7\ : STD_LOGIC;
  signal \sumXA_reg[29]_i_2_n_0\ : STD_LOGIC;
  signal \sumXA_reg[29]_i_2_n_1\ : STD_LOGIC;
  signal \sumXA_reg[29]_i_2_n_2\ : STD_LOGIC;
  signal \sumXA_reg[29]_i_2_n_3\ : STD_LOGIC;
  signal \sumXA_reg[29]_i_2_n_4\ : STD_LOGIC;
  signal \sumXA_reg[29]_i_2_n_5\ : STD_LOGIC;
  signal \sumXA_reg[29]_i_2_n_6\ : STD_LOGIC;
  signal \sumXA_reg[29]_i_2_n_7\ : STD_LOGIC;
  signal \sumXA_reg[37]_i_2_n_0\ : STD_LOGIC;
  signal \sumXA_reg[37]_i_2_n_1\ : STD_LOGIC;
  signal \sumXA_reg[37]_i_2_n_2\ : STD_LOGIC;
  signal \sumXA_reg[37]_i_2_n_3\ : STD_LOGIC;
  signal \sumXA_reg[37]_i_2_n_4\ : STD_LOGIC;
  signal \sumXA_reg[37]_i_2_n_5\ : STD_LOGIC;
  signal \sumXA_reg[37]_i_2_n_6\ : STD_LOGIC;
  signal \sumXA_reg[37]_i_2_n_7\ : STD_LOGIC;
  signal \sumXA_reg[43]_i_2_n_2\ : STD_LOGIC;
  signal \sumXA_reg[43]_i_2_n_4\ : STD_LOGIC;
  signal \sumXA_reg[43]_i_2_n_5\ : STD_LOGIC;
  signal \sumXA_reg[43]_i_2_n_6\ : STD_LOGIC;
  signal \sumXA_reg[43]_i_2_n_7\ : STD_LOGIC;
  signal \sumXA_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \sumXA_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \sumXA_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \sumXA_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \sumXA_reg[7]_i_2_n_4\ : STD_LOGIC;
  signal \sumXA_reg[7]_i_2_n_5\ : STD_LOGIC;
  signal \sumXA_reg[7]_i_2_n_6\ : STD_LOGIC;
  signal \sumXA_reg[7]_i_2_n_7\ : STD_LOGIC;
  signal \sumXB[15]_i_10_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_11_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_12_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_13_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_14_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_15_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_16_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_17_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_2_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_3_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_4_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_5_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_6_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_7_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_8_n_0\ : STD_LOGIC;
  signal \sumXB[15]_i_9_n_0\ : STD_LOGIC;
  signal \sumXB[22]_i_10_n_0\ : STD_LOGIC;
  signal \sumXB[22]_i_11_n_0\ : STD_LOGIC;
  signal \sumXB[22]_i_12_n_0\ : STD_LOGIC;
  signal \sumXB[22]_i_13_n_0\ : STD_LOGIC;
  signal \sumXB[22]_i_14_n_0\ : STD_LOGIC;
  signal \sumXB[22]_i_2_n_0\ : STD_LOGIC;
  signal \sumXB[22]_i_3_n_0\ : STD_LOGIC;
  signal \sumXB[22]_i_4_n_0\ : STD_LOGIC;
  signal \sumXB[22]_i_5_n_0\ : STD_LOGIC;
  signal \sumXB[22]_i_6_n_0\ : STD_LOGIC;
  signal \sumXB[22]_i_7_n_0\ : STD_LOGIC;
  signal \sumXB[22]_i_8_n_0\ : STD_LOGIC;
  signal \sumXB[22]_i_9_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_10_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_11_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_12_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_13_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_14_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_15_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_16_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_17_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_2_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_3_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_4_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_5_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_6_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_7_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_8_n_0\ : STD_LOGIC;
  signal \sumXB[7]_i_9_n_0\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \sumXB_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \sumXB_reg[22]_i_1_n_10\ : STD_LOGIC;
  signal \sumXB_reg[22]_i_1_n_11\ : STD_LOGIC;
  signal \sumXB_reg[22]_i_1_n_12\ : STD_LOGIC;
  signal \sumXB_reg[22]_i_1_n_13\ : STD_LOGIC;
  signal \sumXB_reg[22]_i_1_n_14\ : STD_LOGIC;
  signal \sumXB_reg[22]_i_1_n_15\ : STD_LOGIC;
  signal \sumXB_reg[22]_i_1_n_2\ : STD_LOGIC;
  signal \sumXB_reg[22]_i_1_n_3\ : STD_LOGIC;
  signal \sumXB_reg[22]_i_1_n_4\ : STD_LOGIC;
  signal \sumXB_reg[22]_i_1_n_5\ : STD_LOGIC;
  signal \sumXB_reg[22]_i_1_n_6\ : STD_LOGIC;
  signal \sumXB_reg[22]_i_1_n_7\ : STD_LOGIC;
  signal \sumXB_reg[22]_i_1_n_9\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \sumXB_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[0]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[10]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[11]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[12]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[13]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[14]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[15]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[16]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[17]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[18]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[19]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[1]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[20]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[21]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[22]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[2]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[3]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[4]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[5]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[6]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[7]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[8]\ : STD_LOGIC;
  signal \sumXB_reg_n_0_[9]\ : STD_LOGIC;
  signal sumXY : STD_LOGIC_VECTOR ( 22 downto 0 );
  signal sumXYA : STD_LOGIC_VECTOR ( 43 downto 0 );
  signal sumXYA0 : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal sumXYA00_in : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal \sumXYA[0]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[10]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[11]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[12]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[13]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[14]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[15]_i_10_n_0\ : STD_LOGIC;
  signal \sumXYA[15]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[15]_i_3_n_0\ : STD_LOGIC;
  signal \sumXYA[15]_i_4_n_0\ : STD_LOGIC;
  signal \sumXYA[15]_i_5_n_0\ : STD_LOGIC;
  signal \sumXYA[15]_i_6_n_0\ : STD_LOGIC;
  signal \sumXYA[15]_i_7_n_0\ : STD_LOGIC;
  signal \sumXYA[15]_i_8_n_0\ : STD_LOGIC;
  signal \sumXYA[15]_i_9_n_0\ : STD_LOGIC;
  signal \sumXYA[16]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[17]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[18]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[19]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[1]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[20]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[21]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[21]_i_3_n_0\ : STD_LOGIC;
  signal \sumXYA[21]_i_4_n_0\ : STD_LOGIC;
  signal \sumXYA[21]_i_5_n_0\ : STD_LOGIC;
  signal \sumXYA[21]_i_6_n_0\ : STD_LOGIC;
  signal \sumXYA[21]_i_7_n_0\ : STD_LOGIC;
  signal \sumXYA[21]_i_8_n_0\ : STD_LOGIC;
  signal \sumXYA[22]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[23]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[24]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[25]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[26]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[27]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[28]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[29]_i_10_n_0\ : STD_LOGIC;
  signal \sumXYA[29]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[29]_i_3_n_0\ : STD_LOGIC;
  signal \sumXYA[29]_i_4_n_0\ : STD_LOGIC;
  signal \sumXYA[29]_i_5_n_0\ : STD_LOGIC;
  signal \sumXYA[29]_i_6_n_0\ : STD_LOGIC;
  signal \sumXYA[29]_i_7_n_0\ : STD_LOGIC;
  signal \sumXYA[29]_i_8_n_0\ : STD_LOGIC;
  signal \sumXYA[29]_i_9_n_0\ : STD_LOGIC;
  signal \sumXYA[2]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[30]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[31]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[32]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[33]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[34]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[35]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[36]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[37]_i_10_n_0\ : STD_LOGIC;
  signal \sumXYA[37]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[37]_i_3_n_0\ : STD_LOGIC;
  signal \sumXYA[37]_i_4_n_0\ : STD_LOGIC;
  signal \sumXYA[37]_i_5_n_0\ : STD_LOGIC;
  signal \sumXYA[37]_i_6_n_0\ : STD_LOGIC;
  signal \sumXYA[37]_i_7_n_0\ : STD_LOGIC;
  signal \sumXYA[37]_i_8_n_0\ : STD_LOGIC;
  signal \sumXYA[37]_i_9_n_0\ : STD_LOGIC;
  signal \sumXYA[38]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[39]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[3]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[40]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[41]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[42]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[43]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[43]_i_3_n_0\ : STD_LOGIC;
  signal \sumXYA[43]_i_4_n_0\ : STD_LOGIC;
  signal \sumXYA[43]_i_5_n_0\ : STD_LOGIC;
  signal \sumXYA[43]_i_6_n_0\ : STD_LOGIC;
  signal \sumXYA[43]_i_7_n_0\ : STD_LOGIC;
  signal \sumXYA[43]_i_8_n_0\ : STD_LOGIC;
  signal \sumXYA[4]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[5]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[6]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[7]_i_10_n_0\ : STD_LOGIC;
  signal \sumXYA[7]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[7]_i_3_n_0\ : STD_LOGIC;
  signal \sumXYA[7]_i_4_n_0\ : STD_LOGIC;
  signal \sumXYA[7]_i_5_n_0\ : STD_LOGIC;
  signal \sumXYA[7]_i_6_n_0\ : STD_LOGIC;
  signal \sumXYA[7]_i_7_n_0\ : STD_LOGIC;
  signal \sumXYA[7]_i_8_n_0\ : STD_LOGIC;
  signal \sumXYA[7]_i_9_n_0\ : STD_LOGIC;
  signal \sumXYA[8]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA[9]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYA_reg[15]_i_2_n_0\ : STD_LOGIC;
  signal \sumXYA_reg[15]_i_2_n_1\ : STD_LOGIC;
  signal \sumXYA_reg[15]_i_2_n_2\ : STD_LOGIC;
  signal \sumXYA_reg[15]_i_2_n_3\ : STD_LOGIC;
  signal \sumXYA_reg[15]_i_2_n_4\ : STD_LOGIC;
  signal \sumXYA_reg[15]_i_2_n_5\ : STD_LOGIC;
  signal \sumXYA_reg[15]_i_2_n_6\ : STD_LOGIC;
  signal \sumXYA_reg[15]_i_2_n_7\ : STD_LOGIC;
  signal \sumXYA_reg[21]_i_2_n_2\ : STD_LOGIC;
  signal \sumXYA_reg[21]_i_2_n_4\ : STD_LOGIC;
  signal \sumXYA_reg[21]_i_2_n_5\ : STD_LOGIC;
  signal \sumXYA_reg[21]_i_2_n_6\ : STD_LOGIC;
  signal \sumXYA_reg[21]_i_2_n_7\ : STD_LOGIC;
  signal \sumXYA_reg[29]_i_2_n_0\ : STD_LOGIC;
  signal \sumXYA_reg[29]_i_2_n_1\ : STD_LOGIC;
  signal \sumXYA_reg[29]_i_2_n_2\ : STD_LOGIC;
  signal \sumXYA_reg[29]_i_2_n_3\ : STD_LOGIC;
  signal \sumXYA_reg[29]_i_2_n_4\ : STD_LOGIC;
  signal \sumXYA_reg[29]_i_2_n_5\ : STD_LOGIC;
  signal \sumXYA_reg[29]_i_2_n_6\ : STD_LOGIC;
  signal \sumXYA_reg[29]_i_2_n_7\ : STD_LOGIC;
  signal \sumXYA_reg[37]_i_2_n_0\ : STD_LOGIC;
  signal \sumXYA_reg[37]_i_2_n_1\ : STD_LOGIC;
  signal \sumXYA_reg[37]_i_2_n_2\ : STD_LOGIC;
  signal \sumXYA_reg[37]_i_2_n_3\ : STD_LOGIC;
  signal \sumXYA_reg[37]_i_2_n_4\ : STD_LOGIC;
  signal \sumXYA_reg[37]_i_2_n_5\ : STD_LOGIC;
  signal \sumXYA_reg[37]_i_2_n_6\ : STD_LOGIC;
  signal \sumXYA_reg[37]_i_2_n_7\ : STD_LOGIC;
  signal \sumXYA_reg[43]_i_2_n_2\ : STD_LOGIC;
  signal \sumXYA_reg[43]_i_2_n_4\ : STD_LOGIC;
  signal \sumXYA_reg[43]_i_2_n_5\ : STD_LOGIC;
  signal \sumXYA_reg[43]_i_2_n_6\ : STD_LOGIC;
  signal \sumXYA_reg[43]_i_2_n_7\ : STD_LOGIC;
  signal \sumXYA_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \sumXYA_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \sumXYA_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \sumXYA_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \sumXYA_reg[7]_i_2_n_4\ : STD_LOGIC;
  signal \sumXYA_reg[7]_i_2_n_5\ : STD_LOGIC;
  signal \sumXYA_reg[7]_i_2_n_6\ : STD_LOGIC;
  signal \sumXYA_reg[7]_i_2_n_7\ : STD_LOGIC;
  signal \sumXYB[15]_i_10_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_11_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_12_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_13_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_14_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_15_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_16_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_17_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_2_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_3_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_4_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_5_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_6_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_7_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_8_n_0\ : STD_LOGIC;
  signal \sumXYB[15]_i_9_n_0\ : STD_LOGIC;
  signal \sumXYB[22]_i_10_n_0\ : STD_LOGIC;
  signal \sumXYB[22]_i_11_n_0\ : STD_LOGIC;
  signal \sumXYB[22]_i_12_n_0\ : STD_LOGIC;
  signal \sumXYB[22]_i_13_n_0\ : STD_LOGIC;
  signal \sumXYB[22]_i_14_n_0\ : STD_LOGIC;
  signal \sumXYB[22]_i_2_n_0\ : STD_LOGIC;
  signal \sumXYB[22]_i_3_n_0\ : STD_LOGIC;
  signal \sumXYB[22]_i_4_n_0\ : STD_LOGIC;
  signal \sumXYB[22]_i_5_n_0\ : STD_LOGIC;
  signal \sumXYB[22]_i_6_n_0\ : STD_LOGIC;
  signal \sumXYB[22]_i_7_n_0\ : STD_LOGIC;
  signal \sumXYB[22]_i_8_n_0\ : STD_LOGIC;
  signal \sumXYB[22]_i_9_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_10_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_11_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_12_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_13_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_14_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_15_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_16_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_17_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_2_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_3_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_4_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_5_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_6_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_7_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_8_n_0\ : STD_LOGIC;
  signal \sumXYB[7]_i_9_n_0\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \sumXYB_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \sumXYB_reg[22]_i_1_n_10\ : STD_LOGIC;
  signal \sumXYB_reg[22]_i_1_n_11\ : STD_LOGIC;
  signal \sumXYB_reg[22]_i_1_n_12\ : STD_LOGIC;
  signal \sumXYB_reg[22]_i_1_n_13\ : STD_LOGIC;
  signal \sumXYB_reg[22]_i_1_n_14\ : STD_LOGIC;
  signal \sumXYB_reg[22]_i_1_n_15\ : STD_LOGIC;
  signal \sumXYB_reg[22]_i_1_n_2\ : STD_LOGIC;
  signal \sumXYB_reg[22]_i_1_n_3\ : STD_LOGIC;
  signal \sumXYB_reg[22]_i_1_n_4\ : STD_LOGIC;
  signal \sumXYB_reg[22]_i_1_n_5\ : STD_LOGIC;
  signal \sumXYB_reg[22]_i_1_n_6\ : STD_LOGIC;
  signal \sumXYB_reg[22]_i_1_n_7\ : STD_LOGIC;
  signal \sumXYB_reg[22]_i_1_n_9\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \sumXYB_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[0]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[10]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[11]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[12]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[13]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[14]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[15]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[16]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[17]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[18]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[19]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[1]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[20]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[21]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[22]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[2]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[3]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[4]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[5]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[6]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[7]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[8]\ : STD_LOGIC;
  signal \sumXYB_reg_n_0_[9]\ : STD_LOGIC;
  signal \sumXY[15]_i_10_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_11_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_12_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_13_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_14_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_15_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_16_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_17_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_2_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_3_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_4_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_5_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_6_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_7_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_8_n_0\ : STD_LOGIC;
  signal \sumXY[15]_i_9_n_0\ : STD_LOGIC;
  signal \sumXY[22]_i_10_n_0\ : STD_LOGIC;
  signal \sumXY[22]_i_11_n_0\ : STD_LOGIC;
  signal \sumXY[22]_i_12_n_0\ : STD_LOGIC;
  signal \sumXY[22]_i_13_n_0\ : STD_LOGIC;
  signal \sumXY[22]_i_14_n_0\ : STD_LOGIC;
  signal \sumXY[22]_i_2_n_0\ : STD_LOGIC;
  signal \sumXY[22]_i_3_n_0\ : STD_LOGIC;
  signal \sumXY[22]_i_4_n_0\ : STD_LOGIC;
  signal \sumXY[22]_i_5_n_0\ : STD_LOGIC;
  signal \sumXY[22]_i_6_n_0\ : STD_LOGIC;
  signal \sumXY[22]_i_7_n_0\ : STD_LOGIC;
  signal \sumXY[22]_i_8_n_0\ : STD_LOGIC;
  signal \sumXY[22]_i_9_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_10_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_11_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_12_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_13_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_14_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_15_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_16_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_17_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_2_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_3_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_4_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_5_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_6_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_7_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_8_n_0\ : STD_LOGIC;
  signal \sumXY[7]_i_9_n_0\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \sumXY_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \sumXY_reg[22]_i_1_n_10\ : STD_LOGIC;
  signal \sumXY_reg[22]_i_1_n_11\ : STD_LOGIC;
  signal \sumXY_reg[22]_i_1_n_12\ : STD_LOGIC;
  signal \sumXY_reg[22]_i_1_n_13\ : STD_LOGIC;
  signal \sumXY_reg[22]_i_1_n_14\ : STD_LOGIC;
  signal \sumXY_reg[22]_i_1_n_15\ : STD_LOGIC;
  signal \sumXY_reg[22]_i_1_n_2\ : STD_LOGIC;
  signal \sumXY_reg[22]_i_1_n_3\ : STD_LOGIC;
  signal \sumXY_reg[22]_i_1_n_4\ : STD_LOGIC;
  signal \sumXY_reg[22]_i_1_n_5\ : STD_LOGIC;
  signal \sumXY_reg[22]_i_1_n_6\ : STD_LOGIC;
  signal \sumXY_reg[22]_i_1_n_7\ : STD_LOGIC;
  signal \sumXY_reg[22]_i_1_n_9\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \sumXY_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal \sumX[15]_i_10_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_11_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_12_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_13_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_14_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_15_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_16_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_17_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_2_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_3_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_4_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_5_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_6_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_7_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_8_n_0\ : STD_LOGIC;
  signal \sumX[15]_i_9_n_0\ : STD_LOGIC;
  signal \sumX[22]_i_10_n_0\ : STD_LOGIC;
  signal \sumX[22]_i_11_n_0\ : STD_LOGIC;
  signal \sumX[22]_i_12_n_0\ : STD_LOGIC;
  signal \sumX[22]_i_13_n_0\ : STD_LOGIC;
  signal \sumX[22]_i_14_n_0\ : STD_LOGIC;
  signal \sumX[22]_i_2_n_0\ : STD_LOGIC;
  signal \sumX[22]_i_3_n_0\ : STD_LOGIC;
  signal \sumX[22]_i_4_n_0\ : STD_LOGIC;
  signal \sumX[22]_i_5_n_0\ : STD_LOGIC;
  signal \sumX[22]_i_6_n_0\ : STD_LOGIC;
  signal \sumX[22]_i_7_n_0\ : STD_LOGIC;
  signal \sumX[22]_i_8_n_0\ : STD_LOGIC;
  signal \sumX[22]_i_9_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_10_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_11_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_12_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_13_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_14_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_15_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_16_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_17_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_2_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_3_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_4_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_5_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_6_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_7_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_8_n_0\ : STD_LOGIC;
  signal \sumX[7]_i_9_n_0\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \sumX_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \sumX_reg[22]_i_1_n_10\ : STD_LOGIC;
  signal \sumX_reg[22]_i_1_n_11\ : STD_LOGIC;
  signal \sumX_reg[22]_i_1_n_12\ : STD_LOGIC;
  signal \sumX_reg[22]_i_1_n_13\ : STD_LOGIC;
  signal \sumX_reg[22]_i_1_n_14\ : STD_LOGIC;
  signal \sumX_reg[22]_i_1_n_15\ : STD_LOGIC;
  signal \sumX_reg[22]_i_1_n_2\ : STD_LOGIC;
  signal \sumX_reg[22]_i_1_n_3\ : STD_LOGIC;
  signal \sumX_reg[22]_i_1_n_4\ : STD_LOGIC;
  signal \sumX_reg[22]_i_1_n_5\ : STD_LOGIC;
  signal \sumX_reg[22]_i_1_n_6\ : STD_LOGIC;
  signal \sumX_reg[22]_i_1_n_7\ : STD_LOGIC;
  signal \sumX_reg[22]_i_1_n_9\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \sumX_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal sumYA : STD_LOGIC_VECTOR ( 43 downto 0 );
  signal sumYA0 : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal sumYA00_in : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal \sumYA[0]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[10]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[11]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[12]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[13]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[14]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[15]_i_10_n_0\ : STD_LOGIC;
  signal \sumYA[15]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[15]_i_3_n_0\ : STD_LOGIC;
  signal \sumYA[15]_i_4_n_0\ : STD_LOGIC;
  signal \sumYA[15]_i_5_n_0\ : STD_LOGIC;
  signal \sumYA[15]_i_6_n_0\ : STD_LOGIC;
  signal \sumYA[15]_i_7_n_0\ : STD_LOGIC;
  signal \sumYA[15]_i_8_n_0\ : STD_LOGIC;
  signal \sumYA[15]_i_9_n_0\ : STD_LOGIC;
  signal \sumYA[16]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[17]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[18]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[19]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[1]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[20]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[21]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[21]_i_3_n_0\ : STD_LOGIC;
  signal \sumYA[21]_i_4_n_0\ : STD_LOGIC;
  signal \sumYA[21]_i_5_n_0\ : STD_LOGIC;
  signal \sumYA[21]_i_6_n_0\ : STD_LOGIC;
  signal \sumYA[21]_i_7_n_0\ : STD_LOGIC;
  signal \sumYA[21]_i_8_n_0\ : STD_LOGIC;
  signal \sumYA[22]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[23]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[24]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[25]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[26]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[27]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[28]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[29]_i_10_n_0\ : STD_LOGIC;
  signal \sumYA[29]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[29]_i_3_n_0\ : STD_LOGIC;
  signal \sumYA[29]_i_4_n_0\ : STD_LOGIC;
  signal \sumYA[29]_i_5_n_0\ : STD_LOGIC;
  signal \sumYA[29]_i_6_n_0\ : STD_LOGIC;
  signal \sumYA[29]_i_7_n_0\ : STD_LOGIC;
  signal \sumYA[29]_i_8_n_0\ : STD_LOGIC;
  signal \sumYA[29]_i_9_n_0\ : STD_LOGIC;
  signal \sumYA[2]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[30]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[31]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[32]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[33]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[34]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[35]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[36]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[37]_i_10_n_0\ : STD_LOGIC;
  signal \sumYA[37]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[37]_i_3_n_0\ : STD_LOGIC;
  signal \sumYA[37]_i_4_n_0\ : STD_LOGIC;
  signal \sumYA[37]_i_5_n_0\ : STD_LOGIC;
  signal \sumYA[37]_i_6_n_0\ : STD_LOGIC;
  signal \sumYA[37]_i_7_n_0\ : STD_LOGIC;
  signal \sumYA[37]_i_8_n_0\ : STD_LOGIC;
  signal \sumYA[37]_i_9_n_0\ : STD_LOGIC;
  signal \sumYA[38]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[39]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[3]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[40]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[41]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[42]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[43]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[43]_i_3_n_0\ : STD_LOGIC;
  signal \sumYA[43]_i_4_n_0\ : STD_LOGIC;
  signal \sumYA[43]_i_5_n_0\ : STD_LOGIC;
  signal \sumYA[43]_i_6_n_0\ : STD_LOGIC;
  signal \sumYA[43]_i_7_n_0\ : STD_LOGIC;
  signal \sumYA[43]_i_8_n_0\ : STD_LOGIC;
  signal \sumYA[4]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[5]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[6]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[7]_i_10_n_0\ : STD_LOGIC;
  signal \sumYA[7]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[7]_i_3_n_0\ : STD_LOGIC;
  signal \sumYA[7]_i_4_n_0\ : STD_LOGIC;
  signal \sumYA[7]_i_5_n_0\ : STD_LOGIC;
  signal \sumYA[7]_i_6_n_0\ : STD_LOGIC;
  signal \sumYA[7]_i_7_n_0\ : STD_LOGIC;
  signal \sumYA[7]_i_8_n_0\ : STD_LOGIC;
  signal \sumYA[7]_i_9_n_0\ : STD_LOGIC;
  signal \sumYA[8]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA[9]_i_1_n_0\ : STD_LOGIC;
  signal \sumYA_reg[15]_i_2_n_0\ : STD_LOGIC;
  signal \sumYA_reg[15]_i_2_n_1\ : STD_LOGIC;
  signal \sumYA_reg[15]_i_2_n_2\ : STD_LOGIC;
  signal \sumYA_reg[15]_i_2_n_3\ : STD_LOGIC;
  signal \sumYA_reg[15]_i_2_n_4\ : STD_LOGIC;
  signal \sumYA_reg[15]_i_2_n_5\ : STD_LOGIC;
  signal \sumYA_reg[15]_i_2_n_6\ : STD_LOGIC;
  signal \sumYA_reg[15]_i_2_n_7\ : STD_LOGIC;
  signal \sumYA_reg[21]_i_2_n_2\ : STD_LOGIC;
  signal \sumYA_reg[21]_i_2_n_4\ : STD_LOGIC;
  signal \sumYA_reg[21]_i_2_n_5\ : STD_LOGIC;
  signal \sumYA_reg[21]_i_2_n_6\ : STD_LOGIC;
  signal \sumYA_reg[21]_i_2_n_7\ : STD_LOGIC;
  signal \sumYA_reg[29]_i_2_n_0\ : STD_LOGIC;
  signal \sumYA_reg[29]_i_2_n_1\ : STD_LOGIC;
  signal \sumYA_reg[29]_i_2_n_2\ : STD_LOGIC;
  signal \sumYA_reg[29]_i_2_n_3\ : STD_LOGIC;
  signal \sumYA_reg[29]_i_2_n_4\ : STD_LOGIC;
  signal \sumYA_reg[29]_i_2_n_5\ : STD_LOGIC;
  signal \sumYA_reg[29]_i_2_n_6\ : STD_LOGIC;
  signal \sumYA_reg[29]_i_2_n_7\ : STD_LOGIC;
  signal \sumYA_reg[37]_i_2_n_0\ : STD_LOGIC;
  signal \sumYA_reg[37]_i_2_n_1\ : STD_LOGIC;
  signal \sumYA_reg[37]_i_2_n_2\ : STD_LOGIC;
  signal \sumYA_reg[37]_i_2_n_3\ : STD_LOGIC;
  signal \sumYA_reg[37]_i_2_n_4\ : STD_LOGIC;
  signal \sumYA_reg[37]_i_2_n_5\ : STD_LOGIC;
  signal \sumYA_reg[37]_i_2_n_6\ : STD_LOGIC;
  signal \sumYA_reg[37]_i_2_n_7\ : STD_LOGIC;
  signal \sumYA_reg[43]_i_2_n_2\ : STD_LOGIC;
  signal \sumYA_reg[43]_i_2_n_4\ : STD_LOGIC;
  signal \sumYA_reg[43]_i_2_n_5\ : STD_LOGIC;
  signal \sumYA_reg[43]_i_2_n_6\ : STD_LOGIC;
  signal \sumYA_reg[43]_i_2_n_7\ : STD_LOGIC;
  signal \sumYA_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \sumYA_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \sumYA_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \sumYA_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \sumYA_reg[7]_i_2_n_4\ : STD_LOGIC;
  signal \sumYA_reg[7]_i_2_n_5\ : STD_LOGIC;
  signal \sumYA_reg[7]_i_2_n_6\ : STD_LOGIC;
  signal \sumYA_reg[7]_i_2_n_7\ : STD_LOGIC;
  signal \sumYB[15]_i_10_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_11_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_12_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_13_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_14_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_15_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_16_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_17_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_2_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_3_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_4_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_5_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_6_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_7_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_8_n_0\ : STD_LOGIC;
  signal \sumYB[15]_i_9_n_0\ : STD_LOGIC;
  signal \sumYB[22]_i_10_n_0\ : STD_LOGIC;
  signal \sumYB[22]_i_11_n_0\ : STD_LOGIC;
  signal \sumYB[22]_i_12_n_0\ : STD_LOGIC;
  signal \sumYB[22]_i_13_n_0\ : STD_LOGIC;
  signal \sumYB[22]_i_14_n_0\ : STD_LOGIC;
  signal \sumYB[22]_i_2_n_0\ : STD_LOGIC;
  signal \sumYB[22]_i_3_n_0\ : STD_LOGIC;
  signal \sumYB[22]_i_4_n_0\ : STD_LOGIC;
  signal \sumYB[22]_i_5_n_0\ : STD_LOGIC;
  signal \sumYB[22]_i_6_n_0\ : STD_LOGIC;
  signal \sumYB[22]_i_7_n_0\ : STD_LOGIC;
  signal \sumYB[22]_i_8_n_0\ : STD_LOGIC;
  signal \sumYB[22]_i_9_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_10_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_11_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_12_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_13_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_14_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_15_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_16_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_17_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_2_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_3_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_4_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_5_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_6_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_7_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_8_n_0\ : STD_LOGIC;
  signal \sumYB[7]_i_9_n_0\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \sumYB_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \sumYB_reg[22]_i_1_n_10\ : STD_LOGIC;
  signal \sumYB_reg[22]_i_1_n_11\ : STD_LOGIC;
  signal \sumYB_reg[22]_i_1_n_12\ : STD_LOGIC;
  signal \sumYB_reg[22]_i_1_n_13\ : STD_LOGIC;
  signal \sumYB_reg[22]_i_1_n_14\ : STD_LOGIC;
  signal \sumYB_reg[22]_i_1_n_15\ : STD_LOGIC;
  signal \sumYB_reg[22]_i_1_n_2\ : STD_LOGIC;
  signal \sumYB_reg[22]_i_1_n_3\ : STD_LOGIC;
  signal \sumYB_reg[22]_i_1_n_4\ : STD_LOGIC;
  signal \sumYB_reg[22]_i_1_n_5\ : STD_LOGIC;
  signal \sumYB_reg[22]_i_1_n_6\ : STD_LOGIC;
  signal \sumYB_reg[22]_i_1_n_7\ : STD_LOGIC;
  signal \sumYB_reg[22]_i_1_n_9\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \sumYB_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[0]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[10]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[11]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[12]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[13]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[14]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[15]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[16]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[17]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[18]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[19]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[1]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[20]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[21]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[22]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[2]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[3]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[4]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[5]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[6]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[7]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[8]\ : STD_LOGIC;
  signal \sumYB_reg_n_0_[9]\ : STD_LOGIC;
  signal \sumY[15]_i_10_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_11_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_12_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_13_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_14_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_15_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_16_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_17_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_2_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_3_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_4_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_5_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_6_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_7_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_8_n_0\ : STD_LOGIC;
  signal \sumY[15]_i_9_n_0\ : STD_LOGIC;
  signal \sumY[22]_i_10_n_0\ : STD_LOGIC;
  signal \sumY[22]_i_11_n_0\ : STD_LOGIC;
  signal \sumY[22]_i_12_n_0\ : STD_LOGIC;
  signal \sumY[22]_i_13_n_0\ : STD_LOGIC;
  signal \sumY[22]_i_14_n_0\ : STD_LOGIC;
  signal \sumY[22]_i_2_n_0\ : STD_LOGIC;
  signal \sumY[22]_i_3_n_0\ : STD_LOGIC;
  signal \sumY[22]_i_4_n_0\ : STD_LOGIC;
  signal \sumY[22]_i_5_n_0\ : STD_LOGIC;
  signal \sumY[22]_i_6_n_0\ : STD_LOGIC;
  signal \sumY[22]_i_7_n_0\ : STD_LOGIC;
  signal \sumY[22]_i_8_n_0\ : STD_LOGIC;
  signal \sumY[22]_i_9_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_10_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_11_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_12_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_13_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_14_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_15_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_16_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_17_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_2_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_3_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_4_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_5_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_6_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_7_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_8_n_0\ : STD_LOGIC;
  signal \sumY[7]_i_9_n_0\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_10\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_11\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_12\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_13\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_14\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_15\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_8\ : STD_LOGIC;
  signal \sumY_reg[15]_i_1_n_9\ : STD_LOGIC;
  signal \sumY_reg[22]_i_1_n_10\ : STD_LOGIC;
  signal \sumY_reg[22]_i_1_n_11\ : STD_LOGIC;
  signal \sumY_reg[22]_i_1_n_12\ : STD_LOGIC;
  signal \sumY_reg[22]_i_1_n_13\ : STD_LOGIC;
  signal \sumY_reg[22]_i_1_n_14\ : STD_LOGIC;
  signal \sumY_reg[22]_i_1_n_15\ : STD_LOGIC;
  signal \sumY_reg[22]_i_1_n_2\ : STD_LOGIC;
  signal \sumY_reg[22]_i_1_n_3\ : STD_LOGIC;
  signal \sumY_reg[22]_i_1_n_4\ : STD_LOGIC;
  signal \sumY_reg[22]_i_1_n_5\ : STD_LOGIC;
  signal \sumY_reg[22]_i_1_n_6\ : STD_LOGIC;
  signal \sumY_reg[22]_i_1_n_7\ : STD_LOGIC;
  signal \sumY_reg[22]_i_1_n_9\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_10\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_11\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_12\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_13\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_14\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_15\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_8\ : STD_LOGIC;
  signal \sumY_reg[7]_i_1_n_9\ : STD_LOGIC;
  signal \sumY_reg_n_0_[0]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[10]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[11]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[12]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[13]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[14]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[15]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[16]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[17]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[18]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[19]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[1]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[20]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[21]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[22]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[2]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[3]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[4]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[5]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[6]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[7]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[8]\ : STD_LOGIC;
  signal \sumY_reg_n_0_[9]\ : STD_LOGIC;
  signal termI : STD_LOGIC_VECTOR ( 45 downto 0 );
  signal \termI0__0_n_100\ : STD_LOGIC;
  signal \termI0__0_n_101\ : STD_LOGIC;
  signal \termI0__0_n_102\ : STD_LOGIC;
  signal \termI0__0_n_103\ : STD_LOGIC;
  signal \termI0__0_n_104\ : STD_LOGIC;
  signal \termI0__0_n_105\ : STD_LOGIC;
  signal \termI0__0_n_77\ : STD_LOGIC;
  signal \termI0__0_n_78\ : STD_LOGIC;
  signal \termI0__0_n_79\ : STD_LOGIC;
  signal \termI0__0_n_80\ : STD_LOGIC;
  signal \termI0__0_n_81\ : STD_LOGIC;
  signal \termI0__0_n_82\ : STD_LOGIC;
  signal \termI0__0_n_83\ : STD_LOGIC;
  signal \termI0__0_n_84\ : STD_LOGIC;
  signal \termI0__0_n_85\ : STD_LOGIC;
  signal \termI0__0_n_86\ : STD_LOGIC;
  signal \termI0__0_n_87\ : STD_LOGIC;
  signal \termI0__0_n_88\ : STD_LOGIC;
  signal \termI0__0_n_89\ : STD_LOGIC;
  signal \termI0__0_n_90\ : STD_LOGIC;
  signal \termI0__0_n_91\ : STD_LOGIC;
  signal \termI0__0_n_92\ : STD_LOGIC;
  signal \termI0__0_n_93\ : STD_LOGIC;
  signal \termI0__0_n_94\ : STD_LOGIC;
  signal \termI0__0_n_95\ : STD_LOGIC;
  signal \termI0__0_n_96\ : STD_LOGIC;
  signal \termI0__0_n_97\ : STD_LOGIC;
  signal \termI0__0_n_98\ : STD_LOGIC;
  signal \termI0__0_n_99\ : STD_LOGIC;
  signal termI0_n_100 : STD_LOGIC;
  signal termI0_n_101 : STD_LOGIC;
  signal termI0_n_102 : STD_LOGIC;
  signal termI0_n_103 : STD_LOGIC;
  signal termI0_n_104 : STD_LOGIC;
  signal termI0_n_105 : STD_LOGIC;
  signal termI0_n_106 : STD_LOGIC;
  signal termI0_n_107 : STD_LOGIC;
  signal termI0_n_108 : STD_LOGIC;
  signal termI0_n_109 : STD_LOGIC;
  signal termI0_n_110 : STD_LOGIC;
  signal termI0_n_111 : STD_LOGIC;
  signal termI0_n_112 : STD_LOGIC;
  signal termI0_n_113 : STD_LOGIC;
  signal termI0_n_114 : STD_LOGIC;
  signal termI0_n_115 : STD_LOGIC;
  signal termI0_n_116 : STD_LOGIC;
  signal termI0_n_117 : STD_LOGIC;
  signal termI0_n_118 : STD_LOGIC;
  signal termI0_n_119 : STD_LOGIC;
  signal termI0_n_120 : STD_LOGIC;
  signal termI0_n_121 : STD_LOGIC;
  signal termI0_n_122 : STD_LOGIC;
  signal termI0_n_123 : STD_LOGIC;
  signal termI0_n_124 : STD_LOGIC;
  signal termI0_n_125 : STD_LOGIC;
  signal termI0_n_126 : STD_LOGIC;
  signal termI0_n_127 : STD_LOGIC;
  signal termI0_n_128 : STD_LOGIC;
  signal termI0_n_129 : STD_LOGIC;
  signal termI0_n_130 : STD_LOGIC;
  signal termI0_n_131 : STD_LOGIC;
  signal termI0_n_132 : STD_LOGIC;
  signal termI0_n_133 : STD_LOGIC;
  signal termI0_n_134 : STD_LOGIC;
  signal termI0_n_135 : STD_LOGIC;
  signal termI0_n_136 : STD_LOGIC;
  signal termI0_n_137 : STD_LOGIC;
  signal termI0_n_138 : STD_LOGIC;
  signal termI0_n_139 : STD_LOGIC;
  signal termI0_n_140 : STD_LOGIC;
  signal termI0_n_141 : STD_LOGIC;
  signal termI0_n_142 : STD_LOGIC;
  signal termI0_n_143 : STD_LOGIC;
  signal termI0_n_144 : STD_LOGIC;
  signal termI0_n_145 : STD_LOGIC;
  signal termI0_n_146 : STD_LOGIC;
  signal termI0_n_147 : STD_LOGIC;
  signal termI0_n_148 : STD_LOGIC;
  signal termI0_n_149 : STD_LOGIC;
  signal termI0_n_150 : STD_LOGIC;
  signal termI0_n_151 : STD_LOGIC;
  signal termI0_n_152 : STD_LOGIC;
  signal termI0_n_153 : STD_LOGIC;
  signal termI0_n_58 : STD_LOGIC;
  signal termI0_n_59 : STD_LOGIC;
  signal termI0_n_60 : STD_LOGIC;
  signal termI0_n_61 : STD_LOGIC;
  signal termI0_n_62 : STD_LOGIC;
  signal termI0_n_63 : STD_LOGIC;
  signal termI0_n_64 : STD_LOGIC;
  signal termI0_n_65 : STD_LOGIC;
  signal termI0_n_66 : STD_LOGIC;
  signal termI0_n_67 : STD_LOGIC;
  signal termI0_n_68 : STD_LOGIC;
  signal termI0_n_69 : STD_LOGIC;
  signal termI0_n_70 : STD_LOGIC;
  signal termI0_n_71 : STD_LOGIC;
  signal termI0_n_72 : STD_LOGIC;
  signal termI0_n_73 : STD_LOGIC;
  signal termI0_n_74 : STD_LOGIC;
  signal termI0_n_75 : STD_LOGIC;
  signal termI0_n_76 : STD_LOGIC;
  signal termI0_n_77 : STD_LOGIC;
  signal termI0_n_78 : STD_LOGIC;
  signal termI0_n_79 : STD_LOGIC;
  signal termI0_n_80 : STD_LOGIC;
  signal termI0_n_81 : STD_LOGIC;
  signal termI0_n_82 : STD_LOGIC;
  signal termI0_n_83 : STD_LOGIC;
  signal termI0_n_84 : STD_LOGIC;
  signal termI0_n_85 : STD_LOGIC;
  signal termI0_n_86 : STD_LOGIC;
  signal termI0_n_87 : STD_LOGIC;
  signal termI0_n_88 : STD_LOGIC;
  signal termI0_n_89 : STD_LOGIC;
  signal termI0_n_90 : STD_LOGIC;
  signal termI0_n_91 : STD_LOGIC;
  signal termI0_n_92 : STD_LOGIC;
  signal termI0_n_93 : STD_LOGIC;
  signal termI0_n_94 : STD_LOGIC;
  signal termI0_n_95 : STD_LOGIC;
  signal termI0_n_96 : STD_LOGIC;
  signal termI0_n_97 : STD_LOGIC;
  signal termI0_n_98 : STD_LOGIC;
  signal termI0_n_99 : STD_LOGIC;
  signal \termII0__0_n_100\ : STD_LOGIC;
  signal \termII0__0_n_101\ : STD_LOGIC;
  signal \termII0__0_n_102\ : STD_LOGIC;
  signal \termII0__0_n_103\ : STD_LOGIC;
  signal \termII0__0_n_104\ : STD_LOGIC;
  signal \termII0__0_n_105\ : STD_LOGIC;
  signal \termII0__0_n_77\ : STD_LOGIC;
  signal \termII0__0_n_78\ : STD_LOGIC;
  signal \termII0__0_n_79\ : STD_LOGIC;
  signal \termII0__0_n_80\ : STD_LOGIC;
  signal \termII0__0_n_81\ : STD_LOGIC;
  signal \termII0__0_n_82\ : STD_LOGIC;
  signal \termII0__0_n_83\ : STD_LOGIC;
  signal \termII0__0_n_84\ : STD_LOGIC;
  signal \termII0__0_n_85\ : STD_LOGIC;
  signal \termII0__0_n_86\ : STD_LOGIC;
  signal \termII0__0_n_87\ : STD_LOGIC;
  signal \termII0__0_n_88\ : STD_LOGIC;
  signal \termII0__0_n_89\ : STD_LOGIC;
  signal \termII0__0_n_90\ : STD_LOGIC;
  signal \termII0__0_n_91\ : STD_LOGIC;
  signal \termII0__0_n_92\ : STD_LOGIC;
  signal \termII0__0_n_93\ : STD_LOGIC;
  signal \termII0__0_n_94\ : STD_LOGIC;
  signal \termII0__0_n_95\ : STD_LOGIC;
  signal \termII0__0_n_96\ : STD_LOGIC;
  signal \termII0__0_n_97\ : STD_LOGIC;
  signal \termII0__0_n_98\ : STD_LOGIC;
  signal \termII0__0_n_99\ : STD_LOGIC;
  signal termII0_n_100 : STD_LOGIC;
  signal termII0_n_101 : STD_LOGIC;
  signal termII0_n_102 : STD_LOGIC;
  signal termII0_n_103 : STD_LOGIC;
  signal termII0_n_104 : STD_LOGIC;
  signal termII0_n_105 : STD_LOGIC;
  signal termII0_n_106 : STD_LOGIC;
  signal termII0_n_107 : STD_LOGIC;
  signal termII0_n_108 : STD_LOGIC;
  signal termII0_n_109 : STD_LOGIC;
  signal termII0_n_110 : STD_LOGIC;
  signal termII0_n_111 : STD_LOGIC;
  signal termII0_n_112 : STD_LOGIC;
  signal termII0_n_113 : STD_LOGIC;
  signal termII0_n_114 : STD_LOGIC;
  signal termII0_n_115 : STD_LOGIC;
  signal termII0_n_116 : STD_LOGIC;
  signal termII0_n_117 : STD_LOGIC;
  signal termII0_n_118 : STD_LOGIC;
  signal termII0_n_119 : STD_LOGIC;
  signal termII0_n_120 : STD_LOGIC;
  signal termII0_n_121 : STD_LOGIC;
  signal termII0_n_122 : STD_LOGIC;
  signal termII0_n_123 : STD_LOGIC;
  signal termII0_n_124 : STD_LOGIC;
  signal termII0_n_125 : STD_LOGIC;
  signal termII0_n_126 : STD_LOGIC;
  signal termII0_n_127 : STD_LOGIC;
  signal termII0_n_128 : STD_LOGIC;
  signal termII0_n_129 : STD_LOGIC;
  signal termII0_n_130 : STD_LOGIC;
  signal termII0_n_131 : STD_LOGIC;
  signal termII0_n_132 : STD_LOGIC;
  signal termII0_n_133 : STD_LOGIC;
  signal termII0_n_134 : STD_LOGIC;
  signal termII0_n_135 : STD_LOGIC;
  signal termII0_n_136 : STD_LOGIC;
  signal termII0_n_137 : STD_LOGIC;
  signal termII0_n_138 : STD_LOGIC;
  signal termII0_n_139 : STD_LOGIC;
  signal termII0_n_140 : STD_LOGIC;
  signal termII0_n_141 : STD_LOGIC;
  signal termII0_n_142 : STD_LOGIC;
  signal termII0_n_143 : STD_LOGIC;
  signal termII0_n_144 : STD_LOGIC;
  signal termII0_n_145 : STD_LOGIC;
  signal termII0_n_146 : STD_LOGIC;
  signal termII0_n_147 : STD_LOGIC;
  signal termII0_n_148 : STD_LOGIC;
  signal termII0_n_149 : STD_LOGIC;
  signal termII0_n_150 : STD_LOGIC;
  signal termII0_n_151 : STD_LOGIC;
  signal termII0_n_152 : STD_LOGIC;
  signal termII0_n_153 : STD_LOGIC;
  signal termII0_n_58 : STD_LOGIC;
  signal termII0_n_59 : STD_LOGIC;
  signal termII0_n_60 : STD_LOGIC;
  signal termII0_n_61 : STD_LOGIC;
  signal termII0_n_62 : STD_LOGIC;
  signal termII0_n_63 : STD_LOGIC;
  signal termII0_n_64 : STD_LOGIC;
  signal termII0_n_65 : STD_LOGIC;
  signal termII0_n_66 : STD_LOGIC;
  signal termII0_n_67 : STD_LOGIC;
  signal termII0_n_68 : STD_LOGIC;
  signal termII0_n_69 : STD_LOGIC;
  signal termII0_n_70 : STD_LOGIC;
  signal termII0_n_71 : STD_LOGIC;
  signal termII0_n_72 : STD_LOGIC;
  signal termII0_n_73 : STD_LOGIC;
  signal termII0_n_74 : STD_LOGIC;
  signal termII0_n_75 : STD_LOGIC;
  signal termII0_n_76 : STD_LOGIC;
  signal termII0_n_77 : STD_LOGIC;
  signal termII0_n_78 : STD_LOGIC;
  signal termII0_n_79 : STD_LOGIC;
  signal termII0_n_80 : STD_LOGIC;
  signal termII0_n_81 : STD_LOGIC;
  signal termII0_n_82 : STD_LOGIC;
  signal termII0_n_83 : STD_LOGIC;
  signal termII0_n_84 : STD_LOGIC;
  signal termII0_n_85 : STD_LOGIC;
  signal termII0_n_86 : STD_LOGIC;
  signal termII0_n_87 : STD_LOGIC;
  signal termII0_n_88 : STD_LOGIC;
  signal termII0_n_89 : STD_LOGIC;
  signal termII0_n_90 : STD_LOGIC;
  signal termII0_n_91 : STD_LOGIC;
  signal termII0_n_92 : STD_LOGIC;
  signal termII0_n_93 : STD_LOGIC;
  signal termII0_n_94 : STD_LOGIC;
  signal termII0_n_95 : STD_LOGIC;
  signal termII0_n_96 : STD_LOGIC;
  signal termII0_n_97 : STD_LOGIC;
  signal termII0_n_98 : STD_LOGIC;
  signal termII0_n_99 : STD_LOGIC;
  signal termIII : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal \termIII0__0_n_100\ : STD_LOGIC;
  signal \termIII0__0_n_101\ : STD_LOGIC;
  signal \termIII0__0_n_102\ : STD_LOGIC;
  signal \termIII0__0_n_103\ : STD_LOGIC;
  signal \termIII0__0_n_104\ : STD_LOGIC;
  signal \termIII0__0_n_105\ : STD_LOGIC;
  signal \termIII0__0_n_75\ : STD_LOGIC;
  signal \termIII0__0_n_76\ : STD_LOGIC;
  signal \termIII0__0_n_77\ : STD_LOGIC;
  signal \termIII0__0_n_78\ : STD_LOGIC;
  signal \termIII0__0_n_79\ : STD_LOGIC;
  signal \termIII0__0_n_80\ : STD_LOGIC;
  signal \termIII0__0_n_81\ : STD_LOGIC;
  signal \termIII0__0_n_82\ : STD_LOGIC;
  signal \termIII0__0_n_83\ : STD_LOGIC;
  signal \termIII0__0_n_84\ : STD_LOGIC;
  signal \termIII0__0_n_85\ : STD_LOGIC;
  signal \termIII0__0_n_86\ : STD_LOGIC;
  signal \termIII0__0_n_87\ : STD_LOGIC;
  signal \termIII0__0_n_88\ : STD_LOGIC;
  signal \termIII0__0_n_89\ : STD_LOGIC;
  signal \termIII0__0_n_90\ : STD_LOGIC;
  signal \termIII0__0_n_91\ : STD_LOGIC;
  signal \termIII0__0_n_92\ : STD_LOGIC;
  signal \termIII0__0_n_93\ : STD_LOGIC;
  signal \termIII0__0_n_94\ : STD_LOGIC;
  signal \termIII0__0_n_95\ : STD_LOGIC;
  signal \termIII0__0_n_96\ : STD_LOGIC;
  signal \termIII0__0_n_97\ : STD_LOGIC;
  signal \termIII0__0_n_98\ : STD_LOGIC;
  signal \termIII0__0_n_99\ : STD_LOGIC;
  signal termIII0_n_100 : STD_LOGIC;
  signal termIII0_n_101 : STD_LOGIC;
  signal termIII0_n_102 : STD_LOGIC;
  signal termIII0_n_103 : STD_LOGIC;
  signal termIII0_n_104 : STD_LOGIC;
  signal termIII0_n_105 : STD_LOGIC;
  signal termIII0_n_106 : STD_LOGIC;
  signal termIII0_n_107 : STD_LOGIC;
  signal termIII0_n_108 : STD_LOGIC;
  signal termIII0_n_109 : STD_LOGIC;
  signal termIII0_n_110 : STD_LOGIC;
  signal termIII0_n_111 : STD_LOGIC;
  signal termIII0_n_112 : STD_LOGIC;
  signal termIII0_n_113 : STD_LOGIC;
  signal termIII0_n_114 : STD_LOGIC;
  signal termIII0_n_115 : STD_LOGIC;
  signal termIII0_n_116 : STD_LOGIC;
  signal termIII0_n_117 : STD_LOGIC;
  signal termIII0_n_118 : STD_LOGIC;
  signal termIII0_n_119 : STD_LOGIC;
  signal termIII0_n_120 : STD_LOGIC;
  signal termIII0_n_121 : STD_LOGIC;
  signal termIII0_n_122 : STD_LOGIC;
  signal termIII0_n_123 : STD_LOGIC;
  signal termIII0_n_124 : STD_LOGIC;
  signal termIII0_n_125 : STD_LOGIC;
  signal termIII0_n_126 : STD_LOGIC;
  signal termIII0_n_127 : STD_LOGIC;
  signal termIII0_n_128 : STD_LOGIC;
  signal termIII0_n_129 : STD_LOGIC;
  signal termIII0_n_130 : STD_LOGIC;
  signal termIII0_n_131 : STD_LOGIC;
  signal termIII0_n_132 : STD_LOGIC;
  signal termIII0_n_133 : STD_LOGIC;
  signal termIII0_n_134 : STD_LOGIC;
  signal termIII0_n_135 : STD_LOGIC;
  signal termIII0_n_136 : STD_LOGIC;
  signal termIII0_n_137 : STD_LOGIC;
  signal termIII0_n_138 : STD_LOGIC;
  signal termIII0_n_139 : STD_LOGIC;
  signal termIII0_n_140 : STD_LOGIC;
  signal termIII0_n_141 : STD_LOGIC;
  signal termIII0_n_142 : STD_LOGIC;
  signal termIII0_n_143 : STD_LOGIC;
  signal termIII0_n_144 : STD_LOGIC;
  signal termIII0_n_145 : STD_LOGIC;
  signal termIII0_n_146 : STD_LOGIC;
  signal termIII0_n_147 : STD_LOGIC;
  signal termIII0_n_148 : STD_LOGIC;
  signal termIII0_n_149 : STD_LOGIC;
  signal termIII0_n_150 : STD_LOGIC;
  signal termIII0_n_151 : STD_LOGIC;
  signal termIII0_n_152 : STD_LOGIC;
  signal termIII0_n_153 : STD_LOGIC;
  signal termIII0_n_58 : STD_LOGIC;
  signal termIII0_n_59 : STD_LOGIC;
  signal termIII0_n_60 : STD_LOGIC;
  signal termIII0_n_61 : STD_LOGIC;
  signal termIII0_n_62 : STD_LOGIC;
  signal termIII0_n_63 : STD_LOGIC;
  signal termIII0_n_64 : STD_LOGIC;
  signal termIII0_n_65 : STD_LOGIC;
  signal termIII0_n_66 : STD_LOGIC;
  signal termIII0_n_67 : STD_LOGIC;
  signal termIII0_n_68 : STD_LOGIC;
  signal termIII0_n_69 : STD_LOGIC;
  signal termIII0_n_70 : STD_LOGIC;
  signal termIII0_n_71 : STD_LOGIC;
  signal termIII0_n_72 : STD_LOGIC;
  signal termIII0_n_73 : STD_LOGIC;
  signal termIII0_n_74 : STD_LOGIC;
  signal termIII0_n_75 : STD_LOGIC;
  signal termIII0_n_76 : STD_LOGIC;
  signal termIII0_n_77 : STD_LOGIC;
  signal termIII0_n_78 : STD_LOGIC;
  signal termIII0_n_79 : STD_LOGIC;
  signal termIII0_n_80 : STD_LOGIC;
  signal termIII0_n_81 : STD_LOGIC;
  signal termIII0_n_82 : STD_LOGIC;
  signal termIII0_n_83 : STD_LOGIC;
  signal termIII0_n_84 : STD_LOGIC;
  signal termIII0_n_85 : STD_LOGIC;
  signal termIII0_n_86 : STD_LOGIC;
  signal termIII0_n_87 : STD_LOGIC;
  signal termIII0_n_88 : STD_LOGIC;
  signal termIII0_n_89 : STD_LOGIC;
  signal termIII0_n_90 : STD_LOGIC;
  signal termIII0_n_91 : STD_LOGIC;
  signal termIII0_n_92 : STD_LOGIC;
  signal termIII0_n_93 : STD_LOGIC;
  signal termIII0_n_94 : STD_LOGIC;
  signal termIII0_n_95 : STD_LOGIC;
  signal termIII0_n_96 : STD_LOGIC;
  signal termIII0_n_97 : STD_LOGIC;
  signal termIII0_n_98 : STD_LOGIC;
  signal termIII0_n_99 : STD_LOGIC;
  signal \termIII[0]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[10]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[11]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[12]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[13]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[14]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[15]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[16]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[17]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[18]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[19]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[1]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[20]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[21]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[22]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[23]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[24]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[25]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[26]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[27]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[28]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[29]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[2]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[30]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[31]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[32]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[33]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[34]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[35]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[36]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[37]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[38]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[39]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[3]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[40]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[41]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[42]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[43]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[44]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[45]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[46]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[47]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[4]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[5]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[6]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[7]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[8]_i_1_n_0\ : STD_LOGIC;
  signal \termIII[9]_i_1_n_0\ : STD_LOGIC;
  signal termIIIk : STD_LOGIC_VECTOR ( 43 downto 0 );
  signal termIIIk0 : STD_LOGIC_VECTOR ( 50 downto 7 );
  signal \termIIIk[0]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[10]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[11]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[12]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[13]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[14]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[15]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[16]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[17]_i_10_n_0\ : STD_LOGIC;
  signal \termIIIk[17]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[17]_i_3_n_0\ : STD_LOGIC;
  signal \termIIIk[17]_i_4_n_0\ : STD_LOGIC;
  signal \termIIIk[17]_i_5_n_0\ : STD_LOGIC;
  signal \termIIIk[17]_i_6_n_0\ : STD_LOGIC;
  signal \termIIIk[17]_i_7_n_0\ : STD_LOGIC;
  signal \termIIIk[17]_i_8_n_0\ : STD_LOGIC;
  signal \termIIIk[17]_i_9_n_0\ : STD_LOGIC;
  signal \termIIIk[18]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[19]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[1]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[1]_i_3_n_0\ : STD_LOGIC;
  signal \termIIIk[1]_i_4_n_0\ : STD_LOGIC;
  signal \termIIIk[1]_i_5_n_0\ : STD_LOGIC;
  signal \termIIIk[1]_i_6_n_0\ : STD_LOGIC;
  signal \termIIIk[1]_i_7_n_0\ : STD_LOGIC;
  signal \termIIIk[1]_i_8_n_0\ : STD_LOGIC;
  signal \termIIIk[1]_i_9_n_0\ : STD_LOGIC;
  signal \termIIIk[20]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[21]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[22]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[23]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[24]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[25]_i_10_n_0\ : STD_LOGIC;
  signal \termIIIk[25]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[25]_i_3_n_0\ : STD_LOGIC;
  signal \termIIIk[25]_i_4_n_0\ : STD_LOGIC;
  signal \termIIIk[25]_i_5_n_0\ : STD_LOGIC;
  signal \termIIIk[25]_i_6_n_0\ : STD_LOGIC;
  signal \termIIIk[25]_i_7_n_0\ : STD_LOGIC;
  signal \termIIIk[25]_i_8_n_0\ : STD_LOGIC;
  signal \termIIIk[25]_i_9_n_0\ : STD_LOGIC;
  signal \termIIIk[26]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[27]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[28]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[29]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[2]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[30]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[31]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[32]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[33]_i_10_n_0\ : STD_LOGIC;
  signal \termIIIk[33]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[33]_i_3_n_0\ : STD_LOGIC;
  signal \termIIIk[33]_i_4_n_0\ : STD_LOGIC;
  signal \termIIIk[33]_i_5_n_0\ : STD_LOGIC;
  signal \termIIIk[33]_i_6_n_0\ : STD_LOGIC;
  signal \termIIIk[33]_i_7_n_0\ : STD_LOGIC;
  signal \termIIIk[33]_i_8_n_0\ : STD_LOGIC;
  signal \termIIIk[33]_i_9_n_0\ : STD_LOGIC;
  signal \termIIIk[34]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[35]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[36]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[37]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[38]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[39]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[3]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[40]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[41]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[41]_i_3_n_0\ : STD_LOGIC;
  signal \termIIIk[41]_i_4_n_0\ : STD_LOGIC;
  signal \termIIIk[41]_i_5_n_0\ : STD_LOGIC;
  signal \termIIIk[41]_i_6_n_0\ : STD_LOGIC;
  signal \termIIIk[41]_i_7_n_0\ : STD_LOGIC;
  signal \termIIIk[41]_i_8_n_0\ : STD_LOGIC;
  signal \termIIIk[41]_i_9_n_0\ : STD_LOGIC;
  signal \termIIIk[42]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[43]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[4]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[5]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[6]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[7]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[8]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[9]_i_10_n_0\ : STD_LOGIC;
  signal \termIIIk[9]_i_1_n_0\ : STD_LOGIC;
  signal \termIIIk[9]_i_3_n_0\ : STD_LOGIC;
  signal \termIIIk[9]_i_4_n_0\ : STD_LOGIC;
  signal \termIIIk[9]_i_5_n_0\ : STD_LOGIC;
  signal \termIIIk[9]_i_6_n_0\ : STD_LOGIC;
  signal \termIIIk[9]_i_7_n_0\ : STD_LOGIC;
  signal \termIIIk[9]_i_8_n_0\ : STD_LOGIC;
  signal \termIIIk[9]_i_9_n_0\ : STD_LOGIC;
  signal \termIIIk_reg[17]_i_2_n_0\ : STD_LOGIC;
  signal \termIIIk_reg[17]_i_2_n_1\ : STD_LOGIC;
  signal \termIIIk_reg[17]_i_2_n_2\ : STD_LOGIC;
  signal \termIIIk_reg[17]_i_2_n_3\ : STD_LOGIC;
  signal \termIIIk_reg[17]_i_2_n_4\ : STD_LOGIC;
  signal \termIIIk_reg[17]_i_2_n_5\ : STD_LOGIC;
  signal \termIIIk_reg[17]_i_2_n_6\ : STD_LOGIC;
  signal \termIIIk_reg[17]_i_2_n_7\ : STD_LOGIC;
  signal \termIIIk_reg[1]_i_2_n_0\ : STD_LOGIC;
  signal \termIIIk_reg[1]_i_2_n_1\ : STD_LOGIC;
  signal \termIIIk_reg[1]_i_2_n_2\ : STD_LOGIC;
  signal \termIIIk_reg[1]_i_2_n_3\ : STD_LOGIC;
  signal \termIIIk_reg[1]_i_2_n_4\ : STD_LOGIC;
  signal \termIIIk_reg[1]_i_2_n_5\ : STD_LOGIC;
  signal \termIIIk_reg[1]_i_2_n_6\ : STD_LOGIC;
  signal \termIIIk_reg[1]_i_2_n_7\ : STD_LOGIC;
  signal \termIIIk_reg[25]_i_2_n_0\ : STD_LOGIC;
  signal \termIIIk_reg[25]_i_2_n_1\ : STD_LOGIC;
  signal \termIIIk_reg[25]_i_2_n_2\ : STD_LOGIC;
  signal \termIIIk_reg[25]_i_2_n_3\ : STD_LOGIC;
  signal \termIIIk_reg[25]_i_2_n_4\ : STD_LOGIC;
  signal \termIIIk_reg[25]_i_2_n_5\ : STD_LOGIC;
  signal \termIIIk_reg[25]_i_2_n_6\ : STD_LOGIC;
  signal \termIIIk_reg[25]_i_2_n_7\ : STD_LOGIC;
  signal \termIIIk_reg[33]_i_2_n_0\ : STD_LOGIC;
  signal \termIIIk_reg[33]_i_2_n_1\ : STD_LOGIC;
  signal \termIIIk_reg[33]_i_2_n_2\ : STD_LOGIC;
  signal \termIIIk_reg[33]_i_2_n_3\ : STD_LOGIC;
  signal \termIIIk_reg[33]_i_2_n_4\ : STD_LOGIC;
  signal \termIIIk_reg[33]_i_2_n_5\ : STD_LOGIC;
  signal \termIIIk_reg[33]_i_2_n_6\ : STD_LOGIC;
  signal \termIIIk_reg[33]_i_2_n_7\ : STD_LOGIC;
  signal \termIIIk_reg[41]_i_2_n_0\ : STD_LOGIC;
  signal \termIIIk_reg[41]_i_2_n_1\ : STD_LOGIC;
  signal \termIIIk_reg[41]_i_2_n_2\ : STD_LOGIC;
  signal \termIIIk_reg[41]_i_2_n_3\ : STD_LOGIC;
  signal \termIIIk_reg[41]_i_2_n_4\ : STD_LOGIC;
  signal \termIIIk_reg[41]_i_2_n_5\ : STD_LOGIC;
  signal \termIIIk_reg[41]_i_2_n_6\ : STD_LOGIC;
  signal \termIIIk_reg[41]_i_2_n_7\ : STD_LOGIC;
  signal \termIIIk_reg[9]_i_2_n_0\ : STD_LOGIC;
  signal \termIIIk_reg[9]_i_2_n_1\ : STD_LOGIC;
  signal \termIIIk_reg[9]_i_2_n_2\ : STD_LOGIC;
  signal \termIIIk_reg[9]_i_2_n_3\ : STD_LOGIC;
  signal \termIIIk_reg[9]_i_2_n_4\ : STD_LOGIC;
  signal \termIIIk_reg[9]_i_2_n_5\ : STD_LOGIC;
  signal \termIIIk_reg[9]_i_2_n_6\ : STD_LOGIC;
  signal \termIIIk_reg[9]_i_2_n_7\ : STD_LOGIC;
  signal \termII[0]_i_1_n_0\ : STD_LOGIC;
  signal \termII[10]_i_1_n_0\ : STD_LOGIC;
  signal \termII[11]_i_1_n_0\ : STD_LOGIC;
  signal \termII[12]_i_1_n_0\ : STD_LOGIC;
  signal \termII[13]_i_1_n_0\ : STD_LOGIC;
  signal \termII[14]_i_1_n_0\ : STD_LOGIC;
  signal \termII[15]_i_1_n_0\ : STD_LOGIC;
  signal \termII[16]_i_1_n_0\ : STD_LOGIC;
  signal \termII[17]_i_1_n_0\ : STD_LOGIC;
  signal \termII[18]_i_1_n_0\ : STD_LOGIC;
  signal \termII[19]_i_1_n_0\ : STD_LOGIC;
  signal \termII[1]_i_1_n_0\ : STD_LOGIC;
  signal \termII[20]_i_1_n_0\ : STD_LOGIC;
  signal \termII[21]_i_1_n_0\ : STD_LOGIC;
  signal \termII[22]_i_1_n_0\ : STD_LOGIC;
  signal \termII[23]_i_1_n_0\ : STD_LOGIC;
  signal \termII[24]_i_1_n_0\ : STD_LOGIC;
  signal \termII[25]_i_1_n_0\ : STD_LOGIC;
  signal \termII[26]_i_1_n_0\ : STD_LOGIC;
  signal \termII[27]_i_1_n_0\ : STD_LOGIC;
  signal \termII[28]_i_1_n_0\ : STD_LOGIC;
  signal \termII[29]_i_1_n_0\ : STD_LOGIC;
  signal \termII[2]_i_1_n_0\ : STD_LOGIC;
  signal \termII[30]_i_1_n_0\ : STD_LOGIC;
  signal \termII[31]_i_1_n_0\ : STD_LOGIC;
  signal \termII[32]_i_1_n_0\ : STD_LOGIC;
  signal \termII[33]_i_1_n_0\ : STD_LOGIC;
  signal \termII[34]_i_1_n_0\ : STD_LOGIC;
  signal \termII[35]_i_1_n_0\ : STD_LOGIC;
  signal \termII[36]_i_1_n_0\ : STD_LOGIC;
  signal \termII[37]_i_1_n_0\ : STD_LOGIC;
  signal \termII[38]_i_1_n_0\ : STD_LOGIC;
  signal \termII[39]_i_1_n_0\ : STD_LOGIC;
  signal \termII[3]_i_1_n_0\ : STD_LOGIC;
  signal \termII[40]_i_1_n_0\ : STD_LOGIC;
  signal \termII[41]_i_1_n_0\ : STD_LOGIC;
  signal \termII[42]_i_1_n_0\ : STD_LOGIC;
  signal \termII[43]_i_1_n_0\ : STD_LOGIC;
  signal \termII[44]_i_1_n_0\ : STD_LOGIC;
  signal \termII[45]_i_1_n_0\ : STD_LOGIC;
  signal \termII[4]_i_1_n_0\ : STD_LOGIC;
  signal \termII[5]_i_1_n_0\ : STD_LOGIC;
  signal \termII[6]_i_1_n_0\ : STD_LOGIC;
  signal \termII[7]_i_1_n_0\ : STD_LOGIC;
  signal \termII[8]_i_1_n_0\ : STD_LOGIC;
  signal \termII[9]_i_1_n_0\ : STD_LOGIC;
  signal \termII_reg_n_0_[0]\ : STD_LOGIC;
  signal \termII_reg_n_0_[10]\ : STD_LOGIC;
  signal \termII_reg_n_0_[11]\ : STD_LOGIC;
  signal \termII_reg_n_0_[12]\ : STD_LOGIC;
  signal \termII_reg_n_0_[13]\ : STD_LOGIC;
  signal \termII_reg_n_0_[14]\ : STD_LOGIC;
  signal \termII_reg_n_0_[15]\ : STD_LOGIC;
  signal \termII_reg_n_0_[16]\ : STD_LOGIC;
  signal \termII_reg_n_0_[17]\ : STD_LOGIC;
  signal \termII_reg_n_0_[18]\ : STD_LOGIC;
  signal \termII_reg_n_0_[19]\ : STD_LOGIC;
  signal \termII_reg_n_0_[1]\ : STD_LOGIC;
  signal \termII_reg_n_0_[20]\ : STD_LOGIC;
  signal \termII_reg_n_0_[21]\ : STD_LOGIC;
  signal \termII_reg_n_0_[22]\ : STD_LOGIC;
  signal \termII_reg_n_0_[23]\ : STD_LOGIC;
  signal \termII_reg_n_0_[24]\ : STD_LOGIC;
  signal \termII_reg_n_0_[25]\ : STD_LOGIC;
  signal \termII_reg_n_0_[26]\ : STD_LOGIC;
  signal \termII_reg_n_0_[27]\ : STD_LOGIC;
  signal \termII_reg_n_0_[28]\ : STD_LOGIC;
  signal \termII_reg_n_0_[29]\ : STD_LOGIC;
  signal \termII_reg_n_0_[2]\ : STD_LOGIC;
  signal \termII_reg_n_0_[30]\ : STD_LOGIC;
  signal \termII_reg_n_0_[31]\ : STD_LOGIC;
  signal \termII_reg_n_0_[32]\ : STD_LOGIC;
  signal \termII_reg_n_0_[33]\ : STD_LOGIC;
  signal \termII_reg_n_0_[34]\ : STD_LOGIC;
  signal \termII_reg_n_0_[35]\ : STD_LOGIC;
  signal \termII_reg_n_0_[36]\ : STD_LOGIC;
  signal \termII_reg_n_0_[37]\ : STD_LOGIC;
  signal \termII_reg_n_0_[38]\ : STD_LOGIC;
  signal \termII_reg_n_0_[39]\ : STD_LOGIC;
  signal \termII_reg_n_0_[3]\ : STD_LOGIC;
  signal \termII_reg_n_0_[40]\ : STD_LOGIC;
  signal \termII_reg_n_0_[41]\ : STD_LOGIC;
  signal \termII_reg_n_0_[42]\ : STD_LOGIC;
  signal \termII_reg_n_0_[43]\ : STD_LOGIC;
  signal \termII_reg_n_0_[44]\ : STD_LOGIC;
  signal \termII_reg_n_0_[45]\ : STD_LOGIC;
  signal \termII_reg_n_0_[4]\ : STD_LOGIC;
  signal \termII_reg_n_0_[5]\ : STD_LOGIC;
  signal \termII_reg_n_0_[6]\ : STD_LOGIC;
  signal \termII_reg_n_0_[7]\ : STD_LOGIC;
  signal \termII_reg_n_0_[8]\ : STD_LOGIC;
  signal \termII_reg_n_0_[9]\ : STD_LOGIC;
  signal \termI[0]_i_1_n_0\ : STD_LOGIC;
  signal \termI[10]_i_1_n_0\ : STD_LOGIC;
  signal \termI[11]_i_1_n_0\ : STD_LOGIC;
  signal \termI[12]_i_1_n_0\ : STD_LOGIC;
  signal \termI[13]_i_1_n_0\ : STD_LOGIC;
  signal \termI[14]_i_1_n_0\ : STD_LOGIC;
  signal \termI[15]_i_1_n_0\ : STD_LOGIC;
  signal \termI[16]_i_1_n_0\ : STD_LOGIC;
  signal \termI[17]_i_1_n_0\ : STD_LOGIC;
  signal \termI[18]_i_1_n_0\ : STD_LOGIC;
  signal \termI[19]_i_1_n_0\ : STD_LOGIC;
  signal \termI[1]_i_1_n_0\ : STD_LOGIC;
  signal \termI[20]_i_1_n_0\ : STD_LOGIC;
  signal \termI[21]_i_1_n_0\ : STD_LOGIC;
  signal \termI[22]_i_1_n_0\ : STD_LOGIC;
  signal \termI[23]_i_1_n_0\ : STD_LOGIC;
  signal \termI[24]_i_1_n_0\ : STD_LOGIC;
  signal \termI[25]_i_1_n_0\ : STD_LOGIC;
  signal \termI[26]_i_1_n_0\ : STD_LOGIC;
  signal \termI[27]_i_1_n_0\ : STD_LOGIC;
  signal \termI[28]_i_1_n_0\ : STD_LOGIC;
  signal \termI[29]_i_1_n_0\ : STD_LOGIC;
  signal \termI[2]_i_1_n_0\ : STD_LOGIC;
  signal \termI[30]_i_1_n_0\ : STD_LOGIC;
  signal \termI[31]_i_1_n_0\ : STD_LOGIC;
  signal \termI[32]_i_1_n_0\ : STD_LOGIC;
  signal \termI[33]_i_1_n_0\ : STD_LOGIC;
  signal \termI[34]_i_1_n_0\ : STD_LOGIC;
  signal \termI[35]_i_1_n_0\ : STD_LOGIC;
  signal \termI[36]_i_1_n_0\ : STD_LOGIC;
  signal \termI[37]_i_1_n_0\ : STD_LOGIC;
  signal \termI[38]_i_1_n_0\ : STD_LOGIC;
  signal \termI[39]_i_1_n_0\ : STD_LOGIC;
  signal \termI[3]_i_1_n_0\ : STD_LOGIC;
  signal \termI[40]_i_1_n_0\ : STD_LOGIC;
  signal \termI[41]_i_1_n_0\ : STD_LOGIC;
  signal \termI[42]_i_1_n_0\ : STD_LOGIC;
  signal \termI[43]_i_1_n_0\ : STD_LOGIC;
  signal \termI[44]_i_1_n_0\ : STD_LOGIC;
  signal \termI[45]_i_1_n_0\ : STD_LOGIC;
  signal \termI[4]_i_1_n_0\ : STD_LOGIC;
  signal \termI[5]_i_1_n_0\ : STD_LOGIC;
  signal \termI[6]_i_1_n_0\ : STD_LOGIC;
  signal \termI[7]_i_1_n_0\ : STD_LOGIC;
  signal \termI[8]_i_1_n_0\ : STD_LOGIC;
  signal \termI[9]_i_1_n_0\ : STD_LOGIC;
  signal \thd_reg_n_0_[0]\ : STD_LOGIC;
  signal \thd_reg_n_0_[1]\ : STD_LOGIC;
  signal \thd_reg_n_0_[2]\ : STD_LOGIC;
  signal \thd_reg_n_0_[3]\ : STD_LOGIC;
  signal \thd_reg_n_0_[4]\ : STD_LOGIC;
  signal \thd_reg_n_0_[5]\ : STD_LOGIC;
  signal \thd_reg_n_0_[6]\ : STD_LOGIC;
  signal \thd_reg_n_0_[7]\ : STD_LOGIC;
  signal \^tixvstate_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal tkst : STD_LOGIC;
  signal vsync_last_i_1_n_0 : STD_LOGIC;
  signal vsync_last_reg_n_0 : STD_LOGIC;
  signal xsqr0 : STD_LOGIC_VECTOR ( 17 downto 2 );
  signal xsqr00_in : STD_LOGIC_VECTOR ( 17 downto 2 );
  signal xsqr01_in : STD_LOGIC_VECTOR ( 17 downto 2 );
  signal xsqr02_in : STD_LOGIC_VECTOR ( 17 downto 2 );
  signal xsqr03_in : STD_LOGIC_VECTOR ( 17 downto 2 );
  signal xsqr4p1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \xsqr4p1[0]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[10]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[11]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[12]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[13]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[14]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[15]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[16]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[17]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[2]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[3]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[4]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[5]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[6]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[7]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[8]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p1[9]_i_1_n_0\ : STD_LOGIC;
  signal xsqr4p2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \xsqr4p2[0]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[10]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[11]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[12]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[13]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[14]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[15]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[16]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[17]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[2]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[3]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[4]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[5]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[6]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[7]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[8]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr4p2[9]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[0]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[10]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_17_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_18_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_19_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_3_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_4_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[11]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[12]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[13]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[14]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[15]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[16]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_19_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_20_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_21_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_22_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_23_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_24_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_25_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_26_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_27_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_28_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_29_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_30_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_31_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_32_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_33_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_34_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_35_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_36_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_37_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_38_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_39_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_40_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_41_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_42_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_43_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_44_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_45_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_4_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[17]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[18]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[20]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_17_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_18_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_19_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_20_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_21_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_22_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_23_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_24_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_25_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_26_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_27_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_28_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_29_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_30_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_31_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_32_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_33_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_4_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[21]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[22]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[23]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[24]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[25]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[26]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[27]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[28]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_17_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_18_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_19_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_3_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_4_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[29]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[2]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[30]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[31]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[32]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[33]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[34]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_19_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_20_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_21_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_22_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_23_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_24_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_25_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_26_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_27_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_28_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_29_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_30_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_31_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_32_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_33_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_34_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_35_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_36_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_37_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_38_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_39_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_40_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_41_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_42_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_43_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_44_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_45_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_4_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[35]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[36]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[38]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_17_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_18_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_19_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_20_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_21_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_22_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_23_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_24_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_25_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_26_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_27_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_28_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_29_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_30_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_31_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_32_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_33_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_4_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[39]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_17_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_18_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_19_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_20_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_21_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_22_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_23_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_24_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_25_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_26_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_27_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_28_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_29_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_30_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_31_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_32_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_33_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_4_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[3]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[40]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[41]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[42]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[43]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[44]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[45]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[46]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_17_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_18_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_19_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_3_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_4_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[47]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[48]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[49]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[4]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[50]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[51]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[52]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_19_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_20_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_21_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_22_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_23_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_24_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_25_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_26_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_27_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_28_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_29_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_30_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_31_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_32_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_33_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_34_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_35_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_36_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_37_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_38_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_39_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_40_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_41_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_42_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_43_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_44_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_45_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_4_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[53]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[54]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[56]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_17_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_18_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_19_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_20_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_21_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_22_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_23_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_24_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_25_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_26_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_27_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_28_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_29_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_30_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_31_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_32_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_33_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_4_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[57]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[58]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[59]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[5]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[60]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[61]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[62]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[63]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[64]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_17_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_18_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_19_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_3_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_4_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[65]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[66]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[67]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[68]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[69]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[6]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[70]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_19_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_20_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_21_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_22_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_23_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_24_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_25_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_26_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_27_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_28_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_29_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_30_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_31_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_32_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_33_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_34_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_35_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_36_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_37_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_38_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_39_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_40_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_41_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_42_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_43_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_44_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_45_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_4_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[71]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[72]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[74]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_17_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_18_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_19_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_20_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_21_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_22_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_23_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_24_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_25_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_26_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_27_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_28_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_29_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_30_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_31_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_32_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_33_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_4_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[75]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[76]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[77]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[78]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[79]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[7]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[80]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[81]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[82]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_17_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_18_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_19_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_3_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_4_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[83]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[84]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[85]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[86]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[87]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[88]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_10_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_11_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_12_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_15_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_16_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_17_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_20_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_21_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_22_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_23_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_24_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_25_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_26_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_27_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_28_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_29_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_2_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_30_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_31_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_32_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_33_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_34_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_35_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_36_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_37_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_38_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_39_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_40_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_41_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_42_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_43_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_44_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_45_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_46_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_5_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_6_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_7_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_8_n_0\ : STD_LOGIC;
  signal \xsqr[89]_i_9_n_0\ : STD_LOGIC;
  signal \xsqr[8]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr[9]_i_1_n_0\ : STD_LOGIC;
  signal \xsqr_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \xsqr_reg[11]_i_2_n_1\ : STD_LOGIC;
  signal \xsqr_reg[11]_i_2_n_2\ : STD_LOGIC;
  signal \xsqr_reg[11]_i_2_n_3\ : STD_LOGIC;
  signal \xsqr_reg[11]_i_2_n_4\ : STD_LOGIC;
  signal \xsqr_reg[11]_i_2_n_5\ : STD_LOGIC;
  signal \xsqr_reg[11]_i_2_n_6\ : STD_LOGIC;
  signal \xsqr_reg[11]_i_2_n_7\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_1\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_10\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_11\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_12\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_13\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_14\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_15\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_2\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_3\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_4\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_5\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_6\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_7\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_8\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_13_n_9\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_17_n_13\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_17_n_14\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_17_n_15\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_17_n_4\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_17_n_6\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_17_n_7\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_18_n_14\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_18_n_15\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_18_n_5\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_18_n_7\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_2_n_3\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_2_n_4\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_2_n_5\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_2_n_6\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_2_n_7\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_3_n_12\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_3_n_13\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_3_n_14\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_3_n_15\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_3_n_5\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_3_n_6\ : STD_LOGIC;
  signal \xsqr_reg[17]_i_3_n_7\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_2_n_0\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_2_n_1\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_2_n_10\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_2_n_11\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_2_n_12\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_2_n_13\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_2_n_2\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_2_n_3\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_2_n_4\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_2_n_5\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_2_n_6\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_2_n_7\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_2_n_8\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_2_n_9\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_0\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_1\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_10\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_11\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_12\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_13\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_14\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_15\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_2\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_3\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_4\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_5\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_6\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_7\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_8\ : STD_LOGIC;
  signal \xsqr_reg[21]_i_3_n_9\ : STD_LOGIC;
  signal \xsqr_reg[29]_i_2_n_0\ : STD_LOGIC;
  signal \xsqr_reg[29]_i_2_n_1\ : STD_LOGIC;
  signal \xsqr_reg[29]_i_2_n_2\ : STD_LOGIC;
  signal \xsqr_reg[29]_i_2_n_3\ : STD_LOGIC;
  signal \xsqr_reg[29]_i_2_n_4\ : STD_LOGIC;
  signal \xsqr_reg[29]_i_2_n_5\ : STD_LOGIC;
  signal \xsqr_reg[29]_i_2_n_6\ : STD_LOGIC;
  signal \xsqr_reg[29]_i_2_n_7\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_1\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_10\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_11\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_12\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_13\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_14\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_15\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_2\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_3\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_4\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_5\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_6\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_7\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_8\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_13_n_9\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_17_n_13\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_17_n_14\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_17_n_15\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_17_n_4\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_17_n_6\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_17_n_7\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_18_n_14\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_18_n_15\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_18_n_5\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_18_n_7\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_2_n_3\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_2_n_4\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_2_n_5\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_2_n_6\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_2_n_7\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_3_n_12\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_3_n_13\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_3_n_14\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_3_n_15\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_3_n_5\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_3_n_6\ : STD_LOGIC;
  signal \xsqr_reg[35]_i_3_n_7\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_2_n_0\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_2_n_1\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_2_n_10\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_2_n_11\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_2_n_12\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_2_n_13\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_2_n_2\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_2_n_3\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_2_n_4\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_2_n_5\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_2_n_6\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_2_n_7\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_2_n_8\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_2_n_9\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_0\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_1\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_10\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_11\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_12\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_13\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_14\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_15\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_2\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_3\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_4\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_5\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_6\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_7\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_8\ : STD_LOGIC;
  signal \xsqr_reg[39]_i_3_n_9\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_2_n_1\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_2_n_10\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_2_n_11\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_2_n_12\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_2_n_13\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_2_n_2\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_2_n_3\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_2_n_4\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_2_n_5\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_2_n_6\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_2_n_7\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_2_n_8\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_2_n_9\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_0\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_1\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_10\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_11\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_12\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_13\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_14\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_15\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_2\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_3\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_4\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_5\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_6\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_7\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_8\ : STD_LOGIC;
  signal \xsqr_reg[3]_i_3_n_9\ : STD_LOGIC;
  signal \xsqr_reg[47]_i_2_n_0\ : STD_LOGIC;
  signal \xsqr_reg[47]_i_2_n_1\ : STD_LOGIC;
  signal \xsqr_reg[47]_i_2_n_2\ : STD_LOGIC;
  signal \xsqr_reg[47]_i_2_n_3\ : STD_LOGIC;
  signal \xsqr_reg[47]_i_2_n_4\ : STD_LOGIC;
  signal \xsqr_reg[47]_i_2_n_5\ : STD_LOGIC;
  signal \xsqr_reg[47]_i_2_n_6\ : STD_LOGIC;
  signal \xsqr_reg[47]_i_2_n_7\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_1\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_10\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_11\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_12\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_13\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_14\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_15\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_2\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_3\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_4\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_5\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_6\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_7\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_8\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_13_n_9\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_17_n_13\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_17_n_14\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_17_n_15\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_17_n_4\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_17_n_6\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_17_n_7\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_18_n_14\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_18_n_15\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_18_n_5\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_18_n_7\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_2_n_3\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_2_n_4\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_2_n_5\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_2_n_6\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_2_n_7\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_3_n_12\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_3_n_13\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_3_n_14\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_3_n_15\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_3_n_5\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_3_n_6\ : STD_LOGIC;
  signal \xsqr_reg[53]_i_3_n_7\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_2_n_0\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_2_n_1\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_2_n_10\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_2_n_11\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_2_n_12\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_2_n_13\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_2_n_2\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_2_n_3\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_2_n_4\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_2_n_5\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_2_n_6\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_2_n_7\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_2_n_8\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_2_n_9\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_0\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_1\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_10\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_11\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_12\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_13\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_14\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_15\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_2\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_3\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_4\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_5\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_6\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_7\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_8\ : STD_LOGIC;
  signal \xsqr_reg[57]_i_3_n_9\ : STD_LOGIC;
  signal \xsqr_reg[65]_i_2_n_0\ : STD_LOGIC;
  signal \xsqr_reg[65]_i_2_n_1\ : STD_LOGIC;
  signal \xsqr_reg[65]_i_2_n_2\ : STD_LOGIC;
  signal \xsqr_reg[65]_i_2_n_3\ : STD_LOGIC;
  signal \xsqr_reg[65]_i_2_n_4\ : STD_LOGIC;
  signal \xsqr_reg[65]_i_2_n_5\ : STD_LOGIC;
  signal \xsqr_reg[65]_i_2_n_6\ : STD_LOGIC;
  signal \xsqr_reg[65]_i_2_n_7\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_0\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_1\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_10\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_11\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_12\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_13\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_14\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_15\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_2\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_3\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_4\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_5\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_6\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_7\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_8\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_13_n_9\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_17_n_13\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_17_n_14\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_17_n_15\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_17_n_4\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_17_n_6\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_17_n_7\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_18_n_14\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_18_n_15\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_18_n_5\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_18_n_7\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_2_n_3\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_2_n_4\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_2_n_5\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_2_n_6\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_2_n_7\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_3_n_12\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_3_n_13\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_3_n_14\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_3_n_15\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_3_n_5\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_3_n_6\ : STD_LOGIC;
  signal \xsqr_reg[71]_i_3_n_7\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_2_n_0\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_2_n_1\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_2_n_10\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_2_n_11\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_2_n_12\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_2_n_13\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_2_n_2\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_2_n_3\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_2_n_4\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_2_n_5\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_2_n_6\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_2_n_7\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_2_n_8\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_2_n_9\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_0\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_1\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_10\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_11\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_12\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_13\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_14\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_15\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_2\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_3\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_4\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_5\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_6\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_7\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_8\ : STD_LOGIC;
  signal \xsqr_reg[75]_i_3_n_9\ : STD_LOGIC;
  signal \xsqr_reg[83]_i_2_n_0\ : STD_LOGIC;
  signal \xsqr_reg[83]_i_2_n_1\ : STD_LOGIC;
  signal \xsqr_reg[83]_i_2_n_2\ : STD_LOGIC;
  signal \xsqr_reg[83]_i_2_n_3\ : STD_LOGIC;
  signal \xsqr_reg[83]_i_2_n_4\ : STD_LOGIC;
  signal \xsqr_reg[83]_i_2_n_5\ : STD_LOGIC;
  signal \xsqr_reg[83]_i_2_n_6\ : STD_LOGIC;
  signal \xsqr_reg[83]_i_2_n_7\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_0\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_1\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_10\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_11\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_12\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_13\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_14\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_15\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_2\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_3\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_4\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_5\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_6\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_7\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_8\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_14_n_9\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_18_n_13\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_18_n_14\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_18_n_15\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_18_n_4\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_18_n_6\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_18_n_7\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_19_n_14\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_19_n_15\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_19_n_5\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_19_n_7\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_3_n_3\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_3_n_4\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_3_n_5\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_3_n_6\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_3_n_7\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_4_n_12\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_4_n_13\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_4_n_14\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_4_n_15\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_4_n_5\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_4_n_6\ : STD_LOGIC;
  signal \xsqr_reg[89]_i_4_n_7\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[0]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[10]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[11]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[12]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[13]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[14]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[15]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[16]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[17]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[2]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[3]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[4]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[54]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[56]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[57]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[58]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[59]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[5]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[60]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[61]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[62]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[63]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[64]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[65]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[66]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[67]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[68]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[69]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[6]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[70]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[71]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[72]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[74]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[75]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[76]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[77]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[78]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[79]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[7]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[80]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[81]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[82]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[83]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[84]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[85]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[86]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[87]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[88]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[89]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[8]\ : STD_LOGIC;
  signal \xsqr_reg_n_0_[9]\ : STD_LOGIC;
  signal xy : STD_LOGIC_VECTOR ( 89 downto 0 );
  signal xy0 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal xy00_in : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal xy01_in : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal xy02_in : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal xy03_in : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal xy4p1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \xy4p1[0]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[10]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[11]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[12]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[13]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[14]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[15]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[16]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[17]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[1]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[2]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[3]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[4]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[5]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[6]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[7]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[8]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p1[9]_i_1_n_0\ : STD_LOGIC;
  signal xy4p2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \xy4p2[0]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[10]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[11]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[12]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[13]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[14]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[15]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[16]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[17]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[1]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[2]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[3]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[4]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[5]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[6]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[7]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[8]_i_1_n_0\ : STD_LOGIC;
  signal \xy4p2[9]_i_1_n_0\ : STD_LOGIC;
  signal \xy[0]_i_1_n_0\ : STD_LOGIC;
  signal \xy[10]_i_1_n_0\ : STD_LOGIC;
  signal \xy[11]_i_10_n_0\ : STD_LOGIC;
  signal \xy[11]_i_11_n_0\ : STD_LOGIC;
  signal \xy[11]_i_12_n_0\ : STD_LOGIC;
  signal \xy[11]_i_13_n_0\ : STD_LOGIC;
  signal \xy[11]_i_14_n_0\ : STD_LOGIC;
  signal \xy[11]_i_15_n_0\ : STD_LOGIC;
  signal \xy[11]_i_16_n_0\ : STD_LOGIC;
  signal \xy[11]_i_17_n_0\ : STD_LOGIC;
  signal \xy[11]_i_18_n_0\ : STD_LOGIC;
  signal \xy[11]_i_19_n_0\ : STD_LOGIC;
  signal \xy[11]_i_1_n_0\ : STD_LOGIC;
  signal \xy[11]_i_3_n_0\ : STD_LOGIC;
  signal \xy[11]_i_4_n_0\ : STD_LOGIC;
  signal \xy[11]_i_5_n_0\ : STD_LOGIC;
  signal \xy[11]_i_6_n_0\ : STD_LOGIC;
  signal \xy[11]_i_7_n_0\ : STD_LOGIC;
  signal \xy[11]_i_8_n_0\ : STD_LOGIC;
  signal \xy[11]_i_9_n_0\ : STD_LOGIC;
  signal \xy[12]_i_1_n_0\ : STD_LOGIC;
  signal \xy[13]_i_1_n_0\ : STD_LOGIC;
  signal \xy[14]_i_1_n_0\ : STD_LOGIC;
  signal \xy[15]_i_1_n_0\ : STD_LOGIC;
  signal \xy[16]_i_1_n_0\ : STD_LOGIC;
  signal \xy[17]_i_10_n_0\ : STD_LOGIC;
  signal \xy[17]_i_11_n_0\ : STD_LOGIC;
  signal \xy[17]_i_12_n_0\ : STD_LOGIC;
  signal \xy[17]_i_14_n_0\ : STD_LOGIC;
  signal \xy[17]_i_15_n_0\ : STD_LOGIC;
  signal \xy[17]_i_16_n_0\ : STD_LOGIC;
  signal \xy[17]_i_17_n_0\ : STD_LOGIC;
  signal \xy[17]_i_18_n_0\ : STD_LOGIC;
  signal \xy[17]_i_19_n_0\ : STD_LOGIC;
  signal \xy[17]_i_1_n_0\ : STD_LOGIC;
  signal \xy[17]_i_22_n_0\ : STD_LOGIC;
  signal \xy[17]_i_23_n_0\ : STD_LOGIC;
  signal \xy[17]_i_24_n_0\ : STD_LOGIC;
  signal \xy[17]_i_25_n_0\ : STD_LOGIC;
  signal \xy[17]_i_26_n_0\ : STD_LOGIC;
  signal \xy[17]_i_27_n_0\ : STD_LOGIC;
  signal \xy[17]_i_28_n_0\ : STD_LOGIC;
  signal \xy[17]_i_29_n_0\ : STD_LOGIC;
  signal \xy[17]_i_30_n_0\ : STD_LOGIC;
  signal \xy[17]_i_31_n_0\ : STD_LOGIC;
  signal \xy[17]_i_32_n_0\ : STD_LOGIC;
  signal \xy[17]_i_33_n_0\ : STD_LOGIC;
  signal \xy[17]_i_34_n_0\ : STD_LOGIC;
  signal \xy[17]_i_35_n_0\ : STD_LOGIC;
  signal \xy[17]_i_36_n_0\ : STD_LOGIC;
  signal \xy[17]_i_37_n_0\ : STD_LOGIC;
  signal \xy[17]_i_38_n_0\ : STD_LOGIC;
  signal \xy[17]_i_39_n_0\ : STD_LOGIC;
  signal \xy[17]_i_40_n_0\ : STD_LOGIC;
  signal \xy[17]_i_41_n_0\ : STD_LOGIC;
  signal \xy[17]_i_42_n_0\ : STD_LOGIC;
  signal \xy[17]_i_43_n_0\ : STD_LOGIC;
  signal \xy[17]_i_44_n_0\ : STD_LOGIC;
  signal \xy[17]_i_45_n_0\ : STD_LOGIC;
  signal \xy[17]_i_46_n_0\ : STD_LOGIC;
  signal \xy[17]_i_47_n_0\ : STD_LOGIC;
  signal \xy[17]_i_48_n_0\ : STD_LOGIC;
  signal \xy[17]_i_49_n_0\ : STD_LOGIC;
  signal \xy[17]_i_4_n_0\ : STD_LOGIC;
  signal \xy[17]_i_50_n_0\ : STD_LOGIC;
  signal \xy[17]_i_51_n_0\ : STD_LOGIC;
  signal \xy[17]_i_52_n_0\ : STD_LOGIC;
  signal \xy[17]_i_53_n_0\ : STD_LOGIC;
  signal \xy[17]_i_54_n_0\ : STD_LOGIC;
  signal \xy[17]_i_55_n_0\ : STD_LOGIC;
  signal \xy[17]_i_5_n_0\ : STD_LOGIC;
  signal \xy[17]_i_6_n_0\ : STD_LOGIC;
  signal \xy[17]_i_7_n_0\ : STD_LOGIC;
  signal \xy[17]_i_8_n_0\ : STD_LOGIC;
  signal \xy[17]_i_9_n_0\ : STD_LOGIC;
  signal \xy[18]_i_1_n_0\ : STD_LOGIC;
  signal \xy[19]_i_1_n_0\ : STD_LOGIC;
  signal \xy[1]_i_1_n_0\ : STD_LOGIC;
  signal \xy[20]_i_1_n_0\ : STD_LOGIC;
  signal \xy[21]_i_10_n_0\ : STD_LOGIC;
  signal \xy[21]_i_11_n_0\ : STD_LOGIC;
  signal \xy[21]_i_12_n_0\ : STD_LOGIC;
  signal \xy[21]_i_13_n_0\ : STD_LOGIC;
  signal \xy[21]_i_14_n_0\ : STD_LOGIC;
  signal \xy[21]_i_15_n_0\ : STD_LOGIC;
  signal \xy[21]_i_16_n_0\ : STD_LOGIC;
  signal \xy[21]_i_17_n_0\ : STD_LOGIC;
  signal \xy[21]_i_18_n_0\ : STD_LOGIC;
  signal \xy[21]_i_19_n_0\ : STD_LOGIC;
  signal \xy[21]_i_1_n_0\ : STD_LOGIC;
  signal \xy[21]_i_20_n_0\ : STD_LOGIC;
  signal \xy[21]_i_21_n_0\ : STD_LOGIC;
  signal \xy[21]_i_22_n_0\ : STD_LOGIC;
  signal \xy[21]_i_23_n_0\ : STD_LOGIC;
  signal \xy[21]_i_24_n_0\ : STD_LOGIC;
  signal \xy[21]_i_25_n_0\ : STD_LOGIC;
  signal \xy[21]_i_26_n_0\ : STD_LOGIC;
  signal \xy[21]_i_27_n_0\ : STD_LOGIC;
  signal \xy[21]_i_28_n_0\ : STD_LOGIC;
  signal \xy[21]_i_29_n_0\ : STD_LOGIC;
  signal \xy[21]_i_30_n_0\ : STD_LOGIC;
  signal \xy[21]_i_31_n_0\ : STD_LOGIC;
  signal \xy[21]_i_32_n_0\ : STD_LOGIC;
  signal \xy[21]_i_33_n_0\ : STD_LOGIC;
  signal \xy[21]_i_34_n_0\ : STD_LOGIC;
  signal \xy[21]_i_35_n_0\ : STD_LOGIC;
  signal \xy[21]_i_36_n_0\ : STD_LOGIC;
  signal \xy[21]_i_37_n_0\ : STD_LOGIC;
  signal \xy[21]_i_38_n_0\ : STD_LOGIC;
  signal \xy[21]_i_39_n_0\ : STD_LOGIC;
  signal \xy[21]_i_40_n_0\ : STD_LOGIC;
  signal \xy[21]_i_41_n_0\ : STD_LOGIC;
  signal \xy[21]_i_4_n_0\ : STD_LOGIC;
  signal \xy[21]_i_5_n_0\ : STD_LOGIC;
  signal \xy[21]_i_6_n_0\ : STD_LOGIC;
  signal \xy[21]_i_7_n_0\ : STD_LOGIC;
  signal \xy[21]_i_8_n_0\ : STD_LOGIC;
  signal \xy[21]_i_9_n_0\ : STD_LOGIC;
  signal \xy[22]_i_1_n_0\ : STD_LOGIC;
  signal \xy[23]_i_1_n_0\ : STD_LOGIC;
  signal \xy[24]_i_1_n_0\ : STD_LOGIC;
  signal \xy[25]_i_1_n_0\ : STD_LOGIC;
  signal \xy[26]_i_1_n_0\ : STD_LOGIC;
  signal \xy[27]_i_1_n_0\ : STD_LOGIC;
  signal \xy[28]_i_1_n_0\ : STD_LOGIC;
  signal \xy[29]_i_10_n_0\ : STD_LOGIC;
  signal \xy[29]_i_11_n_0\ : STD_LOGIC;
  signal \xy[29]_i_12_n_0\ : STD_LOGIC;
  signal \xy[29]_i_13_n_0\ : STD_LOGIC;
  signal \xy[29]_i_14_n_0\ : STD_LOGIC;
  signal \xy[29]_i_15_n_0\ : STD_LOGIC;
  signal \xy[29]_i_16_n_0\ : STD_LOGIC;
  signal \xy[29]_i_17_n_0\ : STD_LOGIC;
  signal \xy[29]_i_18_n_0\ : STD_LOGIC;
  signal \xy[29]_i_19_n_0\ : STD_LOGIC;
  signal \xy[29]_i_1_n_0\ : STD_LOGIC;
  signal \xy[29]_i_3_n_0\ : STD_LOGIC;
  signal \xy[29]_i_4_n_0\ : STD_LOGIC;
  signal \xy[29]_i_5_n_0\ : STD_LOGIC;
  signal \xy[29]_i_6_n_0\ : STD_LOGIC;
  signal \xy[29]_i_7_n_0\ : STD_LOGIC;
  signal \xy[29]_i_8_n_0\ : STD_LOGIC;
  signal \xy[29]_i_9_n_0\ : STD_LOGIC;
  signal \xy[2]_i_1_n_0\ : STD_LOGIC;
  signal \xy[30]_i_1_n_0\ : STD_LOGIC;
  signal \xy[31]_i_1_n_0\ : STD_LOGIC;
  signal \xy[32]_i_1_n_0\ : STD_LOGIC;
  signal \xy[33]_i_1_n_0\ : STD_LOGIC;
  signal \xy[34]_i_1_n_0\ : STD_LOGIC;
  signal \xy[35]_i_10_n_0\ : STD_LOGIC;
  signal \xy[35]_i_11_n_0\ : STD_LOGIC;
  signal \xy[35]_i_12_n_0\ : STD_LOGIC;
  signal \xy[35]_i_14_n_0\ : STD_LOGIC;
  signal \xy[35]_i_15_n_0\ : STD_LOGIC;
  signal \xy[35]_i_16_n_0\ : STD_LOGIC;
  signal \xy[35]_i_17_n_0\ : STD_LOGIC;
  signal \xy[35]_i_18_n_0\ : STD_LOGIC;
  signal \xy[35]_i_19_n_0\ : STD_LOGIC;
  signal \xy[35]_i_1_n_0\ : STD_LOGIC;
  signal \xy[35]_i_22_n_0\ : STD_LOGIC;
  signal \xy[35]_i_23_n_0\ : STD_LOGIC;
  signal \xy[35]_i_24_n_0\ : STD_LOGIC;
  signal \xy[35]_i_25_n_0\ : STD_LOGIC;
  signal \xy[35]_i_26_n_0\ : STD_LOGIC;
  signal \xy[35]_i_27_n_0\ : STD_LOGIC;
  signal \xy[35]_i_28_n_0\ : STD_LOGIC;
  signal \xy[35]_i_29_n_0\ : STD_LOGIC;
  signal \xy[35]_i_30_n_0\ : STD_LOGIC;
  signal \xy[35]_i_31_n_0\ : STD_LOGIC;
  signal \xy[35]_i_32_n_0\ : STD_LOGIC;
  signal \xy[35]_i_33_n_0\ : STD_LOGIC;
  signal \xy[35]_i_34_n_0\ : STD_LOGIC;
  signal \xy[35]_i_35_n_0\ : STD_LOGIC;
  signal \xy[35]_i_36_n_0\ : STD_LOGIC;
  signal \xy[35]_i_37_n_0\ : STD_LOGIC;
  signal \xy[35]_i_38_n_0\ : STD_LOGIC;
  signal \xy[35]_i_39_n_0\ : STD_LOGIC;
  signal \xy[35]_i_40_n_0\ : STD_LOGIC;
  signal \xy[35]_i_41_n_0\ : STD_LOGIC;
  signal \xy[35]_i_42_n_0\ : STD_LOGIC;
  signal \xy[35]_i_43_n_0\ : STD_LOGIC;
  signal \xy[35]_i_44_n_0\ : STD_LOGIC;
  signal \xy[35]_i_45_n_0\ : STD_LOGIC;
  signal \xy[35]_i_46_n_0\ : STD_LOGIC;
  signal \xy[35]_i_47_n_0\ : STD_LOGIC;
  signal \xy[35]_i_48_n_0\ : STD_LOGIC;
  signal \xy[35]_i_49_n_0\ : STD_LOGIC;
  signal \xy[35]_i_4_n_0\ : STD_LOGIC;
  signal \xy[35]_i_50_n_0\ : STD_LOGIC;
  signal \xy[35]_i_51_n_0\ : STD_LOGIC;
  signal \xy[35]_i_52_n_0\ : STD_LOGIC;
  signal \xy[35]_i_53_n_0\ : STD_LOGIC;
  signal \xy[35]_i_54_n_0\ : STD_LOGIC;
  signal \xy[35]_i_55_n_0\ : STD_LOGIC;
  signal \xy[35]_i_5_n_0\ : STD_LOGIC;
  signal \xy[35]_i_6_n_0\ : STD_LOGIC;
  signal \xy[35]_i_7_n_0\ : STD_LOGIC;
  signal \xy[35]_i_8_n_0\ : STD_LOGIC;
  signal \xy[35]_i_9_n_0\ : STD_LOGIC;
  signal \xy[36]_i_1_n_0\ : STD_LOGIC;
  signal \xy[37]_i_1_n_0\ : STD_LOGIC;
  signal \xy[38]_i_1_n_0\ : STD_LOGIC;
  signal \xy[39]_i_10_n_0\ : STD_LOGIC;
  signal \xy[39]_i_11_n_0\ : STD_LOGIC;
  signal \xy[39]_i_12_n_0\ : STD_LOGIC;
  signal \xy[39]_i_13_n_0\ : STD_LOGIC;
  signal \xy[39]_i_14_n_0\ : STD_LOGIC;
  signal \xy[39]_i_15_n_0\ : STD_LOGIC;
  signal \xy[39]_i_16_n_0\ : STD_LOGIC;
  signal \xy[39]_i_17_n_0\ : STD_LOGIC;
  signal \xy[39]_i_18_n_0\ : STD_LOGIC;
  signal \xy[39]_i_19_n_0\ : STD_LOGIC;
  signal \xy[39]_i_1_n_0\ : STD_LOGIC;
  signal \xy[39]_i_20_n_0\ : STD_LOGIC;
  signal \xy[39]_i_21_n_0\ : STD_LOGIC;
  signal \xy[39]_i_22_n_0\ : STD_LOGIC;
  signal \xy[39]_i_23_n_0\ : STD_LOGIC;
  signal \xy[39]_i_24_n_0\ : STD_LOGIC;
  signal \xy[39]_i_25_n_0\ : STD_LOGIC;
  signal \xy[39]_i_26_n_0\ : STD_LOGIC;
  signal \xy[39]_i_27_n_0\ : STD_LOGIC;
  signal \xy[39]_i_28_n_0\ : STD_LOGIC;
  signal \xy[39]_i_29_n_0\ : STD_LOGIC;
  signal \xy[39]_i_30_n_0\ : STD_LOGIC;
  signal \xy[39]_i_31_n_0\ : STD_LOGIC;
  signal \xy[39]_i_32_n_0\ : STD_LOGIC;
  signal \xy[39]_i_33_n_0\ : STD_LOGIC;
  signal \xy[39]_i_34_n_0\ : STD_LOGIC;
  signal \xy[39]_i_35_n_0\ : STD_LOGIC;
  signal \xy[39]_i_36_n_0\ : STD_LOGIC;
  signal \xy[39]_i_37_n_0\ : STD_LOGIC;
  signal \xy[39]_i_38_n_0\ : STD_LOGIC;
  signal \xy[39]_i_39_n_0\ : STD_LOGIC;
  signal \xy[39]_i_40_n_0\ : STD_LOGIC;
  signal \xy[39]_i_41_n_0\ : STD_LOGIC;
  signal \xy[39]_i_4_n_0\ : STD_LOGIC;
  signal \xy[39]_i_5_n_0\ : STD_LOGIC;
  signal \xy[39]_i_6_n_0\ : STD_LOGIC;
  signal \xy[39]_i_7_n_0\ : STD_LOGIC;
  signal \xy[39]_i_8_n_0\ : STD_LOGIC;
  signal \xy[39]_i_9_n_0\ : STD_LOGIC;
  signal \xy[3]_i_10_n_0\ : STD_LOGIC;
  signal \xy[3]_i_11_n_0\ : STD_LOGIC;
  signal \xy[3]_i_12_n_0\ : STD_LOGIC;
  signal \xy[3]_i_13_n_0\ : STD_LOGIC;
  signal \xy[3]_i_14_n_0\ : STD_LOGIC;
  signal \xy[3]_i_15_n_0\ : STD_LOGIC;
  signal \xy[3]_i_16_n_0\ : STD_LOGIC;
  signal \xy[3]_i_17_n_0\ : STD_LOGIC;
  signal \xy[3]_i_18_n_0\ : STD_LOGIC;
  signal \xy[3]_i_19_n_0\ : STD_LOGIC;
  signal \xy[3]_i_1_n_0\ : STD_LOGIC;
  signal \xy[3]_i_20_n_0\ : STD_LOGIC;
  signal \xy[3]_i_21_n_0\ : STD_LOGIC;
  signal \xy[3]_i_22_n_0\ : STD_LOGIC;
  signal \xy[3]_i_23_n_0\ : STD_LOGIC;
  signal \xy[3]_i_24_n_0\ : STD_LOGIC;
  signal \xy[3]_i_25_n_0\ : STD_LOGIC;
  signal \xy[3]_i_26_n_0\ : STD_LOGIC;
  signal \xy[3]_i_27_n_0\ : STD_LOGIC;
  signal \xy[3]_i_28_n_0\ : STD_LOGIC;
  signal \xy[3]_i_29_n_0\ : STD_LOGIC;
  signal \xy[3]_i_30_n_0\ : STD_LOGIC;
  signal \xy[3]_i_31_n_0\ : STD_LOGIC;
  signal \xy[3]_i_32_n_0\ : STD_LOGIC;
  signal \xy[3]_i_33_n_0\ : STD_LOGIC;
  signal \xy[3]_i_34_n_0\ : STD_LOGIC;
  signal \xy[3]_i_35_n_0\ : STD_LOGIC;
  signal \xy[3]_i_36_n_0\ : STD_LOGIC;
  signal \xy[3]_i_37_n_0\ : STD_LOGIC;
  signal \xy[3]_i_38_n_0\ : STD_LOGIC;
  signal \xy[3]_i_39_n_0\ : STD_LOGIC;
  signal \xy[3]_i_40_n_0\ : STD_LOGIC;
  signal \xy[3]_i_41_n_0\ : STD_LOGIC;
  signal \xy[3]_i_4_n_0\ : STD_LOGIC;
  signal \xy[3]_i_5_n_0\ : STD_LOGIC;
  signal \xy[3]_i_6_n_0\ : STD_LOGIC;
  signal \xy[3]_i_7_n_0\ : STD_LOGIC;
  signal \xy[3]_i_8_n_0\ : STD_LOGIC;
  signal \xy[3]_i_9_n_0\ : STD_LOGIC;
  signal \xy[40]_i_1_n_0\ : STD_LOGIC;
  signal \xy[41]_i_1_n_0\ : STD_LOGIC;
  signal \xy[42]_i_1_n_0\ : STD_LOGIC;
  signal \xy[43]_i_1_n_0\ : STD_LOGIC;
  signal \xy[44]_i_1_n_0\ : STD_LOGIC;
  signal \xy[45]_i_1_n_0\ : STD_LOGIC;
  signal \xy[46]_i_1_n_0\ : STD_LOGIC;
  signal \xy[47]_i_10_n_0\ : STD_LOGIC;
  signal \xy[47]_i_11_n_0\ : STD_LOGIC;
  signal \xy[47]_i_12_n_0\ : STD_LOGIC;
  signal \xy[47]_i_13_n_0\ : STD_LOGIC;
  signal \xy[47]_i_14_n_0\ : STD_LOGIC;
  signal \xy[47]_i_15_n_0\ : STD_LOGIC;
  signal \xy[47]_i_16_n_0\ : STD_LOGIC;
  signal \xy[47]_i_17_n_0\ : STD_LOGIC;
  signal \xy[47]_i_18_n_0\ : STD_LOGIC;
  signal \xy[47]_i_19_n_0\ : STD_LOGIC;
  signal \xy[47]_i_1_n_0\ : STD_LOGIC;
  signal \xy[47]_i_3_n_0\ : STD_LOGIC;
  signal \xy[47]_i_4_n_0\ : STD_LOGIC;
  signal \xy[47]_i_5_n_0\ : STD_LOGIC;
  signal \xy[47]_i_6_n_0\ : STD_LOGIC;
  signal \xy[47]_i_7_n_0\ : STD_LOGIC;
  signal \xy[47]_i_8_n_0\ : STD_LOGIC;
  signal \xy[47]_i_9_n_0\ : STD_LOGIC;
  signal \xy[48]_i_1_n_0\ : STD_LOGIC;
  signal \xy[49]_i_1_n_0\ : STD_LOGIC;
  signal \xy[4]_i_1_n_0\ : STD_LOGIC;
  signal \xy[50]_i_1_n_0\ : STD_LOGIC;
  signal \xy[51]_i_1_n_0\ : STD_LOGIC;
  signal \xy[52]_i_1_n_0\ : STD_LOGIC;
  signal \xy[53]_i_10_n_0\ : STD_LOGIC;
  signal \xy[53]_i_11_n_0\ : STD_LOGIC;
  signal \xy[53]_i_12_n_0\ : STD_LOGIC;
  signal \xy[53]_i_14_n_0\ : STD_LOGIC;
  signal \xy[53]_i_15_n_0\ : STD_LOGIC;
  signal \xy[53]_i_16_n_0\ : STD_LOGIC;
  signal \xy[53]_i_17_n_0\ : STD_LOGIC;
  signal \xy[53]_i_18_n_0\ : STD_LOGIC;
  signal \xy[53]_i_19_n_0\ : STD_LOGIC;
  signal \xy[53]_i_1_n_0\ : STD_LOGIC;
  signal \xy[53]_i_22_n_0\ : STD_LOGIC;
  signal \xy[53]_i_23_n_0\ : STD_LOGIC;
  signal \xy[53]_i_24_n_0\ : STD_LOGIC;
  signal \xy[53]_i_25_n_0\ : STD_LOGIC;
  signal \xy[53]_i_26_n_0\ : STD_LOGIC;
  signal \xy[53]_i_27_n_0\ : STD_LOGIC;
  signal \xy[53]_i_28_n_0\ : STD_LOGIC;
  signal \xy[53]_i_29_n_0\ : STD_LOGIC;
  signal \xy[53]_i_30_n_0\ : STD_LOGIC;
  signal \xy[53]_i_31_n_0\ : STD_LOGIC;
  signal \xy[53]_i_32_n_0\ : STD_LOGIC;
  signal \xy[53]_i_33_n_0\ : STD_LOGIC;
  signal \xy[53]_i_34_n_0\ : STD_LOGIC;
  signal \xy[53]_i_35_n_0\ : STD_LOGIC;
  signal \xy[53]_i_36_n_0\ : STD_LOGIC;
  signal \xy[53]_i_37_n_0\ : STD_LOGIC;
  signal \xy[53]_i_38_n_0\ : STD_LOGIC;
  signal \xy[53]_i_39_n_0\ : STD_LOGIC;
  signal \xy[53]_i_40_n_0\ : STD_LOGIC;
  signal \xy[53]_i_41_n_0\ : STD_LOGIC;
  signal \xy[53]_i_42_n_0\ : STD_LOGIC;
  signal \xy[53]_i_43_n_0\ : STD_LOGIC;
  signal \xy[53]_i_44_n_0\ : STD_LOGIC;
  signal \xy[53]_i_45_n_0\ : STD_LOGIC;
  signal \xy[53]_i_46_n_0\ : STD_LOGIC;
  signal \xy[53]_i_47_n_0\ : STD_LOGIC;
  signal \xy[53]_i_48_n_0\ : STD_LOGIC;
  signal \xy[53]_i_49_n_0\ : STD_LOGIC;
  signal \xy[53]_i_4_n_0\ : STD_LOGIC;
  signal \xy[53]_i_50_n_0\ : STD_LOGIC;
  signal \xy[53]_i_51_n_0\ : STD_LOGIC;
  signal \xy[53]_i_52_n_0\ : STD_LOGIC;
  signal \xy[53]_i_53_n_0\ : STD_LOGIC;
  signal \xy[53]_i_54_n_0\ : STD_LOGIC;
  signal \xy[53]_i_55_n_0\ : STD_LOGIC;
  signal \xy[53]_i_5_n_0\ : STD_LOGIC;
  signal \xy[53]_i_6_n_0\ : STD_LOGIC;
  signal \xy[53]_i_7_n_0\ : STD_LOGIC;
  signal \xy[53]_i_8_n_0\ : STD_LOGIC;
  signal \xy[53]_i_9_n_0\ : STD_LOGIC;
  signal \xy[54]_i_1_n_0\ : STD_LOGIC;
  signal \xy[55]_i_1_n_0\ : STD_LOGIC;
  signal \xy[56]_i_1_n_0\ : STD_LOGIC;
  signal \xy[57]_i_10_n_0\ : STD_LOGIC;
  signal \xy[57]_i_11_n_0\ : STD_LOGIC;
  signal \xy[57]_i_12_n_0\ : STD_LOGIC;
  signal \xy[57]_i_13_n_0\ : STD_LOGIC;
  signal \xy[57]_i_14_n_0\ : STD_LOGIC;
  signal \xy[57]_i_15_n_0\ : STD_LOGIC;
  signal \xy[57]_i_16_n_0\ : STD_LOGIC;
  signal \xy[57]_i_17_n_0\ : STD_LOGIC;
  signal \xy[57]_i_18_n_0\ : STD_LOGIC;
  signal \xy[57]_i_19_n_0\ : STD_LOGIC;
  signal \xy[57]_i_1_n_0\ : STD_LOGIC;
  signal \xy[57]_i_20_n_0\ : STD_LOGIC;
  signal \xy[57]_i_21_n_0\ : STD_LOGIC;
  signal \xy[57]_i_22_n_0\ : STD_LOGIC;
  signal \xy[57]_i_23_n_0\ : STD_LOGIC;
  signal \xy[57]_i_24_n_0\ : STD_LOGIC;
  signal \xy[57]_i_25_n_0\ : STD_LOGIC;
  signal \xy[57]_i_26_n_0\ : STD_LOGIC;
  signal \xy[57]_i_27_n_0\ : STD_LOGIC;
  signal \xy[57]_i_28_n_0\ : STD_LOGIC;
  signal \xy[57]_i_29_n_0\ : STD_LOGIC;
  signal \xy[57]_i_30_n_0\ : STD_LOGIC;
  signal \xy[57]_i_31_n_0\ : STD_LOGIC;
  signal \xy[57]_i_32_n_0\ : STD_LOGIC;
  signal \xy[57]_i_33_n_0\ : STD_LOGIC;
  signal \xy[57]_i_34_n_0\ : STD_LOGIC;
  signal \xy[57]_i_35_n_0\ : STD_LOGIC;
  signal \xy[57]_i_36_n_0\ : STD_LOGIC;
  signal \xy[57]_i_37_n_0\ : STD_LOGIC;
  signal \xy[57]_i_38_n_0\ : STD_LOGIC;
  signal \xy[57]_i_39_n_0\ : STD_LOGIC;
  signal \xy[57]_i_40_n_0\ : STD_LOGIC;
  signal \xy[57]_i_41_n_0\ : STD_LOGIC;
  signal \xy[57]_i_4_n_0\ : STD_LOGIC;
  signal \xy[57]_i_5_n_0\ : STD_LOGIC;
  signal \xy[57]_i_6_n_0\ : STD_LOGIC;
  signal \xy[57]_i_7_n_0\ : STD_LOGIC;
  signal \xy[57]_i_8_n_0\ : STD_LOGIC;
  signal \xy[57]_i_9_n_0\ : STD_LOGIC;
  signal \xy[58]_i_1_n_0\ : STD_LOGIC;
  signal \xy[59]_i_1_n_0\ : STD_LOGIC;
  signal \xy[5]_i_1_n_0\ : STD_LOGIC;
  signal \xy[60]_i_1_n_0\ : STD_LOGIC;
  signal \xy[61]_i_1_n_0\ : STD_LOGIC;
  signal \xy[62]_i_1_n_0\ : STD_LOGIC;
  signal \xy[63]_i_1_n_0\ : STD_LOGIC;
  signal \xy[64]_i_1_n_0\ : STD_LOGIC;
  signal \xy[65]_i_10_n_0\ : STD_LOGIC;
  signal \xy[65]_i_11_n_0\ : STD_LOGIC;
  signal \xy[65]_i_12_n_0\ : STD_LOGIC;
  signal \xy[65]_i_13_n_0\ : STD_LOGIC;
  signal \xy[65]_i_14_n_0\ : STD_LOGIC;
  signal \xy[65]_i_15_n_0\ : STD_LOGIC;
  signal \xy[65]_i_16_n_0\ : STD_LOGIC;
  signal \xy[65]_i_17_n_0\ : STD_LOGIC;
  signal \xy[65]_i_18_n_0\ : STD_LOGIC;
  signal \xy[65]_i_19_n_0\ : STD_LOGIC;
  signal \xy[65]_i_1_n_0\ : STD_LOGIC;
  signal \xy[65]_i_3_n_0\ : STD_LOGIC;
  signal \xy[65]_i_4_n_0\ : STD_LOGIC;
  signal \xy[65]_i_5_n_0\ : STD_LOGIC;
  signal \xy[65]_i_6_n_0\ : STD_LOGIC;
  signal \xy[65]_i_7_n_0\ : STD_LOGIC;
  signal \xy[65]_i_8_n_0\ : STD_LOGIC;
  signal \xy[65]_i_9_n_0\ : STD_LOGIC;
  signal \xy[66]_i_1_n_0\ : STD_LOGIC;
  signal \xy[67]_i_1_n_0\ : STD_LOGIC;
  signal \xy[68]_i_1_n_0\ : STD_LOGIC;
  signal \xy[69]_i_1_n_0\ : STD_LOGIC;
  signal \xy[6]_i_1_n_0\ : STD_LOGIC;
  signal \xy[70]_i_1_n_0\ : STD_LOGIC;
  signal \xy[71]_i_10_n_0\ : STD_LOGIC;
  signal \xy[71]_i_11_n_0\ : STD_LOGIC;
  signal \xy[71]_i_12_n_0\ : STD_LOGIC;
  signal \xy[71]_i_14_n_0\ : STD_LOGIC;
  signal \xy[71]_i_15_n_0\ : STD_LOGIC;
  signal \xy[71]_i_16_n_0\ : STD_LOGIC;
  signal \xy[71]_i_17_n_0\ : STD_LOGIC;
  signal \xy[71]_i_18_n_0\ : STD_LOGIC;
  signal \xy[71]_i_19_n_0\ : STD_LOGIC;
  signal \xy[71]_i_1_n_0\ : STD_LOGIC;
  signal \xy[71]_i_22_n_0\ : STD_LOGIC;
  signal \xy[71]_i_23_n_0\ : STD_LOGIC;
  signal \xy[71]_i_24_n_0\ : STD_LOGIC;
  signal \xy[71]_i_25_n_0\ : STD_LOGIC;
  signal \xy[71]_i_26_n_0\ : STD_LOGIC;
  signal \xy[71]_i_27_n_0\ : STD_LOGIC;
  signal \xy[71]_i_28_n_0\ : STD_LOGIC;
  signal \xy[71]_i_29_n_0\ : STD_LOGIC;
  signal \xy[71]_i_30_n_0\ : STD_LOGIC;
  signal \xy[71]_i_31_n_0\ : STD_LOGIC;
  signal \xy[71]_i_32_n_0\ : STD_LOGIC;
  signal \xy[71]_i_33_n_0\ : STD_LOGIC;
  signal \xy[71]_i_34_n_0\ : STD_LOGIC;
  signal \xy[71]_i_35_n_0\ : STD_LOGIC;
  signal \xy[71]_i_36_n_0\ : STD_LOGIC;
  signal \xy[71]_i_37_n_0\ : STD_LOGIC;
  signal \xy[71]_i_38_n_0\ : STD_LOGIC;
  signal \xy[71]_i_39_n_0\ : STD_LOGIC;
  signal \xy[71]_i_40_n_0\ : STD_LOGIC;
  signal \xy[71]_i_41_n_0\ : STD_LOGIC;
  signal \xy[71]_i_42_n_0\ : STD_LOGIC;
  signal \xy[71]_i_43_n_0\ : STD_LOGIC;
  signal \xy[71]_i_44_n_0\ : STD_LOGIC;
  signal \xy[71]_i_45_n_0\ : STD_LOGIC;
  signal \xy[71]_i_46_n_0\ : STD_LOGIC;
  signal \xy[71]_i_47_n_0\ : STD_LOGIC;
  signal \xy[71]_i_48_n_0\ : STD_LOGIC;
  signal \xy[71]_i_49_n_0\ : STD_LOGIC;
  signal \xy[71]_i_4_n_0\ : STD_LOGIC;
  signal \xy[71]_i_50_n_0\ : STD_LOGIC;
  signal \xy[71]_i_51_n_0\ : STD_LOGIC;
  signal \xy[71]_i_52_n_0\ : STD_LOGIC;
  signal \xy[71]_i_53_n_0\ : STD_LOGIC;
  signal \xy[71]_i_54_n_0\ : STD_LOGIC;
  signal \xy[71]_i_55_n_0\ : STD_LOGIC;
  signal \xy[71]_i_5_n_0\ : STD_LOGIC;
  signal \xy[71]_i_6_n_0\ : STD_LOGIC;
  signal \xy[71]_i_7_n_0\ : STD_LOGIC;
  signal \xy[71]_i_8_n_0\ : STD_LOGIC;
  signal \xy[71]_i_9_n_0\ : STD_LOGIC;
  signal \xy[72]_i_1_n_0\ : STD_LOGIC;
  signal \xy[73]_i_1_n_0\ : STD_LOGIC;
  signal \xy[74]_i_1_n_0\ : STD_LOGIC;
  signal \xy[75]_i_10_n_0\ : STD_LOGIC;
  signal \xy[75]_i_11_n_0\ : STD_LOGIC;
  signal \xy[75]_i_12_n_0\ : STD_LOGIC;
  signal \xy[75]_i_13_n_0\ : STD_LOGIC;
  signal \xy[75]_i_14_n_0\ : STD_LOGIC;
  signal \xy[75]_i_15_n_0\ : STD_LOGIC;
  signal \xy[75]_i_16_n_0\ : STD_LOGIC;
  signal \xy[75]_i_17_n_0\ : STD_LOGIC;
  signal \xy[75]_i_18_n_0\ : STD_LOGIC;
  signal \xy[75]_i_19_n_0\ : STD_LOGIC;
  signal \xy[75]_i_1_n_0\ : STD_LOGIC;
  signal \xy[75]_i_20_n_0\ : STD_LOGIC;
  signal \xy[75]_i_21_n_0\ : STD_LOGIC;
  signal \xy[75]_i_22_n_0\ : STD_LOGIC;
  signal \xy[75]_i_23_n_0\ : STD_LOGIC;
  signal \xy[75]_i_24_n_0\ : STD_LOGIC;
  signal \xy[75]_i_25_n_0\ : STD_LOGIC;
  signal \xy[75]_i_26_n_0\ : STD_LOGIC;
  signal \xy[75]_i_27_n_0\ : STD_LOGIC;
  signal \xy[75]_i_28_n_0\ : STD_LOGIC;
  signal \xy[75]_i_29_n_0\ : STD_LOGIC;
  signal \xy[75]_i_30_n_0\ : STD_LOGIC;
  signal \xy[75]_i_31_n_0\ : STD_LOGIC;
  signal \xy[75]_i_32_n_0\ : STD_LOGIC;
  signal \xy[75]_i_33_n_0\ : STD_LOGIC;
  signal \xy[75]_i_34_n_0\ : STD_LOGIC;
  signal \xy[75]_i_35_n_0\ : STD_LOGIC;
  signal \xy[75]_i_36_n_0\ : STD_LOGIC;
  signal \xy[75]_i_37_n_0\ : STD_LOGIC;
  signal \xy[75]_i_38_n_0\ : STD_LOGIC;
  signal \xy[75]_i_39_n_0\ : STD_LOGIC;
  signal \xy[75]_i_40_n_0\ : STD_LOGIC;
  signal \xy[75]_i_41_n_0\ : STD_LOGIC;
  signal \xy[75]_i_4_n_0\ : STD_LOGIC;
  signal \xy[75]_i_5_n_0\ : STD_LOGIC;
  signal \xy[75]_i_6_n_0\ : STD_LOGIC;
  signal \xy[75]_i_7_n_0\ : STD_LOGIC;
  signal \xy[75]_i_8_n_0\ : STD_LOGIC;
  signal \xy[75]_i_9_n_0\ : STD_LOGIC;
  signal \xy[76]_i_1_n_0\ : STD_LOGIC;
  signal \xy[77]_i_1_n_0\ : STD_LOGIC;
  signal \xy[78]_i_1_n_0\ : STD_LOGIC;
  signal \xy[79]_i_1_n_0\ : STD_LOGIC;
  signal \xy[7]_i_1_n_0\ : STD_LOGIC;
  signal \xy[80]_i_1_n_0\ : STD_LOGIC;
  signal \xy[81]_i_1_n_0\ : STD_LOGIC;
  signal \xy[82]_i_1_n_0\ : STD_LOGIC;
  signal \xy[83]_i_10_n_0\ : STD_LOGIC;
  signal \xy[83]_i_11_n_0\ : STD_LOGIC;
  signal \xy[83]_i_12_n_0\ : STD_LOGIC;
  signal \xy[83]_i_13_n_0\ : STD_LOGIC;
  signal \xy[83]_i_14_n_0\ : STD_LOGIC;
  signal \xy[83]_i_15_n_0\ : STD_LOGIC;
  signal \xy[83]_i_16_n_0\ : STD_LOGIC;
  signal \xy[83]_i_17_n_0\ : STD_LOGIC;
  signal \xy[83]_i_18_n_0\ : STD_LOGIC;
  signal \xy[83]_i_19_n_0\ : STD_LOGIC;
  signal \xy[83]_i_1_n_0\ : STD_LOGIC;
  signal \xy[83]_i_3_n_0\ : STD_LOGIC;
  signal \xy[83]_i_4_n_0\ : STD_LOGIC;
  signal \xy[83]_i_5_n_0\ : STD_LOGIC;
  signal \xy[83]_i_6_n_0\ : STD_LOGIC;
  signal \xy[83]_i_7_n_0\ : STD_LOGIC;
  signal \xy[83]_i_8_n_0\ : STD_LOGIC;
  signal \xy[83]_i_9_n_0\ : STD_LOGIC;
  signal \xy[84]_i_1_n_0\ : STD_LOGIC;
  signal \xy[85]_i_1_n_0\ : STD_LOGIC;
  signal \xy[86]_i_1_n_0\ : STD_LOGIC;
  signal \xy[87]_i_1_n_0\ : STD_LOGIC;
  signal \xy[88]_i_1_n_0\ : STD_LOGIC;
  signal \xy[89]_i_10_n_0\ : STD_LOGIC;
  signal \xy[89]_i_11_n_0\ : STD_LOGIC;
  signal \xy[89]_i_12_n_0\ : STD_LOGIC;
  signal \xy[89]_i_14_n_0\ : STD_LOGIC;
  signal \xy[89]_i_15_n_0\ : STD_LOGIC;
  signal \xy[89]_i_16_n_0\ : STD_LOGIC;
  signal \xy[89]_i_17_n_0\ : STD_LOGIC;
  signal \xy[89]_i_18_n_0\ : STD_LOGIC;
  signal \xy[89]_i_19_n_0\ : STD_LOGIC;
  signal \xy[89]_i_1_n_0\ : STD_LOGIC;
  signal \xy[89]_i_22_n_0\ : STD_LOGIC;
  signal \xy[89]_i_23_n_0\ : STD_LOGIC;
  signal \xy[89]_i_24_n_0\ : STD_LOGIC;
  signal \xy[89]_i_25_n_0\ : STD_LOGIC;
  signal \xy[89]_i_26_n_0\ : STD_LOGIC;
  signal \xy[89]_i_27_n_0\ : STD_LOGIC;
  signal \xy[89]_i_28_n_0\ : STD_LOGIC;
  signal \xy[89]_i_29_n_0\ : STD_LOGIC;
  signal \xy[89]_i_30_n_0\ : STD_LOGIC;
  signal \xy[89]_i_31_n_0\ : STD_LOGIC;
  signal \xy[89]_i_32_n_0\ : STD_LOGIC;
  signal \xy[89]_i_33_n_0\ : STD_LOGIC;
  signal \xy[89]_i_34_n_0\ : STD_LOGIC;
  signal \xy[89]_i_35_n_0\ : STD_LOGIC;
  signal \xy[89]_i_36_n_0\ : STD_LOGIC;
  signal \xy[89]_i_37_n_0\ : STD_LOGIC;
  signal \xy[89]_i_38_n_0\ : STD_LOGIC;
  signal \xy[89]_i_39_n_0\ : STD_LOGIC;
  signal \xy[89]_i_40_n_0\ : STD_LOGIC;
  signal \xy[89]_i_41_n_0\ : STD_LOGIC;
  signal \xy[89]_i_42_n_0\ : STD_LOGIC;
  signal \xy[89]_i_43_n_0\ : STD_LOGIC;
  signal \xy[89]_i_44_n_0\ : STD_LOGIC;
  signal \xy[89]_i_45_n_0\ : STD_LOGIC;
  signal \xy[89]_i_46_n_0\ : STD_LOGIC;
  signal \xy[89]_i_47_n_0\ : STD_LOGIC;
  signal \xy[89]_i_48_n_0\ : STD_LOGIC;
  signal \xy[89]_i_49_n_0\ : STD_LOGIC;
  signal \xy[89]_i_4_n_0\ : STD_LOGIC;
  signal \xy[89]_i_50_n_0\ : STD_LOGIC;
  signal \xy[89]_i_51_n_0\ : STD_LOGIC;
  signal \xy[89]_i_52_n_0\ : STD_LOGIC;
  signal \xy[89]_i_53_n_0\ : STD_LOGIC;
  signal \xy[89]_i_54_n_0\ : STD_LOGIC;
  signal \xy[89]_i_55_n_0\ : STD_LOGIC;
  signal \xy[89]_i_5_n_0\ : STD_LOGIC;
  signal \xy[89]_i_6_n_0\ : STD_LOGIC;
  signal \xy[89]_i_7_n_0\ : STD_LOGIC;
  signal \xy[89]_i_8_n_0\ : STD_LOGIC;
  signal \xy[89]_i_9_n_0\ : STD_LOGIC;
  signal \xy[8]_i_1_n_0\ : STD_LOGIC;
  signal \xy[9]_i_1_n_0\ : STD_LOGIC;
  signal \xy_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \xy_reg[11]_i_2_n_1\ : STD_LOGIC;
  signal \xy_reg[11]_i_2_n_2\ : STD_LOGIC;
  signal \xy_reg[11]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[11]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[11]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[11]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[11]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_0\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_1\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_10\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_11\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_12\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_13\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_14\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_15\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_2\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_3\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_4\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_5\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_6\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_7\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_8\ : STD_LOGIC;
  signal \xy_reg[17]_i_13_n_9\ : STD_LOGIC;
  signal \xy_reg[17]_i_20_n_13\ : STD_LOGIC;
  signal \xy_reg[17]_i_20_n_14\ : STD_LOGIC;
  signal \xy_reg[17]_i_20_n_15\ : STD_LOGIC;
  signal \xy_reg[17]_i_20_n_4\ : STD_LOGIC;
  signal \xy_reg[17]_i_20_n_6\ : STD_LOGIC;
  signal \xy_reg[17]_i_20_n_7\ : STD_LOGIC;
  signal \xy_reg[17]_i_21_n_13\ : STD_LOGIC;
  signal \xy_reg[17]_i_21_n_14\ : STD_LOGIC;
  signal \xy_reg[17]_i_21_n_15\ : STD_LOGIC;
  signal \xy_reg[17]_i_21_n_4\ : STD_LOGIC;
  signal \xy_reg[17]_i_21_n_6\ : STD_LOGIC;
  signal \xy_reg[17]_i_21_n_7\ : STD_LOGIC;
  signal \xy_reg[17]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[17]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[17]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[17]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[17]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[17]_i_3_n_12\ : STD_LOGIC;
  signal \xy_reg[17]_i_3_n_13\ : STD_LOGIC;
  signal \xy_reg[17]_i_3_n_14\ : STD_LOGIC;
  signal \xy_reg[17]_i_3_n_15\ : STD_LOGIC;
  signal \xy_reg[17]_i_3_n_5\ : STD_LOGIC;
  signal \xy_reg[17]_i_3_n_6\ : STD_LOGIC;
  signal \xy_reg[17]_i_3_n_7\ : STD_LOGIC;
  signal \xy_reg[21]_i_2_n_0\ : STD_LOGIC;
  signal \xy_reg[21]_i_2_n_1\ : STD_LOGIC;
  signal \xy_reg[21]_i_2_n_10\ : STD_LOGIC;
  signal \xy_reg[21]_i_2_n_11\ : STD_LOGIC;
  signal \xy_reg[21]_i_2_n_12\ : STD_LOGIC;
  signal \xy_reg[21]_i_2_n_2\ : STD_LOGIC;
  signal \xy_reg[21]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[21]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[21]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[21]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[21]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[21]_i_2_n_8\ : STD_LOGIC;
  signal \xy_reg[21]_i_2_n_9\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_0\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_1\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_10\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_11\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_12\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_13\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_14\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_15\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_2\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_3\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_4\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_5\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_6\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_7\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_8\ : STD_LOGIC;
  signal \xy_reg[21]_i_3_n_9\ : STD_LOGIC;
  signal \xy_reg[29]_i_2_n_0\ : STD_LOGIC;
  signal \xy_reg[29]_i_2_n_1\ : STD_LOGIC;
  signal \xy_reg[29]_i_2_n_2\ : STD_LOGIC;
  signal \xy_reg[29]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[29]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[29]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[29]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[29]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_0\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_1\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_10\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_11\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_12\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_13\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_14\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_15\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_2\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_3\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_4\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_5\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_6\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_7\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_8\ : STD_LOGIC;
  signal \xy_reg[35]_i_13_n_9\ : STD_LOGIC;
  signal \xy_reg[35]_i_20_n_13\ : STD_LOGIC;
  signal \xy_reg[35]_i_20_n_14\ : STD_LOGIC;
  signal \xy_reg[35]_i_20_n_15\ : STD_LOGIC;
  signal \xy_reg[35]_i_20_n_4\ : STD_LOGIC;
  signal \xy_reg[35]_i_20_n_6\ : STD_LOGIC;
  signal \xy_reg[35]_i_20_n_7\ : STD_LOGIC;
  signal \xy_reg[35]_i_21_n_13\ : STD_LOGIC;
  signal \xy_reg[35]_i_21_n_14\ : STD_LOGIC;
  signal \xy_reg[35]_i_21_n_15\ : STD_LOGIC;
  signal \xy_reg[35]_i_21_n_4\ : STD_LOGIC;
  signal \xy_reg[35]_i_21_n_6\ : STD_LOGIC;
  signal \xy_reg[35]_i_21_n_7\ : STD_LOGIC;
  signal \xy_reg[35]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[35]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[35]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[35]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[35]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[35]_i_3_n_12\ : STD_LOGIC;
  signal \xy_reg[35]_i_3_n_13\ : STD_LOGIC;
  signal \xy_reg[35]_i_3_n_14\ : STD_LOGIC;
  signal \xy_reg[35]_i_3_n_15\ : STD_LOGIC;
  signal \xy_reg[35]_i_3_n_5\ : STD_LOGIC;
  signal \xy_reg[35]_i_3_n_6\ : STD_LOGIC;
  signal \xy_reg[35]_i_3_n_7\ : STD_LOGIC;
  signal \xy_reg[39]_i_2_n_0\ : STD_LOGIC;
  signal \xy_reg[39]_i_2_n_1\ : STD_LOGIC;
  signal \xy_reg[39]_i_2_n_10\ : STD_LOGIC;
  signal \xy_reg[39]_i_2_n_11\ : STD_LOGIC;
  signal \xy_reg[39]_i_2_n_12\ : STD_LOGIC;
  signal \xy_reg[39]_i_2_n_2\ : STD_LOGIC;
  signal \xy_reg[39]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[39]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[39]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[39]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[39]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[39]_i_2_n_8\ : STD_LOGIC;
  signal \xy_reg[39]_i_2_n_9\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_0\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_1\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_10\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_11\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_12\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_13\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_14\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_15\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_2\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_3\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_4\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_5\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_6\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_7\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_8\ : STD_LOGIC;
  signal \xy_reg[39]_i_3_n_9\ : STD_LOGIC;
  signal \xy_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \xy_reg[3]_i_2_n_1\ : STD_LOGIC;
  signal \xy_reg[3]_i_2_n_10\ : STD_LOGIC;
  signal \xy_reg[3]_i_2_n_11\ : STD_LOGIC;
  signal \xy_reg[3]_i_2_n_12\ : STD_LOGIC;
  signal \xy_reg[3]_i_2_n_2\ : STD_LOGIC;
  signal \xy_reg[3]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[3]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[3]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[3]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[3]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[3]_i_2_n_8\ : STD_LOGIC;
  signal \xy_reg[3]_i_2_n_9\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_0\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_1\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_10\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_11\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_12\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_13\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_14\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_15\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_2\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_3\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_4\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_5\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_6\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_7\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_8\ : STD_LOGIC;
  signal \xy_reg[3]_i_3_n_9\ : STD_LOGIC;
  signal \xy_reg[47]_i_2_n_0\ : STD_LOGIC;
  signal \xy_reg[47]_i_2_n_1\ : STD_LOGIC;
  signal \xy_reg[47]_i_2_n_2\ : STD_LOGIC;
  signal \xy_reg[47]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[47]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[47]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[47]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[47]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_0\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_1\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_10\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_11\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_12\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_13\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_14\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_15\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_2\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_3\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_4\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_5\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_6\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_7\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_8\ : STD_LOGIC;
  signal \xy_reg[53]_i_13_n_9\ : STD_LOGIC;
  signal \xy_reg[53]_i_20_n_13\ : STD_LOGIC;
  signal \xy_reg[53]_i_20_n_14\ : STD_LOGIC;
  signal \xy_reg[53]_i_20_n_15\ : STD_LOGIC;
  signal \xy_reg[53]_i_20_n_4\ : STD_LOGIC;
  signal \xy_reg[53]_i_20_n_6\ : STD_LOGIC;
  signal \xy_reg[53]_i_20_n_7\ : STD_LOGIC;
  signal \xy_reg[53]_i_21_n_13\ : STD_LOGIC;
  signal \xy_reg[53]_i_21_n_14\ : STD_LOGIC;
  signal \xy_reg[53]_i_21_n_15\ : STD_LOGIC;
  signal \xy_reg[53]_i_21_n_4\ : STD_LOGIC;
  signal \xy_reg[53]_i_21_n_6\ : STD_LOGIC;
  signal \xy_reg[53]_i_21_n_7\ : STD_LOGIC;
  signal \xy_reg[53]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[53]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[53]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[53]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[53]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[53]_i_3_n_12\ : STD_LOGIC;
  signal \xy_reg[53]_i_3_n_13\ : STD_LOGIC;
  signal \xy_reg[53]_i_3_n_14\ : STD_LOGIC;
  signal \xy_reg[53]_i_3_n_15\ : STD_LOGIC;
  signal \xy_reg[53]_i_3_n_5\ : STD_LOGIC;
  signal \xy_reg[53]_i_3_n_6\ : STD_LOGIC;
  signal \xy_reg[53]_i_3_n_7\ : STD_LOGIC;
  signal \xy_reg[57]_i_2_n_0\ : STD_LOGIC;
  signal \xy_reg[57]_i_2_n_1\ : STD_LOGIC;
  signal \xy_reg[57]_i_2_n_10\ : STD_LOGIC;
  signal \xy_reg[57]_i_2_n_11\ : STD_LOGIC;
  signal \xy_reg[57]_i_2_n_12\ : STD_LOGIC;
  signal \xy_reg[57]_i_2_n_2\ : STD_LOGIC;
  signal \xy_reg[57]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[57]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[57]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[57]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[57]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[57]_i_2_n_8\ : STD_LOGIC;
  signal \xy_reg[57]_i_2_n_9\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_0\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_1\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_10\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_11\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_12\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_13\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_14\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_15\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_2\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_3\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_4\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_5\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_6\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_7\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_8\ : STD_LOGIC;
  signal \xy_reg[57]_i_3_n_9\ : STD_LOGIC;
  signal \xy_reg[65]_i_2_n_0\ : STD_LOGIC;
  signal \xy_reg[65]_i_2_n_1\ : STD_LOGIC;
  signal \xy_reg[65]_i_2_n_2\ : STD_LOGIC;
  signal \xy_reg[65]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[65]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[65]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[65]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[65]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_0\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_1\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_10\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_11\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_12\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_13\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_14\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_15\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_2\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_3\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_4\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_5\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_6\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_7\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_8\ : STD_LOGIC;
  signal \xy_reg[71]_i_13_n_9\ : STD_LOGIC;
  signal \xy_reg[71]_i_20_n_13\ : STD_LOGIC;
  signal \xy_reg[71]_i_20_n_14\ : STD_LOGIC;
  signal \xy_reg[71]_i_20_n_15\ : STD_LOGIC;
  signal \xy_reg[71]_i_20_n_4\ : STD_LOGIC;
  signal \xy_reg[71]_i_20_n_6\ : STD_LOGIC;
  signal \xy_reg[71]_i_20_n_7\ : STD_LOGIC;
  signal \xy_reg[71]_i_21_n_13\ : STD_LOGIC;
  signal \xy_reg[71]_i_21_n_14\ : STD_LOGIC;
  signal \xy_reg[71]_i_21_n_15\ : STD_LOGIC;
  signal \xy_reg[71]_i_21_n_4\ : STD_LOGIC;
  signal \xy_reg[71]_i_21_n_6\ : STD_LOGIC;
  signal \xy_reg[71]_i_21_n_7\ : STD_LOGIC;
  signal \xy_reg[71]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[71]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[71]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[71]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[71]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[71]_i_3_n_12\ : STD_LOGIC;
  signal \xy_reg[71]_i_3_n_13\ : STD_LOGIC;
  signal \xy_reg[71]_i_3_n_14\ : STD_LOGIC;
  signal \xy_reg[71]_i_3_n_15\ : STD_LOGIC;
  signal \xy_reg[71]_i_3_n_5\ : STD_LOGIC;
  signal \xy_reg[71]_i_3_n_6\ : STD_LOGIC;
  signal \xy_reg[71]_i_3_n_7\ : STD_LOGIC;
  signal \xy_reg[75]_i_2_n_0\ : STD_LOGIC;
  signal \xy_reg[75]_i_2_n_1\ : STD_LOGIC;
  signal \xy_reg[75]_i_2_n_10\ : STD_LOGIC;
  signal \xy_reg[75]_i_2_n_11\ : STD_LOGIC;
  signal \xy_reg[75]_i_2_n_12\ : STD_LOGIC;
  signal \xy_reg[75]_i_2_n_2\ : STD_LOGIC;
  signal \xy_reg[75]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[75]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[75]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[75]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[75]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[75]_i_2_n_8\ : STD_LOGIC;
  signal \xy_reg[75]_i_2_n_9\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_0\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_1\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_10\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_11\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_12\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_13\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_14\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_15\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_2\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_3\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_4\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_5\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_6\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_7\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_8\ : STD_LOGIC;
  signal \xy_reg[75]_i_3_n_9\ : STD_LOGIC;
  signal \xy_reg[83]_i_2_n_0\ : STD_LOGIC;
  signal \xy_reg[83]_i_2_n_1\ : STD_LOGIC;
  signal \xy_reg[83]_i_2_n_2\ : STD_LOGIC;
  signal \xy_reg[83]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[83]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[83]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[83]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[83]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_0\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_1\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_10\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_11\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_12\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_13\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_14\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_15\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_2\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_3\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_4\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_5\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_6\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_7\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_8\ : STD_LOGIC;
  signal \xy_reg[89]_i_13_n_9\ : STD_LOGIC;
  signal \xy_reg[89]_i_20_n_13\ : STD_LOGIC;
  signal \xy_reg[89]_i_20_n_14\ : STD_LOGIC;
  signal \xy_reg[89]_i_20_n_15\ : STD_LOGIC;
  signal \xy_reg[89]_i_20_n_4\ : STD_LOGIC;
  signal \xy_reg[89]_i_20_n_6\ : STD_LOGIC;
  signal \xy_reg[89]_i_20_n_7\ : STD_LOGIC;
  signal \xy_reg[89]_i_21_n_13\ : STD_LOGIC;
  signal \xy_reg[89]_i_21_n_14\ : STD_LOGIC;
  signal \xy_reg[89]_i_21_n_15\ : STD_LOGIC;
  signal \xy_reg[89]_i_21_n_4\ : STD_LOGIC;
  signal \xy_reg[89]_i_21_n_6\ : STD_LOGIC;
  signal \xy_reg[89]_i_21_n_7\ : STD_LOGIC;
  signal \xy_reg[89]_i_2_n_3\ : STD_LOGIC;
  signal \xy_reg[89]_i_2_n_4\ : STD_LOGIC;
  signal \xy_reg[89]_i_2_n_5\ : STD_LOGIC;
  signal \xy_reg[89]_i_2_n_6\ : STD_LOGIC;
  signal \xy_reg[89]_i_2_n_7\ : STD_LOGIC;
  signal \xy_reg[89]_i_3_n_12\ : STD_LOGIC;
  signal \xy_reg[89]_i_3_n_13\ : STD_LOGIC;
  signal \xy_reg[89]_i_3_n_14\ : STD_LOGIC;
  signal \xy_reg[89]_i_3_n_15\ : STD_LOGIC;
  signal \xy_reg[89]_i_3_n_5\ : STD_LOGIC;
  signal \xy_reg[89]_i_3_n_6\ : STD_LOGIC;
  signal \xy_reg[89]_i_3_n_7\ : STD_LOGIC;
  signal ysqr : STD_LOGIC_VECTOR ( 89 downto 0 );
  signal ysqr0 : STD_LOGIC_VECTOR ( 17 downto 2 );
  signal ysqr00_in : STD_LOGIC_VECTOR ( 17 downto 2 );
  signal ysqr01_in : STD_LOGIC_VECTOR ( 17 downto 2 );
  signal ysqr02_in : STD_LOGIC_VECTOR ( 17 downto 2 );
  signal ysqr03_in : STD_LOGIC_VECTOR ( 17 downto 2 );
  signal ysqr4p1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \ysqr4p1[0]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[10]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[11]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[12]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[13]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[14]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[15]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[16]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[17]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[2]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[3]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[4]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[5]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[6]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[7]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[8]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p1[9]_i_1_n_0\ : STD_LOGIC;
  signal ysqr4p2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \ysqr4p2[0]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[10]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[11]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[12]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[13]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[14]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[15]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[16]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[17]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[2]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[3]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[4]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[5]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[6]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[7]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[8]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr4p2[9]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[0]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[10]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_17_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_18_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_3_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[11]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[12]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[13]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[14]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[15]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[16]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_20_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_21_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_22_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_23_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_24_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_25_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_26_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_27_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_28_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_29_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_30_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_31_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_32_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_33_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_34_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_35_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_36_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_37_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_38_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_39_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_40_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_41_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_42_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_43_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_44_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_45_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[17]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[18]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[20]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_17_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_18_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_20_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_21_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_22_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_23_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_24_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_25_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_26_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_27_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_28_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_29_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_30_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_31_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_32_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_33_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[21]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[22]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[23]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[24]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[25]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[26]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[27]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[28]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_17_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_18_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_3_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[29]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[2]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[30]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[31]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[32]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[33]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[34]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_20_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_21_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_22_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_23_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_24_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_25_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_26_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_27_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_28_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_29_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_30_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_31_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_32_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_33_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_34_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_35_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_36_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_37_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_38_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_39_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_40_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_41_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_42_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_43_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_44_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_45_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[35]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[36]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[38]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_17_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_18_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_20_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_21_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_22_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_23_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_24_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_25_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_26_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_27_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_28_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_29_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_30_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_31_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_32_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_33_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[39]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_17_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_18_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_20_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_21_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_22_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_23_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_24_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_25_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_26_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_27_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_28_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_29_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_30_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_31_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_32_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_33_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[3]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[40]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[41]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[42]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[43]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[44]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[45]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[46]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_17_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_18_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_3_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[47]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[48]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[49]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[4]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[50]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[51]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[52]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_20_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_21_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_22_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_23_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_24_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_25_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_26_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_27_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_28_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_29_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_30_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_31_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_32_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_33_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_34_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_35_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_36_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_37_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_38_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_39_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_40_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_41_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_42_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_43_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_44_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_45_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[53]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[54]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[56]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_17_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_18_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_20_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_21_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_22_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_23_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_24_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_25_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_26_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_27_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_28_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_29_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_30_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_31_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_32_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_33_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[57]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[58]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[59]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[5]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[60]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[61]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[62]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[63]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[64]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_17_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_18_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_3_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[65]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[66]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[67]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[68]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[69]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[6]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[70]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_20_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_21_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_22_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_23_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_24_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_25_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_26_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_27_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_28_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_29_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_30_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_31_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_32_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_33_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_34_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_35_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_36_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_37_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_38_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_39_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_40_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_41_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_42_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_43_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_44_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_45_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[71]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[72]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[74]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_17_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_18_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_20_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_21_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_22_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_23_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_24_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_25_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_26_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_27_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_28_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_29_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_30_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_31_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_32_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_33_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[75]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[76]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[77]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[78]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[79]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[7]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[80]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[81]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[82]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_17_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_18_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_3_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[83]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[84]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[85]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[86]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[87]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[88]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_10_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_11_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_12_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_14_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_15_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_16_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_19_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_20_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_21_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_22_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_23_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_24_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_25_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_26_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_27_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_28_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_29_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_30_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_31_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_32_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_33_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_34_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_35_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_36_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_37_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_38_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_39_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_40_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_41_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_42_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_43_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_44_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_45_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_4_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_5_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_6_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_7_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_8_n_0\ : STD_LOGIC;
  signal \ysqr[89]_i_9_n_0\ : STD_LOGIC;
  signal \ysqr[8]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr[9]_i_1_n_0\ : STD_LOGIC;
  signal \ysqr_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \ysqr_reg[11]_i_2_n_1\ : STD_LOGIC;
  signal \ysqr_reg[11]_i_2_n_2\ : STD_LOGIC;
  signal \ysqr_reg[11]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[11]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[11]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[11]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[11]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_1\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_10\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_11\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_12\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_13\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_14\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_15\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_2\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_3\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_4\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_5\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_6\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_7\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_8\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_13_n_9\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_17_n_13\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_17_n_14\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_17_n_15\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_17_n_4\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_17_n_6\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_17_n_7\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_18_n_14\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_18_n_15\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_18_n_5\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_18_n_7\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_3_n_12\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_3_n_13\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_3_n_14\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_3_n_15\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_3_n_5\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_3_n_6\ : STD_LOGIC;
  signal \ysqr_reg[17]_i_3_n_7\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_2_n_0\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_2_n_1\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_2_n_10\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_2_n_11\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_2_n_12\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_2_n_13\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_2_n_2\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_2_n_8\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_2_n_9\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_0\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_1\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_10\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_11\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_12\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_13\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_14\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_15\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_2\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_3\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_4\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_5\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_6\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_7\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_8\ : STD_LOGIC;
  signal \ysqr_reg[21]_i_3_n_9\ : STD_LOGIC;
  signal \ysqr_reg[29]_i_2_n_0\ : STD_LOGIC;
  signal \ysqr_reg[29]_i_2_n_1\ : STD_LOGIC;
  signal \ysqr_reg[29]_i_2_n_2\ : STD_LOGIC;
  signal \ysqr_reg[29]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[29]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[29]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[29]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[29]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_1\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_10\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_11\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_12\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_13\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_14\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_15\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_2\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_3\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_4\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_5\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_6\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_7\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_8\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_13_n_9\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_17_n_13\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_17_n_14\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_17_n_15\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_17_n_4\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_17_n_6\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_17_n_7\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_18_n_14\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_18_n_15\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_18_n_5\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_18_n_7\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_3_n_12\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_3_n_13\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_3_n_14\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_3_n_15\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_3_n_5\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_3_n_6\ : STD_LOGIC;
  signal \ysqr_reg[35]_i_3_n_7\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_2_n_0\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_2_n_1\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_2_n_10\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_2_n_11\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_2_n_12\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_2_n_13\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_2_n_2\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_2_n_8\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_2_n_9\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_0\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_1\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_10\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_11\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_12\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_13\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_14\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_15\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_2\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_3\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_4\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_5\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_6\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_7\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_8\ : STD_LOGIC;
  signal \ysqr_reg[39]_i_3_n_9\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_2_n_1\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_2_n_10\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_2_n_11\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_2_n_12\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_2_n_13\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_2_n_2\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_2_n_8\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_2_n_9\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_0\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_1\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_10\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_11\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_12\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_13\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_14\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_15\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_2\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_3\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_4\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_5\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_6\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_7\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_8\ : STD_LOGIC;
  signal \ysqr_reg[3]_i_3_n_9\ : STD_LOGIC;
  signal \ysqr_reg[47]_i_2_n_0\ : STD_LOGIC;
  signal \ysqr_reg[47]_i_2_n_1\ : STD_LOGIC;
  signal \ysqr_reg[47]_i_2_n_2\ : STD_LOGIC;
  signal \ysqr_reg[47]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[47]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[47]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[47]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[47]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_1\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_10\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_11\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_12\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_13\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_14\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_15\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_2\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_3\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_4\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_5\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_6\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_7\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_8\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_13_n_9\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_17_n_13\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_17_n_14\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_17_n_15\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_17_n_4\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_17_n_6\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_17_n_7\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_18_n_14\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_18_n_15\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_18_n_5\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_18_n_7\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_3_n_12\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_3_n_13\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_3_n_14\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_3_n_15\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_3_n_5\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_3_n_6\ : STD_LOGIC;
  signal \ysqr_reg[53]_i_3_n_7\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_2_n_0\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_2_n_1\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_2_n_10\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_2_n_11\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_2_n_12\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_2_n_13\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_2_n_2\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_2_n_8\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_2_n_9\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_0\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_1\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_10\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_11\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_12\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_13\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_14\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_15\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_2\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_3\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_4\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_5\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_6\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_7\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_8\ : STD_LOGIC;
  signal \ysqr_reg[57]_i_3_n_9\ : STD_LOGIC;
  signal \ysqr_reg[65]_i_2_n_0\ : STD_LOGIC;
  signal \ysqr_reg[65]_i_2_n_1\ : STD_LOGIC;
  signal \ysqr_reg[65]_i_2_n_2\ : STD_LOGIC;
  signal \ysqr_reg[65]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[65]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[65]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[65]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[65]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_1\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_10\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_11\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_12\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_13\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_14\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_15\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_2\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_3\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_4\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_5\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_6\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_7\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_8\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_13_n_9\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_17_n_13\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_17_n_14\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_17_n_15\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_17_n_4\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_17_n_6\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_17_n_7\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_18_n_14\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_18_n_15\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_18_n_5\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_18_n_7\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_3_n_12\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_3_n_13\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_3_n_14\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_3_n_15\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_3_n_5\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_3_n_6\ : STD_LOGIC;
  signal \ysqr_reg[71]_i_3_n_7\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_2_n_0\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_2_n_1\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_2_n_10\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_2_n_11\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_2_n_12\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_2_n_13\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_2_n_2\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_2_n_8\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_2_n_9\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_0\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_1\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_10\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_11\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_12\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_13\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_14\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_15\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_2\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_3\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_4\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_5\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_6\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_7\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_8\ : STD_LOGIC;
  signal \ysqr_reg[75]_i_3_n_9\ : STD_LOGIC;
  signal \ysqr_reg[83]_i_2_n_0\ : STD_LOGIC;
  signal \ysqr_reg[83]_i_2_n_1\ : STD_LOGIC;
  signal \ysqr_reg[83]_i_2_n_2\ : STD_LOGIC;
  signal \ysqr_reg[83]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[83]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[83]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[83]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[83]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_0\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_1\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_10\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_11\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_12\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_13\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_14\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_15\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_2\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_3\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_4\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_5\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_6\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_7\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_8\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_13_n_9\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_17_n_13\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_17_n_14\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_17_n_15\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_17_n_4\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_17_n_6\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_17_n_7\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_18_n_14\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_18_n_15\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_18_n_5\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_18_n_7\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_2_n_3\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_2_n_4\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_2_n_5\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_2_n_6\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_2_n_7\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_3_n_12\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_3_n_13\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_3_n_14\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_3_n_15\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_3_n_5\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_3_n_6\ : STD_LOGIC;
  signal \ysqr_reg[89]_i_3_n_7\ : STD_LOGIC;
  signal \NLW_colsumXA_reg[18]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_colsumXA_reg[18]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_colsumXA_reg[37]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_colsumXA_reg[37]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_colsumXB_reg[19]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_colsumXB_reg[19]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_colsumXC_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_colsumXC_reg[20]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_colsumXYA_reg[18]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_colsumXYA_reg[18]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_colsumXYA_reg[37]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_colsumXYA_reg[37]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_colsumXYB_reg[19]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_colsumXYB_reg[19]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_colsumXYC_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_colsumXYC_reg[20]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_colsumYA_reg[18]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_colsumYA_reg[18]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_colsumYA_reg[37]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_colsumYA_reg[37]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_colsumYB_reg[19]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_colsumYB_reg[19]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_colsumYC_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_colsumYC_reg[20]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_diffI_II_reg[46]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_diffI_II_reg[46]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_dwrCoobuf_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_dwrCoobuf_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_dwrCoobuf_reg[31]_i_102_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_dwrCoobuf_reg[31]_i_102_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_dwrCoobuf_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_dwrCoobuf_reg[31]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_dwrCoobuf_reg[31]_i_14_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_dwrCoobuf_reg[31]_i_14_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_dwrCoobuf_reg[31]_i_15_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_dwrCoobuf_reg[31]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_dwrCoobuf_reg[31]_i_17_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_dwrCoobuf_reg[31]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_dwrCoobuf_reg[31]_i_67_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_dwrCoobuf_reg[31]_i_67_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_dwrCoobuf_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_dwrCoobuf_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_dwrCoobuf_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_dwrCoobuf_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_fghij_reg[30]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_fghij_reg[30]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_r_reg[47]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_scoreMax_lcl_reg[7]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_scoreMax_lcl_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_scoreMin_lcl_reg[7]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_scoreMin_lcl_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_sumIII_reg[23]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_sumXA_reg[21]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_sumXA_reg[21]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_sumXA_reg[43]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_sumXA_reg[43]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_sumXB_reg[22]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_sumXB_reg[22]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_sumXYA_reg[21]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_sumXYA_reg[21]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_sumXYA_reg[43]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_sumXYA_reg[43]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_sumXYB_reg[22]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_sumXYB_reg[22]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_sumXY_reg[22]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_sumXY_reg[22]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_sumX_reg[22]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_sumX_reg[22]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_sumYA_reg[21]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_sumYA_reg[21]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_sumYA_reg[43]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_sumYA_reg[43]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_sumYB_reg[22]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_sumYB_reg[22]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_sumY_reg[22]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_sumY_reg[22]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal NLW_termI0_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_termI0_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_termI0_OVERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_termI0_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_termI0_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_termI0_UNDERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_termI0_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_termI0_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_termI0_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_termI0_XOROUT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_termI0__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termI0__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termI0__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termI0__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termI0__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termI0__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termI0__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal \NLW_termI0__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \NLW_termI0__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_termI0__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 29 );
  signal \NLW_termI0__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal \NLW_termI0__0_XOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_termII0_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_termII0_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_termII0_OVERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_termII0_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_termII0_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_termII0_UNDERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_termII0_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_termII0_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_termII0_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_termII0_XOROUT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_termII0__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termII0__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termII0__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termII0__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termII0__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termII0__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termII0__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal \NLW_termII0__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \NLW_termII0__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_termII0__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 29 );
  signal \NLW_termII0__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal \NLW_termII0__0_XOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_termIII0_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_termIII0_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_termIII0_OVERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_termIII0_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_termIII0_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_termIII0_UNDERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_termIII0_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_termIII0_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_termIII0_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_termIII0_XOROUT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_termIII0__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termIII0__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termIII0__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termIII0__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termIII0__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termIII0__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_termIII0__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal \NLW_termIII0__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \NLW_termIII0__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_termIII0__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 31 );
  signal \NLW_termIII0__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal \NLW_termIII0__0_XOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_termIIIk_reg[1]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \NLW_termIIIk_reg[43]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_termIIIk_reg[43]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_xsqr_reg[17]_i_17_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xsqr_reg[17]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xsqr_reg[17]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_xsqr_reg[17]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xsqr_reg[17]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_xsqr_reg[17]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_xsqr_reg[17]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xsqr_reg[17]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_xsqr_reg[21]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_xsqr_reg[35]_i_17_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xsqr_reg[35]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xsqr_reg[35]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_xsqr_reg[35]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xsqr_reg[35]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_xsqr_reg[35]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_xsqr_reg[35]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xsqr_reg[35]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_xsqr_reg[39]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_xsqr_reg[3]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_xsqr_reg[53]_i_17_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xsqr_reg[53]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xsqr_reg[53]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_xsqr_reg[53]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xsqr_reg[53]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_xsqr_reg[53]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_xsqr_reg[53]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xsqr_reg[53]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_xsqr_reg[57]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_xsqr_reg[71]_i_17_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xsqr_reg[71]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xsqr_reg[71]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_xsqr_reg[71]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xsqr_reg[71]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_xsqr_reg[71]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_xsqr_reg[71]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xsqr_reg[71]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_xsqr_reg[75]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_xsqr_reg[89]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xsqr_reg[89]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xsqr_reg[89]_i_19_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_xsqr_reg[89]_i_19_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xsqr_reg[89]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_xsqr_reg[89]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_xsqr_reg[89]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xsqr_reg[89]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_xy_reg[17]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_xy_reg[17]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_xy_reg[17]_i_20_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xy_reg[17]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[17]_i_21_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xy_reg[17]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[17]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[17]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_xy_reg[35]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_xy_reg[35]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_xy_reg[35]_i_20_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xy_reg[35]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[35]_i_21_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xy_reg[35]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[35]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[35]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_xy_reg[53]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_xy_reg[53]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_xy_reg[53]_i_20_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xy_reg[53]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[53]_i_21_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xy_reg[53]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[53]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[53]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_xy_reg[71]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_xy_reg[71]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_xy_reg[71]_i_20_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xy_reg[71]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[71]_i_21_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xy_reg[71]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[71]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[71]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_xy_reg[89]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_xy_reg[89]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_xy_reg[89]_i_20_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xy_reg[89]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[89]_i_21_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_xy_reg[89]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[89]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_xy_reg[89]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_ysqr_reg[17]_i_17_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_ysqr_reg[17]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_ysqr_reg[17]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_ysqr_reg[17]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_ysqr_reg[17]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_ysqr_reg[17]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_ysqr_reg[17]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_ysqr_reg[17]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_ysqr_reg[21]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_ysqr_reg[35]_i_17_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_ysqr_reg[35]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_ysqr_reg[35]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_ysqr_reg[35]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_ysqr_reg[35]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_ysqr_reg[35]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_ysqr_reg[35]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_ysqr_reg[35]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_ysqr_reg[39]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_ysqr_reg[3]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_ysqr_reg[53]_i_17_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_ysqr_reg[53]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_ysqr_reg[53]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_ysqr_reg[53]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_ysqr_reg[53]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_ysqr_reg[53]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_ysqr_reg[53]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_ysqr_reg[53]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_ysqr_reg[57]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_ysqr_reg[71]_i_17_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_ysqr_reg[71]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_ysqr_reg[71]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_ysqr_reg[71]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_ysqr_reg[71]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_ysqr_reg[71]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_ysqr_reg[71]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_ysqr_reg[71]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_ysqr_reg[75]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_ysqr_reg[89]_i_17_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_ysqr_reg[89]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_ysqr_reg[89]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_ysqr_reg[89]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_ysqr_reg[89]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_ysqr_reg[89]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_ysqr_reg[89]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_ysqr_reg[89]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateCoobufB_reg[0]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateCoobufB_reg[1]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateCoobufB_reg[2]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateCoobufB_reg[3]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateCoobufB_reg[5]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \aCoobufB[0]_i_1\ : label is "soft_lutpair952";
  attribute SOFT_HLUTNM of \aCoobufB[2]_i_1\ : label is "soft_lutpair826";
  attribute SOFT_HLUTNM of \aCoobufB[3]_i_1\ : label is "soft_lutpair826";
  attribute SOFT_HLUTNM of \aCoobufB[5]_i_1\ : label is "soft_lutpair952";
  attribute SOFT_HLUTNM of \aCoobufB[6]_i_1\ : label is "soft_lutpair862";
  attribute SOFT_HLUTNM of \aCoobufB[7]_i_2\ : label is "soft_lutpair862";
  attribute SOFT_HLUTNM of \aCoobuf[0]_i_1\ : label is "soft_lutpair803";
  attribute SOFT_HLUTNM of \aCoobuf[1]_i_1\ : label is "soft_lutpair803";
  attribute SOFT_HLUTNM of \aCoobuf[8]_i_2\ : label is "soft_lutpair804";
  attribute SOFT_HLUTNM of \aImdbufB[0]_i_1\ : label is "soft_lutpair798";
  attribute SOFT_HLUTNM of \aImdbufB[4]_i_2\ : label is "soft_lutpair783";
  attribute SOFT_HLUTNM of \aImdbufB[5]_i_2\ : label is "soft_lutpair783";
  attribute SOFT_HLUTNM of \aImdbuf[0]_i_1\ : label is "soft_lutpair799";
  attribute SOFT_HLUTNM of \aImdbuf[10]_i_4\ : label is "soft_lutpair855";
  attribute SOFT_HLUTNM of \aImdbuf[10]_i_6\ : label is "soft_lutpair798";
  attribute SOFT_HLUTNM of \aImdbuf[10]_i_7\ : label is "soft_lutpair854";
  attribute SOFT_HLUTNM of \aImdbuf[4]_i_2\ : label is "soft_lutpair782";
  attribute SOFT_HLUTNM of \aImdbuf[5]_i_2\ : label is "soft_lutpair782";
  attribute SOFT_HLUTNM of ackInvAcquire_sig_i_1 : label is "soft_lutpair833";
  attribute SOFT_HLUTNM of \col_lcl[0]__0_i_1\ : label is "soft_lutpair801";
  attribute SOFT_HLUTNM of \col_lcl[0]_i_1\ : label is "soft_lutpair854";
  attribute SOFT_HLUTNM of \col_lcl[10]__0_i_14\ : label is "soft_lutpair777";
  attribute SOFT_HLUTNM of \col_lcl[10]__0_i_16\ : label is "soft_lutpair827";
  attribute SOFT_HLUTNM of \col_lcl[10]__0_i_17\ : label is "soft_lutpair777";
  attribute SOFT_HLUTNM of \col_lcl[10]__0_i_4\ : label is "soft_lutpair827";
  attribute SOFT_HLUTNM of \col_lcl[10]__0_i_8\ : label is "soft_lutpair863";
  attribute SOFT_HLUTNM of \col_lcl[10]_i_2\ : label is "soft_lutpair946";
  attribute SOFT_HLUTNM of \col_lcl[10]_i_5\ : label is "soft_lutpair797";
  attribute SOFT_HLUTNM of \col_lcl[1]_i_1\ : label is "soft_lutpair945";
  attribute SOFT_HLUTNM of \col_lcl[2]_i_1\ : label is "soft_lutpair796";
  attribute SOFT_HLUTNM of \col_lcl[3]_i_1\ : label is "soft_lutpair796";
  attribute SOFT_HLUTNM of \col_lcl[4]__0_i_2\ : label is "soft_lutpair781";
  attribute SOFT_HLUTNM of \col_lcl[5]__0_i_2\ : label is "soft_lutpair781";
  attribute SOFT_HLUTNM of \col_lcl[5]_i_1\ : label is "soft_lutpair945";
  attribute SOFT_HLUTNM of \col_lcl[6]_i_1\ : label is "soft_lutpair946";
  attribute SOFT_HLUTNM of \col_lcl[7]_i_1\ : label is "soft_lutpair785";
  attribute SOFT_HLUTNM of \col_lcl[8]__0_i_2\ : label is "soft_lutpair786";
  attribute SOFT_HLUTNM of \col_lcl[8]__0_i_3\ : label is "soft_lutpair789";
  attribute SOFT_HLUTNM of \col_lcl[8]_i_1__0\ : label is "soft_lutpair785";
  attribute SOFT_HLUTNM of \col_lcl[9]__0_i_2\ : label is "soft_lutpair863";
  attribute SOFT_HLUTNM of \colsumX4p1[0]_i_1\ : label is "soft_lutpair1122";
  attribute SOFT_HLUTNM of \colsumX4p1[10]_i_1\ : label is "soft_lutpair1117";
  attribute SOFT_HLUTNM of \colsumX4p1[11]_i_1\ : label is "soft_lutpair1117";
  attribute SOFT_HLUTNM of \colsumX4p1[12]_i_1\ : label is "soft_lutpair1116";
  attribute SOFT_HLUTNM of \colsumX4p1[13]_i_1\ : label is "soft_lutpair1116";
  attribute SOFT_HLUTNM of \colsumX4p1[14]_i_1\ : label is "soft_lutpair1115";
  attribute SOFT_HLUTNM of \colsumX4p1[15]_i_1\ : label is "soft_lutpair1115";
  attribute SOFT_HLUTNM of \colsumX4p1[16]_i_1\ : label is "soft_lutpair1114";
  attribute SOFT_HLUTNM of \colsumX4p1[17]_i_1\ : label is "soft_lutpair1113";
  attribute SOFT_HLUTNM of \colsumX4p1[18]_i_1\ : label is "soft_lutpair1113";
  attribute SOFT_HLUTNM of \colsumX4p1[19]_i_1\ : label is "soft_lutpair1112";
  attribute SOFT_HLUTNM of \colsumX4p1[1]_i_1\ : label is "soft_lutpair1122";
  attribute SOFT_HLUTNM of \colsumX4p1[20]_i_1\ : label is "soft_lutpair1112";
  attribute SOFT_HLUTNM of \colsumX4p1[2]_i_1\ : label is "soft_lutpair1121";
  attribute SOFT_HLUTNM of \colsumX4p1[3]_i_1\ : label is "soft_lutpair1121";
  attribute SOFT_HLUTNM of \colsumX4p1[4]_i_1\ : label is "soft_lutpair1120";
  attribute SOFT_HLUTNM of \colsumX4p1[5]_i_1\ : label is "soft_lutpair1120";
  attribute SOFT_HLUTNM of \colsumX4p1[6]_i_1\ : label is "soft_lutpair1119";
  attribute SOFT_HLUTNM of \colsumX4p1[7]_i_1\ : label is "soft_lutpair1119";
  attribute SOFT_HLUTNM of \colsumX4p1[8]_i_1\ : label is "soft_lutpair1118";
  attribute SOFT_HLUTNM of \colsumX4p1[9]_i_1\ : label is "soft_lutpair1118";
  attribute SOFT_HLUTNM of \colsumX4p2[0]_i_1\ : label is "soft_lutpair1132";
  attribute SOFT_HLUTNM of \colsumX4p2[10]_i_1\ : label is "soft_lutpair1127";
  attribute SOFT_HLUTNM of \colsumX4p2[11]_i_1\ : label is "soft_lutpair1127";
  attribute SOFT_HLUTNM of \colsumX4p2[12]_i_1\ : label is "soft_lutpair1126";
  attribute SOFT_HLUTNM of \colsumX4p2[13]_i_1\ : label is "soft_lutpair1126";
  attribute SOFT_HLUTNM of \colsumX4p2[14]_i_1\ : label is "soft_lutpair1125";
  attribute SOFT_HLUTNM of \colsumX4p2[15]_i_1\ : label is "soft_lutpair1125";
  attribute SOFT_HLUTNM of \colsumX4p2[16]_i_1\ : label is "soft_lutpair1124";
  attribute SOFT_HLUTNM of \colsumX4p2[17]_i_1\ : label is "soft_lutpair1124";
  attribute SOFT_HLUTNM of \colsumX4p2[18]_i_1\ : label is "soft_lutpair1123";
  attribute SOFT_HLUTNM of \colsumX4p2[19]_i_1\ : label is "soft_lutpair1123";
  attribute SOFT_HLUTNM of \colsumX4p2[1]_i_1\ : label is "soft_lutpair1132";
  attribute SOFT_HLUTNM of \colsumX4p2[20]_i_1\ : label is "soft_lutpair1114";
  attribute SOFT_HLUTNM of \colsumX4p2[2]_i_1\ : label is "soft_lutpair1131";
  attribute SOFT_HLUTNM of \colsumX4p2[3]_i_1\ : label is "soft_lutpair1131";
  attribute SOFT_HLUTNM of \colsumX4p2[4]_i_1\ : label is "soft_lutpair1130";
  attribute SOFT_HLUTNM of \colsumX4p2[5]_i_1\ : label is "soft_lutpair1130";
  attribute SOFT_HLUTNM of \colsumX4p2[6]_i_1\ : label is "soft_lutpair1129";
  attribute SOFT_HLUTNM of \colsumX4p2[7]_i_1\ : label is "soft_lutpair1129";
  attribute SOFT_HLUTNM of \colsumX4p2[8]_i_1\ : label is "soft_lutpair1128";
  attribute SOFT_HLUTNM of \colsumX4p2[9]_i_1\ : label is "soft_lutpair1128";
  attribute SOFT_HLUTNM of \colsumXA[0]_i_1\ : label is "soft_lutpair936";
  attribute SOFT_HLUTNM of \colsumXA[10]_i_1\ : label is "soft_lutpair1068";
  attribute SOFT_HLUTNM of \colsumXA[11]_i_1\ : label is "soft_lutpair1068";
  attribute SOFT_HLUTNM of \colsumXA[12]_i_1\ : label is "soft_lutpair1067";
  attribute SOFT_HLUTNM of \colsumXA[13]_i_1\ : label is "soft_lutpair1067";
  attribute SOFT_HLUTNM of \colsumXA[14]_i_1\ : label is "soft_lutpair1066";
  attribute SOFT_HLUTNM of \colsumXA[15]_i_1\ : label is "soft_lutpair1066";
  attribute SOFT_HLUTNM of \colsumXA[16]_i_1\ : label is "soft_lutpair1065";
  attribute SOFT_HLUTNM of \colsumXA[17]_i_1\ : label is "soft_lutpair1065";
  attribute SOFT_HLUTNM of \colsumXA[18]_i_1\ : label is "soft_lutpair1057";
  attribute SOFT_HLUTNM of \colsumXA[19]_i_1\ : label is "soft_lutpair937";
  attribute SOFT_HLUTNM of \colsumXA[1]_i_1\ : label is "soft_lutpair936";
  attribute SOFT_HLUTNM of \colsumXA[20]_i_1\ : label is "soft_lutpair937";
  attribute SOFT_HLUTNM of \colsumXA[21]_i_1\ : label is "soft_lutpair1064";
  attribute SOFT_HLUTNM of \colsumXA[22]_i_1\ : label is "soft_lutpair1064";
  attribute SOFT_HLUTNM of \colsumXA[23]_i_1\ : label is "soft_lutpair1063";
  attribute SOFT_HLUTNM of \colsumXA[24]_i_1\ : label is "soft_lutpair1063";
  attribute SOFT_HLUTNM of \colsumXA[25]_i_1\ : label is "soft_lutpair1062";
  attribute SOFT_HLUTNM of \colsumXA[26]_i_1\ : label is "soft_lutpair1062";
  attribute SOFT_HLUTNM of \colsumXA[27]_i_1\ : label is "soft_lutpair1061";
  attribute SOFT_HLUTNM of \colsumXA[28]_i_1\ : label is "soft_lutpair1061";
  attribute SOFT_HLUTNM of \colsumXA[29]_i_1\ : label is "soft_lutpair1060";
  attribute SOFT_HLUTNM of \colsumXA[2]_i_1\ : label is "soft_lutpair1072";
  attribute SOFT_HLUTNM of \colsumXA[30]_i_1\ : label is "soft_lutpair1060";
  attribute SOFT_HLUTNM of \colsumXA[31]_i_1\ : label is "soft_lutpair1059";
  attribute SOFT_HLUTNM of \colsumXA[32]_i_1\ : label is "soft_lutpair1059";
  attribute SOFT_HLUTNM of \colsumXA[33]_i_1\ : label is "soft_lutpair1058";
  attribute SOFT_HLUTNM of \colsumXA[34]_i_1\ : label is "soft_lutpair1058";
  attribute SOFT_HLUTNM of \colsumXA[35]_i_1\ : label is "soft_lutpair1057";
  attribute SOFT_HLUTNM of \colsumXA[36]_i_1\ : label is "soft_lutpair1056";
  attribute SOFT_HLUTNM of \colsumXA[37]_i_1\ : label is "soft_lutpair1056";
  attribute SOFT_HLUTNM of \colsumXA[3]_i_1\ : label is "soft_lutpair1072";
  attribute SOFT_HLUTNM of \colsumXA[4]_i_1\ : label is "soft_lutpair1071";
  attribute SOFT_HLUTNM of \colsumXA[5]_i_1\ : label is "soft_lutpair1071";
  attribute SOFT_HLUTNM of \colsumXA[6]_i_1\ : label is "soft_lutpair1070";
  attribute SOFT_HLUTNM of \colsumXA[7]_i_1\ : label is "soft_lutpair1070";
  attribute SOFT_HLUTNM of \colsumXA[8]_i_1\ : label is "soft_lutpair1069";
  attribute SOFT_HLUTNM of \colsumXA[9]_i_1\ : label is "soft_lutpair1069";
  attribute SOFT_HLUTNM of \colsumXY4p1[0]_i_1\ : label is "soft_lutpair1383";
  attribute SOFT_HLUTNM of \colsumXY4p1[10]_i_1\ : label is "soft_lutpair1378";
  attribute SOFT_HLUTNM of \colsumXY4p1[11]_i_1\ : label is "soft_lutpair1378";
  attribute SOFT_HLUTNM of \colsumXY4p1[12]_i_1\ : label is "soft_lutpair1377";
  attribute SOFT_HLUTNM of \colsumXY4p1[13]_i_1\ : label is "soft_lutpair1377";
  attribute SOFT_HLUTNM of \colsumXY4p1[14]_i_1\ : label is "soft_lutpair1376";
  attribute SOFT_HLUTNM of \colsumXY4p1[15]_i_1\ : label is "soft_lutpair1376";
  attribute SOFT_HLUTNM of \colsumXY4p1[16]_i_1\ : label is "soft_lutpair1375";
  attribute SOFT_HLUTNM of \colsumXY4p1[17]_i_1\ : label is "soft_lutpair1374";
  attribute SOFT_HLUTNM of \colsumXY4p1[18]_i_1\ : label is "soft_lutpair1374";
  attribute SOFT_HLUTNM of \colsumXY4p1[19]_i_1\ : label is "soft_lutpair1373";
  attribute SOFT_HLUTNM of \colsumXY4p1[1]_i_1\ : label is "soft_lutpair1383";
  attribute SOFT_HLUTNM of \colsumXY4p1[20]_i_1\ : label is "soft_lutpair1373";
  attribute SOFT_HLUTNM of \colsumXY4p1[2]_i_1\ : label is "soft_lutpair1382";
  attribute SOFT_HLUTNM of \colsumXY4p1[3]_i_1\ : label is "soft_lutpair1382";
  attribute SOFT_HLUTNM of \colsumXY4p1[4]_i_1\ : label is "soft_lutpair1381";
  attribute SOFT_HLUTNM of \colsumXY4p1[5]_i_1\ : label is "soft_lutpair1381";
  attribute SOFT_HLUTNM of \colsumXY4p1[6]_i_1\ : label is "soft_lutpair1380";
  attribute SOFT_HLUTNM of \colsumXY4p1[7]_i_1\ : label is "soft_lutpair1380";
  attribute SOFT_HLUTNM of \colsumXY4p1[8]_i_1\ : label is "soft_lutpair1379";
  attribute SOFT_HLUTNM of \colsumXY4p1[9]_i_1\ : label is "soft_lutpair1379";
  attribute SOFT_HLUTNM of \colsumXY4p2[0]_i_1\ : label is "soft_lutpair1393";
  attribute SOFT_HLUTNM of \colsumXY4p2[10]_i_1\ : label is "soft_lutpair1388";
  attribute SOFT_HLUTNM of \colsumXY4p2[11]_i_1\ : label is "soft_lutpair1388";
  attribute SOFT_HLUTNM of \colsumXY4p2[12]_i_1\ : label is "soft_lutpair1387";
  attribute SOFT_HLUTNM of \colsumXY4p2[13]_i_1\ : label is "soft_lutpair1387";
  attribute SOFT_HLUTNM of \colsumXY4p2[14]_i_1\ : label is "soft_lutpair1386";
  attribute SOFT_HLUTNM of \colsumXY4p2[15]_i_1\ : label is "soft_lutpair1386";
  attribute SOFT_HLUTNM of \colsumXY4p2[16]_i_1\ : label is "soft_lutpair1385";
  attribute SOFT_HLUTNM of \colsumXY4p2[17]_i_1\ : label is "soft_lutpair1385";
  attribute SOFT_HLUTNM of \colsumXY4p2[18]_i_1\ : label is "soft_lutpair1384";
  attribute SOFT_HLUTNM of \colsumXY4p2[19]_i_1\ : label is "soft_lutpair1384";
  attribute SOFT_HLUTNM of \colsumXY4p2[1]_i_1\ : label is "soft_lutpair1393";
  attribute SOFT_HLUTNM of \colsumXY4p2[20]_i_1\ : label is "soft_lutpair1375";
  attribute SOFT_HLUTNM of \colsumXY4p2[2]_i_1\ : label is "soft_lutpair1392";
  attribute SOFT_HLUTNM of \colsumXY4p2[3]_i_1\ : label is "soft_lutpair1392";
  attribute SOFT_HLUTNM of \colsumXY4p2[4]_i_1\ : label is "soft_lutpair1391";
  attribute SOFT_HLUTNM of \colsumXY4p2[5]_i_1\ : label is "soft_lutpair1391";
  attribute SOFT_HLUTNM of \colsumXY4p2[6]_i_1\ : label is "soft_lutpair1390";
  attribute SOFT_HLUTNM of \colsumXY4p2[7]_i_1\ : label is "soft_lutpair1390";
  attribute SOFT_HLUTNM of \colsumXY4p2[8]_i_1\ : label is "soft_lutpair1389";
  attribute SOFT_HLUTNM of \colsumXY4p2[9]_i_1\ : label is "soft_lutpair1389";
  attribute SOFT_HLUTNM of \colsumXYA[0]_i_1\ : label is "soft_lutpair1332";
  attribute SOFT_HLUTNM of \colsumXYA[10]_i_1\ : label is "soft_lutpair1327";
  attribute SOFT_HLUTNM of \colsumXYA[11]_i_1\ : label is "soft_lutpair1327";
  attribute SOFT_HLUTNM of \colsumXYA[12]_i_1\ : label is "soft_lutpair1326";
  attribute SOFT_HLUTNM of \colsumXYA[13]_i_1\ : label is "soft_lutpair1326";
  attribute SOFT_HLUTNM of \colsumXYA[14]_i_1\ : label is "soft_lutpair1325";
  attribute SOFT_HLUTNM of \colsumXYA[15]_i_1\ : label is "soft_lutpair1325";
  attribute SOFT_HLUTNM of \colsumXYA[16]_i_1\ : label is "soft_lutpair1324";
  attribute SOFT_HLUTNM of \colsumXYA[17]_i_1\ : label is "soft_lutpair1324";
  attribute SOFT_HLUTNM of \colsumXYA[18]_i_1\ : label is "soft_lutpair1315";
  attribute SOFT_HLUTNM of \colsumXYA[19]_i_1\ : label is "soft_lutpair1323";
  attribute SOFT_HLUTNM of \colsumXYA[1]_i_1\ : label is "soft_lutpair1332";
  attribute SOFT_HLUTNM of \colsumXYA[20]_i_1\ : label is "soft_lutpair1323";
  attribute SOFT_HLUTNM of \colsumXYA[21]_i_1\ : label is "soft_lutpair1322";
  attribute SOFT_HLUTNM of \colsumXYA[22]_i_1\ : label is "soft_lutpair1322";
  attribute SOFT_HLUTNM of \colsumXYA[23]_i_1\ : label is "soft_lutpair1321";
  attribute SOFT_HLUTNM of \colsumXYA[24]_i_1\ : label is "soft_lutpair1321";
  attribute SOFT_HLUTNM of \colsumXYA[25]_i_1\ : label is "soft_lutpair1320";
  attribute SOFT_HLUTNM of \colsumXYA[26]_i_1\ : label is "soft_lutpair1320";
  attribute SOFT_HLUTNM of \colsumXYA[27]_i_1\ : label is "soft_lutpair1319";
  attribute SOFT_HLUTNM of \colsumXYA[28]_i_1\ : label is "soft_lutpair1319";
  attribute SOFT_HLUTNM of \colsumXYA[29]_i_1\ : label is "soft_lutpair1318";
  attribute SOFT_HLUTNM of \colsumXYA[2]_i_1\ : label is "soft_lutpair1331";
  attribute SOFT_HLUTNM of \colsumXYA[30]_i_1\ : label is "soft_lutpair1318";
  attribute SOFT_HLUTNM of \colsumXYA[31]_i_1\ : label is "soft_lutpair1317";
  attribute SOFT_HLUTNM of \colsumXYA[32]_i_1\ : label is "soft_lutpair1317";
  attribute SOFT_HLUTNM of \colsumXYA[33]_i_1\ : label is "soft_lutpair1316";
  attribute SOFT_HLUTNM of \colsumXYA[34]_i_1\ : label is "soft_lutpair1316";
  attribute SOFT_HLUTNM of \colsumXYA[35]_i_1\ : label is "soft_lutpair1315";
  attribute SOFT_HLUTNM of \colsumXYA[36]_i_1\ : label is "soft_lutpair1314";
  attribute SOFT_HLUTNM of \colsumXYA[37]_i_1\ : label is "soft_lutpair1314";
  attribute SOFT_HLUTNM of \colsumXYA[3]_i_1\ : label is "soft_lutpair1331";
  attribute SOFT_HLUTNM of \colsumXYA[4]_i_1\ : label is "soft_lutpair1330";
  attribute SOFT_HLUTNM of \colsumXYA[5]_i_1\ : label is "soft_lutpair1330";
  attribute SOFT_HLUTNM of \colsumXYA[6]_i_1\ : label is "soft_lutpair1329";
  attribute SOFT_HLUTNM of \colsumXYA[7]_i_1\ : label is "soft_lutpair1329";
  attribute SOFT_HLUTNM of \colsumXYA[8]_i_1\ : label is "soft_lutpair1328";
  attribute SOFT_HLUTNM of \colsumXYA[9]_i_1\ : label is "soft_lutpair1328";
  attribute SOFT_HLUTNM of \colsumXY[100]_i_1\ : label is "soft_lutpair919";
  attribute SOFT_HLUTNM of \colsumXY[101]_i_1\ : label is "soft_lutpair918";
  attribute SOFT_HLUTNM of \colsumXY[102]_i_1\ : label is "soft_lutpair917";
  attribute SOFT_HLUTNM of \colsumXY[103]_i_1\ : label is "soft_lutpair916";
  attribute SOFT_HLUTNM of \colsumXY[104]_i_1\ : label is "soft_lutpair915";
  attribute SOFT_HLUTNM of \colsumXY[21]_i_1\ : label is "soft_lutpair935";
  attribute SOFT_HLUTNM of \colsumXY[22]_i_1\ : label is "soft_lutpair934";
  attribute SOFT_HLUTNM of \colsumXY[23]_i_1\ : label is "soft_lutpair933";
  attribute SOFT_HLUTNM of \colsumXY[24]_i_1\ : label is "soft_lutpair932";
  attribute SOFT_HLUTNM of \colsumXY[25]_i_1\ : label is "soft_lutpair931";
  attribute SOFT_HLUTNM of \colsumXY[26]_i_1\ : label is "soft_lutpair930";
  attribute SOFT_HLUTNM of \colsumXY[27]_i_1\ : label is "soft_lutpair929";
  attribute SOFT_HLUTNM of \colsumXY[28]_i_1\ : label is "soft_lutpair928";
  attribute SOFT_HLUTNM of \colsumXY[29]_i_1\ : label is "soft_lutpair927";
  attribute SOFT_HLUTNM of \colsumXY[30]_i_1\ : label is "soft_lutpair926";
  attribute SOFT_HLUTNM of \colsumXY[31]_i_1\ : label is "soft_lutpair925";
  attribute SOFT_HLUTNM of \colsumXY[32]_i_1\ : label is "soft_lutpair924";
  attribute SOFT_HLUTNM of \colsumXY[33]_i_1\ : label is "soft_lutpair923";
  attribute SOFT_HLUTNM of \colsumXY[34]_i_1\ : label is "soft_lutpair922";
  attribute SOFT_HLUTNM of \colsumXY[35]_i_1\ : label is "soft_lutpair921";
  attribute SOFT_HLUTNM of \colsumXY[36]_i_1\ : label is "soft_lutpair920";
  attribute SOFT_HLUTNM of \colsumXY[37]_i_1\ : label is "soft_lutpair919";
  attribute SOFT_HLUTNM of \colsumXY[38]_i_1\ : label is "soft_lutpair918";
  attribute SOFT_HLUTNM of \colsumXY[39]_i_1\ : label is "soft_lutpair917";
  attribute SOFT_HLUTNM of \colsumXY[40]_i_1\ : label is "soft_lutpair916";
  attribute SOFT_HLUTNM of \colsumXY[41]_i_1\ : label is "soft_lutpair915";
  attribute SOFT_HLUTNM of \colsumXY[84]_i_1\ : label is "soft_lutpair935";
  attribute SOFT_HLUTNM of \colsumXY[85]_i_1\ : label is "soft_lutpair934";
  attribute SOFT_HLUTNM of \colsumXY[86]_i_1\ : label is "soft_lutpair933";
  attribute SOFT_HLUTNM of \colsumXY[87]_i_1\ : label is "soft_lutpair932";
  attribute SOFT_HLUTNM of \colsumXY[88]_i_1\ : label is "soft_lutpair931";
  attribute SOFT_HLUTNM of \colsumXY[89]_i_1\ : label is "soft_lutpair930";
  attribute SOFT_HLUTNM of \colsumXY[90]_i_1\ : label is "soft_lutpair929";
  attribute SOFT_HLUTNM of \colsumXY[91]_i_1\ : label is "soft_lutpair928";
  attribute SOFT_HLUTNM of \colsumXY[92]_i_1\ : label is "soft_lutpair927";
  attribute SOFT_HLUTNM of \colsumXY[93]_i_1\ : label is "soft_lutpair926";
  attribute SOFT_HLUTNM of \colsumXY[94]_i_1\ : label is "soft_lutpair925";
  attribute SOFT_HLUTNM of \colsumXY[95]_i_1\ : label is "soft_lutpair924";
  attribute SOFT_HLUTNM of \colsumXY[96]_i_1\ : label is "soft_lutpair923";
  attribute SOFT_HLUTNM of \colsumXY[97]_i_1\ : label is "soft_lutpair922";
  attribute SOFT_HLUTNM of \colsumXY[98]_i_1\ : label is "soft_lutpair921";
  attribute SOFT_HLUTNM of \colsumXY[99]_i_1\ : label is "soft_lutpair920";
  attribute SOFT_HLUTNM of \colsumX[100]_i_1\ : label is "soft_lutpair871";
  attribute SOFT_HLUTNM of \colsumX[101]_i_1\ : label is "soft_lutpair870";
  attribute SOFT_HLUTNM of \colsumX[102]_i_1\ : label is "soft_lutpair869";
  attribute SOFT_HLUTNM of \colsumX[103]_i_1\ : label is "soft_lutpair868";
  attribute SOFT_HLUTNM of \colsumX[104]_i_2\ : label is "soft_lutpair867";
  attribute SOFT_HLUTNM of \colsumX[21]_i_1\ : label is "soft_lutpair887";
  attribute SOFT_HLUTNM of \colsumX[22]_i_1\ : label is "soft_lutpair886";
  attribute SOFT_HLUTNM of \colsumX[23]_i_1\ : label is "soft_lutpair885";
  attribute SOFT_HLUTNM of \colsumX[24]_i_1\ : label is "soft_lutpair884";
  attribute SOFT_HLUTNM of \colsumX[25]_i_1\ : label is "soft_lutpair883";
  attribute SOFT_HLUTNM of \colsumX[26]_i_1\ : label is "soft_lutpair882";
  attribute SOFT_HLUTNM of \colsumX[27]_i_1\ : label is "soft_lutpair881";
  attribute SOFT_HLUTNM of \colsumX[28]_i_1\ : label is "soft_lutpair880";
  attribute SOFT_HLUTNM of \colsumX[29]_i_1\ : label is "soft_lutpair879";
  attribute SOFT_HLUTNM of \colsumX[30]_i_1\ : label is "soft_lutpair878";
  attribute SOFT_HLUTNM of \colsumX[31]_i_1\ : label is "soft_lutpair877";
  attribute SOFT_HLUTNM of \colsumX[32]_i_1\ : label is "soft_lutpair876";
  attribute SOFT_HLUTNM of \colsumX[33]_i_1\ : label is "soft_lutpair875";
  attribute SOFT_HLUTNM of \colsumX[34]_i_1\ : label is "soft_lutpair874";
  attribute SOFT_HLUTNM of \colsumX[35]_i_1\ : label is "soft_lutpair873";
  attribute SOFT_HLUTNM of \colsumX[36]_i_1\ : label is "soft_lutpair872";
  attribute SOFT_HLUTNM of \colsumX[37]_i_1\ : label is "soft_lutpair871";
  attribute SOFT_HLUTNM of \colsumX[38]_i_1\ : label is "soft_lutpair870";
  attribute SOFT_HLUTNM of \colsumX[39]_i_1\ : label is "soft_lutpair869";
  attribute SOFT_HLUTNM of \colsumX[40]_i_1\ : label is "soft_lutpair868";
  attribute SOFT_HLUTNM of \colsumX[41]_i_2\ : label is "soft_lutpair867";
  attribute SOFT_HLUTNM of \colsumX[84]_i_1\ : label is "soft_lutpair887";
  attribute SOFT_HLUTNM of \colsumX[85]_i_1\ : label is "soft_lutpair886";
  attribute SOFT_HLUTNM of \colsumX[86]_i_1\ : label is "soft_lutpair885";
  attribute SOFT_HLUTNM of \colsumX[87]_i_1\ : label is "soft_lutpair884";
  attribute SOFT_HLUTNM of \colsumX[88]_i_1\ : label is "soft_lutpair883";
  attribute SOFT_HLUTNM of \colsumX[89]_i_1\ : label is "soft_lutpair882";
  attribute SOFT_HLUTNM of \colsumX[90]_i_1\ : label is "soft_lutpair881";
  attribute SOFT_HLUTNM of \colsumX[91]_i_1\ : label is "soft_lutpair880";
  attribute SOFT_HLUTNM of \colsumX[92]_i_1\ : label is "soft_lutpair879";
  attribute SOFT_HLUTNM of \colsumX[93]_i_1\ : label is "soft_lutpair878";
  attribute SOFT_HLUTNM of \colsumX[94]_i_1\ : label is "soft_lutpair877";
  attribute SOFT_HLUTNM of \colsumX[95]_i_1\ : label is "soft_lutpair876";
  attribute SOFT_HLUTNM of \colsumX[96]_i_1\ : label is "soft_lutpair875";
  attribute SOFT_HLUTNM of \colsumX[97]_i_1\ : label is "soft_lutpair874";
  attribute SOFT_HLUTNM of \colsumX[98]_i_1\ : label is "soft_lutpair873";
  attribute SOFT_HLUTNM of \colsumX[99]_i_1\ : label is "soft_lutpair872";
  attribute SOFT_HLUTNM of \colsumY4p1[0]_i_1\ : label is "soft_lutpair1238";
  attribute SOFT_HLUTNM of \colsumY4p1[10]_i_1\ : label is "soft_lutpair1233";
  attribute SOFT_HLUTNM of \colsumY4p1[11]_i_1\ : label is "soft_lutpair1233";
  attribute SOFT_HLUTNM of \colsumY4p1[12]_i_1\ : label is "soft_lutpair1232";
  attribute SOFT_HLUTNM of \colsumY4p1[13]_i_1\ : label is "soft_lutpair1232";
  attribute SOFT_HLUTNM of \colsumY4p1[14]_i_1\ : label is "soft_lutpair1231";
  attribute SOFT_HLUTNM of \colsumY4p1[15]_i_1\ : label is "soft_lutpair1231";
  attribute SOFT_HLUTNM of \colsumY4p1[16]_i_1\ : label is "soft_lutpair1230";
  attribute SOFT_HLUTNM of \colsumY4p1[17]_i_1\ : label is "soft_lutpair1229";
  attribute SOFT_HLUTNM of \colsumY4p1[18]_i_1\ : label is "soft_lutpair1229";
  attribute SOFT_HLUTNM of \colsumY4p1[19]_i_1\ : label is "soft_lutpair1228";
  attribute SOFT_HLUTNM of \colsumY4p1[1]_i_1\ : label is "soft_lutpair1238";
  attribute SOFT_HLUTNM of \colsumY4p1[20]_i_1\ : label is "soft_lutpair1228";
  attribute SOFT_HLUTNM of \colsumY4p1[2]_i_1\ : label is "soft_lutpair1237";
  attribute SOFT_HLUTNM of \colsumY4p1[3]_i_1\ : label is "soft_lutpair1237";
  attribute SOFT_HLUTNM of \colsumY4p1[4]_i_1\ : label is "soft_lutpair1236";
  attribute SOFT_HLUTNM of \colsumY4p1[5]_i_1\ : label is "soft_lutpair1236";
  attribute SOFT_HLUTNM of \colsumY4p1[6]_i_1\ : label is "soft_lutpair1235";
  attribute SOFT_HLUTNM of \colsumY4p1[7]_i_1\ : label is "soft_lutpair1235";
  attribute SOFT_HLUTNM of \colsumY4p1[8]_i_1\ : label is "soft_lutpair1234";
  attribute SOFT_HLUTNM of \colsumY4p1[9]_i_1\ : label is "soft_lutpair1234";
  attribute SOFT_HLUTNM of \colsumY4p2[0]_i_1\ : label is "soft_lutpair1248";
  attribute SOFT_HLUTNM of \colsumY4p2[10]_i_1\ : label is "soft_lutpair1243";
  attribute SOFT_HLUTNM of \colsumY4p2[11]_i_1\ : label is "soft_lutpair1243";
  attribute SOFT_HLUTNM of \colsumY4p2[12]_i_1\ : label is "soft_lutpair1242";
  attribute SOFT_HLUTNM of \colsumY4p2[13]_i_1\ : label is "soft_lutpair1242";
  attribute SOFT_HLUTNM of \colsumY4p2[14]_i_1\ : label is "soft_lutpair1241";
  attribute SOFT_HLUTNM of \colsumY4p2[15]_i_1\ : label is "soft_lutpair1241";
  attribute SOFT_HLUTNM of \colsumY4p2[16]_i_1\ : label is "soft_lutpair1240";
  attribute SOFT_HLUTNM of \colsumY4p2[17]_i_1\ : label is "soft_lutpair1240";
  attribute SOFT_HLUTNM of \colsumY4p2[18]_i_1\ : label is "soft_lutpair1239";
  attribute SOFT_HLUTNM of \colsumY4p2[19]_i_1\ : label is "soft_lutpair1239";
  attribute SOFT_HLUTNM of \colsumY4p2[1]_i_1\ : label is "soft_lutpair1248";
  attribute SOFT_HLUTNM of \colsumY4p2[20]_i_1\ : label is "soft_lutpair1230";
  attribute SOFT_HLUTNM of \colsumY4p2[2]_i_1\ : label is "soft_lutpair1247";
  attribute SOFT_HLUTNM of \colsumY4p2[3]_i_1\ : label is "soft_lutpair1247";
  attribute SOFT_HLUTNM of \colsumY4p2[4]_i_1\ : label is "soft_lutpair1246";
  attribute SOFT_HLUTNM of \colsumY4p2[5]_i_1\ : label is "soft_lutpair1246";
  attribute SOFT_HLUTNM of \colsumY4p2[6]_i_1\ : label is "soft_lutpair1245";
  attribute SOFT_HLUTNM of \colsumY4p2[7]_i_1\ : label is "soft_lutpair1245";
  attribute SOFT_HLUTNM of \colsumY4p2[8]_i_1\ : label is "soft_lutpair1244";
  attribute SOFT_HLUTNM of \colsumY4p2[9]_i_1\ : label is "soft_lutpair1244";
  attribute SOFT_HLUTNM of \colsumYA[0]_i_1\ : label is "soft_lutpair938";
  attribute SOFT_HLUTNM of \colsumYA[10]_i_1\ : label is "soft_lutpair1185";
  attribute SOFT_HLUTNM of \colsumYA[11]_i_1\ : label is "soft_lutpair1185";
  attribute SOFT_HLUTNM of \colsumYA[12]_i_1\ : label is "soft_lutpair1184";
  attribute SOFT_HLUTNM of \colsumYA[13]_i_1\ : label is "soft_lutpair1184";
  attribute SOFT_HLUTNM of \colsumYA[14]_i_1\ : label is "soft_lutpair1183";
  attribute SOFT_HLUTNM of \colsumYA[15]_i_1\ : label is "soft_lutpair1183";
  attribute SOFT_HLUTNM of \colsumYA[16]_i_1\ : label is "soft_lutpair1182";
  attribute SOFT_HLUTNM of \colsumYA[17]_i_1\ : label is "soft_lutpair1182";
  attribute SOFT_HLUTNM of \colsumYA[18]_i_1\ : label is "soft_lutpair1174";
  attribute SOFT_HLUTNM of \colsumYA[19]_i_1\ : label is "soft_lutpair939";
  attribute SOFT_HLUTNM of \colsumYA[1]_i_1\ : label is "soft_lutpair938";
  attribute SOFT_HLUTNM of \colsumYA[20]_i_1\ : label is "soft_lutpair939";
  attribute SOFT_HLUTNM of \colsumYA[21]_i_1\ : label is "soft_lutpair1181";
  attribute SOFT_HLUTNM of \colsumYA[22]_i_1\ : label is "soft_lutpair1181";
  attribute SOFT_HLUTNM of \colsumYA[23]_i_1\ : label is "soft_lutpair1180";
  attribute SOFT_HLUTNM of \colsumYA[24]_i_1\ : label is "soft_lutpair1180";
  attribute SOFT_HLUTNM of \colsumYA[25]_i_1\ : label is "soft_lutpair1179";
  attribute SOFT_HLUTNM of \colsumYA[26]_i_1\ : label is "soft_lutpair1179";
  attribute SOFT_HLUTNM of \colsumYA[27]_i_1\ : label is "soft_lutpair1178";
  attribute SOFT_HLUTNM of \colsumYA[28]_i_1\ : label is "soft_lutpair1178";
  attribute SOFT_HLUTNM of \colsumYA[29]_i_1\ : label is "soft_lutpair1177";
  attribute SOFT_HLUTNM of \colsumYA[2]_i_1\ : label is "soft_lutpair1189";
  attribute SOFT_HLUTNM of \colsumYA[30]_i_1\ : label is "soft_lutpair1177";
  attribute SOFT_HLUTNM of \colsumYA[31]_i_1\ : label is "soft_lutpair1176";
  attribute SOFT_HLUTNM of \colsumYA[32]_i_1\ : label is "soft_lutpair1176";
  attribute SOFT_HLUTNM of \colsumYA[33]_i_1\ : label is "soft_lutpair1175";
  attribute SOFT_HLUTNM of \colsumYA[34]_i_1\ : label is "soft_lutpair1175";
  attribute SOFT_HLUTNM of \colsumYA[35]_i_1\ : label is "soft_lutpair1174";
  attribute SOFT_HLUTNM of \colsumYA[36]_i_1\ : label is "soft_lutpair1173";
  attribute SOFT_HLUTNM of \colsumYA[37]_i_1\ : label is "soft_lutpair1173";
  attribute SOFT_HLUTNM of \colsumYA[3]_i_1\ : label is "soft_lutpair1189";
  attribute SOFT_HLUTNM of \colsumYA[4]_i_1\ : label is "soft_lutpair1188";
  attribute SOFT_HLUTNM of \colsumYA[5]_i_1\ : label is "soft_lutpair1188";
  attribute SOFT_HLUTNM of \colsumYA[6]_i_1\ : label is "soft_lutpair1187";
  attribute SOFT_HLUTNM of \colsumYA[7]_i_1\ : label is "soft_lutpair1187";
  attribute SOFT_HLUTNM of \colsumYA[8]_i_1\ : label is "soft_lutpair1186";
  attribute SOFT_HLUTNM of \colsumYA[9]_i_1\ : label is "soft_lutpair1186";
  attribute SOFT_HLUTNM of \colsumY[100]_i_1\ : label is "soft_lutpair895";
  attribute SOFT_HLUTNM of \colsumY[101]_i_1\ : label is "soft_lutpair894";
  attribute SOFT_HLUTNM of \colsumY[102]_i_1\ : label is "soft_lutpair893";
  attribute SOFT_HLUTNM of \colsumY[103]_i_1\ : label is "soft_lutpair892";
  attribute SOFT_HLUTNM of \colsumY[104]_i_1\ : label is "soft_lutpair891";
  attribute SOFT_HLUTNM of \colsumY[21]_i_1\ : label is "soft_lutpair911";
  attribute SOFT_HLUTNM of \colsumY[22]_i_1\ : label is "soft_lutpair910";
  attribute SOFT_HLUTNM of \colsumY[23]_i_1\ : label is "soft_lutpair909";
  attribute SOFT_HLUTNM of \colsumY[24]_i_1\ : label is "soft_lutpair908";
  attribute SOFT_HLUTNM of \colsumY[25]_i_1\ : label is "soft_lutpair907";
  attribute SOFT_HLUTNM of \colsumY[26]_i_1\ : label is "soft_lutpair906";
  attribute SOFT_HLUTNM of \colsumY[27]_i_1\ : label is "soft_lutpair905";
  attribute SOFT_HLUTNM of \colsumY[28]_i_1\ : label is "soft_lutpair904";
  attribute SOFT_HLUTNM of \colsumY[29]_i_1\ : label is "soft_lutpair903";
  attribute SOFT_HLUTNM of \colsumY[30]_i_1\ : label is "soft_lutpair902";
  attribute SOFT_HLUTNM of \colsumY[31]_i_1\ : label is "soft_lutpair901";
  attribute SOFT_HLUTNM of \colsumY[32]_i_1\ : label is "soft_lutpair900";
  attribute SOFT_HLUTNM of \colsumY[33]_i_1\ : label is "soft_lutpair899";
  attribute SOFT_HLUTNM of \colsumY[34]_i_1\ : label is "soft_lutpair898";
  attribute SOFT_HLUTNM of \colsumY[35]_i_1\ : label is "soft_lutpair897";
  attribute SOFT_HLUTNM of \colsumY[36]_i_1\ : label is "soft_lutpair896";
  attribute SOFT_HLUTNM of \colsumY[37]_i_1\ : label is "soft_lutpair895";
  attribute SOFT_HLUTNM of \colsumY[38]_i_1\ : label is "soft_lutpair894";
  attribute SOFT_HLUTNM of \colsumY[39]_i_1\ : label is "soft_lutpair893";
  attribute SOFT_HLUTNM of \colsumY[40]_i_1\ : label is "soft_lutpair892";
  attribute SOFT_HLUTNM of \colsumY[41]_i_1\ : label is "soft_lutpair891";
  attribute SOFT_HLUTNM of \colsumY[84]_i_1\ : label is "soft_lutpair911";
  attribute SOFT_HLUTNM of \colsumY[85]_i_1\ : label is "soft_lutpair910";
  attribute SOFT_HLUTNM of \colsumY[86]_i_1\ : label is "soft_lutpair909";
  attribute SOFT_HLUTNM of \colsumY[87]_i_1\ : label is "soft_lutpair908";
  attribute SOFT_HLUTNM of \colsumY[88]_i_1\ : label is "soft_lutpair907";
  attribute SOFT_HLUTNM of \colsumY[89]_i_1\ : label is "soft_lutpair906";
  attribute SOFT_HLUTNM of \colsumY[90]_i_1\ : label is "soft_lutpair905";
  attribute SOFT_HLUTNM of \colsumY[91]_i_1\ : label is "soft_lutpair904";
  attribute SOFT_HLUTNM of \colsumY[92]_i_1\ : label is "soft_lutpair903";
  attribute SOFT_HLUTNM of \colsumY[93]_i_1\ : label is "soft_lutpair902";
  attribute SOFT_HLUTNM of \colsumY[94]_i_1\ : label is "soft_lutpair901";
  attribute SOFT_HLUTNM of \colsumY[95]_i_1\ : label is "soft_lutpair900";
  attribute SOFT_HLUTNM of \colsumY[96]_i_1\ : label is "soft_lutpair899";
  attribute SOFT_HLUTNM of \colsumY[97]_i_1\ : label is "soft_lutpair898";
  attribute SOFT_HLUTNM of \colsumY[98]_i_1\ : label is "soft_lutpair897";
  attribute SOFT_HLUTNM of \colsumY[99]_i_1\ : label is "soft_lutpair896";
  attribute SOFT_HLUTNM of \dIgrm1[0]_i_1\ : label is "soft_lutpair940";
  attribute SOFT_HLUTNM of \dIgrm1[10]_i_1\ : label is "soft_lutpair842";
  attribute SOFT_HLUTNM of \dIgrm1[11]_i_1\ : label is "soft_lutpair843";
  attribute SOFT_HLUTNM of \dIgrm1[12]_i_1\ : label is "soft_lutpair955";
  attribute SOFT_HLUTNM of \dIgrm1[13]_i_1\ : label is "soft_lutpair844";
  attribute SOFT_HLUTNM of \dIgrm1[14]_i_1\ : label is "soft_lutpair956";
  attribute SOFT_HLUTNM of \dIgrm1[15]_i_1\ : label is "soft_lutpair956";
  attribute SOFT_HLUTNM of \dIgrm1[16]_i_1\ : label is "soft_lutpair942";
  attribute SOFT_HLUTNM of \dIgrm1[17]_i_1\ : label is "soft_lutpair957";
  attribute SOFT_HLUTNM of \dIgrm1[18]_i_1\ : label is "soft_lutpair845";
  attribute SOFT_HLUTNM of \dIgrm1[19]_i_1\ : label is "soft_lutpair846";
  attribute SOFT_HLUTNM of \dIgrm1[1]_i_1\ : label is "soft_lutpair953";
  attribute SOFT_HLUTNM of \dIgrm1[20]_i_1\ : label is "soft_lutpair957";
  attribute SOFT_HLUTNM of \dIgrm1[21]_i_1\ : label is "soft_lutpair847";
  attribute SOFT_HLUTNM of \dIgrm1[22]_i_1\ : label is "soft_lutpair958";
  attribute SOFT_HLUTNM of \dIgrm1[23]_i_1\ : label is "soft_lutpair958";
  attribute SOFT_HLUTNM of \dIgrm1[24]_i_1\ : label is "soft_lutpair943";
  attribute SOFT_HLUTNM of \dIgrm1[25]_i_1\ : label is "soft_lutpair959";
  attribute SOFT_HLUTNM of \dIgrm1[26]_i_1\ : label is "soft_lutpair848";
  attribute SOFT_HLUTNM of \dIgrm1[27]_i_1\ : label is "soft_lutpair849";
  attribute SOFT_HLUTNM of \dIgrm1[28]_i_1\ : label is "soft_lutpair959";
  attribute SOFT_HLUTNM of \dIgrm1[29]_i_1\ : label is "soft_lutpair850";
  attribute SOFT_HLUTNM of \dIgrm1[2]_i_1\ : label is "soft_lutpair839";
  attribute SOFT_HLUTNM of \dIgrm1[30]_i_1\ : label is "soft_lutpair960";
  attribute SOFT_HLUTNM of \dIgrm1[31]_i_1\ : label is "soft_lutpair960";
  attribute SOFT_HLUTNM of \dIgrm1[32]_i_1\ : label is "soft_lutpair944";
  attribute SOFT_HLUTNM of \dIgrm1[33]_i_1\ : label is "soft_lutpair961";
  attribute SOFT_HLUTNM of \dIgrm1[34]_i_1\ : label is "soft_lutpair851";
  attribute SOFT_HLUTNM of \dIgrm1[35]_i_1\ : label is "soft_lutpair852";
  attribute SOFT_HLUTNM of \dIgrm1[36]_i_1\ : label is "soft_lutpair961";
  attribute SOFT_HLUTNM of \dIgrm1[37]_i_1\ : label is "soft_lutpair853";
  attribute SOFT_HLUTNM of \dIgrm1[38]_i_1\ : label is "soft_lutpair962";
  attribute SOFT_HLUTNM of \dIgrm1[39]_i_2\ : label is "soft_lutpair962";
  attribute SOFT_HLUTNM of \dIgrm1[3]_i_1\ : label is "soft_lutpair840";
  attribute SOFT_HLUTNM of \dIgrm1[4]_i_1\ : label is "soft_lutpair953";
  attribute SOFT_HLUTNM of \dIgrm1[5]_i_1\ : label is "soft_lutpair841";
  attribute SOFT_HLUTNM of \dIgrm1[6]_i_1\ : label is "soft_lutpair954";
  attribute SOFT_HLUTNM of \dIgrm1[7]_i_1\ : label is "soft_lutpair954";
  attribute SOFT_HLUTNM of \dIgrm1[8]_i_1\ : label is "soft_lutpair941";
  attribute SOFT_HLUTNM of \dIgrm1[9]_i_1\ : label is "soft_lutpair955";
  attribute SOFT_HLUTNM of \dImd[39]_i_5\ : label is "soft_lutpair855";
  attribute SOFT_HLUTNM of \diffI_IIp1[0]_i_1\ : label is "soft_lutpair1440";
  attribute SOFT_HLUTNM of \diffI_IIp1[10]_i_1\ : label is "soft_lutpair1435";
  attribute SOFT_HLUTNM of \diffI_IIp1[11]_i_1\ : label is "soft_lutpair1435";
  attribute SOFT_HLUTNM of \diffI_IIp1[12]_i_1\ : label is "soft_lutpair1434";
  attribute SOFT_HLUTNM of \diffI_IIp1[13]_i_1\ : label is "soft_lutpair1434";
  attribute SOFT_HLUTNM of \diffI_IIp1[14]_i_1\ : label is "soft_lutpair1433";
  attribute SOFT_HLUTNM of \diffI_IIp1[15]_i_1\ : label is "soft_lutpair1433";
  attribute SOFT_HLUTNM of \diffI_IIp1[16]_i_1\ : label is "soft_lutpair1432";
  attribute SOFT_HLUTNM of \diffI_IIp1[17]_i_1\ : label is "soft_lutpair1432";
  attribute SOFT_HLUTNM of \diffI_IIp1[18]_i_1\ : label is "soft_lutpair1431";
  attribute SOFT_HLUTNM of \diffI_IIp1[19]_i_1\ : label is "soft_lutpair1431";
  attribute SOFT_HLUTNM of \diffI_IIp1[1]_i_1\ : label is "soft_lutpair1440";
  attribute SOFT_HLUTNM of \diffI_IIp1[20]_i_1\ : label is "soft_lutpair1430";
  attribute SOFT_HLUTNM of \diffI_IIp1[21]_i_1\ : label is "soft_lutpair1430";
  attribute SOFT_HLUTNM of \diffI_IIp1[22]_i_1\ : label is "soft_lutpair1429";
  attribute SOFT_HLUTNM of \diffI_IIp1[23]_i_1\ : label is "soft_lutpair1429";
  attribute SOFT_HLUTNM of \diffI_IIp1[24]_i_1\ : label is "soft_lutpair1428";
  attribute SOFT_HLUTNM of \diffI_IIp1[25]_i_1\ : label is "soft_lutpair1427";
  attribute SOFT_HLUTNM of \diffI_IIp1[26]_i_1\ : label is "soft_lutpair1427";
  attribute SOFT_HLUTNM of \diffI_IIp1[27]_i_1\ : label is "soft_lutpair1426";
  attribute SOFT_HLUTNM of \diffI_IIp1[28]_i_1\ : label is "soft_lutpair1426";
  attribute SOFT_HLUTNM of \diffI_IIp1[29]_i_1\ : label is "soft_lutpair1425";
  attribute SOFT_HLUTNM of \diffI_IIp1[2]_i_1\ : label is "soft_lutpair1439";
  attribute SOFT_HLUTNM of \diffI_IIp1[30]_i_1\ : label is "soft_lutpair1425";
  attribute SOFT_HLUTNM of \diffI_IIp1[31]_i_1\ : label is "soft_lutpair1424";
  attribute SOFT_HLUTNM of \diffI_IIp1[32]_i_1\ : label is "soft_lutpair1424";
  attribute SOFT_HLUTNM of \diffI_IIp1[33]_i_1\ : label is "soft_lutpair1423";
  attribute SOFT_HLUTNM of \diffI_IIp1[34]_i_1\ : label is "soft_lutpair1423";
  attribute SOFT_HLUTNM of \diffI_IIp1[35]_i_1\ : label is "soft_lutpair1422";
  attribute SOFT_HLUTNM of \diffI_IIp1[36]_i_1\ : label is "soft_lutpair1422";
  attribute SOFT_HLUTNM of \diffI_IIp1[37]_i_1\ : label is "soft_lutpair1421";
  attribute SOFT_HLUTNM of \diffI_IIp1[38]_i_1\ : label is "soft_lutpair1421";
  attribute SOFT_HLUTNM of \diffI_IIp1[39]_i_1\ : label is "soft_lutpair1420";
  attribute SOFT_HLUTNM of \diffI_IIp1[3]_i_1\ : label is "soft_lutpair1439";
  attribute SOFT_HLUTNM of \diffI_IIp1[40]_i_1\ : label is "soft_lutpair1420";
  attribute SOFT_HLUTNM of \diffI_IIp1[41]_i_1\ : label is "soft_lutpair1419";
  attribute SOFT_HLUTNM of \diffI_IIp1[42]_i_1\ : label is "soft_lutpair1419";
  attribute SOFT_HLUTNM of \diffI_IIp1[43]_i_1\ : label is "soft_lutpair1418";
  attribute SOFT_HLUTNM of \diffI_IIp1[44]_i_1\ : label is "soft_lutpair1418";
  attribute SOFT_HLUTNM of \diffI_IIp1[45]_i_1\ : label is "soft_lutpair1417";
  attribute SOFT_HLUTNM of \diffI_IIp1[46]_i_1\ : label is "soft_lutpair1417";
  attribute SOFT_HLUTNM of \diffI_IIp1[4]_i_1\ : label is "soft_lutpair1438";
  attribute SOFT_HLUTNM of \diffI_IIp1[5]_i_1\ : label is "soft_lutpair1438";
  attribute SOFT_HLUTNM of \diffI_IIp1[6]_i_1\ : label is "soft_lutpair1437";
  attribute SOFT_HLUTNM of \diffI_IIp1[7]_i_1\ : label is "soft_lutpair1437";
  attribute SOFT_HLUTNM of \diffI_IIp1[8]_i_1\ : label is "soft_lutpair1436";
  attribute SOFT_HLUTNM of \diffI_IIp1[9]_i_1\ : label is "soft_lutpair1436";
  attribute SOFT_HLUTNM of \dwrCoobuf[0]_i_1\ : label is "soft_lutpair801";
  attribute SOFT_HLUTNM of \dwrCoobuf[10]_i_1\ : label is "soft_lutpair788";
  attribute SOFT_HLUTNM of \dwrCoobuf[16]_i_1\ : label is "soft_lutpair802";
  attribute SOFT_HLUTNM of \dwrCoobuf[1]_i_1\ : label is "soft_lutpair789";
  attribute SOFT_HLUTNM of \dwrCoobuf[25]_i_1\ : label is "soft_lutpair787";
  attribute SOFT_HLUTNM of \dwrCoobuf[26]_i_1\ : label is "soft_lutpair786";
  attribute SOFT_HLUTNM of \dwrCoobuf[31]_i_12\ : label is "soft_lutpair806";
  attribute SOFT_HLUTNM of \dwrCoobuf[31]_i_18\ : label is "soft_lutpair947";
  attribute SOFT_HLUTNM of \dwrCoobuf[31]_i_2\ : label is "soft_lutpair788";
  attribute SOFT_HLUTNM of \dwrCoobuf[31]_i_4\ : label is "soft_lutpair804";
  attribute SOFT_HLUTNM of \dwrCoobuf[31]_i_68\ : label is "soft_lutpair947";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of \dwrCoobuf_reg[31]_i_10\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \dwrCoobuf_reg[31]_i_102\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \dwrCoobuf_reg[31]_i_11\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \dwrCoobuf_reg[31]_i_14\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \dwrCoobuf_reg[31]_i_15\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \dwrCoobuf_reg[31]_i_17\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \dwrCoobuf_reg[31]_i_67\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \dwrCoobuf_reg[31]_i_8\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \dwrCoobuf_reg[31]_i_9\ : label is 11;
  attribute SOFT_HLUTNM of \dx[0]_i_1\ : label is "soft_lutpair940";
  attribute SOFT_HLUTNM of \dx[10]_i_1\ : label is "soft_lutpair792";
  attribute SOFT_HLUTNM of \dx[11]_i_1\ : label is "soft_lutpair842";
  attribute SOFT_HLUTNM of \dx[11]_i_2\ : label is "soft_lutpair792";
  attribute SOFT_HLUTNM of \dx[12]_i_1\ : label is "soft_lutpair843";
  attribute SOFT_HLUTNM of \dx[14]_i_1\ : label is "soft_lutpair844";
  attribute SOFT_HLUTNM of \dx[16]_i_1\ : label is "soft_lutpair835";
  attribute SOFT_HLUTNM of \dx[17]_i_1\ : label is "soft_lutpair835";
  attribute SOFT_HLUTNM of \dx[18]_i_1\ : label is "soft_lutpair942";
  attribute SOFT_HLUTNM of \dx[19]_i_1\ : label is "soft_lutpair793";
  attribute SOFT_HLUTNM of \dx[1]_i_1\ : label is "soft_lutpair791";
  attribute SOFT_HLUTNM of \dx[20]_i_1\ : label is "soft_lutpair845";
  attribute SOFT_HLUTNM of \dx[20]_i_2\ : label is "soft_lutpair793";
  attribute SOFT_HLUTNM of \dx[21]_i_1\ : label is "soft_lutpair846";
  attribute SOFT_HLUTNM of \dx[23]_i_1\ : label is "soft_lutpair847";
  attribute SOFT_HLUTNM of \dx[25]_i_1\ : label is "soft_lutpair836";
  attribute SOFT_HLUTNM of \dx[26]_i_1\ : label is "soft_lutpair836";
  attribute SOFT_HLUTNM of \dx[27]_i_1\ : label is "soft_lutpair943";
  attribute SOFT_HLUTNM of \dx[28]_i_1\ : label is "soft_lutpair794";
  attribute SOFT_HLUTNM of \dx[29]_i_1\ : label is "soft_lutpair848";
  attribute SOFT_HLUTNM of \dx[29]_i_2\ : label is "soft_lutpair794";
  attribute SOFT_HLUTNM of \dx[2]_i_1\ : label is "soft_lutpair839";
  attribute SOFT_HLUTNM of \dx[2]_i_2\ : label is "soft_lutpair791";
  attribute SOFT_HLUTNM of \dx[30]_i_1\ : label is "soft_lutpair849";
  attribute SOFT_HLUTNM of \dx[32]_i_1\ : label is "soft_lutpair850";
  attribute SOFT_HLUTNM of \dx[34]_i_1\ : label is "soft_lutpair837";
  attribute SOFT_HLUTNM of \dx[35]_i_1\ : label is "soft_lutpair837";
  attribute SOFT_HLUTNM of \dx[36]_i_1\ : label is "soft_lutpair944";
  attribute SOFT_HLUTNM of \dx[37]_i_1\ : label is "soft_lutpair795";
  attribute SOFT_HLUTNM of \dx[38]_i_1\ : label is "soft_lutpair851";
  attribute SOFT_HLUTNM of \dx[38]_i_2\ : label is "soft_lutpair795";
  attribute SOFT_HLUTNM of \dx[39]_i_1\ : label is "soft_lutpair852";
  attribute SOFT_HLUTNM of \dx[3]_i_1\ : label is "soft_lutpair840";
  attribute SOFT_HLUTNM of \dx[41]_i_1\ : label is "soft_lutpair853";
  attribute SOFT_HLUTNM of \dx[43]_i_1\ : label is "soft_lutpair838";
  attribute SOFT_HLUTNM of \dx[44]_i_1\ : label is "soft_lutpair838";
  attribute SOFT_HLUTNM of \dx[5]_i_1\ : label is "soft_lutpair841";
  attribute SOFT_HLUTNM of \dx[7]_i_1\ : label is "soft_lutpair834";
  attribute SOFT_HLUTNM of \dx[8]_i_1\ : label is "soft_lutpair834";
  attribute SOFT_HLUTNM of \dx[9]_i_1\ : label is "soft_lutpair941";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \fghij_reg[16]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \fghij_reg[24]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \fghij_reg[30]_i_3\ : label is 35;
  attribute ADDER_THRESHOLD of \fghij_reg[8]_i_2\ : label is 35;
  attribute SOFT_HLUTNM of \i[1]_i_3\ : label is "soft_lutpair806";
  attribute SOFT_HLUTNM of \lat[4]_i_1\ : label is "soft_lutpair829";
  attribute SOFT_HLUTNM of \maximds[4][7]_i_3\ : label is "soft_lutpair787";
  attribute SOFT_HLUTNM of \msb[0]_i_10\ : label is "soft_lutpair779";
  attribute SOFT_HLUTNM of \msb[0]_i_11\ : label is "soft_lutpair816";
  attribute SOFT_HLUTNM of \msb[0]_i_12\ : label is "soft_lutpair779";
  attribute SOFT_HLUTNM of \msb[0]_i_13\ : label is "soft_lutpair860";
  attribute SOFT_HLUTNM of \msb[0]_i_4\ : label is "soft_lutpair813";
  attribute SOFT_HLUTNM of \msb[0]_i_6\ : label is "soft_lutpair815";
  attribute SOFT_HLUTNM of \msb[0]_i_9\ : label is "soft_lutpair820";
  attribute SOFT_HLUTNM of \msb[1]_i_10\ : label is "soft_lutpair819";
  attribute SOFT_HLUTNM of \msb[1]_i_12\ : label is "soft_lutpair861";
  attribute SOFT_HLUTNM of \msb[1]_i_8\ : label is "soft_lutpair819";
  attribute SOFT_HLUTNM of \msb[2]_i_10\ : label is "soft_lutpair816";
  attribute SOFT_HLUTNM of \msb[2]_i_11\ : label is "soft_lutpair812";
  attribute SOFT_HLUTNM of \msb[2]_i_12\ : label is "soft_lutpair820";
  attribute SOFT_HLUTNM of \msb[2]_i_13\ : label is "soft_lutpair861";
  attribute SOFT_HLUTNM of \msb[2]_i_8\ : label is "soft_lutpair818";
  attribute SOFT_HLUTNM of \msb[3]_i_10\ : label is "soft_lutpair814";
  attribute SOFT_HLUTNM of \msb[3]_i_13\ : label is "soft_lutpair815";
  attribute SOFT_HLUTNM of \msb[3]_i_2\ : label is "soft_lutpair813";
  attribute SOFT_HLUTNM of \msb[3]_i_3\ : label is "soft_lutpair812";
  attribute SOFT_HLUTNM of \msb[3]_i_6\ : label is "soft_lutpair818";
  attribute SOFT_HLUTNM of \msb[4]_i_3\ : label is "soft_lutpair814";
  attribute SOFT_HLUTNM of \msb[4]_i_4\ : label is "soft_lutpair860";
  attribute SOFT_HLUTNM of \msb[5]_i_5\ : label is "soft_lutpair817";
  attribute SOFT_HLUTNM of \postcol_lcl[0]_i_1\ : label is "soft_lutpair948";
  attribute SOFT_HLUTNM of \postcol_lcl[10]_i_3\ : label is "soft_lutpair790";
  attribute SOFT_HLUTNM of \postcol_lcl[10]_i_4\ : label is "soft_lutpair821";
  attribute SOFT_HLUTNM of \postcol_lcl[1]_i_1\ : label is "soft_lutpair822";
  attribute SOFT_HLUTNM of \postcol_lcl[2]_i_1\ : label is "soft_lutpair822";
  attribute SOFT_HLUTNM of \postcol_lcl[4]_i_1\ : label is "soft_lutpair790";
  attribute SOFT_HLUTNM of \postcol_lcl[4]_i_2\ : label is "soft_lutpair780";
  attribute SOFT_HLUTNM of \postcol_lcl[5]_i_2\ : label is "soft_lutpair780";
  attribute SOFT_HLUTNM of \postcol_lcl[9]_i_2\ : label is "soft_lutpair948";
  attribute SOFT_HLUTNM of \rexp[0]_i_3\ : label is "soft_lutpair831";
  attribute SOFT_HLUTNM of \rexp[0]_i_5\ : label is "soft_lutpair807";
  attribute SOFT_HLUTNM of \rexp[1]_i_13\ : label is "soft_lutpair808";
  attribute SOFT_HLUTNM of \rexp[1]_i_34\ : label is "soft_lutpair858";
  attribute SOFT_HLUTNM of \rexp[1]_i_35\ : label is "soft_lutpair778";
  attribute SOFT_HLUTNM of \rexp[1]_i_36\ : label is "soft_lutpair778";
  attribute SOFT_HLUTNM of \rexp[1]_i_4\ : label is "soft_lutpair784";
  attribute SOFT_HLUTNM of \rexp[1]_i_5\ : label is "soft_lutpair831";
  attribute SOFT_HLUTNM of \rexp[1]_i_6\ : label is "soft_lutpair963";
  attribute SOFT_HLUTNM of \rexp[1]_i_8\ : label is "soft_lutpair809";
  attribute SOFT_HLUTNM of \rexp[1]_i_9\ : label is "soft_lutpair809";
  attribute SOFT_HLUTNM of \rexp[2]_i_2\ : label is "soft_lutpair949";
  attribute SOFT_HLUTNM of \rexp[2]_i_3\ : label is "soft_lutpair949";
  attribute SOFT_HLUTNM of \rexp[4]_i_3\ : label is "soft_lutpair858";
  attribute SOFT_HLUTNM of \rexp[4]_i_5\ : label is "soft_lutpair951";
  attribute SOFT_HLUTNM of \rexp[4]_i_6\ : label is "soft_lutpair824";
  attribute SOFT_HLUTNM of \rexp[5]_i_3\ : label is "soft_lutpair830";
  attribute SOFT_HLUTNM of \rexp[5]_i_5\ : label is "soft_lutpair951";
  attribute SOFT_HLUTNM of \rexp[5]_i_6\ : label is "soft_lutpair825";
  attribute SOFT_HLUTNM of \rexp[6]_i_2\ : label is "soft_lutpair828";
  attribute SOFT_HLUTNM of \rexp[6]_i_3\ : label is "soft_lutpair784";
  attribute SOFT_HLUTNM of \rexp[6]_i_6\ : label is "soft_lutpair823";
  attribute SOFT_HLUTNM of \rexp[7]_i_12\ : label is "soft_lutpair811";
  attribute SOFT_HLUTNM of \rexp[7]_i_13\ : label is "soft_lutpair810";
  attribute SOFT_HLUTNM of \rexp[7]_i_16\ : label is "soft_lutpair810";
  attribute SOFT_HLUTNM of \rexp[7]_i_17\ : label is "soft_lutpair950";
  attribute SOFT_HLUTNM of \rexp[7]_i_18\ : label is "soft_lutpair859";
  attribute SOFT_HLUTNM of \rexp[7]_i_19\ : label is "soft_lutpair859";
  attribute SOFT_HLUTNM of \rexp[7]_i_21\ : label is "soft_lutpair830";
  attribute SOFT_HLUTNM of \rexp[7]_i_24\ : label is "soft_lutpair825";
  attribute SOFT_HLUTNM of \rexp[7]_i_32\ : label is "soft_lutpair824";
  attribute SOFT_HLUTNM of \rexp[7]_i_35\ : label is "soft_lutpair823";
  attribute SOFT_HLUTNM of \rexp[7]_i_36\ : label is "soft_lutpair950";
  attribute SOFT_HLUTNM of \rexp[7]_i_37\ : label is "soft_lutpair811";
  attribute SOFT_HLUTNM of \rexp[7]_i_38\ : label is "soft_lutpair963";
  attribute SOFT_HLUTNM of \rexp[7]_i_5\ : label is "soft_lutpair828";
  attribute SOFT_HLUTNM of \row_lcl[0]_i_1\ : label is "soft_lutpair802";
  attribute SOFT_HLUTNM of \row_lcl[10]_i_3\ : label is "soft_lutpair805";
  attribute SOFT_HLUTNM of \row_lcl[8]_i_1\ : label is "soft_lutpair805";
  attribute SOFT_HLUTNM of \rshift[1]_i_1\ : label is "soft_lutpair857";
  attribute SOFT_HLUTNM of \rshift[2]_i_1\ : label is "soft_lutpair857";
  attribute SOFT_HLUTNM of \rshift[3]_i_1\ : label is "soft_lutpair832";
  attribute SOFT_HLUTNM of \rshift[4]_i_1\ : label is "soft_lutpair832";
  attribute SOFT_HLUTNM of \rshift[4]_i_4\ : label is "soft_lutpair817";
  attribute SOFT_HLUTNM of \rshift[5]_i_3\ : label is "soft_lutpair807";
  attribute SOFT_HLUTNM of \rshift[5]_i_4\ : label is "soft_lutpair808";
  attribute COMPARATOR_THRESHOLD of \scoreMax_lcl_reg[7]_i_3\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \scoreMin_lcl_reg[7]_i_3\ : label is 11;
  attribute SOFT_HLUTNM of \shift[0]_i_1\ : label is "soft_lutpair800";
  attribute SOFT_HLUTNM of \shift[3]_i_1\ : label is "soft_lutpair800";
  attribute SOFT_HLUTNM of \stateCorner[0]_i_2\ : label is "soft_lutpair829";
  attribute SOFT_HLUTNM of \stateCorner[1]_i_6\ : label is "soft_lutpair821";
  attribute SOFT_HLUTNM of \stateImdstream[0]_i_3\ : label is "soft_lutpair797";
  attribute SOFT_HLUTNM of \stateImdstream[0]_i_4\ : label is "soft_lutpair856";
  attribute SOFT_HLUTNM of \stateImdstream[1]_i_3\ : label is "soft_lutpair799";
  attribute SOFT_HLUTNM of \stateMaxsel[1]_i_2\ : label is "soft_lutpair856";
  attribute SOFT_HLUTNM of \stateOp[1]_i_1\ : label is "soft_lutpair833";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of stateScore_reg : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of stateScore_reg_rep : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__0\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__1\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__10\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__11\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__12\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__13\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__14\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__15\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__16\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__17\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__18\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__2\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__3\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__4\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__5\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__6\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__7\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__8\ : label is "stateScore_reg";
  attribute ORIG_CELL_NAME of \stateScore_reg_rep__9\ : label is "stateScore_reg";
  attribute SOFT_HLUTNM of \sumXA[0]_i_1\ : label is "soft_lutpair1111";
  attribute SOFT_HLUTNM of \sumXA[10]_i_1\ : label is "soft_lutpair1106";
  attribute SOFT_HLUTNM of \sumXA[11]_i_1\ : label is "soft_lutpair1106";
  attribute SOFT_HLUTNM of \sumXA[12]_i_1\ : label is "soft_lutpair1105";
  attribute SOFT_HLUTNM of \sumXA[13]_i_1\ : label is "soft_lutpair1105";
  attribute SOFT_HLUTNM of \sumXA[14]_i_1\ : label is "soft_lutpair1104";
  attribute SOFT_HLUTNM of \sumXA[15]_i_1\ : label is "soft_lutpair1104";
  attribute SOFT_HLUTNM of \sumXA[16]_i_1\ : label is "soft_lutpair1103";
  attribute SOFT_HLUTNM of \sumXA[17]_i_1\ : label is "soft_lutpair1103";
  attribute SOFT_HLUTNM of \sumXA[18]_i_1\ : label is "soft_lutpair1102";
  attribute SOFT_HLUTNM of \sumXA[19]_i_1\ : label is "soft_lutpair1102";
  attribute SOFT_HLUTNM of \sumXA[1]_i_1\ : label is "soft_lutpair1111";
  attribute SOFT_HLUTNM of \sumXA[20]_i_1\ : label is "soft_lutpair1101";
  attribute SOFT_HLUTNM of \sumXA[21]_i_1\ : label is "soft_lutpair1101";
  attribute SOFT_HLUTNM of \sumXA[22]_i_1\ : label is "soft_lutpair1100";
  attribute SOFT_HLUTNM of \sumXA[23]_i_1\ : label is "soft_lutpair1100";
  attribute SOFT_HLUTNM of \sumXA[24]_i_1\ : label is "soft_lutpair1099";
  attribute SOFT_HLUTNM of \sumXA[25]_i_1\ : label is "soft_lutpair1099";
  attribute SOFT_HLUTNM of \sumXA[26]_i_1\ : label is "soft_lutpair1098";
  attribute SOFT_HLUTNM of \sumXA[27]_i_1\ : label is "soft_lutpair1098";
  attribute SOFT_HLUTNM of \sumXA[28]_i_1\ : label is "soft_lutpair1097";
  attribute SOFT_HLUTNM of \sumXA[29]_i_1\ : label is "soft_lutpair1097";
  attribute SOFT_HLUTNM of \sumXA[2]_i_1\ : label is "soft_lutpair1110";
  attribute SOFT_HLUTNM of \sumXA[30]_i_1\ : label is "soft_lutpair1096";
  attribute SOFT_HLUTNM of \sumXA[31]_i_1\ : label is "soft_lutpair1096";
  attribute SOFT_HLUTNM of \sumXA[32]_i_1\ : label is "soft_lutpair1095";
  attribute SOFT_HLUTNM of \sumXA[33]_i_1\ : label is "soft_lutpair1095";
  attribute SOFT_HLUTNM of \sumXA[34]_i_1\ : label is "soft_lutpair1094";
  attribute SOFT_HLUTNM of \sumXA[35]_i_1\ : label is "soft_lutpair1094";
  attribute SOFT_HLUTNM of \sumXA[36]_i_1\ : label is "soft_lutpair1093";
  attribute SOFT_HLUTNM of \sumXA[37]_i_1\ : label is "soft_lutpair1093";
  attribute SOFT_HLUTNM of \sumXA[38]_i_1\ : label is "soft_lutpair1092";
  attribute SOFT_HLUTNM of \sumXA[39]_i_1\ : label is "soft_lutpair1092";
  attribute SOFT_HLUTNM of \sumXA[3]_i_1\ : label is "soft_lutpair1110";
  attribute SOFT_HLUTNM of \sumXA[40]_i_1\ : label is "soft_lutpair1091";
  attribute SOFT_HLUTNM of \sumXA[41]_i_1\ : label is "soft_lutpair1091";
  attribute SOFT_HLUTNM of \sumXA[42]_i_1\ : label is "soft_lutpair1090";
  attribute SOFT_HLUTNM of \sumXA[43]_i_1\ : label is "soft_lutpair1090";
  attribute SOFT_HLUTNM of \sumXA[4]_i_1\ : label is "soft_lutpair1109";
  attribute SOFT_HLUTNM of \sumXA[5]_i_1\ : label is "soft_lutpair1109";
  attribute SOFT_HLUTNM of \sumXA[6]_i_1\ : label is "soft_lutpair1108";
  attribute SOFT_HLUTNM of \sumXA[7]_i_1\ : label is "soft_lutpair1108";
  attribute SOFT_HLUTNM of \sumXA[8]_i_1\ : label is "soft_lutpair1107";
  attribute SOFT_HLUTNM of \sumXA[9]_i_1\ : label is "soft_lutpair1107";
  attribute SOFT_HLUTNM of \sumXYA[0]_i_1\ : label is "soft_lutpair1372";
  attribute SOFT_HLUTNM of \sumXYA[10]_i_1\ : label is "soft_lutpair1367";
  attribute SOFT_HLUTNM of \sumXYA[11]_i_1\ : label is "soft_lutpair1367";
  attribute SOFT_HLUTNM of \sumXYA[12]_i_1\ : label is "soft_lutpair1366";
  attribute SOFT_HLUTNM of \sumXYA[13]_i_1\ : label is "soft_lutpair1366";
  attribute SOFT_HLUTNM of \sumXYA[14]_i_1\ : label is "soft_lutpair1365";
  attribute SOFT_HLUTNM of \sumXYA[15]_i_1\ : label is "soft_lutpair1365";
  attribute SOFT_HLUTNM of \sumXYA[16]_i_1\ : label is "soft_lutpair1364";
  attribute SOFT_HLUTNM of \sumXYA[17]_i_1\ : label is "soft_lutpair1364";
  attribute SOFT_HLUTNM of \sumXYA[18]_i_1\ : label is "soft_lutpair1363";
  attribute SOFT_HLUTNM of \sumXYA[19]_i_1\ : label is "soft_lutpair1363";
  attribute SOFT_HLUTNM of \sumXYA[1]_i_1\ : label is "soft_lutpair1372";
  attribute SOFT_HLUTNM of \sumXYA[20]_i_1\ : label is "soft_lutpair1362";
  attribute SOFT_HLUTNM of \sumXYA[21]_i_1\ : label is "soft_lutpair1362";
  attribute SOFT_HLUTNM of \sumXYA[22]_i_1\ : label is "soft_lutpair1361";
  attribute SOFT_HLUTNM of \sumXYA[23]_i_1\ : label is "soft_lutpair1361";
  attribute SOFT_HLUTNM of \sumXYA[24]_i_1\ : label is "soft_lutpair1360";
  attribute SOFT_HLUTNM of \sumXYA[25]_i_1\ : label is "soft_lutpair1360";
  attribute SOFT_HLUTNM of \sumXYA[26]_i_1\ : label is "soft_lutpair1359";
  attribute SOFT_HLUTNM of \sumXYA[27]_i_1\ : label is "soft_lutpair1359";
  attribute SOFT_HLUTNM of \sumXYA[28]_i_1\ : label is "soft_lutpair1358";
  attribute SOFT_HLUTNM of \sumXYA[29]_i_1\ : label is "soft_lutpair1358";
  attribute SOFT_HLUTNM of \sumXYA[2]_i_1\ : label is "soft_lutpair1371";
  attribute SOFT_HLUTNM of \sumXYA[30]_i_1\ : label is "soft_lutpair1357";
  attribute SOFT_HLUTNM of \sumXYA[31]_i_1\ : label is "soft_lutpair1357";
  attribute SOFT_HLUTNM of \sumXYA[32]_i_1\ : label is "soft_lutpair1356";
  attribute SOFT_HLUTNM of \sumXYA[33]_i_1\ : label is "soft_lutpair1356";
  attribute SOFT_HLUTNM of \sumXYA[34]_i_1\ : label is "soft_lutpair1355";
  attribute SOFT_HLUTNM of \sumXYA[35]_i_1\ : label is "soft_lutpair1355";
  attribute SOFT_HLUTNM of \sumXYA[36]_i_1\ : label is "soft_lutpair1354";
  attribute SOFT_HLUTNM of \sumXYA[37]_i_1\ : label is "soft_lutpair1354";
  attribute SOFT_HLUTNM of \sumXYA[38]_i_1\ : label is "soft_lutpair1353";
  attribute SOFT_HLUTNM of \sumXYA[39]_i_1\ : label is "soft_lutpair1353";
  attribute SOFT_HLUTNM of \sumXYA[3]_i_1\ : label is "soft_lutpair1371";
  attribute SOFT_HLUTNM of \sumXYA[40]_i_1\ : label is "soft_lutpair1352";
  attribute SOFT_HLUTNM of \sumXYA[41]_i_1\ : label is "soft_lutpair1352";
  attribute SOFT_HLUTNM of \sumXYA[42]_i_1\ : label is "soft_lutpair1351";
  attribute SOFT_HLUTNM of \sumXYA[43]_i_1\ : label is "soft_lutpair1351";
  attribute SOFT_HLUTNM of \sumXYA[4]_i_1\ : label is "soft_lutpair1370";
  attribute SOFT_HLUTNM of \sumXYA[5]_i_1\ : label is "soft_lutpair1370";
  attribute SOFT_HLUTNM of \sumXYA[6]_i_1\ : label is "soft_lutpair1369";
  attribute SOFT_HLUTNM of \sumXYA[7]_i_1\ : label is "soft_lutpair1369";
  attribute SOFT_HLUTNM of \sumXYA[8]_i_1\ : label is "soft_lutpair1368";
  attribute SOFT_HLUTNM of \sumXYA[9]_i_1\ : label is "soft_lutpair1368";
  attribute SOFT_HLUTNM of \sumYA[0]_i_1\ : label is "soft_lutpair1227";
  attribute SOFT_HLUTNM of \sumYA[10]_i_1\ : label is "soft_lutpair1222";
  attribute SOFT_HLUTNM of \sumYA[11]_i_1\ : label is "soft_lutpair1222";
  attribute SOFT_HLUTNM of \sumYA[12]_i_1\ : label is "soft_lutpair1221";
  attribute SOFT_HLUTNM of \sumYA[13]_i_1\ : label is "soft_lutpair1221";
  attribute SOFT_HLUTNM of \sumYA[14]_i_1\ : label is "soft_lutpair1220";
  attribute SOFT_HLUTNM of \sumYA[15]_i_1\ : label is "soft_lutpair1220";
  attribute SOFT_HLUTNM of \sumYA[16]_i_1\ : label is "soft_lutpair1219";
  attribute SOFT_HLUTNM of \sumYA[17]_i_1\ : label is "soft_lutpair1219";
  attribute SOFT_HLUTNM of \sumYA[18]_i_1\ : label is "soft_lutpair1218";
  attribute SOFT_HLUTNM of \sumYA[19]_i_1\ : label is "soft_lutpair1218";
  attribute SOFT_HLUTNM of \sumYA[1]_i_1\ : label is "soft_lutpair1227";
  attribute SOFT_HLUTNM of \sumYA[20]_i_1\ : label is "soft_lutpair1217";
  attribute SOFT_HLUTNM of \sumYA[21]_i_1\ : label is "soft_lutpair1217";
  attribute SOFT_HLUTNM of \sumYA[22]_i_1\ : label is "soft_lutpair1216";
  attribute SOFT_HLUTNM of \sumYA[23]_i_1\ : label is "soft_lutpair1216";
  attribute SOFT_HLUTNM of \sumYA[24]_i_1\ : label is "soft_lutpair1215";
  attribute SOFT_HLUTNM of \sumYA[25]_i_1\ : label is "soft_lutpair1215";
  attribute SOFT_HLUTNM of \sumYA[26]_i_1\ : label is "soft_lutpair1214";
  attribute SOFT_HLUTNM of \sumYA[27]_i_1\ : label is "soft_lutpair1214";
  attribute SOFT_HLUTNM of \sumYA[28]_i_1\ : label is "soft_lutpair1213";
  attribute SOFT_HLUTNM of \sumYA[29]_i_1\ : label is "soft_lutpair1213";
  attribute SOFT_HLUTNM of \sumYA[2]_i_1\ : label is "soft_lutpair1226";
  attribute SOFT_HLUTNM of \sumYA[30]_i_1\ : label is "soft_lutpair1212";
  attribute SOFT_HLUTNM of \sumYA[31]_i_1\ : label is "soft_lutpair1212";
  attribute SOFT_HLUTNM of \sumYA[32]_i_1\ : label is "soft_lutpair1211";
  attribute SOFT_HLUTNM of \sumYA[33]_i_1\ : label is "soft_lutpair1211";
  attribute SOFT_HLUTNM of \sumYA[34]_i_1\ : label is "soft_lutpair1210";
  attribute SOFT_HLUTNM of \sumYA[35]_i_1\ : label is "soft_lutpair1210";
  attribute SOFT_HLUTNM of \sumYA[36]_i_1\ : label is "soft_lutpair1209";
  attribute SOFT_HLUTNM of \sumYA[37]_i_1\ : label is "soft_lutpair1209";
  attribute SOFT_HLUTNM of \sumYA[38]_i_1\ : label is "soft_lutpair1208";
  attribute SOFT_HLUTNM of \sumYA[39]_i_1\ : label is "soft_lutpair1208";
  attribute SOFT_HLUTNM of \sumYA[3]_i_1\ : label is "soft_lutpair1226";
  attribute SOFT_HLUTNM of \sumYA[40]_i_1\ : label is "soft_lutpair1207";
  attribute SOFT_HLUTNM of \sumYA[41]_i_1\ : label is "soft_lutpair1207";
  attribute SOFT_HLUTNM of \sumYA[42]_i_1\ : label is "soft_lutpair1206";
  attribute SOFT_HLUTNM of \sumYA[43]_i_1\ : label is "soft_lutpair1206";
  attribute SOFT_HLUTNM of \sumYA[4]_i_1\ : label is "soft_lutpair1225";
  attribute SOFT_HLUTNM of \sumYA[5]_i_1\ : label is "soft_lutpair1225";
  attribute SOFT_HLUTNM of \sumYA[6]_i_1\ : label is "soft_lutpair1224";
  attribute SOFT_HLUTNM of \sumYA[7]_i_1\ : label is "soft_lutpair1224";
  attribute SOFT_HLUTNM of \sumYA[8]_i_1\ : label is "soft_lutpair1223";
  attribute SOFT_HLUTNM of \sumYA[9]_i_1\ : label is "soft_lutpair1223";
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of termI0 : label is "yes";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of termI0 : label is "{SYNTH-13 {cell *THIS*}}";
  attribute KEEP_HIERARCHY of \termI0__0\ : label is "yes";
  attribute METHODOLOGY_DRC_VIOS of \termI0__0\ : label is "{SYNTH-13 {cell *THIS*}}";
  attribute KEEP_HIERARCHY of termII0 : label is "yes";
  attribute METHODOLOGY_DRC_VIOS of termII0 : label is "{SYNTH-13 {cell *THIS*}}";
  attribute KEEP_HIERARCHY of \termII0__0\ : label is "yes";
  attribute METHODOLOGY_DRC_VIOS of \termII0__0\ : label is "{SYNTH-13 {cell *THIS*}}";
  attribute KEEP_HIERARCHY of termIII0 : label is "yes";
  attribute METHODOLOGY_DRC_VIOS of termIII0 : label is "{SYNTH-13 {cell *THIS*}}";
  attribute KEEP_HIERARCHY of \termIII0__0\ : label is "yes";
  attribute METHODOLOGY_DRC_VIOS of \termIII0__0\ : label is "{SYNTH-13 {cell *THIS*}}";
  attribute SOFT_HLUTNM of \termIII[0]_i_1\ : label is "soft_lutpair1464";
  attribute SOFT_HLUTNM of \termIII[10]_i_1\ : label is "soft_lutpair1459";
  attribute SOFT_HLUTNM of \termIII[11]_i_1\ : label is "soft_lutpair1459";
  attribute SOFT_HLUTNM of \termIII[12]_i_1\ : label is "soft_lutpair1458";
  attribute SOFT_HLUTNM of \termIII[13]_i_1\ : label is "soft_lutpair1458";
  attribute SOFT_HLUTNM of \termIII[14]_i_1\ : label is "soft_lutpair1457";
  attribute SOFT_HLUTNM of \termIII[15]_i_1\ : label is "soft_lutpair1457";
  attribute SOFT_HLUTNM of \termIII[16]_i_1\ : label is "soft_lutpair1456";
  attribute SOFT_HLUTNM of \termIII[17]_i_1\ : label is "soft_lutpair1456";
  attribute SOFT_HLUTNM of \termIII[18]_i_1\ : label is "soft_lutpair1455";
  attribute SOFT_HLUTNM of \termIII[19]_i_1\ : label is "soft_lutpair1455";
  attribute SOFT_HLUTNM of \termIII[1]_i_1\ : label is "soft_lutpair1464";
  attribute SOFT_HLUTNM of \termIII[20]_i_1\ : label is "soft_lutpair1454";
  attribute SOFT_HLUTNM of \termIII[21]_i_1\ : label is "soft_lutpair1454";
  attribute SOFT_HLUTNM of \termIII[22]_i_1\ : label is "soft_lutpair1453";
  attribute SOFT_HLUTNM of \termIII[23]_i_1\ : label is "soft_lutpair1453";
  attribute SOFT_HLUTNM of \termIII[24]_i_1\ : label is "soft_lutpair1452";
  attribute SOFT_HLUTNM of \termIII[25]_i_1\ : label is "soft_lutpair1452";
  attribute SOFT_HLUTNM of \termIII[26]_i_1\ : label is "soft_lutpair1451";
  attribute SOFT_HLUTNM of \termIII[27]_i_1\ : label is "soft_lutpair1451";
  attribute SOFT_HLUTNM of \termIII[28]_i_1\ : label is "soft_lutpair1450";
  attribute SOFT_HLUTNM of \termIII[29]_i_1\ : label is "soft_lutpair1450";
  attribute SOFT_HLUTNM of \termIII[2]_i_1\ : label is "soft_lutpair1463";
  attribute SOFT_HLUTNM of \termIII[30]_i_1\ : label is "soft_lutpair1449";
  attribute SOFT_HLUTNM of \termIII[31]_i_1\ : label is "soft_lutpair1449";
  attribute SOFT_HLUTNM of \termIII[32]_i_1\ : label is "soft_lutpair1448";
  attribute SOFT_HLUTNM of \termIII[33]_i_1\ : label is "soft_lutpair1448";
  attribute SOFT_HLUTNM of \termIII[34]_i_1\ : label is "soft_lutpair1447";
  attribute SOFT_HLUTNM of \termIII[35]_i_1\ : label is "soft_lutpair1447";
  attribute SOFT_HLUTNM of \termIII[36]_i_1\ : label is "soft_lutpair1446";
  attribute SOFT_HLUTNM of \termIII[37]_i_1\ : label is "soft_lutpair1446";
  attribute SOFT_HLUTNM of \termIII[38]_i_1\ : label is "soft_lutpair1445";
  attribute SOFT_HLUTNM of \termIII[39]_i_1\ : label is "soft_lutpair1445";
  attribute SOFT_HLUTNM of \termIII[3]_i_1\ : label is "soft_lutpair1463";
  attribute SOFT_HLUTNM of \termIII[40]_i_1\ : label is "soft_lutpair1444";
  attribute SOFT_HLUTNM of \termIII[41]_i_1\ : label is "soft_lutpair1444";
  attribute SOFT_HLUTNM of \termIII[42]_i_1\ : label is "soft_lutpair1443";
  attribute SOFT_HLUTNM of \termIII[43]_i_1\ : label is "soft_lutpair1443";
  attribute SOFT_HLUTNM of \termIII[44]_i_1\ : label is "soft_lutpair1442";
  attribute SOFT_HLUTNM of \termIII[45]_i_1\ : label is "soft_lutpair1442";
  attribute SOFT_HLUTNM of \termIII[46]_i_1\ : label is "soft_lutpair1441";
  attribute SOFT_HLUTNM of \termIII[47]_i_1\ : label is "soft_lutpair1441";
  attribute SOFT_HLUTNM of \termIII[4]_i_1\ : label is "soft_lutpair1462";
  attribute SOFT_HLUTNM of \termIII[5]_i_1\ : label is "soft_lutpair1462";
  attribute SOFT_HLUTNM of \termIII[6]_i_1\ : label is "soft_lutpair1461";
  attribute SOFT_HLUTNM of \termIII[7]_i_1\ : label is "soft_lutpair1461";
  attribute SOFT_HLUTNM of \termIII[8]_i_1\ : label is "soft_lutpair1460";
  attribute SOFT_HLUTNM of \termIII[9]_i_1\ : label is "soft_lutpair1460";
  attribute SOFT_HLUTNM of \termIIIk[0]_i_1\ : label is "soft_lutpair1485";
  attribute SOFT_HLUTNM of \termIIIk[10]_i_1\ : label is "soft_lutpair1480";
  attribute SOFT_HLUTNM of \termIIIk[11]_i_1\ : label is "soft_lutpair1480";
  attribute SOFT_HLUTNM of \termIIIk[12]_i_1\ : label is "soft_lutpair1479";
  attribute SOFT_HLUTNM of \termIIIk[13]_i_1\ : label is "soft_lutpair1479";
  attribute SOFT_HLUTNM of \termIIIk[14]_i_1\ : label is "soft_lutpair1478";
  attribute SOFT_HLUTNM of \termIIIk[15]_i_1\ : label is "soft_lutpair1478";
  attribute SOFT_HLUTNM of \termIIIk[16]_i_1\ : label is "soft_lutpair1477";
  attribute SOFT_HLUTNM of \termIIIk[17]_i_1\ : label is "soft_lutpair1477";
  attribute SOFT_HLUTNM of \termIIIk[18]_i_1\ : label is "soft_lutpair1476";
  attribute SOFT_HLUTNM of \termIIIk[19]_i_1\ : label is "soft_lutpair1476";
  attribute SOFT_HLUTNM of \termIIIk[1]_i_1\ : label is "soft_lutpair1485";
  attribute SOFT_HLUTNM of \termIIIk[20]_i_1\ : label is "soft_lutpair1475";
  attribute SOFT_HLUTNM of \termIIIk[21]_i_1\ : label is "soft_lutpair1475";
  attribute SOFT_HLUTNM of \termIIIk[22]_i_1\ : label is "soft_lutpair1474";
  attribute SOFT_HLUTNM of \termIIIk[23]_i_1\ : label is "soft_lutpair1474";
  attribute SOFT_HLUTNM of \termIIIk[25]_i_1\ : label is "soft_lutpair1473";
  attribute SOFT_HLUTNM of \termIIIk[26]_i_1\ : label is "soft_lutpair1473";
  attribute SOFT_HLUTNM of \termIIIk[27]_i_1\ : label is "soft_lutpair1472";
  attribute SOFT_HLUTNM of \termIIIk[28]_i_1\ : label is "soft_lutpair1472";
  attribute SOFT_HLUTNM of \termIIIk[29]_i_1\ : label is "soft_lutpair1471";
  attribute SOFT_HLUTNM of \termIIIk[2]_i_1\ : label is "soft_lutpair1484";
  attribute SOFT_HLUTNM of \termIIIk[30]_i_1\ : label is "soft_lutpair1471";
  attribute SOFT_HLUTNM of \termIIIk[31]_i_1\ : label is "soft_lutpair1470";
  attribute SOFT_HLUTNM of \termIIIk[32]_i_1\ : label is "soft_lutpair1470";
  attribute SOFT_HLUTNM of \termIIIk[33]_i_1\ : label is "soft_lutpair1469";
  attribute SOFT_HLUTNM of \termIIIk[34]_i_1\ : label is "soft_lutpair1469";
  attribute SOFT_HLUTNM of \termIIIk[35]_i_1\ : label is "soft_lutpair1468";
  attribute SOFT_HLUTNM of \termIIIk[36]_i_1\ : label is "soft_lutpair1468";
  attribute SOFT_HLUTNM of \termIIIk[37]_i_1\ : label is "soft_lutpair1467";
  attribute SOFT_HLUTNM of \termIIIk[38]_i_1\ : label is "soft_lutpair1467";
  attribute SOFT_HLUTNM of \termIIIk[39]_i_1\ : label is "soft_lutpair1466";
  attribute SOFT_HLUTNM of \termIIIk[3]_i_1\ : label is "soft_lutpair1484";
  attribute SOFT_HLUTNM of \termIIIk[40]_i_1\ : label is "soft_lutpair1466";
  attribute SOFT_HLUTNM of \termIIIk[41]_i_1\ : label is "soft_lutpair1465";
  attribute SOFT_HLUTNM of \termIIIk[42]_i_1\ : label is "soft_lutpair1465";
  attribute SOFT_HLUTNM of \termIIIk[43]_i_1\ : label is "soft_lutpair1428";
  attribute SOFT_HLUTNM of \termIIIk[4]_i_1\ : label is "soft_lutpair1483";
  attribute SOFT_HLUTNM of \termIIIk[5]_i_1\ : label is "soft_lutpair1483";
  attribute SOFT_HLUTNM of \termIIIk[6]_i_1\ : label is "soft_lutpair1482";
  attribute SOFT_HLUTNM of \termIIIk[7]_i_1\ : label is "soft_lutpair1482";
  attribute SOFT_HLUTNM of \termIIIk[8]_i_1\ : label is "soft_lutpair1481";
  attribute SOFT_HLUTNM of \termIIIk[9]_i_1\ : label is "soft_lutpair1481";
  attribute SOFT_HLUTNM of \termII[0]_i_1\ : label is "soft_lutpair1416";
  attribute SOFT_HLUTNM of \termII[10]_i_1\ : label is "soft_lutpair1411";
  attribute SOFT_HLUTNM of \termII[11]_i_1\ : label is "soft_lutpair1411";
  attribute SOFT_HLUTNM of \termII[12]_i_1\ : label is "soft_lutpair1410";
  attribute SOFT_HLUTNM of \termII[13]_i_1\ : label is "soft_lutpair1410";
  attribute SOFT_HLUTNM of \termII[14]_i_1\ : label is "soft_lutpair1409";
  attribute SOFT_HLUTNM of \termII[15]_i_1\ : label is "soft_lutpair1409";
  attribute SOFT_HLUTNM of \termII[16]_i_1\ : label is "soft_lutpair1408";
  attribute SOFT_HLUTNM of \termII[17]_i_1\ : label is "soft_lutpair1408";
  attribute SOFT_HLUTNM of \termII[18]_i_1\ : label is "soft_lutpair1407";
  attribute SOFT_HLUTNM of \termII[19]_i_1\ : label is "soft_lutpair1407";
  attribute SOFT_HLUTNM of \termII[1]_i_1\ : label is "soft_lutpair1416";
  attribute SOFT_HLUTNM of \termII[20]_i_1\ : label is "soft_lutpair1406";
  attribute SOFT_HLUTNM of \termII[21]_i_1\ : label is "soft_lutpair1406";
  attribute SOFT_HLUTNM of \termII[22]_i_1\ : label is "soft_lutpair1405";
  attribute SOFT_HLUTNM of \termII[23]_i_1\ : label is "soft_lutpair1405";
  attribute SOFT_HLUTNM of \termII[24]_i_1\ : label is "soft_lutpair1404";
  attribute SOFT_HLUTNM of \termII[25]_i_1\ : label is "soft_lutpair1404";
  attribute SOFT_HLUTNM of \termII[26]_i_1\ : label is "soft_lutpair1403";
  attribute SOFT_HLUTNM of \termII[27]_i_1\ : label is "soft_lutpair1403";
  attribute SOFT_HLUTNM of \termII[28]_i_1\ : label is "soft_lutpair1402";
  attribute SOFT_HLUTNM of \termII[29]_i_1\ : label is "soft_lutpair1402";
  attribute SOFT_HLUTNM of \termII[2]_i_1\ : label is "soft_lutpair1415";
  attribute SOFT_HLUTNM of \termII[30]_i_1\ : label is "soft_lutpair1401";
  attribute SOFT_HLUTNM of \termII[31]_i_1\ : label is "soft_lutpair1401";
  attribute SOFT_HLUTNM of \termII[32]_i_1\ : label is "soft_lutpair1400";
  attribute SOFT_HLUTNM of \termII[33]_i_1\ : label is "soft_lutpair1400";
  attribute SOFT_HLUTNM of \termII[34]_i_1\ : label is "soft_lutpair1399";
  attribute SOFT_HLUTNM of \termII[35]_i_1\ : label is "soft_lutpair1399";
  attribute SOFT_HLUTNM of \termII[36]_i_1\ : label is "soft_lutpair1398";
  attribute SOFT_HLUTNM of \termII[37]_i_1\ : label is "soft_lutpair1398";
  attribute SOFT_HLUTNM of \termII[38]_i_1\ : label is "soft_lutpair1397";
  attribute SOFT_HLUTNM of \termII[39]_i_1\ : label is "soft_lutpair1397";
  attribute SOFT_HLUTNM of \termII[3]_i_1\ : label is "soft_lutpair1415";
  attribute SOFT_HLUTNM of \termII[40]_i_1\ : label is "soft_lutpair1396";
  attribute SOFT_HLUTNM of \termII[41]_i_1\ : label is "soft_lutpair1396";
  attribute SOFT_HLUTNM of \termII[42]_i_1\ : label is "soft_lutpair1395";
  attribute SOFT_HLUTNM of \termII[43]_i_1\ : label is "soft_lutpair1395";
  attribute SOFT_HLUTNM of \termII[44]_i_1\ : label is "soft_lutpair1394";
  attribute SOFT_HLUTNM of \termII[45]_i_1\ : label is "soft_lutpair1394";
  attribute SOFT_HLUTNM of \termII[4]_i_1\ : label is "soft_lutpair1414";
  attribute SOFT_HLUTNM of \termII[5]_i_1\ : label is "soft_lutpair1414";
  attribute SOFT_HLUTNM of \termII[6]_i_1\ : label is "soft_lutpair1413";
  attribute SOFT_HLUTNM of \termII[7]_i_1\ : label is "soft_lutpair1413";
  attribute SOFT_HLUTNM of \termII[8]_i_1\ : label is "soft_lutpair1412";
  attribute SOFT_HLUTNM of \termII[9]_i_1\ : label is "soft_lutpair1412";
  attribute SOFT_HLUTNM of \termI[0]_i_1\ : label is "soft_lutpair1271";
  attribute SOFT_HLUTNM of \termI[10]_i_1\ : label is "soft_lutpair1266";
  attribute SOFT_HLUTNM of \termI[11]_i_1\ : label is "soft_lutpair1266";
  attribute SOFT_HLUTNM of \termI[12]_i_1\ : label is "soft_lutpair1265";
  attribute SOFT_HLUTNM of \termI[13]_i_1\ : label is "soft_lutpair1265";
  attribute SOFT_HLUTNM of \termI[14]_i_1\ : label is "soft_lutpair1264";
  attribute SOFT_HLUTNM of \termI[15]_i_1\ : label is "soft_lutpair1264";
  attribute SOFT_HLUTNM of \termI[16]_i_1\ : label is "soft_lutpair1263";
  attribute SOFT_HLUTNM of \termI[17]_i_1\ : label is "soft_lutpair1263";
  attribute SOFT_HLUTNM of \termI[18]_i_1\ : label is "soft_lutpair1262";
  attribute SOFT_HLUTNM of \termI[19]_i_1\ : label is "soft_lutpair1262";
  attribute SOFT_HLUTNM of \termI[1]_i_1\ : label is "soft_lutpair1271";
  attribute SOFT_HLUTNM of \termI[20]_i_1\ : label is "soft_lutpair1261";
  attribute SOFT_HLUTNM of \termI[21]_i_1\ : label is "soft_lutpair1261";
  attribute SOFT_HLUTNM of \termI[22]_i_1\ : label is "soft_lutpair1260";
  attribute SOFT_HLUTNM of \termI[23]_i_1\ : label is "soft_lutpair1260";
  attribute SOFT_HLUTNM of \termI[24]_i_1\ : label is "soft_lutpair1259";
  attribute SOFT_HLUTNM of \termI[25]_i_1\ : label is "soft_lutpair1259";
  attribute SOFT_HLUTNM of \termI[26]_i_1\ : label is "soft_lutpair1258";
  attribute SOFT_HLUTNM of \termI[27]_i_1\ : label is "soft_lutpair1258";
  attribute SOFT_HLUTNM of \termI[28]_i_1\ : label is "soft_lutpair1257";
  attribute SOFT_HLUTNM of \termI[29]_i_1\ : label is "soft_lutpair1257";
  attribute SOFT_HLUTNM of \termI[2]_i_1\ : label is "soft_lutpair1270";
  attribute SOFT_HLUTNM of \termI[30]_i_1\ : label is "soft_lutpair1256";
  attribute SOFT_HLUTNM of \termI[31]_i_1\ : label is "soft_lutpair1256";
  attribute SOFT_HLUTNM of \termI[32]_i_1\ : label is "soft_lutpair1255";
  attribute SOFT_HLUTNM of \termI[33]_i_1\ : label is "soft_lutpair1255";
  attribute SOFT_HLUTNM of \termI[34]_i_1\ : label is "soft_lutpair1254";
  attribute SOFT_HLUTNM of \termI[35]_i_1\ : label is "soft_lutpair1254";
  attribute SOFT_HLUTNM of \termI[36]_i_1\ : label is "soft_lutpair1253";
  attribute SOFT_HLUTNM of \termI[37]_i_1\ : label is "soft_lutpair1253";
  attribute SOFT_HLUTNM of \termI[38]_i_1\ : label is "soft_lutpair1252";
  attribute SOFT_HLUTNM of \termI[39]_i_1\ : label is "soft_lutpair1252";
  attribute SOFT_HLUTNM of \termI[3]_i_1\ : label is "soft_lutpair1270";
  attribute SOFT_HLUTNM of \termI[40]_i_1\ : label is "soft_lutpair1251";
  attribute SOFT_HLUTNM of \termI[41]_i_1\ : label is "soft_lutpair1251";
  attribute SOFT_HLUTNM of \termI[42]_i_1\ : label is "soft_lutpair1250";
  attribute SOFT_HLUTNM of \termI[43]_i_1\ : label is "soft_lutpair1250";
  attribute SOFT_HLUTNM of \termI[44]_i_1\ : label is "soft_lutpair1249";
  attribute SOFT_HLUTNM of \termI[45]_i_1\ : label is "soft_lutpair1249";
  attribute SOFT_HLUTNM of \termI[4]_i_1\ : label is "soft_lutpair1269";
  attribute SOFT_HLUTNM of \termI[5]_i_1\ : label is "soft_lutpair1269";
  attribute SOFT_HLUTNM of \termI[6]_i_1\ : label is "soft_lutpair1268";
  attribute SOFT_HLUTNM of \termI[7]_i_1\ : label is "soft_lutpair1268";
  attribute SOFT_HLUTNM of \termI[8]_i_1\ : label is "soft_lutpair1267";
  attribute SOFT_HLUTNM of \termI[9]_i_1\ : label is "soft_lutpair1267";
  attribute SOFT_HLUTNM of \xsqr4p1[0]_i_1\ : label is "soft_lutpair1081";
  attribute SOFT_HLUTNM of \xsqr4p1[10]_i_1\ : label is "soft_lutpair1076";
  attribute SOFT_HLUTNM of \xsqr4p1[11]_i_1\ : label is "soft_lutpair1076";
  attribute SOFT_HLUTNM of \xsqr4p1[12]_i_1\ : label is "soft_lutpair1075";
  attribute SOFT_HLUTNM of \xsqr4p1[13]_i_1\ : label is "soft_lutpair1075";
  attribute SOFT_HLUTNM of \xsqr4p1[14]_i_1\ : label is "soft_lutpair1074";
  attribute SOFT_HLUTNM of \xsqr4p1[15]_i_1\ : label is "soft_lutpair1074";
  attribute SOFT_HLUTNM of \xsqr4p1[16]_i_1\ : label is "soft_lutpair1073";
  attribute SOFT_HLUTNM of \xsqr4p1[17]_i_1\ : label is "soft_lutpair1073";
  attribute SOFT_HLUTNM of \xsqr4p1[2]_i_1\ : label is "soft_lutpair1080";
  attribute SOFT_HLUTNM of \xsqr4p1[3]_i_1\ : label is "soft_lutpair1080";
  attribute SOFT_HLUTNM of \xsqr4p1[4]_i_1\ : label is "soft_lutpair1079";
  attribute SOFT_HLUTNM of \xsqr4p1[5]_i_1\ : label is "soft_lutpair1079";
  attribute SOFT_HLUTNM of \xsqr4p1[6]_i_1\ : label is "soft_lutpair1078";
  attribute SOFT_HLUTNM of \xsqr4p1[7]_i_1\ : label is "soft_lutpair1078";
  attribute SOFT_HLUTNM of \xsqr4p1[8]_i_1\ : label is "soft_lutpair1077";
  attribute SOFT_HLUTNM of \xsqr4p1[9]_i_1\ : label is "soft_lutpair1077";
  attribute SOFT_HLUTNM of \xsqr4p2[0]_i_1\ : label is "soft_lutpair1089";
  attribute SOFT_HLUTNM of \xsqr4p2[10]_i_1\ : label is "soft_lutpair1085";
  attribute SOFT_HLUTNM of \xsqr4p2[11]_i_1\ : label is "soft_lutpair1084";
  attribute SOFT_HLUTNM of \xsqr4p2[12]_i_1\ : label is "soft_lutpair1084";
  attribute SOFT_HLUTNM of \xsqr4p2[13]_i_1\ : label is "soft_lutpair1083";
  attribute SOFT_HLUTNM of \xsqr4p2[14]_i_1\ : label is "soft_lutpair1083";
  attribute SOFT_HLUTNM of \xsqr4p2[15]_i_1\ : label is "soft_lutpair1081";
  attribute SOFT_HLUTNM of \xsqr4p2[16]_i_1\ : label is "soft_lutpair1082";
  attribute SOFT_HLUTNM of \xsqr4p2[17]_i_1\ : label is "soft_lutpair1082";
  attribute SOFT_HLUTNM of \xsqr4p2[2]_i_1\ : label is "soft_lutpair1089";
  attribute SOFT_HLUTNM of \xsqr4p2[3]_i_1\ : label is "soft_lutpair1088";
  attribute SOFT_HLUTNM of \xsqr4p2[4]_i_1\ : label is "soft_lutpair1088";
  attribute SOFT_HLUTNM of \xsqr4p2[5]_i_1\ : label is "soft_lutpair1087";
  attribute SOFT_HLUTNM of \xsqr4p2[6]_i_1\ : label is "soft_lutpair1087";
  attribute SOFT_HLUTNM of \xsqr4p2[7]_i_1\ : label is "soft_lutpair1086";
  attribute SOFT_HLUTNM of \xsqr4p2[8]_i_1\ : label is "soft_lutpair1086";
  attribute SOFT_HLUTNM of \xsqr4p2[9]_i_1\ : label is "soft_lutpair1085";
  attribute SOFT_HLUTNM of \xsqr[0]_i_1\ : label is "soft_lutpair964";
  attribute SOFT_HLUTNM of \xsqr[10]_i_1\ : label is "soft_lutpair1052";
  attribute SOFT_HLUTNM of \xsqr[11]_i_1\ : label is "soft_lutpair1051";
  attribute HLUTNM : string;
  attribute HLUTNM of \xsqr[11]_i_15\ : label is "lutpair3";
  attribute HLUTNM of \xsqr[11]_i_16\ : label is "lutpair2";
  attribute HLUTNM of \xsqr[11]_i_17\ : label is "lutpair1";
  attribute HLUTNM of \xsqr[11]_i_6\ : label is "lutpair3";
  attribute HLUTNM of \xsqr[11]_i_7\ : label is "lutpair2";
  attribute HLUTNM of \xsqr[11]_i_8\ : label is "lutpair1";
  attribute SOFT_HLUTNM of \xsqr[12]_i_1\ : label is "soft_lutpair1051";
  attribute SOFT_HLUTNM of \xsqr[13]_i_1\ : label is "soft_lutpair1050";
  attribute SOFT_HLUTNM of \xsqr[14]_i_1\ : label is "soft_lutpair1050";
  attribute SOFT_HLUTNM of \xsqr[15]_i_1\ : label is "soft_lutpair1049";
  attribute SOFT_HLUTNM of \xsqr[16]_i_1\ : label is "soft_lutpair1049";
  attribute SOFT_HLUTNM of \xsqr[17]_i_1\ : label is "soft_lutpair1048";
  attribute HLUTNM of \xsqr[17]_i_11\ : label is "lutpair4";
  attribute SOFT_HLUTNM of \xsqr[17]_i_43\ : label is "soft_lutpair990";
  attribute HLUTNM of \xsqr[17]_i_5\ : label is "lutpair4";
  attribute SOFT_HLUTNM of \xsqr[18]_i_1\ : label is "soft_lutpair966";
  attribute SOFT_HLUTNM of \xsqr[20]_i_1\ : label is "soft_lutpair1048";
  attribute SOFT_HLUTNM of \xsqr[21]_i_1\ : label is "soft_lutpair866";
  attribute HLUTNM of \xsqr[21]_i_14\ : label is "lutpair5";
  attribute SOFT_HLUTNM of \xsqr[21]_i_32\ : label is "soft_lutpair967";
  attribute SOFT_HLUTNM of \xsqr[21]_i_33\ : label is "soft_lutpair966";
  attribute HLUTNM of \xsqr[21]_i_7\ : label is "lutpair5";
  attribute SOFT_HLUTNM of \xsqr[22]_i_1\ : label is "soft_lutpair1047";
  attribute SOFT_HLUTNM of \xsqr[23]_i_1\ : label is "soft_lutpair1047";
  attribute SOFT_HLUTNM of \xsqr[24]_i_1\ : label is "soft_lutpair1046";
  attribute SOFT_HLUTNM of \xsqr[25]_i_1\ : label is "soft_lutpair1046";
  attribute SOFT_HLUTNM of \xsqr[26]_i_1\ : label is "soft_lutpair1045";
  attribute SOFT_HLUTNM of \xsqr[27]_i_1\ : label is "soft_lutpair1045";
  attribute SOFT_HLUTNM of \xsqr[28]_i_1\ : label is "soft_lutpair1044";
  attribute SOFT_HLUTNM of \xsqr[29]_i_1\ : label is "soft_lutpair1044";
  attribute HLUTNM of \xsqr[29]_i_15\ : label is "lutpair8";
  attribute HLUTNM of \xsqr[29]_i_16\ : label is "lutpair7";
  attribute HLUTNM of \xsqr[29]_i_17\ : label is "lutpair6";
  attribute HLUTNM of \xsqr[29]_i_6\ : label is "lutpair8";
  attribute HLUTNM of \xsqr[29]_i_7\ : label is "lutpair7";
  attribute HLUTNM of \xsqr[29]_i_8\ : label is "lutpair6";
  attribute SOFT_HLUTNM of \xsqr[2]_i_1\ : label is "soft_lutpair1055";
  attribute SOFT_HLUTNM of \xsqr[30]_i_1\ : label is "soft_lutpair1043";
  attribute SOFT_HLUTNM of \xsqr[31]_i_1\ : label is "soft_lutpair1043";
  attribute SOFT_HLUTNM of \xsqr[32]_i_1\ : label is "soft_lutpair1042";
  attribute SOFT_HLUTNM of \xsqr[33]_i_1\ : label is "soft_lutpair1042";
  attribute SOFT_HLUTNM of \xsqr[34]_i_1\ : label is "soft_lutpair1041";
  attribute SOFT_HLUTNM of \xsqr[35]_i_1\ : label is "soft_lutpair1041";
  attribute HLUTNM of \xsqr[35]_i_11\ : label is "lutpair9";
  attribute SOFT_HLUTNM of \xsqr[35]_i_43\ : label is "soft_lutpair997";
  attribute HLUTNM of \xsqr[35]_i_5\ : label is "lutpair9";
  attribute SOFT_HLUTNM of \xsqr[36]_i_1\ : label is "soft_lutpair968";
  attribute SOFT_HLUTNM of \xsqr[38]_i_1\ : label is "soft_lutpair1040";
  attribute SOFT_HLUTNM of \xsqr[39]_i_1\ : label is "soft_lutpair865";
  attribute HLUTNM of \xsqr[39]_i_14\ : label is "lutpair10";
  attribute SOFT_HLUTNM of \xsqr[39]_i_32\ : label is "soft_lutpair969";
  attribute SOFT_HLUTNM of \xsqr[39]_i_33\ : label is "soft_lutpair968";
  attribute HLUTNM of \xsqr[39]_i_7\ : label is "lutpair10";
  attribute SOFT_HLUTNM of \xsqr[3]_i_1\ : label is "soft_lutpair866";
  attribute HLUTNM of \xsqr[3]_i_14\ : label is "lutpair0";
  attribute SOFT_HLUTNM of \xsqr[3]_i_32\ : label is "soft_lutpair965";
  attribute SOFT_HLUTNM of \xsqr[3]_i_33\ : label is "soft_lutpair964";
  attribute HLUTNM of \xsqr[3]_i_7\ : label is "lutpair0";
  attribute SOFT_HLUTNM of \xsqr[40]_i_1\ : label is "soft_lutpair1040";
  attribute SOFT_HLUTNM of \xsqr[41]_i_1\ : label is "soft_lutpair1039";
  attribute SOFT_HLUTNM of \xsqr[42]_i_1\ : label is "soft_lutpair1039";
  attribute SOFT_HLUTNM of \xsqr[43]_i_1\ : label is "soft_lutpair1038";
  attribute SOFT_HLUTNM of \xsqr[44]_i_1\ : label is "soft_lutpair1038";
  attribute SOFT_HLUTNM of \xsqr[45]_i_1\ : label is "soft_lutpair1037";
  attribute SOFT_HLUTNM of \xsqr[46]_i_1\ : label is "soft_lutpair1037";
  attribute SOFT_HLUTNM of \xsqr[47]_i_1\ : label is "soft_lutpair1036";
  attribute HLUTNM of \xsqr[47]_i_15\ : label is "lutpair13";
  attribute HLUTNM of \xsqr[47]_i_16\ : label is "lutpair12";
  attribute HLUTNM of \xsqr[47]_i_17\ : label is "lutpair11";
  attribute HLUTNM of \xsqr[47]_i_6\ : label is "lutpair13";
  attribute HLUTNM of \xsqr[47]_i_7\ : label is "lutpair12";
  attribute HLUTNM of \xsqr[47]_i_8\ : label is "lutpair11";
  attribute SOFT_HLUTNM of \xsqr[48]_i_1\ : label is "soft_lutpair1036";
  attribute SOFT_HLUTNM of \xsqr[49]_i_1\ : label is "soft_lutpair1035";
  attribute SOFT_HLUTNM of \xsqr[4]_i_1\ : label is "soft_lutpair1055";
  attribute SOFT_HLUTNM of \xsqr[50]_i_1\ : label is "soft_lutpair1035";
  attribute SOFT_HLUTNM of \xsqr[51]_i_1\ : label is "soft_lutpair1034";
  attribute SOFT_HLUTNM of \xsqr[52]_i_1\ : label is "soft_lutpair1034";
  attribute SOFT_HLUTNM of \xsqr[53]_i_1\ : label is "soft_lutpair1033";
  attribute HLUTNM of \xsqr[53]_i_11\ : label is "lutpair14";
  attribute SOFT_HLUTNM of \xsqr[53]_i_43\ : label is "soft_lutpair1004";
  attribute HLUTNM of \xsqr[53]_i_5\ : label is "lutpair14";
  attribute SOFT_HLUTNM of \xsqr[54]_i_1\ : label is "soft_lutpair970";
  attribute SOFT_HLUTNM of \xsqr[56]_i_1\ : label is "soft_lutpair1033";
  attribute SOFT_HLUTNM of \xsqr[57]_i_1\ : label is "soft_lutpair865";
  attribute HLUTNM of \xsqr[57]_i_14\ : label is "lutpair15";
  attribute SOFT_HLUTNM of \xsqr[57]_i_32\ : label is "soft_lutpair971";
  attribute SOFT_HLUTNM of \xsqr[57]_i_33\ : label is "soft_lutpair970";
  attribute HLUTNM of \xsqr[57]_i_7\ : label is "lutpair15";
  attribute SOFT_HLUTNM of \xsqr[58]_i_1\ : label is "soft_lutpair1032";
  attribute SOFT_HLUTNM of \xsqr[59]_i_1\ : label is "soft_lutpair1032";
  attribute SOFT_HLUTNM of \xsqr[5]_i_1\ : label is "soft_lutpair1054";
  attribute SOFT_HLUTNM of \xsqr[60]_i_1\ : label is "soft_lutpair1031";
  attribute SOFT_HLUTNM of \xsqr[61]_i_1\ : label is "soft_lutpair1031";
  attribute SOFT_HLUTNM of \xsqr[62]_i_1\ : label is "soft_lutpair1030";
  attribute SOFT_HLUTNM of \xsqr[63]_i_1\ : label is "soft_lutpair1030";
  attribute SOFT_HLUTNM of \xsqr[64]_i_1\ : label is "soft_lutpair1029";
  attribute SOFT_HLUTNM of \xsqr[65]_i_1\ : label is "soft_lutpair1029";
  attribute HLUTNM of \xsqr[65]_i_15\ : label is "lutpair18";
  attribute HLUTNM of \xsqr[65]_i_16\ : label is "lutpair17";
  attribute HLUTNM of \xsqr[65]_i_17\ : label is "lutpair16";
  attribute HLUTNM of \xsqr[65]_i_6\ : label is "lutpair18";
  attribute HLUTNM of \xsqr[65]_i_7\ : label is "lutpair17";
  attribute HLUTNM of \xsqr[65]_i_8\ : label is "lutpair16";
  attribute SOFT_HLUTNM of \xsqr[66]_i_1\ : label is "soft_lutpair1028";
  attribute SOFT_HLUTNM of \xsqr[67]_i_1\ : label is "soft_lutpair1028";
  attribute SOFT_HLUTNM of \xsqr[68]_i_1\ : label is "soft_lutpair1027";
  attribute SOFT_HLUTNM of \xsqr[69]_i_1\ : label is "soft_lutpair1027";
  attribute SOFT_HLUTNM of \xsqr[6]_i_1\ : label is "soft_lutpair1054";
  attribute SOFT_HLUTNM of \xsqr[70]_i_1\ : label is "soft_lutpair1026";
  attribute SOFT_HLUTNM of \xsqr[71]_i_1\ : label is "soft_lutpair1026";
  attribute HLUTNM of \xsqr[71]_i_11\ : label is "lutpair19";
  attribute SOFT_HLUTNM of \xsqr[71]_i_43\ : label is "soft_lutpair1011";
  attribute HLUTNM of \xsqr[71]_i_5\ : label is "lutpair19";
  attribute SOFT_HLUTNM of \xsqr[72]_i_1\ : label is "soft_lutpair972";
  attribute SOFT_HLUTNM of \xsqr[74]_i_1\ : label is "soft_lutpair1025";
  attribute SOFT_HLUTNM of \xsqr[75]_i_1\ : label is "soft_lutpair864";
  attribute HLUTNM of \xsqr[75]_i_14\ : label is "lutpair20";
  attribute SOFT_HLUTNM of \xsqr[75]_i_32\ : label is "soft_lutpair973";
  attribute SOFT_HLUTNM of \xsqr[75]_i_33\ : label is "soft_lutpair972";
  attribute HLUTNM of \xsqr[75]_i_7\ : label is "lutpair20";
  attribute SOFT_HLUTNM of \xsqr[76]_i_1\ : label is "soft_lutpair1025";
  attribute SOFT_HLUTNM of \xsqr[77]_i_1\ : label is "soft_lutpair1024";
  attribute SOFT_HLUTNM of \xsqr[78]_i_1\ : label is "soft_lutpair1024";
  attribute SOFT_HLUTNM of \xsqr[79]_i_1\ : label is "soft_lutpair1023";
  attribute SOFT_HLUTNM of \xsqr[7]_i_1\ : label is "soft_lutpair1053";
  attribute SOFT_HLUTNM of \xsqr[80]_i_1\ : label is "soft_lutpair1023";
  attribute SOFT_HLUTNM of \xsqr[81]_i_1\ : label is "soft_lutpair1022";
  attribute SOFT_HLUTNM of \xsqr[82]_i_1\ : label is "soft_lutpair1022";
  attribute SOFT_HLUTNM of \xsqr[83]_i_1\ : label is "soft_lutpair1021";
  attribute HLUTNM of \xsqr[83]_i_15\ : label is "lutpair23";
  attribute HLUTNM of \xsqr[83]_i_16\ : label is "lutpair22";
  attribute HLUTNM of \xsqr[83]_i_17\ : label is "lutpair21";
  attribute HLUTNM of \xsqr[83]_i_6\ : label is "lutpair23";
  attribute HLUTNM of \xsqr[83]_i_7\ : label is "lutpair22";
  attribute HLUTNM of \xsqr[83]_i_8\ : label is "lutpair21";
  attribute SOFT_HLUTNM of \xsqr[84]_i_1\ : label is "soft_lutpair1021";
  attribute SOFT_HLUTNM of \xsqr[85]_i_1\ : label is "soft_lutpair1020";
  attribute SOFT_HLUTNM of \xsqr[86]_i_1\ : label is "soft_lutpair1020";
  attribute SOFT_HLUTNM of \xsqr[87]_i_1\ : label is "soft_lutpair864";
  attribute SOFT_HLUTNM of \xsqr[88]_i_1\ : label is "soft_lutpair1019";
  attribute HLUTNM of \xsqr[89]_i_12\ : label is "lutpair24";
  attribute SOFT_HLUTNM of \xsqr[89]_i_2\ : label is "soft_lutpair1019";
  attribute SOFT_HLUTNM of \xsqr[89]_i_44\ : label is "soft_lutpair1018";
  attribute HLUTNM of \xsqr[89]_i_6\ : label is "lutpair24";
  attribute SOFT_HLUTNM of \xsqr[8]_i_1\ : label is "soft_lutpair1053";
  attribute SOFT_HLUTNM of \xsqr[9]_i_1\ : label is "soft_lutpair1052";
  attribute ADDER_THRESHOLD of \xsqr_reg[11]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xsqr_reg[17]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xsqr_reg[29]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xsqr_reg[35]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xsqr_reg[47]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xsqr_reg[53]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xsqr_reg[65]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xsqr_reg[71]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xsqr_reg[83]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xsqr_reg[89]_i_3\ : label is 35;
  attribute SOFT_HLUTNM of \xy4p1[0]_i_1\ : label is "soft_lutpair1341";
  attribute SOFT_HLUTNM of \xy4p1[10]_i_1\ : label is "soft_lutpair1336";
  attribute SOFT_HLUTNM of \xy4p1[11]_i_1\ : label is "soft_lutpair1336";
  attribute SOFT_HLUTNM of \xy4p1[12]_i_1\ : label is "soft_lutpair1335";
  attribute SOFT_HLUTNM of \xy4p1[13]_i_1\ : label is "soft_lutpair1335";
  attribute SOFT_HLUTNM of \xy4p1[14]_i_1\ : label is "soft_lutpair1334";
  attribute SOFT_HLUTNM of \xy4p1[15]_i_1\ : label is "soft_lutpair1334";
  attribute SOFT_HLUTNM of \xy4p1[16]_i_1\ : label is "soft_lutpair1333";
  attribute SOFT_HLUTNM of \xy4p1[17]_i_1\ : label is "soft_lutpair1333";
  attribute SOFT_HLUTNM of \xy4p1[1]_i_1\ : label is "soft_lutpair1341";
  attribute SOFT_HLUTNM of \xy4p1[2]_i_1\ : label is "soft_lutpair1340";
  attribute SOFT_HLUTNM of \xy4p1[3]_i_1\ : label is "soft_lutpair1340";
  attribute SOFT_HLUTNM of \xy4p1[4]_i_1\ : label is "soft_lutpair1339";
  attribute SOFT_HLUTNM of \xy4p1[5]_i_1\ : label is "soft_lutpair1339";
  attribute SOFT_HLUTNM of \xy4p1[6]_i_1\ : label is "soft_lutpair1338";
  attribute SOFT_HLUTNM of \xy4p1[7]_i_1\ : label is "soft_lutpair1338";
  attribute SOFT_HLUTNM of \xy4p1[8]_i_1\ : label is "soft_lutpair1337";
  attribute SOFT_HLUTNM of \xy4p1[9]_i_1\ : label is "soft_lutpair1337";
  attribute SOFT_HLUTNM of \xy4p2[0]_i_1\ : label is "soft_lutpair1350";
  attribute SOFT_HLUTNM of \xy4p2[10]_i_1\ : label is "soft_lutpair1345";
  attribute SOFT_HLUTNM of \xy4p2[11]_i_1\ : label is "soft_lutpair1345";
  attribute SOFT_HLUTNM of \xy4p2[12]_i_1\ : label is "soft_lutpair1344";
  attribute SOFT_HLUTNM of \xy4p2[13]_i_1\ : label is "soft_lutpair1344";
  attribute SOFT_HLUTNM of \xy4p2[14]_i_1\ : label is "soft_lutpair1343";
  attribute SOFT_HLUTNM of \xy4p2[15]_i_1\ : label is "soft_lutpair1343";
  attribute SOFT_HLUTNM of \xy4p2[16]_i_1\ : label is "soft_lutpair1342";
  attribute SOFT_HLUTNM of \xy4p2[17]_i_1\ : label is "soft_lutpair1342";
  attribute SOFT_HLUTNM of \xy4p2[1]_i_1\ : label is "soft_lutpair1350";
  attribute SOFT_HLUTNM of \xy4p2[2]_i_1\ : label is "soft_lutpair1349";
  attribute SOFT_HLUTNM of \xy4p2[3]_i_1\ : label is "soft_lutpair1349";
  attribute SOFT_HLUTNM of \xy4p2[4]_i_1\ : label is "soft_lutpair1348";
  attribute SOFT_HLUTNM of \xy4p2[5]_i_1\ : label is "soft_lutpair1348";
  attribute SOFT_HLUTNM of \xy4p2[6]_i_1\ : label is "soft_lutpair1347";
  attribute SOFT_HLUTNM of \xy4p2[7]_i_1\ : label is "soft_lutpair1347";
  attribute SOFT_HLUTNM of \xy4p2[8]_i_1\ : label is "soft_lutpair1346";
  attribute SOFT_HLUTNM of \xy4p2[9]_i_1\ : label is "soft_lutpair1346";
  attribute SOFT_HLUTNM of \xy[0]_i_1\ : label is "soft_lutpair1313";
  attribute SOFT_HLUTNM of \xy[10]_i_1\ : label is "soft_lutpair1309";
  attribute SOFT_HLUTNM of \xy[11]_i_1\ : label is "soft_lutpair1308";
  attribute HLUTNM of \xy[11]_i_15\ : label is "lutpair52";
  attribute HLUTNM of \xy[11]_i_16\ : label is "lutpair51";
  attribute HLUTNM of \xy[11]_i_17\ : label is "lutpair50";
  attribute HLUTNM of \xy[11]_i_6\ : label is "lutpair52";
  attribute HLUTNM of \xy[11]_i_7\ : label is "lutpair51";
  attribute HLUTNM of \xy[11]_i_8\ : label is "lutpair50";
  attribute SOFT_HLUTNM of \xy[12]_i_1\ : label is "soft_lutpair1308";
  attribute SOFT_HLUTNM of \xy[13]_i_1\ : label is "soft_lutpair1307";
  attribute SOFT_HLUTNM of \xy[14]_i_1\ : label is "soft_lutpair1307";
  attribute SOFT_HLUTNM of \xy[15]_i_1\ : label is "soft_lutpair1305";
  attribute SOFT_HLUTNM of \xy[16]_i_1\ : label is "soft_lutpair1306";
  attribute SOFT_HLUTNM of \xy[17]_i_1\ : label is "soft_lutpair1306";
  attribute HLUTNM of \xy[17]_i_11\ : label is "lutpair53";
  attribute SOFT_HLUTNM of \xy[17]_i_37\ : label is "soft_lutpair990";
  attribute HLUTNM of \xy[17]_i_5\ : label is "lutpair53";
  attribute SOFT_HLUTNM of \xy[17]_i_50\ : label is "soft_lutpair987";
  attribute SOFT_HLUTNM of \xy[17]_i_51\ : label is "soft_lutpair989";
  attribute SOFT_HLUTNM of \xy[17]_i_52\ : label is "soft_lutpair989";
  attribute SOFT_HLUTNM of \xy[17]_i_53\ : label is "soft_lutpair986";
  attribute SOFT_HLUTNM of \xy[17]_i_54\ : label is "soft_lutpair988";
  attribute SOFT_HLUTNM of \xy[17]_i_55\ : label is "soft_lutpair974";
  attribute SOFT_HLUTNM of \xy[18]_i_1\ : label is "soft_lutpair1305";
  attribute SOFT_HLUTNM of \xy[19]_i_1\ : label is "soft_lutpair1304";
  attribute SOFT_HLUTNM of \xy[1]_i_1\ : label is "soft_lutpair1313";
  attribute SOFT_HLUTNM of \xy[20]_i_1\ : label is "soft_lutpair1304";
  attribute SOFT_HLUTNM of \xy[21]_i_1\ : label is "soft_lutpair914";
  attribute SOFT_HLUTNM of \xy[21]_i_34\ : label is "soft_lutpair967";
  attribute SOFT_HLUTNM of \xy[21]_i_35\ : label is "soft_lutpair992";
  attribute SOFT_HLUTNM of \xy[21]_i_36\ : label is "soft_lutpair991";
  attribute SOFT_HLUTNM of \xy[21]_i_37\ : label is "soft_lutpair977";
  attribute SOFT_HLUTNM of \xy[21]_i_38\ : label is "soft_lutpair994";
  attribute SOFT_HLUTNM of \xy[21]_i_39\ : label is "soft_lutpair992";
  attribute SOFT_HLUTNM of \xy[21]_i_40\ : label is "soft_lutpair991";
  attribute SOFT_HLUTNM of \xy[21]_i_41\ : label is "soft_lutpair993";
  attribute SOFT_HLUTNM of \xy[22]_i_1\ : label is "soft_lutpair1303";
  attribute SOFT_HLUTNM of \xy[23]_i_1\ : label is "soft_lutpair1303";
  attribute SOFT_HLUTNM of \xy[24]_i_1\ : label is "soft_lutpair1302";
  attribute SOFT_HLUTNM of \xy[25]_i_1\ : label is "soft_lutpair1302";
  attribute SOFT_HLUTNM of \xy[26]_i_1\ : label is "soft_lutpair1301";
  attribute SOFT_HLUTNM of \xy[27]_i_1\ : label is "soft_lutpair1301";
  attribute SOFT_HLUTNM of \xy[28]_i_1\ : label is "soft_lutpair1300";
  attribute SOFT_HLUTNM of \xy[29]_i_1\ : label is "soft_lutpair1300";
  attribute HLUTNM of \xy[29]_i_15\ : label is "lutpair56";
  attribute HLUTNM of \xy[29]_i_16\ : label is "lutpair55";
  attribute HLUTNM of \xy[29]_i_17\ : label is "lutpair54";
  attribute HLUTNM of \xy[29]_i_6\ : label is "lutpair56";
  attribute HLUTNM of \xy[29]_i_7\ : label is "lutpair55";
  attribute HLUTNM of \xy[29]_i_8\ : label is "lutpair54";
  attribute SOFT_HLUTNM of \xy[2]_i_1\ : label is "soft_lutpair1312";
  attribute SOFT_HLUTNM of \xy[30]_i_1\ : label is "soft_lutpair1299";
  attribute SOFT_HLUTNM of \xy[31]_i_1\ : label is "soft_lutpair1299";
  attribute SOFT_HLUTNM of \xy[32]_i_1\ : label is "soft_lutpair1298";
  attribute SOFT_HLUTNM of \xy[33]_i_1\ : label is "soft_lutpair1298";
  attribute SOFT_HLUTNM of \xy[34]_i_1\ : label is "soft_lutpair1297";
  attribute SOFT_HLUTNM of \xy[35]_i_1\ : label is "soft_lutpair1297";
  attribute HLUTNM of \xy[35]_i_11\ : label is "lutpair57";
  attribute SOFT_HLUTNM of \xy[35]_i_37\ : label is "soft_lutpair997";
  attribute HLUTNM of \xy[35]_i_5\ : label is "lutpair57";
  attribute SOFT_HLUTNM of \xy[35]_i_50\ : label is "soft_lutpair994";
  attribute SOFT_HLUTNM of \xy[35]_i_51\ : label is "soft_lutpair996";
  attribute SOFT_HLUTNM of \xy[35]_i_52\ : label is "soft_lutpair996";
  attribute SOFT_HLUTNM of \xy[35]_i_53\ : label is "soft_lutpair993";
  attribute SOFT_HLUTNM of \xy[35]_i_54\ : label is "soft_lutpair995";
  attribute SOFT_HLUTNM of \xy[35]_i_55\ : label is "soft_lutpair976";
  attribute SOFT_HLUTNM of \xy[36]_i_1\ : label is "soft_lutpair1296";
  attribute SOFT_HLUTNM of \xy[37]_i_1\ : label is "soft_lutpair1296";
  attribute SOFT_HLUTNM of \xy[38]_i_1\ : label is "soft_lutpair1295";
  attribute SOFT_HLUTNM of \xy[39]_i_1\ : label is "soft_lutpair913";
  attribute SOFT_HLUTNM of \xy[39]_i_34\ : label is "soft_lutpair969";
  attribute SOFT_HLUTNM of \xy[39]_i_35\ : label is "soft_lutpair999";
  attribute SOFT_HLUTNM of \xy[39]_i_36\ : label is "soft_lutpair998";
  attribute SOFT_HLUTNM of \xy[39]_i_37\ : label is "soft_lutpair979";
  attribute SOFT_HLUTNM of \xy[39]_i_38\ : label is "soft_lutpair1001";
  attribute SOFT_HLUTNM of \xy[39]_i_39\ : label is "soft_lutpair999";
  attribute SOFT_HLUTNM of \xy[39]_i_40\ : label is "soft_lutpair998";
  attribute SOFT_HLUTNM of \xy[39]_i_41\ : label is "soft_lutpair1000";
  attribute SOFT_HLUTNM of \xy[3]_i_1\ : label is "soft_lutpair914";
  attribute SOFT_HLUTNM of \xy[3]_i_34\ : label is "soft_lutpair965";
  attribute SOFT_HLUTNM of \xy[3]_i_35\ : label is "soft_lutpair985";
  attribute SOFT_HLUTNM of \xy[3]_i_36\ : label is "soft_lutpair984";
  attribute SOFT_HLUTNM of \xy[3]_i_37\ : label is "soft_lutpair975";
  attribute SOFT_HLUTNM of \xy[3]_i_38\ : label is "soft_lutpair987";
  attribute SOFT_HLUTNM of \xy[3]_i_39\ : label is "soft_lutpair985";
  attribute SOFT_HLUTNM of \xy[3]_i_40\ : label is "soft_lutpair984";
  attribute SOFT_HLUTNM of \xy[3]_i_41\ : label is "soft_lutpair986";
  attribute SOFT_HLUTNM of \xy[40]_i_1\ : label is "soft_lutpair1295";
  attribute SOFT_HLUTNM of \xy[41]_i_1\ : label is "soft_lutpair1294";
  attribute SOFT_HLUTNM of \xy[42]_i_1\ : label is "soft_lutpair1294";
  attribute SOFT_HLUTNM of \xy[43]_i_1\ : label is "soft_lutpair1293";
  attribute SOFT_HLUTNM of \xy[44]_i_1\ : label is "soft_lutpair1293";
  attribute SOFT_HLUTNM of \xy[45]_i_1\ : label is "soft_lutpair1292";
  attribute SOFT_HLUTNM of \xy[46]_i_1\ : label is "soft_lutpair1292";
  attribute SOFT_HLUTNM of \xy[47]_i_1\ : label is "soft_lutpair1291";
  attribute HLUTNM of \xy[47]_i_15\ : label is "lutpair60";
  attribute HLUTNM of \xy[47]_i_16\ : label is "lutpair59";
  attribute HLUTNM of \xy[47]_i_17\ : label is "lutpair58";
  attribute HLUTNM of \xy[47]_i_6\ : label is "lutpair60";
  attribute HLUTNM of \xy[47]_i_7\ : label is "lutpair59";
  attribute HLUTNM of \xy[47]_i_8\ : label is "lutpair58";
  attribute SOFT_HLUTNM of \xy[48]_i_1\ : label is "soft_lutpair1291";
  attribute SOFT_HLUTNM of \xy[49]_i_1\ : label is "soft_lutpair1290";
  attribute SOFT_HLUTNM of \xy[4]_i_1\ : label is "soft_lutpair1312";
  attribute SOFT_HLUTNM of \xy[50]_i_1\ : label is "soft_lutpair1290";
  attribute SOFT_HLUTNM of \xy[51]_i_1\ : label is "soft_lutpair1288";
  attribute SOFT_HLUTNM of \xy[52]_i_1\ : label is "soft_lutpair1289";
  attribute SOFT_HLUTNM of \xy[53]_i_1\ : label is "soft_lutpair1289";
  attribute HLUTNM of \xy[53]_i_11\ : label is "lutpair61";
  attribute SOFT_HLUTNM of \xy[53]_i_37\ : label is "soft_lutpair1004";
  attribute HLUTNM of \xy[53]_i_5\ : label is "lutpair61";
  attribute SOFT_HLUTNM of \xy[53]_i_50\ : label is "soft_lutpair1001";
  attribute SOFT_HLUTNM of \xy[53]_i_51\ : label is "soft_lutpair1003";
  attribute SOFT_HLUTNM of \xy[53]_i_52\ : label is "soft_lutpair1003";
  attribute SOFT_HLUTNM of \xy[53]_i_53\ : label is "soft_lutpair1000";
  attribute SOFT_HLUTNM of \xy[53]_i_54\ : label is "soft_lutpair1002";
  attribute SOFT_HLUTNM of \xy[53]_i_55\ : label is "soft_lutpair978";
  attribute SOFT_HLUTNM of \xy[54]_i_1\ : label is "soft_lutpair1288";
  attribute SOFT_HLUTNM of \xy[55]_i_1\ : label is "soft_lutpair1287";
  attribute SOFT_HLUTNM of \xy[56]_i_1\ : label is "soft_lutpair1287";
  attribute SOFT_HLUTNM of \xy[57]_i_1\ : label is "soft_lutpair913";
  attribute SOFT_HLUTNM of \xy[57]_i_34\ : label is "soft_lutpair971";
  attribute SOFT_HLUTNM of \xy[57]_i_35\ : label is "soft_lutpair1006";
  attribute SOFT_HLUTNM of \xy[57]_i_36\ : label is "soft_lutpair1005";
  attribute SOFT_HLUTNM of \xy[57]_i_37\ : label is "soft_lutpair981";
  attribute SOFT_HLUTNM of \xy[57]_i_38\ : label is "soft_lutpair1008";
  attribute SOFT_HLUTNM of \xy[57]_i_39\ : label is "soft_lutpair1006";
  attribute SOFT_HLUTNM of \xy[57]_i_40\ : label is "soft_lutpair1005";
  attribute SOFT_HLUTNM of \xy[57]_i_41\ : label is "soft_lutpair1007";
  attribute SOFT_HLUTNM of \xy[58]_i_1\ : label is "soft_lutpair1286";
  attribute SOFT_HLUTNM of \xy[59]_i_1\ : label is "soft_lutpair1286";
  attribute SOFT_HLUTNM of \xy[5]_i_1\ : label is "soft_lutpair1311";
  attribute SOFT_HLUTNM of \xy[60]_i_1\ : label is "soft_lutpair1285";
  attribute SOFT_HLUTNM of \xy[61]_i_1\ : label is "soft_lutpair1285";
  attribute SOFT_HLUTNM of \xy[62]_i_1\ : label is "soft_lutpair1284";
  attribute SOFT_HLUTNM of \xy[63]_i_1\ : label is "soft_lutpair1284";
  attribute SOFT_HLUTNM of \xy[64]_i_1\ : label is "soft_lutpair1283";
  attribute SOFT_HLUTNM of \xy[65]_i_1\ : label is "soft_lutpair1283";
  attribute HLUTNM of \xy[65]_i_15\ : label is "lutpair64";
  attribute HLUTNM of \xy[65]_i_16\ : label is "lutpair63";
  attribute HLUTNM of \xy[65]_i_17\ : label is "lutpair62";
  attribute HLUTNM of \xy[65]_i_6\ : label is "lutpair64";
  attribute HLUTNM of \xy[65]_i_7\ : label is "lutpair63";
  attribute HLUTNM of \xy[65]_i_8\ : label is "lutpair62";
  attribute SOFT_HLUTNM of \xy[66]_i_1\ : label is "soft_lutpair1282";
  attribute SOFT_HLUTNM of \xy[67]_i_1\ : label is "soft_lutpair1282";
  attribute SOFT_HLUTNM of \xy[68]_i_1\ : label is "soft_lutpair1281";
  attribute SOFT_HLUTNM of \xy[69]_i_1\ : label is "soft_lutpair1281";
  attribute SOFT_HLUTNM of \xy[6]_i_1\ : label is "soft_lutpair1311";
  attribute SOFT_HLUTNM of \xy[70]_i_1\ : label is "soft_lutpair1280";
  attribute SOFT_HLUTNM of \xy[71]_i_1\ : label is "soft_lutpair1280";
  attribute HLUTNM of \xy[71]_i_11\ : label is "lutpair65";
  attribute SOFT_HLUTNM of \xy[71]_i_37\ : label is "soft_lutpair1011";
  attribute HLUTNM of \xy[71]_i_5\ : label is "lutpair65";
  attribute SOFT_HLUTNM of \xy[71]_i_50\ : label is "soft_lutpair1008";
  attribute SOFT_HLUTNM of \xy[71]_i_51\ : label is "soft_lutpair1010";
  attribute SOFT_HLUTNM of \xy[71]_i_52\ : label is "soft_lutpair1010";
  attribute SOFT_HLUTNM of \xy[71]_i_53\ : label is "soft_lutpair1007";
  attribute SOFT_HLUTNM of \xy[71]_i_54\ : label is "soft_lutpair1009";
  attribute SOFT_HLUTNM of \xy[71]_i_55\ : label is "soft_lutpair980";
  attribute SOFT_HLUTNM of \xy[72]_i_1\ : label is "soft_lutpair1279";
  attribute SOFT_HLUTNM of \xy[73]_i_1\ : label is "soft_lutpair1279";
  attribute SOFT_HLUTNM of \xy[74]_i_1\ : label is "soft_lutpair1278";
  attribute SOFT_HLUTNM of \xy[75]_i_1\ : label is "soft_lutpair912";
  attribute SOFT_HLUTNM of \xy[75]_i_34\ : label is "soft_lutpair973";
  attribute SOFT_HLUTNM of \xy[75]_i_35\ : label is "soft_lutpair1013";
  attribute SOFT_HLUTNM of \xy[75]_i_36\ : label is "soft_lutpair1012";
  attribute SOFT_HLUTNM of \xy[75]_i_37\ : label is "soft_lutpair983";
  attribute SOFT_HLUTNM of \xy[75]_i_38\ : label is "soft_lutpair1015";
  attribute SOFT_HLUTNM of \xy[75]_i_39\ : label is "soft_lutpair1013";
  attribute SOFT_HLUTNM of \xy[75]_i_40\ : label is "soft_lutpair1012";
  attribute SOFT_HLUTNM of \xy[75]_i_41\ : label is "soft_lutpair1014";
  attribute SOFT_HLUTNM of \xy[76]_i_1\ : label is "soft_lutpair1278";
  attribute SOFT_HLUTNM of \xy[77]_i_1\ : label is "soft_lutpair1277";
  attribute SOFT_HLUTNM of \xy[78]_i_1\ : label is "soft_lutpair1277";
  attribute SOFT_HLUTNM of \xy[79]_i_1\ : label is "soft_lutpair1276";
  attribute SOFT_HLUTNM of \xy[7]_i_1\ : label is "soft_lutpair1310";
  attribute SOFT_HLUTNM of \xy[80]_i_1\ : label is "soft_lutpair1276";
  attribute SOFT_HLUTNM of \xy[81]_i_1\ : label is "soft_lutpair1275";
  attribute SOFT_HLUTNM of \xy[82]_i_1\ : label is "soft_lutpair1275";
  attribute SOFT_HLUTNM of \xy[83]_i_1\ : label is "soft_lutpair1274";
  attribute HLUTNM of \xy[83]_i_15\ : label is "lutpair68";
  attribute HLUTNM of \xy[83]_i_16\ : label is "lutpair67";
  attribute HLUTNM of \xy[83]_i_17\ : label is "lutpair66";
  attribute HLUTNM of \xy[83]_i_6\ : label is "lutpair68";
  attribute HLUTNM of \xy[83]_i_7\ : label is "lutpair67";
  attribute HLUTNM of \xy[83]_i_8\ : label is "lutpair66";
  attribute SOFT_HLUTNM of \xy[84]_i_1\ : label is "soft_lutpair1274";
  attribute SOFT_HLUTNM of \xy[85]_i_1\ : label is "soft_lutpair1273";
  attribute SOFT_HLUTNM of \xy[86]_i_1\ : label is "soft_lutpair1273";
  attribute SOFT_HLUTNM of \xy[87]_i_1\ : label is "soft_lutpair912";
  attribute SOFT_HLUTNM of \xy[88]_i_1\ : label is "soft_lutpair1272";
  attribute SOFT_HLUTNM of \xy[89]_i_1\ : label is "soft_lutpair1272";
  attribute HLUTNM of \xy[89]_i_11\ : label is "lutpair69";
  attribute SOFT_HLUTNM of \xy[89]_i_37\ : label is "soft_lutpair1018";
  attribute HLUTNM of \xy[89]_i_5\ : label is "lutpair69";
  attribute SOFT_HLUTNM of \xy[89]_i_50\ : label is "soft_lutpair1015";
  attribute SOFT_HLUTNM of \xy[89]_i_51\ : label is "soft_lutpair1017";
  attribute SOFT_HLUTNM of \xy[89]_i_52\ : label is "soft_lutpair1017";
  attribute SOFT_HLUTNM of \xy[89]_i_53\ : label is "soft_lutpair1014";
  attribute SOFT_HLUTNM of \xy[89]_i_54\ : label is "soft_lutpair1016";
  attribute SOFT_HLUTNM of \xy[89]_i_55\ : label is "soft_lutpair982";
  attribute SOFT_HLUTNM of \xy[8]_i_1\ : label is "soft_lutpair1310";
  attribute SOFT_HLUTNM of \xy[9]_i_1\ : label is "soft_lutpair1309";
  attribute ADDER_THRESHOLD of \xy_reg[11]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xy_reg[17]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xy_reg[29]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xy_reg[35]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xy_reg[47]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xy_reg[53]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xy_reg[65]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xy_reg[71]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xy_reg[83]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \xy_reg[89]_i_2\ : label is 35;
  attribute SOFT_HLUTNM of \ysqr4p1[0]_i_1\ : label is "soft_lutpair1197";
  attribute SOFT_HLUTNM of \ysqr4p1[10]_i_1\ : label is "soft_lutpair1193";
  attribute SOFT_HLUTNM of \ysqr4p1[11]_i_1\ : label is "soft_lutpair1192";
  attribute SOFT_HLUTNM of \ysqr4p1[12]_i_1\ : label is "soft_lutpair1192";
  attribute SOFT_HLUTNM of \ysqr4p1[13]_i_1\ : label is "soft_lutpair1191";
  attribute SOFT_HLUTNM of \ysqr4p1[14]_i_1\ : label is "soft_lutpair1191";
  attribute SOFT_HLUTNM of \ysqr4p1[15]_i_1\ : label is "soft_lutpair1140";
  attribute SOFT_HLUTNM of \ysqr4p1[16]_i_1\ : label is "soft_lutpair1190";
  attribute SOFT_HLUTNM of \ysqr4p1[17]_i_1\ : label is "soft_lutpair1190";
  attribute SOFT_HLUTNM of \ysqr4p1[2]_i_1\ : label is "soft_lutpair1197";
  attribute SOFT_HLUTNM of \ysqr4p1[3]_i_1\ : label is "soft_lutpair1196";
  attribute SOFT_HLUTNM of \ysqr4p1[4]_i_1\ : label is "soft_lutpair1196";
  attribute SOFT_HLUTNM of \ysqr4p1[5]_i_1\ : label is "soft_lutpair1195";
  attribute SOFT_HLUTNM of \ysqr4p1[6]_i_1\ : label is "soft_lutpair1195";
  attribute SOFT_HLUTNM of \ysqr4p1[7]_i_1\ : label is "soft_lutpair1194";
  attribute SOFT_HLUTNM of \ysqr4p1[8]_i_1\ : label is "soft_lutpair1194";
  attribute SOFT_HLUTNM of \ysqr4p1[9]_i_1\ : label is "soft_lutpair1193";
  attribute SOFT_HLUTNM of \ysqr4p2[10]_i_1\ : label is "soft_lutpair1201";
  attribute SOFT_HLUTNM of \ysqr4p2[11]_i_1\ : label is "soft_lutpair1201";
  attribute SOFT_HLUTNM of \ysqr4p2[12]_i_1\ : label is "soft_lutpair1200";
  attribute SOFT_HLUTNM of \ysqr4p2[13]_i_1\ : label is "soft_lutpair1200";
  attribute SOFT_HLUTNM of \ysqr4p2[14]_i_1\ : label is "soft_lutpair1199";
  attribute SOFT_HLUTNM of \ysqr4p2[15]_i_1\ : label is "soft_lutpair1199";
  attribute SOFT_HLUTNM of \ysqr4p2[16]_i_1\ : label is "soft_lutpair1198";
  attribute SOFT_HLUTNM of \ysqr4p2[17]_i_1\ : label is "soft_lutpair1198";
  attribute SOFT_HLUTNM of \ysqr4p2[2]_i_1\ : label is "soft_lutpair1205";
  attribute SOFT_HLUTNM of \ysqr4p2[3]_i_1\ : label is "soft_lutpair1205";
  attribute SOFT_HLUTNM of \ysqr4p2[4]_i_1\ : label is "soft_lutpair1204";
  attribute SOFT_HLUTNM of \ysqr4p2[5]_i_1\ : label is "soft_lutpair1204";
  attribute SOFT_HLUTNM of \ysqr4p2[6]_i_1\ : label is "soft_lutpair1203";
  attribute SOFT_HLUTNM of \ysqr4p2[7]_i_1\ : label is "soft_lutpair1203";
  attribute SOFT_HLUTNM of \ysqr4p2[8]_i_1\ : label is "soft_lutpair1202";
  attribute SOFT_HLUTNM of \ysqr4p2[9]_i_1\ : label is "soft_lutpair1202";
  attribute SOFT_HLUTNM of \ysqr[0]_i_1\ : label is "soft_lutpair1172";
  attribute SOFT_HLUTNM of \ysqr[10]_i_1\ : label is "soft_lutpair1168";
  attribute SOFT_HLUTNM of \ysqr[11]_i_1\ : label is "soft_lutpair1168";
  attribute HLUTNM of \ysqr[11]_i_15\ : label is "lutpair28";
  attribute HLUTNM of \ysqr[11]_i_16\ : label is "lutpair27";
  attribute HLUTNM of \ysqr[11]_i_17\ : label is "lutpair26";
  attribute HLUTNM of \ysqr[11]_i_6\ : label is "lutpair28";
  attribute HLUTNM of \ysqr[11]_i_7\ : label is "lutpair27";
  attribute HLUTNM of \ysqr[11]_i_8\ : label is "lutpair26";
  attribute SOFT_HLUTNM of \ysqr[12]_i_1\ : label is "soft_lutpair1167";
  attribute SOFT_HLUTNM of \ysqr[13]_i_1\ : label is "soft_lutpair1167";
  attribute SOFT_HLUTNM of \ysqr[14]_i_1\ : label is "soft_lutpair1166";
  attribute SOFT_HLUTNM of \ysqr[15]_i_1\ : label is "soft_lutpair1166";
  attribute SOFT_HLUTNM of \ysqr[16]_i_1\ : label is "soft_lutpair1165";
  attribute SOFT_HLUTNM of \ysqr[17]_i_1\ : label is "soft_lutpair1165";
  attribute HLUTNM of \ysqr[17]_i_11\ : label is "lutpair29";
  attribute SOFT_HLUTNM of \ysqr[17]_i_45\ : label is "soft_lutpair988";
  attribute HLUTNM of \ysqr[17]_i_5\ : label is "lutpair29";
  attribute SOFT_HLUTNM of \ysqr[18]_i_1\ : label is "soft_lutpair1164";
  attribute SOFT_HLUTNM of \ysqr[20]_i_1\ : label is "soft_lutpair1164";
  attribute SOFT_HLUTNM of \ysqr[21]_i_1\ : label is "soft_lutpair890";
  attribute HLUTNM of \ysqr[21]_i_14\ : label is "lutpair30";
  attribute SOFT_HLUTNM of \ysqr[21]_i_32\ : label is "soft_lutpair977";
  attribute SOFT_HLUTNM of \ysqr[21]_i_33\ : label is "soft_lutpair976";
  attribute HLUTNM of \ysqr[21]_i_7\ : label is "lutpair30";
  attribute SOFT_HLUTNM of \ysqr[22]_i_1\ : label is "soft_lutpair1163";
  attribute SOFT_HLUTNM of \ysqr[23]_i_1\ : label is "soft_lutpair1163";
  attribute SOFT_HLUTNM of \ysqr[24]_i_1\ : label is "soft_lutpair1162";
  attribute SOFT_HLUTNM of \ysqr[25]_i_1\ : label is "soft_lutpair1162";
  attribute SOFT_HLUTNM of \ysqr[26]_i_1\ : label is "soft_lutpair1161";
  attribute SOFT_HLUTNM of \ysqr[27]_i_1\ : label is "soft_lutpair1161";
  attribute SOFT_HLUTNM of \ysqr[28]_i_1\ : label is "soft_lutpair1160";
  attribute SOFT_HLUTNM of \ysqr[29]_i_1\ : label is "soft_lutpair1160";
  attribute HLUTNM of \ysqr[29]_i_15\ : label is "lutpair33";
  attribute HLUTNM of \ysqr[29]_i_16\ : label is "lutpair32";
  attribute HLUTNM of \ysqr[29]_i_17\ : label is "lutpair31";
  attribute HLUTNM of \ysqr[29]_i_6\ : label is "lutpair33";
  attribute HLUTNM of \ysqr[29]_i_7\ : label is "lutpair32";
  attribute HLUTNM of \ysqr[29]_i_8\ : label is "lutpair31";
  attribute SOFT_HLUTNM of \ysqr[2]_i_1\ : label is "soft_lutpair1172";
  attribute SOFT_HLUTNM of \ysqr[30]_i_1\ : label is "soft_lutpair1159";
  attribute SOFT_HLUTNM of \ysqr[31]_i_1\ : label is "soft_lutpair1159";
  attribute SOFT_HLUTNM of \ysqr[32]_i_1\ : label is "soft_lutpair1158";
  attribute SOFT_HLUTNM of \ysqr[33]_i_1\ : label is "soft_lutpair1158";
  attribute SOFT_HLUTNM of \ysqr[34]_i_1\ : label is "soft_lutpair1157";
  attribute SOFT_HLUTNM of \ysqr[35]_i_1\ : label is "soft_lutpair1157";
  attribute HLUTNM of \ysqr[35]_i_11\ : label is "lutpair34";
  attribute SOFT_HLUTNM of \ysqr[35]_i_45\ : label is "soft_lutpair995";
  attribute HLUTNM of \ysqr[35]_i_5\ : label is "lutpair34";
  attribute SOFT_HLUTNM of \ysqr[36]_i_1\ : label is "soft_lutpair1156";
  attribute SOFT_HLUTNM of \ysqr[38]_i_1\ : label is "soft_lutpair1156";
  attribute SOFT_HLUTNM of \ysqr[39]_i_1\ : label is "soft_lutpair889";
  attribute HLUTNM of \ysqr[39]_i_14\ : label is "lutpair35";
  attribute SOFT_HLUTNM of \ysqr[39]_i_32\ : label is "soft_lutpair979";
  attribute SOFT_HLUTNM of \ysqr[39]_i_33\ : label is "soft_lutpair978";
  attribute HLUTNM of \ysqr[39]_i_7\ : label is "lutpair35";
  attribute SOFT_HLUTNM of \ysqr[3]_i_1\ : label is "soft_lutpair890";
  attribute HLUTNM of \ysqr[3]_i_14\ : label is "lutpair25";
  attribute SOFT_HLUTNM of \ysqr[3]_i_32\ : label is "soft_lutpair975";
  attribute SOFT_HLUTNM of \ysqr[3]_i_33\ : label is "soft_lutpair974";
  attribute HLUTNM of \ysqr[3]_i_7\ : label is "lutpair25";
  attribute SOFT_HLUTNM of \ysqr[40]_i_1\ : label is "soft_lutpair1155";
  attribute SOFT_HLUTNM of \ysqr[41]_i_1\ : label is "soft_lutpair1155";
  attribute SOFT_HLUTNM of \ysqr[42]_i_1\ : label is "soft_lutpair1154";
  attribute SOFT_HLUTNM of \ysqr[43]_i_1\ : label is "soft_lutpair1154";
  attribute SOFT_HLUTNM of \ysqr[44]_i_1\ : label is "soft_lutpair1153";
  attribute SOFT_HLUTNM of \ysqr[45]_i_1\ : label is "soft_lutpair1153";
  attribute SOFT_HLUTNM of \ysqr[46]_i_1\ : label is "soft_lutpair1152";
  attribute SOFT_HLUTNM of \ysqr[47]_i_1\ : label is "soft_lutpair1152";
  attribute HLUTNM of \ysqr[47]_i_15\ : label is "lutpair38";
  attribute HLUTNM of \ysqr[47]_i_16\ : label is "lutpair37";
  attribute HLUTNM of \ysqr[47]_i_17\ : label is "lutpair36";
  attribute HLUTNM of \ysqr[47]_i_6\ : label is "lutpair38";
  attribute HLUTNM of \ysqr[47]_i_7\ : label is "lutpair37";
  attribute HLUTNM of \ysqr[47]_i_8\ : label is "lutpair36";
  attribute SOFT_HLUTNM of \ysqr[48]_i_1\ : label is "soft_lutpair1151";
  attribute SOFT_HLUTNM of \ysqr[49]_i_1\ : label is "soft_lutpair1151";
  attribute SOFT_HLUTNM of \ysqr[4]_i_1\ : label is "soft_lutpair1171";
  attribute SOFT_HLUTNM of \ysqr[50]_i_1\ : label is "soft_lutpair1150";
  attribute SOFT_HLUTNM of \ysqr[51]_i_1\ : label is "soft_lutpair1150";
  attribute SOFT_HLUTNM of \ysqr[52]_i_1\ : label is "soft_lutpair1149";
  attribute SOFT_HLUTNM of \ysqr[53]_i_1\ : label is "soft_lutpair1149";
  attribute HLUTNM of \ysqr[53]_i_11\ : label is "lutpair39";
  attribute SOFT_HLUTNM of \ysqr[53]_i_45\ : label is "soft_lutpair1002";
  attribute HLUTNM of \ysqr[53]_i_5\ : label is "lutpair39";
  attribute SOFT_HLUTNM of \ysqr[54]_i_1\ : label is "soft_lutpair1148";
  attribute SOFT_HLUTNM of \ysqr[56]_i_1\ : label is "soft_lutpair1148";
  attribute SOFT_HLUTNM of \ysqr[57]_i_1\ : label is "soft_lutpair889";
  attribute HLUTNM of \ysqr[57]_i_14\ : label is "lutpair40";
  attribute SOFT_HLUTNM of \ysqr[57]_i_32\ : label is "soft_lutpair981";
  attribute SOFT_HLUTNM of \ysqr[57]_i_33\ : label is "soft_lutpair980";
  attribute HLUTNM of \ysqr[57]_i_7\ : label is "lutpair40";
  attribute SOFT_HLUTNM of \ysqr[58]_i_1\ : label is "soft_lutpair1147";
  attribute SOFT_HLUTNM of \ysqr[59]_i_1\ : label is "soft_lutpair1147";
  attribute SOFT_HLUTNM of \ysqr[5]_i_1\ : label is "soft_lutpair1171";
  attribute SOFT_HLUTNM of \ysqr[60]_i_1\ : label is "soft_lutpair1146";
  attribute SOFT_HLUTNM of \ysqr[61]_i_1\ : label is "soft_lutpair1146";
  attribute SOFT_HLUTNM of \ysqr[62]_i_1\ : label is "soft_lutpair1145";
  attribute SOFT_HLUTNM of \ysqr[63]_i_1\ : label is "soft_lutpair1145";
  attribute SOFT_HLUTNM of \ysqr[64]_i_1\ : label is "soft_lutpair1144";
  attribute SOFT_HLUTNM of \ysqr[65]_i_1\ : label is "soft_lutpair1144";
  attribute HLUTNM of \ysqr[65]_i_15\ : label is "lutpair43";
  attribute HLUTNM of \ysqr[65]_i_16\ : label is "lutpair42";
  attribute HLUTNM of \ysqr[65]_i_17\ : label is "lutpair41";
  attribute HLUTNM of \ysqr[65]_i_6\ : label is "lutpair43";
  attribute HLUTNM of \ysqr[65]_i_7\ : label is "lutpair42";
  attribute HLUTNM of \ysqr[65]_i_8\ : label is "lutpair41";
  attribute SOFT_HLUTNM of \ysqr[66]_i_1\ : label is "soft_lutpair1143";
  attribute SOFT_HLUTNM of \ysqr[67]_i_1\ : label is "soft_lutpair1143";
  attribute SOFT_HLUTNM of \ysqr[68]_i_1\ : label is "soft_lutpair1142";
  attribute SOFT_HLUTNM of \ysqr[69]_i_1\ : label is "soft_lutpair1142";
  attribute SOFT_HLUTNM of \ysqr[6]_i_1\ : label is "soft_lutpair1170";
  attribute SOFT_HLUTNM of \ysqr[70]_i_1\ : label is "soft_lutpair1141";
  attribute SOFT_HLUTNM of \ysqr[71]_i_1\ : label is "soft_lutpair1141";
  attribute HLUTNM of \ysqr[71]_i_11\ : label is "lutpair44";
  attribute SOFT_HLUTNM of \ysqr[71]_i_45\ : label is "soft_lutpair1009";
  attribute HLUTNM of \ysqr[71]_i_5\ : label is "lutpair44";
  attribute SOFT_HLUTNM of \ysqr[72]_i_1\ : label is "soft_lutpair1140";
  attribute SOFT_HLUTNM of \ysqr[74]_i_1\ : label is "soft_lutpair1139";
  attribute SOFT_HLUTNM of \ysqr[75]_i_1\ : label is "soft_lutpair888";
  attribute HLUTNM of \ysqr[75]_i_14\ : label is "lutpair45";
  attribute SOFT_HLUTNM of \ysqr[75]_i_32\ : label is "soft_lutpair983";
  attribute SOFT_HLUTNM of \ysqr[75]_i_33\ : label is "soft_lutpair982";
  attribute HLUTNM of \ysqr[75]_i_7\ : label is "lutpair45";
  attribute SOFT_HLUTNM of \ysqr[76]_i_1\ : label is "soft_lutpair1139";
  attribute SOFT_HLUTNM of \ysqr[77]_i_1\ : label is "soft_lutpair1138";
  attribute SOFT_HLUTNM of \ysqr[78]_i_1\ : label is "soft_lutpair1138";
  attribute SOFT_HLUTNM of \ysqr[79]_i_1\ : label is "soft_lutpair1137";
  attribute SOFT_HLUTNM of \ysqr[7]_i_1\ : label is "soft_lutpair1170";
  attribute SOFT_HLUTNM of \ysqr[80]_i_1\ : label is "soft_lutpair1137";
  attribute SOFT_HLUTNM of \ysqr[81]_i_1\ : label is "soft_lutpair1136";
  attribute SOFT_HLUTNM of \ysqr[82]_i_1\ : label is "soft_lutpair1136";
  attribute SOFT_HLUTNM of \ysqr[83]_i_1\ : label is "soft_lutpair1135";
  attribute HLUTNM of \ysqr[83]_i_15\ : label is "lutpair48";
  attribute HLUTNM of \ysqr[83]_i_16\ : label is "lutpair47";
  attribute HLUTNM of \ysqr[83]_i_17\ : label is "lutpair46";
  attribute HLUTNM of \ysqr[83]_i_6\ : label is "lutpair48";
  attribute HLUTNM of \ysqr[83]_i_7\ : label is "lutpair47";
  attribute HLUTNM of \ysqr[83]_i_8\ : label is "lutpair46";
  attribute SOFT_HLUTNM of \ysqr[84]_i_1\ : label is "soft_lutpair1135";
  attribute SOFT_HLUTNM of \ysqr[85]_i_1\ : label is "soft_lutpair1134";
  attribute SOFT_HLUTNM of \ysqr[86]_i_1\ : label is "soft_lutpair1134";
  attribute SOFT_HLUTNM of \ysqr[87]_i_1\ : label is "soft_lutpair888";
  attribute SOFT_HLUTNM of \ysqr[88]_i_1\ : label is "soft_lutpair1133";
  attribute SOFT_HLUTNM of \ysqr[89]_i_1\ : label is "soft_lutpair1133";
  attribute HLUTNM of \ysqr[89]_i_11\ : label is "lutpair49";
  attribute SOFT_HLUTNM of \ysqr[89]_i_45\ : label is "soft_lutpair1016";
  attribute HLUTNM of \ysqr[89]_i_5\ : label is "lutpair49";
  attribute SOFT_HLUTNM of \ysqr[8]_i_1\ : label is "soft_lutpair1169";
  attribute SOFT_HLUTNM of \ysqr[9]_i_1\ : label is "soft_lutpair1169";
  attribute ADDER_THRESHOLD of \ysqr_reg[11]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \ysqr_reg[17]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \ysqr_reg[29]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \ysqr_reg[35]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \ysqr_reg[47]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \ysqr_reg[53]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \ysqr_reg[65]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \ysqr_reg[71]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \ysqr_reg[83]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \ysqr_reg[89]_i_2\ : label is 35;
begin
  \FSM_onehot_stateCoobufB_reg[5]_0\(1 downto 0) <= \^fsm_onehot_statecoobufb_reg[5]_0\(1 downto 0);
  Q(7 downto 0) <= \^q\(7 downto 0);
  \col_lcl_reg[10]_0\(10 downto 0) <= \^col_lcl_reg[10]_0\(10 downto 0);
  rng_reg_0 <= \^rng_reg_0\;
  rng_reg_1 <= \^rng_reg_1\;
  \stateOp_reg[1]_0\(1 downto 0) <= \^stateop_reg[1]_0\(1 downto 0);
  \tixVState_reg[1]_0\(1 downto 0) <= \^tixvstate_reg[1]_0\(1 downto 0);
\FSM_onehot_stateCoobufB[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000100010001FF01"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB_reg_n_0_[0]\,
      I1 => enCoobufB,
      I2 => \^fsm_onehot_statecoobufb_reg[5]_0\(1),
      I3 => \^fsm_onehot_statecoobufb_reg[5]_0\(0),
      I4 => reqCoobufCornerToHostif,
      I5 => coobufCornerToHostifAXIS_tready,
      O => \FSM_onehot_stateCoobufB[0]_i_1_n_0\
    );
\FSM_onehot_stateCoobufB[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => coobufCornerToHostifAXIS_tready,
      I1 => \^fsm_onehot_statecoobufb_reg[5]_0\(0),
      I2 => \aCoobufB_reg_n_0_[7]\,
      I3 => \FSM_onehot_stateCoobufB[3]_i_2_n_0\,
      I4 => \aCoobufB_reg_n_0_[6]\,
      O => \FSM_onehot_stateCoobufB[2]_i_1_n_0\
    );
\FSM_onehot_stateCoobufB[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFDF000000"
    )
        port map (
      I0 => \aCoobufB_reg_n_0_[7]\,
      I1 => \FSM_onehot_stateCoobufB[3]_i_2_n_0\,
      I2 => \aCoobufB_reg_n_0_[6]\,
      I3 => \^fsm_onehot_statecoobufb_reg[5]_0\(0),
      I4 => coobufCornerToHostifAXIS_tready,
      I5 => \^fsm_onehot_statecoobufb_reg[5]_0\(1),
      O => \FSM_onehot_stateCoobufB[3]_i_1_n_0\
    );
\FSM_onehot_stateCoobufB[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \aCoobufB_reg_n_0_[4]\,
      I1 => \aCoobufB_reg_n_0_[2]\,
      I2 => \aCoobufB_reg_n_0_[0]\,
      I3 => \aCoobufB_reg_n_0_[1]\,
      I4 => \aCoobufB_reg_n_0_[3]\,
      I5 => \aCoobufB_reg_n_0_[5]\,
      O => \FSM_onehot_stateCoobufB[3]_i_2_n_0\
    );
\FSM_onehot_stateCoobufB[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB_reg_n_0_[2]\,
      I1 => dneCoobufCornerToHostif,
      I2 => \FSM_onehot_stateCoobufB[5]_i_3_n_0\,
      O => \FSM_onehot_stateCoobufB[5]_i_1_n_0\
    );
\FSM_onehot_stateCoobufB[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFE2FFF3FFE2"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB_reg_n_0_[0]\,
      I1 => reqCoobufCornerToHostif,
      I2 => \^fsm_onehot_statecoobufb_reg[5]_0\(1),
      I3 => enCoobufB,
      I4 => \^fsm_onehot_statecoobufb_reg[5]_0\(0),
      I5 => coobufCornerToHostifAXIS_tready,
      O => \FSM_onehot_stateCoobufB[5]_i_3_n_0\
    );
\FSM_onehot_stateCoobufB_reg[0]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateCoobufB[5]_i_1_n_0\,
      D => \FSM_onehot_stateCoobufB[0]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \FSM_onehot_stateCoobufB_reg_n_0_[0]\
    );
\FSM_onehot_stateCoobufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateCoobufB[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => enCoobufB,
      Q => \^fsm_onehot_statecoobufb_reg[5]_0\(0)
    );
\FSM_onehot_stateCoobufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateCoobufB[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \FSM_onehot_stateCoobufB[2]_i_1_n_0\,
      Q => \FSM_onehot_stateCoobufB_reg_n_0_[2]\
    );
\FSM_onehot_stateCoobufB_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateCoobufB[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \FSM_onehot_stateCoobufB[3]_i_1_n_0\,
      Q => enCoobufB
    );
\FSM_onehot_stateCoobufB_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateCoobufB[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \FSM_onehot_stateCoobufB_reg_n_0_[0]\,
      Q => \^fsm_onehot_statecoobufb_reg[5]_0\(1)
    );
\aCoobufB[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB_reg_n_0_[0]\,
      I1 => \aCoobufB_reg_n_0_[0]\,
      O => \aCoobufB[0]_i_1_n_0\
    );
\aCoobufB[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"14"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB_reg_n_0_[0]\,
      I1 => \aCoobufB_reg_n_0_[0]\,
      I2 => \aCoobufB_reg_n_0_[1]\,
      O => aCoobufB(1)
    );
\aCoobufB[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0708"
    )
        port map (
      I0 => \aCoobufB_reg_n_0_[0]\,
      I1 => \aCoobufB_reg_n_0_[1]\,
      I2 => \FSM_onehot_stateCoobufB_reg_n_0_[0]\,
      I3 => \aCoobufB_reg_n_0_[2]\,
      O => aCoobufB(2)
    );
\aCoobufB[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"007F0080"
    )
        port map (
      I0 => \aCoobufB_reg_n_0_[1]\,
      I1 => \aCoobufB_reg_n_0_[0]\,
      I2 => \aCoobufB_reg_n_0_[2]\,
      I3 => \FSM_onehot_stateCoobufB_reg_n_0_[0]\,
      I4 => \aCoobufB_reg_n_0_[3]\,
      O => aCoobufB(3)
    );
\aCoobufB[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007FFF00008000"
    )
        port map (
      I0 => \aCoobufB_reg_n_0_[2]\,
      I1 => \aCoobufB_reg_n_0_[0]\,
      I2 => \aCoobufB_reg_n_0_[1]\,
      I3 => \aCoobufB_reg_n_0_[3]\,
      I4 => \FSM_onehot_stateCoobufB_reg_n_0_[0]\,
      I5 => \aCoobufB_reg_n_0_[4]\,
      O => aCoobufB(4)
    );
\aCoobufB[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"21"
    )
        port map (
      I0 => \aCoobufB[5]_i_2_n_0\,
      I1 => \FSM_onehot_stateCoobufB_reg_n_0_[0]\,
      I2 => \aCoobufB_reg_n_0_[5]\,
      O => aCoobufB(5)
    );
\aCoobufB[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \aCoobufB_reg_n_0_[3]\,
      I1 => \aCoobufB_reg_n_0_[1]\,
      I2 => \aCoobufB_reg_n_0_[0]\,
      I3 => \aCoobufB_reg_n_0_[2]\,
      I4 => \aCoobufB_reg_n_0_[4]\,
      O => \aCoobufB[5]_i_2_n_0\
    );
\aCoobufB[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"21"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB[3]_i_2_n_0\,
      I1 => \FSM_onehot_stateCoobufB_reg_n_0_[0]\,
      I2 => \aCoobufB_reg_n_0_[6]\,
      O => aCoobufB(6)
    );
\aCoobufB[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFDF000000"
    )
        port map (
      I0 => \aCoobufB_reg_n_0_[7]\,
      I1 => \FSM_onehot_stateCoobufB[3]_i_2_n_0\,
      I2 => \aCoobufB_reg_n_0_[6]\,
      I3 => \^fsm_onehot_statecoobufb_reg[5]_0\(0),
      I4 => coobufCornerToHostifAXIS_tready,
      I5 => \FSM_onehot_stateCoobufB_reg_n_0_[0]\,
      O => p_0_out
    );
\aCoobufB[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0B04"
    )
        port map (
      I0 => \FSM_onehot_stateCoobufB[3]_i_2_n_0\,
      I1 => \aCoobufB_reg_n_0_[6]\,
      I2 => \FSM_onehot_stateCoobufB_reg_n_0_[0]\,
      I3 => \aCoobufB_reg_n_0_[7]\,
      O => aCoobufB(7)
    );
\aCoobufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => p_0_out,
      CLR => linNotLog_reg_0,
      D => \aCoobufB[0]_i_1_n_0\,
      Q => \aCoobufB_reg_n_0_[0]\
    );
\aCoobufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => p_0_out,
      CLR => linNotLog_reg_0,
      D => aCoobufB(1),
      Q => \aCoobufB_reg_n_0_[1]\
    );
\aCoobufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => p_0_out,
      CLR => linNotLog_reg_0,
      D => aCoobufB(2),
      Q => \aCoobufB_reg_n_0_[2]\
    );
\aCoobufB_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => p_0_out,
      CLR => linNotLog_reg_0,
      D => aCoobufB(3),
      Q => \aCoobufB_reg_n_0_[3]\
    );
\aCoobufB_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => p_0_out,
      CLR => linNotLog_reg_0,
      D => aCoobufB(4),
      Q => \aCoobufB_reg_n_0_[4]\
    );
\aCoobufB_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => p_0_out,
      CLR => linNotLog_reg_0,
      D => aCoobufB(5),
      Q => \aCoobufB_reg_n_0_[5]\
    );
\aCoobufB_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => p_0_out,
      CLR => linNotLog_reg_0,
      D => aCoobufB(6),
      Q => \aCoobufB_reg_n_0_[6]\
    );
\aCoobufB_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => p_0_out,
      CLR => linNotLog_reg_0,
      D => aCoobufB(7),
      Q => \aCoobufB_reg_n_0_[7]\
    );
\aCoobuf[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => aCoobuf_reg(0),
      O => \p_0_in__0\(0)
    );
\aCoobuf[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00A8A800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => aCoobuf_reg(1),
      I4 => aCoobuf_reg(0),
      O => \p_0_in__0\(1)
    );
\aCoobuf[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00A8A8A8A8000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => aCoobuf_reg(0),
      I4 => aCoobuf_reg(1),
      I5 => aCoobuf_reg(2),
      O => \p_0_in__0\(2)
    );
\aCoobuf[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F800000"
    )
        port map (
      I0 => aCoobuf_reg(1),
      I1 => aCoobuf_reg(0),
      I2 => aCoobuf_reg(2),
      I3 => aCoobuf_reg(3),
      I4 => \col_lcl[8]__0_i_2_n_0\,
      O => \aCoobuf[3]_i_1_n_0\
    );
\aCoobuf[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \col_lcl[8]__0_i_2_n_0\,
      I1 => aCoobuf_reg(3),
      I2 => aCoobuf_reg(2),
      I3 => aCoobuf_reg(0),
      I4 => aCoobuf_reg(1),
      I5 => aCoobuf_reg(4),
      O => \p_0_in__0\(4)
    );
\aCoobuf[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00A8A800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => \aCoobuf[5]_i_2_n_0\,
      I4 => aCoobuf_reg(5),
      O => \p_0_in__0\(5)
    );
\aCoobuf[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => aCoobuf_reg(4),
      I1 => aCoobuf_reg(1),
      I2 => aCoobuf_reg(0),
      I3 => aCoobuf_reg(2),
      I4 => aCoobuf_reg(3),
      O => \aCoobuf[5]_i_2_n_0\
    );
\aCoobuf[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00A8A800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => \aCoobuf[8]_i_3_n_0\,
      I4 => aCoobuf_reg(6),
      O => \p_0_in__0\(6)
    );
\aCoobuf[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00A8A8A8A8000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => \aCoobuf[8]_i_3_n_0\,
      I4 => aCoobuf_reg(6),
      I5 => aCoobuf_reg(7),
      O => \p_0_in__0\(7)
    );
\aCoobuf[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0DFF"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[0]\,
      I1 => enCoobuf_reg_n_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      O => sel
    );
\aCoobuf[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \col_lcl[8]__0_i_2_n_0\,
      I1 => aCoobuf_reg(6),
      I2 => \aCoobuf[8]_i_3_n_0\,
      I3 => aCoobuf_reg(7),
      I4 => aCoobuf_reg(8),
      O => \p_0_in__0\(8)
    );
\aCoobuf[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => aCoobuf_reg(3),
      I1 => aCoobuf_reg(2),
      I2 => aCoobuf_reg(0),
      I3 => aCoobuf_reg(1),
      I4 => aCoobuf_reg(4),
      I5 => aCoobuf_reg(5),
      O => \aCoobuf[8]_i_3_n_0\
    );
\aCoobuf_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => sel,
      CLR => linNotLog_reg_0,
      D => \p_0_in__0\(0),
      Q => aCoobuf_reg(0)
    );
\aCoobuf_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => sel,
      CLR => linNotLog_reg_0,
      D => \p_0_in__0\(1),
      Q => aCoobuf_reg(1)
    );
\aCoobuf_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => sel,
      CLR => linNotLog_reg_0,
      D => \p_0_in__0\(2),
      Q => aCoobuf_reg(2)
    );
\aCoobuf_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => sel,
      CLR => linNotLog_reg_0,
      D => \aCoobuf[3]_i_1_n_0\,
      Q => aCoobuf_reg(3)
    );
\aCoobuf_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => sel,
      CLR => linNotLog_reg_0,
      D => \p_0_in__0\(4),
      Q => aCoobuf_reg(4)
    );
\aCoobuf_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => sel,
      CLR => linNotLog_reg_0,
      D => \p_0_in__0\(5),
      Q => aCoobuf_reg(5)
    );
\aCoobuf_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => sel,
      CLR => linNotLog_reg_0,
      D => \p_0_in__0\(6),
      Q => aCoobuf_reg(6)
    );
\aCoobuf_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => sel,
      CLR => linNotLog_reg_0,
      D => \p_0_in__0\(7),
      Q => aCoobuf_reg(7)
    );
\aCoobuf_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => sel,
      CLR => linNotLog_reg_0,
      D => \p_0_in__0\(8),
      Q => aCoobuf_reg(8)
    );
\aImdbufB[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => \aImdbufB_reg_n_0_[0]\,
      O => \aImdbufB[0]_i_1_n_0\
    );
\aImdbufB[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002888"
    )
        port map (
      I0 => \stateImdstream[0]_i_3_n_0\,
      I1 => \aImdbufB_reg_n_0_[10]\,
      I2 => \aImdbufB[10]_i_2_n_0\,
      I3 => \aImdbufB_reg_n_0_[9]\,
      I4 => \aImdbuf[10]_i_6_n_0\,
      O => \aImdbufB[10]_i_1_n_0\
    );
\aImdbufB[10]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \aImdbufB_reg_n_0_[7]\,
      I1 => \aImdbufB[8]_i_2_n_0\,
      I2 => \aImdbufB_reg_n_0_[6]\,
      I3 => \aImdbufB_reg_n_0_[8]\,
      O => \aImdbufB[10]_i_2_n_0\
    );
\aImdbufB[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000100010000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => \aImdbufB_reg_n_0_[1]\,
      I5 => \aImdbufB_reg_n_0_[0]\,
      O => \aImdbufB[1]_i_1_n_0\
    );
\aImdbufB[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002888"
    )
        port map (
      I0 => \stateImdstream[0]_i_3_n_0\,
      I1 => \aImdbufB_reg_n_0_[2]\,
      I2 => \aImdbufB_reg_n_0_[1]\,
      I3 => \aImdbufB_reg_n_0_[0]\,
      I4 => \aImdbuf[10]_i_6_n_0\,
      O => \aImdbufB[2]_i_1_n_0\
    );
\aImdbufB[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000028888888"
    )
        port map (
      I0 => \stateImdstream[0]_i_3_n_0\,
      I1 => \aImdbufB_reg_n_0_[3]\,
      I2 => \aImdbufB_reg_n_0_[2]\,
      I3 => \aImdbufB_reg_n_0_[0]\,
      I4 => \aImdbufB_reg_n_0_[1]\,
      I5 => \aImdbuf[10]_i_6_n_0\,
      O => \aImdbufB[3]_i_1_n_0\
    );
\aImdbufB[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \aImdbufB_reg_n_0_[4]\,
      I2 => \aImdbufB[4]_i_2_n_0\,
      I3 => p_1_in,
      I4 => \stateImdstream_reg_n_0_[0]\,
      I5 => \stateImdstream_reg_n_0_[1]\,
      O => \aImdbufB[4]_i_1_n_0\
    );
\aImdbufB[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \aImdbufB_reg_n_0_[2]\,
      I1 => \aImdbufB_reg_n_0_[0]\,
      I2 => \aImdbufB_reg_n_0_[1]\,
      I3 => \aImdbufB_reg_n_0_[3]\,
      O => \aImdbufB[4]_i_2_n_0\
    );
\aImdbufB[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \aImdbufB_reg_n_0_[5]\,
      I2 => \aImdbufB[5]_i_2_n_0\,
      I3 => p_1_in,
      I4 => \stateImdstream_reg_n_0_[0]\,
      I5 => \stateImdstream_reg_n_0_[1]\,
      O => \aImdbufB[5]_i_1_n_0\
    );
\aImdbufB[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aImdbufB_reg_n_0_[3]\,
      I1 => \aImdbufB_reg_n_0_[1]\,
      I2 => \aImdbufB_reg_n_0_[0]\,
      I3 => \aImdbufB_reg_n_0_[2]\,
      I4 => \aImdbufB_reg_n_0_[4]\,
      O => \aImdbufB[5]_i_2_n_0\
    );
\aImdbufB[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \aImdbufB_reg_n_0_[6]\,
      I2 => \aImdbufB[8]_i_2_n_0\,
      I3 => p_1_in,
      I4 => \stateImdstream_reg_n_0_[0]\,
      I5 => \stateImdstream_reg_n_0_[1]\,
      O => \aImdbufB[6]_i_1_n_0\
    );
\aImdbufB[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002888"
    )
        port map (
      I0 => \stateImdstream[0]_i_3_n_0\,
      I1 => \aImdbufB_reg_n_0_[7]\,
      I2 => \aImdbufB_reg_n_0_[6]\,
      I3 => \aImdbufB[8]_i_2_n_0\,
      I4 => \aImdbuf[10]_i_6_n_0\,
      O => \aImdbufB[7]_i_1_n_0\
    );
\aImdbufB[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000028888888"
    )
        port map (
      I0 => \stateImdstream[0]_i_3_n_0\,
      I1 => \aImdbufB_reg_n_0_[8]\,
      I2 => \aImdbufB_reg_n_0_[7]\,
      I3 => \aImdbufB[8]_i_2_n_0\,
      I4 => \aImdbufB_reg_n_0_[6]\,
      I5 => \aImdbuf[10]_i_6_n_0\,
      O => \aImdbufB[8]_i_1_n_0\
    );
\aImdbufB[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aImdbufB_reg_n_0_[4]\,
      I1 => \aImdbufB_reg_n_0_[2]\,
      I2 => \aImdbufB_reg_n_0_[0]\,
      I3 => \aImdbufB_reg_n_0_[1]\,
      I4 => \aImdbufB_reg_n_0_[3]\,
      I5 => \aImdbufB_reg_n_0_[5]\,
      O => \aImdbufB[8]_i_2_n_0\
    );
\aImdbufB[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \aImdbufB_reg_n_0_[9]\,
      I2 => \aImdbufB[10]_i_2_n_0\,
      I3 => p_1_in,
      I4 => \stateImdstream_reg_n_0_[0]\,
      I5 => \stateImdstream_reg_n_0_[1]\,
      O => \aImdbufB[9]_i_1_n_0\
    );
\aImdbufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbufB[0]_i_1_n_0\,
      Q => \aImdbufB_reg_n_0_[0]\
    );
\aImdbufB_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbufB[10]_i_1_n_0\,
      Q => \aImdbufB_reg_n_0_[10]\
    );
\aImdbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbufB[1]_i_1_n_0\,
      Q => \aImdbufB_reg_n_0_[1]\
    );
\aImdbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbufB[2]_i_1_n_0\,
      Q => \aImdbufB_reg_n_0_[2]\
    );
\aImdbufB_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbufB[3]_i_1_n_0\,
      Q => \aImdbufB_reg_n_0_[3]\
    );
\aImdbufB_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbufB[4]_i_1_n_0\,
      Q => \aImdbufB_reg_n_0_[4]\
    );
\aImdbufB_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbufB[5]_i_1_n_0\,
      Q => \aImdbufB_reg_n_0_[5]\
    );
\aImdbufB_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbufB[6]_i_1_n_0\,
      Q => \aImdbufB_reg_n_0_[6]\
    );
\aImdbufB_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbufB[7]_i_1_n_0\,
      Q => \aImdbufB_reg_n_0_[7]\
    );
\aImdbufB_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbufB[8]_i_1_n_0\,
      Q => \aImdbufB_reg_n_0_[8]\
    );
\aImdbufB_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbufB[9]_i_1_n_0\,
      Q => \aImdbufB_reg_n_0_[9]\
    );
\aImdbuf[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => \aImdbuf_reg_n_0_[0]\,
      O => \aImdbuf[0]_i_1_n_0\
    );
\aImdbuf[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \col_lcl[10]_i_3_n_0\,
      I1 => \aImdbuf[10]_i_3_n_0\,
      I2 => \aImdbuf[10]_i_4_n_0\,
      I3 => \aImdbufB_reg[0]_0\,
      O => aImdbufB
    );
\aImdbuf[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002888"
    )
        port map (
      I0 => \stateImdstream[0]_i_3_n_0\,
      I1 => \aImdbuf_reg_n_0_[10]\,
      I2 => \aImdbuf[10]_i_5_n_0\,
      I3 => \aImdbuf_reg_n_0_[9]\,
      I4 => \aImdbuf[10]_i_6_n_0\,
      O => \aImdbuf[10]_i_2_n_0\
    );
\aImdbuf[10]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \aImdbuf[10]_i_7_n_0\,
      I1 => \^col_lcl_reg[10]_0\(2),
      I2 => \^col_lcl_reg[10]_0\(4),
      I3 => \^col_lcl_reg[10]_0\(1),
      I4 => \aImdbuf[10]_i_8_n_0\,
      O => \aImdbuf[10]_i_3_n_0\
    );
\aImdbuf[10]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => ceScore,
      O => \aImdbuf[10]_i_4_n_0\
    );
\aImdbuf[10]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \aImdbuf_reg_n_0_[7]\,
      I1 => \aImdbuf[8]_i_2_n_0\,
      I2 => \aImdbuf_reg_n_0_[6]\,
      I3 => \aImdbuf_reg_n_0_[8]\,
      O => \aImdbuf[10]_i_5_n_0\
    );
\aImdbuf[10]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      O => \aImdbuf[10]_i_6_n_0\
    );
\aImdbuf[10]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^col_lcl_reg[10]_0\(8),
      I1 => \^col_lcl_reg[10]_0\(0),
      I2 => \^col_lcl_reg[10]_0\(5),
      I3 => \^col_lcl_reg[10]_0\(3),
      O => \aImdbuf[10]_i_7_n_0\
    );
\aImdbuf[10]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^col_lcl_reg[10]_0\(9),
      I1 => \^col_lcl_reg[10]_0\(6),
      I2 => \^col_lcl_reg[10]_0\(10),
      I3 => \^col_lcl_reg[10]_0\(7),
      O => \aImdbuf[10]_i_8_n_0\
    );
\aImdbuf[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000100010000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => \aImdbuf_reg_n_0_[1]\,
      I5 => \aImdbuf_reg_n_0_[0]\,
      O => \aImdbuf[1]_i_1_n_0\
    );
\aImdbuf[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002888"
    )
        port map (
      I0 => \stateImdstream[0]_i_3_n_0\,
      I1 => \aImdbuf_reg_n_0_[2]\,
      I2 => \aImdbuf_reg_n_0_[1]\,
      I3 => \aImdbuf_reg_n_0_[0]\,
      I4 => \aImdbuf[10]_i_6_n_0\,
      O => \aImdbuf[2]_i_1_n_0\
    );
\aImdbuf[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000028888888"
    )
        port map (
      I0 => \stateImdstream[0]_i_3_n_0\,
      I1 => \aImdbuf_reg_n_0_[3]\,
      I2 => \aImdbuf_reg_n_0_[2]\,
      I3 => \aImdbuf_reg_n_0_[0]\,
      I4 => \aImdbuf_reg_n_0_[1]\,
      I5 => \aImdbuf[10]_i_6_n_0\,
      O => \aImdbuf[3]_i_1_n_0\
    );
\aImdbuf[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \aImdbuf_reg_n_0_[4]\,
      I2 => \aImdbuf[4]_i_2_n_0\,
      I3 => p_1_in,
      I4 => \stateImdstream_reg_n_0_[0]\,
      I5 => \stateImdstream_reg_n_0_[1]\,
      O => \aImdbuf[4]_i_1_n_0\
    );
\aImdbuf[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \aImdbuf_reg_n_0_[2]\,
      I1 => \aImdbuf_reg_n_0_[0]\,
      I2 => \aImdbuf_reg_n_0_[1]\,
      I3 => \aImdbuf_reg_n_0_[3]\,
      O => \aImdbuf[4]_i_2_n_0\
    );
\aImdbuf[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \aImdbuf_reg_n_0_[5]\,
      I2 => \aImdbuf[5]_i_2_n_0\,
      I3 => p_1_in,
      I4 => \stateImdstream_reg_n_0_[0]\,
      I5 => \stateImdstream_reg_n_0_[1]\,
      O => \aImdbuf[5]_i_1_n_0\
    );
\aImdbuf[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aImdbuf_reg_n_0_[3]\,
      I1 => \aImdbuf_reg_n_0_[1]\,
      I2 => \aImdbuf_reg_n_0_[0]\,
      I3 => \aImdbuf_reg_n_0_[2]\,
      I4 => \aImdbuf_reg_n_0_[4]\,
      O => \aImdbuf[5]_i_2_n_0\
    );
\aImdbuf[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \aImdbuf_reg_n_0_[6]\,
      I2 => \aImdbuf[8]_i_2_n_0\,
      I3 => p_1_in,
      I4 => \stateImdstream_reg_n_0_[0]\,
      I5 => \stateImdstream_reg_n_0_[1]\,
      O => \aImdbuf[6]_i_1_n_0\
    );
\aImdbuf[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002888"
    )
        port map (
      I0 => \stateImdstream[0]_i_3_n_0\,
      I1 => \aImdbuf_reg_n_0_[7]\,
      I2 => \aImdbuf_reg_n_0_[6]\,
      I3 => \aImdbuf[8]_i_2_n_0\,
      I4 => \aImdbuf[10]_i_6_n_0\,
      O => \aImdbuf[7]_i_1_n_0\
    );
\aImdbuf[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000028888888"
    )
        port map (
      I0 => \stateImdstream[0]_i_3_n_0\,
      I1 => \aImdbuf_reg_n_0_[8]\,
      I2 => \aImdbuf_reg_n_0_[7]\,
      I3 => \aImdbuf[8]_i_2_n_0\,
      I4 => \aImdbuf_reg_n_0_[6]\,
      I5 => \aImdbuf[10]_i_6_n_0\,
      O => \aImdbuf[8]_i_1_n_0\
    );
\aImdbuf[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aImdbuf_reg_n_0_[4]\,
      I1 => \aImdbuf_reg_n_0_[2]\,
      I2 => \aImdbuf_reg_n_0_[0]\,
      I3 => \aImdbuf_reg_n_0_[1]\,
      I4 => \aImdbuf_reg_n_0_[3]\,
      I5 => \aImdbuf_reg_n_0_[5]\,
      O => \aImdbuf[8]_i_2_n_0\
    );
\aImdbuf[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \aImdbuf_reg_n_0_[9]\,
      I2 => \aImdbuf[10]_i_5_n_0\,
      I3 => p_1_in,
      I4 => \stateImdstream_reg_n_0_[0]\,
      I5 => \stateImdstream_reg_n_0_[1]\,
      O => \aImdbuf[9]_i_1_n_0\
    );
\aImdbuf_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbuf[0]_i_1_n_0\,
      Q => \aImdbuf_reg_n_0_[0]\
    );
\aImdbuf_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbuf[10]_i_2_n_0\,
      Q => \aImdbuf_reg_n_0_[10]\
    );
\aImdbuf_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbuf[1]_i_1_n_0\,
      Q => \aImdbuf_reg_n_0_[1]\
    );
\aImdbuf_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbuf[2]_i_1_n_0\,
      Q => \aImdbuf_reg_n_0_[2]\
    );
\aImdbuf_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbuf[3]_i_1_n_0\,
      Q => \aImdbuf_reg_n_0_[3]\
    );
\aImdbuf_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbuf[4]_i_1_n_0\,
      Q => \aImdbuf_reg_n_0_[4]\
    );
\aImdbuf_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbuf[5]_i_1_n_0\,
      Q => \aImdbuf_reg_n_0_[5]\
    );
\aImdbuf_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbuf[6]_i_1_n_0\,
      Q => \aImdbuf_reg_n_0_[6]\
    );
\aImdbuf_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbuf[7]_i_1_n_0\,
      Q => \aImdbuf_reg_n_0_[7]\
    );
\aImdbuf_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbuf[8]_i_1_n_0\,
      Q => \aImdbuf_reg_n_0_[8]\
    );
\aImdbuf_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => aImdbufB,
      CLR => linNotLog_reg_0,
      D => \aImdbuf[9]_i_1_n_0\,
      Q => \aImdbuf_reg_n_0_[9]\
    );
\abcde[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000020200020"
    )
        port map (
      I0 => stateCorner(0),
      I1 => stateCorner(1),
      I2 => \^rng_reg_0\,
      I3 => \abcde__0\(2),
      I4 => \abcde__0\(1),
      I5 => \abcde__0\(0),
      O => \abcde[0]_i_1_n_0\
    );
\abcde[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002800"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => \abcde__0\(0),
      I2 => \abcde__0\(1),
      I3 => stateCorner(0),
      I4 => stateCorner(1),
      O => \abcde[1]_i_1_n_0\
    );
\abcde[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"33BB3F3333BB3333"
    )
        port map (
      I0 => ceScore,
      I1 => \^rng_reg_1\,
      I2 => \tkst_reg[0]_0\,
      I3 => stateCorner(1),
      I4 => stateCorner(0),
      I5 => \stateCorner[1]_i_4_n_0\,
      O => \abcde[2]_i_1_n_0\
    );
\abcde[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000028800000"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => \abcde__0\(0),
      I2 => \abcde__0\(1),
      I3 => \abcde__0\(2),
      I4 => stateCorner(0),
      I5 => stateCorner(1),
      O => \abcde[2]_i_2_n_0\
    );
\abcde_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \abcde[2]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \abcde[0]_i_1_n_0\,
      Q => \abcde__0\(0)
    );
\abcde_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \abcde[2]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \abcde[1]_i_1_n_0\,
      Q => \abcde__0\(1)
    );
\abcde_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \abcde[2]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \abcde[2]_i_2_n_0\,
      Q => \abcde__0\(2)
    );
ackInvAcquire_sig_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8C"
    )
        port map (
      I0 => \^stateop_reg[1]_0\(1),
      I1 => reqInvAcquire,
      I2 => \^stateop_reg[1]_0\(0),
      O => ackInvAcquire_sig
    );
ackInvAcquire_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => linNotLog_reg_0,
      D => ackInvAcquire_sig,
      Q => ackInvCornerAcquire
    );
\ackInvConfig_sig_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2030"
    )
        port map (
      I0 => \^stateop_reg[1]_0\(1),
      I1 => reqInvAcquire,
      I2 => reqInvCornerConfig,
      I3 => \^stateop_reg[1]_0\(0),
      O => ackInvConfig_sig
    );
ackInvConfig_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => linNotLog_reg_0,
      D => ackInvConfig_sig,
      Q => ackInvCornerConfig
    );
ackInvSet_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => linNotLog_reg_0,
      D => ackInvSet_sig,
      Q => ackInvCornerSet
    );
ackInvUnlock_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => linNotLog_reg_0,
      D => ackInvUnlock_sig0_in,
      Q => ackInvCornerUnlock
    );
\capt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^tixvstate_reg[1]_0\(0),
      I1 => \capt_reg[1]\,
      O => D(0)
    );
\capt[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^tixvstate_reg[1]_0\(1),
      I1 => \capt_reg[2]\,
      O => D(1)
    );
ceMaxsel_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \aImdbuf[10]_i_6_n_0\,
      I1 => \^rng_reg_0\,
      I2 => \aImdbuf[10]_i_3_n_0\,
      I3 => ceMaxsel_i_2_n_0,
      I4 => ceMaxsel_reg_n_0,
      O => ceMaxsel_i_1_n_0
    );
ceMaxsel_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55775577DD77FD77"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => ceScore,
      I3 => \stateImdstream_reg_n_0_[1]\,
      I4 => \aImdbuf[10]_i_3_n_0\,
      I5 => p_1_in,
      O => ceMaxsel_i_2_n_0
    );
ceMaxsel_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => ceMaxsel_i_1_n_0,
      Q => ceMaxsel_reg_n_0
    );
ceScore_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00002000"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => stateCorner(1),
      I2 => stateCorner(0),
      I3 => grayVideoinToManyAXIS_tvalid,
      I4 => \tkst_reg[0]_0\,
      I5 => \stateCorner[0]_i_2_n_0\,
      O => ceScore15_out
    );
ceScore_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => ceScore15_out,
      Q => ceScore
    );
\col0_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \col0_reg[10]_0\(0),
      Q => col0(0)
    );
\col0_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \col0_reg[10]_0\(10),
      Q => col0(10)
    );
\col0_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \col0_reg[10]_0\(1),
      Q => col0(1)
    );
\col0_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \col0_reg[10]_0\(2),
      Q => col0(2)
    );
\col0_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \col0_reg[10]_0\(3),
      Q => col0(3)
    );
\col0_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \col0_reg[10]_0\(4),
      Q => col0(4)
    );
\col0_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \col0_reg[10]_0\(5),
      Q => col0(5)
    );
\col0_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \col0_reg[10]_0\(6),
      Q => col0(6)
    );
\col0_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \col0_reg[10]_0\(7),
      Q => col0(7)
    );
\col0_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \col0_reg[10]_0\(8),
      Q => col0(8)
    );
\col0_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \col0_reg[10]_0\(9),
      Q => col0(9)
    );
\col1_reg[0]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \col1_reg[10]_0\(0),
      PRE => linNotLog_reg_0,
      Q => col1(0)
    );
\col1_reg[10]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \col1_reg[10]_0\(10),
      PRE => linNotLog_reg_0,
      Q => col1(10)
    );
\col1_reg[1]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \col1_reg[10]_0\(1),
      PRE => linNotLog_reg_0,
      Q => col1(1)
    );
\col1_reg[2]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \col1_reg[10]_0\(2),
      PRE => linNotLog_reg_0,
      Q => col1(2)
    );
\col1_reg[3]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \col1_reg[10]_0\(3),
      PRE => linNotLog_reg_0,
      Q => col1(3)
    );
\col1_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \col1_reg[10]_0\(4),
      Q => col1(4)
    );
\col1_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \col1_reg[10]_0\(5),
      Q => col1(5)
    );
\col1_reg[6]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \col1_reg[10]_0\(6),
      PRE => linNotLog_reg_0,
      Q => col1(6)
    );
\col1_reg[7]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \col1_reg[10]_0\(7),
      PRE => linNotLog_reg_0,
      Q => col1(7)
    );
\col1_reg[8]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \col1_reg[10]_0\(8),
      PRE => linNotLog_reg_0,
      Q => col1(8)
    );
\col1_reg[9]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \col1_reg[10]_0\(9),
      PRE => linNotLog_reg_0,
      Q => col1(9)
    );
\col_lcl[0]__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[1]\,
      I1 => \^rng_reg_0\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => \col_lcl_reg[0]__0_n_0\,
      O => \col_lcl[0]__0_i_1_n_0\
    );
\col_lcl[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \col_lcl[10]_i_5_n_0\,
      I1 => \^col_lcl_reg[10]_0\(0),
      O => \col_lcl[0]_i_1_n_0\
    );
\col_lcl[10]__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000FFFF4440"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[1]\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => ceMaxsel_reg_n_0,
      I3 => postNotLive_reg_n_0,
      I4 => \row_lcl[10]_i_1_n_0\,
      I5 => \col_lcl[10]__0_i_3_n_0\,
      O => \col_lcl[10]__0_i_1_n_0\
    );
\col_lcl[10]__0_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BD7EEBD7D7EBBD7E"
    )
        port map (
      I0 => \col_lcl_reg[10]__0_n_0\,
      I1 => \col_lcl_reg[9]__0_n_0\,
      I2 => \col_lcl[10]__0_i_16_n_0\,
      I3 => NColRaw(9),
      I4 => NColRaw(8),
      I5 => \col_lcl[10]__0_i_3_2\,
      O => \col_lcl[10]__0_i_10_n_0\
    );
\col_lcl[10]__0_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \col_lcl_reg[5]__0_n_0\,
      I1 => \col_lcl_reg[3]__0_n_0\,
      I2 => \col_lcl_reg[1]__0_n_0\,
      I3 => \col_lcl_reg[2]__0_n_0\,
      I4 => \col_lcl_reg[4]__0_n_0\,
      I5 => \col_lcl_reg[6]__0_n_0\,
      O => \col_lcl[10]__0_i_11_n_0\
    );
\col_lcl[10]__0_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BD7EEBD7D7EBBD7E"
    )
        port map (
      I0 => \col_lcl_reg[5]__0_n_0\,
      I1 => \col_lcl_reg[4]__0_n_0\,
      I2 => \col_lcl[10]__0_i_17_n_0\,
      I3 => NColRaw(5),
      I4 => NColRaw(4),
      I5 => \col_lcl[10]__0_i_5_0\,
      O => \col_lcl[10]__0_i_12_n_0\
    );
\col_lcl[10]__0_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \col_lcl_reg[4]__0_n_0\,
      I1 => \col_lcl_reg[2]__0_n_0\,
      I2 => \col_lcl_reg[1]__0_n_0\,
      I3 => \col_lcl_reg[3]__0_n_0\,
      I4 => \col_lcl_reg[5]__0_n_0\,
      O => \col_lcl[10]__0_i_14_n_0\
    );
\col_lcl[10]__0_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \col_lcl_reg[7]__0_n_0\,
      I1 => \col_lcl[10]__0_i_11_n_0\,
      I2 => \col_lcl_reg[8]__0_n_0\,
      O => \col_lcl[10]__0_i_16_n_0\
    );
\col_lcl[10]__0_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \col_lcl_reg[2]__0_n_0\,
      I1 => \col_lcl_reg[1]__0_n_0\,
      I2 => \col_lcl_reg[3]__0_n_0\,
      O => \col_lcl[10]__0_i_17_n_0\
    );
\col_lcl[10]__0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008080008000800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \col_lcl_reg[10]__0_n_0\,
      I4 => \col_lcl[10]__0_i_4_n_0\,
      I5 => \col_lcl_reg[0]__0_n_0\,
      O => \col_lcl[10]__0_i_2_n_0\
    );
\col_lcl[10]__0_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010010000"
    )
        port map (
      I0 => \col_lcl[10]__0_i_5_n_0\,
      I1 => \col_lcl[10]__0_i_6_n_0\,
      I2 => \col_lcl_reg[0]__0_0\,
      I3 => \col_lcl[10]__0_i_8_n_0\,
      I4 => \col_lcl[10]__0_i_9_n_0\,
      I5 => \col_lcl[10]__0_i_10_n_0\,
      O => \col_lcl[10]__0_i_3_n_0\
    );
\col_lcl[10]__0_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \col_lcl_reg[8]__0_n_0\,
      I1 => \col_lcl[10]__0_i_11_n_0\,
      I2 => \col_lcl_reg[7]__0_n_0\,
      I3 => \col_lcl_reg[9]__0_n_0\,
      O => \col_lcl[10]__0_i_4_n_0\
    );
\col_lcl[10]__0_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BEEEEBBBEBBBBEEE"
    )
        port map (
      I0 => \col_lcl[10]__0_i_12_n_0\,
      I1 => \col_lcl_reg[3]__0_n_0\,
      I2 => \col_lcl_reg[2]__0_n_0\,
      I3 => \col_lcl_reg[1]__0_n_0\,
      I4 => NColRaw(3),
      I5 => \col_lcl[10]__0_i_3_0\,
      O => \col_lcl[10]__0_i_5_n_0\
    );
\col_lcl[10]__0_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFFFFB7DFB7DEFFF"
    )
        port map (
      I0 => \col_lcl_reg[0]__0_n_0\,
      I1 => \col_lcl_reg[1]__0_n_0\,
      I2 => NColRaw(1),
      I3 => NColRaw(0),
      I4 => NColRaw(2),
      I5 => \col_lcl_reg[2]__0_n_0\,
      O => \col_lcl[10]__0_i_6_n_0\
    );
\col_lcl[10]__0_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \col_lcl_reg[8]__0_n_0\,
      I1 => \col_lcl_reg[7]__0_n_0\,
      I2 => \col_lcl[10]__0_i_11_n_0\,
      O => \col_lcl[10]__0_i_8_n_0\
    );
\col_lcl[10]__0_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4281142828144281"
    )
        port map (
      I0 => \col_lcl_reg[7]__0_n_0\,
      I1 => \col_lcl_reg[6]__0_n_0\,
      I2 => \col_lcl[10]__0_i_14_n_0\,
      I3 => NColRaw(7),
      I4 => NColRaw(6),
      I5 => \col_lcl[10]__0_i_3_1\,
      O => \col_lcl[10]__0_i_9_n_0\
    );
\col_lcl[10]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00003800"
    )
        port map (
      I0 => \aImdbufB_reg[0]_0\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => \stateImdstream_reg_n_0_[0]\,
      I3 => ceScore,
      I4 => p_1_in,
      I5 => \col_lcl[10]_i_3_n_0\,
      O => \col_lcl[10]_i_1__0_n_0\
    );
\col_lcl[10]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \^col_lcl_reg[10]_0\(10),
      I1 => \col_lcl[10]_i_4_n_0\,
      I2 => \col_lcl[10]_i_5_n_0\,
      O => \col_lcl[10]_i_2_n_0\
    );
\col_lcl[10]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0111FFFF"
    )
        port map (
      I0 => \stateImdstream_reg_n_0_[0]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => \tkst_reg[0]_0\,
      I3 => p_1_in,
      I4 => \^rng_reg_0\,
      O => \col_lcl[10]_i_3_n_0\
    );
\col_lcl[10]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^col_lcl_reg[10]_0\(8),
      I1 => \^col_lcl_reg[10]_0\(7),
      I2 => \^col_lcl_reg[10]_0\(6),
      I3 => \col_lcl[9]_i_2__0_n_0\,
      I4 => \^col_lcl_reg[10]_0\(9),
      O => \col_lcl[10]_i_4_n_0\
    );
\col_lcl[10]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00005400"
    )
        port map (
      I0 => \stateImdstream[1]_i_2_n_0\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => \stateImdstream_reg_n_0_[0]\,
      I3 => \^rng_reg_0\,
      I4 => p_1_in,
      O => \col_lcl[10]_i_5_n_0\
    );
\col_lcl[1]__0_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00404000"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[1]\,
      I1 => \^rng_reg_0\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => \col_lcl_reg[1]__0_n_0\,
      I4 => \col_lcl_reg[0]__0_n_0\,
      O => \col_lcl[1]__0_i_1_n_0\
    );
\col_lcl[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \col_lcl[10]_i_5_n_0\,
      I1 => \^col_lcl_reg[10]_0\(1),
      I2 => \^col_lcl_reg[10]_0\(0),
      O => \col_lcl[1]_i_1_n_0\
    );
\col_lcl[2]__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008080008000800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \col_lcl_reg[2]__0_n_0\,
      I4 => \col_lcl_reg[1]__0_n_0\,
      I5 => \col_lcl_reg[0]__0_n_0\,
      O => \col_lcl[2]__0_i_1_n_0\
    );
\col_lcl[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \col_lcl[10]_i_5_n_0\,
      I1 => \^col_lcl_reg[10]_0\(0),
      I2 => \^col_lcl_reg[10]_0\(1),
      I3 => \^col_lcl_reg[10]_0\(2),
      O => \col_lcl[2]_i_1_n_0\
    );
\col_lcl[3]__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880808080808080"
    )
        port map (
      I0 => \col_lcl[8]__0_i_2_n_0\,
      I1 => \col_lcl[8]__0_i_3_n_0\,
      I2 => \col_lcl_reg[3]__0_n_0\,
      I3 => \col_lcl_reg[2]__0_n_0\,
      I4 => \col_lcl_reg[0]__0_n_0\,
      I5 => \col_lcl_reg[1]__0_n_0\,
      O => \col_lcl[3]__0_i_1_n_0\
    );
\col_lcl[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \col_lcl[10]_i_5_n_0\,
      I1 => \^col_lcl_reg[10]_0\(1),
      I2 => \^col_lcl_reg[10]_0\(0),
      I3 => \^col_lcl_reg[10]_0\(2),
      I4 => \^col_lcl_reg[10]_0\(3),
      O => \col_lcl[3]_i_1_n_0\
    );
\col_lcl[4]__0_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \col_lcl_reg[4]__0_n_0\,
      I4 => \col_lcl[4]__0_i_2_n_0\,
      O => \col_lcl[4]__0_i_1_n_0\
    );
\col_lcl[4]__0_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \col_lcl_reg[2]__0_n_0\,
      I1 => \col_lcl_reg[0]__0_n_0\,
      I2 => \col_lcl_reg[1]__0_n_0\,
      I3 => \col_lcl_reg[3]__0_n_0\,
      O => \col_lcl[4]__0_i_2_n_0\
    );
\col_lcl[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \col_lcl[10]_i_5_n_0\,
      I1 => \^col_lcl_reg[10]_0\(2),
      I2 => \^col_lcl_reg[10]_0\(0),
      I3 => \^col_lcl_reg[10]_0\(1),
      I4 => \^col_lcl_reg[10]_0\(3),
      I5 => \^col_lcl_reg[10]_0\(4),
      O => \col_lcl[4]_i_1_n_0\
    );
\col_lcl[5]__0_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \col_lcl_reg[5]__0_n_0\,
      I4 => \col_lcl[5]__0_i_2_n_0\,
      O => \col_lcl[5]__0_i_1_n_0\
    );
\col_lcl[5]__0_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \col_lcl_reg[3]__0_n_0\,
      I1 => \col_lcl_reg[1]__0_n_0\,
      I2 => \col_lcl_reg[0]__0_n_0\,
      I3 => \col_lcl_reg[2]__0_n_0\,
      I4 => \col_lcl_reg[4]__0_n_0\,
      O => \col_lcl[5]__0_i_2_n_0\
    );
\col_lcl[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \col_lcl[10]_i_5_n_0\,
      I1 => \col_lcl[5]_i_2__0_n_0\,
      I2 => \^col_lcl_reg[10]_0\(5),
      O => \col_lcl[5]_i_1_n_0\
    );
\col_lcl[5]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^col_lcl_reg[10]_0\(3),
      I1 => \^col_lcl_reg[10]_0\(1),
      I2 => \^col_lcl_reg[10]_0\(0),
      I3 => \^col_lcl_reg[10]_0\(2),
      I4 => \^col_lcl_reg[10]_0\(4),
      O => \col_lcl[5]_i_2__0_n_0\
    );
\col_lcl[6]__0_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \col_lcl_reg[6]__0_n_0\,
      I4 => \col_lcl[8]__0_i_4_n_0\,
      O => \col_lcl[6]__0_i_1_n_0\
    );
\col_lcl[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \col_lcl[10]_i_5_n_0\,
      I1 => \col_lcl[9]_i_2__0_n_0\,
      I2 => \^col_lcl_reg[10]_0\(6),
      O => \col_lcl[6]_i_1_n_0\
    );
\col_lcl[7]__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008080008000800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \col_lcl_reg[7]__0_n_0\,
      I4 => \col_lcl_reg[6]__0_n_0\,
      I5 => \col_lcl[8]__0_i_4_n_0\,
      O => \col_lcl[7]__0_i_1_n_0\
    );
\col_lcl[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \col_lcl[10]_i_5_n_0\,
      I1 => \col_lcl[9]_i_2__0_n_0\,
      I2 => \^col_lcl_reg[10]_0\(6),
      I3 => \^col_lcl_reg[10]_0\(7),
      O => \col_lcl[7]_i_1_n_0\
    );
\col_lcl[8]__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880808080808080"
    )
        port map (
      I0 => \col_lcl[8]__0_i_2_n_0\,
      I1 => \col_lcl[8]__0_i_3_n_0\,
      I2 => \col_lcl_reg[8]__0_n_0\,
      I3 => \col_lcl_reg[7]__0_n_0\,
      I4 => \col_lcl[8]__0_i_4_n_0\,
      I5 => \col_lcl_reg[6]__0_n_0\,
      O => \col_lcl[8]__0_i_1_n_0\
    );
\col_lcl[8]__0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[0]\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \^rng_reg_0\,
      O => \col_lcl[8]__0_i_2_n_0\
    );
\col_lcl[8]__0_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[0]\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      O => \col_lcl[8]__0_i_3_n_0\
    );
\col_lcl[8]__0_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \col_lcl_reg[4]__0_n_0\,
      I1 => \col_lcl_reg[2]__0_n_0\,
      I2 => \col_lcl_reg[0]__0_n_0\,
      I3 => \col_lcl_reg[1]__0_n_0\,
      I4 => \col_lcl_reg[3]__0_n_0\,
      I5 => \col_lcl_reg[5]__0_n_0\,
      O => \col_lcl[8]__0_i_4_n_0\
    );
\col_lcl[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F008000"
    )
        port map (
      I0 => \^col_lcl_reg[10]_0\(7),
      I1 => \^col_lcl_reg[10]_0\(6),
      I2 => \col_lcl[9]_i_2__0_n_0\,
      I3 => \col_lcl[10]_i_5_n_0\,
      I4 => \^col_lcl_reg[10]_0\(8),
      O => \col_lcl[8]_i_1__0_n_0\
    );
\col_lcl[9]__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008080008000800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \col_lcl_reg[9]__0_n_0\,
      I4 => \col_lcl_reg[8]__0_n_0\,
      I5 => \col_lcl[9]__0_i_2_n_0\,
      O => \col_lcl[9]__0_i_1_n_0\
    );
\col_lcl[9]__0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \col_lcl_reg[6]__0_n_0\,
      I1 => \col_lcl[8]__0_i_4_n_0\,
      I2 => \col_lcl_reg[7]__0_n_0\,
      O => \col_lcl[9]__0_i_2_n_0\
    );
\col_lcl[9]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF000080000000"
    )
        port map (
      I0 => \col_lcl[9]_i_2__0_n_0\,
      I1 => \^col_lcl_reg[10]_0\(6),
      I2 => \^col_lcl_reg[10]_0\(7),
      I3 => \^col_lcl_reg[10]_0\(8),
      I4 => \col_lcl[10]_i_5_n_0\,
      I5 => \^col_lcl_reg[10]_0\(9),
      O => \col_lcl[9]_i_1__0_n_0\
    );
\col_lcl[9]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^col_lcl_reg[10]_0\(4),
      I1 => \^col_lcl_reg[10]_0\(2),
      I2 => \^col_lcl_reg[10]_0\(0),
      I3 => \^col_lcl_reg[10]_0\(1),
      I4 => \^col_lcl_reg[10]_0\(3),
      I5 => \^col_lcl_reg[10]_0\(5),
      O => \col_lcl[9]_i_2__0_n_0\
    );
\col_lcl_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1__0_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[0]_i_1_n_0\,
      Q => \^col_lcl_reg[10]_0\(0)
    );
\col_lcl_reg[0]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__0_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[0]__0_i_1_n_0\,
      Q => \col_lcl_reg[0]__0_n_0\
    );
\col_lcl_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1__0_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[10]_i_2_n_0\,
      Q => \^col_lcl_reg[10]_0\(10)
    );
\col_lcl_reg[10]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__0_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[10]__0_i_2_n_0\,
      Q => \col_lcl_reg[10]__0_n_0\
    );
\col_lcl_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1__0_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[1]_i_1_n_0\,
      Q => \^col_lcl_reg[10]_0\(1)
    );
\col_lcl_reg[1]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__0_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[1]__0_i_1_n_0\,
      Q => \col_lcl_reg[1]__0_n_0\
    );
\col_lcl_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1__0_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[2]_i_1_n_0\,
      Q => \^col_lcl_reg[10]_0\(2)
    );
\col_lcl_reg[2]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__0_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[2]__0_i_1_n_0\,
      Q => \col_lcl_reg[2]__0_n_0\
    );
\col_lcl_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1__0_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[3]_i_1_n_0\,
      Q => \^col_lcl_reg[10]_0\(3)
    );
\col_lcl_reg[3]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__0_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[3]__0_i_1_n_0\,
      Q => \col_lcl_reg[3]__0_n_0\
    );
\col_lcl_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1__0_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[4]_i_1_n_0\,
      Q => \^col_lcl_reg[10]_0\(4)
    );
\col_lcl_reg[4]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__0_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[4]__0_i_1_n_0\,
      Q => \col_lcl_reg[4]__0_n_0\
    );
\col_lcl_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1__0_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[5]_i_1_n_0\,
      Q => \^col_lcl_reg[10]_0\(5)
    );
\col_lcl_reg[5]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__0_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[5]__0_i_1_n_0\,
      Q => \col_lcl_reg[5]__0_n_0\
    );
\col_lcl_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1__0_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[6]_i_1_n_0\,
      Q => \^col_lcl_reg[10]_0\(6)
    );
\col_lcl_reg[6]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__0_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[6]__0_i_1_n_0\,
      Q => \col_lcl_reg[6]__0_n_0\
    );
\col_lcl_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1__0_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[7]_i_1_n_0\,
      Q => \^col_lcl_reg[10]_0\(7)
    );
\col_lcl_reg[7]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__0_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[7]__0_i_1_n_0\,
      Q => \col_lcl_reg[7]__0_n_0\
    );
\col_lcl_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1__0_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[8]_i_1__0_n_0\,
      Q => \^col_lcl_reg[10]_0\(8)
    );
\col_lcl_reg[8]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__0_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[8]__0_i_1_n_0\,
      Q => \col_lcl_reg[8]__0_n_0\
    );
\col_lcl_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1__0_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[9]_i_1__0_n_0\,
      Q => \^col_lcl_reg[10]_0\(9)
    );
\col_lcl_reg[9]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__0_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \col_lcl[9]__0_i_1_n_0\,
      Q => \col_lcl_reg[9]__0_n_0\
    );
\colmax_lcl[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200020000000200"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \colmax_lcl_reg_n_0_[0]\,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \colmax_lcl_reg_n_0_[2]\,
      I5 => \colmax_lcl_reg_n_0_[1]\,
      O => \colmax_lcl[0]_i_1_n_0\
    );
\colmax_lcl[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00404000"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[1]\,
      I1 => \^rng_reg_0\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => \colmax_lcl_reg_n_0_[0]\,
      I4 => \colmax_lcl_reg_n_0_[1]\,
      O => \colmax_lcl[1]_i_1_n_0\
    );
\colmax_lcl[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAFEAA"
    )
        port map (
      I0 => \row_lcl[10]_i_1_n_0\,
      I1 => postNotLive_reg_n_0,
      I2 => ceMaxsel_reg_n_0,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \stateMaxsel_reg_n_0_[1]\,
      O => colmax_lcl
    );
\colmax_lcl[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040400040000000"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[1]\,
      I1 => \^rng_reg_0\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => \colmax_lcl_reg_n_0_[2]\,
      I4 => \colmax_lcl_reg_n_0_[1]\,
      I5 => \colmax_lcl_reg_n_0_[0]\,
      O => \colmax_lcl[2]_i_2_n_0\
    );
\colmax_lcl_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => colmax_lcl,
      CLR => linNotLog_reg_0,
      D => \colmax_lcl[0]_i_1_n_0\,
      Q => \colmax_lcl_reg_n_0_[0]\
    );
\colmax_lcl_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => colmax_lcl,
      CLR => linNotLog_reg_0,
      D => \colmax_lcl[1]_i_1_n_0\,
      Q => \colmax_lcl_reg_n_0_[1]\
    );
\colmax_lcl_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => colmax_lcl,
      CLR => linNotLog_reg_0,
      D => \colmax_lcl[2]_i_2_n_0\,
      Q => \colmax_lcl_reg_n_0_[2]\
    );
\colsumX4p1[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[84]\,
      O => \colsumX4p1[0]_i_1_n_0\
    );
\colsumX4p1[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[94]\,
      O => \colsumX4p1[10]_i_1_n_0\
    );
\colsumX4p1[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[95]\,
      O => \colsumX4p1[11]_i_1_n_0\
    );
\colsumX4p1[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[96]\,
      O => \colsumX4p1[12]_i_1_n_0\
    );
\colsumX4p1[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[97]\,
      O => \colsumX4p1[13]_i_1_n_0\
    );
\colsumX4p1[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[98]\,
      O => \colsumX4p1[14]_i_1_n_0\
    );
\colsumX4p1[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[99]\,
      O => \colsumX4p1[15]_i_1_n_0\
    );
\colsumX4p1[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => \colsumX_reg_n_0_[100]\,
      O => \colsumX4p1[16]_i_1_n_0\
    );
\colsumX4p1[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => \colsumX_reg_n_0_[101]\,
      O => \colsumX4p1[17]_i_1_n_0\
    );
\colsumX4p1[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => \colsumX_reg_n_0_[102]\,
      O => \colsumX4p1[18]_i_1_n_0\
    );
\colsumX4p1[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => \colsumX_reg_n_0_[103]\,
      O => \colsumX4p1[19]_i_1_n_0\
    );
\colsumX4p1[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[85]\,
      O => \colsumX4p1[1]_i_1_n_0\
    );
\colsumX4p1[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => \colsumX_reg_n_0_[104]\,
      O => \colsumX4p1[20]_i_1_n_0\
    );
\colsumX4p1[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[86]\,
      O => \colsumX4p1[2]_i_1_n_0\
    );
\colsumX4p1[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[87]\,
      O => \colsumX4p1[3]_i_1_n_0\
    );
\colsumX4p1[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[88]\,
      O => \colsumX4p1[4]_i_1_n_0\
    );
\colsumX4p1[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[89]\,
      O => \colsumX4p1[5]_i_1_n_0\
    );
\colsumX4p1[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[90]\,
      O => \colsumX4p1[6]_i_1_n_0\
    );
\colsumX4p1[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[91]\,
      O => \colsumX4p1[7]_i_1_n_0\
    );
\colsumX4p1[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[92]\,
      O => \colsumX4p1[8]_i_1_n_0\
    );
\colsumX4p1[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => \colsumX_reg_n_0_[93]\,
      O => \colsumX4p1[9]_i_1_n_0\
    );
\colsumX4p1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[0]_i_1_n_0\,
      Q => colsumX4p1(0)
    );
\colsumX4p1_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[10]_i_1_n_0\,
      Q => colsumX4p1(10)
    );
\colsumX4p1_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[11]_i_1_n_0\,
      Q => colsumX4p1(11)
    );
\colsumX4p1_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[12]_i_1_n_0\,
      Q => colsumX4p1(12)
    );
\colsumX4p1_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[13]_i_1_n_0\,
      Q => colsumX4p1(13)
    );
\colsumX4p1_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[14]_i_1_n_0\,
      Q => colsumX4p1(14)
    );
\colsumX4p1_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[15]_i_1_n_0\,
      Q => colsumX4p1(15)
    );
\colsumX4p1_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[16]_i_1_n_0\,
      Q => colsumX4p1(16)
    );
\colsumX4p1_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[17]_i_1_n_0\,
      Q => colsumX4p1(17)
    );
\colsumX4p1_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[18]_i_1_n_0\,
      Q => colsumX4p1(18)
    );
\colsumX4p1_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[19]_i_1_n_0\,
      Q => colsumX4p1(19)
    );
\colsumX4p1_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[1]_i_1_n_0\,
      Q => colsumX4p1(1)
    );
\colsumX4p1_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[20]_i_1_n_0\,
      Q => colsumX4p1(20)
    );
\colsumX4p1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[2]_i_1_n_0\,
      Q => colsumX4p1(2)
    );
\colsumX4p1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[3]_i_1_n_0\,
      Q => colsumX4p1(3)
    );
\colsumX4p1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[4]_i_1_n_0\,
      Q => colsumX4p1(4)
    );
\colsumX4p1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[5]_i_1_n_0\,
      Q => colsumX4p1(5)
    );
\colsumX4p1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[6]_i_1_n_0\,
      Q => colsumX4p1(6)
    );
\colsumX4p1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[7]_i_1_n_0\,
      Q => colsumX4p1(7)
    );
\colsumX4p1_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[8]_i_1_n_0\,
      Q => colsumX4p1(8)
    );
\colsumX4p1_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p1[9]_i_1_n_0\,
      Q => colsumX4p1(9)
    );
\colsumX4p2[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(0),
      O => \colsumX4p2[0]_i_1_n_0\
    );
\colsumX4p2[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(10),
      O => \colsumX4p2[10]_i_1_n_0\
    );
\colsumX4p2[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(11),
      O => \colsumX4p2[11]_i_1_n_0\
    );
\colsumX4p2[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(12),
      O => \colsumX4p2[12]_i_1_n_0\
    );
\colsumX4p2[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(13),
      O => \colsumX4p2[13]_i_1_n_0\
    );
\colsumX4p2[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(14),
      O => \colsumX4p2[14]_i_1_n_0\
    );
\colsumX4p2[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(15),
      O => \colsumX4p2[15]_i_1_n_0\
    );
\colsumX4p2[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => colsumX4p1(16),
      O => \colsumX4p2[16]_i_1_n_0\
    );
\colsumX4p2[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => colsumX4p1(17),
      O => \colsumX4p2[17]_i_1_n_0\
    );
\colsumX4p2[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => colsumX4p1(18),
      O => \colsumX4p2[18]_i_1_n_0\
    );
\colsumX4p2[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => colsumX4p1(19),
      O => \colsumX4p2[19]_i_1_n_0\
    );
\colsumX4p2[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(1),
      O => \colsumX4p2[1]_i_1_n_0\
    );
\colsumX4p2[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => colsumX4p1(20),
      O => \colsumX4p2[20]_i_1_n_0\
    );
\colsumX4p2[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(2),
      O => \colsumX4p2[2]_i_1_n_0\
    );
\colsumX4p2[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(3),
      O => \colsumX4p2[3]_i_1_n_0\
    );
\colsumX4p2[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(4),
      O => \colsumX4p2[4]_i_1_n_0\
    );
\colsumX4p2[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(5),
      O => \colsumX4p2[5]_i_1_n_0\
    );
\colsumX4p2[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(6),
      O => \colsumX4p2[6]_i_1_n_0\
    );
\colsumX4p2[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(7),
      O => \colsumX4p2[7]_i_1_n_0\
    );
\colsumX4p2[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(8),
      O => \colsumX4p2[8]_i_1_n_0\
    );
\colsumX4p2[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__9_n_0\,
      I1 => colsumX4p1(9),
      O => \colsumX4p2[9]_i_1_n_0\
    );
\colsumX4p2_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[0]_i_1_n_0\,
      Q => colsumX4p2(0)
    );
\colsumX4p2_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[10]_i_1_n_0\,
      Q => colsumX4p2(10)
    );
\colsumX4p2_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[11]_i_1_n_0\,
      Q => colsumX4p2(11)
    );
\colsumX4p2_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[12]_i_1_n_0\,
      Q => colsumX4p2(12)
    );
\colsumX4p2_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[13]_i_1_n_0\,
      Q => colsumX4p2(13)
    );
\colsumX4p2_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[14]_i_1_n_0\,
      Q => colsumX4p2(14)
    );
\colsumX4p2_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[15]_i_1_n_0\,
      Q => colsumX4p2(15)
    );
\colsumX4p2_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[16]_i_1_n_0\,
      Q => colsumX4p2(16)
    );
\colsumX4p2_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[17]_i_1_n_0\,
      Q => colsumX4p2(17)
    );
\colsumX4p2_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[18]_i_1_n_0\,
      Q => colsumX4p2(18)
    );
\colsumX4p2_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[19]_i_1_n_0\,
      Q => colsumX4p2(19)
    );
\colsumX4p2_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[1]_i_1_n_0\,
      Q => colsumX4p2(1)
    );
\colsumX4p2_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[20]_i_1_n_0\,
      Q => colsumX4p2(20)
    );
\colsumX4p2_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[2]_i_1_n_0\,
      Q => colsumX4p2(2)
    );
\colsumX4p2_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[3]_i_1_n_0\,
      Q => colsumX4p2(3)
    );
\colsumX4p2_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[4]_i_1_n_0\,
      Q => colsumX4p2(4)
    );
\colsumX4p2_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[5]_i_1_n_0\,
      Q => colsumX4p2(5)
    );
\colsumX4p2_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[6]_i_1_n_0\,
      Q => colsumX4p2(6)
    );
\colsumX4p2_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[7]_i_1_n_0\,
      Q => colsumX4p2(7)
    );
\colsumX4p2_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[8]_i_1_n_0\,
      Q => colsumX4p2(8)
    );
\colsumX4p2_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX4p2[9]_i_1_n_0\,
      Q => colsumX4p2(9)
    );
\colsumXA[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => \xsqr_reg_n_0_[0]\,
      I2 => RESIZE0_in(0),
      O => \colsumXA[0]_i_1_n_0\
    );
\colsumXA[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA0(10),
      O => \colsumXA[10]_i_1_n_0\
    );
\colsumXA[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA0(11),
      O => \colsumXA[11]_i_1_n_0\
    );
\colsumXA[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA0(12),
      O => \colsumXA[12]_i_1_n_0\
    );
\colsumXA[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA0(13),
      O => \colsumXA[13]_i_1_n_0\
    );
\colsumXA[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA0(14),
      O => \colsumXA[14]_i_1_n_0\
    );
\colsumXA[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA0(15),
      O => \colsumXA[15]_i_1_n_0\
    );
\colsumXA[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => colsumXA0(16),
      O => \colsumXA[16]_i_1_n_0\
    );
\colsumXA[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => colsumXA0(17),
      O => \colsumXA[17]_i_1_n_0\
    );
\colsumXA[17]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(11),
      I1 => \xsqr_reg_n_0_[11]\,
      O => \colsumXA[17]_i_10_n_0\
    );
\colsumXA[17]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(10),
      I1 => \xsqr_reg_n_0_[10]\,
      O => \colsumXA[17]_i_11_n_0\
    );
\colsumXA[17]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => RESIZE0_in(17),
      O => \colsumXA[17]_i_3_n_0\
    );
\colsumXA[17]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(17),
      I1 => \xsqr_reg_n_0_[17]\,
      O => \colsumXA[17]_i_4_n_0\
    );
\colsumXA[17]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(16),
      I1 => \xsqr_reg_n_0_[16]\,
      O => \colsumXA[17]_i_5_n_0\
    );
\colsumXA[17]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(15),
      I1 => \xsqr_reg_n_0_[15]\,
      O => \colsumXA[17]_i_6_n_0\
    );
\colsumXA[17]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(14),
      I1 => \xsqr_reg_n_0_[14]\,
      O => \colsumXA[17]_i_7_n_0\
    );
\colsumXA[17]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(13),
      I1 => \xsqr_reg_n_0_[13]\,
      O => \colsumXA[17]_i_8_n_0\
    );
\colsumXA[17]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(12),
      I1 => \xsqr_reg_n_0_[12]\,
      O => \colsumXA[17]_i_9_n_0\
    );
\colsumXA[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => \colsumXA_reg[18]_i_2_n_7\,
      O => \colsumXA[18]_i_1_n_0\
    );
\colsumXA[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => RESIZE(0),
      I2 => \xsqr_reg_n_0_[54]\,
      O => \colsumXA[19]_i_1_n_0\
    );
\colsumXA[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => RESIZE0_in(0),
      I2 => \xsqr_reg_n_0_[0]\,
      O => \colsumXA[1]_i_1_n_0\
    );
\colsumXA[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => \xsqr_reg_n_0_[54]\,
      I2 => RESIZE(0),
      O => \colsumXA[20]_i_1_n_0\
    );
\colsumXA[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA00_in(2),
      O => \colsumXA[21]_i_1_n_0\
    );
\colsumXA[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA00_in(3),
      O => \colsumXA[22]_i_1_n_0\
    );
\colsumXA[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA00_in(4),
      O => \colsumXA[23]_i_1_n_0\
    );
\colsumXA[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA00_in(5),
      O => \colsumXA[24]_i_1_n_0\
    );
\colsumXA[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA00_in(6),
      O => \colsumXA[25]_i_1_n_0\
    );
\colsumXA[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA00_in(7),
      O => \colsumXA[26]_i_1_n_0\
    );
\colsumXA[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA00_in(8),
      O => \colsumXA[27]_i_1_n_0\
    );
\colsumXA[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA00_in(9),
      O => \colsumXA[28]_i_1_n_0\
    );
\colsumXA[28]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[56]\,
      I1 => RESIZE(2),
      O => \colsumXA[28]_i_10_n_0\
    );
\colsumXA[28]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[63]\,
      I1 => RESIZE(9),
      O => \colsumXA[28]_i_3_n_0\
    );
\colsumXA[28]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[62]\,
      I1 => RESIZE(8),
      O => \colsumXA[28]_i_4_n_0\
    );
\colsumXA[28]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[61]\,
      I1 => RESIZE(7),
      O => \colsumXA[28]_i_5_n_0\
    );
\colsumXA[28]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[60]\,
      I1 => RESIZE(6),
      O => \colsumXA[28]_i_6_n_0\
    );
\colsumXA[28]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[59]\,
      I1 => RESIZE(5),
      O => \colsumXA[28]_i_7_n_0\
    );
\colsumXA[28]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[58]\,
      I1 => RESIZE(4),
      O => \colsumXA[28]_i_8_n_0\
    );
\colsumXA[28]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[57]\,
      I1 => RESIZE(3),
      O => \colsumXA[28]_i_9_n_0\
    );
\colsumXA[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA00_in(10),
      O => \colsumXA[29]_i_1_n_0\
    );
\colsumXA[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA0(2),
      O => \colsumXA[2]_i_1_n_0\
    );
\colsumXA[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA00_in(11),
      O => \colsumXA[30]_i_1_n_0\
    );
\colsumXA[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA00_in(12),
      O => \colsumXA[31]_i_1_n_0\
    );
\colsumXA[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA00_in(13),
      O => \colsumXA[32]_i_1_n_0\
    );
\colsumXA[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA00_in(14),
      O => \colsumXA[33]_i_1_n_0\
    );
\colsumXA[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA00_in(15),
      O => \colsumXA[34]_i_1_n_0\
    );
\colsumXA[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => colsumXA00_in(16),
      O => \colsumXA[35]_i_1_n_0\
    );
\colsumXA[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => colsumXA00_in(17),
      O => \colsumXA[36]_i_1_n_0\
    );
\colsumXA[36]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[65]\,
      I1 => RESIZE(11),
      O => \colsumXA[36]_i_10_n_0\
    );
\colsumXA[36]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[64]\,
      I1 => RESIZE(10),
      O => \colsumXA[36]_i_11_n_0\
    );
\colsumXA[36]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \xsqr_reg_n_0_[71]\,
      O => \colsumXA[36]_i_3_n_0\
    );
\colsumXA[36]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[71]\,
      I1 => RESIZE(17),
      O => \colsumXA[36]_i_4_n_0\
    );
\colsumXA[36]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[70]\,
      I1 => RESIZE(16),
      O => \colsumXA[36]_i_5_n_0\
    );
\colsumXA[36]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[69]\,
      I1 => RESIZE(15),
      O => \colsumXA[36]_i_6_n_0\
    );
\colsumXA[36]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[68]\,
      I1 => RESIZE(14),
      O => \colsumXA[36]_i_7_n_0\
    );
\colsumXA[36]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[67]\,
      I1 => RESIZE(13),
      O => \colsumXA[36]_i_8_n_0\
    );
\colsumXA[36]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \xsqr_reg_n_0_[66]\,
      I1 => RESIZE(12),
      O => \colsumXA[36]_i_9_n_0\
    );
\colsumXA[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => \colsumXA_reg[37]_i_2_n_7\,
      O => \colsumXA[37]_i_1_n_0\
    );
\colsumXA[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA0(3),
      O => \colsumXA[3]_i_1_n_0\
    );
\colsumXA[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA0(4),
      O => \colsumXA[4]_i_1_n_0\
    );
\colsumXA[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA0(5),
      O => \colsumXA[5]_i_1_n_0\
    );
\colsumXA[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA0(6),
      O => \colsumXA[6]_i_1_n_0\
    );
\colsumXA[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA0(7),
      O => \colsumXA[7]_i_1_n_0\
    );
\colsumXA[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA0(8),
      O => \colsumXA[8]_i_1_n_0\
    );
\colsumXA[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => colsumXA0(9),
      O => \colsumXA[9]_i_1_n_0\
    );
\colsumXA[9]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(2),
      I1 => \xsqr_reg_n_0_[2]\,
      O => \colsumXA[9]_i_10_n_0\
    );
\colsumXA[9]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(9),
      I1 => \xsqr_reg_n_0_[9]\,
      O => \colsumXA[9]_i_3_n_0\
    );
\colsumXA[9]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(8),
      I1 => \xsqr_reg_n_0_[8]\,
      O => \colsumXA[9]_i_4_n_0\
    );
\colsumXA[9]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(7),
      I1 => \xsqr_reg_n_0_[7]\,
      O => \colsumXA[9]_i_5_n_0\
    );
\colsumXA[9]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(6),
      I1 => \xsqr_reg_n_0_[6]\,
      O => \colsumXA[9]_i_6_n_0\
    );
\colsumXA[9]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(5),
      I1 => \xsqr_reg_n_0_[5]\,
      O => \colsumXA[9]_i_7_n_0\
    );
\colsumXA[9]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(4),
      I1 => \xsqr_reg_n_0_[4]\,
      O => \colsumXA[9]_i_8_n_0\
    );
\colsumXA[9]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RESIZE0_in(3),
      I1 => \xsqr_reg_n_0_[3]\,
      O => \colsumXA[9]_i_9_n_0\
    );
\colsumXA_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[0]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[0]\
    );
\colsumXA_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[10]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[10]\
    );
\colsumXA_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[11]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[11]\
    );
\colsumXA_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[12]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[12]\
    );
\colsumXA_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[13]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[13]\
    );
\colsumXA_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[14]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[14]\
    );
\colsumXA_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[15]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[15]\
    );
\colsumXA_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[16]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[16]\
    );
\colsumXA_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[17]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[17]\
    );
\colsumXA_reg[17]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXA_reg[9]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \colsumXA_reg[17]_i_2_n_0\,
      CO(6) => \colsumXA_reg[17]_i_2_n_1\,
      CO(5) => \colsumXA_reg[17]_i_2_n_2\,
      CO(4) => \colsumXA_reg[17]_i_2_n_3\,
      CO(3) => \colsumXA_reg[17]_i_2_n_4\,
      CO(2) => \colsumXA_reg[17]_i_2_n_5\,
      CO(1) => \colsumXA_reg[17]_i_2_n_6\,
      CO(0) => \colsumXA_reg[17]_i_2_n_7\,
      DI(7) => \colsumXA[17]_i_3_n_0\,
      DI(6 downto 0) => RESIZE0_in(16 downto 10),
      O(7 downto 0) => colsumXA0(17 downto 10),
      S(7) => \colsumXA[17]_i_4_n_0\,
      S(6) => \colsumXA[17]_i_5_n_0\,
      S(5) => \colsumXA[17]_i_6_n_0\,
      S(4) => \colsumXA[17]_i_7_n_0\,
      S(3) => \colsumXA[17]_i_8_n_0\,
      S(2) => \colsumXA[17]_i_9_n_0\,
      S(1) => \colsumXA[17]_i_10_n_0\,
      S(0) => \colsumXA[17]_i_11_n_0\
    );
\colsumXA_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[18]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[18]\
    );
\colsumXA_reg[18]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXA_reg[17]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 1) => \NLW_colsumXA_reg[18]_i_2_CO_UNCONNECTED\(7 downto 1),
      CO(0) => \colsumXA_reg[18]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_colsumXA_reg[18]_i_2_O_UNCONNECTED\(7 downto 0),
      S(7 downto 0) => B"00000001"
    );
\colsumXA_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[19]_i_1_n_0\,
      Q => ARG(19)
    );
\colsumXA_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[1]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[1]\
    );
\colsumXA_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[20]_i_1_n_0\,
      Q => ARG(20)
    );
\colsumXA_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[21]_i_1_n_0\,
      Q => ARG(21)
    );
\colsumXA_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[22]_i_1_n_0\,
      Q => ARG(22)
    );
\colsumXA_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[23]_i_1_n_0\,
      Q => ARG(23)
    );
\colsumXA_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[24]_i_1_n_0\,
      Q => ARG(24)
    );
\colsumXA_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[25]_i_1_n_0\,
      Q => ARG(25)
    );
\colsumXA_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[26]_i_1_n_0\,
      Q => ARG(26)
    );
\colsumXA_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[27]_i_1_n_0\,
      Q => ARG(27)
    );
\colsumXA_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[28]_i_1_n_0\,
      Q => ARG(28)
    );
\colsumXA_reg[28]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \colsumXA_reg[28]_i_2_n_0\,
      CO(6) => \colsumXA_reg[28]_i_2_n_1\,
      CO(5) => \colsumXA_reg[28]_i_2_n_2\,
      CO(4) => \colsumXA_reg[28]_i_2_n_3\,
      CO(3) => \colsumXA_reg[28]_i_2_n_4\,
      CO(2) => \colsumXA_reg[28]_i_2_n_5\,
      CO(1) => \colsumXA_reg[28]_i_2_n_6\,
      CO(0) => \colsumXA_reg[28]_i_2_n_7\,
      DI(7) => \xsqr_reg_n_0_[63]\,
      DI(6) => \xsqr_reg_n_0_[62]\,
      DI(5) => \xsqr_reg_n_0_[61]\,
      DI(4) => \xsqr_reg_n_0_[60]\,
      DI(3) => \xsqr_reg_n_0_[59]\,
      DI(2) => \xsqr_reg_n_0_[58]\,
      DI(1) => \xsqr_reg_n_0_[57]\,
      DI(0) => \xsqr_reg_n_0_[56]\,
      O(7 downto 0) => colsumXA00_in(9 downto 2),
      S(7) => \colsumXA[28]_i_3_n_0\,
      S(6) => \colsumXA[28]_i_4_n_0\,
      S(5) => \colsumXA[28]_i_5_n_0\,
      S(4) => \colsumXA[28]_i_6_n_0\,
      S(3) => \colsumXA[28]_i_7_n_0\,
      S(2) => \colsumXA[28]_i_8_n_0\,
      S(1) => \colsumXA[28]_i_9_n_0\,
      S(0) => \colsumXA[28]_i_10_n_0\
    );
\colsumXA_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[29]_i_1_n_0\,
      Q => ARG(29)
    );
\colsumXA_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[2]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[2]\
    );
\colsumXA_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[30]_i_1_n_0\,
      Q => ARG(30)
    );
\colsumXA_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[31]_i_1_n_0\,
      Q => ARG(31)
    );
\colsumXA_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[32]_i_1_n_0\,
      Q => ARG(32)
    );
\colsumXA_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[33]_i_1_n_0\,
      Q => ARG(33)
    );
\colsumXA_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[34]_i_1_n_0\,
      Q => ARG(34)
    );
\colsumXA_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[35]_i_1_n_0\,
      Q => ARG(35)
    );
\colsumXA_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[36]_i_1_n_0\,
      Q => ARG(36)
    );
\colsumXA_reg[36]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXA_reg[28]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \colsumXA_reg[36]_i_2_n_0\,
      CO(6) => \colsumXA_reg[36]_i_2_n_1\,
      CO(5) => \colsumXA_reg[36]_i_2_n_2\,
      CO(4) => \colsumXA_reg[36]_i_2_n_3\,
      CO(3) => \colsumXA_reg[36]_i_2_n_4\,
      CO(2) => \colsumXA_reg[36]_i_2_n_5\,
      CO(1) => \colsumXA_reg[36]_i_2_n_6\,
      CO(0) => \colsumXA_reg[36]_i_2_n_7\,
      DI(7) => \colsumXA[36]_i_3_n_0\,
      DI(6) => \xsqr_reg_n_0_[70]\,
      DI(5) => \xsqr_reg_n_0_[69]\,
      DI(4) => \xsqr_reg_n_0_[68]\,
      DI(3) => \xsqr_reg_n_0_[67]\,
      DI(2) => \xsqr_reg_n_0_[66]\,
      DI(1) => \xsqr_reg_n_0_[65]\,
      DI(0) => \xsqr_reg_n_0_[64]\,
      O(7 downto 0) => colsumXA00_in(17 downto 10),
      S(7) => \colsumXA[36]_i_4_n_0\,
      S(6) => \colsumXA[36]_i_5_n_0\,
      S(5) => \colsumXA[36]_i_6_n_0\,
      S(4) => \colsumXA[36]_i_7_n_0\,
      S(3) => \colsumXA[36]_i_8_n_0\,
      S(2) => \colsumXA[36]_i_9_n_0\,
      S(1) => \colsumXA[36]_i_10_n_0\,
      S(0) => \colsumXA[36]_i_11_n_0\
    );
\colsumXA_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[37]_i_1_n_0\,
      Q => ARG(37)
    );
\colsumXA_reg[37]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXA_reg[36]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 1) => \NLW_colsumXA_reg[37]_i_2_CO_UNCONNECTED\(7 downto 1),
      CO(0) => \colsumXA_reg[37]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_colsumXA_reg[37]_i_2_O_UNCONNECTED\(7 downto 0),
      S(7 downto 0) => B"00000001"
    );
\colsumXA_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[3]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[3]\
    );
\colsumXA_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[4]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[4]\
    );
\colsumXA_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[5]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[5]\
    );
\colsumXA_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[6]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[6]\
    );
\colsumXA_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[7]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[7]\
    );
\colsumXA_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[8]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[8]\
    );
\colsumXA_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXA[9]_i_1_n_0\,
      Q => \colsumXA_reg_n_0_[9]\
    );
\colsumXA_reg[9]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \colsumXA_reg[9]_i_2_n_0\,
      CO(6) => \colsumXA_reg[9]_i_2_n_1\,
      CO(5) => \colsumXA_reg[9]_i_2_n_2\,
      CO(4) => \colsumXA_reg[9]_i_2_n_3\,
      CO(3) => \colsumXA_reg[9]_i_2_n_4\,
      CO(2) => \colsumXA_reg[9]_i_2_n_5\,
      CO(1) => \colsumXA_reg[9]_i_2_n_6\,
      CO(0) => \colsumXA_reg[9]_i_2_n_7\,
      DI(7 downto 0) => RESIZE0_in(9 downto 2),
      O(7 downto 0) => colsumXA0(9 downto 2),
      S(7) => \colsumXA[9]_i_3_n_0\,
      S(6) => \colsumXA[9]_i_4_n_0\,
      S(5) => \colsumXA[9]_i_5_n_0\,
      S(4) => \colsumXA[9]_i_6_n_0\,
      S(3) => \colsumXA[9]_i_7_n_0\,
      S(2) => \colsumXA[9]_i_8_n_0\,
      S(1) => \colsumXA[9]_i_9_n_0\,
      S(0) => \colsumXA[9]_i_10_n_0\
    );
\colsumXB[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[15]\,
      I1 => ARG(34),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_10_n_0\
    );
\colsumXB[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[14]\,
      I1 => ARG(33),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_11_n_0\
    );
\colsumXB[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[13]\,
      I1 => ARG(32),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_12_n_0\
    );
\colsumXB[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[12]\,
      I1 => ARG(31),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_13_n_0\
    );
\colsumXB[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[11]\,
      I1 => ARG(30),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_14_n_0\
    );
\colsumXB[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[10]\,
      I1 => ARG(29),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_15_n_0\
    );
\colsumXB[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[9]\,
      I1 => ARG(28),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_16_n_0\
    );
\colsumXB[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[8]\,
      I1 => ARG(27),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_17_n_0\
    );
\colsumXB[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[15]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_2_n_0\
    );
\colsumXB[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[14]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_3_n_0\
    );
\colsumXB[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[13]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_4_n_0\
    );
\colsumXB[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[12]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_5_n_0\
    );
\colsumXB[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[11]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_6_n_0\
    );
\colsumXB[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[10]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_7_n_0\
    );
\colsumXB[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[9]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_8_n_0\
    );
\colsumXB[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[8]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[15]_i_9_n_0\
    );
\colsumXB[19]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[18]\,
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXB[19]_i_2_n_0\
    );
\colsumXB[19]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[17]\,
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXB[19]_i_3_n_0\
    );
\colsumXB[19]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[16]\,
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXB[19]_i_4_n_0\
    );
\colsumXB[19]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[18]\,
      I1 => ARG(37),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXB[19]_i_5_n_0\
    );
\colsumXB[19]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[18]\,
      I1 => ARG(37),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXB[19]_i_6_n_0\
    );
\colsumXB[19]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[17]\,
      I1 => ARG(36),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXB[19]_i_7_n_0\
    );
\colsumXB[19]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[16]\,
      I1 => ARG(35),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXB[19]_i_8_n_0\
    );
\colsumXB[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[7]\,
      I1 => ARG(26),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_10_n_0\
    );
\colsumXB[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[6]\,
      I1 => ARG(25),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_11_n_0\
    );
\colsumXB[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[5]\,
      I1 => ARG(24),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_12_n_0\
    );
\colsumXB[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[4]\,
      I1 => ARG(23),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_13_n_0\
    );
\colsumXB[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[3]\,
      I1 => ARG(22),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_14_n_0\
    );
\colsumXB[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[2]\,
      I1 => ARG(21),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_15_n_0\
    );
\colsumXB[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[1]\,
      I1 => ARG(20),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_16_n_0\
    );
\colsumXB[7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[0]\,
      I1 => ARG(19),
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_17_n_0\
    );
\colsumXB[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[7]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_2_n_0\
    );
\colsumXB[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[6]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_3_n_0\
    );
\colsumXB[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[5]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_4_n_0\
    );
\colsumXB[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[4]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_5_n_0\
    );
\colsumXB[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[3]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_6_n_0\
    );
\colsumXB[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[2]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_7_n_0\
    );
\colsumXB[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[1]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_8_n_0\
    );
\colsumXB[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \colsumXA_reg_n_0_[0]\,
      I1 => \stateScore_reg_rep__12_n_0\,
      O => \colsumXB[7]_i_9_n_0\
    );
\colsumXB_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[7]_i_1_n_15\,
      Q => colsumXB(0)
    );
\colsumXB_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[15]_i_1_n_13\,
      Q => colsumXB(10)
    );
\colsumXB_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[15]_i_1_n_12\,
      Q => colsumXB(11)
    );
\colsumXB_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[15]_i_1_n_11\,
      Q => colsumXB(12)
    );
\colsumXB_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[15]_i_1_n_10\,
      Q => colsumXB(13)
    );
\colsumXB_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[15]_i_1_n_9\,
      Q => colsumXB(14)
    );
\colsumXB_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[15]_i_1_n_8\,
      Q => colsumXB(15)
    );
\colsumXB_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXB_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \colsumXB_reg[15]_i_1_n_0\,
      CO(6) => \colsumXB_reg[15]_i_1_n_1\,
      CO(5) => \colsumXB_reg[15]_i_1_n_2\,
      CO(4) => \colsumXB_reg[15]_i_1_n_3\,
      CO(3) => \colsumXB_reg[15]_i_1_n_4\,
      CO(2) => \colsumXB_reg[15]_i_1_n_5\,
      CO(1) => \colsumXB_reg[15]_i_1_n_6\,
      CO(0) => \colsumXB_reg[15]_i_1_n_7\,
      DI(7) => \colsumXB[15]_i_2_n_0\,
      DI(6) => \colsumXB[15]_i_3_n_0\,
      DI(5) => \colsumXB[15]_i_4_n_0\,
      DI(4) => \colsumXB[15]_i_5_n_0\,
      DI(3) => \colsumXB[15]_i_6_n_0\,
      DI(2) => \colsumXB[15]_i_7_n_0\,
      DI(1) => \colsumXB[15]_i_8_n_0\,
      DI(0) => \colsumXB[15]_i_9_n_0\,
      O(7) => \colsumXB_reg[15]_i_1_n_8\,
      O(6) => \colsumXB_reg[15]_i_1_n_9\,
      O(5) => \colsumXB_reg[15]_i_1_n_10\,
      O(4) => \colsumXB_reg[15]_i_1_n_11\,
      O(3) => \colsumXB_reg[15]_i_1_n_12\,
      O(2) => \colsumXB_reg[15]_i_1_n_13\,
      O(1) => \colsumXB_reg[15]_i_1_n_14\,
      O(0) => \colsumXB_reg[15]_i_1_n_15\,
      S(7) => \colsumXB[15]_i_10_n_0\,
      S(6) => \colsumXB[15]_i_11_n_0\,
      S(5) => \colsumXB[15]_i_12_n_0\,
      S(4) => \colsumXB[15]_i_13_n_0\,
      S(3) => \colsumXB[15]_i_14_n_0\,
      S(2) => \colsumXB[15]_i_15_n_0\,
      S(1) => \colsumXB[15]_i_16_n_0\,
      S(0) => \colsumXB[15]_i_17_n_0\
    );
\colsumXB_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[19]_i_1_n_15\,
      Q => colsumXB(16)
    );
\colsumXB_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[19]_i_1_n_14\,
      Q => colsumXB(17)
    );
\colsumXB_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[19]_i_1_n_13\,
      Q => colsumXB(18)
    );
\colsumXB_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[19]_i_1_n_12\,
      Q => colsumXB(19)
    );
\colsumXB_reg[19]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXB_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_colsumXB_reg[19]_i_1_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \colsumXB_reg[19]_i_1_n_5\,
      CO(1) => \colsumXB_reg[19]_i_1_n_6\,
      CO(0) => \colsumXB_reg[19]_i_1_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \colsumXB[19]_i_2_n_0\,
      DI(1) => \colsumXB[19]_i_3_n_0\,
      DI(0) => \colsumXB[19]_i_4_n_0\,
      O(7 downto 4) => \NLW_colsumXB_reg[19]_i_1_O_UNCONNECTED\(7 downto 4),
      O(3) => \colsumXB_reg[19]_i_1_n_12\,
      O(2) => \colsumXB_reg[19]_i_1_n_13\,
      O(1) => \colsumXB_reg[19]_i_1_n_14\,
      O(0) => \colsumXB_reg[19]_i_1_n_15\,
      S(7 downto 4) => B"0000",
      S(3) => \colsumXB[19]_i_5_n_0\,
      S(2) => \colsumXB[19]_i_6_n_0\,
      S(1) => \colsumXB[19]_i_7_n_0\,
      S(0) => \colsumXB[19]_i_8_n_0\
    );
\colsumXB_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[7]_i_1_n_14\,
      Q => colsumXB(1)
    );
\colsumXB_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[7]_i_1_n_13\,
      Q => colsumXB(2)
    );
\colsumXB_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[7]_i_1_n_12\,
      Q => colsumXB(3)
    );
\colsumXB_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[7]_i_1_n_11\,
      Q => colsumXB(4)
    );
\colsumXB_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[7]_i_1_n_10\,
      Q => colsumXB(5)
    );
\colsumXB_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[7]_i_1_n_9\,
      Q => colsumXB(6)
    );
\colsumXB_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[7]_i_1_n_8\,
      Q => colsumXB(7)
    );
\colsumXB_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \colsumXB_reg[7]_i_1_n_0\,
      CO(6) => \colsumXB_reg[7]_i_1_n_1\,
      CO(5) => \colsumXB_reg[7]_i_1_n_2\,
      CO(4) => \colsumXB_reg[7]_i_1_n_3\,
      CO(3) => \colsumXB_reg[7]_i_1_n_4\,
      CO(2) => \colsumXB_reg[7]_i_1_n_5\,
      CO(1) => \colsumXB_reg[7]_i_1_n_6\,
      CO(0) => \colsumXB_reg[7]_i_1_n_7\,
      DI(7) => \colsumXB[7]_i_2_n_0\,
      DI(6) => \colsumXB[7]_i_3_n_0\,
      DI(5) => \colsumXB[7]_i_4_n_0\,
      DI(4) => \colsumXB[7]_i_5_n_0\,
      DI(3) => \colsumXB[7]_i_6_n_0\,
      DI(2) => \colsumXB[7]_i_7_n_0\,
      DI(1) => \colsumXB[7]_i_8_n_0\,
      DI(0) => \colsumXB[7]_i_9_n_0\,
      O(7) => \colsumXB_reg[7]_i_1_n_8\,
      O(6) => \colsumXB_reg[7]_i_1_n_9\,
      O(5) => \colsumXB_reg[7]_i_1_n_10\,
      O(4) => \colsumXB_reg[7]_i_1_n_11\,
      O(3) => \colsumXB_reg[7]_i_1_n_12\,
      O(2) => \colsumXB_reg[7]_i_1_n_13\,
      O(1) => \colsumXB_reg[7]_i_1_n_14\,
      O(0) => \colsumXB_reg[7]_i_1_n_15\,
      S(7) => \colsumXB[7]_i_10_n_0\,
      S(6) => \colsumXB[7]_i_11_n_0\,
      S(5) => \colsumXB[7]_i_12_n_0\,
      S(4) => \colsumXB[7]_i_13_n_0\,
      S(3) => \colsumXB[7]_i_14_n_0\,
      S(2) => \colsumXB[7]_i_15_n_0\,
      S(1) => \colsumXB[7]_i_16_n_0\,
      S(0) => \colsumXB[7]_i_17_n_0\
    );
\colsumXB_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[15]_i_1_n_15\,
      Q => colsumXB(8)
    );
\colsumXB_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXB_reg[15]_i_1_n_14\,
      Q => colsumXB(9)
    );
\colsumXC[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(15),
      I1 => colsumXB(15),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_10_n_0\
    );
\colsumXC[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(14),
      I1 => colsumXB(14),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_11_n_0\
    );
\colsumXC[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(13),
      I1 => colsumXB(13),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_12_n_0\
    );
\colsumXC[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(12),
      I1 => colsumXB(12),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_13_n_0\
    );
\colsumXC[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(11),
      I1 => colsumXB(11),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_14_n_0\
    );
\colsumXC[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(10),
      I1 => colsumXB(10),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_15_n_0\
    );
\colsumXC[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(9),
      I1 => colsumXB(9),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_16_n_0\
    );
\colsumXC[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(8),
      I1 => colsumXB(8),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_17_n_0\
    );
\colsumXC[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(15),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_2_n_0\
    );
\colsumXC[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(14),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_3_n_0\
    );
\colsumXC[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(13),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_4_n_0\
    );
\colsumXC[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(12),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_5_n_0\
    );
\colsumXC[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(11),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_6_n_0\
    );
\colsumXC[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(10),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_7_n_0\
    );
\colsumXC[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(9),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_8_n_0\
    );
\colsumXC[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(8),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[15]_i_9_n_0\
    );
\colsumXC[20]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(16),
      I1 => colsumXB(16),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXC[20]_i_10_n_0\
    );
\colsumXC[20]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(17),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXC[20]_i_2_n_0\
    );
\colsumXC[20]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(17),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXC[20]_i_3_n_0\
    );
\colsumXC[20]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(17),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXC[20]_i_4_n_0\
    );
\colsumXC[20]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(16),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXC[20]_i_5_n_0\
    );
\colsumXC[20]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(17),
      I1 => colsumXB(19),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXC[20]_i_6_n_0\
    );
\colsumXC[20]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(17),
      I1 => colsumXB(19),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXC[20]_i_7_n_0\
    );
\colsumXC[20]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(17),
      I1 => colsumXB(18),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXC[20]_i_8_n_0\
    );
\colsumXC[20]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(17),
      I1 => colsumXB(17),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXC[20]_i_9_n_0\
    );
\colsumXC[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(6),
      I1 => colsumXB(6),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[7]_i_10_n_0\
    );
\colsumXC[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(5),
      I1 => colsumXB(5),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[7]_i_11_n_0\
    );
\colsumXC[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(4),
      I1 => colsumXB(4),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[7]_i_12_n_0\
    );
\colsumXC[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(3),
      I1 => colsumXB(3),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[7]_i_13_n_0\
    );
\colsumXC[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(2),
      I1 => colsumXB(2),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[7]_i_14_n_0\
    );
\colsumXC[7]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => colsumXB(1),
      O => \colsumXC[7]_i_15_n_0\
    );
\colsumXC[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(0),
      I1 => colsumXB(0),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[7]_i_16_n_0\
    );
\colsumXC[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(7),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[7]_i_2_n_0\
    );
\colsumXC[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(6),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[7]_i_3_n_0\
    );
\colsumXC[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(5),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[7]_i_4_n_0\
    );
\colsumXC[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(4),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[7]_i_5_n_0\
    );
\colsumXC[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(3),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[7]_i_6_n_0\
    );
\colsumXC[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(2),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[7]_i_7_n_0\
    );
\colsumXC[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xsqr4p2(0),
      I1 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[7]_i_8_n_0\
    );
\colsumXC[7]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xsqr4p2(7),
      I1 => colsumXB(7),
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \colsumXC[7]_i_9_n_0\
    );
\colsumXC_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[7]_i_1_n_15\,
      Q => colsumX(21)
    );
\colsumXC_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[15]_i_1_n_13\,
      Q => colsumX(31)
    );
\colsumXC_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[15]_i_1_n_12\,
      Q => colsumX(32)
    );
\colsumXC_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[15]_i_1_n_11\,
      Q => colsumX(33)
    );
\colsumXC_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[15]_i_1_n_10\,
      Q => colsumX(34)
    );
\colsumXC_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[15]_i_1_n_9\,
      Q => colsumX(35)
    );
\colsumXC_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[15]_i_1_n_8\,
      Q => colsumX(36)
    );
\colsumXC_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXC_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \colsumXC_reg[15]_i_1_n_0\,
      CO(6) => \colsumXC_reg[15]_i_1_n_1\,
      CO(5) => \colsumXC_reg[15]_i_1_n_2\,
      CO(4) => \colsumXC_reg[15]_i_1_n_3\,
      CO(3) => \colsumXC_reg[15]_i_1_n_4\,
      CO(2) => \colsumXC_reg[15]_i_1_n_5\,
      CO(1) => \colsumXC_reg[15]_i_1_n_6\,
      CO(0) => \colsumXC_reg[15]_i_1_n_7\,
      DI(7) => \colsumXC[15]_i_2_n_0\,
      DI(6) => \colsumXC[15]_i_3_n_0\,
      DI(5) => \colsumXC[15]_i_4_n_0\,
      DI(4) => \colsumXC[15]_i_5_n_0\,
      DI(3) => \colsumXC[15]_i_6_n_0\,
      DI(2) => \colsumXC[15]_i_7_n_0\,
      DI(1) => \colsumXC[15]_i_8_n_0\,
      DI(0) => \colsumXC[15]_i_9_n_0\,
      O(7) => \colsumXC_reg[15]_i_1_n_8\,
      O(6) => \colsumXC_reg[15]_i_1_n_9\,
      O(5) => \colsumXC_reg[15]_i_1_n_10\,
      O(4) => \colsumXC_reg[15]_i_1_n_11\,
      O(3) => \colsumXC_reg[15]_i_1_n_12\,
      O(2) => \colsumXC_reg[15]_i_1_n_13\,
      O(1) => \colsumXC_reg[15]_i_1_n_14\,
      O(0) => \colsumXC_reg[15]_i_1_n_15\,
      S(7) => \colsumXC[15]_i_10_n_0\,
      S(6) => \colsumXC[15]_i_11_n_0\,
      S(5) => \colsumXC[15]_i_12_n_0\,
      S(4) => \colsumXC[15]_i_13_n_0\,
      S(3) => \colsumXC[15]_i_14_n_0\,
      S(2) => \colsumXC[15]_i_15_n_0\,
      S(1) => \colsumXC[15]_i_16_n_0\,
      S(0) => \colsumXC[15]_i_17_n_0\
    );
\colsumXC_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[20]_i_1_n_15\,
      Q => colsumX(37)
    );
\colsumXC_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[20]_i_1_n_14\,
      Q => colsumX(38)
    );
\colsumXC_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[20]_i_1_n_13\,
      Q => colsumX(39)
    );
\colsumXC_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[20]_i_1_n_12\,
      Q => colsumX(40)
    );
\colsumXC_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[7]_i_1_n_14\,
      Q => colsumX(22)
    );
\colsumXC_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[20]_i_1_n_11\,
      Q => colsumX(41)
    );
\colsumXC_reg[20]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXC_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_colsumXC_reg[20]_i_1_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \colsumXC_reg[20]_i_1_n_4\,
      CO(2) => \colsumXC_reg[20]_i_1_n_5\,
      CO(1) => \colsumXC_reg[20]_i_1_n_6\,
      CO(0) => \colsumXC_reg[20]_i_1_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3) => \colsumXC[20]_i_2_n_0\,
      DI(2) => \colsumXC[20]_i_3_n_0\,
      DI(1) => \colsumXC[20]_i_4_n_0\,
      DI(0) => \colsumXC[20]_i_5_n_0\,
      O(7 downto 5) => \NLW_colsumXC_reg[20]_i_1_O_UNCONNECTED\(7 downto 5),
      O(4) => \colsumXC_reg[20]_i_1_n_11\,
      O(3) => \colsumXC_reg[20]_i_1_n_12\,
      O(2) => \colsumXC_reg[20]_i_1_n_13\,
      O(1) => \colsumXC_reg[20]_i_1_n_14\,
      O(0) => \colsumXC_reg[20]_i_1_n_15\,
      S(7 downto 5) => B"000",
      S(4) => \colsumXC[20]_i_6_n_0\,
      S(3) => \colsumXC[20]_i_7_n_0\,
      S(2) => \colsumXC[20]_i_8_n_0\,
      S(1) => \colsumXC[20]_i_9_n_0\,
      S(0) => \colsumXC[20]_i_10_n_0\
    );
\colsumXC_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[7]_i_1_n_13\,
      Q => colsumX(23)
    );
\colsumXC_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[7]_i_1_n_12\,
      Q => colsumX(24)
    );
\colsumXC_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[7]_i_1_n_11\,
      Q => colsumX(25)
    );
\colsumXC_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[7]_i_1_n_10\,
      Q => colsumX(26)
    );
\colsumXC_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[7]_i_1_n_9\,
      Q => colsumX(27)
    );
\colsumXC_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[7]_i_1_n_8\,
      Q => colsumX(28)
    );
\colsumXC_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \colsumXC_reg[7]_i_1_n_0\,
      CO(6) => \colsumXC_reg[7]_i_1_n_1\,
      CO(5) => \colsumXC_reg[7]_i_1_n_2\,
      CO(4) => \colsumXC_reg[7]_i_1_n_3\,
      CO(3) => \colsumXC_reg[7]_i_1_n_4\,
      CO(2) => \colsumXC_reg[7]_i_1_n_5\,
      CO(1) => \colsumXC_reg[7]_i_1_n_6\,
      CO(0) => \colsumXC_reg[7]_i_1_n_7\,
      DI(7) => \colsumXC[7]_i_2_n_0\,
      DI(6) => \colsumXC[7]_i_3_n_0\,
      DI(5) => \colsumXC[7]_i_4_n_0\,
      DI(4) => \colsumXC[7]_i_5_n_0\,
      DI(3) => \colsumXC[7]_i_6_n_0\,
      DI(2) => \colsumXC[7]_i_7_n_0\,
      DI(1) => '0',
      DI(0) => \colsumXC[7]_i_8_n_0\,
      O(7) => \colsumXC_reg[7]_i_1_n_8\,
      O(6) => \colsumXC_reg[7]_i_1_n_9\,
      O(5) => \colsumXC_reg[7]_i_1_n_10\,
      O(4) => \colsumXC_reg[7]_i_1_n_11\,
      O(3) => \colsumXC_reg[7]_i_1_n_12\,
      O(2) => \colsumXC_reg[7]_i_1_n_13\,
      O(1) => \colsumXC_reg[7]_i_1_n_14\,
      O(0) => \colsumXC_reg[7]_i_1_n_15\,
      S(7) => \colsumXC[7]_i_9_n_0\,
      S(6) => \colsumXC[7]_i_10_n_0\,
      S(5) => \colsumXC[7]_i_11_n_0\,
      S(4) => \colsumXC[7]_i_12_n_0\,
      S(3) => \colsumXC[7]_i_13_n_0\,
      S(2) => \colsumXC[7]_i_14_n_0\,
      S(1) => \colsumXC[7]_i_15_n_0\,
      S(0) => \colsumXC[7]_i_16_n_0\
    );
\colsumXC_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[15]_i_1_n_15\,
      Q => colsumX(29)
    );
\colsumXC_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXC_reg[15]_i_1_n_14\,
      Q => colsumX(30)
    );
\colsumXY4p1[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[84]\,
      O => \colsumXY4p1[0]_i_1_n_0\
    );
\colsumXY4p1[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[94]\,
      O => \colsumXY4p1[10]_i_1_n_0\
    );
\colsumXY4p1[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[95]\,
      O => \colsumXY4p1[11]_i_1_n_0\
    );
\colsumXY4p1[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[96]\,
      O => \colsumXY4p1[12]_i_1_n_0\
    );
\colsumXY4p1[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[97]\,
      O => \colsumXY4p1[13]_i_1_n_0\
    );
\colsumXY4p1[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[98]\,
      O => \colsumXY4p1[14]_i_1_n_0\
    );
\colsumXY4p1[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[99]\,
      O => \colsumXY4p1[15]_i_1_n_0\
    );
\colsumXY4p1[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => \colsumXY_reg_n_0_[100]\,
      O => \colsumXY4p1[16]_i_1_n_0\
    );
\colsumXY4p1[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => \colsumXY_reg_n_0_[101]\,
      O => \colsumXY4p1[17]_i_1_n_0\
    );
\colsumXY4p1[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => \colsumXY_reg_n_0_[102]\,
      O => \colsumXY4p1[18]_i_1_n_0\
    );
\colsumXY4p1[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => \colsumXY_reg_n_0_[103]\,
      O => \colsumXY4p1[19]_i_1_n_0\
    );
\colsumXY4p1[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[85]\,
      O => \colsumXY4p1[1]_i_1_n_0\
    );
\colsumXY4p1[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => \colsumXY_reg_n_0_[104]\,
      O => \colsumXY4p1[20]_i_1_n_0\
    );
\colsumXY4p1[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[86]\,
      O => \colsumXY4p1[2]_i_1_n_0\
    );
\colsumXY4p1[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[87]\,
      O => \colsumXY4p1[3]_i_1_n_0\
    );
\colsumXY4p1[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[88]\,
      O => \colsumXY4p1[4]_i_1_n_0\
    );
\colsumXY4p1[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[89]\,
      O => \colsumXY4p1[5]_i_1_n_0\
    );
\colsumXY4p1[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[90]\,
      O => \colsumXY4p1[6]_i_1_n_0\
    );
\colsumXY4p1[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[91]\,
      O => \colsumXY4p1[7]_i_1_n_0\
    );
\colsumXY4p1[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[92]\,
      O => \colsumXY4p1[8]_i_1_n_0\
    );
\colsumXY4p1[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => \colsumXY_reg_n_0_[93]\,
      O => \colsumXY4p1[9]_i_1_n_0\
    );
\colsumXY4p1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[0]_i_1_n_0\,
      Q => colsumXY4p1(0)
    );
\colsumXY4p1_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[10]_i_1_n_0\,
      Q => colsumXY4p1(10)
    );
\colsumXY4p1_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[11]_i_1_n_0\,
      Q => colsumXY4p1(11)
    );
\colsumXY4p1_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[12]_i_1_n_0\,
      Q => colsumXY4p1(12)
    );
\colsumXY4p1_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[13]_i_1_n_0\,
      Q => colsumXY4p1(13)
    );
\colsumXY4p1_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[14]_i_1_n_0\,
      Q => colsumXY4p1(14)
    );
\colsumXY4p1_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[15]_i_1_n_0\,
      Q => colsumXY4p1(15)
    );
\colsumXY4p1_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[16]_i_1_n_0\,
      Q => colsumXY4p1(16)
    );
\colsumXY4p1_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[17]_i_1_n_0\,
      Q => colsumXY4p1(17)
    );
\colsumXY4p1_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[18]_i_1_n_0\,
      Q => colsumXY4p1(18)
    );
\colsumXY4p1_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[19]_i_1_n_0\,
      Q => colsumXY4p1(19)
    );
\colsumXY4p1_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[1]_i_1_n_0\,
      Q => colsumXY4p1(1)
    );
\colsumXY4p1_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[20]_i_1_n_0\,
      Q => colsumXY4p1(20)
    );
\colsumXY4p1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[2]_i_1_n_0\,
      Q => colsumXY4p1(2)
    );
\colsumXY4p1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[3]_i_1_n_0\,
      Q => colsumXY4p1(3)
    );
\colsumXY4p1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[4]_i_1_n_0\,
      Q => colsumXY4p1(4)
    );
\colsumXY4p1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[5]_i_1_n_0\,
      Q => colsumXY4p1(5)
    );
\colsumXY4p1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[6]_i_1_n_0\,
      Q => colsumXY4p1(6)
    );
\colsumXY4p1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[7]_i_1_n_0\,
      Q => colsumXY4p1(7)
    );
\colsumXY4p1_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[8]_i_1_n_0\,
      Q => colsumXY4p1(8)
    );
\colsumXY4p1_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p1[9]_i_1_n_0\,
      Q => colsumXY4p1(9)
    );
\colsumXY4p2[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(0),
      O => \colsumXY4p2[0]_i_1_n_0\
    );
\colsumXY4p2[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(10),
      O => \colsumXY4p2[10]_i_1_n_0\
    );
\colsumXY4p2[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(11),
      O => \colsumXY4p2[11]_i_1_n_0\
    );
\colsumXY4p2[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(12),
      O => \colsumXY4p2[12]_i_1_n_0\
    );
\colsumXY4p2[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(13),
      O => \colsumXY4p2[13]_i_1_n_0\
    );
\colsumXY4p2[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(14),
      O => \colsumXY4p2[14]_i_1_n_0\
    );
\colsumXY4p2[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(15),
      O => \colsumXY4p2[15]_i_1_n_0\
    );
\colsumXY4p2[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => colsumXY4p1(16),
      O => \colsumXY4p2[16]_i_1_n_0\
    );
\colsumXY4p2[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => colsumXY4p1(17),
      O => \colsumXY4p2[17]_i_1_n_0\
    );
\colsumXY4p2[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => colsumXY4p1(18),
      O => \colsumXY4p2[18]_i_1_n_0\
    );
\colsumXY4p2[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => colsumXY4p1(19),
      O => \colsumXY4p2[19]_i_1_n_0\
    );
\colsumXY4p2[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(1),
      O => \colsumXY4p2[1]_i_1_n_0\
    );
\colsumXY4p2[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => colsumXY4p1(20),
      O => \colsumXY4p2[20]_i_1_n_0\
    );
\colsumXY4p2[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(2),
      O => \colsumXY4p2[2]_i_1_n_0\
    );
\colsumXY4p2[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(3),
      O => \colsumXY4p2[3]_i_1_n_0\
    );
\colsumXY4p2[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(4),
      O => \colsumXY4p2[4]_i_1_n_0\
    );
\colsumXY4p2[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(5),
      O => \colsumXY4p2[5]_i_1_n_0\
    );
\colsumXY4p2[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(6),
      O => \colsumXY4p2[6]_i_1_n_0\
    );
\colsumXY4p2[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(7),
      O => \colsumXY4p2[7]_i_1_n_0\
    );
\colsumXY4p2[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(8),
      O => \colsumXY4p2[8]_i_1_n_0\
    );
\colsumXY4p2[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore,
      I1 => colsumXY4p1(9),
      O => \colsumXY4p2[9]_i_1_n_0\
    );
\colsumXY4p2_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[0]_i_1_n_0\,
      Q => colsumXY4p2(0)
    );
\colsumXY4p2_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[10]_i_1_n_0\,
      Q => colsumXY4p2(10)
    );
\colsumXY4p2_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[11]_i_1_n_0\,
      Q => colsumXY4p2(11)
    );
\colsumXY4p2_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[12]_i_1_n_0\,
      Q => colsumXY4p2(12)
    );
\colsumXY4p2_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[13]_i_1_n_0\,
      Q => colsumXY4p2(13)
    );
\colsumXY4p2_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[14]_i_1_n_0\,
      Q => colsumXY4p2(14)
    );
\colsumXY4p2_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[15]_i_1_n_0\,
      Q => colsumXY4p2(15)
    );
\colsumXY4p2_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[16]_i_1_n_0\,
      Q => colsumXY4p2(16)
    );
\colsumXY4p2_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[17]_i_1_n_0\,
      Q => colsumXY4p2(17)
    );
\colsumXY4p2_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[18]_i_1_n_0\,
      Q => colsumXY4p2(18)
    );
\colsumXY4p2_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[19]_i_1_n_0\,
      Q => colsumXY4p2(19)
    );
\colsumXY4p2_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[1]_i_1_n_0\,
      Q => colsumXY4p2(1)
    );
\colsumXY4p2_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[20]_i_1_n_0\,
      Q => colsumXY4p2(20)
    );
\colsumXY4p2_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[2]_i_1_n_0\,
      Q => colsumXY4p2(2)
    );
\colsumXY4p2_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[3]_i_1_n_0\,
      Q => colsumXY4p2(3)
    );
\colsumXY4p2_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[4]_i_1_n_0\,
      Q => colsumXY4p2(4)
    );
\colsumXY4p2_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[5]_i_1_n_0\,
      Q => colsumXY4p2(5)
    );
\colsumXY4p2_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[6]_i_1_n_0\,
      Q => colsumXY4p2(6)
    );
\colsumXY4p2_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[7]_i_1_n_0\,
      Q => colsumXY4p2(7)
    );
\colsumXY4p2_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[8]_i_1_n_0\,
      Q => colsumXY4p2(8)
    );
\colsumXY4p2_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY4p2[9]_i_1_n_0\,
      Q => colsumXY4p2(9)
    );
\colsumXYA[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(0),
      O => \colsumXYA[0]_i_1_n_0\
    );
\colsumXYA[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(10),
      O => \colsumXYA[10]_i_1_n_0\
    );
\colsumXYA[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(11),
      O => \colsumXYA[11]_i_1_n_0\
    );
\colsumXYA[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(12),
      O => \colsumXYA[12]_i_1_n_0\
    );
\colsumXYA[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(13),
      O => \colsumXYA[13]_i_1_n_0\
    );
\colsumXYA[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(14),
      O => \colsumXYA[14]_i_1_n_0\
    );
\colsumXYA[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(15),
      O => \colsumXYA[15]_i_1_n_0\
    );
\colsumXYA[15]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(26),
      I1 => xy(8),
      O => \colsumXYA[15]_i_10_n_0\
    );
\colsumXYA[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(33),
      I1 => xy(15),
      O => \colsumXYA[15]_i_3_n_0\
    );
\colsumXYA[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(32),
      I1 => xy(14),
      O => \colsumXYA[15]_i_4_n_0\
    );
\colsumXYA[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(31),
      I1 => xy(13),
      O => \colsumXYA[15]_i_5_n_0\
    );
\colsumXYA[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(30),
      I1 => xy(12),
      O => \colsumXYA[15]_i_6_n_0\
    );
\colsumXYA[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(29),
      I1 => xy(11),
      O => \colsumXYA[15]_i_7_n_0\
    );
\colsumXYA[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(28),
      I1 => xy(10),
      O => \colsumXYA[15]_i_8_n_0\
    );
\colsumXYA[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(27),
      I1 => xy(9),
      O => \colsumXYA[15]_i_9_n_0\
    );
\colsumXYA[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => colsumXYA0(16),
      O => \colsumXYA[16]_i_1_n_0\
    );
\colsumXYA[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => colsumXYA0(17),
      O => \colsumXYA[17]_i_1_n_0\
    );
\colsumXYA[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => \colsumXYA_reg[18]_i_2_n_5\,
      O => \colsumXYA[18]_i_1_n_0\
    );
\colsumXYA[18]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => xy(35),
      O => \colsumXYA[18]_i_3_n_0\
    );
\colsumXYA[18]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(35),
      I1 => xy(17),
      O => \colsumXYA[18]_i_4_n_0\
    );
\colsumXYA[18]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(34),
      I1 => xy(16),
      O => \colsumXYA[18]_i_5_n_0\
    );
\colsumXYA[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(0),
      O => \colsumXYA[19]_i_1_n_0\
    );
\colsumXYA[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(1),
      O => \colsumXYA[1]_i_1_n_0\
    );
\colsumXYA[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(1),
      O => \colsumXYA[20]_i_1_n_0\
    );
\colsumXYA[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(2),
      O => \colsumXYA[21]_i_1_n_0\
    );
\colsumXYA[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(3),
      O => \colsumXYA[22]_i_1_n_0\
    );
\colsumXYA[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(4),
      O => \colsumXYA[23]_i_1_n_0\
    );
\colsumXYA[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(5),
      O => \colsumXYA[24]_i_1_n_0\
    );
\colsumXYA[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(6),
      O => \colsumXYA[25]_i_1_n_0\
    );
\colsumXYA[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(7),
      O => \colsumXYA[26]_i_1_n_0\
    );
\colsumXYA[26]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(54),
      I1 => xy(36),
      O => \colsumXYA[26]_i_10_n_0\
    );
\colsumXYA[26]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(61),
      I1 => xy(43),
      O => \colsumXYA[26]_i_3_n_0\
    );
\colsumXYA[26]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(60),
      I1 => xy(42),
      O => \colsumXYA[26]_i_4_n_0\
    );
\colsumXYA[26]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(59),
      I1 => xy(41),
      O => \colsumXYA[26]_i_5_n_0\
    );
\colsumXYA[26]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(58),
      I1 => xy(40),
      O => \colsumXYA[26]_i_6_n_0\
    );
\colsumXYA[26]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(57),
      I1 => xy(39),
      O => \colsumXYA[26]_i_7_n_0\
    );
\colsumXYA[26]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(56),
      I1 => xy(38),
      O => \colsumXYA[26]_i_8_n_0\
    );
\colsumXYA[26]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(55),
      I1 => xy(37),
      O => \colsumXYA[26]_i_9_n_0\
    );
\colsumXYA[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(8),
      O => \colsumXYA[27]_i_1_n_0\
    );
\colsumXYA[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(9),
      O => \colsumXYA[28]_i_1_n_0\
    );
\colsumXYA[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(10),
      O => \colsumXYA[29]_i_1_n_0\
    );
\colsumXYA[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(2),
      O => \colsumXYA[2]_i_1_n_0\
    );
\colsumXYA[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(11),
      O => \colsumXYA[30]_i_1_n_0\
    );
\colsumXYA[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(12),
      O => \colsumXYA[31]_i_1_n_0\
    );
\colsumXYA[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(13),
      O => \colsumXYA[32]_i_1_n_0\
    );
\colsumXYA[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(14),
      O => \colsumXYA[33]_i_1_n_0\
    );
\colsumXYA[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA00_in(15),
      O => \colsumXYA[34]_i_1_n_0\
    );
\colsumXYA[34]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(62),
      I1 => xy(44),
      O => \colsumXYA[34]_i_10_n_0\
    );
\colsumXYA[34]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(69),
      I1 => xy(51),
      O => \colsumXYA[34]_i_3_n_0\
    );
\colsumXYA[34]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(68),
      I1 => xy(50),
      O => \colsumXYA[34]_i_4_n_0\
    );
\colsumXYA[34]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(67),
      I1 => xy(49),
      O => \colsumXYA[34]_i_5_n_0\
    );
\colsumXYA[34]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(66),
      I1 => xy(48),
      O => \colsumXYA[34]_i_6_n_0\
    );
\colsumXYA[34]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(65),
      I1 => xy(47),
      O => \colsumXYA[34]_i_7_n_0\
    );
\colsumXYA[34]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(64),
      I1 => xy(46),
      O => \colsumXYA[34]_i_8_n_0\
    );
\colsumXYA[34]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(63),
      I1 => xy(45),
      O => \colsumXYA[34]_i_9_n_0\
    );
\colsumXYA[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => colsumXYA00_in(16),
      O => \colsumXYA[35]_i_1_n_0\
    );
\colsumXYA[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => colsumXYA00_in(17),
      O => \colsumXYA[36]_i_1_n_0\
    );
\colsumXYA[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => \colsumXYA_reg[37]_i_2_n_5\,
      O => \colsumXYA[37]_i_1_n_0\
    );
\colsumXYA[37]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => xy(71),
      O => \colsumXYA[37]_i_3_n_0\
    );
\colsumXYA[37]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(71),
      I1 => xy(53),
      O => \colsumXYA[37]_i_4_n_0\
    );
\colsumXYA[37]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(70),
      I1 => xy(52),
      O => \colsumXYA[37]_i_5_n_0\
    );
\colsumXYA[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(3),
      O => \colsumXYA[3]_i_1_n_0\
    );
\colsumXYA[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(4),
      O => \colsumXYA[4]_i_1_n_0\
    );
\colsumXYA[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(5),
      O => \colsumXYA[5]_i_1_n_0\
    );
\colsumXYA[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(6),
      O => \colsumXYA[6]_i_1_n_0\
    );
\colsumXYA[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(7),
      O => \colsumXYA[7]_i_1_n_0\
    );
\colsumXYA[7]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(18),
      I1 => xy(0),
      O => \colsumXYA[7]_i_10_n_0\
    );
\colsumXYA[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(25),
      I1 => xy(7),
      O => \colsumXYA[7]_i_3_n_0\
    );
\colsumXYA[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(24),
      I1 => xy(6),
      O => \colsumXYA[7]_i_4_n_0\
    );
\colsumXYA[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(23),
      I1 => xy(5),
      O => \colsumXYA[7]_i_5_n_0\
    );
\colsumXYA[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(22),
      I1 => xy(4),
      O => \colsumXYA[7]_i_6_n_0\
    );
\colsumXYA[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(21),
      I1 => xy(3),
      O => \colsumXYA[7]_i_7_n_0\
    );
\colsumXYA[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(20),
      I1 => xy(2),
      O => \colsumXYA[7]_i_8_n_0\
    );
\colsumXYA[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xy(19),
      I1 => xy(1),
      O => \colsumXYA[7]_i_9_n_0\
    );
\colsumXYA[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(8),
      O => \colsumXYA[8]_i_1_n_0\
    );
\colsumXYA[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => colsumXYA0(9),
      O => \colsumXYA[9]_i_1_n_0\
    );
\colsumXYA_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[0]_i_1_n_0\,
      Q => colsumXYA(0)
    );
\colsumXYA_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[10]_i_1_n_0\,
      Q => colsumXYA(10)
    );
\colsumXYA_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[11]_i_1_n_0\,
      Q => colsumXYA(11)
    );
\colsumXYA_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[12]_i_1_n_0\,
      Q => colsumXYA(12)
    );
\colsumXYA_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[13]_i_1_n_0\,
      Q => colsumXYA(13)
    );
\colsumXYA_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[14]_i_1_n_0\,
      Q => colsumXYA(14)
    );
\colsumXYA_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[15]_i_1_n_0\,
      Q => colsumXYA(15)
    );
\colsumXYA_reg[15]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXYA_reg[7]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \colsumXYA_reg[15]_i_2_n_0\,
      CO(6) => \colsumXYA_reg[15]_i_2_n_1\,
      CO(5) => \colsumXYA_reg[15]_i_2_n_2\,
      CO(4) => \colsumXYA_reg[15]_i_2_n_3\,
      CO(3) => \colsumXYA_reg[15]_i_2_n_4\,
      CO(2) => \colsumXYA_reg[15]_i_2_n_5\,
      CO(1) => \colsumXYA_reg[15]_i_2_n_6\,
      CO(0) => \colsumXYA_reg[15]_i_2_n_7\,
      DI(7 downto 0) => xy(33 downto 26),
      O(7 downto 0) => colsumXYA0(15 downto 8),
      S(7) => \colsumXYA[15]_i_3_n_0\,
      S(6) => \colsumXYA[15]_i_4_n_0\,
      S(5) => \colsumXYA[15]_i_5_n_0\,
      S(4) => \colsumXYA[15]_i_6_n_0\,
      S(3) => \colsumXYA[15]_i_7_n_0\,
      S(2) => \colsumXYA[15]_i_8_n_0\,
      S(1) => \colsumXYA[15]_i_9_n_0\,
      S(0) => \colsumXYA[15]_i_10_n_0\
    );
\colsumXYA_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[16]_i_1_n_0\,
      Q => colsumXYA(16)
    );
\colsumXYA_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[17]_i_1_n_0\,
      Q => colsumXYA(17)
    );
\colsumXYA_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[18]_i_1_n_0\,
      Q => colsumXYA(18)
    );
\colsumXYA_reg[18]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXYA_reg[15]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_colsumXYA_reg[18]_i_2_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \colsumXYA_reg[18]_i_2_n_5\,
      CO(1) => \NLW_colsumXYA_reg[18]_i_2_CO_UNCONNECTED\(1),
      CO(0) => \colsumXYA_reg[18]_i_2_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \colsumXYA[18]_i_3_n_0\,
      DI(0) => xy(34),
      O(7 downto 2) => \NLW_colsumXYA_reg[18]_i_2_O_UNCONNECTED\(7 downto 2),
      O(1 downto 0) => colsumXYA0(17 downto 16),
      S(7 downto 2) => B"000001",
      S(1) => \colsumXYA[18]_i_4_n_0\,
      S(0) => \colsumXYA[18]_i_5_n_0\
    );
\colsumXYA_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[19]_i_1_n_0\,
      Q => colsumXYA(19)
    );
\colsumXYA_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[1]_i_1_n_0\,
      Q => colsumXYA(1)
    );
\colsumXYA_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[20]_i_1_n_0\,
      Q => colsumXYA(20)
    );
\colsumXYA_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[21]_i_1_n_0\,
      Q => colsumXYA(21)
    );
\colsumXYA_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[22]_i_1_n_0\,
      Q => colsumXYA(22)
    );
\colsumXYA_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[23]_i_1_n_0\,
      Q => colsumXYA(23)
    );
\colsumXYA_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[24]_i_1_n_0\,
      Q => colsumXYA(24)
    );
\colsumXYA_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[25]_i_1_n_0\,
      Q => colsumXYA(25)
    );
\colsumXYA_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[26]_i_1_n_0\,
      Q => colsumXYA(26)
    );
\colsumXYA_reg[26]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \colsumXYA_reg[26]_i_2_n_0\,
      CO(6) => \colsumXYA_reg[26]_i_2_n_1\,
      CO(5) => \colsumXYA_reg[26]_i_2_n_2\,
      CO(4) => \colsumXYA_reg[26]_i_2_n_3\,
      CO(3) => \colsumXYA_reg[26]_i_2_n_4\,
      CO(2) => \colsumXYA_reg[26]_i_2_n_5\,
      CO(1) => \colsumXYA_reg[26]_i_2_n_6\,
      CO(0) => \colsumXYA_reg[26]_i_2_n_7\,
      DI(7 downto 0) => xy(61 downto 54),
      O(7 downto 0) => colsumXYA00_in(7 downto 0),
      S(7) => \colsumXYA[26]_i_3_n_0\,
      S(6) => \colsumXYA[26]_i_4_n_0\,
      S(5) => \colsumXYA[26]_i_5_n_0\,
      S(4) => \colsumXYA[26]_i_6_n_0\,
      S(3) => \colsumXYA[26]_i_7_n_0\,
      S(2) => \colsumXYA[26]_i_8_n_0\,
      S(1) => \colsumXYA[26]_i_9_n_0\,
      S(0) => \colsumXYA[26]_i_10_n_0\
    );
\colsumXYA_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[27]_i_1_n_0\,
      Q => colsumXYA(27)
    );
\colsumXYA_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[28]_i_1_n_0\,
      Q => colsumXYA(28)
    );
\colsumXYA_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[29]_i_1_n_0\,
      Q => colsumXYA(29)
    );
\colsumXYA_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[2]_i_1_n_0\,
      Q => colsumXYA(2)
    );
\colsumXYA_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[30]_i_1_n_0\,
      Q => colsumXYA(30)
    );
\colsumXYA_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[31]_i_1_n_0\,
      Q => colsumXYA(31)
    );
\colsumXYA_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[32]_i_1_n_0\,
      Q => colsumXYA(32)
    );
\colsumXYA_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[33]_i_1_n_0\,
      Q => colsumXYA(33)
    );
\colsumXYA_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[34]_i_1_n_0\,
      Q => colsumXYA(34)
    );
\colsumXYA_reg[34]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXYA_reg[26]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \colsumXYA_reg[34]_i_2_n_0\,
      CO(6) => \colsumXYA_reg[34]_i_2_n_1\,
      CO(5) => \colsumXYA_reg[34]_i_2_n_2\,
      CO(4) => \colsumXYA_reg[34]_i_2_n_3\,
      CO(3) => \colsumXYA_reg[34]_i_2_n_4\,
      CO(2) => \colsumXYA_reg[34]_i_2_n_5\,
      CO(1) => \colsumXYA_reg[34]_i_2_n_6\,
      CO(0) => \colsumXYA_reg[34]_i_2_n_7\,
      DI(7 downto 0) => xy(69 downto 62),
      O(7 downto 0) => colsumXYA00_in(15 downto 8),
      S(7) => \colsumXYA[34]_i_3_n_0\,
      S(6) => \colsumXYA[34]_i_4_n_0\,
      S(5) => \colsumXYA[34]_i_5_n_0\,
      S(4) => \colsumXYA[34]_i_6_n_0\,
      S(3) => \colsumXYA[34]_i_7_n_0\,
      S(2) => \colsumXYA[34]_i_8_n_0\,
      S(1) => \colsumXYA[34]_i_9_n_0\,
      S(0) => \colsumXYA[34]_i_10_n_0\
    );
\colsumXYA_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[35]_i_1_n_0\,
      Q => colsumXYA(35)
    );
\colsumXYA_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[36]_i_1_n_0\,
      Q => colsumXYA(36)
    );
\colsumXYA_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[37]_i_1_n_0\,
      Q => colsumXYA(37)
    );
\colsumXYA_reg[37]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXYA_reg[34]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_colsumXYA_reg[37]_i_2_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \colsumXYA_reg[37]_i_2_n_5\,
      CO(1) => \NLW_colsumXYA_reg[37]_i_2_CO_UNCONNECTED\(1),
      CO(0) => \colsumXYA_reg[37]_i_2_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \colsumXYA[37]_i_3_n_0\,
      DI(0) => xy(70),
      O(7 downto 2) => \NLW_colsumXYA_reg[37]_i_2_O_UNCONNECTED\(7 downto 2),
      O(1 downto 0) => colsumXYA00_in(17 downto 16),
      S(7 downto 2) => B"000001",
      S(1) => \colsumXYA[37]_i_4_n_0\,
      S(0) => \colsumXYA[37]_i_5_n_0\
    );
\colsumXYA_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[3]_i_1_n_0\,
      Q => colsumXYA(3)
    );
\colsumXYA_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[4]_i_1_n_0\,
      Q => colsumXYA(4)
    );
\colsumXYA_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[5]_i_1_n_0\,
      Q => colsumXYA(5)
    );
\colsumXYA_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[6]_i_1_n_0\,
      Q => colsumXYA(6)
    );
\colsumXYA_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[7]_i_1_n_0\,
      Q => colsumXYA(7)
    );
\colsumXYA_reg[7]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \colsumXYA_reg[7]_i_2_n_0\,
      CO(6) => \colsumXYA_reg[7]_i_2_n_1\,
      CO(5) => \colsumXYA_reg[7]_i_2_n_2\,
      CO(4) => \colsumXYA_reg[7]_i_2_n_3\,
      CO(3) => \colsumXYA_reg[7]_i_2_n_4\,
      CO(2) => \colsumXYA_reg[7]_i_2_n_5\,
      CO(1) => \colsumXYA_reg[7]_i_2_n_6\,
      CO(0) => \colsumXYA_reg[7]_i_2_n_7\,
      DI(7 downto 0) => xy(25 downto 18),
      O(7 downto 0) => colsumXYA0(7 downto 0),
      S(7) => \colsumXYA[7]_i_3_n_0\,
      S(6) => \colsumXYA[7]_i_4_n_0\,
      S(5) => \colsumXYA[7]_i_5_n_0\,
      S(4) => \colsumXYA[7]_i_6_n_0\,
      S(3) => \colsumXYA[7]_i_7_n_0\,
      S(2) => \colsumXYA[7]_i_8_n_0\,
      S(1) => \colsumXYA[7]_i_9_n_0\,
      S(0) => \colsumXYA[7]_i_10_n_0\
    );
\colsumXYA_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[8]_i_1_n_0\,
      Q => colsumXYA(8)
    );
\colsumXYA_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYA[9]_i_1_n_0\,
      Q => colsumXYA(9)
    );
\colsumXYB[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(15),
      I1 => colsumXYA(34),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_10_n_0\
    );
\colsumXYB[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(14),
      I1 => colsumXYA(33),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_11_n_0\
    );
\colsumXYB[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(13),
      I1 => colsumXYA(32),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_12_n_0\
    );
\colsumXYB[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(12),
      I1 => colsumXYA(31),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_13_n_0\
    );
\colsumXYB[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(11),
      I1 => colsumXYA(30),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_14_n_0\
    );
\colsumXYB[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(10),
      I1 => colsumXYA(29),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_15_n_0\
    );
\colsumXYB[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(9),
      I1 => colsumXYA(28),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_16_n_0\
    );
\colsumXYB[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(8),
      I1 => colsumXYA(27),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_17_n_0\
    );
\colsumXYB[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(15),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_2_n_0\
    );
\colsumXYB[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(14),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_3_n_0\
    );
\colsumXYB[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(13),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_4_n_0\
    );
\colsumXYB[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(12),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_5_n_0\
    );
\colsumXYB[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(11),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_6_n_0\
    );
\colsumXYB[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(10),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_7_n_0\
    );
\colsumXYB[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(9),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_8_n_0\
    );
\colsumXYB[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(8),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[15]_i_9_n_0\
    );
\colsumXYB[19]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(18),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYB[19]_i_2_n_0\
    );
\colsumXYB[19]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(17),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYB[19]_i_3_n_0\
    );
\colsumXYB[19]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(16),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYB[19]_i_4_n_0\
    );
\colsumXYB[19]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(18),
      I1 => colsumXYA(37),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYB[19]_i_5_n_0\
    );
\colsumXYB[19]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(18),
      I1 => colsumXYA(37),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYB[19]_i_6_n_0\
    );
\colsumXYB[19]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(17),
      I1 => colsumXYA(36),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYB[19]_i_7_n_0\
    );
\colsumXYB[19]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(16),
      I1 => colsumXYA(35),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYB[19]_i_8_n_0\
    );
\colsumXYB[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(7),
      I1 => colsumXYA(26),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_10_n_0\
    );
\colsumXYB[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(6),
      I1 => colsumXYA(25),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_11_n_0\
    );
\colsumXYB[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(5),
      I1 => colsumXYA(24),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_12_n_0\
    );
\colsumXYB[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(4),
      I1 => colsumXYA(23),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_13_n_0\
    );
\colsumXYB[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(3),
      I1 => colsumXYA(22),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_14_n_0\
    );
\colsumXYB[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(2),
      I1 => colsumXYA(21),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_15_n_0\
    );
\colsumXYB[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(1),
      I1 => colsumXYA(20),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_16_n_0\
    );
\colsumXYB[7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXYA(0),
      I1 => colsumXYA(19),
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_17_n_0\
    );
\colsumXYB[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(7),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_2_n_0\
    );
\colsumXYB[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(6),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_3_n_0\
    );
\colsumXYB[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(5),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_4_n_0\
    );
\colsumXYB[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(4),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_5_n_0\
    );
\colsumXYB[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(3),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_6_n_0\
    );
\colsumXYB[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(2),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_7_n_0\
    );
\colsumXYB[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(1),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_8_n_0\
    );
\colsumXYB[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXYA(0),
      I1 => \stateScore_reg_rep__1_n_0\,
      O => \colsumXYB[7]_i_9_n_0\
    );
\colsumXYB_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[7]_i_1_n_15\,
      Q => colsumXYB(0)
    );
\colsumXYB_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[15]_i_1_n_13\,
      Q => colsumXYB(10)
    );
\colsumXYB_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[15]_i_1_n_12\,
      Q => colsumXYB(11)
    );
\colsumXYB_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[15]_i_1_n_11\,
      Q => colsumXYB(12)
    );
\colsumXYB_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[15]_i_1_n_10\,
      Q => colsumXYB(13)
    );
\colsumXYB_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[15]_i_1_n_9\,
      Q => colsumXYB(14)
    );
\colsumXYB_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[15]_i_1_n_8\,
      Q => colsumXYB(15)
    );
\colsumXYB_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXYB_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \colsumXYB_reg[15]_i_1_n_0\,
      CO(6) => \colsumXYB_reg[15]_i_1_n_1\,
      CO(5) => \colsumXYB_reg[15]_i_1_n_2\,
      CO(4) => \colsumXYB_reg[15]_i_1_n_3\,
      CO(3) => \colsumXYB_reg[15]_i_1_n_4\,
      CO(2) => \colsumXYB_reg[15]_i_1_n_5\,
      CO(1) => \colsumXYB_reg[15]_i_1_n_6\,
      CO(0) => \colsumXYB_reg[15]_i_1_n_7\,
      DI(7) => \colsumXYB[15]_i_2_n_0\,
      DI(6) => \colsumXYB[15]_i_3_n_0\,
      DI(5) => \colsumXYB[15]_i_4_n_0\,
      DI(4) => \colsumXYB[15]_i_5_n_0\,
      DI(3) => \colsumXYB[15]_i_6_n_0\,
      DI(2) => \colsumXYB[15]_i_7_n_0\,
      DI(1) => \colsumXYB[15]_i_8_n_0\,
      DI(0) => \colsumXYB[15]_i_9_n_0\,
      O(7) => \colsumXYB_reg[15]_i_1_n_8\,
      O(6) => \colsumXYB_reg[15]_i_1_n_9\,
      O(5) => \colsumXYB_reg[15]_i_1_n_10\,
      O(4) => \colsumXYB_reg[15]_i_1_n_11\,
      O(3) => \colsumXYB_reg[15]_i_1_n_12\,
      O(2) => \colsumXYB_reg[15]_i_1_n_13\,
      O(1) => \colsumXYB_reg[15]_i_1_n_14\,
      O(0) => \colsumXYB_reg[15]_i_1_n_15\,
      S(7) => \colsumXYB[15]_i_10_n_0\,
      S(6) => \colsumXYB[15]_i_11_n_0\,
      S(5) => \colsumXYB[15]_i_12_n_0\,
      S(4) => \colsumXYB[15]_i_13_n_0\,
      S(3) => \colsumXYB[15]_i_14_n_0\,
      S(2) => \colsumXYB[15]_i_15_n_0\,
      S(1) => \colsumXYB[15]_i_16_n_0\,
      S(0) => \colsumXYB[15]_i_17_n_0\
    );
\colsumXYB_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[19]_i_1_n_15\,
      Q => colsumXYB(16)
    );
\colsumXYB_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[19]_i_1_n_14\,
      Q => colsumXYB(17)
    );
\colsumXYB_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[19]_i_1_n_13\,
      Q => colsumXYB(18)
    );
\colsumXYB_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[19]_i_1_n_12\,
      Q => colsumXYB(19)
    );
\colsumXYB_reg[19]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXYB_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_colsumXYB_reg[19]_i_1_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \colsumXYB_reg[19]_i_1_n_5\,
      CO(1) => \colsumXYB_reg[19]_i_1_n_6\,
      CO(0) => \colsumXYB_reg[19]_i_1_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \colsumXYB[19]_i_2_n_0\,
      DI(1) => \colsumXYB[19]_i_3_n_0\,
      DI(0) => \colsumXYB[19]_i_4_n_0\,
      O(7 downto 4) => \NLW_colsumXYB_reg[19]_i_1_O_UNCONNECTED\(7 downto 4),
      O(3) => \colsumXYB_reg[19]_i_1_n_12\,
      O(2) => \colsumXYB_reg[19]_i_1_n_13\,
      O(1) => \colsumXYB_reg[19]_i_1_n_14\,
      O(0) => \colsumXYB_reg[19]_i_1_n_15\,
      S(7 downto 4) => B"0000",
      S(3) => \colsumXYB[19]_i_5_n_0\,
      S(2) => \colsumXYB[19]_i_6_n_0\,
      S(1) => \colsumXYB[19]_i_7_n_0\,
      S(0) => \colsumXYB[19]_i_8_n_0\
    );
\colsumXYB_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[7]_i_1_n_14\,
      Q => colsumXYB(1)
    );
\colsumXYB_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[7]_i_1_n_13\,
      Q => colsumXYB(2)
    );
\colsumXYB_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[7]_i_1_n_12\,
      Q => colsumXYB(3)
    );
\colsumXYB_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[7]_i_1_n_11\,
      Q => colsumXYB(4)
    );
\colsumXYB_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[7]_i_1_n_10\,
      Q => colsumXYB(5)
    );
\colsumXYB_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[7]_i_1_n_9\,
      Q => colsumXYB(6)
    );
\colsumXYB_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[7]_i_1_n_8\,
      Q => colsumXYB(7)
    );
\colsumXYB_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \colsumXYB_reg[7]_i_1_n_0\,
      CO(6) => \colsumXYB_reg[7]_i_1_n_1\,
      CO(5) => \colsumXYB_reg[7]_i_1_n_2\,
      CO(4) => \colsumXYB_reg[7]_i_1_n_3\,
      CO(3) => \colsumXYB_reg[7]_i_1_n_4\,
      CO(2) => \colsumXYB_reg[7]_i_1_n_5\,
      CO(1) => \colsumXYB_reg[7]_i_1_n_6\,
      CO(0) => \colsumXYB_reg[7]_i_1_n_7\,
      DI(7) => \colsumXYB[7]_i_2_n_0\,
      DI(6) => \colsumXYB[7]_i_3_n_0\,
      DI(5) => \colsumXYB[7]_i_4_n_0\,
      DI(4) => \colsumXYB[7]_i_5_n_0\,
      DI(3) => \colsumXYB[7]_i_6_n_0\,
      DI(2) => \colsumXYB[7]_i_7_n_0\,
      DI(1) => \colsumXYB[7]_i_8_n_0\,
      DI(0) => \colsumXYB[7]_i_9_n_0\,
      O(7) => \colsumXYB_reg[7]_i_1_n_8\,
      O(6) => \colsumXYB_reg[7]_i_1_n_9\,
      O(5) => \colsumXYB_reg[7]_i_1_n_10\,
      O(4) => \colsumXYB_reg[7]_i_1_n_11\,
      O(3) => \colsumXYB_reg[7]_i_1_n_12\,
      O(2) => \colsumXYB_reg[7]_i_1_n_13\,
      O(1) => \colsumXYB_reg[7]_i_1_n_14\,
      O(0) => \colsumXYB_reg[7]_i_1_n_15\,
      S(7) => \colsumXYB[7]_i_10_n_0\,
      S(6) => \colsumXYB[7]_i_11_n_0\,
      S(5) => \colsumXYB[7]_i_12_n_0\,
      S(4) => \colsumXYB[7]_i_13_n_0\,
      S(3) => \colsumXYB[7]_i_14_n_0\,
      S(2) => \colsumXYB[7]_i_15_n_0\,
      S(1) => \colsumXYB[7]_i_16_n_0\,
      S(0) => \colsumXYB[7]_i_17_n_0\
    );
\colsumXYB_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[15]_i_1_n_15\,
      Q => colsumXYB(8)
    );
\colsumXYB_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYB_reg[15]_i_1_n_14\,
      Q => colsumXYB(9)
    );
\colsumXYC[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(15),
      I1 => colsumXYB(15),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_10_n_0\
    );
\colsumXYC[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(14),
      I1 => colsumXYB(14),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_11_n_0\
    );
\colsumXYC[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(13),
      I1 => colsumXYB(13),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_12_n_0\
    );
\colsumXYC[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(12),
      I1 => colsumXYB(12),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_13_n_0\
    );
\colsumXYC[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(11),
      I1 => colsumXYB(11),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_14_n_0\
    );
\colsumXYC[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(10),
      I1 => colsumXYB(10),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_15_n_0\
    );
\colsumXYC[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(9),
      I1 => colsumXYB(9),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_16_n_0\
    );
\colsumXYC[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(8),
      I1 => colsumXYB(8),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_17_n_0\
    );
\colsumXYC[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(15),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_2_n_0\
    );
\colsumXYC[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(14),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_3_n_0\
    );
\colsumXYC[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(13),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_4_n_0\
    );
\colsumXYC[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(12),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_5_n_0\
    );
\colsumXYC[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(11),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_6_n_0\
    );
\colsumXYC[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(10),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_7_n_0\
    );
\colsumXYC[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(9),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_8_n_0\
    );
\colsumXYC[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(8),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[15]_i_9_n_0\
    );
\colsumXYC[20]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(16),
      I1 => colsumXYB(16),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYC[20]_i_10_n_0\
    );
\colsumXYC[20]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(17),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYC[20]_i_2_n_0\
    );
\colsumXYC[20]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(17),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYC[20]_i_3_n_0\
    );
\colsumXYC[20]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(17),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYC[20]_i_4_n_0\
    );
\colsumXYC[20]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(16),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYC[20]_i_5_n_0\
    );
\colsumXYC[20]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(17),
      I1 => colsumXYB(19),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYC[20]_i_6_n_0\
    );
\colsumXYC[20]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(17),
      I1 => colsumXYB(19),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYC[20]_i_7_n_0\
    );
\colsumXYC[20]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(17),
      I1 => colsumXYB(18),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYC[20]_i_8_n_0\
    );
\colsumXYC[20]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(17),
      I1 => colsumXYB(17),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXYC[20]_i_9_n_0\
    );
\colsumXYC[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(7),
      I1 => colsumXYB(7),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_10_n_0\
    );
\colsumXYC[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(6),
      I1 => colsumXYB(6),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_11_n_0\
    );
\colsumXYC[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(5),
      I1 => colsumXYB(5),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_12_n_0\
    );
\colsumXYC[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(4),
      I1 => colsumXYB(4),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_13_n_0\
    );
\colsumXYC[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(3),
      I1 => colsumXYB(3),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_14_n_0\
    );
\colsumXYC[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(2),
      I1 => colsumXYB(2),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_15_n_0\
    );
\colsumXYC[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(1),
      I1 => colsumXYB(1),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_16_n_0\
    );
\colsumXYC[7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => xy4p2(0),
      I1 => colsumXYB(0),
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_17_n_0\
    );
\colsumXYC[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(7),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_2_n_0\
    );
\colsumXYC[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(6),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_3_n_0\
    );
\colsumXYC[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(5),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_4_n_0\
    );
\colsumXYC[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(4),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_5_n_0\
    );
\colsumXYC[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(3),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_6_n_0\
    );
\colsumXYC[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(2),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_7_n_0\
    );
\colsumXYC[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(1),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_8_n_0\
    );
\colsumXYC[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => xy4p2(0),
      I1 => \stateScore_reg_rep__2_n_0\,
      O => \colsumXYC[7]_i_9_n_0\
    );
\colsumXYC_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[7]_i_1_n_15\,
      Q => colsumXYC(0)
    );
\colsumXYC_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[15]_i_1_n_13\,
      Q => colsumXYC(10)
    );
\colsumXYC_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[15]_i_1_n_12\,
      Q => colsumXYC(11)
    );
\colsumXYC_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[15]_i_1_n_11\,
      Q => colsumXYC(12)
    );
\colsumXYC_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[15]_i_1_n_10\,
      Q => colsumXYC(13)
    );
\colsumXYC_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[15]_i_1_n_9\,
      Q => colsumXYC(14)
    );
\colsumXYC_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[15]_i_1_n_8\,
      Q => colsumXYC(15)
    );
\colsumXYC_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXYC_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \colsumXYC_reg[15]_i_1_n_0\,
      CO(6) => \colsumXYC_reg[15]_i_1_n_1\,
      CO(5) => \colsumXYC_reg[15]_i_1_n_2\,
      CO(4) => \colsumXYC_reg[15]_i_1_n_3\,
      CO(3) => \colsumXYC_reg[15]_i_1_n_4\,
      CO(2) => \colsumXYC_reg[15]_i_1_n_5\,
      CO(1) => \colsumXYC_reg[15]_i_1_n_6\,
      CO(0) => \colsumXYC_reg[15]_i_1_n_7\,
      DI(7) => \colsumXYC[15]_i_2_n_0\,
      DI(6) => \colsumXYC[15]_i_3_n_0\,
      DI(5) => \colsumXYC[15]_i_4_n_0\,
      DI(4) => \colsumXYC[15]_i_5_n_0\,
      DI(3) => \colsumXYC[15]_i_6_n_0\,
      DI(2) => \colsumXYC[15]_i_7_n_0\,
      DI(1) => \colsumXYC[15]_i_8_n_0\,
      DI(0) => \colsumXYC[15]_i_9_n_0\,
      O(7) => \colsumXYC_reg[15]_i_1_n_8\,
      O(6) => \colsumXYC_reg[15]_i_1_n_9\,
      O(5) => \colsumXYC_reg[15]_i_1_n_10\,
      O(4) => \colsumXYC_reg[15]_i_1_n_11\,
      O(3) => \colsumXYC_reg[15]_i_1_n_12\,
      O(2) => \colsumXYC_reg[15]_i_1_n_13\,
      O(1) => \colsumXYC_reg[15]_i_1_n_14\,
      O(0) => \colsumXYC_reg[15]_i_1_n_15\,
      S(7) => \colsumXYC[15]_i_10_n_0\,
      S(6) => \colsumXYC[15]_i_11_n_0\,
      S(5) => \colsumXYC[15]_i_12_n_0\,
      S(4) => \colsumXYC[15]_i_13_n_0\,
      S(3) => \colsumXYC[15]_i_14_n_0\,
      S(2) => \colsumXYC[15]_i_15_n_0\,
      S(1) => \colsumXYC[15]_i_16_n_0\,
      S(0) => \colsumXYC[15]_i_17_n_0\
    );
\colsumXYC_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[20]_i_1_n_15\,
      Q => colsumXYC(16)
    );
\colsumXYC_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[20]_i_1_n_14\,
      Q => colsumXYC(17)
    );
\colsumXYC_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[20]_i_1_n_13\,
      Q => colsumXYC(18)
    );
\colsumXYC_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[20]_i_1_n_12\,
      Q => colsumXYC(19)
    );
\colsumXYC_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[7]_i_1_n_14\,
      Q => colsumXYC(1)
    );
\colsumXYC_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[20]_i_1_n_11\,
      Q => colsumXYC(20)
    );
\colsumXYC_reg[20]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumXYC_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_colsumXYC_reg[20]_i_1_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \colsumXYC_reg[20]_i_1_n_4\,
      CO(2) => \colsumXYC_reg[20]_i_1_n_5\,
      CO(1) => \colsumXYC_reg[20]_i_1_n_6\,
      CO(0) => \colsumXYC_reg[20]_i_1_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3) => \colsumXYC[20]_i_2_n_0\,
      DI(2) => \colsumXYC[20]_i_3_n_0\,
      DI(1) => \colsumXYC[20]_i_4_n_0\,
      DI(0) => \colsumXYC[20]_i_5_n_0\,
      O(7 downto 5) => \NLW_colsumXYC_reg[20]_i_1_O_UNCONNECTED\(7 downto 5),
      O(4) => \colsumXYC_reg[20]_i_1_n_11\,
      O(3) => \colsumXYC_reg[20]_i_1_n_12\,
      O(2) => \colsumXYC_reg[20]_i_1_n_13\,
      O(1) => \colsumXYC_reg[20]_i_1_n_14\,
      O(0) => \colsumXYC_reg[20]_i_1_n_15\,
      S(7 downto 5) => B"000",
      S(4) => \colsumXYC[20]_i_6_n_0\,
      S(3) => \colsumXYC[20]_i_7_n_0\,
      S(2) => \colsumXYC[20]_i_8_n_0\,
      S(1) => \colsumXYC[20]_i_9_n_0\,
      S(0) => \colsumXYC[20]_i_10_n_0\
    );
\colsumXYC_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[7]_i_1_n_13\,
      Q => colsumXYC(2)
    );
\colsumXYC_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[7]_i_1_n_12\,
      Q => colsumXYC(3)
    );
\colsumXYC_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[7]_i_1_n_11\,
      Q => colsumXYC(4)
    );
\colsumXYC_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[7]_i_1_n_10\,
      Q => colsumXYC(5)
    );
\colsumXYC_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[7]_i_1_n_9\,
      Q => colsumXYC(6)
    );
\colsumXYC_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[7]_i_1_n_8\,
      Q => colsumXYC(7)
    );
\colsumXYC_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \colsumXYC_reg[7]_i_1_n_0\,
      CO(6) => \colsumXYC_reg[7]_i_1_n_1\,
      CO(5) => \colsumXYC_reg[7]_i_1_n_2\,
      CO(4) => \colsumXYC_reg[7]_i_1_n_3\,
      CO(3) => \colsumXYC_reg[7]_i_1_n_4\,
      CO(2) => \colsumXYC_reg[7]_i_1_n_5\,
      CO(1) => \colsumXYC_reg[7]_i_1_n_6\,
      CO(0) => \colsumXYC_reg[7]_i_1_n_7\,
      DI(7) => \colsumXYC[7]_i_2_n_0\,
      DI(6) => \colsumXYC[7]_i_3_n_0\,
      DI(5) => \colsumXYC[7]_i_4_n_0\,
      DI(4) => \colsumXYC[7]_i_5_n_0\,
      DI(3) => \colsumXYC[7]_i_6_n_0\,
      DI(2) => \colsumXYC[7]_i_7_n_0\,
      DI(1) => \colsumXYC[7]_i_8_n_0\,
      DI(0) => \colsumXYC[7]_i_9_n_0\,
      O(7) => \colsumXYC_reg[7]_i_1_n_8\,
      O(6) => \colsumXYC_reg[7]_i_1_n_9\,
      O(5) => \colsumXYC_reg[7]_i_1_n_10\,
      O(4) => \colsumXYC_reg[7]_i_1_n_11\,
      O(3) => \colsumXYC_reg[7]_i_1_n_12\,
      O(2) => \colsumXYC_reg[7]_i_1_n_13\,
      O(1) => \colsumXYC_reg[7]_i_1_n_14\,
      O(0) => \colsumXYC_reg[7]_i_1_n_15\,
      S(7) => \colsumXYC[7]_i_10_n_0\,
      S(6) => \colsumXYC[7]_i_11_n_0\,
      S(5) => \colsumXYC[7]_i_12_n_0\,
      S(4) => \colsumXYC[7]_i_13_n_0\,
      S(3) => \colsumXYC[7]_i_14_n_0\,
      S(2) => \colsumXYC[7]_i_15_n_0\,
      S(1) => \colsumXYC[7]_i_16_n_0\,
      S(0) => \colsumXYC[7]_i_17_n_0\
    );
\colsumXYC_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[15]_i_1_n_15\,
      Q => colsumXYC(8)
    );
\colsumXYC_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXYC_reg[15]_i_1_n_14\,
      Q => colsumXYC(9)
    );
\colsumXY[100]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(16),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[100]_i_1_n_0\
    );
\colsumXY[101]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(17),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[101]_i_1_n_0\
    );
\colsumXY[102]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(18),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[102]_i_1_n_0\
    );
\colsumXY[103]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(19),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[103]_i_1_n_0\
    );
\colsumXY[104]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(20),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[104]_i_1_n_0\
    );
\colsumXY[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(0),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[21]_i_1_n_0\
    );
\colsumXY[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(1),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[22]_i_1_n_0\
    );
\colsumXY[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(2),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[23]_i_1_n_0\
    );
\colsumXY[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(3),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[24]_i_1_n_0\
    );
\colsumXY[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(4),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[25]_i_1_n_0\
    );
\colsumXY[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(5),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[26]_i_1_n_0\
    );
\colsumXY[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(6),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[27]_i_1_n_0\
    );
\colsumXY[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(7),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[28]_i_1_n_0\
    );
\colsumXY[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(8),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[29]_i_1_n_0\
    );
\colsumXY[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(9),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[30]_i_1_n_0\
    );
\colsumXY[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(10),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[31]_i_1_n_0\
    );
\colsumXY[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(11),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[32]_i_1_n_0\
    );
\colsumXY[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(12),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[33]_i_1_n_0\
    );
\colsumXY[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(13),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[34]_i_1_n_0\
    );
\colsumXY[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(14),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXY[35]_i_1_n_0\
    );
\colsumXY[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(15),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXY[36]_i_1_n_0\
    );
\colsumXY[37]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(16),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXY[37]_i_1_n_0\
    );
\colsumXY[38]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(17),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXY[38]_i_1_n_0\
    );
\colsumXY[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(18),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXY[39]_i_1_n_0\
    );
\colsumXY[40]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(19),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumXY[40]_i_1_n_0\
    );
\colsumXY[41]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(20),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[41]_i_1_n_0\
    );
\colsumXY[84]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(0),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[84]_i_1_n_0\
    );
\colsumXY[85]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(1),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[85]_i_1_n_0\
    );
\colsumXY[86]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(2),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[86]_i_1_n_0\
    );
\colsumXY[87]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(3),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[87]_i_1_n_0\
    );
\colsumXY[88]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(4),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[88]_i_1_n_0\
    );
\colsumXY[89]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(5),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[89]_i_1_n_0\
    );
\colsumXY[90]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(6),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[90]_i_1_n_0\
    );
\colsumXY[91]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(7),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[91]_i_1_n_0\
    );
\colsumXY[92]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(8),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[92]_i_1_n_0\
    );
\colsumXY[93]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(9),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[93]_i_1_n_0\
    );
\colsumXY[94]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(10),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[94]_i_1_n_0\
    );
\colsumXY[95]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(11),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[95]_i_1_n_0\
    );
\colsumXY[96]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(12),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[96]_i_1_n_0\
    );
\colsumXY[97]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(13),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[97]_i_1_n_0\
    );
\colsumXY[98]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(14),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[98]_i_1_n_0\
    );
\colsumXY[99]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumXYC(15),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumXY[99]_i_1_n_0\
    );
\colsumXY_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[84]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[0]\
    );
\colsumXY_reg[100]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[100]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[100]\
    );
\colsumXY_reg[101]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[101]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[101]\
    );
\colsumXY_reg[102]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[102]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[102]\
    );
\colsumXY_reg[103]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[103]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[103]\
    );
\colsumXY_reg[104]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[104]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[104]\
    );
\colsumXY_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[94]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[10]\
    );
\colsumXY_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[95]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[11]\
    );
\colsumXY_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[96]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[12]\
    );
\colsumXY_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[97]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[13]\
    );
\colsumXY_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[98]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[14]\
    );
\colsumXY_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[99]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[15]\
    );
\colsumXY_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[100]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[16]\
    );
\colsumXY_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[101]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[17]\
    );
\colsumXY_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[102]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[18]\
    );
\colsumXY_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[103]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[19]\
    );
\colsumXY_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[85]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[1]\
    );
\colsumXY_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[104]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[20]\
    );
\colsumXY_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[21]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[21]\
    );
\colsumXY_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[22]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[22]\
    );
\colsumXY_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[23]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[23]\
    );
\colsumXY_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[24]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[24]\
    );
\colsumXY_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[25]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[25]\
    );
\colsumXY_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[26]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[26]\
    );
\colsumXY_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[27]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[27]\
    );
\colsumXY_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[28]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[28]\
    );
\colsumXY_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[29]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[29]\
    );
\colsumXY_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[86]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[2]\
    );
\colsumXY_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[30]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[30]\
    );
\colsumXY_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[31]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[31]\
    );
\colsumXY_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[32]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[32]\
    );
\colsumXY_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[33]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[33]\
    );
\colsumXY_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[34]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[34]\
    );
\colsumXY_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[35]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[35]\
    );
\colsumXY_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[36]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[36]\
    );
\colsumXY_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[37]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[37]\
    );
\colsumXY_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[38]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[38]\
    );
\colsumXY_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[39]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[39]\
    );
\colsumXY_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[87]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[3]\
    );
\colsumXY_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[40]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[40]\
    );
\colsumXY_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[41]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[41]\
    );
\colsumXY_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[84]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[42]\
    );
\colsumXY_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[85]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[43]\
    );
\colsumXY_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[86]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[44]\
    );
\colsumXY_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[87]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[45]\
    );
\colsumXY_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[88]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[46]\
    );
\colsumXY_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[89]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[47]\
    );
\colsumXY_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[90]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[48]\
    );
\colsumXY_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[91]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[49]\
    );
\colsumXY_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[88]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[4]\
    );
\colsumXY_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[92]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[50]\
    );
\colsumXY_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[93]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[51]\
    );
\colsumXY_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[94]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[52]\
    );
\colsumXY_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[95]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[53]\
    );
\colsumXY_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[96]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[54]\
    );
\colsumXY_reg[55]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[97]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[55]\
    );
\colsumXY_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[98]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[56]\
    );
\colsumXY_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[99]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[57]\
    );
\colsumXY_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[100]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[58]\
    );
\colsumXY_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[101]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[59]\
    );
\colsumXY_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[89]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[5]\
    );
\colsumXY_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[102]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[60]\
    );
\colsumXY_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[103]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[61]\
    );
\colsumXY_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[104]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[62]\
    );
\colsumXY_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[84]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[63]\
    );
\colsumXY_reg[64]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[85]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[64]\
    );
\colsumXY_reg[65]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[86]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[65]\
    );
\colsumXY_reg[66]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[87]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[66]\
    );
\colsumXY_reg[67]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[88]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[67]\
    );
\colsumXY_reg[68]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[89]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[68]\
    );
\colsumXY_reg[69]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[90]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[69]\
    );
\colsumXY_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[90]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[6]\
    );
\colsumXY_reg[70]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[91]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[70]\
    );
\colsumXY_reg[71]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[92]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[71]\
    );
\colsumXY_reg[72]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[93]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[72]\
    );
\colsumXY_reg[73]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[94]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[73]\
    );
\colsumXY_reg[74]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[95]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[74]\
    );
\colsumXY_reg[75]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[96]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[75]\
    );
\colsumXY_reg[76]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[97]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[76]\
    );
\colsumXY_reg[77]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[98]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[77]\
    );
\colsumXY_reg[78]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[99]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[78]\
    );
\colsumXY_reg[79]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[100]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[79]\
    );
\colsumXY_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[91]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[7]\
    );
\colsumXY_reg[80]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[101]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[80]\
    );
\colsumXY_reg[81]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[102]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[81]\
    );
\colsumXY_reg[82]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[103]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[82]\
    );
\colsumXY_reg[83]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[104]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[83]\
    );
\colsumXY_reg[84]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[84]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[84]\
    );
\colsumXY_reg[85]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[85]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[85]\
    );
\colsumXY_reg[86]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[86]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[86]\
    );
\colsumXY_reg[87]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[87]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[87]\
    );
\colsumXY_reg[88]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[88]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[88]\
    );
\colsumXY_reg[89]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[89]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[89]\
    );
\colsumXY_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[92]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[8]\
    );
\colsumXY_reg[90]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[90]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[90]\
    );
\colsumXY_reg[91]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[91]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[91]\
    );
\colsumXY_reg[92]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[92]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[92]\
    );
\colsumXY_reg[93]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[93]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[93]\
    );
\colsumXY_reg[94]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[94]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[94]\
    );
\colsumXY_reg[95]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[95]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[95]\
    );
\colsumXY_reg[96]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[96]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[96]\
    );
\colsumXY_reg[97]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[97]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[97]\
    );
\colsumXY_reg[98]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[98]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[98]\
    );
\colsumXY_reg[99]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[99]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[99]\
    );
\colsumXY_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumXY[93]_i_1_n_0\,
      Q => \colsumXY_reg_n_0_[9]\
    );
\colsumX[100]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(37),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[100]_i_1_n_0\
    );
\colsumX[101]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(38),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[101]_i_1_n_0\
    );
\colsumX[102]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(39),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[102]_i_1_n_0\
    );
\colsumX[103]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(40),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[103]_i_1_n_0\
    );
\colsumX[104]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0040FFFF"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => \abcde__0\(0),
      I2 => ceScore,
      I3 => \abcde__0\(1),
      I4 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[104]_i_1_n_0\
    );
\colsumX[104]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(41),
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \colsumX[104]_i_2_n_0\
    );
\colsumX[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0010FFFF"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => \abcde__0\(0),
      I2 => ceScore,
      I3 => \abcde__0\(1),
      I4 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[20]_i_1_n_0\
    );
\colsumX[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(21),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[21]_i_1_n_0\
    );
\colsumX[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(22),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[22]_i_1_n_0\
    );
\colsumX[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(23),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[23]_i_1_n_0\
    );
\colsumX[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(24),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[24]_i_1_n_0\
    );
\colsumX[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(25),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[25]_i_1_n_0\
    );
\colsumX[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(26),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[26]_i_1_n_0\
    );
\colsumX[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(27),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[27]_i_1_n_0\
    );
\colsumX[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(28),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[28]_i_1_n_0\
    );
\colsumX[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(29),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[29]_i_1_n_0\
    );
\colsumX[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(30),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[30]_i_1_n_0\
    );
\colsumX[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(31),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[31]_i_1_n_0\
    );
\colsumX[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(32),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[32]_i_1_n_0\
    );
\colsumX[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(33),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[33]_i_1_n_0\
    );
\colsumX[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(34),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[34]_i_1_n_0\
    );
\colsumX[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(35),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumX[35]_i_1_n_0\
    );
\colsumX[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(36),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumX[36]_i_1_n_0\
    );
\colsumX[37]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(37),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumX[37]_i_1_n_0\
    );
\colsumX[38]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(38),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumX[38]_i_1_n_0\
    );
\colsumX[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(39),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumX[39]_i_1_n_0\
    );
\colsumX[40]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(40),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumX[40]_i_1_n_0\
    );
\colsumX[41]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0200FFFF"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => \abcde__0\(1),
      I2 => \abcde__0\(0),
      I3 => ceScore,
      I4 => \stateScore_reg_rep__17_n_0\,
      O => \colsumX[41]_i_1_n_0\
    );
\colsumX[41]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(41),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[41]_i_2_n_0\
    );
\colsumX[62]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0800FFFF"
    )
        port map (
      I0 => ceScore,
      I1 => \abcde__0\(1),
      I2 => \abcde__0\(2),
      I3 => \abcde__0\(0),
      I4 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[62]_i_1_n_0\
    );
\colsumX[83]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0008FFFF"
    )
        port map (
      I0 => ceScore,
      I1 => \abcde__0\(1),
      I2 => \abcde__0\(2),
      I3 => \abcde__0\(0),
      I4 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[83]_i_1_n_0\
    );
\colsumX[84]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(21),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[84]_i_1_n_0\
    );
\colsumX[85]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(22),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[85]_i_1_n_0\
    );
\colsumX[86]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(23),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[86]_i_1_n_0\
    );
\colsumX[87]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(24),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[87]_i_1_n_0\
    );
\colsumX[88]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(25),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[88]_i_1_n_0\
    );
\colsumX[89]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(26),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[89]_i_1_n_0\
    );
\colsumX[90]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(27),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[90]_i_1_n_0\
    );
\colsumX[91]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(28),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[91]_i_1_n_0\
    );
\colsumX[92]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(29),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[92]_i_1_n_0\
    );
\colsumX[93]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(30),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[93]_i_1_n_0\
    );
\colsumX[94]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(31),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[94]_i_1_n_0\
    );
\colsumX[95]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(32),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[95]_i_1_n_0\
    );
\colsumX[96]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(33),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[96]_i_1_n_0\
    );
\colsumX[97]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(34),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[97]_i_1_n_0\
    );
\colsumX[98]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(35),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[98]_i_1_n_0\
    );
\colsumX[99]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumX(36),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumX[99]_i_1_n_0\
    );
\colsumX_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[84]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[0]\
    );
\colsumX_reg[100]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[100]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[100]\
    );
\colsumX_reg[101]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[101]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[101]\
    );
\colsumX_reg[102]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[102]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[102]\
    );
\colsumX_reg[103]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[103]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[103]\
    );
\colsumX_reg[104]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[104]_i_2_n_0\,
      Q => \colsumX_reg_n_0_[104]\
    );
\colsumX_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[94]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[10]\
    );
\colsumX_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[95]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[11]\
    );
\colsumX_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[96]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[12]\
    );
\colsumX_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[97]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[13]\
    );
\colsumX_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[98]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[14]\
    );
\colsumX_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[99]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[15]\
    );
\colsumX_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[100]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[16]\
    );
\colsumX_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[101]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[17]\
    );
\colsumX_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[102]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[18]\
    );
\colsumX_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[103]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[19]\
    );
\colsumX_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[85]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[1]\
    );
\colsumX_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[104]_i_2_n_0\,
      Q => \colsumX_reg_n_0_[20]\
    );
\colsumX_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[21]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[21]\
    );
\colsumX_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[22]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[22]\
    );
\colsumX_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[23]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[23]\
    );
\colsumX_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[24]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[24]\
    );
\colsumX_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[25]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[25]\
    );
\colsumX_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[26]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[26]\
    );
\colsumX_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[27]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[27]\
    );
\colsumX_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[28]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[28]\
    );
\colsumX_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[29]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[29]\
    );
\colsumX_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[86]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[2]\
    );
\colsumX_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[30]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[30]\
    );
\colsumX_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[31]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[31]\
    );
\colsumX_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[32]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[32]\
    );
\colsumX_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[33]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[33]\
    );
\colsumX_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[34]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[34]\
    );
\colsumX_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[35]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[35]\
    );
\colsumX_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[36]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[36]\
    );
\colsumX_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[37]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[37]\
    );
\colsumX_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[38]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[38]\
    );
\colsumX_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[39]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[39]\
    );
\colsumX_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[87]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[3]\
    );
\colsumX_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[40]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[40]\
    );
\colsumX_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[41]_i_2_n_0\,
      Q => \colsumX_reg_n_0_[41]\
    );
\colsumX_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[84]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[42]\
    );
\colsumX_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[85]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[43]\
    );
\colsumX_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[86]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[44]\
    );
\colsumX_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[87]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[45]\
    );
\colsumX_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[88]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[46]\
    );
\colsumX_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[89]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[47]\
    );
\colsumX_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[90]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[48]\
    );
\colsumX_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[91]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[49]\
    );
\colsumX_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[88]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[4]\
    );
\colsumX_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[92]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[50]\
    );
\colsumX_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[93]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[51]\
    );
\colsumX_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[94]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[52]\
    );
\colsumX_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[95]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[53]\
    );
\colsumX_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[96]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[54]\
    );
\colsumX_reg[55]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[97]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[55]\
    );
\colsumX_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[98]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[56]\
    );
\colsumX_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[99]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[57]\
    );
\colsumX_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[100]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[58]\
    );
\colsumX_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[101]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[59]\
    );
\colsumX_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[89]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[5]\
    );
\colsumX_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[102]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[60]\
    );
\colsumX_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[103]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[61]\
    );
\colsumX_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[104]_i_2_n_0\,
      Q => \colsumX_reg_n_0_[62]\
    );
\colsumX_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[84]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[63]\
    );
\colsumX_reg[64]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[85]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[64]\
    );
\colsumX_reg[65]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[86]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[65]\
    );
\colsumX_reg[66]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[87]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[66]\
    );
\colsumX_reg[67]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[88]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[67]\
    );
\colsumX_reg[68]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[89]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[68]\
    );
\colsumX_reg[69]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[90]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[69]\
    );
\colsumX_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[90]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[6]\
    );
\colsumX_reg[70]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[91]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[70]\
    );
\colsumX_reg[71]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[92]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[71]\
    );
\colsumX_reg[72]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[93]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[72]\
    );
\colsumX_reg[73]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[94]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[73]\
    );
\colsumX_reg[74]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[95]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[74]\
    );
\colsumX_reg[75]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[96]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[75]\
    );
\colsumX_reg[76]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[97]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[76]\
    );
\colsumX_reg[77]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[98]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[77]\
    );
\colsumX_reg[78]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[99]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[78]\
    );
\colsumX_reg[79]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[100]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[79]\
    );
\colsumX_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[91]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[7]\
    );
\colsumX_reg[80]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[101]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[80]\
    );
\colsumX_reg[81]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[102]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[81]\
    );
\colsumX_reg[82]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[103]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[82]\
    );
\colsumX_reg[83]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[104]_i_2_n_0\,
      Q => \colsumX_reg_n_0_[83]\
    );
\colsumX_reg[84]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[84]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[84]\
    );
\colsumX_reg[85]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[85]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[85]\
    );
\colsumX_reg[86]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[86]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[86]\
    );
\colsumX_reg[87]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[87]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[87]\
    );
\colsumX_reg[88]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[88]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[88]\
    );
\colsumX_reg[89]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[89]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[89]\
    );
\colsumX_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[92]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[8]\
    );
\colsumX_reg[90]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[90]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[90]\
    );
\colsumX_reg[91]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[91]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[91]\
    );
\colsumX_reg[92]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[92]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[92]\
    );
\colsumX_reg[93]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[93]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[93]\
    );
\colsumX_reg[94]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[94]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[94]\
    );
\colsumX_reg[95]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[95]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[95]\
    );
\colsumX_reg[96]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[96]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[96]\
    );
\colsumX_reg[97]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[97]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[97]\
    );
\colsumX_reg[98]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[98]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[98]\
    );
\colsumX_reg[99]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[99]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[99]\
    );
\colsumX_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumX[93]_i_1_n_0\,
      Q => \colsumX_reg_n_0_[9]\
    );
\colsumY4p1[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[84]\,
      O => \colsumY4p1[0]_i_1_n_0\
    );
\colsumY4p1[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[94]\,
      O => \colsumY4p1[10]_i_1_n_0\
    );
\colsumY4p1[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[95]\,
      O => \colsumY4p1[11]_i_1_n_0\
    );
\colsumY4p1[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[96]\,
      O => \colsumY4p1[12]_i_1_n_0\
    );
\colsumY4p1[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[97]\,
      O => \colsumY4p1[13]_i_1_n_0\
    );
\colsumY4p1[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[98]\,
      O => \colsumY4p1[14]_i_1_n_0\
    );
\colsumY4p1[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[99]\,
      O => \colsumY4p1[15]_i_1_n_0\
    );
\colsumY4p1[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => \colsumY_reg_n_0_[100]\,
      O => \colsumY4p1[16]_i_1_n_0\
    );
\colsumY4p1[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => \colsumY_reg_n_0_[101]\,
      O => \colsumY4p1[17]_i_1_n_0\
    );
\colsumY4p1[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => \colsumY_reg_n_0_[102]\,
      O => \colsumY4p1[18]_i_1_n_0\
    );
\colsumY4p1[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => \colsumY_reg_n_0_[103]\,
      O => \colsumY4p1[19]_i_1_n_0\
    );
\colsumY4p1[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[85]\,
      O => \colsumY4p1[1]_i_1_n_0\
    );
\colsumY4p1[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => \colsumY_reg_n_0_[104]\,
      O => \colsumY4p1[20]_i_1_n_0\
    );
\colsumY4p1[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[86]\,
      O => \colsumY4p1[2]_i_1_n_0\
    );
\colsumY4p1[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[87]\,
      O => \colsumY4p1[3]_i_1_n_0\
    );
\colsumY4p1[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[88]\,
      O => \colsumY4p1[4]_i_1_n_0\
    );
\colsumY4p1[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[89]\,
      O => \colsumY4p1[5]_i_1_n_0\
    );
\colsumY4p1[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[90]\,
      O => \colsumY4p1[6]_i_1_n_0\
    );
\colsumY4p1[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[91]\,
      O => \colsumY4p1[7]_i_1_n_0\
    );
\colsumY4p1[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[92]\,
      O => \colsumY4p1[8]_i_1_n_0\
    );
\colsumY4p1[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => \colsumY_reg_n_0_[93]\,
      O => \colsumY4p1[9]_i_1_n_0\
    );
\colsumY4p1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[0]_i_1_n_0\,
      Q => colsumY4p1(0)
    );
\colsumY4p1_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[10]_i_1_n_0\,
      Q => colsumY4p1(10)
    );
\colsumY4p1_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[11]_i_1_n_0\,
      Q => colsumY4p1(11)
    );
\colsumY4p1_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[12]_i_1_n_0\,
      Q => colsumY4p1(12)
    );
\colsumY4p1_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[13]_i_1_n_0\,
      Q => colsumY4p1(13)
    );
\colsumY4p1_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[14]_i_1_n_0\,
      Q => colsumY4p1(14)
    );
\colsumY4p1_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[15]_i_1_n_0\,
      Q => colsumY4p1(15)
    );
\colsumY4p1_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[16]_i_1_n_0\,
      Q => colsumY4p1(16)
    );
\colsumY4p1_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[17]_i_1_n_0\,
      Q => colsumY4p1(17)
    );
\colsumY4p1_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[18]_i_1_n_0\,
      Q => colsumY4p1(18)
    );
\colsumY4p1_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[19]_i_1_n_0\,
      Q => colsumY4p1(19)
    );
\colsumY4p1_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[1]_i_1_n_0\,
      Q => colsumY4p1(1)
    );
\colsumY4p1_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[20]_i_1_n_0\,
      Q => colsumY4p1(20)
    );
\colsumY4p1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[2]_i_1_n_0\,
      Q => colsumY4p1(2)
    );
\colsumY4p1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[3]_i_1_n_0\,
      Q => colsumY4p1(3)
    );
\colsumY4p1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[4]_i_1_n_0\,
      Q => colsumY4p1(4)
    );
\colsumY4p1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[5]_i_1_n_0\,
      Q => colsumY4p1(5)
    );
\colsumY4p1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[6]_i_1_n_0\,
      Q => colsumY4p1(6)
    );
\colsumY4p1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[7]_i_1_n_0\,
      Q => colsumY4p1(7)
    );
\colsumY4p1_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[8]_i_1_n_0\,
      Q => colsumY4p1(8)
    );
\colsumY4p1_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p1[9]_i_1_n_0\,
      Q => colsumY4p1(9)
    );
\colsumY4p2[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(0),
      O => \colsumY4p2[0]_i_1_n_0\
    );
\colsumY4p2[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(10),
      O => \colsumY4p2[10]_i_1_n_0\
    );
\colsumY4p2[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(11),
      O => \colsumY4p2[11]_i_1_n_0\
    );
\colsumY4p2[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(12),
      O => \colsumY4p2[12]_i_1_n_0\
    );
\colsumY4p2[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(13),
      O => \colsumY4p2[13]_i_1_n_0\
    );
\colsumY4p2[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(14),
      O => \colsumY4p2[14]_i_1_n_0\
    );
\colsumY4p2[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(15),
      O => \colsumY4p2[15]_i_1_n_0\
    );
\colsumY4p2[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => colsumY4p1(16),
      O => \colsumY4p2[16]_i_1_n_0\
    );
\colsumY4p2[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => colsumY4p1(17),
      O => \colsumY4p2[17]_i_1_n_0\
    );
\colsumY4p2[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => colsumY4p1(18),
      O => \colsumY4p2[18]_i_1_n_0\
    );
\colsumY4p2[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => colsumY4p1(19),
      O => \colsumY4p2[19]_i_1_n_0\
    );
\colsumY4p2[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(1),
      O => \colsumY4p2[1]_i_1_n_0\
    );
\colsumY4p2[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => colsumY4p1(20),
      O => \colsumY4p2[20]_i_1_n_0\
    );
\colsumY4p2[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(2),
      O => \colsumY4p2[2]_i_1_n_0\
    );
\colsumY4p2[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(3),
      O => \colsumY4p2[3]_i_1_n_0\
    );
\colsumY4p2[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(4),
      O => \colsumY4p2[4]_i_1_n_0\
    );
\colsumY4p2[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(5),
      O => \colsumY4p2[5]_i_1_n_0\
    );
\colsumY4p2[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(6),
      O => \colsumY4p2[6]_i_1_n_0\
    );
\colsumY4p2[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(7),
      O => \colsumY4p2[7]_i_1_n_0\
    );
\colsumY4p2[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(8),
      O => \colsumY4p2[8]_i_1_n_0\
    );
\colsumY4p2[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__5_n_0\,
      I1 => colsumY4p1(9),
      O => \colsumY4p2[9]_i_1_n_0\
    );
\colsumY4p2_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[0]_i_1_n_0\,
      Q => colsumY4p2(0)
    );
\colsumY4p2_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[10]_i_1_n_0\,
      Q => colsumY4p2(10)
    );
\colsumY4p2_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[11]_i_1_n_0\,
      Q => colsumY4p2(11)
    );
\colsumY4p2_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[12]_i_1_n_0\,
      Q => colsumY4p2(12)
    );
\colsumY4p2_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[13]_i_1_n_0\,
      Q => colsumY4p2(13)
    );
\colsumY4p2_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[14]_i_1_n_0\,
      Q => colsumY4p2(14)
    );
\colsumY4p2_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[15]_i_1_n_0\,
      Q => colsumY4p2(15)
    );
\colsumY4p2_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[16]_i_1_n_0\,
      Q => colsumY4p2(16)
    );
\colsumY4p2_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[17]_i_1_n_0\,
      Q => colsumY4p2(17)
    );
\colsumY4p2_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[18]_i_1_n_0\,
      Q => colsumY4p2(18)
    );
\colsumY4p2_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[19]_i_1_n_0\,
      Q => colsumY4p2(19)
    );
\colsumY4p2_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[1]_i_1_n_0\,
      Q => colsumY4p2(1)
    );
\colsumY4p2_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[20]_i_1_n_0\,
      Q => colsumY4p2(20)
    );
\colsumY4p2_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[2]_i_1_n_0\,
      Q => colsumY4p2(2)
    );
\colsumY4p2_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[3]_i_1_n_0\,
      Q => colsumY4p2(3)
    );
\colsumY4p2_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[4]_i_1_n_0\,
      Q => colsumY4p2(4)
    );
\colsumY4p2_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[5]_i_1_n_0\,
      Q => colsumY4p2(5)
    );
\colsumY4p2_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[6]_i_1_n_0\,
      Q => colsumY4p2(6)
    );
\colsumY4p2_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[7]_i_1_n_0\,
      Q => colsumY4p2(7)
    );
\colsumY4p2_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[8]_i_1_n_0\,
      Q => colsumY4p2(8)
    );
\colsumY4p2_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY4p2[9]_i_1_n_0\,
      Q => colsumY4p2(9)
    );
\colsumYA[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr(0),
      I2 => ysqr(18),
      O => \colsumYA[0]_i_1_n_0\
    );
\colsumYA[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA0(10),
      O => \colsumYA[10]_i_1_n_0\
    );
\colsumYA[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA0(11),
      O => \colsumYA[11]_i_1_n_0\
    );
\colsumYA[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA0(12),
      O => \colsumYA[12]_i_1_n_0\
    );
\colsumYA[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA0(13),
      O => \colsumYA[13]_i_1_n_0\
    );
\colsumYA[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA0(14),
      O => \colsumYA[14]_i_1_n_0\
    );
\colsumYA[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA0(15),
      O => \colsumYA[15]_i_1_n_0\
    );
\colsumYA[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => colsumYA0(16),
      O => \colsumYA[16]_i_1_n_0\
    );
\colsumYA[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => colsumYA0(17),
      O => \colsumYA[17]_i_1_n_0\
    );
\colsumYA[17]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(29),
      I1 => ysqr(11),
      O => \colsumYA[17]_i_10_n_0\
    );
\colsumYA[17]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(28),
      I1 => ysqr(10),
      O => \colsumYA[17]_i_11_n_0\
    );
\colsumYA[17]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ysqr(35),
      O => \colsumYA[17]_i_3_n_0\
    );
\colsumYA[17]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(35),
      I1 => ysqr(17),
      O => \colsumYA[17]_i_4_n_0\
    );
\colsumYA[17]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(34),
      I1 => ysqr(16),
      O => \colsumYA[17]_i_5_n_0\
    );
\colsumYA[17]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(33),
      I1 => ysqr(15),
      O => \colsumYA[17]_i_6_n_0\
    );
\colsumYA[17]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(32),
      I1 => ysqr(14),
      O => \colsumYA[17]_i_7_n_0\
    );
\colsumYA[17]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(31),
      I1 => ysqr(13),
      O => \colsumYA[17]_i_8_n_0\
    );
\colsumYA[17]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(30),
      I1 => ysqr(12),
      O => \colsumYA[17]_i_9_n_0\
    );
\colsumYA[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => \colsumYA_reg[18]_i_2_n_7\,
      O => \colsumYA[18]_i_1_n_0\
    );
\colsumYA[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr(36),
      I2 => ysqr(54),
      O => \colsumYA[19]_i_1_n_0\
    );
\colsumYA[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr(18),
      I2 => ysqr(0),
      O => \colsumYA[1]_i_1_n_0\
    );
\colsumYA[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr(54),
      I2 => ysqr(36),
      O => \colsumYA[20]_i_1_n_0\
    );
\colsumYA[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA00_in(2),
      O => \colsumYA[21]_i_1_n_0\
    );
\colsumYA[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA00_in(3),
      O => \colsumYA[22]_i_1_n_0\
    );
\colsumYA[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA00_in(4),
      O => \colsumYA[23]_i_1_n_0\
    );
\colsumYA[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA00_in(5),
      O => \colsumYA[24]_i_1_n_0\
    );
\colsumYA[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA00_in(6),
      O => \colsumYA[25]_i_1_n_0\
    );
\colsumYA[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA00_in(7),
      O => \colsumYA[26]_i_1_n_0\
    );
\colsumYA[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA00_in(8),
      O => \colsumYA[27]_i_1_n_0\
    );
\colsumYA[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA00_in(9),
      O => \colsumYA[28]_i_1_n_0\
    );
\colsumYA[28]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(56),
      I1 => ysqr(38),
      O => \colsumYA[28]_i_10_n_0\
    );
\colsumYA[28]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(63),
      I1 => ysqr(45),
      O => \colsumYA[28]_i_3_n_0\
    );
\colsumYA[28]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(62),
      I1 => ysqr(44),
      O => \colsumYA[28]_i_4_n_0\
    );
\colsumYA[28]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(61),
      I1 => ysqr(43),
      O => \colsumYA[28]_i_5_n_0\
    );
\colsumYA[28]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(60),
      I1 => ysqr(42),
      O => \colsumYA[28]_i_6_n_0\
    );
\colsumYA[28]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(59),
      I1 => ysqr(41),
      O => \colsumYA[28]_i_7_n_0\
    );
\colsumYA[28]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(58),
      I1 => ysqr(40),
      O => \colsumYA[28]_i_8_n_0\
    );
\colsumYA[28]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(57),
      I1 => ysqr(39),
      O => \colsumYA[28]_i_9_n_0\
    );
\colsumYA[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA00_in(10),
      O => \colsumYA[29]_i_1_n_0\
    );
\colsumYA[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA0(2),
      O => \colsumYA[2]_i_1_n_0\
    );
\colsumYA[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA00_in(11),
      O => \colsumYA[30]_i_1_n_0\
    );
\colsumYA[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA00_in(12),
      O => \colsumYA[31]_i_1_n_0\
    );
\colsumYA[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA00_in(13),
      O => \colsumYA[32]_i_1_n_0\
    );
\colsumYA[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA00_in(14),
      O => \colsumYA[33]_i_1_n_0\
    );
\colsumYA[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA00_in(15),
      O => \colsumYA[34]_i_1_n_0\
    );
\colsumYA[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => colsumYA00_in(16),
      O => \colsumYA[35]_i_1_n_0\
    );
\colsumYA[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => colsumYA00_in(17),
      O => \colsumYA[36]_i_1_n_0\
    );
\colsumYA[36]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(65),
      I1 => ysqr(47),
      O => \colsumYA[36]_i_10_n_0\
    );
\colsumYA[36]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(64),
      I1 => ysqr(46),
      O => \colsumYA[36]_i_11_n_0\
    );
\colsumYA[36]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ysqr(71),
      O => \colsumYA[36]_i_3_n_0\
    );
\colsumYA[36]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(71),
      I1 => ysqr(53),
      O => \colsumYA[36]_i_4_n_0\
    );
\colsumYA[36]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(70),
      I1 => ysqr(52),
      O => \colsumYA[36]_i_5_n_0\
    );
\colsumYA[36]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(69),
      I1 => ysqr(51),
      O => \colsumYA[36]_i_6_n_0\
    );
\colsumYA[36]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(68),
      I1 => ysqr(50),
      O => \colsumYA[36]_i_7_n_0\
    );
\colsumYA[36]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(67),
      I1 => ysqr(49),
      O => \colsumYA[36]_i_8_n_0\
    );
\colsumYA[36]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(66),
      I1 => ysqr(48),
      O => \colsumYA[36]_i_9_n_0\
    );
\colsumYA[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => \colsumYA_reg[37]_i_2_n_7\,
      O => \colsumYA[37]_i_1_n_0\
    );
\colsumYA[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA0(3),
      O => \colsumYA[3]_i_1_n_0\
    );
\colsumYA[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA0(4),
      O => \colsumYA[4]_i_1_n_0\
    );
\colsumYA[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA0(5),
      O => \colsumYA[5]_i_1_n_0\
    );
\colsumYA[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA0(6),
      O => \colsumYA[6]_i_1_n_0\
    );
\colsumYA[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA0(7),
      O => \colsumYA[7]_i_1_n_0\
    );
\colsumYA[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA0(8),
      O => \colsumYA[8]_i_1_n_0\
    );
\colsumYA[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => colsumYA0(9),
      O => \colsumYA[9]_i_1_n_0\
    );
\colsumYA[9]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(20),
      I1 => ysqr(2),
      O => \colsumYA[9]_i_10_n_0\
    );
\colsumYA[9]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(27),
      I1 => ysqr(9),
      O => \colsumYA[9]_i_3_n_0\
    );
\colsumYA[9]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(26),
      I1 => ysqr(8),
      O => \colsumYA[9]_i_4_n_0\
    );
\colsumYA[9]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(25),
      I1 => ysqr(7),
      O => \colsumYA[9]_i_5_n_0\
    );
\colsumYA[9]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(24),
      I1 => ysqr(6),
      O => \colsumYA[9]_i_6_n_0\
    );
\colsumYA[9]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(23),
      I1 => ysqr(5),
      O => \colsumYA[9]_i_7_n_0\
    );
\colsumYA[9]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(22),
      I1 => ysqr(4),
      O => \colsumYA[9]_i_8_n_0\
    );
\colsumYA[9]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ysqr(21),
      I1 => ysqr(3),
      O => \colsumYA[9]_i_9_n_0\
    );
\colsumYA_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[0]_i_1_n_0\,
      Q => colsumYA(0)
    );
\colsumYA_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[10]_i_1_n_0\,
      Q => colsumYA(10)
    );
\colsumYA_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[11]_i_1_n_0\,
      Q => colsumYA(11)
    );
\colsumYA_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[12]_i_1_n_0\,
      Q => colsumYA(12)
    );
\colsumYA_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[13]_i_1_n_0\,
      Q => colsumYA(13)
    );
\colsumYA_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[14]_i_1_n_0\,
      Q => colsumYA(14)
    );
\colsumYA_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[15]_i_1_n_0\,
      Q => colsumYA(15)
    );
\colsumYA_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[16]_i_1_n_0\,
      Q => colsumYA(16)
    );
\colsumYA_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[17]_i_1_n_0\,
      Q => colsumYA(17)
    );
\colsumYA_reg[17]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumYA_reg[9]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \colsumYA_reg[17]_i_2_n_0\,
      CO(6) => \colsumYA_reg[17]_i_2_n_1\,
      CO(5) => \colsumYA_reg[17]_i_2_n_2\,
      CO(4) => \colsumYA_reg[17]_i_2_n_3\,
      CO(3) => \colsumYA_reg[17]_i_2_n_4\,
      CO(2) => \colsumYA_reg[17]_i_2_n_5\,
      CO(1) => \colsumYA_reg[17]_i_2_n_6\,
      CO(0) => \colsumYA_reg[17]_i_2_n_7\,
      DI(7) => \colsumYA[17]_i_3_n_0\,
      DI(6 downto 0) => ysqr(34 downto 28),
      O(7 downto 0) => colsumYA0(17 downto 10),
      S(7) => \colsumYA[17]_i_4_n_0\,
      S(6) => \colsumYA[17]_i_5_n_0\,
      S(5) => \colsumYA[17]_i_6_n_0\,
      S(4) => \colsumYA[17]_i_7_n_0\,
      S(3) => \colsumYA[17]_i_8_n_0\,
      S(2) => \colsumYA[17]_i_9_n_0\,
      S(1) => \colsumYA[17]_i_10_n_0\,
      S(0) => \colsumYA[17]_i_11_n_0\
    );
\colsumYA_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[18]_i_1_n_0\,
      Q => colsumYA(18)
    );
\colsumYA_reg[18]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumYA_reg[17]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 1) => \NLW_colsumYA_reg[18]_i_2_CO_UNCONNECTED\(7 downto 1),
      CO(0) => \colsumYA_reg[18]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_colsumYA_reg[18]_i_2_O_UNCONNECTED\(7 downto 0),
      S(7 downto 0) => B"00000001"
    );
\colsumYA_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[19]_i_1_n_0\,
      Q => colsumYA(19)
    );
\colsumYA_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[1]_i_1_n_0\,
      Q => colsumYA(1)
    );
\colsumYA_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[20]_i_1_n_0\,
      Q => colsumYA(20)
    );
\colsumYA_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[21]_i_1_n_0\,
      Q => colsumYA(21)
    );
\colsumYA_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[22]_i_1_n_0\,
      Q => colsumYA(22)
    );
\colsumYA_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[23]_i_1_n_0\,
      Q => colsumYA(23)
    );
\colsumYA_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[24]_i_1_n_0\,
      Q => colsumYA(24)
    );
\colsumYA_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[25]_i_1_n_0\,
      Q => colsumYA(25)
    );
\colsumYA_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[26]_i_1_n_0\,
      Q => colsumYA(26)
    );
\colsumYA_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[27]_i_1_n_0\,
      Q => colsumYA(27)
    );
\colsumYA_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[28]_i_1_n_0\,
      Q => colsumYA(28)
    );
\colsumYA_reg[28]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \colsumYA_reg[28]_i_2_n_0\,
      CO(6) => \colsumYA_reg[28]_i_2_n_1\,
      CO(5) => \colsumYA_reg[28]_i_2_n_2\,
      CO(4) => \colsumYA_reg[28]_i_2_n_3\,
      CO(3) => \colsumYA_reg[28]_i_2_n_4\,
      CO(2) => \colsumYA_reg[28]_i_2_n_5\,
      CO(1) => \colsumYA_reg[28]_i_2_n_6\,
      CO(0) => \colsumYA_reg[28]_i_2_n_7\,
      DI(7 downto 0) => ysqr(63 downto 56),
      O(7 downto 0) => colsumYA00_in(9 downto 2),
      S(7) => \colsumYA[28]_i_3_n_0\,
      S(6) => \colsumYA[28]_i_4_n_0\,
      S(5) => \colsumYA[28]_i_5_n_0\,
      S(4) => \colsumYA[28]_i_6_n_0\,
      S(3) => \colsumYA[28]_i_7_n_0\,
      S(2) => \colsumYA[28]_i_8_n_0\,
      S(1) => \colsumYA[28]_i_9_n_0\,
      S(0) => \colsumYA[28]_i_10_n_0\
    );
\colsumYA_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[29]_i_1_n_0\,
      Q => colsumYA(29)
    );
\colsumYA_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[2]_i_1_n_0\,
      Q => colsumYA(2)
    );
\colsumYA_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[30]_i_1_n_0\,
      Q => colsumYA(30)
    );
\colsumYA_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[31]_i_1_n_0\,
      Q => colsumYA(31)
    );
\colsumYA_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[32]_i_1_n_0\,
      Q => colsumYA(32)
    );
\colsumYA_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[33]_i_1_n_0\,
      Q => colsumYA(33)
    );
\colsumYA_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[34]_i_1_n_0\,
      Q => colsumYA(34)
    );
\colsumYA_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[35]_i_1_n_0\,
      Q => colsumYA(35)
    );
\colsumYA_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[36]_i_1_n_0\,
      Q => colsumYA(36)
    );
\colsumYA_reg[36]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumYA_reg[28]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \colsumYA_reg[36]_i_2_n_0\,
      CO(6) => \colsumYA_reg[36]_i_2_n_1\,
      CO(5) => \colsumYA_reg[36]_i_2_n_2\,
      CO(4) => \colsumYA_reg[36]_i_2_n_3\,
      CO(3) => \colsumYA_reg[36]_i_2_n_4\,
      CO(2) => \colsumYA_reg[36]_i_2_n_5\,
      CO(1) => \colsumYA_reg[36]_i_2_n_6\,
      CO(0) => \colsumYA_reg[36]_i_2_n_7\,
      DI(7) => \colsumYA[36]_i_3_n_0\,
      DI(6 downto 0) => ysqr(70 downto 64),
      O(7 downto 0) => colsumYA00_in(17 downto 10),
      S(7) => \colsumYA[36]_i_4_n_0\,
      S(6) => \colsumYA[36]_i_5_n_0\,
      S(5) => \colsumYA[36]_i_6_n_0\,
      S(4) => \colsumYA[36]_i_7_n_0\,
      S(3) => \colsumYA[36]_i_8_n_0\,
      S(2) => \colsumYA[36]_i_9_n_0\,
      S(1) => \colsumYA[36]_i_10_n_0\,
      S(0) => \colsumYA[36]_i_11_n_0\
    );
\colsumYA_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[37]_i_1_n_0\,
      Q => colsumYA(37)
    );
\colsumYA_reg[37]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumYA_reg[36]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 1) => \NLW_colsumYA_reg[37]_i_2_CO_UNCONNECTED\(7 downto 1),
      CO(0) => \colsumYA_reg[37]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \NLW_colsumYA_reg[37]_i_2_O_UNCONNECTED\(7 downto 0),
      S(7 downto 0) => B"00000001"
    );
\colsumYA_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[3]_i_1_n_0\,
      Q => colsumYA(3)
    );
\colsumYA_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[4]_i_1_n_0\,
      Q => colsumYA(4)
    );
\colsumYA_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[5]_i_1_n_0\,
      Q => colsumYA(5)
    );
\colsumYA_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[6]_i_1_n_0\,
      Q => colsumYA(6)
    );
\colsumYA_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[7]_i_1_n_0\,
      Q => colsumYA(7)
    );
\colsumYA_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[8]_i_1_n_0\,
      Q => colsumYA(8)
    );
\colsumYA_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYA[9]_i_1_n_0\,
      Q => colsumYA(9)
    );
\colsumYA_reg[9]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \colsumYA_reg[9]_i_2_n_0\,
      CO(6) => \colsumYA_reg[9]_i_2_n_1\,
      CO(5) => \colsumYA_reg[9]_i_2_n_2\,
      CO(4) => \colsumYA_reg[9]_i_2_n_3\,
      CO(3) => \colsumYA_reg[9]_i_2_n_4\,
      CO(2) => \colsumYA_reg[9]_i_2_n_5\,
      CO(1) => \colsumYA_reg[9]_i_2_n_6\,
      CO(0) => \colsumYA_reg[9]_i_2_n_7\,
      DI(7 downto 0) => ysqr(27 downto 20),
      O(7 downto 0) => colsumYA0(9 downto 2),
      S(7) => \colsumYA[9]_i_3_n_0\,
      S(6) => \colsumYA[9]_i_4_n_0\,
      S(5) => \colsumYA[9]_i_5_n_0\,
      S(4) => \colsumYA[9]_i_6_n_0\,
      S(3) => \colsumYA[9]_i_7_n_0\,
      S(2) => \colsumYA[9]_i_8_n_0\,
      S(1) => \colsumYA[9]_i_9_n_0\,
      S(0) => \colsumYA[9]_i_10_n_0\
    );
\colsumYB[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(15),
      I1 => colsumYA(34),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_10_n_0\
    );
\colsumYB[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(14),
      I1 => colsumYA(33),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_11_n_0\
    );
\colsumYB[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(13),
      I1 => colsumYA(32),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_12_n_0\
    );
\colsumYB[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(12),
      I1 => colsumYA(31),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_13_n_0\
    );
\colsumYB[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(11),
      I1 => colsumYA(30),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_14_n_0\
    );
\colsumYB[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(10),
      I1 => colsumYA(29),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_15_n_0\
    );
\colsumYB[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(9),
      I1 => colsumYA(28),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_16_n_0\
    );
\colsumYB[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(8),
      I1 => colsumYA(27),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_17_n_0\
    );
\colsumYB[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(15),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_2_n_0\
    );
\colsumYB[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(14),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_3_n_0\
    );
\colsumYB[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(13),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_4_n_0\
    );
\colsumYB[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(12),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_5_n_0\
    );
\colsumYB[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(11),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_6_n_0\
    );
\colsumYB[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(10),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_7_n_0\
    );
\colsumYB[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(9),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_8_n_0\
    );
\colsumYB[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(8),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[15]_i_9_n_0\
    );
\colsumYB[19]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(18),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYB[19]_i_2_n_0\
    );
\colsumYB[19]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(17),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYB[19]_i_3_n_0\
    );
\colsumYB[19]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(16),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYB[19]_i_4_n_0\
    );
\colsumYB[19]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(18),
      I1 => colsumYA(37),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYB[19]_i_5_n_0\
    );
\colsumYB[19]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(18),
      I1 => colsumYA(37),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYB[19]_i_6_n_0\
    );
\colsumYB[19]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(17),
      I1 => colsumYA(36),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYB[19]_i_7_n_0\
    );
\colsumYB[19]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(16),
      I1 => colsumYA(35),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYB[19]_i_8_n_0\
    );
\colsumYB[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(7),
      I1 => colsumYA(26),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_10_n_0\
    );
\colsumYB[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(6),
      I1 => colsumYA(25),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_11_n_0\
    );
\colsumYB[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(5),
      I1 => colsumYA(24),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_12_n_0\
    );
\colsumYB[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(4),
      I1 => colsumYA(23),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_13_n_0\
    );
\colsumYB[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(3),
      I1 => colsumYA(22),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_14_n_0\
    );
\colsumYB[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(2),
      I1 => colsumYA(21),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_15_n_0\
    );
\colsumYB[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(1),
      I1 => colsumYA(20),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_16_n_0\
    );
\colsumYB[7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumYA(0),
      I1 => colsumYA(19),
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_17_n_0\
    );
\colsumYB[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(7),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_2_n_0\
    );
\colsumYB[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(6),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_3_n_0\
    );
\colsumYB[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(5),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_4_n_0\
    );
\colsumYB[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(4),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_5_n_0\
    );
\colsumYB[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(3),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_6_n_0\
    );
\colsumYB[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(2),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_7_n_0\
    );
\colsumYB[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(1),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_8_n_0\
    );
\colsumYB[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumYA(0),
      I1 => \stateScore_reg_rep__7_n_0\,
      O => \colsumYB[7]_i_9_n_0\
    );
\colsumYB_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[7]_i_1_n_15\,
      Q => colsumYB(0)
    );
\colsumYB_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[15]_i_1_n_13\,
      Q => colsumYB(10)
    );
\colsumYB_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[15]_i_1_n_12\,
      Q => colsumYB(11)
    );
\colsumYB_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[15]_i_1_n_11\,
      Q => colsumYB(12)
    );
\colsumYB_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[15]_i_1_n_10\,
      Q => colsumYB(13)
    );
\colsumYB_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[15]_i_1_n_9\,
      Q => colsumYB(14)
    );
\colsumYB_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[15]_i_1_n_8\,
      Q => colsumYB(15)
    );
\colsumYB_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumYB_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \colsumYB_reg[15]_i_1_n_0\,
      CO(6) => \colsumYB_reg[15]_i_1_n_1\,
      CO(5) => \colsumYB_reg[15]_i_1_n_2\,
      CO(4) => \colsumYB_reg[15]_i_1_n_3\,
      CO(3) => \colsumYB_reg[15]_i_1_n_4\,
      CO(2) => \colsumYB_reg[15]_i_1_n_5\,
      CO(1) => \colsumYB_reg[15]_i_1_n_6\,
      CO(0) => \colsumYB_reg[15]_i_1_n_7\,
      DI(7) => \colsumYB[15]_i_2_n_0\,
      DI(6) => \colsumYB[15]_i_3_n_0\,
      DI(5) => \colsumYB[15]_i_4_n_0\,
      DI(4) => \colsumYB[15]_i_5_n_0\,
      DI(3) => \colsumYB[15]_i_6_n_0\,
      DI(2) => \colsumYB[15]_i_7_n_0\,
      DI(1) => \colsumYB[15]_i_8_n_0\,
      DI(0) => \colsumYB[15]_i_9_n_0\,
      O(7) => \colsumYB_reg[15]_i_1_n_8\,
      O(6) => \colsumYB_reg[15]_i_1_n_9\,
      O(5) => \colsumYB_reg[15]_i_1_n_10\,
      O(4) => \colsumYB_reg[15]_i_1_n_11\,
      O(3) => \colsumYB_reg[15]_i_1_n_12\,
      O(2) => \colsumYB_reg[15]_i_1_n_13\,
      O(1) => \colsumYB_reg[15]_i_1_n_14\,
      O(0) => \colsumYB_reg[15]_i_1_n_15\,
      S(7) => \colsumYB[15]_i_10_n_0\,
      S(6) => \colsumYB[15]_i_11_n_0\,
      S(5) => \colsumYB[15]_i_12_n_0\,
      S(4) => \colsumYB[15]_i_13_n_0\,
      S(3) => \colsumYB[15]_i_14_n_0\,
      S(2) => \colsumYB[15]_i_15_n_0\,
      S(1) => \colsumYB[15]_i_16_n_0\,
      S(0) => \colsumYB[15]_i_17_n_0\
    );
\colsumYB_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[19]_i_1_n_15\,
      Q => colsumYB(16)
    );
\colsumYB_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[19]_i_1_n_14\,
      Q => colsumYB(17)
    );
\colsumYB_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[19]_i_1_n_13\,
      Q => colsumYB(18)
    );
\colsumYB_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[19]_i_1_n_12\,
      Q => colsumYB(19)
    );
\colsumYB_reg[19]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumYB_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_colsumYB_reg[19]_i_1_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \colsumYB_reg[19]_i_1_n_5\,
      CO(1) => \colsumYB_reg[19]_i_1_n_6\,
      CO(0) => \colsumYB_reg[19]_i_1_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \colsumYB[19]_i_2_n_0\,
      DI(1) => \colsumYB[19]_i_3_n_0\,
      DI(0) => \colsumYB[19]_i_4_n_0\,
      O(7 downto 4) => \NLW_colsumYB_reg[19]_i_1_O_UNCONNECTED\(7 downto 4),
      O(3) => \colsumYB_reg[19]_i_1_n_12\,
      O(2) => \colsumYB_reg[19]_i_1_n_13\,
      O(1) => \colsumYB_reg[19]_i_1_n_14\,
      O(0) => \colsumYB_reg[19]_i_1_n_15\,
      S(7 downto 4) => B"0000",
      S(3) => \colsumYB[19]_i_5_n_0\,
      S(2) => \colsumYB[19]_i_6_n_0\,
      S(1) => \colsumYB[19]_i_7_n_0\,
      S(0) => \colsumYB[19]_i_8_n_0\
    );
\colsumYB_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[7]_i_1_n_14\,
      Q => colsumYB(1)
    );
\colsumYB_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[7]_i_1_n_13\,
      Q => colsumYB(2)
    );
\colsumYB_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[7]_i_1_n_12\,
      Q => colsumYB(3)
    );
\colsumYB_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[7]_i_1_n_11\,
      Q => colsumYB(4)
    );
\colsumYB_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[7]_i_1_n_10\,
      Q => colsumYB(5)
    );
\colsumYB_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[7]_i_1_n_9\,
      Q => colsumYB(6)
    );
\colsumYB_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[7]_i_1_n_8\,
      Q => colsumYB(7)
    );
\colsumYB_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \colsumYB_reg[7]_i_1_n_0\,
      CO(6) => \colsumYB_reg[7]_i_1_n_1\,
      CO(5) => \colsumYB_reg[7]_i_1_n_2\,
      CO(4) => \colsumYB_reg[7]_i_1_n_3\,
      CO(3) => \colsumYB_reg[7]_i_1_n_4\,
      CO(2) => \colsumYB_reg[7]_i_1_n_5\,
      CO(1) => \colsumYB_reg[7]_i_1_n_6\,
      CO(0) => \colsumYB_reg[7]_i_1_n_7\,
      DI(7) => \colsumYB[7]_i_2_n_0\,
      DI(6) => \colsumYB[7]_i_3_n_0\,
      DI(5) => \colsumYB[7]_i_4_n_0\,
      DI(4) => \colsumYB[7]_i_5_n_0\,
      DI(3) => \colsumYB[7]_i_6_n_0\,
      DI(2) => \colsumYB[7]_i_7_n_0\,
      DI(1) => \colsumYB[7]_i_8_n_0\,
      DI(0) => \colsumYB[7]_i_9_n_0\,
      O(7) => \colsumYB_reg[7]_i_1_n_8\,
      O(6) => \colsumYB_reg[7]_i_1_n_9\,
      O(5) => \colsumYB_reg[7]_i_1_n_10\,
      O(4) => \colsumYB_reg[7]_i_1_n_11\,
      O(3) => \colsumYB_reg[7]_i_1_n_12\,
      O(2) => \colsumYB_reg[7]_i_1_n_13\,
      O(1) => \colsumYB_reg[7]_i_1_n_14\,
      O(0) => \colsumYB_reg[7]_i_1_n_15\,
      S(7) => \colsumYB[7]_i_10_n_0\,
      S(6) => \colsumYB[7]_i_11_n_0\,
      S(5) => \colsumYB[7]_i_12_n_0\,
      S(4) => \colsumYB[7]_i_13_n_0\,
      S(3) => \colsumYB[7]_i_14_n_0\,
      S(2) => \colsumYB[7]_i_15_n_0\,
      S(1) => \colsumYB[7]_i_16_n_0\,
      S(0) => \colsumYB[7]_i_17_n_0\
    );
\colsumYB_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[15]_i_1_n_15\,
      Q => colsumYB(8)
    );
\colsumYB_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYB_reg[15]_i_1_n_14\,
      Q => colsumYB(9)
    );
\colsumYC[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(15),
      I1 => colsumYB(15),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_10_n_0\
    );
\colsumYC[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(14),
      I1 => colsumYB(14),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_11_n_0\
    );
\colsumYC[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(13),
      I1 => colsumYB(13),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_12_n_0\
    );
\colsumYC[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(12),
      I1 => colsumYB(12),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_13_n_0\
    );
\colsumYC[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(11),
      I1 => colsumYB(11),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_14_n_0\
    );
\colsumYC[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(10),
      I1 => colsumYB(10),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_15_n_0\
    );
\colsumYC[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(9),
      I1 => colsumYB(9),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_16_n_0\
    );
\colsumYC[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(8),
      I1 => colsumYB(8),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_17_n_0\
    );
\colsumYC[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(15),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_2_n_0\
    );
\colsumYC[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(14),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_3_n_0\
    );
\colsumYC[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(13),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_4_n_0\
    );
\colsumYC[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(12),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_5_n_0\
    );
\colsumYC[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(11),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_6_n_0\
    );
\colsumYC[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(10),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_7_n_0\
    );
\colsumYC[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(9),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_8_n_0\
    );
\colsumYC[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(8),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[15]_i_9_n_0\
    );
\colsumYC[20]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(16),
      I1 => colsumYB(16),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYC[20]_i_10_n_0\
    );
\colsumYC[20]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(17),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYC[20]_i_2_n_0\
    );
\colsumYC[20]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(17),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYC[20]_i_3_n_0\
    );
\colsumYC[20]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(17),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYC[20]_i_4_n_0\
    );
\colsumYC[20]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(16),
      I1 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYC[20]_i_5_n_0\
    );
\colsumYC[20]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(17),
      I1 => colsumYB(19),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYC[20]_i_6_n_0\
    );
\colsumYC[20]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(17),
      I1 => colsumYB(19),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYC[20]_i_7_n_0\
    );
\colsumYC[20]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(17),
      I1 => colsumYB(18),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYC[20]_i_8_n_0\
    );
\colsumYC[20]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(17),
      I1 => colsumYB(17),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumYC[20]_i_9_n_0\
    );
\colsumYC[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(6),
      I1 => colsumYB(6),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[7]_i_10_n_0\
    );
\colsumYC[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(5),
      I1 => colsumYB(5),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[7]_i_11_n_0\
    );
\colsumYC[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(4),
      I1 => colsumYB(4),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[7]_i_12_n_0\
    );
\colsumYC[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(3),
      I1 => colsumYB(3),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[7]_i_13_n_0\
    );
\colsumYC[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(2),
      I1 => colsumYB(2),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[7]_i_14_n_0\
    );
\colsumYC[7]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => colsumYB(1),
      O => \colsumYC[7]_i_15_n_0\
    );
\colsumYC[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(0),
      I1 => colsumYB(0),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[7]_i_16_n_0\
    );
\colsumYC[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(7),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[7]_i_2_n_0\
    );
\colsumYC[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(6),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[7]_i_3_n_0\
    );
\colsumYC[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(5),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[7]_i_4_n_0\
    );
\colsumYC[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(4),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[7]_i_5_n_0\
    );
\colsumYC[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(3),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[7]_i_6_n_0\
    );
\colsumYC[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(2),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[7]_i_7_n_0\
    );
\colsumYC[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ysqr4p2(0),
      I1 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[7]_i_8_n_0\
    );
\colsumYC[7]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => ysqr4p2(7),
      I1 => colsumYB(7),
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \colsumYC[7]_i_9_n_0\
    );
\colsumYC_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[7]_i_1_n_15\,
      Q => colsumY(21)
    );
\colsumYC_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[15]_i_1_n_13\,
      Q => colsumY(31)
    );
\colsumYC_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[15]_i_1_n_12\,
      Q => colsumY(32)
    );
\colsumYC_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[15]_i_1_n_11\,
      Q => colsumY(33)
    );
\colsumYC_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[15]_i_1_n_10\,
      Q => colsumY(34)
    );
\colsumYC_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[15]_i_1_n_9\,
      Q => colsumY(35)
    );
\colsumYC_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[15]_i_1_n_8\,
      Q => colsumY(36)
    );
\colsumYC_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumYC_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \colsumYC_reg[15]_i_1_n_0\,
      CO(6) => \colsumYC_reg[15]_i_1_n_1\,
      CO(5) => \colsumYC_reg[15]_i_1_n_2\,
      CO(4) => \colsumYC_reg[15]_i_1_n_3\,
      CO(3) => \colsumYC_reg[15]_i_1_n_4\,
      CO(2) => \colsumYC_reg[15]_i_1_n_5\,
      CO(1) => \colsumYC_reg[15]_i_1_n_6\,
      CO(0) => \colsumYC_reg[15]_i_1_n_7\,
      DI(7) => \colsumYC[15]_i_2_n_0\,
      DI(6) => \colsumYC[15]_i_3_n_0\,
      DI(5) => \colsumYC[15]_i_4_n_0\,
      DI(4) => \colsumYC[15]_i_5_n_0\,
      DI(3) => \colsumYC[15]_i_6_n_0\,
      DI(2) => \colsumYC[15]_i_7_n_0\,
      DI(1) => \colsumYC[15]_i_8_n_0\,
      DI(0) => \colsumYC[15]_i_9_n_0\,
      O(7) => \colsumYC_reg[15]_i_1_n_8\,
      O(6) => \colsumYC_reg[15]_i_1_n_9\,
      O(5) => \colsumYC_reg[15]_i_1_n_10\,
      O(4) => \colsumYC_reg[15]_i_1_n_11\,
      O(3) => \colsumYC_reg[15]_i_1_n_12\,
      O(2) => \colsumYC_reg[15]_i_1_n_13\,
      O(1) => \colsumYC_reg[15]_i_1_n_14\,
      O(0) => \colsumYC_reg[15]_i_1_n_15\,
      S(7) => \colsumYC[15]_i_10_n_0\,
      S(6) => \colsumYC[15]_i_11_n_0\,
      S(5) => \colsumYC[15]_i_12_n_0\,
      S(4) => \colsumYC[15]_i_13_n_0\,
      S(3) => \colsumYC[15]_i_14_n_0\,
      S(2) => \colsumYC[15]_i_15_n_0\,
      S(1) => \colsumYC[15]_i_16_n_0\,
      S(0) => \colsumYC[15]_i_17_n_0\
    );
\colsumYC_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[20]_i_1_n_15\,
      Q => colsumY(37)
    );
\colsumYC_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[20]_i_1_n_14\,
      Q => colsumY(38)
    );
\colsumYC_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[20]_i_1_n_13\,
      Q => colsumY(39)
    );
\colsumYC_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[20]_i_1_n_12\,
      Q => colsumY(40)
    );
\colsumYC_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[7]_i_1_n_14\,
      Q => colsumY(22)
    );
\colsumYC_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[20]_i_1_n_11\,
      Q => colsumY(41)
    );
\colsumYC_reg[20]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \colsumYC_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_colsumYC_reg[20]_i_1_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \colsumYC_reg[20]_i_1_n_4\,
      CO(2) => \colsumYC_reg[20]_i_1_n_5\,
      CO(1) => \colsumYC_reg[20]_i_1_n_6\,
      CO(0) => \colsumYC_reg[20]_i_1_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3) => \colsumYC[20]_i_2_n_0\,
      DI(2) => \colsumYC[20]_i_3_n_0\,
      DI(1) => \colsumYC[20]_i_4_n_0\,
      DI(0) => \colsumYC[20]_i_5_n_0\,
      O(7 downto 5) => \NLW_colsumYC_reg[20]_i_1_O_UNCONNECTED\(7 downto 5),
      O(4) => \colsumYC_reg[20]_i_1_n_11\,
      O(3) => \colsumYC_reg[20]_i_1_n_12\,
      O(2) => \colsumYC_reg[20]_i_1_n_13\,
      O(1) => \colsumYC_reg[20]_i_1_n_14\,
      O(0) => \colsumYC_reg[20]_i_1_n_15\,
      S(7 downto 5) => B"000",
      S(4) => \colsumYC[20]_i_6_n_0\,
      S(3) => \colsumYC[20]_i_7_n_0\,
      S(2) => \colsumYC[20]_i_8_n_0\,
      S(1) => \colsumYC[20]_i_9_n_0\,
      S(0) => \colsumYC[20]_i_10_n_0\
    );
\colsumYC_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[7]_i_1_n_13\,
      Q => colsumY(23)
    );
\colsumYC_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[7]_i_1_n_12\,
      Q => colsumY(24)
    );
\colsumYC_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[7]_i_1_n_11\,
      Q => colsumY(25)
    );
\colsumYC_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[7]_i_1_n_10\,
      Q => colsumY(26)
    );
\colsumYC_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[7]_i_1_n_9\,
      Q => colsumY(27)
    );
\colsumYC_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[7]_i_1_n_8\,
      Q => colsumY(28)
    );
\colsumYC_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \colsumYC_reg[7]_i_1_n_0\,
      CO(6) => \colsumYC_reg[7]_i_1_n_1\,
      CO(5) => \colsumYC_reg[7]_i_1_n_2\,
      CO(4) => \colsumYC_reg[7]_i_1_n_3\,
      CO(3) => \colsumYC_reg[7]_i_1_n_4\,
      CO(2) => \colsumYC_reg[7]_i_1_n_5\,
      CO(1) => \colsumYC_reg[7]_i_1_n_6\,
      CO(0) => \colsumYC_reg[7]_i_1_n_7\,
      DI(7) => \colsumYC[7]_i_2_n_0\,
      DI(6) => \colsumYC[7]_i_3_n_0\,
      DI(5) => \colsumYC[7]_i_4_n_0\,
      DI(4) => \colsumYC[7]_i_5_n_0\,
      DI(3) => \colsumYC[7]_i_6_n_0\,
      DI(2) => \colsumYC[7]_i_7_n_0\,
      DI(1) => '0',
      DI(0) => \colsumYC[7]_i_8_n_0\,
      O(7) => \colsumYC_reg[7]_i_1_n_8\,
      O(6) => \colsumYC_reg[7]_i_1_n_9\,
      O(5) => \colsumYC_reg[7]_i_1_n_10\,
      O(4) => \colsumYC_reg[7]_i_1_n_11\,
      O(3) => \colsumYC_reg[7]_i_1_n_12\,
      O(2) => \colsumYC_reg[7]_i_1_n_13\,
      O(1) => \colsumYC_reg[7]_i_1_n_14\,
      O(0) => \colsumYC_reg[7]_i_1_n_15\,
      S(7) => \colsumYC[7]_i_9_n_0\,
      S(6) => \colsumYC[7]_i_10_n_0\,
      S(5) => \colsumYC[7]_i_11_n_0\,
      S(4) => \colsumYC[7]_i_12_n_0\,
      S(3) => \colsumYC[7]_i_13_n_0\,
      S(2) => \colsumYC[7]_i_14_n_0\,
      S(1) => \colsumYC[7]_i_15_n_0\,
      S(0) => \colsumYC[7]_i_16_n_0\
    );
\colsumYC_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[15]_i_1_n_15\,
      Q => colsumY(29)
    );
\colsumYC_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumYC_reg[15]_i_1_n_14\,
      Q => colsumY(30)
    );
\colsumY[100]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(37),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[100]_i_1_n_0\
    );
\colsumY[101]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(38),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[101]_i_1_n_0\
    );
\colsumY[102]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(39),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[102]_i_1_n_0\
    );
\colsumY[103]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(40),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[103]_i_1_n_0\
    );
\colsumY[104]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(41),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[104]_i_1_n_0\
    );
\colsumY[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(21),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[21]_i_1_n_0\
    );
\colsumY[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(22),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[22]_i_1_n_0\
    );
\colsumY[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(23),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[23]_i_1_n_0\
    );
\colsumY[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(24),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[24]_i_1_n_0\
    );
\colsumY[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(25),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[25]_i_1_n_0\
    );
\colsumY[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(26),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[26]_i_1_n_0\
    );
\colsumY[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(27),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[27]_i_1_n_0\
    );
\colsumY[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(28),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[28]_i_1_n_0\
    );
\colsumY[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(29),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[29]_i_1_n_0\
    );
\colsumY[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(30),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[30]_i_1_n_0\
    );
\colsumY[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(31),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[31]_i_1_n_0\
    );
\colsumY[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(32),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[32]_i_1_n_0\
    );
\colsumY[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(33),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[33]_i_1_n_0\
    );
\colsumY[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(34),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[34]_i_1_n_0\
    );
\colsumY[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(35),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumY[35]_i_1_n_0\
    );
\colsumY[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(36),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumY[36]_i_1_n_0\
    );
\colsumY[37]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(37),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumY[37]_i_1_n_0\
    );
\colsumY[38]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(38),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumY[38]_i_1_n_0\
    );
\colsumY[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(39),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumY[39]_i_1_n_0\
    );
\colsumY[40]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(40),
      I2 => \stateScore_reg_rep__17_n_0\,
      O => \colsumY[40]_i_1_n_0\
    );
\colsumY[41]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(41),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[41]_i_1_n_0\
    );
\colsumY[84]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(21),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[84]_i_1_n_0\
    );
\colsumY[85]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(22),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[85]_i_1_n_0\
    );
\colsumY[86]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(23),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[86]_i_1_n_0\
    );
\colsumY[87]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(24),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[87]_i_1_n_0\
    );
\colsumY[88]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(25),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[88]_i_1_n_0\
    );
\colsumY[89]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(26),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[89]_i_1_n_0\
    );
\colsumY[90]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(27),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[90]_i_1_n_0\
    );
\colsumY[91]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(28),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[91]_i_1_n_0\
    );
\colsumY[92]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(29),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[92]_i_1_n_0\
    );
\colsumY[93]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(30),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[93]_i_1_n_0\
    );
\colsumY[94]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(31),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[94]_i_1_n_0\
    );
\colsumY[95]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(32),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[95]_i_1_n_0\
    );
\colsumY[96]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(33),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[96]_i_1_n_0\
    );
\colsumY[97]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(34),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[97]_i_1_n_0\
    );
\colsumY[98]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(35),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[98]_i_1_n_0\
    );
\colsumY[99]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \abcde__0\(2),
      I1 => colsumY(36),
      I2 => \stateScore_reg_rep__18_n_0\,
      O => \colsumY[99]_i_1_n_0\
    );
\colsumY_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[84]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[0]\
    );
\colsumY_reg[100]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[100]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[100]\
    );
\colsumY_reg[101]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[101]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[101]\
    );
\colsumY_reg[102]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[102]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[102]\
    );
\colsumY_reg[103]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[103]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[103]\
    );
\colsumY_reg[104]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[104]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[104]\
    );
\colsumY_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[94]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[10]\
    );
\colsumY_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[95]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[11]\
    );
\colsumY_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[96]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[12]\
    );
\colsumY_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[97]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[13]\
    );
\colsumY_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[98]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[14]\
    );
\colsumY_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[99]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[15]\
    );
\colsumY_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[100]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[16]\
    );
\colsumY_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[101]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[17]\
    );
\colsumY_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[102]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[18]\
    );
\colsumY_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[103]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[19]\
    );
\colsumY_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[85]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[1]\
    );
\colsumY_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[104]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[20]\
    );
\colsumY_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[21]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[21]\
    );
\colsumY_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[22]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[22]\
    );
\colsumY_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[23]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[23]\
    );
\colsumY_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[24]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[24]\
    );
\colsumY_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[25]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[25]\
    );
\colsumY_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[26]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[26]\
    );
\colsumY_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[27]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[27]\
    );
\colsumY_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[28]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[28]\
    );
\colsumY_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[29]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[29]\
    );
\colsumY_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[86]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[2]\
    );
\colsumY_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[30]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[30]\
    );
\colsumY_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[31]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[31]\
    );
\colsumY_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[32]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[32]\
    );
\colsumY_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[33]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[33]\
    );
\colsumY_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[34]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[34]\
    );
\colsumY_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[35]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[35]\
    );
\colsumY_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[36]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[36]\
    );
\colsumY_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[37]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[37]\
    );
\colsumY_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[38]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[38]\
    );
\colsumY_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[39]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[39]\
    );
\colsumY_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[87]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[3]\
    );
\colsumY_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[40]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[40]\
    );
\colsumY_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[41]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[41]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[41]\
    );
\colsumY_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[84]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[42]\
    );
\colsumY_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[85]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[43]\
    );
\colsumY_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[86]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[44]\
    );
\colsumY_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[87]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[45]\
    );
\colsumY_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[88]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[46]\
    );
\colsumY_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[89]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[47]\
    );
\colsumY_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[90]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[48]\
    );
\colsumY_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[91]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[49]\
    );
\colsumY_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[88]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[4]\
    );
\colsumY_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[92]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[50]\
    );
\colsumY_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[93]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[51]\
    );
\colsumY_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[94]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[52]\
    );
\colsumY_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[95]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[53]\
    );
\colsumY_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[96]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[54]\
    );
\colsumY_reg[55]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[97]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[55]\
    );
\colsumY_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[98]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[56]\
    );
\colsumY_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[99]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[57]\
    );
\colsumY_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[100]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[58]\
    );
\colsumY_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[101]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[59]\
    );
\colsumY_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[89]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[5]\
    );
\colsumY_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[102]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[60]\
    );
\colsumY_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[103]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[61]\
    );
\colsumY_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[62]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[104]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[62]\
    );
\colsumY_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[84]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[63]\
    );
\colsumY_reg[64]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[85]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[64]\
    );
\colsumY_reg[65]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[86]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[65]\
    );
\colsumY_reg[66]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[87]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[66]\
    );
\colsumY_reg[67]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[88]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[67]\
    );
\colsumY_reg[68]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[89]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[68]\
    );
\colsumY_reg[69]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[90]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[69]\
    );
\colsumY_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[90]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[6]\
    );
\colsumY_reg[70]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[91]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[70]\
    );
\colsumY_reg[71]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[92]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[71]\
    );
\colsumY_reg[72]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[93]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[72]\
    );
\colsumY_reg[73]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[94]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[73]\
    );
\colsumY_reg[74]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[95]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[74]\
    );
\colsumY_reg[75]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[96]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[75]\
    );
\colsumY_reg[76]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[97]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[76]\
    );
\colsumY_reg[77]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[98]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[77]\
    );
\colsumY_reg[78]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[99]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[78]\
    );
\colsumY_reg[79]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[100]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[79]\
    );
\colsumY_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[91]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[7]\
    );
\colsumY_reg[80]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[101]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[80]\
    );
\colsumY_reg[81]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[102]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[81]\
    );
\colsumY_reg[82]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[103]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[82]\
    );
\colsumY_reg[83]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[83]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[104]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[83]\
    );
\colsumY_reg[84]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[84]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[84]\
    );
\colsumY_reg[85]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[85]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[85]\
    );
\colsumY_reg[86]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[86]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[86]\
    );
\colsumY_reg[87]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[87]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[87]\
    );
\colsumY_reg[88]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[88]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[88]\
    );
\colsumY_reg[89]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[89]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[89]\
    );
\colsumY_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[92]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[8]\
    );
\colsumY_reg[90]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[90]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[90]\
    );
\colsumY_reg[91]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[91]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[91]\
    );
\colsumY_reg[92]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[92]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[92]\
    );
\colsumY_reg[93]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[93]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[93]\
    );
\colsumY_reg[94]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[94]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[94]\
    );
\colsumY_reg[95]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[95]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[95]\
    );
\colsumY_reg[96]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[96]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[96]\
    );
\colsumY_reg[97]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[97]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[97]\
    );
\colsumY_reg[98]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[98]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[98]\
    );
\colsumY_reg[99]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[104]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[99]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[99]\
    );
\colsumY_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colsumX[20]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \colsumY[93]_i_1_n_0\,
      Q => \colsumY_reg_n_0_[9]\
    );
\dIgrm1[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(0),
      O => \dIgrm1[0]_i_1_n_0\
    );
\dIgrm1[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(10),
      O => \dIgrm1[10]_i_1_n_0\
    );
\dIgrm1[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(11),
      O => \dIgrm1[11]_i_1_n_0\
    );
\dIgrm1[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(12),
      O => \dIgrm1[12]_i_1_n_0\
    );
\dIgrm1[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(13),
      O => \dIgrm1[13]_i_1_n_0\
    );
\dIgrm1[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(14),
      O => \dIgrm1[14]_i_1_n_0\
    );
\dIgrm1[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(15),
      O => \dIgrm1[15]_i_1_n_0\
    );
\dIgrm1[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(16),
      O => \dIgrm1[16]_i_1_n_0\
    );
\dIgrm1[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(17),
      O => \dIgrm1[17]_i_1_n_0\
    );
\dIgrm1[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(18),
      O => \dIgrm1[18]_i_1_n_0\
    );
\dIgrm1[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(19),
      O => \dIgrm1[19]_i_1_n_0\
    );
\dIgrm1[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(1),
      O => \dIgrm1[1]_i_1_n_0\
    );
\dIgrm1[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(20),
      O => \dIgrm1[20]_i_1_n_0\
    );
\dIgrm1[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(21),
      O => \dIgrm1[21]_i_1_n_0\
    );
\dIgrm1[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(22),
      O => \dIgrm1[22]_i_1_n_0\
    );
\dIgrm1[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(23),
      O => \dIgrm1[23]_i_1_n_0\
    );
\dIgrm1[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(24),
      O => \dIgrm1[24]_i_1_n_0\
    );
\dIgrm1[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(25),
      O => \dIgrm1[25]_i_1_n_0\
    );
\dIgrm1[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(26),
      O => \dIgrm1[26]_i_1_n_0\
    );
\dIgrm1[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(27),
      O => \dIgrm1[27]_i_1_n_0\
    );
\dIgrm1[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(28),
      O => \dIgrm1[28]_i_1_n_0\
    );
\dIgrm1[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(29),
      O => \dIgrm1[29]_i_1_n_0\
    );
\dIgrm1[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(2),
      O => \dIgrm1[2]_i_1_n_0\
    );
\dIgrm1[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(30),
      O => \dIgrm1[30]_i_1_n_0\
    );
\dIgrm1[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(31),
      O => \dIgrm1[31]_i_1_n_0\
    );
\dIgrm1[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(32),
      O => \dIgrm1[32]_i_1_n_0\
    );
\dIgrm1[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(33),
      O => \dIgrm1[33]_i_1_n_0\
    );
\dIgrm1[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(34),
      O => \dIgrm1[34]_i_1_n_0\
    );
\dIgrm1[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(35),
      O => \dIgrm1[35]_i_1_n_0\
    );
\dIgrm1[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(36),
      O => \dIgrm1[36]_i_1_n_0\
    );
\dIgrm1[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(37),
      O => \dIgrm1[37]_i_1_n_0\
    );
\dIgrm1[38]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(38),
      O => \dIgrm1[38]_i_1_n_0\
    );
\dIgrm1[39]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0040FFFF"
    )
        port map (
      I0 => \tkst_reg[0]_0\,
      I1 => grayVideoinToManyAXIS_tvalid,
      I2 => stateCorner(0),
      I3 => stateCorner(1),
      I4 => \^rng_reg_1\,
      O => dy
    );
\dIgrm1[39]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(39),
      O => \dIgrm1[39]_i_2_n_0\
    );
\dIgrm1[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(3),
      O => \dIgrm1[3]_i_1_n_0\
    );
\dIgrm1[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(4),
      O => \dIgrm1[4]_i_1_n_0\
    );
\dIgrm1[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(5),
      O => \dIgrm1[5]_i_1_n_0\
    );
\dIgrm1[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(6),
      O => \dIgrm1[6]_i_1_n_0\
    );
\dIgrm1[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(7),
      O => \dIgrm1[7]_i_1_n_0\
    );
\dIgrm1[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(8),
      O => \dIgrm1[8]_i_1_n_0\
    );
\dIgrm1[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(9),
      O => \dIgrm1[9]_i_1_n_0\
    );
\dIgrm1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[0]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[0]\
    );
\dIgrm1_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[10]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[10]\
    );
\dIgrm1_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[11]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[11]\
    );
\dIgrm1_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[12]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[12]\
    );
\dIgrm1_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[13]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[13]\
    );
\dIgrm1_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[14]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[14]\
    );
\dIgrm1_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[15]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[15]\
    );
\dIgrm1_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[16]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[16]\
    );
\dIgrm1_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[17]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[17]\
    );
\dIgrm1_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[18]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[18]\
    );
\dIgrm1_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[19]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[19]\
    );
\dIgrm1_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[1]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[1]\
    );
\dIgrm1_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[20]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[20]\
    );
\dIgrm1_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[21]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[21]\
    );
\dIgrm1_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[22]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[22]\
    );
\dIgrm1_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[23]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[23]\
    );
\dIgrm1_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[24]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[24]\
    );
\dIgrm1_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[25]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[25]\
    );
\dIgrm1_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[26]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[26]\
    );
\dIgrm1_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[27]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[27]\
    );
\dIgrm1_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[28]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[28]\
    );
\dIgrm1_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[29]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[29]\
    );
\dIgrm1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[2]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[2]\
    );
\dIgrm1_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[30]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[30]\
    );
\dIgrm1_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[31]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[31]\
    );
\dIgrm1_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[32]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[32]\
    );
\dIgrm1_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[33]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[33]\
    );
\dIgrm1_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[34]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[34]\
    );
\dIgrm1_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[35]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[35]\
    );
\dIgrm1_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[36]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[36]\
    );
\dIgrm1_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[37]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[37]\
    );
\dIgrm1_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[38]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[38]\
    );
\dIgrm1_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[39]_i_2_n_0\,
      Q => \dIgrm1_reg_n_0_[39]\
    );
\dIgrm1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[3]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[3]\
    );
\dIgrm1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[4]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[4]\
    );
\dIgrm1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[5]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[5]\
    );
\dIgrm1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[6]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[6]\
    );
\dIgrm1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[7]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[7]\
    );
\dIgrm1_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[8]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[8]\
    );
\dIgrm1_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dIgrm1[9]_i_1_n_0\,
      Q => \dIgrm1_reg_n_0_[9]\
    );
\dImd[39]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0100FFFF"
    )
        port map (
      I0 => myImd1buf_n_17,
      I1 => \dImd[39]_i_3_n_0\,
      I2 => myImd1buf_n_18,
      I3 => \dImd[39]_i_5_n_0\,
      I4 => \stateImdstream[0]_i_3_n_0\,
      O => \dImd[39]_i_1_n_0\
    );
\dImd[39]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFA8"
    )
        port map (
      I0 => fghij(2),
      I1 => fghij(1),
      I2 => fghij(0),
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => p_1_in,
      I5 => myImd1buf_n_19,
      O => \dImd[39]_i_3_n_0\
    );
\dImd[39]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \aImdbuf[10]_i_3_n_0\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => ceScore,
      O => \dImd[39]_i_5_n_0\
    );
\dImd_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd4buf_n_15,
      Q => \dImd_reg_n_0_[0]\
    );
\dImd_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd3buf_n_13,
      Q => data3(2)
    );
\dImd_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd3buf_n_12,
      Q => data3(3)
    );
\dImd_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd3buf_n_11,
      Q => data3(4)
    );
\dImd_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd3buf_n_10,
      Q => data3(5)
    );
\dImd_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd3buf_n_9,
      Q => data3(6)
    );
\dImd_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd3buf_n_8,
      Q => data3(7)
    );
\dImd_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd2buf_n_15,
      Q => data2(0)
    );
\dImd_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd2buf_n_14,
      Q => data2(1)
    );
\dImd_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd2buf_n_13,
      Q => data2(2)
    );
\dImd_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd2buf_n_12,
      Q => data2(3)
    );
\dImd_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd4buf_n_14,
      Q => \dImd_reg_n_0_[1]\
    );
\dImd_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd2buf_n_11,
      Q => data2(4)
    );
\dImd_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd2buf_n_10,
      Q => data2(5)
    );
\dImd_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd2buf_n_9,
      Q => data2(6)
    );
\dImd_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd2buf_n_8,
      Q => data2(7)
    );
\dImd_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd1buf_n_15,
      Q => data1(0)
    );
\dImd_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd1buf_n_14,
      Q => data1(1)
    );
\dImd_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd1buf_n_13,
      Q => data1(2)
    );
\dImd_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd1buf_n_12,
      Q => data1(3)
    );
\dImd_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd1buf_n_11,
      Q => data1(4)
    );
\dImd_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd1buf_n_10,
      Q => data1(5)
    );
\dImd_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd4buf_n_13,
      Q => \dImd_reg_n_0_[2]\
    );
\dImd_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd1buf_n_9,
      Q => data1(6)
    );
\dImd_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd1buf_n_8,
      Q => data1(7)
    );
\dImd_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd0buf_n_15,
      Q => data0(0)
    );
\dImd_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd0buf_n_14,
      Q => data0(1)
    );
\dImd_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd0buf_n_13,
      Q => data0(2)
    );
\dImd_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd0buf_n_12,
      Q => data0(3)
    );
\dImd_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd0buf_n_11,
      Q => data0(4)
    );
\dImd_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd0buf_n_10,
      Q => data0(5)
    );
\dImd_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd0buf_n_9,
      Q => data0(6)
    );
\dImd_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd0buf_n_8,
      Q => data0(7)
    );
\dImd_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd4buf_n_12,
      Q => \dImd_reg_n_0_[3]\
    );
\dImd_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd4buf_n_11,
      Q => \dImd_reg_n_0_[4]\
    );
\dImd_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd4buf_n_10,
      Q => \dImd_reg_n_0_[5]\
    );
\dImd_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd4buf_n_9,
      Q => \dImd_reg_n_0_[6]\
    );
\dImd_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd4buf_n_8,
      Q => \dImd_reg_n_0_[7]\
    );
\dImd_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd3buf_n_15,
      Q => data3(0)
    );
\dImd_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dImd[39]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => myImd3buf_n_14,
      Q => data3(1)
    );
\diffI_II[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[15]\,
      I1 => termI(15),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[15]_i_10_n_0\
    );
\diffI_II[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[14]\,
      I1 => termI(14),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[15]_i_11_n_0\
    );
\diffI_II[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[13]\,
      I1 => termI(13),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[15]_i_12_n_0\
    );
\diffI_II[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[12]\,
      I1 => termI(12),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[15]_i_13_n_0\
    );
\diffI_II[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[11]\,
      I1 => termI(11),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[15]_i_14_n_0\
    );
\diffI_II[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[10]\,
      I1 => termI(10),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[15]_i_15_n_0\
    );
\diffI_II[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[9]\,
      I1 => termI(9),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[15]_i_16_n_0\
    );
\diffI_II[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[8]\,
      I1 => termI(8),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[15]_i_17_n_0\
    );
\diffI_II[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[15]\,
      O => \diffI_II[15]_i_2_n_0\
    );
\diffI_II[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[14]\,
      O => \diffI_II[15]_i_3_n_0\
    );
\diffI_II[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[13]\,
      O => \diffI_II[15]_i_4_n_0\
    );
\diffI_II[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[12]\,
      O => \diffI_II[15]_i_5_n_0\
    );
\diffI_II[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[11]\,
      O => \diffI_II[15]_i_6_n_0\
    );
\diffI_II[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[10]\,
      O => \diffI_II[15]_i_7_n_0\
    );
\diffI_II[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[9]\,
      O => \diffI_II[15]_i_8_n_0\
    );
\diffI_II[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[8]\,
      O => \diffI_II[15]_i_9_n_0\
    );
\diffI_II[23]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[23]\,
      I1 => termI(23),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[23]_i_10_n_0\
    );
\diffI_II[23]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[22]\,
      I1 => termI(22),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[23]_i_11_n_0\
    );
\diffI_II[23]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[21]\,
      I1 => termI(21),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[23]_i_12_n_0\
    );
\diffI_II[23]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[20]\,
      I1 => termI(20),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[23]_i_13_n_0\
    );
\diffI_II[23]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[19]\,
      I1 => termI(19),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[23]_i_14_n_0\
    );
\diffI_II[23]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[18]\,
      I1 => termI(18),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[23]_i_15_n_0\
    );
\diffI_II[23]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[17]\,
      I1 => termI(17),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[23]_i_16_n_0\
    );
\diffI_II[23]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[16]\,
      I1 => termI(16),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[23]_i_17_n_0\
    );
\diffI_II[23]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[23]\,
      O => \diffI_II[23]_i_2_n_0\
    );
\diffI_II[23]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[22]\,
      O => \diffI_II[23]_i_3_n_0\
    );
\diffI_II[23]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[21]\,
      O => \diffI_II[23]_i_4_n_0\
    );
\diffI_II[23]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[20]\,
      O => \diffI_II[23]_i_5_n_0\
    );
\diffI_II[23]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[19]\,
      O => \diffI_II[23]_i_6_n_0\
    );
\diffI_II[23]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[18]\,
      O => \diffI_II[23]_i_7_n_0\
    );
\diffI_II[23]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[17]\,
      O => \diffI_II[23]_i_8_n_0\
    );
\diffI_II[23]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[16]\,
      O => \diffI_II[23]_i_9_n_0\
    );
\diffI_II[31]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[31]\,
      I1 => termI(31),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[31]_i_10_n_0\
    );
\diffI_II[31]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[30]\,
      I1 => termI(30),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[31]_i_11_n_0\
    );
\diffI_II[31]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[29]\,
      I1 => termI(29),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[31]_i_12_n_0\
    );
\diffI_II[31]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[28]\,
      I1 => termI(28),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[31]_i_13_n_0\
    );
\diffI_II[31]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[27]\,
      I1 => termI(27),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[31]_i_14_n_0\
    );
\diffI_II[31]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[26]\,
      I1 => termI(26),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[31]_i_15_n_0\
    );
\diffI_II[31]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[25]\,
      I1 => termI(25),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[31]_i_16_n_0\
    );
\diffI_II[31]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[24]\,
      I1 => termI(24),
      I2 => \stateScore_reg_rep__4_n_0\,
      O => \diffI_II[31]_i_17_n_0\
    );
\diffI_II[31]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[31]\,
      O => \diffI_II[31]_i_2_n_0\
    );
\diffI_II[31]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[30]\,
      O => \diffI_II[31]_i_3_n_0\
    );
\diffI_II[31]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[29]\,
      O => \diffI_II[31]_i_4_n_0\
    );
\diffI_II[31]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[28]\,
      O => \diffI_II[31]_i_5_n_0\
    );
\diffI_II[31]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[27]\,
      O => \diffI_II[31]_i_6_n_0\
    );
\diffI_II[31]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[26]\,
      O => \diffI_II[31]_i_7_n_0\
    );
\diffI_II[31]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[25]\,
      O => \diffI_II[31]_i_8_n_0\
    );
\diffI_II[31]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII_reg_n_0_[24]\,
      O => \diffI_II[31]_i_9_n_0\
    );
\diffI_II[39]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[39]\,
      I1 => termI(39),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[39]_i_10_n_0\
    );
\diffI_II[39]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[38]\,
      I1 => termI(38),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[39]_i_11_n_0\
    );
\diffI_II[39]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[37]\,
      I1 => termI(37),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[39]_i_12_n_0\
    );
\diffI_II[39]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[36]\,
      I1 => termI(36),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[39]_i_13_n_0\
    );
\diffI_II[39]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[35]\,
      I1 => termI(35),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[39]_i_14_n_0\
    );
\diffI_II[39]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[34]\,
      I1 => termI(34),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[39]_i_15_n_0\
    );
\diffI_II[39]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[33]\,
      I1 => termI(33),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[39]_i_16_n_0\
    );
\diffI_II[39]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[32]\,
      I1 => termI(32),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[39]_i_17_n_0\
    );
\diffI_II[39]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII_reg_n_0_[39]\,
      O => \diffI_II[39]_i_2_n_0\
    );
\diffI_II[39]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII_reg_n_0_[38]\,
      O => \diffI_II[39]_i_3_n_0\
    );
\diffI_II[39]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII_reg_n_0_[37]\,
      O => \diffI_II[39]_i_4_n_0\
    );
\diffI_II[39]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII_reg_n_0_[36]\,
      O => \diffI_II[39]_i_5_n_0\
    );
\diffI_II[39]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII_reg_n_0_[35]\,
      O => \diffI_II[39]_i_6_n_0\
    );
\diffI_II[39]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII_reg_n_0_[34]\,
      O => \diffI_II[39]_i_7_n_0\
    );
\diffI_II[39]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII_reg_n_0_[33]\,
      O => \diffI_II[39]_i_8_n_0\
    );
\diffI_II[39]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII_reg_n_0_[32]\,
      O => \diffI_II[39]_i_9_n_0\
    );
\diffI_II[46]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[44]\,
      I1 => termI(44),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[46]_i_10_n_0\
    );
\diffI_II[46]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[43]\,
      I1 => termI(43),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[46]_i_11_n_0\
    );
\diffI_II[46]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[42]\,
      I1 => termI(42),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[46]_i_12_n_0\
    );
\diffI_II[46]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[41]\,
      I1 => termI(41),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[46]_i_13_n_0\
    );
\diffI_II[46]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[40]\,
      I1 => termI(40),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[46]_i_14_n_0\
    );
\diffI_II[46]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII_reg_n_0_[45]\,
      O => \diffI_II[46]_i_2_n_0\
    );
\diffI_II[46]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII_reg_n_0_[44]\,
      O => \diffI_II[46]_i_3_n_0\
    );
\diffI_II[46]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII_reg_n_0_[43]\,
      O => \diffI_II[46]_i_4_n_0\
    );
\diffI_II[46]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII_reg_n_0_[42]\,
      O => \diffI_II[46]_i_5_n_0\
    );
\diffI_II[46]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII_reg_n_0_[41]\,
      O => \diffI_II[46]_i_6_n_0\
    );
\diffI_II[46]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII_reg_n_0_[40]\,
      O => \diffI_II[46]_i_7_n_0\
    );
\diffI_II[46]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[45]\,
      I1 => termI(45),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[46]_i_8_n_0\
    );
\diffI_II[46]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[45]\,
      I1 => termI(45),
      I2 => \stateScore_reg_rep__14_n_0\,
      O => \diffI_II[46]_i_9_n_0\
    );
\diffI_II[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[7]\,
      I1 => termI(7),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[7]_i_10_n_0\
    );
\diffI_II[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[6]\,
      I1 => termI(6),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[7]_i_11_n_0\
    );
\diffI_II[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[5]\,
      I1 => termI(5),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[7]_i_12_n_0\
    );
\diffI_II[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[4]\,
      I1 => termI(4),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[7]_i_13_n_0\
    );
\diffI_II[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[3]\,
      I1 => termI(3),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[7]_i_14_n_0\
    );
\diffI_II[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[2]\,
      I1 => termI(2),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[7]_i_15_n_0\
    );
\diffI_II[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[1]\,
      I1 => termI(1),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[7]_i_16_n_0\
    );
\diffI_II[7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \termII_reg_n_0_[0]\,
      I1 => termI(0),
      I2 => \stateScore_reg_rep__3_n_0\,
      O => \diffI_II[7]_i_17_n_0\
    );
\diffI_II[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[7]\,
      O => \diffI_II[7]_i_2_n_0\
    );
\diffI_II[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[6]\,
      O => \diffI_II[7]_i_3_n_0\
    );
\diffI_II[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[5]\,
      O => \diffI_II[7]_i_4_n_0\
    );
\diffI_II[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[4]\,
      O => \diffI_II[7]_i_5_n_0\
    );
\diffI_II[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[3]\,
      O => \diffI_II[7]_i_6_n_0\
    );
\diffI_II[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[2]\,
      O => \diffI_II[7]_i_7_n_0\
    );
\diffI_II[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[1]\,
      O => \diffI_II[7]_i_8_n_0\
    );
\diffI_II[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => \termII_reg_n_0_[0]\,
      O => \diffI_II[7]_i_9_n_0\
    );
\diffI_II_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[7]_i_1_n_15\,
      Q => diffI_II(0)
    );
\diffI_II_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[15]_i_1_n_13\,
      Q => diffI_II(10)
    );
\diffI_II_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[15]_i_1_n_12\,
      Q => diffI_II(11)
    );
\diffI_II_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[15]_i_1_n_11\,
      Q => diffI_II(12)
    );
\diffI_II_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[15]_i_1_n_10\,
      Q => diffI_II(13)
    );
\diffI_II_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[15]_i_1_n_9\,
      Q => diffI_II(14)
    );
\diffI_II_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[15]_i_1_n_8\,
      Q => diffI_II(15)
    );
\diffI_II_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \diffI_II_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \diffI_II_reg[15]_i_1_n_0\,
      CO(6) => \diffI_II_reg[15]_i_1_n_1\,
      CO(5) => \diffI_II_reg[15]_i_1_n_2\,
      CO(4) => \diffI_II_reg[15]_i_1_n_3\,
      CO(3) => \diffI_II_reg[15]_i_1_n_4\,
      CO(2) => \diffI_II_reg[15]_i_1_n_5\,
      CO(1) => \diffI_II_reg[15]_i_1_n_6\,
      CO(0) => \diffI_II_reg[15]_i_1_n_7\,
      DI(7) => \diffI_II[15]_i_2_n_0\,
      DI(6) => \diffI_II[15]_i_3_n_0\,
      DI(5) => \diffI_II[15]_i_4_n_0\,
      DI(4) => \diffI_II[15]_i_5_n_0\,
      DI(3) => \diffI_II[15]_i_6_n_0\,
      DI(2) => \diffI_II[15]_i_7_n_0\,
      DI(1) => \diffI_II[15]_i_8_n_0\,
      DI(0) => \diffI_II[15]_i_9_n_0\,
      O(7) => \diffI_II_reg[15]_i_1_n_8\,
      O(6) => \diffI_II_reg[15]_i_1_n_9\,
      O(5) => \diffI_II_reg[15]_i_1_n_10\,
      O(4) => \diffI_II_reg[15]_i_1_n_11\,
      O(3) => \diffI_II_reg[15]_i_1_n_12\,
      O(2) => \diffI_II_reg[15]_i_1_n_13\,
      O(1) => \diffI_II_reg[15]_i_1_n_14\,
      O(0) => \diffI_II_reg[15]_i_1_n_15\,
      S(7) => \diffI_II[15]_i_10_n_0\,
      S(6) => \diffI_II[15]_i_11_n_0\,
      S(5) => \diffI_II[15]_i_12_n_0\,
      S(4) => \diffI_II[15]_i_13_n_0\,
      S(3) => \diffI_II[15]_i_14_n_0\,
      S(2) => \diffI_II[15]_i_15_n_0\,
      S(1) => \diffI_II[15]_i_16_n_0\,
      S(0) => \diffI_II[15]_i_17_n_0\
    );
\diffI_II_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[23]_i_1_n_15\,
      Q => diffI_II(16)
    );
\diffI_II_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[23]_i_1_n_14\,
      Q => diffI_II(17)
    );
\diffI_II_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[23]_i_1_n_13\,
      Q => diffI_II(18)
    );
\diffI_II_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[23]_i_1_n_12\,
      Q => diffI_II(19)
    );
\diffI_II_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[7]_i_1_n_14\,
      Q => diffI_II(1)
    );
\diffI_II_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[23]_i_1_n_11\,
      Q => diffI_II(20)
    );
\diffI_II_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[23]_i_1_n_10\,
      Q => diffI_II(21)
    );
\diffI_II_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[23]_i_1_n_9\,
      Q => diffI_II(22)
    );
\diffI_II_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[23]_i_1_n_8\,
      Q => diffI_II(23)
    );
\diffI_II_reg[23]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \diffI_II_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \diffI_II_reg[23]_i_1_n_0\,
      CO(6) => \diffI_II_reg[23]_i_1_n_1\,
      CO(5) => \diffI_II_reg[23]_i_1_n_2\,
      CO(4) => \diffI_II_reg[23]_i_1_n_3\,
      CO(3) => \diffI_II_reg[23]_i_1_n_4\,
      CO(2) => \diffI_II_reg[23]_i_1_n_5\,
      CO(1) => \diffI_II_reg[23]_i_1_n_6\,
      CO(0) => \diffI_II_reg[23]_i_1_n_7\,
      DI(7) => \diffI_II[23]_i_2_n_0\,
      DI(6) => \diffI_II[23]_i_3_n_0\,
      DI(5) => \diffI_II[23]_i_4_n_0\,
      DI(4) => \diffI_II[23]_i_5_n_0\,
      DI(3) => \diffI_II[23]_i_6_n_0\,
      DI(2) => \diffI_II[23]_i_7_n_0\,
      DI(1) => \diffI_II[23]_i_8_n_0\,
      DI(0) => \diffI_II[23]_i_9_n_0\,
      O(7) => \diffI_II_reg[23]_i_1_n_8\,
      O(6) => \diffI_II_reg[23]_i_1_n_9\,
      O(5) => \diffI_II_reg[23]_i_1_n_10\,
      O(4) => \diffI_II_reg[23]_i_1_n_11\,
      O(3) => \diffI_II_reg[23]_i_1_n_12\,
      O(2) => \diffI_II_reg[23]_i_1_n_13\,
      O(1) => \diffI_II_reg[23]_i_1_n_14\,
      O(0) => \diffI_II_reg[23]_i_1_n_15\,
      S(7) => \diffI_II[23]_i_10_n_0\,
      S(6) => \diffI_II[23]_i_11_n_0\,
      S(5) => \diffI_II[23]_i_12_n_0\,
      S(4) => \diffI_II[23]_i_13_n_0\,
      S(3) => \diffI_II[23]_i_14_n_0\,
      S(2) => \diffI_II[23]_i_15_n_0\,
      S(1) => \diffI_II[23]_i_16_n_0\,
      S(0) => \diffI_II[23]_i_17_n_0\
    );
\diffI_II_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[31]_i_1_n_15\,
      Q => diffI_II(24)
    );
\diffI_II_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[31]_i_1_n_14\,
      Q => diffI_II(25)
    );
\diffI_II_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[31]_i_1_n_13\,
      Q => diffI_II(26)
    );
\diffI_II_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[31]_i_1_n_12\,
      Q => diffI_II(27)
    );
\diffI_II_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[31]_i_1_n_11\,
      Q => diffI_II(28)
    );
\diffI_II_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[31]_i_1_n_10\,
      Q => diffI_II(29)
    );
\diffI_II_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[7]_i_1_n_13\,
      Q => diffI_II(2)
    );
\diffI_II_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[31]_i_1_n_9\,
      Q => diffI_II(30)
    );
\diffI_II_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[31]_i_1_n_8\,
      Q => diffI_II(31)
    );
\diffI_II_reg[31]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \diffI_II_reg[23]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \diffI_II_reg[31]_i_1_n_0\,
      CO(6) => \diffI_II_reg[31]_i_1_n_1\,
      CO(5) => \diffI_II_reg[31]_i_1_n_2\,
      CO(4) => \diffI_II_reg[31]_i_1_n_3\,
      CO(3) => \diffI_II_reg[31]_i_1_n_4\,
      CO(2) => \diffI_II_reg[31]_i_1_n_5\,
      CO(1) => \diffI_II_reg[31]_i_1_n_6\,
      CO(0) => \diffI_II_reg[31]_i_1_n_7\,
      DI(7) => \diffI_II[31]_i_2_n_0\,
      DI(6) => \diffI_II[31]_i_3_n_0\,
      DI(5) => \diffI_II[31]_i_4_n_0\,
      DI(4) => \diffI_II[31]_i_5_n_0\,
      DI(3) => \diffI_II[31]_i_6_n_0\,
      DI(2) => \diffI_II[31]_i_7_n_0\,
      DI(1) => \diffI_II[31]_i_8_n_0\,
      DI(0) => \diffI_II[31]_i_9_n_0\,
      O(7) => \diffI_II_reg[31]_i_1_n_8\,
      O(6) => \diffI_II_reg[31]_i_1_n_9\,
      O(5) => \diffI_II_reg[31]_i_1_n_10\,
      O(4) => \diffI_II_reg[31]_i_1_n_11\,
      O(3) => \diffI_II_reg[31]_i_1_n_12\,
      O(2) => \diffI_II_reg[31]_i_1_n_13\,
      O(1) => \diffI_II_reg[31]_i_1_n_14\,
      O(0) => \diffI_II_reg[31]_i_1_n_15\,
      S(7) => \diffI_II[31]_i_10_n_0\,
      S(6) => \diffI_II[31]_i_11_n_0\,
      S(5) => \diffI_II[31]_i_12_n_0\,
      S(4) => \diffI_II[31]_i_13_n_0\,
      S(3) => \diffI_II[31]_i_14_n_0\,
      S(2) => \diffI_II[31]_i_15_n_0\,
      S(1) => \diffI_II[31]_i_16_n_0\,
      S(0) => \diffI_II[31]_i_17_n_0\
    );
\diffI_II_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[39]_i_1_n_15\,
      Q => diffI_II(32)
    );
\diffI_II_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[39]_i_1_n_14\,
      Q => diffI_II(33)
    );
\diffI_II_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[39]_i_1_n_13\,
      Q => diffI_II(34)
    );
\diffI_II_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[39]_i_1_n_12\,
      Q => diffI_II(35)
    );
\diffI_II_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[39]_i_1_n_11\,
      Q => diffI_II(36)
    );
\diffI_II_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[39]_i_1_n_10\,
      Q => diffI_II(37)
    );
\diffI_II_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[39]_i_1_n_9\,
      Q => diffI_II(38)
    );
\diffI_II_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[39]_i_1_n_8\,
      Q => diffI_II(39)
    );
\diffI_II_reg[39]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \diffI_II_reg[31]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \diffI_II_reg[39]_i_1_n_0\,
      CO(6) => \diffI_II_reg[39]_i_1_n_1\,
      CO(5) => \diffI_II_reg[39]_i_1_n_2\,
      CO(4) => \diffI_II_reg[39]_i_1_n_3\,
      CO(3) => \diffI_II_reg[39]_i_1_n_4\,
      CO(2) => \diffI_II_reg[39]_i_1_n_5\,
      CO(1) => \diffI_II_reg[39]_i_1_n_6\,
      CO(0) => \diffI_II_reg[39]_i_1_n_7\,
      DI(7) => \diffI_II[39]_i_2_n_0\,
      DI(6) => \diffI_II[39]_i_3_n_0\,
      DI(5) => \diffI_II[39]_i_4_n_0\,
      DI(4) => \diffI_II[39]_i_5_n_0\,
      DI(3) => \diffI_II[39]_i_6_n_0\,
      DI(2) => \diffI_II[39]_i_7_n_0\,
      DI(1) => \diffI_II[39]_i_8_n_0\,
      DI(0) => \diffI_II[39]_i_9_n_0\,
      O(7) => \diffI_II_reg[39]_i_1_n_8\,
      O(6) => \diffI_II_reg[39]_i_1_n_9\,
      O(5) => \diffI_II_reg[39]_i_1_n_10\,
      O(4) => \diffI_II_reg[39]_i_1_n_11\,
      O(3) => \diffI_II_reg[39]_i_1_n_12\,
      O(2) => \diffI_II_reg[39]_i_1_n_13\,
      O(1) => \diffI_II_reg[39]_i_1_n_14\,
      O(0) => \diffI_II_reg[39]_i_1_n_15\,
      S(7) => \diffI_II[39]_i_10_n_0\,
      S(6) => \diffI_II[39]_i_11_n_0\,
      S(5) => \diffI_II[39]_i_12_n_0\,
      S(4) => \diffI_II[39]_i_13_n_0\,
      S(3) => \diffI_II[39]_i_14_n_0\,
      S(2) => \diffI_II[39]_i_15_n_0\,
      S(1) => \diffI_II[39]_i_16_n_0\,
      S(0) => \diffI_II[39]_i_17_n_0\
    );
\diffI_II_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[7]_i_1_n_12\,
      Q => diffI_II(3)
    );
\diffI_II_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[46]_i_1_n_15\,
      Q => diffI_II(40)
    );
\diffI_II_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[46]_i_1_n_14\,
      Q => diffI_II(41)
    );
\diffI_II_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[46]_i_1_n_13\,
      Q => diffI_II(42)
    );
\diffI_II_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[46]_i_1_n_12\,
      Q => diffI_II(43)
    );
\diffI_II_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[46]_i_1_n_11\,
      Q => diffI_II(44)
    );
\diffI_II_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[46]_i_1_n_10\,
      Q => diffI_II(45)
    );
\diffI_II_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[46]_i_1_n_9\,
      Q => diffI_II(46)
    );
\diffI_II_reg[46]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \diffI_II_reg[39]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_diffI_II_reg[46]_i_1_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \diffI_II_reg[46]_i_1_n_2\,
      CO(4) => \diffI_II_reg[46]_i_1_n_3\,
      CO(3) => \diffI_II_reg[46]_i_1_n_4\,
      CO(2) => \diffI_II_reg[46]_i_1_n_5\,
      CO(1) => \diffI_II_reg[46]_i_1_n_6\,
      CO(0) => \diffI_II_reg[46]_i_1_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \diffI_II[46]_i_2_n_0\,
      DI(4) => \diffI_II[46]_i_3_n_0\,
      DI(3) => \diffI_II[46]_i_4_n_0\,
      DI(2) => \diffI_II[46]_i_5_n_0\,
      DI(1) => \diffI_II[46]_i_6_n_0\,
      DI(0) => \diffI_II[46]_i_7_n_0\,
      O(7) => \NLW_diffI_II_reg[46]_i_1_O_UNCONNECTED\(7),
      O(6) => \diffI_II_reg[46]_i_1_n_9\,
      O(5) => \diffI_II_reg[46]_i_1_n_10\,
      O(4) => \diffI_II_reg[46]_i_1_n_11\,
      O(3) => \diffI_II_reg[46]_i_1_n_12\,
      O(2) => \diffI_II_reg[46]_i_1_n_13\,
      O(1) => \diffI_II_reg[46]_i_1_n_14\,
      O(0) => \diffI_II_reg[46]_i_1_n_15\,
      S(7) => '0',
      S(6) => \diffI_II[46]_i_8_n_0\,
      S(5) => \diffI_II[46]_i_9_n_0\,
      S(4) => \diffI_II[46]_i_10_n_0\,
      S(3) => \diffI_II[46]_i_11_n_0\,
      S(2) => \diffI_II[46]_i_12_n_0\,
      S(1) => \diffI_II[46]_i_13_n_0\,
      S(0) => \diffI_II[46]_i_14_n_0\
    );
\diffI_II_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[7]_i_1_n_11\,
      Q => diffI_II(4)
    );
\diffI_II_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[7]_i_1_n_10\,
      Q => diffI_II(5)
    );
\diffI_II_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[7]_i_1_n_9\,
      Q => diffI_II(6)
    );
\diffI_II_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[7]_i_1_n_8\,
      Q => diffI_II(7)
    );
\diffI_II_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \stateScore_reg_rep__3_n_0\,
      CI_TOP => '0',
      CO(7) => \diffI_II_reg[7]_i_1_n_0\,
      CO(6) => \diffI_II_reg[7]_i_1_n_1\,
      CO(5) => \diffI_II_reg[7]_i_1_n_2\,
      CO(4) => \diffI_II_reg[7]_i_1_n_3\,
      CO(3) => \diffI_II_reg[7]_i_1_n_4\,
      CO(2) => \diffI_II_reg[7]_i_1_n_5\,
      CO(1) => \diffI_II_reg[7]_i_1_n_6\,
      CO(0) => \diffI_II_reg[7]_i_1_n_7\,
      DI(7) => \diffI_II[7]_i_2_n_0\,
      DI(6) => \diffI_II[7]_i_3_n_0\,
      DI(5) => \diffI_II[7]_i_4_n_0\,
      DI(4) => \diffI_II[7]_i_5_n_0\,
      DI(3) => \diffI_II[7]_i_6_n_0\,
      DI(2) => \diffI_II[7]_i_7_n_0\,
      DI(1) => \diffI_II[7]_i_8_n_0\,
      DI(0) => \diffI_II[7]_i_9_n_0\,
      O(7) => \diffI_II_reg[7]_i_1_n_8\,
      O(6) => \diffI_II_reg[7]_i_1_n_9\,
      O(5) => \diffI_II_reg[7]_i_1_n_10\,
      O(4) => \diffI_II_reg[7]_i_1_n_11\,
      O(3) => \diffI_II_reg[7]_i_1_n_12\,
      O(2) => \diffI_II_reg[7]_i_1_n_13\,
      O(1) => \diffI_II_reg[7]_i_1_n_14\,
      O(0) => \diffI_II_reg[7]_i_1_n_15\,
      S(7) => \diffI_II[7]_i_10_n_0\,
      S(6) => \diffI_II[7]_i_11_n_0\,
      S(5) => \diffI_II[7]_i_12_n_0\,
      S(4) => \diffI_II[7]_i_13_n_0\,
      S(3) => \diffI_II[7]_i_14_n_0\,
      S(2) => \diffI_II[7]_i_15_n_0\,
      S(1) => \diffI_II[7]_i_16_n_0\,
      S(0) => \diffI_II[7]_i_17_n_0\
    );
\diffI_II_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[15]_i_1_n_15\,
      Q => diffI_II(8)
    );
\diffI_II_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_II_reg[15]_i_1_n_14\,
      Q => diffI_II(9)
    );
\diffI_IIp1[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(0),
      O => \diffI_IIp1[0]_i_1_n_0\
    );
\diffI_IIp1[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(10),
      O => \diffI_IIp1[10]_i_1_n_0\
    );
\diffI_IIp1[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(11),
      O => \diffI_IIp1[11]_i_1_n_0\
    );
\diffI_IIp1[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(12),
      O => \diffI_IIp1[12]_i_1_n_0\
    );
\diffI_IIp1[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(13),
      O => \diffI_IIp1[13]_i_1_n_0\
    );
\diffI_IIp1[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(14),
      O => \diffI_IIp1[14]_i_1_n_0\
    );
\diffI_IIp1[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(15),
      O => \diffI_IIp1[15]_i_1_n_0\
    );
\diffI_IIp1[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(16),
      O => \diffI_IIp1[16]_i_1_n_0\
    );
\diffI_IIp1[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(17),
      O => \diffI_IIp1[17]_i_1_n_0\
    );
\diffI_IIp1[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(18),
      O => \diffI_IIp1[18]_i_1_n_0\
    );
\diffI_IIp1[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(19),
      O => \diffI_IIp1[19]_i_1_n_0\
    );
\diffI_IIp1[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(1),
      O => \diffI_IIp1[1]_i_1_n_0\
    );
\diffI_IIp1[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(20),
      O => \diffI_IIp1[20]_i_1_n_0\
    );
\diffI_IIp1[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(21),
      O => \diffI_IIp1[21]_i_1_n_0\
    );
\diffI_IIp1[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(22),
      O => \diffI_IIp1[22]_i_1_n_0\
    );
\diffI_IIp1[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(23),
      O => \diffI_IIp1[23]_i_1_n_0\
    );
\diffI_IIp1[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(24),
      O => \diffI_IIp1[24]_i_1_n_0\
    );
\diffI_IIp1[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(25),
      O => \diffI_IIp1[25]_i_1_n_0\
    );
\diffI_IIp1[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(26),
      O => \diffI_IIp1[26]_i_1_n_0\
    );
\diffI_IIp1[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(27),
      O => \diffI_IIp1[27]_i_1_n_0\
    );
\diffI_IIp1[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(28),
      O => \diffI_IIp1[28]_i_1_n_0\
    );
\diffI_IIp1[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(29),
      O => \diffI_IIp1[29]_i_1_n_0\
    );
\diffI_IIp1[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(2),
      O => \diffI_IIp1[2]_i_1_n_0\
    );
\diffI_IIp1[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(30),
      O => \diffI_IIp1[30]_i_1_n_0\
    );
\diffI_IIp1[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(31),
      O => \diffI_IIp1[31]_i_1_n_0\
    );
\diffI_IIp1[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(32),
      O => \diffI_IIp1[32]_i_1_n_0\
    );
\diffI_IIp1[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(33),
      O => \diffI_IIp1[33]_i_1_n_0\
    );
\diffI_IIp1[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(34),
      O => \diffI_IIp1[34]_i_1_n_0\
    );
\diffI_IIp1[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(35),
      O => \diffI_IIp1[35]_i_1_n_0\
    );
\diffI_IIp1[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(36),
      O => \diffI_IIp1[36]_i_1_n_0\
    );
\diffI_IIp1[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(37),
      O => \diffI_IIp1[37]_i_1_n_0\
    );
\diffI_IIp1[38]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(38),
      O => \diffI_IIp1[38]_i_1_n_0\
    );
\diffI_IIp1[39]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(39),
      O => \diffI_IIp1[39]_i_1_n_0\
    );
\diffI_IIp1[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(3),
      O => \diffI_IIp1[3]_i_1_n_0\
    );
\diffI_IIp1[40]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(40),
      O => \diffI_IIp1[40]_i_1_n_0\
    );
\diffI_IIp1[41]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(41),
      O => \diffI_IIp1[41]_i_1_n_0\
    );
\diffI_IIp1[42]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(42),
      O => \diffI_IIp1[42]_i_1_n_0\
    );
\diffI_IIp1[43]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(43),
      O => \diffI_IIp1[43]_i_1_n_0\
    );
\diffI_IIp1[44]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(44),
      O => \diffI_IIp1[44]_i_1_n_0\
    );
\diffI_IIp1[45]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(45),
      O => \diffI_IIp1[45]_i_1_n_0\
    );
\diffI_IIp1[46]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => diffI_II(46),
      O => \diffI_IIp1[46]_i_1_n_0\
    );
\diffI_IIp1[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(4),
      O => \diffI_IIp1[4]_i_1_n_0\
    );
\diffI_IIp1[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(5),
      O => \diffI_IIp1[5]_i_1_n_0\
    );
\diffI_IIp1[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(6),
      O => \diffI_IIp1[6]_i_1_n_0\
    );
\diffI_IIp1[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(7),
      O => \diffI_IIp1[7]_i_1_n_0\
    );
\diffI_IIp1[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(8),
      O => \diffI_IIp1[8]_i_1_n_0\
    );
\diffI_IIp1[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => diffI_II(9),
      O => \diffI_IIp1[9]_i_1_n_0\
    );
\diffI_IIp1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[0]_i_1_n_0\,
      Q => diffI_IIp1(0)
    );
\diffI_IIp1_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[10]_i_1_n_0\,
      Q => diffI_IIp1(10)
    );
\diffI_IIp1_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[11]_i_1_n_0\,
      Q => diffI_IIp1(11)
    );
\diffI_IIp1_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[12]_i_1_n_0\,
      Q => diffI_IIp1(12)
    );
\diffI_IIp1_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[13]_i_1_n_0\,
      Q => diffI_IIp1(13)
    );
\diffI_IIp1_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[14]_i_1_n_0\,
      Q => diffI_IIp1(14)
    );
\diffI_IIp1_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[15]_i_1_n_0\,
      Q => diffI_IIp1(15)
    );
\diffI_IIp1_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[16]_i_1_n_0\,
      Q => diffI_IIp1(16)
    );
\diffI_IIp1_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[17]_i_1_n_0\,
      Q => diffI_IIp1(17)
    );
\diffI_IIp1_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[18]_i_1_n_0\,
      Q => diffI_IIp1(18)
    );
\diffI_IIp1_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[19]_i_1_n_0\,
      Q => diffI_IIp1(19)
    );
\diffI_IIp1_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[1]_i_1_n_0\,
      Q => diffI_IIp1(1)
    );
\diffI_IIp1_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[20]_i_1_n_0\,
      Q => diffI_IIp1(20)
    );
\diffI_IIp1_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[21]_i_1_n_0\,
      Q => diffI_IIp1(21)
    );
\diffI_IIp1_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[22]_i_1_n_0\,
      Q => diffI_IIp1(22)
    );
\diffI_IIp1_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[23]_i_1_n_0\,
      Q => diffI_IIp1(23)
    );
\diffI_IIp1_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[24]_i_1_n_0\,
      Q => diffI_IIp1(24)
    );
\diffI_IIp1_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[25]_i_1_n_0\,
      Q => diffI_IIp1(25)
    );
\diffI_IIp1_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[26]_i_1_n_0\,
      Q => diffI_IIp1(26)
    );
\diffI_IIp1_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[27]_i_1_n_0\,
      Q => diffI_IIp1(27)
    );
\diffI_IIp1_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[28]_i_1_n_0\,
      Q => diffI_IIp1(28)
    );
\diffI_IIp1_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[29]_i_1_n_0\,
      Q => diffI_IIp1(29)
    );
\diffI_IIp1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[2]_i_1_n_0\,
      Q => diffI_IIp1(2)
    );
\diffI_IIp1_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[30]_i_1_n_0\,
      Q => diffI_IIp1(30)
    );
\diffI_IIp1_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[31]_i_1_n_0\,
      Q => diffI_IIp1(31)
    );
\diffI_IIp1_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[32]_i_1_n_0\,
      Q => diffI_IIp1(32)
    );
\diffI_IIp1_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[33]_i_1_n_0\,
      Q => diffI_IIp1(33)
    );
\diffI_IIp1_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[34]_i_1_n_0\,
      Q => diffI_IIp1(34)
    );
\diffI_IIp1_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[35]_i_1_n_0\,
      Q => diffI_IIp1(35)
    );
\diffI_IIp1_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[36]_i_1_n_0\,
      Q => diffI_IIp1(36)
    );
\diffI_IIp1_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[37]_i_1_n_0\,
      Q => diffI_IIp1(37)
    );
\diffI_IIp1_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[38]_i_1_n_0\,
      Q => diffI_IIp1(38)
    );
\diffI_IIp1_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[39]_i_1_n_0\,
      Q => diffI_IIp1(39)
    );
\diffI_IIp1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[3]_i_1_n_0\,
      Q => diffI_IIp1(3)
    );
\diffI_IIp1_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[40]_i_1_n_0\,
      Q => diffI_IIp1(40)
    );
\diffI_IIp1_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[41]_i_1_n_0\,
      Q => diffI_IIp1(41)
    );
\diffI_IIp1_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[42]_i_1_n_0\,
      Q => diffI_IIp1(42)
    );
\diffI_IIp1_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[43]_i_1_n_0\,
      Q => diffI_IIp1(43)
    );
\diffI_IIp1_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[44]_i_1_n_0\,
      Q => diffI_IIp1(44)
    );
\diffI_IIp1_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[45]_i_1_n_0\,
      Q => diffI_IIp1(45)
    );
\diffI_IIp1_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[46]_i_1_n_0\,
      Q => diffI_IIp1(46)
    );
\diffI_IIp1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[4]_i_1_n_0\,
      Q => diffI_IIp1(4)
    );
\diffI_IIp1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[5]_i_1_n_0\,
      Q => diffI_IIp1(5)
    );
\diffI_IIp1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[6]_i_1_n_0\,
      Q => diffI_IIp1(6)
    );
\diffI_IIp1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[7]_i_1_n_0\,
      Q => diffI_IIp1(7)
    );
\diffI_IIp1_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[8]_i_1_n_0\,
      Q => diffI_IIp1(8)
    );
\diffI_IIp1_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \diffI_IIp1[9]_i_1_n_0\,
      Q => diffI_IIp1(9)
    );
\dwrCoobuf[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \col_lcl_reg[0]__0_n_0\,
      O => \dwrCoobuf[0]_i_1_n_0\
    );
\dwrCoobuf[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4E000A00"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[1]\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => enCoobuf_reg_0,
      I3 => \^rng_reg_0\,
      I4 => \col_lcl_reg[10]__0_n_0\,
      O => \dwrCoobuf[10]_i_1_n_0\
    );
\dwrCoobuf[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => row_lcl_reg(0),
      O => \dwrCoobuf[16]_i_1_n_0\
    );
\dwrCoobuf[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => row_lcl_reg(1),
      O => \dwrCoobuf[17]_i_1_n_0\
    );
\dwrCoobuf[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => row_lcl_reg(2),
      O => \dwrCoobuf[18]_i_1_n_0\
    );
\dwrCoobuf[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \^q\(0),
      O => \dwrCoobuf[19]_i_1_n_0\
    );
\dwrCoobuf[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4E000A00"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[1]\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => enCoobuf_reg_0,
      I3 => \^rng_reg_0\,
      I4 => \col_lcl_reg[1]__0_n_0\,
      O => \dwrCoobuf[1]_i_1_n_0\
    );
\dwrCoobuf[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \^q\(1),
      O => \dwrCoobuf[20]_i_1_n_0\
    );
\dwrCoobuf[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \^q\(2),
      O => \dwrCoobuf[21]_i_1_n_0\
    );
\dwrCoobuf[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \^q\(3),
      O => \dwrCoobuf[22]_i_1_n_0\
    );
\dwrCoobuf[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \^q\(4),
      O => \dwrCoobuf[23]_i_1_n_0\
    );
\dwrCoobuf[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \^q\(5),
      O => \dwrCoobuf[24]_i_1_n_0\
    );
\dwrCoobuf[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4E000A00"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[1]\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => enCoobuf_reg_0,
      I3 => \^rng_reg_0\,
      I4 => \^q\(6),
      O => \dwrCoobuf[25]_i_1_n_0\
    );
\dwrCoobuf[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4E000A00"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[1]\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => enCoobuf_reg_0,
      I3 => \^rng_reg_0\,
      I4 => \^q\(7),
      O => \dwrCoobuf[26]_i_1_n_0\
    );
\dwrCoobuf[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \col_lcl_reg[2]__0_n_0\,
      O => \dwrCoobuf[2]_i_1_n_0\
    );
\dwrCoobuf[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"373FFFFF"
    )
        port map (
      I0 => enCoobuf_reg_0,
      I1 => \dwrCoobuf[31]_i_3_n_0\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => \stateMaxsel_reg_n_0_[1]\,
      I4 => \^rng_reg_0\,
      O => \dwrCoobuf[31]_i_1_n_0\
    );
\dwrCoobuf[31]_i_100\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[2]_39\(3),
      I1 => \thd_reg_n_0_[3]\,
      I2 => \maximdsm1_reg[2]_39\(2),
      I3 => \thd_reg_n_0_[2]\,
      O => \dwrCoobuf[31]_i_100_n_0\
    );
\dwrCoobuf[31]_i_101\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[2]_39\(1),
      I1 => \thd_reg_n_0_[1]\,
      I2 => \maximdsm1_reg[2]_39\(0),
      I3 => \thd_reg_n_0_[0]\,
      O => \dwrCoobuf[31]_i_101_n_0\
    );
\dwrCoobuf[31]_i_103\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[7]\,
      I1 => \maximdsm1_reg[3]_38\(7),
      I2 => \maximdsm1_reg[3]_38\(6),
      I3 => \thd_reg_n_0_[6]\,
      O => \dwrCoobuf[31]_i_103_n_0\
    );
\dwrCoobuf[31]_i_104\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[5]\,
      I1 => \maximdsm1_reg[3]_38\(5),
      I2 => \maximdsm1_reg[3]_38\(4),
      I3 => \thd_reg_n_0_[4]\,
      O => \dwrCoobuf[31]_i_104_n_0\
    );
\dwrCoobuf[31]_i_105\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[3]\,
      I1 => \maximdsm1_reg[3]_38\(3),
      I2 => \maximdsm1_reg[3]_38\(2),
      I3 => \thd_reg_n_0_[2]\,
      O => \dwrCoobuf[31]_i_105_n_0\
    );
\dwrCoobuf[31]_i_106\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[1]\,
      I1 => \maximdsm1_reg[3]_38\(1),
      I2 => \maximdsm1_reg[3]_38\(0),
      I3 => \thd_reg_n_0_[0]\,
      O => \dwrCoobuf[31]_i_106_n_0\
    );
\dwrCoobuf[31]_i_107\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[3]_38\(7),
      I1 => \thd_reg_n_0_[7]\,
      I2 => \maximdsm1_reg[3]_38\(6),
      I3 => \thd_reg_n_0_[6]\,
      O => \dwrCoobuf[31]_i_107_n_0\
    );
\dwrCoobuf[31]_i_108\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[3]_38\(5),
      I1 => \thd_reg_n_0_[5]\,
      I2 => \maximdsm1_reg[3]_38\(4),
      I3 => \thd_reg_n_0_[4]\,
      O => \dwrCoobuf[31]_i_108_n_0\
    );
\dwrCoobuf[31]_i_109\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[3]_38\(3),
      I1 => \thd_reg_n_0_[3]\,
      I2 => \maximdsm1_reg[3]_38\(2),
      I3 => \thd_reg_n_0_[2]\,
      O => \dwrCoobuf[31]_i_109_n_0\
    );
\dwrCoobuf[31]_i_110\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[3]_38\(1),
      I1 => \thd_reg_n_0_[1]\,
      I2 => \maximdsm1_reg[3]_38\(0),
      I3 => \thd_reg_n_0_[0]\,
      O => \dwrCoobuf[31]_i_110_n_0\
    );
\dwrCoobuf[31]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BBBF"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[1]\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => ceMaxsel_reg_n_0,
      I3 => postNotLive_reg_n_0,
      O => \dwrCoobuf[31]_i_12_n_0\
    );
\dwrCoobuf[31]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FDFF0000"
    )
        port map (
      I0 => flag1,
      I1 => \ixMax_reg_n_0_[2]\,
      I2 => \ixMax_reg_n_0_[0]\,
      I3 => \dwrCoobuf[31]_i_68_n_0\,
      I4 => \ixMax_reg_n_0_[1]\,
      I5 => \dwrCoobuf[31]_i_69_n_0\,
      O => \dwrCoobuf[31]_i_13_n_0\
    );
\dwrCoobuf[31]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \colmax_lcl_reg_n_0_[1]\,
      I1 => \colmax_lcl_reg_n_0_[2]\,
      I2 => \colmax_lcl_reg_n_0_[0]\,
      O => \dwrCoobuf[31]_i_16_n_0\
    );
\dwrCoobuf[31]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \colmax_lcl_reg_n_0_[1]\,
      I1 => \colmax_lcl_reg_n_0_[0]\,
      I2 => \colmax_lcl_reg_n_0_[2]\,
      O => \dwrCoobuf[31]_i_18_n_0\
    );
\dwrCoobuf[31]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => col0(10),
      I1 => \col_lcl_reg[10]__0_n_0\,
      O => \dwrCoobuf[31]_i_19_n_0\
    );
\dwrCoobuf[31]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[1]\,
      I1 => \^rng_reg_0\,
      I2 => enCoobuf_reg_0,
      O => \dwrCoobuf[31]_i_2_n_0\
    );
\dwrCoobuf[31]_i_20\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \col_lcl_reg[9]__0_n_0\,
      I1 => col0(9),
      I2 => col0(8),
      I3 => \col_lcl_reg[8]__0_n_0\,
      O => \dwrCoobuf[31]_i_20_n_0\
    );
\dwrCoobuf[31]_i_21\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \col_lcl_reg[7]__0_n_0\,
      I1 => col0(7),
      I2 => col0(6),
      I3 => \col_lcl_reg[6]__0_n_0\,
      O => \dwrCoobuf[31]_i_21_n_0\
    );
\dwrCoobuf[31]_i_22\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \col_lcl_reg[5]__0_n_0\,
      I1 => col0(5),
      I2 => col0(4),
      I3 => \col_lcl_reg[4]__0_n_0\,
      O => \dwrCoobuf[31]_i_22_n_0\
    );
\dwrCoobuf[31]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \col_lcl_reg[3]__0_n_0\,
      I1 => col0(3),
      I2 => col0(2),
      I3 => \col_lcl_reg[2]__0_n_0\,
      O => \dwrCoobuf[31]_i_23_n_0\
    );
\dwrCoobuf[31]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \col_lcl_reg[1]__0_n_0\,
      I1 => col0(1),
      I2 => col0(0),
      I3 => \col_lcl_reg[0]__0_n_0\,
      O => \dwrCoobuf[31]_i_24_n_0\
    );
\dwrCoobuf[31]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \col_lcl_reg[10]__0_n_0\,
      I1 => col0(10),
      O => \dwrCoobuf[31]_i_25_n_0\
    );
\dwrCoobuf[31]_i_26\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => col0(9),
      I1 => \col_lcl_reg[9]__0_n_0\,
      I2 => col0(8),
      I3 => \col_lcl_reg[8]__0_n_0\,
      O => \dwrCoobuf[31]_i_26_n_0\
    );
\dwrCoobuf[31]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => col0(7),
      I1 => \col_lcl_reg[7]__0_n_0\,
      I2 => col0(6),
      I3 => \col_lcl_reg[6]__0_n_0\,
      O => \dwrCoobuf[31]_i_27_n_0\
    );
\dwrCoobuf[31]_i_28\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => col0(5),
      I1 => \col_lcl_reg[5]__0_n_0\,
      I2 => col0(4),
      I3 => \col_lcl_reg[4]__0_n_0\,
      O => \dwrCoobuf[31]_i_28_n_0\
    );
\dwrCoobuf[31]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => col0(3),
      I1 => \col_lcl_reg[3]__0_n_0\,
      I2 => col0(2),
      I3 => \col_lcl_reg[2]__0_n_0\,
      O => \dwrCoobuf[31]_i_29_n_0\
    );
\dwrCoobuf[31]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8F8F8FF"
    )
        port map (
      I0 => aCoobuf_reg(8),
      I1 => \dwrCoobuf[31]_i_4_n_0\,
      I2 => \dwrCoobuf[31]_i_5_n_0\,
      I3 => \dwrCoobuf[31]_i_6_n_0\,
      I4 => \ixMax_reg_n_0_[1]\,
      I5 => \dwrCoobuf[31]_i_7_n_0\,
      O => \dwrCoobuf[31]_i_3_n_0\
    );
\dwrCoobuf[31]_i_30\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => col0(1),
      I1 => \col_lcl_reg[1]__0_n_0\,
      I2 => col0(0),
      I3 => \col_lcl_reg[0]__0_n_0\,
      O => \dwrCoobuf[31]_i_30_n_0\
    );
\dwrCoobuf[31]_i_31\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^q\(7),
      I1 => row1(10),
      O => \dwrCoobuf[31]_i_31_n_0\
    );
\dwrCoobuf[31]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(6),
      I1 => row1(9),
      I2 => \^q\(5),
      I3 => row1(8),
      O => \dwrCoobuf[31]_i_32_n_0\
    );
\dwrCoobuf[31]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(4),
      I1 => row1(7),
      I2 => \^q\(3),
      I3 => row1(6),
      O => \dwrCoobuf[31]_i_33_n_0\
    );
\dwrCoobuf[31]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(2),
      I1 => row1(5),
      I2 => \^q\(1),
      I3 => row1(4),
      O => \dwrCoobuf[31]_i_34_n_0\
    );
\dwrCoobuf[31]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(0),
      I1 => row1(3),
      I2 => row_lcl_reg(2),
      I3 => row1(2),
      O => \dwrCoobuf[31]_i_35_n_0\
    );
\dwrCoobuf[31]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => row_lcl_reg(1),
      I1 => row1(1),
      I2 => row_lcl_reg(0),
      I3 => row1(0),
      O => \dwrCoobuf[31]_i_36_n_0\
    );
\dwrCoobuf[31]_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => row1(10),
      I1 => \^q\(7),
      O => \dwrCoobuf[31]_i_37_n_0\
    );
\dwrCoobuf[31]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => row1(9),
      I1 => \^q\(6),
      I2 => row1(8),
      I3 => \^q\(5),
      O => \dwrCoobuf[31]_i_38_n_0\
    );
\dwrCoobuf[31]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => row1(7),
      I1 => \^q\(4),
      I2 => row1(6),
      I3 => \^q\(3),
      O => \dwrCoobuf[31]_i_39_n_0\
    );
\dwrCoobuf[31]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => aCoobuf_reg(6),
      I1 => \aCoobuf[8]_i_3_n_0\,
      I2 => aCoobuf_reg(7),
      O => \dwrCoobuf[31]_i_4_n_0\
    );
\dwrCoobuf[31]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => row1(5),
      I1 => \^q\(2),
      I2 => row1(4),
      I3 => \^q\(1),
      O => \dwrCoobuf[31]_i_40_n_0\
    );
\dwrCoobuf[31]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => row1(3),
      I1 => \^q\(0),
      I2 => row1(2),
      I3 => row_lcl_reg(2),
      O => \dwrCoobuf[31]_i_41_n_0\
    );
\dwrCoobuf[31]_i_42\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => row1(1),
      I1 => row_lcl_reg(1),
      I2 => row1(0),
      I3 => row_lcl_reg(0),
      O => \dwrCoobuf[31]_i_42_n_0\
    );
\dwrCoobuf[31]_i_43\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => row0(10),
      I1 => \^q\(7),
      O => \dwrCoobuf[31]_i_43_n_0\
    );
\dwrCoobuf[31]_i_44\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \^q\(6),
      I1 => row0(9),
      I2 => row0(8),
      I3 => \^q\(5),
      O => \dwrCoobuf[31]_i_44_n_0\
    );
\dwrCoobuf[31]_i_45\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \^q\(4),
      I1 => row0(7),
      I2 => row0(6),
      I3 => \^q\(3),
      O => \dwrCoobuf[31]_i_45_n_0\
    );
\dwrCoobuf[31]_i_46\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \^q\(2),
      I1 => row0(5),
      I2 => row0(4),
      I3 => \^q\(1),
      O => \dwrCoobuf[31]_i_46_n_0\
    );
\dwrCoobuf[31]_i_47\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \^q\(0),
      I1 => row0(3),
      I2 => row0(2),
      I3 => row_lcl_reg(2),
      O => \dwrCoobuf[31]_i_47_n_0\
    );
\dwrCoobuf[31]_i_48\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => row_lcl_reg(1),
      I1 => row0(1),
      I2 => row0(0),
      I3 => row_lcl_reg(0),
      O => \dwrCoobuf[31]_i_48_n_0\
    );
\dwrCoobuf[31]_i_49\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(7),
      I1 => row0(10),
      O => \dwrCoobuf[31]_i_49_n_0\
    );
\dwrCoobuf[31]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => flag52_in,
      I1 => flag3,
      I2 => flag4,
      I3 => flag5,
      I4 => \dwrCoobuf[31]_i_12_n_0\,
      I5 => \dwrCoobuf[31]_i_13_n_0\,
      O => \dwrCoobuf[31]_i_5_n_0\
    );
\dwrCoobuf[31]_i_50\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => row0(9),
      I1 => \^q\(6),
      I2 => row0(8),
      I3 => \^q\(5),
      O => \dwrCoobuf[31]_i_50_n_0\
    );
\dwrCoobuf[31]_i_51\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => row0(7),
      I1 => \^q\(4),
      I2 => row0(6),
      I3 => \^q\(3),
      O => \dwrCoobuf[31]_i_51_n_0\
    );
\dwrCoobuf[31]_i_52\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => row0(5),
      I1 => \^q\(2),
      I2 => row0(4),
      I3 => \^q\(1),
      O => \dwrCoobuf[31]_i_52_n_0\
    );
\dwrCoobuf[31]_i_53\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => row0(3),
      I1 => \^q\(0),
      I2 => row0(2),
      I3 => row_lcl_reg(2),
      O => \dwrCoobuf[31]_i_53_n_0\
    );
\dwrCoobuf[31]_i_54\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => row0(1),
      I1 => row_lcl_reg(1),
      I2 => row0(0),
      I3 => row_lcl_reg(0),
      O => \dwrCoobuf[31]_i_54_n_0\
    );
\dwrCoobuf[31]_i_55\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \col_lcl_reg[10]__0_n_0\,
      I1 => col1(10),
      O => \dwrCoobuf[31]_i_55_n_0\
    );
\dwrCoobuf[31]_i_56\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \col_lcl_reg[9]__0_n_0\,
      I1 => col1(9),
      I2 => \col_lcl_reg[8]__0_n_0\,
      I3 => col1(8),
      O => \dwrCoobuf[31]_i_56_n_0\
    );
\dwrCoobuf[31]_i_57\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \col_lcl_reg[7]__0_n_0\,
      I1 => col1(7),
      I2 => \col_lcl_reg[6]__0_n_0\,
      I3 => col1(6),
      O => \dwrCoobuf[31]_i_57_n_0\
    );
\dwrCoobuf[31]_i_58\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \col_lcl_reg[5]__0_n_0\,
      I1 => col1(5),
      I2 => \col_lcl_reg[4]__0_n_0\,
      I3 => col1(4),
      O => \dwrCoobuf[31]_i_58_n_0\
    );
\dwrCoobuf[31]_i_59\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \col_lcl_reg[3]__0_n_0\,
      I1 => col1(3),
      I2 => \col_lcl_reg[2]__0_n_0\,
      I3 => col1(2),
      O => \dwrCoobuf[31]_i_59_n_0\
    );
\dwrCoobuf[31]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000400000000000"
    )
        port map (
      I0 => \colmax_lcl_reg_n_0_[2]\,
      I1 => \colmax_lcl_reg_n_0_[0]\,
      I2 => \colmax_lcl_reg_n_0_[1]\,
      I3 => flag2,
      I4 => \ixMax_reg_n_0_[2]\,
      I5 => \ixMax_reg_n_0_[0]\,
      O => \dwrCoobuf[31]_i_6_n_0\
    );
\dwrCoobuf[31]_i_60\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \col_lcl_reg[1]__0_n_0\,
      I1 => col1(1),
      I2 => \col_lcl_reg[0]__0_n_0\,
      I3 => col1(0),
      O => \dwrCoobuf[31]_i_60_n_0\
    );
\dwrCoobuf[31]_i_61\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => col1(10),
      I1 => \col_lcl_reg[10]__0_n_0\,
      O => \dwrCoobuf[31]_i_61_n_0\
    );
\dwrCoobuf[31]_i_62\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => col1(9),
      I1 => \col_lcl_reg[9]__0_n_0\,
      I2 => col1(8),
      I3 => \col_lcl_reg[8]__0_n_0\,
      O => \dwrCoobuf[31]_i_62_n_0\
    );
\dwrCoobuf[31]_i_63\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => col1(7),
      I1 => \col_lcl_reg[7]__0_n_0\,
      I2 => col1(6),
      I3 => \col_lcl_reg[6]__0_n_0\,
      O => \dwrCoobuf[31]_i_63_n_0\
    );
\dwrCoobuf[31]_i_64\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => col1(5),
      I1 => \col_lcl_reg[5]__0_n_0\,
      I2 => col1(4),
      I3 => \col_lcl_reg[4]__0_n_0\,
      O => \dwrCoobuf[31]_i_64_n_0\
    );
\dwrCoobuf[31]_i_65\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => col1(3),
      I1 => \col_lcl_reg[3]__0_n_0\,
      I2 => col1(2),
      I3 => \col_lcl_reg[2]__0_n_0\,
      O => \dwrCoobuf[31]_i_65_n_0\
    );
\dwrCoobuf[31]_i_66\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => col1(1),
      I1 => \col_lcl_reg[1]__0_n_0\,
      I2 => col1(0),
      I3 => \col_lcl_reg[0]__0_n_0\,
      O => \dwrCoobuf[31]_i_66_n_0\
    );
\dwrCoobuf[31]_i_68\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \colmax_lcl_reg_n_0_[2]\,
      I1 => \colmax_lcl_reg_n_0_[1]\,
      I2 => \colmax_lcl_reg_n_0_[0]\,
      O => \dwrCoobuf[31]_i_68_n_0\
    );
\dwrCoobuf[31]_i_69\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000000"
    )
        port map (
      I0 => \colmax_lcl_reg_n_0_[0]\,
      I1 => \colmax_lcl_reg_n_0_[1]\,
      I2 => \colmax_lcl_reg_n_0_[2]\,
      I3 => flag241_in,
      I4 => \ixMax_reg_n_0_[2]\,
      I5 => \ixMax_reg_n_0_[0]\,
      O => \dwrCoobuf[31]_i_69_n_0\
    );
\dwrCoobuf[31]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F8000800080008"
    )
        port map (
      I0 => flag234_in,
      I1 => \dwrCoobuf[31]_i_16_n_0\,
      I2 => \ixMax_reg_n_0_[2]\,
      I3 => \ixMax_reg_n_0_[0]\,
      I4 => flag238_in,
      I5 => \dwrCoobuf[31]_i_18_n_0\,
      O => \dwrCoobuf[31]_i_7_n_0\
    );
\dwrCoobuf[31]_i_70\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \maximdsm1_reg[1]_35\(7),
      I1 => \thd_reg_n_0_[7]\,
      I2 => \maximdsm1_reg[1]_35\(6),
      I3 => \thd_reg_n_0_[6]\,
      O => \dwrCoobuf[31]_i_70_n_0\
    );
\dwrCoobuf[31]_i_71\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \maximdsm1_reg[1]_35\(5),
      I1 => \thd_reg_n_0_[5]\,
      I2 => \maximdsm1_reg[1]_35\(4),
      I3 => \thd_reg_n_0_[4]\,
      O => \dwrCoobuf[31]_i_71_n_0\
    );
\dwrCoobuf[31]_i_72\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \maximdsm1_reg[1]_35\(3),
      I1 => \thd_reg_n_0_[3]\,
      I2 => \maximdsm1_reg[1]_35\(2),
      I3 => \thd_reg_n_0_[2]\,
      O => \dwrCoobuf[31]_i_72_n_0\
    );
\dwrCoobuf[31]_i_73\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \maximdsm1_reg[1]_35\(1),
      I1 => \thd_reg_n_0_[1]\,
      I2 => \maximdsm1_reg[1]_35\(0),
      I3 => \thd_reg_n_0_[0]\,
      O => \dwrCoobuf[31]_i_73_n_0\
    );
\dwrCoobuf[31]_i_74\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \thd_reg_n_0_[7]\,
      I1 => \maximdsm1_reg[1]_35\(7),
      I2 => \thd_reg_n_0_[6]\,
      I3 => \maximdsm1_reg[1]_35\(6),
      O => \dwrCoobuf[31]_i_74_n_0\
    );
\dwrCoobuf[31]_i_75\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \thd_reg_n_0_[5]\,
      I1 => \maximdsm1_reg[1]_35\(5),
      I2 => \thd_reg_n_0_[4]\,
      I3 => \maximdsm1_reg[1]_35\(4),
      O => \dwrCoobuf[31]_i_75_n_0\
    );
\dwrCoobuf[31]_i_76\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \thd_reg_n_0_[3]\,
      I1 => \maximdsm1_reg[1]_35\(3),
      I2 => \thd_reg_n_0_[2]\,
      I3 => \maximdsm1_reg[1]_35\(2),
      O => \dwrCoobuf[31]_i_76_n_0\
    );
\dwrCoobuf[31]_i_77\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \thd_reg_n_0_[1]\,
      I1 => \maximdsm1_reg[1]_35\(1),
      I2 => \thd_reg_n_0_[0]\,
      I3 => \maximdsm1_reg[1]_35\(0),
      O => \dwrCoobuf[31]_i_77_n_0\
    );
\dwrCoobuf[31]_i_78\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[7]\,
      I1 => \maximdsm1_reg[0]_36\(7),
      I2 => \maximdsm1_reg[0]_36\(6),
      I3 => \thd_reg_n_0_[6]\,
      O => \dwrCoobuf[31]_i_78_n_0\
    );
\dwrCoobuf[31]_i_79\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[5]\,
      I1 => \maximdsm1_reg[0]_36\(5),
      I2 => \maximdsm1_reg[0]_36\(4),
      I3 => \thd_reg_n_0_[4]\,
      O => \dwrCoobuf[31]_i_79_n_0\
    );
\dwrCoobuf[31]_i_80\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[3]\,
      I1 => \maximdsm1_reg[0]_36\(3),
      I2 => \maximdsm1_reg[0]_36\(2),
      I3 => \thd_reg_n_0_[2]\,
      O => \dwrCoobuf[31]_i_80_n_0\
    );
\dwrCoobuf[31]_i_81\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[1]\,
      I1 => \maximdsm1_reg[0]_36\(1),
      I2 => \maximdsm1_reg[0]_36\(0),
      I3 => \thd_reg_n_0_[0]\,
      O => \dwrCoobuf[31]_i_81_n_0\
    );
\dwrCoobuf[31]_i_82\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[0]_36\(7),
      I1 => \thd_reg_n_0_[7]\,
      I2 => \maximdsm1_reg[0]_36\(6),
      I3 => \thd_reg_n_0_[6]\,
      O => \dwrCoobuf[31]_i_82_n_0\
    );
\dwrCoobuf[31]_i_83\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[0]_36\(5),
      I1 => \thd_reg_n_0_[5]\,
      I2 => \maximdsm1_reg[0]_36\(4),
      I3 => \thd_reg_n_0_[4]\,
      O => \dwrCoobuf[31]_i_83_n_0\
    );
\dwrCoobuf[31]_i_84\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[0]_36\(3),
      I1 => \thd_reg_n_0_[3]\,
      I2 => \maximdsm1_reg[0]_36\(2),
      I3 => \thd_reg_n_0_[2]\,
      O => \dwrCoobuf[31]_i_84_n_0\
    );
\dwrCoobuf[31]_i_85\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[0]_36\(1),
      I1 => \thd_reg_n_0_[1]\,
      I2 => \maximdsm1_reg[0]_36\(0),
      I3 => \thd_reg_n_0_[0]\,
      O => \dwrCoobuf[31]_i_85_n_0\
    );
\dwrCoobuf[31]_i_86\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[7]\,
      I1 => \maximdsm1_reg[4]_37\(7),
      I2 => \maximdsm1_reg[4]_37\(6),
      I3 => \thd_reg_n_0_[6]\,
      O => \dwrCoobuf[31]_i_86_n_0\
    );
\dwrCoobuf[31]_i_87\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[5]\,
      I1 => \maximdsm1_reg[4]_37\(5),
      I2 => \maximdsm1_reg[4]_37\(4),
      I3 => \thd_reg_n_0_[4]\,
      O => \dwrCoobuf[31]_i_87_n_0\
    );
\dwrCoobuf[31]_i_88\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[3]\,
      I1 => \maximdsm1_reg[4]_37\(3),
      I2 => \maximdsm1_reg[4]_37\(2),
      I3 => \thd_reg_n_0_[2]\,
      O => \dwrCoobuf[31]_i_88_n_0\
    );
\dwrCoobuf[31]_i_89\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[1]\,
      I1 => \maximdsm1_reg[4]_37\(1),
      I2 => \maximdsm1_reg[4]_37\(0),
      I3 => \thd_reg_n_0_[0]\,
      O => \dwrCoobuf[31]_i_89_n_0\
    );
\dwrCoobuf[31]_i_90\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[4]_37\(7),
      I1 => \thd_reg_n_0_[7]\,
      I2 => \maximdsm1_reg[4]_37\(6),
      I3 => \thd_reg_n_0_[6]\,
      O => \dwrCoobuf[31]_i_90_n_0\
    );
\dwrCoobuf[31]_i_91\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[4]_37\(5),
      I1 => \thd_reg_n_0_[5]\,
      I2 => \maximdsm1_reg[4]_37\(4),
      I3 => \thd_reg_n_0_[4]\,
      O => \dwrCoobuf[31]_i_91_n_0\
    );
\dwrCoobuf[31]_i_92\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[4]_37\(3),
      I1 => \thd_reg_n_0_[3]\,
      I2 => \maximdsm1_reg[4]_37\(2),
      I3 => \thd_reg_n_0_[2]\,
      O => \dwrCoobuf[31]_i_92_n_0\
    );
\dwrCoobuf[31]_i_93\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[4]_37\(1),
      I1 => \thd_reg_n_0_[1]\,
      I2 => \maximdsm1_reg[4]_37\(0),
      I3 => \thd_reg_n_0_[0]\,
      O => \dwrCoobuf[31]_i_93_n_0\
    );
\dwrCoobuf[31]_i_94\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[7]\,
      I1 => \maximdsm1_reg[2]_39\(7),
      I2 => \maximdsm1_reg[2]_39\(6),
      I3 => \thd_reg_n_0_[6]\,
      O => \dwrCoobuf[31]_i_94_n_0\
    );
\dwrCoobuf[31]_i_95\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[5]\,
      I1 => \maximdsm1_reg[2]_39\(5),
      I2 => \maximdsm1_reg[2]_39\(4),
      I3 => \thd_reg_n_0_[4]\,
      O => \dwrCoobuf[31]_i_95_n_0\
    );
\dwrCoobuf[31]_i_96\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[3]\,
      I1 => \maximdsm1_reg[2]_39\(3),
      I2 => \maximdsm1_reg[2]_39\(2),
      I3 => \thd_reg_n_0_[2]\,
      O => \dwrCoobuf[31]_i_96_n_0\
    );
\dwrCoobuf[31]_i_97\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \thd_reg_n_0_[1]\,
      I1 => \maximdsm1_reg[2]_39\(1),
      I2 => \maximdsm1_reg[2]_39\(0),
      I3 => \thd_reg_n_0_[0]\,
      O => \dwrCoobuf[31]_i_97_n_0\
    );
\dwrCoobuf[31]_i_98\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[2]_39\(7),
      I1 => \thd_reg_n_0_[7]\,
      I2 => \maximdsm1_reg[2]_39\(6),
      I3 => \thd_reg_n_0_[6]\,
      O => \dwrCoobuf[31]_i_98_n_0\
    );
\dwrCoobuf[31]_i_99\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \maximdsm1_reg[2]_39\(5),
      I1 => \thd_reg_n_0_[5]\,
      I2 => \maximdsm1_reg[2]_39\(4),
      I3 => \thd_reg_n_0_[4]\,
      O => \dwrCoobuf[31]_i_99_n_0\
    );
\dwrCoobuf[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \col_lcl_reg[3]__0_n_0\,
      O => \dwrCoobuf[3]_i_1_n_0\
    );
\dwrCoobuf[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \col_lcl_reg[4]__0_n_0\,
      O => \dwrCoobuf[4]_i_1_n_0\
    );
\dwrCoobuf[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \col_lcl_reg[5]__0_n_0\,
      O => \dwrCoobuf[5]_i_1_n_0\
    );
\dwrCoobuf[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \col_lcl_reg[6]__0_n_0\,
      O => \dwrCoobuf[6]_i_1_n_0\
    );
\dwrCoobuf[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \col_lcl_reg[7]__0_n_0\,
      O => \dwrCoobuf[7]_i_1_n_0\
    );
\dwrCoobuf[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \col_lcl_reg[8]__0_n_0\,
      O => \dwrCoobuf[8]_i_1_n_0\
    );
\dwrCoobuf[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2A202020"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => enCoobuf_reg_0,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \col_lcl_reg[9]__0_n_0\,
      O => \dwrCoobuf[9]_i_1_n_0\
    );
\dwrCoobuf_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[0]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[0]\
    );
\dwrCoobuf_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[10]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[10]\
    );
\dwrCoobuf_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[16]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[16]\
    );
\dwrCoobuf_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[17]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[17]\
    );
\dwrCoobuf_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[18]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[18]\
    );
\dwrCoobuf_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[19]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[19]\
    );
\dwrCoobuf_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[1]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[1]\
    );
\dwrCoobuf_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[20]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[20]\
    );
\dwrCoobuf_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[21]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[21]\
    );
\dwrCoobuf_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[22]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[22]\
    );
\dwrCoobuf_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[23]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[23]\
    );
\dwrCoobuf_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[24]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[24]\
    );
\dwrCoobuf_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[25]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[25]\
    );
\dwrCoobuf_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[26]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[26]\
    );
\dwrCoobuf_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[2]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[2]\
    );
\dwrCoobuf_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[31]_i_2_n_0\,
      Q => \dwrCoobuf_reg_n_0_[31]\
    );
\dwrCoobuf_reg[31]_i_10\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_dwrCoobuf_reg[31]_i_10_CO_UNCONNECTED\(7 downto 6),
      CO(5) => flag4,
      CO(4) => \dwrCoobuf_reg[31]_i_10_n_3\,
      CO(3) => \dwrCoobuf_reg[31]_i_10_n_4\,
      CO(2) => \dwrCoobuf_reg[31]_i_10_n_5\,
      CO(1) => \dwrCoobuf_reg[31]_i_10_n_6\,
      CO(0) => \dwrCoobuf_reg[31]_i_10_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \dwrCoobuf[31]_i_43_n_0\,
      DI(4) => \dwrCoobuf[31]_i_44_n_0\,
      DI(3) => \dwrCoobuf[31]_i_45_n_0\,
      DI(2) => \dwrCoobuf[31]_i_46_n_0\,
      DI(1) => \dwrCoobuf[31]_i_47_n_0\,
      DI(0) => \dwrCoobuf[31]_i_48_n_0\,
      O(7 downto 0) => \NLW_dwrCoobuf_reg[31]_i_10_O_UNCONNECTED\(7 downto 0),
      S(7 downto 6) => B"00",
      S(5) => \dwrCoobuf[31]_i_49_n_0\,
      S(4) => \dwrCoobuf[31]_i_50_n_0\,
      S(3) => \dwrCoobuf[31]_i_51_n_0\,
      S(2) => \dwrCoobuf[31]_i_52_n_0\,
      S(1) => \dwrCoobuf[31]_i_53_n_0\,
      S(0) => \dwrCoobuf[31]_i_54_n_0\
    );
\dwrCoobuf_reg[31]_i_102\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_dwrCoobuf_reg[31]_i_102_CO_UNCONNECTED\(7 downto 4),
      CO(3) => flag241_in,
      CO(2) => \dwrCoobuf_reg[31]_i_102_n_5\,
      CO(1) => \dwrCoobuf_reg[31]_i_102_n_6\,
      CO(0) => \dwrCoobuf_reg[31]_i_102_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3) => \dwrCoobuf[31]_i_103_n_0\,
      DI(2) => \dwrCoobuf[31]_i_104_n_0\,
      DI(1) => \dwrCoobuf[31]_i_105_n_0\,
      DI(0) => \dwrCoobuf[31]_i_106_n_0\,
      O(7 downto 0) => \NLW_dwrCoobuf_reg[31]_i_102_O_UNCONNECTED\(7 downto 0),
      S(7 downto 4) => B"0000",
      S(3) => \dwrCoobuf[31]_i_107_n_0\,
      S(2) => \dwrCoobuf[31]_i_108_n_0\,
      S(1) => \dwrCoobuf[31]_i_109_n_0\,
      S(0) => \dwrCoobuf[31]_i_110_n_0\
    );
\dwrCoobuf_reg[31]_i_11\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_dwrCoobuf_reg[31]_i_11_CO_UNCONNECTED\(7 downto 6),
      CO(5) => flag5,
      CO(4) => \dwrCoobuf_reg[31]_i_11_n_3\,
      CO(3) => \dwrCoobuf_reg[31]_i_11_n_4\,
      CO(2) => \dwrCoobuf_reg[31]_i_11_n_5\,
      CO(1) => \dwrCoobuf_reg[31]_i_11_n_6\,
      CO(0) => \dwrCoobuf_reg[31]_i_11_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \dwrCoobuf[31]_i_55_n_0\,
      DI(4) => \dwrCoobuf[31]_i_56_n_0\,
      DI(3) => \dwrCoobuf[31]_i_57_n_0\,
      DI(2) => \dwrCoobuf[31]_i_58_n_0\,
      DI(1) => \dwrCoobuf[31]_i_59_n_0\,
      DI(0) => \dwrCoobuf[31]_i_60_n_0\,
      O(7 downto 0) => \NLW_dwrCoobuf_reg[31]_i_11_O_UNCONNECTED\(7 downto 0),
      S(7 downto 6) => B"00",
      S(5) => \dwrCoobuf[31]_i_61_n_0\,
      S(4) => \dwrCoobuf[31]_i_62_n_0\,
      S(3) => \dwrCoobuf[31]_i_63_n_0\,
      S(2) => \dwrCoobuf[31]_i_64_n_0\,
      S(1) => \dwrCoobuf[31]_i_65_n_0\,
      S(0) => \dwrCoobuf[31]_i_66_n_0\
    );
\dwrCoobuf_reg[31]_i_14\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_dwrCoobuf_reg[31]_i_14_CO_UNCONNECTED\(7 downto 4),
      CO(3) => flag2,
      CO(2) => \dwrCoobuf_reg[31]_i_14_n_5\,
      CO(1) => \dwrCoobuf_reg[31]_i_14_n_6\,
      CO(0) => \dwrCoobuf_reg[31]_i_14_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3) => \dwrCoobuf[31]_i_70_n_0\,
      DI(2) => \dwrCoobuf[31]_i_71_n_0\,
      DI(1) => \dwrCoobuf[31]_i_72_n_0\,
      DI(0) => \dwrCoobuf[31]_i_73_n_0\,
      O(7 downto 0) => \NLW_dwrCoobuf_reg[31]_i_14_O_UNCONNECTED\(7 downto 0),
      S(7 downto 4) => B"0000",
      S(3) => \dwrCoobuf[31]_i_74_n_0\,
      S(2) => \dwrCoobuf[31]_i_75_n_0\,
      S(1) => \dwrCoobuf[31]_i_76_n_0\,
      S(0) => \dwrCoobuf[31]_i_77_n_0\
    );
\dwrCoobuf_reg[31]_i_15\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_dwrCoobuf_reg[31]_i_15_CO_UNCONNECTED\(7 downto 4),
      CO(3) => flag234_in,
      CO(2) => \dwrCoobuf_reg[31]_i_15_n_5\,
      CO(1) => \dwrCoobuf_reg[31]_i_15_n_6\,
      CO(0) => \dwrCoobuf_reg[31]_i_15_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3) => \dwrCoobuf[31]_i_78_n_0\,
      DI(2) => \dwrCoobuf[31]_i_79_n_0\,
      DI(1) => \dwrCoobuf[31]_i_80_n_0\,
      DI(0) => \dwrCoobuf[31]_i_81_n_0\,
      O(7 downto 0) => \NLW_dwrCoobuf_reg[31]_i_15_O_UNCONNECTED\(7 downto 0),
      S(7 downto 4) => B"0000",
      S(3) => \dwrCoobuf[31]_i_82_n_0\,
      S(2) => \dwrCoobuf[31]_i_83_n_0\,
      S(1) => \dwrCoobuf[31]_i_84_n_0\,
      S(0) => \dwrCoobuf[31]_i_85_n_0\
    );
\dwrCoobuf_reg[31]_i_17\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_dwrCoobuf_reg[31]_i_17_CO_UNCONNECTED\(7 downto 4),
      CO(3) => flag238_in,
      CO(2) => \dwrCoobuf_reg[31]_i_17_n_5\,
      CO(1) => \dwrCoobuf_reg[31]_i_17_n_6\,
      CO(0) => \dwrCoobuf_reg[31]_i_17_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3) => \dwrCoobuf[31]_i_86_n_0\,
      DI(2) => \dwrCoobuf[31]_i_87_n_0\,
      DI(1) => \dwrCoobuf[31]_i_88_n_0\,
      DI(0) => \dwrCoobuf[31]_i_89_n_0\,
      O(7 downto 0) => \NLW_dwrCoobuf_reg[31]_i_17_O_UNCONNECTED\(7 downto 0),
      S(7 downto 4) => B"0000",
      S(3) => \dwrCoobuf[31]_i_90_n_0\,
      S(2) => \dwrCoobuf[31]_i_91_n_0\,
      S(1) => \dwrCoobuf[31]_i_92_n_0\,
      S(0) => \dwrCoobuf[31]_i_93_n_0\
    );
\dwrCoobuf_reg[31]_i_67\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_dwrCoobuf_reg[31]_i_67_CO_UNCONNECTED\(7 downto 4),
      CO(3) => flag1,
      CO(2) => \dwrCoobuf_reg[31]_i_67_n_5\,
      CO(1) => \dwrCoobuf_reg[31]_i_67_n_6\,
      CO(0) => \dwrCoobuf_reg[31]_i_67_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3) => \dwrCoobuf[31]_i_94_n_0\,
      DI(2) => \dwrCoobuf[31]_i_95_n_0\,
      DI(1) => \dwrCoobuf[31]_i_96_n_0\,
      DI(0) => \dwrCoobuf[31]_i_97_n_0\,
      O(7 downto 0) => \NLW_dwrCoobuf_reg[31]_i_67_O_UNCONNECTED\(7 downto 0),
      S(7 downto 4) => B"0000",
      S(3) => \dwrCoobuf[31]_i_98_n_0\,
      S(2) => \dwrCoobuf[31]_i_99_n_0\,
      S(1) => \dwrCoobuf[31]_i_100_n_0\,
      S(0) => \dwrCoobuf[31]_i_101_n_0\
    );
\dwrCoobuf_reg[31]_i_8\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_dwrCoobuf_reg[31]_i_8_CO_UNCONNECTED\(7 downto 6),
      CO(5) => flag52_in,
      CO(4) => \dwrCoobuf_reg[31]_i_8_n_3\,
      CO(3) => \dwrCoobuf_reg[31]_i_8_n_4\,
      CO(2) => \dwrCoobuf_reg[31]_i_8_n_5\,
      CO(1) => \dwrCoobuf_reg[31]_i_8_n_6\,
      CO(0) => \dwrCoobuf_reg[31]_i_8_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \dwrCoobuf[31]_i_19_n_0\,
      DI(4) => \dwrCoobuf[31]_i_20_n_0\,
      DI(3) => \dwrCoobuf[31]_i_21_n_0\,
      DI(2) => \dwrCoobuf[31]_i_22_n_0\,
      DI(1) => \dwrCoobuf[31]_i_23_n_0\,
      DI(0) => \dwrCoobuf[31]_i_24_n_0\,
      O(7 downto 0) => \NLW_dwrCoobuf_reg[31]_i_8_O_UNCONNECTED\(7 downto 0),
      S(7 downto 6) => B"00",
      S(5) => \dwrCoobuf[31]_i_25_n_0\,
      S(4) => \dwrCoobuf[31]_i_26_n_0\,
      S(3) => \dwrCoobuf[31]_i_27_n_0\,
      S(2) => \dwrCoobuf[31]_i_28_n_0\,
      S(1) => \dwrCoobuf[31]_i_29_n_0\,
      S(0) => \dwrCoobuf[31]_i_30_n_0\
    );
\dwrCoobuf_reg[31]_i_9\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_dwrCoobuf_reg[31]_i_9_CO_UNCONNECTED\(7 downto 6),
      CO(5) => flag3,
      CO(4) => \dwrCoobuf_reg[31]_i_9_n_3\,
      CO(3) => \dwrCoobuf_reg[31]_i_9_n_4\,
      CO(2) => \dwrCoobuf_reg[31]_i_9_n_5\,
      CO(1) => \dwrCoobuf_reg[31]_i_9_n_6\,
      CO(0) => \dwrCoobuf_reg[31]_i_9_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \dwrCoobuf[31]_i_31_n_0\,
      DI(4) => \dwrCoobuf[31]_i_32_n_0\,
      DI(3) => \dwrCoobuf[31]_i_33_n_0\,
      DI(2) => \dwrCoobuf[31]_i_34_n_0\,
      DI(1) => \dwrCoobuf[31]_i_35_n_0\,
      DI(0) => \dwrCoobuf[31]_i_36_n_0\,
      O(7 downto 0) => \NLW_dwrCoobuf_reg[31]_i_9_O_UNCONNECTED\(7 downto 0),
      S(7 downto 6) => B"00",
      S(5) => \dwrCoobuf[31]_i_37_n_0\,
      S(4) => \dwrCoobuf[31]_i_38_n_0\,
      S(3) => \dwrCoobuf[31]_i_39_n_0\,
      S(2) => \dwrCoobuf[31]_i_40_n_0\,
      S(1) => \dwrCoobuf[31]_i_41_n_0\,
      S(0) => \dwrCoobuf[31]_i_42_n_0\
    );
\dwrCoobuf_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[3]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[3]\
    );
\dwrCoobuf_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[4]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[4]\
    );
\dwrCoobuf_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[5]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[5]\
    );
\dwrCoobuf_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[6]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[6]\
    );
\dwrCoobuf_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[7]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[7]\
    );
\dwrCoobuf_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[8]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[8]\
    );
\dwrCoobuf_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrCoobuf[31]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \dwrCoobuf[9]_i_1_n_0\,
      Q => \dwrCoobuf_reg_n_0_[9]\
    );
\dx[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => \dIgrm1_reg_n_0_[0]\,
      I2 => grayVideoinToManyAXIS_tdata(0),
      O => \dx[0]_i_1_n_0\
    );
\dx[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(9),
      I2 => \dIgrm1_reg_n_0_[9]\,
      I3 => \dIgrm1_reg_n_0_[8]\,
      I4 => grayVideoinToManyAXIS_tdata(8),
      O => \dx[10]_i_1_n_0\
    );
\dx[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(10),
      I2 => \dIgrm1_reg_n_0_[10]\,
      I3 => \dx[11]_i_2_n_0\,
      O => \dx[11]_i_1_n_0\
    );
\dx[11]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2B22"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[9]\,
      I1 => grayVideoinToManyAXIS_tdata(9),
      I2 => grayVideoinToManyAXIS_tdata(8),
      I3 => \dIgrm1_reg_n_0_[8]\,
      O => \dx[11]_i_2_n_0\
    );
\dx[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(11),
      I2 => \dIgrm1_reg_n_0_[11]\,
      I3 => \dx[13]_i_2_n_0\,
      O => \dx[12]_i_1_n_0\
    );
\dx[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228828228288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(12),
      I2 => \dIgrm1_reg_n_0_[12]\,
      I3 => \dIgrm1_reg_n_0_[11]\,
      I4 => grayVideoinToManyAXIS_tdata(11),
      I5 => \dx[13]_i_2_n_0\,
      O => \dx[13]_i_1_n_0\
    );
\dx[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22B2BBBB222222B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[10]\,
      I1 => grayVideoinToManyAXIS_tdata(10),
      I2 => \dIgrm1_reg_n_0_[8]\,
      I3 => grayVideoinToManyAXIS_tdata(8),
      I4 => grayVideoinToManyAXIS_tdata(9),
      I5 => \dIgrm1_reg_n_0_[9]\,
      O => \dx[13]_i_2_n_0\
    );
\dx[14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(13),
      I2 => \dIgrm1_reg_n_0_[13]\,
      I3 => \dx[15]_i_2_n_0\,
      O => \dx[14]_i_1_n_0\
    );
\dx[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228828228288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(14),
      I2 => \dIgrm1_reg_n_0_[14]\,
      I3 => \dIgrm1_reg_n_0_[13]\,
      I4 => grayVideoinToManyAXIS_tdata(13),
      I5 => \dx[15]_i_2_n_0\,
      O => \dx[15]_i_1_n_0\
    );
\dx[15]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B2BB22B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[12]\,
      I1 => grayVideoinToManyAXIS_tdata(12),
      I2 => \dx[13]_i_2_n_0\,
      I3 => grayVideoinToManyAXIS_tdata(11),
      I4 => \dIgrm1_reg_n_0_[11]\,
      O => \dx[15]_i_2_n_0\
    );
\dx[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(15),
      I2 => \dIgrm1_reg_n_0_[15]\,
      I3 => \dx[17]_i_2_n_0\,
      O => \dx[16]_i_1_n_0\
    );
\dx[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8C08"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[15]\,
      I1 => \^rng_reg_1\,
      I2 => grayVideoinToManyAXIS_tdata(15),
      I3 => \dx[17]_i_2_n_0\,
      O => \dx[17]_i_1_n_0\
    );
\dx[17]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B2BB22B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[14]\,
      I1 => grayVideoinToManyAXIS_tdata(14),
      I2 => \dx[15]_i_2_n_0\,
      I3 => grayVideoinToManyAXIS_tdata(13),
      I4 => \dIgrm1_reg_n_0_[13]\,
      O => \dx[17]_i_2_n_0\
    );
\dx[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => \dIgrm1_reg_n_0_[16]\,
      I2 => grayVideoinToManyAXIS_tdata(16),
      O => \dx[18]_i_1_n_0\
    );
\dx[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(17),
      I2 => \dIgrm1_reg_n_0_[17]\,
      I3 => \dIgrm1_reg_n_0_[16]\,
      I4 => grayVideoinToManyAXIS_tdata(16),
      O => \dx[19]_i_1_n_0\
    );
\dx[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(1),
      I2 => \dIgrm1_reg_n_0_[1]\,
      I3 => \dIgrm1_reg_n_0_[0]\,
      I4 => grayVideoinToManyAXIS_tdata(0),
      O => \dx[1]_i_1_n_0\
    );
\dx[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(18),
      I2 => \dIgrm1_reg_n_0_[18]\,
      I3 => \dx[20]_i_2_n_0\,
      O => \dx[20]_i_1_n_0\
    );
\dx[20]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2B22"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[17]\,
      I1 => grayVideoinToManyAXIS_tdata(17),
      I2 => grayVideoinToManyAXIS_tdata(16),
      I3 => \dIgrm1_reg_n_0_[16]\,
      O => \dx[20]_i_2_n_0\
    );
\dx[21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(19),
      I2 => \dIgrm1_reg_n_0_[19]\,
      I3 => \dx[22]_i_2_n_0\,
      O => \dx[21]_i_1_n_0\
    );
\dx[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228828228288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(20),
      I2 => \dIgrm1_reg_n_0_[20]\,
      I3 => \dIgrm1_reg_n_0_[19]\,
      I4 => grayVideoinToManyAXIS_tdata(19),
      I5 => \dx[22]_i_2_n_0\,
      O => \dx[22]_i_1_n_0\
    );
\dx[22]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22B2BBBB222222B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[18]\,
      I1 => grayVideoinToManyAXIS_tdata(18),
      I2 => \dIgrm1_reg_n_0_[16]\,
      I3 => grayVideoinToManyAXIS_tdata(16),
      I4 => grayVideoinToManyAXIS_tdata(17),
      I5 => \dIgrm1_reg_n_0_[17]\,
      O => \dx[22]_i_2_n_0\
    );
\dx[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(21),
      I2 => \dIgrm1_reg_n_0_[21]\,
      I3 => \dx[24]_i_2_n_0\,
      O => \dx[23]_i_1_n_0\
    );
\dx[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228828228288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(22),
      I2 => \dIgrm1_reg_n_0_[22]\,
      I3 => \dIgrm1_reg_n_0_[21]\,
      I4 => grayVideoinToManyAXIS_tdata(21),
      I5 => \dx[24]_i_2_n_0\,
      O => \dx[24]_i_1_n_0\
    );
\dx[24]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B2BB22B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[20]\,
      I1 => grayVideoinToManyAXIS_tdata(20),
      I2 => \dx[22]_i_2_n_0\,
      I3 => grayVideoinToManyAXIS_tdata(19),
      I4 => \dIgrm1_reg_n_0_[19]\,
      O => \dx[24]_i_2_n_0\
    );
\dx[25]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(23),
      I2 => \dIgrm1_reg_n_0_[23]\,
      I3 => \dx[26]_i_2_n_0\,
      O => \dx[25]_i_1_n_0\
    );
\dx[26]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8C08"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[23]\,
      I1 => \^rng_reg_1\,
      I2 => grayVideoinToManyAXIS_tdata(23),
      I3 => \dx[26]_i_2_n_0\,
      O => \dx[26]_i_1_n_0\
    );
\dx[26]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B2BB22B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[22]\,
      I1 => grayVideoinToManyAXIS_tdata(22),
      I2 => \dx[24]_i_2_n_0\,
      I3 => grayVideoinToManyAXIS_tdata(21),
      I4 => \dIgrm1_reg_n_0_[21]\,
      O => \dx[26]_i_2_n_0\
    );
\dx[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => \dIgrm1_reg_n_0_[24]\,
      I2 => grayVideoinToManyAXIS_tdata(24),
      O => \dx[27]_i_1_n_0\
    );
\dx[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(25),
      I2 => \dIgrm1_reg_n_0_[25]\,
      I3 => \dIgrm1_reg_n_0_[24]\,
      I4 => grayVideoinToManyAXIS_tdata(24),
      O => \dx[28]_i_1_n_0\
    );
\dx[29]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(26),
      I2 => \dIgrm1_reg_n_0_[26]\,
      I3 => \dx[29]_i_2_n_0\,
      O => \dx[29]_i_1_n_0\
    );
\dx[29]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2B22"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[25]\,
      I1 => grayVideoinToManyAXIS_tdata(25),
      I2 => grayVideoinToManyAXIS_tdata(24),
      I3 => \dIgrm1_reg_n_0_[24]\,
      O => \dx[29]_i_2_n_0\
    );
\dx[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(2),
      I2 => \dIgrm1_reg_n_0_[2]\,
      I3 => \dx[2]_i_2_n_0\,
      O => \dx[2]_i_1_n_0\
    );
\dx[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2B22"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[1]\,
      I1 => grayVideoinToManyAXIS_tdata(1),
      I2 => grayVideoinToManyAXIS_tdata(0),
      I3 => \dIgrm1_reg_n_0_[0]\,
      O => \dx[2]_i_2_n_0\
    );
\dx[30]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(27),
      I2 => \dIgrm1_reg_n_0_[27]\,
      I3 => \dx[31]_i_2_n_0\,
      O => \dx[30]_i_1_n_0\
    );
\dx[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228828228288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(28),
      I2 => \dIgrm1_reg_n_0_[28]\,
      I3 => \dIgrm1_reg_n_0_[27]\,
      I4 => grayVideoinToManyAXIS_tdata(27),
      I5 => \dx[31]_i_2_n_0\,
      O => \dx[31]_i_1_n_0\
    );
\dx[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22B2BBBB222222B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[26]\,
      I1 => grayVideoinToManyAXIS_tdata(26),
      I2 => \dIgrm1_reg_n_0_[24]\,
      I3 => grayVideoinToManyAXIS_tdata(24),
      I4 => grayVideoinToManyAXIS_tdata(25),
      I5 => \dIgrm1_reg_n_0_[25]\,
      O => \dx[31]_i_2_n_0\
    );
\dx[32]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(29),
      I2 => \dIgrm1_reg_n_0_[29]\,
      I3 => \dx[33]_i_2_n_0\,
      O => \dx[32]_i_1_n_0\
    );
\dx[33]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228828228288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(30),
      I2 => \dIgrm1_reg_n_0_[30]\,
      I3 => \dIgrm1_reg_n_0_[29]\,
      I4 => grayVideoinToManyAXIS_tdata(29),
      I5 => \dx[33]_i_2_n_0\,
      O => \dx[33]_i_1_n_0\
    );
\dx[33]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B2BB22B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[28]\,
      I1 => grayVideoinToManyAXIS_tdata(28),
      I2 => \dx[31]_i_2_n_0\,
      I3 => grayVideoinToManyAXIS_tdata(27),
      I4 => \dIgrm1_reg_n_0_[27]\,
      O => \dx[33]_i_2_n_0\
    );
\dx[34]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(31),
      I2 => \dIgrm1_reg_n_0_[31]\,
      I3 => \dx[35]_i_2_n_0\,
      O => \dx[34]_i_1_n_0\
    );
\dx[35]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8C08"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[31]\,
      I1 => \^rng_reg_1\,
      I2 => grayVideoinToManyAXIS_tdata(31),
      I3 => \dx[35]_i_2_n_0\,
      O => \dx[35]_i_1_n_0\
    );
\dx[35]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B2BB22B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[30]\,
      I1 => grayVideoinToManyAXIS_tdata(30),
      I2 => \dx[33]_i_2_n_0\,
      I3 => grayVideoinToManyAXIS_tdata(29),
      I4 => \dIgrm1_reg_n_0_[29]\,
      O => \dx[35]_i_2_n_0\
    );
\dx[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => \dIgrm1_reg_n_0_[32]\,
      I2 => grayVideoinToManyAXIS_tdata(32),
      O => \dx[36]_i_1_n_0\
    );
\dx[37]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(33),
      I2 => \dIgrm1_reg_n_0_[33]\,
      I3 => \dIgrm1_reg_n_0_[32]\,
      I4 => grayVideoinToManyAXIS_tdata(32),
      O => \dx[37]_i_1_n_0\
    );
\dx[38]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(34),
      I2 => \dIgrm1_reg_n_0_[34]\,
      I3 => \dx[38]_i_2_n_0\,
      O => \dx[38]_i_1_n_0\
    );
\dx[38]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2B22"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[33]\,
      I1 => grayVideoinToManyAXIS_tdata(33),
      I2 => grayVideoinToManyAXIS_tdata(32),
      I3 => \dIgrm1_reg_n_0_[32]\,
      O => \dx[38]_i_2_n_0\
    );
\dx[39]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(35),
      I2 => \dIgrm1_reg_n_0_[35]\,
      I3 => \dx[40]_i_2_n_0\,
      O => \dx[39]_i_1_n_0\
    );
\dx[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(3),
      I2 => \dIgrm1_reg_n_0_[3]\,
      I3 => \dx[4]_i_2_n_0\,
      O => \dx[3]_i_1_n_0\
    );
\dx[40]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228828228288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(36),
      I2 => \dIgrm1_reg_n_0_[36]\,
      I3 => \dIgrm1_reg_n_0_[35]\,
      I4 => grayVideoinToManyAXIS_tdata(35),
      I5 => \dx[40]_i_2_n_0\,
      O => \dx[40]_i_1_n_0\
    );
\dx[40]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22B2BBBB222222B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[34]\,
      I1 => grayVideoinToManyAXIS_tdata(34),
      I2 => \dIgrm1_reg_n_0_[32]\,
      I3 => grayVideoinToManyAXIS_tdata(32),
      I4 => grayVideoinToManyAXIS_tdata(33),
      I5 => \dIgrm1_reg_n_0_[33]\,
      O => \dx[40]_i_2_n_0\
    );
\dx[41]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(37),
      I2 => \dIgrm1_reg_n_0_[37]\,
      I3 => \dx[42]_i_2_n_0\,
      O => \dx[41]_i_1_n_0\
    );
\dx[42]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228828228288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(38),
      I2 => \dIgrm1_reg_n_0_[38]\,
      I3 => \dIgrm1_reg_n_0_[37]\,
      I4 => grayVideoinToManyAXIS_tdata(37),
      I5 => \dx[42]_i_2_n_0\,
      O => \dx[42]_i_1_n_0\
    );
\dx[42]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B2BB22B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[36]\,
      I1 => grayVideoinToManyAXIS_tdata(36),
      I2 => \dx[40]_i_2_n_0\,
      I3 => grayVideoinToManyAXIS_tdata(35),
      I4 => \dIgrm1_reg_n_0_[35]\,
      O => \dx[42]_i_2_n_0\
    );
\dx[43]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(39),
      I2 => \dIgrm1_reg_n_0_[39]\,
      I3 => \dx[44]_i_2_n_0\,
      O => \dx[43]_i_1_n_0\
    );
\dx[44]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8C08"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[39]\,
      I1 => \^rng_reg_1\,
      I2 => grayVideoinToManyAXIS_tdata(39),
      I3 => \dx[44]_i_2_n_0\,
      O => \dx[44]_i_1_n_0\
    );
\dx[44]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B2BB22B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[38]\,
      I1 => grayVideoinToManyAXIS_tdata(38),
      I2 => \dx[42]_i_2_n_0\,
      I3 => grayVideoinToManyAXIS_tdata(37),
      I4 => \dIgrm1_reg_n_0_[37]\,
      O => \dx[44]_i_2_n_0\
    );
\dx[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228828228288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(4),
      I2 => \dIgrm1_reg_n_0_[4]\,
      I3 => \dIgrm1_reg_n_0_[3]\,
      I4 => grayVideoinToManyAXIS_tdata(3),
      I5 => \dx[4]_i_2_n_0\,
      O => \dx[4]_i_1_n_0\
    );
\dx[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22B2BBBB222222B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[2]\,
      I1 => grayVideoinToManyAXIS_tdata(2),
      I2 => \dIgrm1_reg_n_0_[0]\,
      I3 => grayVideoinToManyAXIS_tdata(0),
      I4 => grayVideoinToManyAXIS_tdata(1),
      I5 => \dIgrm1_reg_n_0_[1]\,
      O => \dx[4]_i_2_n_0\
    );
\dx[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(5),
      I2 => \dIgrm1_reg_n_0_[5]\,
      I3 => \dx[6]_i_2_n_0\,
      O => \dx[5]_i_1_n_0\
    );
\dx[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228828228288228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(6),
      I2 => \dIgrm1_reg_n_0_[6]\,
      I3 => \dIgrm1_reg_n_0_[5]\,
      I4 => grayVideoinToManyAXIS_tdata(5),
      I5 => \dx[6]_i_2_n_0\,
      O => \dx[6]_i_1_n_0\
    );
\dx[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B2BB22B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[4]\,
      I1 => grayVideoinToManyAXIS_tdata(4),
      I2 => \dx[4]_i_2_n_0\,
      I3 => grayVideoinToManyAXIS_tdata(3),
      I4 => \dIgrm1_reg_n_0_[3]\,
      O => \dx[6]_i_2_n_0\
    );
\dx[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => grayVideoinToManyAXIS_tdata(7),
      I2 => \dIgrm1_reg_n_0_[7]\,
      I3 => \dx[8]_i_2_n_0\,
      O => \dx[7]_i_1_n_0\
    );
\dx[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8C08"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[7]\,
      I1 => \^rng_reg_1\,
      I2 => grayVideoinToManyAXIS_tdata(7),
      I3 => \dx[8]_i_2_n_0\,
      O => \dx[8]_i_1_n_0\
    );
\dx[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B2BB22B2"
    )
        port map (
      I0 => \dIgrm1_reg_n_0_[6]\,
      I1 => grayVideoinToManyAXIS_tdata(6),
      I2 => \dx[6]_i_2_n_0\,
      I3 => grayVideoinToManyAXIS_tdata(5),
      I4 => \dIgrm1_reg_n_0_[5]\,
      O => \dx[8]_i_2_n_0\
    );
\dx[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => \dIgrm1_reg_n_0_[8]\,
      I2 => grayVideoinToManyAXIS_tdata(8),
      O => \dx[9]_i_1_n_0\
    );
\dx_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[0]_i_1_n_0\,
      Q => \dx_reg_n_0_[0]\
    );
\dx_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[10]_i_1_n_0\,
      Q => A(1)
    );
\dx_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[11]_i_1_n_0\,
      Q => A(2)
    );
\dx_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[12]_i_1_n_0\,
      Q => A(3)
    );
\dx_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[13]_i_1_n_0\,
      Q => A(4)
    );
\dx_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[14]_i_1_n_0\,
      Q => A(5)
    );
\dx_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[15]_i_1_n_0\,
      Q => A(6)
    );
\dx_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[16]_i_1_n_0\,
      Q => A(7)
    );
\dx_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[17]_i_1_n_0\,
      Q => A(8)
    );
\dx_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[18]_i_1_n_0\,
      Q => \dx_reg_n_0_[18]\
    );
\dx_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[19]_i_1_n_0\,
      Q => \dx_reg_n_0_[19]\
    );
\dx_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[1]_i_1_n_0\,
      Q => \dx_reg_n_0_[1]\
    );
\dx_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[20]_i_1_n_0\,
      Q => \dx_reg_n_0_[20]\
    );
\dx_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[21]_i_1_n_0\,
      Q => \dx_reg_n_0_[21]\
    );
\dx_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[22]_i_1_n_0\,
      Q => \dx_reg_n_0_[22]\
    );
\dx_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[23]_i_1_n_0\,
      Q => \dx_reg_n_0_[23]\
    );
\dx_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[24]_i_1_n_0\,
      Q => \dx_reg_n_0_[24]\
    );
\dx_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[25]_i_1_n_0\,
      Q => \dx_reg_n_0_[25]\
    );
\dx_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[26]_i_1_n_0\,
      Q => \dx_reg_n_0_[26]\
    );
\dx_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[27]_i_1_n_0\,
      Q => \dx_reg_n_0_[27]\
    );
\dx_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[28]_i_1_n_0\,
      Q => \dx_reg_n_0_[28]\
    );
\dx_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[29]_i_1_n_0\,
      Q => \dx_reg_n_0_[29]\
    );
\dx_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[2]_i_1_n_0\,
      Q => \dx_reg_n_0_[2]\
    );
\dx_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[30]_i_1_n_0\,
      Q => \dx_reg_n_0_[30]\
    );
\dx_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[31]_i_1_n_0\,
      Q => \dx_reg_n_0_[31]\
    );
\dx_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[32]_i_1_n_0\,
      Q => \dx_reg_n_0_[32]\
    );
\dx_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[33]_i_1_n_0\,
      Q => \dx_reg_n_0_[33]\
    );
\dx_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[34]_i_1_n_0\,
      Q => \dx_reg_n_0_[34]\
    );
\dx_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[35]_i_1_n_0\,
      Q => \dx_reg_n_0_[35]\
    );
\dx_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[36]_i_1_n_0\,
      Q => \dx_reg_n_0_[36]\
    );
\dx_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[37]_i_1_n_0\,
      Q => \dx_reg_n_0_[37]\
    );
\dx_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[38]_i_1_n_0\,
      Q => \dx_reg_n_0_[38]\
    );
\dx_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[39]_i_1_n_0\,
      Q => \dx_reg_n_0_[39]\
    );
\dx_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[3]_i_1_n_0\,
      Q => \dx_reg_n_0_[3]\
    );
\dx_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[40]_i_1_n_0\,
      Q => \dx_reg_n_0_[40]\
    );
\dx_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[41]_i_1_n_0\,
      Q => \dx_reg_n_0_[41]\
    );
\dx_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[42]_i_1_n_0\,
      Q => \dx_reg_n_0_[42]\
    );
\dx_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[43]_i_1_n_0\,
      Q => \dx_reg_n_0_[43]\
    );
\dx_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[44]_i_1_n_0\,
      Q => \dx_reg_n_0_[44]\
    );
\dx_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[4]_i_1_n_0\,
      Q => \dx_reg_n_0_[4]\
    );
\dx_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[5]_i_1_n_0\,
      Q => \dx_reg_n_0_[5]\
    );
\dx_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[6]_i_1_n_0\,
      Q => \dx_reg_n_0_[6]\
    );
\dx_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[7]_i_1_n_0\,
      Q => \dx_reg_n_0_[7]\
    );
\dx_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[8]_i_1_n_0\,
      Q => \dx_reg_n_0_[8]\
    );
\dx_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dx[9]_i_1_n_0\,
      Q => A(0)
    );
\dy_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(0),
      Q => \dy_reg_n_0_[0]\
    );
\dy_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(10),
      Q => B(1)
    );
\dy_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(11),
      Q => B(2)
    );
\dy_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(12),
      Q => B(3)
    );
\dy_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(13),
      Q => B(4)
    );
\dy_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(14),
      Q => B(5)
    );
\dy_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(15),
      Q => B(6)
    );
\dy_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(16),
      Q => B(7)
    );
\dy_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(17),
      Q => B(8)
    );
\dy_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(18),
      Q => \dy_reg_n_0_[18]\
    );
\dy_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(19),
      Q => \dy_reg_n_0_[19]\
    );
\dy_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(1),
      Q => \dy_reg_n_0_[1]\
    );
\dy_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(20),
      Q => \dy_reg_n_0_[20]\
    );
\dy_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(21),
      Q => \dy_reg_n_0_[21]\
    );
\dy_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(22),
      Q => \dy_reg_n_0_[22]\
    );
\dy_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(23),
      Q => \dy_reg_n_0_[23]\
    );
\dy_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(24),
      Q => \dy_reg_n_0_[24]\
    );
\dy_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(25),
      Q => \dy_reg_n_0_[25]\
    );
\dy_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(26),
      Q => \dy_reg_n_0_[26]\
    );
\dy_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(27),
      Q => \dy_reg_n_0_[27]\
    );
\dy_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(28),
      Q => \dy_reg_n_0_[28]\
    );
\dy_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(29),
      Q => \dy_reg_n_0_[29]\
    );
\dy_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(2),
      Q => \dy_reg_n_0_[2]\
    );
\dy_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(30),
      Q => \dy_reg_n_0_[30]\
    );
\dy_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(31),
      Q => \dy_reg_n_0_[31]\
    );
\dy_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(32),
      Q => \dy_reg_n_0_[32]\
    );
\dy_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(33),
      Q => \dy_reg_n_0_[33]\
    );
\dy_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(34),
      Q => \dy_reg_n_0_[34]\
    );
\dy_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(35),
      Q => \dy_reg_n_0_[35]\
    );
\dy_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(36),
      Q => \dy_reg_n_0_[36]\
    );
\dy_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(37),
      Q => \dy_reg_n_0_[37]\
    );
\dy_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(38),
      Q => \dy_reg_n_0_[38]\
    );
\dy_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(39),
      Q => \dy_reg_n_0_[39]\
    );
\dy_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(3),
      Q => \dy_reg_n_0_[3]\
    );
\dy_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(40),
      Q => \dy_reg_n_0_[40]\
    );
\dy_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(41),
      Q => \dy_reg_n_0_[41]\
    );
\dy_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(42),
      Q => \dy_reg_n_0_[42]\
    );
\dy_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(43),
      Q => \dy_reg_n_0_[43]\
    );
\dy_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(44),
      Q => \dy_reg_n_0_[44]\
    );
\dy_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(4),
      Q => \dy_reg_n_0_[4]\
    );
\dy_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(5),
      Q => \dy_reg_n_0_[5]\
    );
\dy_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(6),
      Q => \dy_reg_n_0_[6]\
    );
\dy_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(7),
      Q => \dy_reg_n_0_[7]\
    );
\dy_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(8),
      Q => \dy_reg_n_0_[8]\
    );
\dy_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => dy,
      CLR => linNotLog_reg_0,
      D => \dy_reg[44]_0\(9),
      Q => B(0)
    );
enCoobuf_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F370000003700000"
    )
        port map (
      I0 => enCoobuf_reg_0,
      I1 => \dwrCoobuf[31]_i_3_n_0\,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      I5 => enCoobuf_reg_n_0,
      O => enCoobuf_i_1_n_0
    );
enCoobuf_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => enCoobuf_i_1_n_0,
      Q => enCoobuf_reg_n_0
    );
enImdbuf_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA00AA000000080"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => ceScore,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => p_1_in,
      I5 => enImdbuf_reg_n_0,
      O => enImdbuf_i_1_n_0
    );
enImdbuf_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => enImdbuf_i_1_n_0,
      Q => enImdbuf_reg_n_0
    );
\fghij[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij(0),
      O => \fghij[0]_i_1_n_0\
    );
\fghij[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(10),
      O => \fghij[10]_i_1_n_0\
    );
\fghij[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(11),
      O => \fghij[11]_i_1_n_0\
    );
\fghij[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(12),
      O => \fghij[12]_i_1_n_0\
    );
\fghij[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(13),
      O => \fghij[13]_i_1_n_0\
    );
\fghij[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(14),
      O => \fghij[14]_i_1_n_0\
    );
\fghij[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(15),
      O => \fghij[15]_i_1_n_0\
    );
\fghij[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(16),
      O => \fghij[16]_i_1_n_0\
    );
\fghij[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(17),
      O => \fghij[17]_i_1_n_0\
    );
\fghij[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(18),
      O => \fghij[18]_i_1_n_0\
    );
\fghij[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(19),
      O => \fghij[19]_i_1_n_0\
    );
\fghij[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(1),
      O => \fghij[1]_i_1_n_0\
    );
\fghij[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(20),
      O => \fghij[20]_i_1_n_0\
    );
\fghij[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(21),
      O => \fghij[21]_i_1_n_0\
    );
\fghij[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(22),
      O => \fghij[22]_i_1_n_0\
    );
\fghij[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(23),
      O => \fghij[23]_i_1_n_0\
    );
\fghij[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(24),
      O => \fghij[24]_i_1_n_0\
    );
\fghij[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(25),
      O => \fghij[25]_i_1_n_0\
    );
\fghij[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(26),
      O => \fghij[26]_i_1_n_0\
    );
\fghij[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(27),
      O => \fghij[27]_i_1_n_0\
    );
\fghij[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(28),
      O => \fghij[28]_i_1_n_0\
    );
\fghij[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(29),
      O => \fghij[29]_i_1_n_0\
    );
\fghij[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(2),
      O => \fghij[2]_i_1_n_0\
    );
\fghij[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555555775555F5FF"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \tkst_reg[0]_0\,
      I2 => ceScore,
      I3 => \stateImdstream_reg_n_0_[1]\,
      I4 => \stateImdstream_reg_n_0_[0]\,
      I5 => p_1_in,
      O => \fghij[30]_i_1_n_0\
    );
\fghij[30]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(30),
      O => \fghij[30]_i_2_n_0\
    );
\fghij[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(3),
      O => \fghij[3]_i_1_n_0\
    );
\fghij[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(4),
      O => \fghij[4]_i_1_n_0\
    );
\fghij[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(5),
      O => \fghij[5]_i_1_n_0\
    );
\fghij[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(6),
      O => \fghij[6]_i_1_n_0\
    );
\fghij[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(7),
      O => \fghij[7]_i_1_n_0\
    );
\fghij[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(8),
      O => \fghij[8]_i_1_n_0\
    );
\fghij[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => myImd4buf_n_16,
      I5 => fghij0(9),
      O => \fghij[9]_i_1_n_0\
    );
\fghij_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[0]_i_1_n_0\,
      Q => fghij(0)
    );
\fghij_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[10]_i_1_n_0\,
      Q => fghij(10)
    );
\fghij_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[11]_i_1_n_0\,
      Q => fghij(11)
    );
\fghij_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[12]_i_1_n_0\,
      Q => fghij(12)
    );
\fghij_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[13]_i_1_n_0\,
      Q => fghij(13)
    );
\fghij_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[14]_i_1_n_0\,
      Q => fghij(14)
    );
\fghij_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[15]_i_1_n_0\,
      Q => fghij(15)
    );
\fghij_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[16]_i_1_n_0\,
      Q => fghij(16)
    );
\fghij_reg[16]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \fghij_reg[8]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \fghij_reg[16]_i_2_n_0\,
      CO(6) => \fghij_reg[16]_i_2_n_1\,
      CO(5) => \fghij_reg[16]_i_2_n_2\,
      CO(4) => \fghij_reg[16]_i_2_n_3\,
      CO(3) => \fghij_reg[16]_i_2_n_4\,
      CO(2) => \fghij_reg[16]_i_2_n_5\,
      CO(1) => \fghij_reg[16]_i_2_n_6\,
      CO(0) => \fghij_reg[16]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => fghij0(16 downto 9),
      S(7 downto 0) => fghij(16 downto 9)
    );
\fghij_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[17]_i_1_n_0\,
      Q => fghij(17)
    );
\fghij_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[18]_i_1_n_0\,
      Q => fghij(18)
    );
\fghij_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[19]_i_1_n_0\,
      Q => fghij(19)
    );
\fghij_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[1]_i_1_n_0\,
      Q => fghij(1)
    );
\fghij_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[20]_i_1_n_0\,
      Q => fghij(20)
    );
\fghij_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[21]_i_1_n_0\,
      Q => fghij(21)
    );
\fghij_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[22]_i_1_n_0\,
      Q => fghij(22)
    );
\fghij_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[23]_i_1_n_0\,
      Q => fghij(23)
    );
\fghij_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[24]_i_1_n_0\,
      Q => fghij(24)
    );
\fghij_reg[24]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \fghij_reg[16]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \fghij_reg[24]_i_2_n_0\,
      CO(6) => \fghij_reg[24]_i_2_n_1\,
      CO(5) => \fghij_reg[24]_i_2_n_2\,
      CO(4) => \fghij_reg[24]_i_2_n_3\,
      CO(3) => \fghij_reg[24]_i_2_n_4\,
      CO(2) => \fghij_reg[24]_i_2_n_5\,
      CO(1) => \fghij_reg[24]_i_2_n_6\,
      CO(0) => \fghij_reg[24]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => fghij0(24 downto 17),
      S(7 downto 0) => fghij(24 downto 17)
    );
\fghij_reg[25]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[25]_i_1_n_0\,
      Q => fghij(25)
    );
\fghij_reg[26]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[26]_i_1_n_0\,
      Q => fghij(26)
    );
\fghij_reg[27]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[27]_i_1_n_0\,
      Q => fghij(27)
    );
\fghij_reg[28]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[28]_i_1_n_0\,
      Q => fghij(28)
    );
\fghij_reg[29]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[29]_i_1_n_0\,
      Q => fghij(29)
    );
\fghij_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[2]_i_1_n_0\,
      Q => fghij(2)
    );
\fghij_reg[30]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[30]_i_2_n_0\,
      Q => fghij(30)
    );
\fghij_reg[30]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \fghij_reg[24]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_fghij_reg[30]_i_3_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \fghij_reg[30]_i_3_n_3\,
      CO(3) => \fghij_reg[30]_i_3_n_4\,
      CO(2) => \fghij_reg[30]_i_3_n_5\,
      CO(1) => \fghij_reg[30]_i_3_n_6\,
      CO(0) => \fghij_reg[30]_i_3_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 6) => \NLW_fghij_reg[30]_i_3_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => fghij0(30 downto 25),
      S(7 downto 6) => B"00",
      S(5 downto 0) => fghij(30 downto 25)
    );
\fghij_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[3]_i_1_n_0\,
      Q => fghij(3)
    );
\fghij_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[4]_i_1_n_0\,
      Q => fghij(4)
    );
\fghij_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[5]_i_1_n_0\,
      Q => fghij(5)
    );
\fghij_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[6]_i_1_n_0\,
      Q => fghij(6)
    );
\fghij_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[7]_i_1_n_0\,
      Q => fghij(7)
    );
\fghij_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[8]_i_1_n_0\,
      Q => fghij(8)
    );
\fghij_reg[8]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => fghij(0),
      CI_TOP => '0',
      CO(7) => \fghij_reg[8]_i_2_n_0\,
      CO(6) => \fghij_reg[8]_i_2_n_1\,
      CO(5) => \fghij_reg[8]_i_2_n_2\,
      CO(4) => \fghij_reg[8]_i_2_n_3\,
      CO(3) => \fghij_reg[8]_i_2_n_4\,
      CO(2) => \fghij_reg[8]_i_2_n_5\,
      CO(1) => \fghij_reg[8]_i_2_n_6\,
      CO(0) => \fghij_reg[8]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => fghij0(8 downto 1),
      S(7 downto 0) => fghij(8 downto 1)
    );
\fghij_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \fghij[30]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \fghij[9]_i_1_n_0\,
      Q => fghij(9)
    );
\i[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000E000"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[0]\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \^rng_reg_0\,
      I3 => postNotLive_reg_n_0,
      I4 => \i__0\(0),
      O => \i[0]_i_1__1_n_0\
    );
\i[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F700FFFF"
    )
        port map (
      I0 => postNotLive_reg_n_0,
      I1 => \i__0\(1),
      I2 => \i__0\(0),
      I3 => \i[1]_i_3_n_0\,
      I4 => \col_lcl[8]__0_i_2_n_0\,
      O => \i[1]_i_1__4_n_0\
    );
\i[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000E000E0000000"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[0]\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \^rng_reg_0\,
      I3 => postNotLive_reg_n_0,
      I4 => \i__0\(1),
      I5 => \i__0\(0),
      O => \i[1]_i_2_n_0\
    );
\i[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000A800"
    )
        port map (
      I0 => \col_lcl[10]__0_i_3_n_0\,
      I1 => postNotLive_reg_n_0,
      I2 => ceMaxsel_reg_n_0,
      I3 => \stateMaxsel_reg_n_0_[0]\,
      I4 => \stateMaxsel_reg_n_0_[1]\,
      O => \i[1]_i_3_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[1]_i_1__4_n_0\,
      CLR => linNotLog_reg_0,
      D => \i[0]_i_1__1_n_0\,
      Q => \i__0\(0)
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[1]_i_1__4_n_0\,
      CLR => linNotLog_reg_0,
      D => \i[1]_i_2_n_0\,
      Q => \i__0\(1)
    );
\ixMax[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \ixMax[2]_i_7_n_0\,
      I1 => \ixMax[2]_i_6_n_0\,
      I2 => \ixMax[2]_i_2_n_0\,
      O => ixMax(0)
    );
\ixMax[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000557500000000"
    )
        port map (
      I0 => \ixMax[2]_i_2_n_0\,
      I1 => \ixMax[2]_i_3_n_0\,
      I2 => \ixMax[2]_i_4_n_0\,
      I3 => \ixMax[2]_i_5_n_0\,
      I4 => \ixMax[2]_i_6_n_0\,
      I5 => \ixMax[2]_i_7_n_0\,
      O => ixMax(1)
    );
\ixMax[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AA8A00000000"
    )
        port map (
      I0 => \ixMax[2]_i_2_n_0\,
      I1 => \ixMax[2]_i_3_n_0\,
      I2 => \ixMax[2]_i_4_n_0\,
      I3 => \ixMax[2]_i_5_n_0\,
      I4 => \ixMax[2]_i_6_n_0\,
      I5 => \ixMax[2]_i_7_n_0\,
      O => ixMax(2)
    );
\ixMax[2]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B0FB00F0"
    )
        port map (
      I0 => \maximds_reg_n_0_[1][6]\,
      I1 => \maximds_reg_n_0_[3][6]\,
      I2 => \maximds_reg_n_0_[1][7]\,
      I3 => \maximds_reg_n_0_[3][7]\,
      I4 => \ixMax[2]_i_20_n_0\,
      O => \ixMax[2]_i_10_n_0\
    );
\ixMax[2]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F04FF0F"
    )
        port map (
      I0 => \maximds_reg_n_0_[1][6]\,
      I1 => \maximds_reg_n_0_[2][6]\,
      I2 => \maximds_reg_n_0_[1][7]\,
      I3 => \maximds_reg_n_0_[2][7]\,
      I4 => \ixMax[2]_i_21_n_0\,
      O => \ixMax[2]_i_11_n_0\
    );
\ixMax[2]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[2][4]\,
      I1 => \maximds_reg_n_0_[4][4]\,
      I2 => \maximds_reg_n_0_[2][5]\,
      I3 => \maximds_reg_n_0_[4][5]\,
      I4 => \ixMax[2]_i_22_n_0\,
      I5 => \ixMax[2]_i_23_n_0\,
      O => \ixMax[2]_i_12_n_0\
    );
\ixMax[2]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[2][4]\,
      I1 => \maximds_reg_n_0_[3][4]\,
      I2 => \maximds_reg_n_0_[2][5]\,
      I3 => \maximds_reg_n_0_[3][5]\,
      I4 => \ixMax[2]_i_24_n_0\,
      I5 => \ixMax[2]_i_25_n_0\,
      O => \ixMax[2]_i_13_n_0\
    );
\ixMax[2]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][4]\,
      I1 => \maximds_reg_n_0_[2][4]\,
      I2 => \maximds_reg_n_0_[0][5]\,
      I3 => \maximds_reg_n_0_[2][5]\,
      I4 => \ixMax[2]_i_26_n_0\,
      I5 => \ixMax[2]_i_27_n_0\,
      O => \ixMax[2]_i_14_n_0\
    );
\ixMax[2]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F04FF0F"
    )
        port map (
      I0 => \maximds_reg_n_0_[1][6]\,
      I1 => \maximds_reg_n_0_[4][6]\,
      I2 => \maximds_reg_n_0_[1][7]\,
      I3 => \maximds_reg_n_0_[4][7]\,
      I4 => \ixMax[2]_i_28_n_0\,
      O => \ixMax[2]_i_15_n_0\
    );
\ixMax[2]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F04FF0F"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][6]\,
      I1 => \maximds_reg_n_0_[1][6]\,
      I2 => \maximds_reg_n_0_[0][7]\,
      I3 => \maximds_reg_n_0_[1][7]\,
      I4 => \ixMax[2]_i_29_n_0\,
      O => \ixMax[2]_i_16_n_0\
    );
\ixMax[2]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAFBBAFBFAFFBAFB"
    )
        port map (
      I0 => \ixMax[2]_i_8_n_0\,
      I1 => \ixMax[2]_i_30_n_0\,
      I2 => \maximds_reg_n_0_[4][7]\,
      I3 => \maximds_reg_n_0_[0][7]\,
      I4 => \maximds_reg_n_0_[4][6]\,
      I5 => \maximds_reg_n_0_[0][6]\,
      O => \ixMax[2]_i_17_n_0\
    );
\ixMax[2]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][4]\,
      I1 => \maximds_reg_n_0_[3][4]\,
      I2 => \maximds_reg_n_0_[0][5]\,
      I3 => \maximds_reg_n_0_[3][5]\,
      I4 => \ixMax[2]_i_31_n_0\,
      I5 => \ixMax[2]_i_32_n_0\,
      O => \ixMax[2]_i_18_n_0\
    );
\ixMax[2]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[3][4]\,
      I1 => \maximds_reg_n_0_[4][4]\,
      I2 => \maximds_reg_n_0_[3][5]\,
      I3 => \maximds_reg_n_0_[4][5]\,
      I4 => \ixMax[2]_i_33_n_0\,
      I5 => \ixMax[2]_i_34_n_0\,
      O => \ixMax[2]_i_19_n_0\
    );
\ixMax[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \ixMax[2]_i_8_n_0\,
      I1 => \ixMax[2]_i_9_n_0\,
      I2 => \ixMax[2]_i_4_n_0\,
      I3 => \ixMax[2]_i_10_n_0\,
      O => \ixMax[2]_i_2_n_0\
    );
\ixMax[2]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[1][4]\,
      I1 => \maximds_reg_n_0_[3][4]\,
      I2 => \maximds_reg_n_0_[1][5]\,
      I3 => \maximds_reg_n_0_[3][5]\,
      I4 => \ixMax[2]_i_35_n_0\,
      I5 => \ixMax[2]_i_36_n_0\,
      O => \ixMax[2]_i_20_n_0\
    );
\ixMax[2]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[1][4]\,
      I1 => \maximds_reg_n_0_[2][4]\,
      I2 => \maximds_reg_n_0_[1][5]\,
      I3 => \maximds_reg_n_0_[2][5]\,
      I4 => \ixMax[2]_i_37_n_0\,
      I5 => \ixMax[2]_i_38_n_0\,
      O => \ixMax[2]_i_21_n_0\
    );
\ixMax[2]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[2][2]\,
      I1 => \maximds_reg_n_0_[4][2]\,
      I2 => \maximds_reg_n_0_[2][3]\,
      I3 => \maximds_reg_n_0_[4][3]\,
      I4 => \ixMax[2]_i_39_n_0\,
      I5 => \ixMax[2]_i_40_n_0\,
      O => \ixMax[2]_i_22_n_0\
    );
\ixMax[2]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[4][6]\,
      I1 => \maximds_reg_n_0_[2][6]\,
      I2 => \maximds_reg_n_0_[4][5]\,
      I3 => \maximds_reg_n_0_[2][5]\,
      O => \ixMax[2]_i_23_n_0\
    );
\ixMax[2]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[2][3]\,
      I1 => \maximds_reg_n_0_[3][3]\,
      I2 => \maximds_reg_n_0_[2][2]\,
      I3 => \maximds_reg_n_0_[3][2]\,
      I4 => \ixMax[2]_i_41_n_0\,
      I5 => \ixMax[2]_i_42_n_0\,
      O => \ixMax[2]_i_24_n_0\
    );
\ixMax[2]_i_25\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[3][6]\,
      I1 => \maximds_reg_n_0_[2][6]\,
      I2 => \maximds_reg_n_0_[3][5]\,
      I3 => \maximds_reg_n_0_[2][5]\,
      O => \ixMax[2]_i_25_n_0\
    );
\ixMax[2]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][3]\,
      I1 => \maximds_reg_n_0_[2][3]\,
      I2 => \maximds_reg_n_0_[0][2]\,
      I3 => \maximds_reg_n_0_[2][2]\,
      I4 => \ixMax[2]_i_43_n_0\,
      I5 => \ixMax[2]_i_44_n_0\,
      O => \ixMax[2]_i_26_n_0\
    );
\ixMax[2]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[2][6]\,
      I1 => \maximds_reg_n_0_[0][6]\,
      I2 => \maximds_reg_n_0_[2][5]\,
      I3 => \maximds_reg_n_0_[0][5]\,
      O => \ixMax[2]_i_27_n_0\
    );
\ixMax[2]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[1][4]\,
      I1 => \maximds_reg_n_0_[4][4]\,
      I2 => \maximds_reg_n_0_[1][5]\,
      I3 => \maximds_reg_n_0_[4][5]\,
      I4 => \ixMax[2]_i_45_n_0\,
      I5 => \ixMax[2]_i_46_n_0\,
      O => \ixMax[2]_i_28_n_0\
    );
\ixMax[2]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][4]\,
      I1 => \maximds_reg_n_0_[1][4]\,
      I2 => \maximds_reg_n_0_[0][5]\,
      I3 => \maximds_reg_n_0_[1][5]\,
      I4 => \ixMax[2]_i_47_n_0\,
      I5 => \ixMax[2]_i_48_n_0\,
      O => \ixMax[2]_i_29_n_0\
    );
\ixMax[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5DDF5DDFDFDF5DDF"
    )
        port map (
      I0 => \ixMax[2]_i_11_n_0\,
      I1 => \maximds_reg_n_0_[4][7]\,
      I2 => \maximds_reg_n_0_[2][7]\,
      I3 => \ixMax[2]_i_12_n_0\,
      I4 => \maximds_reg_n_0_[4][6]\,
      I5 => \maximds_reg_n_0_[2][6]\,
      O => \ixMax[2]_i_3_n_0\
    );
\ixMax[2]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][5]\,
      I1 => \maximds_reg_n_0_[4][5]\,
      I2 => \maximds_reg_n_0_[0][4]\,
      I3 => \maximds_reg_n_0_[4][4]\,
      I4 => \ixMax[2]_i_49_n_0\,
      I5 => \ixMax[2]_i_50_n_0\,
      O => \ixMax[2]_i_30_n_0\
    );
\ixMax[2]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][2]\,
      I1 => \maximds_reg_n_0_[3][2]\,
      I2 => \maximds_reg_n_0_[0][3]\,
      I3 => \maximds_reg_n_0_[3][3]\,
      I4 => \ixMax[2]_i_51_n_0\,
      I5 => \ixMax[2]_i_52_n_0\,
      O => \ixMax[2]_i_31_n_0\
    );
\ixMax[2]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[3][6]\,
      I1 => \maximds_reg_n_0_[0][6]\,
      I2 => \maximds_reg_n_0_[3][5]\,
      I3 => \maximds_reg_n_0_[0][5]\,
      O => \ixMax[2]_i_32_n_0\
    );
\ixMax[2]_i_33\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[3][2]\,
      I1 => \maximds_reg_n_0_[4][2]\,
      I2 => \maximds_reg_n_0_[3][3]\,
      I3 => \maximds_reg_n_0_[4][3]\,
      I4 => \ixMax[2]_i_53_n_0\,
      I5 => \ixMax[2]_i_54_n_0\,
      O => \ixMax[2]_i_33_n_0\
    );
\ixMax[2]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[4][6]\,
      I1 => \maximds_reg_n_0_[3][6]\,
      I2 => \maximds_reg_n_0_[4][5]\,
      I3 => \maximds_reg_n_0_[3][5]\,
      O => \ixMax[2]_i_34_n_0\
    );
\ixMax[2]_i_35\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[1][3]\,
      I1 => \maximds_reg_n_0_[3][3]\,
      I2 => \maximds_reg_n_0_[1][2]\,
      I3 => \maximds_reg_n_0_[3][2]\,
      I4 => \ixMax[2]_i_55_n_0\,
      I5 => \ixMax[2]_i_56_n_0\,
      O => \ixMax[2]_i_35_n_0\
    );
\ixMax[2]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[3][6]\,
      I1 => \maximds_reg_n_0_[1][6]\,
      I2 => \maximds_reg_n_0_[3][5]\,
      I3 => \maximds_reg_n_0_[1][5]\,
      O => \ixMax[2]_i_36_n_0\
    );
\ixMax[2]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[1][3]\,
      I1 => \maximds_reg_n_0_[2][3]\,
      I2 => \maximds_reg_n_0_[1][2]\,
      I3 => \maximds_reg_n_0_[2][2]\,
      I4 => \ixMax[2]_i_57_n_0\,
      I5 => \ixMax[2]_i_58_n_0\,
      O => \ixMax[2]_i_37_n_0\
    );
\ixMax[2]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[2][6]\,
      I1 => \maximds_reg_n_0_[1][6]\,
      I2 => \maximds_reg_n_0_[2][5]\,
      I3 => \maximds_reg_n_0_[1][5]\,
      O => \ixMax[2]_i_38_n_0\
    );
\ixMax[2]_i_39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => \maximds_reg_n_0_[2][0]\,
      I1 => \maximds_reg_n_0_[4][0]\,
      I2 => \maximds_reg_n_0_[2][1]\,
      I3 => \maximds_reg_n_0_[4][1]\,
      I4 => \maximds_reg_n_0_[2][2]\,
      I5 => \maximds_reg_n_0_[4][2]\,
      O => \ixMax[2]_i_39_n_0\
    );
\ixMax[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B0FB00F0"
    )
        port map (
      I0 => \maximds_reg_n_0_[2][6]\,
      I1 => \maximds_reg_n_0_[3][6]\,
      I2 => \maximds_reg_n_0_[2][7]\,
      I3 => \maximds_reg_n_0_[3][7]\,
      I4 => \ixMax[2]_i_13_n_0\,
      O => \ixMax[2]_i_4_n_0\
    );
\ixMax[2]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[4][4]\,
      I1 => \maximds_reg_n_0_[2][4]\,
      I2 => \maximds_reg_n_0_[4][3]\,
      I3 => \maximds_reg_n_0_[2][3]\,
      O => \ixMax[2]_i_40_n_0\
    );
\ixMax[2]_i_41\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => \maximds_reg_n_0_[2][0]\,
      I1 => \maximds_reg_n_0_[3][0]\,
      I2 => \maximds_reg_n_0_[2][1]\,
      I3 => \maximds_reg_n_0_[3][1]\,
      I4 => \maximds_reg_n_0_[2][2]\,
      I5 => \maximds_reg_n_0_[3][2]\,
      O => \ixMax[2]_i_41_n_0\
    );
\ixMax[2]_i_42\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[3][4]\,
      I1 => \maximds_reg_n_0_[2][4]\,
      I2 => \maximds_reg_n_0_[3][3]\,
      I3 => \maximds_reg_n_0_[2][3]\,
      O => \ixMax[2]_i_42_n_0\
    );
\ixMax[2]_i_43\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][0]\,
      I1 => \maximds_reg_n_0_[2][0]\,
      I2 => \maximds_reg_n_0_[0][1]\,
      I3 => \maximds_reg_n_0_[2][1]\,
      I4 => \maximds_reg_n_0_[0][2]\,
      I5 => \maximds_reg_n_0_[2][2]\,
      O => \ixMax[2]_i_43_n_0\
    );
\ixMax[2]_i_44\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[2][4]\,
      I1 => \maximds_reg_n_0_[0][4]\,
      I2 => \maximds_reg_n_0_[2][3]\,
      I3 => \maximds_reg_n_0_[0][3]\,
      O => \ixMax[2]_i_44_n_0\
    );
\ixMax[2]_i_45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[1][2]\,
      I1 => \maximds_reg_n_0_[4][2]\,
      I2 => \maximds_reg_n_0_[1][3]\,
      I3 => \maximds_reg_n_0_[4][3]\,
      I4 => \ixMax[2]_i_59_n_0\,
      I5 => \ixMax[2]_i_60_n_0\,
      O => \ixMax[2]_i_45_n_0\
    );
\ixMax[2]_i_46\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[4][6]\,
      I1 => \maximds_reg_n_0_[1][6]\,
      I2 => \maximds_reg_n_0_[4][5]\,
      I3 => \maximds_reg_n_0_[1][5]\,
      O => \ixMax[2]_i_46_n_0\
    );
\ixMax[2]_i_47\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][3]\,
      I1 => \maximds_reg_n_0_[1][3]\,
      I2 => \maximds_reg_n_0_[0][2]\,
      I3 => \maximds_reg_n_0_[1][2]\,
      I4 => \ixMax[2]_i_61_n_0\,
      I5 => \ixMax[2]_i_62_n_0\,
      O => \ixMax[2]_i_47_n_0\
    );
\ixMax[2]_i_48\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[1][6]\,
      I1 => \maximds_reg_n_0_[0][6]\,
      I2 => \maximds_reg_n_0_[1][5]\,
      I3 => \maximds_reg_n_0_[0][5]\,
      O => \ixMax[2]_i_48_n_0\
    );
\ixMax[2]_i_49\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][3]\,
      I1 => \maximds_reg_n_0_[4][3]\,
      I2 => \maximds_reg_n_0_[0][2]\,
      I3 => \maximds_reg_n_0_[4][2]\,
      I4 => \ixMax[2]_i_63_n_0\,
      I5 => \ixMax[2]_i_64_n_0\,
      O => \ixMax[2]_i_49_n_0\
    );
\ixMax[2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B0FB00F0"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][6]\,
      I1 => \maximds_reg_n_0_[2][6]\,
      I2 => \maximds_reg_n_0_[0][7]\,
      I3 => \maximds_reg_n_0_[2][7]\,
      I4 => \ixMax[2]_i_14_n_0\,
      O => \ixMax[2]_i_5_n_0\
    );
\ixMax[2]_i_50\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[4][6]\,
      I1 => \maximds_reg_n_0_[0][6]\,
      I2 => \maximds_reg_n_0_[4][5]\,
      I3 => \maximds_reg_n_0_[0][5]\,
      O => \ixMax[2]_i_50_n_0\
    );
\ixMax[2]_i_51\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][0]\,
      I1 => \maximds_reg_n_0_[3][0]\,
      I2 => \maximds_reg_n_0_[0][1]\,
      I3 => \maximds_reg_n_0_[3][1]\,
      I4 => \maximds_reg_n_0_[0][2]\,
      I5 => \maximds_reg_n_0_[3][2]\,
      O => \ixMax[2]_i_51_n_0\
    );
\ixMax[2]_i_52\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[3][4]\,
      I1 => \maximds_reg_n_0_[0][4]\,
      I2 => \maximds_reg_n_0_[3][3]\,
      I3 => \maximds_reg_n_0_[0][3]\,
      O => \ixMax[2]_i_52_n_0\
    );
\ixMax[2]_i_53\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => \maximds_reg_n_0_[3][0]\,
      I1 => \maximds_reg_n_0_[4][0]\,
      I2 => \maximds_reg_n_0_[3][1]\,
      I3 => \maximds_reg_n_0_[4][1]\,
      I4 => \maximds_reg_n_0_[3][2]\,
      I5 => \maximds_reg_n_0_[4][2]\,
      O => \ixMax[2]_i_53_n_0\
    );
\ixMax[2]_i_54\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[4][4]\,
      I1 => \maximds_reg_n_0_[3][4]\,
      I2 => \maximds_reg_n_0_[4][3]\,
      I3 => \maximds_reg_n_0_[3][3]\,
      O => \ixMax[2]_i_54_n_0\
    );
\ixMax[2]_i_55\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => \maximds_reg_n_0_[1][0]\,
      I1 => \maximds_reg_n_0_[3][0]\,
      I2 => \maximds_reg_n_0_[1][1]\,
      I3 => \maximds_reg_n_0_[3][1]\,
      I4 => \maximds_reg_n_0_[1][2]\,
      I5 => \maximds_reg_n_0_[3][2]\,
      O => \ixMax[2]_i_55_n_0\
    );
\ixMax[2]_i_56\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[3][4]\,
      I1 => \maximds_reg_n_0_[1][4]\,
      I2 => \maximds_reg_n_0_[3][3]\,
      I3 => \maximds_reg_n_0_[1][3]\,
      O => \ixMax[2]_i_56_n_0\
    );
\ixMax[2]_i_57\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => \maximds_reg_n_0_[1][0]\,
      I1 => \maximds_reg_n_0_[2][0]\,
      I2 => \maximds_reg_n_0_[1][1]\,
      I3 => \maximds_reg_n_0_[2][1]\,
      I4 => \maximds_reg_n_0_[1][2]\,
      I5 => \maximds_reg_n_0_[2][2]\,
      O => \ixMax[2]_i_57_n_0\
    );
\ixMax[2]_i_58\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[2][4]\,
      I1 => \maximds_reg_n_0_[1][4]\,
      I2 => \maximds_reg_n_0_[2][3]\,
      I3 => \maximds_reg_n_0_[1][3]\,
      O => \ixMax[2]_i_58_n_0\
    );
\ixMax[2]_i_59\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => \maximds_reg_n_0_[1][0]\,
      I1 => \maximds_reg_n_0_[4][0]\,
      I2 => \maximds_reg_n_0_[1][1]\,
      I3 => \maximds_reg_n_0_[4][1]\,
      I4 => \maximds_reg_n_0_[1][2]\,
      I5 => \maximds_reg_n_0_[4][2]\,
      O => \ixMax[2]_i_59_n_0\
    );
\ixMax[2]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \ixMax[2]_i_15_n_0\,
      I1 => \ixMax[2]_i_10_n_0\,
      I2 => \ixMax[2]_i_16_n_0\,
      I3 => \ixMax[2]_i_11_n_0\,
      O => \ixMax[2]_i_6_n_0\
    );
\ixMax[2]_i_60\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[4][4]\,
      I1 => \maximds_reg_n_0_[1][4]\,
      I2 => \maximds_reg_n_0_[4][3]\,
      I3 => \maximds_reg_n_0_[1][3]\,
      O => \ixMax[2]_i_60_n_0\
    );
\ixMax[2]_i_61\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][0]\,
      I1 => \maximds_reg_n_0_[1][0]\,
      I2 => \maximds_reg_n_0_[0][1]\,
      I3 => \maximds_reg_n_0_[1][1]\,
      I4 => \maximds_reg_n_0_[0][2]\,
      I5 => \maximds_reg_n_0_[1][2]\,
      O => \ixMax[2]_i_61_n_0\
    );
\ixMax[2]_i_62\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[1][4]\,
      I1 => \maximds_reg_n_0_[0][4]\,
      I2 => \maximds_reg_n_0_[1][3]\,
      I3 => \maximds_reg_n_0_[0][3]\,
      O => \ixMax[2]_i_62_n_0\
    );
\ixMax[2]_i_63\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][0]\,
      I1 => \maximds_reg_n_0_[4][0]\,
      I2 => \maximds_reg_n_0_[0][1]\,
      I3 => \maximds_reg_n_0_[4][1]\,
      I4 => \maximds_reg_n_0_[0][2]\,
      I5 => \maximds_reg_n_0_[4][2]\,
      O => \ixMax[2]_i_63_n_0\
    );
\ixMax[2]_i_64\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \maximds_reg_n_0_[4][4]\,
      I1 => \maximds_reg_n_0_[0][4]\,
      I2 => \maximds_reg_n_0_[4][3]\,
      I3 => \maximds_reg_n_0_[0][3]\,
      O => \ixMax[2]_i_64_n_0\
    );
\ixMax[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4040404040004040"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[1]\,
      I1 => \^rng_reg_0\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => \ixMax[2]_i_17_n_0\,
      I4 => \ixMax[2]_i_5_n_0\,
      I5 => \ixMax[2]_i_16_n_0\,
      O => \ixMax[2]_i_7_n_0\
    );
\ixMax[2]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F04FF0F"
    )
        port map (
      I0 => \maximds_reg_n_0_[0][6]\,
      I1 => \maximds_reg_n_0_[3][6]\,
      I2 => \maximds_reg_n_0_[0][7]\,
      I3 => \maximds_reg_n_0_[3][7]\,
      I4 => \ixMax[2]_i_18_n_0\,
      O => \ixMax[2]_i_8_n_0\
    );
\ixMax[2]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F04FF0F"
    )
        port map (
      I0 => \maximds_reg_n_0_[3][6]\,
      I1 => \maximds_reg_n_0_[4][6]\,
      I2 => \maximds_reg_n_0_[3][7]\,
      I3 => \maximds_reg_n_0_[4][7]\,
      I4 => \ixMax[2]_i_19_n_0\,
      O => \ixMax[2]_i_9_n_0\
    );
\ixMax_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => colmax_lcl,
      CLR => linNotLog_reg_0,
      D => ixMax(0),
      Q => \ixMax_reg_n_0_[0]\
    );
\ixMax_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => colmax_lcl,
      CLR => linNotLog_reg_0,
      D => ixMax(1),
      Q => \ixMax_reg_n_0_[1]\
    );
\ixMax_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => colmax_lcl,
      CLR => linNotLog_reg_0,
      D => ixMax(2),
      Q => \ixMax_reg_n_0_[2]\
    );
\lat[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1F"
    )
        port map (
      I0 => stateCorner(1),
      I1 => stateCorner(0),
      I2 => \^rng_reg_0\,
      I3 => lat(4),
      O => \lat[4]_i_1_n_0\
    );
\lat_reg[4]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      D => \lat[4]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => lat(4)
    );
linNotLog_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => hdrNotFix,
      Q => linNotLog_reg_n_0
    );
\maximds[0][7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888888A"
    )
        port map (
      I0 => colmax_lcl,
      I1 => \row_lcl[10]_i_1_n_0\,
      I2 => \colmax_lcl_reg_n_0_[2]\,
      I3 => \colmax_lcl_reg_n_0_[1]\,
      I4 => \colmax_lcl_reg_n_0_[0]\,
      O => \maximds[0][7]_i_1_n_0\
    );
\maximds[1][7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888A88"
    )
        port map (
      I0 => colmax_lcl,
      I1 => \row_lcl[10]_i_1_n_0\,
      I2 => \colmax_lcl_reg_n_0_[1]\,
      I3 => \colmax_lcl_reg_n_0_[0]\,
      I4 => \colmax_lcl_reg_n_0_[2]\,
      O => \maximds[1][7]_i_1_n_0\
    );
\maximds[2][7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888888A8"
    )
        port map (
      I0 => colmax_lcl,
      I1 => \row_lcl[10]_i_1_n_0\,
      I2 => \colmax_lcl_reg_n_0_[1]\,
      I3 => \colmax_lcl_reg_n_0_[2]\,
      I4 => \colmax_lcl_reg_n_0_[0]\,
      O => \maximds[2][7]_i_1_n_0\
    );
\maximds[3][7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888A888"
    )
        port map (
      I0 => colmax_lcl,
      I1 => \row_lcl[10]_i_1_n_0\,
      I2 => \colmax_lcl_reg_n_0_[1]\,
      I3 => \colmax_lcl_reg_n_0_[0]\,
      I4 => \colmax_lcl_reg_n_0_[2]\,
      O => \maximds[3][7]_i_1_n_0\
    );
\maximds[4][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20AA2020AAAAAAAA"
    )
        port map (
      I0 => \maximds[4][7]_i_3_n_0\,
      I1 => \maximds[4][7]_i_4_n_0\,
      I2 => data1(0),
      I3 => \maximds[4][7]_i_5_n_0\,
      I4 => data0(0),
      I5 => \maximds[4][0]_i_2_n_0\,
      O => \maximds[0]_40\(0)
    );
\maximds[4][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF474700FF"
    )
        port map (
      I0 => \dImd_reg_n_0_[0]\,
      I1 => \maximds[4][7]_i_14_n_0\,
      I2 => data3(0),
      I3 => data2(0),
      I4 => \maximds[4][7]_i_15_n_0\,
      I5 => \maximds[4][7]_i_16_n_0\,
      O => \maximds[4][0]_i_2_n_0\
    );
\maximds[4][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20AA2020AAAAAAAA"
    )
        port map (
      I0 => \maximds[4][7]_i_3_n_0\,
      I1 => \maximds[4][7]_i_4_n_0\,
      I2 => data1(1),
      I3 => \maximds[4][7]_i_5_n_0\,
      I4 => data0(1),
      I5 => \maximds[4][1]_i_2_n_0\,
      O => \maximds[0]_40\(1)
    );
\maximds[4][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF474700FF"
    )
        port map (
      I0 => \dImd_reg_n_0_[1]\,
      I1 => \maximds[4][7]_i_14_n_0\,
      I2 => data3(1),
      I3 => data2(1),
      I4 => \maximds[4][7]_i_15_n_0\,
      I5 => \maximds[4][7]_i_16_n_0\,
      O => \maximds[4][1]_i_2_n_0\
    );
\maximds[4][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20AA2020AAAAAAAA"
    )
        port map (
      I0 => \maximds[4][7]_i_3_n_0\,
      I1 => \maximds[4][7]_i_4_n_0\,
      I2 => data1(2),
      I3 => \maximds[4][7]_i_5_n_0\,
      I4 => data0(2),
      I5 => \maximds[4][2]_i_2_n_0\,
      O => \maximds[0]_40\(2)
    );
\maximds[4][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF474700FF"
    )
        port map (
      I0 => \dImd_reg_n_0_[2]\,
      I1 => \maximds[4][7]_i_14_n_0\,
      I2 => data3(2),
      I3 => data2(2),
      I4 => \maximds[4][7]_i_15_n_0\,
      I5 => \maximds[4][7]_i_16_n_0\,
      O => \maximds[4][2]_i_2_n_0\
    );
\maximds[4][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20AA2020AAAAAAAA"
    )
        port map (
      I0 => \maximds[4][7]_i_3_n_0\,
      I1 => \maximds[4][7]_i_4_n_0\,
      I2 => data1(3),
      I3 => \maximds[4][7]_i_5_n_0\,
      I4 => data0(3),
      I5 => \maximds[4][3]_i_2_n_0\,
      O => \maximds[0]_40\(3)
    );
\maximds[4][3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF474700FF"
    )
        port map (
      I0 => \dImd_reg_n_0_[3]\,
      I1 => \maximds[4][7]_i_14_n_0\,
      I2 => data3(3),
      I3 => data2(3),
      I4 => \maximds[4][7]_i_15_n_0\,
      I5 => \maximds[4][7]_i_16_n_0\,
      O => \maximds[4][3]_i_2_n_0\
    );
\maximds[4][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20AA2020AAAAAAAA"
    )
        port map (
      I0 => \maximds[4][7]_i_3_n_0\,
      I1 => \maximds[4][7]_i_4_n_0\,
      I2 => data1(4),
      I3 => \maximds[4][7]_i_5_n_0\,
      I4 => data0(4),
      I5 => \maximds[4][4]_i_2_n_0\,
      O => \maximds[0]_40\(4)
    );
\maximds[4][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF474700FF"
    )
        port map (
      I0 => \dImd_reg_n_0_[4]\,
      I1 => \maximds[4][7]_i_14_n_0\,
      I2 => data3(4),
      I3 => data2(4),
      I4 => \maximds[4][7]_i_15_n_0\,
      I5 => \maximds[4][7]_i_16_n_0\,
      O => \maximds[4][4]_i_2_n_0\
    );
\maximds[4][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20AA2020AAAAAAAA"
    )
        port map (
      I0 => \maximds[4][7]_i_3_n_0\,
      I1 => \maximds[4][7]_i_4_n_0\,
      I2 => data1(5),
      I3 => \maximds[4][7]_i_5_n_0\,
      I4 => data0(5),
      I5 => \maximds[4][5]_i_2_n_0\,
      O => \maximds[0]_40\(5)
    );
\maximds[4][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF474700FF"
    )
        port map (
      I0 => \dImd_reg_n_0_[5]\,
      I1 => \maximds[4][7]_i_14_n_0\,
      I2 => data3(5),
      I3 => data2(5),
      I4 => \maximds[4][7]_i_15_n_0\,
      I5 => \maximds[4][7]_i_16_n_0\,
      O => \maximds[4][5]_i_2_n_0\
    );
\maximds[4][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20AA2020AAAAAAAA"
    )
        port map (
      I0 => \maximds[4][7]_i_3_n_0\,
      I1 => \maximds[4][7]_i_4_n_0\,
      I2 => data1(6),
      I3 => \maximds[4][7]_i_5_n_0\,
      I4 => data0(6),
      I5 => \maximds[4][6]_i_2_n_0\,
      O => \maximds[0]_40\(6)
    );
\maximds[4][6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF474700FF"
    )
        port map (
      I0 => \dImd_reg_n_0_[6]\,
      I1 => \maximds[4][7]_i_14_n_0\,
      I2 => data3(6),
      I3 => data2(6),
      I4 => \maximds[4][7]_i_15_n_0\,
      I5 => \maximds[4][7]_i_16_n_0\,
      O => \maximds[4][6]_i_2_n_0\
    );
\maximds[4][7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888888A8"
    )
        port map (
      I0 => colmax_lcl,
      I1 => \row_lcl[10]_i_1_n_0\,
      I2 => \colmax_lcl_reg_n_0_[2]\,
      I3 => \colmax_lcl_reg_n_0_[1]\,
      I4 => \colmax_lcl_reg_n_0_[0]\,
      O => \maximds[4][7]_i_1_n_0\
    );
\maximds[4][7]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F04FF0F"
    )
        port map (
      I0 => data1(6),
      I1 => data3(6),
      I2 => data1(7),
      I3 => data3(7),
      I4 => \maximds[4][7]_i_20_n_0\,
      O => \maximds[4][7]_i_10_n_0\
    );
\maximds[4][7]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B0FB00F0"
    )
        port map (
      I0 => data0(6),
      I1 => data3(6),
      I2 => data0(7),
      I3 => data3(7),
      I4 => \maximds[4][7]_i_21_n_0\,
      O => \maximds[4][7]_i_11_n_0\
    );
\maximds[4][7]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F04FF0F"
    )
        port map (
      I0 => data0(6),
      I1 => \dImd_reg_n_0_[6]\,
      I2 => data0(7),
      I3 => \dImd_reg_n_0_[7]\,
      I4 => \maximds[4][7]_i_22_n_0\,
      O => \maximds[4][7]_i_12_n_0\
    );
\maximds[4][7]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F04FF0F"
    )
        port map (
      I0 => data0(6),
      I1 => data2(6),
      I2 => data0(7),
      I3 => data2(7),
      I4 => \maximds[4][7]_i_23_n_0\,
      O => \maximds[4][7]_i_13_n_0\
    );
\maximds[4][7]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => \maximds[4][7]_i_24_n_0\,
      I1 => \maximds[4][7]_i_10_n_0\,
      I2 => \maximds[4][7]_i_25_n_0\,
      I3 => \maximds[4][7]_i_11_n_0\,
      O => \maximds[4][7]_i_14_n_0\
    );
\maximds[4][7]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \maximds[4][7]_i_25_n_0\,
      I1 => \maximds[4][7]_i_8_n_0\,
      I2 => \maximds[4][7]_i_26_n_0\,
      I3 => \maximds[4][7]_i_13_n_0\,
      O => \maximds[4][7]_i_15_n_0\
    );
\maximds[4][7]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \maximds[4][7]_i_5_n_0\,
      I1 => \maximds[4][7]_i_4_n_0\,
      O => \maximds[4][7]_i_16_n_0\
    );
\maximds[4][7]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data0(4),
      I1 => data1(4),
      I2 => data0(5),
      I3 => data1(5),
      I4 => \maximds[4][7]_i_27_n_0\,
      I5 => \maximds[4][7]_i_28_n_0\,
      O => \maximds[4][7]_i_17_n_0\
    );
\maximds[4][7]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data1(4),
      I1 => data2(4),
      I2 => data1(5),
      I3 => data2(5),
      I4 => \maximds[4][7]_i_29_n_0\,
      I5 => \maximds[4][7]_i_30_n_0\,
      O => \maximds[4][7]_i_18_n_0\
    );
\maximds[4][7]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data1(4),
      I1 => \dImd_reg_n_0_[4]\,
      I2 => data1(5),
      I3 => \dImd_reg_n_0_[5]\,
      I4 => \maximds[4][7]_i_31_n_0\,
      I5 => \maximds[4][7]_i_32_n_0\,
      O => \maximds[4][7]_i_19_n_0\
    );
\maximds[4][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20AA2020AAAAAAAA"
    )
        port map (
      I0 => \maximds[4][7]_i_3_n_0\,
      I1 => \maximds[4][7]_i_4_n_0\,
      I2 => data1(7),
      I3 => \maximds[4][7]_i_5_n_0\,
      I4 => data0(7),
      I5 => \maximds[4][7]_i_6_n_0\,
      O => \maximds[0]_40\(7)
    );
\maximds[4][7]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data1(4),
      I1 => data3(4),
      I2 => data1(5),
      I3 => data3(5),
      I4 => \maximds[4][7]_i_33_n_0\,
      I5 => \maximds[4][7]_i_34_n_0\,
      O => \maximds[4][7]_i_20_n_0\
    );
\maximds[4][7]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data0(4),
      I1 => data3(4),
      I2 => data0(5),
      I3 => data3(5),
      I4 => \maximds[4][7]_i_35_n_0\,
      I5 => \maximds[4][7]_i_36_n_0\,
      O => \maximds[4][7]_i_21_n_0\
    );
\maximds[4][7]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data0(4),
      I1 => \dImd_reg_n_0_[4]\,
      I2 => data0(5),
      I3 => \dImd_reg_n_0_[5]\,
      I4 => \maximds[4][7]_i_37_n_0\,
      I5 => \maximds[4][7]_i_38_n_0\,
      O => \maximds[4][7]_i_22_n_0\
    );
\maximds[4][7]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data0(4),
      I1 => data2(4),
      I2 => data0(5),
      I3 => data2(5),
      I4 => \maximds[4][7]_i_39_n_0\,
      I5 => \maximds[4][7]_i_40_n_0\,
      O => \maximds[4][7]_i_23_n_0\
    );
\maximds[4][7]_i_24\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B000FFB0"
    )
        port map (
      I0 => data3(6),
      I1 => \dImd_reg_n_0_[6]\,
      I2 => \maximds[4][7]_i_41_n_0\,
      I3 => data3(7),
      I4 => \dImd_reg_n_0_[7]\,
      O => \maximds[4][7]_i_24_n_0\
    );
\maximds[4][7]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F04FF0F"
    )
        port map (
      I0 => data2(6),
      I1 => data3(6),
      I2 => data2(7),
      I3 => data3(7),
      I4 => \maximds[4][7]_i_42_n_0\,
      O => \maximds[4][7]_i_25_n_0\
    );
\maximds[4][7]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B000FFB0"
    )
        port map (
      I0 => data2(6),
      I1 => \dImd_reg_n_0_[6]\,
      I2 => \maximds[4][7]_i_43_n_0\,
      I3 => data2(7),
      I4 => \dImd_reg_n_0_[7]\,
      O => \maximds[4][7]_i_26_n_0\
    );
\maximds[4][7]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data0(3),
      I1 => data1(3),
      I2 => data0(2),
      I3 => data1(2),
      I4 => \maximds[4][7]_i_44_n_0\,
      I5 => \maximds[4][7]_i_45_n_0\,
      O => \maximds[4][7]_i_27_n_0\
    );
\maximds[4][7]_i_28\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => data1(6),
      I1 => data0(6),
      I2 => data1(5),
      I3 => data0(5),
      O => \maximds[4][7]_i_28_n_0\
    );
\maximds[4][7]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data1(2),
      I1 => data2(2),
      I2 => data1(3),
      I3 => data2(3),
      I4 => \maximds[4][7]_i_46_n_0\,
      I5 => \maximds[4][7]_i_47_n_0\,
      O => \maximds[4][7]_i_29_n_0\
    );
\maximds[4][7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[0]\,
      I1 => \^rng_reg_0\,
      I2 => \stateMaxsel_reg_n_0_[1]\,
      O => \maximds[4][7]_i_3_n_0\
    );
\maximds[4][7]_i_30\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => data2(6),
      I1 => data1(6),
      I2 => data2(5),
      I3 => data1(5),
      O => \maximds[4][7]_i_30_n_0\
    );
\maximds[4][7]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data1(2),
      I1 => \dImd_reg_n_0_[2]\,
      I2 => data1(3),
      I3 => \dImd_reg_n_0_[3]\,
      I4 => \maximds[4][7]_i_48_n_0\,
      I5 => \maximds[4][7]_i_49_n_0\,
      O => \maximds[4][7]_i_31_n_0\
    );
\maximds[4][7]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \dImd_reg_n_0_[6]\,
      I1 => data1(6),
      I2 => \dImd_reg_n_0_[5]\,
      I3 => data1(5),
      O => \maximds[4][7]_i_32_n_0\
    );
\maximds[4][7]_i_33\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data1(2),
      I1 => data3(2),
      I2 => data1(3),
      I3 => data3(3),
      I4 => \maximds[4][7]_i_50_n_0\,
      I5 => \maximds[4][7]_i_51_n_0\,
      O => \maximds[4][7]_i_33_n_0\
    );
\maximds[4][7]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => data3(6),
      I1 => data1(6),
      I2 => data3(5),
      I3 => data1(5),
      O => \maximds[4][7]_i_34_n_0\
    );
\maximds[4][7]_i_35\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data0(2),
      I1 => data3(2),
      I2 => data0(3),
      I3 => data3(3),
      I4 => \maximds[4][7]_i_52_n_0\,
      I5 => \maximds[4][7]_i_53_n_0\,
      O => \maximds[4][7]_i_35_n_0\
    );
\maximds[4][7]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => data3(6),
      I1 => data0(6),
      I2 => data3(5),
      I3 => data0(5),
      O => \maximds[4][7]_i_36_n_0\
    );
\maximds[4][7]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data0(3),
      I1 => \dImd_reg_n_0_[3]\,
      I2 => data0(2),
      I3 => \dImd_reg_n_0_[2]\,
      I4 => \maximds[4][7]_i_54_n_0\,
      I5 => \maximds[4][7]_i_55_n_0\,
      O => \maximds[4][7]_i_37_n_0\
    );
\maximds[4][7]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \dImd_reg_n_0_[6]\,
      I1 => data0(6),
      I2 => \dImd_reg_n_0_[5]\,
      I3 => data0(5),
      O => \maximds[4][7]_i_38_n_0\
    );
\maximds[4][7]_i_39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data0(3),
      I1 => data2(3),
      I2 => data0(2),
      I3 => data2(2),
      I4 => \maximds[4][7]_i_56_n_0\,
      I5 => \maximds[4][7]_i_57_n_0\,
      O => \maximds[4][7]_i_39_n_0\
    );
\maximds[4][7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => \maximds[4][7]_i_7_n_0\,
      I1 => \maximds[4][7]_i_8_n_0\,
      I2 => \maximds[4][7]_i_9_n_0\,
      I3 => \maximds[4][7]_i_10_n_0\,
      O => \maximds[4][7]_i_4_n_0\
    );
\maximds[4][7]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => data2(6),
      I1 => data0(6),
      I2 => data2(5),
      I3 => data0(5),
      O => \maximds[4][7]_i_40_n_0\
    );
\maximds[4][7]_i_41\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data3(4),
      I1 => \dImd_reg_n_0_[4]\,
      I2 => data3(5),
      I3 => \dImd_reg_n_0_[5]\,
      I4 => \maximds[4][7]_i_58_n_0\,
      I5 => \maximds[4][7]_i_59_n_0\,
      O => \maximds[4][7]_i_41_n_0\
    );
\maximds[4][7]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data2(4),
      I1 => data3(4),
      I2 => data2(5),
      I3 => data3(5),
      I4 => \maximds[4][7]_i_60_n_0\,
      I5 => \maximds[4][7]_i_61_n_0\,
      O => \maximds[4][7]_i_42_n_0\
    );
\maximds[4][7]_i_43\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data2(4),
      I1 => \dImd_reg_n_0_[4]\,
      I2 => data2(5),
      I3 => \dImd_reg_n_0_[5]\,
      I4 => \maximds[4][7]_i_62_n_0\,
      I5 => \maximds[4][7]_i_63_n_0\,
      O => \maximds[4][7]_i_43_n_0\
    );
\maximds[4][7]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => data0(0),
      I1 => data1(0),
      I2 => data0(1),
      I3 => data1(1),
      I4 => data0(2),
      I5 => data1(2),
      O => \maximds[4][7]_i_44_n_0\
    );
\maximds[4][7]_i_45\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => data1(4),
      I1 => data0(4),
      I2 => data1(3),
      I3 => data0(3),
      O => \maximds[4][7]_i_45_n_0\
    );
\maximds[4][7]_i_46\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => data1(0),
      I1 => data2(0),
      I2 => data1(1),
      I3 => data2(1),
      I4 => data1(2),
      I5 => data2(2),
      O => \maximds[4][7]_i_46_n_0\
    );
\maximds[4][7]_i_47\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => data2(4),
      I1 => data1(4),
      I2 => data2(3),
      I3 => data1(3),
      O => \maximds[4][7]_i_47_n_0\
    );
\maximds[4][7]_i_48\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => data1(0),
      I1 => \dImd_reg_n_0_[0]\,
      I2 => data1(1),
      I3 => \dImd_reg_n_0_[1]\,
      I4 => data1(2),
      I5 => \dImd_reg_n_0_[2]\,
      O => \maximds[4][7]_i_48_n_0\
    );
\maximds[4][7]_i_49\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \dImd_reg_n_0_[4]\,
      I1 => data1(4),
      I2 => \dImd_reg_n_0_[3]\,
      I3 => data1(3),
      O => \maximds[4][7]_i_49_n_0\
    );
\maximds[4][7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \maximds[4][7]_i_11_n_0\,
      I1 => \maximds[4][7]_i_7_n_0\,
      I2 => \maximds[4][7]_i_12_n_0\,
      I3 => \maximds[4][7]_i_13_n_0\,
      O => \maximds[4][7]_i_5_n_0\
    );
\maximds[4][7]_i_50\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => data1(0),
      I1 => data3(0),
      I2 => data1(1),
      I3 => data3(1),
      I4 => data1(2),
      I5 => data3(2),
      O => \maximds[4][7]_i_50_n_0\
    );
\maximds[4][7]_i_51\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => data3(4),
      I1 => data1(4),
      I2 => data3(3),
      I3 => data1(3),
      O => \maximds[4][7]_i_51_n_0\
    );
\maximds[4][7]_i_52\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => data0(0),
      I1 => data3(0),
      I2 => data0(1),
      I3 => data3(1),
      I4 => data0(2),
      I5 => data3(2),
      O => \maximds[4][7]_i_52_n_0\
    );
\maximds[4][7]_i_53\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => data3(4),
      I1 => data0(4),
      I2 => data3(3),
      I3 => data0(3),
      O => \maximds[4][7]_i_53_n_0\
    );
\maximds[4][7]_i_54\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => data0(0),
      I1 => \dImd_reg_n_0_[0]\,
      I2 => data0(1),
      I3 => \dImd_reg_n_0_[1]\,
      I4 => data0(2),
      I5 => \dImd_reg_n_0_[2]\,
      O => \maximds[4][7]_i_54_n_0\
    );
\maximds[4][7]_i_55\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \dImd_reg_n_0_[4]\,
      I1 => data0(4),
      I2 => \dImd_reg_n_0_[3]\,
      I3 => data0(3),
      O => \maximds[4][7]_i_55_n_0\
    );
\maximds[4][7]_i_56\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => data0(0),
      I1 => data2(0),
      I2 => data0(1),
      I3 => data2(1),
      I4 => data0(2),
      I5 => data2(2),
      O => \maximds[4][7]_i_56_n_0\
    );
\maximds[4][7]_i_57\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => data2(4),
      I1 => data0(4),
      I2 => data2(3),
      I3 => data0(3),
      O => \maximds[4][7]_i_57_n_0\
    );
\maximds[4][7]_i_58\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data3(3),
      I1 => \dImd_reg_n_0_[3]\,
      I2 => data3(2),
      I3 => \dImd_reg_n_0_[2]\,
      I4 => \maximds[4][7]_i_64_n_0\,
      I5 => \maximds[4][7]_i_65_n_0\,
      O => \maximds[4][7]_i_58_n_0\
    );
\maximds[4][7]_i_59\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \dImd_reg_n_0_[6]\,
      I1 => data3(6),
      I2 => \dImd_reg_n_0_[5]\,
      I3 => data3(5),
      O => \maximds[4][7]_i_59_n_0\
    );
\maximds[4][7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF474700FF"
    )
        port map (
      I0 => \dImd_reg_n_0_[7]\,
      I1 => \maximds[4][7]_i_14_n_0\,
      I2 => data3(7),
      I3 => data2(7),
      I4 => \maximds[4][7]_i_15_n_0\,
      I5 => \maximds[4][7]_i_16_n_0\,
      O => \maximds[4][7]_i_6_n_0\
    );
\maximds[4][7]_i_60\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data2(3),
      I1 => data3(3),
      I2 => data2(2),
      I3 => data3(2),
      I4 => \maximds[4][7]_i_66_n_0\,
      I5 => \maximds[4][7]_i_67_n_0\,
      O => \maximds[4][7]_i_60_n_0\
    );
\maximds[4][7]_i_61\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => data3(6),
      I1 => data2(6),
      I2 => data3(5),
      I3 => data2(5),
      O => \maximds[4][7]_i_61_n_0\
    );
\maximds[4][7]_i_62\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0BB0000"
    )
        port map (
      I0 => data2(2),
      I1 => \dImd_reg_n_0_[2]\,
      I2 => data2(3),
      I3 => \dImd_reg_n_0_[3]\,
      I4 => \maximds[4][7]_i_68_n_0\,
      I5 => \maximds[4][7]_i_69_n_0\,
      O => \maximds[4][7]_i_62_n_0\
    );
\maximds[4][7]_i_63\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \dImd_reg_n_0_[6]\,
      I1 => data2(6),
      I2 => \dImd_reg_n_0_[5]\,
      I3 => data2(5),
      O => \maximds[4][7]_i_63_n_0\
    );
\maximds[4][7]_i_64\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => data3(0),
      I1 => \dImd_reg_n_0_[0]\,
      I2 => data3(1),
      I3 => \dImd_reg_n_0_[1]\,
      I4 => data3(2),
      I5 => \dImd_reg_n_0_[2]\,
      O => \maximds[4][7]_i_64_n_0\
    );
\maximds[4][7]_i_65\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \dImd_reg_n_0_[4]\,
      I1 => data3(4),
      I2 => \dImd_reg_n_0_[3]\,
      I3 => data3(3),
      O => \maximds[4][7]_i_65_n_0\
    );
\maximds[4][7]_i_66\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => data2(0),
      I1 => data3(0),
      I2 => data2(1),
      I3 => data3(1),
      I4 => data2(2),
      I5 => data3(2),
      O => \maximds[4][7]_i_66_n_0\
    );
\maximds[4][7]_i_67\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => data3(4),
      I1 => data2(4),
      I2 => data3(3),
      I3 => data2(3),
      O => \maximds[4][7]_i_67_n_0\
    );
\maximds[4][7]_i_68\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0FBB0FBFFFFB0FB"
    )
        port map (
      I0 => data2(0),
      I1 => \dImd_reg_n_0_[0]\,
      I2 => data2(1),
      I3 => \dImd_reg_n_0_[1]\,
      I4 => data2(2),
      I5 => \dImd_reg_n_0_[2]\,
      O => \maximds[4][7]_i_68_n_0\
    );
\maximds[4][7]_i_69\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \dImd_reg_n_0_[4]\,
      I1 => data2(4),
      I2 => \dImd_reg_n_0_[3]\,
      I3 => data2(3),
      O => \maximds[4][7]_i_69_n_0\
    );
\maximds[4][7]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F04FF0F"
    )
        port map (
      I0 => data0(6),
      I1 => data1(6),
      I2 => data0(7),
      I3 => data1(7),
      I4 => \maximds[4][7]_i_17_n_0\,
      O => \maximds[4][7]_i_7_n_0\
    );
\maximds[4][7]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B0FB00F0"
    )
        port map (
      I0 => data1(6),
      I1 => data2(6),
      I2 => data1(7),
      I3 => data2(7),
      I4 => \maximds[4][7]_i_18_n_0\,
      O => \maximds[4][7]_i_8_n_0\
    );
\maximds[4][7]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F04FF0F"
    )
        port map (
      I0 => data1(6),
      I1 => \dImd_reg_n_0_[6]\,
      I2 => data1(7),
      I3 => \dImd_reg_n_0_[7]\,
      I4 => \maximds[4][7]_i_19_n_0\,
      O => \maximds[4][7]_i_9_n_0\
    );
\maximds_reg[0][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[0][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(0),
      Q => \maximds_reg_n_0_[0][0]\
    );
\maximds_reg[0][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[0][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(1),
      Q => \maximds_reg_n_0_[0][1]\
    );
\maximds_reg[0][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[0][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(2),
      Q => \maximds_reg_n_0_[0][2]\
    );
\maximds_reg[0][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[0][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(3),
      Q => \maximds_reg_n_0_[0][3]\
    );
\maximds_reg[0][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[0][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(4),
      Q => \maximds_reg_n_0_[0][4]\
    );
\maximds_reg[0][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[0][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(5),
      Q => \maximds_reg_n_0_[0][5]\
    );
\maximds_reg[0][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[0][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(6),
      Q => \maximds_reg_n_0_[0][6]\
    );
\maximds_reg[0][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[0][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(7),
      Q => \maximds_reg_n_0_[0][7]\
    );
\maximds_reg[1][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[1][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(0),
      Q => \maximds_reg_n_0_[1][0]\
    );
\maximds_reg[1][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[1][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(1),
      Q => \maximds_reg_n_0_[1][1]\
    );
\maximds_reg[1][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[1][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(2),
      Q => \maximds_reg_n_0_[1][2]\
    );
\maximds_reg[1][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[1][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(3),
      Q => \maximds_reg_n_0_[1][3]\
    );
\maximds_reg[1][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[1][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(4),
      Q => \maximds_reg_n_0_[1][4]\
    );
\maximds_reg[1][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[1][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(5),
      Q => \maximds_reg_n_0_[1][5]\
    );
\maximds_reg[1][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[1][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(6),
      Q => \maximds_reg_n_0_[1][6]\
    );
\maximds_reg[1][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[1][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(7),
      Q => \maximds_reg_n_0_[1][7]\
    );
\maximds_reg[2][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[2][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(0),
      Q => \maximds_reg_n_0_[2][0]\
    );
\maximds_reg[2][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[2][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(1),
      Q => \maximds_reg_n_0_[2][1]\
    );
\maximds_reg[2][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[2][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(2),
      Q => \maximds_reg_n_0_[2][2]\
    );
\maximds_reg[2][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[2][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(3),
      Q => \maximds_reg_n_0_[2][3]\
    );
\maximds_reg[2][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[2][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(4),
      Q => \maximds_reg_n_0_[2][4]\
    );
\maximds_reg[2][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[2][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(5),
      Q => \maximds_reg_n_0_[2][5]\
    );
\maximds_reg[2][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[2][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(6),
      Q => \maximds_reg_n_0_[2][6]\
    );
\maximds_reg[2][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[2][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(7),
      Q => \maximds_reg_n_0_[2][7]\
    );
\maximds_reg[3][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[3][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(0),
      Q => \maximds_reg_n_0_[3][0]\
    );
\maximds_reg[3][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[3][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(1),
      Q => \maximds_reg_n_0_[3][1]\
    );
\maximds_reg[3][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[3][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(2),
      Q => \maximds_reg_n_0_[3][2]\
    );
\maximds_reg[3][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[3][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(3),
      Q => \maximds_reg_n_0_[3][3]\
    );
\maximds_reg[3][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[3][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(4),
      Q => \maximds_reg_n_0_[3][4]\
    );
\maximds_reg[3][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[3][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(5),
      Q => \maximds_reg_n_0_[3][5]\
    );
\maximds_reg[3][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[3][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(6),
      Q => \maximds_reg_n_0_[3][6]\
    );
\maximds_reg[3][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[3][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(7),
      Q => \maximds_reg_n_0_[3][7]\
    );
\maximds_reg[4][0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[4][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(0),
      Q => \maximds_reg_n_0_[4][0]\
    );
\maximds_reg[4][1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[4][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(1),
      Q => \maximds_reg_n_0_[4][1]\
    );
\maximds_reg[4][2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[4][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(2),
      Q => \maximds_reg_n_0_[4][2]\
    );
\maximds_reg[4][3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[4][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(3),
      Q => \maximds_reg_n_0_[4][3]\
    );
\maximds_reg[4][4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[4][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(4),
      Q => \maximds_reg_n_0_[4][4]\
    );
\maximds_reg[4][5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[4][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(5),
      Q => \maximds_reg_n_0_[4][5]\
    );
\maximds_reg[4][6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[4][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(6),
      Q => \maximds_reg_n_0_[4][6]\
    );
\maximds_reg[4][7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \maximds[4][7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \maximds[0]_40\(7),
      Q => \maximds_reg_n_0_[4][7]\
    );
\maximdsm1[1][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000020202000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => ceMaxsel_reg_n_0,
      I4 => postNotLive_reg_n_0,
      I5 => linNotLog_reg_0,
      O => \maximdsm1_reg[0]0\
    );
\maximdsm1_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[0][0]\,
      Q => \maximdsm1_reg[0]_36\(0),
      R => '0'
    );
\maximdsm1_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[0][1]\,
      Q => \maximdsm1_reg[0]_36\(1),
      R => '0'
    );
\maximdsm1_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[0][2]\,
      Q => \maximdsm1_reg[0]_36\(2),
      R => '0'
    );
\maximdsm1_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[0][3]\,
      Q => \maximdsm1_reg[0]_36\(3),
      R => '0'
    );
\maximdsm1_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[0][4]\,
      Q => \maximdsm1_reg[0]_36\(4),
      R => '0'
    );
\maximdsm1_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[0][5]\,
      Q => \maximdsm1_reg[0]_36\(5),
      R => '0'
    );
\maximdsm1_reg[0][6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[0][6]\,
      Q => \maximdsm1_reg[0]_36\(6),
      R => '0'
    );
\maximdsm1_reg[0][7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[0][7]\,
      Q => \maximdsm1_reg[0]_36\(7),
      R => '0'
    );
\maximdsm1_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[1][0]\,
      Q => \maximdsm1_reg[1]_35\(0),
      R => '0'
    );
\maximdsm1_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[1][1]\,
      Q => \maximdsm1_reg[1]_35\(1),
      R => '0'
    );
\maximdsm1_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[1][2]\,
      Q => \maximdsm1_reg[1]_35\(2),
      R => '0'
    );
\maximdsm1_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[1][3]\,
      Q => \maximdsm1_reg[1]_35\(3),
      R => '0'
    );
\maximdsm1_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[1][4]\,
      Q => \maximdsm1_reg[1]_35\(4),
      R => '0'
    );
\maximdsm1_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[1][5]\,
      Q => \maximdsm1_reg[1]_35\(5),
      R => '0'
    );
\maximdsm1_reg[1][6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[1][6]\,
      Q => \maximdsm1_reg[1]_35\(6),
      R => '0'
    );
\maximdsm1_reg[1][7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[1][7]\,
      Q => \maximdsm1_reg[1]_35\(7),
      R => '0'
    );
\maximdsm1_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[2][0]\,
      Q => \maximdsm1_reg[2]_39\(0),
      R => '0'
    );
\maximdsm1_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[2][1]\,
      Q => \maximdsm1_reg[2]_39\(1),
      R => '0'
    );
\maximdsm1_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[2][2]\,
      Q => \maximdsm1_reg[2]_39\(2),
      R => '0'
    );
\maximdsm1_reg[2][3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[2][3]\,
      Q => \maximdsm1_reg[2]_39\(3),
      R => '0'
    );
\maximdsm1_reg[2][4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[2][4]\,
      Q => \maximdsm1_reg[2]_39\(4),
      R => '0'
    );
\maximdsm1_reg[2][5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[2][5]\,
      Q => \maximdsm1_reg[2]_39\(5),
      R => '0'
    );
\maximdsm1_reg[2][6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[2][6]\,
      Q => \maximdsm1_reg[2]_39\(6),
      R => '0'
    );
\maximdsm1_reg[2][7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[2][7]\,
      Q => \maximdsm1_reg[2]_39\(7),
      R => '0'
    );
\maximdsm1_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[3][0]\,
      Q => \maximdsm1_reg[3]_38\(0),
      R => '0'
    );
\maximdsm1_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[3][1]\,
      Q => \maximdsm1_reg[3]_38\(1),
      R => '0'
    );
\maximdsm1_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[3][2]\,
      Q => \maximdsm1_reg[3]_38\(2),
      R => '0'
    );
\maximdsm1_reg[3][3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[3][3]\,
      Q => \maximdsm1_reg[3]_38\(3),
      R => '0'
    );
\maximdsm1_reg[3][4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[3][4]\,
      Q => \maximdsm1_reg[3]_38\(4),
      R => '0'
    );
\maximdsm1_reg[3][5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[3][5]\,
      Q => \maximdsm1_reg[3]_38\(5),
      R => '0'
    );
\maximdsm1_reg[3][6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[3][6]\,
      Q => \maximdsm1_reg[3]_38\(6),
      R => '0'
    );
\maximdsm1_reg[3][7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[3][7]\,
      Q => \maximdsm1_reg[3]_38\(7),
      R => '0'
    );
\maximdsm1_reg[4][0]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[4][0]\,
      Q => \maximdsm1_reg[4]_37\(0),
      R => '0'
    );
\maximdsm1_reg[4][1]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[4][1]\,
      Q => \maximdsm1_reg[4]_37\(1),
      R => '0'
    );
\maximdsm1_reg[4][2]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[4][2]\,
      Q => \maximdsm1_reg[4]_37\(2),
      R => '0'
    );
\maximdsm1_reg[4][3]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[4][3]\,
      Q => \maximdsm1_reg[4]_37\(3),
      R => '0'
    );
\maximdsm1_reg[4][4]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[4][4]\,
      Q => \maximdsm1_reg[4]_37\(4),
      R => '0'
    );
\maximdsm1_reg[4][5]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[4][5]\,
      Q => \maximdsm1_reg[4]_37\(5),
      R => '0'
    );
\maximdsm1_reg[4][6]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[4][6]\,
      Q => \maximdsm1_reg[4]_37\(6),
      R => '0'
    );
\maximdsm1_reg[4][7]\: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => \maximdsm1_reg[0]0\,
      D => \maximds_reg_n_0_[4][7]\,
      Q => \maximdsm1_reg[4]_37\(7),
      R => '0'
    );
\msb[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAFB"
    )
        port map (
      I0 => \msb[0]_i_2_n_0\,
      I1 => \msb[0]_i_3_n_0\,
      I2 => \msb[0]_i_4_n_0\,
      I3 => \msb[2]_i_7_n_0\,
      O => \msb[0]_i_1_n_0\
    );
\msb[0]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \msb[3]_i_12_n_0\,
      I1 => \r_reg_n_0_[37]\,
      I2 => \r_reg_n_0_[36]\,
      I3 => \r_reg_n_0_[35]\,
      O => \msb[0]_i_10_n_0\
    );
\msb[0]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"45444545"
    )
        port map (
      I0 => \r_reg_n_0_[31]\,
      I1 => \r_reg_n_0_[30]\,
      I2 => \r_reg_n_0_[29]\,
      I3 => \r_reg_n_0_[28]\,
      I4 => \r_reg_n_0_[27]\,
      O => \msb[0]_i_11_n_0\
    );
\msb[0]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFDFFFF"
    )
        port map (
      I0 => \msb[3]_i_12_n_0\,
      I1 => \r_reg_n_0_[37]\,
      I2 => \r_reg_n_0_[36]\,
      I3 => \r_reg_n_0_[35]\,
      I4 => \msb[3]_i_11_n_0\,
      O => \msb[0]_i_12_n_0\
    );
\msb[0]_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"55F7"
    )
        port map (
      I0 => \msb[4]_i_5_n_0\,
      I1 => msb(0),
      I2 => \r_reg_n_0_[0]\,
      I3 => \r_reg_n_0_[1]\,
      O => \msb[0]_i_13_n_0\
    );
\msb[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBABABABB"
    )
        port map (
      I0 => \r_reg_n_0_[47]\,
      I1 => \r_reg_n_0_[46]\,
      I2 => \r_reg_n_0_[45]\,
      I3 => \r_reg_n_0_[44]\,
      I4 => \msb[0]_i_5_n_0\,
      I5 => \msb[0]_i_6_n_0\,
      O => \msb[0]_i_2_n_0\
    );
\msb[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF4F4F0FF"
    )
        port map (
      I0 => \r_reg_n_0_[15]\,
      I1 => \msb[0]_i_7_n_0\,
      I2 => \msb[2]_i_5_n_0\,
      I3 => \msb[0]_i_8_n_0\,
      I4 => \msb[4]_i_3_n_0\,
      I5 => \r_reg_n_0_[16]\,
      O => \msb[0]_i_3_n_0\
    );
\msb[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0F04"
    )
        port map (
      I0 => \r_reg_n_0_[22]\,
      I1 => \msb[0]_i_9_n_0\,
      I2 => \r_reg_n_0_[24]\,
      I3 => \r_reg_n_0_[23]\,
      I4 => \r_reg_n_0_[25]\,
      O => \msb[0]_i_4_n_0\
    );
\msb[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000F000F0B"
    )
        port map (
      I0 => \r_reg_n_0_[40]\,
      I1 => \r_reg_n_0_[39]\,
      I2 => \r_reg_n_0_[43]\,
      I3 => \r_reg_n_0_[42]\,
      I4 => \r_reg_n_0_[41]\,
      I5 => \msb[0]_i_10_n_0\,
      O => \msb[0]_i_5_n_0\
    );
\msb[0]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00005501"
    )
        port map (
      I0 => \r_reg_n_0_[34]\,
      I1 => \r_reg_n_0_[32]\,
      I2 => \msb[0]_i_11_n_0\,
      I3 => \r_reg_n_0_[33]\,
      I4 => \msb[0]_i_12_n_0\,
      O => \msb[0]_i_6_n_0\
    );
\msb[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABABABABBBABBBB"
    )
        port map (
      I0 => \r_reg_n_0_[14]\,
      I1 => \r_reg_n_0_[13]\,
      I2 => \r_reg_n_0_[12]\,
      I3 => \r_reg_n_0_[10]\,
      I4 => \r_reg_n_0_[9]\,
      I5 => \r_reg_n_0_[11]\,
      O => \msb[0]_i_7_n_0\
    );
\msb[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0FFFFFFF0FFF4F"
    )
        port map (
      I0 => \r_reg_n_0_[4]\,
      I1 => \r_reg_n_0_[3]\,
      I2 => \msb[0]_i_13_n_0\,
      I3 => \r_reg_n_0_[7]\,
      I4 => \r_reg_n_0_[6]\,
      I5 => \r_reg_n_0_[5]\,
      O => \msb[0]_i_8_n_0\
    );
\msb[0]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAEFEE"
    )
        port map (
      I0 => \r_reg_n_0_[21]\,
      I1 => \r_reg_n_0_[19]\,
      I2 => \r_reg_n_0_[18]\,
      I3 => \r_reg_n_0_[17]\,
      I4 => \r_reg_n_0_[20]\,
      O => \msb[0]_i_9_n_0\
    );
\msb[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFB0BFB0BFBFBFB0"
    )
        port map (
      I0 => \msb[1]_i_2_n_0\,
      I1 => \msb[1]_i_3_n_0\,
      I2 => \msb[2]_i_7_n_0\,
      I3 => \msb[1]_i_4_n_0\,
      I4 => \msb[1]_i_5_n_0\,
      I5 => \msb[1]_i_6_n_0\,
      O => \msb[1]_i_1_n_0\
    );
\msb[1]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000FB"
    )
        port map (
      I0 => \r_reg_n_0_[36]\,
      I1 => \r_reg_n_0_[35]\,
      I2 => \r_reg_n_0_[37]\,
      I3 => \r_reg_n_0_[39]\,
      I4 => \r_reg_n_0_[38]\,
      O => \msb[1]_i_10_n_0\
    );
\msb[1]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000FD"
    )
        port map (
      I0 => msb(1),
      I1 => \r_reg_n_0_[0]\,
      I2 => \r_reg_n_0_[1]\,
      I3 => \r_reg_n_0_[3]\,
      I4 => \r_reg_n_0_[2]\,
      O => \msb[1]_i_11_n_0\
    );
\msb[1]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \r_reg_n_0_[6]\,
      I1 => \r_reg_n_0_[7]\,
      O => \msb[1]_i_12_n_0\
    );
\msb[1]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FFF1"
    )
        port map (
      I0 => \r_reg_n_0_[8]\,
      I1 => \r_reg_n_0_[9]\,
      I2 => \r_reg_n_0_[10]\,
      I3 => \r_reg_n_0_[11]\,
      I4 => \r_reg_n_0_[13]\,
      I5 => \r_reg_n_0_[12]\,
      O => \msb[1]_i_13_n_0\
    );
\msb[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F200000000000000"
    )
        port map (
      I0 => \msb[3]_i_13_n_0\,
      I1 => \msb[1]_i_7_n_0\,
      I2 => \r_reg_n_0_[34]\,
      I3 => \msb[3]_i_11_n_0\,
      I4 => \msb[1]_i_8_n_0\,
      I5 => \msb[3]_i_12_n_0\,
      O => \msb[1]_i_2_n_0\
    );
\msb[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000101011111111"
    )
        port map (
      I0 => \r_reg_n_0_[47]\,
      I1 => \r_reg_n_0_[46]\,
      I2 => \msb[1]_i_9_n_0\,
      I3 => \msb[1]_i_10_n_0\,
      I4 => \msb[2]_i_8_n_0\,
      I5 => \msb[3]_i_11_n_0\,
      O => \msb[1]_i_3_n_0\
    );
\msb[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFF54"
    )
        port map (
      I0 => \msb[2]_i_12_n_0\,
      I1 => \r_reg_n_0_[19]\,
      I2 => \r_reg_n_0_[18]\,
      I3 => \r_reg_n_0_[22]\,
      I4 => \r_reg_n_0_[23]\,
      I5 => \msb[3]_i_2_n_0\,
      O => \msb[1]_i_4_n_0\
    );
\msb[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF4FF"
    )
        port map (
      I0 => \msb[1]_i_11_n_0\,
      I1 => \msb[2]_i_13_n_0\,
      I2 => \r_reg_n_0_[16]\,
      I3 => \msb[3]_i_9_n_0\,
      I4 => \msb[3]_i_10_n_0\,
      I5 => \msb[1]_i_12_n_0\,
      O => \msb[1]_i_5_n_0\
    );
\msb[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFEFEFEFEFF"
    )
        port map (
      I0 => \msb[2]_i_11_n_0\,
      I1 => \msb[3]_i_8_n_0\,
      I2 => \r_reg_n_0_[16]\,
      I3 => \msb[1]_i_13_n_0\,
      I4 => \r_reg_n_0_[14]\,
      I5 => \r_reg_n_0_[15]\,
      O => \msb[1]_i_6_n_0\
    );
\msb[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1110111011101111"
    )
        port map (
      I0 => \r_reg_n_0_[31]\,
      I1 => \r_reg_n_0_[30]\,
      I2 => \r_reg_n_0_[28]\,
      I3 => \r_reg_n_0_[29]\,
      I4 => \r_reg_n_0_[26]\,
      I5 => \r_reg_n_0_[27]\,
      O => \msb[1]_i_7_n_0\
    );
\msb[1]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \r_reg_n_0_[37]\,
      I1 => \r_reg_n_0_[36]\,
      I2 => \r_reg_n_0_[35]\,
      O => \msb[1]_i_8_n_0\
    );
\msb[1]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \r_reg_n_0_[42]\,
      I1 => \r_reg_n_0_[43]\,
      O => \msb[1]_i_9_n_0\
    );
\msb[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEFEEEFFF"
    )
        port map (
      I0 => \msb[2]_i_2_n_0\,
      I1 => \msb[2]_i_3_n_0\,
      I2 => \msb[2]_i_4_n_0\,
      I3 => \msb[2]_i_5_n_0\,
      I4 => \msb[2]_i_6_n_0\,
      I5 => \msb[2]_i_7_n_0\,
      O => \msb[2]_i_1_n_0\
    );
\msb[2]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \r_reg_n_0_[31]\,
      I1 => \r_reg_n_0_[30]\,
      I2 => \r_reg_n_0_[29]\,
      I3 => \r_reg_n_0_[28]\,
      O => \msb[2]_i_10_n_0\
    );
\msb[2]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \r_reg_n_0_[23]\,
      I1 => \r_reg_n_0_[25]\,
      I2 => \r_reg_n_0_[24]\,
      O => \msb[2]_i_11_n_0\
    );
\msb[2]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \r_reg_n_0_[20]\,
      I1 => \r_reg_n_0_[21]\,
      O => \msb[2]_i_12_n_0\
    );
\msb[2]_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \r_reg_n_0_[6]\,
      I1 => \r_reg_n_0_[7]\,
      I2 => \r_reg_n_0_[5]\,
      I3 => \r_reg_n_0_[4]\,
      O => \msb[2]_i_13_n_0\
    );
\msb[2]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \r_reg_n_0_[2]\,
      I1 => \r_reg_n_0_[3]\,
      I2 => \r_reg_n_0_[4]\,
      I3 => msb(2),
      I4 => \r_reg_n_0_[0]\,
      I5 => \r_reg_n_0_[1]\,
      O => \msb[2]_i_14_n_0\
    );
\msb[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFE0000FFFFFFFF"
    )
        port map (
      I0 => \r_reg_n_0_[37]\,
      I1 => \r_reg_n_0_[36]\,
      I2 => \r_reg_n_0_[39]\,
      I3 => \r_reg_n_0_[38]\,
      I4 => \msb[2]_i_8_n_0\,
      I5 => \msb[3]_i_11_n_0\,
      O => \msb[2]_i_2_n_0\
    );
\msb[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000800000"
    )
        port map (
      I0 => \msb[3]_i_13_n_0\,
      I1 => \msb[3]_i_12_n_0\,
      I2 => \msb[2]_i_9_n_0\,
      I3 => \r_reg_n_0_[35]\,
      I4 => \msb[3]_i_11_n_0\,
      I5 => \msb[2]_i_10_n_0\,
      O => \msb[2]_i_3_n_0\
    );
\msb[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEEEEEEEF"
    )
        port map (
      I0 => \r_reg_n_0_[25]\,
      I1 => \r_reg_n_0_[24]\,
      I2 => \r_reg_n_0_[22]\,
      I3 => \r_reg_n_0_[23]\,
      I4 => \r_reg_n_0_[20]\,
      I5 => \r_reg_n_0_[21]\,
      O => \msb[2]_i_4_n_0\
    );
\msb[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \msb[2]_i_11_n_0\,
      I1 => \r_reg_n_0_[19]\,
      I2 => \r_reg_n_0_[18]\,
      I3 => \r_reg_n_0_[22]\,
      I4 => \r_reg_n_0_[17]\,
      I5 => \msb[2]_i_12_n_0\,
      O => \msb[2]_i_5_n_0\
    );
\msb[2]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF200"
    )
        port map (
      I0 => \msb[2]_i_13_n_0\,
      I1 => \msb[2]_i_14_n_0\,
      I2 => \msb[3]_i_10_n_0\,
      I3 => \msb[3]_i_9_n_0\,
      I4 => \r_reg_n_0_[16]\,
      O => \msb[2]_i_6_n_0\
    );
\msb[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF7FFFFF"
    )
        port map (
      I0 => \msb[3]_i_13_n_0\,
      I1 => \msb[3]_i_12_n_0\,
      I2 => \msb[2]_i_9_n_0\,
      I3 => \r_reg_n_0_[35]\,
      I4 => \msb[3]_i_11_n_0\,
      I5 => \msb[3]_i_5_n_0\,
      O => \msb[2]_i_7_n_0\
    );
\msb[2]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \r_reg_n_0_[40]\,
      I1 => \r_reg_n_0_[42]\,
      I2 => \r_reg_n_0_[43]\,
      I3 => \r_reg_n_0_[41]\,
      O => \msb[2]_i_8_n_0\
    );
\msb[2]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \r_reg_n_0_[36]\,
      I1 => \r_reg_n_0_[37]\,
      O => \msb[2]_i_9_n_0\
    );
\msb[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000FFBAFFBA"
    )
        port map (
      I0 => \msb[3]_i_2_n_0\,
      I1 => \msb[3]_i_3_n_0\,
      I2 => \msb[3]_i_4_n_0\,
      I3 => \msb[3]_i_5_n_0\,
      I4 => \msb[3]_i_6_n_0\,
      I5 => \msb[3]_i_7_n_0\,
      O => \msb[3]_i_1_n_0\
    );
\msb[3]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \r_reg_n_0_[9]\,
      I1 => \r_reg_n_0_[8]\,
      I2 => \r_reg_n_0_[11]\,
      I3 => \r_reg_n_0_[10]\,
      O => \msb[3]_i_10_n_0\
    );
\msb[3]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \r_reg_n_0_[47]\,
      I1 => \r_reg_n_0_[46]\,
      I2 => \r_reg_n_0_[45]\,
      I3 => \r_reg_n_0_[44]\,
      O => \msb[3]_i_11_n_0\
    );
\msb[3]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \r_reg_n_0_[38]\,
      I1 => \r_reg_n_0_[39]\,
      I2 => \r_reg_n_0_[40]\,
      I3 => \r_reg_n_0_[42]\,
      I4 => \r_reg_n_0_[43]\,
      I5 => \r_reg_n_0_[41]\,
      O => \msb[3]_i_12_n_0\
    );
\msb[3]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \r_reg_n_0_[33]\,
      I1 => \r_reg_n_0_[34]\,
      I2 => \r_reg_n_0_[32]\,
      O => \msb[3]_i_13_n_0\
    );
\msb[3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \r_reg_n_0_[24]\,
      I1 => \r_reg_n_0_[25]\,
      O => \msb[3]_i_2_n_0\
    );
\msb[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \r_reg_n_0_[16]\,
      I1 => \msb[3]_i_8_n_0\,
      I2 => \r_reg_n_0_[23]\,
      I3 => \r_reg_n_0_[25]\,
      I4 => \r_reg_n_0_[24]\,
      O => \msb[3]_i_3_n_0\
    );
\msb[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDFDDDDDDDDDDDD"
    )
        port map (
      I0 => \msb[3]_i_9_n_0\,
      I1 => \msb[3]_i_10_n_0\,
      I2 => \r_reg_n_0_[1]\,
      I3 => \r_reg_n_0_[0]\,
      I4 => msb(3),
      I5 => \msb[4]_i_5_n_0\,
      O => \msb[3]_i_4_n_0\
    );
\msb[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \r_reg_n_0_[27]\,
      I1 => \r_reg_n_0_[26]\,
      I2 => \r_reg_n_0_[28]\,
      I3 => \r_reg_n_0_[29]\,
      I4 => \r_reg_n_0_[30]\,
      I5 => \r_reg_n_0_[31]\,
      O => \msb[3]_i_5_n_0\
    );
\msb[3]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFD"
    )
        port map (
      I0 => \msb[3]_i_11_n_0\,
      I1 => \r_reg_n_0_[41]\,
      I2 => \r_reg_n_0_[43]\,
      I3 => \r_reg_n_0_[42]\,
      I4 => \r_reg_n_0_[40]\,
      O => \msb[3]_i_6_n_0\
    );
\msb[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFDFFFFFFFFFFFF"
    )
        port map (
      I0 => \msb[3]_i_11_n_0\,
      I1 => \r_reg_n_0_[35]\,
      I2 => \r_reg_n_0_[36]\,
      I3 => \r_reg_n_0_[37]\,
      I4 => \msb[3]_i_12_n_0\,
      I5 => \msb[3]_i_13_n_0\,
      O => \msb[3]_i_7_n_0\
    );
\msb[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \r_reg_n_0_[21]\,
      I1 => \r_reg_n_0_[20]\,
      I2 => \r_reg_n_0_[17]\,
      I3 => \r_reg_n_0_[22]\,
      I4 => \r_reg_n_0_[18]\,
      I5 => \r_reg_n_0_[19]\,
      O => \msb[3]_i_8_n_0\
    );
\msb[3]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \r_reg_n_0_[15]\,
      I1 => \r_reg_n_0_[14]\,
      I2 => \r_reg_n_0_[13]\,
      I3 => \r_reg_n_0_[12]\,
      O => \msb[3]_i_9_n_0\
    );
\msb[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \msb[4]_i_2_n_0\,
      O => \msb[4]_i_1_n_0\
    );
\msb[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAABBBABBBB"
    )
        port map (
      I0 => \msb[3]_i_7_n_0\,
      I1 => \msb[3]_i_5_n_0\,
      I2 => \msb[4]_i_3_n_0\,
      I3 => \msb[4]_i_4_n_0\,
      I4 => \msb[4]_i_5_n_0\,
      I5 => \msb[3]_i_3_n_0\,
      O => \msb[4]_i_2_n_0\
    );
\msb[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \r_reg_n_0_[10]\,
      I1 => \r_reg_n_0_[11]\,
      I2 => \r_reg_n_0_[8]\,
      I3 => \r_reg_n_0_[9]\,
      I4 => \msb[3]_i_9_n_0\,
      O => \msb[4]_i_3_n_0\
    );
\msb[4]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \r_reg_n_0_[1]\,
      I1 => \r_reg_n_0_[0]\,
      I2 => msb(4),
      O => \msb[4]_i_4_n_0\
    );
\msb[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \r_reg_n_0_[6]\,
      I1 => \r_reg_n_0_[7]\,
      I2 => \r_reg_n_0_[5]\,
      I3 => \r_reg_n_0_[2]\,
      I4 => \r_reg_n_0_[3]\,
      I5 => \r_reg_n_0_[4]\,
      O => \msb[4]_i_5_n_0\
    );
\msb[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => ceScore,
      I2 => linNotLog_reg_0,
      O => msb0
    );
\msb[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \msb[5]_i_3_n_0\,
      O => \msb[5]_i_2_n_0\
    );
\msb[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5455"
    )
        port map (
      I0 => \msb[3]_i_7_n_0\,
      I1 => \msb[5]_i_4_n_0\,
      I2 => \msb[2]_i_5_n_0\,
      I3 => \msb[5]_i_5_n_0\,
      O => \msb[5]_i_3_n_0\
    );
\msb[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFB"
    )
        port map (
      I0 => \r_reg_n_0_[16]\,
      I1 => \msb[3]_i_9_n_0\,
      I2 => \r_reg_n_0_[9]\,
      I3 => \r_reg_n_0_[8]\,
      I4 => \r_reg_n_0_[11]\,
      I5 => \r_reg_n_0_[10]\,
      O => \msb[5]_i_4_n_0\
    );
\msb[5]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => \r_reg_n_0_[1]\,
      I1 => \r_reg_n_0_[0]\,
      I2 => msb(5),
      I3 => \msb[4]_i_5_n_0\,
      I4 => \msb[3]_i_5_n_0\,
      O => \msb[5]_i_5_n_0\
    );
\msb_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => msb0,
      D => \msb[0]_i_1_n_0\,
      Q => msb(0),
      R => '0'
    );
\msb_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => msb0,
      D => \msb[1]_i_1_n_0\,
      Q => msb(1),
      R => '0'
    );
\msb_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => msb0,
      D => \msb[2]_i_1_n_0\,
      Q => msb(2),
      R => '0'
    );
\msb_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => msb0,
      D => \msb[3]_i_1_n_0\,
      Q => msb(3),
      R => '0'
    );
\msb_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => msb0,
      D => \msb[4]_i_1_n_0\,
      Q => msb(4),
      R => '0'
    );
\msb_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => msb0,
      D => \msb[5]_i_2_n_0\,
      Q => msb(5),
      R => '0'
    );
myCoobuf: entity work.design_1_Vsp_core_0_0_Dpbram_size2kB_a32b64
     port map (
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(22) => \dwrCoobuf_reg_n_0_[31]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(21) => \dwrCoobuf_reg_n_0_[26]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(20) => \dwrCoobuf_reg_n_0_[25]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(19) => \dwrCoobuf_reg_n_0_[24]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(18) => \dwrCoobuf_reg_n_0_[23]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(17) => \dwrCoobuf_reg_n_0_[22]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(16) => \dwrCoobuf_reg_n_0_[21]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(15) => \dwrCoobuf_reg_n_0_[20]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(14) => \dwrCoobuf_reg_n_0_[19]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(13) => \dwrCoobuf_reg_n_0_[18]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(12) => \dwrCoobuf_reg_n_0_[17]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(11) => \dwrCoobuf_reg_n_0_[16]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(10) => \dwrCoobuf_reg_n_0_[10]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(9) => \dwrCoobuf_reg_n_0_[9]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(8) => \dwrCoobuf_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \dwrCoobuf_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \dwrCoobuf_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \dwrCoobuf_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \dwrCoobuf_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \dwrCoobuf_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \dwrCoobuf_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \dwrCoobuf_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \dwrCoobuf_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => enCoobufB,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \aCoobufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \aCoobufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \aCoobufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \aCoobufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \aCoobufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \aCoobufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \aCoobufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \aCoobufB_reg_n_0_[0]\,
      Q(8 downto 0) => aCoobuf_reg(8 downto 0),
      aclk_sig => aclk_sig,
      doutb(63 downto 0) => doutb(63 downto 0),
      ena => enCoobuf_reg_n_0
    );
myImd0buf: entity work.\design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__1\
     port map (
      D(7) => myImd0buf_n_8,
      D(6) => myImd0buf_n_9,
      D(5) => myImd0buf_n_10,
      D(4) => myImd0buf_n_11,
      D(3) => myImd0buf_n_12,
      D(2) => myImd0buf_n_13,
      D(1) => myImd0buf_n_14,
      D(0) => myImd0buf_n_15,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(7) => \rexp_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(6) => \rexp_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(5) => \rexp_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(4) => \rexp_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(3) => \rexp_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(2) => \rexp_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(1) => \rexp_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(0) => \rexp_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\ => enImdbuf_reg_n_0,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(10) => \aImdbufB_reg_n_0_[10]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(9) => \aImdbufB_reg_n_0_[9]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(8) => \aImdbufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(7) => \aImdbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(6) => \aImdbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(5) => \aImdbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(4) => \aImdbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(3) => \aImdbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(2) => \aImdbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(1) => \aImdbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(0) => \aImdbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\ => myImd1buf_n_16,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_3\ => myImd1buf_n_17,
      Q(10) => \aImdbuf_reg_n_0_[10]\,
      Q(9) => \aImdbuf_reg_n_0_[9]\,
      Q(8) => \aImdbuf_reg_n_0_[8]\,
      Q(7) => \aImdbuf_reg_n_0_[7]\,
      Q(6) => \aImdbuf_reg_n_0_[6]\,
      Q(5) => \aImdbuf_reg_n_0_[5]\,
      Q(4) => \aImdbuf_reg_n_0_[4]\,
      Q(3) => \aImdbuf_reg_n_0_[3]\,
      Q(2) => \aImdbuf_reg_n_0_[2]\,
      Q(1) => \aImdbuf_reg_n_0_[1]\,
      Q(0) => \aImdbuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      \dImd_reg[39]\(2 downto 0) => fghij(2 downto 0),
      \dImd_reg[39]_0\(7 downto 0) => drdImd1bufB(7 downto 0),
      \dImd_reg[39]_1\ => \stateImdstream[0]_i_3_n_0\,
      \dImd_reg[39]_2\(7 downto 0) => drdImd4bufB(7 downto 0),
      \dImd_reg[39]_3\(7 downto 0) => drdImd3bufB(7 downto 0),
      \dImd_reg[39]_4\(7 downto 0) => drdImd2bufB(7 downto 0),
      doutb(7 downto 0) => drdImd0bufB(7 downto 0)
    );
myImd1buf: entity work.\design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__2\
     port map (
      D(7) => myImd1buf_n_8,
      D(6) => myImd1buf_n_9,
      D(5) => myImd1buf_n_10,
      D(4) => myImd1buf_n_11,
      D(3) => myImd1buf_n_12,
      D(2) => myImd1buf_n_13,
      D(1) => myImd1buf_n_14,
      D(0) => myImd1buf_n_15,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(7) => \rexp_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(6) => \rexp_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(5) => \rexp_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(4) => \rexp_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(3) => \rexp_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(2) => \rexp_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(1) => \rexp_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(0) => \rexp_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\ => enImdbuf_reg_n_0,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(10) => \aImdbufB_reg_n_0_[10]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(9) => \aImdbufB_reg_n_0_[9]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(8) => \aImdbufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(7) => \aImdbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(6) => \aImdbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(5) => \aImdbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(4) => \aImdbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(3) => \aImdbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(2) => \aImdbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(1) => \aImdbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(0) => \aImdbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\(30 downto 0) => fghij(30 downto 0),
      Q(10) => \aImdbuf_reg_n_0_[10]\,
      Q(9) => \aImdbuf_reg_n_0_[9]\,
      Q(8) => \aImdbuf_reg_n_0_[8]\,
      Q(7) => \aImdbuf_reg_n_0_[7]\,
      Q(6) => \aImdbuf_reg_n_0_[6]\,
      Q(5) => \aImdbuf_reg_n_0_[5]\,
      Q(4) => \aImdbuf_reg_n_0_[4]\,
      Q(3) => \aImdbuf_reg_n_0_[3]\,
      Q(2) => \aImdbuf_reg_n_0_[2]\,
      Q(1) => \aImdbuf_reg_n_0_[1]\,
      Q(0) => \aImdbuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      \dImd_reg[31]\(7 downto 0) => drdImd2bufB(7 downto 0),
      \dImd_reg[31]_0\ => \stateImdstream[0]_i_3_n_0\,
      \dImd_reg[31]_1\(7 downto 0) => drdImd0bufB(7 downto 0),
      \dImd_reg[31]_2\(7 downto 0) => drdImd4bufB(7 downto 0),
      \dImd_reg[31]_3\(7 downto 0) => drdImd3bufB(7 downto 0),
      doutb(7 downto 0) => drdImd1bufB(7 downto 0),
      \fghij_reg[11]\ => myImd1buf_n_16,
      \fghij_reg[11]_0\ => myImd1buf_n_18,
      \fghij_reg[13]\ => myImd1buf_n_19,
      \fghij_reg[30]\ => myImd1buf_n_17
    );
myImd2buf: entity work.\design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__3\
     port map (
      D(7) => myImd2buf_n_8,
      D(6) => myImd2buf_n_9,
      D(5) => myImd2buf_n_10,
      D(4) => myImd2buf_n_11,
      D(3) => myImd2buf_n_12,
      D(2) => myImd2buf_n_13,
      D(1) => myImd2buf_n_14,
      D(0) => myImd2buf_n_15,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(7) => \rexp_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(6) => \rexp_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(5) => \rexp_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(4) => \rexp_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(3) => \rexp_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(2) => \rexp_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(1) => \rexp_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(0) => \rexp_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\ => enImdbuf_reg_n_0,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(10) => \aImdbufB_reg_n_0_[10]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(9) => \aImdbufB_reg_n_0_[9]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(8) => \aImdbufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(7) => \aImdbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(6) => \aImdbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(5) => \aImdbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(4) => \aImdbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(3) => \aImdbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(2) => \aImdbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(1) => \aImdbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(0) => \aImdbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\ => myImd1buf_n_16,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_3\ => myImd1buf_n_17,
      Q(10) => \aImdbuf_reg_n_0_[10]\,
      Q(9) => \aImdbuf_reg_n_0_[9]\,
      Q(8) => \aImdbuf_reg_n_0_[8]\,
      Q(7) => \aImdbuf_reg_n_0_[7]\,
      Q(6) => \aImdbuf_reg_n_0_[6]\,
      Q(5) => \aImdbuf_reg_n_0_[5]\,
      Q(4) => \aImdbuf_reg_n_0_[4]\,
      Q(3) => \aImdbuf_reg_n_0_[3]\,
      Q(2) => \aImdbuf_reg_n_0_[2]\,
      Q(1) => \aImdbuf_reg_n_0_[1]\,
      Q(0) => \aImdbuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      \dImd_reg[23]\(2 downto 0) => fghij(2 downto 0),
      \dImd_reg[23]_0\(7 downto 0) => drdImd3bufB(7 downto 0),
      \dImd_reg[23]_1\ => \stateImdstream[0]_i_3_n_0\,
      \dImd_reg[23]_2\(7 downto 0) => drdImd1bufB(7 downto 0),
      \dImd_reg[23]_3\(7 downto 0) => drdImd0bufB(7 downto 0),
      \dImd_reg[23]_4\(7 downto 0) => drdImd4bufB(7 downto 0),
      doutb(7 downto 0) => drdImd2bufB(7 downto 0)
    );
myImd3buf: entity work.\design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8__xdcDup__4\
     port map (
      D(7) => myImd3buf_n_8,
      D(6) => myImd3buf_n_9,
      D(5) => myImd3buf_n_10,
      D(4) => myImd3buf_n_11,
      D(3) => myImd3buf_n_12,
      D(2) => myImd3buf_n_13,
      D(1) => myImd3buf_n_14,
      D(0) => myImd3buf_n_15,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(7) => \rexp_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(6) => \rexp_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(5) => \rexp_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(4) => \rexp_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(3) => \rexp_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(2) => \rexp_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(1) => \rexp_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(0) => \rexp_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\ => enImdbuf_reg_n_0,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(10) => \aImdbufB_reg_n_0_[10]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(9) => \aImdbufB_reg_n_0_[9]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(8) => \aImdbufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(7) => \aImdbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(6) => \aImdbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(5) => \aImdbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(4) => \aImdbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(3) => \aImdbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(2) => \aImdbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(1) => \aImdbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(0) => \aImdbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\ => myImd1buf_n_16,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_3\ => myImd1buf_n_17,
      Q(10) => \aImdbuf_reg_n_0_[10]\,
      Q(9) => \aImdbuf_reg_n_0_[9]\,
      Q(8) => \aImdbuf_reg_n_0_[8]\,
      Q(7) => \aImdbuf_reg_n_0_[7]\,
      Q(6) => \aImdbuf_reg_n_0_[6]\,
      Q(5) => \aImdbuf_reg_n_0_[5]\,
      Q(4) => \aImdbuf_reg_n_0_[4]\,
      Q(3) => \aImdbuf_reg_n_0_[3]\,
      Q(2) => \aImdbuf_reg_n_0_[2]\,
      Q(1) => \aImdbuf_reg_n_0_[1]\,
      Q(0) => \aImdbuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      \dImd_reg[15]\(2 downto 0) => fghij(2 downto 0),
      \dImd_reg[15]_0\(7 downto 0) => drdImd4bufB(7 downto 0),
      \dImd_reg[15]_1\ => \stateImdstream[0]_i_3_n_0\,
      \dImd_reg[15]_2\(7 downto 0) => drdImd2bufB(7 downto 0),
      \dImd_reg[15]_3\(7 downto 0) => drdImd1bufB(7 downto 0),
      \dImd_reg[15]_4\(7 downto 0) => drdImd0bufB(7 downto 0),
      doutb(7 downto 0) => drdImd3bufB(7 downto 0)
    );
myImd4buf: entity work.design_1_Vsp_core_0_0_Dpbram_size2kB_a8b8
     port map (
      D(7) => myImd4buf_n_8,
      D(6) => myImd4buf_n_9,
      D(5) => myImd4buf_n_10,
      D(4) => myImd4buf_n_11,
      D(3) => myImd4buf_n_12,
      D(2) => myImd4buf_n_13,
      D(1) => myImd4buf_n_14,
      D(0) => myImd4buf_n_15,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(7) => \rexp_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(6) => \rexp_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(5) => \rexp_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(4) => \rexp_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(3) => \rexp_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(2) => \rexp_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(1) => \rexp_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\(0) => \rexp_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_0\ => enImdbuf_reg_n_0,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(10) => \aImdbufB_reg_n_0_[10]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(9) => \aImdbufB_reg_n_0_[9]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(8) => \aImdbufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(7) => \aImdbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(6) => \aImdbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(5) => \aImdbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(4) => \aImdbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(3) => \aImdbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(2) => \aImdbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(1) => \aImdbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_1\(0) => \aImdbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_2\ => myImd1buf_n_17,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_3\ => myImd1buf_n_16,
      Q(10) => \aImdbuf_reg_n_0_[10]\,
      Q(9) => \aImdbuf_reg_n_0_[9]\,
      Q(8) => \aImdbuf_reg_n_0_[8]\,
      Q(7) => \aImdbuf_reg_n_0_[7]\,
      Q(6) => \aImdbuf_reg_n_0_[6]\,
      Q(5) => \aImdbuf_reg_n_0_[5]\,
      Q(4) => \aImdbuf_reg_n_0_[4]\,
      Q(3) => \aImdbuf_reg_n_0_[3]\,
      Q(2) => \aImdbuf_reg_n_0_[2]\,
      Q(1) => \aImdbuf_reg_n_0_[1]\,
      Q(0) => \aImdbuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      \dImd_reg[7]\(2 downto 0) => fghij(2 downto 0),
      \dImd_reg[7]_0\(7 downto 0) => drdImd0bufB(7 downto 0),
      \dImd_reg[7]_1\ => \stateImdstream[0]_i_3_n_0\,
      \dImd_reg[7]_2\(7 downto 0) => drdImd3bufB(7 downto 0),
      \dImd_reg[7]_3\(7 downto 0) => drdImd2bufB(7 downto 0),
      \dImd_reg[7]_4\(7 downto 0) => drdImd1bufB(7 downto 0),
      doutb(7 downto 0) => drdImd4bufB(7 downto 0),
      \fghij_reg[2]\ => myImd4buf_n_16
    );
postNotLive_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BA30B830B830B830"
    )
        port map (
      I0 => \maximds[4][7]_i_3_n_0\,
      I1 => \row_lcl[10]_i_1_n_0\,
      I2 => postNotLive_reg_n_0,
      I3 => \col_lcl[10]__0_i_3_n_0\,
      I4 => ceMaxsel_reg_n_0,
      I5 => \col_lcl[8]__0_i_3_n_0\,
      O => postNotLive_i_1_n_0
    );
postNotLive_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => postNotLive_i_1_n_0,
      Q => postNotLive_reg_n_0
    );
\postcol_lcl[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => stateCorner(1),
      I1 => \^rng_reg_0\,
      I2 => \postcol_lcl__0\(0),
      O => \postcol_lcl[0]_i_1_n_0\
    );
\postcol_lcl[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBFBBBBBBBBBBBBB"
    )
        port map (
      I0 => \stateCorner[0]_i_2_n_0\,
      I1 => \^rng_reg_1\,
      I2 => grayVideoinToManyAXIS_tlast,
      I3 => \tkst_reg[0]_0\,
      I4 => grayVideoinToManyAXIS_tvalid,
      I5 => \postcol_lcl[10]_i_3_n_0\,
      O => \postcol_lcl[10]_i_1_n_0\
    );
\postcol_lcl[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28280028"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => \postcol_lcl__0\(10),
      I2 => \postcol_lcl[10]_i_4_n_0\,
      I3 => stateCorner(0),
      I4 => stateCorner(1),
      O => \postcol_lcl[10]_i_2_n_0\
    );
\postcol_lcl[10]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => stateCorner(0),
      I1 => stateCorner(1),
      O => \postcol_lcl[10]_i_3_n_0\
    );
\postcol_lcl[10]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \postcol_lcl__0\(9),
      I1 => \postcol_lcl__0\(8),
      I2 => \postcol_lcl__0\(6),
      I3 => \postcol_lcl[9]_i_3_n_0\,
      I4 => \postcol_lcl__0\(7),
      O => \postcol_lcl[10]_i_4_n_0\
    );
\postcol_lcl[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => stateCorner(1),
      I1 => \^rng_reg_0\,
      I2 => \postcol_lcl__0\(1),
      I3 => \postcol_lcl__0\(0),
      O => \postcol_lcl[1]_i_1_n_0\
    );
\postcol_lcl[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08888000"
    )
        port map (
      I0 => stateCorner(1),
      I1 => \^rng_reg_0\,
      I2 => \postcol_lcl__0\(0),
      I3 => \postcol_lcl__0\(1),
      I4 => \postcol_lcl__0\(2),
      O => \postcol_lcl[2]_i_1_n_0\
    );
\postcol_lcl[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0888888880000000"
    )
        port map (
      I0 => stateCorner(1),
      I1 => \^rng_reg_0\,
      I2 => \postcol_lcl__0\(1),
      I3 => \postcol_lcl__0\(0),
      I4 => \postcol_lcl__0\(2),
      I5 => \postcol_lcl__0\(3),
      O => \postcol_lcl[3]_i_1_n_0\
    );
\postcol_lcl[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28280028"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => \postcol_lcl__0\(4),
      I2 => \postcol_lcl[4]_i_2_n_0\,
      I3 => stateCorner(0),
      I4 => stateCorner(1),
      O => \postcol_lcl[4]_i_1_n_0\
    );
\postcol_lcl[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \postcol_lcl__0\(2),
      I1 => \postcol_lcl__0\(0),
      I2 => \postcol_lcl__0\(1),
      I3 => \postcol_lcl__0\(3),
      O => \postcol_lcl[4]_i_2_n_0\
    );
\postcol_lcl[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28280028"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => \postcol_lcl__0\(5),
      I2 => \postcol_lcl[5]_i_2_n_0\,
      I3 => stateCorner(0),
      I4 => stateCorner(1),
      O => \postcol_lcl[5]_i_1_n_0\
    );
\postcol_lcl[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \postcol_lcl__0\(3),
      I1 => \postcol_lcl__0\(1),
      I2 => \postcol_lcl__0\(0),
      I3 => \postcol_lcl__0\(2),
      I4 => \postcol_lcl__0\(4),
      O => \postcol_lcl[5]_i_2_n_0\
    );
\postcol_lcl[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28280028"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => \postcol_lcl__0\(6),
      I2 => \postcol_lcl[9]_i_3_n_0\,
      I3 => stateCorner(0),
      I4 => stateCorner(1),
      O => \postcol_lcl[6]_i_1_n_0\
    );
\postcol_lcl[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888288800002888"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => \postcol_lcl__0\(7),
      I2 => \postcol_lcl__0\(6),
      I3 => \postcol_lcl[9]_i_3_n_0\,
      I4 => stateCorner(0),
      I5 => stateCorner(1),
      O => \postcol_lcl[7]_i_1_n_0\
    );
\postcol_lcl[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000028888888"
    )
        port map (
      I0 => \^rng_reg_1\,
      I1 => \postcol_lcl__0\(8),
      I2 => \postcol_lcl__0\(7),
      I3 => \postcol_lcl[9]_i_3_n_0\,
      I4 => \postcol_lcl__0\(6),
      I5 => \postcol_lcl[10]_i_3_n_0\,
      O => \postcol_lcl[8]_i_1_n_0\
    );
\postcol_lcl[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \postcol_lcl[9]_i_2_n_0\,
      I1 => \postcol_lcl__0\(9),
      I2 => \postcol_lcl__0\(8),
      I3 => \postcol_lcl__0\(6),
      I4 => \postcol_lcl[9]_i_3_n_0\,
      I5 => \postcol_lcl__0\(7),
      O => \postcol_lcl[9]_i_1_n_0\
    );
\postcol_lcl[9]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => stateCorner(1),
      O => \postcol_lcl[9]_i_2_n_0\
    );
\postcol_lcl[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \postcol_lcl__0\(4),
      I1 => \postcol_lcl__0\(2),
      I2 => \postcol_lcl__0\(0),
      I3 => \postcol_lcl__0\(1),
      I4 => \postcol_lcl__0\(3),
      I5 => \postcol_lcl__0\(5),
      O => \postcol_lcl[9]_i_3_n_0\
    );
\postcol_lcl_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \postcol_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \postcol_lcl[0]_i_1_n_0\,
      Q => \postcol_lcl__0\(0)
    );
\postcol_lcl_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \postcol_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \postcol_lcl[10]_i_2_n_0\,
      Q => \postcol_lcl__0\(10)
    );
\postcol_lcl_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \postcol_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \postcol_lcl[1]_i_1_n_0\,
      Q => \postcol_lcl__0\(1)
    );
\postcol_lcl_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \postcol_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \postcol_lcl[2]_i_1_n_0\,
      Q => \postcol_lcl__0\(2)
    );
\postcol_lcl_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \postcol_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \postcol_lcl[3]_i_1_n_0\,
      Q => \postcol_lcl__0\(3)
    );
\postcol_lcl_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \postcol_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \postcol_lcl[4]_i_1_n_0\,
      Q => \postcol_lcl__0\(4)
    );
\postcol_lcl_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \postcol_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \postcol_lcl[5]_i_1_n_0\,
      Q => \postcol_lcl__0\(5)
    );
\postcol_lcl_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \postcol_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \postcol_lcl[6]_i_1_n_0\,
      Q => \postcol_lcl__0\(6)
    );
\postcol_lcl_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \postcol_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \postcol_lcl[7]_i_1_n_0\,
      Q => \postcol_lcl__0\(7)
    );
\postcol_lcl_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \postcol_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \postcol_lcl[8]_i_1_n_0\,
      Q => \postcol_lcl__0\(8)
    );
\postcol_lcl_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \postcol_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \postcol_lcl[9]_i_1_n_0\,
      Q => \postcol_lcl__0\(9)
    );
\r[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(15),
      I1 => diffI_IIp1(15),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[15]_i_10_n_0\
    );
\r[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(14),
      I1 => diffI_IIp1(14),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[15]_i_11_n_0\
    );
\r[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(13),
      I1 => diffI_IIp1(13),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[15]_i_12_n_0\
    );
\r[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(12),
      I1 => diffI_IIp1(12),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[15]_i_13_n_0\
    );
\r[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(11),
      I1 => diffI_IIp1(11),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[15]_i_14_n_0\
    );
\r[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(10),
      I1 => diffI_IIp1(10),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[15]_i_15_n_0\
    );
\r[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(9),
      I1 => diffI_IIp1(9),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[15]_i_16_n_0\
    );
\r[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(8),
      I1 => diffI_IIp1(8),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[15]_i_17_n_0\
    );
\r[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(15),
      O => \r[15]_i_2_n_0\
    );
\r[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(14),
      O => \r[15]_i_3_n_0\
    );
\r[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(13),
      O => \r[15]_i_4_n_0\
    );
\r[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(12),
      O => \r[15]_i_5_n_0\
    );
\r[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(11),
      O => \r[15]_i_6_n_0\
    );
\r[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(10),
      O => \r[15]_i_7_n_0\
    );
\r[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(9),
      O => \r[15]_i_8_n_0\
    );
\r[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(8),
      O => \r[15]_i_9_n_0\
    );
\r[23]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(23),
      I1 => diffI_IIp1(23),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[23]_i_10_n_0\
    );
\r[23]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(22),
      I1 => diffI_IIp1(22),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[23]_i_11_n_0\
    );
\r[23]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(21),
      I1 => diffI_IIp1(21),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[23]_i_12_n_0\
    );
\r[23]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(20),
      I1 => diffI_IIp1(20),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[23]_i_13_n_0\
    );
\r[23]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(19),
      I1 => diffI_IIp1(19),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[23]_i_14_n_0\
    );
\r[23]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(18),
      I1 => diffI_IIp1(18),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[23]_i_15_n_0\
    );
\r[23]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(17),
      I1 => diffI_IIp1(17),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[23]_i_16_n_0\
    );
\r[23]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(16),
      I1 => diffI_IIp1(16),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[23]_i_17_n_0\
    );
\r[23]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(23),
      O => \r[23]_i_2_n_0\
    );
\r[23]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(22),
      O => \r[23]_i_3_n_0\
    );
\r[23]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(21),
      O => \r[23]_i_4_n_0\
    );
\r[23]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(20),
      O => \r[23]_i_5_n_0\
    );
\r[23]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(19),
      O => \r[23]_i_6_n_0\
    );
\r[23]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(18),
      O => \r[23]_i_7_n_0\
    );
\r[23]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(17),
      O => \r[23]_i_8_n_0\
    );
\r[23]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(16),
      O => \r[23]_i_9_n_0\
    );
\r[31]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(31),
      I1 => diffI_IIp1(31),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[31]_i_10_n_0\
    );
\r[31]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(30),
      I1 => diffI_IIp1(30),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[31]_i_11_n_0\
    );
\r[31]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(29),
      I1 => diffI_IIp1(29),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[31]_i_12_n_0\
    );
\r[31]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(28),
      I1 => diffI_IIp1(28),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[31]_i_13_n_0\
    );
\r[31]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(27),
      I1 => diffI_IIp1(27),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[31]_i_14_n_0\
    );
\r[31]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(26),
      I1 => diffI_IIp1(26),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[31]_i_15_n_0\
    );
\r[31]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(25),
      I1 => diffI_IIp1(25),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[31]_i_16_n_0\
    );
\r[31]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(24),
      I1 => diffI_IIp1(24),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[31]_i_17_n_0\
    );
\r[31]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(31),
      O => \r[31]_i_2_n_0\
    );
\r[31]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(30),
      O => \r[31]_i_3_n_0\
    );
\r[31]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(29),
      O => \r[31]_i_4_n_0\
    );
\r[31]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(28),
      O => \r[31]_i_5_n_0\
    );
\r[31]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(27),
      O => \r[31]_i_6_n_0\
    );
\r[31]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(26),
      O => \r[31]_i_7_n_0\
    );
\r[31]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(25),
      O => \r[31]_i_8_n_0\
    );
\r[31]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(24),
      O => \r[31]_i_9_n_0\
    );
\r[39]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(39),
      I1 => diffI_IIp1(39),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[39]_i_10_n_0\
    );
\r[39]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(38),
      I1 => diffI_IIp1(38),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[39]_i_11_n_0\
    );
\r[39]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(37),
      I1 => diffI_IIp1(37),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[39]_i_12_n_0\
    );
\r[39]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(36),
      I1 => diffI_IIp1(36),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[39]_i_13_n_0\
    );
\r[39]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(35),
      I1 => diffI_IIp1(35),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[39]_i_14_n_0\
    );
\r[39]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(34),
      I1 => diffI_IIp1(34),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[39]_i_15_n_0\
    );
\r[39]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(33),
      I1 => diffI_IIp1(33),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[39]_i_16_n_0\
    );
\r[39]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(32),
      I1 => diffI_IIp1(32),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[39]_i_17_n_0\
    );
\r[39]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(39),
      O => \r[39]_i_2_n_0\
    );
\r[39]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(38),
      O => \r[39]_i_3_n_0\
    );
\r[39]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(37),
      O => \r[39]_i_4_n_0\
    );
\r[39]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(36),
      O => \r[39]_i_5_n_0\
    );
\r[39]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(35),
      O => \r[39]_i_6_n_0\
    );
\r[39]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(34),
      O => \r[39]_i_7_n_0\
    );
\r[39]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(33),
      O => \r[39]_i_8_n_0\
    );
\r[39]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(32),
      O => \r[39]_i_9_n_0\
    );
\r[47]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(43),
      I1 => diffI_IIp1(46),
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \r[47]_i_10_n_0\
    );
\r[47]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(43),
      I1 => diffI_IIp1(45),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[47]_i_11_n_0\
    );
\r[47]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(43),
      I1 => diffI_IIp1(44),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[47]_i_12_n_0\
    );
\r[47]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(43),
      I1 => diffI_IIp1(43),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[47]_i_13_n_0\
    );
\r[47]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(42),
      I1 => diffI_IIp1(42),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[47]_i_14_n_0\
    );
\r[47]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(41),
      I1 => diffI_IIp1(41),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[47]_i_15_n_0\
    );
\r[47]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(40),
      I1 => diffI_IIp1(40),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[47]_i_16_n_0\
    );
\r[47]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(43),
      O => \r[47]_i_2_n_0\
    );
\r[47]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(43),
      O => \r[47]_i_3_n_0\
    );
\r[47]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(43),
      O => \r[47]_i_4_n_0\
    );
\r[47]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(43),
      O => \r[47]_i_5_n_0\
    );
\r[47]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(42),
      O => \r[47]_i_6_n_0\
    );
\r[47]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(41),
      O => \r[47]_i_7_n_0\
    );
\r[47]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk(40),
      O => \r[47]_i_8_n_0\
    );
\r[47]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(43),
      I1 => diffI_IIp1(46),
      I2 => \stateScore_reg_rep__16_n_0\,
      O => \r[47]_i_9_n_0\
    );
\r[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(7),
      I1 => diffI_IIp1(7),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[7]_i_10_n_0\
    );
\r[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(6),
      I1 => diffI_IIp1(6),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[7]_i_11_n_0\
    );
\r[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(5),
      I1 => diffI_IIp1(5),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[7]_i_12_n_0\
    );
\r[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(4),
      I1 => diffI_IIp1(4),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[7]_i_13_n_0\
    );
\r[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(3),
      I1 => diffI_IIp1(3),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[7]_i_14_n_0\
    );
\r[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(2),
      I1 => diffI_IIp1(2),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[7]_i_15_n_0\
    );
\r[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(1),
      I1 => diffI_IIp1(1),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[7]_i_16_n_0\
    );
\r[7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => termIIIk(0),
      I1 => diffI_IIp1(0),
      I2 => \stateScore_reg_rep__15_n_0\,
      O => \r[7]_i_17_n_0\
    );
\r[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(7),
      O => \r[7]_i_2_n_0\
    );
\r[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(6),
      O => \r[7]_i_3_n_0\
    );
\r[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(5),
      O => \r[7]_i_4_n_0\
    );
\r[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(4),
      O => \r[7]_i_5_n_0\
    );
\r[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(3),
      O => \r[7]_i_6_n_0\
    );
\r[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(2),
      O => \r[7]_i_7_n_0\
    );
\r[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(1),
      O => \r[7]_i_8_n_0\
    );
\r[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk(0),
      O => \r[7]_i_9_n_0\
    );
\r_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[7]_i_1_n_15\,
      Q => \r_reg_n_0_[0]\
    );
\r_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[15]_i_1_n_13\,
      Q => \r_reg_n_0_[10]\
    );
\r_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[15]_i_1_n_12\,
      Q => \r_reg_n_0_[11]\
    );
\r_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[15]_i_1_n_11\,
      Q => \r_reg_n_0_[12]\
    );
\r_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[15]_i_1_n_10\,
      Q => \r_reg_n_0_[13]\
    );
\r_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[15]_i_1_n_9\,
      Q => \r_reg_n_0_[14]\
    );
\r_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[15]_i_1_n_8\,
      Q => \r_reg_n_0_[15]\
    );
\r_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \r_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \r_reg[15]_i_1_n_0\,
      CO(6) => \r_reg[15]_i_1_n_1\,
      CO(5) => \r_reg[15]_i_1_n_2\,
      CO(4) => \r_reg[15]_i_1_n_3\,
      CO(3) => \r_reg[15]_i_1_n_4\,
      CO(2) => \r_reg[15]_i_1_n_5\,
      CO(1) => \r_reg[15]_i_1_n_6\,
      CO(0) => \r_reg[15]_i_1_n_7\,
      DI(7) => \r[15]_i_2_n_0\,
      DI(6) => \r[15]_i_3_n_0\,
      DI(5) => \r[15]_i_4_n_0\,
      DI(4) => \r[15]_i_5_n_0\,
      DI(3) => \r[15]_i_6_n_0\,
      DI(2) => \r[15]_i_7_n_0\,
      DI(1) => \r[15]_i_8_n_0\,
      DI(0) => \r[15]_i_9_n_0\,
      O(7) => \r_reg[15]_i_1_n_8\,
      O(6) => \r_reg[15]_i_1_n_9\,
      O(5) => \r_reg[15]_i_1_n_10\,
      O(4) => \r_reg[15]_i_1_n_11\,
      O(3) => \r_reg[15]_i_1_n_12\,
      O(2) => \r_reg[15]_i_1_n_13\,
      O(1) => \r_reg[15]_i_1_n_14\,
      O(0) => \r_reg[15]_i_1_n_15\,
      S(7) => \r[15]_i_10_n_0\,
      S(6) => \r[15]_i_11_n_0\,
      S(5) => \r[15]_i_12_n_0\,
      S(4) => \r[15]_i_13_n_0\,
      S(3) => \r[15]_i_14_n_0\,
      S(2) => \r[15]_i_15_n_0\,
      S(1) => \r[15]_i_16_n_0\,
      S(0) => \r[15]_i_17_n_0\
    );
\r_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[23]_i_1_n_15\,
      Q => \r_reg_n_0_[16]\
    );
\r_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[23]_i_1_n_14\,
      Q => \r_reg_n_0_[17]\
    );
\r_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[23]_i_1_n_13\,
      Q => \r_reg_n_0_[18]\
    );
\r_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[23]_i_1_n_12\,
      Q => \r_reg_n_0_[19]\
    );
\r_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[7]_i_1_n_14\,
      Q => \r_reg_n_0_[1]\
    );
\r_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[23]_i_1_n_11\,
      Q => \r_reg_n_0_[20]\
    );
\r_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[23]_i_1_n_10\,
      Q => \r_reg_n_0_[21]\
    );
\r_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[23]_i_1_n_9\,
      Q => \r_reg_n_0_[22]\
    );
\r_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[23]_i_1_n_8\,
      Q => \r_reg_n_0_[23]\
    );
\r_reg[23]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \r_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \r_reg[23]_i_1_n_0\,
      CO(6) => \r_reg[23]_i_1_n_1\,
      CO(5) => \r_reg[23]_i_1_n_2\,
      CO(4) => \r_reg[23]_i_1_n_3\,
      CO(3) => \r_reg[23]_i_1_n_4\,
      CO(2) => \r_reg[23]_i_1_n_5\,
      CO(1) => \r_reg[23]_i_1_n_6\,
      CO(0) => \r_reg[23]_i_1_n_7\,
      DI(7) => \r[23]_i_2_n_0\,
      DI(6) => \r[23]_i_3_n_0\,
      DI(5) => \r[23]_i_4_n_0\,
      DI(4) => \r[23]_i_5_n_0\,
      DI(3) => \r[23]_i_6_n_0\,
      DI(2) => \r[23]_i_7_n_0\,
      DI(1) => \r[23]_i_8_n_0\,
      DI(0) => \r[23]_i_9_n_0\,
      O(7) => \r_reg[23]_i_1_n_8\,
      O(6) => \r_reg[23]_i_1_n_9\,
      O(5) => \r_reg[23]_i_1_n_10\,
      O(4) => \r_reg[23]_i_1_n_11\,
      O(3) => \r_reg[23]_i_1_n_12\,
      O(2) => \r_reg[23]_i_1_n_13\,
      O(1) => \r_reg[23]_i_1_n_14\,
      O(0) => \r_reg[23]_i_1_n_15\,
      S(7) => \r[23]_i_10_n_0\,
      S(6) => \r[23]_i_11_n_0\,
      S(5) => \r[23]_i_12_n_0\,
      S(4) => \r[23]_i_13_n_0\,
      S(3) => \r[23]_i_14_n_0\,
      S(2) => \r[23]_i_15_n_0\,
      S(1) => \r[23]_i_16_n_0\,
      S(0) => \r[23]_i_17_n_0\
    );
\r_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[31]_i_1_n_15\,
      Q => \r_reg_n_0_[24]\
    );
\r_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[31]_i_1_n_14\,
      Q => \r_reg_n_0_[25]\
    );
\r_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[31]_i_1_n_13\,
      Q => \r_reg_n_0_[26]\
    );
\r_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[31]_i_1_n_12\,
      Q => \r_reg_n_0_[27]\
    );
\r_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[31]_i_1_n_11\,
      Q => \r_reg_n_0_[28]\
    );
\r_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[31]_i_1_n_10\,
      Q => \r_reg_n_0_[29]\
    );
\r_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[7]_i_1_n_13\,
      Q => \r_reg_n_0_[2]\
    );
\r_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[31]_i_1_n_9\,
      Q => \r_reg_n_0_[30]\
    );
\r_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[31]_i_1_n_8\,
      Q => \r_reg_n_0_[31]\
    );
\r_reg[31]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \r_reg[23]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \r_reg[31]_i_1_n_0\,
      CO(6) => \r_reg[31]_i_1_n_1\,
      CO(5) => \r_reg[31]_i_1_n_2\,
      CO(4) => \r_reg[31]_i_1_n_3\,
      CO(3) => \r_reg[31]_i_1_n_4\,
      CO(2) => \r_reg[31]_i_1_n_5\,
      CO(1) => \r_reg[31]_i_1_n_6\,
      CO(0) => \r_reg[31]_i_1_n_7\,
      DI(7) => \r[31]_i_2_n_0\,
      DI(6) => \r[31]_i_3_n_0\,
      DI(5) => \r[31]_i_4_n_0\,
      DI(4) => \r[31]_i_5_n_0\,
      DI(3) => \r[31]_i_6_n_0\,
      DI(2) => \r[31]_i_7_n_0\,
      DI(1) => \r[31]_i_8_n_0\,
      DI(0) => \r[31]_i_9_n_0\,
      O(7) => \r_reg[31]_i_1_n_8\,
      O(6) => \r_reg[31]_i_1_n_9\,
      O(5) => \r_reg[31]_i_1_n_10\,
      O(4) => \r_reg[31]_i_1_n_11\,
      O(3) => \r_reg[31]_i_1_n_12\,
      O(2) => \r_reg[31]_i_1_n_13\,
      O(1) => \r_reg[31]_i_1_n_14\,
      O(0) => \r_reg[31]_i_1_n_15\,
      S(7) => \r[31]_i_10_n_0\,
      S(6) => \r[31]_i_11_n_0\,
      S(5) => \r[31]_i_12_n_0\,
      S(4) => \r[31]_i_13_n_0\,
      S(3) => \r[31]_i_14_n_0\,
      S(2) => \r[31]_i_15_n_0\,
      S(1) => \r[31]_i_16_n_0\,
      S(0) => \r[31]_i_17_n_0\
    );
\r_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[39]_i_1_n_15\,
      Q => \r_reg_n_0_[32]\
    );
\r_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[39]_i_1_n_14\,
      Q => \r_reg_n_0_[33]\
    );
\r_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[39]_i_1_n_13\,
      Q => \r_reg_n_0_[34]\
    );
\r_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[39]_i_1_n_12\,
      Q => \r_reg_n_0_[35]\
    );
\r_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[39]_i_1_n_11\,
      Q => \r_reg_n_0_[36]\
    );
\r_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[39]_i_1_n_10\,
      Q => \r_reg_n_0_[37]\
    );
\r_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[39]_i_1_n_9\,
      Q => \r_reg_n_0_[38]\
    );
\r_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[39]_i_1_n_8\,
      Q => \r_reg_n_0_[39]\
    );
\r_reg[39]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \r_reg[31]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \r_reg[39]_i_1_n_0\,
      CO(6) => \r_reg[39]_i_1_n_1\,
      CO(5) => \r_reg[39]_i_1_n_2\,
      CO(4) => \r_reg[39]_i_1_n_3\,
      CO(3) => \r_reg[39]_i_1_n_4\,
      CO(2) => \r_reg[39]_i_1_n_5\,
      CO(1) => \r_reg[39]_i_1_n_6\,
      CO(0) => \r_reg[39]_i_1_n_7\,
      DI(7) => \r[39]_i_2_n_0\,
      DI(6) => \r[39]_i_3_n_0\,
      DI(5) => \r[39]_i_4_n_0\,
      DI(4) => \r[39]_i_5_n_0\,
      DI(3) => \r[39]_i_6_n_0\,
      DI(2) => \r[39]_i_7_n_0\,
      DI(1) => \r[39]_i_8_n_0\,
      DI(0) => \r[39]_i_9_n_0\,
      O(7) => \r_reg[39]_i_1_n_8\,
      O(6) => \r_reg[39]_i_1_n_9\,
      O(5) => \r_reg[39]_i_1_n_10\,
      O(4) => \r_reg[39]_i_1_n_11\,
      O(3) => \r_reg[39]_i_1_n_12\,
      O(2) => \r_reg[39]_i_1_n_13\,
      O(1) => \r_reg[39]_i_1_n_14\,
      O(0) => \r_reg[39]_i_1_n_15\,
      S(7) => \r[39]_i_10_n_0\,
      S(6) => \r[39]_i_11_n_0\,
      S(5) => \r[39]_i_12_n_0\,
      S(4) => \r[39]_i_13_n_0\,
      S(3) => \r[39]_i_14_n_0\,
      S(2) => \r[39]_i_15_n_0\,
      S(1) => \r[39]_i_16_n_0\,
      S(0) => \r[39]_i_17_n_0\
    );
\r_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[7]_i_1_n_12\,
      Q => \r_reg_n_0_[3]\
    );
\r_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[47]_i_1_n_15\,
      Q => \r_reg_n_0_[40]\
    );
\r_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[47]_i_1_n_14\,
      Q => \r_reg_n_0_[41]\
    );
\r_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[47]_i_1_n_13\,
      Q => \r_reg_n_0_[42]\
    );
\r_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[47]_i_1_n_12\,
      Q => \r_reg_n_0_[43]\
    );
\r_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[47]_i_1_n_11\,
      Q => \r_reg_n_0_[44]\
    );
\r_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[47]_i_1_n_10\,
      Q => \r_reg_n_0_[45]\
    );
\r_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[47]_i_1_n_9\,
      Q => \r_reg_n_0_[46]\
    );
\r_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[47]_i_1_n_8\,
      Q => \r_reg_n_0_[47]\
    );
\r_reg[47]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \r_reg[39]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \NLW_r_reg[47]_i_1_CO_UNCONNECTED\(7),
      CO(6) => \r_reg[47]_i_1_n_1\,
      CO(5) => \r_reg[47]_i_1_n_2\,
      CO(4) => \r_reg[47]_i_1_n_3\,
      CO(3) => \r_reg[47]_i_1_n_4\,
      CO(2) => \r_reg[47]_i_1_n_5\,
      CO(1) => \r_reg[47]_i_1_n_6\,
      CO(0) => \r_reg[47]_i_1_n_7\,
      DI(7) => '0',
      DI(6) => \r[47]_i_2_n_0\,
      DI(5) => \r[47]_i_3_n_0\,
      DI(4) => \r[47]_i_4_n_0\,
      DI(3) => \r[47]_i_5_n_0\,
      DI(2) => \r[47]_i_6_n_0\,
      DI(1) => \r[47]_i_7_n_0\,
      DI(0) => \r[47]_i_8_n_0\,
      O(7) => \r_reg[47]_i_1_n_8\,
      O(6) => \r_reg[47]_i_1_n_9\,
      O(5) => \r_reg[47]_i_1_n_10\,
      O(4) => \r_reg[47]_i_1_n_11\,
      O(3) => \r_reg[47]_i_1_n_12\,
      O(2) => \r_reg[47]_i_1_n_13\,
      O(1) => \r_reg[47]_i_1_n_14\,
      O(0) => \r_reg[47]_i_1_n_15\,
      S(7) => \r[47]_i_9_n_0\,
      S(6) => \r[47]_i_10_n_0\,
      S(5) => \r[47]_i_11_n_0\,
      S(4) => \r[47]_i_12_n_0\,
      S(3) => \r[47]_i_13_n_0\,
      S(2) => \r[47]_i_14_n_0\,
      S(1) => \r[47]_i_15_n_0\,
      S(0) => \r[47]_i_16_n_0\
    );
\r_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[7]_i_1_n_11\,
      Q => \r_reg_n_0_[4]\
    );
\r_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[7]_i_1_n_10\,
      Q => \r_reg_n_0_[5]\
    );
\r_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[7]_i_1_n_9\,
      Q => \r_reg_n_0_[6]\
    );
\r_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[7]_i_1_n_8\,
      Q => \r_reg_n_0_[7]\
    );
\r_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \stateScore_reg_rep__15_n_0\,
      CI_TOP => '0',
      CO(7) => \r_reg[7]_i_1_n_0\,
      CO(6) => \r_reg[7]_i_1_n_1\,
      CO(5) => \r_reg[7]_i_1_n_2\,
      CO(4) => \r_reg[7]_i_1_n_3\,
      CO(3) => \r_reg[7]_i_1_n_4\,
      CO(2) => \r_reg[7]_i_1_n_5\,
      CO(1) => \r_reg[7]_i_1_n_6\,
      CO(0) => \r_reg[7]_i_1_n_7\,
      DI(7) => \r[7]_i_2_n_0\,
      DI(6) => \r[7]_i_3_n_0\,
      DI(5) => \r[7]_i_4_n_0\,
      DI(4) => \r[7]_i_5_n_0\,
      DI(3) => \r[7]_i_6_n_0\,
      DI(2) => \r[7]_i_7_n_0\,
      DI(1) => \r[7]_i_8_n_0\,
      DI(0) => \r[7]_i_9_n_0\,
      O(7) => \r_reg[7]_i_1_n_8\,
      O(6) => \r_reg[7]_i_1_n_9\,
      O(5) => \r_reg[7]_i_1_n_10\,
      O(4) => \r_reg[7]_i_1_n_11\,
      O(3) => \r_reg[7]_i_1_n_12\,
      O(2) => \r_reg[7]_i_1_n_13\,
      O(1) => \r_reg[7]_i_1_n_14\,
      O(0) => \r_reg[7]_i_1_n_15\,
      S(7) => \r[7]_i_10_n_0\,
      S(6) => \r[7]_i_11_n_0\,
      S(5) => \r[7]_i_12_n_0\,
      S(4) => \r[7]_i_13_n_0\,
      S(3) => \r[7]_i_14_n_0\,
      S(2) => \r[7]_i_15_n_0\,
      S(1) => \r[7]_i_16_n_0\,
      S(0) => \r[7]_i_17_n_0\
    );
\r_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[15]_i_1_n_15\,
      Q => \r_reg_n_0_[8]\
    );
\r_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \r_reg[15]_i_1_n_14\,
      Q => \r_reg_n_0_[9]\
    );
\rexp[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F4F4FFF44444444"
    )
        port map (
      I0 => \rexp[0]_i_2_n_0\,
      I1 => \rexp[7]_i_4_n_0\,
      I2 => \rexp[0]_i_3_n_0\,
      I3 => \rexp[0]_i_4_n_0\,
      I4 => \rexp[0]_i_5_n_0\,
      I5 => \rexp[1]_i_6_n_0\,
      O => \rexp[0]_i_1_n_0\
    );
\rexp[0]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAABFBFFFFABFB"
    )
        port map (
      I0 => shift(3),
      I1 => \r_reg_n_0_[0]\,
      I2 => shift(5),
      I3 => \r_reg_n_0_[32]\,
      I4 => shift(4),
      I5 => \r_reg_n_0_[16]\,
      O => \rexp[0]_i_10_n_0\
    );
\rexp[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A888A888A8A8A88"
    )
        port map (
      I0 => \rexp[0]_i_6_n_0\,
      I1 => \rexp[1]_i_8_n_0\,
      I2 => \rexp[1]_i_9_n_0\,
      I3 => \rexp[7]_i_13_n_0\,
      I4 => \rexp[7]_i_12_n_0\,
      I5 => \rexp[7]_i_11_n_0\,
      O => \rexp[0]_i_2_n_0\
    );
\rexp[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \msb[5]_i_3_n_0\,
      I1 => \rshift[4]_i_3_n_0\,
      I2 => \rexp[7]_i_21_n_0\,
      I3 => \r_reg_n_0_[0]\,
      O => \rexp[0]_i_3_n_0\
    );
\rexp[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2F202F2F2F202020"
    )
        port map (
      I0 => \rexp[1]_i_12_n_0\,
      I1 => \rexp[1]_i_13_n_0\,
      I2 => \msb[0]_i_1_n_0\,
      I3 => \rexp[0]_i_7_n_0\,
      I4 => \msb[1]_i_1_n_0\,
      I5 => \rexp[1]_i_10_n_0\,
      O => \rexp[0]_i_4_n_0\
    );
\rexp[0]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \msb[3]_i_1_n_0\,
      I1 => \msb[0]_i_1_n_0\,
      I2 => \rshift[5]_i_4_n_0\,
      I3 => \msb[4]_i_2_n_0\,
      I4 => \msb[5]_i_3_n_0\,
      O => \rexp[0]_i_5_n_0\
    );
\rexp[0]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888BBB"
    )
        port map (
      I0 => \rexp[1]_i_14_n_0\,
      I1 => shift(0),
      I2 => \rexp[2]_i_6_n_0\,
      I3 => shift(1),
      I4 => \rexp[0]_i_8_n_0\,
      O => \rexp[0]_i_6_n_0\
    );
\rexp[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A0C0C0AFAFC0CF"
    )
        port map (
      I0 => \rexp[1]_i_24_n_0\,
      I1 => \rexp[0]_i_9_n_0\,
      I2 => \rexp[1]_i_19_n_0\,
      I3 => \rexp[1]_i_20_n_0\,
      I4 => \rexp[1]_i_23_n_0\,
      I5 => \rexp[1]_i_21_n_0\,
      O => \rexp[0]_i_7_n_0\
    );
\rexp[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4540404045454545"
    )
        port map (
      I0 => shift(1),
      I1 => \rexp[4]_i_5_n_0\,
      I2 => shift(2),
      I3 => \rexp[7]_i_31_n_0\,
      I4 => shift(3),
      I5 => \rexp[0]_i_10_n_0\,
      O => \rexp[0]_i_8_n_0\
    );
\rexp[0]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"470047FF"
    )
        port map (
      I0 => \r_reg_n_0_[0]\,
      I1 => \rexp[1]_i_35_n_0\,
      I2 => \r_reg_n_0_[32]\,
      I3 => \rexp[1]_i_34_n_0\,
      I4 => \r_reg_n_0_[16]\,
      O => \rexp[0]_i_9_n_0\
    );
\rexp[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF444F44444444"
    )
        port map (
      I0 => \rexp[1]_i_2_n_0\,
      I1 => \rexp[7]_i_4_n_0\,
      I2 => \rexp[1]_i_3_n_0\,
      I3 => \rexp[1]_i_4_n_0\,
      I4 => \rexp[1]_i_5_n_0\,
      I5 => \rexp[1]_i_6_n_0\,
      O => \rexp[1]_i_1_n_0\
    );
\rexp[1]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00404444"
    )
        port map (
      I0 => \rexp[1]_i_15_n_0\,
      I1 => \rexp[1]_i_16_n_0\,
      I2 => \rexp[1]_i_17_n_0\,
      I3 => \rexp[1]_i_18_n_0\,
      I4 => \rexp[1]_i_19_n_0\,
      O => \rexp[1]_i_10_n_0\
    );
\rexp[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F301F1F3F301010"
    )
        port map (
      I0 => \rexp[1]_i_20_n_0\,
      I1 => \rexp[1]_i_21_n_0\,
      I2 => \rexp[1]_i_19_n_0\,
      I3 => \rexp[1]_i_22_n_0\,
      I4 => \rexp[1]_i_23_n_0\,
      I5 => \rexp[1]_i_24_n_0\,
      O => \rexp[1]_i_11_n_0\
    );
\rexp[1]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF444400F0"
    )
        port map (
      I0 => \rexp[1]_i_25_n_0\,
      I1 => \rexp[1]_i_26_n_0\,
      I2 => \rexp[1]_i_27_n_0\,
      I3 => \rexp[1]_i_28_n_0\,
      I4 => \msb[2]_i_1_n_0\,
      I5 => \msb[1]_i_1_n_0\,
      O => \rexp[1]_i_12_n_0\
    );
\rexp[1]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DD000F00"
    )
        port map (
      I0 => \rexp[1]_i_29_n_0\,
      I1 => \rexp[1]_i_30_n_0\,
      I2 => \rexp_reg[1]_i_31_n_0\,
      I3 => \msb[1]_i_1_n_0\,
      I4 => \msb[2]_i_1_n_0\,
      O => \rexp[1]_i_13_n_0\
    );
\rexp[1]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF55035503"
    )
        port map (
      I0 => \rexp[5]_i_5_n_0\,
      I1 => \rexp[1]_i_32_n_0\,
      I2 => \rexp[1]_i_33_n_0\,
      I3 => shift(2),
      I4 => \rexp[2]_i_5_n_0\,
      I5 => shift(1),
      O => \rexp[1]_i_14_n_0\
    );
\rexp[1]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \r_reg_n_0_[22]\,
      I1 => \rexp[1]_i_34_n_0\,
      I2 => \r_reg_n_0_[38]\,
      I3 => \rexp[1]_i_35_n_0\,
      I4 => \r_reg_n_0_[6]\,
      I5 => \rexp[1]_i_23_n_0\,
      O => \rexp[1]_i_15_n_0\
    );
\rexp[1]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"111F0000111FFFFF"
    )
        port map (
      I0 => \rexp[1]_i_35_n_0\,
      I1 => \r_reg_n_0_[46]\,
      I2 => \rexp[1]_i_36_n_0\,
      I3 => \r_reg_n_0_[14]\,
      I4 => \rexp[1]_i_34_n_0\,
      I5 => \r_reg_n_0_[30]\,
      O => \rexp[1]_i_16_n_0\
    );
\rexp[1]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFDDCFDDCCDDCFDD"
    )
        port map (
      I0 => \r_reg_n_0_[18]\,
      I1 => \rexp[1]_i_23_n_0\,
      I2 => \r_reg_n_0_[34]\,
      I3 => \rexp[1]_i_34_n_0\,
      I4 => \r_reg_n_0_[2]\,
      I5 => \rexp[1]_i_36_n_0\,
      O => \rexp[1]_i_17_n_0\
    );
\rexp[1]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \r_reg_n_0_[10]\,
      I1 => \rexp[1]_i_35_n_0\,
      I2 => \r_reg_n_0_[42]\,
      I3 => \rexp[1]_i_34_n_0\,
      I4 => \r_reg_n_0_[26]\,
      O => \rexp[1]_i_18_n_0\
    );
\rexp[1]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \msb[1]_i_1_n_0\,
      I1 => \msb[2]_i_1_n_0\,
      O => \rexp[1]_i_19_n_0\
    );
\rexp[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A888A888A8A8A88"
    )
        port map (
      I0 => \rexp[1]_i_7_n_0\,
      I1 => \rexp[1]_i_8_n_0\,
      I2 => \rexp[1]_i_9_n_0\,
      I3 => \rexp[7]_i_13_n_0\,
      I4 => \rexp[7]_i_12_n_0\,
      I5 => \rexp[7]_i_11_n_0\,
      O => \rexp[1]_i_2_n_0\
    );
\rexp[1]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \r_reg_n_0_[4]\,
      I1 => \rexp[1]_i_35_n_0\,
      I2 => \r_reg_n_0_[36]\,
      I3 => \rexp[1]_i_34_n_0\,
      I4 => \r_reg_n_0_[20]\,
      O => \rexp[1]_i_20_n_0\
    );
\rexp[1]_i_21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \r_reg_n_0_[12]\,
      I1 => \rexp[1]_i_35_n_0\,
      I2 => \r_reg_n_0_[44]\,
      I3 => \rexp[1]_i_34_n_0\,
      I4 => \r_reg_n_0_[28]\,
      O => \rexp[1]_i_21_n_0\
    );
\rexp[1]_i_22\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"47444777"
    )
        port map (
      I0 => \r_reg_n_0_[16]\,
      I1 => \rexp[1]_i_34_n_0\,
      I2 => \r_reg_n_0_[0]\,
      I3 => \rexp[1]_i_36_n_0\,
      I4 => \r_reg_n_0_[32]\,
      O => \rexp[1]_i_22_n_0\
    );
\rexp[1]_i_23\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \msb[3]_i_1_n_0\,
      I1 => \msb[2]_i_1_n_0\,
      I2 => \msb[1]_i_1_n_0\,
      O => \rexp[1]_i_23_n_0\
    );
\rexp[1]_i_24\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"450045FF"
    )
        port map (
      I0 => \r_reg_n_0_[40]\,
      I1 => \rexp[1]_i_36_n_0\,
      I2 => \r_reg_n_0_[8]\,
      I3 => \rexp[1]_i_34_n_0\,
      I4 => \r_reg_n_0_[24]\,
      O => \rexp[1]_i_24_n_0\
    );
\rexp[1]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \r_reg_n_0_[11]\,
      I1 => \rexp[1]_i_35_n_0\,
      I2 => \r_reg_n_0_[43]\,
      I3 => \rexp[1]_i_34_n_0\,
      I4 => \r_reg_n_0_[27]\,
      O => \rexp[1]_i_25_n_0\
    );
\rexp[1]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABABABFBFBFBABFB"
    )
        port map (
      I0 => \rexp[1]_i_23_n_0\,
      I1 => \r_reg_n_0_[19]\,
      I2 => \rexp[1]_i_34_n_0\,
      I3 => \r_reg_n_0_[35]\,
      I4 => \rexp[1]_i_35_n_0\,
      I5 => \r_reg_n_0_[3]\,
      O => \rexp[1]_i_26_n_0\
    );
\rexp[1]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABABABFBFBFBABFB"
    )
        port map (
      I0 => \rexp[1]_i_23_n_0\,
      I1 => \r_reg_n_0_[23]\,
      I2 => \rexp[1]_i_34_n_0\,
      I3 => \r_reg_n_0_[39]\,
      I4 => \rexp[1]_i_35_n_0\,
      I5 => \r_reg_n_0_[7]\,
      O => \rexp[1]_i_27_n_0\
    );
\rexp[1]_i_28\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \r_reg_n_0_[15]\,
      I1 => \rexp[1]_i_35_n_0\,
      I2 => \r_reg_n_0_[47]\,
      I3 => \rexp[1]_i_34_n_0\,
      I4 => \r_reg_n_0_[31]\,
      O => \rexp[1]_i_28_n_0\
    );
\rexp[1]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"111F0000111FFFFF"
    )
        port map (
      I0 => \rexp[1]_i_35_n_0\,
      I1 => \r_reg_n_0_[45]\,
      I2 => \rexp[1]_i_36_n_0\,
      I3 => \r_reg_n_0_[13]\,
      I4 => \rexp[1]_i_34_n_0\,
      I5 => \r_reg_n_0_[29]\,
      O => \rexp[1]_i_29_n_0\
    );
\rexp[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800B800B8FFB800"
    )
        port map (
      I0 => \rexp[1]_i_10_n_0\,
      I1 => \msb[1]_i_1_n_0\,
      I2 => \rexp[1]_i_11_n_0\,
      I3 => \msb[0]_i_1_n_0\,
      I4 => \rexp[1]_i_12_n_0\,
      I5 => \rexp[1]_i_13_n_0\,
      O => \rexp[1]_i_3_n_0\
    );
\rexp[1]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => \r_reg_n_0_[21]\,
      I1 => \rexp[1]_i_34_n_0\,
      I2 => \r_reg_n_0_[37]\,
      I3 => \rexp[1]_i_35_n_0\,
      I4 => \r_reg_n_0_[5]\,
      I5 => \rexp[1]_i_23_n_0\,
      O => \rexp[1]_i_30_n_0\
    );
\rexp[1]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5554445411100010"
    )
        port map (
      I0 => shift(3),
      I1 => shift(4),
      I2 => \r_reg_n_0_[1]\,
      I3 => shift(5),
      I4 => \r_reg_n_0_[33]\,
      I5 => \r_reg_n_0_[17]\,
      O => \rexp[1]_i_32_n_0\
    );
\rexp[1]_i_33\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE200E200000000"
    )
        port map (
      I0 => \r_reg_n_0_[9]\,
      I1 => shift(5),
      I2 => \r_reg_n_0_[41]\,
      I3 => shift(4),
      I4 => \r_reg_n_0_[25]\,
      I5 => shift(3),
      O => \rexp[1]_i_33_n_0\
    );
\rexp[1]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \msb[4]_i_2_n_0\,
      I1 => \msb[1]_i_1_n_0\,
      I2 => \msb[2]_i_1_n_0\,
      I3 => \msb[3]_i_1_n_0\,
      O => \rexp[1]_i_34_n_0\
    );
\rexp[1]_i_35\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA6"
    )
        port map (
      I0 => \msb[5]_i_3_n_0\,
      I1 => \msb[4]_i_2_n_0\,
      I2 => \msb[3]_i_1_n_0\,
      I3 => \msb[2]_i_1_n_0\,
      I4 => \msb[1]_i_1_n_0\,
      O => \rexp[1]_i_35_n_0\
    );
\rexp[1]_i_36\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55555559"
    )
        port map (
      I0 => \msb[5]_i_3_n_0\,
      I1 => \msb[4]_i_2_n_0\,
      I2 => \msb[3]_i_1_n_0\,
      I3 => \msb[2]_i_1_n_0\,
      I4 => \msb[1]_i_1_n_0\,
      O => \rexp[1]_i_36_n_0\
    );
\rexp[1]_i_37\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"470047FF"
    )
        port map (
      I0 => \r_reg_n_0_[1]\,
      I1 => \rexp[1]_i_35_n_0\,
      I2 => \r_reg_n_0_[33]\,
      I3 => \rexp[1]_i_34_n_0\,
      I4 => \r_reg_n_0_[17]\,
      O => \rexp[1]_i_37_n_0\
    );
\rexp[1]_i_38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"111F0000111FFFFF"
    )
        port map (
      I0 => \rexp[1]_i_35_n_0\,
      I1 => \r_reg_n_0_[41]\,
      I2 => \rexp[1]_i_36_n_0\,
      I3 => \r_reg_n_0_[9]\,
      I4 => \rexp[1]_i_34_n_0\,
      I5 => \r_reg_n_0_[25]\,
      O => \rexp[1]_i_38_n_0\
    );
\rexp[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF80"
    )
        port map (
      I0 => \msb[5]_i_3_n_0\,
      I1 => \rshift[4]_i_3_n_0\,
      I2 => \rexp[7]_i_21_n_0\,
      I3 => \rexp[0]_i_5_n_0\,
      O => \rexp[1]_i_4_n_0\
    );
\rexp[1]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \msb[5]_i_3_n_0\,
      I1 => \rshift[4]_i_3_n_0\,
      I2 => \rexp[7]_i_21_n_0\,
      I3 => \r_reg_n_0_[1]\,
      O => \rexp[1]_i_5_n_0\
    );
\rexp[1]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => linNotLog_reg_n_0,
      O => \rexp[1]_i_6_n_0\
    );
\rexp[1]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2E"
    )
        port map (
      I0 => \rexp[1]_i_14_n_0\,
      I1 => shift(0),
      I2 => \rexp[2]_i_3_n_0\,
      O => \rexp[1]_i_7_n_0\
    );
\rexp[1]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \msb[5]_i_3_n_0\,
      I1 => \rexp[7]_i_37_n_0\,
      I2 => shift(4),
      I3 => shift(5),
      O => \rexp[1]_i_8_n_0\
    );
\rexp[1]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4111F11F"
    )
        port map (
      I0 => \msb[5]_i_3_n_0\,
      I1 => shift(5),
      I2 => shift(4),
      I3 => \rexp[7]_i_37_n_0\,
      I4 => \msb[4]_i_2_n_0\,
      O => \rexp[1]_i_9_n_0\
    );
\rexp[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFB80000"
    )
        port map (
      I0 => \rexp[2]_i_2_n_0\,
      I1 => shift(0),
      I2 => \rexp[2]_i_3_n_0\,
      I3 => \rexp[7]_i_3_n_0\,
      I4 => \rexp[7]_i_4_n_0\,
      I5 => \rexp[2]_i_4_n_0\,
      O => \rexp[2]_i_1_n_0\
    );
\rexp[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rexp[5]_i_4_n_0\,
      I1 => shift(1),
      I2 => \rexp[2]_i_5_n_0\,
      O => \rexp[2]_i_2_n_0\
    );
\rexp[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rexp[4]_i_4_n_0\,
      I1 => shift(1),
      I2 => \rexp[2]_i_6_n_0\,
      O => \rexp[2]_i_3_n_0\
    );
\rexp[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000007F00"
    )
        port map (
      I0 => \msb[5]_i_3_n_0\,
      I1 => \rshift[4]_i_3_n_0\,
      I2 => \rexp[7]_i_21_n_0\,
      I3 => \stateScore_reg_rep__0_n_0\,
      I4 => linNotLog_reg_n_0,
      I5 => \msb[0]_i_1_n_0\,
      O => \rexp[2]_i_4_n_0\
    );
\rexp[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFB0BFBFBFB0B0B0"
    )
        port map (
      I0 => \rexp[7]_i_26_n_0\,
      I1 => \rexp[7]_i_27_n_0\,
      I2 => shift(2),
      I3 => \rexp[7]_i_29_n_0\,
      I4 => shift(3),
      I5 => \rexp[2]_i_7_n_0\,
      O => \rexp[2]_i_5_n_0\
    );
\rexp[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8B8B8B8FFCCFF00"
    )
        port map (
      I0 => \rexp[7]_i_34_n_0\,
      I1 => shift(3),
      I2 => \rexp[6]_i_6_n_0\,
      I3 => \rexp[2]_i_8_n_0\,
      I4 => \rexp[2]_i_9_n_0\,
      I5 => shift(2),
      O => \rexp[2]_i_6_n_0\
    );
\rexp[2]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \r_reg_n_0_[19]\,
      I1 => shift(4),
      I2 => \r_reg_n_0_[35]\,
      I3 => shift(5),
      I4 => \r_reg_n_0_[3]\,
      O => \rexp[2]_i_7_n_0\
    );
\rexp[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => \r_reg_n_0_[2]\,
      I1 => shift(5),
      I2 => \r_reg_n_0_[34]\,
      I3 => shift(4),
      I4 => \r_reg_n_0_[18]\,
      I5 => shift(3),
      O => \rexp[2]_i_8_n_0\
    );
\rexp[2]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \r_reg_n_0_[26]\,
      I1 => shift(4),
      I2 => \r_reg_n_0_[42]\,
      I3 => shift(5),
      I4 => \r_reg_n_0_[10]\,
      O => \rexp[2]_i_9_n_0\
    );
\rexp[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF9F9999FF0F0000"
    )
        port map (
      I0 => \msb[1]_i_1_n_0\,
      I1 => \msb[0]_i_1_n_0\,
      I2 => \rexp[3]_i_2_n_0\,
      I3 => \rexp[7]_i_3_n_0\,
      I4 => \rexp[7]_i_4_n_0\,
      I5 => \rexp[7]_i_6_n_0\,
      O => \rexp[3]_i_1_n_0\
    );
\rexp[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"474700FF"
    )
        port map (
      I0 => \rexp[6]_i_5_n_0\,
      I1 => shift(1),
      I2 => \rexp[4]_i_4_n_0\,
      I3 => \rexp[2]_i_2_n_0\,
      I4 => shift(0),
      O => \rexp[3]_i_2_n_0\
    );
\rexp[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D0FFD0D0"
    )
        port map (
      I0 => \rexp[4]_i_2_n_0\,
      I1 => \rexp[7]_i_3_n_0\,
      I2 => \rexp[7]_i_4_n_0\,
      I3 => \rexp[4]_i_3_n_0\,
      I4 => \rexp[7]_i_6_n_0\,
      O => \rexp[4]_i_1_n_0\
    );
\rexp[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B8B8B8B00CC33FF"
    )
        port map (
      I0 => \rexp[7]_i_8_n_0\,
      I1 => shift(1),
      I2 => \rexp[5]_i_4_n_0\,
      I3 => \rexp[6]_i_5_n_0\,
      I4 => \rexp[4]_i_4_n_0\,
      I5 => shift(0),
      O => \rexp[4]_i_2_n_0\
    );
\rexp[4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"56"
    )
        port map (
      I0 => \msb[2]_i_1_n_0\,
      I1 => \msb[0]_i_1_n_0\,
      I2 => \msb[1]_i_1_n_0\,
      O => \rexp[4]_i_3_n_0\
    );
\rexp[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \rexp[7]_i_30_n_0\,
      I1 => shift(3),
      I2 => \rexp[7]_i_31_n_0\,
      I3 => shift(2),
      I4 => \rexp[4]_i_5_n_0\,
      O => \rexp[4]_i_4_n_0\
    );
\rexp[4]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rexp[7]_i_33_n_0\,
      I1 => shift(3),
      I2 => \rexp[4]_i_6_n_0\,
      O => \rexp[4]_i_5_n_0\
    );
\rexp[4]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \r_reg_n_0_[20]\,
      I1 => shift(4),
      I2 => \r_reg_n_0_[36]\,
      I3 => shift(5),
      I4 => \r_reg_n_0_[4]\,
      O => \rexp[4]_i_6_n_0\
    );
\rexp[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D0FFD0D0"
    )
        port map (
      I0 => \rexp[5]_i_2_n_0\,
      I1 => \rexp[7]_i_3_n_0\,
      I2 => \rexp[7]_i_4_n_0\,
      I3 => \rexp[5]_i_3_n_0\,
      I4 => \rexp[7]_i_6_n_0\,
      O => \rexp[5]_i_1_n_0\
    );
\rexp[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00CC33FF8B8B8B8B"
    )
        port map (
      I0 => \rexp[7]_i_8_n_0\,
      I1 => shift(1),
      I2 => \rexp[5]_i_4_n_0\,
      I3 => \rexp[7]_i_9_n_0\,
      I4 => \rexp[6]_i_5_n_0\,
      I5 => shift(0),
      O => \rexp[5]_i_2_n_0\
    );
\rexp[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F1E"
    )
        port map (
      I0 => \msb[1]_i_1_n_0\,
      I1 => \msb[2]_i_1_n_0\,
      I2 => \msb[3]_i_1_n_0\,
      I3 => \msb[0]_i_1_n_0\,
      O => \rexp[5]_i_3_n_0\
    );
\rexp[5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \rexp[7]_i_22_n_0\,
      I1 => shift(3),
      I2 => \rexp[7]_i_23_n_0\,
      I3 => shift(2),
      I4 => \rexp[5]_i_5_n_0\,
      O => \rexp[5]_i_4_n_0\
    );
\rexp[5]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rexp[7]_i_25_n_0\,
      I1 => shift(3),
      I2 => \rexp[5]_i_6_n_0\,
      O => \rexp[5]_i_5_n_0\
    );
\rexp[5]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \r_reg_n_0_[21]\,
      I1 => shift(4),
      I2 => \r_reg_n_0_[37]\,
      I3 => shift(5),
      I4 => \r_reg_n_0_[5]\,
      O => \rexp[5]_i_6_n_0\
    );
\rexp[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF4F4444"
    )
        port map (
      I0 => \rexp[6]_i_2_n_0\,
      I1 => \rexp[6]_i_3_n_0\,
      I2 => \rexp[6]_i_4_n_0\,
      I3 => \rexp[7]_i_3_n_0\,
      I4 => \rexp[7]_i_4_n_0\,
      O => \rexp[6]_i_1_n_0\
    );
\rexp[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A6FF"
    )
        port map (
      I0 => \msb[4]_i_2_n_0\,
      I1 => \rexp[7]_i_21_n_0\,
      I2 => \msb[0]_i_1_n_0\,
      I3 => \stateScore_reg_rep__0_n_0\,
      O => \rexp[6]_i_2_n_0\
    );
\rexp[6]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000007F"
    )
        port map (
      I0 => \msb[5]_i_3_n_0\,
      I1 => \rshift[4]_i_3_n_0\,
      I2 => \rexp[7]_i_21_n_0\,
      I3 => linNotLog_reg_n_0,
      I4 => \rexp[0]_i_5_n_0\,
      O => \rexp[6]_i_3_n_0\
    );
\rexp[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8B8B8B800CC33FF"
    )
        port map (
      I0 => \rexp[7]_i_7_n_0\,
      I1 => shift(1),
      I2 => \rexp[7]_i_8_n_0\,
      I3 => \rexp[7]_i_9_n_0\,
      I4 => \rexp[6]_i_5_n_0\,
      I5 => shift(0),
      O => \rexp[6]_i_4_n_0\
    );
\rexp[6]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF00B8B8"
    )
        port map (
      I0 => \rexp[7]_i_34_n_0\,
      I1 => shift(3),
      I2 => \rexp[6]_i_6_n_0\,
      I3 => \rexp[7]_i_36_n_0\,
      I4 => shift(2),
      O => \rexp[6]_i_5_n_0\
    );
\rexp[6]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \r_reg_n_0_[22]\,
      I1 => shift(4),
      I2 => \r_reg_n_0_[38]\,
      I3 => shift(5),
      I4 => \r_reg_n_0_[6]\,
      O => \rexp[6]_i_6_n_0\
    );
\rexp[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFD0D0FFD0D0D0D0"
    )
        port map (
      I0 => \rexp[7]_i_2_n_0\,
      I1 => \rexp[7]_i_3_n_0\,
      I2 => \rexp[7]_i_4_n_0\,
      I3 => \msb[5]_i_3_n_0\,
      I4 => \rexp[7]_i_5_n_0\,
      I5 => \rexp[7]_i_6_n_0\,
      O => \rexp[7]_i_1_n_0\
    );
\rexp[7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FD5DFFFFFD5D5555"
    )
        port map (
      I0 => shift(1),
      I1 => \rexp[7]_i_34_n_0\,
      I2 => shift(3),
      I3 => \rexp[7]_i_35_n_0\,
      I4 => shift(2),
      I5 => \rexp[7]_i_36_n_0\,
      O => \rexp[7]_i_10_n_0\
    );
\rexp[7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B2BBB2BB22B2B2BB"
    )
        port map (
      I0 => \msb[2]_i_1_n_0\,
      I1 => shift(2),
      I2 => \msb[1]_i_1_n_0\,
      I3 => shift(1),
      I4 => shift(0),
      I5 => \msb[0]_i_1_n_0\,
      O => \rexp[7]_i_11_n_0\
    );
\rexp[7]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"77777770"
    )
        port map (
      I0 => \msb[3]_i_1_n_0\,
      I1 => shift(3),
      I2 => shift(0),
      I3 => shift(1),
      I4 => shift(2),
      O => \rexp[7]_i_12_n_0\
    );
\rexp[7]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4444FF8F"
    )
        port map (
      I0 => shift(4),
      I1 => \msb[4]_i_2_n_0\,
      I2 => \msb[3]_i_1_n_0\,
      I3 => shift(3),
      I4 => \rexp[7]_i_37_n_0\,
      O => \rexp[7]_i_13_n_0\
    );
\rexp[7]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444011111115"
    )
        port map (
      I0 => \msb[4]_i_2_n_0\,
      I1 => shift(3),
      I2 => shift(0),
      I3 => shift(1),
      I4 => shift(2),
      I5 => shift(4),
      O => \rexp[7]_i_14_n_0\
    );
\rexp[7]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9595959595959555"
    )
        port map (
      I0 => shift(5),
      I1 => shift(4),
      I2 => shift(3),
      I3 => shift(0),
      I4 => shift(1),
      I5 => shift(2),
      O => \rexp[7]_i_15_n_0\
    );
\rexp[7]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"444F"
    )
        port map (
      I0 => shift(3),
      I1 => \msb[3]_i_1_n_0\,
      I2 => \msb[4]_i_2_n_0\,
      I3 => shift(4),
      O => \rexp[7]_i_16_n_0\
    );
\rexp[7]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => shift(3),
      I1 => \msb[3]_i_1_n_0\,
      O => \rexp[7]_i_17_n_0\
    );
\rexp[7]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => shift(5),
      I1 => \msb[5]_i_3_n_0\,
      I2 => shift(4),
      I3 => \msb[4]_i_2_n_0\,
      O => \rexp[7]_i_18_n_0\
    );
\rexp[7]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => shift(5),
      I1 => \msb[5]_i_3_n_0\,
      O => \rexp[7]_i_19_n_0\
    );
\rexp[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0033FFFFB8B8B8B8"
    )
        port map (
      I0 => \rexp[7]_i_7_n_0\,
      I1 => shift(1),
      I2 => \rexp[7]_i_8_n_0\,
      I3 => \rexp[7]_i_9_n_0\,
      I4 => \rexp[7]_i_10_n_0\,
      I5 => shift(0),
      O => \rexp[7]_i_2_n_0\
    );
\rexp[7]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF40000000"
    )
        port map (
      I0 => \msb[5]_i_3_n_0\,
      I1 => \msb[4]_i_2_n_0\,
      I2 => \rshift[5]_i_4_n_0\,
      I3 => \msb[0]_i_1_n_0\,
      I4 => \msb[3]_i_1_n_0\,
      I5 => \rexp[7]_i_38_n_0\,
      O => \rexp[7]_i_20_n_0\
    );
\rexp[7]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \msb[3]_i_1_n_0\,
      I1 => \msb[2]_i_1_n_0\,
      I2 => \msb[1]_i_1_n_0\,
      O => \rexp[7]_i_21_n_0\
    );
\rexp[7]_i_22\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \r_reg_n_0_[1]\,
      I1 => shift(5),
      I2 => \r_reg_n_0_[33]\,
      I3 => shift(4),
      I4 => \r_reg_n_0_[17]\,
      O => \rexp[7]_i_22_n_0\
    );
\rexp[7]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \r_reg_n_0_[25]\,
      I1 => shift(4),
      I2 => \r_reg_n_0_[41]\,
      I3 => shift(5),
      I4 => \r_reg_n_0_[9]\,
      O => \rexp[7]_i_23_n_0\
    );
\rexp[7]_i_24\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \r_reg_n_0_[5]\,
      I1 => shift(5),
      I2 => \r_reg_n_0_[37]\,
      I3 => shift(4),
      I4 => \r_reg_n_0_[21]\,
      O => \rexp[7]_i_24_n_0\
    );
\rexp[7]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \r_reg_n_0_[29]\,
      I1 => shift(4),
      I2 => \r_reg_n_0_[45]\,
      I3 => shift(5),
      I4 => \r_reg_n_0_[13]\,
      O => \rexp[7]_i_25_n_0\
    );
\rexp[7]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => \r_reg_n_0_[7]\,
      I1 => shift(5),
      I2 => \r_reg_n_0_[39]\,
      I3 => shift(4),
      I4 => \r_reg_n_0_[23]\,
      I5 => shift(3),
      O => \rexp[7]_i_26_n_0\
    );
\rexp[7]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555557F7FFFF57F7"
    )
        port map (
      I0 => shift(3),
      I1 => \r_reg_n_0_[15]\,
      I2 => shift(5),
      I3 => \r_reg_n_0_[47]\,
      I4 => shift(4),
      I5 => \r_reg_n_0_[31]\,
      O => \rexp[7]_i_27_n_0\
    );
\rexp[7]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \r_reg_n_0_[19]\,
      I1 => shift(4),
      I2 => \r_reg_n_0_[35]\,
      I3 => shift(5),
      I4 => \r_reg_n_0_[3]\,
      I5 => shift(3),
      O => \rexp[7]_i_28_n_0\
    );
\rexp[7]_i_29\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \r_reg_n_0_[27]\,
      I1 => shift(4),
      I2 => \r_reg_n_0_[43]\,
      I3 => shift(5),
      I4 => \r_reg_n_0_[11]\,
      O => \rexp[7]_i_29_n_0\
    );
\rexp[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0B0000FFFFFF0B"
    )
        port map (
      I0 => \rexp[7]_i_11_n_0\,
      I1 => \rexp[7]_i_12_n_0\,
      I2 => \rexp[7]_i_13_n_0\,
      I3 => \rexp[7]_i_14_n_0\,
      I4 => \rexp[7]_i_15_n_0\,
      I5 => \msb[5]_i_3_n_0\,
      O => \rexp[7]_i_3_n_0\
    );
\rexp[7]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \r_reg_n_0_[0]\,
      I1 => shift(5),
      I2 => \r_reg_n_0_[32]\,
      I3 => shift(4),
      I4 => \r_reg_n_0_[16]\,
      O => \rexp[7]_i_30_n_0\
    );
\rexp[7]_i_31\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \r_reg_n_0_[24]\,
      I1 => shift(4),
      I2 => \r_reg_n_0_[40]\,
      I3 => shift(5),
      I4 => \r_reg_n_0_[8]\,
      O => \rexp[7]_i_31_n_0\
    );
\rexp[7]_i_32\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \r_reg_n_0_[4]\,
      I1 => shift(5),
      I2 => \r_reg_n_0_[36]\,
      I3 => shift(4),
      I4 => \r_reg_n_0_[20]\,
      O => \rexp[7]_i_32_n_0\
    );
\rexp[7]_i_33\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \r_reg_n_0_[28]\,
      I1 => shift(4),
      I2 => \r_reg_n_0_[44]\,
      I3 => shift(5),
      I4 => \r_reg_n_0_[12]\,
      O => \rexp[7]_i_33_n_0\
    );
\rexp[7]_i_34\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \r_reg_n_0_[30]\,
      I1 => shift(4),
      I2 => \r_reg_n_0_[46]\,
      I3 => shift(5),
      I4 => \r_reg_n_0_[14]\,
      O => \rexp[7]_i_34_n_0\
    );
\rexp[7]_i_35\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \r_reg_n_0_[6]\,
      I1 => shift(5),
      I2 => \r_reg_n_0_[38]\,
      I3 => shift(4),
      I4 => \r_reg_n_0_[22]\,
      O => \rexp[7]_i_35_n_0\
    );
\rexp[7]_i_36\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rexp[7]_i_39_n_0\,
      I1 => shift(3),
      I2 => \rexp[2]_i_9_n_0\,
      O => \rexp[7]_i_36_n_0\
    );
\rexp[7]_i_37\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => shift(3),
      I1 => shift(0),
      I2 => shift(1),
      I3 => shift(2),
      O => \rexp[7]_i_37_n_0\
    );
\rexp[7]_i_38\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => linNotLog_reg_n_0,
      O => \rexp[7]_i_38_n_0\
    );
\rexp[7]_i_39\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \r_reg_n_0_[2]\,
      I1 => shift(5),
      I2 => \r_reg_n_0_[34]\,
      I3 => shift(4),
      I4 => \r_reg_n_0_[18]\,
      O => \rexp[7]_i_39_n_0\
    );
\rexp[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF00AE"
    )
        port map (
      I0 => \rexp[7]_i_16_n_0\,
      I1 => \rexp[7]_i_11_n_0\,
      I2 => \rexp[7]_i_17_n_0\,
      I3 => \rexp[7]_i_18_n_0\,
      I4 => \rexp[7]_i_19_n_0\,
      I5 => \rexp[7]_i_20_n_0\,
      O => \rexp[7]_i_4_n_0\
    );
\rexp[7]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \msb[4]_i_2_n_0\,
      I1 => \rexp[7]_i_21_n_0\,
      I2 => \msb[0]_i_1_n_0\,
      O => \rexp[7]_i_5_n_0\
    );
\rexp[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000007F00000000"
    )
        port map (
      I0 => \msb[5]_i_3_n_0\,
      I1 => \rshift[4]_i_3_n_0\,
      I2 => \rexp[7]_i_21_n_0\,
      I3 => \rexp[0]_i_5_n_0\,
      I4 => linNotLog_reg_n_0,
      I5 => \stateScore_reg_rep__0_n_0\,
      O => \rexp[7]_i_6_n_0\
    );
\rexp[7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0047CC473347FF47"
    )
        port map (
      I0 => \rexp[7]_i_22_n_0\,
      I1 => shift(3),
      I2 => \rexp[7]_i_23_n_0\,
      I3 => shift(2),
      I4 => \rexp[7]_i_24_n_0\,
      I5 => \rexp[7]_i_25_n_0\,
      O => \rexp[7]_i_7_n_0\
    );
\rexp[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F000F44444444"
    )
        port map (
      I0 => \rexp[7]_i_26_n_0\,
      I1 => \rexp[7]_i_27_n_0\,
      I2 => \rexp[7]_i_28_n_0\,
      I3 => \rexp[7]_i_29_n_0\,
      I4 => shift(3),
      I5 => shift(2),
      O => \rexp[7]_i_8_n_0\
    );
\rexp[7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF33CC00B8B8B8B8"
    )
        port map (
      I0 => \rexp[7]_i_30_n_0\,
      I1 => shift(3),
      I2 => \rexp[7]_i_31_n_0\,
      I3 => \rexp[7]_i_32_n_0\,
      I4 => \rexp[7]_i_33_n_0\,
      I5 => shift(2),
      O => \rexp[7]_i_9_n_0\
    );
\rexp_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \rexp[0]_i_1_n_0\,
      Q => \rexp_reg_n_0_[0]\
    );
\rexp_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \rexp[1]_i_1_n_0\,
      Q => \rexp_reg_n_0_[1]\
    );
\rexp_reg[1]_i_31\: unisim.vcomponents.MUXF7
     port map (
      I0 => \rexp[1]_i_37_n_0\,
      I1 => \rexp[1]_i_38_n_0\,
      O => \rexp_reg[1]_i_31_n_0\,
      S => \rexp[1]_i_23_n_0\
    );
\rexp_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \rexp[2]_i_1_n_0\,
      Q => \rexp_reg_n_0_[2]\
    );
\rexp_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \rexp[3]_i_1_n_0\,
      Q => \rexp_reg_n_0_[3]\
    );
\rexp_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \rexp[4]_i_1_n_0\,
      Q => \rexp_reg_n_0_[4]\
    );
\rexp_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \rexp[5]_i_1_n_0\,
      Q => \rexp_reg_n_0_[5]\
    );
\rexp_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \rexp[6]_i_1_n_0\,
      Q => \rexp_reg_n_0_[6]\
    );
\rexp_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \rexp[7]_i_1_n_0\,
      Q => \rexp_reg_n_0_[7]\
    );
rng_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => rng_reg_2,
      Q => \^rng_reg_0\
    );
\row0_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(3),
      Q => row0(0)
    );
\row0_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(13),
      Q => row0(10)
    );
\row0_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(4),
      Q => row0(1)
    );
\row0_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(5),
      Q => row0(2)
    );
\row0_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(6),
      Q => row0(3)
    );
\row0_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(7),
      Q => row0(4)
    );
\row0_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(8),
      Q => row0(5)
    );
\row0_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(9),
      Q => row0(6)
    );
\row0_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(10),
      Q => row0(7)
    );
\row0_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(11),
      Q => row0(8)
    );
\row0_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(12),
      Q => row0(9)
    );
\row1_reg[0]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \row1_reg[7]_0\(0),
      PRE => linNotLog_reg_0,
      Q => row1(0)
    );
\row1_reg[10]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \thd_reg[7]_0\(2),
      PRE => linNotLog_reg_0,
      Q => row1(10)
    );
\row1_reg[1]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \row1_reg[7]_0\(1),
      PRE => linNotLog_reg_0,
      Q => row1(1)
    );
\row1_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \row1_reg[7]_0\(2),
      Q => row1(2)
    );
\row1_reg[3]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \row1_reg[7]_0\(3),
      PRE => linNotLog_reg_0,
      Q => row1(3)
    );
\row1_reg[4]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \row1_reg[7]_0\(4),
      PRE => linNotLog_reg_0,
      Q => row1(4)
    );
\row1_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \row1_reg[7]_0\(5),
      Q => row1(5)
    );
\row1_reg[6]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \row1_reg[7]_0\(6),
      PRE => linNotLog_reg_0,
      Q => row1(6)
    );
\row1_reg[7]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \row1_reg[7]_0\(7),
      PRE => linNotLog_reg_0,
      Q => row1(7)
    );
\row1_reg[8]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \thd_reg[7]_0\(0),
      PRE => linNotLog_reg_0,
      Q => row1(8)
    );
\row1_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(1),
      Q => row1(9)
    );
\row_lcl[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => row_lcl_reg(0),
      O => p_0_in(0)
    );
\row_lcl[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F5F"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[0]\,
      I1 => enCoobuf_reg_0,
      I2 => \^rng_reg_0\,
      I3 => \stateMaxsel_reg_n_0_[1]\,
      O => \row_lcl[10]_i_1_n_0\
    );
\row_lcl[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00A8A8A8A8000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => \^q\(6),
      I4 => \row_lcl[10]_i_3_n_0\,
      I5 => \^q\(7),
      O => p_0_in(10)
    );
\row_lcl[10]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \row_lcl[9]_i_2_n_0\,
      I2 => \^q\(3),
      I3 => \^q\(5),
      O => \row_lcl[10]_i_3_n_0\
    );
\row_lcl[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00A8A800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => row_lcl_reg(0),
      I4 => row_lcl_reg(1),
      O => p_0_in(1)
    );
\row_lcl[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00A8A8A8A8000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => row_lcl_reg(1),
      I4 => row_lcl_reg(0),
      I5 => row_lcl_reg(2),
      O => p_0_in(2)
    );
\row_lcl[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \col_lcl[8]__0_i_2_n_0\,
      I1 => row_lcl_reg(0),
      I2 => row_lcl_reg(1),
      I3 => row_lcl_reg(2),
      I4 => \^q\(0),
      O => p_0_in(3)
    );
\row_lcl[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \col_lcl[8]__0_i_2_n_0\,
      I1 => row_lcl_reg(2),
      I2 => row_lcl_reg(1),
      I3 => row_lcl_reg(0),
      I4 => \^q\(0),
      I5 => \^q\(1),
      O => p_0_in(4)
    );
\row_lcl[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00A8A800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => \row_lcl[5]_i_2_n_0\,
      I4 => \^q\(2),
      O => p_0_in(5)
    );
\row_lcl[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => row_lcl_reg(0),
      I2 => row_lcl_reg(1),
      I3 => row_lcl_reg(2),
      I4 => \^q\(1),
      O => \row_lcl[5]_i_2_n_0\
    );
\row_lcl[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00A8A800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => \row_lcl[9]_i_2_n_0\,
      I4 => \^q\(3),
      O => p_0_in(6)
    );
\row_lcl[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00A8A8A8A8000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel_reg_n_0_[1]\,
      I2 => \stateMaxsel_reg_n_0_[0]\,
      I3 => \row_lcl[9]_i_2_n_0\,
      I4 => \^q\(3),
      I5 => \^q\(4),
      O => p_0_in(7)
    );
\row_lcl[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \col_lcl[8]__0_i_2_n_0\,
      I1 => \^q\(3),
      I2 => \row_lcl[9]_i_2_n_0\,
      I3 => \^q\(4),
      I4 => \^q\(5),
      O => p_0_in(8)
    );
\row_lcl[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF800000000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \row_lcl[9]_i_2_n_0\,
      I2 => \^q\(3),
      I3 => \^q\(5),
      I4 => \^q\(6),
      I5 => \col_lcl[8]__0_i_2_n_0\,
      O => \row_lcl[9]_i_1_n_0\
    );
\row_lcl[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => row_lcl_reg(2),
      I2 => row_lcl_reg(1),
      I3 => row_lcl_reg(0),
      I4 => \^q\(0),
      I5 => \^q\(2),
      O => \row_lcl[9]_i_2_n_0\
    );
\row_lcl_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \row_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => p_0_in(0),
      Q => row_lcl_reg(0)
    );
\row_lcl_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \row_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => p_0_in(10),
      Q => \^q\(7)
    );
\row_lcl_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \row_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => p_0_in(1),
      Q => row_lcl_reg(1)
    );
\row_lcl_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \row_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => p_0_in(2),
      Q => row_lcl_reg(2)
    );
\row_lcl_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \row_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => p_0_in(3),
      Q => \^q\(0)
    );
\row_lcl_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \row_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => p_0_in(4),
      Q => \^q\(1)
    );
\row_lcl_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \row_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => p_0_in(5),
      Q => \^q\(2)
    );
\row_lcl_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \row_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => p_0_in(6),
      Q => \^q\(3)
    );
\row_lcl_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \row_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => p_0_in(7),
      Q => \^q\(4)
    );
\row_lcl_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \row_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => p_0_in(8),
      Q => \^q\(5)
    );
\row_lcl_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \row_lcl[10]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \row_lcl[9]_i_1_n_0\,
      Q => \^q\(6)
    );
\rshift[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rshift[4]_i_2_n_0\,
      I1 => \msb[0]_i_1_n_0\,
      O => \rshift[0]_i_1_n_0\
    );
\rshift[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \msb[1]_i_1_n_0\,
      I1 => \msb[0]_i_1_n_0\,
      I2 => \rshift[4]_i_2_n_0\,
      O => \rshift[1]_i_1_n_0\
    );
\rshift[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \rshift[4]_i_2_n_0\,
      I1 => \msb[0]_i_1_n_0\,
      I2 => \msb[1]_i_1_n_0\,
      I3 => \msb[2]_i_1_n_0\,
      O => \rshift[2]_i_1_n_0\
    );
\rshift[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \msb[3]_i_1_n_0\,
      I1 => \rshift[5]_i_3_n_0\,
      I2 => \rshift[4]_i_2_n_0\,
      O => \rshift[3]_i_1_n_0\
    );
\rshift[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"10E0"
    )
        port map (
      I0 => \msb[3]_i_1_n_0\,
      I1 => \rshift[5]_i_3_n_0\,
      I2 => \rshift[4]_i_2_n_0\,
      I3 => \msb[4]_i_2_n_0\,
      O => \rshift[4]_i_1_n_0\
    );
\rshift[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0F0F070F0F0F070"
    )
        port map (
      I0 => \msb[5]_i_3_n_0\,
      I1 => \rshift[4]_i_3_n_0\,
      I2 => \stateScore_reg_rep__0_n_0\,
      I3 => \rshift[5]_i_3_n_0\,
      I4 => \msb[3]_i_1_n_0\,
      I5 => \msb[4]_i_2_n_0\,
      O => \rshift[4]_i_2_n_0\
    );
\rshift[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055555155"
    )
        port map (
      I0 => \msb[3]_i_3_n_0\,
      I1 => \msb[4]_i_5_n_0\,
      I2 => \rshift[4]_i_4_n_0\,
      I3 => msb(4),
      I4 => \msb[4]_i_3_n_0\,
      I5 => \msb[3]_i_5_n_0\,
      O => \rshift[4]_i_3_n_0\
    );
\rshift[4]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \r_reg_n_0_[0]\,
      I1 => \r_reg_n_0_[1]\,
      O => \rshift[4]_i_4_n_0\
    );
\rshift[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B3"
    )
        port map (
      I0 => ceScore,
      I1 => \stateScore_reg_rep__0_n_0\,
      I2 => linNotLog_reg_n_0,
      O => \rshift[5]_i_1_n_0\
    );
\rshift[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006F00"
    )
        port map (
      I0 => \msb[3]_i_1_n_0\,
      I1 => \rshift[5]_i_3_n_0\,
      I2 => \msb[4]_i_2_n_0\,
      I3 => \stateScore_reg_rep__0_n_0\,
      I4 => \msb[5]_i_3_n_0\,
      O => \rshift[5]_i_2_n_0\
    );
\rshift[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \msb[0]_i_1_n_0\,
      I1 => \rshift[5]_i_4_n_0\,
      O => \rshift[5]_i_3_n_0\
    );
\rshift[5]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \msb[1]_i_1_n_0\,
      I1 => \msb[2]_i_1_n_0\,
      O => \rshift[5]_i_4_n_0\
    );
\rshift_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rshift[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \rshift[0]_i_1_n_0\,
      Q => \rshift__0\(0)
    );
\rshift_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rshift[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \rshift[1]_i_1_n_0\,
      Q => \rshift__0\(1)
    );
\rshift_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rshift[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \rshift[2]_i_1_n_0\,
      Q => \rshift__0\(2)
    );
\rshift_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rshift[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \rshift[3]_i_1_n_0\,
      Q => \rshift__0\(3)
    );
\rshift_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rshift[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \rshift[4]_i_1_n_0\,
      Q => \rshift__0\(4)
    );
\rshift_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rshift[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \rshift[5]_i_2_n_0\,
      Q => \rshift__0\(5)
    );
\scoreMax[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \scoreMax_lcl__0\(0),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax[0]_i_1_n_0\
    );
\scoreMax[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \scoreMax_lcl__0\(1),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax[1]_i_1_n_0\
    );
\scoreMax[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \scoreMax_lcl__0\(2),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax[2]_i_1_n_0\
    );
\scoreMax[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \scoreMax_lcl__0\(3),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax[3]_i_1_n_0\
    );
\scoreMax[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \scoreMax_lcl__0\(4),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax[4]_i_1_n_0\
    );
\scoreMax[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \scoreMax_lcl__0\(5),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax[5]_i_1_n_0\
    );
\scoreMax[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \scoreMax_lcl__0\(6),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax[6]_i_1_n_0\
    );
\scoreMax[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \scoreMax_lcl__0\(7),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax[7]_i_1_n_0\
    );
\scoreMax_lcl[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \rexp_reg_n_0_[0]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax_lcl[0]_i_1_n_0\
    );
\scoreMax_lcl[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \rexp_reg_n_0_[1]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax_lcl[1]_i_1_n_0\
    );
\scoreMax_lcl[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \rexp_reg_n_0_[2]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax_lcl[2]_i_1_n_0\
    );
\scoreMax_lcl[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \rexp_reg_n_0_[3]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax_lcl[3]_i_1_n_0\
    );
\scoreMax_lcl[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \rexp_reg_n_0_[4]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax_lcl[4]_i_1_n_0\
    );
\scoreMax_lcl[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \rexp_reg_n_0_[5]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax_lcl[5]_i_1_n_0\
    );
\scoreMax_lcl[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \rexp_reg_n_0_[6]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax_lcl[6]_i_1_n_0\
    );
\scoreMax_lcl[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555D555F5555555F"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => scoreMax_lcl0,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \stateImdstream_reg_n_0_[1]\,
      I5 => ceScore,
      O => \scoreMax_lcl[7]_i_1_n_0\
    );
\scoreMax_lcl[7]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \scoreMax_lcl__0\(3),
      I1 => \rexp_reg_n_0_[3]\,
      I2 => \scoreMax_lcl__0\(2),
      I3 => \rexp_reg_n_0_[2]\,
      O => \scoreMax_lcl[7]_i_10_n_0\
    );
\scoreMax_lcl[7]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \scoreMax_lcl__0\(1),
      I1 => \rexp_reg_n_0_[1]\,
      I2 => \scoreMax_lcl__0\(0),
      I3 => \rexp_reg_n_0_[0]\,
      O => \scoreMax_lcl[7]_i_11_n_0\
    );
\scoreMax_lcl[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \rexp_reg_n_0_[7]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMax_lcl[7]_i_2_n_0\
    );
\scoreMax_lcl[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \rexp_reg_n_0_[7]\,
      I1 => \scoreMax_lcl__0\(7),
      I2 => \rexp_reg_n_0_[6]\,
      I3 => \scoreMax_lcl__0\(6),
      O => \scoreMax_lcl[7]_i_4_n_0\
    );
\scoreMax_lcl[7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \rexp_reg_n_0_[5]\,
      I1 => \scoreMax_lcl__0\(5),
      I2 => \rexp_reg_n_0_[4]\,
      I3 => \scoreMax_lcl__0\(4),
      O => \scoreMax_lcl[7]_i_5_n_0\
    );
\scoreMax_lcl[7]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \rexp_reg_n_0_[3]\,
      I1 => \scoreMax_lcl__0\(3),
      I2 => \rexp_reg_n_0_[2]\,
      I3 => \scoreMax_lcl__0\(2),
      O => \scoreMax_lcl[7]_i_6_n_0\
    );
\scoreMax_lcl[7]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \rexp_reg_n_0_[1]\,
      I1 => \scoreMax_lcl__0\(1),
      I2 => \rexp_reg_n_0_[0]\,
      I3 => \scoreMax_lcl__0\(0),
      O => \scoreMax_lcl[7]_i_7_n_0\
    );
\scoreMax_lcl[7]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \scoreMax_lcl__0\(7),
      I1 => \rexp_reg_n_0_[7]\,
      I2 => \scoreMax_lcl__0\(6),
      I3 => \rexp_reg_n_0_[6]\,
      O => \scoreMax_lcl[7]_i_8_n_0\
    );
\scoreMax_lcl[7]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \scoreMax_lcl__0\(5),
      I1 => \rexp_reg_n_0_[5]\,
      I2 => \scoreMax_lcl__0\(4),
      I3 => \rexp_reg_n_0_[4]\,
      O => \scoreMax_lcl[7]_i_9_n_0\
    );
\scoreMax_lcl_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \scoreMax_lcl[7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \scoreMax_lcl[0]_i_1_n_0\,
      Q => \scoreMax_lcl__0\(0)
    );
\scoreMax_lcl_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \scoreMax_lcl[7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \scoreMax_lcl[1]_i_1_n_0\,
      Q => \scoreMax_lcl__0\(1)
    );
\scoreMax_lcl_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \scoreMax_lcl[7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \scoreMax_lcl[2]_i_1_n_0\,
      Q => \scoreMax_lcl__0\(2)
    );
\scoreMax_lcl_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \scoreMax_lcl[7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \scoreMax_lcl[3]_i_1_n_0\,
      Q => \scoreMax_lcl__0\(3)
    );
\scoreMax_lcl_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \scoreMax_lcl[7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \scoreMax_lcl[4]_i_1_n_0\,
      Q => \scoreMax_lcl__0\(4)
    );
\scoreMax_lcl_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \scoreMax_lcl[7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \scoreMax_lcl[5]_i_1_n_0\,
      Q => \scoreMax_lcl__0\(5)
    );
\scoreMax_lcl_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \scoreMax_lcl[7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \scoreMax_lcl[6]_i_1_n_0\,
      Q => \scoreMax_lcl__0\(6)
    );
\scoreMax_lcl_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \scoreMax_lcl[7]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \scoreMax_lcl[7]_i_2_n_0\,
      Q => \scoreMax_lcl__0\(7)
    );
\scoreMax_lcl_reg[7]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_scoreMax_lcl_reg[7]_i_3_CO_UNCONNECTED\(7 downto 4),
      CO(3) => scoreMax_lcl0,
      CO(2) => \scoreMax_lcl_reg[7]_i_3_n_5\,
      CO(1) => \scoreMax_lcl_reg[7]_i_3_n_6\,
      CO(0) => \scoreMax_lcl_reg[7]_i_3_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3) => \scoreMax_lcl[7]_i_4_n_0\,
      DI(2) => \scoreMax_lcl[7]_i_5_n_0\,
      DI(1) => \scoreMax_lcl[7]_i_6_n_0\,
      DI(0) => \scoreMax_lcl[7]_i_7_n_0\,
      O(7 downto 0) => \NLW_scoreMax_lcl_reg[7]_i_3_O_UNCONNECTED\(7 downto 0),
      S(7 downto 4) => B"0000",
      S(3) => \scoreMax_lcl[7]_i_8_n_0\,
      S(2) => \scoreMax_lcl[7]_i_9_n_0\,
      S(1) => \scoreMax_lcl[7]_i_10_n_0\,
      S(0) => \scoreMax_lcl[7]_i_11_n_0\
    );
\scoreMax_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      CLR => linNotLog_reg_0,
      D => \scoreMax[0]_i_1_n_0\,
      Q => \scoreMax_reg[7]_0\(0)
    );
\scoreMax_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      CLR => linNotLog_reg_0,
      D => \scoreMax[1]_i_1_n_0\,
      Q => \scoreMax_reg[7]_0\(1)
    );
\scoreMax_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      CLR => linNotLog_reg_0,
      D => \scoreMax[2]_i_1_n_0\,
      Q => \scoreMax_reg[7]_0\(2)
    );
\scoreMax_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      CLR => linNotLog_reg_0,
      D => \scoreMax[3]_i_1_n_0\,
      Q => \scoreMax_reg[7]_0\(3)
    );
\scoreMax_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      CLR => linNotLog_reg_0,
      D => \scoreMax[4]_i_1_n_0\,
      Q => \scoreMax_reg[7]_0\(4)
    );
\scoreMax_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      CLR => linNotLog_reg_0,
      D => \scoreMax[5]_i_1_n_0\,
      Q => \scoreMax_reg[7]_0\(5)
    );
\scoreMax_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      CLR => linNotLog_reg_0,
      D => \scoreMax[6]_i_1_n_0\,
      Q => \scoreMax_reg[7]_0\(6)
    );
\scoreMax_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      CLR => linNotLog_reg_0,
      D => \scoreMax[7]_i_1_n_0\,
      Q => \scoreMax_reg[7]_0\(7)
    );
\scoreMin[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \scoreMin_lcl__0\(0),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin[0]_i_1_n_0\
    );
\scoreMin[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \scoreMin_lcl__0\(1),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin[1]_i_1_n_0\
    );
\scoreMin[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \scoreMin_lcl__0\(2),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin[2]_i_1_n_0\
    );
\scoreMin[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \scoreMin_lcl__0\(3),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin[3]_i_1_n_0\
    );
\scoreMin[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \scoreMin_lcl__0\(4),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin[4]_i_1_n_0\
    );
\scoreMin[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \scoreMin_lcl__0\(5),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin[5]_i_1_n_0\
    );
\scoreMin[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \scoreMin_lcl__0\(6),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin[6]_i_1_n_0\
    );
\scoreMin[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \scoreMin_lcl__0\(7),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin[7]_i_1_n_0\
    );
\scoreMin_lcl[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \rexp_reg_n_0_[0]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin_lcl[0]_i_1_n_0\
    );
\scoreMin_lcl[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \rexp_reg_n_0_[1]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin_lcl[1]_i_1_n_0\
    );
\scoreMin_lcl[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \rexp_reg_n_0_[2]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin_lcl[2]_i_1_n_0\
    );
\scoreMin_lcl[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \rexp_reg_n_0_[3]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin_lcl[3]_i_1_n_0\
    );
\scoreMin_lcl[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \rexp_reg_n_0_[4]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin_lcl[4]_i_1_n_0\
    );
\scoreMin_lcl[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \rexp_reg_n_0_[5]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin_lcl[5]_i_1_n_0\
    );
\scoreMin_lcl[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \rexp_reg_n_0_[6]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin_lcl[6]_i_1_n_0\
    );
\scoreMin_lcl[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555D555F5555555F"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => scoreMin_lcl0,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \stateImdstream_reg_n_0_[1]\,
      I5 => ceScore,
      O => \scoreMin_lcl[7]_i_1_n_0\
    );
\scoreMin_lcl[7]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \rexp_reg_n_0_[3]\,
      I1 => \scoreMin_lcl__0\(3),
      I2 => \rexp_reg_n_0_[2]\,
      I3 => \scoreMin_lcl__0\(2),
      O => \scoreMin_lcl[7]_i_10_n_0\
    );
\scoreMin_lcl[7]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \rexp_reg_n_0_[1]\,
      I1 => \scoreMin_lcl__0\(1),
      I2 => \rexp_reg_n_0_[0]\,
      I3 => \scoreMin_lcl__0\(0),
      O => \scoreMin_lcl[7]_i_11_n_0\
    );
\scoreMin_lcl[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \rexp_reg_n_0_[7]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \scoreMin_lcl[7]_i_2_n_0\
    );
\scoreMin_lcl[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \scoreMin_lcl__0\(7),
      I1 => \rexp_reg_n_0_[7]\,
      I2 => \scoreMin_lcl__0\(6),
      I3 => \rexp_reg_n_0_[6]\,
      O => \scoreMin_lcl[7]_i_4_n_0\
    );
\scoreMin_lcl[7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \scoreMin_lcl__0\(5),
      I1 => \rexp_reg_n_0_[5]\,
      I2 => \scoreMin_lcl__0\(4),
      I3 => \rexp_reg_n_0_[4]\,
      O => \scoreMin_lcl[7]_i_5_n_0\
    );
\scoreMin_lcl[7]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \scoreMin_lcl__0\(3),
      I1 => \rexp_reg_n_0_[3]\,
      I2 => \scoreMin_lcl__0\(2),
      I3 => \rexp_reg_n_0_[2]\,
      O => \scoreMin_lcl[7]_i_6_n_0\
    );
\scoreMin_lcl[7]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \scoreMin_lcl__0\(1),
      I1 => \rexp_reg_n_0_[1]\,
      I2 => \scoreMin_lcl__0\(0),
      I3 => \rexp_reg_n_0_[0]\,
      O => \scoreMin_lcl[7]_i_7_n_0\
    );
\scoreMin_lcl[7]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \rexp_reg_n_0_[7]\,
      I1 => \scoreMin_lcl__0\(7),
      I2 => \rexp_reg_n_0_[6]\,
      I3 => \scoreMin_lcl__0\(6),
      O => \scoreMin_lcl[7]_i_8_n_0\
    );
\scoreMin_lcl[7]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \rexp_reg_n_0_[5]\,
      I1 => \scoreMin_lcl__0\(5),
      I2 => \rexp_reg_n_0_[4]\,
      I3 => \scoreMin_lcl__0\(4),
      O => \scoreMin_lcl[7]_i_9_n_0\
    );
\scoreMin_lcl_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \scoreMin_lcl[7]_i_1_n_0\,
      D => \scoreMin_lcl[0]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_lcl__0\(0)
    );
\scoreMin_lcl_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \scoreMin_lcl[7]_i_1_n_0\,
      D => \scoreMin_lcl[1]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_lcl__0\(1)
    );
\scoreMin_lcl_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \scoreMin_lcl[7]_i_1_n_0\,
      D => \scoreMin_lcl[2]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_lcl__0\(2)
    );
\scoreMin_lcl_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \scoreMin_lcl[7]_i_1_n_0\,
      D => \scoreMin_lcl[3]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_lcl__0\(3)
    );
\scoreMin_lcl_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \scoreMin_lcl[7]_i_1_n_0\,
      D => \scoreMin_lcl[4]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_lcl__0\(4)
    );
\scoreMin_lcl_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \scoreMin_lcl[7]_i_1_n_0\,
      D => \scoreMin_lcl[5]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_lcl__0\(5)
    );
\scoreMin_lcl_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \scoreMin_lcl[7]_i_1_n_0\,
      D => \scoreMin_lcl[6]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_lcl__0\(6)
    );
\scoreMin_lcl_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \scoreMin_lcl[7]_i_1_n_0\,
      D => \scoreMin_lcl[7]_i_2_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_lcl__0\(7)
    );
\scoreMin_lcl_reg[7]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_scoreMin_lcl_reg[7]_i_3_CO_UNCONNECTED\(7 downto 4),
      CO(3) => scoreMin_lcl0,
      CO(2) => \scoreMin_lcl_reg[7]_i_3_n_5\,
      CO(1) => \scoreMin_lcl_reg[7]_i_3_n_6\,
      CO(0) => \scoreMin_lcl_reg[7]_i_3_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3) => \scoreMin_lcl[7]_i_4_n_0\,
      DI(2) => \scoreMin_lcl[7]_i_5_n_0\,
      DI(1) => \scoreMin_lcl[7]_i_6_n_0\,
      DI(0) => \scoreMin_lcl[7]_i_7_n_0\,
      O(7 downto 0) => \NLW_scoreMin_lcl_reg[7]_i_3_O_UNCONNECTED\(7 downto 0),
      S(7 downto 4) => B"0000",
      S(3) => \scoreMin_lcl[7]_i_8_n_0\,
      S(2) => \scoreMin_lcl[7]_i_9_n_0\,
      S(1) => \scoreMin_lcl[7]_i_10_n_0\,
      S(0) => \scoreMin_lcl[7]_i_11_n_0\
    );
\scoreMin_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      D => \scoreMin[0]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_reg[7]_0\(0)
    );
\scoreMin_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      D => \scoreMin[1]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_reg[7]_0\(1)
    );
\scoreMin_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      D => \scoreMin[2]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_reg[7]_0\(2)
    );
\scoreMin_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      D => \scoreMin[3]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_reg[7]_0\(3)
    );
\scoreMin_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      D => \scoreMin[4]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_reg[7]_0\(4)
    );
\scoreMin_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      D => \scoreMin[5]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_reg[7]_0\(5)
    );
\scoreMin_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      D => \scoreMin[6]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_reg[7]_0\(6)
    );
\scoreMin_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => scoreMax,
      D => \scoreMin[7]_i_1_n_0\,
      PRE => linNotLog_reg_0,
      Q => \scoreMin_reg[7]_0\(7)
    );
\shift[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08080888"
    )
        port map (
      I0 => \stateImdstream[0]_i_3_n_0\,
      I1 => \shift_lcl__0\(0),
      I2 => \shift_lcl__0\(5),
      I3 => \shift_lcl__0\(4),
      I4 => \shift_lcl__0\(3),
      O => \shift[0]_i_1_n_0\
    );
\shift[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08080888"
    )
        port map (
      I0 => \stateImdstream[0]_i_3_n_0\,
      I1 => \shift_lcl__0\(1),
      I2 => \shift_lcl__0\(5),
      I3 => \shift_lcl__0\(4),
      I4 => \shift_lcl__0\(3),
      O => \shift[1]_i_1_n_0\
    );
\shift[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08080888"
    )
        port map (
      I0 => \stateImdstream[0]_i_3_n_0\,
      I1 => \shift_lcl__0\(2),
      I2 => \shift_lcl__0\(5),
      I3 => \shift_lcl__0\(4),
      I4 => \shift_lcl__0\(3),
      O => \shift[2]_i_1_n_0\
    );
\shift[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA80"
    )
        port map (
      I0 => \stateImdstream[0]_i_3_n_0\,
      I1 => \shift_lcl__0\(5),
      I2 => \shift_lcl__0\(4),
      I3 => \shift_lcl__0\(3),
      O => \shift[3]_i_1_n_0\
    );
\shift[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FE000000"
    )
        port map (
      I0 => \stateImdstream_reg_n_0_[1]\,
      I1 => p_1_in,
      I2 => \stateImdstream_reg_n_0_[0]\,
      I3 => \^rng_reg_0\,
      I4 => \shift_lcl__0\(4),
      I5 => \shift_lcl__0\(5),
      O => \shift[4]_i_1_n_0\
    );
\shift[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"555555DF"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \tkst_reg[0]_0\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \stateImdstream_reg_n_0_[1]\,
      O => scoreMax
    );
\shift[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \shift_lcl__0\(5),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \shift[5]_i_2_n_0\
    );
\shift_lcl[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \rshift__0\(0),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \shift_lcl[0]_i_1_n_0\
    );
\shift_lcl[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \rshift__0\(1),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \shift_lcl[1]_i_1_n_0\
    );
\shift_lcl[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \rshift__0\(2),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \shift_lcl[2]_i_1_n_0\
    );
\shift_lcl[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \rshift__0\(3),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \shift_lcl[3]_i_1_n_0\
    );
\shift_lcl[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \rshift__0\(4),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \shift_lcl[4]_i_1_n_0\
    );
\shift_lcl[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFFF"
    )
        port map (
      I0 => \shift_lcl[5]_i_3_n_0\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \shift_lcl[5]_i_1_n_0\
    );
\shift_lcl[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA80000"
    )
        port map (
      I0 => \rshift__0\(5),
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      O => \shift_lcl[5]_i_2_n_0\
    );
\shift_lcl[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F4FF00F4"
    )
        port map (
      I0 => \shift_lcl__0\(4),
      I1 => \rshift__0\(4),
      I2 => \shift_lcl[5]_i_4_n_0\,
      I3 => \shift_lcl__0\(5),
      I4 => \rshift__0\(5),
      I5 => \aImdbuf[10]_i_4_n_0\,
      O => \shift_lcl[5]_i_3_n_0\
    );
\shift_lcl[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF4F44"
    )
        port map (
      I0 => \shift_lcl__0\(3),
      I1 => \rshift__0\(3),
      I2 => \shift_lcl__0\(2),
      I3 => \rshift__0\(2),
      I4 => \shift_lcl[5]_i_5_n_0\,
      I5 => \shift_lcl[5]_i_6_n_0\,
      O => \shift_lcl[5]_i_4_n_0\
    );
\shift_lcl[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40F4000040F440F4"
    )
        port map (
      I0 => \shift_lcl__0\(0),
      I1 => \rshift__0\(0),
      I2 => \rshift__0\(1),
      I3 => \shift_lcl__0\(1),
      I4 => \rshift__0\(2),
      I5 => \shift_lcl__0\(2),
      O => \shift_lcl[5]_i_5_n_0\
    );
\shift_lcl[5]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \rshift__0\(3),
      I1 => \shift_lcl__0\(3),
      I2 => \rshift__0\(4),
      I3 => \shift_lcl__0\(4),
      O => \shift_lcl[5]_i_6_n_0\
    );
\shift_lcl_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \shift_lcl[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \shift_lcl[0]_i_1_n_0\,
      Q => \shift_lcl__0\(0)
    );
\shift_lcl_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \shift_lcl[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \shift_lcl[1]_i_1_n_0\,
      Q => \shift_lcl__0\(1)
    );
\shift_lcl_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \shift_lcl[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \shift_lcl[2]_i_1_n_0\,
      Q => \shift_lcl__0\(2)
    );
\shift_lcl_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \shift_lcl[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \shift_lcl[3]_i_1_n_0\,
      Q => \shift_lcl__0\(3)
    );
\shift_lcl_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \shift_lcl[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \shift_lcl[4]_i_1_n_0\,
      Q => \shift_lcl__0\(4)
    );
\shift_lcl_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \shift_lcl[5]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \shift_lcl[5]_i_2_n_0\,
      Q => \shift_lcl__0\(5)
    );
\shift_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => scoreMax,
      CLR => linNotLog_reg_0,
      D => \shift[0]_i_1_n_0\,
      Q => shift(0)
    );
\shift_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => scoreMax,
      CLR => linNotLog_reg_0,
      D => \shift[1]_i_1_n_0\,
      Q => shift(1)
    );
\shift_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => scoreMax,
      CLR => linNotLog_reg_0,
      D => \shift[2]_i_1_n_0\,
      Q => shift(2)
    );
\shift_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => scoreMax,
      CLR => linNotLog_reg_0,
      D => \shift[3]_i_1_n_0\,
      Q => shift(3)
    );
\shift_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => scoreMax,
      CLR => linNotLog_reg_0,
      D => \shift[4]_i_1_n_0\,
      Q => shift(4)
    );
\shift_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => scoreMax,
      CLR => linNotLog_reg_0,
      D => \shift[5]_i_2_n_0\,
      Q => shift(5)
    );
\stateCorner[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAFFBA00BE00BE00"
    )
        port map (
      I0 => \stateCorner[0]_i_2_n_0\,
      I1 => stateCorner(1),
      I2 => stateCorner(0),
      I3 => \^rng_reg_1\,
      I4 => \^rng_reg_0\,
      I5 => \tkst_reg[0]_0\,
      O => \stateCorner[0]_i_1_n_0\
    );
\stateCorner[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => stateCorner(1),
      I1 => stateCorner(0),
      I2 => \stateCorner[1]_i_4_n_0\,
      O => \stateCorner[0]_i_2_n_0\
    );
\stateCorner[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F00040F0F0F040F0"
    )
        port map (
      I0 => \stateCorner_reg[1]_0\,
      I1 => grayVideoinToManyAXIS_tlast,
      I2 => \^rng_reg_1\,
      I3 => stateCorner(0),
      I4 => stateCorner(1),
      I5 => \stateCorner[1]_i_4_n_0\,
      O => \stateCorner[1]_i_1_n_0\
    );
\stateCorner[1]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => stateCorner(0),
      I2 => stateCorner(1),
      O => \^rng_reg_1\
    );
\stateCorner[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000100"
    )
        port map (
      I0 => \stateCorner[1]_i_5_n_0\,
      I1 => \stateCorner[1]_i_6_n_0\,
      I2 => \postcol_lcl__0\(3),
      I3 => \postcol_lcl__0\(1),
      I4 => \postcol_lcl__0\(4),
      I5 => lat(4),
      O => \stateCorner[1]_i_4_n_0\
    );
\stateCorner[1]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \postcol_lcl__0\(5),
      I1 => \postcol_lcl__0\(0),
      I2 => \postcol_lcl__0\(10),
      I3 => \postcol_lcl__0\(2),
      O => \stateCorner[1]_i_5_n_0\
    );
\stateCorner[1]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \postcol_lcl__0\(7),
      I1 => \postcol_lcl__0\(6),
      I2 => \postcol_lcl__0\(9),
      I3 => \postcol_lcl__0\(8),
      O => \stateCorner[1]_i_6_n_0\
    );
\stateCorner_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => \stateCorner[0]_i_1_n_0\,
      Q => stateCorner(0)
    );
\stateCorner_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => \stateCorner[1]_i_1_n_0\,
      Q => stateCorner(1)
    );
\stateImdstream[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4474FFFF44740000"
    )
        port map (
      I0 => \tkst_reg[0]_0\,
      I1 => p_1_in,
      I2 => \stateImdstream[0]_i_2_n_0\,
      I3 => \stateImdstream[1]_i_2_n_0\,
      I4 => \stateImdstream[0]_i_3_n_0\,
      I5 => \stateImdstream[0]_i_4_n_0\,
      O => \stateImdstream[0]_i_1_n_0\
    );
\stateImdstream[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F8FB"
    )
        port map (
      I0 => \aImdbufB_reg[0]_0\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => \stateImdstream_reg_n_0_[0]\,
      I3 => \tkst_reg[0]_0\,
      O => \stateImdstream[0]_i_2_n_0\
    );
\stateImdstream[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => p_1_in,
      I3 => \stateImdstream_reg_n_0_[1]\,
      O => \stateImdstream[0]_i_3_n_0\
    );
\stateImdstream[0]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8088"
    )
        port map (
      I0 => \tkst_reg[0]_0\,
      I1 => \^rng_reg_0\,
      I2 => \^tixvstate_reg[1]_0\(0),
      I3 => \^tixvstate_reg[1]_0\(1),
      O => \stateImdstream[0]_i_4_n_0\
    );
\stateImdstream[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F8C80000"
    )
        port map (
      I0 => \aImdbufB_reg[0]_0\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      I2 => \stateImdstream[1]_i_2_n_0\,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => \^rng_reg_0\,
      I5 => p_1_in,
      O => \stateImdstream[1]_i_1_n_0\
    );
\stateImdstream[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAABAAAAAAAA"
    )
        port map (
      I0 => \stateImdstream[1]_i_3_n_0\,
      I1 => lat(4),
      I2 => \^col_lcl_reg[10]_0\(2),
      I3 => \^col_lcl_reg[10]_0\(4),
      I4 => \^col_lcl_reg[10]_0\(1),
      I5 => \stateImdstream[1]_i_4_n_0\,
      O => \stateImdstream[1]_i_2_n_0\
    );
\stateImdstream[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateImdstream_reg_n_0_[0]\,
      I1 => \stateImdstream_reg_n_0_[1]\,
      O => \stateImdstream[1]_i_3_n_0\
    );
\stateImdstream[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \^col_lcl_reg[10]_0\(3),
      I1 => \^col_lcl_reg[10]_0\(5),
      I2 => \^col_lcl_reg[10]_0\(0),
      I3 => \^col_lcl_reg[10]_0\(8),
      I4 => \stateImdstream_reg_n_0_[0]\,
      I5 => \aImdbuf[10]_i_8_n_0\,
      O => \stateImdstream[1]_i_4_n_0\
    );
\stateImdstream[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"555FFDDF"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => ceScore,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \stateImdstream_reg_n_0_[0]\,
      I4 => p_1_in,
      O => \stateImdstream[2]_i_1_n_0\
    );
\stateImdstream[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => p_1_in,
      I1 => \stateImdstream_reg_n_0_[0]\,
      I2 => \stateImdstream_reg_n_0_[1]\,
      I3 => \^rng_reg_0\,
      I4 => \aImdbufB_reg[0]_0\,
      O => \stateImdstream[2]_i_2_n_0\
    );
\stateImdstream_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateImdstream[2]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \stateImdstream[0]_i_1_n_0\,
      Q => \stateImdstream_reg_n_0_[0]\
    );
\stateImdstream_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateImdstream[2]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \stateImdstream[1]_i_1_n_0\,
      Q => \stateImdstream_reg_n_0_[1]\
    );
\stateImdstream_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateImdstream[2]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \stateImdstream[2]_i_2_n_0\,
      Q => p_1_in
    );
\stateMaxsel[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE4FF00FF00FF00"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[1]\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => enCoobuf_reg_0,
      I3 => tkst,
      I4 => \^rng_reg_0\,
      I5 => \stateMaxsel[1]_i_3_n_0\,
      O => \stateMaxsel[0]_i_1_n_0\
    );
\stateMaxsel[0]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBDDB6FF6FFFF"
    )
        port map (
      I0 => row_lcl_reg(1),
      I1 => NRowRaw(1),
      I2 => row_lcl_reg(2),
      I3 => NRowRaw(2),
      I4 => NRowRaw(0),
      I5 => row_lcl_reg(0),
      O => \row_lcl_reg[1]_0\
    );
\stateMaxsel[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \stateMaxsel_reg_n_0_[1]\,
      I1 => \stateMaxsel_reg_n_0_[0]\,
      I2 => \^rng_reg_0\,
      O => \stateMaxsel[1]_i_1_n_0\
    );
\stateMaxsel[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \stateMaxsel[1]_i_3_n_0\,
      O => \stateMaxsel[1]_i_2_n_0\
    );
\stateMaxsel[1]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => \i[1]_i_3_n_0\,
      I1 => \i__0\(0),
      I2 => \i__0\(1),
      I3 => postNotLive_reg_n_0,
      O => \stateMaxsel[1]_i_3_n_0\
    );
\stateMaxsel_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateMaxsel[1]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \stateMaxsel[0]_i_1_n_0\,
      Q => \stateMaxsel_reg_n_0_[0]\
    );
\stateMaxsel_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateMaxsel[1]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \stateMaxsel[1]_i_2_n_0\,
      Q => \stateMaxsel_reg_n_0_[1]\
    );
\stateOp[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \^stateop_reg[1]_0\(0),
      I1 => vsync_last_reg_0,
      I2 => \^rng_reg_0\,
      I3 => \^stateop_reg[1]_0\(1),
      O => stateOp(1)
    );
\stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => linNotLog_reg_0,
      D => \stateOp_reg[0]_0\(0),
      Q => \^stateop_reg[1]_0\(0)
    );
\stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => linNotLog_reg_0,
      D => stateOp(1),
      Q => \^stateop_reg[1]_0\(1)
    );
stateScore_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => stateScore
    );
stateScore_reg_rep: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => stateScore_reg_rep_n_0
    );
\stateScore_reg_rep__0\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__0_n_0\
    );
\stateScore_reg_rep__1\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__1_n_0\
    );
\stateScore_reg_rep__10\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__10_n_0\
    );
\stateScore_reg_rep__11\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__11_n_0\
    );
\stateScore_reg_rep__12\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__12_n_0\
    );
\stateScore_reg_rep__13\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__13_n_0\
    );
\stateScore_reg_rep__14\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__14_n_0\
    );
\stateScore_reg_rep__15\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__15_n_0\
    );
\stateScore_reg_rep__16\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__16_n_0\
    );
\stateScore_reg_rep__17\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__17_n_0\
    );
\stateScore_reg_rep__18\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__18_n_0\
    );
\stateScore_reg_rep__2\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__2_n_0\
    );
\stateScore_reg_rep__3\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__3_n_0\
    );
\stateScore_reg_rep__4\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__4_n_0\
    );
\stateScore_reg_rep__5\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__5_n_0\
    );
\stateScore_reg_rep__6\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__6_n_0\
    );
\stateScore_reg_rep__7\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__7_n_0\
    );
\stateScore_reg_rep__8\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__8_n_0\
    );
\stateScore_reg_rep__9\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => '1',
      Q => \stateScore_reg_rep__9_n_0\
    );
\sumIII[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[15]\,
      I1 => sumX(15),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_10_n_0\
    );
\sumIII[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[14]\,
      I1 => sumX(14),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_11_n_0\
    );
\sumIII[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[13]\,
      I1 => sumX(13),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_12_n_0\
    );
\sumIII[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[12]\,
      I1 => sumX(12),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_13_n_0\
    );
\sumIII[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[11]\,
      I1 => sumX(11),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_14_n_0\
    );
\sumIII[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[10]\,
      I1 => sumX(10),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_15_n_0\
    );
\sumIII[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[9]\,
      I1 => sumX(9),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_16_n_0\
    );
\sumIII[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[8]\,
      I1 => sumX(8),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_17_n_0\
    );
\sumIII[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[15]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_2_n_0\
    );
\sumIII[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[14]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_3_n_0\
    );
\sumIII[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[13]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_4_n_0\
    );
\sumIII[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[12]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_5_n_0\
    );
\sumIII[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[11]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_6_n_0\
    );
\sumIII[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[10]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_7_n_0\
    );
\sumIII[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[9]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_8_n_0\
    );
\sumIII[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[8]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[15]_i_9_n_0\
    );
\sumIII[23]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[22]\,
      I1 => sumX(22),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_10_n_0\
    );
\sumIII[23]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[21]\,
      I1 => sumX(21),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_11_n_0\
    );
\sumIII[23]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[20]\,
      I1 => sumX(20),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_12_n_0\
    );
\sumIII[23]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[19]\,
      I1 => sumX(19),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_13_n_0\
    );
\sumIII[23]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[18]\,
      I1 => sumX(18),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_14_n_0\
    );
\sumIII[23]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[17]\,
      I1 => sumX(17),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_15_n_0\
    );
\sumIII[23]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[16]\,
      I1 => sumX(16),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_16_n_0\
    );
\sumIII[23]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[22]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_2_n_0\
    );
\sumIII[23]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[21]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_3_n_0\
    );
\sumIII[23]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[20]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_4_n_0\
    );
\sumIII[23]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[19]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_5_n_0\
    );
\sumIII[23]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[18]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_6_n_0\
    );
\sumIII[23]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[17]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_7_n_0\
    );
\sumIII[23]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[16]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_8_n_0\
    );
\sumIII[23]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[22]\,
      I1 => sumX(22),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[23]_i_9_n_0\
    );
\sumIII[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[7]\,
      I1 => sumX(7),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_10_n_0\
    );
\sumIII[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[6]\,
      I1 => sumX(6),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_11_n_0\
    );
\sumIII[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[5]\,
      I1 => sumX(5),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_12_n_0\
    );
\sumIII[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[4]\,
      I1 => sumX(4),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_13_n_0\
    );
\sumIII[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[3]\,
      I1 => sumX(3),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_14_n_0\
    );
\sumIII[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[2]\,
      I1 => sumX(2),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_15_n_0\
    );
\sumIII[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[1]\,
      I1 => sumX(1),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_16_n_0\
    );
\sumIII[7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sumY_reg_n_0_[0]\,
      I1 => sumX(0),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_17_n_0\
    );
\sumIII[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[7]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_2_n_0\
    );
\sumIII[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[6]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_3_n_0\
    );
\sumIII[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[5]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_4_n_0\
    );
\sumIII[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[4]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_5_n_0\
    );
\sumIII[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[3]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_6_n_0\
    );
\sumIII[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[2]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_7_n_0\
    );
\sumIII[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[1]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_8_n_0\
    );
\sumIII[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \sumY_reg_n_0_[0]\,
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumIII[7]_i_9_n_0\
    );
\sumIII_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[7]_i_1_n_15\,
      Q => sumIII(0)
    );
\sumIII_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[15]_i_1_n_13\,
      Q => sumIII(10)
    );
\sumIII_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[15]_i_1_n_12\,
      Q => sumIII(11)
    );
\sumIII_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[15]_i_1_n_11\,
      Q => sumIII(12)
    );
\sumIII_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[15]_i_1_n_10\,
      Q => sumIII(13)
    );
\sumIII_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[15]_i_1_n_9\,
      Q => sumIII(14)
    );
\sumIII_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[15]_i_1_n_8\,
      Q => sumIII(15)
    );
\sumIII_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumIII_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \sumIII_reg[15]_i_1_n_0\,
      CO(6) => \sumIII_reg[15]_i_1_n_1\,
      CO(5) => \sumIII_reg[15]_i_1_n_2\,
      CO(4) => \sumIII_reg[15]_i_1_n_3\,
      CO(3) => \sumIII_reg[15]_i_1_n_4\,
      CO(2) => \sumIII_reg[15]_i_1_n_5\,
      CO(1) => \sumIII_reg[15]_i_1_n_6\,
      CO(0) => \sumIII_reg[15]_i_1_n_7\,
      DI(7) => \sumIII[15]_i_2_n_0\,
      DI(6) => \sumIII[15]_i_3_n_0\,
      DI(5) => \sumIII[15]_i_4_n_0\,
      DI(4) => \sumIII[15]_i_5_n_0\,
      DI(3) => \sumIII[15]_i_6_n_0\,
      DI(2) => \sumIII[15]_i_7_n_0\,
      DI(1) => \sumIII[15]_i_8_n_0\,
      DI(0) => \sumIII[15]_i_9_n_0\,
      O(7) => \sumIII_reg[15]_i_1_n_8\,
      O(6) => \sumIII_reg[15]_i_1_n_9\,
      O(5) => \sumIII_reg[15]_i_1_n_10\,
      O(4) => \sumIII_reg[15]_i_1_n_11\,
      O(3) => \sumIII_reg[15]_i_1_n_12\,
      O(2) => \sumIII_reg[15]_i_1_n_13\,
      O(1) => \sumIII_reg[15]_i_1_n_14\,
      O(0) => \sumIII_reg[15]_i_1_n_15\,
      S(7) => \sumIII[15]_i_10_n_0\,
      S(6) => \sumIII[15]_i_11_n_0\,
      S(5) => \sumIII[15]_i_12_n_0\,
      S(4) => \sumIII[15]_i_13_n_0\,
      S(3) => \sumIII[15]_i_14_n_0\,
      S(2) => \sumIII[15]_i_15_n_0\,
      S(1) => \sumIII[15]_i_16_n_0\,
      S(0) => \sumIII[15]_i_17_n_0\
    );
\sumIII_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[23]_i_1_n_15\,
      Q => sumIII(16)
    );
\sumIII_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[23]_i_1_n_14\,
      Q => sumIII(17)
    );
\sumIII_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[23]_i_1_n_13\,
      Q => sumIII(18)
    );
\sumIII_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[23]_i_1_n_12\,
      Q => sumIII(19)
    );
\sumIII_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[7]_i_1_n_14\,
      Q => sumIII(1)
    );
\sumIII_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[23]_i_1_n_11\,
      Q => sumIII(20)
    );
\sumIII_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[23]_i_1_n_10\,
      Q => sumIII(21)
    );
\sumIII_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[23]_i_1_n_9\,
      Q => sumIII(22)
    );
\sumIII_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[23]_i_1_n_8\,
      Q => sumIII(23)
    );
\sumIII_reg[23]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumIII_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \NLW_sumIII_reg[23]_i_1_CO_UNCONNECTED\(7),
      CO(6) => \sumIII_reg[23]_i_1_n_1\,
      CO(5) => \sumIII_reg[23]_i_1_n_2\,
      CO(4) => \sumIII_reg[23]_i_1_n_3\,
      CO(3) => \sumIII_reg[23]_i_1_n_4\,
      CO(2) => \sumIII_reg[23]_i_1_n_5\,
      CO(1) => \sumIII_reg[23]_i_1_n_6\,
      CO(0) => \sumIII_reg[23]_i_1_n_7\,
      DI(7) => '0',
      DI(6) => \sumIII[23]_i_2_n_0\,
      DI(5) => \sumIII[23]_i_3_n_0\,
      DI(4) => \sumIII[23]_i_4_n_0\,
      DI(3) => \sumIII[23]_i_5_n_0\,
      DI(2) => \sumIII[23]_i_6_n_0\,
      DI(1) => \sumIII[23]_i_7_n_0\,
      DI(0) => \sumIII[23]_i_8_n_0\,
      O(7) => \sumIII_reg[23]_i_1_n_8\,
      O(6) => \sumIII_reg[23]_i_1_n_9\,
      O(5) => \sumIII_reg[23]_i_1_n_10\,
      O(4) => \sumIII_reg[23]_i_1_n_11\,
      O(3) => \sumIII_reg[23]_i_1_n_12\,
      O(2) => \sumIII_reg[23]_i_1_n_13\,
      O(1) => \sumIII_reg[23]_i_1_n_14\,
      O(0) => \sumIII_reg[23]_i_1_n_15\,
      S(7) => \sumIII[23]_i_9_n_0\,
      S(6) => \sumIII[23]_i_10_n_0\,
      S(5) => \sumIII[23]_i_11_n_0\,
      S(4) => \sumIII[23]_i_12_n_0\,
      S(3) => \sumIII[23]_i_13_n_0\,
      S(2) => \sumIII[23]_i_14_n_0\,
      S(1) => \sumIII[23]_i_15_n_0\,
      S(0) => \sumIII[23]_i_16_n_0\
    );
\sumIII_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[7]_i_1_n_13\,
      Q => sumIII(2)
    );
\sumIII_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[7]_i_1_n_12\,
      Q => sumIII(3)
    );
\sumIII_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[7]_i_1_n_11\,
      Q => sumIII(4)
    );
\sumIII_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[7]_i_1_n_10\,
      Q => sumIII(5)
    );
\sumIII_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[7]_i_1_n_9\,
      Q => sumIII(6)
    );
\sumIII_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[7]_i_1_n_8\,
      Q => sumIII(7)
    );
\sumIII_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \sumIII_reg[7]_i_1_n_0\,
      CO(6) => \sumIII_reg[7]_i_1_n_1\,
      CO(5) => \sumIII_reg[7]_i_1_n_2\,
      CO(4) => \sumIII_reg[7]_i_1_n_3\,
      CO(3) => \sumIII_reg[7]_i_1_n_4\,
      CO(2) => \sumIII_reg[7]_i_1_n_5\,
      CO(1) => \sumIII_reg[7]_i_1_n_6\,
      CO(0) => \sumIII_reg[7]_i_1_n_7\,
      DI(7) => \sumIII[7]_i_2_n_0\,
      DI(6) => \sumIII[7]_i_3_n_0\,
      DI(5) => \sumIII[7]_i_4_n_0\,
      DI(4) => \sumIII[7]_i_5_n_0\,
      DI(3) => \sumIII[7]_i_6_n_0\,
      DI(2) => \sumIII[7]_i_7_n_0\,
      DI(1) => \sumIII[7]_i_8_n_0\,
      DI(0) => \sumIII[7]_i_9_n_0\,
      O(7) => \sumIII_reg[7]_i_1_n_8\,
      O(6) => \sumIII_reg[7]_i_1_n_9\,
      O(5) => \sumIII_reg[7]_i_1_n_10\,
      O(4) => \sumIII_reg[7]_i_1_n_11\,
      O(3) => \sumIII_reg[7]_i_1_n_12\,
      O(2) => \sumIII_reg[7]_i_1_n_13\,
      O(1) => \sumIII_reg[7]_i_1_n_14\,
      O(0) => \sumIII_reg[7]_i_1_n_15\,
      S(7) => \sumIII[7]_i_10_n_0\,
      S(6) => \sumIII[7]_i_11_n_0\,
      S(5) => \sumIII[7]_i_12_n_0\,
      S(4) => \sumIII[7]_i_13_n_0\,
      S(3) => \sumIII[7]_i_14_n_0\,
      S(2) => \sumIII[7]_i_15_n_0\,
      S(1) => \sumIII[7]_i_16_n_0\,
      S(0) => \sumIII[7]_i_17_n_0\
    );
\sumIII_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[15]_i_1_n_15\,
      Q => sumIII(8)
    );
\sumIII_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumIII_reg[15]_i_1_n_14\,
      Q => sumIII(9)
    );
\sumXA[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(0),
      O => \sumXA[0]_i_1_n_0\
    );
\sumXA[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(10),
      O => \sumXA[10]_i_1_n_0\
    );
\sumXA[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(11),
      O => \sumXA[11]_i_1_n_0\
    );
\sumXA[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(12),
      O => \sumXA[12]_i_1_n_0\
    );
\sumXA[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(13),
      O => \sumXA[13]_i_1_n_0\
    );
\sumXA[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(14),
      O => \sumXA[14]_i_1_n_0\
    );
\sumXA[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(15),
      O => \sumXA[15]_i_1_n_0\
    );
\sumXA[15]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[29]\,
      I1 => \colsumX_reg_n_0_[8]\,
      O => \sumXA[15]_i_10_n_0\
    );
\sumXA[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[36]\,
      I1 => \colsumX_reg_n_0_[15]\,
      O => \sumXA[15]_i_3_n_0\
    );
\sumXA[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[35]\,
      I1 => \colsumX_reg_n_0_[14]\,
      O => \sumXA[15]_i_4_n_0\
    );
\sumXA[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[34]\,
      I1 => \colsumX_reg_n_0_[13]\,
      O => \sumXA[15]_i_5_n_0\
    );
\sumXA[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[33]\,
      I1 => \colsumX_reg_n_0_[12]\,
      O => \sumXA[15]_i_6_n_0\
    );
\sumXA[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[32]\,
      I1 => \colsumX_reg_n_0_[11]\,
      O => \sumXA[15]_i_7_n_0\
    );
\sumXA[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[31]\,
      I1 => \colsumX_reg_n_0_[10]\,
      O => \sumXA[15]_i_8_n_0\
    );
\sumXA[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[30]\,
      I1 => \colsumX_reg_n_0_[9]\,
      O => \sumXA[15]_i_9_n_0\
    );
\sumXA[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumXA0(16),
      O => \sumXA[16]_i_1_n_0\
    );
\sumXA[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumXA0(17),
      O => \sumXA[17]_i_1_n_0\
    );
\sumXA[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumXA0(18),
      O => \sumXA[18]_i_1_n_0\
    );
\sumXA[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumXA0(19),
      O => \sumXA[19]_i_1_n_0\
    );
\sumXA[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(1),
      O => \sumXA[1]_i_1_n_0\
    );
\sumXA[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumXA0(20),
      O => \sumXA[20]_i_1_n_0\
    );
\sumXA[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => \sumXA_reg[21]_i_2_n_2\,
      O => \sumXA[21]_i_1_n_0\
    );
\sumXA[21]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \colsumX_reg_n_0_[41]\,
      O => \sumXA[21]_i_3_n_0\
    );
\sumXA[21]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[41]\,
      I1 => \colsumX_reg_n_0_[20]\,
      O => \sumXA[21]_i_4_n_0\
    );
\sumXA[21]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[40]\,
      I1 => \colsumX_reg_n_0_[19]\,
      O => \sumXA[21]_i_5_n_0\
    );
\sumXA[21]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[39]\,
      I1 => \colsumX_reg_n_0_[18]\,
      O => \sumXA[21]_i_6_n_0\
    );
\sumXA[21]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[38]\,
      I1 => \colsumX_reg_n_0_[17]\,
      O => \sumXA[21]_i_7_n_0\
    );
\sumXA[21]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[37]\,
      I1 => \colsumX_reg_n_0_[16]\,
      O => \sumXA[21]_i_8_n_0\
    );
\sumXA[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(0),
      O => \sumXA[22]_i_1_n_0\
    );
\sumXA[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(1),
      O => \sumXA[23]_i_1_n_0\
    );
\sumXA[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(2),
      O => \sumXA[24]_i_1_n_0\
    );
\sumXA[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(3),
      O => \sumXA[25]_i_1_n_0\
    );
\sumXA[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(4),
      O => \sumXA[26]_i_1_n_0\
    );
\sumXA[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(5),
      O => \sumXA[27]_i_1_n_0\
    );
\sumXA[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(6),
      O => \sumXA[28]_i_1_n_0\
    );
\sumXA[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(7),
      O => \sumXA[29]_i_1_n_0\
    );
\sumXA[29]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[63]\,
      I1 => \colsumX_reg_n_0_[42]\,
      O => \sumXA[29]_i_10_n_0\
    );
\sumXA[29]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[70]\,
      I1 => \colsumX_reg_n_0_[49]\,
      O => \sumXA[29]_i_3_n_0\
    );
\sumXA[29]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[69]\,
      I1 => \colsumX_reg_n_0_[48]\,
      O => \sumXA[29]_i_4_n_0\
    );
\sumXA[29]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[68]\,
      I1 => \colsumX_reg_n_0_[47]\,
      O => \sumXA[29]_i_5_n_0\
    );
\sumXA[29]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[67]\,
      I1 => \colsumX_reg_n_0_[46]\,
      O => \sumXA[29]_i_6_n_0\
    );
\sumXA[29]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[66]\,
      I1 => \colsumX_reg_n_0_[45]\,
      O => \sumXA[29]_i_7_n_0\
    );
\sumXA[29]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[65]\,
      I1 => \colsumX_reg_n_0_[44]\,
      O => \sumXA[29]_i_8_n_0\
    );
\sumXA[29]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[64]\,
      I1 => \colsumX_reg_n_0_[43]\,
      O => \sumXA[29]_i_9_n_0\
    );
\sumXA[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(2),
      O => \sumXA[2]_i_1_n_0\
    );
\sumXA[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(8),
      O => \sumXA[30]_i_1_n_0\
    );
\sumXA[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(9),
      O => \sumXA[31]_i_1_n_0\
    );
\sumXA[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(10),
      O => \sumXA[32]_i_1_n_0\
    );
\sumXA[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(11),
      O => \sumXA[33]_i_1_n_0\
    );
\sumXA[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(12),
      O => \sumXA[34]_i_1_n_0\
    );
\sumXA[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(13),
      O => \sumXA[35]_i_1_n_0\
    );
\sumXA[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(14),
      O => \sumXA[36]_i_1_n_0\
    );
\sumXA[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA00_in(15),
      O => \sumXA[37]_i_1_n_0\
    );
\sumXA[37]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[71]\,
      I1 => \colsumX_reg_n_0_[50]\,
      O => \sumXA[37]_i_10_n_0\
    );
\sumXA[37]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[78]\,
      I1 => \colsumX_reg_n_0_[57]\,
      O => \sumXA[37]_i_3_n_0\
    );
\sumXA[37]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[77]\,
      I1 => \colsumX_reg_n_0_[56]\,
      O => \sumXA[37]_i_4_n_0\
    );
\sumXA[37]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[76]\,
      I1 => \colsumX_reg_n_0_[55]\,
      O => \sumXA[37]_i_5_n_0\
    );
\sumXA[37]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[75]\,
      I1 => \colsumX_reg_n_0_[54]\,
      O => \sumXA[37]_i_6_n_0\
    );
\sumXA[37]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[74]\,
      I1 => \colsumX_reg_n_0_[53]\,
      O => \sumXA[37]_i_7_n_0\
    );
\sumXA[37]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[73]\,
      I1 => \colsumX_reg_n_0_[52]\,
      O => \sumXA[37]_i_8_n_0\
    );
\sumXA[37]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[72]\,
      I1 => \colsumX_reg_n_0_[51]\,
      O => \sumXA[37]_i_9_n_0\
    );
\sumXA[38]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumXA00_in(16),
      O => \sumXA[38]_i_1_n_0\
    );
\sumXA[39]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumXA00_in(17),
      O => \sumXA[39]_i_1_n_0\
    );
\sumXA[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(3),
      O => \sumXA[3]_i_1_n_0\
    );
\sumXA[40]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumXA00_in(18),
      O => \sumXA[40]_i_1_n_0\
    );
\sumXA[41]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumXA00_in(19),
      O => \sumXA[41]_i_1_n_0\
    );
\sumXA[42]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumXA00_in(20),
      O => \sumXA[42]_i_1_n_0\
    );
\sumXA[43]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => \sumXA_reg[43]_i_2_n_2\,
      O => \sumXA[43]_i_1_n_0\
    );
\sumXA[43]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \colsumX_reg_n_0_[83]\,
      O => \sumXA[43]_i_3_n_0\
    );
\sumXA[43]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[83]\,
      I1 => \colsumX_reg_n_0_[62]\,
      O => \sumXA[43]_i_4_n_0\
    );
\sumXA[43]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[82]\,
      I1 => \colsumX_reg_n_0_[61]\,
      O => \sumXA[43]_i_5_n_0\
    );
\sumXA[43]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[81]\,
      I1 => \colsumX_reg_n_0_[60]\,
      O => \sumXA[43]_i_6_n_0\
    );
\sumXA[43]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[80]\,
      I1 => \colsumX_reg_n_0_[59]\,
      O => \sumXA[43]_i_7_n_0\
    );
\sumXA[43]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[79]\,
      I1 => \colsumX_reg_n_0_[58]\,
      O => \sumXA[43]_i_8_n_0\
    );
\sumXA[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(4),
      O => \sumXA[4]_i_1_n_0\
    );
\sumXA[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(5),
      O => \sumXA[5]_i_1_n_0\
    );
\sumXA[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(6),
      O => \sumXA[6]_i_1_n_0\
    );
\sumXA[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(7),
      O => \sumXA[7]_i_1_n_0\
    );
\sumXA[7]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[21]\,
      I1 => \colsumX_reg_n_0_[0]\,
      O => \sumXA[7]_i_10_n_0\
    );
\sumXA[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[28]\,
      I1 => \colsumX_reg_n_0_[7]\,
      O => \sumXA[7]_i_3_n_0\
    );
\sumXA[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[27]\,
      I1 => \colsumX_reg_n_0_[6]\,
      O => \sumXA[7]_i_4_n_0\
    );
\sumXA[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[26]\,
      I1 => \colsumX_reg_n_0_[5]\,
      O => \sumXA[7]_i_5_n_0\
    );
\sumXA[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[25]\,
      I1 => \colsumX_reg_n_0_[4]\,
      O => \sumXA[7]_i_6_n_0\
    );
\sumXA[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[24]\,
      I1 => \colsumX_reg_n_0_[3]\,
      O => \sumXA[7]_i_7_n_0\
    );
\sumXA[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[23]\,
      I1 => \colsumX_reg_n_0_[2]\,
      O => \sumXA[7]_i_8_n_0\
    );
\sumXA[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumX_reg_n_0_[22]\,
      I1 => \colsumX_reg_n_0_[1]\,
      O => \sumXA[7]_i_9_n_0\
    );
\sumXA[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(8),
      O => \sumXA[8]_i_1_n_0\
    );
\sumXA[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__10_n_0\,
      I1 => sumXA0(9),
      O => \sumXA[9]_i_1_n_0\
    );
\sumXA_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[0]_i_1_n_0\,
      Q => sumXA(0)
    );
\sumXA_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[10]_i_1_n_0\,
      Q => sumXA(10)
    );
\sumXA_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[11]_i_1_n_0\,
      Q => sumXA(11)
    );
\sumXA_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[12]_i_1_n_0\,
      Q => sumXA(12)
    );
\sumXA_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[13]_i_1_n_0\,
      Q => sumXA(13)
    );
\sumXA_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[14]_i_1_n_0\,
      Q => sumXA(14)
    );
\sumXA_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[15]_i_1_n_0\,
      Q => sumXA(15)
    );
\sumXA_reg[15]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumXA_reg[7]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \sumXA_reg[15]_i_2_n_0\,
      CO(6) => \sumXA_reg[15]_i_2_n_1\,
      CO(5) => \sumXA_reg[15]_i_2_n_2\,
      CO(4) => \sumXA_reg[15]_i_2_n_3\,
      CO(3) => \sumXA_reg[15]_i_2_n_4\,
      CO(2) => \sumXA_reg[15]_i_2_n_5\,
      CO(1) => \sumXA_reg[15]_i_2_n_6\,
      CO(0) => \sumXA_reg[15]_i_2_n_7\,
      DI(7) => \colsumX_reg_n_0_[36]\,
      DI(6) => \colsumX_reg_n_0_[35]\,
      DI(5) => \colsumX_reg_n_0_[34]\,
      DI(4) => \colsumX_reg_n_0_[33]\,
      DI(3) => \colsumX_reg_n_0_[32]\,
      DI(2) => \colsumX_reg_n_0_[31]\,
      DI(1) => \colsumX_reg_n_0_[30]\,
      DI(0) => \colsumX_reg_n_0_[29]\,
      O(7 downto 0) => sumXA0(15 downto 8),
      S(7) => \sumXA[15]_i_3_n_0\,
      S(6) => \sumXA[15]_i_4_n_0\,
      S(5) => \sumXA[15]_i_5_n_0\,
      S(4) => \sumXA[15]_i_6_n_0\,
      S(3) => \sumXA[15]_i_7_n_0\,
      S(2) => \sumXA[15]_i_8_n_0\,
      S(1) => \sumXA[15]_i_9_n_0\,
      S(0) => \sumXA[15]_i_10_n_0\
    );
\sumXA_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[16]_i_1_n_0\,
      Q => sumXA(16)
    );
\sumXA_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[17]_i_1_n_0\,
      Q => sumXA(17)
    );
\sumXA_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[18]_i_1_n_0\,
      Q => sumXA(18)
    );
\sumXA_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[19]_i_1_n_0\,
      Q => sumXA(19)
    );
\sumXA_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[1]_i_1_n_0\,
      Q => sumXA(1)
    );
\sumXA_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[20]_i_1_n_0\,
      Q => sumXA(20)
    );
\sumXA_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[21]_i_1_n_0\,
      Q => sumXA(21)
    );
\sumXA_reg[21]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumXA_reg[15]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_sumXA_reg[21]_i_2_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \sumXA_reg[21]_i_2_n_2\,
      CO(4) => \NLW_sumXA_reg[21]_i_2_CO_UNCONNECTED\(4),
      CO(3) => \sumXA_reg[21]_i_2_n_4\,
      CO(2) => \sumXA_reg[21]_i_2_n_5\,
      CO(1) => \sumXA_reg[21]_i_2_n_6\,
      CO(0) => \sumXA_reg[21]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \sumXA[21]_i_3_n_0\,
      DI(3) => \colsumX_reg_n_0_[40]\,
      DI(2) => \colsumX_reg_n_0_[39]\,
      DI(1) => \colsumX_reg_n_0_[38]\,
      DI(0) => \colsumX_reg_n_0_[37]\,
      O(7 downto 5) => \NLW_sumXA_reg[21]_i_2_O_UNCONNECTED\(7 downto 5),
      O(4 downto 0) => sumXA0(20 downto 16),
      S(7 downto 5) => B"001",
      S(4) => \sumXA[21]_i_4_n_0\,
      S(3) => \sumXA[21]_i_5_n_0\,
      S(2) => \sumXA[21]_i_6_n_0\,
      S(1) => \sumXA[21]_i_7_n_0\,
      S(0) => \sumXA[21]_i_8_n_0\
    );
\sumXA_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[22]_i_1_n_0\,
      Q => sumXA(22)
    );
\sumXA_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[23]_i_1_n_0\,
      Q => sumXA(23)
    );
\sumXA_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[24]_i_1_n_0\,
      Q => sumXA(24)
    );
\sumXA_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[25]_i_1_n_0\,
      Q => sumXA(25)
    );
\sumXA_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[26]_i_1_n_0\,
      Q => sumXA(26)
    );
\sumXA_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[27]_i_1_n_0\,
      Q => sumXA(27)
    );
\sumXA_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[28]_i_1_n_0\,
      Q => sumXA(28)
    );
\sumXA_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[29]_i_1_n_0\,
      Q => sumXA(29)
    );
\sumXA_reg[29]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \sumXA_reg[29]_i_2_n_0\,
      CO(6) => \sumXA_reg[29]_i_2_n_1\,
      CO(5) => \sumXA_reg[29]_i_2_n_2\,
      CO(4) => \sumXA_reg[29]_i_2_n_3\,
      CO(3) => \sumXA_reg[29]_i_2_n_4\,
      CO(2) => \sumXA_reg[29]_i_2_n_5\,
      CO(1) => \sumXA_reg[29]_i_2_n_6\,
      CO(0) => \sumXA_reg[29]_i_2_n_7\,
      DI(7) => \colsumX_reg_n_0_[70]\,
      DI(6) => \colsumX_reg_n_0_[69]\,
      DI(5) => \colsumX_reg_n_0_[68]\,
      DI(4) => \colsumX_reg_n_0_[67]\,
      DI(3) => \colsumX_reg_n_0_[66]\,
      DI(2) => \colsumX_reg_n_0_[65]\,
      DI(1) => \colsumX_reg_n_0_[64]\,
      DI(0) => \colsumX_reg_n_0_[63]\,
      O(7 downto 0) => sumXA00_in(7 downto 0),
      S(7) => \sumXA[29]_i_3_n_0\,
      S(6) => \sumXA[29]_i_4_n_0\,
      S(5) => \sumXA[29]_i_5_n_0\,
      S(4) => \sumXA[29]_i_6_n_0\,
      S(3) => \sumXA[29]_i_7_n_0\,
      S(2) => \sumXA[29]_i_8_n_0\,
      S(1) => \sumXA[29]_i_9_n_0\,
      S(0) => \sumXA[29]_i_10_n_0\
    );
\sumXA_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[2]_i_1_n_0\,
      Q => sumXA(2)
    );
\sumXA_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[30]_i_1_n_0\,
      Q => sumXA(30)
    );
\sumXA_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[31]_i_1_n_0\,
      Q => sumXA(31)
    );
\sumXA_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[32]_i_1_n_0\,
      Q => sumXA(32)
    );
\sumXA_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[33]_i_1_n_0\,
      Q => sumXA(33)
    );
\sumXA_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[34]_i_1_n_0\,
      Q => sumXA(34)
    );
\sumXA_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[35]_i_1_n_0\,
      Q => sumXA(35)
    );
\sumXA_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[36]_i_1_n_0\,
      Q => sumXA(36)
    );
\sumXA_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[37]_i_1_n_0\,
      Q => sumXA(37)
    );
\sumXA_reg[37]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumXA_reg[29]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \sumXA_reg[37]_i_2_n_0\,
      CO(6) => \sumXA_reg[37]_i_2_n_1\,
      CO(5) => \sumXA_reg[37]_i_2_n_2\,
      CO(4) => \sumXA_reg[37]_i_2_n_3\,
      CO(3) => \sumXA_reg[37]_i_2_n_4\,
      CO(2) => \sumXA_reg[37]_i_2_n_5\,
      CO(1) => \sumXA_reg[37]_i_2_n_6\,
      CO(0) => \sumXA_reg[37]_i_2_n_7\,
      DI(7) => \colsumX_reg_n_0_[78]\,
      DI(6) => \colsumX_reg_n_0_[77]\,
      DI(5) => \colsumX_reg_n_0_[76]\,
      DI(4) => \colsumX_reg_n_0_[75]\,
      DI(3) => \colsumX_reg_n_0_[74]\,
      DI(2) => \colsumX_reg_n_0_[73]\,
      DI(1) => \colsumX_reg_n_0_[72]\,
      DI(0) => \colsumX_reg_n_0_[71]\,
      O(7 downto 0) => sumXA00_in(15 downto 8),
      S(7) => \sumXA[37]_i_3_n_0\,
      S(6) => \sumXA[37]_i_4_n_0\,
      S(5) => \sumXA[37]_i_5_n_0\,
      S(4) => \sumXA[37]_i_6_n_0\,
      S(3) => \sumXA[37]_i_7_n_0\,
      S(2) => \sumXA[37]_i_8_n_0\,
      S(1) => \sumXA[37]_i_9_n_0\,
      S(0) => \sumXA[37]_i_10_n_0\
    );
\sumXA_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[38]_i_1_n_0\,
      Q => sumXA(38)
    );
\sumXA_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[39]_i_1_n_0\,
      Q => sumXA(39)
    );
\sumXA_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[3]_i_1_n_0\,
      Q => sumXA(3)
    );
\sumXA_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[40]_i_1_n_0\,
      Q => sumXA(40)
    );
\sumXA_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[41]_i_1_n_0\,
      Q => sumXA(41)
    );
\sumXA_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[42]_i_1_n_0\,
      Q => sumXA(42)
    );
\sumXA_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[43]_i_1_n_0\,
      Q => sumXA(43)
    );
\sumXA_reg[43]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumXA_reg[37]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_sumXA_reg[43]_i_2_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \sumXA_reg[43]_i_2_n_2\,
      CO(4) => \NLW_sumXA_reg[43]_i_2_CO_UNCONNECTED\(4),
      CO(3) => \sumXA_reg[43]_i_2_n_4\,
      CO(2) => \sumXA_reg[43]_i_2_n_5\,
      CO(1) => \sumXA_reg[43]_i_2_n_6\,
      CO(0) => \sumXA_reg[43]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \sumXA[43]_i_3_n_0\,
      DI(3) => \colsumX_reg_n_0_[82]\,
      DI(2) => \colsumX_reg_n_0_[81]\,
      DI(1) => \colsumX_reg_n_0_[80]\,
      DI(0) => \colsumX_reg_n_0_[79]\,
      O(7 downto 5) => \NLW_sumXA_reg[43]_i_2_O_UNCONNECTED\(7 downto 5),
      O(4 downto 0) => sumXA00_in(20 downto 16),
      S(7 downto 5) => B"001",
      S(4) => \sumXA[43]_i_4_n_0\,
      S(3) => \sumXA[43]_i_5_n_0\,
      S(2) => \sumXA[43]_i_6_n_0\,
      S(1) => \sumXA[43]_i_7_n_0\,
      S(0) => \sumXA[43]_i_8_n_0\
    );
\sumXA_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[4]_i_1_n_0\,
      Q => sumXA(4)
    );
\sumXA_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[5]_i_1_n_0\,
      Q => sumXA(5)
    );
\sumXA_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[6]_i_1_n_0\,
      Q => sumXA(6)
    );
\sumXA_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[7]_i_1_n_0\,
      Q => sumXA(7)
    );
\sumXA_reg[7]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \sumXA_reg[7]_i_2_n_0\,
      CO(6) => \sumXA_reg[7]_i_2_n_1\,
      CO(5) => \sumXA_reg[7]_i_2_n_2\,
      CO(4) => \sumXA_reg[7]_i_2_n_3\,
      CO(3) => \sumXA_reg[7]_i_2_n_4\,
      CO(2) => \sumXA_reg[7]_i_2_n_5\,
      CO(1) => \sumXA_reg[7]_i_2_n_6\,
      CO(0) => \sumXA_reg[7]_i_2_n_7\,
      DI(7) => \colsumX_reg_n_0_[28]\,
      DI(6) => \colsumX_reg_n_0_[27]\,
      DI(5) => \colsumX_reg_n_0_[26]\,
      DI(4) => \colsumX_reg_n_0_[25]\,
      DI(3) => \colsumX_reg_n_0_[24]\,
      DI(2) => \colsumX_reg_n_0_[23]\,
      DI(1) => \colsumX_reg_n_0_[22]\,
      DI(0) => \colsumX_reg_n_0_[21]\,
      O(7 downto 0) => sumXA0(7 downto 0),
      S(7) => \sumXA[7]_i_3_n_0\,
      S(6) => \sumXA[7]_i_4_n_0\,
      S(5) => \sumXA[7]_i_5_n_0\,
      S(4) => \sumXA[7]_i_6_n_0\,
      S(3) => \sumXA[7]_i_7_n_0\,
      S(2) => \sumXA[7]_i_8_n_0\,
      S(1) => \sumXA[7]_i_9_n_0\,
      S(0) => \sumXA[7]_i_10_n_0\
    );
\sumXA_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[8]_i_1_n_0\,
      Q => sumXA(8)
    );
\sumXA_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXA[9]_i_1_n_0\,
      Q => sumXA(9)
    );
\sumXB[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(15),
      I1 => sumXA(37),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_10_n_0\
    );
\sumXB[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(14),
      I1 => sumXA(36),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_11_n_0\
    );
\sumXB[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(13),
      I1 => sumXA(35),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_12_n_0\
    );
\sumXB[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(12),
      I1 => sumXA(34),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_13_n_0\
    );
\sumXB[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(11),
      I1 => sumXA(33),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_14_n_0\
    );
\sumXB[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(10),
      I1 => sumXA(32),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_15_n_0\
    );
\sumXB[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(9),
      I1 => sumXA(31),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_16_n_0\
    );
\sumXB[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(8),
      I1 => sumXA(30),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_17_n_0\
    );
\sumXB[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(15),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_2_n_0\
    );
\sumXB[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(14),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_3_n_0\
    );
\sumXB[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(13),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_4_n_0\
    );
\sumXB[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(12),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_5_n_0\
    );
\sumXB[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(11),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_6_n_0\
    );
\sumXB[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(10),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_7_n_0\
    );
\sumXB[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(9),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_8_n_0\
    );
\sumXB[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(8),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[15]_i_9_n_0\
    );
\sumXB[22]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(20),
      I1 => sumXA(42),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumXB[22]_i_10_n_0\
    );
\sumXB[22]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(19),
      I1 => sumXA(41),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumXB[22]_i_11_n_0\
    );
\sumXB[22]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(18),
      I1 => sumXA(40),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumXB[22]_i_12_n_0\
    );
\sumXB[22]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(17),
      I1 => sumXA(39),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumXB[22]_i_13_n_0\
    );
\sumXB[22]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(16),
      I1 => sumXA(38),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumXB[22]_i_14_n_0\
    );
\sumXB[22]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(21),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumXB[22]_i_2_n_0\
    );
\sumXB[22]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(20),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumXB[22]_i_3_n_0\
    );
\sumXB[22]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(19),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumXB[22]_i_4_n_0\
    );
\sumXB[22]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(18),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumXB[22]_i_5_n_0\
    );
\sumXB[22]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(17),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumXB[22]_i_6_n_0\
    );
\sumXB[22]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(16),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumXB[22]_i_7_n_0\
    );
\sumXB[22]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(21),
      I1 => sumXA(43),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumXB[22]_i_8_n_0\
    );
\sumXB[22]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(21),
      I1 => sumXA(43),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumXB[22]_i_9_n_0\
    );
\sumXB[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(7),
      I1 => sumXA(29),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_10_n_0\
    );
\sumXB[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(6),
      I1 => sumXA(28),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_11_n_0\
    );
\sumXB[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(5),
      I1 => sumXA(27),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_12_n_0\
    );
\sumXB[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(4),
      I1 => sumXA(26),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_13_n_0\
    );
\sumXB[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(3),
      I1 => sumXA(25),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_14_n_0\
    );
\sumXB[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(2),
      I1 => sumXA(24),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_15_n_0\
    );
\sumXB[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(1),
      I1 => sumXA(23),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_16_n_0\
    );
\sumXB[7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXA(0),
      I1 => sumXA(22),
      I2 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_17_n_0\
    );
\sumXB[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(7),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_2_n_0\
    );
\sumXB[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(6),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_3_n_0\
    );
\sumXB[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(5),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_4_n_0\
    );
\sumXB[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(4),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_5_n_0\
    );
\sumXB[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(3),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_6_n_0\
    );
\sumXB[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(2),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_7_n_0\
    );
\sumXB[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(1),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_8_n_0\
    );
\sumXB[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXA(0),
      I1 => \stateScore_reg_rep__10_n_0\,
      O => \sumXB[7]_i_9_n_0\
    );
\sumXB_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[7]_i_1_n_15\,
      Q => \sumXB_reg_n_0_[0]\
    );
\sumXB_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[15]_i_1_n_13\,
      Q => \sumXB_reg_n_0_[10]\
    );
\sumXB_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[15]_i_1_n_12\,
      Q => \sumXB_reg_n_0_[11]\
    );
\sumXB_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[15]_i_1_n_11\,
      Q => \sumXB_reg_n_0_[12]\
    );
\sumXB_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[15]_i_1_n_10\,
      Q => \sumXB_reg_n_0_[13]\
    );
\sumXB_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[15]_i_1_n_9\,
      Q => \sumXB_reg_n_0_[14]\
    );
\sumXB_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[15]_i_1_n_8\,
      Q => \sumXB_reg_n_0_[15]\
    );
\sumXB_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumXB_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \sumXB_reg[15]_i_1_n_0\,
      CO(6) => \sumXB_reg[15]_i_1_n_1\,
      CO(5) => \sumXB_reg[15]_i_1_n_2\,
      CO(4) => \sumXB_reg[15]_i_1_n_3\,
      CO(3) => \sumXB_reg[15]_i_1_n_4\,
      CO(2) => \sumXB_reg[15]_i_1_n_5\,
      CO(1) => \sumXB_reg[15]_i_1_n_6\,
      CO(0) => \sumXB_reg[15]_i_1_n_7\,
      DI(7) => \sumXB[15]_i_2_n_0\,
      DI(6) => \sumXB[15]_i_3_n_0\,
      DI(5) => \sumXB[15]_i_4_n_0\,
      DI(4) => \sumXB[15]_i_5_n_0\,
      DI(3) => \sumXB[15]_i_6_n_0\,
      DI(2) => \sumXB[15]_i_7_n_0\,
      DI(1) => \sumXB[15]_i_8_n_0\,
      DI(0) => \sumXB[15]_i_9_n_0\,
      O(7) => \sumXB_reg[15]_i_1_n_8\,
      O(6) => \sumXB_reg[15]_i_1_n_9\,
      O(5) => \sumXB_reg[15]_i_1_n_10\,
      O(4) => \sumXB_reg[15]_i_1_n_11\,
      O(3) => \sumXB_reg[15]_i_1_n_12\,
      O(2) => \sumXB_reg[15]_i_1_n_13\,
      O(1) => \sumXB_reg[15]_i_1_n_14\,
      O(0) => \sumXB_reg[15]_i_1_n_15\,
      S(7) => \sumXB[15]_i_10_n_0\,
      S(6) => \sumXB[15]_i_11_n_0\,
      S(5) => \sumXB[15]_i_12_n_0\,
      S(4) => \sumXB[15]_i_13_n_0\,
      S(3) => \sumXB[15]_i_14_n_0\,
      S(2) => \sumXB[15]_i_15_n_0\,
      S(1) => \sumXB[15]_i_16_n_0\,
      S(0) => \sumXB[15]_i_17_n_0\
    );
\sumXB_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[22]_i_1_n_15\,
      Q => \sumXB_reg_n_0_[16]\
    );
\sumXB_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[22]_i_1_n_14\,
      Q => \sumXB_reg_n_0_[17]\
    );
\sumXB_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[22]_i_1_n_13\,
      Q => \sumXB_reg_n_0_[18]\
    );
\sumXB_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[22]_i_1_n_12\,
      Q => \sumXB_reg_n_0_[19]\
    );
\sumXB_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[7]_i_1_n_14\,
      Q => \sumXB_reg_n_0_[1]\
    );
\sumXB_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[22]_i_1_n_11\,
      Q => \sumXB_reg_n_0_[20]\
    );
\sumXB_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[22]_i_1_n_10\,
      Q => \sumXB_reg_n_0_[21]\
    );
\sumXB_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[22]_i_1_n_9\,
      Q => \sumXB_reg_n_0_[22]\
    );
\sumXB_reg[22]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumXB_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_sumXB_reg[22]_i_1_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \sumXB_reg[22]_i_1_n_2\,
      CO(4) => \sumXB_reg[22]_i_1_n_3\,
      CO(3) => \sumXB_reg[22]_i_1_n_4\,
      CO(2) => \sumXB_reg[22]_i_1_n_5\,
      CO(1) => \sumXB_reg[22]_i_1_n_6\,
      CO(0) => \sumXB_reg[22]_i_1_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \sumXB[22]_i_2_n_0\,
      DI(4) => \sumXB[22]_i_3_n_0\,
      DI(3) => \sumXB[22]_i_4_n_0\,
      DI(2) => \sumXB[22]_i_5_n_0\,
      DI(1) => \sumXB[22]_i_6_n_0\,
      DI(0) => \sumXB[22]_i_7_n_0\,
      O(7) => \NLW_sumXB_reg[22]_i_1_O_UNCONNECTED\(7),
      O(6) => \sumXB_reg[22]_i_1_n_9\,
      O(5) => \sumXB_reg[22]_i_1_n_10\,
      O(4) => \sumXB_reg[22]_i_1_n_11\,
      O(3) => \sumXB_reg[22]_i_1_n_12\,
      O(2) => \sumXB_reg[22]_i_1_n_13\,
      O(1) => \sumXB_reg[22]_i_1_n_14\,
      O(0) => \sumXB_reg[22]_i_1_n_15\,
      S(7) => '0',
      S(6) => \sumXB[22]_i_8_n_0\,
      S(5) => \sumXB[22]_i_9_n_0\,
      S(4) => \sumXB[22]_i_10_n_0\,
      S(3) => \sumXB[22]_i_11_n_0\,
      S(2) => \sumXB[22]_i_12_n_0\,
      S(1) => \sumXB[22]_i_13_n_0\,
      S(0) => \sumXB[22]_i_14_n_0\
    );
\sumXB_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[7]_i_1_n_13\,
      Q => \sumXB_reg_n_0_[2]\
    );
\sumXB_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[7]_i_1_n_12\,
      Q => \sumXB_reg_n_0_[3]\
    );
\sumXB_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[7]_i_1_n_11\,
      Q => \sumXB_reg_n_0_[4]\
    );
\sumXB_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[7]_i_1_n_10\,
      Q => \sumXB_reg_n_0_[5]\
    );
\sumXB_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[7]_i_1_n_9\,
      Q => \sumXB_reg_n_0_[6]\
    );
\sumXB_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[7]_i_1_n_8\,
      Q => \sumXB_reg_n_0_[7]\
    );
\sumXB_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \sumXB_reg[7]_i_1_n_0\,
      CO(6) => \sumXB_reg[7]_i_1_n_1\,
      CO(5) => \sumXB_reg[7]_i_1_n_2\,
      CO(4) => \sumXB_reg[7]_i_1_n_3\,
      CO(3) => \sumXB_reg[7]_i_1_n_4\,
      CO(2) => \sumXB_reg[7]_i_1_n_5\,
      CO(1) => \sumXB_reg[7]_i_1_n_6\,
      CO(0) => \sumXB_reg[7]_i_1_n_7\,
      DI(7) => \sumXB[7]_i_2_n_0\,
      DI(6) => \sumXB[7]_i_3_n_0\,
      DI(5) => \sumXB[7]_i_4_n_0\,
      DI(4) => \sumXB[7]_i_5_n_0\,
      DI(3) => \sumXB[7]_i_6_n_0\,
      DI(2) => \sumXB[7]_i_7_n_0\,
      DI(1) => \sumXB[7]_i_8_n_0\,
      DI(0) => \sumXB[7]_i_9_n_0\,
      O(7) => \sumXB_reg[7]_i_1_n_8\,
      O(6) => \sumXB_reg[7]_i_1_n_9\,
      O(5) => \sumXB_reg[7]_i_1_n_10\,
      O(4) => \sumXB_reg[7]_i_1_n_11\,
      O(3) => \sumXB_reg[7]_i_1_n_12\,
      O(2) => \sumXB_reg[7]_i_1_n_13\,
      O(1) => \sumXB_reg[7]_i_1_n_14\,
      O(0) => \sumXB_reg[7]_i_1_n_15\,
      S(7) => \sumXB[7]_i_10_n_0\,
      S(6) => \sumXB[7]_i_11_n_0\,
      S(5) => \sumXB[7]_i_12_n_0\,
      S(4) => \sumXB[7]_i_13_n_0\,
      S(3) => \sumXB[7]_i_14_n_0\,
      S(2) => \sumXB[7]_i_15_n_0\,
      S(1) => \sumXB[7]_i_16_n_0\,
      S(0) => \sumXB[7]_i_17_n_0\
    );
\sumXB_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[15]_i_1_n_15\,
      Q => \sumXB_reg_n_0_[8]\
    );
\sumXB_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXB_reg[15]_i_1_n_14\,
      Q => \sumXB_reg_n_0_[9]\
    );
\sumXYA[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(0),
      O => \sumXYA[0]_i_1_n_0\
    );
\sumXYA[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(10),
      O => \sumXYA[10]_i_1_n_0\
    );
\sumXYA[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(11),
      O => \sumXYA[11]_i_1_n_0\
    );
\sumXYA[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(12),
      O => \sumXYA[12]_i_1_n_0\
    );
\sumXYA[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(13),
      O => \sumXYA[13]_i_1_n_0\
    );
\sumXYA[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(14),
      O => \sumXYA[14]_i_1_n_0\
    );
\sumXYA[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(15),
      O => \sumXYA[15]_i_1_n_0\
    );
\sumXYA[15]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[29]\,
      I1 => \colsumXY_reg_n_0_[8]\,
      O => \sumXYA[15]_i_10_n_0\
    );
\sumXYA[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[36]\,
      I1 => \colsumXY_reg_n_0_[15]\,
      O => \sumXYA[15]_i_3_n_0\
    );
\sumXYA[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[35]\,
      I1 => \colsumXY_reg_n_0_[14]\,
      O => \sumXYA[15]_i_4_n_0\
    );
\sumXYA[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[34]\,
      I1 => \colsumXY_reg_n_0_[13]\,
      O => \sumXYA[15]_i_5_n_0\
    );
\sumXYA[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[33]\,
      I1 => \colsumXY_reg_n_0_[12]\,
      O => \sumXYA[15]_i_6_n_0\
    );
\sumXYA[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[32]\,
      I1 => \colsumXY_reg_n_0_[11]\,
      O => \sumXYA[15]_i_7_n_0\
    );
\sumXYA[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[31]\,
      I1 => \colsumXY_reg_n_0_[10]\,
      O => \sumXYA[15]_i_8_n_0\
    );
\sumXYA[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[30]\,
      I1 => \colsumXY_reg_n_0_[9]\,
      O => \sumXYA[15]_i_9_n_0\
    );
\sumXYA[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => sumXYA0(16),
      O => \sumXYA[16]_i_1_n_0\
    );
\sumXYA[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => sumXYA0(17),
      O => \sumXYA[17]_i_1_n_0\
    );
\sumXYA[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => sumXYA0(18),
      O => \sumXYA[18]_i_1_n_0\
    );
\sumXYA[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => sumXYA0(19),
      O => \sumXYA[19]_i_1_n_0\
    );
\sumXYA[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(1),
      O => \sumXYA[1]_i_1_n_0\
    );
\sumXYA[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => sumXYA0(20),
      O => \sumXYA[20]_i_1_n_0\
    );
\sumXYA[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => \sumXYA_reg[21]_i_2_n_2\,
      O => \sumXYA[21]_i_1_n_0\
    );
\sumXYA[21]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[41]\,
      O => \sumXYA[21]_i_3_n_0\
    );
\sumXYA[21]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[41]\,
      I1 => \colsumXY_reg_n_0_[20]\,
      O => \sumXYA[21]_i_4_n_0\
    );
\sumXYA[21]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[40]\,
      I1 => \colsumXY_reg_n_0_[19]\,
      O => \sumXYA[21]_i_5_n_0\
    );
\sumXYA[21]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[39]\,
      I1 => \colsumXY_reg_n_0_[18]\,
      O => \sumXYA[21]_i_6_n_0\
    );
\sumXYA[21]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[38]\,
      I1 => \colsumXY_reg_n_0_[17]\,
      O => \sumXYA[21]_i_7_n_0\
    );
\sumXYA[21]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[37]\,
      I1 => \colsumXY_reg_n_0_[16]\,
      O => \sumXYA[21]_i_8_n_0\
    );
\sumXYA[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(0),
      O => \sumXYA[22]_i_1_n_0\
    );
\sumXYA[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(1),
      O => \sumXYA[23]_i_1_n_0\
    );
\sumXYA[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(2),
      O => \sumXYA[24]_i_1_n_0\
    );
\sumXYA[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(3),
      O => \sumXYA[25]_i_1_n_0\
    );
\sumXYA[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(4),
      O => \sumXYA[26]_i_1_n_0\
    );
\sumXYA[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(5),
      O => \sumXYA[27]_i_1_n_0\
    );
\sumXYA[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(6),
      O => \sumXYA[28]_i_1_n_0\
    );
\sumXYA[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(7),
      O => \sumXYA[29]_i_1_n_0\
    );
\sumXYA[29]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[63]\,
      I1 => \colsumXY_reg_n_0_[42]\,
      O => \sumXYA[29]_i_10_n_0\
    );
\sumXYA[29]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[70]\,
      I1 => \colsumXY_reg_n_0_[49]\,
      O => \sumXYA[29]_i_3_n_0\
    );
\sumXYA[29]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[69]\,
      I1 => \colsumXY_reg_n_0_[48]\,
      O => \sumXYA[29]_i_4_n_0\
    );
\sumXYA[29]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[68]\,
      I1 => \colsumXY_reg_n_0_[47]\,
      O => \sumXYA[29]_i_5_n_0\
    );
\sumXYA[29]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[67]\,
      I1 => \colsumXY_reg_n_0_[46]\,
      O => \sumXYA[29]_i_6_n_0\
    );
\sumXYA[29]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[66]\,
      I1 => \colsumXY_reg_n_0_[45]\,
      O => \sumXYA[29]_i_7_n_0\
    );
\sumXYA[29]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[65]\,
      I1 => \colsumXY_reg_n_0_[44]\,
      O => \sumXYA[29]_i_8_n_0\
    );
\sumXYA[29]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[64]\,
      I1 => \colsumXY_reg_n_0_[43]\,
      O => \sumXYA[29]_i_9_n_0\
    );
\sumXYA[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(2),
      O => \sumXYA[2]_i_1_n_0\
    );
\sumXYA[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(8),
      O => \sumXYA[30]_i_1_n_0\
    );
\sumXYA[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(9),
      O => \sumXYA[31]_i_1_n_0\
    );
\sumXYA[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(10),
      O => \sumXYA[32]_i_1_n_0\
    );
\sumXYA[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(11),
      O => \sumXYA[33]_i_1_n_0\
    );
\sumXYA[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(12),
      O => \sumXYA[34]_i_1_n_0\
    );
\sumXYA[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(13),
      O => \sumXYA[35]_i_1_n_0\
    );
\sumXYA[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(14),
      O => \sumXYA[36]_i_1_n_0\
    );
\sumXYA[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA00_in(15),
      O => \sumXYA[37]_i_1_n_0\
    );
\sumXYA[37]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[71]\,
      I1 => \colsumXY_reg_n_0_[50]\,
      O => \sumXYA[37]_i_10_n_0\
    );
\sumXYA[37]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[78]\,
      I1 => \colsumXY_reg_n_0_[57]\,
      O => \sumXYA[37]_i_3_n_0\
    );
\sumXYA[37]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[77]\,
      I1 => \colsumXY_reg_n_0_[56]\,
      O => \sumXYA[37]_i_4_n_0\
    );
\sumXYA[37]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[76]\,
      I1 => \colsumXY_reg_n_0_[55]\,
      O => \sumXYA[37]_i_5_n_0\
    );
\sumXYA[37]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[75]\,
      I1 => \colsumXY_reg_n_0_[54]\,
      O => \sumXYA[37]_i_6_n_0\
    );
\sumXYA[37]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[74]\,
      I1 => \colsumXY_reg_n_0_[53]\,
      O => \sumXYA[37]_i_7_n_0\
    );
\sumXYA[37]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[73]\,
      I1 => \colsumXY_reg_n_0_[52]\,
      O => \sumXYA[37]_i_8_n_0\
    );
\sumXYA[37]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[72]\,
      I1 => \colsumXY_reg_n_0_[51]\,
      O => \sumXYA[37]_i_9_n_0\
    );
\sumXYA[38]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => sumXYA00_in(16),
      O => \sumXYA[38]_i_1_n_0\
    );
\sumXYA[39]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => sumXYA00_in(17),
      O => \sumXYA[39]_i_1_n_0\
    );
\sumXYA[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(3),
      O => \sumXYA[3]_i_1_n_0\
    );
\sumXYA[40]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => sumXYA00_in(18),
      O => \sumXYA[40]_i_1_n_0\
    );
\sumXYA[41]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => sumXYA00_in(19),
      O => \sumXYA[41]_i_1_n_0\
    );
\sumXYA[42]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => sumXYA00_in(20),
      O => \sumXYA[42]_i_1_n_0\
    );
\sumXYA[43]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__0_n_0\,
      I1 => \sumXYA_reg[43]_i_2_n_2\,
      O => \sumXYA[43]_i_1_n_0\
    );
\sumXYA[43]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[83]\,
      O => \sumXYA[43]_i_3_n_0\
    );
\sumXYA[43]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[83]\,
      I1 => \colsumXY_reg_n_0_[62]\,
      O => \sumXYA[43]_i_4_n_0\
    );
\sumXYA[43]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[82]\,
      I1 => \colsumXY_reg_n_0_[61]\,
      O => \sumXYA[43]_i_5_n_0\
    );
\sumXYA[43]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[81]\,
      I1 => \colsumXY_reg_n_0_[60]\,
      O => \sumXYA[43]_i_6_n_0\
    );
\sumXYA[43]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[80]\,
      I1 => \colsumXY_reg_n_0_[59]\,
      O => \sumXYA[43]_i_7_n_0\
    );
\sumXYA[43]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[79]\,
      I1 => \colsumXY_reg_n_0_[58]\,
      O => \sumXYA[43]_i_8_n_0\
    );
\sumXYA[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(4),
      O => \sumXYA[4]_i_1_n_0\
    );
\sumXYA[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(5),
      O => \sumXYA[5]_i_1_n_0\
    );
\sumXYA[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(6),
      O => \sumXYA[6]_i_1_n_0\
    );
\sumXYA[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(7),
      O => \sumXYA[7]_i_1_n_0\
    );
\sumXYA[7]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[21]\,
      I1 => \colsumXY_reg_n_0_[0]\,
      O => \sumXYA[7]_i_10_n_0\
    );
\sumXYA[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[28]\,
      I1 => \colsumXY_reg_n_0_[7]\,
      O => \sumXYA[7]_i_3_n_0\
    );
\sumXYA[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[27]\,
      I1 => \colsumXY_reg_n_0_[6]\,
      O => \sumXYA[7]_i_4_n_0\
    );
\sumXYA[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[26]\,
      I1 => \colsumXY_reg_n_0_[5]\,
      O => \sumXYA[7]_i_5_n_0\
    );
\sumXYA[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[25]\,
      I1 => \colsumXY_reg_n_0_[4]\,
      O => \sumXYA[7]_i_6_n_0\
    );
\sumXYA[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[24]\,
      I1 => \colsumXY_reg_n_0_[3]\,
      O => \sumXYA[7]_i_7_n_0\
    );
\sumXYA[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[23]\,
      I1 => \colsumXY_reg_n_0_[2]\,
      O => \sumXYA[7]_i_8_n_0\
    );
\sumXYA[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumXY_reg_n_0_[22]\,
      I1 => \colsumXY_reg_n_0_[1]\,
      O => \sumXYA[7]_i_9_n_0\
    );
\sumXYA[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(8),
      O => \sumXYA[8]_i_1_n_0\
    );
\sumXYA[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stateScore_reg_rep_n_0,
      I1 => sumXYA0(9),
      O => \sumXYA[9]_i_1_n_0\
    );
\sumXYA_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[0]_i_1_n_0\,
      Q => sumXYA(0)
    );
\sumXYA_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[10]_i_1_n_0\,
      Q => sumXYA(10)
    );
\sumXYA_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[11]_i_1_n_0\,
      Q => sumXYA(11)
    );
\sumXYA_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[12]_i_1_n_0\,
      Q => sumXYA(12)
    );
\sumXYA_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[13]_i_1_n_0\,
      Q => sumXYA(13)
    );
\sumXYA_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[14]_i_1_n_0\,
      Q => sumXYA(14)
    );
\sumXYA_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[15]_i_1_n_0\,
      Q => sumXYA(15)
    );
\sumXYA_reg[15]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumXYA_reg[7]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \sumXYA_reg[15]_i_2_n_0\,
      CO(6) => \sumXYA_reg[15]_i_2_n_1\,
      CO(5) => \sumXYA_reg[15]_i_2_n_2\,
      CO(4) => \sumXYA_reg[15]_i_2_n_3\,
      CO(3) => \sumXYA_reg[15]_i_2_n_4\,
      CO(2) => \sumXYA_reg[15]_i_2_n_5\,
      CO(1) => \sumXYA_reg[15]_i_2_n_6\,
      CO(0) => \sumXYA_reg[15]_i_2_n_7\,
      DI(7) => \colsumXY_reg_n_0_[36]\,
      DI(6) => \colsumXY_reg_n_0_[35]\,
      DI(5) => \colsumXY_reg_n_0_[34]\,
      DI(4) => \colsumXY_reg_n_0_[33]\,
      DI(3) => \colsumXY_reg_n_0_[32]\,
      DI(2) => \colsumXY_reg_n_0_[31]\,
      DI(1) => \colsumXY_reg_n_0_[30]\,
      DI(0) => \colsumXY_reg_n_0_[29]\,
      O(7 downto 0) => sumXYA0(15 downto 8),
      S(7) => \sumXYA[15]_i_3_n_0\,
      S(6) => \sumXYA[15]_i_4_n_0\,
      S(5) => \sumXYA[15]_i_5_n_0\,
      S(4) => \sumXYA[15]_i_6_n_0\,
      S(3) => \sumXYA[15]_i_7_n_0\,
      S(2) => \sumXYA[15]_i_8_n_0\,
      S(1) => \sumXYA[15]_i_9_n_0\,
      S(0) => \sumXYA[15]_i_10_n_0\
    );
\sumXYA_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[16]_i_1_n_0\,
      Q => sumXYA(16)
    );
\sumXYA_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[17]_i_1_n_0\,
      Q => sumXYA(17)
    );
\sumXYA_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[18]_i_1_n_0\,
      Q => sumXYA(18)
    );
\sumXYA_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[19]_i_1_n_0\,
      Q => sumXYA(19)
    );
\sumXYA_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[1]_i_1_n_0\,
      Q => sumXYA(1)
    );
\sumXYA_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[20]_i_1_n_0\,
      Q => sumXYA(20)
    );
\sumXYA_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[21]_i_1_n_0\,
      Q => sumXYA(21)
    );
\sumXYA_reg[21]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumXYA_reg[15]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_sumXYA_reg[21]_i_2_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \sumXYA_reg[21]_i_2_n_2\,
      CO(4) => \NLW_sumXYA_reg[21]_i_2_CO_UNCONNECTED\(4),
      CO(3) => \sumXYA_reg[21]_i_2_n_4\,
      CO(2) => \sumXYA_reg[21]_i_2_n_5\,
      CO(1) => \sumXYA_reg[21]_i_2_n_6\,
      CO(0) => \sumXYA_reg[21]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \sumXYA[21]_i_3_n_0\,
      DI(3) => \colsumXY_reg_n_0_[40]\,
      DI(2) => \colsumXY_reg_n_0_[39]\,
      DI(1) => \colsumXY_reg_n_0_[38]\,
      DI(0) => \colsumXY_reg_n_0_[37]\,
      O(7 downto 5) => \NLW_sumXYA_reg[21]_i_2_O_UNCONNECTED\(7 downto 5),
      O(4 downto 0) => sumXYA0(20 downto 16),
      S(7 downto 5) => B"001",
      S(4) => \sumXYA[21]_i_4_n_0\,
      S(3) => \sumXYA[21]_i_5_n_0\,
      S(2) => \sumXYA[21]_i_6_n_0\,
      S(1) => \sumXYA[21]_i_7_n_0\,
      S(0) => \sumXYA[21]_i_8_n_0\
    );
\sumXYA_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[22]_i_1_n_0\,
      Q => sumXYA(22)
    );
\sumXYA_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[23]_i_1_n_0\,
      Q => sumXYA(23)
    );
\sumXYA_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[24]_i_1_n_0\,
      Q => sumXYA(24)
    );
\sumXYA_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[25]_i_1_n_0\,
      Q => sumXYA(25)
    );
\sumXYA_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[26]_i_1_n_0\,
      Q => sumXYA(26)
    );
\sumXYA_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[27]_i_1_n_0\,
      Q => sumXYA(27)
    );
\sumXYA_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[28]_i_1_n_0\,
      Q => sumXYA(28)
    );
\sumXYA_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[29]_i_1_n_0\,
      Q => sumXYA(29)
    );
\sumXYA_reg[29]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \sumXYA_reg[29]_i_2_n_0\,
      CO(6) => \sumXYA_reg[29]_i_2_n_1\,
      CO(5) => \sumXYA_reg[29]_i_2_n_2\,
      CO(4) => \sumXYA_reg[29]_i_2_n_3\,
      CO(3) => \sumXYA_reg[29]_i_2_n_4\,
      CO(2) => \sumXYA_reg[29]_i_2_n_5\,
      CO(1) => \sumXYA_reg[29]_i_2_n_6\,
      CO(0) => \sumXYA_reg[29]_i_2_n_7\,
      DI(7) => \colsumXY_reg_n_0_[70]\,
      DI(6) => \colsumXY_reg_n_0_[69]\,
      DI(5) => \colsumXY_reg_n_0_[68]\,
      DI(4) => \colsumXY_reg_n_0_[67]\,
      DI(3) => \colsumXY_reg_n_0_[66]\,
      DI(2) => \colsumXY_reg_n_0_[65]\,
      DI(1) => \colsumXY_reg_n_0_[64]\,
      DI(0) => \colsumXY_reg_n_0_[63]\,
      O(7 downto 0) => sumXYA00_in(7 downto 0),
      S(7) => \sumXYA[29]_i_3_n_0\,
      S(6) => \sumXYA[29]_i_4_n_0\,
      S(5) => \sumXYA[29]_i_5_n_0\,
      S(4) => \sumXYA[29]_i_6_n_0\,
      S(3) => \sumXYA[29]_i_7_n_0\,
      S(2) => \sumXYA[29]_i_8_n_0\,
      S(1) => \sumXYA[29]_i_9_n_0\,
      S(0) => \sumXYA[29]_i_10_n_0\
    );
\sumXYA_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[2]_i_1_n_0\,
      Q => sumXYA(2)
    );
\sumXYA_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[30]_i_1_n_0\,
      Q => sumXYA(30)
    );
\sumXYA_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[31]_i_1_n_0\,
      Q => sumXYA(31)
    );
\sumXYA_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[32]_i_1_n_0\,
      Q => sumXYA(32)
    );
\sumXYA_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[33]_i_1_n_0\,
      Q => sumXYA(33)
    );
\sumXYA_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[34]_i_1_n_0\,
      Q => sumXYA(34)
    );
\sumXYA_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[35]_i_1_n_0\,
      Q => sumXYA(35)
    );
\sumXYA_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[36]_i_1_n_0\,
      Q => sumXYA(36)
    );
\sumXYA_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[37]_i_1_n_0\,
      Q => sumXYA(37)
    );
\sumXYA_reg[37]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumXYA_reg[29]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \sumXYA_reg[37]_i_2_n_0\,
      CO(6) => \sumXYA_reg[37]_i_2_n_1\,
      CO(5) => \sumXYA_reg[37]_i_2_n_2\,
      CO(4) => \sumXYA_reg[37]_i_2_n_3\,
      CO(3) => \sumXYA_reg[37]_i_2_n_4\,
      CO(2) => \sumXYA_reg[37]_i_2_n_5\,
      CO(1) => \sumXYA_reg[37]_i_2_n_6\,
      CO(0) => \sumXYA_reg[37]_i_2_n_7\,
      DI(7) => \colsumXY_reg_n_0_[78]\,
      DI(6) => \colsumXY_reg_n_0_[77]\,
      DI(5) => \colsumXY_reg_n_0_[76]\,
      DI(4) => \colsumXY_reg_n_0_[75]\,
      DI(3) => \colsumXY_reg_n_0_[74]\,
      DI(2) => \colsumXY_reg_n_0_[73]\,
      DI(1) => \colsumXY_reg_n_0_[72]\,
      DI(0) => \colsumXY_reg_n_0_[71]\,
      O(7 downto 0) => sumXYA00_in(15 downto 8),
      S(7) => \sumXYA[37]_i_3_n_0\,
      S(6) => \sumXYA[37]_i_4_n_0\,
      S(5) => \sumXYA[37]_i_5_n_0\,
      S(4) => \sumXYA[37]_i_6_n_0\,
      S(3) => \sumXYA[37]_i_7_n_0\,
      S(2) => \sumXYA[37]_i_8_n_0\,
      S(1) => \sumXYA[37]_i_9_n_0\,
      S(0) => \sumXYA[37]_i_10_n_0\
    );
\sumXYA_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[38]_i_1_n_0\,
      Q => sumXYA(38)
    );
\sumXYA_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[39]_i_1_n_0\,
      Q => sumXYA(39)
    );
\sumXYA_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[3]_i_1_n_0\,
      Q => sumXYA(3)
    );
\sumXYA_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[40]_i_1_n_0\,
      Q => sumXYA(40)
    );
\sumXYA_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[41]_i_1_n_0\,
      Q => sumXYA(41)
    );
\sumXYA_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[42]_i_1_n_0\,
      Q => sumXYA(42)
    );
\sumXYA_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[43]_i_1_n_0\,
      Q => sumXYA(43)
    );
\sumXYA_reg[43]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumXYA_reg[37]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_sumXYA_reg[43]_i_2_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \sumXYA_reg[43]_i_2_n_2\,
      CO(4) => \NLW_sumXYA_reg[43]_i_2_CO_UNCONNECTED\(4),
      CO(3) => \sumXYA_reg[43]_i_2_n_4\,
      CO(2) => \sumXYA_reg[43]_i_2_n_5\,
      CO(1) => \sumXYA_reg[43]_i_2_n_6\,
      CO(0) => \sumXYA_reg[43]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \sumXYA[43]_i_3_n_0\,
      DI(3) => \colsumXY_reg_n_0_[82]\,
      DI(2) => \colsumXY_reg_n_0_[81]\,
      DI(1) => \colsumXY_reg_n_0_[80]\,
      DI(0) => \colsumXY_reg_n_0_[79]\,
      O(7 downto 5) => \NLW_sumXYA_reg[43]_i_2_O_UNCONNECTED\(7 downto 5),
      O(4 downto 0) => sumXYA00_in(20 downto 16),
      S(7 downto 5) => B"001",
      S(4) => \sumXYA[43]_i_4_n_0\,
      S(3) => \sumXYA[43]_i_5_n_0\,
      S(2) => \sumXYA[43]_i_6_n_0\,
      S(1) => \sumXYA[43]_i_7_n_0\,
      S(0) => \sumXYA[43]_i_8_n_0\
    );
\sumXYA_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[4]_i_1_n_0\,
      Q => sumXYA(4)
    );
\sumXYA_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[5]_i_1_n_0\,
      Q => sumXYA(5)
    );
\sumXYA_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[6]_i_1_n_0\,
      Q => sumXYA(6)
    );
\sumXYA_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[7]_i_1_n_0\,
      Q => sumXYA(7)
    );
\sumXYA_reg[7]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \sumXYA_reg[7]_i_2_n_0\,
      CO(6) => \sumXYA_reg[7]_i_2_n_1\,
      CO(5) => \sumXYA_reg[7]_i_2_n_2\,
      CO(4) => \sumXYA_reg[7]_i_2_n_3\,
      CO(3) => \sumXYA_reg[7]_i_2_n_4\,
      CO(2) => \sumXYA_reg[7]_i_2_n_5\,
      CO(1) => \sumXYA_reg[7]_i_2_n_6\,
      CO(0) => \sumXYA_reg[7]_i_2_n_7\,
      DI(7) => \colsumXY_reg_n_0_[28]\,
      DI(6) => \colsumXY_reg_n_0_[27]\,
      DI(5) => \colsumXY_reg_n_0_[26]\,
      DI(4) => \colsumXY_reg_n_0_[25]\,
      DI(3) => \colsumXY_reg_n_0_[24]\,
      DI(2) => \colsumXY_reg_n_0_[23]\,
      DI(1) => \colsumXY_reg_n_0_[22]\,
      DI(0) => \colsumXY_reg_n_0_[21]\,
      O(7 downto 0) => sumXYA0(7 downto 0),
      S(7) => \sumXYA[7]_i_3_n_0\,
      S(6) => \sumXYA[7]_i_4_n_0\,
      S(5) => \sumXYA[7]_i_5_n_0\,
      S(4) => \sumXYA[7]_i_6_n_0\,
      S(3) => \sumXYA[7]_i_7_n_0\,
      S(2) => \sumXYA[7]_i_8_n_0\,
      S(1) => \sumXYA[7]_i_9_n_0\,
      S(0) => \sumXYA[7]_i_10_n_0\
    );
\sumXYA_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[8]_i_1_n_0\,
      Q => sumXYA(8)
    );
\sumXYA_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYA[9]_i_1_n_0\,
      Q => sumXYA(9)
    );
\sumXYB[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(15),
      I1 => sumXYA(37),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_10_n_0\
    );
\sumXYB[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(14),
      I1 => sumXYA(36),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_11_n_0\
    );
\sumXYB[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(13),
      I1 => sumXYA(35),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_12_n_0\
    );
\sumXYB[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(12),
      I1 => sumXYA(34),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_13_n_0\
    );
\sumXYB[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(11),
      I1 => sumXYA(33),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_14_n_0\
    );
\sumXYB[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(10),
      I1 => sumXYA(32),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_15_n_0\
    );
\sumXYB[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(9),
      I1 => sumXYA(31),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_16_n_0\
    );
\sumXYB[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(8),
      I1 => sumXYA(30),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_17_n_0\
    );
\sumXYB[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(15),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_2_n_0\
    );
\sumXYB[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(14),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_3_n_0\
    );
\sumXYB[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(13),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_4_n_0\
    );
\sumXYB[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(12),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_5_n_0\
    );
\sumXYB[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(11),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_6_n_0\
    );
\sumXYB[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(10),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_7_n_0\
    );
\sumXYB[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(9),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_8_n_0\
    );
\sumXYB[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(8),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[15]_i_9_n_0\
    );
\sumXYB[22]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(20),
      I1 => sumXYA(42),
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \sumXYB[22]_i_10_n_0\
    );
\sumXYB[22]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(19),
      I1 => sumXYA(41),
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \sumXYB[22]_i_11_n_0\
    );
\sumXYB[22]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(18),
      I1 => sumXYA(40),
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \sumXYB[22]_i_12_n_0\
    );
\sumXYB[22]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(17),
      I1 => sumXYA(39),
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \sumXYB[22]_i_13_n_0\
    );
\sumXYB[22]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(16),
      I1 => sumXYA(38),
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \sumXYB[22]_i_14_n_0\
    );
\sumXYB[22]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(21),
      I1 => \stateScore_reg_rep__0_n_0\,
      O => \sumXYB[22]_i_2_n_0\
    );
\sumXYB[22]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(20),
      I1 => \stateScore_reg_rep__0_n_0\,
      O => \sumXYB[22]_i_3_n_0\
    );
\sumXYB[22]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(19),
      I1 => \stateScore_reg_rep__0_n_0\,
      O => \sumXYB[22]_i_4_n_0\
    );
\sumXYB[22]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(18),
      I1 => \stateScore_reg_rep__0_n_0\,
      O => \sumXYB[22]_i_5_n_0\
    );
\sumXYB[22]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(17),
      I1 => \stateScore_reg_rep__0_n_0\,
      O => \sumXYB[22]_i_6_n_0\
    );
\sumXYB[22]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(16),
      I1 => \stateScore_reg_rep__0_n_0\,
      O => \sumXYB[22]_i_7_n_0\
    );
\sumXYB[22]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(21),
      I1 => sumXYA(43),
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \sumXYB[22]_i_8_n_0\
    );
\sumXYB[22]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(21),
      I1 => sumXYA(43),
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \sumXYB[22]_i_9_n_0\
    );
\sumXYB[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(7),
      I1 => sumXYA(29),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_10_n_0\
    );
\sumXYB[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(6),
      I1 => sumXYA(28),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_11_n_0\
    );
\sumXYB[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(5),
      I1 => sumXYA(27),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_12_n_0\
    );
\sumXYB[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(4),
      I1 => sumXYA(26),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_13_n_0\
    );
\sumXYB[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(3),
      I1 => sumXYA(25),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_14_n_0\
    );
\sumXYB[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(2),
      I1 => sumXYA(24),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_15_n_0\
    );
\sumXYB[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(1),
      I1 => sumXYA(23),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_16_n_0\
    );
\sumXYB[7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumXYA(0),
      I1 => sumXYA(22),
      I2 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_17_n_0\
    );
\sumXYB[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(7),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_2_n_0\
    );
\sumXYB[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(6),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_3_n_0\
    );
\sumXYB[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(5),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_4_n_0\
    );
\sumXYB[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(4),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_5_n_0\
    );
\sumXYB[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(3),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_6_n_0\
    );
\sumXYB[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(2),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_7_n_0\
    );
\sumXYB[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(1),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_8_n_0\
    );
\sumXYB[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumXYA(0),
      I1 => stateScore_reg_rep_n_0,
      O => \sumXYB[7]_i_9_n_0\
    );
\sumXYB_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[7]_i_1_n_15\,
      Q => \sumXYB_reg_n_0_[0]\
    );
\sumXYB_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[15]_i_1_n_13\,
      Q => \sumXYB_reg_n_0_[10]\
    );
\sumXYB_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[15]_i_1_n_12\,
      Q => \sumXYB_reg_n_0_[11]\
    );
\sumXYB_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[15]_i_1_n_11\,
      Q => \sumXYB_reg_n_0_[12]\
    );
\sumXYB_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[15]_i_1_n_10\,
      Q => \sumXYB_reg_n_0_[13]\
    );
\sumXYB_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[15]_i_1_n_9\,
      Q => \sumXYB_reg_n_0_[14]\
    );
\sumXYB_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[15]_i_1_n_8\,
      Q => \sumXYB_reg_n_0_[15]\
    );
\sumXYB_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumXYB_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \sumXYB_reg[15]_i_1_n_0\,
      CO(6) => \sumXYB_reg[15]_i_1_n_1\,
      CO(5) => \sumXYB_reg[15]_i_1_n_2\,
      CO(4) => \sumXYB_reg[15]_i_1_n_3\,
      CO(3) => \sumXYB_reg[15]_i_1_n_4\,
      CO(2) => \sumXYB_reg[15]_i_1_n_5\,
      CO(1) => \sumXYB_reg[15]_i_1_n_6\,
      CO(0) => \sumXYB_reg[15]_i_1_n_7\,
      DI(7) => \sumXYB[15]_i_2_n_0\,
      DI(6) => \sumXYB[15]_i_3_n_0\,
      DI(5) => \sumXYB[15]_i_4_n_0\,
      DI(4) => \sumXYB[15]_i_5_n_0\,
      DI(3) => \sumXYB[15]_i_6_n_0\,
      DI(2) => \sumXYB[15]_i_7_n_0\,
      DI(1) => \sumXYB[15]_i_8_n_0\,
      DI(0) => \sumXYB[15]_i_9_n_0\,
      O(7) => \sumXYB_reg[15]_i_1_n_8\,
      O(6) => \sumXYB_reg[15]_i_1_n_9\,
      O(5) => \sumXYB_reg[15]_i_1_n_10\,
      O(4) => \sumXYB_reg[15]_i_1_n_11\,
      O(3) => \sumXYB_reg[15]_i_1_n_12\,
      O(2) => \sumXYB_reg[15]_i_1_n_13\,
      O(1) => \sumXYB_reg[15]_i_1_n_14\,
      O(0) => \sumXYB_reg[15]_i_1_n_15\,
      S(7) => \sumXYB[15]_i_10_n_0\,
      S(6) => \sumXYB[15]_i_11_n_0\,
      S(5) => \sumXYB[15]_i_12_n_0\,
      S(4) => \sumXYB[15]_i_13_n_0\,
      S(3) => \sumXYB[15]_i_14_n_0\,
      S(2) => \sumXYB[15]_i_15_n_0\,
      S(1) => \sumXYB[15]_i_16_n_0\,
      S(0) => \sumXYB[15]_i_17_n_0\
    );
\sumXYB_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[22]_i_1_n_15\,
      Q => \sumXYB_reg_n_0_[16]\
    );
\sumXYB_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[22]_i_1_n_14\,
      Q => \sumXYB_reg_n_0_[17]\
    );
\sumXYB_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[22]_i_1_n_13\,
      Q => \sumXYB_reg_n_0_[18]\
    );
\sumXYB_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[22]_i_1_n_12\,
      Q => \sumXYB_reg_n_0_[19]\
    );
\sumXYB_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[7]_i_1_n_14\,
      Q => \sumXYB_reg_n_0_[1]\
    );
\sumXYB_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[22]_i_1_n_11\,
      Q => \sumXYB_reg_n_0_[20]\
    );
\sumXYB_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[22]_i_1_n_10\,
      Q => \sumXYB_reg_n_0_[21]\
    );
\sumXYB_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[22]_i_1_n_9\,
      Q => \sumXYB_reg_n_0_[22]\
    );
\sumXYB_reg[22]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumXYB_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_sumXYB_reg[22]_i_1_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \sumXYB_reg[22]_i_1_n_2\,
      CO(4) => \sumXYB_reg[22]_i_1_n_3\,
      CO(3) => \sumXYB_reg[22]_i_1_n_4\,
      CO(2) => \sumXYB_reg[22]_i_1_n_5\,
      CO(1) => \sumXYB_reg[22]_i_1_n_6\,
      CO(0) => \sumXYB_reg[22]_i_1_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \sumXYB[22]_i_2_n_0\,
      DI(4) => \sumXYB[22]_i_3_n_0\,
      DI(3) => \sumXYB[22]_i_4_n_0\,
      DI(2) => \sumXYB[22]_i_5_n_0\,
      DI(1) => \sumXYB[22]_i_6_n_0\,
      DI(0) => \sumXYB[22]_i_7_n_0\,
      O(7) => \NLW_sumXYB_reg[22]_i_1_O_UNCONNECTED\(7),
      O(6) => \sumXYB_reg[22]_i_1_n_9\,
      O(5) => \sumXYB_reg[22]_i_1_n_10\,
      O(4) => \sumXYB_reg[22]_i_1_n_11\,
      O(3) => \sumXYB_reg[22]_i_1_n_12\,
      O(2) => \sumXYB_reg[22]_i_1_n_13\,
      O(1) => \sumXYB_reg[22]_i_1_n_14\,
      O(0) => \sumXYB_reg[22]_i_1_n_15\,
      S(7) => '0',
      S(6) => \sumXYB[22]_i_8_n_0\,
      S(5) => \sumXYB[22]_i_9_n_0\,
      S(4) => \sumXYB[22]_i_10_n_0\,
      S(3) => \sumXYB[22]_i_11_n_0\,
      S(2) => \sumXYB[22]_i_12_n_0\,
      S(1) => \sumXYB[22]_i_13_n_0\,
      S(0) => \sumXYB[22]_i_14_n_0\
    );
\sumXYB_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[7]_i_1_n_13\,
      Q => \sumXYB_reg_n_0_[2]\
    );
\sumXYB_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[7]_i_1_n_12\,
      Q => \sumXYB_reg_n_0_[3]\
    );
\sumXYB_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[7]_i_1_n_11\,
      Q => \sumXYB_reg_n_0_[4]\
    );
\sumXYB_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[7]_i_1_n_10\,
      Q => \sumXYB_reg_n_0_[5]\
    );
\sumXYB_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[7]_i_1_n_9\,
      Q => \sumXYB_reg_n_0_[6]\
    );
\sumXYB_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[7]_i_1_n_8\,
      Q => \sumXYB_reg_n_0_[7]\
    );
\sumXYB_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \sumXYB_reg[7]_i_1_n_0\,
      CO(6) => \sumXYB_reg[7]_i_1_n_1\,
      CO(5) => \sumXYB_reg[7]_i_1_n_2\,
      CO(4) => \sumXYB_reg[7]_i_1_n_3\,
      CO(3) => \sumXYB_reg[7]_i_1_n_4\,
      CO(2) => \sumXYB_reg[7]_i_1_n_5\,
      CO(1) => \sumXYB_reg[7]_i_1_n_6\,
      CO(0) => \sumXYB_reg[7]_i_1_n_7\,
      DI(7) => \sumXYB[7]_i_2_n_0\,
      DI(6) => \sumXYB[7]_i_3_n_0\,
      DI(5) => \sumXYB[7]_i_4_n_0\,
      DI(4) => \sumXYB[7]_i_5_n_0\,
      DI(3) => \sumXYB[7]_i_6_n_0\,
      DI(2) => \sumXYB[7]_i_7_n_0\,
      DI(1) => \sumXYB[7]_i_8_n_0\,
      DI(0) => \sumXYB[7]_i_9_n_0\,
      O(7) => \sumXYB_reg[7]_i_1_n_8\,
      O(6) => \sumXYB_reg[7]_i_1_n_9\,
      O(5) => \sumXYB_reg[7]_i_1_n_10\,
      O(4) => \sumXYB_reg[7]_i_1_n_11\,
      O(3) => \sumXYB_reg[7]_i_1_n_12\,
      O(2) => \sumXYB_reg[7]_i_1_n_13\,
      O(1) => \sumXYB_reg[7]_i_1_n_14\,
      O(0) => \sumXYB_reg[7]_i_1_n_15\,
      S(7) => \sumXYB[7]_i_10_n_0\,
      S(6) => \sumXYB[7]_i_11_n_0\,
      S(5) => \sumXYB[7]_i_12_n_0\,
      S(4) => \sumXYB[7]_i_13_n_0\,
      S(3) => \sumXYB[7]_i_14_n_0\,
      S(2) => \sumXYB[7]_i_15_n_0\,
      S(1) => \sumXYB[7]_i_16_n_0\,
      S(0) => \sumXYB[7]_i_17_n_0\
    );
\sumXYB_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[15]_i_1_n_15\,
      Q => \sumXYB_reg_n_0_[8]\
    );
\sumXYB_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXYB_reg[15]_i_1_n_14\,
      Q => \sumXYB_reg_n_0_[9]\
    );
\sumXY[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(15),
      I1 => \sumXYB_reg_n_0_[15]\,
      I2 => stateScore,
      O => \sumXY[15]_i_10_n_0\
    );
\sumXY[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(14),
      I1 => \sumXYB_reg_n_0_[14]\,
      I2 => stateScore,
      O => \sumXY[15]_i_11_n_0\
    );
\sumXY[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(13),
      I1 => \sumXYB_reg_n_0_[13]\,
      I2 => stateScore,
      O => \sumXY[15]_i_12_n_0\
    );
\sumXY[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(12),
      I1 => \sumXYB_reg_n_0_[12]\,
      I2 => stateScore,
      O => \sumXY[15]_i_13_n_0\
    );
\sumXY[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(11),
      I1 => \sumXYB_reg_n_0_[11]\,
      I2 => stateScore,
      O => \sumXY[15]_i_14_n_0\
    );
\sumXY[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(10),
      I1 => \sumXYB_reg_n_0_[10]\,
      I2 => stateScore,
      O => \sumXY[15]_i_15_n_0\
    );
\sumXY[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(9),
      I1 => \sumXYB_reg_n_0_[9]\,
      I2 => stateScore,
      O => \sumXY[15]_i_16_n_0\
    );
\sumXY[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(8),
      I1 => \sumXYB_reg_n_0_[8]\,
      I2 => stateScore,
      O => \sumXY[15]_i_17_n_0\
    );
\sumXY[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(15),
      I1 => stateScore,
      O => \sumXY[15]_i_2_n_0\
    );
\sumXY[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(14),
      I1 => stateScore,
      O => \sumXY[15]_i_3_n_0\
    );
\sumXY[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(13),
      I1 => stateScore,
      O => \sumXY[15]_i_4_n_0\
    );
\sumXY[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(12),
      I1 => stateScore,
      O => \sumXY[15]_i_5_n_0\
    );
\sumXY[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(11),
      I1 => stateScore,
      O => \sumXY[15]_i_6_n_0\
    );
\sumXY[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(10),
      I1 => stateScore,
      O => \sumXY[15]_i_7_n_0\
    );
\sumXY[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(9),
      I1 => stateScore,
      O => \sumXY[15]_i_8_n_0\
    );
\sumXY[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(8),
      I1 => stateScore,
      O => \sumXY[15]_i_9_n_0\
    );
\sumXY[22]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(20),
      I1 => \sumXYB_reg_n_0_[20]\,
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \sumXY[22]_i_10_n_0\
    );
\sumXY[22]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(19),
      I1 => \sumXYB_reg_n_0_[19]\,
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \sumXY[22]_i_11_n_0\
    );
\sumXY[22]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(18),
      I1 => \sumXYB_reg_n_0_[18]\,
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \sumXY[22]_i_12_n_0\
    );
\sumXY[22]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(17),
      I1 => \sumXYB_reg_n_0_[17]\,
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \sumXY[22]_i_13_n_0\
    );
\sumXY[22]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(16),
      I1 => \sumXYB_reg_n_0_[16]\,
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \sumXY[22]_i_14_n_0\
    );
\sumXY[22]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(20),
      I1 => \stateScore_reg_rep__0_n_0\,
      O => \sumXY[22]_i_2_n_0\
    );
\sumXY[22]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(20),
      I1 => \stateScore_reg_rep__0_n_0\,
      O => \sumXY[22]_i_3_n_0\
    );
\sumXY[22]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(19),
      I1 => \stateScore_reg_rep__0_n_0\,
      O => \sumXY[22]_i_4_n_0\
    );
\sumXY[22]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(18),
      I1 => \stateScore_reg_rep__0_n_0\,
      O => \sumXY[22]_i_5_n_0\
    );
\sumXY[22]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(17),
      I1 => \stateScore_reg_rep__0_n_0\,
      O => \sumXY[22]_i_6_n_0\
    );
\sumXY[22]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(16),
      I1 => \stateScore_reg_rep__0_n_0\,
      O => \sumXY[22]_i_7_n_0\
    );
\sumXY[22]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(20),
      I1 => \sumXYB_reg_n_0_[22]\,
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \sumXY[22]_i_8_n_0\
    );
\sumXY[22]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(20),
      I1 => \sumXYB_reg_n_0_[21]\,
      I2 => \stateScore_reg_rep__0_n_0\,
      O => \sumXY[22]_i_9_n_0\
    );
\sumXY[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(7),
      I1 => \sumXYB_reg_n_0_[7]\,
      I2 => stateScore,
      O => \sumXY[7]_i_10_n_0\
    );
\sumXY[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(6),
      I1 => \sumXYB_reg_n_0_[6]\,
      I2 => stateScore,
      O => \sumXY[7]_i_11_n_0\
    );
\sumXY[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(5),
      I1 => \sumXYB_reg_n_0_[5]\,
      I2 => stateScore,
      O => \sumXY[7]_i_12_n_0\
    );
\sumXY[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(4),
      I1 => \sumXYB_reg_n_0_[4]\,
      I2 => stateScore,
      O => \sumXY[7]_i_13_n_0\
    );
\sumXY[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(3),
      I1 => \sumXYB_reg_n_0_[3]\,
      I2 => stateScore,
      O => \sumXY[7]_i_14_n_0\
    );
\sumXY[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(2),
      I1 => \sumXYB_reg_n_0_[2]\,
      I2 => stateScore,
      O => \sumXY[7]_i_15_n_0\
    );
\sumXY[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(1),
      I1 => \sumXYB_reg_n_0_[1]\,
      I2 => stateScore,
      O => \sumXY[7]_i_16_n_0\
    );
\sumXY[7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumXY4p2(0),
      I1 => \sumXYB_reg_n_0_[0]\,
      I2 => stateScore,
      O => \sumXY[7]_i_17_n_0\
    );
\sumXY[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(7),
      I1 => stateScore,
      O => \sumXY[7]_i_2_n_0\
    );
\sumXY[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(6),
      I1 => stateScore,
      O => \sumXY[7]_i_3_n_0\
    );
\sumXY[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(5),
      I1 => stateScore,
      O => \sumXY[7]_i_4_n_0\
    );
\sumXY[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(4),
      I1 => stateScore,
      O => \sumXY[7]_i_5_n_0\
    );
\sumXY[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(3),
      I1 => stateScore,
      O => \sumXY[7]_i_6_n_0\
    );
\sumXY[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(2),
      I1 => stateScore,
      O => \sumXY[7]_i_7_n_0\
    );
\sumXY[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(1),
      I1 => stateScore,
      O => \sumXY[7]_i_8_n_0\
    );
\sumXY[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumXY4p2(0),
      I1 => stateScore,
      O => \sumXY[7]_i_9_n_0\
    );
\sumXY_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[7]_i_1_n_15\,
      Q => sumXY(0)
    );
\sumXY_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[15]_i_1_n_13\,
      Q => sumXY(10)
    );
\sumXY_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[15]_i_1_n_12\,
      Q => sumXY(11)
    );
\sumXY_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[15]_i_1_n_11\,
      Q => sumXY(12)
    );
\sumXY_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[15]_i_1_n_10\,
      Q => sumXY(13)
    );
\sumXY_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[15]_i_1_n_9\,
      Q => sumXY(14)
    );
\sumXY_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[15]_i_1_n_8\,
      Q => sumXY(15)
    );
\sumXY_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumXY_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \sumXY_reg[15]_i_1_n_0\,
      CO(6) => \sumXY_reg[15]_i_1_n_1\,
      CO(5) => \sumXY_reg[15]_i_1_n_2\,
      CO(4) => \sumXY_reg[15]_i_1_n_3\,
      CO(3) => \sumXY_reg[15]_i_1_n_4\,
      CO(2) => \sumXY_reg[15]_i_1_n_5\,
      CO(1) => \sumXY_reg[15]_i_1_n_6\,
      CO(0) => \sumXY_reg[15]_i_1_n_7\,
      DI(7) => \sumXY[15]_i_2_n_0\,
      DI(6) => \sumXY[15]_i_3_n_0\,
      DI(5) => \sumXY[15]_i_4_n_0\,
      DI(4) => \sumXY[15]_i_5_n_0\,
      DI(3) => \sumXY[15]_i_6_n_0\,
      DI(2) => \sumXY[15]_i_7_n_0\,
      DI(1) => \sumXY[15]_i_8_n_0\,
      DI(0) => \sumXY[15]_i_9_n_0\,
      O(7) => \sumXY_reg[15]_i_1_n_8\,
      O(6) => \sumXY_reg[15]_i_1_n_9\,
      O(5) => \sumXY_reg[15]_i_1_n_10\,
      O(4) => \sumXY_reg[15]_i_1_n_11\,
      O(3) => \sumXY_reg[15]_i_1_n_12\,
      O(2) => \sumXY_reg[15]_i_1_n_13\,
      O(1) => \sumXY_reg[15]_i_1_n_14\,
      O(0) => \sumXY_reg[15]_i_1_n_15\,
      S(7) => \sumXY[15]_i_10_n_0\,
      S(6) => \sumXY[15]_i_11_n_0\,
      S(5) => \sumXY[15]_i_12_n_0\,
      S(4) => \sumXY[15]_i_13_n_0\,
      S(3) => \sumXY[15]_i_14_n_0\,
      S(2) => \sumXY[15]_i_15_n_0\,
      S(1) => \sumXY[15]_i_16_n_0\,
      S(0) => \sumXY[15]_i_17_n_0\
    );
\sumXY_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[22]_i_1_n_15\,
      Q => sumXY(16)
    );
\sumXY_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[22]_i_1_n_14\,
      Q => sumXY(17)
    );
\sumXY_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[22]_i_1_n_13\,
      Q => sumXY(18)
    );
\sumXY_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[22]_i_1_n_12\,
      Q => sumXY(19)
    );
\sumXY_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[7]_i_1_n_14\,
      Q => sumXY(1)
    );
\sumXY_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[22]_i_1_n_11\,
      Q => sumXY(20)
    );
\sumXY_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[22]_i_1_n_10\,
      Q => sumXY(21)
    );
\sumXY_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[22]_i_1_n_9\,
      Q => sumXY(22)
    );
\sumXY_reg[22]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumXY_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_sumXY_reg[22]_i_1_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \sumXY_reg[22]_i_1_n_2\,
      CO(4) => \sumXY_reg[22]_i_1_n_3\,
      CO(3) => \sumXY_reg[22]_i_1_n_4\,
      CO(2) => \sumXY_reg[22]_i_1_n_5\,
      CO(1) => \sumXY_reg[22]_i_1_n_6\,
      CO(0) => \sumXY_reg[22]_i_1_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \sumXY[22]_i_2_n_0\,
      DI(4) => \sumXY[22]_i_3_n_0\,
      DI(3) => \sumXY[22]_i_4_n_0\,
      DI(2) => \sumXY[22]_i_5_n_0\,
      DI(1) => \sumXY[22]_i_6_n_0\,
      DI(0) => \sumXY[22]_i_7_n_0\,
      O(7) => \NLW_sumXY_reg[22]_i_1_O_UNCONNECTED\(7),
      O(6) => \sumXY_reg[22]_i_1_n_9\,
      O(5) => \sumXY_reg[22]_i_1_n_10\,
      O(4) => \sumXY_reg[22]_i_1_n_11\,
      O(3) => \sumXY_reg[22]_i_1_n_12\,
      O(2) => \sumXY_reg[22]_i_1_n_13\,
      O(1) => \sumXY_reg[22]_i_1_n_14\,
      O(0) => \sumXY_reg[22]_i_1_n_15\,
      S(7) => '0',
      S(6) => \sumXY[22]_i_8_n_0\,
      S(5) => \sumXY[22]_i_9_n_0\,
      S(4) => \sumXY[22]_i_10_n_0\,
      S(3) => \sumXY[22]_i_11_n_0\,
      S(2) => \sumXY[22]_i_12_n_0\,
      S(1) => \sumXY[22]_i_13_n_0\,
      S(0) => \sumXY[22]_i_14_n_0\
    );
\sumXY_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[7]_i_1_n_13\,
      Q => sumXY(2)
    );
\sumXY_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[7]_i_1_n_12\,
      Q => sumXY(3)
    );
\sumXY_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[7]_i_1_n_11\,
      Q => sumXY(4)
    );
\sumXY_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[7]_i_1_n_10\,
      Q => sumXY(5)
    );
\sumXY_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[7]_i_1_n_9\,
      Q => sumXY(6)
    );
\sumXY_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[7]_i_1_n_8\,
      Q => sumXY(7)
    );
\sumXY_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \sumXY_reg[7]_i_1_n_0\,
      CO(6) => \sumXY_reg[7]_i_1_n_1\,
      CO(5) => \sumXY_reg[7]_i_1_n_2\,
      CO(4) => \sumXY_reg[7]_i_1_n_3\,
      CO(3) => \sumXY_reg[7]_i_1_n_4\,
      CO(2) => \sumXY_reg[7]_i_1_n_5\,
      CO(1) => \sumXY_reg[7]_i_1_n_6\,
      CO(0) => \sumXY_reg[7]_i_1_n_7\,
      DI(7) => \sumXY[7]_i_2_n_0\,
      DI(6) => \sumXY[7]_i_3_n_0\,
      DI(5) => \sumXY[7]_i_4_n_0\,
      DI(4) => \sumXY[7]_i_5_n_0\,
      DI(3) => \sumXY[7]_i_6_n_0\,
      DI(2) => \sumXY[7]_i_7_n_0\,
      DI(1) => \sumXY[7]_i_8_n_0\,
      DI(0) => \sumXY[7]_i_9_n_0\,
      O(7) => \sumXY_reg[7]_i_1_n_8\,
      O(6) => \sumXY_reg[7]_i_1_n_9\,
      O(5) => \sumXY_reg[7]_i_1_n_10\,
      O(4) => \sumXY_reg[7]_i_1_n_11\,
      O(3) => \sumXY_reg[7]_i_1_n_12\,
      O(2) => \sumXY_reg[7]_i_1_n_13\,
      O(1) => \sumXY_reg[7]_i_1_n_14\,
      O(0) => \sumXY_reg[7]_i_1_n_15\,
      S(7) => \sumXY[7]_i_10_n_0\,
      S(6) => \sumXY[7]_i_11_n_0\,
      S(5) => \sumXY[7]_i_12_n_0\,
      S(4) => \sumXY[7]_i_13_n_0\,
      S(3) => \sumXY[7]_i_14_n_0\,
      S(2) => \sumXY[7]_i_15_n_0\,
      S(1) => \sumXY[7]_i_16_n_0\,
      S(0) => \sumXY[7]_i_17_n_0\
    );
\sumXY_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[15]_i_1_n_15\,
      Q => sumXY(8)
    );
\sumXY_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumXY_reg[15]_i_1_n_14\,
      Q => sumXY(9)
    );
\sumX[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(15),
      I1 => \sumXB_reg_n_0_[15]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_10_n_0\
    );
\sumX[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(14),
      I1 => \sumXB_reg_n_0_[14]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_11_n_0\
    );
\sumX[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(13),
      I1 => \sumXB_reg_n_0_[13]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_12_n_0\
    );
\sumX[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(12),
      I1 => \sumXB_reg_n_0_[12]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_13_n_0\
    );
\sumX[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(11),
      I1 => \sumXB_reg_n_0_[11]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_14_n_0\
    );
\sumX[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(10),
      I1 => \sumXB_reg_n_0_[10]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_15_n_0\
    );
\sumX[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(9),
      I1 => \sumXB_reg_n_0_[9]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_16_n_0\
    );
\sumX[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(8),
      I1 => \sumXB_reg_n_0_[8]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_17_n_0\
    );
\sumX[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(15),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_2_n_0\
    );
\sumX[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(14),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_3_n_0\
    );
\sumX[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(13),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_4_n_0\
    );
\sumX[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(12),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_5_n_0\
    );
\sumX[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(11),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_6_n_0\
    );
\sumX[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(10),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_7_n_0\
    );
\sumX[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(9),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_8_n_0\
    );
\sumX[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(8),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[15]_i_9_n_0\
    );
\sumX[22]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(20),
      I1 => \sumXB_reg_n_0_[20]\,
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumX[22]_i_10_n_0\
    );
\sumX[22]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(19),
      I1 => \sumXB_reg_n_0_[19]\,
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumX[22]_i_11_n_0\
    );
\sumX[22]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(18),
      I1 => \sumXB_reg_n_0_[18]\,
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumX[22]_i_12_n_0\
    );
\sumX[22]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(17),
      I1 => \sumXB_reg_n_0_[17]\,
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumX[22]_i_13_n_0\
    );
\sumX[22]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(16),
      I1 => \sumXB_reg_n_0_[16]\,
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumX[22]_i_14_n_0\
    );
\sumX[22]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(20),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumX[22]_i_2_n_0\
    );
\sumX[22]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(20),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumX[22]_i_3_n_0\
    );
\sumX[22]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(19),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumX[22]_i_4_n_0\
    );
\sumX[22]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(18),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumX[22]_i_5_n_0\
    );
\sumX[22]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(17),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumX[22]_i_6_n_0\
    );
\sumX[22]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(16),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumX[22]_i_7_n_0\
    );
\sumX[22]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(20),
      I1 => \sumXB_reg_n_0_[22]\,
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumX[22]_i_8_n_0\
    );
\sumX[22]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(20),
      I1 => \sumXB_reg_n_0_[21]\,
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumX[22]_i_9_n_0\
    );
\sumX[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(7),
      I1 => \sumXB_reg_n_0_[7]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_10_n_0\
    );
\sumX[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(6),
      I1 => \sumXB_reg_n_0_[6]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_11_n_0\
    );
\sumX[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(5),
      I1 => \sumXB_reg_n_0_[5]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_12_n_0\
    );
\sumX[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(4),
      I1 => \sumXB_reg_n_0_[4]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_13_n_0\
    );
\sumX[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(3),
      I1 => \sumXB_reg_n_0_[3]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_14_n_0\
    );
\sumX[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(2),
      I1 => \sumXB_reg_n_0_[2]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_15_n_0\
    );
\sumX[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(1),
      I1 => \sumXB_reg_n_0_[1]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_16_n_0\
    );
\sumX[7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumX4p2(0),
      I1 => \sumXB_reg_n_0_[0]\,
      I2 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_17_n_0\
    );
\sumX[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(7),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_2_n_0\
    );
\sumX[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(6),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_3_n_0\
    );
\sumX[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(5),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_4_n_0\
    );
\sumX[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(4),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_5_n_0\
    );
\sumX[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(3),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_6_n_0\
    );
\sumX[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(2),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_7_n_0\
    );
\sumX[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(1),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_8_n_0\
    );
\sumX[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumX4p2(0),
      I1 => \stateScore_reg_rep__9_n_0\,
      O => \sumX[7]_i_9_n_0\
    );
\sumX_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[7]_i_1_n_15\,
      Q => sumX(0)
    );
\sumX_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[15]_i_1_n_13\,
      Q => sumX(10)
    );
\sumX_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[15]_i_1_n_12\,
      Q => sumX(11)
    );
\sumX_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[15]_i_1_n_11\,
      Q => sumX(12)
    );
\sumX_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[15]_i_1_n_10\,
      Q => sumX(13)
    );
\sumX_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[15]_i_1_n_9\,
      Q => sumX(14)
    );
\sumX_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[15]_i_1_n_8\,
      Q => sumX(15)
    );
\sumX_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumX_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \sumX_reg[15]_i_1_n_0\,
      CO(6) => \sumX_reg[15]_i_1_n_1\,
      CO(5) => \sumX_reg[15]_i_1_n_2\,
      CO(4) => \sumX_reg[15]_i_1_n_3\,
      CO(3) => \sumX_reg[15]_i_1_n_4\,
      CO(2) => \sumX_reg[15]_i_1_n_5\,
      CO(1) => \sumX_reg[15]_i_1_n_6\,
      CO(0) => \sumX_reg[15]_i_1_n_7\,
      DI(7) => \sumX[15]_i_2_n_0\,
      DI(6) => \sumX[15]_i_3_n_0\,
      DI(5) => \sumX[15]_i_4_n_0\,
      DI(4) => \sumX[15]_i_5_n_0\,
      DI(3) => \sumX[15]_i_6_n_0\,
      DI(2) => \sumX[15]_i_7_n_0\,
      DI(1) => \sumX[15]_i_8_n_0\,
      DI(0) => \sumX[15]_i_9_n_0\,
      O(7) => \sumX_reg[15]_i_1_n_8\,
      O(6) => \sumX_reg[15]_i_1_n_9\,
      O(5) => \sumX_reg[15]_i_1_n_10\,
      O(4) => \sumX_reg[15]_i_1_n_11\,
      O(3) => \sumX_reg[15]_i_1_n_12\,
      O(2) => \sumX_reg[15]_i_1_n_13\,
      O(1) => \sumX_reg[15]_i_1_n_14\,
      O(0) => \sumX_reg[15]_i_1_n_15\,
      S(7) => \sumX[15]_i_10_n_0\,
      S(6) => \sumX[15]_i_11_n_0\,
      S(5) => \sumX[15]_i_12_n_0\,
      S(4) => \sumX[15]_i_13_n_0\,
      S(3) => \sumX[15]_i_14_n_0\,
      S(2) => \sumX[15]_i_15_n_0\,
      S(1) => \sumX[15]_i_16_n_0\,
      S(0) => \sumX[15]_i_17_n_0\
    );
\sumX_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[22]_i_1_n_15\,
      Q => sumX(16)
    );
\sumX_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[22]_i_1_n_14\,
      Q => sumX(17)
    );
\sumX_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[22]_i_1_n_13\,
      Q => sumX(18)
    );
\sumX_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[22]_i_1_n_12\,
      Q => sumX(19)
    );
\sumX_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[7]_i_1_n_14\,
      Q => sumX(1)
    );
\sumX_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[22]_i_1_n_11\,
      Q => sumX(20)
    );
\sumX_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[22]_i_1_n_10\,
      Q => sumX(21)
    );
\sumX_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[22]_i_1_n_9\,
      Q => sumX(22)
    );
\sumX_reg[22]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumX_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_sumX_reg[22]_i_1_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \sumX_reg[22]_i_1_n_2\,
      CO(4) => \sumX_reg[22]_i_1_n_3\,
      CO(3) => \sumX_reg[22]_i_1_n_4\,
      CO(2) => \sumX_reg[22]_i_1_n_5\,
      CO(1) => \sumX_reg[22]_i_1_n_6\,
      CO(0) => \sumX_reg[22]_i_1_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \sumX[22]_i_2_n_0\,
      DI(4) => \sumX[22]_i_3_n_0\,
      DI(3) => \sumX[22]_i_4_n_0\,
      DI(2) => \sumX[22]_i_5_n_0\,
      DI(1) => \sumX[22]_i_6_n_0\,
      DI(0) => \sumX[22]_i_7_n_0\,
      O(7) => \NLW_sumX_reg[22]_i_1_O_UNCONNECTED\(7),
      O(6) => \sumX_reg[22]_i_1_n_9\,
      O(5) => \sumX_reg[22]_i_1_n_10\,
      O(4) => \sumX_reg[22]_i_1_n_11\,
      O(3) => \sumX_reg[22]_i_1_n_12\,
      O(2) => \sumX_reg[22]_i_1_n_13\,
      O(1) => \sumX_reg[22]_i_1_n_14\,
      O(0) => \sumX_reg[22]_i_1_n_15\,
      S(7) => '0',
      S(6) => \sumX[22]_i_8_n_0\,
      S(5) => \sumX[22]_i_9_n_0\,
      S(4) => \sumX[22]_i_10_n_0\,
      S(3) => \sumX[22]_i_11_n_0\,
      S(2) => \sumX[22]_i_12_n_0\,
      S(1) => \sumX[22]_i_13_n_0\,
      S(0) => \sumX[22]_i_14_n_0\
    );
\sumX_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[7]_i_1_n_13\,
      Q => sumX(2)
    );
\sumX_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[7]_i_1_n_12\,
      Q => sumX(3)
    );
\sumX_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[7]_i_1_n_11\,
      Q => sumX(4)
    );
\sumX_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[7]_i_1_n_10\,
      Q => sumX(5)
    );
\sumX_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[7]_i_1_n_9\,
      Q => sumX(6)
    );
\sumX_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[7]_i_1_n_8\,
      Q => sumX(7)
    );
\sumX_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \sumX_reg[7]_i_1_n_0\,
      CO(6) => \sumX_reg[7]_i_1_n_1\,
      CO(5) => \sumX_reg[7]_i_1_n_2\,
      CO(4) => \sumX_reg[7]_i_1_n_3\,
      CO(3) => \sumX_reg[7]_i_1_n_4\,
      CO(2) => \sumX_reg[7]_i_1_n_5\,
      CO(1) => \sumX_reg[7]_i_1_n_6\,
      CO(0) => \sumX_reg[7]_i_1_n_7\,
      DI(7) => \sumX[7]_i_2_n_0\,
      DI(6) => \sumX[7]_i_3_n_0\,
      DI(5) => \sumX[7]_i_4_n_0\,
      DI(4) => \sumX[7]_i_5_n_0\,
      DI(3) => \sumX[7]_i_6_n_0\,
      DI(2) => \sumX[7]_i_7_n_0\,
      DI(1) => \sumX[7]_i_8_n_0\,
      DI(0) => \sumX[7]_i_9_n_0\,
      O(7) => \sumX_reg[7]_i_1_n_8\,
      O(6) => \sumX_reg[7]_i_1_n_9\,
      O(5) => \sumX_reg[7]_i_1_n_10\,
      O(4) => \sumX_reg[7]_i_1_n_11\,
      O(3) => \sumX_reg[7]_i_1_n_12\,
      O(2) => \sumX_reg[7]_i_1_n_13\,
      O(1) => \sumX_reg[7]_i_1_n_14\,
      O(0) => \sumX_reg[7]_i_1_n_15\,
      S(7) => \sumX[7]_i_10_n_0\,
      S(6) => \sumX[7]_i_11_n_0\,
      S(5) => \sumX[7]_i_12_n_0\,
      S(4) => \sumX[7]_i_13_n_0\,
      S(3) => \sumX[7]_i_14_n_0\,
      S(2) => \sumX[7]_i_15_n_0\,
      S(1) => \sumX[7]_i_16_n_0\,
      S(0) => \sumX[7]_i_17_n_0\
    );
\sumX_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[15]_i_1_n_15\,
      Q => sumX(8)
    );
\sumX_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumX_reg[15]_i_1_n_14\,
      Q => sumX(9)
    );
\sumYA[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(0),
      O => \sumYA[0]_i_1_n_0\
    );
\sumYA[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(10),
      O => \sumYA[10]_i_1_n_0\
    );
\sumYA[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(11),
      O => \sumYA[11]_i_1_n_0\
    );
\sumYA[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(12),
      O => \sumYA[12]_i_1_n_0\
    );
\sumYA[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(13),
      O => \sumYA[13]_i_1_n_0\
    );
\sumYA[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(14),
      O => \sumYA[14]_i_1_n_0\
    );
\sumYA[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(15),
      O => \sumYA[15]_i_1_n_0\
    );
\sumYA[15]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[29]\,
      I1 => \colsumY_reg_n_0_[8]\,
      O => \sumYA[15]_i_10_n_0\
    );
\sumYA[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[36]\,
      I1 => \colsumY_reg_n_0_[15]\,
      O => \sumYA[15]_i_3_n_0\
    );
\sumYA[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[35]\,
      I1 => \colsumY_reg_n_0_[14]\,
      O => \sumYA[15]_i_4_n_0\
    );
\sumYA[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[34]\,
      I1 => \colsumY_reg_n_0_[13]\,
      O => \sumYA[15]_i_5_n_0\
    );
\sumYA[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[33]\,
      I1 => \colsumY_reg_n_0_[12]\,
      O => \sumYA[15]_i_6_n_0\
    );
\sumYA[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[32]\,
      I1 => \colsumY_reg_n_0_[11]\,
      O => \sumYA[15]_i_7_n_0\
    );
\sumYA[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[31]\,
      I1 => \colsumY_reg_n_0_[10]\,
      O => \sumYA[15]_i_8_n_0\
    );
\sumYA[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[30]\,
      I1 => \colsumY_reg_n_0_[9]\,
      O => \sumYA[15]_i_9_n_0\
    );
\sumYA[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumYA0(16),
      O => \sumYA[16]_i_1_n_0\
    );
\sumYA[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumYA0(17),
      O => \sumYA[17]_i_1_n_0\
    );
\sumYA[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumYA0(18),
      O => \sumYA[18]_i_1_n_0\
    );
\sumYA[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumYA0(19),
      O => \sumYA[19]_i_1_n_0\
    );
\sumYA[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(1),
      O => \sumYA[1]_i_1_n_0\
    );
\sumYA[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumYA0(20),
      O => \sumYA[20]_i_1_n_0\
    );
\sumYA[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => \sumYA_reg[21]_i_2_n_2\,
      O => \sumYA[21]_i_1_n_0\
    );
\sumYA[21]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \colsumY_reg_n_0_[41]\,
      O => \sumYA[21]_i_3_n_0\
    );
\sumYA[21]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[41]\,
      I1 => \colsumY_reg_n_0_[20]\,
      O => \sumYA[21]_i_4_n_0\
    );
\sumYA[21]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[40]\,
      I1 => \colsumY_reg_n_0_[19]\,
      O => \sumYA[21]_i_5_n_0\
    );
\sumYA[21]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[39]\,
      I1 => \colsumY_reg_n_0_[18]\,
      O => \sumYA[21]_i_6_n_0\
    );
\sumYA[21]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[38]\,
      I1 => \colsumY_reg_n_0_[17]\,
      O => \sumYA[21]_i_7_n_0\
    );
\sumYA[21]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[37]\,
      I1 => \colsumY_reg_n_0_[16]\,
      O => \sumYA[21]_i_8_n_0\
    );
\sumYA[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(0),
      O => \sumYA[22]_i_1_n_0\
    );
\sumYA[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(1),
      O => \sumYA[23]_i_1_n_0\
    );
\sumYA[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(2),
      O => \sumYA[24]_i_1_n_0\
    );
\sumYA[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(3),
      O => \sumYA[25]_i_1_n_0\
    );
\sumYA[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(4),
      O => \sumYA[26]_i_1_n_0\
    );
\sumYA[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(5),
      O => \sumYA[27]_i_1_n_0\
    );
\sumYA[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(6),
      O => \sumYA[28]_i_1_n_0\
    );
\sumYA[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(7),
      O => \sumYA[29]_i_1_n_0\
    );
\sumYA[29]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[63]\,
      I1 => \colsumY_reg_n_0_[42]\,
      O => \sumYA[29]_i_10_n_0\
    );
\sumYA[29]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[70]\,
      I1 => \colsumY_reg_n_0_[49]\,
      O => \sumYA[29]_i_3_n_0\
    );
\sumYA[29]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[69]\,
      I1 => \colsumY_reg_n_0_[48]\,
      O => \sumYA[29]_i_4_n_0\
    );
\sumYA[29]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[68]\,
      I1 => \colsumY_reg_n_0_[47]\,
      O => \sumYA[29]_i_5_n_0\
    );
\sumYA[29]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[67]\,
      I1 => \colsumY_reg_n_0_[46]\,
      O => \sumYA[29]_i_6_n_0\
    );
\sumYA[29]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[66]\,
      I1 => \colsumY_reg_n_0_[45]\,
      O => \sumYA[29]_i_7_n_0\
    );
\sumYA[29]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[65]\,
      I1 => \colsumY_reg_n_0_[44]\,
      O => \sumYA[29]_i_8_n_0\
    );
\sumYA[29]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[64]\,
      I1 => \colsumY_reg_n_0_[43]\,
      O => \sumYA[29]_i_9_n_0\
    );
\sumYA[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(2),
      O => \sumYA[2]_i_1_n_0\
    );
\sumYA[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(8),
      O => \sumYA[30]_i_1_n_0\
    );
\sumYA[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(9),
      O => \sumYA[31]_i_1_n_0\
    );
\sumYA[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(10),
      O => \sumYA[32]_i_1_n_0\
    );
\sumYA[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(11),
      O => \sumYA[33]_i_1_n_0\
    );
\sumYA[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(12),
      O => \sumYA[34]_i_1_n_0\
    );
\sumYA[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(13),
      O => \sumYA[35]_i_1_n_0\
    );
\sumYA[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(14),
      O => \sumYA[36]_i_1_n_0\
    );
\sumYA[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA00_in(15),
      O => \sumYA[37]_i_1_n_0\
    );
\sumYA[37]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[71]\,
      I1 => \colsumY_reg_n_0_[50]\,
      O => \sumYA[37]_i_10_n_0\
    );
\sumYA[37]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[78]\,
      I1 => \colsumY_reg_n_0_[57]\,
      O => \sumYA[37]_i_3_n_0\
    );
\sumYA[37]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[77]\,
      I1 => \colsumY_reg_n_0_[56]\,
      O => \sumYA[37]_i_4_n_0\
    );
\sumYA[37]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[76]\,
      I1 => \colsumY_reg_n_0_[55]\,
      O => \sumYA[37]_i_5_n_0\
    );
\sumYA[37]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[75]\,
      I1 => \colsumY_reg_n_0_[54]\,
      O => \sumYA[37]_i_6_n_0\
    );
\sumYA[37]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[74]\,
      I1 => \colsumY_reg_n_0_[53]\,
      O => \sumYA[37]_i_7_n_0\
    );
\sumYA[37]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[73]\,
      I1 => \colsumY_reg_n_0_[52]\,
      O => \sumYA[37]_i_8_n_0\
    );
\sumYA[37]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[72]\,
      I1 => \colsumY_reg_n_0_[51]\,
      O => \sumYA[37]_i_9_n_0\
    );
\sumYA[38]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumYA00_in(16),
      O => \sumYA[38]_i_1_n_0\
    );
\sumYA[39]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumYA00_in(17),
      O => \sumYA[39]_i_1_n_0\
    );
\sumYA[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(3),
      O => \sumYA[3]_i_1_n_0\
    );
\sumYA[40]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumYA00_in(18),
      O => \sumYA[40]_i_1_n_0\
    );
\sumYA[41]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumYA00_in(19),
      O => \sumYA[41]_i_1_n_0\
    );
\sumYA[42]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => sumYA00_in(20),
      O => \sumYA[42]_i_1_n_0\
    );
\sumYA[43]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateScore_reg_rep__11_n_0\,
      I1 => \sumYA_reg[43]_i_2_n_2\,
      O => \sumYA[43]_i_1_n_0\
    );
\sumYA[43]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \colsumY_reg_n_0_[83]\,
      O => \sumYA[43]_i_3_n_0\
    );
\sumYA[43]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[83]\,
      I1 => \colsumY_reg_n_0_[62]\,
      O => \sumYA[43]_i_4_n_0\
    );
\sumYA[43]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[82]\,
      I1 => \colsumY_reg_n_0_[61]\,
      O => \sumYA[43]_i_5_n_0\
    );
\sumYA[43]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[81]\,
      I1 => \colsumY_reg_n_0_[60]\,
      O => \sumYA[43]_i_6_n_0\
    );
\sumYA[43]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[80]\,
      I1 => \colsumY_reg_n_0_[59]\,
      O => \sumYA[43]_i_7_n_0\
    );
\sumYA[43]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[79]\,
      I1 => \colsumY_reg_n_0_[58]\,
      O => \sumYA[43]_i_8_n_0\
    );
\sumYA[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(4),
      O => \sumYA[4]_i_1_n_0\
    );
\sumYA[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(5),
      O => \sumYA[5]_i_1_n_0\
    );
\sumYA[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(6),
      O => \sumYA[6]_i_1_n_0\
    );
\sumYA[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(7),
      O => \sumYA[7]_i_1_n_0\
    );
\sumYA[7]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[21]\,
      I1 => \colsumY_reg_n_0_[0]\,
      O => \sumYA[7]_i_10_n_0\
    );
\sumYA[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[28]\,
      I1 => \colsumY_reg_n_0_[7]\,
      O => \sumYA[7]_i_3_n_0\
    );
\sumYA[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[27]\,
      I1 => \colsumY_reg_n_0_[6]\,
      O => \sumYA[7]_i_4_n_0\
    );
\sumYA[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[26]\,
      I1 => \colsumY_reg_n_0_[5]\,
      O => \sumYA[7]_i_5_n_0\
    );
\sumYA[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[25]\,
      I1 => \colsumY_reg_n_0_[4]\,
      O => \sumYA[7]_i_6_n_0\
    );
\sumYA[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[24]\,
      I1 => \colsumY_reg_n_0_[3]\,
      O => \sumYA[7]_i_7_n_0\
    );
\sumYA[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[23]\,
      I1 => \colsumY_reg_n_0_[2]\,
      O => \sumYA[7]_i_8_n_0\
    );
\sumYA[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \colsumY_reg_n_0_[22]\,
      I1 => \colsumY_reg_n_0_[1]\,
      O => \sumYA[7]_i_9_n_0\
    );
\sumYA[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(8),
      O => \sumYA[8]_i_1_n_0\
    );
\sumYA[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__6_n_0\,
      I1 => sumYA0(9),
      O => \sumYA[9]_i_1_n_0\
    );
\sumYA_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[0]_i_1_n_0\,
      Q => sumYA(0)
    );
\sumYA_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[10]_i_1_n_0\,
      Q => sumYA(10)
    );
\sumYA_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[11]_i_1_n_0\,
      Q => sumYA(11)
    );
\sumYA_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[12]_i_1_n_0\,
      Q => sumYA(12)
    );
\sumYA_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[13]_i_1_n_0\,
      Q => sumYA(13)
    );
\sumYA_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[14]_i_1_n_0\,
      Q => sumYA(14)
    );
\sumYA_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[15]_i_1_n_0\,
      Q => sumYA(15)
    );
\sumYA_reg[15]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumYA_reg[7]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \sumYA_reg[15]_i_2_n_0\,
      CO(6) => \sumYA_reg[15]_i_2_n_1\,
      CO(5) => \sumYA_reg[15]_i_2_n_2\,
      CO(4) => \sumYA_reg[15]_i_2_n_3\,
      CO(3) => \sumYA_reg[15]_i_2_n_4\,
      CO(2) => \sumYA_reg[15]_i_2_n_5\,
      CO(1) => \sumYA_reg[15]_i_2_n_6\,
      CO(0) => \sumYA_reg[15]_i_2_n_7\,
      DI(7) => \colsumY_reg_n_0_[36]\,
      DI(6) => \colsumY_reg_n_0_[35]\,
      DI(5) => \colsumY_reg_n_0_[34]\,
      DI(4) => \colsumY_reg_n_0_[33]\,
      DI(3) => \colsumY_reg_n_0_[32]\,
      DI(2) => \colsumY_reg_n_0_[31]\,
      DI(1) => \colsumY_reg_n_0_[30]\,
      DI(0) => \colsumY_reg_n_0_[29]\,
      O(7 downto 0) => sumYA0(15 downto 8),
      S(7) => \sumYA[15]_i_3_n_0\,
      S(6) => \sumYA[15]_i_4_n_0\,
      S(5) => \sumYA[15]_i_5_n_0\,
      S(4) => \sumYA[15]_i_6_n_0\,
      S(3) => \sumYA[15]_i_7_n_0\,
      S(2) => \sumYA[15]_i_8_n_0\,
      S(1) => \sumYA[15]_i_9_n_0\,
      S(0) => \sumYA[15]_i_10_n_0\
    );
\sumYA_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[16]_i_1_n_0\,
      Q => sumYA(16)
    );
\sumYA_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[17]_i_1_n_0\,
      Q => sumYA(17)
    );
\sumYA_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[18]_i_1_n_0\,
      Q => sumYA(18)
    );
\sumYA_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[19]_i_1_n_0\,
      Q => sumYA(19)
    );
\sumYA_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[1]_i_1_n_0\,
      Q => sumYA(1)
    );
\sumYA_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[20]_i_1_n_0\,
      Q => sumYA(20)
    );
\sumYA_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[21]_i_1_n_0\,
      Q => sumYA(21)
    );
\sumYA_reg[21]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumYA_reg[15]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_sumYA_reg[21]_i_2_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \sumYA_reg[21]_i_2_n_2\,
      CO(4) => \NLW_sumYA_reg[21]_i_2_CO_UNCONNECTED\(4),
      CO(3) => \sumYA_reg[21]_i_2_n_4\,
      CO(2) => \sumYA_reg[21]_i_2_n_5\,
      CO(1) => \sumYA_reg[21]_i_2_n_6\,
      CO(0) => \sumYA_reg[21]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \sumYA[21]_i_3_n_0\,
      DI(3) => \colsumY_reg_n_0_[40]\,
      DI(2) => \colsumY_reg_n_0_[39]\,
      DI(1) => \colsumY_reg_n_0_[38]\,
      DI(0) => \colsumY_reg_n_0_[37]\,
      O(7 downto 5) => \NLW_sumYA_reg[21]_i_2_O_UNCONNECTED\(7 downto 5),
      O(4 downto 0) => sumYA0(20 downto 16),
      S(7 downto 5) => B"001",
      S(4) => \sumYA[21]_i_4_n_0\,
      S(3) => \sumYA[21]_i_5_n_0\,
      S(2) => \sumYA[21]_i_6_n_0\,
      S(1) => \sumYA[21]_i_7_n_0\,
      S(0) => \sumYA[21]_i_8_n_0\
    );
\sumYA_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[22]_i_1_n_0\,
      Q => sumYA(22)
    );
\sumYA_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[23]_i_1_n_0\,
      Q => sumYA(23)
    );
\sumYA_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[24]_i_1_n_0\,
      Q => sumYA(24)
    );
\sumYA_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[25]_i_1_n_0\,
      Q => sumYA(25)
    );
\sumYA_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[26]_i_1_n_0\,
      Q => sumYA(26)
    );
\sumYA_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[27]_i_1_n_0\,
      Q => sumYA(27)
    );
\sumYA_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[28]_i_1_n_0\,
      Q => sumYA(28)
    );
\sumYA_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[29]_i_1_n_0\,
      Q => sumYA(29)
    );
\sumYA_reg[29]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \sumYA_reg[29]_i_2_n_0\,
      CO(6) => \sumYA_reg[29]_i_2_n_1\,
      CO(5) => \sumYA_reg[29]_i_2_n_2\,
      CO(4) => \sumYA_reg[29]_i_2_n_3\,
      CO(3) => \sumYA_reg[29]_i_2_n_4\,
      CO(2) => \sumYA_reg[29]_i_2_n_5\,
      CO(1) => \sumYA_reg[29]_i_2_n_6\,
      CO(0) => \sumYA_reg[29]_i_2_n_7\,
      DI(7) => \colsumY_reg_n_0_[70]\,
      DI(6) => \colsumY_reg_n_0_[69]\,
      DI(5) => \colsumY_reg_n_0_[68]\,
      DI(4) => \colsumY_reg_n_0_[67]\,
      DI(3) => \colsumY_reg_n_0_[66]\,
      DI(2) => \colsumY_reg_n_0_[65]\,
      DI(1) => \colsumY_reg_n_0_[64]\,
      DI(0) => \colsumY_reg_n_0_[63]\,
      O(7 downto 0) => sumYA00_in(7 downto 0),
      S(7) => \sumYA[29]_i_3_n_0\,
      S(6) => \sumYA[29]_i_4_n_0\,
      S(5) => \sumYA[29]_i_5_n_0\,
      S(4) => \sumYA[29]_i_6_n_0\,
      S(3) => \sumYA[29]_i_7_n_0\,
      S(2) => \sumYA[29]_i_8_n_0\,
      S(1) => \sumYA[29]_i_9_n_0\,
      S(0) => \sumYA[29]_i_10_n_0\
    );
\sumYA_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[2]_i_1_n_0\,
      Q => sumYA(2)
    );
\sumYA_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[30]_i_1_n_0\,
      Q => sumYA(30)
    );
\sumYA_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[31]_i_1_n_0\,
      Q => sumYA(31)
    );
\sumYA_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[32]_i_1_n_0\,
      Q => sumYA(32)
    );
\sumYA_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[33]_i_1_n_0\,
      Q => sumYA(33)
    );
\sumYA_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[34]_i_1_n_0\,
      Q => sumYA(34)
    );
\sumYA_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[35]_i_1_n_0\,
      Q => sumYA(35)
    );
\sumYA_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[36]_i_1_n_0\,
      Q => sumYA(36)
    );
\sumYA_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[37]_i_1_n_0\,
      Q => sumYA(37)
    );
\sumYA_reg[37]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumYA_reg[29]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \sumYA_reg[37]_i_2_n_0\,
      CO(6) => \sumYA_reg[37]_i_2_n_1\,
      CO(5) => \sumYA_reg[37]_i_2_n_2\,
      CO(4) => \sumYA_reg[37]_i_2_n_3\,
      CO(3) => \sumYA_reg[37]_i_2_n_4\,
      CO(2) => \sumYA_reg[37]_i_2_n_5\,
      CO(1) => \sumYA_reg[37]_i_2_n_6\,
      CO(0) => \sumYA_reg[37]_i_2_n_7\,
      DI(7) => \colsumY_reg_n_0_[78]\,
      DI(6) => \colsumY_reg_n_0_[77]\,
      DI(5) => \colsumY_reg_n_0_[76]\,
      DI(4) => \colsumY_reg_n_0_[75]\,
      DI(3) => \colsumY_reg_n_0_[74]\,
      DI(2) => \colsumY_reg_n_0_[73]\,
      DI(1) => \colsumY_reg_n_0_[72]\,
      DI(0) => \colsumY_reg_n_0_[71]\,
      O(7 downto 0) => sumYA00_in(15 downto 8),
      S(7) => \sumYA[37]_i_3_n_0\,
      S(6) => \sumYA[37]_i_4_n_0\,
      S(5) => \sumYA[37]_i_5_n_0\,
      S(4) => \sumYA[37]_i_6_n_0\,
      S(3) => \sumYA[37]_i_7_n_0\,
      S(2) => \sumYA[37]_i_8_n_0\,
      S(1) => \sumYA[37]_i_9_n_0\,
      S(0) => \sumYA[37]_i_10_n_0\
    );
\sumYA_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[38]_i_1_n_0\,
      Q => sumYA(38)
    );
\sumYA_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[39]_i_1_n_0\,
      Q => sumYA(39)
    );
\sumYA_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[3]_i_1_n_0\,
      Q => sumYA(3)
    );
\sumYA_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[40]_i_1_n_0\,
      Q => sumYA(40)
    );
\sumYA_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[41]_i_1_n_0\,
      Q => sumYA(41)
    );
\sumYA_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[42]_i_1_n_0\,
      Q => sumYA(42)
    );
\sumYA_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[43]_i_1_n_0\,
      Q => sumYA(43)
    );
\sumYA_reg[43]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumYA_reg[37]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_sumYA_reg[43]_i_2_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \sumYA_reg[43]_i_2_n_2\,
      CO(4) => \NLW_sumYA_reg[43]_i_2_CO_UNCONNECTED\(4),
      CO(3) => \sumYA_reg[43]_i_2_n_4\,
      CO(2) => \sumYA_reg[43]_i_2_n_5\,
      CO(1) => \sumYA_reg[43]_i_2_n_6\,
      CO(0) => \sumYA_reg[43]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \sumYA[43]_i_3_n_0\,
      DI(3) => \colsumY_reg_n_0_[82]\,
      DI(2) => \colsumY_reg_n_0_[81]\,
      DI(1) => \colsumY_reg_n_0_[80]\,
      DI(0) => \colsumY_reg_n_0_[79]\,
      O(7 downto 5) => \NLW_sumYA_reg[43]_i_2_O_UNCONNECTED\(7 downto 5),
      O(4 downto 0) => sumYA00_in(20 downto 16),
      S(7 downto 5) => B"001",
      S(4) => \sumYA[43]_i_4_n_0\,
      S(3) => \sumYA[43]_i_5_n_0\,
      S(2) => \sumYA[43]_i_6_n_0\,
      S(1) => \sumYA[43]_i_7_n_0\,
      S(0) => \sumYA[43]_i_8_n_0\
    );
\sumYA_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[4]_i_1_n_0\,
      Q => sumYA(4)
    );
\sumYA_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[5]_i_1_n_0\,
      Q => sumYA(5)
    );
\sumYA_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[6]_i_1_n_0\,
      Q => sumYA(6)
    );
\sumYA_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[7]_i_1_n_0\,
      Q => sumYA(7)
    );
\sumYA_reg[7]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \sumYA_reg[7]_i_2_n_0\,
      CO(6) => \sumYA_reg[7]_i_2_n_1\,
      CO(5) => \sumYA_reg[7]_i_2_n_2\,
      CO(4) => \sumYA_reg[7]_i_2_n_3\,
      CO(3) => \sumYA_reg[7]_i_2_n_4\,
      CO(2) => \sumYA_reg[7]_i_2_n_5\,
      CO(1) => \sumYA_reg[7]_i_2_n_6\,
      CO(0) => \sumYA_reg[7]_i_2_n_7\,
      DI(7) => \colsumY_reg_n_0_[28]\,
      DI(6) => \colsumY_reg_n_0_[27]\,
      DI(5) => \colsumY_reg_n_0_[26]\,
      DI(4) => \colsumY_reg_n_0_[25]\,
      DI(3) => \colsumY_reg_n_0_[24]\,
      DI(2) => \colsumY_reg_n_0_[23]\,
      DI(1) => \colsumY_reg_n_0_[22]\,
      DI(0) => \colsumY_reg_n_0_[21]\,
      O(7 downto 0) => sumYA0(7 downto 0),
      S(7) => \sumYA[7]_i_3_n_0\,
      S(6) => \sumYA[7]_i_4_n_0\,
      S(5) => \sumYA[7]_i_5_n_0\,
      S(4) => \sumYA[7]_i_6_n_0\,
      S(3) => \sumYA[7]_i_7_n_0\,
      S(2) => \sumYA[7]_i_8_n_0\,
      S(1) => \sumYA[7]_i_9_n_0\,
      S(0) => \sumYA[7]_i_10_n_0\
    );
\sumYA_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[8]_i_1_n_0\,
      Q => sumYA(8)
    );
\sumYA_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYA[9]_i_1_n_0\,
      Q => sumYA(9)
    );
\sumYB[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(15),
      I1 => sumYA(37),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_10_n_0\
    );
\sumYB[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(14),
      I1 => sumYA(36),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_11_n_0\
    );
\sumYB[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(13),
      I1 => sumYA(35),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_12_n_0\
    );
\sumYB[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(12),
      I1 => sumYA(34),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_13_n_0\
    );
\sumYB[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(11),
      I1 => sumYA(33),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_14_n_0\
    );
\sumYB[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(10),
      I1 => sumYA(32),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_15_n_0\
    );
\sumYB[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(9),
      I1 => sumYA(31),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_16_n_0\
    );
\sumYB[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(8),
      I1 => sumYA(30),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_17_n_0\
    );
\sumYB[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(15),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_2_n_0\
    );
\sumYB[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(14),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_3_n_0\
    );
\sumYB[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(13),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_4_n_0\
    );
\sumYB[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(12),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_5_n_0\
    );
\sumYB[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(11),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_6_n_0\
    );
\sumYB[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(10),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_7_n_0\
    );
\sumYB[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(9),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_8_n_0\
    );
\sumYB[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(8),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[15]_i_9_n_0\
    );
\sumYB[22]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(20),
      I1 => sumYA(42),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumYB[22]_i_10_n_0\
    );
\sumYB[22]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(19),
      I1 => sumYA(41),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumYB[22]_i_11_n_0\
    );
\sumYB[22]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(18),
      I1 => sumYA(40),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumYB[22]_i_12_n_0\
    );
\sumYB[22]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(17),
      I1 => sumYA(39),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumYB[22]_i_13_n_0\
    );
\sumYB[22]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(16),
      I1 => sumYA(38),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumYB[22]_i_14_n_0\
    );
\sumYB[22]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(21),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumYB[22]_i_2_n_0\
    );
\sumYB[22]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(20),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumYB[22]_i_3_n_0\
    );
\sumYB[22]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(19),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumYB[22]_i_4_n_0\
    );
\sumYB[22]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(18),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumYB[22]_i_5_n_0\
    );
\sumYB[22]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(17),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumYB[22]_i_6_n_0\
    );
\sumYB[22]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(16),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumYB[22]_i_7_n_0\
    );
\sumYB[22]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(21),
      I1 => sumYA(43),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumYB[22]_i_8_n_0\
    );
\sumYB[22]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(21),
      I1 => sumYA(43),
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumYB[22]_i_9_n_0\
    );
\sumYB[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(7),
      I1 => sumYA(29),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_10_n_0\
    );
\sumYB[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(6),
      I1 => sumYA(28),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_11_n_0\
    );
\sumYB[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(5),
      I1 => sumYA(27),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_12_n_0\
    );
\sumYB[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(4),
      I1 => sumYA(26),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_13_n_0\
    );
\sumYB[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(3),
      I1 => sumYA(25),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_14_n_0\
    );
\sumYB[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(2),
      I1 => sumYA(24),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_15_n_0\
    );
\sumYB[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(1),
      I1 => sumYA(23),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_16_n_0\
    );
\sumYB[7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => sumYA(0),
      I1 => sumYA(22),
      I2 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_17_n_0\
    );
\sumYB[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(7),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_2_n_0\
    );
\sumYB[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(6),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_3_n_0\
    );
\sumYB[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(5),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_4_n_0\
    );
\sumYB[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(4),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_5_n_0\
    );
\sumYB[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(3),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_6_n_0\
    );
\sumYB[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(2),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_7_n_0\
    );
\sumYB[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(1),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_8_n_0\
    );
\sumYB[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => sumYA(0),
      I1 => \stateScore_reg_rep__6_n_0\,
      O => \sumYB[7]_i_9_n_0\
    );
\sumYB_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[7]_i_1_n_15\,
      Q => \sumYB_reg_n_0_[0]\
    );
\sumYB_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[15]_i_1_n_13\,
      Q => \sumYB_reg_n_0_[10]\
    );
\sumYB_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[15]_i_1_n_12\,
      Q => \sumYB_reg_n_0_[11]\
    );
\sumYB_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[15]_i_1_n_11\,
      Q => \sumYB_reg_n_0_[12]\
    );
\sumYB_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[15]_i_1_n_10\,
      Q => \sumYB_reg_n_0_[13]\
    );
\sumYB_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[15]_i_1_n_9\,
      Q => \sumYB_reg_n_0_[14]\
    );
\sumYB_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[15]_i_1_n_8\,
      Q => \sumYB_reg_n_0_[15]\
    );
\sumYB_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumYB_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \sumYB_reg[15]_i_1_n_0\,
      CO(6) => \sumYB_reg[15]_i_1_n_1\,
      CO(5) => \sumYB_reg[15]_i_1_n_2\,
      CO(4) => \sumYB_reg[15]_i_1_n_3\,
      CO(3) => \sumYB_reg[15]_i_1_n_4\,
      CO(2) => \sumYB_reg[15]_i_1_n_5\,
      CO(1) => \sumYB_reg[15]_i_1_n_6\,
      CO(0) => \sumYB_reg[15]_i_1_n_7\,
      DI(7) => \sumYB[15]_i_2_n_0\,
      DI(6) => \sumYB[15]_i_3_n_0\,
      DI(5) => \sumYB[15]_i_4_n_0\,
      DI(4) => \sumYB[15]_i_5_n_0\,
      DI(3) => \sumYB[15]_i_6_n_0\,
      DI(2) => \sumYB[15]_i_7_n_0\,
      DI(1) => \sumYB[15]_i_8_n_0\,
      DI(0) => \sumYB[15]_i_9_n_0\,
      O(7) => \sumYB_reg[15]_i_1_n_8\,
      O(6) => \sumYB_reg[15]_i_1_n_9\,
      O(5) => \sumYB_reg[15]_i_1_n_10\,
      O(4) => \sumYB_reg[15]_i_1_n_11\,
      O(3) => \sumYB_reg[15]_i_1_n_12\,
      O(2) => \sumYB_reg[15]_i_1_n_13\,
      O(1) => \sumYB_reg[15]_i_1_n_14\,
      O(0) => \sumYB_reg[15]_i_1_n_15\,
      S(7) => \sumYB[15]_i_10_n_0\,
      S(6) => \sumYB[15]_i_11_n_0\,
      S(5) => \sumYB[15]_i_12_n_0\,
      S(4) => \sumYB[15]_i_13_n_0\,
      S(3) => \sumYB[15]_i_14_n_0\,
      S(2) => \sumYB[15]_i_15_n_0\,
      S(1) => \sumYB[15]_i_16_n_0\,
      S(0) => \sumYB[15]_i_17_n_0\
    );
\sumYB_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[22]_i_1_n_15\,
      Q => \sumYB_reg_n_0_[16]\
    );
\sumYB_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[22]_i_1_n_14\,
      Q => \sumYB_reg_n_0_[17]\
    );
\sumYB_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[22]_i_1_n_13\,
      Q => \sumYB_reg_n_0_[18]\
    );
\sumYB_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[22]_i_1_n_12\,
      Q => \sumYB_reg_n_0_[19]\
    );
\sumYB_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[7]_i_1_n_14\,
      Q => \sumYB_reg_n_0_[1]\
    );
\sumYB_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[22]_i_1_n_11\,
      Q => \sumYB_reg_n_0_[20]\
    );
\sumYB_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[22]_i_1_n_10\,
      Q => \sumYB_reg_n_0_[21]\
    );
\sumYB_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[22]_i_1_n_9\,
      Q => \sumYB_reg_n_0_[22]\
    );
\sumYB_reg[22]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumYB_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_sumYB_reg[22]_i_1_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \sumYB_reg[22]_i_1_n_2\,
      CO(4) => \sumYB_reg[22]_i_1_n_3\,
      CO(3) => \sumYB_reg[22]_i_1_n_4\,
      CO(2) => \sumYB_reg[22]_i_1_n_5\,
      CO(1) => \sumYB_reg[22]_i_1_n_6\,
      CO(0) => \sumYB_reg[22]_i_1_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \sumYB[22]_i_2_n_0\,
      DI(4) => \sumYB[22]_i_3_n_0\,
      DI(3) => \sumYB[22]_i_4_n_0\,
      DI(2) => \sumYB[22]_i_5_n_0\,
      DI(1) => \sumYB[22]_i_6_n_0\,
      DI(0) => \sumYB[22]_i_7_n_0\,
      O(7) => \NLW_sumYB_reg[22]_i_1_O_UNCONNECTED\(7),
      O(6) => \sumYB_reg[22]_i_1_n_9\,
      O(5) => \sumYB_reg[22]_i_1_n_10\,
      O(4) => \sumYB_reg[22]_i_1_n_11\,
      O(3) => \sumYB_reg[22]_i_1_n_12\,
      O(2) => \sumYB_reg[22]_i_1_n_13\,
      O(1) => \sumYB_reg[22]_i_1_n_14\,
      O(0) => \sumYB_reg[22]_i_1_n_15\,
      S(7) => '0',
      S(6) => \sumYB[22]_i_8_n_0\,
      S(5) => \sumYB[22]_i_9_n_0\,
      S(4) => \sumYB[22]_i_10_n_0\,
      S(3) => \sumYB[22]_i_11_n_0\,
      S(2) => \sumYB[22]_i_12_n_0\,
      S(1) => \sumYB[22]_i_13_n_0\,
      S(0) => \sumYB[22]_i_14_n_0\
    );
\sumYB_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[7]_i_1_n_13\,
      Q => \sumYB_reg_n_0_[2]\
    );
\sumYB_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[7]_i_1_n_12\,
      Q => \sumYB_reg_n_0_[3]\
    );
\sumYB_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[7]_i_1_n_11\,
      Q => \sumYB_reg_n_0_[4]\
    );
\sumYB_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[7]_i_1_n_10\,
      Q => \sumYB_reg_n_0_[5]\
    );
\sumYB_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[7]_i_1_n_9\,
      Q => \sumYB_reg_n_0_[6]\
    );
\sumYB_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[7]_i_1_n_8\,
      Q => \sumYB_reg_n_0_[7]\
    );
\sumYB_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \sumYB_reg[7]_i_1_n_0\,
      CO(6) => \sumYB_reg[7]_i_1_n_1\,
      CO(5) => \sumYB_reg[7]_i_1_n_2\,
      CO(4) => \sumYB_reg[7]_i_1_n_3\,
      CO(3) => \sumYB_reg[7]_i_1_n_4\,
      CO(2) => \sumYB_reg[7]_i_1_n_5\,
      CO(1) => \sumYB_reg[7]_i_1_n_6\,
      CO(0) => \sumYB_reg[7]_i_1_n_7\,
      DI(7) => \sumYB[7]_i_2_n_0\,
      DI(6) => \sumYB[7]_i_3_n_0\,
      DI(5) => \sumYB[7]_i_4_n_0\,
      DI(4) => \sumYB[7]_i_5_n_0\,
      DI(3) => \sumYB[7]_i_6_n_0\,
      DI(2) => \sumYB[7]_i_7_n_0\,
      DI(1) => \sumYB[7]_i_8_n_0\,
      DI(0) => \sumYB[7]_i_9_n_0\,
      O(7) => \sumYB_reg[7]_i_1_n_8\,
      O(6) => \sumYB_reg[7]_i_1_n_9\,
      O(5) => \sumYB_reg[7]_i_1_n_10\,
      O(4) => \sumYB_reg[7]_i_1_n_11\,
      O(3) => \sumYB_reg[7]_i_1_n_12\,
      O(2) => \sumYB_reg[7]_i_1_n_13\,
      O(1) => \sumYB_reg[7]_i_1_n_14\,
      O(0) => \sumYB_reg[7]_i_1_n_15\,
      S(7) => \sumYB[7]_i_10_n_0\,
      S(6) => \sumYB[7]_i_11_n_0\,
      S(5) => \sumYB[7]_i_12_n_0\,
      S(4) => \sumYB[7]_i_13_n_0\,
      S(3) => \sumYB[7]_i_14_n_0\,
      S(2) => \sumYB[7]_i_15_n_0\,
      S(1) => \sumYB[7]_i_16_n_0\,
      S(0) => \sumYB[7]_i_17_n_0\
    );
\sumYB_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[15]_i_1_n_15\,
      Q => \sumYB_reg_n_0_[8]\
    );
\sumYB_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumYB_reg[15]_i_1_n_14\,
      Q => \sumYB_reg_n_0_[9]\
    );
\sumY[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(15),
      I1 => \sumYB_reg_n_0_[15]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_10_n_0\
    );
\sumY[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(14),
      I1 => \sumYB_reg_n_0_[14]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_11_n_0\
    );
\sumY[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(13),
      I1 => \sumYB_reg_n_0_[13]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_12_n_0\
    );
\sumY[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(12),
      I1 => \sumYB_reg_n_0_[12]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_13_n_0\
    );
\sumY[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(11),
      I1 => \sumYB_reg_n_0_[11]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_14_n_0\
    );
\sumY[15]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(10),
      I1 => \sumYB_reg_n_0_[10]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_15_n_0\
    );
\sumY[15]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(9),
      I1 => \sumYB_reg_n_0_[9]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_16_n_0\
    );
\sumY[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(8),
      I1 => \sumYB_reg_n_0_[8]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_17_n_0\
    );
\sumY[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(15),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_2_n_0\
    );
\sumY[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(14),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_3_n_0\
    );
\sumY[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(13),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_4_n_0\
    );
\sumY[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(12),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_5_n_0\
    );
\sumY[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(11),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_6_n_0\
    );
\sumY[15]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(10),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_7_n_0\
    );
\sumY[15]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(9),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_8_n_0\
    );
\sumY[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(8),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[15]_i_9_n_0\
    );
\sumY[22]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(20),
      I1 => \sumYB_reg_n_0_[20]\,
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumY[22]_i_10_n_0\
    );
\sumY[22]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(19),
      I1 => \sumYB_reg_n_0_[19]\,
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumY[22]_i_11_n_0\
    );
\sumY[22]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(18),
      I1 => \sumYB_reg_n_0_[18]\,
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumY[22]_i_12_n_0\
    );
\sumY[22]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(17),
      I1 => \sumYB_reg_n_0_[17]\,
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumY[22]_i_13_n_0\
    );
\sumY[22]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(16),
      I1 => \sumYB_reg_n_0_[16]\,
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumY[22]_i_14_n_0\
    );
\sumY[22]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(20),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumY[22]_i_2_n_0\
    );
\sumY[22]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(20),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumY[22]_i_3_n_0\
    );
\sumY[22]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(19),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumY[22]_i_4_n_0\
    );
\sumY[22]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(18),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumY[22]_i_5_n_0\
    );
\sumY[22]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(17),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumY[22]_i_6_n_0\
    );
\sumY[22]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(16),
      I1 => \stateScore_reg_rep__11_n_0\,
      O => \sumY[22]_i_7_n_0\
    );
\sumY[22]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(20),
      I1 => \sumYB_reg_n_0_[22]\,
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumY[22]_i_8_n_0\
    );
\sumY[22]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(20),
      I1 => \sumYB_reg_n_0_[21]\,
      I2 => \stateScore_reg_rep__11_n_0\,
      O => \sumY[22]_i_9_n_0\
    );
\sumY[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(7),
      I1 => \sumYB_reg_n_0_[7]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_10_n_0\
    );
\sumY[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(6),
      I1 => \sumYB_reg_n_0_[6]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_11_n_0\
    );
\sumY[7]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(5),
      I1 => \sumYB_reg_n_0_[5]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_12_n_0\
    );
\sumY[7]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(4),
      I1 => \sumYB_reg_n_0_[4]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_13_n_0\
    );
\sumY[7]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(3),
      I1 => \sumYB_reg_n_0_[3]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_14_n_0\
    );
\sumY[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(2),
      I1 => \sumYB_reg_n_0_[2]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_15_n_0\
    );
\sumY[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(1),
      I1 => \sumYB_reg_n_0_[1]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_16_n_0\
    );
\sumY[7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => colsumY4p2(0),
      I1 => \sumYB_reg_n_0_[0]\,
      I2 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_17_n_0\
    );
\sumY[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(7),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_2_n_0\
    );
\sumY[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(6),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_3_n_0\
    );
\sumY[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(5),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_4_n_0\
    );
\sumY[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(4),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_5_n_0\
    );
\sumY[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(3),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_6_n_0\
    );
\sumY[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(2),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_7_n_0\
    );
\sumY[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(1),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_8_n_0\
    );
\sumY[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => colsumY4p2(0),
      I1 => \stateScore_reg_rep__5_n_0\,
      O => \sumY[7]_i_9_n_0\
    );
\sumY_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[7]_i_1_n_15\,
      Q => \sumY_reg_n_0_[0]\
    );
\sumY_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[15]_i_1_n_13\,
      Q => \sumY_reg_n_0_[10]\
    );
\sumY_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[15]_i_1_n_12\,
      Q => \sumY_reg_n_0_[11]\
    );
\sumY_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[15]_i_1_n_11\,
      Q => \sumY_reg_n_0_[12]\
    );
\sumY_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[15]_i_1_n_10\,
      Q => \sumY_reg_n_0_[13]\
    );
\sumY_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[15]_i_1_n_9\,
      Q => \sumY_reg_n_0_[14]\
    );
\sumY_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[15]_i_1_n_8\,
      Q => \sumY_reg_n_0_[15]\
    );
\sumY_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumY_reg[7]_i_1_n_0\,
      CI_TOP => '0',
      CO(7) => \sumY_reg[15]_i_1_n_0\,
      CO(6) => \sumY_reg[15]_i_1_n_1\,
      CO(5) => \sumY_reg[15]_i_1_n_2\,
      CO(4) => \sumY_reg[15]_i_1_n_3\,
      CO(3) => \sumY_reg[15]_i_1_n_4\,
      CO(2) => \sumY_reg[15]_i_1_n_5\,
      CO(1) => \sumY_reg[15]_i_1_n_6\,
      CO(0) => \sumY_reg[15]_i_1_n_7\,
      DI(7) => \sumY[15]_i_2_n_0\,
      DI(6) => \sumY[15]_i_3_n_0\,
      DI(5) => \sumY[15]_i_4_n_0\,
      DI(4) => \sumY[15]_i_5_n_0\,
      DI(3) => \sumY[15]_i_6_n_0\,
      DI(2) => \sumY[15]_i_7_n_0\,
      DI(1) => \sumY[15]_i_8_n_0\,
      DI(0) => \sumY[15]_i_9_n_0\,
      O(7) => \sumY_reg[15]_i_1_n_8\,
      O(6) => \sumY_reg[15]_i_1_n_9\,
      O(5) => \sumY_reg[15]_i_1_n_10\,
      O(4) => \sumY_reg[15]_i_1_n_11\,
      O(3) => \sumY_reg[15]_i_1_n_12\,
      O(2) => \sumY_reg[15]_i_1_n_13\,
      O(1) => \sumY_reg[15]_i_1_n_14\,
      O(0) => \sumY_reg[15]_i_1_n_15\,
      S(7) => \sumY[15]_i_10_n_0\,
      S(6) => \sumY[15]_i_11_n_0\,
      S(5) => \sumY[15]_i_12_n_0\,
      S(4) => \sumY[15]_i_13_n_0\,
      S(3) => \sumY[15]_i_14_n_0\,
      S(2) => \sumY[15]_i_15_n_0\,
      S(1) => \sumY[15]_i_16_n_0\,
      S(0) => \sumY[15]_i_17_n_0\
    );
\sumY_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[22]_i_1_n_15\,
      Q => \sumY_reg_n_0_[16]\
    );
\sumY_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[22]_i_1_n_14\,
      Q => \sumY_reg_n_0_[17]\
    );
\sumY_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[22]_i_1_n_13\,
      Q => \sumY_reg_n_0_[18]\
    );
\sumY_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[22]_i_1_n_12\,
      Q => \sumY_reg_n_0_[19]\
    );
\sumY_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[7]_i_1_n_14\,
      Q => \sumY_reg_n_0_[1]\
    );
\sumY_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[22]_i_1_n_11\,
      Q => \sumY_reg_n_0_[20]\
    );
\sumY_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[22]_i_1_n_10\,
      Q => \sumY_reg_n_0_[21]\
    );
\sumY_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[22]_i_1_n_9\,
      Q => \sumY_reg_n_0_[22]\
    );
\sumY_reg[22]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => \sumY_reg[15]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_sumY_reg[22]_i_1_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \sumY_reg[22]_i_1_n_2\,
      CO(4) => \sumY_reg[22]_i_1_n_3\,
      CO(3) => \sumY_reg[22]_i_1_n_4\,
      CO(2) => \sumY_reg[22]_i_1_n_5\,
      CO(1) => \sumY_reg[22]_i_1_n_6\,
      CO(0) => \sumY_reg[22]_i_1_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \sumY[22]_i_2_n_0\,
      DI(4) => \sumY[22]_i_3_n_0\,
      DI(3) => \sumY[22]_i_4_n_0\,
      DI(2) => \sumY[22]_i_5_n_0\,
      DI(1) => \sumY[22]_i_6_n_0\,
      DI(0) => \sumY[22]_i_7_n_0\,
      O(7) => \NLW_sumY_reg[22]_i_1_O_UNCONNECTED\(7),
      O(6) => \sumY_reg[22]_i_1_n_9\,
      O(5) => \sumY_reg[22]_i_1_n_10\,
      O(4) => \sumY_reg[22]_i_1_n_11\,
      O(3) => \sumY_reg[22]_i_1_n_12\,
      O(2) => \sumY_reg[22]_i_1_n_13\,
      O(1) => \sumY_reg[22]_i_1_n_14\,
      O(0) => \sumY_reg[22]_i_1_n_15\,
      S(7) => '0',
      S(6) => \sumY[22]_i_8_n_0\,
      S(5) => \sumY[22]_i_9_n_0\,
      S(4) => \sumY[22]_i_10_n_0\,
      S(3) => \sumY[22]_i_11_n_0\,
      S(2) => \sumY[22]_i_12_n_0\,
      S(1) => \sumY[22]_i_13_n_0\,
      S(0) => \sumY[22]_i_14_n_0\
    );
\sumY_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[7]_i_1_n_13\,
      Q => \sumY_reg_n_0_[2]\
    );
\sumY_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[7]_i_1_n_12\,
      Q => \sumY_reg_n_0_[3]\
    );
\sumY_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[7]_i_1_n_11\,
      Q => \sumY_reg_n_0_[4]\
    );
\sumY_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[7]_i_1_n_10\,
      Q => \sumY_reg_n_0_[5]\
    );
\sumY_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[7]_i_1_n_9\,
      Q => \sumY_reg_n_0_[6]\
    );
\sumY_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[7]_i_1_n_8\,
      Q => \sumY_reg_n_0_[7]\
    );
\sumY_reg[7]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \sumY_reg[7]_i_1_n_0\,
      CO(6) => \sumY_reg[7]_i_1_n_1\,
      CO(5) => \sumY_reg[7]_i_1_n_2\,
      CO(4) => \sumY_reg[7]_i_1_n_3\,
      CO(3) => \sumY_reg[7]_i_1_n_4\,
      CO(2) => \sumY_reg[7]_i_1_n_5\,
      CO(1) => \sumY_reg[7]_i_1_n_6\,
      CO(0) => \sumY_reg[7]_i_1_n_7\,
      DI(7) => \sumY[7]_i_2_n_0\,
      DI(6) => \sumY[7]_i_3_n_0\,
      DI(5) => \sumY[7]_i_4_n_0\,
      DI(4) => \sumY[7]_i_5_n_0\,
      DI(3) => \sumY[7]_i_6_n_0\,
      DI(2) => \sumY[7]_i_7_n_0\,
      DI(1) => \sumY[7]_i_8_n_0\,
      DI(0) => \sumY[7]_i_9_n_0\,
      O(7) => \sumY_reg[7]_i_1_n_8\,
      O(6) => \sumY_reg[7]_i_1_n_9\,
      O(5) => \sumY_reg[7]_i_1_n_10\,
      O(4) => \sumY_reg[7]_i_1_n_11\,
      O(3) => \sumY_reg[7]_i_1_n_12\,
      O(2) => \sumY_reg[7]_i_1_n_13\,
      O(1) => \sumY_reg[7]_i_1_n_14\,
      O(0) => \sumY_reg[7]_i_1_n_15\,
      S(7) => \sumY[7]_i_10_n_0\,
      S(6) => \sumY[7]_i_11_n_0\,
      S(5) => \sumY[7]_i_12_n_0\,
      S(4) => \sumY[7]_i_13_n_0\,
      S(3) => \sumY[7]_i_14_n_0\,
      S(2) => \sumY[7]_i_15_n_0\,
      S(1) => \sumY[7]_i_16_n_0\,
      S(0) => \sumY[7]_i_17_n_0\
    );
\sumY_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[15]_i_1_n_15\,
      Q => \sumY_reg_n_0_[8]\
    );
\sumY_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \sumY_reg[15]_i_1_n_14\,
      Q => \sumY_reg_n_0_[9]\
    );
termI0: unisim.vcomponents.DSP48E2
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AMULTSEL => "A",
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      AUTORESET_PRIORITY => "RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BMULTSEL => "B",
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREADDINSEL => "A",
      PREG => 0,
      RND => X"000000000000",
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48",
      USE_WIDEXOR => "FALSE",
      XORSIMD => "XOR24_48_96"
    )
        port map (
      A(29) => \sumY_reg_n_0_[22]\,
      A(28) => \sumY_reg_n_0_[22]\,
      A(27) => \sumY_reg_n_0_[22]\,
      A(26) => \sumY_reg_n_0_[22]\,
      A(25) => \sumY_reg_n_0_[22]\,
      A(24) => \sumY_reg_n_0_[22]\,
      A(23) => \sumY_reg_n_0_[22]\,
      A(22) => \sumY_reg_n_0_[22]\,
      A(21) => \sumY_reg_n_0_[21]\,
      A(20) => \sumY_reg_n_0_[20]\,
      A(19) => \sumY_reg_n_0_[19]\,
      A(18) => \sumY_reg_n_0_[18]\,
      A(17) => \sumY_reg_n_0_[17]\,
      A(16) => \sumY_reg_n_0_[16]\,
      A(15) => \sumY_reg_n_0_[15]\,
      A(14) => \sumY_reg_n_0_[14]\,
      A(13) => \sumY_reg_n_0_[13]\,
      A(12) => \sumY_reg_n_0_[12]\,
      A(11) => \sumY_reg_n_0_[11]\,
      A(10) => \sumY_reg_n_0_[10]\,
      A(9) => \sumY_reg_n_0_[9]\,
      A(8) => \sumY_reg_n_0_[8]\,
      A(7) => \sumY_reg_n_0_[7]\,
      A(6) => \sumY_reg_n_0_[6]\,
      A(5) => \sumY_reg_n_0_[5]\,
      A(4) => \sumY_reg_n_0_[4]\,
      A(3) => \sumY_reg_n_0_[3]\,
      A(2) => \sumY_reg_n_0_[2]\,
      A(1) => \sumY_reg_n_0_[1]\,
      A(0) => \sumY_reg_n_0_[0]\,
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => NLW_termI0_ACOUT_UNCONNECTED(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17) => '0',
      B(16 downto 0) => sumX(16 downto 0),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => NLW_termI0_BCOUT_UNCONNECTED(17 downto 0),
      C(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      CARRYCASCIN => '0',
      CARRYCASCOUT => NLW_termI0_CARRYCASCOUT_UNCONNECTED,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => NLW_termI0_CARRYOUT_UNCONNECTED(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(26 downto 0) => B"000000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => NLW_termI0_MULTSIGNOUT_UNCONNECTED,
      OPMODE(8 downto 0) => B"000000101",
      OVERFLOW => NLW_termI0_OVERFLOW_UNCONNECTED,
      P(47) => termI0_n_58,
      P(46) => termI0_n_59,
      P(45) => termI0_n_60,
      P(44) => termI0_n_61,
      P(43) => termI0_n_62,
      P(42) => termI0_n_63,
      P(41) => termI0_n_64,
      P(40) => termI0_n_65,
      P(39) => termI0_n_66,
      P(38) => termI0_n_67,
      P(37) => termI0_n_68,
      P(36) => termI0_n_69,
      P(35) => termI0_n_70,
      P(34) => termI0_n_71,
      P(33) => termI0_n_72,
      P(32) => termI0_n_73,
      P(31) => termI0_n_74,
      P(30) => termI0_n_75,
      P(29) => termI0_n_76,
      P(28) => termI0_n_77,
      P(27) => termI0_n_78,
      P(26) => termI0_n_79,
      P(25) => termI0_n_80,
      P(24) => termI0_n_81,
      P(23) => termI0_n_82,
      P(22) => termI0_n_83,
      P(21) => termI0_n_84,
      P(20) => termI0_n_85,
      P(19) => termI0_n_86,
      P(18) => termI0_n_87,
      P(17) => termI0_n_88,
      P(16) => termI0_n_89,
      P(15) => termI0_n_90,
      P(14) => termI0_n_91,
      P(13) => termI0_n_92,
      P(12) => termI0_n_93,
      P(11) => termI0_n_94,
      P(10) => termI0_n_95,
      P(9) => termI0_n_96,
      P(8) => termI0_n_97,
      P(7) => termI0_n_98,
      P(6) => termI0_n_99,
      P(5) => termI0_n_100,
      P(4) => termI0_n_101,
      P(3) => termI0_n_102,
      P(2) => termI0_n_103,
      P(1) => termI0_n_104,
      P(0) => termI0_n_105,
      PATTERNBDETECT => NLW_termI0_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_termI0_PATTERNDETECT_UNCONNECTED,
      PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      PCOUT(47) => termI0_n_106,
      PCOUT(46) => termI0_n_107,
      PCOUT(45) => termI0_n_108,
      PCOUT(44) => termI0_n_109,
      PCOUT(43) => termI0_n_110,
      PCOUT(42) => termI0_n_111,
      PCOUT(41) => termI0_n_112,
      PCOUT(40) => termI0_n_113,
      PCOUT(39) => termI0_n_114,
      PCOUT(38) => termI0_n_115,
      PCOUT(37) => termI0_n_116,
      PCOUT(36) => termI0_n_117,
      PCOUT(35) => termI0_n_118,
      PCOUT(34) => termI0_n_119,
      PCOUT(33) => termI0_n_120,
      PCOUT(32) => termI0_n_121,
      PCOUT(31) => termI0_n_122,
      PCOUT(30) => termI0_n_123,
      PCOUT(29) => termI0_n_124,
      PCOUT(28) => termI0_n_125,
      PCOUT(27) => termI0_n_126,
      PCOUT(26) => termI0_n_127,
      PCOUT(25) => termI0_n_128,
      PCOUT(24) => termI0_n_129,
      PCOUT(23) => termI0_n_130,
      PCOUT(22) => termI0_n_131,
      PCOUT(21) => termI0_n_132,
      PCOUT(20) => termI0_n_133,
      PCOUT(19) => termI0_n_134,
      PCOUT(18) => termI0_n_135,
      PCOUT(17) => termI0_n_136,
      PCOUT(16) => termI0_n_137,
      PCOUT(15) => termI0_n_138,
      PCOUT(14) => termI0_n_139,
      PCOUT(13) => termI0_n_140,
      PCOUT(12) => termI0_n_141,
      PCOUT(11) => termI0_n_142,
      PCOUT(10) => termI0_n_143,
      PCOUT(9) => termI0_n_144,
      PCOUT(8) => termI0_n_145,
      PCOUT(7) => termI0_n_146,
      PCOUT(6) => termI0_n_147,
      PCOUT(5) => termI0_n_148,
      PCOUT(4) => termI0_n_149,
      PCOUT(3) => termI0_n_150,
      PCOUT(2) => termI0_n_151,
      PCOUT(1) => termI0_n_152,
      PCOUT(0) => termI0_n_153,
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => NLW_termI0_UNDERFLOW_UNCONNECTED,
      XOROUT(7 downto 0) => NLW_termI0_XOROUT_UNCONNECTED(7 downto 0)
    );
\termI0__0\: unisim.vcomponents.DSP48E2
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AMULTSEL => "A",
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      AUTORESET_PRIORITY => "RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BMULTSEL => "B",
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREADDINSEL => "A",
      PREG => 0,
      RND => X"000000000000",
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48",
      USE_WIDEXOR => "FALSE",
      XORSIMD => "XOR24_48_96"
    )
        port map (
      A(29) => \sumY_reg_n_0_[22]\,
      A(28) => \sumY_reg_n_0_[22]\,
      A(27) => \sumY_reg_n_0_[22]\,
      A(26) => \sumY_reg_n_0_[22]\,
      A(25) => \sumY_reg_n_0_[22]\,
      A(24) => \sumY_reg_n_0_[22]\,
      A(23) => \sumY_reg_n_0_[22]\,
      A(22) => \sumY_reg_n_0_[22]\,
      A(21) => \sumY_reg_n_0_[21]\,
      A(20) => \sumY_reg_n_0_[20]\,
      A(19) => \sumY_reg_n_0_[19]\,
      A(18) => \sumY_reg_n_0_[18]\,
      A(17) => \sumY_reg_n_0_[17]\,
      A(16) => \sumY_reg_n_0_[16]\,
      A(15) => \sumY_reg_n_0_[15]\,
      A(14) => \sumY_reg_n_0_[14]\,
      A(13) => \sumY_reg_n_0_[13]\,
      A(12) => \sumY_reg_n_0_[12]\,
      A(11) => \sumY_reg_n_0_[11]\,
      A(10) => \sumY_reg_n_0_[10]\,
      A(9) => \sumY_reg_n_0_[9]\,
      A(8) => \sumY_reg_n_0_[8]\,
      A(7) => \sumY_reg_n_0_[7]\,
      A(6) => \sumY_reg_n_0_[6]\,
      A(5) => \sumY_reg_n_0_[5]\,
      A(4) => \sumY_reg_n_0_[4]\,
      A(3) => \sumY_reg_n_0_[3]\,
      A(2) => \sumY_reg_n_0_[2]\,
      A(1) => \sumY_reg_n_0_[1]\,
      A(0) => \sumY_reg_n_0_[0]\,
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => \NLW_termI0__0_ACOUT_UNCONNECTED\(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17) => sumX(22),
      B(16) => sumX(22),
      B(15) => sumX(22),
      B(14) => sumX(22),
      B(13) => sumX(22),
      B(12) => sumX(22),
      B(11) => sumX(22),
      B(10) => sumX(22),
      B(9) => sumX(22),
      B(8) => sumX(22),
      B(7) => sumX(22),
      B(6) => sumX(22),
      B(5 downto 0) => sumX(22 downto 17),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => \NLW_termI0__0_BCOUT_UNCONNECTED\(17 downto 0),
      C(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      CARRYCASCIN => '0',
      CARRYCASCOUT => \NLW_termI0__0_CARRYCASCOUT_UNCONNECTED\,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => \NLW_termI0__0_CARRYOUT_UNCONNECTED\(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(26 downto 0) => B"000000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => \NLW_termI0__0_MULTSIGNOUT_UNCONNECTED\,
      OPMODE(8 downto 0) => B"001010101",
      OVERFLOW => \NLW_termI0__0_OVERFLOW_UNCONNECTED\,
      P(47 downto 29) => \NLW_termI0__0_P_UNCONNECTED\(47 downto 29),
      P(28) => \termI0__0_n_77\,
      P(27) => \termI0__0_n_78\,
      P(26) => \termI0__0_n_79\,
      P(25) => \termI0__0_n_80\,
      P(24) => \termI0__0_n_81\,
      P(23) => \termI0__0_n_82\,
      P(22) => \termI0__0_n_83\,
      P(21) => \termI0__0_n_84\,
      P(20) => \termI0__0_n_85\,
      P(19) => \termI0__0_n_86\,
      P(18) => \termI0__0_n_87\,
      P(17) => \termI0__0_n_88\,
      P(16) => \termI0__0_n_89\,
      P(15) => \termI0__0_n_90\,
      P(14) => \termI0__0_n_91\,
      P(13) => \termI0__0_n_92\,
      P(12) => \termI0__0_n_93\,
      P(11) => \termI0__0_n_94\,
      P(10) => \termI0__0_n_95\,
      P(9) => \termI0__0_n_96\,
      P(8) => \termI0__0_n_97\,
      P(7) => \termI0__0_n_98\,
      P(6) => \termI0__0_n_99\,
      P(5) => \termI0__0_n_100\,
      P(4) => \termI0__0_n_101\,
      P(3) => \termI0__0_n_102\,
      P(2) => \termI0__0_n_103\,
      P(1) => \termI0__0_n_104\,
      P(0) => \termI0__0_n_105\,
      PATTERNBDETECT => \NLW_termI0__0_PATTERNBDETECT_UNCONNECTED\,
      PATTERNDETECT => \NLW_termI0__0_PATTERNDETECT_UNCONNECTED\,
      PCIN(47) => termI0_n_106,
      PCIN(46) => termI0_n_107,
      PCIN(45) => termI0_n_108,
      PCIN(44) => termI0_n_109,
      PCIN(43) => termI0_n_110,
      PCIN(42) => termI0_n_111,
      PCIN(41) => termI0_n_112,
      PCIN(40) => termI0_n_113,
      PCIN(39) => termI0_n_114,
      PCIN(38) => termI0_n_115,
      PCIN(37) => termI0_n_116,
      PCIN(36) => termI0_n_117,
      PCIN(35) => termI0_n_118,
      PCIN(34) => termI0_n_119,
      PCIN(33) => termI0_n_120,
      PCIN(32) => termI0_n_121,
      PCIN(31) => termI0_n_122,
      PCIN(30) => termI0_n_123,
      PCIN(29) => termI0_n_124,
      PCIN(28) => termI0_n_125,
      PCIN(27) => termI0_n_126,
      PCIN(26) => termI0_n_127,
      PCIN(25) => termI0_n_128,
      PCIN(24) => termI0_n_129,
      PCIN(23) => termI0_n_130,
      PCIN(22) => termI0_n_131,
      PCIN(21) => termI0_n_132,
      PCIN(20) => termI0_n_133,
      PCIN(19) => termI0_n_134,
      PCIN(18) => termI0_n_135,
      PCIN(17) => termI0_n_136,
      PCIN(16) => termI0_n_137,
      PCIN(15) => termI0_n_138,
      PCIN(14) => termI0_n_139,
      PCIN(13) => termI0_n_140,
      PCIN(12) => termI0_n_141,
      PCIN(11) => termI0_n_142,
      PCIN(10) => termI0_n_143,
      PCIN(9) => termI0_n_144,
      PCIN(8) => termI0_n_145,
      PCIN(7) => termI0_n_146,
      PCIN(6) => termI0_n_147,
      PCIN(5) => termI0_n_148,
      PCIN(4) => termI0_n_149,
      PCIN(3) => termI0_n_150,
      PCIN(2) => termI0_n_151,
      PCIN(1) => termI0_n_152,
      PCIN(0) => termI0_n_153,
      PCOUT(47 downto 0) => \NLW_termI0__0_PCOUT_UNCONNECTED\(47 downto 0),
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => \NLW_termI0__0_UNDERFLOW_UNCONNECTED\,
      XOROUT(7 downto 0) => \NLW_termI0__0_XOROUT_UNCONNECTED\(7 downto 0)
    );
termII0: unisim.vcomponents.DSP48E2
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AMULTSEL => "A",
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      AUTORESET_PRIORITY => "RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BMULTSEL => "B",
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREADDINSEL => "A",
      PREG => 0,
      RND => X"000000000000",
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48",
      USE_WIDEXOR => "FALSE",
      XORSIMD => "XOR24_48_96"
    )
        port map (
      A(29) => sumXY(22),
      A(28) => sumXY(22),
      A(27) => sumXY(22),
      A(26) => sumXY(22),
      A(25) => sumXY(22),
      A(24) => sumXY(22),
      A(23) => sumXY(22),
      A(22 downto 0) => sumXY(22 downto 0),
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => NLW_termII0_ACOUT_UNCONNECTED(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17) => '0',
      B(16 downto 0) => sumXY(16 downto 0),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => NLW_termII0_BCOUT_UNCONNECTED(17 downto 0),
      C(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      CARRYCASCIN => '0',
      CARRYCASCOUT => NLW_termII0_CARRYCASCOUT_UNCONNECTED,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => NLW_termII0_CARRYOUT_UNCONNECTED(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(26 downto 0) => B"000000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => NLW_termII0_MULTSIGNOUT_UNCONNECTED,
      OPMODE(8 downto 0) => B"000000101",
      OVERFLOW => NLW_termII0_OVERFLOW_UNCONNECTED,
      P(47) => termII0_n_58,
      P(46) => termII0_n_59,
      P(45) => termII0_n_60,
      P(44) => termII0_n_61,
      P(43) => termII0_n_62,
      P(42) => termII0_n_63,
      P(41) => termII0_n_64,
      P(40) => termII0_n_65,
      P(39) => termII0_n_66,
      P(38) => termII0_n_67,
      P(37) => termII0_n_68,
      P(36) => termII0_n_69,
      P(35) => termII0_n_70,
      P(34) => termII0_n_71,
      P(33) => termII0_n_72,
      P(32) => termII0_n_73,
      P(31) => termII0_n_74,
      P(30) => termII0_n_75,
      P(29) => termII0_n_76,
      P(28) => termII0_n_77,
      P(27) => termII0_n_78,
      P(26) => termII0_n_79,
      P(25) => termII0_n_80,
      P(24) => termII0_n_81,
      P(23) => termII0_n_82,
      P(22) => termII0_n_83,
      P(21) => termII0_n_84,
      P(20) => termII0_n_85,
      P(19) => termII0_n_86,
      P(18) => termII0_n_87,
      P(17) => termII0_n_88,
      P(16) => termII0_n_89,
      P(15) => termII0_n_90,
      P(14) => termII0_n_91,
      P(13) => termII0_n_92,
      P(12) => termII0_n_93,
      P(11) => termII0_n_94,
      P(10) => termII0_n_95,
      P(9) => termII0_n_96,
      P(8) => termII0_n_97,
      P(7) => termII0_n_98,
      P(6) => termII0_n_99,
      P(5) => termII0_n_100,
      P(4) => termII0_n_101,
      P(3) => termII0_n_102,
      P(2) => termII0_n_103,
      P(1) => termII0_n_104,
      P(0) => termII0_n_105,
      PATTERNBDETECT => NLW_termII0_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_termII0_PATTERNDETECT_UNCONNECTED,
      PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      PCOUT(47) => termII0_n_106,
      PCOUT(46) => termII0_n_107,
      PCOUT(45) => termII0_n_108,
      PCOUT(44) => termII0_n_109,
      PCOUT(43) => termII0_n_110,
      PCOUT(42) => termII0_n_111,
      PCOUT(41) => termII0_n_112,
      PCOUT(40) => termII0_n_113,
      PCOUT(39) => termII0_n_114,
      PCOUT(38) => termII0_n_115,
      PCOUT(37) => termII0_n_116,
      PCOUT(36) => termII0_n_117,
      PCOUT(35) => termII0_n_118,
      PCOUT(34) => termII0_n_119,
      PCOUT(33) => termII0_n_120,
      PCOUT(32) => termII0_n_121,
      PCOUT(31) => termII0_n_122,
      PCOUT(30) => termII0_n_123,
      PCOUT(29) => termII0_n_124,
      PCOUT(28) => termII0_n_125,
      PCOUT(27) => termII0_n_126,
      PCOUT(26) => termII0_n_127,
      PCOUT(25) => termII0_n_128,
      PCOUT(24) => termII0_n_129,
      PCOUT(23) => termII0_n_130,
      PCOUT(22) => termII0_n_131,
      PCOUT(21) => termII0_n_132,
      PCOUT(20) => termII0_n_133,
      PCOUT(19) => termII0_n_134,
      PCOUT(18) => termII0_n_135,
      PCOUT(17) => termII0_n_136,
      PCOUT(16) => termII0_n_137,
      PCOUT(15) => termII0_n_138,
      PCOUT(14) => termII0_n_139,
      PCOUT(13) => termII0_n_140,
      PCOUT(12) => termII0_n_141,
      PCOUT(11) => termII0_n_142,
      PCOUT(10) => termII0_n_143,
      PCOUT(9) => termII0_n_144,
      PCOUT(8) => termII0_n_145,
      PCOUT(7) => termII0_n_146,
      PCOUT(6) => termII0_n_147,
      PCOUT(5) => termII0_n_148,
      PCOUT(4) => termII0_n_149,
      PCOUT(3) => termII0_n_150,
      PCOUT(2) => termII0_n_151,
      PCOUT(1) => termII0_n_152,
      PCOUT(0) => termII0_n_153,
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => NLW_termII0_UNDERFLOW_UNCONNECTED,
      XOROUT(7 downto 0) => NLW_termII0_XOROUT_UNCONNECTED(7 downto 0)
    );
\termII0__0\: unisim.vcomponents.DSP48E2
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AMULTSEL => "A",
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      AUTORESET_PRIORITY => "RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BMULTSEL => "B",
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREADDINSEL => "A",
      PREG => 0,
      RND => X"000000000000",
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48",
      USE_WIDEXOR => "FALSE",
      XORSIMD => "XOR24_48_96"
    )
        port map (
      A(29) => sumXY(22),
      A(28) => sumXY(22),
      A(27) => sumXY(22),
      A(26) => sumXY(22),
      A(25) => sumXY(22),
      A(24) => sumXY(22),
      A(23) => sumXY(22),
      A(22 downto 0) => sumXY(22 downto 0),
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => \NLW_termII0__0_ACOUT_UNCONNECTED\(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17) => sumXY(22),
      B(16) => sumXY(22),
      B(15) => sumXY(22),
      B(14) => sumXY(22),
      B(13) => sumXY(22),
      B(12) => sumXY(22),
      B(11) => sumXY(22),
      B(10) => sumXY(22),
      B(9) => sumXY(22),
      B(8) => sumXY(22),
      B(7) => sumXY(22),
      B(6) => sumXY(22),
      B(5 downto 0) => sumXY(22 downto 17),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => \NLW_termII0__0_BCOUT_UNCONNECTED\(17 downto 0),
      C(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      CARRYCASCIN => '0',
      CARRYCASCOUT => \NLW_termII0__0_CARRYCASCOUT_UNCONNECTED\,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => \NLW_termII0__0_CARRYOUT_UNCONNECTED\(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(26 downto 0) => B"000000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => \NLW_termII0__0_MULTSIGNOUT_UNCONNECTED\,
      OPMODE(8 downto 0) => B"001010101",
      OVERFLOW => \NLW_termII0__0_OVERFLOW_UNCONNECTED\,
      P(47 downto 29) => \NLW_termII0__0_P_UNCONNECTED\(47 downto 29),
      P(28) => \termII0__0_n_77\,
      P(27) => \termII0__0_n_78\,
      P(26) => \termII0__0_n_79\,
      P(25) => \termII0__0_n_80\,
      P(24) => \termII0__0_n_81\,
      P(23) => \termII0__0_n_82\,
      P(22) => \termII0__0_n_83\,
      P(21) => \termII0__0_n_84\,
      P(20) => \termII0__0_n_85\,
      P(19) => \termII0__0_n_86\,
      P(18) => \termII0__0_n_87\,
      P(17) => \termII0__0_n_88\,
      P(16) => \termII0__0_n_89\,
      P(15) => \termII0__0_n_90\,
      P(14) => \termII0__0_n_91\,
      P(13) => \termII0__0_n_92\,
      P(12) => \termII0__0_n_93\,
      P(11) => \termII0__0_n_94\,
      P(10) => \termII0__0_n_95\,
      P(9) => \termII0__0_n_96\,
      P(8) => \termII0__0_n_97\,
      P(7) => \termII0__0_n_98\,
      P(6) => \termII0__0_n_99\,
      P(5) => \termII0__0_n_100\,
      P(4) => \termII0__0_n_101\,
      P(3) => \termII0__0_n_102\,
      P(2) => \termII0__0_n_103\,
      P(1) => \termII0__0_n_104\,
      P(0) => \termII0__0_n_105\,
      PATTERNBDETECT => \NLW_termII0__0_PATTERNBDETECT_UNCONNECTED\,
      PATTERNDETECT => \NLW_termII0__0_PATTERNDETECT_UNCONNECTED\,
      PCIN(47) => termII0_n_106,
      PCIN(46) => termII0_n_107,
      PCIN(45) => termII0_n_108,
      PCIN(44) => termII0_n_109,
      PCIN(43) => termII0_n_110,
      PCIN(42) => termII0_n_111,
      PCIN(41) => termII0_n_112,
      PCIN(40) => termII0_n_113,
      PCIN(39) => termII0_n_114,
      PCIN(38) => termII0_n_115,
      PCIN(37) => termII0_n_116,
      PCIN(36) => termII0_n_117,
      PCIN(35) => termII0_n_118,
      PCIN(34) => termII0_n_119,
      PCIN(33) => termII0_n_120,
      PCIN(32) => termII0_n_121,
      PCIN(31) => termII0_n_122,
      PCIN(30) => termII0_n_123,
      PCIN(29) => termII0_n_124,
      PCIN(28) => termII0_n_125,
      PCIN(27) => termII0_n_126,
      PCIN(26) => termII0_n_127,
      PCIN(25) => termII0_n_128,
      PCIN(24) => termII0_n_129,
      PCIN(23) => termII0_n_130,
      PCIN(22) => termII0_n_131,
      PCIN(21) => termII0_n_132,
      PCIN(20) => termII0_n_133,
      PCIN(19) => termII0_n_134,
      PCIN(18) => termII0_n_135,
      PCIN(17) => termII0_n_136,
      PCIN(16) => termII0_n_137,
      PCIN(15) => termII0_n_138,
      PCIN(14) => termII0_n_139,
      PCIN(13) => termII0_n_140,
      PCIN(12) => termII0_n_141,
      PCIN(11) => termII0_n_142,
      PCIN(10) => termII0_n_143,
      PCIN(9) => termII0_n_144,
      PCIN(8) => termII0_n_145,
      PCIN(7) => termII0_n_146,
      PCIN(6) => termII0_n_147,
      PCIN(5) => termII0_n_148,
      PCIN(4) => termII0_n_149,
      PCIN(3) => termII0_n_150,
      PCIN(2) => termII0_n_151,
      PCIN(1) => termII0_n_152,
      PCIN(0) => termII0_n_153,
      PCOUT(47 downto 0) => \NLW_termII0__0_PCOUT_UNCONNECTED\(47 downto 0),
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => \NLW_termII0__0_UNDERFLOW_UNCONNECTED\,
      XOROUT(7 downto 0) => \NLW_termII0__0_XOROUT_UNCONNECTED\(7 downto 0)
    );
termIII0: unisim.vcomponents.DSP48E2
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AMULTSEL => "A",
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      AUTORESET_PRIORITY => "RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BMULTSEL => "B",
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREADDINSEL => "A",
      PREG => 0,
      RND => X"000000000000",
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48",
      USE_WIDEXOR => "FALSE",
      XORSIMD => "XOR24_48_96"
    )
        port map (
      A(29) => sumIII(23),
      A(28) => sumIII(23),
      A(27) => sumIII(23),
      A(26) => sumIII(23),
      A(25) => sumIII(23),
      A(24) => sumIII(23),
      A(23 downto 0) => sumIII(23 downto 0),
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => NLW_termIII0_ACOUT_UNCONNECTED(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17) => '0',
      B(16 downto 0) => sumIII(16 downto 0),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => NLW_termIII0_BCOUT_UNCONNECTED(17 downto 0),
      C(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      CARRYCASCIN => '0',
      CARRYCASCOUT => NLW_termIII0_CARRYCASCOUT_UNCONNECTED,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => NLW_termIII0_CARRYOUT_UNCONNECTED(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(26 downto 0) => B"000000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => NLW_termIII0_MULTSIGNOUT_UNCONNECTED,
      OPMODE(8 downto 0) => B"000000101",
      OVERFLOW => NLW_termIII0_OVERFLOW_UNCONNECTED,
      P(47) => termIII0_n_58,
      P(46) => termIII0_n_59,
      P(45) => termIII0_n_60,
      P(44) => termIII0_n_61,
      P(43) => termIII0_n_62,
      P(42) => termIII0_n_63,
      P(41) => termIII0_n_64,
      P(40) => termIII0_n_65,
      P(39) => termIII0_n_66,
      P(38) => termIII0_n_67,
      P(37) => termIII0_n_68,
      P(36) => termIII0_n_69,
      P(35) => termIII0_n_70,
      P(34) => termIII0_n_71,
      P(33) => termIII0_n_72,
      P(32) => termIII0_n_73,
      P(31) => termIII0_n_74,
      P(30) => termIII0_n_75,
      P(29) => termIII0_n_76,
      P(28) => termIII0_n_77,
      P(27) => termIII0_n_78,
      P(26) => termIII0_n_79,
      P(25) => termIII0_n_80,
      P(24) => termIII0_n_81,
      P(23) => termIII0_n_82,
      P(22) => termIII0_n_83,
      P(21) => termIII0_n_84,
      P(20) => termIII0_n_85,
      P(19) => termIII0_n_86,
      P(18) => termIII0_n_87,
      P(17) => termIII0_n_88,
      P(16) => termIII0_n_89,
      P(15) => termIII0_n_90,
      P(14) => termIII0_n_91,
      P(13) => termIII0_n_92,
      P(12) => termIII0_n_93,
      P(11) => termIII0_n_94,
      P(10) => termIII0_n_95,
      P(9) => termIII0_n_96,
      P(8) => termIII0_n_97,
      P(7) => termIII0_n_98,
      P(6) => termIII0_n_99,
      P(5) => termIII0_n_100,
      P(4) => termIII0_n_101,
      P(3) => termIII0_n_102,
      P(2) => termIII0_n_103,
      P(1) => termIII0_n_104,
      P(0) => termIII0_n_105,
      PATTERNBDETECT => NLW_termIII0_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_termIII0_PATTERNDETECT_UNCONNECTED,
      PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      PCOUT(47) => termIII0_n_106,
      PCOUT(46) => termIII0_n_107,
      PCOUT(45) => termIII0_n_108,
      PCOUT(44) => termIII0_n_109,
      PCOUT(43) => termIII0_n_110,
      PCOUT(42) => termIII0_n_111,
      PCOUT(41) => termIII0_n_112,
      PCOUT(40) => termIII0_n_113,
      PCOUT(39) => termIII0_n_114,
      PCOUT(38) => termIII0_n_115,
      PCOUT(37) => termIII0_n_116,
      PCOUT(36) => termIII0_n_117,
      PCOUT(35) => termIII0_n_118,
      PCOUT(34) => termIII0_n_119,
      PCOUT(33) => termIII0_n_120,
      PCOUT(32) => termIII0_n_121,
      PCOUT(31) => termIII0_n_122,
      PCOUT(30) => termIII0_n_123,
      PCOUT(29) => termIII0_n_124,
      PCOUT(28) => termIII0_n_125,
      PCOUT(27) => termIII0_n_126,
      PCOUT(26) => termIII0_n_127,
      PCOUT(25) => termIII0_n_128,
      PCOUT(24) => termIII0_n_129,
      PCOUT(23) => termIII0_n_130,
      PCOUT(22) => termIII0_n_131,
      PCOUT(21) => termIII0_n_132,
      PCOUT(20) => termIII0_n_133,
      PCOUT(19) => termIII0_n_134,
      PCOUT(18) => termIII0_n_135,
      PCOUT(17) => termIII0_n_136,
      PCOUT(16) => termIII0_n_137,
      PCOUT(15) => termIII0_n_138,
      PCOUT(14) => termIII0_n_139,
      PCOUT(13) => termIII0_n_140,
      PCOUT(12) => termIII0_n_141,
      PCOUT(11) => termIII0_n_142,
      PCOUT(10) => termIII0_n_143,
      PCOUT(9) => termIII0_n_144,
      PCOUT(8) => termIII0_n_145,
      PCOUT(7) => termIII0_n_146,
      PCOUT(6) => termIII0_n_147,
      PCOUT(5) => termIII0_n_148,
      PCOUT(4) => termIII0_n_149,
      PCOUT(3) => termIII0_n_150,
      PCOUT(2) => termIII0_n_151,
      PCOUT(1) => termIII0_n_152,
      PCOUT(0) => termIII0_n_153,
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => NLW_termIII0_UNDERFLOW_UNCONNECTED,
      XOROUT(7 downto 0) => NLW_termIII0_XOROUT_UNCONNECTED(7 downto 0)
    );
\termIII0__0\: unisim.vcomponents.DSP48E2
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AMULTSEL => "A",
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      AUTORESET_PRIORITY => "RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BMULTSEL => "B",
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREADDINSEL => "A",
      PREG => 0,
      RND => X"000000000000",
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48",
      USE_WIDEXOR => "FALSE",
      XORSIMD => "XOR24_48_96"
    )
        port map (
      A(29) => sumIII(23),
      A(28) => sumIII(23),
      A(27) => sumIII(23),
      A(26) => sumIII(23),
      A(25) => sumIII(23),
      A(24) => sumIII(23),
      A(23 downto 0) => sumIII(23 downto 0),
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => \NLW_termIII0__0_ACOUT_UNCONNECTED\(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17) => sumIII(23),
      B(16) => sumIII(23),
      B(15) => sumIII(23),
      B(14) => sumIII(23),
      B(13) => sumIII(23),
      B(12) => sumIII(23),
      B(11) => sumIII(23),
      B(10) => sumIII(23),
      B(9) => sumIII(23),
      B(8) => sumIII(23),
      B(7) => sumIII(23),
      B(6 downto 0) => sumIII(23 downto 17),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => \NLW_termIII0__0_BCOUT_UNCONNECTED\(17 downto 0),
      C(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      CARRYCASCIN => '0',
      CARRYCASCOUT => \NLW_termIII0__0_CARRYCASCOUT_UNCONNECTED\,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => \NLW_termIII0__0_CARRYOUT_UNCONNECTED\(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(26 downto 0) => B"000000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => \NLW_termIII0__0_MULTSIGNOUT_UNCONNECTED\,
      OPMODE(8 downto 0) => B"001010101",
      OVERFLOW => \NLW_termIII0__0_OVERFLOW_UNCONNECTED\,
      P(47 downto 31) => \NLW_termIII0__0_P_UNCONNECTED\(47 downto 31),
      P(30) => \termIII0__0_n_75\,
      P(29) => \termIII0__0_n_76\,
      P(28) => \termIII0__0_n_77\,
      P(27) => \termIII0__0_n_78\,
      P(26) => \termIII0__0_n_79\,
      P(25) => \termIII0__0_n_80\,
      P(24) => \termIII0__0_n_81\,
      P(23) => \termIII0__0_n_82\,
      P(22) => \termIII0__0_n_83\,
      P(21) => \termIII0__0_n_84\,
      P(20) => \termIII0__0_n_85\,
      P(19) => \termIII0__0_n_86\,
      P(18) => \termIII0__0_n_87\,
      P(17) => \termIII0__0_n_88\,
      P(16) => \termIII0__0_n_89\,
      P(15) => \termIII0__0_n_90\,
      P(14) => \termIII0__0_n_91\,
      P(13) => \termIII0__0_n_92\,
      P(12) => \termIII0__0_n_93\,
      P(11) => \termIII0__0_n_94\,
      P(10) => \termIII0__0_n_95\,
      P(9) => \termIII0__0_n_96\,
      P(8) => \termIII0__0_n_97\,
      P(7) => \termIII0__0_n_98\,
      P(6) => \termIII0__0_n_99\,
      P(5) => \termIII0__0_n_100\,
      P(4) => \termIII0__0_n_101\,
      P(3) => \termIII0__0_n_102\,
      P(2) => \termIII0__0_n_103\,
      P(1) => \termIII0__0_n_104\,
      P(0) => \termIII0__0_n_105\,
      PATTERNBDETECT => \NLW_termIII0__0_PATTERNBDETECT_UNCONNECTED\,
      PATTERNDETECT => \NLW_termIII0__0_PATTERNDETECT_UNCONNECTED\,
      PCIN(47) => termIII0_n_106,
      PCIN(46) => termIII0_n_107,
      PCIN(45) => termIII0_n_108,
      PCIN(44) => termIII0_n_109,
      PCIN(43) => termIII0_n_110,
      PCIN(42) => termIII0_n_111,
      PCIN(41) => termIII0_n_112,
      PCIN(40) => termIII0_n_113,
      PCIN(39) => termIII0_n_114,
      PCIN(38) => termIII0_n_115,
      PCIN(37) => termIII0_n_116,
      PCIN(36) => termIII0_n_117,
      PCIN(35) => termIII0_n_118,
      PCIN(34) => termIII0_n_119,
      PCIN(33) => termIII0_n_120,
      PCIN(32) => termIII0_n_121,
      PCIN(31) => termIII0_n_122,
      PCIN(30) => termIII0_n_123,
      PCIN(29) => termIII0_n_124,
      PCIN(28) => termIII0_n_125,
      PCIN(27) => termIII0_n_126,
      PCIN(26) => termIII0_n_127,
      PCIN(25) => termIII0_n_128,
      PCIN(24) => termIII0_n_129,
      PCIN(23) => termIII0_n_130,
      PCIN(22) => termIII0_n_131,
      PCIN(21) => termIII0_n_132,
      PCIN(20) => termIII0_n_133,
      PCIN(19) => termIII0_n_134,
      PCIN(18) => termIII0_n_135,
      PCIN(17) => termIII0_n_136,
      PCIN(16) => termIII0_n_137,
      PCIN(15) => termIII0_n_138,
      PCIN(14) => termIII0_n_139,
      PCIN(13) => termIII0_n_140,
      PCIN(12) => termIII0_n_141,
      PCIN(11) => termIII0_n_142,
      PCIN(10) => termIII0_n_143,
      PCIN(9) => termIII0_n_144,
      PCIN(8) => termIII0_n_145,
      PCIN(7) => termIII0_n_146,
      PCIN(6) => termIII0_n_147,
      PCIN(5) => termIII0_n_148,
      PCIN(4) => termIII0_n_149,
      PCIN(3) => termIII0_n_150,
      PCIN(2) => termIII0_n_151,
      PCIN(1) => termIII0_n_152,
      PCIN(0) => termIII0_n_153,
      PCOUT(47 downto 0) => \NLW_termIII0__0_PCOUT_UNCONNECTED\(47 downto 0),
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => \NLW_termIII0__0_UNDERFLOW_UNCONNECTED\,
      XOROUT(7 downto 0) => \NLW_termIII0__0_XOROUT_UNCONNECTED\(7 downto 0)
    );
\termIII[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIII0_n_105,
      O => \termIII[0]_i_1_n_0\
    );
\termIII[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => termIII0_n_95,
      O => \termIII[10]_i_1_n_0\
    );
\termIII[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => termIII0_n_94,
      O => \termIII[11]_i_1_n_0\
    );
\termIII[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => termIII0_n_93,
      O => \termIII[12]_i_1_n_0\
    );
\termIII[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => termIII0_n_92,
      O => \termIII[13]_i_1_n_0\
    );
\termIII[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => termIII0_n_91,
      O => \termIII[14]_i_1_n_0\
    );
\termIII[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => termIII0_n_90,
      O => \termIII[15]_i_1_n_0\
    );
\termIII[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => termIII0_n_89,
      O => \termIII[16]_i_1_n_0\
    );
\termIII[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_105\,
      O => \termIII[17]_i_1_n_0\
    );
\termIII[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_104\,
      O => \termIII[18]_i_1_n_0\
    );
\termIII[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_103\,
      O => \termIII[19]_i_1_n_0\
    );
\termIII[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIII0_n_104,
      O => \termIII[1]_i_1_n_0\
    );
\termIII[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_102\,
      O => \termIII[20]_i_1_n_0\
    );
\termIII[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_101\,
      O => \termIII[21]_i_1_n_0\
    );
\termIII[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_100\,
      O => \termIII[22]_i_1_n_0\
    );
\termIII[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_99\,
      O => \termIII[23]_i_1_n_0\
    );
\termIII[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_98\,
      O => \termIII[24]_i_1_n_0\
    );
\termIII[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_97\,
      O => \termIII[25]_i_1_n_0\
    );
\termIII[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_96\,
      O => \termIII[26]_i_1_n_0\
    );
\termIII[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_95\,
      O => \termIII[27]_i_1_n_0\
    );
\termIII[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_94\,
      O => \termIII[28]_i_1_n_0\
    );
\termIII[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_93\,
      O => \termIII[29]_i_1_n_0\
    );
\termIII[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIII0_n_103,
      O => \termIII[2]_i_1_n_0\
    );
\termIII[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_92\,
      O => \termIII[30]_i_1_n_0\
    );
\termIII[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_91\,
      O => \termIII[31]_i_1_n_0\
    );
\termIII[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_90\,
      O => \termIII[32]_i_1_n_0\
    );
\termIII[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_89\,
      O => \termIII[33]_i_1_n_0\
    );
\termIII[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_88\,
      O => \termIII[34]_i_1_n_0\
    );
\termIII[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_87\,
      O => \termIII[35]_i_1_n_0\
    );
\termIII[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_86\,
      O => \termIII[36]_i_1_n_0\
    );
\termIII[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_85\,
      O => \termIII[37]_i_1_n_0\
    );
\termIII[38]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_84\,
      O => \termIII[38]_i_1_n_0\
    );
\termIII[39]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_83\,
      O => \termIII[39]_i_1_n_0\
    );
\termIII[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIII0_n_102,
      O => \termIII[3]_i_1_n_0\
    );
\termIII[40]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_82\,
      O => \termIII[40]_i_1_n_0\
    );
\termIII[41]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_81\,
      O => \termIII[41]_i_1_n_0\
    );
\termIII[42]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_80\,
      O => \termIII[42]_i_1_n_0\
    );
\termIII[43]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_79\,
      O => \termIII[43]_i_1_n_0\
    );
\termIII[44]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_78\,
      O => \termIII[44]_i_1_n_0\
    );
\termIII[45]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_77\,
      O => \termIII[45]_i_1_n_0\
    );
\termIII[46]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_76\,
      O => \termIII[46]_i_1_n_0\
    );
\termIII[47]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termIII0__0_n_75\,
      O => \termIII[47]_i_1_n_0\
    );
\termIII[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIII0_n_101,
      O => \termIII[4]_i_1_n_0\
    );
\termIII[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIII0_n_100,
      O => \termIII[5]_i_1_n_0\
    );
\termIII[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIII0_n_99,
      O => \termIII[6]_i_1_n_0\
    );
\termIII[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIII0_n_98,
      O => \termIII[7]_i_1_n_0\
    );
\termIII[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => termIII0_n_97,
      O => \termIII[8]_i_1_n_0\
    );
\termIII[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => termIII0_n_96,
      O => \termIII[9]_i_1_n_0\
    );
\termIII_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[0]_i_1_n_0\,
      Q => termIII(0)
    );
\termIII_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[10]_i_1_n_0\,
      Q => termIII(10)
    );
\termIII_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[11]_i_1_n_0\,
      Q => termIII(11)
    );
\termIII_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[12]_i_1_n_0\,
      Q => termIII(12)
    );
\termIII_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[13]_i_1_n_0\,
      Q => termIII(13)
    );
\termIII_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[14]_i_1_n_0\,
      Q => termIII(14)
    );
\termIII_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[15]_i_1_n_0\,
      Q => termIII(15)
    );
\termIII_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[16]_i_1_n_0\,
      Q => termIII(16)
    );
\termIII_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[17]_i_1_n_0\,
      Q => termIII(17)
    );
\termIII_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[18]_i_1_n_0\,
      Q => termIII(18)
    );
\termIII_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[19]_i_1_n_0\,
      Q => termIII(19)
    );
\termIII_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[1]_i_1_n_0\,
      Q => termIII(1)
    );
\termIII_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[20]_i_1_n_0\,
      Q => termIII(20)
    );
\termIII_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[21]_i_1_n_0\,
      Q => termIII(21)
    );
\termIII_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[22]_i_1_n_0\,
      Q => termIII(22)
    );
\termIII_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[23]_i_1_n_0\,
      Q => termIII(23)
    );
\termIII_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[24]_i_1_n_0\,
      Q => termIII(24)
    );
\termIII_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[25]_i_1_n_0\,
      Q => termIII(25)
    );
\termIII_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[26]_i_1_n_0\,
      Q => termIII(26)
    );
\termIII_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[27]_i_1_n_0\,
      Q => termIII(27)
    );
\termIII_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[28]_i_1_n_0\,
      Q => termIII(28)
    );
\termIII_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[29]_i_1_n_0\,
      Q => termIII(29)
    );
\termIII_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[2]_i_1_n_0\,
      Q => termIII(2)
    );
\termIII_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[30]_i_1_n_0\,
      Q => termIII(30)
    );
\termIII_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[31]_i_1_n_0\,
      Q => termIII(31)
    );
\termIII_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[32]_i_1_n_0\,
      Q => termIII(32)
    );
\termIII_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[33]_i_1_n_0\,
      Q => termIII(33)
    );
\termIII_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[34]_i_1_n_0\,
      Q => termIII(34)
    );
\termIII_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[35]_i_1_n_0\,
      Q => termIII(35)
    );
\termIII_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[36]_i_1_n_0\,
      Q => termIII(36)
    );
\termIII_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[37]_i_1_n_0\,
      Q => termIII(37)
    );
\termIII_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[38]_i_1_n_0\,
      Q => termIII(38)
    );
\termIII_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[39]_i_1_n_0\,
      Q => termIII(39)
    );
\termIII_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[3]_i_1_n_0\,
      Q => termIII(3)
    );
\termIII_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[40]_i_1_n_0\,
      Q => termIII(40)
    );
\termIII_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[41]_i_1_n_0\,
      Q => termIII(41)
    );
\termIII_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[42]_i_1_n_0\,
      Q => termIII(42)
    );
\termIII_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[43]_i_1_n_0\,
      Q => termIII(43)
    );
\termIII_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[44]_i_1_n_0\,
      Q => termIII(44)
    );
\termIII_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[45]_i_1_n_0\,
      Q => termIII(45)
    );
\termIII_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[46]_i_1_n_0\,
      Q => termIII(46)
    );
\termIII_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[47]_i_1_n_0\,
      Q => termIII(47)
    );
\termIII_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[4]_i_1_n_0\,
      Q => termIII(4)
    );
\termIII_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[5]_i_1_n_0\,
      Q => termIII(5)
    );
\termIII_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[6]_i_1_n_0\,
      Q => termIII(6)
    );
\termIII_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[7]_i_1_n_0\,
      Q => termIII(7)
    );
\termIII_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[8]_i_1_n_0\,
      Q => termIII(8)
    );
\termIII_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIII[9]_i_1_n_0\,
      Q => termIII(9)
    );
\termIIIk[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(7),
      O => \termIIIk[0]_i_1_n_0\
    );
\termIIIk[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(17),
      O => \termIIIk[10]_i_1_n_0\
    );
\termIIIk[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(18),
      O => \termIIIk[11]_i_1_n_0\
    );
\termIIIk[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(19),
      O => \termIIIk[12]_i_1_n_0\
    );
\termIIIk[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(20),
      O => \termIIIk[13]_i_1_n_0\
    );
\termIIIk[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(21),
      O => \termIIIk[14]_i_1_n_0\
    );
\termIIIk[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(22),
      O => \termIIIk[15]_i_1_n_0\
    );
\termIIIk[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(23),
      O => \termIIIk[16]_i_1_n_0\
    );
\termIIIk[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(24),
      O => \termIIIk[17]_i_1_n_0\
    );
\termIIIk[17]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(15),
      I1 => termIII(17),
      O => \termIIIk[17]_i_10_n_0\
    );
\termIIIk[17]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(22),
      I1 => termIII(24),
      O => \termIIIk[17]_i_3_n_0\
    );
\termIIIk[17]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(21),
      I1 => termIII(23),
      O => \termIIIk[17]_i_4_n_0\
    );
\termIIIk[17]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(20),
      I1 => termIII(22),
      O => \termIIIk[17]_i_5_n_0\
    );
\termIIIk[17]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(19),
      I1 => termIII(21),
      O => \termIIIk[17]_i_6_n_0\
    );
\termIIIk[17]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(18),
      I1 => termIII(20),
      O => \termIIIk[17]_i_7_n_0\
    );
\termIIIk[17]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(17),
      I1 => termIII(19),
      O => \termIIIk[17]_i_8_n_0\
    );
\termIIIk[17]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(16),
      I1 => termIII(18),
      O => \termIIIk[17]_i_9_n_0\
    );
\termIIIk[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(25),
      O => \termIIIk[18]_i_1_n_0\
    );
\termIIIk[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(26),
      O => \termIIIk[19]_i_1_n_0\
    );
\termIIIk[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(8),
      O => \termIIIk[1]_i_1_n_0\
    );
\termIIIk[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(6),
      I1 => termIII(8),
      O => \termIIIk[1]_i_3_n_0\
    );
\termIIIk[1]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(5),
      I1 => termIII(7),
      O => \termIIIk[1]_i_4_n_0\
    );
\termIIIk[1]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(4),
      I1 => termIII(6),
      O => \termIIIk[1]_i_5_n_0\
    );
\termIIIk[1]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(3),
      I1 => termIII(5),
      O => \termIIIk[1]_i_6_n_0\
    );
\termIIIk[1]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(2),
      I1 => termIII(4),
      O => \termIIIk[1]_i_7_n_0\
    );
\termIIIk[1]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(1),
      I1 => termIII(3),
      O => \termIIIk[1]_i_8_n_0\
    );
\termIIIk[1]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(0),
      I1 => termIII(2),
      O => \termIIIk[1]_i_9_n_0\
    );
\termIIIk[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(27),
      O => \termIIIk[20]_i_1_n_0\
    );
\termIIIk[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(28),
      O => \termIIIk[21]_i_1_n_0\
    );
\termIIIk[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(29),
      O => \termIIIk[22]_i_1_n_0\
    );
\termIIIk[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(30),
      O => \termIIIk[23]_i_1_n_0\
    );
\termIIIk[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(31),
      O => \termIIIk[24]_i_1_n_0\
    );
\termIIIk[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(32),
      O => \termIIIk[25]_i_1_n_0\
    );
\termIIIk[25]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(23),
      I1 => termIII(25),
      O => \termIIIk[25]_i_10_n_0\
    );
\termIIIk[25]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(30),
      I1 => termIII(32),
      O => \termIIIk[25]_i_3_n_0\
    );
\termIIIk[25]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(29),
      I1 => termIII(31),
      O => \termIIIk[25]_i_4_n_0\
    );
\termIIIk[25]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(28),
      I1 => termIII(30),
      O => \termIIIk[25]_i_5_n_0\
    );
\termIIIk[25]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(27),
      I1 => termIII(29),
      O => \termIIIk[25]_i_6_n_0\
    );
\termIIIk[25]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(26),
      I1 => termIII(28),
      O => \termIIIk[25]_i_7_n_0\
    );
\termIIIk[25]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(25),
      I1 => termIII(27),
      O => \termIIIk[25]_i_8_n_0\
    );
\termIIIk[25]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(24),
      I1 => termIII(26),
      O => \termIIIk[25]_i_9_n_0\
    );
\termIIIk[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(33),
      O => \termIIIk[26]_i_1_n_0\
    );
\termIIIk[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(34),
      O => \termIIIk[27]_i_1_n_0\
    );
\termIIIk[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(35),
      O => \termIIIk[28]_i_1_n_0\
    );
\termIIIk[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(36),
      O => \termIIIk[29]_i_1_n_0\
    );
\termIIIk[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(9),
      O => \termIIIk[2]_i_1_n_0\
    );
\termIIIk[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(37),
      O => \termIIIk[30]_i_1_n_0\
    );
\termIIIk[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(38),
      O => \termIIIk[31]_i_1_n_0\
    );
\termIIIk[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(39),
      O => \termIIIk[32]_i_1_n_0\
    );
\termIIIk[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(40),
      O => \termIIIk[33]_i_1_n_0\
    );
\termIIIk[33]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(31),
      I1 => termIII(33),
      O => \termIIIk[33]_i_10_n_0\
    );
\termIIIk[33]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(38),
      I1 => termIII(40),
      O => \termIIIk[33]_i_3_n_0\
    );
\termIIIk[33]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(37),
      I1 => termIII(39),
      O => \termIIIk[33]_i_4_n_0\
    );
\termIIIk[33]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(36),
      I1 => termIII(38),
      O => \termIIIk[33]_i_5_n_0\
    );
\termIIIk[33]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(35),
      I1 => termIII(37),
      O => \termIIIk[33]_i_6_n_0\
    );
\termIIIk[33]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(34),
      I1 => termIII(36),
      O => \termIIIk[33]_i_7_n_0\
    );
\termIIIk[33]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(33),
      I1 => termIII(35),
      O => \termIIIk[33]_i_8_n_0\
    );
\termIIIk[33]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(32),
      I1 => termIII(34),
      O => \termIIIk[33]_i_9_n_0\
    );
\termIIIk[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(41),
      O => \termIIIk[34]_i_1_n_0\
    );
\termIIIk[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(42),
      O => \termIIIk[35]_i_1_n_0\
    );
\termIIIk[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(43),
      O => \termIIIk[36]_i_1_n_0\
    );
\termIIIk[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(44),
      O => \termIIIk[37]_i_1_n_0\
    );
\termIIIk[38]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(45),
      O => \termIIIk[38]_i_1_n_0\
    );
\termIIIk[39]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(46),
      O => \termIIIk[39]_i_1_n_0\
    );
\termIIIk[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(10),
      O => \termIIIk[3]_i_1_n_0\
    );
\termIIIk[40]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(47),
      O => \termIIIk[40]_i_1_n_0\
    );
\termIIIk[41]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(48),
      O => \termIIIk[41]_i_1_n_0\
    );
\termIIIk[41]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(45),
      I1 => termIII(47),
      O => \termIIIk[41]_i_3_n_0\
    );
\termIIIk[41]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(44),
      I1 => termIII(46),
      O => \termIIIk[41]_i_4_n_0\
    );
\termIIIk[41]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(43),
      I1 => termIII(45),
      O => \termIIIk[41]_i_5_n_0\
    );
\termIIIk[41]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(42),
      I1 => termIII(44),
      O => \termIIIk[41]_i_6_n_0\
    );
\termIIIk[41]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(41),
      I1 => termIII(43),
      O => \termIIIk[41]_i_7_n_0\
    );
\termIIIk[41]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(40),
      I1 => termIII(42),
      O => \termIIIk[41]_i_8_n_0\
    );
\termIIIk[41]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(39),
      I1 => termIII(41),
      O => \termIIIk[41]_i_9_n_0\
    );
\termIIIk[42]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(49),
      O => \termIIIk[42]_i_1_n_0\
    );
\termIIIk[43]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__16_n_0\,
      I1 => termIIIk0(50),
      O => \termIIIk[43]_i_1_n_0\
    );
\termIIIk[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(11),
      O => \termIIIk[4]_i_1_n_0\
    );
\termIIIk[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(12),
      O => \termIIIk[5]_i_1_n_0\
    );
\termIIIk[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(13),
      O => \termIIIk[6]_i_1_n_0\
    );
\termIIIk[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(14),
      O => \termIIIk[7]_i_1_n_0\
    );
\termIIIk[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(15),
      O => \termIIIk[8]_i_1_n_0\
    );
\termIIIk[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__15_n_0\,
      I1 => termIIIk0(16),
      O => \termIIIk[9]_i_1_n_0\
    );
\termIIIk[9]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(7),
      I1 => termIII(9),
      O => \termIIIk[9]_i_10_n_0\
    );
\termIIIk[9]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(14),
      I1 => termIII(16),
      O => \termIIIk[9]_i_3_n_0\
    );
\termIIIk[9]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(13),
      I1 => termIII(15),
      O => \termIIIk[9]_i_4_n_0\
    );
\termIIIk[9]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(12),
      I1 => termIII(14),
      O => \termIIIk[9]_i_5_n_0\
    );
\termIIIk[9]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(11),
      I1 => termIII(13),
      O => \termIIIk[9]_i_6_n_0\
    );
\termIIIk[9]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(10),
      I1 => termIII(12),
      O => \termIIIk[9]_i_7_n_0\
    );
\termIIIk[9]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(9),
      I1 => termIII(11),
      O => \termIIIk[9]_i_8_n_0\
    );
\termIIIk[9]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => termIII(8),
      I1 => termIII(10),
      O => \termIIIk[9]_i_9_n_0\
    );
\termIIIk_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[0]_i_1_n_0\,
      Q => termIIIk(0)
    );
\termIIIk_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[10]_i_1_n_0\,
      Q => termIIIk(10)
    );
\termIIIk_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[11]_i_1_n_0\,
      Q => termIIIk(11)
    );
\termIIIk_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[12]_i_1_n_0\,
      Q => termIIIk(12)
    );
\termIIIk_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[13]_i_1_n_0\,
      Q => termIIIk(13)
    );
\termIIIk_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[14]_i_1_n_0\,
      Q => termIIIk(14)
    );
\termIIIk_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[15]_i_1_n_0\,
      Q => termIIIk(15)
    );
\termIIIk_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[16]_i_1_n_0\,
      Q => termIIIk(16)
    );
\termIIIk_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[17]_i_1_n_0\,
      Q => termIIIk(17)
    );
\termIIIk_reg[17]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \termIIIk_reg[9]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \termIIIk_reg[17]_i_2_n_0\,
      CO(6) => \termIIIk_reg[17]_i_2_n_1\,
      CO(5) => \termIIIk_reg[17]_i_2_n_2\,
      CO(4) => \termIIIk_reg[17]_i_2_n_3\,
      CO(3) => \termIIIk_reg[17]_i_2_n_4\,
      CO(2) => \termIIIk_reg[17]_i_2_n_5\,
      CO(1) => \termIIIk_reg[17]_i_2_n_6\,
      CO(0) => \termIIIk_reg[17]_i_2_n_7\,
      DI(7 downto 0) => termIII(22 downto 15),
      O(7 downto 0) => termIIIk0(24 downto 17),
      S(7) => \termIIIk[17]_i_3_n_0\,
      S(6) => \termIIIk[17]_i_4_n_0\,
      S(5) => \termIIIk[17]_i_5_n_0\,
      S(4) => \termIIIk[17]_i_6_n_0\,
      S(3) => \termIIIk[17]_i_7_n_0\,
      S(2) => \termIIIk[17]_i_8_n_0\,
      S(1) => \termIIIk[17]_i_9_n_0\,
      S(0) => \termIIIk[17]_i_10_n_0\
    );
\termIIIk_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[18]_i_1_n_0\,
      Q => termIIIk(18)
    );
\termIIIk_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[19]_i_1_n_0\,
      Q => termIIIk(19)
    );
\termIIIk_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[1]_i_1_n_0\,
      Q => termIIIk(1)
    );
\termIIIk_reg[1]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \termIIIk_reg[1]_i_2_n_0\,
      CO(6) => \termIIIk_reg[1]_i_2_n_1\,
      CO(5) => \termIIIk_reg[1]_i_2_n_2\,
      CO(4) => \termIIIk_reg[1]_i_2_n_3\,
      CO(3) => \termIIIk_reg[1]_i_2_n_4\,
      CO(2) => \termIIIk_reg[1]_i_2_n_5\,
      CO(1) => \termIIIk_reg[1]_i_2_n_6\,
      CO(0) => \termIIIk_reg[1]_i_2_n_7\,
      DI(7 downto 1) => termIII(6 downto 0),
      DI(0) => '0',
      O(7 downto 6) => termIIIk0(8 downto 7),
      O(5 downto 0) => \NLW_termIIIk_reg[1]_i_2_O_UNCONNECTED\(5 downto 0),
      S(7) => \termIIIk[1]_i_3_n_0\,
      S(6) => \termIIIk[1]_i_4_n_0\,
      S(5) => \termIIIk[1]_i_5_n_0\,
      S(4) => \termIIIk[1]_i_6_n_0\,
      S(3) => \termIIIk[1]_i_7_n_0\,
      S(2) => \termIIIk[1]_i_8_n_0\,
      S(1) => \termIIIk[1]_i_9_n_0\,
      S(0) => termIII(1)
    );
\termIIIk_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[20]_i_1_n_0\,
      Q => termIIIk(20)
    );
\termIIIk_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[21]_i_1_n_0\,
      Q => termIIIk(21)
    );
\termIIIk_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[22]_i_1_n_0\,
      Q => termIIIk(22)
    );
\termIIIk_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[23]_i_1_n_0\,
      Q => termIIIk(23)
    );
\termIIIk_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[24]_i_1_n_0\,
      Q => termIIIk(24)
    );
\termIIIk_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[25]_i_1_n_0\,
      Q => termIIIk(25)
    );
\termIIIk_reg[25]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \termIIIk_reg[17]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \termIIIk_reg[25]_i_2_n_0\,
      CO(6) => \termIIIk_reg[25]_i_2_n_1\,
      CO(5) => \termIIIk_reg[25]_i_2_n_2\,
      CO(4) => \termIIIk_reg[25]_i_2_n_3\,
      CO(3) => \termIIIk_reg[25]_i_2_n_4\,
      CO(2) => \termIIIk_reg[25]_i_2_n_5\,
      CO(1) => \termIIIk_reg[25]_i_2_n_6\,
      CO(0) => \termIIIk_reg[25]_i_2_n_7\,
      DI(7 downto 0) => termIII(30 downto 23),
      O(7 downto 0) => termIIIk0(32 downto 25),
      S(7) => \termIIIk[25]_i_3_n_0\,
      S(6) => \termIIIk[25]_i_4_n_0\,
      S(5) => \termIIIk[25]_i_5_n_0\,
      S(4) => \termIIIk[25]_i_6_n_0\,
      S(3) => \termIIIk[25]_i_7_n_0\,
      S(2) => \termIIIk[25]_i_8_n_0\,
      S(1) => \termIIIk[25]_i_9_n_0\,
      S(0) => \termIIIk[25]_i_10_n_0\
    );
\termIIIk_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[26]_i_1_n_0\,
      Q => termIIIk(26)
    );
\termIIIk_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[27]_i_1_n_0\,
      Q => termIIIk(27)
    );
\termIIIk_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[28]_i_1_n_0\,
      Q => termIIIk(28)
    );
\termIIIk_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[29]_i_1_n_0\,
      Q => termIIIk(29)
    );
\termIIIk_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[2]_i_1_n_0\,
      Q => termIIIk(2)
    );
\termIIIk_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[30]_i_1_n_0\,
      Q => termIIIk(30)
    );
\termIIIk_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[31]_i_1_n_0\,
      Q => termIIIk(31)
    );
\termIIIk_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[32]_i_1_n_0\,
      Q => termIIIk(32)
    );
\termIIIk_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[33]_i_1_n_0\,
      Q => termIIIk(33)
    );
\termIIIk_reg[33]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \termIIIk_reg[25]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \termIIIk_reg[33]_i_2_n_0\,
      CO(6) => \termIIIk_reg[33]_i_2_n_1\,
      CO(5) => \termIIIk_reg[33]_i_2_n_2\,
      CO(4) => \termIIIk_reg[33]_i_2_n_3\,
      CO(3) => \termIIIk_reg[33]_i_2_n_4\,
      CO(2) => \termIIIk_reg[33]_i_2_n_5\,
      CO(1) => \termIIIk_reg[33]_i_2_n_6\,
      CO(0) => \termIIIk_reg[33]_i_2_n_7\,
      DI(7 downto 0) => termIII(38 downto 31),
      O(7 downto 0) => termIIIk0(40 downto 33),
      S(7) => \termIIIk[33]_i_3_n_0\,
      S(6) => \termIIIk[33]_i_4_n_0\,
      S(5) => \termIIIk[33]_i_5_n_0\,
      S(4) => \termIIIk[33]_i_6_n_0\,
      S(3) => \termIIIk[33]_i_7_n_0\,
      S(2) => \termIIIk[33]_i_8_n_0\,
      S(1) => \termIIIk[33]_i_9_n_0\,
      S(0) => \termIIIk[33]_i_10_n_0\
    );
\termIIIk_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[34]_i_1_n_0\,
      Q => termIIIk(34)
    );
\termIIIk_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[35]_i_1_n_0\,
      Q => termIIIk(35)
    );
\termIIIk_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[36]_i_1_n_0\,
      Q => termIIIk(36)
    );
\termIIIk_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[37]_i_1_n_0\,
      Q => termIIIk(37)
    );
\termIIIk_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[38]_i_1_n_0\,
      Q => termIIIk(38)
    );
\termIIIk_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[39]_i_1_n_0\,
      Q => termIIIk(39)
    );
\termIIIk_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[3]_i_1_n_0\,
      Q => termIIIk(3)
    );
\termIIIk_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[40]_i_1_n_0\,
      Q => termIIIk(40)
    );
\termIIIk_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[41]_i_1_n_0\,
      Q => termIIIk(41)
    );
\termIIIk_reg[41]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \termIIIk_reg[33]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \termIIIk_reg[41]_i_2_n_0\,
      CO(6) => \termIIIk_reg[41]_i_2_n_1\,
      CO(5) => \termIIIk_reg[41]_i_2_n_2\,
      CO(4) => \termIIIk_reg[41]_i_2_n_3\,
      CO(3) => \termIIIk_reg[41]_i_2_n_4\,
      CO(2) => \termIIIk_reg[41]_i_2_n_5\,
      CO(1) => \termIIIk_reg[41]_i_2_n_6\,
      CO(0) => \termIIIk_reg[41]_i_2_n_7\,
      DI(7) => '0',
      DI(6 downto 0) => termIII(45 downto 39),
      O(7 downto 0) => termIIIk0(48 downto 41),
      S(7) => termIII(46),
      S(6) => \termIIIk[41]_i_3_n_0\,
      S(5) => \termIIIk[41]_i_4_n_0\,
      S(4) => \termIIIk[41]_i_5_n_0\,
      S(3) => \termIIIk[41]_i_6_n_0\,
      S(2) => \termIIIk[41]_i_7_n_0\,
      S(1) => \termIIIk[41]_i_8_n_0\,
      S(0) => \termIIIk[41]_i_9_n_0\
    );
\termIIIk_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[42]_i_1_n_0\,
      Q => termIIIk(42)
    );
\termIIIk_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[43]_i_1_n_0\,
      Q => termIIIk(43)
    );
\termIIIk_reg[43]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \termIIIk_reg[41]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 2) => \NLW_termIIIk_reg[43]_i_2_CO_UNCONNECTED\(7 downto 2),
      CO(1) => termIIIk0(50),
      CO(0) => \NLW_termIIIk_reg[43]_i_2_CO_UNCONNECTED\(0),
      DI(7 downto 0) => B"00000000",
      O(7 downto 1) => \NLW_termIIIk_reg[43]_i_2_O_UNCONNECTED\(7 downto 1),
      O(0) => termIIIk0(49),
      S(7 downto 1) => B"0000001",
      S(0) => termIII(47)
    );
\termIIIk_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[4]_i_1_n_0\,
      Q => termIIIk(4)
    );
\termIIIk_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[5]_i_1_n_0\,
      Q => termIIIk(5)
    );
\termIIIk_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[6]_i_1_n_0\,
      Q => termIIIk(6)
    );
\termIIIk_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[7]_i_1_n_0\,
      Q => termIIIk(7)
    );
\termIIIk_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[8]_i_1_n_0\,
      Q => termIIIk(8)
    );
\termIIIk_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termIIIk[9]_i_1_n_0\,
      Q => termIIIk(9)
    );
\termIIIk_reg[9]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \termIIIk_reg[1]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \termIIIk_reg[9]_i_2_n_0\,
      CO(6) => \termIIIk_reg[9]_i_2_n_1\,
      CO(5) => \termIIIk_reg[9]_i_2_n_2\,
      CO(4) => \termIIIk_reg[9]_i_2_n_3\,
      CO(3) => \termIIIk_reg[9]_i_2_n_4\,
      CO(2) => \termIIIk_reg[9]_i_2_n_5\,
      CO(1) => \termIIIk_reg[9]_i_2_n_6\,
      CO(0) => \termIIIk_reg[9]_i_2_n_7\,
      DI(7 downto 0) => termIII(14 downto 7),
      O(7 downto 0) => termIIIk0(16 downto 9),
      S(7) => \termIIIk[9]_i_3_n_0\,
      S(6) => \termIIIk[9]_i_4_n_0\,
      S(5) => \termIIIk[9]_i_5_n_0\,
      S(4) => \termIIIk[9]_i_6_n_0\,
      S(3) => \termIIIk[9]_i_7_n_0\,
      S(2) => \termIIIk[9]_i_8_n_0\,
      S(1) => \termIIIk[9]_i_9_n_0\,
      S(0) => \termIIIk[9]_i_10_n_0\
    );
\termII[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_105,
      O => \termII[0]_i_1_n_0\
    );
\termII[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_95,
      O => \termII[10]_i_1_n_0\
    );
\termII[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_94,
      O => \termII[11]_i_1_n_0\
    );
\termII[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_93,
      O => \termII[12]_i_1_n_0\
    );
\termII[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_92,
      O => \termII[13]_i_1_n_0\
    );
\termII[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_91,
      O => \termII[14]_i_1_n_0\
    );
\termII[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_90,
      O => \termII[15]_i_1_n_0\
    );
\termII[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => termII0_n_89,
      O => \termII[16]_i_1_n_0\
    );
\termII[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_105\,
      O => \termII[17]_i_1_n_0\
    );
\termII[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_104\,
      O => \termII[18]_i_1_n_0\
    );
\termII[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_103\,
      O => \termII[19]_i_1_n_0\
    );
\termII[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_104,
      O => \termII[1]_i_1_n_0\
    );
\termII[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_102\,
      O => \termII[20]_i_1_n_0\
    );
\termII[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_101\,
      O => \termII[21]_i_1_n_0\
    );
\termII[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_100\,
      O => \termII[22]_i_1_n_0\
    );
\termII[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_99\,
      O => \termII[23]_i_1_n_0\
    );
\termII[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_98\,
      O => \termII[24]_i_1_n_0\
    );
\termII[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_97\,
      O => \termII[25]_i_1_n_0\
    );
\termII[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_96\,
      O => \termII[26]_i_1_n_0\
    );
\termII[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_95\,
      O => \termII[27]_i_1_n_0\
    );
\termII[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_94\,
      O => \termII[28]_i_1_n_0\
    );
\termII[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_93\,
      O => \termII[29]_i_1_n_0\
    );
\termII[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_103,
      O => \termII[2]_i_1_n_0\
    );
\termII[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_92\,
      O => \termII[30]_i_1_n_0\
    );
\termII[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termII0__0_n_91\,
      O => \termII[31]_i_1_n_0\
    );
\termII[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII0__0_n_90\,
      O => \termII[32]_i_1_n_0\
    );
\termII[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII0__0_n_89\,
      O => \termII[33]_i_1_n_0\
    );
\termII[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII0__0_n_88\,
      O => \termII[34]_i_1_n_0\
    );
\termII[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII0__0_n_87\,
      O => \termII[35]_i_1_n_0\
    );
\termII[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII0__0_n_86\,
      O => \termII[36]_i_1_n_0\
    );
\termII[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII0__0_n_85\,
      O => \termII[37]_i_1_n_0\
    );
\termII[38]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII0__0_n_84\,
      O => \termII[38]_i_1_n_0\
    );
\termII[39]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII0__0_n_83\,
      O => \termII[39]_i_1_n_0\
    );
\termII[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_102,
      O => \termII[3]_i_1_n_0\
    );
\termII[40]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII0__0_n_82\,
      O => \termII[40]_i_1_n_0\
    );
\termII[41]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII0__0_n_81\,
      O => \termII[41]_i_1_n_0\
    );
\termII[42]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII0__0_n_80\,
      O => \termII[42]_i_1_n_0\
    );
\termII[43]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII0__0_n_79\,
      O => \termII[43]_i_1_n_0\
    );
\termII[44]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII0__0_n_78\,
      O => \termII[44]_i_1_n_0\
    );
\termII[45]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termII0__0_n_77\,
      O => \termII[45]_i_1_n_0\
    );
\termII[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_101,
      O => \termII[4]_i_1_n_0\
    );
\termII[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_100,
      O => \termII[5]_i_1_n_0\
    );
\termII[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_99,
      O => \termII[6]_i_1_n_0\
    );
\termII[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_98,
      O => \termII[7]_i_1_n_0\
    );
\termII[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_97,
      O => \termII[8]_i_1_n_0\
    );
\termII[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termII0_n_96,
      O => \termII[9]_i_1_n_0\
    );
\termII_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[0]_i_1_n_0\,
      Q => \termII_reg_n_0_[0]\
    );
\termII_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[10]_i_1_n_0\,
      Q => \termII_reg_n_0_[10]\
    );
\termII_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[11]_i_1_n_0\,
      Q => \termII_reg_n_0_[11]\
    );
\termII_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[12]_i_1_n_0\,
      Q => \termII_reg_n_0_[12]\
    );
\termII_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[13]_i_1_n_0\,
      Q => \termII_reg_n_0_[13]\
    );
\termII_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[14]_i_1_n_0\,
      Q => \termII_reg_n_0_[14]\
    );
\termII_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[15]_i_1_n_0\,
      Q => \termII_reg_n_0_[15]\
    );
\termII_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[16]_i_1_n_0\,
      Q => \termII_reg_n_0_[16]\
    );
\termII_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[17]_i_1_n_0\,
      Q => \termII_reg_n_0_[17]\
    );
\termII_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[18]_i_1_n_0\,
      Q => \termII_reg_n_0_[18]\
    );
\termII_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[19]_i_1_n_0\,
      Q => \termII_reg_n_0_[19]\
    );
\termII_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[1]_i_1_n_0\,
      Q => \termII_reg_n_0_[1]\
    );
\termII_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[20]_i_1_n_0\,
      Q => \termII_reg_n_0_[20]\
    );
\termII_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[21]_i_1_n_0\,
      Q => \termII_reg_n_0_[21]\
    );
\termII_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[22]_i_1_n_0\,
      Q => \termII_reg_n_0_[22]\
    );
\termII_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[23]_i_1_n_0\,
      Q => \termII_reg_n_0_[23]\
    );
\termII_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[24]_i_1_n_0\,
      Q => \termII_reg_n_0_[24]\
    );
\termII_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[25]_i_1_n_0\,
      Q => \termII_reg_n_0_[25]\
    );
\termII_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[26]_i_1_n_0\,
      Q => \termII_reg_n_0_[26]\
    );
\termII_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[27]_i_1_n_0\,
      Q => \termII_reg_n_0_[27]\
    );
\termII_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[28]_i_1_n_0\,
      Q => \termII_reg_n_0_[28]\
    );
\termII_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[29]_i_1_n_0\,
      Q => \termII_reg_n_0_[29]\
    );
\termII_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[2]_i_1_n_0\,
      Q => \termII_reg_n_0_[2]\
    );
\termII_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[30]_i_1_n_0\,
      Q => \termII_reg_n_0_[30]\
    );
\termII_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[31]_i_1_n_0\,
      Q => \termII_reg_n_0_[31]\
    );
\termII_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[32]_i_1_n_0\,
      Q => \termII_reg_n_0_[32]\
    );
\termII_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[33]_i_1_n_0\,
      Q => \termII_reg_n_0_[33]\
    );
\termII_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[34]_i_1_n_0\,
      Q => \termII_reg_n_0_[34]\
    );
\termII_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[35]_i_1_n_0\,
      Q => \termII_reg_n_0_[35]\
    );
\termII_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[36]_i_1_n_0\,
      Q => \termII_reg_n_0_[36]\
    );
\termII_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[37]_i_1_n_0\,
      Q => \termII_reg_n_0_[37]\
    );
\termII_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[38]_i_1_n_0\,
      Q => \termII_reg_n_0_[38]\
    );
\termII_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[39]_i_1_n_0\,
      Q => \termII_reg_n_0_[39]\
    );
\termII_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[3]_i_1_n_0\,
      Q => \termII_reg_n_0_[3]\
    );
\termII_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[40]_i_1_n_0\,
      Q => \termII_reg_n_0_[40]\
    );
\termII_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[41]_i_1_n_0\,
      Q => \termII_reg_n_0_[41]\
    );
\termII_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[42]_i_1_n_0\,
      Q => \termII_reg_n_0_[42]\
    );
\termII_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[43]_i_1_n_0\,
      Q => \termII_reg_n_0_[43]\
    );
\termII_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[44]_i_1_n_0\,
      Q => \termII_reg_n_0_[44]\
    );
\termII_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[45]_i_1_n_0\,
      Q => \termII_reg_n_0_[45]\
    );
\termII_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[4]_i_1_n_0\,
      Q => \termII_reg_n_0_[4]\
    );
\termII_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[5]_i_1_n_0\,
      Q => \termII_reg_n_0_[5]\
    );
\termII_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[6]_i_1_n_0\,
      Q => \termII_reg_n_0_[6]\
    );
\termII_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[7]_i_1_n_0\,
      Q => \termII_reg_n_0_[7]\
    );
\termII_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[8]_i_1_n_0\,
      Q => \termII_reg_n_0_[8]\
    );
\termII_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termII[9]_i_1_n_0\,
      Q => \termII_reg_n_0_[9]\
    );
\termI[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_105,
      O => \termI[0]_i_1_n_0\
    );
\termI[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_95,
      O => \termI[10]_i_1_n_0\
    );
\termI[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_94,
      O => \termI[11]_i_1_n_0\
    );
\termI[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_93,
      O => \termI[12]_i_1_n_0\
    );
\termI[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_92,
      O => \termI[13]_i_1_n_0\
    );
\termI[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_91,
      O => \termI[14]_i_1_n_0\
    );
\termI[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_90,
      O => \termI[15]_i_1_n_0\
    );
\termI[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => termI0_n_89,
      O => \termI[16]_i_1_n_0\
    );
\termI[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_105\,
      O => \termI[17]_i_1_n_0\
    );
\termI[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_104\,
      O => \termI[18]_i_1_n_0\
    );
\termI[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_103\,
      O => \termI[19]_i_1_n_0\
    );
\termI[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_104,
      O => \termI[1]_i_1_n_0\
    );
\termI[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_102\,
      O => \termI[20]_i_1_n_0\
    );
\termI[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_101\,
      O => \termI[21]_i_1_n_0\
    );
\termI[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_100\,
      O => \termI[22]_i_1_n_0\
    );
\termI[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_99\,
      O => \termI[23]_i_1_n_0\
    );
\termI[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_98\,
      O => \termI[24]_i_1_n_0\
    );
\termI[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_97\,
      O => \termI[25]_i_1_n_0\
    );
\termI[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_96\,
      O => \termI[26]_i_1_n_0\
    );
\termI[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_95\,
      O => \termI[27]_i_1_n_0\
    );
\termI[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_94\,
      O => \termI[28]_i_1_n_0\
    );
\termI[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_93\,
      O => \termI[29]_i_1_n_0\
    );
\termI[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_103,
      O => \termI[2]_i_1_n_0\
    );
\termI[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_92\,
      O => \termI[30]_i_1_n_0\
    );
\termI[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__4_n_0\,
      I1 => \termI0__0_n_91\,
      O => \termI[31]_i_1_n_0\
    );
\termI[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termI0__0_n_90\,
      O => \termI[32]_i_1_n_0\
    );
\termI[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termI0__0_n_89\,
      O => \termI[33]_i_1_n_0\
    );
\termI[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termI0__0_n_88\,
      O => \termI[34]_i_1_n_0\
    );
\termI[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termI0__0_n_87\,
      O => \termI[35]_i_1_n_0\
    );
\termI[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termI0__0_n_86\,
      O => \termI[36]_i_1_n_0\
    );
\termI[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termI0__0_n_85\,
      O => \termI[37]_i_1_n_0\
    );
\termI[38]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termI0__0_n_84\,
      O => \termI[38]_i_1_n_0\
    );
\termI[39]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termI0__0_n_83\,
      O => \termI[39]_i_1_n_0\
    );
\termI[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_102,
      O => \termI[3]_i_1_n_0\
    );
\termI[40]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termI0__0_n_82\,
      O => \termI[40]_i_1_n_0\
    );
\termI[41]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termI0__0_n_81\,
      O => \termI[41]_i_1_n_0\
    );
\termI[42]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termI0__0_n_80\,
      O => \termI[42]_i_1_n_0\
    );
\termI[43]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termI0__0_n_79\,
      O => \termI[43]_i_1_n_0\
    );
\termI[44]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termI0__0_n_78\,
      O => \termI[44]_i_1_n_0\
    );
\termI[45]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__14_n_0\,
      I1 => \termI0__0_n_77\,
      O => \termI[45]_i_1_n_0\
    );
\termI[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_101,
      O => \termI[4]_i_1_n_0\
    );
\termI[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_100,
      O => \termI[5]_i_1_n_0\
    );
\termI[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_99,
      O => \termI[6]_i_1_n_0\
    );
\termI[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_98,
      O => \termI[7]_i_1_n_0\
    );
\termI[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_97,
      O => \termI[8]_i_1_n_0\
    );
\termI[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__3_n_0\,
      I1 => termI0_n_96,
      O => \termI[9]_i_1_n_0\
    );
\termI_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[0]_i_1_n_0\,
      Q => termI(0)
    );
\termI_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[10]_i_1_n_0\,
      Q => termI(10)
    );
\termI_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[11]_i_1_n_0\,
      Q => termI(11)
    );
\termI_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[12]_i_1_n_0\,
      Q => termI(12)
    );
\termI_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[13]_i_1_n_0\,
      Q => termI(13)
    );
\termI_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[14]_i_1_n_0\,
      Q => termI(14)
    );
\termI_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[15]_i_1_n_0\,
      Q => termI(15)
    );
\termI_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[16]_i_1_n_0\,
      Q => termI(16)
    );
\termI_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[17]_i_1_n_0\,
      Q => termI(17)
    );
\termI_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[18]_i_1_n_0\,
      Q => termI(18)
    );
\termI_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[19]_i_1_n_0\,
      Q => termI(19)
    );
\termI_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[1]_i_1_n_0\,
      Q => termI(1)
    );
\termI_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[20]_i_1_n_0\,
      Q => termI(20)
    );
\termI_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[21]_i_1_n_0\,
      Q => termI(21)
    );
\termI_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[22]_i_1_n_0\,
      Q => termI(22)
    );
\termI_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[23]_i_1_n_0\,
      Q => termI(23)
    );
\termI_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[24]_i_1_n_0\,
      Q => termI(24)
    );
\termI_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[25]_i_1_n_0\,
      Q => termI(25)
    );
\termI_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[26]_i_1_n_0\,
      Q => termI(26)
    );
\termI_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[27]_i_1_n_0\,
      Q => termI(27)
    );
\termI_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[28]_i_1_n_0\,
      Q => termI(28)
    );
\termI_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[29]_i_1_n_0\,
      Q => termI(29)
    );
\termI_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[2]_i_1_n_0\,
      Q => termI(2)
    );
\termI_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[30]_i_1_n_0\,
      Q => termI(30)
    );
\termI_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[31]_i_1_n_0\,
      Q => termI(31)
    );
\termI_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[32]_i_1_n_0\,
      Q => termI(32)
    );
\termI_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[33]_i_1_n_0\,
      Q => termI(33)
    );
\termI_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[34]_i_1_n_0\,
      Q => termI(34)
    );
\termI_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[35]_i_1_n_0\,
      Q => termI(35)
    );
\termI_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[36]_i_1_n_0\,
      Q => termI(36)
    );
\termI_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[37]_i_1_n_0\,
      Q => termI(37)
    );
\termI_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[38]_i_1_n_0\,
      Q => termI(38)
    );
\termI_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[39]_i_1_n_0\,
      Q => termI(39)
    );
\termI_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[3]_i_1_n_0\,
      Q => termI(3)
    );
\termI_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[40]_i_1_n_0\,
      Q => termI(40)
    );
\termI_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[41]_i_1_n_0\,
      Q => termI(41)
    );
\termI_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[42]_i_1_n_0\,
      Q => termI(42)
    );
\termI_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[43]_i_1_n_0\,
      Q => termI(43)
    );
\termI_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[44]_i_1_n_0\,
      Q => termI(44)
    );
\termI_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[45]_i_1_n_0\,
      Q => termI(45)
    );
\termI_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[4]_i_1_n_0\,
      Q => termI(4)
    );
\termI_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[5]_i_1_n_0\,
      Q => termI(5)
    );
\termI_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[6]_i_1_n_0\,
      Q => termI(6)
    );
\termI_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[7]_i_1_n_0\,
      Q => termI(7)
    );
\termI_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[8]_i_1_n_0\,
      Q => termI(8)
    );
\termI_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \termI[9]_i_1_n_0\,
      Q => termI(9)
    );
\thd_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(14),
      Q => \thd_reg_n_0_[0]\
    );
\thd_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(15),
      Q => \thd_reg_n_0_[1]\
    );
\thd_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(16),
      Q => \thd_reg_n_0_[2]\
    );
\thd_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(17),
      Q => \thd_reg_n_0_[3]\
    );
\thd_reg[4]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \thd_reg[7]_0\(18),
      PRE => linNotLog_reg_0,
      Q => \thd_reg_n_0_[4]\
    );
\thd_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(19),
      Q => \thd_reg_n_0_[5]\
    );
\thd_reg[6]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => \thd_reg[7]_0\(20),
      PRE => linNotLog_reg_0,
      Q => \thd_reg_n_0_[6]\
    );
\thd_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => linNotLog_reg_0,
      D => \thd_reg[7]_0\(21),
      Q => \thd_reg_n_0_[7]\
    );
\tixVState[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFBFFAAAAAAAA"
    )
        port map (
      I0 => \^tixvstate_reg[1]_0\(1),
      I1 => \tixVState_reg[1]_2\,
      I2 => \^stateop_reg[1]_0\(0),
      I3 => \tkst_reg[0]_0\,
      I4 => vsync_last_reg_n_0,
      I5 => \^tixvstate_reg[1]_0\(0),
      O => \tixVState_reg[1]_1\
    );
\tixVState_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tixVState_reg[1]_3\(0),
      CLR => linNotLog_reg_0,
      D => ackInvAcquire_sig,
      Q => \^tixvstate_reg[1]_0\(0)
    );
\tixVState_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tixVState_reg[1]_3\(0),
      CLR => linNotLog_reg_0,
      D => \tixVState_reg[1]_4\(0),
      Q => \^tixvstate_reg[1]_0\(1)
    );
\tkst[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000D000"
    )
        port map (
      I0 => \^tixvstate_reg[1]_0\(1),
      I1 => \^tixvstate_reg[1]_0\(0),
      I2 => \tkst_reg[0]_0\,
      I3 => \^rng_reg_0\,
      I4 => \stateMaxsel_reg_n_0_[1]\,
      I5 => \stateMaxsel_reg_n_0_[0]\,
      O => tkst
    );
\tkst_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(0),
      Q => \tkst_reg[31]_0\(0)
    );
\tkst_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(10),
      Q => \tkst_reg[31]_0\(10)
    );
\tkst_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(11),
      Q => \tkst_reg[31]_0\(11)
    );
\tkst_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(12),
      Q => \tkst_reg[31]_0\(12)
    );
\tkst_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(13),
      Q => \tkst_reg[31]_0\(13)
    );
\tkst_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(14),
      Q => \tkst_reg[31]_0\(14)
    );
\tkst_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(15),
      Q => \tkst_reg[31]_0\(15)
    );
\tkst_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(16),
      Q => \tkst_reg[31]_0\(16)
    );
\tkst_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(17),
      Q => \tkst_reg[31]_0\(17)
    );
\tkst_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(18),
      Q => \tkst_reg[31]_0\(18)
    );
\tkst_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(19),
      Q => \tkst_reg[31]_0\(19)
    );
\tkst_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(1),
      Q => \tkst_reg[31]_0\(1)
    );
\tkst_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(20),
      Q => \tkst_reg[31]_0\(20)
    );
\tkst_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(21),
      Q => \tkst_reg[31]_0\(21)
    );
\tkst_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(22),
      Q => \tkst_reg[31]_0\(22)
    );
\tkst_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(23),
      Q => \tkst_reg[31]_0\(23)
    );
\tkst_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(24),
      Q => \tkst_reg[31]_0\(24)
    );
\tkst_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(25),
      Q => \tkst_reg[31]_0\(25)
    );
\tkst_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(26),
      Q => \tkst_reg[31]_0\(26)
    );
\tkst_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(27),
      Q => \tkst_reg[31]_0\(27)
    );
\tkst_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(28),
      Q => \tkst_reg[31]_0\(28)
    );
\tkst_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(29),
      Q => \tkst_reg[31]_0\(29)
    );
\tkst_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(2),
      Q => \tkst_reg[31]_0\(2)
    );
\tkst_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(30),
      Q => \tkst_reg[31]_0\(30)
    );
\tkst_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(31),
      Q => \tkst_reg[31]_0\(31)
    );
\tkst_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(3),
      Q => \tkst_reg[31]_0\(3)
    );
\tkst_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(4),
      Q => \tkst_reg[31]_0\(4)
    );
\tkst_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(5),
      Q => \tkst_reg[31]_0\(5)
    );
\tkst_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(6),
      Q => \tkst_reg[31]_0\(6)
    );
\tkst_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(7),
      Q => \tkst_reg[31]_0\(7)
    );
\tkst_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(8),
      Q => \tkst_reg[31]_0\(8)
    );
\tkst_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => linNotLog_reg_0,
      D => \tkst_reg[31]_1\(9),
      Q => \tkst_reg[31]_0\(9)
    );
vsync_last_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => \tkst_reg[0]_0\,
      I1 => vsync_last_reg_0,
      I2 => \^stateop_reg[1]_0\(0),
      I3 => vsync_last_reg_n_0,
      O => vsync_last_i_1_n_0
    );
vsync_last_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => linNotLog_reg_0,
      D => vsync_last_i_1_n_0,
      Q => vsync_last_reg_n_0
    );
\wordcntLast[28]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => enCoobufB,
      I1 => \FSM_onehot_stateCoobufB_reg_n_0_[2]\,
      I2 => \^fsm_onehot_statecoobufb_reg[5]_0\(0),
      O => ackCoobufCornerToHostif
    );
\xsqr4p1[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[72]\,
      O => \xsqr4p1[0]_i_1_n_0\
    );
\xsqr4p1[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[82]\,
      O => \xsqr4p1[10]_i_1_n_0\
    );
\xsqr4p1[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[83]\,
      O => \xsqr4p1[11]_i_1_n_0\
    );
\xsqr4p1[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[84]\,
      O => \xsqr4p1[12]_i_1_n_0\
    );
\xsqr4p1[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[85]\,
      O => \xsqr4p1[13]_i_1_n_0\
    );
\xsqr4p1[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[86]\,
      O => \xsqr4p1[14]_i_1_n_0\
    );
\xsqr4p1[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[87]\,
      O => \xsqr4p1[15]_i_1_n_0\
    );
\xsqr4p1[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => \xsqr_reg_n_0_[88]\,
      O => \xsqr4p1[16]_i_1_n_0\
    );
\xsqr4p1[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => \xsqr_reg_n_0_[89]\,
      O => \xsqr4p1[17]_i_1_n_0\
    );
\xsqr4p1[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[74]\,
      O => \xsqr4p1[2]_i_1_n_0\
    );
\xsqr4p1[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[75]\,
      O => \xsqr4p1[3]_i_1_n_0\
    );
\xsqr4p1[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[76]\,
      O => \xsqr4p1[4]_i_1_n_0\
    );
\xsqr4p1[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[77]\,
      O => \xsqr4p1[5]_i_1_n_0\
    );
\xsqr4p1[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[78]\,
      O => \xsqr4p1[6]_i_1_n_0\
    );
\xsqr4p1[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[79]\,
      O => \xsqr4p1[7]_i_1_n_0\
    );
\xsqr4p1[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[80]\,
      O => \xsqr4p1[8]_i_1_n_0\
    );
\xsqr4p1[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \xsqr_reg_n_0_[81]\,
      O => \xsqr4p1[9]_i_1_n_0\
    );
\xsqr4p1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[0]_i_1_n_0\,
      Q => xsqr4p1(0)
    );
\xsqr4p1_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[10]_i_1_n_0\,
      Q => xsqr4p1(10)
    );
\xsqr4p1_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[11]_i_1_n_0\,
      Q => xsqr4p1(11)
    );
\xsqr4p1_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[12]_i_1_n_0\,
      Q => xsqr4p1(12)
    );
\xsqr4p1_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[13]_i_1_n_0\,
      Q => xsqr4p1(13)
    );
\xsqr4p1_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[14]_i_1_n_0\,
      Q => xsqr4p1(14)
    );
\xsqr4p1_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[15]_i_1_n_0\,
      Q => xsqr4p1(15)
    );
\xsqr4p1_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[16]_i_1_n_0\,
      Q => xsqr4p1(16)
    );
\xsqr4p1_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[17]_i_1_n_0\,
      Q => xsqr4p1(17)
    );
\xsqr4p1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[2]_i_1_n_0\,
      Q => xsqr4p1(2)
    );
\xsqr4p1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[3]_i_1_n_0\,
      Q => xsqr4p1(3)
    );
\xsqr4p1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[4]_i_1_n_0\,
      Q => xsqr4p1(4)
    );
\xsqr4p1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[5]_i_1_n_0\,
      Q => xsqr4p1(5)
    );
\xsqr4p1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[6]_i_1_n_0\,
      Q => xsqr4p1(6)
    );
\xsqr4p1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[7]_i_1_n_0\,
      Q => xsqr4p1(7)
    );
\xsqr4p1_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[8]_i_1_n_0\,
      Q => xsqr4p1(8)
    );
\xsqr4p1_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p1[9]_i_1_n_0\,
      Q => xsqr4p1(9)
    );
\xsqr4p2[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(0),
      O => \xsqr4p2[0]_i_1_n_0\
    );
\xsqr4p2[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(10),
      O => \xsqr4p2[10]_i_1_n_0\
    );
\xsqr4p2[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(11),
      O => \xsqr4p2[11]_i_1_n_0\
    );
\xsqr4p2[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(12),
      O => \xsqr4p2[12]_i_1_n_0\
    );
\xsqr4p2[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(13),
      O => \xsqr4p2[13]_i_1_n_0\
    );
\xsqr4p2[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(14),
      O => \xsqr4p2[14]_i_1_n_0\
    );
\xsqr4p2[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(15),
      O => \xsqr4p2[15]_i_1_n_0\
    );
\xsqr4p2[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xsqr4p1(16),
      O => \xsqr4p2[16]_i_1_n_0\
    );
\xsqr4p2[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xsqr4p1(17),
      O => \xsqr4p2[17]_i_1_n_0\
    );
\xsqr4p2[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(2),
      O => \xsqr4p2[2]_i_1_n_0\
    );
\xsqr4p2[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(3),
      O => \xsqr4p2[3]_i_1_n_0\
    );
\xsqr4p2[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(4),
      O => \xsqr4p2[4]_i_1_n_0\
    );
\xsqr4p2[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(5),
      O => \xsqr4p2[5]_i_1_n_0\
    );
\xsqr4p2[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(6),
      O => \xsqr4p2[6]_i_1_n_0\
    );
\xsqr4p2[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(7),
      O => \xsqr4p2[7]_i_1_n_0\
    );
\xsqr4p2[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(8),
      O => \xsqr4p2[8]_i_1_n_0\
    );
\xsqr4p2[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr4p1(9),
      O => \xsqr4p2[9]_i_1_n_0\
    );
\xsqr4p2_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[0]_i_1_n_0\,
      Q => xsqr4p2(0)
    );
\xsqr4p2_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[10]_i_1_n_0\,
      Q => xsqr4p2(10)
    );
\xsqr4p2_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[11]_i_1_n_0\,
      Q => xsqr4p2(11)
    );
\xsqr4p2_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[12]_i_1_n_0\,
      Q => xsqr4p2(12)
    );
\xsqr4p2_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[13]_i_1_n_0\,
      Q => xsqr4p2(13)
    );
\xsqr4p2_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[14]_i_1_n_0\,
      Q => xsqr4p2(14)
    );
\xsqr4p2_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[15]_i_1_n_0\,
      Q => xsqr4p2(15)
    );
\xsqr4p2_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[16]_i_1_n_0\,
      Q => xsqr4p2(16)
    );
\xsqr4p2_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[17]_i_1_n_0\,
      Q => xsqr4p2(17)
    );
\xsqr4p2_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[2]_i_1_n_0\,
      Q => xsqr4p2(2)
    );
\xsqr4p2_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[3]_i_1_n_0\,
      Q => xsqr4p2(3)
    );
\xsqr4p2_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[4]_i_1_n_0\,
      Q => xsqr4p2(4)
    );
\xsqr4p2_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[5]_i_1_n_0\,
      Q => xsqr4p2(5)
    );
\xsqr4p2_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[6]_i_1_n_0\,
      Q => xsqr4p2(6)
    );
\xsqr4p2_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[7]_i_1_n_0\,
      Q => xsqr4p2(7)
    );
\xsqr4p2_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[8]_i_1_n_0\,
      Q => xsqr4p2(8)
    );
\xsqr4p2_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr4p2[9]_i_1_n_0\,
      Q => xsqr4p2(9)
    );
\xsqr[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => \dx_reg_n_0_[0]\,
      O => \xsqr[0]_i_1_n_0\
    );
\xsqr[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(10),
      O => \xsqr[10]_i_1_n_0\
    );
\xsqr[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(11),
      O => \xsqr[11]_i_1_n_0\
    );
\xsqr[11]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[3]_i_3_n_15\,
      I1 => \xsqr_reg[3]_i_2_n_13\,
      O => \xsqr[11]_i_10_n_0\
    );
\xsqr[11]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \xsqr_reg[3]_i_3_n_9\,
      I1 => \xsqr_reg[17]_i_13_n_12\,
      I2 => \xsqr_reg[17]_i_18_n_14\,
      I3 => \xsqr_reg[17]_i_13_n_11\,
      I4 => \xsqr_reg[3]_i_3_n_8\,
      I5 => \xsqr[11]_i_19_n_0\,
      O => \xsqr[11]_i_11_n_0\
    );
\xsqr[11]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \xsqr_reg[17]_i_18_n_15\,
      I1 => \xsqr_reg[3]_i_3_n_9\,
      I2 => \xsqr_reg[17]_i_13_n_12\,
      I3 => \xsqr_reg[3]_i_3_n_8\,
      I4 => \xsqr_reg[17]_i_13_n_11\,
      I5 => \xsqr_reg[17]_i_18_n_14\,
      O => \xsqr[11]_i_12_n_0\
    );
\xsqr[11]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \xsqr_reg[17]_i_18_n_15\,
      I1 => \xsqr_reg[17]_i_13_n_12\,
      I2 => \xsqr_reg[3]_i_3_n_9\,
      I3 => \xsqr_reg[3]_i_3_n_10\,
      I4 => \xsqr_reg[3]_i_2_n_8\,
      I5 => \xsqr_reg[17]_i_13_n_13\,
      O => \xsqr[11]_i_13_n_0\
    );
\xsqr[11]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr[11]_i_6_n_0\,
      I1 => \xsqr_reg[17]_i_13_n_13\,
      I2 => \xsqr_reg[3]_i_2_n_8\,
      I3 => \xsqr_reg[3]_i_3_n_10\,
      O => \xsqr[11]_i_14_n_0\
    );
\xsqr[11]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr_reg[17]_i_13_n_14\,
      I1 => \xsqr_reg[3]_i_2_n_9\,
      I2 => \xsqr_reg[3]_i_3_n_11\,
      I3 => \xsqr[11]_i_7_n_0\,
      O => \xsqr[11]_i_15_n_0\
    );
\xsqr[11]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr_reg[17]_i_13_n_15\,
      I1 => \xsqr_reg[3]_i_2_n_10\,
      I2 => \xsqr_reg[3]_i_3_n_12\,
      I3 => \xsqr[11]_i_8_n_0\,
      O => \xsqr[11]_i_16_n_0\
    );
\xsqr[11]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xsqr_reg[3]_i_3_n_13\,
      I1 => \xsqr_reg[3]_i_2_n_11\,
      I2 => \xsqr_reg[3]_i_2_n_12\,
      I3 => \xsqr_reg[3]_i_3_n_14\,
      O => \xsqr[11]_i_17_n_0\
    );
\xsqr[11]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \xsqr_reg[3]_i_2_n_13\,
      I1 => \xsqr_reg[3]_i_3_n_15\,
      I2 => \xsqr_reg[3]_i_2_n_12\,
      I3 => \xsqr_reg[3]_i_3_n_14\,
      O => \xsqr[11]_i_18_n_0\
    );
\xsqr[11]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xsqr_reg[17]_i_17_n_15\,
      I1 => \xsqr_reg[17]_i_13_n_10\,
      I2 => \xsqr_reg[17]_i_18_n_5\,
      O => \xsqr[11]_i_19_n_0\
    );
\xsqr[11]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \xsqr_reg[3]_i_3_n_9\,
      I1 => \xsqr_reg[17]_i_13_n_12\,
      I2 => \xsqr_reg[17]_i_18_n_14\,
      I3 => \xsqr_reg[17]_i_13_n_11\,
      I4 => \xsqr_reg[3]_i_3_n_8\,
      O => \xsqr[11]_i_3_n_0\
    );
\xsqr[11]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \xsqr_reg[17]_i_18_n_15\,
      I1 => \xsqr_reg[3]_i_3_n_9\,
      I2 => \xsqr_reg[17]_i_13_n_12\,
      O => \xsqr[11]_i_4_n_0\
    );
\xsqr[11]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xsqr_reg[3]_i_3_n_9\,
      I1 => \xsqr_reg[17]_i_13_n_12\,
      I2 => \xsqr_reg[17]_i_18_n_15\,
      O => \xsqr[11]_i_5_n_0\
    );
\xsqr[11]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xsqr_reg[17]_i_13_n_14\,
      I1 => \xsqr_reg[3]_i_2_n_9\,
      I2 => \xsqr_reg[3]_i_3_n_11\,
      O => \xsqr[11]_i_6_n_0\
    );
\xsqr[11]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xsqr_reg[17]_i_13_n_15\,
      I1 => \xsqr_reg[3]_i_2_n_10\,
      I2 => \xsqr_reg[3]_i_3_n_12\,
      O => \xsqr[11]_i_7_n_0\
    );
\xsqr[11]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[3]_i_3_n_13\,
      I1 => \xsqr_reg[3]_i_2_n_11\,
      O => \xsqr[11]_i_8_n_0\
    );
\xsqr[11]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[3]_i_3_n_14\,
      I1 => \xsqr_reg[3]_i_2_n_12\,
      O => \xsqr[11]_i_9_n_0\
    );
\xsqr[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(12),
      O => \xsqr[12]_i_1_n_0\
    );
\xsqr[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(13),
      O => \xsqr[13]_i_1_n_0\
    );
\xsqr[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(14),
      O => \xsqr[14]_i_1_n_0\
    );
\xsqr[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(15),
      O => \xsqr[15]_i_1_n_0\
    );
\xsqr[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(16),
      O => \xsqr[16]_i_1_n_0\
    );
\xsqr[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(17),
      O => \xsqr[17]_i_1_n_0\
    );
\xsqr[17]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \xsqr[17]_i_5_n_0\,
      I1 => \xsqr_reg[17]_i_3_n_15\,
      I2 => \xsqr_reg[17]_i_17_n_4\,
      I3 => \xsqr_reg[17]_i_13_n_8\,
      I4 => \xsqr_reg[17]_i_17_n_13\,
      O => \xsqr[17]_i_10_n_0\
    );
\xsqr[17]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \xsqr_reg[17]_i_17_n_14\,
      I1 => \xsqr_reg[17]_i_13_n_9\,
      I2 => \xsqr_reg[17]_i_17_n_13\,
      I3 => \xsqr_reg[17]_i_13_n_8\,
      I4 => \xsqr[17]_i_6_n_0\,
      O => \xsqr[17]_i_11_n_0\
    );
\xsqr[17]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \xsqr[17]_i_7_n_0\,
      I1 => \xsqr_reg[17]_i_17_n_15\,
      I2 => \xsqr_reg[17]_i_18_n_5\,
      I3 => \xsqr_reg[17]_i_13_n_10\,
      I4 => \xsqr_reg[17]_i_17_n_14\,
      I5 => \xsqr_reg[17]_i_13_n_9\,
      O => \xsqr[17]_i_12_n_0\
    );
\xsqr[17]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \dx_reg_n_0_[7]\,
      I1 => \dx_reg_n_0_[8]\,
      O => \xsqr[17]_i_14_n_0\
    );
\xsqr[17]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \dx_reg_n_0_[6]\,
      I1 => \dx_reg_n_0_[8]\,
      O => \xsqr[17]_i_15_n_0\
    );
\xsqr[17]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dx_reg_n_0_[7]\,
      I1 => \dx_reg_n_0_[6]\,
      O => \xsqr[17]_i_16_n_0\
    );
\xsqr[17]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7777000"
    )
        port map (
      I0 => \dx_reg_n_0_[8]\,
      I1 => \dx_reg_n_0_[4]\,
      I2 => \dx_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[5]\,
      I4 => \dx_reg_n_0_[6]\,
      O => \xsqr[17]_i_19_n_0\
    );
\xsqr[17]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dx_reg_n_0_[8]\,
      I1 => \dx_reg_n_0_[3]\,
      I2 => \dx_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[4]\,
      I4 => \dx_reg_n_0_[5]\,
      I5 => \dx_reg_n_0_[6]\,
      O => \xsqr[17]_i_20_n_0\
    );
\xsqr[17]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dx_reg_n_0_[8]\,
      I1 => \dx_reg_n_0_[2]\,
      I2 => \dx_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[3]\,
      I4 => \dx_reg_n_0_[4]\,
      I5 => \dx_reg_n_0_[6]\,
      O => \xsqr[17]_i_21_n_0\
    );
\xsqr[17]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dx_reg_n_0_[8]\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dx_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[2]\,
      I4 => \dx_reg_n_0_[3]\,
      I5 => \dx_reg_n_0_[6]\,
      O => \xsqr[17]_i_22_n_0\
    );
\xsqr[17]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => \dx_reg_n_0_[8]\,
      I1 => \dx_reg_n_0_[0]\,
      I2 => \dx_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[1]\,
      O => \xsqr[17]_i_23_n_0\
    );
\xsqr[17]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[1]\,
      I1 => \dx_reg_n_0_[6]\,
      O => \xsqr[17]_i_24_n_0\
    );
\xsqr[17]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8E11F555"
    )
        port map (
      I0 => \dx_reg_n_0_[6]\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dx_reg_n_0_[4]\,
      I3 => \dx_reg_n_0_[8]\,
      I4 => \dx_reg_n_0_[5]\,
      O => \xsqr[17]_i_25_n_0\
    );
\xsqr[17]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EB843C0C903FCF3F"
    )
        port map (
      I0 => \dx_reg_n_0_[3]\,
      I1 => \dx_reg_n_0_[5]\,
      I2 => \dx_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[4]\,
      I4 => \dx_reg_n_0_[8]\,
      I5 => \dx_reg_n_0_[6]\,
      O => \xsqr[17]_i_26_n_0\
    );
\xsqr[17]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F07070780F8F8F8"
    )
        port map (
      I0 => \dx_reg_n_0_[6]\,
      I1 => \dx_reg_n_0_[4]\,
      I2 => \xsqr[17]_i_43_n_0\,
      I3 => \dx_reg_n_0_[2]\,
      I4 => \dx_reg_n_0_[8]\,
      I5 => \xsqr[17]_i_44_n_0\,
      O => \xsqr[17]_i_27_n_0\
    );
\xsqr[17]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A956A956A95"
    )
        port map (
      I0 => \xsqr[17]_i_22_n_0\,
      I1 => \dx_reg_n_0_[8]\,
      I2 => \dx_reg_n_0_[2]\,
      I3 => \xsqr[17]_i_43_n_0\,
      I4 => \dx_reg_n_0_[4]\,
      I5 => \dx_reg_n_0_[6]\,
      O => \xsqr[17]_i_28_n_0\
    );
\xsqr[17]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"69C399C369336933"
    )
        port map (
      I0 => \dx_reg_n_0_[2]\,
      I1 => \xsqr[17]_i_45_n_0\,
      I2 => \dx_reg_n_0_[1]\,
      I3 => \dx_reg_n_0_[7]\,
      I4 => \dx_reg_n_0_[0]\,
      I5 => \dx_reg_n_0_[8]\,
      O => \xsqr[17]_i_29_n_0\
    );
\xsqr[17]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dx_reg_n_0_[1]\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dx_reg_n_0_[0]\,
      I3 => \dx_reg_n_0_[8]\,
      I4 => \dx_reg_n_0_[6]\,
      I5 => \dx_reg_n_0_[2]\,
      O => \xsqr[17]_i_30_n_0\
    );
\xsqr[17]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dx_reg_n_0_[6]\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dx_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[0]\,
      O => \xsqr[17]_i_31_n_0\
    );
\xsqr[17]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[0]\,
      I1 => \dx_reg_n_0_[6]\,
      O => \xsqr[17]_i_32_n_0\
    );
\xsqr[17]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dx_reg_n_0_[7]\,
      I1 => \dx_reg_n_0_[5]\,
      I2 => \dx_reg_n_0_[8]\,
      I3 => \dx_reg_n_0_[4]\,
      O => \xsqr[17]_i_33_n_0\
    );
\xsqr[17]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dx_reg_n_0_[5]\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dx_reg_n_0_[4]\,
      I3 => \dx_reg_n_0_[8]\,
      O => \xsqr[17]_i_34_n_0\
    );
\xsqr[17]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[4]\,
      I1 => \dx_reg_n_0_[5]\,
      O => \xsqr[17]_i_35_n_0\
    );
\xsqr[17]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dx_reg_n_0_[4]\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dx_reg_n_0_[8]\,
      I3 => \dx_reg_n_0_[5]\,
      O => \xsqr[17]_i_36_n_0\
    );
\xsqr[17]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dx_reg_n_0_[6]\,
      I1 => \dx_reg_n_0_[3]\,
      I2 => \dx_reg_n_0_[8]\,
      I3 => \dx_reg_n_0_[4]\,
      I4 => \dx_reg_n_0_[7]\,
      I5 => \dx_reg_n_0_[5]\,
      O => \xsqr[17]_i_37_n_0\
    );
\xsqr[17]_i_38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D22287772DDD8777"
    )
        port map (
      I0 => \dx_reg_n_0_[4]\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dx_reg_n_0_[3]\,
      I3 => \dx_reg_n_0_[8]\,
      I4 => \dx_reg_n_0_[5]\,
      I5 => \dx_reg_n_0_[6]\,
      O => \xsqr[17]_i_38_n_0\
    );
\xsqr[17]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dx_reg_n_0_[7]\,
      I1 => \dx_reg_n_0_[2]\,
      I2 => \dx_reg_n_0_[8]\,
      I3 => \dx_reg_n_0_[1]\,
      O => \xsqr[17]_i_39_n_0\
    );
\xsqr[17]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xsqr_reg[17]_i_17_n_13\,
      I1 => \xsqr_reg[17]_i_13_n_8\,
      I2 => \xsqr_reg[17]_i_17_n_4\,
      I3 => \xsqr_reg[17]_i_3_n_15\,
      O => \xsqr[17]_i_4_n_0\
    );
\xsqr[17]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dx_reg_n_0_[2]\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dx_reg_n_0_[1]\,
      I3 => \dx_reg_n_0_[8]\,
      O => \xsqr[17]_i_40_n_0\
    );
\xsqr[17]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dx_reg_n_0_[1]\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dx_reg_n_0_[8]\,
      I3 => \dx_reg_n_0_[2]\,
      O => \xsqr[17]_i_41_n_0\
    );
\xsqr[17]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dx_reg_n_0_[6]\,
      I1 => \dx_reg_n_0_[0]\,
      I2 => \dx_reg_n_0_[8]\,
      I3 => \dx_reg_n_0_[1]\,
      I4 => \dx_reg_n_0_[7]\,
      I5 => \dx_reg_n_0_[2]\,
      O => \xsqr[17]_i_42_n_0\
    );
\xsqr[17]_i_43\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[3]\,
      I1 => \dx_reg_n_0_[7]\,
      O => \xsqr[17]_i_43_n_0\
    );
\xsqr[17]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dx_reg_n_0_[6]\,
      I1 => \dx_reg_n_0_[5]\,
      I2 => \dx_reg_n_0_[8]\,
      I3 => \dx_reg_n_0_[3]\,
      I4 => \dx_reg_n_0_[7]\,
      I5 => \dx_reg_n_0_[4]\,
      O => \xsqr[17]_i_44_n_0\
    );
\xsqr[17]_i_45\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[3]\,
      I1 => \dx_reg_n_0_[6]\,
      O => \xsqr[17]_i_45_n_0\
    );
\xsqr[17]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xsqr_reg[17]_i_17_n_14\,
      I1 => \xsqr_reg[17]_i_13_n_9\,
      I2 => \xsqr_reg[17]_i_17_n_13\,
      I3 => \xsqr_reg[17]_i_13_n_8\,
      O => \xsqr[17]_i_5_n_0\
    );
\xsqr[17]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \xsqr_reg[17]_i_17_n_14\,
      I1 => \xsqr_reg[17]_i_13_n_9\,
      I2 => \xsqr_reg[17]_i_17_n_15\,
      I3 => \xsqr_reg[17]_i_18_n_5\,
      I4 => \xsqr_reg[17]_i_13_n_10\,
      O => \xsqr[17]_i_6_n_0\
    );
\xsqr[17]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \xsqr_reg[3]_i_3_n_8\,
      I1 => \xsqr_reg[17]_i_18_n_14\,
      I2 => \xsqr_reg[17]_i_13_n_11\,
      I3 => \xsqr_reg[17]_i_18_n_5\,
      I4 => \xsqr_reg[17]_i_13_n_10\,
      I5 => \xsqr_reg[17]_i_17_n_15\,
      O => \xsqr[17]_i_7_n_0\
    );
\xsqr[17]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \xsqr_reg[17]_i_3_n_15\,
      I1 => \xsqr_reg[17]_i_17_n_4\,
      I2 => \xsqr_reg[17]_i_3_n_14\,
      I3 => \xsqr_reg[17]_i_3_n_13\,
      O => \xsqr[17]_i_8_n_0\
    );
\xsqr[17]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \xsqr_reg[17]_i_13_n_8\,
      I1 => \xsqr_reg[17]_i_17_n_13\,
      I2 => \xsqr_reg[17]_i_3_n_15\,
      I3 => \xsqr_reg[17]_i_17_n_4\,
      I4 => \xsqr_reg[17]_i_3_n_14\,
      O => \xsqr[17]_i_9_n_0\
    );
\xsqr[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => A(0),
      O => \xsqr[18]_i_1_n_0\
    );
\xsqr[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(2),
      O => \xsqr[20]_i_1_n_0\
    );
\xsqr[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \xsqr_reg[21]_i_2_n_13\,
      I1 => \xsqr_reg[21]_i_3_n_15\,
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \xsqr[21]_i_1_n_0\
    );
\xsqr[21]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xsqr[21]_i_4_n_0\,
      I1 => \xsqr[21]_i_31_n_0\,
      I2 => A(2),
      I3 => A(6),
      O => \xsqr[21]_i_10_n_0\
    );
\xsqr[21]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xsqr[21]_i_5_n_0\,
      I1 => A(5),
      I2 => A(2),
      I3 => \xsqr[21]_i_32_n_0\,
      I4 => A(0),
      I5 => A(7),
      O => \xsqr[21]_i_11_n_0\
    );
\xsqr[21]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \xsqr[21]_i_6_n_0\,
      I1 => A(4),
      I2 => A(2),
      I3 => A(5),
      I4 => A(1),
      I5 => \xsqr[21]_i_33_n_0\,
      O => \xsqr[21]_i_12_n_0\
    );
\xsqr[21]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xsqr[21]_i_7_n_0\,
      I1 => A(4),
      I2 => A(1),
      I3 => \xsqr[21]_i_21_n_0\,
      I4 => A(0),
      I5 => A(5),
      O => \xsqr[21]_i_13_n_0\
    );
\xsqr[21]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => A(1),
      I1 => A(2),
      I2 => A(3),
      I3 => A(4),
      I4 => A(0),
      O => \xsqr[21]_i_14_n_0\
    );
\xsqr[21]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => A(3),
      I1 => A(2),
      I2 => A(0),
      O => \xsqr[21]_i_15_n_0\
    );
\xsqr[21]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => A(1),
      I1 => A(0),
      O => \xsqr[21]_i_16_n_0\
    );
\xsqr[21]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(3),
      I1 => A(7),
      O => \xsqr[21]_i_17_n_0\
    );
\xsqr[21]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(3),
      I1 => A(6),
      O => \xsqr[21]_i_18_n_0\
    );
\xsqr[21]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(2),
      I1 => A(5),
      O => \xsqr[21]_i_19_n_0\
    );
\xsqr[21]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"956A6A6A"
    )
        port map (
      I0 => A(3),
      I1 => A(1),
      I2 => A(5),
      I3 => A(2),
      I4 => A(4),
      O => \xsqr[21]_i_20_n_0\
    );
\xsqr[21]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(2),
      I1 => A(3),
      O => \xsqr[21]_i_21_n_0\
    );
\xsqr[21]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(1),
      I1 => A(3),
      O => \xsqr[21]_i_22_n_0\
    );
\xsqr[21]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => A(4),
      I1 => A(5),
      I2 => A(6),
      I3 => A(7),
      I4 => A(3),
      O => \xsqr[21]_i_23_n_0\
    );
\xsqr[21]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => A(6),
      I1 => A(5),
      I2 => A(3),
      O => \xsqr[21]_i_24_n_0\
    );
\xsqr[21]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => A(4),
      I1 => A(3),
      O => \xsqr[21]_i_25_n_0\
    );
\xsqr[21]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17A08800"
    )
        port map (
      I0 => A(3),
      I1 => A(1),
      I2 => A(4),
      I3 => A(5),
      I4 => A(2),
      O => \xsqr[21]_i_26_n_0\
    );
\xsqr[21]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"663C963C66CC66CC"
    )
        port map (
      I0 => A(2),
      I1 => A(3),
      I2 => A(1),
      I3 => A(4),
      I4 => A(0),
      I5 => A(5),
      O => \xsqr[21]_i_27_n_0\
    );
\xsqr[21]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => A(0),
      I1 => A(5),
      I2 => A(1),
      I3 => A(4),
      I4 => A(3),
      I5 => A(2),
      O => \xsqr[21]_i_28_n_0\
    );
\xsqr[21]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => A(3),
      I1 => A(1),
      I2 => A(4),
      I3 => A(0),
      O => \xsqr[21]_i_29_n_0\
    );
\xsqr[21]_i_30\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(0),
      I1 => A(3),
      O => \xsqr[21]_i_30_n_0\
    );
\xsqr[21]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => A(8),
      I1 => A(0),
      I2 => A(7),
      I3 => A(1),
      O => \xsqr[21]_i_31_n_0\
    );
\xsqr[21]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(1),
      I1 => A(6),
      O => \xsqr[21]_i_32_n_0\
    );
\xsqr[21]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(0),
      I1 => A(6),
      O => \xsqr[21]_i_33_n_0\
    );
\xsqr[21]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => A(5),
      I1 => A(2),
      I2 => A(6),
      I3 => A(1),
      I4 => A(0),
      I5 => A(7),
      O => \xsqr[21]_i_4_n_0\
    );
\xsqr[21]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => A(4),
      I1 => A(2),
      I2 => A(5),
      I3 => A(1),
      I4 => A(0),
      I5 => A(6),
      O => \xsqr[21]_i_5_n_0\
    );
\xsqr[21]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => A(4),
      I1 => A(1),
      I2 => A(3),
      I3 => A(2),
      I4 => A(0),
      I5 => A(5),
      O => \xsqr[21]_i_6_n_0\
    );
\xsqr[21]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(1),
      I1 => A(2),
      O => \xsqr[21]_i_7_n_0\
    );
\xsqr[21]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => A(3),
      I1 => A(2),
      I2 => A(1),
      O => \xsqr[21]_i_8_n_0\
    );
\xsqr[21]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(0),
      I1 => A(3),
      O => \xsqr[21]_i_9_n_0\
    );
\xsqr[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(4),
      O => \xsqr[22]_i_1_n_0\
    );
\xsqr[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(5),
      O => \xsqr[23]_i_1_n_0\
    );
\xsqr[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(6),
      O => \xsqr[24]_i_1_n_0\
    );
\xsqr[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(7),
      O => \xsqr[25]_i_1_n_0\
    );
\xsqr[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(8),
      O => \xsqr[26]_i_1_n_0\
    );
\xsqr[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(9),
      O => \xsqr[27]_i_1_n_0\
    );
\xsqr[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(10),
      O => \xsqr[28]_i_1_n_0\
    );
\xsqr[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(11),
      O => \xsqr[29]_i_1_n_0\
    );
\xsqr[29]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[21]_i_3_n_15\,
      I1 => \xsqr_reg[21]_i_2_n_13\,
      O => \xsqr[29]_i_10_n_0\
    );
\xsqr[29]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \xsqr_reg[21]_i_3_n_9\,
      I1 => \xsqr_reg[35]_i_13_n_12\,
      I2 => \xsqr_reg[35]_i_18_n_14\,
      I3 => \xsqr_reg[35]_i_13_n_11\,
      I4 => \xsqr_reg[21]_i_3_n_8\,
      I5 => \xsqr[29]_i_19_n_0\,
      O => \xsqr[29]_i_11_n_0\
    );
\xsqr[29]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \xsqr_reg[35]_i_18_n_15\,
      I1 => \xsqr_reg[21]_i_3_n_9\,
      I2 => \xsqr_reg[35]_i_13_n_12\,
      I3 => \xsqr_reg[21]_i_3_n_8\,
      I4 => \xsqr_reg[35]_i_13_n_11\,
      I5 => \xsqr_reg[35]_i_18_n_14\,
      O => \xsqr[29]_i_12_n_0\
    );
\xsqr[29]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \xsqr_reg[35]_i_18_n_15\,
      I1 => \xsqr_reg[35]_i_13_n_12\,
      I2 => \xsqr_reg[21]_i_3_n_9\,
      I3 => \xsqr_reg[21]_i_3_n_10\,
      I4 => \xsqr_reg[21]_i_2_n_8\,
      I5 => \xsqr_reg[35]_i_13_n_13\,
      O => \xsqr[29]_i_13_n_0\
    );
\xsqr[29]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr[29]_i_6_n_0\,
      I1 => \xsqr_reg[35]_i_13_n_13\,
      I2 => \xsqr_reg[21]_i_2_n_8\,
      I3 => \xsqr_reg[21]_i_3_n_10\,
      O => \xsqr[29]_i_14_n_0\
    );
\xsqr[29]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr_reg[35]_i_13_n_14\,
      I1 => \xsqr_reg[21]_i_2_n_9\,
      I2 => \xsqr_reg[21]_i_3_n_11\,
      I3 => \xsqr[29]_i_7_n_0\,
      O => \xsqr[29]_i_15_n_0\
    );
\xsqr[29]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr_reg[35]_i_13_n_15\,
      I1 => \xsqr_reg[21]_i_2_n_10\,
      I2 => \xsqr_reg[21]_i_3_n_12\,
      I3 => \xsqr[29]_i_8_n_0\,
      O => \xsqr[29]_i_16_n_0\
    );
\xsqr[29]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xsqr_reg[21]_i_3_n_13\,
      I1 => \xsqr_reg[21]_i_2_n_11\,
      I2 => \xsqr_reg[21]_i_2_n_12\,
      I3 => \xsqr_reg[21]_i_3_n_14\,
      O => \xsqr[29]_i_17_n_0\
    );
\xsqr[29]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \xsqr_reg[21]_i_2_n_13\,
      I1 => \xsqr_reg[21]_i_3_n_15\,
      I2 => \xsqr_reg[21]_i_2_n_12\,
      I3 => \xsqr_reg[21]_i_3_n_14\,
      O => \xsqr[29]_i_18_n_0\
    );
\xsqr[29]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xsqr_reg[35]_i_17_n_15\,
      I1 => \xsqr_reg[35]_i_13_n_10\,
      I2 => \xsqr_reg[35]_i_18_n_5\,
      O => \xsqr[29]_i_19_n_0\
    );
\xsqr[29]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \xsqr_reg[21]_i_3_n_9\,
      I1 => \xsqr_reg[35]_i_13_n_12\,
      I2 => \xsqr_reg[35]_i_18_n_14\,
      I3 => \xsqr_reg[35]_i_13_n_11\,
      I4 => \xsqr_reg[21]_i_3_n_8\,
      O => \xsqr[29]_i_3_n_0\
    );
\xsqr[29]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \xsqr_reg[35]_i_18_n_15\,
      I1 => \xsqr_reg[21]_i_3_n_9\,
      I2 => \xsqr_reg[35]_i_13_n_12\,
      O => \xsqr[29]_i_4_n_0\
    );
\xsqr[29]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xsqr_reg[21]_i_3_n_9\,
      I1 => \xsqr_reg[35]_i_13_n_12\,
      I2 => \xsqr_reg[35]_i_18_n_15\,
      O => \xsqr[29]_i_5_n_0\
    );
\xsqr[29]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xsqr_reg[35]_i_13_n_14\,
      I1 => \xsqr_reg[21]_i_2_n_9\,
      I2 => \xsqr_reg[21]_i_3_n_11\,
      O => \xsqr[29]_i_6_n_0\
    );
\xsqr[29]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xsqr_reg[35]_i_13_n_15\,
      I1 => \xsqr_reg[21]_i_2_n_10\,
      I2 => \xsqr_reg[21]_i_3_n_12\,
      O => \xsqr[29]_i_7_n_0\
    );
\xsqr[29]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[21]_i_3_n_13\,
      I1 => \xsqr_reg[21]_i_2_n_11\,
      O => \xsqr[29]_i_8_n_0\
    );
\xsqr[29]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[21]_i_3_n_14\,
      I1 => \xsqr_reg[21]_i_2_n_12\,
      O => \xsqr[29]_i_9_n_0\
    );
\xsqr[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(2),
      O => \xsqr[2]_i_1_n_0\
    );
\xsqr[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(12),
      O => \xsqr[30]_i_1_n_0\
    );
\xsqr[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(13),
      O => \xsqr[31]_i_1_n_0\
    );
\xsqr[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(14),
      O => \xsqr[32]_i_1_n_0\
    );
\xsqr[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(15),
      O => \xsqr[33]_i_1_n_0\
    );
\xsqr[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(16),
      O => \xsqr[34]_i_1_n_0\
    );
\xsqr[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr00_in(17),
      O => \xsqr[35]_i_1_n_0\
    );
\xsqr[35]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \xsqr[35]_i_5_n_0\,
      I1 => \xsqr_reg[35]_i_3_n_15\,
      I2 => \xsqr_reg[35]_i_17_n_4\,
      I3 => \xsqr_reg[35]_i_13_n_8\,
      I4 => \xsqr_reg[35]_i_17_n_13\,
      O => \xsqr[35]_i_10_n_0\
    );
\xsqr[35]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \xsqr_reg[35]_i_17_n_14\,
      I1 => \xsqr_reg[35]_i_13_n_9\,
      I2 => \xsqr_reg[35]_i_17_n_13\,
      I3 => \xsqr_reg[35]_i_13_n_8\,
      I4 => \xsqr[35]_i_6_n_0\,
      O => \xsqr[35]_i_11_n_0\
    );
\xsqr[35]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \xsqr[35]_i_7_n_0\,
      I1 => \xsqr_reg[35]_i_17_n_15\,
      I2 => \xsqr_reg[35]_i_18_n_5\,
      I3 => \xsqr_reg[35]_i_13_n_10\,
      I4 => \xsqr_reg[35]_i_17_n_14\,
      I5 => \xsqr_reg[35]_i_13_n_9\,
      O => \xsqr[35]_i_12_n_0\
    );
\xsqr[35]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => A(7),
      I1 => A(8),
      O => \xsqr[35]_i_14_n_0\
    );
\xsqr[35]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => A(6),
      I1 => A(8),
      O => \xsqr[35]_i_15_n_0\
    );
\xsqr[35]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => A(7),
      I1 => A(6),
      O => \xsqr[35]_i_16_n_0\
    );
\xsqr[35]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7777000"
    )
        port map (
      I0 => A(8),
      I1 => A(4),
      I2 => A(7),
      I3 => A(5),
      I4 => A(6),
      O => \xsqr[35]_i_19_n_0\
    );
\xsqr[35]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => A(8),
      I1 => A(3),
      I2 => A(7),
      I3 => A(4),
      I4 => A(5),
      I5 => A(6),
      O => \xsqr[35]_i_20_n_0\
    );
\xsqr[35]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => A(8),
      I1 => A(2),
      I2 => A(7),
      I3 => A(3),
      I4 => A(4),
      I5 => A(6),
      O => \xsqr[35]_i_21_n_0\
    );
\xsqr[35]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => A(8),
      I1 => A(1),
      I2 => A(7),
      I3 => A(2),
      I4 => A(3),
      I5 => A(6),
      O => \xsqr[35]_i_22_n_0\
    );
\xsqr[35]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => A(8),
      I1 => A(0),
      I2 => A(7),
      I3 => A(1),
      O => \xsqr[35]_i_23_n_0\
    );
\xsqr[35]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(1),
      I1 => A(6),
      O => \xsqr[35]_i_24_n_0\
    );
\xsqr[35]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8E11F555"
    )
        port map (
      I0 => A(6),
      I1 => A(7),
      I2 => A(4),
      I3 => A(8),
      I4 => A(5),
      O => \xsqr[35]_i_25_n_0\
    );
\xsqr[35]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EB843C0C903FCF3F"
    )
        port map (
      I0 => A(3),
      I1 => A(5),
      I2 => A(7),
      I3 => A(4),
      I4 => A(8),
      I5 => A(6),
      O => \xsqr[35]_i_26_n_0\
    );
\xsqr[35]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F07070780F8F8F8"
    )
        port map (
      I0 => A(6),
      I1 => A(4),
      I2 => \xsqr[35]_i_43_n_0\,
      I3 => A(2),
      I4 => A(8),
      I5 => \xsqr[35]_i_44_n_0\,
      O => \xsqr[35]_i_27_n_0\
    );
\xsqr[35]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A956A956A95"
    )
        port map (
      I0 => \xsqr[35]_i_22_n_0\,
      I1 => A(8),
      I2 => A(2),
      I3 => \xsqr[35]_i_43_n_0\,
      I4 => A(4),
      I5 => A(6),
      O => \xsqr[35]_i_28_n_0\
    );
\xsqr[35]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"69C399C369336933"
    )
        port map (
      I0 => A(2),
      I1 => \xsqr[35]_i_45_n_0\,
      I2 => A(1),
      I3 => A(7),
      I4 => A(0),
      I5 => A(8),
      O => \xsqr[35]_i_29_n_0\
    );
\xsqr[35]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => A(1),
      I1 => A(7),
      I2 => A(0),
      I3 => A(8),
      I4 => A(6),
      I5 => A(2),
      O => \xsqr[35]_i_30_n_0\
    );
\xsqr[35]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => A(6),
      I1 => A(1),
      I2 => A(7),
      I3 => A(0),
      O => \xsqr[35]_i_31_n_0\
    );
\xsqr[35]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(0),
      I1 => A(6),
      O => \xsqr[35]_i_32_n_0\
    );
\xsqr[35]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => A(7),
      I1 => A(5),
      I2 => A(8),
      I3 => A(4),
      O => \xsqr[35]_i_33_n_0\
    );
\xsqr[35]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => A(5),
      I1 => A(7),
      I2 => A(4),
      I3 => A(8),
      O => \xsqr[35]_i_34_n_0\
    );
\xsqr[35]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(4),
      I1 => A(5),
      O => \xsqr[35]_i_35_n_0\
    );
\xsqr[35]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => A(4),
      I1 => A(7),
      I2 => A(8),
      I3 => A(5),
      O => \xsqr[35]_i_36_n_0\
    );
\xsqr[35]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => A(6),
      I1 => A(3),
      I2 => A(8),
      I3 => A(4),
      I4 => A(7),
      I5 => A(5),
      O => \xsqr[35]_i_37_n_0\
    );
\xsqr[35]_i_38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D22287772DDD8777"
    )
        port map (
      I0 => A(4),
      I1 => A(7),
      I2 => A(3),
      I3 => A(8),
      I4 => A(5),
      I5 => A(6),
      O => \xsqr[35]_i_38_n_0\
    );
\xsqr[35]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => A(7),
      I1 => A(2),
      I2 => A(8),
      I3 => A(1),
      O => \xsqr[35]_i_39_n_0\
    );
\xsqr[35]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xsqr_reg[35]_i_17_n_13\,
      I1 => \xsqr_reg[35]_i_13_n_8\,
      I2 => \xsqr_reg[35]_i_17_n_4\,
      I3 => \xsqr_reg[35]_i_3_n_15\,
      O => \xsqr[35]_i_4_n_0\
    );
\xsqr[35]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => A(2),
      I1 => A(7),
      I2 => A(1),
      I3 => A(8),
      O => \xsqr[35]_i_40_n_0\
    );
\xsqr[35]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => A(1),
      I1 => A(7),
      I2 => A(8),
      I3 => A(2),
      O => \xsqr[35]_i_41_n_0\
    );
\xsqr[35]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => A(6),
      I1 => A(0),
      I2 => A(8),
      I3 => A(1),
      I4 => A(7),
      I5 => A(2),
      O => \xsqr[35]_i_42_n_0\
    );
\xsqr[35]_i_43\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(3),
      I1 => A(7),
      O => \xsqr[35]_i_43_n_0\
    );
\xsqr[35]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => A(6),
      I1 => A(5),
      I2 => A(8),
      I3 => A(3),
      I4 => A(7),
      I5 => A(4),
      O => \xsqr[35]_i_44_n_0\
    );
\xsqr[35]_i_45\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(3),
      I1 => A(6),
      O => \xsqr[35]_i_45_n_0\
    );
\xsqr[35]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xsqr_reg[35]_i_17_n_14\,
      I1 => \xsqr_reg[35]_i_13_n_9\,
      I2 => \xsqr_reg[35]_i_17_n_13\,
      I3 => \xsqr_reg[35]_i_13_n_8\,
      O => \xsqr[35]_i_5_n_0\
    );
\xsqr[35]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \xsqr_reg[35]_i_17_n_14\,
      I1 => \xsqr_reg[35]_i_13_n_9\,
      I2 => \xsqr_reg[35]_i_17_n_15\,
      I3 => \xsqr_reg[35]_i_18_n_5\,
      I4 => \xsqr_reg[35]_i_13_n_10\,
      O => \xsqr[35]_i_6_n_0\
    );
\xsqr[35]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \xsqr_reg[21]_i_3_n_8\,
      I1 => \xsqr_reg[35]_i_18_n_14\,
      I2 => \xsqr_reg[35]_i_13_n_11\,
      I3 => \xsqr_reg[35]_i_18_n_5\,
      I4 => \xsqr_reg[35]_i_13_n_10\,
      I5 => \xsqr_reg[35]_i_17_n_15\,
      O => \xsqr[35]_i_7_n_0\
    );
\xsqr[35]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \xsqr_reg[35]_i_3_n_15\,
      I1 => \xsqr_reg[35]_i_17_n_4\,
      I2 => \xsqr_reg[35]_i_3_n_14\,
      I3 => \xsqr_reg[35]_i_3_n_13\,
      O => \xsqr[35]_i_8_n_0\
    );
\xsqr[35]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \xsqr_reg[35]_i_13_n_8\,
      I1 => \xsqr_reg[35]_i_17_n_13\,
      I2 => \xsqr_reg[35]_i_3_n_15\,
      I3 => \xsqr_reg[35]_i_17_n_4\,
      I4 => \xsqr_reg[35]_i_3_n_14\,
      O => \xsqr[35]_i_9_n_0\
    );
\xsqr[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => \dx_reg_n_0_[18]\,
      O => \xsqr[36]_i_1_n_0\
    );
\xsqr[38]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(2),
      O => \xsqr[38]_i_1_n_0\
    );
\xsqr[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \xsqr_reg[39]_i_2_n_13\,
      I1 => \xsqr_reg[39]_i_3_n_15\,
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \xsqr[39]_i_1_n_0\
    );
\xsqr[39]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xsqr[39]_i_4_n_0\,
      I1 => \xsqr[39]_i_31_n_0\,
      I2 => \dx_reg_n_0_[20]\,
      I3 => \dx_reg_n_0_[24]\,
      O => \xsqr[39]_i_10_n_0\
    );
\xsqr[39]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xsqr[39]_i_5_n_0\,
      I1 => \dx_reg_n_0_[23]\,
      I2 => \dx_reg_n_0_[20]\,
      I3 => \xsqr[39]_i_32_n_0\,
      I4 => \dx_reg_n_0_[18]\,
      I5 => \dx_reg_n_0_[25]\,
      O => \xsqr[39]_i_11_n_0\
    );
\xsqr[39]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \xsqr[39]_i_6_n_0\,
      I1 => \dx_reg_n_0_[22]\,
      I2 => \dx_reg_n_0_[20]\,
      I3 => \dx_reg_n_0_[23]\,
      I4 => \dx_reg_n_0_[19]\,
      I5 => \xsqr[39]_i_33_n_0\,
      O => \xsqr[39]_i_12_n_0\
    );
\xsqr[39]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xsqr[39]_i_7_n_0\,
      I1 => \dx_reg_n_0_[22]\,
      I2 => \dx_reg_n_0_[19]\,
      I3 => \xsqr[39]_i_21_n_0\,
      I4 => \dx_reg_n_0_[18]\,
      I5 => \dx_reg_n_0_[23]\,
      O => \xsqr[39]_i_13_n_0\
    );
\xsqr[39]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dx_reg_n_0_[19]\,
      I1 => \dx_reg_n_0_[20]\,
      I2 => \dx_reg_n_0_[21]\,
      I3 => \dx_reg_n_0_[22]\,
      I4 => \dx_reg_n_0_[18]\,
      O => \xsqr[39]_i_14_n_0\
    );
\xsqr[39]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dx_reg_n_0_[21]\,
      I1 => \dx_reg_n_0_[20]\,
      I2 => \dx_reg_n_0_[18]\,
      O => \xsqr[39]_i_15_n_0\
    );
\xsqr[39]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dx_reg_n_0_[19]\,
      I1 => \dx_reg_n_0_[18]\,
      O => \xsqr[39]_i_16_n_0\
    );
\xsqr[39]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[21]\,
      I1 => \dx_reg_n_0_[25]\,
      O => \xsqr[39]_i_17_n_0\
    );
\xsqr[39]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[21]\,
      I1 => \dx_reg_n_0_[24]\,
      O => \xsqr[39]_i_18_n_0\
    );
\xsqr[39]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[20]\,
      I1 => \dx_reg_n_0_[23]\,
      O => \xsqr[39]_i_19_n_0\
    );
\xsqr[39]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"956A6A6A"
    )
        port map (
      I0 => \dx_reg_n_0_[21]\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dx_reg_n_0_[23]\,
      I3 => \dx_reg_n_0_[20]\,
      I4 => \dx_reg_n_0_[22]\,
      O => \xsqr[39]_i_20_n_0\
    );
\xsqr[39]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[20]\,
      I1 => \dx_reg_n_0_[21]\,
      O => \xsqr[39]_i_21_n_0\
    );
\xsqr[39]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[19]\,
      I1 => \dx_reg_n_0_[21]\,
      O => \xsqr[39]_i_22_n_0\
    );
\xsqr[39]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dx_reg_n_0_[22]\,
      I1 => \dx_reg_n_0_[23]\,
      I2 => \dx_reg_n_0_[24]\,
      I3 => \dx_reg_n_0_[25]\,
      I4 => \dx_reg_n_0_[21]\,
      O => \xsqr[39]_i_23_n_0\
    );
\xsqr[39]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dx_reg_n_0_[24]\,
      I1 => \dx_reg_n_0_[23]\,
      I2 => \dx_reg_n_0_[21]\,
      O => \xsqr[39]_i_24_n_0\
    );
\xsqr[39]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dx_reg_n_0_[22]\,
      I1 => \dx_reg_n_0_[21]\,
      O => \xsqr[39]_i_25_n_0\
    );
\xsqr[39]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17A08800"
    )
        port map (
      I0 => \dx_reg_n_0_[21]\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dx_reg_n_0_[22]\,
      I3 => \dx_reg_n_0_[23]\,
      I4 => \dx_reg_n_0_[20]\,
      O => \xsqr[39]_i_26_n_0\
    );
\xsqr[39]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"663C963C66CC66CC"
    )
        port map (
      I0 => \dx_reg_n_0_[20]\,
      I1 => \dx_reg_n_0_[21]\,
      I2 => \dx_reg_n_0_[19]\,
      I3 => \dx_reg_n_0_[22]\,
      I4 => \dx_reg_n_0_[18]\,
      I5 => \dx_reg_n_0_[23]\,
      O => \xsqr[39]_i_27_n_0\
    );
\xsqr[39]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dx_reg_n_0_[18]\,
      I1 => \dx_reg_n_0_[23]\,
      I2 => \dx_reg_n_0_[19]\,
      I3 => \dx_reg_n_0_[22]\,
      I4 => \dx_reg_n_0_[21]\,
      I5 => \dx_reg_n_0_[20]\,
      O => \xsqr[39]_i_28_n_0\
    );
\xsqr[39]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dx_reg_n_0_[21]\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dx_reg_n_0_[22]\,
      I3 => \dx_reg_n_0_[18]\,
      O => \xsqr[39]_i_29_n_0\
    );
\xsqr[39]_i_30\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[18]\,
      I1 => \dx_reg_n_0_[21]\,
      O => \xsqr[39]_i_30_n_0\
    );
\xsqr[39]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dx_reg_n_0_[26]\,
      I1 => \dx_reg_n_0_[18]\,
      I2 => \dx_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[19]\,
      O => \xsqr[39]_i_31_n_0\
    );
\xsqr[39]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[19]\,
      I1 => \dx_reg_n_0_[24]\,
      O => \xsqr[39]_i_32_n_0\
    );
\xsqr[39]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[18]\,
      I1 => \dx_reg_n_0_[24]\,
      O => \xsqr[39]_i_33_n_0\
    );
\xsqr[39]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dx_reg_n_0_[23]\,
      I1 => \dx_reg_n_0_[20]\,
      I2 => \dx_reg_n_0_[24]\,
      I3 => \dx_reg_n_0_[19]\,
      I4 => \dx_reg_n_0_[18]\,
      I5 => \dx_reg_n_0_[25]\,
      O => \xsqr[39]_i_4_n_0\
    );
\xsqr[39]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dx_reg_n_0_[22]\,
      I1 => \dx_reg_n_0_[20]\,
      I2 => \dx_reg_n_0_[23]\,
      I3 => \dx_reg_n_0_[19]\,
      I4 => \dx_reg_n_0_[18]\,
      I5 => \dx_reg_n_0_[24]\,
      O => \xsqr[39]_i_5_n_0\
    );
\xsqr[39]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dx_reg_n_0_[22]\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dx_reg_n_0_[21]\,
      I3 => \dx_reg_n_0_[20]\,
      I4 => \dx_reg_n_0_[18]\,
      I5 => \dx_reg_n_0_[23]\,
      O => \xsqr[39]_i_6_n_0\
    );
\xsqr[39]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[19]\,
      I1 => \dx_reg_n_0_[20]\,
      O => \xsqr[39]_i_7_n_0\
    );
\xsqr[39]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \dx_reg_n_0_[21]\,
      I1 => \dx_reg_n_0_[20]\,
      I2 => \dx_reg_n_0_[19]\,
      O => \xsqr[39]_i_8_n_0\
    );
\xsqr[39]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[18]\,
      I1 => \dx_reg_n_0_[21]\,
      O => \xsqr[39]_i_9_n_0\
    );
\xsqr[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \xsqr_reg[3]_i_2_n_13\,
      I1 => \xsqr_reg[3]_i_3_n_15\,
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \xsqr[3]_i_1_n_0\
    );
\xsqr[3]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xsqr[3]_i_4_n_0\,
      I1 => \xsqr[3]_i_31_n_0\,
      I2 => \dx_reg_n_0_[2]\,
      I3 => \dx_reg_n_0_[6]\,
      O => \xsqr[3]_i_10_n_0\
    );
\xsqr[3]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xsqr[3]_i_5_n_0\,
      I1 => \dx_reg_n_0_[5]\,
      I2 => \dx_reg_n_0_[2]\,
      I3 => \xsqr[3]_i_32_n_0\,
      I4 => \dx_reg_n_0_[0]\,
      I5 => \dx_reg_n_0_[7]\,
      O => \xsqr[3]_i_11_n_0\
    );
\xsqr[3]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \xsqr[3]_i_6_n_0\,
      I1 => \dx_reg_n_0_[4]\,
      I2 => \dx_reg_n_0_[2]\,
      I3 => \dx_reg_n_0_[5]\,
      I4 => \dx_reg_n_0_[1]\,
      I5 => \xsqr[3]_i_33_n_0\,
      O => \xsqr[3]_i_12_n_0\
    );
\xsqr[3]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xsqr[3]_i_7_n_0\,
      I1 => \dx_reg_n_0_[4]\,
      I2 => \dx_reg_n_0_[1]\,
      I3 => \xsqr[3]_i_21_n_0\,
      I4 => \dx_reg_n_0_[0]\,
      I5 => \dx_reg_n_0_[5]\,
      O => \xsqr[3]_i_13_n_0\
    );
\xsqr[3]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dx_reg_n_0_[1]\,
      I1 => \dx_reg_n_0_[2]\,
      I2 => \dx_reg_n_0_[3]\,
      I3 => \dx_reg_n_0_[4]\,
      I4 => \dx_reg_n_0_[0]\,
      O => \xsqr[3]_i_14_n_0\
    );
\xsqr[3]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dx_reg_n_0_[3]\,
      I1 => \dx_reg_n_0_[2]\,
      I2 => \dx_reg_n_0_[0]\,
      O => \xsqr[3]_i_15_n_0\
    );
\xsqr[3]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dx_reg_n_0_[1]\,
      I1 => \dx_reg_n_0_[0]\,
      O => \xsqr[3]_i_16_n_0\
    );
\xsqr[3]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[3]\,
      I1 => \dx_reg_n_0_[7]\,
      O => \xsqr[3]_i_17_n_0\
    );
\xsqr[3]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[3]\,
      I1 => \dx_reg_n_0_[6]\,
      O => \xsqr[3]_i_18_n_0\
    );
\xsqr[3]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[2]\,
      I1 => \dx_reg_n_0_[5]\,
      O => \xsqr[3]_i_19_n_0\
    );
\xsqr[3]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"956A6A6A"
    )
        port map (
      I0 => \dx_reg_n_0_[3]\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dx_reg_n_0_[5]\,
      I3 => \dx_reg_n_0_[2]\,
      I4 => \dx_reg_n_0_[4]\,
      O => \xsqr[3]_i_20_n_0\
    );
\xsqr[3]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[2]\,
      I1 => \dx_reg_n_0_[3]\,
      O => \xsqr[3]_i_21_n_0\
    );
\xsqr[3]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[1]\,
      I1 => \dx_reg_n_0_[3]\,
      O => \xsqr[3]_i_22_n_0\
    );
\xsqr[3]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dx_reg_n_0_[4]\,
      I1 => \dx_reg_n_0_[5]\,
      I2 => \dx_reg_n_0_[6]\,
      I3 => \dx_reg_n_0_[7]\,
      I4 => \dx_reg_n_0_[3]\,
      O => \xsqr[3]_i_23_n_0\
    );
\xsqr[3]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dx_reg_n_0_[6]\,
      I1 => \dx_reg_n_0_[5]\,
      I2 => \dx_reg_n_0_[3]\,
      O => \xsqr[3]_i_24_n_0\
    );
\xsqr[3]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dx_reg_n_0_[4]\,
      I1 => \dx_reg_n_0_[3]\,
      O => \xsqr[3]_i_25_n_0\
    );
\xsqr[3]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17A08800"
    )
        port map (
      I0 => \dx_reg_n_0_[3]\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dx_reg_n_0_[4]\,
      I3 => \dx_reg_n_0_[5]\,
      I4 => \dx_reg_n_0_[2]\,
      O => \xsqr[3]_i_26_n_0\
    );
\xsqr[3]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"663C963C66CC66CC"
    )
        port map (
      I0 => \dx_reg_n_0_[2]\,
      I1 => \dx_reg_n_0_[3]\,
      I2 => \dx_reg_n_0_[1]\,
      I3 => \dx_reg_n_0_[4]\,
      I4 => \dx_reg_n_0_[0]\,
      I5 => \dx_reg_n_0_[5]\,
      O => \xsqr[3]_i_27_n_0\
    );
\xsqr[3]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dx_reg_n_0_[0]\,
      I1 => \dx_reg_n_0_[5]\,
      I2 => \dx_reg_n_0_[1]\,
      I3 => \dx_reg_n_0_[4]\,
      I4 => \dx_reg_n_0_[3]\,
      I5 => \dx_reg_n_0_[2]\,
      O => \xsqr[3]_i_28_n_0\
    );
\xsqr[3]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dx_reg_n_0_[3]\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dx_reg_n_0_[4]\,
      I3 => \dx_reg_n_0_[0]\,
      O => \xsqr[3]_i_29_n_0\
    );
\xsqr[3]_i_30\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[0]\,
      I1 => \dx_reg_n_0_[3]\,
      O => \xsqr[3]_i_30_n_0\
    );
\xsqr[3]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dx_reg_n_0_[8]\,
      I1 => \dx_reg_n_0_[0]\,
      I2 => \dx_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[1]\,
      O => \xsqr[3]_i_31_n_0\
    );
\xsqr[3]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[1]\,
      I1 => \dx_reg_n_0_[6]\,
      O => \xsqr[3]_i_32_n_0\
    );
\xsqr[3]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[0]\,
      I1 => \dx_reg_n_0_[6]\,
      O => \xsqr[3]_i_33_n_0\
    );
\xsqr[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dx_reg_n_0_[5]\,
      I1 => \dx_reg_n_0_[2]\,
      I2 => \dx_reg_n_0_[6]\,
      I3 => \dx_reg_n_0_[1]\,
      I4 => \dx_reg_n_0_[0]\,
      I5 => \dx_reg_n_0_[7]\,
      O => \xsqr[3]_i_4_n_0\
    );
\xsqr[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dx_reg_n_0_[4]\,
      I1 => \dx_reg_n_0_[2]\,
      I2 => \dx_reg_n_0_[5]\,
      I3 => \dx_reg_n_0_[1]\,
      I4 => \dx_reg_n_0_[0]\,
      I5 => \dx_reg_n_0_[6]\,
      O => \xsqr[3]_i_5_n_0\
    );
\xsqr[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dx_reg_n_0_[4]\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dx_reg_n_0_[3]\,
      I3 => \dx_reg_n_0_[2]\,
      I4 => \dx_reg_n_0_[0]\,
      I5 => \dx_reg_n_0_[5]\,
      O => \xsqr[3]_i_6_n_0\
    );
\xsqr[3]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[1]\,
      I1 => \dx_reg_n_0_[2]\,
      O => \xsqr[3]_i_7_n_0\
    );
\xsqr[3]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \dx_reg_n_0_[3]\,
      I1 => \dx_reg_n_0_[2]\,
      I2 => \dx_reg_n_0_[1]\,
      O => \xsqr[3]_i_8_n_0\
    );
\xsqr[3]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[0]\,
      I1 => \dx_reg_n_0_[3]\,
      O => \xsqr[3]_i_9_n_0\
    );
\xsqr[40]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(4),
      O => \xsqr[40]_i_1_n_0\
    );
\xsqr[41]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(5),
      O => \xsqr[41]_i_1_n_0\
    );
\xsqr[42]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(6),
      O => \xsqr[42]_i_1_n_0\
    );
\xsqr[43]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(7),
      O => \xsqr[43]_i_1_n_0\
    );
\xsqr[44]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(8),
      O => \xsqr[44]_i_1_n_0\
    );
\xsqr[45]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(9),
      O => \xsqr[45]_i_1_n_0\
    );
\xsqr[46]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(10),
      O => \xsqr[46]_i_1_n_0\
    );
\xsqr[47]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(11),
      O => \xsqr[47]_i_1_n_0\
    );
\xsqr[47]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[39]_i_3_n_15\,
      I1 => \xsqr_reg[39]_i_2_n_13\,
      O => \xsqr[47]_i_10_n_0\
    );
\xsqr[47]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \xsqr_reg[39]_i_3_n_9\,
      I1 => \xsqr_reg[53]_i_13_n_12\,
      I2 => \xsqr_reg[53]_i_18_n_14\,
      I3 => \xsqr_reg[53]_i_13_n_11\,
      I4 => \xsqr_reg[39]_i_3_n_8\,
      I5 => \xsqr[47]_i_19_n_0\,
      O => \xsqr[47]_i_11_n_0\
    );
\xsqr[47]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \xsqr_reg[53]_i_18_n_15\,
      I1 => \xsqr_reg[39]_i_3_n_9\,
      I2 => \xsqr_reg[53]_i_13_n_12\,
      I3 => \xsqr_reg[39]_i_3_n_8\,
      I4 => \xsqr_reg[53]_i_13_n_11\,
      I5 => \xsqr_reg[53]_i_18_n_14\,
      O => \xsqr[47]_i_12_n_0\
    );
\xsqr[47]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \xsqr_reg[53]_i_18_n_15\,
      I1 => \xsqr_reg[53]_i_13_n_12\,
      I2 => \xsqr_reg[39]_i_3_n_9\,
      I3 => \xsqr_reg[39]_i_3_n_10\,
      I4 => \xsqr_reg[39]_i_2_n_8\,
      I5 => \xsqr_reg[53]_i_13_n_13\,
      O => \xsqr[47]_i_13_n_0\
    );
\xsqr[47]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr[47]_i_6_n_0\,
      I1 => \xsqr_reg[53]_i_13_n_13\,
      I2 => \xsqr_reg[39]_i_2_n_8\,
      I3 => \xsqr_reg[39]_i_3_n_10\,
      O => \xsqr[47]_i_14_n_0\
    );
\xsqr[47]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr_reg[53]_i_13_n_14\,
      I1 => \xsqr_reg[39]_i_2_n_9\,
      I2 => \xsqr_reg[39]_i_3_n_11\,
      I3 => \xsqr[47]_i_7_n_0\,
      O => \xsqr[47]_i_15_n_0\
    );
\xsqr[47]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr_reg[53]_i_13_n_15\,
      I1 => \xsqr_reg[39]_i_2_n_10\,
      I2 => \xsqr_reg[39]_i_3_n_12\,
      I3 => \xsqr[47]_i_8_n_0\,
      O => \xsqr[47]_i_16_n_0\
    );
\xsqr[47]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xsqr_reg[39]_i_3_n_13\,
      I1 => \xsqr_reg[39]_i_2_n_11\,
      I2 => \xsqr_reg[39]_i_2_n_12\,
      I3 => \xsqr_reg[39]_i_3_n_14\,
      O => \xsqr[47]_i_17_n_0\
    );
\xsqr[47]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \xsqr_reg[39]_i_2_n_13\,
      I1 => \xsqr_reg[39]_i_3_n_15\,
      I2 => \xsqr_reg[39]_i_2_n_12\,
      I3 => \xsqr_reg[39]_i_3_n_14\,
      O => \xsqr[47]_i_18_n_0\
    );
\xsqr[47]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xsqr_reg[53]_i_17_n_15\,
      I1 => \xsqr_reg[53]_i_13_n_10\,
      I2 => \xsqr_reg[53]_i_18_n_5\,
      O => \xsqr[47]_i_19_n_0\
    );
\xsqr[47]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \xsqr_reg[39]_i_3_n_9\,
      I1 => \xsqr_reg[53]_i_13_n_12\,
      I2 => \xsqr_reg[53]_i_18_n_14\,
      I3 => \xsqr_reg[53]_i_13_n_11\,
      I4 => \xsqr_reg[39]_i_3_n_8\,
      O => \xsqr[47]_i_3_n_0\
    );
\xsqr[47]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \xsqr_reg[53]_i_18_n_15\,
      I1 => \xsqr_reg[39]_i_3_n_9\,
      I2 => \xsqr_reg[53]_i_13_n_12\,
      O => \xsqr[47]_i_4_n_0\
    );
\xsqr[47]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xsqr_reg[39]_i_3_n_9\,
      I1 => \xsqr_reg[53]_i_13_n_12\,
      I2 => \xsqr_reg[53]_i_18_n_15\,
      O => \xsqr[47]_i_5_n_0\
    );
\xsqr[47]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xsqr_reg[53]_i_13_n_14\,
      I1 => \xsqr_reg[39]_i_2_n_9\,
      I2 => \xsqr_reg[39]_i_3_n_11\,
      O => \xsqr[47]_i_6_n_0\
    );
\xsqr[47]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xsqr_reg[53]_i_13_n_15\,
      I1 => \xsqr_reg[39]_i_2_n_10\,
      I2 => \xsqr_reg[39]_i_3_n_12\,
      O => \xsqr[47]_i_7_n_0\
    );
\xsqr[47]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[39]_i_3_n_13\,
      I1 => \xsqr_reg[39]_i_2_n_11\,
      O => \xsqr[47]_i_8_n_0\
    );
\xsqr[47]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[39]_i_3_n_14\,
      I1 => \xsqr_reg[39]_i_2_n_12\,
      O => \xsqr[47]_i_9_n_0\
    );
\xsqr[48]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(12),
      O => \xsqr[48]_i_1_n_0\
    );
\xsqr[49]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(13),
      O => \xsqr[49]_i_1_n_0\
    );
\xsqr[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(4),
      O => \xsqr[4]_i_1_n_0\
    );
\xsqr[50]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(14),
      O => \xsqr[50]_i_1_n_0\
    );
\xsqr[51]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(15),
      O => \xsqr[51]_i_1_n_0\
    );
\xsqr[52]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(16),
      O => \xsqr[52]_i_1_n_0\
    );
\xsqr[53]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr01_in(17),
      O => \xsqr[53]_i_1_n_0\
    );
\xsqr[53]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \xsqr[53]_i_5_n_0\,
      I1 => \xsqr_reg[53]_i_3_n_15\,
      I2 => \xsqr_reg[53]_i_17_n_4\,
      I3 => \xsqr_reg[53]_i_13_n_8\,
      I4 => \xsqr_reg[53]_i_17_n_13\,
      O => \xsqr[53]_i_10_n_0\
    );
\xsqr[53]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \xsqr_reg[53]_i_17_n_14\,
      I1 => \xsqr_reg[53]_i_13_n_9\,
      I2 => \xsqr_reg[53]_i_17_n_13\,
      I3 => \xsqr_reg[53]_i_13_n_8\,
      I4 => \xsqr[53]_i_6_n_0\,
      O => \xsqr[53]_i_11_n_0\
    );
\xsqr[53]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \xsqr[53]_i_7_n_0\,
      I1 => \xsqr_reg[53]_i_17_n_15\,
      I2 => \xsqr_reg[53]_i_18_n_5\,
      I3 => \xsqr_reg[53]_i_13_n_10\,
      I4 => \xsqr_reg[53]_i_17_n_14\,
      I5 => \xsqr_reg[53]_i_13_n_9\,
      O => \xsqr[53]_i_12_n_0\
    );
\xsqr[53]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \dx_reg_n_0_[25]\,
      I1 => \dx_reg_n_0_[26]\,
      O => \xsqr[53]_i_14_n_0\
    );
\xsqr[53]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \dx_reg_n_0_[24]\,
      I1 => \dx_reg_n_0_[26]\,
      O => \xsqr[53]_i_15_n_0\
    );
\xsqr[53]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dx_reg_n_0_[25]\,
      I1 => \dx_reg_n_0_[24]\,
      O => \xsqr[53]_i_16_n_0\
    );
\xsqr[53]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7777000"
    )
        port map (
      I0 => \dx_reg_n_0_[26]\,
      I1 => \dx_reg_n_0_[22]\,
      I2 => \dx_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[23]\,
      I4 => \dx_reg_n_0_[24]\,
      O => \xsqr[53]_i_19_n_0\
    );
\xsqr[53]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dx_reg_n_0_[26]\,
      I1 => \dx_reg_n_0_[21]\,
      I2 => \dx_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[22]\,
      I4 => \dx_reg_n_0_[23]\,
      I5 => \dx_reg_n_0_[24]\,
      O => \xsqr[53]_i_20_n_0\
    );
\xsqr[53]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dx_reg_n_0_[26]\,
      I1 => \dx_reg_n_0_[20]\,
      I2 => \dx_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[21]\,
      I4 => \dx_reg_n_0_[22]\,
      I5 => \dx_reg_n_0_[24]\,
      O => \xsqr[53]_i_21_n_0\
    );
\xsqr[53]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dx_reg_n_0_[26]\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dx_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[20]\,
      I4 => \dx_reg_n_0_[21]\,
      I5 => \dx_reg_n_0_[24]\,
      O => \xsqr[53]_i_22_n_0\
    );
\xsqr[53]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => \dx_reg_n_0_[26]\,
      I1 => \dx_reg_n_0_[18]\,
      I2 => \dx_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[19]\,
      O => \xsqr[53]_i_23_n_0\
    );
\xsqr[53]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[19]\,
      I1 => \dx_reg_n_0_[24]\,
      O => \xsqr[53]_i_24_n_0\
    );
\xsqr[53]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8E11F555"
    )
        port map (
      I0 => \dx_reg_n_0_[24]\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dx_reg_n_0_[22]\,
      I3 => \dx_reg_n_0_[26]\,
      I4 => \dx_reg_n_0_[23]\,
      O => \xsqr[53]_i_25_n_0\
    );
\xsqr[53]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EB843C0C903FCF3F"
    )
        port map (
      I0 => \dx_reg_n_0_[21]\,
      I1 => \dx_reg_n_0_[23]\,
      I2 => \dx_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[22]\,
      I4 => \dx_reg_n_0_[26]\,
      I5 => \dx_reg_n_0_[24]\,
      O => \xsqr[53]_i_26_n_0\
    );
\xsqr[53]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F07070780F8F8F8"
    )
        port map (
      I0 => \dx_reg_n_0_[24]\,
      I1 => \dx_reg_n_0_[22]\,
      I2 => \xsqr[53]_i_43_n_0\,
      I3 => \dx_reg_n_0_[20]\,
      I4 => \dx_reg_n_0_[26]\,
      I5 => \xsqr[53]_i_44_n_0\,
      O => \xsqr[53]_i_27_n_0\
    );
\xsqr[53]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A956A956A95"
    )
        port map (
      I0 => \xsqr[53]_i_22_n_0\,
      I1 => \dx_reg_n_0_[26]\,
      I2 => \dx_reg_n_0_[20]\,
      I3 => \xsqr[53]_i_43_n_0\,
      I4 => \dx_reg_n_0_[22]\,
      I5 => \dx_reg_n_0_[24]\,
      O => \xsqr[53]_i_28_n_0\
    );
\xsqr[53]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"69C399C369336933"
    )
        port map (
      I0 => \dx_reg_n_0_[20]\,
      I1 => \xsqr[53]_i_45_n_0\,
      I2 => \dx_reg_n_0_[19]\,
      I3 => \dx_reg_n_0_[25]\,
      I4 => \dx_reg_n_0_[18]\,
      I5 => \dx_reg_n_0_[26]\,
      O => \xsqr[53]_i_29_n_0\
    );
\xsqr[53]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dx_reg_n_0_[19]\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dx_reg_n_0_[18]\,
      I3 => \dx_reg_n_0_[26]\,
      I4 => \dx_reg_n_0_[24]\,
      I5 => \dx_reg_n_0_[20]\,
      O => \xsqr[53]_i_30_n_0\
    );
\xsqr[53]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dx_reg_n_0_[24]\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dx_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[18]\,
      O => \xsqr[53]_i_31_n_0\
    );
\xsqr[53]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[18]\,
      I1 => \dx_reg_n_0_[24]\,
      O => \xsqr[53]_i_32_n_0\
    );
\xsqr[53]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dx_reg_n_0_[25]\,
      I1 => \dx_reg_n_0_[23]\,
      I2 => \dx_reg_n_0_[26]\,
      I3 => \dx_reg_n_0_[22]\,
      O => \xsqr[53]_i_33_n_0\
    );
\xsqr[53]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dx_reg_n_0_[23]\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dx_reg_n_0_[22]\,
      I3 => \dx_reg_n_0_[26]\,
      O => \xsqr[53]_i_34_n_0\
    );
\xsqr[53]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[22]\,
      I1 => \dx_reg_n_0_[23]\,
      O => \xsqr[53]_i_35_n_0\
    );
\xsqr[53]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dx_reg_n_0_[22]\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dx_reg_n_0_[26]\,
      I3 => \dx_reg_n_0_[23]\,
      O => \xsqr[53]_i_36_n_0\
    );
\xsqr[53]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dx_reg_n_0_[24]\,
      I1 => \dx_reg_n_0_[21]\,
      I2 => \dx_reg_n_0_[26]\,
      I3 => \dx_reg_n_0_[22]\,
      I4 => \dx_reg_n_0_[25]\,
      I5 => \dx_reg_n_0_[23]\,
      O => \xsqr[53]_i_37_n_0\
    );
\xsqr[53]_i_38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D22287772DDD8777"
    )
        port map (
      I0 => \dx_reg_n_0_[22]\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dx_reg_n_0_[21]\,
      I3 => \dx_reg_n_0_[26]\,
      I4 => \dx_reg_n_0_[23]\,
      I5 => \dx_reg_n_0_[24]\,
      O => \xsqr[53]_i_38_n_0\
    );
\xsqr[53]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dx_reg_n_0_[25]\,
      I1 => \dx_reg_n_0_[20]\,
      I2 => \dx_reg_n_0_[26]\,
      I3 => \dx_reg_n_0_[19]\,
      O => \xsqr[53]_i_39_n_0\
    );
\xsqr[53]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xsqr_reg[53]_i_17_n_13\,
      I1 => \xsqr_reg[53]_i_13_n_8\,
      I2 => \xsqr_reg[53]_i_17_n_4\,
      I3 => \xsqr_reg[53]_i_3_n_15\,
      O => \xsqr[53]_i_4_n_0\
    );
\xsqr[53]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dx_reg_n_0_[20]\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dx_reg_n_0_[19]\,
      I3 => \dx_reg_n_0_[26]\,
      O => \xsqr[53]_i_40_n_0\
    );
\xsqr[53]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dx_reg_n_0_[19]\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dx_reg_n_0_[26]\,
      I3 => \dx_reg_n_0_[20]\,
      O => \xsqr[53]_i_41_n_0\
    );
\xsqr[53]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dx_reg_n_0_[24]\,
      I1 => \dx_reg_n_0_[18]\,
      I2 => \dx_reg_n_0_[26]\,
      I3 => \dx_reg_n_0_[19]\,
      I4 => \dx_reg_n_0_[25]\,
      I5 => \dx_reg_n_0_[20]\,
      O => \xsqr[53]_i_42_n_0\
    );
\xsqr[53]_i_43\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[21]\,
      I1 => \dx_reg_n_0_[25]\,
      O => \xsqr[53]_i_43_n_0\
    );
\xsqr[53]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dx_reg_n_0_[24]\,
      I1 => \dx_reg_n_0_[23]\,
      I2 => \dx_reg_n_0_[26]\,
      I3 => \dx_reg_n_0_[21]\,
      I4 => \dx_reg_n_0_[25]\,
      I5 => \dx_reg_n_0_[22]\,
      O => \xsqr[53]_i_44_n_0\
    );
\xsqr[53]_i_45\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[21]\,
      I1 => \dx_reg_n_0_[24]\,
      O => \xsqr[53]_i_45_n_0\
    );
\xsqr[53]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xsqr_reg[53]_i_17_n_14\,
      I1 => \xsqr_reg[53]_i_13_n_9\,
      I2 => \xsqr_reg[53]_i_17_n_13\,
      I3 => \xsqr_reg[53]_i_13_n_8\,
      O => \xsqr[53]_i_5_n_0\
    );
\xsqr[53]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \xsqr_reg[53]_i_17_n_14\,
      I1 => \xsqr_reg[53]_i_13_n_9\,
      I2 => \xsqr_reg[53]_i_17_n_15\,
      I3 => \xsqr_reg[53]_i_18_n_5\,
      I4 => \xsqr_reg[53]_i_13_n_10\,
      O => \xsqr[53]_i_6_n_0\
    );
\xsqr[53]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \xsqr_reg[39]_i_3_n_8\,
      I1 => \xsqr_reg[53]_i_18_n_14\,
      I2 => \xsqr_reg[53]_i_13_n_11\,
      I3 => \xsqr_reg[53]_i_18_n_5\,
      I4 => \xsqr_reg[53]_i_13_n_10\,
      I5 => \xsqr_reg[53]_i_17_n_15\,
      O => \xsqr[53]_i_7_n_0\
    );
\xsqr[53]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \xsqr_reg[53]_i_3_n_15\,
      I1 => \xsqr_reg[53]_i_17_n_4\,
      I2 => \xsqr_reg[53]_i_3_n_14\,
      I3 => \xsqr_reg[53]_i_3_n_13\,
      O => \xsqr[53]_i_8_n_0\
    );
\xsqr[53]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \xsqr_reg[53]_i_13_n_8\,
      I1 => \xsqr_reg[53]_i_17_n_13\,
      I2 => \xsqr_reg[53]_i_3_n_15\,
      I3 => \xsqr_reg[53]_i_17_n_4\,
      I4 => \xsqr_reg[53]_i_3_n_14\,
      O => \xsqr[53]_i_9_n_0\
    );
\xsqr[54]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => \dx_reg_n_0_[27]\,
      O => \xsqr[54]_i_1_n_0\
    );
\xsqr[56]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(2),
      O => \xsqr[56]_i_1_n_0\
    );
\xsqr[57]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \xsqr_reg[57]_i_2_n_13\,
      I1 => \xsqr_reg[57]_i_3_n_15\,
      I2 => \stateScore_reg_rep__12_n_0\,
      O => \xsqr[57]_i_1_n_0\
    );
\xsqr[57]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xsqr[57]_i_4_n_0\,
      I1 => \xsqr[57]_i_31_n_0\,
      I2 => \dx_reg_n_0_[29]\,
      I3 => \dx_reg_n_0_[33]\,
      O => \xsqr[57]_i_10_n_0\
    );
\xsqr[57]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xsqr[57]_i_5_n_0\,
      I1 => \dx_reg_n_0_[32]\,
      I2 => \dx_reg_n_0_[29]\,
      I3 => \xsqr[57]_i_32_n_0\,
      I4 => \dx_reg_n_0_[27]\,
      I5 => \dx_reg_n_0_[34]\,
      O => \xsqr[57]_i_11_n_0\
    );
\xsqr[57]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \xsqr[57]_i_6_n_0\,
      I1 => \dx_reg_n_0_[31]\,
      I2 => \dx_reg_n_0_[29]\,
      I3 => \dx_reg_n_0_[32]\,
      I4 => \dx_reg_n_0_[28]\,
      I5 => \xsqr[57]_i_33_n_0\,
      O => \xsqr[57]_i_12_n_0\
    );
\xsqr[57]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xsqr[57]_i_7_n_0\,
      I1 => \dx_reg_n_0_[31]\,
      I2 => \dx_reg_n_0_[28]\,
      I3 => \xsqr[57]_i_21_n_0\,
      I4 => \dx_reg_n_0_[27]\,
      I5 => \dx_reg_n_0_[32]\,
      O => \xsqr[57]_i_13_n_0\
    );
\xsqr[57]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dx_reg_n_0_[28]\,
      I1 => \dx_reg_n_0_[29]\,
      I2 => \dx_reg_n_0_[30]\,
      I3 => \dx_reg_n_0_[31]\,
      I4 => \dx_reg_n_0_[27]\,
      O => \xsqr[57]_i_14_n_0\
    );
\xsqr[57]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dx_reg_n_0_[30]\,
      I1 => \dx_reg_n_0_[29]\,
      I2 => \dx_reg_n_0_[27]\,
      O => \xsqr[57]_i_15_n_0\
    );
\xsqr[57]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dx_reg_n_0_[28]\,
      I1 => \dx_reg_n_0_[27]\,
      O => \xsqr[57]_i_16_n_0\
    );
\xsqr[57]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[30]\,
      I1 => \dx_reg_n_0_[34]\,
      O => \xsqr[57]_i_17_n_0\
    );
\xsqr[57]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[30]\,
      I1 => \dx_reg_n_0_[33]\,
      O => \xsqr[57]_i_18_n_0\
    );
\xsqr[57]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[29]\,
      I1 => \dx_reg_n_0_[32]\,
      O => \xsqr[57]_i_19_n_0\
    );
\xsqr[57]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"956A6A6A"
    )
        port map (
      I0 => \dx_reg_n_0_[30]\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dx_reg_n_0_[32]\,
      I3 => \dx_reg_n_0_[29]\,
      I4 => \dx_reg_n_0_[31]\,
      O => \xsqr[57]_i_20_n_0\
    );
\xsqr[57]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[29]\,
      I1 => \dx_reg_n_0_[30]\,
      O => \xsqr[57]_i_21_n_0\
    );
\xsqr[57]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[28]\,
      I1 => \dx_reg_n_0_[30]\,
      O => \xsqr[57]_i_22_n_0\
    );
\xsqr[57]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dx_reg_n_0_[31]\,
      I1 => \dx_reg_n_0_[32]\,
      I2 => \dx_reg_n_0_[33]\,
      I3 => \dx_reg_n_0_[34]\,
      I4 => \dx_reg_n_0_[30]\,
      O => \xsqr[57]_i_23_n_0\
    );
\xsqr[57]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dx_reg_n_0_[33]\,
      I1 => \dx_reg_n_0_[32]\,
      I2 => \dx_reg_n_0_[30]\,
      O => \xsqr[57]_i_24_n_0\
    );
\xsqr[57]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dx_reg_n_0_[31]\,
      I1 => \dx_reg_n_0_[30]\,
      O => \xsqr[57]_i_25_n_0\
    );
\xsqr[57]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17A08800"
    )
        port map (
      I0 => \dx_reg_n_0_[30]\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dx_reg_n_0_[31]\,
      I3 => \dx_reg_n_0_[32]\,
      I4 => \dx_reg_n_0_[29]\,
      O => \xsqr[57]_i_26_n_0\
    );
\xsqr[57]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"663C963C66CC66CC"
    )
        port map (
      I0 => \dx_reg_n_0_[29]\,
      I1 => \dx_reg_n_0_[30]\,
      I2 => \dx_reg_n_0_[28]\,
      I3 => \dx_reg_n_0_[31]\,
      I4 => \dx_reg_n_0_[27]\,
      I5 => \dx_reg_n_0_[32]\,
      O => \xsqr[57]_i_27_n_0\
    );
\xsqr[57]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dx_reg_n_0_[27]\,
      I1 => \dx_reg_n_0_[32]\,
      I2 => \dx_reg_n_0_[28]\,
      I3 => \dx_reg_n_0_[31]\,
      I4 => \dx_reg_n_0_[30]\,
      I5 => \dx_reg_n_0_[29]\,
      O => \xsqr[57]_i_28_n_0\
    );
\xsqr[57]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dx_reg_n_0_[30]\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dx_reg_n_0_[31]\,
      I3 => \dx_reg_n_0_[27]\,
      O => \xsqr[57]_i_29_n_0\
    );
\xsqr[57]_i_30\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[27]\,
      I1 => \dx_reg_n_0_[30]\,
      O => \xsqr[57]_i_30_n_0\
    );
\xsqr[57]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dx_reg_n_0_[35]\,
      I1 => \dx_reg_n_0_[27]\,
      I2 => \dx_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[28]\,
      O => \xsqr[57]_i_31_n_0\
    );
\xsqr[57]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[28]\,
      I1 => \dx_reg_n_0_[33]\,
      O => \xsqr[57]_i_32_n_0\
    );
\xsqr[57]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[27]\,
      I1 => \dx_reg_n_0_[33]\,
      O => \xsqr[57]_i_33_n_0\
    );
\xsqr[57]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dx_reg_n_0_[32]\,
      I1 => \dx_reg_n_0_[29]\,
      I2 => \dx_reg_n_0_[33]\,
      I3 => \dx_reg_n_0_[28]\,
      I4 => \dx_reg_n_0_[27]\,
      I5 => \dx_reg_n_0_[34]\,
      O => \xsqr[57]_i_4_n_0\
    );
\xsqr[57]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dx_reg_n_0_[31]\,
      I1 => \dx_reg_n_0_[29]\,
      I2 => \dx_reg_n_0_[32]\,
      I3 => \dx_reg_n_0_[28]\,
      I4 => \dx_reg_n_0_[27]\,
      I5 => \dx_reg_n_0_[33]\,
      O => \xsqr[57]_i_5_n_0\
    );
\xsqr[57]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dx_reg_n_0_[31]\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dx_reg_n_0_[30]\,
      I3 => \dx_reg_n_0_[29]\,
      I4 => \dx_reg_n_0_[27]\,
      I5 => \dx_reg_n_0_[32]\,
      O => \xsqr[57]_i_6_n_0\
    );
\xsqr[57]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[28]\,
      I1 => \dx_reg_n_0_[29]\,
      O => \xsqr[57]_i_7_n_0\
    );
\xsqr[57]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \dx_reg_n_0_[30]\,
      I1 => \dx_reg_n_0_[29]\,
      I2 => \dx_reg_n_0_[28]\,
      O => \xsqr[57]_i_8_n_0\
    );
\xsqr[57]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[27]\,
      I1 => \dx_reg_n_0_[30]\,
      O => \xsqr[57]_i_9_n_0\
    );
\xsqr[58]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(4),
      O => \xsqr[58]_i_1_n_0\
    );
\xsqr[59]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(5),
      O => \xsqr[59]_i_1_n_0\
    );
\xsqr[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(5),
      O => \xsqr[5]_i_1_n_0\
    );
\xsqr[60]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(6),
      O => \xsqr[60]_i_1_n_0\
    );
\xsqr[61]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(7),
      O => \xsqr[61]_i_1_n_0\
    );
\xsqr[62]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(8),
      O => \xsqr[62]_i_1_n_0\
    );
\xsqr[63]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(9),
      O => \xsqr[63]_i_1_n_0\
    );
\xsqr[64]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(10),
      O => \xsqr[64]_i_1_n_0\
    );
\xsqr[65]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(11),
      O => \xsqr[65]_i_1_n_0\
    );
\xsqr[65]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[57]_i_3_n_15\,
      I1 => \xsqr_reg[57]_i_2_n_13\,
      O => \xsqr[65]_i_10_n_0\
    );
\xsqr[65]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \xsqr_reg[57]_i_3_n_9\,
      I1 => \xsqr_reg[71]_i_13_n_12\,
      I2 => \xsqr_reg[71]_i_18_n_14\,
      I3 => \xsqr_reg[71]_i_13_n_11\,
      I4 => \xsqr_reg[57]_i_3_n_8\,
      I5 => \xsqr[65]_i_19_n_0\,
      O => \xsqr[65]_i_11_n_0\
    );
\xsqr[65]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \xsqr_reg[71]_i_18_n_15\,
      I1 => \xsqr_reg[57]_i_3_n_9\,
      I2 => \xsqr_reg[71]_i_13_n_12\,
      I3 => \xsqr_reg[57]_i_3_n_8\,
      I4 => \xsqr_reg[71]_i_13_n_11\,
      I5 => \xsqr_reg[71]_i_18_n_14\,
      O => \xsqr[65]_i_12_n_0\
    );
\xsqr[65]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \xsqr_reg[71]_i_18_n_15\,
      I1 => \xsqr_reg[71]_i_13_n_12\,
      I2 => \xsqr_reg[57]_i_3_n_9\,
      I3 => \xsqr_reg[57]_i_3_n_10\,
      I4 => \xsqr_reg[57]_i_2_n_8\,
      I5 => \xsqr_reg[71]_i_13_n_13\,
      O => \xsqr[65]_i_13_n_0\
    );
\xsqr[65]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr[65]_i_6_n_0\,
      I1 => \xsqr_reg[71]_i_13_n_13\,
      I2 => \xsqr_reg[57]_i_2_n_8\,
      I3 => \xsqr_reg[57]_i_3_n_10\,
      O => \xsqr[65]_i_14_n_0\
    );
\xsqr[65]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr_reg[71]_i_13_n_14\,
      I1 => \xsqr_reg[57]_i_2_n_9\,
      I2 => \xsqr_reg[57]_i_3_n_11\,
      I3 => \xsqr[65]_i_7_n_0\,
      O => \xsqr[65]_i_15_n_0\
    );
\xsqr[65]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr_reg[71]_i_13_n_15\,
      I1 => \xsqr_reg[57]_i_2_n_10\,
      I2 => \xsqr_reg[57]_i_3_n_12\,
      I3 => \xsqr[65]_i_8_n_0\,
      O => \xsqr[65]_i_16_n_0\
    );
\xsqr[65]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xsqr_reg[57]_i_3_n_13\,
      I1 => \xsqr_reg[57]_i_2_n_11\,
      I2 => \xsqr_reg[57]_i_2_n_12\,
      I3 => \xsqr_reg[57]_i_3_n_14\,
      O => \xsqr[65]_i_17_n_0\
    );
\xsqr[65]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \xsqr_reg[57]_i_2_n_13\,
      I1 => \xsqr_reg[57]_i_3_n_15\,
      I2 => \xsqr_reg[57]_i_2_n_12\,
      I3 => \xsqr_reg[57]_i_3_n_14\,
      O => \xsqr[65]_i_18_n_0\
    );
\xsqr[65]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xsqr_reg[71]_i_17_n_15\,
      I1 => \xsqr_reg[71]_i_13_n_10\,
      I2 => \xsqr_reg[71]_i_18_n_5\,
      O => \xsqr[65]_i_19_n_0\
    );
\xsqr[65]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \xsqr_reg[57]_i_3_n_9\,
      I1 => \xsqr_reg[71]_i_13_n_12\,
      I2 => \xsqr_reg[71]_i_18_n_14\,
      I3 => \xsqr_reg[71]_i_13_n_11\,
      I4 => \xsqr_reg[57]_i_3_n_8\,
      O => \xsqr[65]_i_3_n_0\
    );
\xsqr[65]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \xsqr_reg[71]_i_18_n_15\,
      I1 => \xsqr_reg[57]_i_3_n_9\,
      I2 => \xsqr_reg[71]_i_13_n_12\,
      O => \xsqr[65]_i_4_n_0\
    );
\xsqr[65]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xsqr_reg[57]_i_3_n_9\,
      I1 => \xsqr_reg[71]_i_13_n_12\,
      I2 => \xsqr_reg[71]_i_18_n_15\,
      O => \xsqr[65]_i_5_n_0\
    );
\xsqr[65]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xsqr_reg[71]_i_13_n_14\,
      I1 => \xsqr_reg[57]_i_2_n_9\,
      I2 => \xsqr_reg[57]_i_3_n_11\,
      O => \xsqr[65]_i_6_n_0\
    );
\xsqr[65]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xsqr_reg[71]_i_13_n_15\,
      I1 => \xsqr_reg[57]_i_2_n_10\,
      I2 => \xsqr_reg[57]_i_3_n_12\,
      O => \xsqr[65]_i_7_n_0\
    );
\xsqr[65]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[57]_i_3_n_13\,
      I1 => \xsqr_reg[57]_i_2_n_11\,
      O => \xsqr[65]_i_8_n_0\
    );
\xsqr[65]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[57]_i_3_n_14\,
      I1 => \xsqr_reg[57]_i_2_n_12\,
      O => \xsqr[65]_i_9_n_0\
    );
\xsqr[66]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(12),
      O => \xsqr[66]_i_1_n_0\
    );
\xsqr[67]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(13),
      O => \xsqr[67]_i_1_n_0\
    );
\xsqr[68]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(14),
      O => \xsqr[68]_i_1_n_0\
    );
\xsqr[69]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(15),
      O => \xsqr[69]_i_1_n_0\
    );
\xsqr[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(6),
      O => \xsqr[6]_i_1_n_0\
    );
\xsqr[70]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(16),
      O => \xsqr[70]_i_1_n_0\
    );
\xsqr[71]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr02_in(17),
      O => \xsqr[71]_i_1_n_0\
    );
\xsqr[71]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \xsqr[71]_i_5_n_0\,
      I1 => \xsqr_reg[71]_i_3_n_15\,
      I2 => \xsqr_reg[71]_i_17_n_4\,
      I3 => \xsqr_reg[71]_i_13_n_8\,
      I4 => \xsqr_reg[71]_i_17_n_13\,
      O => \xsqr[71]_i_10_n_0\
    );
\xsqr[71]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \xsqr_reg[71]_i_17_n_14\,
      I1 => \xsqr_reg[71]_i_13_n_9\,
      I2 => \xsqr_reg[71]_i_17_n_13\,
      I3 => \xsqr_reg[71]_i_13_n_8\,
      I4 => \xsqr[71]_i_6_n_0\,
      O => \xsqr[71]_i_11_n_0\
    );
\xsqr[71]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \xsqr[71]_i_7_n_0\,
      I1 => \xsqr_reg[71]_i_17_n_15\,
      I2 => \xsqr_reg[71]_i_18_n_5\,
      I3 => \xsqr_reg[71]_i_13_n_10\,
      I4 => \xsqr_reg[71]_i_17_n_14\,
      I5 => \xsqr_reg[71]_i_13_n_9\,
      O => \xsqr[71]_i_12_n_0\
    );
\xsqr[71]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \dx_reg_n_0_[34]\,
      I1 => \dx_reg_n_0_[35]\,
      O => \xsqr[71]_i_14_n_0\
    );
\xsqr[71]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \dx_reg_n_0_[33]\,
      I1 => \dx_reg_n_0_[35]\,
      O => \xsqr[71]_i_15_n_0\
    );
\xsqr[71]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dx_reg_n_0_[34]\,
      I1 => \dx_reg_n_0_[33]\,
      O => \xsqr[71]_i_16_n_0\
    );
\xsqr[71]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7777000"
    )
        port map (
      I0 => \dx_reg_n_0_[35]\,
      I1 => \dx_reg_n_0_[31]\,
      I2 => \dx_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[32]\,
      I4 => \dx_reg_n_0_[33]\,
      O => \xsqr[71]_i_19_n_0\
    );
\xsqr[71]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dx_reg_n_0_[35]\,
      I1 => \dx_reg_n_0_[30]\,
      I2 => \dx_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[31]\,
      I4 => \dx_reg_n_0_[32]\,
      I5 => \dx_reg_n_0_[33]\,
      O => \xsqr[71]_i_20_n_0\
    );
\xsqr[71]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dx_reg_n_0_[35]\,
      I1 => \dx_reg_n_0_[29]\,
      I2 => \dx_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[30]\,
      I4 => \dx_reg_n_0_[31]\,
      I5 => \dx_reg_n_0_[33]\,
      O => \xsqr[71]_i_21_n_0\
    );
\xsqr[71]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dx_reg_n_0_[35]\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dx_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[29]\,
      I4 => \dx_reg_n_0_[30]\,
      I5 => \dx_reg_n_0_[33]\,
      O => \xsqr[71]_i_22_n_0\
    );
\xsqr[71]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => \dx_reg_n_0_[35]\,
      I1 => \dx_reg_n_0_[27]\,
      I2 => \dx_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[28]\,
      O => \xsqr[71]_i_23_n_0\
    );
\xsqr[71]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[28]\,
      I1 => \dx_reg_n_0_[33]\,
      O => \xsqr[71]_i_24_n_0\
    );
\xsqr[71]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8E11F555"
    )
        port map (
      I0 => \dx_reg_n_0_[33]\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dx_reg_n_0_[31]\,
      I3 => \dx_reg_n_0_[35]\,
      I4 => \dx_reg_n_0_[32]\,
      O => \xsqr[71]_i_25_n_0\
    );
\xsqr[71]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EB843C0C903FCF3F"
    )
        port map (
      I0 => \dx_reg_n_0_[30]\,
      I1 => \dx_reg_n_0_[32]\,
      I2 => \dx_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[31]\,
      I4 => \dx_reg_n_0_[35]\,
      I5 => \dx_reg_n_0_[33]\,
      O => \xsqr[71]_i_26_n_0\
    );
\xsqr[71]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F07070780F8F8F8"
    )
        port map (
      I0 => \dx_reg_n_0_[33]\,
      I1 => \dx_reg_n_0_[31]\,
      I2 => \xsqr[71]_i_43_n_0\,
      I3 => \dx_reg_n_0_[29]\,
      I4 => \dx_reg_n_0_[35]\,
      I5 => \xsqr[71]_i_44_n_0\,
      O => \xsqr[71]_i_27_n_0\
    );
\xsqr[71]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A956A956A95"
    )
        port map (
      I0 => \xsqr[71]_i_22_n_0\,
      I1 => \dx_reg_n_0_[35]\,
      I2 => \dx_reg_n_0_[29]\,
      I3 => \xsqr[71]_i_43_n_0\,
      I4 => \dx_reg_n_0_[31]\,
      I5 => \dx_reg_n_0_[33]\,
      O => \xsqr[71]_i_28_n_0\
    );
\xsqr[71]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"69C399C369336933"
    )
        port map (
      I0 => \dx_reg_n_0_[29]\,
      I1 => \xsqr[71]_i_45_n_0\,
      I2 => \dx_reg_n_0_[28]\,
      I3 => \dx_reg_n_0_[34]\,
      I4 => \dx_reg_n_0_[27]\,
      I5 => \dx_reg_n_0_[35]\,
      O => \xsqr[71]_i_29_n_0\
    );
\xsqr[71]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dx_reg_n_0_[28]\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dx_reg_n_0_[27]\,
      I3 => \dx_reg_n_0_[35]\,
      I4 => \dx_reg_n_0_[33]\,
      I5 => \dx_reg_n_0_[29]\,
      O => \xsqr[71]_i_30_n_0\
    );
\xsqr[71]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dx_reg_n_0_[33]\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dx_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[27]\,
      O => \xsqr[71]_i_31_n_0\
    );
\xsqr[71]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[27]\,
      I1 => \dx_reg_n_0_[33]\,
      O => \xsqr[71]_i_32_n_0\
    );
\xsqr[71]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dx_reg_n_0_[34]\,
      I1 => \dx_reg_n_0_[32]\,
      I2 => \dx_reg_n_0_[35]\,
      I3 => \dx_reg_n_0_[31]\,
      O => \xsqr[71]_i_33_n_0\
    );
\xsqr[71]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dx_reg_n_0_[32]\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dx_reg_n_0_[31]\,
      I3 => \dx_reg_n_0_[35]\,
      O => \xsqr[71]_i_34_n_0\
    );
\xsqr[71]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[31]\,
      I1 => \dx_reg_n_0_[32]\,
      O => \xsqr[71]_i_35_n_0\
    );
\xsqr[71]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dx_reg_n_0_[31]\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dx_reg_n_0_[35]\,
      I3 => \dx_reg_n_0_[32]\,
      O => \xsqr[71]_i_36_n_0\
    );
\xsqr[71]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dx_reg_n_0_[33]\,
      I1 => \dx_reg_n_0_[30]\,
      I2 => \dx_reg_n_0_[35]\,
      I3 => \dx_reg_n_0_[31]\,
      I4 => \dx_reg_n_0_[34]\,
      I5 => \dx_reg_n_0_[32]\,
      O => \xsqr[71]_i_37_n_0\
    );
\xsqr[71]_i_38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D22287772DDD8777"
    )
        port map (
      I0 => \dx_reg_n_0_[31]\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dx_reg_n_0_[30]\,
      I3 => \dx_reg_n_0_[35]\,
      I4 => \dx_reg_n_0_[32]\,
      I5 => \dx_reg_n_0_[33]\,
      O => \xsqr[71]_i_38_n_0\
    );
\xsqr[71]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dx_reg_n_0_[34]\,
      I1 => \dx_reg_n_0_[29]\,
      I2 => \dx_reg_n_0_[35]\,
      I3 => \dx_reg_n_0_[28]\,
      O => \xsqr[71]_i_39_n_0\
    );
\xsqr[71]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xsqr_reg[71]_i_17_n_13\,
      I1 => \xsqr_reg[71]_i_13_n_8\,
      I2 => \xsqr_reg[71]_i_17_n_4\,
      I3 => \xsqr_reg[71]_i_3_n_15\,
      O => \xsqr[71]_i_4_n_0\
    );
\xsqr[71]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dx_reg_n_0_[29]\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dx_reg_n_0_[28]\,
      I3 => \dx_reg_n_0_[35]\,
      O => \xsqr[71]_i_40_n_0\
    );
\xsqr[71]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dx_reg_n_0_[28]\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dx_reg_n_0_[35]\,
      I3 => \dx_reg_n_0_[29]\,
      O => \xsqr[71]_i_41_n_0\
    );
\xsqr[71]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dx_reg_n_0_[33]\,
      I1 => \dx_reg_n_0_[27]\,
      I2 => \dx_reg_n_0_[35]\,
      I3 => \dx_reg_n_0_[28]\,
      I4 => \dx_reg_n_0_[34]\,
      I5 => \dx_reg_n_0_[29]\,
      O => \xsqr[71]_i_42_n_0\
    );
\xsqr[71]_i_43\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[30]\,
      I1 => \dx_reg_n_0_[34]\,
      O => \xsqr[71]_i_43_n_0\
    );
\xsqr[71]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dx_reg_n_0_[33]\,
      I1 => \dx_reg_n_0_[32]\,
      I2 => \dx_reg_n_0_[35]\,
      I3 => \dx_reg_n_0_[30]\,
      I4 => \dx_reg_n_0_[34]\,
      I5 => \dx_reg_n_0_[31]\,
      O => \xsqr[71]_i_44_n_0\
    );
\xsqr[71]_i_45\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[30]\,
      I1 => \dx_reg_n_0_[33]\,
      O => \xsqr[71]_i_45_n_0\
    );
\xsqr[71]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xsqr_reg[71]_i_17_n_14\,
      I1 => \xsqr_reg[71]_i_13_n_9\,
      I2 => \xsqr_reg[71]_i_17_n_13\,
      I3 => \xsqr_reg[71]_i_13_n_8\,
      O => \xsqr[71]_i_5_n_0\
    );
\xsqr[71]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \xsqr_reg[71]_i_17_n_14\,
      I1 => \xsqr_reg[71]_i_13_n_9\,
      I2 => \xsqr_reg[71]_i_17_n_15\,
      I3 => \xsqr_reg[71]_i_18_n_5\,
      I4 => \xsqr_reg[71]_i_13_n_10\,
      O => \xsqr[71]_i_6_n_0\
    );
\xsqr[71]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \xsqr_reg[57]_i_3_n_8\,
      I1 => \xsqr_reg[71]_i_18_n_14\,
      I2 => \xsqr_reg[71]_i_13_n_11\,
      I3 => \xsqr_reg[71]_i_18_n_5\,
      I4 => \xsqr_reg[71]_i_13_n_10\,
      I5 => \xsqr_reg[71]_i_17_n_15\,
      O => \xsqr[71]_i_7_n_0\
    );
\xsqr[71]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \xsqr_reg[71]_i_3_n_15\,
      I1 => \xsqr_reg[71]_i_17_n_4\,
      I2 => \xsqr_reg[71]_i_3_n_14\,
      I3 => \xsqr_reg[71]_i_3_n_13\,
      O => \xsqr[71]_i_8_n_0\
    );
\xsqr[71]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \xsqr_reg[71]_i_13_n_8\,
      I1 => \xsqr_reg[71]_i_17_n_13\,
      I2 => \xsqr_reg[71]_i_3_n_15\,
      I3 => \xsqr_reg[71]_i_17_n_4\,
      I4 => \xsqr_reg[71]_i_3_n_14\,
      O => \xsqr[71]_i_9_n_0\
    );
\xsqr[72]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => \dx_reg_n_0_[36]\,
      O => \xsqr[72]_i_1_n_0\
    );
\xsqr[74]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr03_in(2),
      O => \xsqr[74]_i_1_n_0\
    );
\xsqr[75]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \xsqr_reg[75]_i_2_n_13\,
      I1 => \xsqr_reg[75]_i_3_n_15\,
      I2 => \stateScore_reg_rep__13_n_0\,
      O => \xsqr[75]_i_1_n_0\
    );
\xsqr[75]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xsqr[75]_i_4_n_0\,
      I1 => \xsqr[75]_i_31_n_0\,
      I2 => \dx_reg_n_0_[38]\,
      I3 => \dx_reg_n_0_[42]\,
      O => \xsqr[75]_i_10_n_0\
    );
\xsqr[75]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xsqr[75]_i_5_n_0\,
      I1 => \dx_reg_n_0_[41]\,
      I2 => \dx_reg_n_0_[38]\,
      I3 => \xsqr[75]_i_32_n_0\,
      I4 => \dx_reg_n_0_[36]\,
      I5 => \dx_reg_n_0_[43]\,
      O => \xsqr[75]_i_11_n_0\
    );
\xsqr[75]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \xsqr[75]_i_6_n_0\,
      I1 => \dx_reg_n_0_[40]\,
      I2 => \dx_reg_n_0_[38]\,
      I3 => \dx_reg_n_0_[41]\,
      I4 => \dx_reg_n_0_[37]\,
      I5 => \xsqr[75]_i_33_n_0\,
      O => \xsqr[75]_i_12_n_0\
    );
\xsqr[75]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xsqr[75]_i_7_n_0\,
      I1 => \dx_reg_n_0_[40]\,
      I2 => \dx_reg_n_0_[37]\,
      I3 => \xsqr[75]_i_21_n_0\,
      I4 => \dx_reg_n_0_[36]\,
      I5 => \dx_reg_n_0_[41]\,
      O => \xsqr[75]_i_13_n_0\
    );
\xsqr[75]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dx_reg_n_0_[37]\,
      I1 => \dx_reg_n_0_[38]\,
      I2 => \dx_reg_n_0_[39]\,
      I3 => \dx_reg_n_0_[40]\,
      I4 => \dx_reg_n_0_[36]\,
      O => \xsqr[75]_i_14_n_0\
    );
\xsqr[75]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dx_reg_n_0_[39]\,
      I1 => \dx_reg_n_0_[38]\,
      I2 => \dx_reg_n_0_[36]\,
      O => \xsqr[75]_i_15_n_0\
    );
\xsqr[75]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dx_reg_n_0_[37]\,
      I1 => \dx_reg_n_0_[36]\,
      O => \xsqr[75]_i_16_n_0\
    );
\xsqr[75]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[39]\,
      I1 => \dx_reg_n_0_[43]\,
      O => \xsqr[75]_i_17_n_0\
    );
\xsqr[75]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[39]\,
      I1 => \dx_reg_n_0_[42]\,
      O => \xsqr[75]_i_18_n_0\
    );
\xsqr[75]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[38]\,
      I1 => \dx_reg_n_0_[41]\,
      O => \xsqr[75]_i_19_n_0\
    );
\xsqr[75]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"956A6A6A"
    )
        port map (
      I0 => \dx_reg_n_0_[39]\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dx_reg_n_0_[41]\,
      I3 => \dx_reg_n_0_[38]\,
      I4 => \dx_reg_n_0_[40]\,
      O => \xsqr[75]_i_20_n_0\
    );
\xsqr[75]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[38]\,
      I1 => \dx_reg_n_0_[39]\,
      O => \xsqr[75]_i_21_n_0\
    );
\xsqr[75]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[37]\,
      I1 => \dx_reg_n_0_[39]\,
      O => \xsqr[75]_i_22_n_0\
    );
\xsqr[75]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dx_reg_n_0_[40]\,
      I1 => \dx_reg_n_0_[41]\,
      I2 => \dx_reg_n_0_[42]\,
      I3 => \dx_reg_n_0_[43]\,
      I4 => \dx_reg_n_0_[39]\,
      O => \xsqr[75]_i_23_n_0\
    );
\xsqr[75]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dx_reg_n_0_[42]\,
      I1 => \dx_reg_n_0_[41]\,
      I2 => \dx_reg_n_0_[39]\,
      O => \xsqr[75]_i_24_n_0\
    );
\xsqr[75]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dx_reg_n_0_[40]\,
      I1 => \dx_reg_n_0_[39]\,
      O => \xsqr[75]_i_25_n_0\
    );
\xsqr[75]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17A08800"
    )
        port map (
      I0 => \dx_reg_n_0_[39]\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dx_reg_n_0_[40]\,
      I3 => \dx_reg_n_0_[41]\,
      I4 => \dx_reg_n_0_[38]\,
      O => \xsqr[75]_i_26_n_0\
    );
\xsqr[75]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"663C963C66CC66CC"
    )
        port map (
      I0 => \dx_reg_n_0_[38]\,
      I1 => \dx_reg_n_0_[39]\,
      I2 => \dx_reg_n_0_[37]\,
      I3 => \dx_reg_n_0_[40]\,
      I4 => \dx_reg_n_0_[36]\,
      I5 => \dx_reg_n_0_[41]\,
      O => \xsqr[75]_i_27_n_0\
    );
\xsqr[75]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dx_reg_n_0_[36]\,
      I1 => \dx_reg_n_0_[41]\,
      I2 => \dx_reg_n_0_[37]\,
      I3 => \dx_reg_n_0_[40]\,
      I4 => \dx_reg_n_0_[39]\,
      I5 => \dx_reg_n_0_[38]\,
      O => \xsqr[75]_i_28_n_0\
    );
\xsqr[75]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dx_reg_n_0_[39]\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dx_reg_n_0_[40]\,
      I3 => \dx_reg_n_0_[36]\,
      O => \xsqr[75]_i_29_n_0\
    );
\xsqr[75]_i_30\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[36]\,
      I1 => \dx_reg_n_0_[39]\,
      O => \xsqr[75]_i_30_n_0\
    );
\xsqr[75]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dx_reg_n_0_[44]\,
      I1 => \dx_reg_n_0_[36]\,
      I2 => \dx_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[37]\,
      O => \xsqr[75]_i_31_n_0\
    );
\xsqr[75]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[37]\,
      I1 => \dx_reg_n_0_[42]\,
      O => \xsqr[75]_i_32_n_0\
    );
\xsqr[75]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[36]\,
      I1 => \dx_reg_n_0_[42]\,
      O => \xsqr[75]_i_33_n_0\
    );
\xsqr[75]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dx_reg_n_0_[41]\,
      I1 => \dx_reg_n_0_[38]\,
      I2 => \dx_reg_n_0_[42]\,
      I3 => \dx_reg_n_0_[37]\,
      I4 => \dx_reg_n_0_[36]\,
      I5 => \dx_reg_n_0_[43]\,
      O => \xsqr[75]_i_4_n_0\
    );
\xsqr[75]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dx_reg_n_0_[40]\,
      I1 => \dx_reg_n_0_[38]\,
      I2 => \dx_reg_n_0_[41]\,
      I3 => \dx_reg_n_0_[37]\,
      I4 => \dx_reg_n_0_[36]\,
      I5 => \dx_reg_n_0_[42]\,
      O => \xsqr[75]_i_5_n_0\
    );
\xsqr[75]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dx_reg_n_0_[40]\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dx_reg_n_0_[39]\,
      I3 => \dx_reg_n_0_[38]\,
      I4 => \dx_reg_n_0_[36]\,
      I5 => \dx_reg_n_0_[41]\,
      O => \xsqr[75]_i_6_n_0\
    );
\xsqr[75]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[37]\,
      I1 => \dx_reg_n_0_[38]\,
      O => \xsqr[75]_i_7_n_0\
    );
\xsqr[75]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \dx_reg_n_0_[39]\,
      I1 => \dx_reg_n_0_[38]\,
      I2 => \dx_reg_n_0_[37]\,
      O => \xsqr[75]_i_8_n_0\
    );
\xsqr[75]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[36]\,
      I1 => \dx_reg_n_0_[39]\,
      O => \xsqr[75]_i_9_n_0\
    );
\xsqr[76]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr03_in(4),
      O => \xsqr[76]_i_1_n_0\
    );
\xsqr[77]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr03_in(5),
      O => \xsqr[77]_i_1_n_0\
    );
\xsqr[78]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr03_in(6),
      O => \xsqr[78]_i_1_n_0\
    );
\xsqr[79]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr03_in(7),
      O => \xsqr[79]_i_1_n_0\
    );
\xsqr[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(7),
      O => \xsqr[7]_i_1_n_0\
    );
\xsqr[80]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr03_in(8),
      O => \xsqr[80]_i_1_n_0\
    );
\xsqr[81]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr03_in(9),
      O => \xsqr[81]_i_1_n_0\
    );
\xsqr[82]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr03_in(10),
      O => \xsqr[82]_i_1_n_0\
    );
\xsqr[83]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr03_in(11),
      O => \xsqr[83]_i_1_n_0\
    );
\xsqr[83]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[75]_i_3_n_15\,
      I1 => \xsqr_reg[75]_i_2_n_13\,
      O => \xsqr[83]_i_10_n_0\
    );
\xsqr[83]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \xsqr_reg[75]_i_3_n_9\,
      I1 => \xsqr_reg[89]_i_14_n_12\,
      I2 => \xsqr_reg[89]_i_19_n_14\,
      I3 => \xsqr_reg[89]_i_14_n_11\,
      I4 => \xsqr_reg[75]_i_3_n_8\,
      I5 => \xsqr[83]_i_19_n_0\,
      O => \xsqr[83]_i_11_n_0\
    );
\xsqr[83]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \xsqr_reg[89]_i_19_n_15\,
      I1 => \xsqr_reg[75]_i_3_n_9\,
      I2 => \xsqr_reg[89]_i_14_n_12\,
      I3 => \xsqr_reg[75]_i_3_n_8\,
      I4 => \xsqr_reg[89]_i_14_n_11\,
      I5 => \xsqr_reg[89]_i_19_n_14\,
      O => \xsqr[83]_i_12_n_0\
    );
\xsqr[83]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \xsqr_reg[89]_i_19_n_15\,
      I1 => \xsqr_reg[89]_i_14_n_12\,
      I2 => \xsqr_reg[75]_i_3_n_9\,
      I3 => \xsqr_reg[75]_i_3_n_10\,
      I4 => \xsqr_reg[75]_i_2_n_8\,
      I5 => \xsqr_reg[89]_i_14_n_13\,
      O => \xsqr[83]_i_13_n_0\
    );
\xsqr[83]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr[83]_i_6_n_0\,
      I1 => \xsqr_reg[89]_i_14_n_13\,
      I2 => \xsqr_reg[75]_i_2_n_8\,
      I3 => \xsqr_reg[75]_i_3_n_10\,
      O => \xsqr[83]_i_14_n_0\
    );
\xsqr[83]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr_reg[89]_i_14_n_14\,
      I1 => \xsqr_reg[75]_i_2_n_9\,
      I2 => \xsqr_reg[75]_i_3_n_11\,
      I3 => \xsqr[83]_i_7_n_0\,
      O => \xsqr[83]_i_15_n_0\
    );
\xsqr[83]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xsqr_reg[89]_i_14_n_15\,
      I1 => \xsqr_reg[75]_i_2_n_10\,
      I2 => \xsqr_reg[75]_i_3_n_12\,
      I3 => \xsqr[83]_i_8_n_0\,
      O => \xsqr[83]_i_16_n_0\
    );
\xsqr[83]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xsqr_reg[75]_i_3_n_13\,
      I1 => \xsqr_reg[75]_i_2_n_11\,
      I2 => \xsqr_reg[75]_i_2_n_12\,
      I3 => \xsqr_reg[75]_i_3_n_14\,
      O => \xsqr[83]_i_17_n_0\
    );
\xsqr[83]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \xsqr_reg[75]_i_2_n_13\,
      I1 => \xsqr_reg[75]_i_3_n_15\,
      I2 => \xsqr_reg[75]_i_2_n_12\,
      I3 => \xsqr_reg[75]_i_3_n_14\,
      O => \xsqr[83]_i_18_n_0\
    );
\xsqr[83]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xsqr_reg[89]_i_18_n_15\,
      I1 => \xsqr_reg[89]_i_14_n_10\,
      I2 => \xsqr_reg[89]_i_19_n_5\,
      O => \xsqr[83]_i_19_n_0\
    );
\xsqr[83]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \xsqr_reg[75]_i_3_n_9\,
      I1 => \xsqr_reg[89]_i_14_n_12\,
      I2 => \xsqr_reg[89]_i_19_n_14\,
      I3 => \xsqr_reg[89]_i_14_n_11\,
      I4 => \xsqr_reg[75]_i_3_n_8\,
      O => \xsqr[83]_i_3_n_0\
    );
\xsqr[83]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \xsqr_reg[89]_i_19_n_15\,
      I1 => \xsqr_reg[75]_i_3_n_9\,
      I2 => \xsqr_reg[89]_i_14_n_12\,
      O => \xsqr[83]_i_4_n_0\
    );
\xsqr[83]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xsqr_reg[75]_i_3_n_9\,
      I1 => \xsqr_reg[89]_i_14_n_12\,
      I2 => \xsqr_reg[89]_i_19_n_15\,
      O => \xsqr[83]_i_5_n_0\
    );
\xsqr[83]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xsqr_reg[89]_i_14_n_14\,
      I1 => \xsqr_reg[75]_i_2_n_9\,
      I2 => \xsqr_reg[75]_i_3_n_11\,
      O => \xsqr[83]_i_6_n_0\
    );
\xsqr[83]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xsqr_reg[89]_i_14_n_15\,
      I1 => \xsqr_reg[75]_i_2_n_10\,
      I2 => \xsqr_reg[75]_i_3_n_12\,
      O => \xsqr[83]_i_7_n_0\
    );
\xsqr[83]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[75]_i_3_n_13\,
      I1 => \xsqr_reg[75]_i_2_n_11\,
      O => \xsqr[83]_i_8_n_0\
    );
\xsqr[83]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xsqr_reg[75]_i_3_n_14\,
      I1 => \xsqr_reg[75]_i_2_n_12\,
      O => \xsqr[83]_i_9_n_0\
    );
\xsqr[84]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr03_in(12),
      O => \xsqr[84]_i_1_n_0\
    );
\xsqr[85]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr03_in(13),
      O => \xsqr[85]_i_1_n_0\
    );
\xsqr[86]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr03_in(14),
      O => \xsqr[86]_i_1_n_0\
    );
\xsqr[87]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__13_n_0\,
      I1 => xsqr03_in(15),
      O => \xsqr[87]_i_1_n_0\
    );
\xsqr[88]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xsqr03_in(16),
      O => \xsqr[88]_i_1_n_0\
    );
\xsqr[89]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => ceScore,
      I1 => \stateScore_reg_rep__0_n_0\,
      O => \xsqr[89]_i_1_n_0\
    );
\xsqr[89]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \xsqr_reg[89]_i_14_n_8\,
      I1 => \xsqr_reg[89]_i_18_n_13\,
      I2 => \xsqr_reg[89]_i_4_n_15\,
      I3 => \xsqr_reg[89]_i_18_n_4\,
      I4 => \xsqr_reg[89]_i_4_n_14\,
      O => \xsqr[89]_i_10_n_0\
    );
\xsqr[89]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \xsqr[89]_i_6_n_0\,
      I1 => \xsqr_reg[89]_i_4_n_15\,
      I2 => \xsqr_reg[89]_i_18_n_4\,
      I3 => \xsqr_reg[89]_i_14_n_8\,
      I4 => \xsqr_reg[89]_i_18_n_13\,
      O => \xsqr[89]_i_11_n_0\
    );
\xsqr[89]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \xsqr_reg[89]_i_18_n_14\,
      I1 => \xsqr_reg[89]_i_14_n_9\,
      I2 => \xsqr_reg[89]_i_18_n_13\,
      I3 => \xsqr_reg[89]_i_14_n_8\,
      I4 => \xsqr[89]_i_7_n_0\,
      O => \xsqr[89]_i_12_n_0\
    );
\xsqr[89]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \xsqr[89]_i_8_n_0\,
      I1 => \xsqr_reg[89]_i_18_n_15\,
      I2 => \xsqr_reg[89]_i_19_n_5\,
      I3 => \xsqr_reg[89]_i_14_n_10\,
      I4 => \xsqr_reg[89]_i_18_n_14\,
      I5 => \xsqr_reg[89]_i_14_n_9\,
      O => \xsqr[89]_i_13_n_0\
    );
\xsqr[89]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \dx_reg_n_0_[43]\,
      I1 => \dx_reg_n_0_[44]\,
      O => \xsqr[89]_i_15_n_0\
    );
\xsqr[89]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \dx_reg_n_0_[42]\,
      I1 => \dx_reg_n_0_[44]\,
      O => \xsqr[89]_i_16_n_0\
    );
\xsqr[89]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dx_reg_n_0_[43]\,
      I1 => \dx_reg_n_0_[42]\,
      O => \xsqr[89]_i_17_n_0\
    );
\xsqr[89]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xsqr03_in(17),
      O => \xsqr[89]_i_2_n_0\
    );
\xsqr[89]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7777000"
    )
        port map (
      I0 => \dx_reg_n_0_[44]\,
      I1 => \dx_reg_n_0_[40]\,
      I2 => \dx_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[41]\,
      I4 => \dx_reg_n_0_[42]\,
      O => \xsqr[89]_i_20_n_0\
    );
\xsqr[89]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dx_reg_n_0_[44]\,
      I1 => \dx_reg_n_0_[39]\,
      I2 => \dx_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[40]\,
      I4 => \dx_reg_n_0_[41]\,
      I5 => \dx_reg_n_0_[42]\,
      O => \xsqr[89]_i_21_n_0\
    );
\xsqr[89]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dx_reg_n_0_[44]\,
      I1 => \dx_reg_n_0_[38]\,
      I2 => \dx_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[39]\,
      I4 => \dx_reg_n_0_[40]\,
      I5 => \dx_reg_n_0_[42]\,
      O => \xsqr[89]_i_22_n_0\
    );
\xsqr[89]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dx_reg_n_0_[44]\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dx_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[38]\,
      I4 => \dx_reg_n_0_[39]\,
      I5 => \dx_reg_n_0_[42]\,
      O => \xsqr[89]_i_23_n_0\
    );
\xsqr[89]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => \dx_reg_n_0_[44]\,
      I1 => \dx_reg_n_0_[36]\,
      I2 => \dx_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[37]\,
      O => \xsqr[89]_i_24_n_0\
    );
\xsqr[89]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[37]\,
      I1 => \dx_reg_n_0_[42]\,
      O => \xsqr[89]_i_25_n_0\
    );
\xsqr[89]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8E11F555"
    )
        port map (
      I0 => \dx_reg_n_0_[42]\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dx_reg_n_0_[40]\,
      I3 => \dx_reg_n_0_[44]\,
      I4 => \dx_reg_n_0_[41]\,
      O => \xsqr[89]_i_26_n_0\
    );
\xsqr[89]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EB843C0C903FCF3F"
    )
        port map (
      I0 => \dx_reg_n_0_[39]\,
      I1 => \dx_reg_n_0_[41]\,
      I2 => \dx_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[40]\,
      I4 => \dx_reg_n_0_[44]\,
      I5 => \dx_reg_n_0_[42]\,
      O => \xsqr[89]_i_27_n_0\
    );
\xsqr[89]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F07070780F8F8F8"
    )
        port map (
      I0 => \dx_reg_n_0_[42]\,
      I1 => \dx_reg_n_0_[40]\,
      I2 => \xsqr[89]_i_44_n_0\,
      I3 => \dx_reg_n_0_[38]\,
      I4 => \dx_reg_n_0_[44]\,
      I5 => \xsqr[89]_i_45_n_0\,
      O => \xsqr[89]_i_28_n_0\
    );
\xsqr[89]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A956A956A95"
    )
        port map (
      I0 => \xsqr[89]_i_23_n_0\,
      I1 => \dx_reg_n_0_[44]\,
      I2 => \dx_reg_n_0_[38]\,
      I3 => \xsqr[89]_i_44_n_0\,
      I4 => \dx_reg_n_0_[40]\,
      I5 => \dx_reg_n_0_[42]\,
      O => \xsqr[89]_i_29_n_0\
    );
\xsqr[89]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"69C399C369336933"
    )
        port map (
      I0 => \dx_reg_n_0_[38]\,
      I1 => \xsqr[89]_i_46_n_0\,
      I2 => \dx_reg_n_0_[37]\,
      I3 => \dx_reg_n_0_[43]\,
      I4 => \dx_reg_n_0_[36]\,
      I5 => \dx_reg_n_0_[44]\,
      O => \xsqr[89]_i_30_n_0\
    );
\xsqr[89]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dx_reg_n_0_[37]\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dx_reg_n_0_[36]\,
      I3 => \dx_reg_n_0_[44]\,
      I4 => \dx_reg_n_0_[42]\,
      I5 => \dx_reg_n_0_[38]\,
      O => \xsqr[89]_i_31_n_0\
    );
\xsqr[89]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dx_reg_n_0_[42]\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dx_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[36]\,
      O => \xsqr[89]_i_32_n_0\
    );
\xsqr[89]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[36]\,
      I1 => \dx_reg_n_0_[42]\,
      O => \xsqr[89]_i_33_n_0\
    );
\xsqr[89]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dx_reg_n_0_[43]\,
      I1 => \dx_reg_n_0_[41]\,
      I2 => \dx_reg_n_0_[44]\,
      I3 => \dx_reg_n_0_[40]\,
      O => \xsqr[89]_i_34_n_0\
    );
\xsqr[89]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dx_reg_n_0_[41]\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dx_reg_n_0_[40]\,
      I3 => \dx_reg_n_0_[44]\,
      O => \xsqr[89]_i_35_n_0\
    );
\xsqr[89]_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[40]\,
      I1 => \dx_reg_n_0_[41]\,
      O => \xsqr[89]_i_36_n_0\
    );
\xsqr[89]_i_37\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dx_reg_n_0_[40]\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dx_reg_n_0_[44]\,
      I3 => \dx_reg_n_0_[41]\,
      O => \xsqr[89]_i_37_n_0\
    );
\xsqr[89]_i_38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dx_reg_n_0_[42]\,
      I1 => \dx_reg_n_0_[39]\,
      I2 => \dx_reg_n_0_[44]\,
      I3 => \dx_reg_n_0_[40]\,
      I4 => \dx_reg_n_0_[43]\,
      I5 => \dx_reg_n_0_[41]\,
      O => \xsqr[89]_i_38_n_0\
    );
\xsqr[89]_i_39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D22287772DDD8777"
    )
        port map (
      I0 => \dx_reg_n_0_[40]\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dx_reg_n_0_[39]\,
      I3 => \dx_reg_n_0_[44]\,
      I4 => \dx_reg_n_0_[41]\,
      I5 => \dx_reg_n_0_[42]\,
      O => \xsqr[89]_i_39_n_0\
    );
\xsqr[89]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dx_reg_n_0_[43]\,
      I1 => \dx_reg_n_0_[38]\,
      I2 => \dx_reg_n_0_[44]\,
      I3 => \dx_reg_n_0_[37]\,
      O => \xsqr[89]_i_40_n_0\
    );
\xsqr[89]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dx_reg_n_0_[38]\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dx_reg_n_0_[37]\,
      I3 => \dx_reg_n_0_[44]\,
      O => \xsqr[89]_i_41_n_0\
    );
\xsqr[89]_i_42\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dx_reg_n_0_[37]\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dx_reg_n_0_[44]\,
      I3 => \dx_reg_n_0_[38]\,
      O => \xsqr[89]_i_42_n_0\
    );
\xsqr[89]_i_43\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dx_reg_n_0_[42]\,
      I1 => \dx_reg_n_0_[36]\,
      I2 => \dx_reg_n_0_[44]\,
      I3 => \dx_reg_n_0_[37]\,
      I4 => \dx_reg_n_0_[43]\,
      I5 => \dx_reg_n_0_[38]\,
      O => \xsqr[89]_i_43_n_0\
    );
\xsqr[89]_i_44\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[39]\,
      I1 => \dx_reg_n_0_[43]\,
      O => \xsqr[89]_i_44_n_0\
    );
\xsqr[89]_i_45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dx_reg_n_0_[42]\,
      I1 => \dx_reg_n_0_[41]\,
      I2 => \dx_reg_n_0_[44]\,
      I3 => \dx_reg_n_0_[39]\,
      I4 => \dx_reg_n_0_[43]\,
      I5 => \dx_reg_n_0_[40]\,
      O => \xsqr[89]_i_45_n_0\
    );
\xsqr[89]_i_46\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[39]\,
      I1 => \dx_reg_n_0_[42]\,
      O => \xsqr[89]_i_46_n_0\
    );
\xsqr[89]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xsqr_reg[89]_i_18_n_13\,
      I1 => \xsqr_reg[89]_i_14_n_8\,
      I2 => \xsqr_reg[89]_i_18_n_4\,
      I3 => \xsqr_reg[89]_i_4_n_15\,
      O => \xsqr[89]_i_5_n_0\
    );
\xsqr[89]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xsqr_reg[89]_i_18_n_14\,
      I1 => \xsqr_reg[89]_i_14_n_9\,
      I2 => \xsqr_reg[89]_i_18_n_13\,
      I3 => \xsqr_reg[89]_i_14_n_8\,
      O => \xsqr[89]_i_6_n_0\
    );
\xsqr[89]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \xsqr_reg[89]_i_18_n_14\,
      I1 => \xsqr_reg[89]_i_14_n_9\,
      I2 => \xsqr_reg[89]_i_18_n_15\,
      I3 => \xsqr_reg[89]_i_19_n_5\,
      I4 => \xsqr_reg[89]_i_14_n_10\,
      O => \xsqr[89]_i_7_n_0\
    );
\xsqr[89]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \xsqr_reg[75]_i_3_n_8\,
      I1 => \xsqr_reg[89]_i_19_n_14\,
      I2 => \xsqr_reg[89]_i_14_n_11\,
      I3 => \xsqr_reg[89]_i_19_n_5\,
      I4 => \xsqr_reg[89]_i_14_n_10\,
      I5 => \xsqr_reg[89]_i_18_n_15\,
      O => \xsqr[89]_i_8_n_0\
    );
\xsqr[89]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \xsqr_reg[89]_i_4_n_15\,
      I1 => \xsqr_reg[89]_i_18_n_4\,
      I2 => \xsqr_reg[89]_i_4_n_14\,
      I3 => \xsqr_reg[89]_i_4_n_13\,
      O => \xsqr[89]_i_9_n_0\
    );
\xsqr[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(8),
      O => \xsqr[8]_i_1_n_0\
    );
\xsqr[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__12_n_0\,
      I1 => xsqr0(9),
      O => \xsqr[9]_i_1_n_0\
    );
\xsqr_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[0]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[0]\
    );
\xsqr_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[10]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[10]\
    );
\xsqr_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[11]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[11]\
    );
\xsqr_reg[11]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[11]_i_2_n_0\,
      CO(6) => \xsqr_reg[11]_i_2_n_1\,
      CO(5) => \xsqr_reg[11]_i_2_n_2\,
      CO(4) => \xsqr_reg[11]_i_2_n_3\,
      CO(3) => \xsqr_reg[11]_i_2_n_4\,
      CO(2) => \xsqr_reg[11]_i_2_n_5\,
      CO(1) => \xsqr_reg[11]_i_2_n_6\,
      CO(0) => \xsqr_reg[11]_i_2_n_7\,
      DI(7) => \xsqr[11]_i_3_n_0\,
      DI(6) => \xsqr[11]_i_4_n_0\,
      DI(5) => \xsqr[11]_i_5_n_0\,
      DI(4) => \xsqr[11]_i_6_n_0\,
      DI(3) => \xsqr[11]_i_7_n_0\,
      DI(2) => \xsqr[11]_i_8_n_0\,
      DI(1) => \xsqr[11]_i_9_n_0\,
      DI(0) => \xsqr[11]_i_10_n_0\,
      O(7 downto 0) => xsqr0(11 downto 4),
      S(7) => \xsqr[11]_i_11_n_0\,
      S(6) => \xsqr[11]_i_12_n_0\,
      S(5) => \xsqr[11]_i_13_n_0\,
      S(4) => \xsqr[11]_i_14_n_0\,
      S(3) => \xsqr[11]_i_15_n_0\,
      S(2) => \xsqr[11]_i_16_n_0\,
      S(1) => \xsqr[11]_i_17_n_0\,
      S(0) => \xsqr[11]_i_18_n_0\
    );
\xsqr_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[12]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[12]\
    );
\xsqr_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[13]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[13]\
    );
\xsqr_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[14]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[14]\
    );
\xsqr_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[15]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[15]\
    );
\xsqr_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[16]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[16]\
    );
\xsqr_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[17]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[17]\
    );
\xsqr_reg[17]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[17]_i_13_n_0\,
      CO(6) => \xsqr_reg[17]_i_13_n_1\,
      CO(5) => \xsqr_reg[17]_i_13_n_2\,
      CO(4) => \xsqr_reg[17]_i_13_n_3\,
      CO(3) => \xsqr_reg[17]_i_13_n_4\,
      CO(2) => \xsqr_reg[17]_i_13_n_5\,
      CO(1) => \xsqr_reg[17]_i_13_n_6\,
      CO(0) => \xsqr_reg[17]_i_13_n_7\,
      DI(7) => \xsqr[17]_i_19_n_0\,
      DI(6) => \xsqr[17]_i_20_n_0\,
      DI(5) => \xsqr[17]_i_21_n_0\,
      DI(4) => \xsqr[17]_i_22_n_0\,
      DI(3) => \xsqr[17]_i_23_n_0\,
      DI(2) => \xsqr[3]_i_31_n_0\,
      DI(1) => \xsqr[17]_i_24_n_0\,
      DI(0) => '0',
      O(7) => \xsqr_reg[17]_i_13_n_8\,
      O(6) => \xsqr_reg[17]_i_13_n_9\,
      O(5) => \xsqr_reg[17]_i_13_n_10\,
      O(4) => \xsqr_reg[17]_i_13_n_11\,
      O(3) => \xsqr_reg[17]_i_13_n_12\,
      O(2) => \xsqr_reg[17]_i_13_n_13\,
      O(1) => \xsqr_reg[17]_i_13_n_14\,
      O(0) => \xsqr_reg[17]_i_13_n_15\,
      S(7) => \xsqr[17]_i_25_n_0\,
      S(6) => \xsqr[17]_i_26_n_0\,
      S(5) => \xsqr[17]_i_27_n_0\,
      S(4) => \xsqr[17]_i_28_n_0\,
      S(3) => \xsqr[17]_i_29_n_0\,
      S(2) => \xsqr[17]_i_30_n_0\,
      S(1) => \xsqr[17]_i_31_n_0\,
      S(0) => \xsqr[17]_i_32_n_0\
    );
\xsqr_reg[17]_i_17\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[3]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xsqr_reg[17]_i_17_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xsqr_reg[17]_i_17_n_4\,
      CO(2) => \NLW_xsqr_reg[17]_i_17_CO_UNCONNECTED\(2),
      CO(1) => \xsqr_reg[17]_i_17_n_6\,
      CO(0) => \xsqr_reg[17]_i_17_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xsqr[17]_i_33_n_0\,
      DI(1) => \xsqr[17]_i_34_n_0\,
      DI(0) => \xsqr[17]_i_35_n_0\,
      O(7 downto 3) => \NLW_xsqr_reg[17]_i_17_O_UNCONNECTED\(7 downto 3),
      O(2) => \xsqr_reg[17]_i_17_n_13\,
      O(1) => \xsqr_reg[17]_i_17_n_14\,
      O(0) => \xsqr_reg[17]_i_17_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xsqr[17]_i_36_n_0\,
      S(1) => \xsqr[17]_i_37_n_0\,
      S(0) => \xsqr[17]_i_38_n_0\
    );
\xsqr_reg[17]_i_18\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[3]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xsqr_reg[17]_i_18_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xsqr_reg[17]_i_18_n_5\,
      CO(1) => \NLW_xsqr_reg[17]_i_18_CO_UNCONNECTED\(1),
      CO(0) => \xsqr_reg[17]_i_18_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \xsqr[17]_i_39_n_0\,
      DI(0) => \xsqr[17]_i_40_n_0\,
      O(7 downto 2) => \NLW_xsqr_reg[17]_i_18_O_UNCONNECTED\(7 downto 2),
      O(1) => \xsqr_reg[17]_i_18_n_14\,
      O(0) => \xsqr_reg[17]_i_18_n_15\,
      S(7 downto 2) => B"000001",
      S(1) => \xsqr[17]_i_41_n_0\,
      S(0) => \xsqr[17]_i_42_n_0\
    );
\xsqr_reg[17]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[11]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_xsqr_reg[17]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \xsqr_reg[17]_i_2_n_3\,
      CO(3) => \xsqr_reg[17]_i_2_n_4\,
      CO(2) => \xsqr_reg[17]_i_2_n_5\,
      CO(1) => \xsqr_reg[17]_i_2_n_6\,
      CO(0) => \xsqr_reg[17]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \xsqr_reg[17]_i_3_n_13\,
      DI(3) => \xsqr[17]_i_4_n_0\,
      DI(2) => \xsqr[17]_i_5_n_0\,
      DI(1) => \xsqr[17]_i_6_n_0\,
      DI(0) => \xsqr[17]_i_7_n_0\,
      O(7 downto 6) => \NLW_xsqr_reg[17]_i_2_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => xsqr0(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \xsqr_reg[17]_i_3_n_12\,
      S(4) => \xsqr[17]_i_8_n_0\,
      S(3) => \xsqr[17]_i_9_n_0\,
      S(2) => \xsqr[17]_i_10_n_0\,
      S(1) => \xsqr[17]_i_11_n_0\,
      S(0) => \xsqr[17]_i_12_n_0\
    );
\xsqr_reg[17]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[17]_i_13_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xsqr_reg[17]_i_3_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xsqr_reg[17]_i_3_n_5\,
      CO(1) => \xsqr_reg[17]_i_3_n_6\,
      CO(0) => \xsqr_reg[17]_i_3_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \dx_reg_n_0_[8]\,
      DI(1) => '0',
      DI(0) => \dx_reg_n_0_[7]\,
      O(7 downto 4) => \NLW_xsqr_reg[17]_i_3_O_UNCONNECTED\(7 downto 4),
      O(3) => \xsqr_reg[17]_i_3_n_12\,
      O(2) => \xsqr_reg[17]_i_3_n_13\,
      O(1) => \xsqr_reg[17]_i_3_n_14\,
      O(0) => \xsqr_reg[17]_i_3_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xsqr[17]_i_14_n_0\,
      S(1) => \xsqr[17]_i_15_n_0\,
      S(0) => \xsqr[17]_i_16_n_0\
    );
\xsqr_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[18]_i_1_n_0\,
      Q => RESIZE0_in(0)
    );
\xsqr_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[20]_i_1_n_0\,
      Q => RESIZE0_in(2)
    );
\xsqr_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[21]_i_1_n_0\,
      Q => RESIZE0_in(3)
    );
\xsqr_reg[21]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[21]_i_2_n_0\,
      CO(6) => \xsqr_reg[21]_i_2_n_1\,
      CO(5) => \xsqr_reg[21]_i_2_n_2\,
      CO(4) => \xsqr_reg[21]_i_2_n_3\,
      CO(3) => \xsqr_reg[21]_i_2_n_4\,
      CO(2) => \xsqr_reg[21]_i_2_n_5\,
      CO(1) => \xsqr_reg[21]_i_2_n_6\,
      CO(0) => \xsqr_reg[21]_i_2_n_7\,
      DI(7) => \xsqr[21]_i_4_n_0\,
      DI(6) => \xsqr[21]_i_5_n_0\,
      DI(5) => \xsqr[21]_i_6_n_0\,
      DI(4) => \xsqr[21]_i_7_n_0\,
      DI(3) => \xsqr[21]_i_8_n_0\,
      DI(2) => \xsqr[21]_i_9_n_0\,
      DI(1) => A(1),
      DI(0) => '0',
      O(7) => \xsqr_reg[21]_i_2_n_8\,
      O(6) => \xsqr_reg[21]_i_2_n_9\,
      O(5) => \xsqr_reg[21]_i_2_n_10\,
      O(4) => \xsqr_reg[21]_i_2_n_11\,
      O(3) => \xsqr_reg[21]_i_2_n_12\,
      O(2) => \xsqr_reg[21]_i_2_n_13\,
      O(1) => xsqr00_in(2),
      O(0) => \NLW_xsqr_reg[21]_i_2_O_UNCONNECTED\(0),
      S(7) => \xsqr[21]_i_10_n_0\,
      S(6) => \xsqr[21]_i_11_n_0\,
      S(5) => \xsqr[21]_i_12_n_0\,
      S(4) => \xsqr[21]_i_13_n_0\,
      S(3) => \xsqr[21]_i_14_n_0\,
      S(2) => \xsqr[21]_i_15_n_0\,
      S(1) => \xsqr[21]_i_16_n_0\,
      S(0) => '0'
    );
\xsqr_reg[21]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[21]_i_3_n_0\,
      CO(6) => \xsqr_reg[21]_i_3_n_1\,
      CO(5) => \xsqr_reg[21]_i_3_n_2\,
      CO(4) => \xsqr_reg[21]_i_3_n_3\,
      CO(3) => \xsqr_reg[21]_i_3_n_4\,
      CO(2) => \xsqr_reg[21]_i_3_n_5\,
      CO(1) => \xsqr_reg[21]_i_3_n_6\,
      CO(0) => \xsqr_reg[21]_i_3_n_7\,
      DI(7) => \xsqr[21]_i_17_n_0\,
      DI(6) => \xsqr[21]_i_18_n_0\,
      DI(5) => A(4),
      DI(4) => \xsqr[21]_i_19_n_0\,
      DI(3) => \xsqr[21]_i_20_n_0\,
      DI(2) => \xsqr[21]_i_21_n_0\,
      DI(1) => \xsqr[21]_i_22_n_0\,
      DI(0) => '0',
      O(7) => \xsqr_reg[21]_i_3_n_8\,
      O(6) => \xsqr_reg[21]_i_3_n_9\,
      O(5) => \xsqr_reg[21]_i_3_n_10\,
      O(4) => \xsqr_reg[21]_i_3_n_11\,
      O(3) => \xsqr_reg[21]_i_3_n_12\,
      O(2) => \xsqr_reg[21]_i_3_n_13\,
      O(1) => \xsqr_reg[21]_i_3_n_14\,
      O(0) => \xsqr_reg[21]_i_3_n_15\,
      S(7) => \xsqr[21]_i_23_n_0\,
      S(6) => \xsqr[21]_i_24_n_0\,
      S(5) => \xsqr[21]_i_25_n_0\,
      S(4) => \xsqr[21]_i_26_n_0\,
      S(3) => \xsqr[21]_i_27_n_0\,
      S(2) => \xsqr[21]_i_28_n_0\,
      S(1) => \xsqr[21]_i_29_n_0\,
      S(0) => \xsqr[21]_i_30_n_0\
    );
\xsqr_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[22]_i_1_n_0\,
      Q => RESIZE0_in(4)
    );
\xsqr_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[23]_i_1_n_0\,
      Q => RESIZE0_in(5)
    );
\xsqr_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[24]_i_1_n_0\,
      Q => RESIZE0_in(6)
    );
\xsqr_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[25]_i_1_n_0\,
      Q => RESIZE0_in(7)
    );
\xsqr_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[26]_i_1_n_0\,
      Q => RESIZE0_in(8)
    );
\xsqr_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[27]_i_1_n_0\,
      Q => RESIZE0_in(9)
    );
\xsqr_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[28]_i_1_n_0\,
      Q => RESIZE0_in(10)
    );
\xsqr_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[29]_i_1_n_0\,
      Q => RESIZE0_in(11)
    );
\xsqr_reg[29]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[29]_i_2_n_0\,
      CO(6) => \xsqr_reg[29]_i_2_n_1\,
      CO(5) => \xsqr_reg[29]_i_2_n_2\,
      CO(4) => \xsqr_reg[29]_i_2_n_3\,
      CO(3) => \xsqr_reg[29]_i_2_n_4\,
      CO(2) => \xsqr_reg[29]_i_2_n_5\,
      CO(1) => \xsqr_reg[29]_i_2_n_6\,
      CO(0) => \xsqr_reg[29]_i_2_n_7\,
      DI(7) => \xsqr[29]_i_3_n_0\,
      DI(6) => \xsqr[29]_i_4_n_0\,
      DI(5) => \xsqr[29]_i_5_n_0\,
      DI(4) => \xsqr[29]_i_6_n_0\,
      DI(3) => \xsqr[29]_i_7_n_0\,
      DI(2) => \xsqr[29]_i_8_n_0\,
      DI(1) => \xsqr[29]_i_9_n_0\,
      DI(0) => \xsqr[29]_i_10_n_0\,
      O(7 downto 0) => xsqr00_in(11 downto 4),
      S(7) => \xsqr[29]_i_11_n_0\,
      S(6) => \xsqr[29]_i_12_n_0\,
      S(5) => \xsqr[29]_i_13_n_0\,
      S(4) => \xsqr[29]_i_14_n_0\,
      S(3) => \xsqr[29]_i_15_n_0\,
      S(2) => \xsqr[29]_i_16_n_0\,
      S(1) => \xsqr[29]_i_17_n_0\,
      S(0) => \xsqr[29]_i_18_n_0\
    );
\xsqr_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[2]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[2]\
    );
\xsqr_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[30]_i_1_n_0\,
      Q => RESIZE0_in(12)
    );
\xsqr_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[31]_i_1_n_0\,
      Q => RESIZE0_in(13)
    );
\xsqr_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[32]_i_1_n_0\,
      Q => RESIZE0_in(14)
    );
\xsqr_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[33]_i_1_n_0\,
      Q => RESIZE0_in(15)
    );
\xsqr_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[34]_i_1_n_0\,
      Q => RESIZE0_in(16)
    );
\xsqr_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[35]_i_1_n_0\,
      Q => RESIZE0_in(17)
    );
\xsqr_reg[35]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[35]_i_13_n_0\,
      CO(6) => \xsqr_reg[35]_i_13_n_1\,
      CO(5) => \xsqr_reg[35]_i_13_n_2\,
      CO(4) => \xsqr_reg[35]_i_13_n_3\,
      CO(3) => \xsqr_reg[35]_i_13_n_4\,
      CO(2) => \xsqr_reg[35]_i_13_n_5\,
      CO(1) => \xsqr_reg[35]_i_13_n_6\,
      CO(0) => \xsqr_reg[35]_i_13_n_7\,
      DI(7) => \xsqr[35]_i_19_n_0\,
      DI(6) => \xsqr[35]_i_20_n_0\,
      DI(5) => \xsqr[35]_i_21_n_0\,
      DI(4) => \xsqr[35]_i_22_n_0\,
      DI(3) => \xsqr[35]_i_23_n_0\,
      DI(2) => \xsqr[21]_i_31_n_0\,
      DI(1) => \xsqr[35]_i_24_n_0\,
      DI(0) => '0',
      O(7) => \xsqr_reg[35]_i_13_n_8\,
      O(6) => \xsqr_reg[35]_i_13_n_9\,
      O(5) => \xsqr_reg[35]_i_13_n_10\,
      O(4) => \xsqr_reg[35]_i_13_n_11\,
      O(3) => \xsqr_reg[35]_i_13_n_12\,
      O(2) => \xsqr_reg[35]_i_13_n_13\,
      O(1) => \xsqr_reg[35]_i_13_n_14\,
      O(0) => \xsqr_reg[35]_i_13_n_15\,
      S(7) => \xsqr[35]_i_25_n_0\,
      S(6) => \xsqr[35]_i_26_n_0\,
      S(5) => \xsqr[35]_i_27_n_0\,
      S(4) => \xsqr[35]_i_28_n_0\,
      S(3) => \xsqr[35]_i_29_n_0\,
      S(2) => \xsqr[35]_i_30_n_0\,
      S(1) => \xsqr[35]_i_31_n_0\,
      S(0) => \xsqr[35]_i_32_n_0\
    );
\xsqr_reg[35]_i_17\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[21]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xsqr_reg[35]_i_17_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xsqr_reg[35]_i_17_n_4\,
      CO(2) => \NLW_xsqr_reg[35]_i_17_CO_UNCONNECTED\(2),
      CO(1) => \xsqr_reg[35]_i_17_n_6\,
      CO(0) => \xsqr_reg[35]_i_17_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xsqr[35]_i_33_n_0\,
      DI(1) => \xsqr[35]_i_34_n_0\,
      DI(0) => \xsqr[35]_i_35_n_0\,
      O(7 downto 3) => \NLW_xsqr_reg[35]_i_17_O_UNCONNECTED\(7 downto 3),
      O(2) => \xsqr_reg[35]_i_17_n_13\,
      O(1) => \xsqr_reg[35]_i_17_n_14\,
      O(0) => \xsqr_reg[35]_i_17_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xsqr[35]_i_36_n_0\,
      S(1) => \xsqr[35]_i_37_n_0\,
      S(0) => \xsqr[35]_i_38_n_0\
    );
\xsqr_reg[35]_i_18\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[21]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xsqr_reg[35]_i_18_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xsqr_reg[35]_i_18_n_5\,
      CO(1) => \NLW_xsqr_reg[35]_i_18_CO_UNCONNECTED\(1),
      CO(0) => \xsqr_reg[35]_i_18_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \xsqr[35]_i_39_n_0\,
      DI(0) => \xsqr[35]_i_40_n_0\,
      O(7 downto 2) => \NLW_xsqr_reg[35]_i_18_O_UNCONNECTED\(7 downto 2),
      O(1) => \xsqr_reg[35]_i_18_n_14\,
      O(0) => \xsqr_reg[35]_i_18_n_15\,
      S(7 downto 2) => B"000001",
      S(1) => \xsqr[35]_i_41_n_0\,
      S(0) => \xsqr[35]_i_42_n_0\
    );
\xsqr_reg[35]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[29]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_xsqr_reg[35]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \xsqr_reg[35]_i_2_n_3\,
      CO(3) => \xsqr_reg[35]_i_2_n_4\,
      CO(2) => \xsqr_reg[35]_i_2_n_5\,
      CO(1) => \xsqr_reg[35]_i_2_n_6\,
      CO(0) => \xsqr_reg[35]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \xsqr_reg[35]_i_3_n_13\,
      DI(3) => \xsqr[35]_i_4_n_0\,
      DI(2) => \xsqr[35]_i_5_n_0\,
      DI(1) => \xsqr[35]_i_6_n_0\,
      DI(0) => \xsqr[35]_i_7_n_0\,
      O(7 downto 6) => \NLW_xsqr_reg[35]_i_2_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => xsqr00_in(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \xsqr_reg[35]_i_3_n_12\,
      S(4) => \xsqr[35]_i_8_n_0\,
      S(3) => \xsqr[35]_i_9_n_0\,
      S(2) => \xsqr[35]_i_10_n_0\,
      S(1) => \xsqr[35]_i_11_n_0\,
      S(0) => \xsqr[35]_i_12_n_0\
    );
\xsqr_reg[35]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[35]_i_13_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xsqr_reg[35]_i_3_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xsqr_reg[35]_i_3_n_5\,
      CO(1) => \xsqr_reg[35]_i_3_n_6\,
      CO(0) => \xsqr_reg[35]_i_3_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => A(8),
      DI(1) => '0',
      DI(0) => A(7),
      O(7 downto 4) => \NLW_xsqr_reg[35]_i_3_O_UNCONNECTED\(7 downto 4),
      O(3) => \xsqr_reg[35]_i_3_n_12\,
      O(2) => \xsqr_reg[35]_i_3_n_13\,
      O(1) => \xsqr_reg[35]_i_3_n_14\,
      O(0) => \xsqr_reg[35]_i_3_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xsqr[35]_i_14_n_0\,
      S(1) => \xsqr[35]_i_15_n_0\,
      S(0) => \xsqr[35]_i_16_n_0\
    );
\xsqr_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[36]_i_1_n_0\,
      Q => RESIZE(0)
    );
\xsqr_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[38]_i_1_n_0\,
      Q => RESIZE(2)
    );
\xsqr_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[39]_i_1_n_0\,
      Q => RESIZE(3)
    );
\xsqr_reg[39]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[39]_i_2_n_0\,
      CO(6) => \xsqr_reg[39]_i_2_n_1\,
      CO(5) => \xsqr_reg[39]_i_2_n_2\,
      CO(4) => \xsqr_reg[39]_i_2_n_3\,
      CO(3) => \xsqr_reg[39]_i_2_n_4\,
      CO(2) => \xsqr_reg[39]_i_2_n_5\,
      CO(1) => \xsqr_reg[39]_i_2_n_6\,
      CO(0) => \xsqr_reg[39]_i_2_n_7\,
      DI(7) => \xsqr[39]_i_4_n_0\,
      DI(6) => \xsqr[39]_i_5_n_0\,
      DI(5) => \xsqr[39]_i_6_n_0\,
      DI(4) => \xsqr[39]_i_7_n_0\,
      DI(3) => \xsqr[39]_i_8_n_0\,
      DI(2) => \xsqr[39]_i_9_n_0\,
      DI(1) => \dx_reg_n_0_[19]\,
      DI(0) => '0',
      O(7) => \xsqr_reg[39]_i_2_n_8\,
      O(6) => \xsqr_reg[39]_i_2_n_9\,
      O(5) => \xsqr_reg[39]_i_2_n_10\,
      O(4) => \xsqr_reg[39]_i_2_n_11\,
      O(3) => \xsqr_reg[39]_i_2_n_12\,
      O(2) => \xsqr_reg[39]_i_2_n_13\,
      O(1) => xsqr01_in(2),
      O(0) => \NLW_xsqr_reg[39]_i_2_O_UNCONNECTED\(0),
      S(7) => \xsqr[39]_i_10_n_0\,
      S(6) => \xsqr[39]_i_11_n_0\,
      S(5) => \xsqr[39]_i_12_n_0\,
      S(4) => \xsqr[39]_i_13_n_0\,
      S(3) => \xsqr[39]_i_14_n_0\,
      S(2) => \xsqr[39]_i_15_n_0\,
      S(1) => \xsqr[39]_i_16_n_0\,
      S(0) => '0'
    );
\xsqr_reg[39]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[39]_i_3_n_0\,
      CO(6) => \xsqr_reg[39]_i_3_n_1\,
      CO(5) => \xsqr_reg[39]_i_3_n_2\,
      CO(4) => \xsqr_reg[39]_i_3_n_3\,
      CO(3) => \xsqr_reg[39]_i_3_n_4\,
      CO(2) => \xsqr_reg[39]_i_3_n_5\,
      CO(1) => \xsqr_reg[39]_i_3_n_6\,
      CO(0) => \xsqr_reg[39]_i_3_n_7\,
      DI(7) => \xsqr[39]_i_17_n_0\,
      DI(6) => \xsqr[39]_i_18_n_0\,
      DI(5) => \dx_reg_n_0_[22]\,
      DI(4) => \xsqr[39]_i_19_n_0\,
      DI(3) => \xsqr[39]_i_20_n_0\,
      DI(2) => \xsqr[39]_i_21_n_0\,
      DI(1) => \xsqr[39]_i_22_n_0\,
      DI(0) => '0',
      O(7) => \xsqr_reg[39]_i_3_n_8\,
      O(6) => \xsqr_reg[39]_i_3_n_9\,
      O(5) => \xsqr_reg[39]_i_3_n_10\,
      O(4) => \xsqr_reg[39]_i_3_n_11\,
      O(3) => \xsqr_reg[39]_i_3_n_12\,
      O(2) => \xsqr_reg[39]_i_3_n_13\,
      O(1) => \xsqr_reg[39]_i_3_n_14\,
      O(0) => \xsqr_reg[39]_i_3_n_15\,
      S(7) => \xsqr[39]_i_23_n_0\,
      S(6) => \xsqr[39]_i_24_n_0\,
      S(5) => \xsqr[39]_i_25_n_0\,
      S(4) => \xsqr[39]_i_26_n_0\,
      S(3) => \xsqr[39]_i_27_n_0\,
      S(2) => \xsqr[39]_i_28_n_0\,
      S(1) => \xsqr[39]_i_29_n_0\,
      S(0) => \xsqr[39]_i_30_n_0\
    );
\xsqr_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[3]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[3]\
    );
\xsqr_reg[3]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[3]_i_2_n_0\,
      CO(6) => \xsqr_reg[3]_i_2_n_1\,
      CO(5) => \xsqr_reg[3]_i_2_n_2\,
      CO(4) => \xsqr_reg[3]_i_2_n_3\,
      CO(3) => \xsqr_reg[3]_i_2_n_4\,
      CO(2) => \xsqr_reg[3]_i_2_n_5\,
      CO(1) => \xsqr_reg[3]_i_2_n_6\,
      CO(0) => \xsqr_reg[3]_i_2_n_7\,
      DI(7) => \xsqr[3]_i_4_n_0\,
      DI(6) => \xsqr[3]_i_5_n_0\,
      DI(5) => \xsqr[3]_i_6_n_0\,
      DI(4) => \xsqr[3]_i_7_n_0\,
      DI(3) => \xsqr[3]_i_8_n_0\,
      DI(2) => \xsqr[3]_i_9_n_0\,
      DI(1) => \dx_reg_n_0_[1]\,
      DI(0) => '0',
      O(7) => \xsqr_reg[3]_i_2_n_8\,
      O(6) => \xsqr_reg[3]_i_2_n_9\,
      O(5) => \xsqr_reg[3]_i_2_n_10\,
      O(4) => \xsqr_reg[3]_i_2_n_11\,
      O(3) => \xsqr_reg[3]_i_2_n_12\,
      O(2) => \xsqr_reg[3]_i_2_n_13\,
      O(1) => xsqr0(2),
      O(0) => \NLW_xsqr_reg[3]_i_2_O_UNCONNECTED\(0),
      S(7) => \xsqr[3]_i_10_n_0\,
      S(6) => \xsqr[3]_i_11_n_0\,
      S(5) => \xsqr[3]_i_12_n_0\,
      S(4) => \xsqr[3]_i_13_n_0\,
      S(3) => \xsqr[3]_i_14_n_0\,
      S(2) => \xsqr[3]_i_15_n_0\,
      S(1) => \xsqr[3]_i_16_n_0\,
      S(0) => '0'
    );
\xsqr_reg[3]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[3]_i_3_n_0\,
      CO(6) => \xsqr_reg[3]_i_3_n_1\,
      CO(5) => \xsqr_reg[3]_i_3_n_2\,
      CO(4) => \xsqr_reg[3]_i_3_n_3\,
      CO(3) => \xsqr_reg[3]_i_3_n_4\,
      CO(2) => \xsqr_reg[3]_i_3_n_5\,
      CO(1) => \xsqr_reg[3]_i_3_n_6\,
      CO(0) => \xsqr_reg[3]_i_3_n_7\,
      DI(7) => \xsqr[3]_i_17_n_0\,
      DI(6) => \xsqr[3]_i_18_n_0\,
      DI(5) => \dx_reg_n_0_[4]\,
      DI(4) => \xsqr[3]_i_19_n_0\,
      DI(3) => \xsqr[3]_i_20_n_0\,
      DI(2) => \xsqr[3]_i_21_n_0\,
      DI(1) => \xsqr[3]_i_22_n_0\,
      DI(0) => '0',
      O(7) => \xsqr_reg[3]_i_3_n_8\,
      O(6) => \xsqr_reg[3]_i_3_n_9\,
      O(5) => \xsqr_reg[3]_i_3_n_10\,
      O(4) => \xsqr_reg[3]_i_3_n_11\,
      O(3) => \xsqr_reg[3]_i_3_n_12\,
      O(2) => \xsqr_reg[3]_i_3_n_13\,
      O(1) => \xsqr_reg[3]_i_3_n_14\,
      O(0) => \xsqr_reg[3]_i_3_n_15\,
      S(7) => \xsqr[3]_i_23_n_0\,
      S(6) => \xsqr[3]_i_24_n_0\,
      S(5) => \xsqr[3]_i_25_n_0\,
      S(4) => \xsqr[3]_i_26_n_0\,
      S(3) => \xsqr[3]_i_27_n_0\,
      S(2) => \xsqr[3]_i_28_n_0\,
      S(1) => \xsqr[3]_i_29_n_0\,
      S(0) => \xsqr[3]_i_30_n_0\
    );
\xsqr_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[40]_i_1_n_0\,
      Q => RESIZE(4)
    );
\xsqr_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[41]_i_1_n_0\,
      Q => RESIZE(5)
    );
\xsqr_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[42]_i_1_n_0\,
      Q => RESIZE(6)
    );
\xsqr_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[43]_i_1_n_0\,
      Q => RESIZE(7)
    );
\xsqr_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[44]_i_1_n_0\,
      Q => RESIZE(8)
    );
\xsqr_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[45]_i_1_n_0\,
      Q => RESIZE(9)
    );
\xsqr_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[46]_i_1_n_0\,
      Q => RESIZE(10)
    );
\xsqr_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[47]_i_1_n_0\,
      Q => RESIZE(11)
    );
\xsqr_reg[47]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[47]_i_2_n_0\,
      CO(6) => \xsqr_reg[47]_i_2_n_1\,
      CO(5) => \xsqr_reg[47]_i_2_n_2\,
      CO(4) => \xsqr_reg[47]_i_2_n_3\,
      CO(3) => \xsqr_reg[47]_i_2_n_4\,
      CO(2) => \xsqr_reg[47]_i_2_n_5\,
      CO(1) => \xsqr_reg[47]_i_2_n_6\,
      CO(0) => \xsqr_reg[47]_i_2_n_7\,
      DI(7) => \xsqr[47]_i_3_n_0\,
      DI(6) => \xsqr[47]_i_4_n_0\,
      DI(5) => \xsqr[47]_i_5_n_0\,
      DI(4) => \xsqr[47]_i_6_n_0\,
      DI(3) => \xsqr[47]_i_7_n_0\,
      DI(2) => \xsqr[47]_i_8_n_0\,
      DI(1) => \xsqr[47]_i_9_n_0\,
      DI(0) => \xsqr[47]_i_10_n_0\,
      O(7 downto 0) => xsqr01_in(11 downto 4),
      S(7) => \xsqr[47]_i_11_n_0\,
      S(6) => \xsqr[47]_i_12_n_0\,
      S(5) => \xsqr[47]_i_13_n_0\,
      S(4) => \xsqr[47]_i_14_n_0\,
      S(3) => \xsqr[47]_i_15_n_0\,
      S(2) => \xsqr[47]_i_16_n_0\,
      S(1) => \xsqr[47]_i_17_n_0\,
      S(0) => \xsqr[47]_i_18_n_0\
    );
\xsqr_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[48]_i_1_n_0\,
      Q => RESIZE(12)
    );
\xsqr_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[49]_i_1_n_0\,
      Q => RESIZE(13)
    );
\xsqr_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[4]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[4]\
    );
\xsqr_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[50]_i_1_n_0\,
      Q => RESIZE(14)
    );
\xsqr_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[51]_i_1_n_0\,
      Q => RESIZE(15)
    );
\xsqr_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[52]_i_1_n_0\,
      Q => RESIZE(16)
    );
\xsqr_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[53]_i_1_n_0\,
      Q => RESIZE(17)
    );
\xsqr_reg[53]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[53]_i_13_n_0\,
      CO(6) => \xsqr_reg[53]_i_13_n_1\,
      CO(5) => \xsqr_reg[53]_i_13_n_2\,
      CO(4) => \xsqr_reg[53]_i_13_n_3\,
      CO(3) => \xsqr_reg[53]_i_13_n_4\,
      CO(2) => \xsqr_reg[53]_i_13_n_5\,
      CO(1) => \xsqr_reg[53]_i_13_n_6\,
      CO(0) => \xsqr_reg[53]_i_13_n_7\,
      DI(7) => \xsqr[53]_i_19_n_0\,
      DI(6) => \xsqr[53]_i_20_n_0\,
      DI(5) => \xsqr[53]_i_21_n_0\,
      DI(4) => \xsqr[53]_i_22_n_0\,
      DI(3) => \xsqr[53]_i_23_n_0\,
      DI(2) => \xsqr[39]_i_31_n_0\,
      DI(1) => \xsqr[53]_i_24_n_0\,
      DI(0) => '0',
      O(7) => \xsqr_reg[53]_i_13_n_8\,
      O(6) => \xsqr_reg[53]_i_13_n_9\,
      O(5) => \xsqr_reg[53]_i_13_n_10\,
      O(4) => \xsqr_reg[53]_i_13_n_11\,
      O(3) => \xsqr_reg[53]_i_13_n_12\,
      O(2) => \xsqr_reg[53]_i_13_n_13\,
      O(1) => \xsqr_reg[53]_i_13_n_14\,
      O(0) => \xsqr_reg[53]_i_13_n_15\,
      S(7) => \xsqr[53]_i_25_n_0\,
      S(6) => \xsqr[53]_i_26_n_0\,
      S(5) => \xsqr[53]_i_27_n_0\,
      S(4) => \xsqr[53]_i_28_n_0\,
      S(3) => \xsqr[53]_i_29_n_0\,
      S(2) => \xsqr[53]_i_30_n_0\,
      S(1) => \xsqr[53]_i_31_n_0\,
      S(0) => \xsqr[53]_i_32_n_0\
    );
\xsqr_reg[53]_i_17\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[39]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xsqr_reg[53]_i_17_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xsqr_reg[53]_i_17_n_4\,
      CO(2) => \NLW_xsqr_reg[53]_i_17_CO_UNCONNECTED\(2),
      CO(1) => \xsqr_reg[53]_i_17_n_6\,
      CO(0) => \xsqr_reg[53]_i_17_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xsqr[53]_i_33_n_0\,
      DI(1) => \xsqr[53]_i_34_n_0\,
      DI(0) => \xsqr[53]_i_35_n_0\,
      O(7 downto 3) => \NLW_xsqr_reg[53]_i_17_O_UNCONNECTED\(7 downto 3),
      O(2) => \xsqr_reg[53]_i_17_n_13\,
      O(1) => \xsqr_reg[53]_i_17_n_14\,
      O(0) => \xsqr_reg[53]_i_17_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xsqr[53]_i_36_n_0\,
      S(1) => \xsqr[53]_i_37_n_0\,
      S(0) => \xsqr[53]_i_38_n_0\
    );
\xsqr_reg[53]_i_18\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[39]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xsqr_reg[53]_i_18_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xsqr_reg[53]_i_18_n_5\,
      CO(1) => \NLW_xsqr_reg[53]_i_18_CO_UNCONNECTED\(1),
      CO(0) => \xsqr_reg[53]_i_18_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \xsqr[53]_i_39_n_0\,
      DI(0) => \xsqr[53]_i_40_n_0\,
      O(7 downto 2) => \NLW_xsqr_reg[53]_i_18_O_UNCONNECTED\(7 downto 2),
      O(1) => \xsqr_reg[53]_i_18_n_14\,
      O(0) => \xsqr_reg[53]_i_18_n_15\,
      S(7 downto 2) => B"000001",
      S(1) => \xsqr[53]_i_41_n_0\,
      S(0) => \xsqr[53]_i_42_n_0\
    );
\xsqr_reg[53]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[47]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_xsqr_reg[53]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \xsqr_reg[53]_i_2_n_3\,
      CO(3) => \xsqr_reg[53]_i_2_n_4\,
      CO(2) => \xsqr_reg[53]_i_2_n_5\,
      CO(1) => \xsqr_reg[53]_i_2_n_6\,
      CO(0) => \xsqr_reg[53]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \xsqr_reg[53]_i_3_n_13\,
      DI(3) => \xsqr[53]_i_4_n_0\,
      DI(2) => \xsqr[53]_i_5_n_0\,
      DI(1) => \xsqr[53]_i_6_n_0\,
      DI(0) => \xsqr[53]_i_7_n_0\,
      O(7 downto 6) => \NLW_xsqr_reg[53]_i_2_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => xsqr01_in(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \xsqr_reg[53]_i_3_n_12\,
      S(4) => \xsqr[53]_i_8_n_0\,
      S(3) => \xsqr[53]_i_9_n_0\,
      S(2) => \xsqr[53]_i_10_n_0\,
      S(1) => \xsqr[53]_i_11_n_0\,
      S(0) => \xsqr[53]_i_12_n_0\
    );
\xsqr_reg[53]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[53]_i_13_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xsqr_reg[53]_i_3_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xsqr_reg[53]_i_3_n_5\,
      CO(1) => \xsqr_reg[53]_i_3_n_6\,
      CO(0) => \xsqr_reg[53]_i_3_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \dx_reg_n_0_[26]\,
      DI(1) => '0',
      DI(0) => \dx_reg_n_0_[25]\,
      O(7 downto 4) => \NLW_xsqr_reg[53]_i_3_O_UNCONNECTED\(7 downto 4),
      O(3) => \xsqr_reg[53]_i_3_n_12\,
      O(2) => \xsqr_reg[53]_i_3_n_13\,
      O(1) => \xsqr_reg[53]_i_3_n_14\,
      O(0) => \xsqr_reg[53]_i_3_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xsqr[53]_i_14_n_0\,
      S(1) => \xsqr[53]_i_15_n_0\,
      S(0) => \xsqr[53]_i_16_n_0\
    );
\xsqr_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[54]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[54]\
    );
\xsqr_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[56]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[56]\
    );
\xsqr_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[57]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[57]\
    );
\xsqr_reg[57]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[57]_i_2_n_0\,
      CO(6) => \xsqr_reg[57]_i_2_n_1\,
      CO(5) => \xsqr_reg[57]_i_2_n_2\,
      CO(4) => \xsqr_reg[57]_i_2_n_3\,
      CO(3) => \xsqr_reg[57]_i_2_n_4\,
      CO(2) => \xsqr_reg[57]_i_2_n_5\,
      CO(1) => \xsqr_reg[57]_i_2_n_6\,
      CO(0) => \xsqr_reg[57]_i_2_n_7\,
      DI(7) => \xsqr[57]_i_4_n_0\,
      DI(6) => \xsqr[57]_i_5_n_0\,
      DI(5) => \xsqr[57]_i_6_n_0\,
      DI(4) => \xsqr[57]_i_7_n_0\,
      DI(3) => \xsqr[57]_i_8_n_0\,
      DI(2) => \xsqr[57]_i_9_n_0\,
      DI(1) => \dx_reg_n_0_[28]\,
      DI(0) => '0',
      O(7) => \xsqr_reg[57]_i_2_n_8\,
      O(6) => \xsqr_reg[57]_i_2_n_9\,
      O(5) => \xsqr_reg[57]_i_2_n_10\,
      O(4) => \xsqr_reg[57]_i_2_n_11\,
      O(3) => \xsqr_reg[57]_i_2_n_12\,
      O(2) => \xsqr_reg[57]_i_2_n_13\,
      O(1) => xsqr02_in(2),
      O(0) => \NLW_xsqr_reg[57]_i_2_O_UNCONNECTED\(0),
      S(7) => \xsqr[57]_i_10_n_0\,
      S(6) => \xsqr[57]_i_11_n_0\,
      S(5) => \xsqr[57]_i_12_n_0\,
      S(4) => \xsqr[57]_i_13_n_0\,
      S(3) => \xsqr[57]_i_14_n_0\,
      S(2) => \xsqr[57]_i_15_n_0\,
      S(1) => \xsqr[57]_i_16_n_0\,
      S(0) => '0'
    );
\xsqr_reg[57]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[57]_i_3_n_0\,
      CO(6) => \xsqr_reg[57]_i_3_n_1\,
      CO(5) => \xsqr_reg[57]_i_3_n_2\,
      CO(4) => \xsqr_reg[57]_i_3_n_3\,
      CO(3) => \xsqr_reg[57]_i_3_n_4\,
      CO(2) => \xsqr_reg[57]_i_3_n_5\,
      CO(1) => \xsqr_reg[57]_i_3_n_6\,
      CO(0) => \xsqr_reg[57]_i_3_n_7\,
      DI(7) => \xsqr[57]_i_17_n_0\,
      DI(6) => \xsqr[57]_i_18_n_0\,
      DI(5) => \dx_reg_n_0_[31]\,
      DI(4) => \xsqr[57]_i_19_n_0\,
      DI(3) => \xsqr[57]_i_20_n_0\,
      DI(2) => \xsqr[57]_i_21_n_0\,
      DI(1) => \xsqr[57]_i_22_n_0\,
      DI(0) => '0',
      O(7) => \xsqr_reg[57]_i_3_n_8\,
      O(6) => \xsqr_reg[57]_i_3_n_9\,
      O(5) => \xsqr_reg[57]_i_3_n_10\,
      O(4) => \xsqr_reg[57]_i_3_n_11\,
      O(3) => \xsqr_reg[57]_i_3_n_12\,
      O(2) => \xsqr_reg[57]_i_3_n_13\,
      O(1) => \xsqr_reg[57]_i_3_n_14\,
      O(0) => \xsqr_reg[57]_i_3_n_15\,
      S(7) => \xsqr[57]_i_23_n_0\,
      S(6) => \xsqr[57]_i_24_n_0\,
      S(5) => \xsqr[57]_i_25_n_0\,
      S(4) => \xsqr[57]_i_26_n_0\,
      S(3) => \xsqr[57]_i_27_n_0\,
      S(2) => \xsqr[57]_i_28_n_0\,
      S(1) => \xsqr[57]_i_29_n_0\,
      S(0) => \xsqr[57]_i_30_n_0\
    );
\xsqr_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[58]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[58]\
    );
\xsqr_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[59]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[59]\
    );
\xsqr_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[5]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[5]\
    );
\xsqr_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[60]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[60]\
    );
\xsqr_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[61]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[61]\
    );
\xsqr_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[62]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[62]\
    );
\xsqr_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[63]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[63]\
    );
\xsqr_reg[64]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[64]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[64]\
    );
\xsqr_reg[65]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[65]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[65]\
    );
\xsqr_reg[65]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[65]_i_2_n_0\,
      CO(6) => \xsqr_reg[65]_i_2_n_1\,
      CO(5) => \xsqr_reg[65]_i_2_n_2\,
      CO(4) => \xsqr_reg[65]_i_2_n_3\,
      CO(3) => \xsqr_reg[65]_i_2_n_4\,
      CO(2) => \xsqr_reg[65]_i_2_n_5\,
      CO(1) => \xsqr_reg[65]_i_2_n_6\,
      CO(0) => \xsqr_reg[65]_i_2_n_7\,
      DI(7) => \xsqr[65]_i_3_n_0\,
      DI(6) => \xsqr[65]_i_4_n_0\,
      DI(5) => \xsqr[65]_i_5_n_0\,
      DI(4) => \xsqr[65]_i_6_n_0\,
      DI(3) => \xsqr[65]_i_7_n_0\,
      DI(2) => \xsqr[65]_i_8_n_0\,
      DI(1) => \xsqr[65]_i_9_n_0\,
      DI(0) => \xsqr[65]_i_10_n_0\,
      O(7 downto 0) => xsqr02_in(11 downto 4),
      S(7) => \xsqr[65]_i_11_n_0\,
      S(6) => \xsqr[65]_i_12_n_0\,
      S(5) => \xsqr[65]_i_13_n_0\,
      S(4) => \xsqr[65]_i_14_n_0\,
      S(3) => \xsqr[65]_i_15_n_0\,
      S(2) => \xsqr[65]_i_16_n_0\,
      S(1) => \xsqr[65]_i_17_n_0\,
      S(0) => \xsqr[65]_i_18_n_0\
    );
\xsqr_reg[66]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[66]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[66]\
    );
\xsqr_reg[67]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[67]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[67]\
    );
\xsqr_reg[68]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[68]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[68]\
    );
\xsqr_reg[69]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[69]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[69]\
    );
\xsqr_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[6]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[6]\
    );
\xsqr_reg[70]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[70]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[70]\
    );
\xsqr_reg[71]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[71]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[71]\
    );
\xsqr_reg[71]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[71]_i_13_n_0\,
      CO(6) => \xsqr_reg[71]_i_13_n_1\,
      CO(5) => \xsqr_reg[71]_i_13_n_2\,
      CO(4) => \xsqr_reg[71]_i_13_n_3\,
      CO(3) => \xsqr_reg[71]_i_13_n_4\,
      CO(2) => \xsqr_reg[71]_i_13_n_5\,
      CO(1) => \xsqr_reg[71]_i_13_n_6\,
      CO(0) => \xsqr_reg[71]_i_13_n_7\,
      DI(7) => \xsqr[71]_i_19_n_0\,
      DI(6) => \xsqr[71]_i_20_n_0\,
      DI(5) => \xsqr[71]_i_21_n_0\,
      DI(4) => \xsqr[71]_i_22_n_0\,
      DI(3) => \xsqr[71]_i_23_n_0\,
      DI(2) => \xsqr[57]_i_31_n_0\,
      DI(1) => \xsqr[71]_i_24_n_0\,
      DI(0) => '0',
      O(7) => \xsqr_reg[71]_i_13_n_8\,
      O(6) => \xsqr_reg[71]_i_13_n_9\,
      O(5) => \xsqr_reg[71]_i_13_n_10\,
      O(4) => \xsqr_reg[71]_i_13_n_11\,
      O(3) => \xsqr_reg[71]_i_13_n_12\,
      O(2) => \xsqr_reg[71]_i_13_n_13\,
      O(1) => \xsqr_reg[71]_i_13_n_14\,
      O(0) => \xsqr_reg[71]_i_13_n_15\,
      S(7) => \xsqr[71]_i_25_n_0\,
      S(6) => \xsqr[71]_i_26_n_0\,
      S(5) => \xsqr[71]_i_27_n_0\,
      S(4) => \xsqr[71]_i_28_n_0\,
      S(3) => \xsqr[71]_i_29_n_0\,
      S(2) => \xsqr[71]_i_30_n_0\,
      S(1) => \xsqr[71]_i_31_n_0\,
      S(0) => \xsqr[71]_i_32_n_0\
    );
\xsqr_reg[71]_i_17\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[57]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xsqr_reg[71]_i_17_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xsqr_reg[71]_i_17_n_4\,
      CO(2) => \NLW_xsqr_reg[71]_i_17_CO_UNCONNECTED\(2),
      CO(1) => \xsqr_reg[71]_i_17_n_6\,
      CO(0) => \xsqr_reg[71]_i_17_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xsqr[71]_i_33_n_0\,
      DI(1) => \xsqr[71]_i_34_n_0\,
      DI(0) => \xsqr[71]_i_35_n_0\,
      O(7 downto 3) => \NLW_xsqr_reg[71]_i_17_O_UNCONNECTED\(7 downto 3),
      O(2) => \xsqr_reg[71]_i_17_n_13\,
      O(1) => \xsqr_reg[71]_i_17_n_14\,
      O(0) => \xsqr_reg[71]_i_17_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xsqr[71]_i_36_n_0\,
      S(1) => \xsqr[71]_i_37_n_0\,
      S(0) => \xsqr[71]_i_38_n_0\
    );
\xsqr_reg[71]_i_18\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[57]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xsqr_reg[71]_i_18_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xsqr_reg[71]_i_18_n_5\,
      CO(1) => \NLW_xsqr_reg[71]_i_18_CO_UNCONNECTED\(1),
      CO(0) => \xsqr_reg[71]_i_18_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \xsqr[71]_i_39_n_0\,
      DI(0) => \xsqr[71]_i_40_n_0\,
      O(7 downto 2) => \NLW_xsqr_reg[71]_i_18_O_UNCONNECTED\(7 downto 2),
      O(1) => \xsqr_reg[71]_i_18_n_14\,
      O(0) => \xsqr_reg[71]_i_18_n_15\,
      S(7 downto 2) => B"000001",
      S(1) => \xsqr[71]_i_41_n_0\,
      S(0) => \xsqr[71]_i_42_n_0\
    );
\xsqr_reg[71]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[65]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_xsqr_reg[71]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \xsqr_reg[71]_i_2_n_3\,
      CO(3) => \xsqr_reg[71]_i_2_n_4\,
      CO(2) => \xsqr_reg[71]_i_2_n_5\,
      CO(1) => \xsqr_reg[71]_i_2_n_6\,
      CO(0) => \xsqr_reg[71]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \xsqr_reg[71]_i_3_n_13\,
      DI(3) => \xsqr[71]_i_4_n_0\,
      DI(2) => \xsqr[71]_i_5_n_0\,
      DI(1) => \xsqr[71]_i_6_n_0\,
      DI(0) => \xsqr[71]_i_7_n_0\,
      O(7 downto 6) => \NLW_xsqr_reg[71]_i_2_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => xsqr02_in(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \xsqr_reg[71]_i_3_n_12\,
      S(4) => \xsqr[71]_i_8_n_0\,
      S(3) => \xsqr[71]_i_9_n_0\,
      S(2) => \xsqr[71]_i_10_n_0\,
      S(1) => \xsqr[71]_i_11_n_0\,
      S(0) => \xsqr[71]_i_12_n_0\
    );
\xsqr_reg[71]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[71]_i_13_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xsqr_reg[71]_i_3_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xsqr_reg[71]_i_3_n_5\,
      CO(1) => \xsqr_reg[71]_i_3_n_6\,
      CO(0) => \xsqr_reg[71]_i_3_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \dx_reg_n_0_[35]\,
      DI(1) => '0',
      DI(0) => \dx_reg_n_0_[34]\,
      O(7 downto 4) => \NLW_xsqr_reg[71]_i_3_O_UNCONNECTED\(7 downto 4),
      O(3) => \xsqr_reg[71]_i_3_n_12\,
      O(2) => \xsqr_reg[71]_i_3_n_13\,
      O(1) => \xsqr_reg[71]_i_3_n_14\,
      O(0) => \xsqr_reg[71]_i_3_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xsqr[71]_i_14_n_0\,
      S(1) => \xsqr[71]_i_15_n_0\,
      S(0) => \xsqr[71]_i_16_n_0\
    );
\xsqr_reg[72]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[72]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[72]\
    );
\xsqr_reg[74]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[74]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[74]\
    );
\xsqr_reg[75]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[75]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[75]\
    );
\xsqr_reg[75]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[75]_i_2_n_0\,
      CO(6) => \xsqr_reg[75]_i_2_n_1\,
      CO(5) => \xsqr_reg[75]_i_2_n_2\,
      CO(4) => \xsqr_reg[75]_i_2_n_3\,
      CO(3) => \xsqr_reg[75]_i_2_n_4\,
      CO(2) => \xsqr_reg[75]_i_2_n_5\,
      CO(1) => \xsqr_reg[75]_i_2_n_6\,
      CO(0) => \xsqr_reg[75]_i_2_n_7\,
      DI(7) => \xsqr[75]_i_4_n_0\,
      DI(6) => \xsqr[75]_i_5_n_0\,
      DI(5) => \xsqr[75]_i_6_n_0\,
      DI(4) => \xsqr[75]_i_7_n_0\,
      DI(3) => \xsqr[75]_i_8_n_0\,
      DI(2) => \xsqr[75]_i_9_n_0\,
      DI(1) => \dx_reg_n_0_[37]\,
      DI(0) => '0',
      O(7) => \xsqr_reg[75]_i_2_n_8\,
      O(6) => \xsqr_reg[75]_i_2_n_9\,
      O(5) => \xsqr_reg[75]_i_2_n_10\,
      O(4) => \xsqr_reg[75]_i_2_n_11\,
      O(3) => \xsqr_reg[75]_i_2_n_12\,
      O(2) => \xsqr_reg[75]_i_2_n_13\,
      O(1) => xsqr03_in(2),
      O(0) => \NLW_xsqr_reg[75]_i_2_O_UNCONNECTED\(0),
      S(7) => \xsqr[75]_i_10_n_0\,
      S(6) => \xsqr[75]_i_11_n_0\,
      S(5) => \xsqr[75]_i_12_n_0\,
      S(4) => \xsqr[75]_i_13_n_0\,
      S(3) => \xsqr[75]_i_14_n_0\,
      S(2) => \xsqr[75]_i_15_n_0\,
      S(1) => \xsqr[75]_i_16_n_0\,
      S(0) => '0'
    );
\xsqr_reg[75]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[75]_i_3_n_0\,
      CO(6) => \xsqr_reg[75]_i_3_n_1\,
      CO(5) => \xsqr_reg[75]_i_3_n_2\,
      CO(4) => \xsqr_reg[75]_i_3_n_3\,
      CO(3) => \xsqr_reg[75]_i_3_n_4\,
      CO(2) => \xsqr_reg[75]_i_3_n_5\,
      CO(1) => \xsqr_reg[75]_i_3_n_6\,
      CO(0) => \xsqr_reg[75]_i_3_n_7\,
      DI(7) => \xsqr[75]_i_17_n_0\,
      DI(6) => \xsqr[75]_i_18_n_0\,
      DI(5) => \dx_reg_n_0_[40]\,
      DI(4) => \xsqr[75]_i_19_n_0\,
      DI(3) => \xsqr[75]_i_20_n_0\,
      DI(2) => \xsqr[75]_i_21_n_0\,
      DI(1) => \xsqr[75]_i_22_n_0\,
      DI(0) => '0',
      O(7) => \xsqr_reg[75]_i_3_n_8\,
      O(6) => \xsqr_reg[75]_i_3_n_9\,
      O(5) => \xsqr_reg[75]_i_3_n_10\,
      O(4) => \xsqr_reg[75]_i_3_n_11\,
      O(3) => \xsqr_reg[75]_i_3_n_12\,
      O(2) => \xsqr_reg[75]_i_3_n_13\,
      O(1) => \xsqr_reg[75]_i_3_n_14\,
      O(0) => \xsqr_reg[75]_i_3_n_15\,
      S(7) => \xsqr[75]_i_23_n_0\,
      S(6) => \xsqr[75]_i_24_n_0\,
      S(5) => \xsqr[75]_i_25_n_0\,
      S(4) => \xsqr[75]_i_26_n_0\,
      S(3) => \xsqr[75]_i_27_n_0\,
      S(2) => \xsqr[75]_i_28_n_0\,
      S(1) => \xsqr[75]_i_29_n_0\,
      S(0) => \xsqr[75]_i_30_n_0\
    );
\xsqr_reg[76]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[76]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[76]\
    );
\xsqr_reg[77]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[77]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[77]\
    );
\xsqr_reg[78]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[78]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[78]\
    );
\xsqr_reg[79]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[79]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[79]\
    );
\xsqr_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[7]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[7]\
    );
\xsqr_reg[80]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[80]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[80]\
    );
\xsqr_reg[81]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[81]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[81]\
    );
\xsqr_reg[82]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[82]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[82]\
    );
\xsqr_reg[83]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[83]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[83]\
    );
\xsqr_reg[83]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[83]_i_2_n_0\,
      CO(6) => \xsqr_reg[83]_i_2_n_1\,
      CO(5) => \xsqr_reg[83]_i_2_n_2\,
      CO(4) => \xsqr_reg[83]_i_2_n_3\,
      CO(3) => \xsqr_reg[83]_i_2_n_4\,
      CO(2) => \xsqr_reg[83]_i_2_n_5\,
      CO(1) => \xsqr_reg[83]_i_2_n_6\,
      CO(0) => \xsqr_reg[83]_i_2_n_7\,
      DI(7) => \xsqr[83]_i_3_n_0\,
      DI(6) => \xsqr[83]_i_4_n_0\,
      DI(5) => \xsqr[83]_i_5_n_0\,
      DI(4) => \xsqr[83]_i_6_n_0\,
      DI(3) => \xsqr[83]_i_7_n_0\,
      DI(2) => \xsqr[83]_i_8_n_0\,
      DI(1) => \xsqr[83]_i_9_n_0\,
      DI(0) => \xsqr[83]_i_10_n_0\,
      O(7 downto 0) => xsqr03_in(11 downto 4),
      S(7) => \xsqr[83]_i_11_n_0\,
      S(6) => \xsqr[83]_i_12_n_0\,
      S(5) => \xsqr[83]_i_13_n_0\,
      S(4) => \xsqr[83]_i_14_n_0\,
      S(3) => \xsqr[83]_i_15_n_0\,
      S(2) => \xsqr[83]_i_16_n_0\,
      S(1) => \xsqr[83]_i_17_n_0\,
      S(0) => \xsqr[83]_i_18_n_0\
    );
\xsqr_reg[84]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[84]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[84]\
    );
\xsqr_reg[85]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[85]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[85]\
    );
\xsqr_reg[86]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[86]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[86]\
    );
\xsqr_reg[87]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[87]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[87]\
    );
\xsqr_reg[88]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[88]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[88]\
    );
\xsqr_reg[89]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[89]_i_2_n_0\,
      Q => \xsqr_reg_n_0_[89]\
    );
\xsqr_reg[89]_i_14\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xsqr_reg[89]_i_14_n_0\,
      CO(6) => \xsqr_reg[89]_i_14_n_1\,
      CO(5) => \xsqr_reg[89]_i_14_n_2\,
      CO(4) => \xsqr_reg[89]_i_14_n_3\,
      CO(3) => \xsqr_reg[89]_i_14_n_4\,
      CO(2) => \xsqr_reg[89]_i_14_n_5\,
      CO(1) => \xsqr_reg[89]_i_14_n_6\,
      CO(0) => \xsqr_reg[89]_i_14_n_7\,
      DI(7) => \xsqr[89]_i_20_n_0\,
      DI(6) => \xsqr[89]_i_21_n_0\,
      DI(5) => \xsqr[89]_i_22_n_0\,
      DI(4) => \xsqr[89]_i_23_n_0\,
      DI(3) => \xsqr[89]_i_24_n_0\,
      DI(2) => \xsqr[75]_i_31_n_0\,
      DI(1) => \xsqr[89]_i_25_n_0\,
      DI(0) => '0',
      O(7) => \xsqr_reg[89]_i_14_n_8\,
      O(6) => \xsqr_reg[89]_i_14_n_9\,
      O(5) => \xsqr_reg[89]_i_14_n_10\,
      O(4) => \xsqr_reg[89]_i_14_n_11\,
      O(3) => \xsqr_reg[89]_i_14_n_12\,
      O(2) => \xsqr_reg[89]_i_14_n_13\,
      O(1) => \xsqr_reg[89]_i_14_n_14\,
      O(0) => \xsqr_reg[89]_i_14_n_15\,
      S(7) => \xsqr[89]_i_26_n_0\,
      S(6) => \xsqr[89]_i_27_n_0\,
      S(5) => \xsqr[89]_i_28_n_0\,
      S(4) => \xsqr[89]_i_29_n_0\,
      S(3) => \xsqr[89]_i_30_n_0\,
      S(2) => \xsqr[89]_i_31_n_0\,
      S(1) => \xsqr[89]_i_32_n_0\,
      S(0) => \xsqr[89]_i_33_n_0\
    );
\xsqr_reg[89]_i_18\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[75]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xsqr_reg[89]_i_18_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xsqr_reg[89]_i_18_n_4\,
      CO(2) => \NLW_xsqr_reg[89]_i_18_CO_UNCONNECTED\(2),
      CO(1) => \xsqr_reg[89]_i_18_n_6\,
      CO(0) => \xsqr_reg[89]_i_18_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xsqr[89]_i_34_n_0\,
      DI(1) => \xsqr[89]_i_35_n_0\,
      DI(0) => \xsqr[89]_i_36_n_0\,
      O(7 downto 3) => \NLW_xsqr_reg[89]_i_18_O_UNCONNECTED\(7 downto 3),
      O(2) => \xsqr_reg[89]_i_18_n_13\,
      O(1) => \xsqr_reg[89]_i_18_n_14\,
      O(0) => \xsqr_reg[89]_i_18_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xsqr[89]_i_37_n_0\,
      S(1) => \xsqr[89]_i_38_n_0\,
      S(0) => \xsqr[89]_i_39_n_0\
    );
\xsqr_reg[89]_i_19\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[75]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xsqr_reg[89]_i_19_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xsqr_reg[89]_i_19_n_5\,
      CO(1) => \NLW_xsqr_reg[89]_i_19_CO_UNCONNECTED\(1),
      CO(0) => \xsqr_reg[89]_i_19_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \xsqr[89]_i_40_n_0\,
      DI(0) => \xsqr[89]_i_41_n_0\,
      O(7 downto 2) => \NLW_xsqr_reg[89]_i_19_O_UNCONNECTED\(7 downto 2),
      O(1) => \xsqr_reg[89]_i_19_n_14\,
      O(0) => \xsqr_reg[89]_i_19_n_15\,
      S(7 downto 2) => B"000001",
      S(1) => \xsqr[89]_i_42_n_0\,
      S(0) => \xsqr[89]_i_43_n_0\
    );
\xsqr_reg[89]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[83]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_xsqr_reg[89]_i_3_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \xsqr_reg[89]_i_3_n_3\,
      CO(3) => \xsqr_reg[89]_i_3_n_4\,
      CO(2) => \xsqr_reg[89]_i_3_n_5\,
      CO(1) => \xsqr_reg[89]_i_3_n_6\,
      CO(0) => \xsqr_reg[89]_i_3_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \xsqr_reg[89]_i_4_n_13\,
      DI(3) => \xsqr[89]_i_5_n_0\,
      DI(2) => \xsqr[89]_i_6_n_0\,
      DI(1) => \xsqr[89]_i_7_n_0\,
      DI(0) => \xsqr[89]_i_8_n_0\,
      O(7 downto 6) => \NLW_xsqr_reg[89]_i_3_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => xsqr03_in(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \xsqr_reg[89]_i_4_n_12\,
      S(4) => \xsqr[89]_i_9_n_0\,
      S(3) => \xsqr[89]_i_10_n_0\,
      S(2) => \xsqr[89]_i_11_n_0\,
      S(1) => \xsqr[89]_i_12_n_0\,
      S(0) => \xsqr[89]_i_13_n_0\
    );
\xsqr_reg[89]_i_4\: unisim.vcomponents.CARRY8
     port map (
      CI => \xsqr_reg[89]_i_14_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xsqr_reg[89]_i_4_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xsqr_reg[89]_i_4_n_5\,
      CO(1) => \xsqr_reg[89]_i_4_n_6\,
      CO(0) => \xsqr_reg[89]_i_4_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \dx_reg_n_0_[44]\,
      DI(1) => '0',
      DI(0) => \dx_reg_n_0_[43]\,
      O(7 downto 4) => \NLW_xsqr_reg[89]_i_4_O_UNCONNECTED\(7 downto 4),
      O(3) => \xsqr_reg[89]_i_4_n_12\,
      O(2) => \xsqr_reg[89]_i_4_n_13\,
      O(1) => \xsqr_reg[89]_i_4_n_14\,
      O(0) => \xsqr_reg[89]_i_4_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xsqr[89]_i_15_n_0\,
      S(1) => \xsqr[89]_i_16_n_0\,
      S(0) => \xsqr[89]_i_17_n_0\
    );
\xsqr_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[8]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[8]\
    );
\xsqr_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xsqr[9]_i_1_n_0\,
      Q => \xsqr_reg_n_0_[9]\
    );
\xy4p1[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(72),
      O => \xy4p1[0]_i_1_n_0\
    );
\xy4p1[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(82),
      O => \xy4p1[10]_i_1_n_0\
    );
\xy4p1[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(83),
      O => \xy4p1[11]_i_1_n_0\
    );
\xy4p1[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(84),
      O => \xy4p1[12]_i_1_n_0\
    );
\xy4p1[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(85),
      O => \xy4p1[13]_i_1_n_0\
    );
\xy4p1[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(86),
      O => \xy4p1[14]_i_1_n_0\
    );
\xy4p1[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(87),
      O => \xy4p1[15]_i_1_n_0\
    );
\xy4p1[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xy(88),
      O => \xy4p1[16]_i_1_n_0\
    );
\xy4p1[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xy(89),
      O => \xy4p1[17]_i_1_n_0\
    );
\xy4p1[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(73),
      O => \xy4p1[1]_i_1_n_0\
    );
\xy4p1[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(74),
      O => \xy4p1[2]_i_1_n_0\
    );
\xy4p1[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(75),
      O => \xy4p1[3]_i_1_n_0\
    );
\xy4p1[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(76),
      O => \xy4p1[4]_i_1_n_0\
    );
\xy4p1[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(77),
      O => \xy4p1[5]_i_1_n_0\
    );
\xy4p1[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(78),
      O => \xy4p1[6]_i_1_n_0\
    );
\xy4p1[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(79),
      O => \xy4p1[7]_i_1_n_0\
    );
\xy4p1[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(80),
      O => \xy4p1[8]_i_1_n_0\
    );
\xy4p1[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy(81),
      O => \xy4p1[9]_i_1_n_0\
    );
\xy4p1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[0]_i_1_n_0\,
      Q => xy4p1(0)
    );
\xy4p1_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[10]_i_1_n_0\,
      Q => xy4p1(10)
    );
\xy4p1_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[11]_i_1_n_0\,
      Q => xy4p1(11)
    );
\xy4p1_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[12]_i_1_n_0\,
      Q => xy4p1(12)
    );
\xy4p1_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[13]_i_1_n_0\,
      Q => xy4p1(13)
    );
\xy4p1_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[14]_i_1_n_0\,
      Q => xy4p1(14)
    );
\xy4p1_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[15]_i_1_n_0\,
      Q => xy4p1(15)
    );
\xy4p1_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[16]_i_1_n_0\,
      Q => xy4p1(16)
    );
\xy4p1_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[17]_i_1_n_0\,
      Q => xy4p1(17)
    );
\xy4p1_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[1]_i_1_n_0\,
      Q => xy4p1(1)
    );
\xy4p1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[2]_i_1_n_0\,
      Q => xy4p1(2)
    );
\xy4p1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[3]_i_1_n_0\,
      Q => xy4p1(3)
    );
\xy4p1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[4]_i_1_n_0\,
      Q => xy4p1(4)
    );
\xy4p1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[5]_i_1_n_0\,
      Q => xy4p1(5)
    );
\xy4p1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[6]_i_1_n_0\,
      Q => xy4p1(6)
    );
\xy4p1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[7]_i_1_n_0\,
      Q => xy4p1(7)
    );
\xy4p1_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[8]_i_1_n_0\,
      Q => xy4p1(8)
    );
\xy4p1_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p1[9]_i_1_n_0\,
      Q => xy4p1(9)
    );
\xy4p2[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(0),
      O => \xy4p2[0]_i_1_n_0\
    );
\xy4p2[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(10),
      O => \xy4p2[10]_i_1_n_0\
    );
\xy4p2[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(11),
      O => \xy4p2[11]_i_1_n_0\
    );
\xy4p2[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(12),
      O => \xy4p2[12]_i_1_n_0\
    );
\xy4p2[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(13),
      O => \xy4p2[13]_i_1_n_0\
    );
\xy4p2[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(14),
      O => \xy4p2[14]_i_1_n_0\
    );
\xy4p2[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(15),
      O => \xy4p2[15]_i_1_n_0\
    );
\xy4p2[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xy4p1(16),
      O => \xy4p2[16]_i_1_n_0\
    );
\xy4p2[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xy4p1(17),
      O => \xy4p2[17]_i_1_n_0\
    );
\xy4p2[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(1),
      O => \xy4p2[1]_i_1_n_0\
    );
\xy4p2[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(2),
      O => \xy4p2[2]_i_1_n_0\
    );
\xy4p2[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(3),
      O => \xy4p2[3]_i_1_n_0\
    );
\xy4p2[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(4),
      O => \xy4p2[4]_i_1_n_0\
    );
\xy4p2[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(5),
      O => \xy4p2[5]_i_1_n_0\
    );
\xy4p2[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(6),
      O => \xy4p2[6]_i_1_n_0\
    );
\xy4p2[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(7),
      O => \xy4p2[7]_i_1_n_0\
    );
\xy4p2[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(8),
      O => \xy4p2[8]_i_1_n_0\
    );
\xy4p2[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy4p1(9),
      O => \xy4p2[9]_i_1_n_0\
    );
\xy4p2_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[0]_i_1_n_0\,
      Q => xy4p2(0)
    );
\xy4p2_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[10]_i_1_n_0\,
      Q => xy4p2(10)
    );
\xy4p2_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[11]_i_1_n_0\,
      Q => xy4p2(11)
    );
\xy4p2_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[12]_i_1_n_0\,
      Q => xy4p2(12)
    );
\xy4p2_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[13]_i_1_n_0\,
      Q => xy4p2(13)
    );
\xy4p2_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[14]_i_1_n_0\,
      Q => xy4p2(14)
    );
\xy4p2_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[15]_i_1_n_0\,
      Q => xy4p2(15)
    );
\xy4p2_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[16]_i_1_n_0\,
      Q => xy4p2(16)
    );
\xy4p2_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[17]_i_1_n_0\,
      Q => xy4p2(17)
    );
\xy4p2_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[1]_i_1_n_0\,
      Q => xy4p2(1)
    );
\xy4p2_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[2]_i_1_n_0\,
      Q => xy4p2(2)
    );
\xy4p2_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[3]_i_1_n_0\,
      Q => xy4p2(3)
    );
\xy4p2_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[4]_i_1_n_0\,
      Q => xy4p2(4)
    );
\xy4p2_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[5]_i_1_n_0\,
      Q => xy4p2(5)
    );
\xy4p2_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[6]_i_1_n_0\,
      Q => xy4p2(6)
    );
\xy4p2_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[7]_i_1_n_0\,
      Q => xy4p2(7)
    );
\xy4p2_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[8]_i_1_n_0\,
      Q => xy4p2(8)
    );
\xy4p2_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy4p2[9]_i_1_n_0\,
      Q => xy4p2(9)
    );
\xy[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(0),
      O => \xy[0]_i_1_n_0\
    );
\xy[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(10),
      O => \xy[10]_i_1_n_0\
    );
\xy[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(11),
      O => \xy[11]_i_1_n_0\
    );
\xy[11]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[3]_i_3_n_15\,
      I1 => \xy_reg[3]_i_2_n_12\,
      O => \xy[11]_i_10_n_0\
    );
\xy[11]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \xy_reg[3]_i_3_n_9\,
      I1 => \xy_reg[17]_i_13_n_12\,
      I2 => \xy_reg[17]_i_21_n_13\,
      I3 => \xy_reg[17]_i_13_n_11\,
      I4 => \xy_reg[3]_i_3_n_8\,
      I5 => \xy[11]_i_19_n_0\,
      O => \xy[11]_i_11_n_0\
    );
\xy[11]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \xy_reg[17]_i_21_n_14\,
      I1 => \xy_reg[3]_i_3_n_9\,
      I2 => \xy_reg[17]_i_13_n_12\,
      I3 => \xy_reg[3]_i_3_n_8\,
      I4 => \xy_reg[17]_i_13_n_11\,
      I5 => \xy_reg[17]_i_21_n_13\,
      O => \xy[11]_i_12_n_0\
    );
\xy[11]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \xy_reg[17]_i_21_n_14\,
      I1 => \xy_reg[17]_i_13_n_12\,
      I2 => \xy_reg[3]_i_3_n_9\,
      I3 => \xy_reg[3]_i_3_n_10\,
      I4 => \xy_reg[17]_i_21_n_15\,
      I5 => \xy_reg[17]_i_13_n_13\,
      O => \xy[11]_i_13_n_0\
    );
\xy[11]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy[11]_i_6_n_0\,
      I1 => \xy_reg[17]_i_13_n_13\,
      I2 => \xy_reg[17]_i_21_n_15\,
      I3 => \xy_reg[3]_i_3_n_10\,
      O => \xy[11]_i_14_n_0\
    );
\xy[11]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy_reg[17]_i_13_n_14\,
      I1 => \xy_reg[3]_i_2_n_8\,
      I2 => \xy_reg[3]_i_3_n_11\,
      I3 => \xy[11]_i_7_n_0\,
      O => \xy[11]_i_15_n_0\
    );
\xy[11]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy_reg[17]_i_13_n_15\,
      I1 => \xy_reg[3]_i_2_n_9\,
      I2 => \xy_reg[3]_i_3_n_12\,
      I3 => \xy[11]_i_8_n_0\,
      O => \xy[11]_i_16_n_0\
    );
\xy[11]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xy_reg[3]_i_3_n_13\,
      I1 => \xy_reg[3]_i_2_n_10\,
      I2 => \xy_reg[3]_i_2_n_11\,
      I3 => \xy_reg[3]_i_3_n_14\,
      O => \xy[11]_i_17_n_0\
    );
\xy[11]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \xy_reg[3]_i_2_n_12\,
      I1 => \xy_reg[3]_i_3_n_15\,
      I2 => \xy_reg[3]_i_2_n_11\,
      I3 => \xy_reg[3]_i_3_n_14\,
      O => \xy[11]_i_18_n_0\
    );
\xy[11]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xy_reg[17]_i_20_n_15\,
      I1 => \xy_reg[17]_i_13_n_10\,
      I2 => \xy_reg[17]_i_21_n_4\,
      O => \xy[11]_i_19_n_0\
    );
\xy[11]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \xy_reg[3]_i_3_n_9\,
      I1 => \xy_reg[17]_i_13_n_12\,
      I2 => \xy_reg[17]_i_21_n_13\,
      I3 => \xy_reg[17]_i_13_n_11\,
      I4 => \xy_reg[3]_i_3_n_8\,
      O => \xy[11]_i_3_n_0\
    );
\xy[11]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \xy_reg[17]_i_21_n_14\,
      I1 => \xy_reg[3]_i_3_n_9\,
      I2 => \xy_reg[17]_i_13_n_12\,
      O => \xy[11]_i_4_n_0\
    );
\xy[11]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xy_reg[3]_i_3_n_9\,
      I1 => \xy_reg[17]_i_13_n_12\,
      I2 => \xy_reg[17]_i_21_n_14\,
      O => \xy[11]_i_5_n_0\
    );
\xy[11]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xy_reg[17]_i_13_n_14\,
      I1 => \xy_reg[3]_i_2_n_8\,
      I2 => \xy_reg[3]_i_3_n_11\,
      O => \xy[11]_i_6_n_0\
    );
\xy[11]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xy_reg[17]_i_13_n_15\,
      I1 => \xy_reg[3]_i_2_n_9\,
      I2 => \xy_reg[3]_i_3_n_12\,
      O => \xy[11]_i_7_n_0\
    );
\xy[11]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[3]_i_3_n_13\,
      I1 => \xy_reg[3]_i_2_n_10\,
      O => \xy[11]_i_8_n_0\
    );
\xy[11]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[3]_i_3_n_14\,
      I1 => \xy_reg[3]_i_2_n_11\,
      O => \xy[11]_i_9_n_0\
    );
\xy[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(12),
      O => \xy[12]_i_1_n_0\
    );
\xy[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(13),
      O => \xy[13]_i_1_n_0\
    );
\xy[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(14),
      O => \xy[14]_i_1_n_0\
    );
\xy[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(15),
      O => \xy[15]_i_1_n_0\
    );
\xy[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xy0(16),
      O => \xy[16]_i_1_n_0\
    );
\xy[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xy0(17),
      O => \xy[17]_i_1_n_0\
    );
\xy[17]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \xy[17]_i_5_n_0\,
      I1 => \xy_reg[17]_i_3_n_15\,
      I2 => \xy_reg[17]_i_20_n_4\,
      I3 => \xy_reg[17]_i_13_n_8\,
      I4 => \xy_reg[17]_i_20_n_13\,
      O => \xy[17]_i_10_n_0\
    );
\xy[17]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \xy_reg[17]_i_20_n_14\,
      I1 => \xy_reg[17]_i_13_n_9\,
      I2 => \xy_reg[17]_i_20_n_13\,
      I3 => \xy_reg[17]_i_13_n_8\,
      I4 => \xy[17]_i_6_n_0\,
      O => \xy[17]_i_11_n_0\
    );
\xy[17]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \xy[17]_i_7_n_0\,
      I1 => \xy_reg[17]_i_20_n_15\,
      I2 => \xy_reg[17]_i_21_n_4\,
      I3 => \xy_reg[17]_i_13_n_10\,
      I4 => \xy_reg[17]_i_20_n_14\,
      I5 => \xy_reg[17]_i_13_n_9\,
      O => \xy[17]_i_12_n_0\
    );
\xy[17]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => \dy_reg_n_0_[8]\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[8]\,
      O => \xy[17]_i_14_n_0\
    );
\xy[17]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08888FFF8FFF8FFF"
    )
        port map (
      I0 => \dy_reg_n_0_[7]\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[8]\,
      I3 => \dx_reg_n_0_[6]\,
      I4 => \dx_reg_n_0_[8]\,
      I5 => \dy_reg_n_0_[6]\,
      O => \xy[17]_i_15_n_0\
    );
\xy[17]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[8]\,
      I1 => \dx_reg_n_0_[5]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[6]\,
      I4 => \dx_reg_n_0_[7]\,
      I5 => \dy_reg_n_0_[6]\,
      O => \xy[17]_i_16_n_0\
    );
\xy[17]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E53F"
    )
        port map (
      I0 => \dy_reg_n_0_[7]\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[8]\,
      I3 => \dx_reg_n_0_[8]\,
      O => \xy[17]_i_17_n_0\
    );
\xy[17]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"70ECE3130F5FAF5F"
    )
        port map (
      I0 => \dy_reg_n_0_[6]\,
      I1 => \dx_reg_n_0_[6]\,
      I2 => \dx_reg_n_0_[8]\,
      I3 => \dy_reg_n_0_[7]\,
      I4 => \dx_reg_n_0_[7]\,
      I5 => \dy_reg_n_0_[8]\,
      O => \xy[17]_i_18_n_0\
    );
\xy[17]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \xy[17]_i_16_n_0\,
      I1 => \dx_reg_n_0_[8]\,
      I2 => \dy_reg_n_0_[6]\,
      I3 => \dy_reg_n_0_[8]\,
      I4 => \dx_reg_n_0_[6]\,
      I5 => \xy[17]_i_37_n_0\,
      O => \xy[17]_i_19_n_0\
    );
\xy[17]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[8]\,
      I1 => \dx_reg_n_0_[4]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[5]\,
      I4 => \dx_reg_n_0_[6]\,
      I5 => \dy_reg_n_0_[6]\,
      O => \xy[17]_i_22_n_0\
    );
\xy[17]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[8]\,
      I1 => \dx_reg_n_0_[3]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[4]\,
      I4 => \dx_reg_n_0_[5]\,
      I5 => \dy_reg_n_0_[6]\,
      O => \xy[17]_i_23_n_0\
    );
\xy[17]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[8]\,
      I1 => \dx_reg_n_0_[2]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[3]\,
      I4 => \dx_reg_n_0_[4]\,
      I5 => \dy_reg_n_0_[6]\,
      O => \xy[17]_i_24_n_0\
    );
\xy[17]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[8]\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[2]\,
      I4 => \dx_reg_n_0_[3]\,
      I5 => \dy_reg_n_0_[6]\,
      O => \xy[17]_i_25_n_0\
    );
\xy[17]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dy_reg_n_0_[6]\,
      I1 => \dx_reg_n_0_[3]\,
      I2 => \dx_reg_n_0_[2]\,
      I3 => \dy_reg_n_0_[7]\,
      I4 => \dx_reg_n_0_[1]\,
      I5 => \dy_reg_n_0_[8]\,
      O => \xy[17]_i_26_n_0\
    );
\xy[17]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[8]\,
      I1 => \dx_reg_n_0_[0]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[1]\,
      O => \xy[17]_i_27_n_0\
    );
\xy[17]_i_28\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[1]\,
      I1 => \dy_reg_n_0_[6]\,
      O => \xy[17]_i_28_n_0\
    );
\xy[17]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[17]_i_22_n_0\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[6]\,
      I3 => \dy_reg_n_0_[8]\,
      I4 => \dx_reg_n_0_[5]\,
      I5 => \xy[17]_i_50_n_0\,
      O => \xy[17]_i_29_n_0\
    );
\xy[17]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[17]_i_23_n_0\,
      I1 => \dx_reg_n_0_[6]\,
      I2 => \dy_reg_n_0_[6]\,
      I3 => \dy_reg_n_0_[8]\,
      I4 => \dx_reg_n_0_[4]\,
      I5 => \xy[17]_i_51_n_0\,
      O => \xy[17]_i_30_n_0\
    );
\xy[17]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[17]_i_24_n_0\,
      I1 => \dx_reg_n_0_[5]\,
      I2 => \dy_reg_n_0_[6]\,
      I3 => \dy_reg_n_0_[8]\,
      I4 => \dx_reg_n_0_[3]\,
      I5 => \xy[17]_i_52_n_0\,
      O => \xy[17]_i_31_n_0\
    );
\xy[17]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[17]_i_25_n_0\,
      I1 => \dx_reg_n_0_[4]\,
      I2 => \dy_reg_n_0_[6]\,
      I3 => \dy_reg_n_0_[8]\,
      I4 => \dx_reg_n_0_[2]\,
      I5 => \xy[17]_i_53_n_0\,
      O => \xy[17]_i_32_n_0\
    );
\xy[17]_i_33\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A6A6A"
    )
        port map (
      I0 => \xy[17]_i_26_n_0\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[0]\,
      I4 => \dy_reg_n_0_[8]\,
      O => \xy[17]_i_33_n_0\
    );
\xy[17]_i_34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dx_reg_n_0_[1]\,
      I1 => \dy_reg_n_0_[7]\,
      I2 => \dx_reg_n_0_[0]\,
      I3 => \dy_reg_n_0_[8]\,
      I4 => \dy_reg_n_0_[6]\,
      I5 => \dx_reg_n_0_[2]\,
      O => \xy[17]_i_34_n_0\
    );
\xy[17]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[6]\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dx_reg_n_0_[0]\,
      O => \xy[17]_i_35_n_0\
    );
\xy[17]_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[0]\,
      I1 => \dy_reg_n_0_[6]\,
      O => \xy[17]_i_36_n_0\
    );
\xy[17]_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[7]\,
      I1 => \dy_reg_n_0_[7]\,
      O => \xy[17]_i_37_n_0\
    );
\xy[17]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[5]\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[4]\,
      I3 => \dx_reg_n_0_[8]\,
      O => \xy[17]_i_38_n_0\
    );
\xy[17]_i_39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000EAC0EAC0EAC0"
    )
        port map (
      I0 => \dx_reg_n_0_[7]\,
      I1 => \dx_reg_n_0_[6]\,
      I2 => \dy_reg_n_0_[5]\,
      I3 => \dy_reg_n_0_[4]\,
      I4 => \dx_reg_n_0_[8]\,
      I5 => \dy_reg_n_0_[3]\,
      O => \xy[17]_i_39_n_0\
    );
\xy[17]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xy_reg[17]_i_20_n_13\,
      I1 => \xy_reg[17]_i_13_n_8\,
      I2 => \xy_reg[17]_i_20_n_4\,
      I3 => \xy_reg[17]_i_3_n_15\,
      O => \xy[17]_i_4_n_0\
    );
\xy[17]_i_40\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[5]\,
      I1 => \dx_reg_n_0_[5]\,
      I2 => \dy_reg_n_0_[4]\,
      I3 => \dx_reg_n_0_[6]\,
      I4 => \dx_reg_n_0_[7]\,
      I5 => \dy_reg_n_0_[3]\,
      O => \xy[17]_i_40_n_0\
    );
\xy[17]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F3F"
    )
        port map (
      I0 => \dy_reg_n_0_[4]\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[5]\,
      I3 => \dx_reg_n_0_[8]\,
      O => \xy[17]_i_41_n_0\
    );
\xy[17]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"25404FBFF03FCF3F"
    )
        port map (
      I0 => \dy_reg_n_0_[3]\,
      I1 => \dx_reg_n_0_[6]\,
      I2 => \dy_reg_n_0_[5]\,
      I3 => \dx_reg_n_0_[7]\,
      I4 => \dy_reg_n_0_[4]\,
      I5 => \dx_reg_n_0_[8]\,
      O => \xy[17]_i_42_n_0\
    );
\xy[17]_i_43\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[17]_i_40_n_0\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[4]\,
      I3 => \dx_reg_n_0_[6]\,
      I4 => \dy_reg_n_0_[5]\,
      I5 => \xy[17]_i_54_n_0\,
      O => \xy[17]_i_43_n_0\
    );
\xy[17]_i_44\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[2]\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[1]\,
      I3 => \dx_reg_n_0_[8]\,
      O => \xy[17]_i_44_n_0\
    );
\xy[17]_i_45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000EAC0EAC0EAC0"
    )
        port map (
      I0 => \dx_reg_n_0_[7]\,
      I1 => \dx_reg_n_0_[6]\,
      I2 => \dy_reg_n_0_[2]\,
      I3 => \dy_reg_n_0_[1]\,
      I4 => \dx_reg_n_0_[8]\,
      I5 => \dy_reg_n_0_[0]\,
      O => \xy[17]_i_45_n_0\
    );
\xy[17]_i_46\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[2]\,
      I1 => \dx_reg_n_0_[5]\,
      I2 => \dy_reg_n_0_[1]\,
      I3 => \dx_reg_n_0_[6]\,
      I4 => \dx_reg_n_0_[7]\,
      I5 => \dy_reg_n_0_[0]\,
      O => \xy[17]_i_46_n_0\
    );
\xy[17]_i_47\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F3F"
    )
        port map (
      I0 => \dy_reg_n_0_[1]\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[2]\,
      I3 => \dx_reg_n_0_[8]\,
      O => \xy[17]_i_47_n_0\
    );
\xy[17]_i_48\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"25404FBFF03FCF3F"
    )
        port map (
      I0 => \dy_reg_n_0_[0]\,
      I1 => \dx_reg_n_0_[6]\,
      I2 => \dy_reg_n_0_[2]\,
      I3 => \dx_reg_n_0_[7]\,
      I4 => \dy_reg_n_0_[1]\,
      I5 => \dx_reg_n_0_[8]\,
      O => \xy[17]_i_48_n_0\
    );
\xy[17]_i_49\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[17]_i_46_n_0\,
      I1 => \dx_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[1]\,
      I3 => \dx_reg_n_0_[6]\,
      I4 => \dy_reg_n_0_[2]\,
      I5 => \xy[17]_i_55_n_0\,
      O => \xy[17]_i_49_n_0\
    );
\xy[17]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xy_reg[17]_i_20_n_14\,
      I1 => \xy_reg[17]_i_13_n_9\,
      I2 => \xy_reg[17]_i_20_n_13\,
      I3 => \xy_reg[17]_i_13_n_8\,
      O => \xy[17]_i_5_n_0\
    );
\xy[17]_i_50\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[6]\,
      I1 => \dy_reg_n_0_[7]\,
      O => \xy[17]_i_50_n_0\
    );
\xy[17]_i_51\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[5]\,
      I1 => \dy_reg_n_0_[7]\,
      O => \xy[17]_i_51_n_0\
    );
\xy[17]_i_52\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[4]\,
      I1 => \dy_reg_n_0_[7]\,
      O => \xy[17]_i_52_n_0\
    );
\xy[17]_i_53\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[3]\,
      I1 => \dy_reg_n_0_[7]\,
      O => \xy[17]_i_53_n_0\
    );
\xy[17]_i_54\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[8]\,
      I1 => \dy_reg_n_0_[3]\,
      O => \xy[17]_i_54_n_0\
    );
\xy[17]_i_55\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[8]\,
      I1 => \dy_reg_n_0_[0]\,
      O => \xy[17]_i_55_n_0\
    );
\xy[17]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \xy_reg[17]_i_20_n_14\,
      I1 => \xy_reg[17]_i_13_n_9\,
      I2 => \xy_reg[17]_i_20_n_15\,
      I3 => \xy_reg[17]_i_21_n_4\,
      I4 => \xy_reg[17]_i_13_n_10\,
      O => \xy[17]_i_6_n_0\
    );
\xy[17]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \xy_reg[3]_i_3_n_8\,
      I1 => \xy_reg[17]_i_21_n_13\,
      I2 => \xy_reg[17]_i_13_n_11\,
      I3 => \xy_reg[17]_i_21_n_4\,
      I4 => \xy_reg[17]_i_13_n_10\,
      I5 => \xy_reg[17]_i_20_n_15\,
      O => \xy[17]_i_7_n_0\
    );
\xy[17]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \xy_reg[17]_i_3_n_15\,
      I1 => \xy_reg[17]_i_20_n_4\,
      I2 => \xy_reg[17]_i_3_n_14\,
      I3 => \xy_reg[17]_i_3_n_13\,
      O => \xy[17]_i_8_n_0\
    );
\xy[17]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \xy_reg[17]_i_13_n_8\,
      I1 => \xy_reg[17]_i_20_n_13\,
      I2 => \xy_reg[17]_i_3_n_15\,
      I3 => \xy_reg[17]_i_20_n_4\,
      I4 => \xy_reg[17]_i_3_n_14\,
      O => \xy[17]_i_9_n_0\
    );
\xy[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(0),
      O => \xy[18]_i_1_n_0\
    );
\xy[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(1),
      O => \xy[19]_i_1_n_0\
    );
\xy[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(1),
      O => \xy[1]_i_1_n_0\
    );
\xy[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(2),
      O => \xy[20]_i_1_n_0\
    );
\xy[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \xy_reg[21]_i_2_n_12\,
      I1 => \xy_reg[21]_i_3_n_15\,
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \xy[21]_i_1_n_0\
    );
\xy[21]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(1),
      I1 => B(0),
      O => \xy[21]_i_10_n_0\
    );
\xy[21]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[21]_i_4_n_0\,
      I1 => B(2),
      I2 => A(5),
      I3 => \xy[21]_i_34_n_0\,
      I4 => A(7),
      I5 => B(0),
      O => \xy[21]_i_11_n_0\
    );
\xy[21]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[21]_i_5_n_0\,
      I1 => B(2),
      I2 => A(4),
      I3 => \xy[21]_i_35_n_0\,
      I4 => A(6),
      I5 => B(0),
      O => \xy[21]_i_12_n_0\
    );
\xy[21]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[21]_i_6_n_0\,
      I1 => B(2),
      I2 => A(3),
      I3 => \xy[21]_i_36_n_0\,
      I4 => A(5),
      I5 => B(0),
      O => \xy[21]_i_13_n_0\
    );
\xy[21]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[21]_i_7_n_0\,
      I1 => B(2),
      I2 => A(2),
      I3 => \xy[21]_i_37_n_0\,
      I4 => A(4),
      I5 => B(0),
      O => \xy[21]_i_14_n_0\
    );
\xy[21]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \xy[21]_i_8_n_0\,
      I1 => B(1),
      I2 => B(2),
      I3 => A(0),
      I4 => A(1),
      O => \xy[21]_i_15_n_0\
    );
\xy[21]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => A(0),
      I1 => B(2),
      I2 => A(1),
      I3 => B(1),
      I4 => B(0),
      I5 => A(2),
      O => \xy[21]_i_16_n_0\
    );
\xy[21]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => B(0),
      I1 => A(1),
      I2 => B(1),
      I3 => A(0),
      O => \xy[21]_i_17_n_0\
    );
\xy[21]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(0),
      I1 => B(0),
      O => \xy[21]_i_18_n_0\
    );
\xy[21]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => B(5),
      I1 => A(4),
      I2 => B(4),
      I3 => A(5),
      I4 => A(6),
      I5 => B(3),
      O => \xy[21]_i_19_n_0\
    );
\xy[21]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => B(5),
      I1 => A(3),
      I2 => B(4),
      I3 => A(4),
      I4 => A(5),
      I5 => B(3),
      O => \xy[21]_i_20_n_0\
    );
\xy[21]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => B(5),
      I1 => A(2),
      I2 => B(4),
      I3 => A(3),
      I4 => A(4),
      I5 => B(3),
      O => \xy[21]_i_21_n_0\
    );
\xy[21]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => B(5),
      I1 => A(1),
      I2 => B(4),
      I3 => A(2),
      I4 => A(3),
      I5 => B(3),
      O => \xy[21]_i_22_n_0\
    );
\xy[21]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => B(3),
      I1 => A(3),
      I2 => A(2),
      I3 => B(4),
      I4 => A(1),
      I5 => B(5),
      O => \xy[21]_i_23_n_0\
    );
\xy[21]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => B(4),
      I1 => A(1),
      I2 => B(5),
      I3 => A(0),
      O => \xy[21]_i_24_n_0\
    );
\xy[21]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(1),
      I1 => B(3),
      O => \xy[21]_i_25_n_0\
    );
\xy[21]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[21]_i_19_n_0\,
      I1 => B(5),
      I2 => A(5),
      I3 => \xy[21]_i_38_n_0\,
      I4 => A(7),
      I5 => B(3),
      O => \xy[21]_i_26_n_0\
    );
\xy[21]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[21]_i_20_n_0\,
      I1 => B(5),
      I2 => A(4),
      I3 => \xy[21]_i_39_n_0\,
      I4 => A(6),
      I5 => B(3),
      O => \xy[21]_i_27_n_0\
    );
\xy[21]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[21]_i_21_n_0\,
      I1 => B(5),
      I2 => A(3),
      I3 => \xy[21]_i_40_n_0\,
      I4 => A(5),
      I5 => B(3),
      O => \xy[21]_i_28_n_0\
    );
\xy[21]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[21]_i_22_n_0\,
      I1 => B(5),
      I2 => A(2),
      I3 => \xy[21]_i_41_n_0\,
      I4 => A(4),
      I5 => B(3),
      O => \xy[21]_i_29_n_0\
    );
\xy[21]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \xy[21]_i_23_n_0\,
      I1 => B(4),
      I2 => B(5),
      I3 => A(0),
      I4 => A(1),
      O => \xy[21]_i_30_n_0\
    );
\xy[21]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => A(0),
      I1 => B(5),
      I2 => A(1),
      I3 => B(4),
      I4 => B(3),
      I5 => A(2),
      O => \xy[21]_i_31_n_0\
    );
\xy[21]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => B(3),
      I1 => A(1),
      I2 => B(4),
      I3 => A(0),
      O => \xy[21]_i_32_n_0\
    );
\xy[21]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(0),
      I1 => B(3),
      O => \xy[21]_i_33_n_0\
    );
\xy[21]_i_34\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(6),
      I1 => B(1),
      O => \xy[21]_i_34_n_0\
    );
\xy[21]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(5),
      I1 => B(1),
      O => \xy[21]_i_35_n_0\
    );
\xy[21]_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(4),
      I1 => B(1),
      O => \xy[21]_i_36_n_0\
    );
\xy[21]_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(3),
      I1 => B(1),
      O => \xy[21]_i_37_n_0\
    );
\xy[21]_i_38\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(6),
      I1 => B(4),
      O => \xy[21]_i_38_n_0\
    );
\xy[21]_i_39\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(5),
      I1 => B(4),
      O => \xy[21]_i_39_n_0\
    );
\xy[21]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => B(2),
      I1 => A(4),
      I2 => B(1),
      I3 => A(5),
      I4 => A(6),
      I5 => B(0),
      O => \xy[21]_i_4_n_0\
    );
\xy[21]_i_40\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(4),
      I1 => B(4),
      O => \xy[21]_i_40_n_0\
    );
\xy[21]_i_41\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(3),
      I1 => B(4),
      O => \xy[21]_i_41_n_0\
    );
\xy[21]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => B(2),
      I1 => A(3),
      I2 => B(1),
      I3 => A(4),
      I4 => A(5),
      I5 => B(0),
      O => \xy[21]_i_5_n_0\
    );
\xy[21]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => B(2),
      I1 => A(2),
      I2 => B(1),
      I3 => A(3),
      I4 => A(4),
      I5 => B(0),
      O => \xy[21]_i_6_n_0\
    );
\xy[21]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => B(2),
      I1 => A(1),
      I2 => B(1),
      I3 => A(2),
      I4 => A(3),
      I5 => B(0),
      O => \xy[21]_i_7_n_0\
    );
\xy[21]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => B(0),
      I1 => A(3),
      I2 => A(2),
      I3 => B(1),
      I4 => A(1),
      I5 => B(2),
      O => \xy[21]_i_8_n_0\
    );
\xy[21]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => B(1),
      I1 => A(1),
      I2 => B(2),
      I3 => A(0),
      O => \xy[21]_i_9_n_0\
    );
\xy[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(4),
      O => \xy[22]_i_1_n_0\
    );
\xy[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(5),
      O => \xy[23]_i_1_n_0\
    );
\xy[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(6),
      O => \xy[24]_i_1_n_0\
    );
\xy[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(7),
      O => \xy[25]_i_1_n_0\
    );
\xy[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(8),
      O => \xy[26]_i_1_n_0\
    );
\xy[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(9),
      O => \xy[27]_i_1_n_0\
    );
\xy[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(10),
      O => \xy[28]_i_1_n_0\
    );
\xy[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(11),
      O => \xy[29]_i_1_n_0\
    );
\xy[29]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[21]_i_3_n_15\,
      I1 => \xy_reg[21]_i_2_n_12\,
      O => \xy[29]_i_10_n_0\
    );
\xy[29]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \xy_reg[21]_i_3_n_9\,
      I1 => \xy_reg[35]_i_13_n_12\,
      I2 => \xy_reg[35]_i_21_n_13\,
      I3 => \xy_reg[35]_i_13_n_11\,
      I4 => \xy_reg[21]_i_3_n_8\,
      I5 => \xy[29]_i_19_n_0\,
      O => \xy[29]_i_11_n_0\
    );
\xy[29]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \xy_reg[35]_i_21_n_14\,
      I1 => \xy_reg[21]_i_3_n_9\,
      I2 => \xy_reg[35]_i_13_n_12\,
      I3 => \xy_reg[21]_i_3_n_8\,
      I4 => \xy_reg[35]_i_13_n_11\,
      I5 => \xy_reg[35]_i_21_n_13\,
      O => \xy[29]_i_12_n_0\
    );
\xy[29]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \xy_reg[35]_i_21_n_14\,
      I1 => \xy_reg[35]_i_13_n_12\,
      I2 => \xy_reg[21]_i_3_n_9\,
      I3 => \xy_reg[21]_i_3_n_10\,
      I4 => \xy_reg[35]_i_21_n_15\,
      I5 => \xy_reg[35]_i_13_n_13\,
      O => \xy[29]_i_13_n_0\
    );
\xy[29]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy[29]_i_6_n_0\,
      I1 => \xy_reg[35]_i_13_n_13\,
      I2 => \xy_reg[35]_i_21_n_15\,
      I3 => \xy_reg[21]_i_3_n_10\,
      O => \xy[29]_i_14_n_0\
    );
\xy[29]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy_reg[35]_i_13_n_14\,
      I1 => \xy_reg[21]_i_2_n_8\,
      I2 => \xy_reg[21]_i_3_n_11\,
      I3 => \xy[29]_i_7_n_0\,
      O => \xy[29]_i_15_n_0\
    );
\xy[29]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy_reg[35]_i_13_n_15\,
      I1 => \xy_reg[21]_i_2_n_9\,
      I2 => \xy_reg[21]_i_3_n_12\,
      I3 => \xy[29]_i_8_n_0\,
      O => \xy[29]_i_16_n_0\
    );
\xy[29]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xy_reg[21]_i_3_n_13\,
      I1 => \xy_reg[21]_i_2_n_10\,
      I2 => \xy_reg[21]_i_2_n_11\,
      I3 => \xy_reg[21]_i_3_n_14\,
      O => \xy[29]_i_17_n_0\
    );
\xy[29]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \xy_reg[21]_i_2_n_12\,
      I1 => \xy_reg[21]_i_3_n_15\,
      I2 => \xy_reg[21]_i_2_n_11\,
      I3 => \xy_reg[21]_i_3_n_14\,
      O => \xy[29]_i_18_n_0\
    );
\xy[29]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xy_reg[35]_i_20_n_15\,
      I1 => \xy_reg[35]_i_13_n_10\,
      I2 => \xy_reg[35]_i_21_n_4\,
      O => \xy[29]_i_19_n_0\
    );
\xy[29]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \xy_reg[21]_i_3_n_9\,
      I1 => \xy_reg[35]_i_13_n_12\,
      I2 => \xy_reg[35]_i_21_n_13\,
      I3 => \xy_reg[35]_i_13_n_11\,
      I4 => \xy_reg[21]_i_3_n_8\,
      O => \xy[29]_i_3_n_0\
    );
\xy[29]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \xy_reg[35]_i_21_n_14\,
      I1 => \xy_reg[21]_i_3_n_9\,
      I2 => \xy_reg[35]_i_13_n_12\,
      O => \xy[29]_i_4_n_0\
    );
\xy[29]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xy_reg[21]_i_3_n_9\,
      I1 => \xy_reg[35]_i_13_n_12\,
      I2 => \xy_reg[35]_i_21_n_14\,
      O => \xy[29]_i_5_n_0\
    );
\xy[29]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xy_reg[35]_i_13_n_14\,
      I1 => \xy_reg[21]_i_2_n_8\,
      I2 => \xy_reg[21]_i_3_n_11\,
      O => \xy[29]_i_6_n_0\
    );
\xy[29]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xy_reg[35]_i_13_n_15\,
      I1 => \xy_reg[21]_i_2_n_9\,
      I2 => \xy_reg[21]_i_3_n_12\,
      O => \xy[29]_i_7_n_0\
    );
\xy[29]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[21]_i_3_n_13\,
      I1 => \xy_reg[21]_i_2_n_10\,
      O => \xy[29]_i_8_n_0\
    );
\xy[29]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[21]_i_3_n_14\,
      I1 => \xy_reg[21]_i_2_n_11\,
      O => \xy[29]_i_9_n_0\
    );
\xy[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(2),
      O => \xy[2]_i_1_n_0\
    );
\xy[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(12),
      O => \xy[30]_i_1_n_0\
    );
\xy[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(13),
      O => \xy[31]_i_1_n_0\
    );
\xy[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(14),
      O => \xy[32]_i_1_n_0\
    );
\xy[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy00_in(15),
      O => \xy[33]_i_1_n_0\
    );
\xy[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xy00_in(16),
      O => \xy[34]_i_1_n_0\
    );
\xy[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xy00_in(17),
      O => \xy[35]_i_1_n_0\
    );
\xy[35]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \xy[35]_i_5_n_0\,
      I1 => \xy_reg[35]_i_3_n_15\,
      I2 => \xy_reg[35]_i_20_n_4\,
      I3 => \xy_reg[35]_i_13_n_8\,
      I4 => \xy_reg[35]_i_20_n_13\,
      O => \xy[35]_i_10_n_0\
    );
\xy[35]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \xy_reg[35]_i_20_n_14\,
      I1 => \xy_reg[35]_i_13_n_9\,
      I2 => \xy_reg[35]_i_20_n_13\,
      I3 => \xy_reg[35]_i_13_n_8\,
      I4 => \xy[35]_i_6_n_0\,
      O => \xy[35]_i_11_n_0\
    );
\xy[35]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \xy[35]_i_7_n_0\,
      I1 => \xy_reg[35]_i_20_n_15\,
      I2 => \xy_reg[35]_i_21_n_4\,
      I3 => \xy_reg[35]_i_13_n_10\,
      I4 => \xy_reg[35]_i_20_n_14\,
      I5 => \xy_reg[35]_i_13_n_9\,
      O => \xy[35]_i_12_n_0\
    );
\xy[35]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => B(8),
      I1 => A(7),
      I2 => B(7),
      I3 => A(8),
      O => \xy[35]_i_14_n_0\
    );
\xy[35]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08888FFF8FFF8FFF"
    )
        port map (
      I0 => B(7),
      I1 => A(7),
      I2 => B(8),
      I3 => A(6),
      I4 => A(8),
      I5 => B(6),
      O => \xy[35]_i_15_n_0\
    );
\xy[35]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => B(8),
      I1 => A(5),
      I2 => B(7),
      I3 => A(6),
      I4 => A(7),
      I5 => B(6),
      O => \xy[35]_i_16_n_0\
    );
\xy[35]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E53F"
    )
        port map (
      I0 => B(7),
      I1 => A(7),
      I2 => B(8),
      I3 => A(8),
      O => \xy[35]_i_17_n_0\
    );
\xy[35]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"70ECE3130F5FAF5F"
    )
        port map (
      I0 => B(6),
      I1 => A(6),
      I2 => A(8),
      I3 => B(7),
      I4 => A(7),
      I5 => B(8),
      O => \xy[35]_i_18_n_0\
    );
\xy[35]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \xy[35]_i_16_n_0\,
      I1 => A(8),
      I2 => B(6),
      I3 => B(8),
      I4 => A(6),
      I5 => \xy[35]_i_37_n_0\,
      O => \xy[35]_i_19_n_0\
    );
\xy[35]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => B(8),
      I1 => A(4),
      I2 => B(7),
      I3 => A(5),
      I4 => A(6),
      I5 => B(6),
      O => \xy[35]_i_22_n_0\
    );
\xy[35]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => B(8),
      I1 => A(3),
      I2 => B(7),
      I3 => A(4),
      I4 => A(5),
      I5 => B(6),
      O => \xy[35]_i_23_n_0\
    );
\xy[35]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => B(8),
      I1 => A(2),
      I2 => B(7),
      I3 => A(3),
      I4 => A(4),
      I5 => B(6),
      O => \xy[35]_i_24_n_0\
    );
\xy[35]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => B(8),
      I1 => A(1),
      I2 => B(7),
      I3 => A(2),
      I4 => A(3),
      I5 => B(6),
      O => \xy[35]_i_25_n_0\
    );
\xy[35]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => B(6),
      I1 => A(3),
      I2 => A(2),
      I3 => B(7),
      I4 => A(1),
      I5 => B(8),
      O => \xy[35]_i_26_n_0\
    );
\xy[35]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => B(8),
      I1 => A(0),
      I2 => B(7),
      I3 => A(1),
      O => \xy[35]_i_27_n_0\
    );
\xy[35]_i_28\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(1),
      I1 => B(6),
      O => \xy[35]_i_28_n_0\
    );
\xy[35]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[35]_i_22_n_0\,
      I1 => A(7),
      I2 => B(6),
      I3 => B(8),
      I4 => A(5),
      I5 => \xy[35]_i_50_n_0\,
      O => \xy[35]_i_29_n_0\
    );
\xy[35]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[35]_i_23_n_0\,
      I1 => A(6),
      I2 => B(6),
      I3 => B(8),
      I4 => A(4),
      I5 => \xy[35]_i_51_n_0\,
      O => \xy[35]_i_30_n_0\
    );
\xy[35]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[35]_i_24_n_0\,
      I1 => A(5),
      I2 => B(6),
      I3 => B(8),
      I4 => A(3),
      I5 => \xy[35]_i_52_n_0\,
      O => \xy[35]_i_31_n_0\
    );
\xy[35]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[35]_i_25_n_0\,
      I1 => A(4),
      I2 => B(6),
      I3 => B(8),
      I4 => A(2),
      I5 => \xy[35]_i_53_n_0\,
      O => \xy[35]_i_32_n_0\
    );
\xy[35]_i_33\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A6A6A"
    )
        port map (
      I0 => \xy[35]_i_26_n_0\,
      I1 => A(1),
      I2 => B(7),
      I3 => A(0),
      I4 => B(8),
      O => \xy[35]_i_33_n_0\
    );
\xy[35]_i_34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => A(1),
      I1 => B(7),
      I2 => A(0),
      I3 => B(8),
      I4 => B(6),
      I5 => A(2),
      O => \xy[35]_i_34_n_0\
    );
\xy[35]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => B(6),
      I1 => A(1),
      I2 => B(7),
      I3 => A(0),
      O => \xy[35]_i_35_n_0\
    );
\xy[35]_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(0),
      I1 => B(6),
      O => \xy[35]_i_36_n_0\
    );
\xy[35]_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(7),
      I1 => B(7),
      O => \xy[35]_i_37_n_0\
    );
\xy[35]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => B(5),
      I1 => A(7),
      I2 => B(4),
      I3 => A(8),
      O => \xy[35]_i_38_n_0\
    );
\xy[35]_i_39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000EAC0EAC0EAC0"
    )
        port map (
      I0 => A(7),
      I1 => A(6),
      I2 => B(5),
      I3 => B(4),
      I4 => A(8),
      I5 => B(3),
      O => \xy[35]_i_39_n_0\
    );
\xy[35]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xy_reg[35]_i_20_n_13\,
      I1 => \xy_reg[35]_i_13_n_8\,
      I2 => \xy_reg[35]_i_20_n_4\,
      I3 => \xy_reg[35]_i_3_n_15\,
      O => \xy[35]_i_4_n_0\
    );
\xy[35]_i_40\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => B(5),
      I1 => A(5),
      I2 => B(4),
      I3 => A(6),
      I4 => A(7),
      I5 => B(3),
      O => \xy[35]_i_40_n_0\
    );
\xy[35]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F3F"
    )
        port map (
      I0 => B(4),
      I1 => A(7),
      I2 => B(5),
      I3 => A(8),
      O => \xy[35]_i_41_n_0\
    );
\xy[35]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"25404FBFF03FCF3F"
    )
        port map (
      I0 => B(3),
      I1 => A(6),
      I2 => B(5),
      I3 => A(7),
      I4 => B(4),
      I5 => A(8),
      O => \xy[35]_i_42_n_0\
    );
\xy[35]_i_43\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[35]_i_40_n_0\,
      I1 => A(7),
      I2 => B(4),
      I3 => A(6),
      I4 => B(5),
      I5 => \xy[35]_i_54_n_0\,
      O => \xy[35]_i_43_n_0\
    );
\xy[35]_i_44\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => B(2),
      I1 => A(7),
      I2 => B(1),
      I3 => A(8),
      O => \xy[35]_i_44_n_0\
    );
\xy[35]_i_45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000EAC0EAC0EAC0"
    )
        port map (
      I0 => A(7),
      I1 => A(6),
      I2 => B(2),
      I3 => B(1),
      I4 => A(8),
      I5 => B(0),
      O => \xy[35]_i_45_n_0\
    );
\xy[35]_i_46\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => B(2),
      I1 => A(5),
      I2 => B(1),
      I3 => A(6),
      I4 => A(7),
      I5 => B(0),
      O => \xy[35]_i_46_n_0\
    );
\xy[35]_i_47\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F3F"
    )
        port map (
      I0 => B(1),
      I1 => A(7),
      I2 => B(2),
      I3 => A(8),
      O => \xy[35]_i_47_n_0\
    );
\xy[35]_i_48\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"25404FBFF03FCF3F"
    )
        port map (
      I0 => B(0),
      I1 => A(6),
      I2 => B(2),
      I3 => A(7),
      I4 => B(1),
      I5 => A(8),
      O => \xy[35]_i_48_n_0\
    );
\xy[35]_i_49\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[35]_i_46_n_0\,
      I1 => A(7),
      I2 => B(1),
      I3 => A(6),
      I4 => B(2),
      I5 => \xy[35]_i_55_n_0\,
      O => \xy[35]_i_49_n_0\
    );
\xy[35]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xy_reg[35]_i_20_n_14\,
      I1 => \xy_reg[35]_i_13_n_9\,
      I2 => \xy_reg[35]_i_20_n_13\,
      I3 => \xy_reg[35]_i_13_n_8\,
      O => \xy[35]_i_5_n_0\
    );
\xy[35]_i_50\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(6),
      I1 => B(7),
      O => \xy[35]_i_50_n_0\
    );
\xy[35]_i_51\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(5),
      I1 => B(7),
      O => \xy[35]_i_51_n_0\
    );
\xy[35]_i_52\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(4),
      I1 => B(7),
      O => \xy[35]_i_52_n_0\
    );
\xy[35]_i_53\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(3),
      I1 => B(7),
      O => \xy[35]_i_53_n_0\
    );
\xy[35]_i_54\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(8),
      I1 => B(3),
      O => \xy[35]_i_54_n_0\
    );
\xy[35]_i_55\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => A(8),
      I1 => B(0),
      O => \xy[35]_i_55_n_0\
    );
\xy[35]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \xy_reg[35]_i_20_n_14\,
      I1 => \xy_reg[35]_i_13_n_9\,
      I2 => \xy_reg[35]_i_20_n_15\,
      I3 => \xy_reg[35]_i_21_n_4\,
      I4 => \xy_reg[35]_i_13_n_10\,
      O => \xy[35]_i_6_n_0\
    );
\xy[35]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \xy_reg[21]_i_3_n_8\,
      I1 => \xy_reg[35]_i_21_n_13\,
      I2 => \xy_reg[35]_i_13_n_11\,
      I3 => \xy_reg[35]_i_21_n_4\,
      I4 => \xy_reg[35]_i_13_n_10\,
      I5 => \xy_reg[35]_i_20_n_15\,
      O => \xy[35]_i_7_n_0\
    );
\xy[35]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \xy_reg[35]_i_3_n_15\,
      I1 => \xy_reg[35]_i_20_n_4\,
      I2 => \xy_reg[35]_i_3_n_14\,
      I3 => \xy_reg[35]_i_3_n_13\,
      O => \xy[35]_i_8_n_0\
    );
\xy[35]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \xy_reg[35]_i_13_n_8\,
      I1 => \xy_reg[35]_i_20_n_13\,
      I2 => \xy_reg[35]_i_3_n_15\,
      I3 => \xy_reg[35]_i_20_n_4\,
      I4 => \xy_reg[35]_i_3_n_14\,
      O => \xy[35]_i_9_n_0\
    );
\xy[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(0),
      O => \xy[36]_i_1_n_0\
    );
\xy[37]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(1),
      O => \xy[37]_i_1_n_0\
    );
\xy[38]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(2),
      O => \xy[38]_i_1_n_0\
    );
\xy[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \xy_reg[39]_i_2_n_12\,
      I1 => \xy_reg[39]_i_3_n_15\,
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \xy[39]_i_1_n_0\
    );
\xy[39]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[19]\,
      I1 => \dy_reg_n_0_[18]\,
      O => \xy[39]_i_10_n_0\
    );
\xy[39]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[39]_i_4_n_0\,
      I1 => \dy_reg_n_0_[20]\,
      I2 => \dx_reg_n_0_[23]\,
      I3 => \xy[39]_i_34_n_0\,
      I4 => \dx_reg_n_0_[25]\,
      I5 => \dy_reg_n_0_[18]\,
      O => \xy[39]_i_11_n_0\
    );
\xy[39]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[39]_i_5_n_0\,
      I1 => \dy_reg_n_0_[20]\,
      I2 => \dx_reg_n_0_[22]\,
      I3 => \xy[39]_i_35_n_0\,
      I4 => \dx_reg_n_0_[24]\,
      I5 => \dy_reg_n_0_[18]\,
      O => \xy[39]_i_12_n_0\
    );
\xy[39]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[39]_i_6_n_0\,
      I1 => \dy_reg_n_0_[20]\,
      I2 => \dx_reg_n_0_[21]\,
      I3 => \xy[39]_i_36_n_0\,
      I4 => \dx_reg_n_0_[23]\,
      I5 => \dy_reg_n_0_[18]\,
      O => \xy[39]_i_13_n_0\
    );
\xy[39]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[39]_i_7_n_0\,
      I1 => \dy_reg_n_0_[20]\,
      I2 => \dx_reg_n_0_[20]\,
      I3 => \xy[39]_i_37_n_0\,
      I4 => \dx_reg_n_0_[22]\,
      I5 => \dy_reg_n_0_[18]\,
      O => \xy[39]_i_14_n_0\
    );
\xy[39]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \xy[39]_i_8_n_0\,
      I1 => \dy_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[20]\,
      I3 => \dx_reg_n_0_[18]\,
      I4 => \dx_reg_n_0_[19]\,
      O => \xy[39]_i_15_n_0\
    );
\xy[39]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dx_reg_n_0_[18]\,
      I1 => \dy_reg_n_0_[20]\,
      I2 => \dx_reg_n_0_[19]\,
      I3 => \dy_reg_n_0_[19]\,
      I4 => \dy_reg_n_0_[18]\,
      I5 => \dx_reg_n_0_[20]\,
      O => \xy[39]_i_16_n_0\
    );
\xy[39]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[18]\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[19]\,
      I3 => \dx_reg_n_0_[18]\,
      O => \xy[39]_i_17_n_0\
    );
\xy[39]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[18]\,
      I1 => \dy_reg_n_0_[18]\,
      O => \xy[39]_i_18_n_0\
    );
\xy[39]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[23]\,
      I1 => \dx_reg_n_0_[22]\,
      I2 => \dy_reg_n_0_[22]\,
      I3 => \dx_reg_n_0_[23]\,
      I4 => \dx_reg_n_0_[24]\,
      I5 => \dy_reg_n_0_[21]\,
      O => \xy[39]_i_19_n_0\
    );
\xy[39]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[23]\,
      I1 => \dx_reg_n_0_[21]\,
      I2 => \dy_reg_n_0_[22]\,
      I3 => \dx_reg_n_0_[22]\,
      I4 => \dx_reg_n_0_[23]\,
      I5 => \dy_reg_n_0_[21]\,
      O => \xy[39]_i_20_n_0\
    );
\xy[39]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[23]\,
      I1 => \dx_reg_n_0_[20]\,
      I2 => \dy_reg_n_0_[22]\,
      I3 => \dx_reg_n_0_[21]\,
      I4 => \dx_reg_n_0_[22]\,
      I5 => \dy_reg_n_0_[21]\,
      O => \xy[39]_i_21_n_0\
    );
\xy[39]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[23]\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[22]\,
      I3 => \dx_reg_n_0_[20]\,
      I4 => \dx_reg_n_0_[21]\,
      I5 => \dy_reg_n_0_[21]\,
      O => \xy[39]_i_22_n_0\
    );
\xy[39]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dy_reg_n_0_[21]\,
      I1 => \dx_reg_n_0_[21]\,
      I2 => \dx_reg_n_0_[20]\,
      I3 => \dy_reg_n_0_[22]\,
      I4 => \dx_reg_n_0_[19]\,
      I5 => \dy_reg_n_0_[23]\,
      O => \xy[39]_i_23_n_0\
    );
\xy[39]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[22]\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[23]\,
      I3 => \dx_reg_n_0_[18]\,
      O => \xy[39]_i_24_n_0\
    );
\xy[39]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[19]\,
      I1 => \dy_reg_n_0_[21]\,
      O => \xy[39]_i_25_n_0\
    );
\xy[39]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[39]_i_19_n_0\,
      I1 => \dy_reg_n_0_[23]\,
      I2 => \dx_reg_n_0_[23]\,
      I3 => \xy[39]_i_38_n_0\,
      I4 => \dx_reg_n_0_[25]\,
      I5 => \dy_reg_n_0_[21]\,
      O => \xy[39]_i_26_n_0\
    );
\xy[39]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[39]_i_20_n_0\,
      I1 => \dy_reg_n_0_[23]\,
      I2 => \dx_reg_n_0_[22]\,
      I3 => \xy[39]_i_39_n_0\,
      I4 => \dx_reg_n_0_[24]\,
      I5 => \dy_reg_n_0_[21]\,
      O => \xy[39]_i_27_n_0\
    );
\xy[39]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[39]_i_21_n_0\,
      I1 => \dy_reg_n_0_[23]\,
      I2 => \dx_reg_n_0_[21]\,
      I3 => \xy[39]_i_40_n_0\,
      I4 => \dx_reg_n_0_[23]\,
      I5 => \dy_reg_n_0_[21]\,
      O => \xy[39]_i_28_n_0\
    );
\xy[39]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[39]_i_22_n_0\,
      I1 => \dy_reg_n_0_[23]\,
      I2 => \dx_reg_n_0_[20]\,
      I3 => \xy[39]_i_41_n_0\,
      I4 => \dx_reg_n_0_[22]\,
      I5 => \dy_reg_n_0_[21]\,
      O => \xy[39]_i_29_n_0\
    );
\xy[39]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \xy[39]_i_23_n_0\,
      I1 => \dy_reg_n_0_[22]\,
      I2 => \dy_reg_n_0_[23]\,
      I3 => \dx_reg_n_0_[18]\,
      I4 => \dx_reg_n_0_[19]\,
      O => \xy[39]_i_30_n_0\
    );
\xy[39]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dx_reg_n_0_[18]\,
      I1 => \dy_reg_n_0_[23]\,
      I2 => \dx_reg_n_0_[19]\,
      I3 => \dy_reg_n_0_[22]\,
      I4 => \dy_reg_n_0_[21]\,
      I5 => \dx_reg_n_0_[20]\,
      O => \xy[39]_i_31_n_0\
    );
\xy[39]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[21]\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[22]\,
      I3 => \dx_reg_n_0_[18]\,
      O => \xy[39]_i_32_n_0\
    );
\xy[39]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[18]\,
      I1 => \dy_reg_n_0_[21]\,
      O => \xy[39]_i_33_n_0\
    );
\xy[39]_i_34\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[24]\,
      I1 => \dy_reg_n_0_[19]\,
      O => \xy[39]_i_34_n_0\
    );
\xy[39]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[23]\,
      I1 => \dy_reg_n_0_[19]\,
      O => \xy[39]_i_35_n_0\
    );
\xy[39]_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[22]\,
      I1 => \dy_reg_n_0_[19]\,
      O => \xy[39]_i_36_n_0\
    );
\xy[39]_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[21]\,
      I1 => \dy_reg_n_0_[19]\,
      O => \xy[39]_i_37_n_0\
    );
\xy[39]_i_38\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[24]\,
      I1 => \dy_reg_n_0_[22]\,
      O => \xy[39]_i_38_n_0\
    );
\xy[39]_i_39\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[23]\,
      I1 => \dy_reg_n_0_[22]\,
      O => \xy[39]_i_39_n_0\
    );
\xy[39]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[20]\,
      I1 => \dx_reg_n_0_[22]\,
      I2 => \dy_reg_n_0_[19]\,
      I3 => \dx_reg_n_0_[23]\,
      I4 => \dx_reg_n_0_[24]\,
      I5 => \dy_reg_n_0_[18]\,
      O => \xy[39]_i_4_n_0\
    );
\xy[39]_i_40\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[22]\,
      I1 => \dy_reg_n_0_[22]\,
      O => \xy[39]_i_40_n_0\
    );
\xy[39]_i_41\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[21]\,
      I1 => \dy_reg_n_0_[22]\,
      O => \xy[39]_i_41_n_0\
    );
\xy[39]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[20]\,
      I1 => \dx_reg_n_0_[21]\,
      I2 => \dy_reg_n_0_[19]\,
      I3 => \dx_reg_n_0_[22]\,
      I4 => \dx_reg_n_0_[23]\,
      I5 => \dy_reg_n_0_[18]\,
      O => \xy[39]_i_5_n_0\
    );
\xy[39]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[20]\,
      I1 => \dx_reg_n_0_[20]\,
      I2 => \dy_reg_n_0_[19]\,
      I3 => \dx_reg_n_0_[21]\,
      I4 => \dx_reg_n_0_[22]\,
      I5 => \dy_reg_n_0_[18]\,
      O => \xy[39]_i_6_n_0\
    );
\xy[39]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[20]\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[19]\,
      I3 => \dx_reg_n_0_[20]\,
      I4 => \dx_reg_n_0_[21]\,
      I5 => \dy_reg_n_0_[18]\,
      O => \xy[39]_i_7_n_0\
    );
\xy[39]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dy_reg_n_0_[18]\,
      I1 => \dx_reg_n_0_[21]\,
      I2 => \dx_reg_n_0_[20]\,
      I3 => \dy_reg_n_0_[19]\,
      I4 => \dx_reg_n_0_[19]\,
      I5 => \dy_reg_n_0_[20]\,
      O => \xy[39]_i_8_n_0\
    );
\xy[39]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[19]\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[20]\,
      I3 => \dx_reg_n_0_[18]\,
      O => \xy[39]_i_9_n_0\
    );
\xy[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \xy_reg[3]_i_2_n_12\,
      I1 => \xy_reg[3]_i_3_n_15\,
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \xy[3]_i_1_n_0\
    );
\xy[3]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[1]\,
      I1 => \dy_reg_n_0_[0]\,
      O => \xy[3]_i_10_n_0\
    );
\xy[3]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[3]_i_4_n_0\,
      I1 => \dy_reg_n_0_[2]\,
      I2 => \dx_reg_n_0_[5]\,
      I3 => \xy[3]_i_34_n_0\,
      I4 => \dx_reg_n_0_[7]\,
      I5 => \dy_reg_n_0_[0]\,
      O => \xy[3]_i_11_n_0\
    );
\xy[3]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[3]_i_5_n_0\,
      I1 => \dy_reg_n_0_[2]\,
      I2 => \dx_reg_n_0_[4]\,
      I3 => \xy[3]_i_35_n_0\,
      I4 => \dx_reg_n_0_[6]\,
      I5 => \dy_reg_n_0_[0]\,
      O => \xy[3]_i_12_n_0\
    );
\xy[3]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[3]_i_6_n_0\,
      I1 => \dy_reg_n_0_[2]\,
      I2 => \dx_reg_n_0_[3]\,
      I3 => \xy[3]_i_36_n_0\,
      I4 => \dx_reg_n_0_[5]\,
      I5 => \dy_reg_n_0_[0]\,
      O => \xy[3]_i_13_n_0\
    );
\xy[3]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[3]_i_7_n_0\,
      I1 => \dy_reg_n_0_[2]\,
      I2 => \dx_reg_n_0_[2]\,
      I3 => \xy[3]_i_37_n_0\,
      I4 => \dx_reg_n_0_[4]\,
      I5 => \dy_reg_n_0_[0]\,
      O => \xy[3]_i_14_n_0\
    );
\xy[3]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \xy[3]_i_8_n_0\,
      I1 => \dy_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[2]\,
      I3 => \dx_reg_n_0_[0]\,
      I4 => \dx_reg_n_0_[1]\,
      O => \xy[3]_i_15_n_0\
    );
\xy[3]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dx_reg_n_0_[0]\,
      I1 => \dy_reg_n_0_[2]\,
      I2 => \dx_reg_n_0_[1]\,
      I3 => \dy_reg_n_0_[1]\,
      I4 => \dy_reg_n_0_[0]\,
      I5 => \dx_reg_n_0_[2]\,
      O => \xy[3]_i_16_n_0\
    );
\xy[3]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[0]\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[1]\,
      I3 => \dx_reg_n_0_[0]\,
      O => \xy[3]_i_17_n_0\
    );
\xy[3]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[0]\,
      I1 => \dy_reg_n_0_[0]\,
      O => \xy[3]_i_18_n_0\
    );
\xy[3]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[5]\,
      I1 => \dx_reg_n_0_[4]\,
      I2 => \dy_reg_n_0_[4]\,
      I3 => \dx_reg_n_0_[5]\,
      I4 => \dx_reg_n_0_[6]\,
      I5 => \dy_reg_n_0_[3]\,
      O => \xy[3]_i_19_n_0\
    );
\xy[3]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[5]\,
      I1 => \dx_reg_n_0_[3]\,
      I2 => \dy_reg_n_0_[4]\,
      I3 => \dx_reg_n_0_[4]\,
      I4 => \dx_reg_n_0_[5]\,
      I5 => \dy_reg_n_0_[3]\,
      O => \xy[3]_i_20_n_0\
    );
\xy[3]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[5]\,
      I1 => \dx_reg_n_0_[2]\,
      I2 => \dy_reg_n_0_[4]\,
      I3 => \dx_reg_n_0_[3]\,
      I4 => \dx_reg_n_0_[4]\,
      I5 => \dy_reg_n_0_[3]\,
      O => \xy[3]_i_21_n_0\
    );
\xy[3]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[5]\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[4]\,
      I3 => \dx_reg_n_0_[2]\,
      I4 => \dx_reg_n_0_[3]\,
      I5 => \dy_reg_n_0_[3]\,
      O => \xy[3]_i_22_n_0\
    );
\xy[3]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dy_reg_n_0_[3]\,
      I1 => \dx_reg_n_0_[3]\,
      I2 => \dx_reg_n_0_[2]\,
      I3 => \dy_reg_n_0_[4]\,
      I4 => \dx_reg_n_0_[1]\,
      I5 => \dy_reg_n_0_[5]\,
      O => \xy[3]_i_23_n_0\
    );
\xy[3]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[4]\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[5]\,
      I3 => \dx_reg_n_0_[0]\,
      O => \xy[3]_i_24_n_0\
    );
\xy[3]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[1]\,
      I1 => \dy_reg_n_0_[3]\,
      O => \xy[3]_i_25_n_0\
    );
\xy[3]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[3]_i_19_n_0\,
      I1 => \dy_reg_n_0_[5]\,
      I2 => \dx_reg_n_0_[5]\,
      I3 => \xy[3]_i_38_n_0\,
      I4 => \dx_reg_n_0_[7]\,
      I5 => \dy_reg_n_0_[3]\,
      O => \xy[3]_i_26_n_0\
    );
\xy[3]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[3]_i_20_n_0\,
      I1 => \dy_reg_n_0_[5]\,
      I2 => \dx_reg_n_0_[4]\,
      I3 => \xy[3]_i_39_n_0\,
      I4 => \dx_reg_n_0_[6]\,
      I5 => \dy_reg_n_0_[3]\,
      O => \xy[3]_i_27_n_0\
    );
\xy[3]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[3]_i_21_n_0\,
      I1 => \dy_reg_n_0_[5]\,
      I2 => \dx_reg_n_0_[3]\,
      I3 => \xy[3]_i_40_n_0\,
      I4 => \dx_reg_n_0_[5]\,
      I5 => \dy_reg_n_0_[3]\,
      O => \xy[3]_i_28_n_0\
    );
\xy[3]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[3]_i_22_n_0\,
      I1 => \dy_reg_n_0_[5]\,
      I2 => \dx_reg_n_0_[2]\,
      I3 => \xy[3]_i_41_n_0\,
      I4 => \dx_reg_n_0_[4]\,
      I5 => \dy_reg_n_0_[3]\,
      O => \xy[3]_i_29_n_0\
    );
\xy[3]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \xy[3]_i_23_n_0\,
      I1 => \dy_reg_n_0_[4]\,
      I2 => \dy_reg_n_0_[5]\,
      I3 => \dx_reg_n_0_[0]\,
      I4 => \dx_reg_n_0_[1]\,
      O => \xy[3]_i_30_n_0\
    );
\xy[3]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dx_reg_n_0_[0]\,
      I1 => \dy_reg_n_0_[5]\,
      I2 => \dx_reg_n_0_[1]\,
      I3 => \dy_reg_n_0_[4]\,
      I4 => \dy_reg_n_0_[3]\,
      I5 => \dx_reg_n_0_[2]\,
      O => \xy[3]_i_31_n_0\
    );
\xy[3]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[3]\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[4]\,
      I3 => \dx_reg_n_0_[0]\,
      O => \xy[3]_i_32_n_0\
    );
\xy[3]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[0]\,
      I1 => \dy_reg_n_0_[3]\,
      O => \xy[3]_i_33_n_0\
    );
\xy[3]_i_34\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[6]\,
      I1 => \dy_reg_n_0_[1]\,
      O => \xy[3]_i_34_n_0\
    );
\xy[3]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[5]\,
      I1 => \dy_reg_n_0_[1]\,
      O => \xy[3]_i_35_n_0\
    );
\xy[3]_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[4]\,
      I1 => \dy_reg_n_0_[1]\,
      O => \xy[3]_i_36_n_0\
    );
\xy[3]_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[3]\,
      I1 => \dy_reg_n_0_[1]\,
      O => \xy[3]_i_37_n_0\
    );
\xy[3]_i_38\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[6]\,
      I1 => \dy_reg_n_0_[4]\,
      O => \xy[3]_i_38_n_0\
    );
\xy[3]_i_39\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[5]\,
      I1 => \dy_reg_n_0_[4]\,
      O => \xy[3]_i_39_n_0\
    );
\xy[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[2]\,
      I1 => \dx_reg_n_0_[4]\,
      I2 => \dy_reg_n_0_[1]\,
      I3 => \dx_reg_n_0_[5]\,
      I4 => \dx_reg_n_0_[6]\,
      I5 => \dy_reg_n_0_[0]\,
      O => \xy[3]_i_4_n_0\
    );
\xy[3]_i_40\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[4]\,
      I1 => \dy_reg_n_0_[4]\,
      O => \xy[3]_i_40_n_0\
    );
\xy[3]_i_41\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[3]\,
      I1 => \dy_reg_n_0_[4]\,
      O => \xy[3]_i_41_n_0\
    );
\xy[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[2]\,
      I1 => \dx_reg_n_0_[3]\,
      I2 => \dy_reg_n_0_[1]\,
      I3 => \dx_reg_n_0_[4]\,
      I4 => \dx_reg_n_0_[5]\,
      I5 => \dy_reg_n_0_[0]\,
      O => \xy[3]_i_5_n_0\
    );
\xy[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[2]\,
      I1 => \dx_reg_n_0_[2]\,
      I2 => \dy_reg_n_0_[1]\,
      I3 => \dx_reg_n_0_[3]\,
      I4 => \dx_reg_n_0_[4]\,
      I5 => \dy_reg_n_0_[0]\,
      O => \xy[3]_i_6_n_0\
    );
\xy[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[2]\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[1]\,
      I3 => \dx_reg_n_0_[2]\,
      I4 => \dx_reg_n_0_[3]\,
      I5 => \dy_reg_n_0_[0]\,
      O => \xy[3]_i_7_n_0\
    );
\xy[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dy_reg_n_0_[0]\,
      I1 => \dx_reg_n_0_[3]\,
      I2 => \dx_reg_n_0_[2]\,
      I3 => \dy_reg_n_0_[1]\,
      I4 => \dx_reg_n_0_[1]\,
      I5 => \dy_reg_n_0_[2]\,
      O => \xy[3]_i_8_n_0\
    );
\xy[3]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[1]\,
      I1 => \dx_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[2]\,
      I3 => \dx_reg_n_0_[0]\,
      O => \xy[3]_i_9_n_0\
    );
\xy[40]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(4),
      O => \xy[40]_i_1_n_0\
    );
\xy[41]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(5),
      O => \xy[41]_i_1_n_0\
    );
\xy[42]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(6),
      O => \xy[42]_i_1_n_0\
    );
\xy[43]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(7),
      O => \xy[43]_i_1_n_0\
    );
\xy[44]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(8),
      O => \xy[44]_i_1_n_0\
    );
\xy[45]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(9),
      O => \xy[45]_i_1_n_0\
    );
\xy[46]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(10),
      O => \xy[46]_i_1_n_0\
    );
\xy[47]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(11),
      O => \xy[47]_i_1_n_0\
    );
\xy[47]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[39]_i_3_n_15\,
      I1 => \xy_reg[39]_i_2_n_12\,
      O => \xy[47]_i_10_n_0\
    );
\xy[47]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \xy_reg[39]_i_3_n_9\,
      I1 => \xy_reg[53]_i_13_n_12\,
      I2 => \xy_reg[53]_i_21_n_13\,
      I3 => \xy_reg[53]_i_13_n_11\,
      I4 => \xy_reg[39]_i_3_n_8\,
      I5 => \xy[47]_i_19_n_0\,
      O => \xy[47]_i_11_n_0\
    );
\xy[47]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \xy_reg[53]_i_21_n_14\,
      I1 => \xy_reg[39]_i_3_n_9\,
      I2 => \xy_reg[53]_i_13_n_12\,
      I3 => \xy_reg[39]_i_3_n_8\,
      I4 => \xy_reg[53]_i_13_n_11\,
      I5 => \xy_reg[53]_i_21_n_13\,
      O => \xy[47]_i_12_n_0\
    );
\xy[47]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \xy_reg[53]_i_21_n_14\,
      I1 => \xy_reg[53]_i_13_n_12\,
      I2 => \xy_reg[39]_i_3_n_9\,
      I3 => \xy_reg[39]_i_3_n_10\,
      I4 => \xy_reg[53]_i_21_n_15\,
      I5 => \xy_reg[53]_i_13_n_13\,
      O => \xy[47]_i_13_n_0\
    );
\xy[47]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy[47]_i_6_n_0\,
      I1 => \xy_reg[53]_i_13_n_13\,
      I2 => \xy_reg[53]_i_21_n_15\,
      I3 => \xy_reg[39]_i_3_n_10\,
      O => \xy[47]_i_14_n_0\
    );
\xy[47]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy_reg[53]_i_13_n_14\,
      I1 => \xy_reg[39]_i_2_n_8\,
      I2 => \xy_reg[39]_i_3_n_11\,
      I3 => \xy[47]_i_7_n_0\,
      O => \xy[47]_i_15_n_0\
    );
\xy[47]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy_reg[53]_i_13_n_15\,
      I1 => \xy_reg[39]_i_2_n_9\,
      I2 => \xy_reg[39]_i_3_n_12\,
      I3 => \xy[47]_i_8_n_0\,
      O => \xy[47]_i_16_n_0\
    );
\xy[47]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xy_reg[39]_i_3_n_13\,
      I1 => \xy_reg[39]_i_2_n_10\,
      I2 => \xy_reg[39]_i_2_n_11\,
      I3 => \xy_reg[39]_i_3_n_14\,
      O => \xy[47]_i_17_n_0\
    );
\xy[47]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \xy_reg[39]_i_2_n_12\,
      I1 => \xy_reg[39]_i_3_n_15\,
      I2 => \xy_reg[39]_i_2_n_11\,
      I3 => \xy_reg[39]_i_3_n_14\,
      O => \xy[47]_i_18_n_0\
    );
\xy[47]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xy_reg[53]_i_20_n_15\,
      I1 => \xy_reg[53]_i_13_n_10\,
      I2 => \xy_reg[53]_i_21_n_4\,
      O => \xy[47]_i_19_n_0\
    );
\xy[47]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \xy_reg[39]_i_3_n_9\,
      I1 => \xy_reg[53]_i_13_n_12\,
      I2 => \xy_reg[53]_i_21_n_13\,
      I3 => \xy_reg[53]_i_13_n_11\,
      I4 => \xy_reg[39]_i_3_n_8\,
      O => \xy[47]_i_3_n_0\
    );
\xy[47]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \xy_reg[53]_i_21_n_14\,
      I1 => \xy_reg[39]_i_3_n_9\,
      I2 => \xy_reg[53]_i_13_n_12\,
      O => \xy[47]_i_4_n_0\
    );
\xy[47]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xy_reg[39]_i_3_n_9\,
      I1 => \xy_reg[53]_i_13_n_12\,
      I2 => \xy_reg[53]_i_21_n_14\,
      O => \xy[47]_i_5_n_0\
    );
\xy[47]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xy_reg[53]_i_13_n_14\,
      I1 => \xy_reg[39]_i_2_n_8\,
      I2 => \xy_reg[39]_i_3_n_11\,
      O => \xy[47]_i_6_n_0\
    );
\xy[47]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xy_reg[53]_i_13_n_15\,
      I1 => \xy_reg[39]_i_2_n_9\,
      I2 => \xy_reg[39]_i_3_n_12\,
      O => \xy[47]_i_7_n_0\
    );
\xy[47]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[39]_i_3_n_13\,
      I1 => \xy_reg[39]_i_2_n_10\,
      O => \xy[47]_i_8_n_0\
    );
\xy[47]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[39]_i_3_n_14\,
      I1 => \xy_reg[39]_i_2_n_11\,
      O => \xy[47]_i_9_n_0\
    );
\xy[48]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(12),
      O => \xy[48]_i_1_n_0\
    );
\xy[49]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(13),
      O => \xy[49]_i_1_n_0\
    );
\xy[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(4),
      O => \xy[4]_i_1_n_0\
    );
\xy[50]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(14),
      O => \xy[50]_i_1_n_0\
    );
\xy[51]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy01_in(15),
      O => \xy[51]_i_1_n_0\
    );
\xy[52]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xy01_in(16),
      O => \xy[52]_i_1_n_0\
    );
\xy[53]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xy01_in(17),
      O => \xy[53]_i_1_n_0\
    );
\xy[53]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \xy[53]_i_5_n_0\,
      I1 => \xy_reg[53]_i_3_n_15\,
      I2 => \xy_reg[53]_i_20_n_4\,
      I3 => \xy_reg[53]_i_13_n_8\,
      I4 => \xy_reg[53]_i_20_n_13\,
      O => \xy[53]_i_10_n_0\
    );
\xy[53]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \xy_reg[53]_i_20_n_14\,
      I1 => \xy_reg[53]_i_13_n_9\,
      I2 => \xy_reg[53]_i_20_n_13\,
      I3 => \xy_reg[53]_i_13_n_8\,
      I4 => \xy[53]_i_6_n_0\,
      O => \xy[53]_i_11_n_0\
    );
\xy[53]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \xy[53]_i_7_n_0\,
      I1 => \xy_reg[53]_i_20_n_15\,
      I2 => \xy_reg[53]_i_21_n_4\,
      I3 => \xy_reg[53]_i_13_n_10\,
      I4 => \xy_reg[53]_i_20_n_14\,
      I5 => \xy_reg[53]_i_13_n_9\,
      O => \xy[53]_i_12_n_0\
    );
\xy[53]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => \dy_reg_n_0_[26]\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[26]\,
      O => \xy[53]_i_14_n_0\
    );
\xy[53]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08888FFF8FFF8FFF"
    )
        port map (
      I0 => \dy_reg_n_0_[25]\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[26]\,
      I3 => \dx_reg_n_0_[24]\,
      I4 => \dx_reg_n_0_[26]\,
      I5 => \dy_reg_n_0_[24]\,
      O => \xy[53]_i_15_n_0\
    );
\xy[53]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[26]\,
      I1 => \dx_reg_n_0_[23]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[24]\,
      I4 => \dx_reg_n_0_[25]\,
      I5 => \dy_reg_n_0_[24]\,
      O => \xy[53]_i_16_n_0\
    );
\xy[53]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E53F"
    )
        port map (
      I0 => \dy_reg_n_0_[25]\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[26]\,
      I3 => \dx_reg_n_0_[26]\,
      O => \xy[53]_i_17_n_0\
    );
\xy[53]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"70ECE3130F5FAF5F"
    )
        port map (
      I0 => \dy_reg_n_0_[24]\,
      I1 => \dx_reg_n_0_[24]\,
      I2 => \dx_reg_n_0_[26]\,
      I3 => \dy_reg_n_0_[25]\,
      I4 => \dx_reg_n_0_[25]\,
      I5 => \dy_reg_n_0_[26]\,
      O => \xy[53]_i_18_n_0\
    );
\xy[53]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \xy[53]_i_16_n_0\,
      I1 => \dx_reg_n_0_[26]\,
      I2 => \dy_reg_n_0_[24]\,
      I3 => \dy_reg_n_0_[26]\,
      I4 => \dx_reg_n_0_[24]\,
      I5 => \xy[53]_i_37_n_0\,
      O => \xy[53]_i_19_n_0\
    );
\xy[53]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[26]\,
      I1 => \dx_reg_n_0_[22]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[23]\,
      I4 => \dx_reg_n_0_[24]\,
      I5 => \dy_reg_n_0_[24]\,
      O => \xy[53]_i_22_n_0\
    );
\xy[53]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[26]\,
      I1 => \dx_reg_n_0_[21]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[22]\,
      I4 => \dx_reg_n_0_[23]\,
      I5 => \dy_reg_n_0_[24]\,
      O => \xy[53]_i_23_n_0\
    );
\xy[53]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[26]\,
      I1 => \dx_reg_n_0_[20]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[21]\,
      I4 => \dx_reg_n_0_[22]\,
      I5 => \dy_reg_n_0_[24]\,
      O => \xy[53]_i_24_n_0\
    );
\xy[53]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[26]\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[20]\,
      I4 => \dx_reg_n_0_[21]\,
      I5 => \dy_reg_n_0_[24]\,
      O => \xy[53]_i_25_n_0\
    );
\xy[53]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dy_reg_n_0_[24]\,
      I1 => \dx_reg_n_0_[21]\,
      I2 => \dx_reg_n_0_[20]\,
      I3 => \dy_reg_n_0_[25]\,
      I4 => \dx_reg_n_0_[19]\,
      I5 => \dy_reg_n_0_[26]\,
      O => \xy[53]_i_26_n_0\
    );
\xy[53]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[26]\,
      I1 => \dx_reg_n_0_[18]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[19]\,
      O => \xy[53]_i_27_n_0\
    );
\xy[53]_i_28\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[19]\,
      I1 => \dy_reg_n_0_[24]\,
      O => \xy[53]_i_28_n_0\
    );
\xy[53]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[53]_i_22_n_0\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[24]\,
      I3 => \dy_reg_n_0_[26]\,
      I4 => \dx_reg_n_0_[23]\,
      I5 => \xy[53]_i_50_n_0\,
      O => \xy[53]_i_29_n_0\
    );
\xy[53]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[53]_i_23_n_0\,
      I1 => \dx_reg_n_0_[24]\,
      I2 => \dy_reg_n_0_[24]\,
      I3 => \dy_reg_n_0_[26]\,
      I4 => \dx_reg_n_0_[22]\,
      I5 => \xy[53]_i_51_n_0\,
      O => \xy[53]_i_30_n_0\
    );
\xy[53]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[53]_i_24_n_0\,
      I1 => \dx_reg_n_0_[23]\,
      I2 => \dy_reg_n_0_[24]\,
      I3 => \dy_reg_n_0_[26]\,
      I4 => \dx_reg_n_0_[21]\,
      I5 => \xy[53]_i_52_n_0\,
      O => \xy[53]_i_31_n_0\
    );
\xy[53]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[53]_i_25_n_0\,
      I1 => \dx_reg_n_0_[22]\,
      I2 => \dy_reg_n_0_[24]\,
      I3 => \dy_reg_n_0_[26]\,
      I4 => \dx_reg_n_0_[20]\,
      I5 => \xy[53]_i_53_n_0\,
      O => \xy[53]_i_32_n_0\
    );
\xy[53]_i_33\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A6A6A"
    )
        port map (
      I0 => \xy[53]_i_26_n_0\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[18]\,
      I4 => \dy_reg_n_0_[26]\,
      O => \xy[53]_i_33_n_0\
    );
\xy[53]_i_34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dx_reg_n_0_[19]\,
      I1 => \dy_reg_n_0_[25]\,
      I2 => \dx_reg_n_0_[18]\,
      I3 => \dy_reg_n_0_[26]\,
      I4 => \dy_reg_n_0_[24]\,
      I5 => \dx_reg_n_0_[20]\,
      O => \xy[53]_i_34_n_0\
    );
\xy[53]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[24]\,
      I1 => \dx_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dx_reg_n_0_[18]\,
      O => \xy[53]_i_35_n_0\
    );
\xy[53]_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[18]\,
      I1 => \dy_reg_n_0_[24]\,
      O => \xy[53]_i_36_n_0\
    );
\xy[53]_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[25]\,
      I1 => \dy_reg_n_0_[25]\,
      O => \xy[53]_i_37_n_0\
    );
\xy[53]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[23]\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[22]\,
      I3 => \dx_reg_n_0_[26]\,
      O => \xy[53]_i_38_n_0\
    );
\xy[53]_i_39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000EAC0EAC0EAC0"
    )
        port map (
      I0 => \dx_reg_n_0_[25]\,
      I1 => \dx_reg_n_0_[24]\,
      I2 => \dy_reg_n_0_[23]\,
      I3 => \dy_reg_n_0_[22]\,
      I4 => \dx_reg_n_0_[26]\,
      I5 => \dy_reg_n_0_[21]\,
      O => \xy[53]_i_39_n_0\
    );
\xy[53]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xy_reg[53]_i_20_n_13\,
      I1 => \xy_reg[53]_i_13_n_8\,
      I2 => \xy_reg[53]_i_20_n_4\,
      I3 => \xy_reg[53]_i_3_n_15\,
      O => \xy[53]_i_4_n_0\
    );
\xy[53]_i_40\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[23]\,
      I1 => \dx_reg_n_0_[23]\,
      I2 => \dy_reg_n_0_[22]\,
      I3 => \dx_reg_n_0_[24]\,
      I4 => \dx_reg_n_0_[25]\,
      I5 => \dy_reg_n_0_[21]\,
      O => \xy[53]_i_40_n_0\
    );
\xy[53]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F3F"
    )
        port map (
      I0 => \dy_reg_n_0_[22]\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[23]\,
      I3 => \dx_reg_n_0_[26]\,
      O => \xy[53]_i_41_n_0\
    );
\xy[53]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"25404FBFF03FCF3F"
    )
        port map (
      I0 => \dy_reg_n_0_[21]\,
      I1 => \dx_reg_n_0_[24]\,
      I2 => \dy_reg_n_0_[23]\,
      I3 => \dx_reg_n_0_[25]\,
      I4 => \dy_reg_n_0_[22]\,
      I5 => \dx_reg_n_0_[26]\,
      O => \xy[53]_i_42_n_0\
    );
\xy[53]_i_43\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[53]_i_40_n_0\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[22]\,
      I3 => \dx_reg_n_0_[24]\,
      I4 => \dy_reg_n_0_[23]\,
      I5 => \xy[53]_i_54_n_0\,
      O => \xy[53]_i_43_n_0\
    );
\xy[53]_i_44\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[20]\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[19]\,
      I3 => \dx_reg_n_0_[26]\,
      O => \xy[53]_i_44_n_0\
    );
\xy[53]_i_45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000EAC0EAC0EAC0"
    )
        port map (
      I0 => \dx_reg_n_0_[25]\,
      I1 => \dx_reg_n_0_[24]\,
      I2 => \dy_reg_n_0_[20]\,
      I3 => \dy_reg_n_0_[19]\,
      I4 => \dx_reg_n_0_[26]\,
      I5 => \dy_reg_n_0_[18]\,
      O => \xy[53]_i_45_n_0\
    );
\xy[53]_i_46\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[20]\,
      I1 => \dx_reg_n_0_[23]\,
      I2 => \dy_reg_n_0_[19]\,
      I3 => \dx_reg_n_0_[24]\,
      I4 => \dx_reg_n_0_[25]\,
      I5 => \dy_reg_n_0_[18]\,
      O => \xy[53]_i_46_n_0\
    );
\xy[53]_i_47\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F3F"
    )
        port map (
      I0 => \dy_reg_n_0_[19]\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[20]\,
      I3 => \dx_reg_n_0_[26]\,
      O => \xy[53]_i_47_n_0\
    );
\xy[53]_i_48\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"25404FBFF03FCF3F"
    )
        port map (
      I0 => \dy_reg_n_0_[18]\,
      I1 => \dx_reg_n_0_[24]\,
      I2 => \dy_reg_n_0_[20]\,
      I3 => \dx_reg_n_0_[25]\,
      I4 => \dy_reg_n_0_[19]\,
      I5 => \dx_reg_n_0_[26]\,
      O => \xy[53]_i_48_n_0\
    );
\xy[53]_i_49\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[53]_i_46_n_0\,
      I1 => \dx_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[19]\,
      I3 => \dx_reg_n_0_[24]\,
      I4 => \dy_reg_n_0_[20]\,
      I5 => \xy[53]_i_55_n_0\,
      O => \xy[53]_i_49_n_0\
    );
\xy[53]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xy_reg[53]_i_20_n_14\,
      I1 => \xy_reg[53]_i_13_n_9\,
      I2 => \xy_reg[53]_i_20_n_13\,
      I3 => \xy_reg[53]_i_13_n_8\,
      O => \xy[53]_i_5_n_0\
    );
\xy[53]_i_50\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[24]\,
      I1 => \dy_reg_n_0_[25]\,
      O => \xy[53]_i_50_n_0\
    );
\xy[53]_i_51\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[23]\,
      I1 => \dy_reg_n_0_[25]\,
      O => \xy[53]_i_51_n_0\
    );
\xy[53]_i_52\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[22]\,
      I1 => \dy_reg_n_0_[25]\,
      O => \xy[53]_i_52_n_0\
    );
\xy[53]_i_53\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[21]\,
      I1 => \dy_reg_n_0_[25]\,
      O => \xy[53]_i_53_n_0\
    );
\xy[53]_i_54\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[26]\,
      I1 => \dy_reg_n_0_[21]\,
      O => \xy[53]_i_54_n_0\
    );
\xy[53]_i_55\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[26]\,
      I1 => \dy_reg_n_0_[18]\,
      O => \xy[53]_i_55_n_0\
    );
\xy[53]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \xy_reg[53]_i_20_n_14\,
      I1 => \xy_reg[53]_i_13_n_9\,
      I2 => \xy_reg[53]_i_20_n_15\,
      I3 => \xy_reg[53]_i_21_n_4\,
      I4 => \xy_reg[53]_i_13_n_10\,
      O => \xy[53]_i_6_n_0\
    );
\xy[53]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \xy_reg[39]_i_3_n_8\,
      I1 => \xy_reg[53]_i_21_n_13\,
      I2 => \xy_reg[53]_i_13_n_11\,
      I3 => \xy_reg[53]_i_21_n_4\,
      I4 => \xy_reg[53]_i_13_n_10\,
      I5 => \xy_reg[53]_i_20_n_15\,
      O => \xy[53]_i_7_n_0\
    );
\xy[53]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \xy_reg[53]_i_3_n_15\,
      I1 => \xy_reg[53]_i_20_n_4\,
      I2 => \xy_reg[53]_i_3_n_14\,
      I3 => \xy_reg[53]_i_3_n_13\,
      O => \xy[53]_i_8_n_0\
    );
\xy[53]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \xy_reg[53]_i_13_n_8\,
      I1 => \xy_reg[53]_i_20_n_13\,
      I2 => \xy_reg[53]_i_3_n_15\,
      I3 => \xy_reg[53]_i_20_n_4\,
      I4 => \xy_reg[53]_i_3_n_14\,
      O => \xy[53]_i_9_n_0\
    );
\xy[54]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(0),
      O => \xy[54]_i_1_n_0\
    );
\xy[55]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(1),
      O => \xy[55]_i_1_n_0\
    );
\xy[56]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(2),
      O => \xy[56]_i_1_n_0\
    );
\xy[57]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \xy_reg[57]_i_2_n_12\,
      I1 => \xy_reg[57]_i_3_n_15\,
      I2 => \stateScore_reg_rep__1_n_0\,
      O => \xy[57]_i_1_n_0\
    );
\xy[57]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[28]\,
      I1 => \dy_reg_n_0_[27]\,
      O => \xy[57]_i_10_n_0\
    );
\xy[57]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[57]_i_4_n_0\,
      I1 => \dy_reg_n_0_[29]\,
      I2 => \dx_reg_n_0_[32]\,
      I3 => \xy[57]_i_34_n_0\,
      I4 => \dx_reg_n_0_[34]\,
      I5 => \dy_reg_n_0_[27]\,
      O => \xy[57]_i_11_n_0\
    );
\xy[57]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[57]_i_5_n_0\,
      I1 => \dy_reg_n_0_[29]\,
      I2 => \dx_reg_n_0_[31]\,
      I3 => \xy[57]_i_35_n_0\,
      I4 => \dx_reg_n_0_[33]\,
      I5 => \dy_reg_n_0_[27]\,
      O => \xy[57]_i_12_n_0\
    );
\xy[57]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[57]_i_6_n_0\,
      I1 => \dy_reg_n_0_[29]\,
      I2 => \dx_reg_n_0_[30]\,
      I3 => \xy[57]_i_36_n_0\,
      I4 => \dx_reg_n_0_[32]\,
      I5 => \dy_reg_n_0_[27]\,
      O => \xy[57]_i_13_n_0\
    );
\xy[57]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[57]_i_7_n_0\,
      I1 => \dy_reg_n_0_[29]\,
      I2 => \dx_reg_n_0_[29]\,
      I3 => \xy[57]_i_37_n_0\,
      I4 => \dx_reg_n_0_[31]\,
      I5 => \dy_reg_n_0_[27]\,
      O => \xy[57]_i_14_n_0\
    );
\xy[57]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \xy[57]_i_8_n_0\,
      I1 => \dy_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[29]\,
      I3 => \dx_reg_n_0_[27]\,
      I4 => \dx_reg_n_0_[28]\,
      O => \xy[57]_i_15_n_0\
    );
\xy[57]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dx_reg_n_0_[27]\,
      I1 => \dy_reg_n_0_[29]\,
      I2 => \dx_reg_n_0_[28]\,
      I3 => \dy_reg_n_0_[28]\,
      I4 => \dy_reg_n_0_[27]\,
      I5 => \dx_reg_n_0_[29]\,
      O => \xy[57]_i_16_n_0\
    );
\xy[57]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[27]\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[28]\,
      I3 => \dx_reg_n_0_[27]\,
      O => \xy[57]_i_17_n_0\
    );
\xy[57]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[27]\,
      I1 => \dy_reg_n_0_[27]\,
      O => \xy[57]_i_18_n_0\
    );
\xy[57]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[32]\,
      I1 => \dx_reg_n_0_[31]\,
      I2 => \dy_reg_n_0_[31]\,
      I3 => \dx_reg_n_0_[32]\,
      I4 => \dx_reg_n_0_[33]\,
      I5 => \dy_reg_n_0_[30]\,
      O => \xy[57]_i_19_n_0\
    );
\xy[57]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[32]\,
      I1 => \dx_reg_n_0_[30]\,
      I2 => \dy_reg_n_0_[31]\,
      I3 => \dx_reg_n_0_[31]\,
      I4 => \dx_reg_n_0_[32]\,
      I5 => \dy_reg_n_0_[30]\,
      O => \xy[57]_i_20_n_0\
    );
\xy[57]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[32]\,
      I1 => \dx_reg_n_0_[29]\,
      I2 => \dy_reg_n_0_[31]\,
      I3 => \dx_reg_n_0_[30]\,
      I4 => \dx_reg_n_0_[31]\,
      I5 => \dy_reg_n_0_[30]\,
      O => \xy[57]_i_21_n_0\
    );
\xy[57]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[32]\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[31]\,
      I3 => \dx_reg_n_0_[29]\,
      I4 => \dx_reg_n_0_[30]\,
      I5 => \dy_reg_n_0_[30]\,
      O => \xy[57]_i_22_n_0\
    );
\xy[57]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dy_reg_n_0_[30]\,
      I1 => \dx_reg_n_0_[30]\,
      I2 => \dx_reg_n_0_[29]\,
      I3 => \dy_reg_n_0_[31]\,
      I4 => \dx_reg_n_0_[28]\,
      I5 => \dy_reg_n_0_[32]\,
      O => \xy[57]_i_23_n_0\
    );
\xy[57]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[31]\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[32]\,
      I3 => \dx_reg_n_0_[27]\,
      O => \xy[57]_i_24_n_0\
    );
\xy[57]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[28]\,
      I1 => \dy_reg_n_0_[30]\,
      O => \xy[57]_i_25_n_0\
    );
\xy[57]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[57]_i_19_n_0\,
      I1 => \dy_reg_n_0_[32]\,
      I2 => \dx_reg_n_0_[32]\,
      I3 => \xy[57]_i_38_n_0\,
      I4 => \dx_reg_n_0_[34]\,
      I5 => \dy_reg_n_0_[30]\,
      O => \xy[57]_i_26_n_0\
    );
\xy[57]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[57]_i_20_n_0\,
      I1 => \dy_reg_n_0_[32]\,
      I2 => \dx_reg_n_0_[31]\,
      I3 => \xy[57]_i_39_n_0\,
      I4 => \dx_reg_n_0_[33]\,
      I5 => \dy_reg_n_0_[30]\,
      O => \xy[57]_i_27_n_0\
    );
\xy[57]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[57]_i_21_n_0\,
      I1 => \dy_reg_n_0_[32]\,
      I2 => \dx_reg_n_0_[30]\,
      I3 => \xy[57]_i_40_n_0\,
      I4 => \dx_reg_n_0_[32]\,
      I5 => \dy_reg_n_0_[30]\,
      O => \xy[57]_i_28_n_0\
    );
\xy[57]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[57]_i_22_n_0\,
      I1 => \dy_reg_n_0_[32]\,
      I2 => \dx_reg_n_0_[29]\,
      I3 => \xy[57]_i_41_n_0\,
      I4 => \dx_reg_n_0_[31]\,
      I5 => \dy_reg_n_0_[30]\,
      O => \xy[57]_i_29_n_0\
    );
\xy[57]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \xy[57]_i_23_n_0\,
      I1 => \dy_reg_n_0_[31]\,
      I2 => \dy_reg_n_0_[32]\,
      I3 => \dx_reg_n_0_[27]\,
      I4 => \dx_reg_n_0_[28]\,
      O => \xy[57]_i_30_n_0\
    );
\xy[57]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dx_reg_n_0_[27]\,
      I1 => \dy_reg_n_0_[32]\,
      I2 => \dx_reg_n_0_[28]\,
      I3 => \dy_reg_n_0_[31]\,
      I4 => \dy_reg_n_0_[30]\,
      I5 => \dx_reg_n_0_[29]\,
      O => \xy[57]_i_31_n_0\
    );
\xy[57]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[30]\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[31]\,
      I3 => \dx_reg_n_0_[27]\,
      O => \xy[57]_i_32_n_0\
    );
\xy[57]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[27]\,
      I1 => \dy_reg_n_0_[30]\,
      O => \xy[57]_i_33_n_0\
    );
\xy[57]_i_34\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[33]\,
      I1 => \dy_reg_n_0_[28]\,
      O => \xy[57]_i_34_n_0\
    );
\xy[57]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[32]\,
      I1 => \dy_reg_n_0_[28]\,
      O => \xy[57]_i_35_n_0\
    );
\xy[57]_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[31]\,
      I1 => \dy_reg_n_0_[28]\,
      O => \xy[57]_i_36_n_0\
    );
\xy[57]_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[30]\,
      I1 => \dy_reg_n_0_[28]\,
      O => \xy[57]_i_37_n_0\
    );
\xy[57]_i_38\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[33]\,
      I1 => \dy_reg_n_0_[31]\,
      O => \xy[57]_i_38_n_0\
    );
\xy[57]_i_39\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[32]\,
      I1 => \dy_reg_n_0_[31]\,
      O => \xy[57]_i_39_n_0\
    );
\xy[57]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[29]\,
      I1 => \dx_reg_n_0_[31]\,
      I2 => \dy_reg_n_0_[28]\,
      I3 => \dx_reg_n_0_[32]\,
      I4 => \dx_reg_n_0_[33]\,
      I5 => \dy_reg_n_0_[27]\,
      O => \xy[57]_i_4_n_0\
    );
\xy[57]_i_40\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[31]\,
      I1 => \dy_reg_n_0_[31]\,
      O => \xy[57]_i_40_n_0\
    );
\xy[57]_i_41\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[30]\,
      I1 => \dy_reg_n_0_[31]\,
      O => \xy[57]_i_41_n_0\
    );
\xy[57]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[29]\,
      I1 => \dx_reg_n_0_[30]\,
      I2 => \dy_reg_n_0_[28]\,
      I3 => \dx_reg_n_0_[31]\,
      I4 => \dx_reg_n_0_[32]\,
      I5 => \dy_reg_n_0_[27]\,
      O => \xy[57]_i_5_n_0\
    );
\xy[57]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[29]\,
      I1 => \dx_reg_n_0_[29]\,
      I2 => \dy_reg_n_0_[28]\,
      I3 => \dx_reg_n_0_[30]\,
      I4 => \dx_reg_n_0_[31]\,
      I5 => \dy_reg_n_0_[27]\,
      O => \xy[57]_i_6_n_0\
    );
\xy[57]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[29]\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[28]\,
      I3 => \dx_reg_n_0_[29]\,
      I4 => \dx_reg_n_0_[30]\,
      I5 => \dy_reg_n_0_[27]\,
      O => \xy[57]_i_7_n_0\
    );
\xy[57]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dy_reg_n_0_[27]\,
      I1 => \dx_reg_n_0_[30]\,
      I2 => \dx_reg_n_0_[29]\,
      I3 => \dy_reg_n_0_[28]\,
      I4 => \dx_reg_n_0_[28]\,
      I5 => \dy_reg_n_0_[29]\,
      O => \xy[57]_i_8_n_0\
    );
\xy[57]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[28]\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[29]\,
      I3 => \dx_reg_n_0_[27]\,
      O => \xy[57]_i_9_n_0\
    );
\xy[58]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(4),
      O => \xy[58]_i_1_n_0\
    );
\xy[59]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(5),
      O => \xy[59]_i_1_n_0\
    );
\xy[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(5),
      O => \xy[5]_i_1_n_0\
    );
\xy[60]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(6),
      O => \xy[60]_i_1_n_0\
    );
\xy[61]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(7),
      O => \xy[61]_i_1_n_0\
    );
\xy[62]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(8),
      O => \xy[62]_i_1_n_0\
    );
\xy[63]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(9),
      O => \xy[63]_i_1_n_0\
    );
\xy[64]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(10),
      O => \xy[64]_i_1_n_0\
    );
\xy[65]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(11),
      O => \xy[65]_i_1_n_0\
    );
\xy[65]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[57]_i_3_n_15\,
      I1 => \xy_reg[57]_i_2_n_12\,
      O => \xy[65]_i_10_n_0\
    );
\xy[65]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \xy_reg[57]_i_3_n_9\,
      I1 => \xy_reg[71]_i_13_n_12\,
      I2 => \xy_reg[71]_i_21_n_13\,
      I3 => \xy_reg[71]_i_13_n_11\,
      I4 => \xy_reg[57]_i_3_n_8\,
      I5 => \xy[65]_i_19_n_0\,
      O => \xy[65]_i_11_n_0\
    );
\xy[65]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \xy_reg[71]_i_21_n_14\,
      I1 => \xy_reg[57]_i_3_n_9\,
      I2 => \xy_reg[71]_i_13_n_12\,
      I3 => \xy_reg[57]_i_3_n_8\,
      I4 => \xy_reg[71]_i_13_n_11\,
      I5 => \xy_reg[71]_i_21_n_13\,
      O => \xy[65]_i_12_n_0\
    );
\xy[65]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \xy_reg[71]_i_21_n_14\,
      I1 => \xy_reg[71]_i_13_n_12\,
      I2 => \xy_reg[57]_i_3_n_9\,
      I3 => \xy_reg[57]_i_3_n_10\,
      I4 => \xy_reg[71]_i_21_n_15\,
      I5 => \xy_reg[71]_i_13_n_13\,
      O => \xy[65]_i_13_n_0\
    );
\xy[65]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy[65]_i_6_n_0\,
      I1 => \xy_reg[71]_i_13_n_13\,
      I2 => \xy_reg[71]_i_21_n_15\,
      I3 => \xy_reg[57]_i_3_n_10\,
      O => \xy[65]_i_14_n_0\
    );
\xy[65]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy_reg[71]_i_13_n_14\,
      I1 => \xy_reg[57]_i_2_n_8\,
      I2 => \xy_reg[57]_i_3_n_11\,
      I3 => \xy[65]_i_7_n_0\,
      O => \xy[65]_i_15_n_0\
    );
\xy[65]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy_reg[71]_i_13_n_15\,
      I1 => \xy_reg[57]_i_2_n_9\,
      I2 => \xy_reg[57]_i_3_n_12\,
      I3 => \xy[65]_i_8_n_0\,
      O => \xy[65]_i_16_n_0\
    );
\xy[65]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xy_reg[57]_i_3_n_13\,
      I1 => \xy_reg[57]_i_2_n_10\,
      I2 => \xy_reg[57]_i_2_n_11\,
      I3 => \xy_reg[57]_i_3_n_14\,
      O => \xy[65]_i_17_n_0\
    );
\xy[65]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \xy_reg[57]_i_2_n_12\,
      I1 => \xy_reg[57]_i_3_n_15\,
      I2 => \xy_reg[57]_i_2_n_11\,
      I3 => \xy_reg[57]_i_3_n_14\,
      O => \xy[65]_i_18_n_0\
    );
\xy[65]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xy_reg[71]_i_20_n_15\,
      I1 => \xy_reg[71]_i_13_n_10\,
      I2 => \xy_reg[71]_i_21_n_4\,
      O => \xy[65]_i_19_n_0\
    );
\xy[65]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \xy_reg[57]_i_3_n_9\,
      I1 => \xy_reg[71]_i_13_n_12\,
      I2 => \xy_reg[71]_i_21_n_13\,
      I3 => \xy_reg[71]_i_13_n_11\,
      I4 => \xy_reg[57]_i_3_n_8\,
      O => \xy[65]_i_3_n_0\
    );
\xy[65]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \xy_reg[71]_i_21_n_14\,
      I1 => \xy_reg[57]_i_3_n_9\,
      I2 => \xy_reg[71]_i_13_n_12\,
      O => \xy[65]_i_4_n_0\
    );
\xy[65]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xy_reg[57]_i_3_n_9\,
      I1 => \xy_reg[71]_i_13_n_12\,
      I2 => \xy_reg[71]_i_21_n_14\,
      O => \xy[65]_i_5_n_0\
    );
\xy[65]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xy_reg[71]_i_13_n_14\,
      I1 => \xy_reg[57]_i_2_n_8\,
      I2 => \xy_reg[57]_i_3_n_11\,
      O => \xy[65]_i_6_n_0\
    );
\xy[65]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xy_reg[71]_i_13_n_15\,
      I1 => \xy_reg[57]_i_2_n_9\,
      I2 => \xy_reg[57]_i_3_n_12\,
      O => \xy[65]_i_7_n_0\
    );
\xy[65]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[57]_i_3_n_13\,
      I1 => \xy_reg[57]_i_2_n_10\,
      O => \xy[65]_i_8_n_0\
    );
\xy[65]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[57]_i_3_n_14\,
      I1 => \xy_reg[57]_i_2_n_11\,
      O => \xy[65]_i_9_n_0\
    );
\xy[66]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(12),
      O => \xy[66]_i_1_n_0\
    );
\xy[67]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(13),
      O => \xy[67]_i_1_n_0\
    );
\xy[68]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(14),
      O => \xy[68]_i_1_n_0\
    );
\xy[69]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy02_in(15),
      O => \xy[69]_i_1_n_0\
    );
\xy[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(6),
      O => \xy[6]_i_1_n_0\
    );
\xy[70]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xy02_in(16),
      O => \xy[70]_i_1_n_0\
    );
\xy[71]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xy02_in(17),
      O => \xy[71]_i_1_n_0\
    );
\xy[71]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \xy[71]_i_5_n_0\,
      I1 => \xy_reg[71]_i_3_n_15\,
      I2 => \xy_reg[71]_i_20_n_4\,
      I3 => \xy_reg[71]_i_13_n_8\,
      I4 => \xy_reg[71]_i_20_n_13\,
      O => \xy[71]_i_10_n_0\
    );
\xy[71]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \xy_reg[71]_i_20_n_14\,
      I1 => \xy_reg[71]_i_13_n_9\,
      I2 => \xy_reg[71]_i_20_n_13\,
      I3 => \xy_reg[71]_i_13_n_8\,
      I4 => \xy[71]_i_6_n_0\,
      O => \xy[71]_i_11_n_0\
    );
\xy[71]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \xy[71]_i_7_n_0\,
      I1 => \xy_reg[71]_i_20_n_15\,
      I2 => \xy_reg[71]_i_21_n_4\,
      I3 => \xy_reg[71]_i_13_n_10\,
      I4 => \xy_reg[71]_i_20_n_14\,
      I5 => \xy_reg[71]_i_13_n_9\,
      O => \xy[71]_i_12_n_0\
    );
\xy[71]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => \dy_reg_n_0_[35]\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[35]\,
      O => \xy[71]_i_14_n_0\
    );
\xy[71]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08888FFF8FFF8FFF"
    )
        port map (
      I0 => \dy_reg_n_0_[34]\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[35]\,
      I3 => \dx_reg_n_0_[33]\,
      I4 => \dx_reg_n_0_[35]\,
      I5 => \dy_reg_n_0_[33]\,
      O => \xy[71]_i_15_n_0\
    );
\xy[71]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[35]\,
      I1 => \dx_reg_n_0_[32]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[33]\,
      I4 => \dx_reg_n_0_[34]\,
      I5 => \dy_reg_n_0_[33]\,
      O => \xy[71]_i_16_n_0\
    );
\xy[71]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E53F"
    )
        port map (
      I0 => \dy_reg_n_0_[34]\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[35]\,
      I3 => \dx_reg_n_0_[35]\,
      O => \xy[71]_i_17_n_0\
    );
\xy[71]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"70ECE3130F5FAF5F"
    )
        port map (
      I0 => \dy_reg_n_0_[33]\,
      I1 => \dx_reg_n_0_[33]\,
      I2 => \dx_reg_n_0_[35]\,
      I3 => \dy_reg_n_0_[34]\,
      I4 => \dx_reg_n_0_[34]\,
      I5 => \dy_reg_n_0_[35]\,
      O => \xy[71]_i_18_n_0\
    );
\xy[71]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \xy[71]_i_16_n_0\,
      I1 => \dx_reg_n_0_[35]\,
      I2 => \dy_reg_n_0_[33]\,
      I3 => \dy_reg_n_0_[35]\,
      I4 => \dx_reg_n_0_[33]\,
      I5 => \xy[71]_i_37_n_0\,
      O => \xy[71]_i_19_n_0\
    );
\xy[71]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[35]\,
      I1 => \dx_reg_n_0_[31]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[32]\,
      I4 => \dx_reg_n_0_[33]\,
      I5 => \dy_reg_n_0_[33]\,
      O => \xy[71]_i_22_n_0\
    );
\xy[71]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[35]\,
      I1 => \dx_reg_n_0_[30]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[31]\,
      I4 => \dx_reg_n_0_[32]\,
      I5 => \dy_reg_n_0_[33]\,
      O => \xy[71]_i_23_n_0\
    );
\xy[71]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[35]\,
      I1 => \dx_reg_n_0_[29]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[30]\,
      I4 => \dx_reg_n_0_[31]\,
      I5 => \dy_reg_n_0_[33]\,
      O => \xy[71]_i_24_n_0\
    );
\xy[71]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[35]\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[29]\,
      I4 => \dx_reg_n_0_[30]\,
      I5 => \dy_reg_n_0_[33]\,
      O => \xy[71]_i_25_n_0\
    );
\xy[71]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dy_reg_n_0_[33]\,
      I1 => \dx_reg_n_0_[30]\,
      I2 => \dx_reg_n_0_[29]\,
      I3 => \dy_reg_n_0_[34]\,
      I4 => \dx_reg_n_0_[28]\,
      I5 => \dy_reg_n_0_[35]\,
      O => \xy[71]_i_26_n_0\
    );
\xy[71]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[35]\,
      I1 => \dx_reg_n_0_[27]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[28]\,
      O => \xy[71]_i_27_n_0\
    );
\xy[71]_i_28\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[28]\,
      I1 => \dy_reg_n_0_[33]\,
      O => \xy[71]_i_28_n_0\
    );
\xy[71]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[71]_i_22_n_0\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[33]\,
      I3 => \dy_reg_n_0_[35]\,
      I4 => \dx_reg_n_0_[32]\,
      I5 => \xy[71]_i_50_n_0\,
      O => \xy[71]_i_29_n_0\
    );
\xy[71]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[71]_i_23_n_0\,
      I1 => \dx_reg_n_0_[33]\,
      I2 => \dy_reg_n_0_[33]\,
      I3 => \dy_reg_n_0_[35]\,
      I4 => \dx_reg_n_0_[31]\,
      I5 => \xy[71]_i_51_n_0\,
      O => \xy[71]_i_30_n_0\
    );
\xy[71]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[71]_i_24_n_0\,
      I1 => \dx_reg_n_0_[32]\,
      I2 => \dy_reg_n_0_[33]\,
      I3 => \dy_reg_n_0_[35]\,
      I4 => \dx_reg_n_0_[30]\,
      I5 => \xy[71]_i_52_n_0\,
      O => \xy[71]_i_31_n_0\
    );
\xy[71]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[71]_i_25_n_0\,
      I1 => \dx_reg_n_0_[31]\,
      I2 => \dy_reg_n_0_[33]\,
      I3 => \dy_reg_n_0_[35]\,
      I4 => \dx_reg_n_0_[29]\,
      I5 => \xy[71]_i_53_n_0\,
      O => \xy[71]_i_32_n_0\
    );
\xy[71]_i_33\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A6A6A"
    )
        port map (
      I0 => \xy[71]_i_26_n_0\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[27]\,
      I4 => \dy_reg_n_0_[35]\,
      O => \xy[71]_i_33_n_0\
    );
\xy[71]_i_34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dx_reg_n_0_[28]\,
      I1 => \dy_reg_n_0_[34]\,
      I2 => \dx_reg_n_0_[27]\,
      I3 => \dy_reg_n_0_[35]\,
      I4 => \dy_reg_n_0_[33]\,
      I5 => \dx_reg_n_0_[29]\,
      O => \xy[71]_i_34_n_0\
    );
\xy[71]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[33]\,
      I1 => \dx_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dx_reg_n_0_[27]\,
      O => \xy[71]_i_35_n_0\
    );
\xy[71]_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[27]\,
      I1 => \dy_reg_n_0_[33]\,
      O => \xy[71]_i_36_n_0\
    );
\xy[71]_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[34]\,
      I1 => \dy_reg_n_0_[34]\,
      O => \xy[71]_i_37_n_0\
    );
\xy[71]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[32]\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[31]\,
      I3 => \dx_reg_n_0_[35]\,
      O => \xy[71]_i_38_n_0\
    );
\xy[71]_i_39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000EAC0EAC0EAC0"
    )
        port map (
      I0 => \dx_reg_n_0_[34]\,
      I1 => \dx_reg_n_0_[33]\,
      I2 => \dy_reg_n_0_[32]\,
      I3 => \dy_reg_n_0_[31]\,
      I4 => \dx_reg_n_0_[35]\,
      I5 => \dy_reg_n_0_[30]\,
      O => \xy[71]_i_39_n_0\
    );
\xy[71]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xy_reg[71]_i_20_n_13\,
      I1 => \xy_reg[71]_i_13_n_8\,
      I2 => \xy_reg[71]_i_20_n_4\,
      I3 => \xy_reg[71]_i_3_n_15\,
      O => \xy[71]_i_4_n_0\
    );
\xy[71]_i_40\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[32]\,
      I1 => \dx_reg_n_0_[32]\,
      I2 => \dy_reg_n_0_[31]\,
      I3 => \dx_reg_n_0_[33]\,
      I4 => \dx_reg_n_0_[34]\,
      I5 => \dy_reg_n_0_[30]\,
      O => \xy[71]_i_40_n_0\
    );
\xy[71]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F3F"
    )
        port map (
      I0 => \dy_reg_n_0_[31]\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[32]\,
      I3 => \dx_reg_n_0_[35]\,
      O => \xy[71]_i_41_n_0\
    );
\xy[71]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"25404FBFF03FCF3F"
    )
        port map (
      I0 => \dy_reg_n_0_[30]\,
      I1 => \dx_reg_n_0_[33]\,
      I2 => \dy_reg_n_0_[32]\,
      I3 => \dx_reg_n_0_[34]\,
      I4 => \dy_reg_n_0_[31]\,
      I5 => \dx_reg_n_0_[35]\,
      O => \xy[71]_i_42_n_0\
    );
\xy[71]_i_43\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[71]_i_40_n_0\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[31]\,
      I3 => \dx_reg_n_0_[33]\,
      I4 => \dy_reg_n_0_[32]\,
      I5 => \xy[71]_i_54_n_0\,
      O => \xy[71]_i_43_n_0\
    );
\xy[71]_i_44\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[29]\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[28]\,
      I3 => \dx_reg_n_0_[35]\,
      O => \xy[71]_i_44_n_0\
    );
\xy[71]_i_45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000EAC0EAC0EAC0"
    )
        port map (
      I0 => \dx_reg_n_0_[34]\,
      I1 => \dx_reg_n_0_[33]\,
      I2 => \dy_reg_n_0_[29]\,
      I3 => \dy_reg_n_0_[28]\,
      I4 => \dx_reg_n_0_[35]\,
      I5 => \dy_reg_n_0_[27]\,
      O => \xy[71]_i_45_n_0\
    );
\xy[71]_i_46\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F880808088000000"
    )
        port map (
      I0 => \dx_reg_n_0_[34]\,
      I1 => \dy_reg_n_0_[27]\,
      I2 => \dx_reg_n_0_[33]\,
      I3 => \dx_reg_n_0_[32]\,
      I4 => \dy_reg_n_0_[29]\,
      I5 => \dy_reg_n_0_[28]\,
      O => \xy[71]_i_46_n_0\
    );
\xy[71]_i_47\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F3F"
    )
        port map (
      I0 => \dy_reg_n_0_[28]\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[29]\,
      I3 => \dx_reg_n_0_[35]\,
      O => \xy[71]_i_47_n_0\
    );
\xy[71]_i_48\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"25404FBFF03FCF3F"
    )
        port map (
      I0 => \dy_reg_n_0_[27]\,
      I1 => \dx_reg_n_0_[33]\,
      I2 => \dy_reg_n_0_[29]\,
      I3 => \dx_reg_n_0_[34]\,
      I4 => \dy_reg_n_0_[28]\,
      I5 => \dx_reg_n_0_[35]\,
      O => \xy[71]_i_48_n_0\
    );
\xy[71]_i_49\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[71]_i_46_n_0\,
      I1 => \dx_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[28]\,
      I3 => \dx_reg_n_0_[33]\,
      I4 => \dy_reg_n_0_[29]\,
      I5 => \xy[71]_i_55_n_0\,
      O => \xy[71]_i_49_n_0\
    );
\xy[71]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xy_reg[71]_i_20_n_14\,
      I1 => \xy_reg[71]_i_13_n_9\,
      I2 => \xy_reg[71]_i_20_n_13\,
      I3 => \xy_reg[71]_i_13_n_8\,
      O => \xy[71]_i_5_n_0\
    );
\xy[71]_i_50\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[33]\,
      I1 => \dy_reg_n_0_[34]\,
      O => \xy[71]_i_50_n_0\
    );
\xy[71]_i_51\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[32]\,
      I1 => \dy_reg_n_0_[34]\,
      O => \xy[71]_i_51_n_0\
    );
\xy[71]_i_52\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[31]\,
      I1 => \dy_reg_n_0_[34]\,
      O => \xy[71]_i_52_n_0\
    );
\xy[71]_i_53\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[30]\,
      I1 => \dy_reg_n_0_[34]\,
      O => \xy[71]_i_53_n_0\
    );
\xy[71]_i_54\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[35]\,
      I1 => \dy_reg_n_0_[30]\,
      O => \xy[71]_i_54_n_0\
    );
\xy[71]_i_55\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[35]\,
      I1 => \dy_reg_n_0_[27]\,
      O => \xy[71]_i_55_n_0\
    );
\xy[71]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \xy_reg[71]_i_20_n_14\,
      I1 => \xy_reg[71]_i_13_n_9\,
      I2 => \xy_reg[71]_i_20_n_15\,
      I3 => \xy_reg[71]_i_21_n_4\,
      I4 => \xy_reg[71]_i_13_n_10\,
      O => \xy[71]_i_6_n_0\
    );
\xy[71]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \xy_reg[57]_i_3_n_8\,
      I1 => \xy_reg[71]_i_21_n_13\,
      I2 => \xy_reg[71]_i_13_n_11\,
      I3 => \xy_reg[71]_i_21_n_4\,
      I4 => \xy_reg[71]_i_13_n_10\,
      I5 => \xy_reg[71]_i_20_n_15\,
      O => \xy[71]_i_7_n_0\
    );
\xy[71]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \xy_reg[71]_i_3_n_15\,
      I1 => \xy_reg[71]_i_20_n_4\,
      I2 => \xy_reg[71]_i_3_n_14\,
      I3 => \xy_reg[71]_i_3_n_13\,
      O => \xy[71]_i_8_n_0\
    );
\xy[71]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \xy_reg[71]_i_13_n_8\,
      I1 => \xy_reg[71]_i_20_n_13\,
      I2 => \xy_reg[71]_i_3_n_15\,
      I3 => \xy_reg[71]_i_20_n_4\,
      I4 => \xy_reg[71]_i_3_n_14\,
      O => \xy[71]_i_9_n_0\
    );
\xy[72]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(0),
      O => \xy[72]_i_1_n_0\
    );
\xy[73]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(1),
      O => \xy[73]_i_1_n_0\
    );
\xy[74]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(2),
      O => \xy[74]_i_1_n_0\
    );
\xy[75]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \xy_reg[75]_i_2_n_12\,
      I1 => \xy_reg[75]_i_3_n_15\,
      I2 => \stateScore_reg_rep__2_n_0\,
      O => \xy[75]_i_1_n_0\
    );
\xy[75]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[37]\,
      I1 => \dy_reg_n_0_[36]\,
      O => \xy[75]_i_10_n_0\
    );
\xy[75]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[75]_i_4_n_0\,
      I1 => \dy_reg_n_0_[38]\,
      I2 => \dx_reg_n_0_[41]\,
      I3 => \xy[75]_i_34_n_0\,
      I4 => \dx_reg_n_0_[43]\,
      I5 => \dy_reg_n_0_[36]\,
      O => \xy[75]_i_11_n_0\
    );
\xy[75]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[75]_i_5_n_0\,
      I1 => \dy_reg_n_0_[38]\,
      I2 => \dx_reg_n_0_[40]\,
      I3 => \xy[75]_i_35_n_0\,
      I4 => \dx_reg_n_0_[42]\,
      I5 => \dy_reg_n_0_[36]\,
      O => \xy[75]_i_12_n_0\
    );
\xy[75]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[75]_i_6_n_0\,
      I1 => \dy_reg_n_0_[38]\,
      I2 => \dx_reg_n_0_[39]\,
      I3 => \xy[75]_i_36_n_0\,
      I4 => \dx_reg_n_0_[41]\,
      I5 => \dy_reg_n_0_[36]\,
      O => \xy[75]_i_13_n_0\
    );
\xy[75]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[75]_i_7_n_0\,
      I1 => \dy_reg_n_0_[38]\,
      I2 => \dx_reg_n_0_[38]\,
      I3 => \xy[75]_i_37_n_0\,
      I4 => \dx_reg_n_0_[40]\,
      I5 => \dy_reg_n_0_[36]\,
      O => \xy[75]_i_14_n_0\
    );
\xy[75]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \xy[75]_i_8_n_0\,
      I1 => \dy_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[38]\,
      I3 => \dx_reg_n_0_[36]\,
      I4 => \dx_reg_n_0_[37]\,
      O => \xy[75]_i_15_n_0\
    );
\xy[75]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dx_reg_n_0_[36]\,
      I1 => \dy_reg_n_0_[38]\,
      I2 => \dx_reg_n_0_[37]\,
      I3 => \dy_reg_n_0_[37]\,
      I4 => \dy_reg_n_0_[36]\,
      I5 => \dx_reg_n_0_[38]\,
      O => \xy[75]_i_16_n_0\
    );
\xy[75]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[36]\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[37]\,
      I3 => \dx_reg_n_0_[36]\,
      O => \xy[75]_i_17_n_0\
    );
\xy[75]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[36]\,
      I1 => \dy_reg_n_0_[36]\,
      O => \xy[75]_i_18_n_0\
    );
\xy[75]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[41]\,
      I1 => \dx_reg_n_0_[40]\,
      I2 => \dy_reg_n_0_[40]\,
      I3 => \dx_reg_n_0_[41]\,
      I4 => \dx_reg_n_0_[42]\,
      I5 => \dy_reg_n_0_[39]\,
      O => \xy[75]_i_19_n_0\
    );
\xy[75]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[41]\,
      I1 => \dx_reg_n_0_[39]\,
      I2 => \dy_reg_n_0_[40]\,
      I3 => \dx_reg_n_0_[40]\,
      I4 => \dx_reg_n_0_[41]\,
      I5 => \dy_reg_n_0_[39]\,
      O => \xy[75]_i_20_n_0\
    );
\xy[75]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[41]\,
      I1 => \dx_reg_n_0_[38]\,
      I2 => \dy_reg_n_0_[40]\,
      I3 => \dx_reg_n_0_[39]\,
      I4 => \dx_reg_n_0_[40]\,
      I5 => \dy_reg_n_0_[39]\,
      O => \xy[75]_i_21_n_0\
    );
\xy[75]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[41]\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[40]\,
      I3 => \dx_reg_n_0_[38]\,
      I4 => \dx_reg_n_0_[39]\,
      I5 => \dy_reg_n_0_[39]\,
      O => \xy[75]_i_22_n_0\
    );
\xy[75]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dy_reg_n_0_[39]\,
      I1 => \dx_reg_n_0_[39]\,
      I2 => \dx_reg_n_0_[38]\,
      I3 => \dy_reg_n_0_[40]\,
      I4 => \dx_reg_n_0_[37]\,
      I5 => \dy_reg_n_0_[41]\,
      O => \xy[75]_i_23_n_0\
    );
\xy[75]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[40]\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[41]\,
      I3 => \dx_reg_n_0_[36]\,
      O => \xy[75]_i_24_n_0\
    );
\xy[75]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[37]\,
      I1 => \dy_reg_n_0_[39]\,
      O => \xy[75]_i_25_n_0\
    );
\xy[75]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[75]_i_19_n_0\,
      I1 => \dy_reg_n_0_[41]\,
      I2 => \dx_reg_n_0_[41]\,
      I3 => \xy[75]_i_38_n_0\,
      I4 => \dx_reg_n_0_[43]\,
      I5 => \dy_reg_n_0_[39]\,
      O => \xy[75]_i_26_n_0\
    );
\xy[75]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[75]_i_20_n_0\,
      I1 => \dy_reg_n_0_[41]\,
      I2 => \dx_reg_n_0_[40]\,
      I3 => \xy[75]_i_39_n_0\,
      I4 => \dx_reg_n_0_[42]\,
      I5 => \dy_reg_n_0_[39]\,
      O => \xy[75]_i_27_n_0\
    );
\xy[75]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[75]_i_21_n_0\,
      I1 => \dy_reg_n_0_[41]\,
      I2 => \dx_reg_n_0_[39]\,
      I3 => \xy[75]_i_40_n_0\,
      I4 => \dx_reg_n_0_[41]\,
      I5 => \dy_reg_n_0_[39]\,
      O => \xy[75]_i_28_n_0\
    );
\xy[75]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \xy[75]_i_22_n_0\,
      I1 => \dy_reg_n_0_[41]\,
      I2 => \dx_reg_n_0_[38]\,
      I3 => \xy[75]_i_41_n_0\,
      I4 => \dx_reg_n_0_[40]\,
      I5 => \dy_reg_n_0_[39]\,
      O => \xy[75]_i_29_n_0\
    );
\xy[75]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \xy[75]_i_23_n_0\,
      I1 => \dy_reg_n_0_[40]\,
      I2 => \dy_reg_n_0_[41]\,
      I3 => \dx_reg_n_0_[36]\,
      I4 => \dx_reg_n_0_[37]\,
      O => \xy[75]_i_30_n_0\
    );
\xy[75]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dx_reg_n_0_[36]\,
      I1 => \dy_reg_n_0_[41]\,
      I2 => \dx_reg_n_0_[37]\,
      I3 => \dy_reg_n_0_[40]\,
      I4 => \dy_reg_n_0_[39]\,
      I5 => \dx_reg_n_0_[38]\,
      O => \xy[75]_i_31_n_0\
    );
\xy[75]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[39]\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[40]\,
      I3 => \dx_reg_n_0_[36]\,
      O => \xy[75]_i_32_n_0\
    );
\xy[75]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[36]\,
      I1 => \dy_reg_n_0_[39]\,
      O => \xy[75]_i_33_n_0\
    );
\xy[75]_i_34\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[42]\,
      I1 => \dy_reg_n_0_[37]\,
      O => \xy[75]_i_34_n_0\
    );
\xy[75]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[41]\,
      I1 => \dy_reg_n_0_[37]\,
      O => \xy[75]_i_35_n_0\
    );
\xy[75]_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[40]\,
      I1 => \dy_reg_n_0_[37]\,
      O => \xy[75]_i_36_n_0\
    );
\xy[75]_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[39]\,
      I1 => \dy_reg_n_0_[37]\,
      O => \xy[75]_i_37_n_0\
    );
\xy[75]_i_38\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[42]\,
      I1 => \dy_reg_n_0_[40]\,
      O => \xy[75]_i_38_n_0\
    );
\xy[75]_i_39\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[41]\,
      I1 => \dy_reg_n_0_[40]\,
      O => \xy[75]_i_39_n_0\
    );
\xy[75]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[38]\,
      I1 => \dx_reg_n_0_[40]\,
      I2 => \dy_reg_n_0_[37]\,
      I3 => \dx_reg_n_0_[41]\,
      I4 => \dx_reg_n_0_[42]\,
      I5 => \dy_reg_n_0_[36]\,
      O => \xy[75]_i_4_n_0\
    );
\xy[75]_i_40\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[40]\,
      I1 => \dy_reg_n_0_[40]\,
      O => \xy[75]_i_40_n_0\
    );
\xy[75]_i_41\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[39]\,
      I1 => \dy_reg_n_0_[40]\,
      O => \xy[75]_i_41_n_0\
    );
\xy[75]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[38]\,
      I1 => \dx_reg_n_0_[39]\,
      I2 => \dy_reg_n_0_[37]\,
      I3 => \dx_reg_n_0_[40]\,
      I4 => \dx_reg_n_0_[41]\,
      I5 => \dy_reg_n_0_[36]\,
      O => \xy[75]_i_5_n_0\
    );
\xy[75]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[38]\,
      I1 => \dx_reg_n_0_[38]\,
      I2 => \dy_reg_n_0_[37]\,
      I3 => \dx_reg_n_0_[39]\,
      I4 => \dx_reg_n_0_[40]\,
      I5 => \dy_reg_n_0_[36]\,
      O => \xy[75]_i_6_n_0\
    );
\xy[75]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[38]\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[37]\,
      I3 => \dx_reg_n_0_[38]\,
      I4 => \dx_reg_n_0_[39]\,
      I5 => \dy_reg_n_0_[36]\,
      O => \xy[75]_i_7_n_0\
    );
\xy[75]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dy_reg_n_0_[36]\,
      I1 => \dx_reg_n_0_[39]\,
      I2 => \dx_reg_n_0_[38]\,
      I3 => \dy_reg_n_0_[37]\,
      I4 => \dx_reg_n_0_[37]\,
      I5 => \dy_reg_n_0_[38]\,
      O => \xy[75]_i_8_n_0\
    );
\xy[75]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[37]\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[38]\,
      I3 => \dx_reg_n_0_[36]\,
      O => \xy[75]_i_9_n_0\
    );
\xy[76]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(4),
      O => \xy[76]_i_1_n_0\
    );
\xy[77]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(5),
      O => \xy[77]_i_1_n_0\
    );
\xy[78]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(6),
      O => \xy[78]_i_1_n_0\
    );
\xy[79]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(7),
      O => \xy[79]_i_1_n_0\
    );
\xy[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(7),
      O => \xy[7]_i_1_n_0\
    );
\xy[80]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(8),
      O => \xy[80]_i_1_n_0\
    );
\xy[81]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(9),
      O => \xy[81]_i_1_n_0\
    );
\xy[82]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(10),
      O => \xy[82]_i_1_n_0\
    );
\xy[83]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(11),
      O => \xy[83]_i_1_n_0\
    );
\xy[83]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[75]_i_3_n_15\,
      I1 => \xy_reg[75]_i_2_n_12\,
      O => \xy[83]_i_10_n_0\
    );
\xy[83]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \xy_reg[75]_i_3_n_9\,
      I1 => \xy_reg[89]_i_13_n_12\,
      I2 => \xy_reg[89]_i_21_n_13\,
      I3 => \xy_reg[89]_i_13_n_11\,
      I4 => \xy_reg[75]_i_3_n_8\,
      I5 => \xy[83]_i_19_n_0\,
      O => \xy[83]_i_11_n_0\
    );
\xy[83]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \xy_reg[89]_i_21_n_14\,
      I1 => \xy_reg[75]_i_3_n_9\,
      I2 => \xy_reg[89]_i_13_n_12\,
      I3 => \xy_reg[75]_i_3_n_8\,
      I4 => \xy_reg[89]_i_13_n_11\,
      I5 => \xy_reg[89]_i_21_n_13\,
      O => \xy[83]_i_12_n_0\
    );
\xy[83]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \xy_reg[89]_i_21_n_14\,
      I1 => \xy_reg[89]_i_13_n_12\,
      I2 => \xy_reg[75]_i_3_n_9\,
      I3 => \xy_reg[75]_i_3_n_10\,
      I4 => \xy_reg[89]_i_21_n_15\,
      I5 => \xy_reg[89]_i_13_n_13\,
      O => \xy[83]_i_13_n_0\
    );
\xy[83]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy[83]_i_6_n_0\,
      I1 => \xy_reg[89]_i_13_n_13\,
      I2 => \xy_reg[89]_i_21_n_15\,
      I3 => \xy_reg[75]_i_3_n_10\,
      O => \xy[83]_i_14_n_0\
    );
\xy[83]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy_reg[89]_i_13_n_14\,
      I1 => \xy_reg[75]_i_2_n_8\,
      I2 => \xy_reg[75]_i_3_n_11\,
      I3 => \xy[83]_i_7_n_0\,
      O => \xy[83]_i_15_n_0\
    );
\xy[83]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \xy_reg[89]_i_13_n_15\,
      I1 => \xy_reg[75]_i_2_n_9\,
      I2 => \xy_reg[75]_i_3_n_12\,
      I3 => \xy[83]_i_8_n_0\,
      O => \xy[83]_i_16_n_0\
    );
\xy[83]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \xy_reg[75]_i_3_n_13\,
      I1 => \xy_reg[75]_i_2_n_10\,
      I2 => \xy_reg[75]_i_2_n_11\,
      I3 => \xy_reg[75]_i_3_n_14\,
      O => \xy[83]_i_17_n_0\
    );
\xy[83]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \xy_reg[75]_i_2_n_12\,
      I1 => \xy_reg[75]_i_3_n_15\,
      I2 => \xy_reg[75]_i_2_n_11\,
      I3 => \xy_reg[75]_i_3_n_14\,
      O => \xy[83]_i_18_n_0\
    );
\xy[83]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xy_reg[89]_i_20_n_15\,
      I1 => \xy_reg[89]_i_13_n_10\,
      I2 => \xy_reg[89]_i_21_n_4\,
      O => \xy[83]_i_19_n_0\
    );
\xy[83]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \xy_reg[75]_i_3_n_9\,
      I1 => \xy_reg[89]_i_13_n_12\,
      I2 => \xy_reg[89]_i_21_n_13\,
      I3 => \xy_reg[89]_i_13_n_11\,
      I4 => \xy_reg[75]_i_3_n_8\,
      O => \xy[83]_i_3_n_0\
    );
\xy[83]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \xy_reg[89]_i_21_n_14\,
      I1 => \xy_reg[75]_i_3_n_9\,
      I2 => \xy_reg[89]_i_13_n_12\,
      O => \xy[83]_i_4_n_0\
    );
\xy[83]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \xy_reg[75]_i_3_n_9\,
      I1 => \xy_reg[89]_i_13_n_12\,
      I2 => \xy_reg[89]_i_21_n_14\,
      O => \xy[83]_i_5_n_0\
    );
\xy[83]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xy_reg[89]_i_13_n_14\,
      I1 => \xy_reg[75]_i_2_n_8\,
      I2 => \xy_reg[75]_i_3_n_11\,
      O => \xy[83]_i_6_n_0\
    );
\xy[83]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \xy_reg[89]_i_13_n_15\,
      I1 => \xy_reg[75]_i_2_n_9\,
      I2 => \xy_reg[75]_i_3_n_12\,
      O => \xy[83]_i_7_n_0\
    );
\xy[83]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[75]_i_3_n_13\,
      I1 => \xy_reg[75]_i_2_n_10\,
      O => \xy[83]_i_8_n_0\
    );
\xy[83]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \xy_reg[75]_i_3_n_14\,
      I1 => \xy_reg[75]_i_2_n_11\,
      O => \xy[83]_i_9_n_0\
    );
\xy[84]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(12),
      O => \xy[84]_i_1_n_0\
    );
\xy[85]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(13),
      O => \xy[85]_i_1_n_0\
    );
\xy[86]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(14),
      O => \xy[86]_i_1_n_0\
    );
\xy[87]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__2_n_0\,
      I1 => xy03_in(15),
      O => \xy[87]_i_1_n_0\
    );
\xy[88]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xy03_in(16),
      O => \xy[88]_i_1_n_0\
    );
\xy[89]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => xy03_in(17),
      O => \xy[89]_i_1_n_0\
    );
\xy[89]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \xy[89]_i_5_n_0\,
      I1 => \xy_reg[89]_i_3_n_15\,
      I2 => \xy_reg[89]_i_20_n_4\,
      I3 => \xy_reg[89]_i_13_n_8\,
      I4 => \xy_reg[89]_i_20_n_13\,
      O => \xy[89]_i_10_n_0\
    );
\xy[89]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \xy_reg[89]_i_20_n_14\,
      I1 => \xy_reg[89]_i_13_n_9\,
      I2 => \xy_reg[89]_i_20_n_13\,
      I3 => \xy_reg[89]_i_13_n_8\,
      I4 => \xy[89]_i_6_n_0\,
      O => \xy[89]_i_11_n_0\
    );
\xy[89]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \xy[89]_i_7_n_0\,
      I1 => \xy_reg[89]_i_20_n_15\,
      I2 => \xy_reg[89]_i_21_n_4\,
      I3 => \xy_reg[89]_i_13_n_10\,
      I4 => \xy_reg[89]_i_20_n_14\,
      I5 => \xy_reg[89]_i_13_n_9\,
      O => \xy[89]_i_12_n_0\
    );
\xy[89]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0777"
    )
        port map (
      I0 => \dy_reg_n_0_[44]\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[44]\,
      O => \xy[89]_i_14_n_0\
    );
\xy[89]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08888FFF8FFF8FFF"
    )
        port map (
      I0 => \dy_reg_n_0_[43]\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[44]\,
      I3 => \dx_reg_n_0_[42]\,
      I4 => \dx_reg_n_0_[44]\,
      I5 => \dy_reg_n_0_[42]\,
      O => \xy[89]_i_15_n_0\
    );
\xy[89]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[44]\,
      I1 => \dx_reg_n_0_[41]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[42]\,
      I4 => \dx_reg_n_0_[43]\,
      I5 => \dy_reg_n_0_[42]\,
      O => \xy[89]_i_16_n_0\
    );
\xy[89]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E53F"
    )
        port map (
      I0 => \dy_reg_n_0_[43]\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[44]\,
      I3 => \dx_reg_n_0_[44]\,
      O => \xy[89]_i_17_n_0\
    );
\xy[89]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"70ECE3130F5FAF5F"
    )
        port map (
      I0 => \dy_reg_n_0_[42]\,
      I1 => \dx_reg_n_0_[42]\,
      I2 => \dx_reg_n_0_[44]\,
      I3 => \dy_reg_n_0_[43]\,
      I4 => \dx_reg_n_0_[43]\,
      I5 => \dy_reg_n_0_[44]\,
      O => \xy[89]_i_18_n_0\
    );
\xy[89]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \xy[89]_i_16_n_0\,
      I1 => \dx_reg_n_0_[44]\,
      I2 => \dy_reg_n_0_[42]\,
      I3 => \dy_reg_n_0_[44]\,
      I4 => \dx_reg_n_0_[42]\,
      I5 => \xy[89]_i_37_n_0\,
      O => \xy[89]_i_19_n_0\
    );
\xy[89]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[44]\,
      I1 => \dx_reg_n_0_[40]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[41]\,
      I4 => \dx_reg_n_0_[42]\,
      I5 => \dy_reg_n_0_[42]\,
      O => \xy[89]_i_22_n_0\
    );
\xy[89]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[44]\,
      I1 => \dx_reg_n_0_[39]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[40]\,
      I4 => \dx_reg_n_0_[41]\,
      I5 => \dy_reg_n_0_[42]\,
      O => \xy[89]_i_23_n_0\
    );
\xy[89]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[44]\,
      I1 => \dx_reg_n_0_[38]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[39]\,
      I4 => \dx_reg_n_0_[40]\,
      I5 => \dy_reg_n_0_[42]\,
      O => \xy[89]_i_24_n_0\
    );
\xy[89]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[44]\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[38]\,
      I4 => \dx_reg_n_0_[39]\,
      I5 => \dy_reg_n_0_[42]\,
      O => \xy[89]_i_25_n_0\
    );
\xy[89]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dy_reg_n_0_[42]\,
      I1 => \dx_reg_n_0_[39]\,
      I2 => \dx_reg_n_0_[38]\,
      I3 => \dy_reg_n_0_[43]\,
      I4 => \dx_reg_n_0_[37]\,
      I5 => \dy_reg_n_0_[44]\,
      O => \xy[89]_i_26_n_0\
    );
\xy[89]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[44]\,
      I1 => \dx_reg_n_0_[36]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[37]\,
      O => \xy[89]_i_27_n_0\
    );
\xy[89]_i_28\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[37]\,
      I1 => \dy_reg_n_0_[42]\,
      O => \xy[89]_i_28_n_0\
    );
\xy[89]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[89]_i_22_n_0\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[42]\,
      I3 => \dy_reg_n_0_[44]\,
      I4 => \dx_reg_n_0_[41]\,
      I5 => \xy[89]_i_50_n_0\,
      O => \xy[89]_i_29_n_0\
    );
\xy[89]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[89]_i_23_n_0\,
      I1 => \dx_reg_n_0_[42]\,
      I2 => \dy_reg_n_0_[42]\,
      I3 => \dy_reg_n_0_[44]\,
      I4 => \dx_reg_n_0_[40]\,
      I5 => \xy[89]_i_51_n_0\,
      O => \xy[89]_i_30_n_0\
    );
\xy[89]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[89]_i_24_n_0\,
      I1 => \dx_reg_n_0_[41]\,
      I2 => \dy_reg_n_0_[42]\,
      I3 => \dy_reg_n_0_[44]\,
      I4 => \dx_reg_n_0_[39]\,
      I5 => \xy[89]_i_52_n_0\,
      O => \xy[89]_i_31_n_0\
    );
\xy[89]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[89]_i_25_n_0\,
      I1 => \dx_reg_n_0_[40]\,
      I2 => \dy_reg_n_0_[42]\,
      I3 => \dy_reg_n_0_[44]\,
      I4 => \dx_reg_n_0_[38]\,
      I5 => \xy[89]_i_53_n_0\,
      O => \xy[89]_i_32_n_0\
    );
\xy[89]_i_33\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA6A6A6A"
    )
        port map (
      I0 => \xy[89]_i_26_n_0\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[36]\,
      I4 => \dy_reg_n_0_[44]\,
      O => \xy[89]_i_33_n_0\
    );
\xy[89]_i_34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dx_reg_n_0_[37]\,
      I1 => \dy_reg_n_0_[43]\,
      I2 => \dx_reg_n_0_[36]\,
      I3 => \dy_reg_n_0_[44]\,
      I4 => \dy_reg_n_0_[42]\,
      I5 => \dx_reg_n_0_[38]\,
      O => \xy[89]_i_34_n_0\
    );
\xy[89]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[42]\,
      I1 => \dx_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dx_reg_n_0_[36]\,
      O => \xy[89]_i_35_n_0\
    );
\xy[89]_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[36]\,
      I1 => \dy_reg_n_0_[42]\,
      O => \xy[89]_i_36_n_0\
    );
\xy[89]_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[43]\,
      I1 => \dy_reg_n_0_[43]\,
      O => \xy[89]_i_37_n_0\
    );
\xy[89]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[41]\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[40]\,
      I3 => \dx_reg_n_0_[44]\,
      O => \xy[89]_i_38_n_0\
    );
\xy[89]_i_39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000EAC0EAC0EAC0"
    )
        port map (
      I0 => \dx_reg_n_0_[43]\,
      I1 => \dx_reg_n_0_[42]\,
      I2 => \dy_reg_n_0_[41]\,
      I3 => \dy_reg_n_0_[40]\,
      I4 => \dx_reg_n_0_[44]\,
      I5 => \dy_reg_n_0_[39]\,
      O => \xy[89]_i_39_n_0\
    );
\xy[89]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xy_reg[89]_i_20_n_13\,
      I1 => \xy_reg[89]_i_13_n_8\,
      I2 => \xy_reg[89]_i_20_n_4\,
      I3 => \xy_reg[89]_i_3_n_15\,
      O => \xy[89]_i_4_n_0\
    );
\xy[89]_i_40\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[41]\,
      I1 => \dx_reg_n_0_[41]\,
      I2 => \dy_reg_n_0_[40]\,
      I3 => \dx_reg_n_0_[42]\,
      I4 => \dx_reg_n_0_[43]\,
      I5 => \dy_reg_n_0_[39]\,
      O => \xy[89]_i_40_n_0\
    );
\xy[89]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F3F"
    )
        port map (
      I0 => \dy_reg_n_0_[40]\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[41]\,
      I3 => \dx_reg_n_0_[44]\,
      O => \xy[89]_i_41_n_0\
    );
\xy[89]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"25404FBFF03FCF3F"
    )
        port map (
      I0 => \dy_reg_n_0_[39]\,
      I1 => \dx_reg_n_0_[42]\,
      I2 => \dy_reg_n_0_[41]\,
      I3 => \dx_reg_n_0_[43]\,
      I4 => \dy_reg_n_0_[40]\,
      I5 => \dx_reg_n_0_[44]\,
      O => \xy[89]_i_42_n_0\
    );
\xy[89]_i_43\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[89]_i_40_n_0\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[40]\,
      I3 => \dx_reg_n_0_[42]\,
      I4 => \dy_reg_n_0_[41]\,
      I5 => \xy[89]_i_54_n_0\,
      O => \xy[89]_i_43_n_0\
    );
\xy[89]_i_44\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[38]\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[37]\,
      I3 => \dx_reg_n_0_[44]\,
      O => \xy[89]_i_44_n_0\
    );
\xy[89]_i_45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000EAC0EAC0EAC0"
    )
        port map (
      I0 => \dx_reg_n_0_[43]\,
      I1 => \dx_reg_n_0_[42]\,
      I2 => \dy_reg_n_0_[38]\,
      I3 => \dy_reg_n_0_[37]\,
      I4 => \dx_reg_n_0_[44]\,
      I5 => \dy_reg_n_0_[36]\,
      O => \xy[89]_i_45_n_0\
    );
\xy[89]_i_46\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[38]\,
      I1 => \dx_reg_n_0_[41]\,
      I2 => \dy_reg_n_0_[37]\,
      I3 => \dx_reg_n_0_[42]\,
      I4 => \dx_reg_n_0_[43]\,
      I5 => \dy_reg_n_0_[36]\,
      O => \xy[89]_i_46_n_0\
    );
\xy[89]_i_47\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F3F"
    )
        port map (
      I0 => \dy_reg_n_0_[37]\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[38]\,
      I3 => \dx_reg_n_0_[44]\,
      O => \xy[89]_i_47_n_0\
    );
\xy[89]_i_48\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"25404FBFF03FCF3F"
    )
        port map (
      I0 => \dy_reg_n_0_[36]\,
      I1 => \dx_reg_n_0_[42]\,
      I2 => \dy_reg_n_0_[38]\,
      I3 => \dx_reg_n_0_[43]\,
      I4 => \dy_reg_n_0_[37]\,
      I5 => \dx_reg_n_0_[44]\,
      O => \xy[89]_i_48_n_0\
    );
\xy[89]_i_49\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A6A6A959595"
    )
        port map (
      I0 => \xy[89]_i_46_n_0\,
      I1 => \dx_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[37]\,
      I3 => \dx_reg_n_0_[42]\,
      I4 => \dy_reg_n_0_[38]\,
      I5 => \xy[89]_i_55_n_0\,
      O => \xy[89]_i_49_n_0\
    );
\xy[89]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \xy_reg[89]_i_20_n_14\,
      I1 => \xy_reg[89]_i_13_n_9\,
      I2 => \xy_reg[89]_i_20_n_13\,
      I3 => \xy_reg[89]_i_13_n_8\,
      O => \xy[89]_i_5_n_0\
    );
\xy[89]_i_50\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[42]\,
      I1 => \dy_reg_n_0_[43]\,
      O => \xy[89]_i_50_n_0\
    );
\xy[89]_i_51\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[41]\,
      I1 => \dy_reg_n_0_[43]\,
      O => \xy[89]_i_51_n_0\
    );
\xy[89]_i_52\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[40]\,
      I1 => \dy_reg_n_0_[43]\,
      O => \xy[89]_i_52_n_0\
    );
\xy[89]_i_53\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[39]\,
      I1 => \dy_reg_n_0_[43]\,
      O => \xy[89]_i_53_n_0\
    );
\xy[89]_i_54\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[44]\,
      I1 => \dy_reg_n_0_[39]\,
      O => \xy[89]_i_54_n_0\
    );
\xy[89]_i_55\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dx_reg_n_0_[44]\,
      I1 => \dy_reg_n_0_[36]\,
      O => \xy[89]_i_55_n_0\
    );
\xy[89]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \xy_reg[89]_i_20_n_14\,
      I1 => \xy_reg[89]_i_13_n_9\,
      I2 => \xy_reg[89]_i_20_n_15\,
      I3 => \xy_reg[89]_i_21_n_4\,
      I4 => \xy_reg[89]_i_13_n_10\,
      O => \xy[89]_i_6_n_0\
    );
\xy[89]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \xy_reg[75]_i_3_n_8\,
      I1 => \xy_reg[89]_i_21_n_13\,
      I2 => \xy_reg[89]_i_13_n_11\,
      I3 => \xy_reg[89]_i_21_n_4\,
      I4 => \xy_reg[89]_i_13_n_10\,
      I5 => \xy_reg[89]_i_20_n_15\,
      O => \xy[89]_i_7_n_0\
    );
\xy[89]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \xy_reg[89]_i_3_n_15\,
      I1 => \xy_reg[89]_i_20_n_4\,
      I2 => \xy_reg[89]_i_3_n_14\,
      I3 => \xy_reg[89]_i_3_n_13\,
      O => \xy[89]_i_8_n_0\
    );
\xy[89]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \xy_reg[89]_i_13_n_8\,
      I1 => \xy_reg[89]_i_20_n_13\,
      I2 => \xy_reg[89]_i_3_n_15\,
      I3 => \xy_reg[89]_i_20_n_4\,
      I4 => \xy_reg[89]_i_3_n_14\,
      O => \xy[89]_i_9_n_0\
    );
\xy[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(8),
      O => \xy[8]_i_1_n_0\
    );
\xy[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__1_n_0\,
      I1 => xy0(9),
      O => \xy[9]_i_1_n_0\
    );
\xy_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[0]_i_1_n_0\,
      Q => xy(0)
    );
\xy_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[10]_i_1_n_0\,
      Q => xy(10)
    );
\xy_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[11]_i_1_n_0\,
      Q => xy(11)
    );
\xy_reg[11]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[11]_i_2_n_0\,
      CO(6) => \xy_reg[11]_i_2_n_1\,
      CO(5) => \xy_reg[11]_i_2_n_2\,
      CO(4) => \xy_reg[11]_i_2_n_3\,
      CO(3) => \xy_reg[11]_i_2_n_4\,
      CO(2) => \xy_reg[11]_i_2_n_5\,
      CO(1) => \xy_reg[11]_i_2_n_6\,
      CO(0) => \xy_reg[11]_i_2_n_7\,
      DI(7) => \xy[11]_i_3_n_0\,
      DI(6) => \xy[11]_i_4_n_0\,
      DI(5) => \xy[11]_i_5_n_0\,
      DI(4) => \xy[11]_i_6_n_0\,
      DI(3) => \xy[11]_i_7_n_0\,
      DI(2) => \xy[11]_i_8_n_0\,
      DI(1) => \xy[11]_i_9_n_0\,
      DI(0) => \xy[11]_i_10_n_0\,
      O(7 downto 0) => xy0(11 downto 4),
      S(7) => \xy[11]_i_11_n_0\,
      S(6) => \xy[11]_i_12_n_0\,
      S(5) => \xy[11]_i_13_n_0\,
      S(4) => \xy[11]_i_14_n_0\,
      S(3) => \xy[11]_i_15_n_0\,
      S(2) => \xy[11]_i_16_n_0\,
      S(1) => \xy[11]_i_17_n_0\,
      S(0) => \xy[11]_i_18_n_0\
    );
\xy_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[12]_i_1_n_0\,
      Q => xy(12)
    );
\xy_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[13]_i_1_n_0\,
      Q => xy(13)
    );
\xy_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[14]_i_1_n_0\,
      Q => xy(14)
    );
\xy_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[15]_i_1_n_0\,
      Q => xy(15)
    );
\xy_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[16]_i_1_n_0\,
      Q => xy(16)
    );
\xy_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[17]_i_1_n_0\,
      Q => xy(17)
    );
\xy_reg[17]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[17]_i_13_n_0\,
      CO(6) => \xy_reg[17]_i_13_n_1\,
      CO(5) => \xy_reg[17]_i_13_n_2\,
      CO(4) => \xy_reg[17]_i_13_n_3\,
      CO(3) => \xy_reg[17]_i_13_n_4\,
      CO(2) => \xy_reg[17]_i_13_n_5\,
      CO(1) => \xy_reg[17]_i_13_n_6\,
      CO(0) => \xy_reg[17]_i_13_n_7\,
      DI(7) => \xy[17]_i_22_n_0\,
      DI(6) => \xy[17]_i_23_n_0\,
      DI(5) => \xy[17]_i_24_n_0\,
      DI(4) => \xy[17]_i_25_n_0\,
      DI(3) => \xy[17]_i_26_n_0\,
      DI(2) => \xy[17]_i_27_n_0\,
      DI(1) => \xy[17]_i_28_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[17]_i_13_n_8\,
      O(6) => \xy_reg[17]_i_13_n_9\,
      O(5) => \xy_reg[17]_i_13_n_10\,
      O(4) => \xy_reg[17]_i_13_n_11\,
      O(3) => \xy_reg[17]_i_13_n_12\,
      O(2) => \xy_reg[17]_i_13_n_13\,
      O(1) => \xy_reg[17]_i_13_n_14\,
      O(0) => \xy_reg[17]_i_13_n_15\,
      S(7) => \xy[17]_i_29_n_0\,
      S(6) => \xy[17]_i_30_n_0\,
      S(5) => \xy[17]_i_31_n_0\,
      S(4) => \xy[17]_i_32_n_0\,
      S(3) => \xy[17]_i_33_n_0\,
      S(2) => \xy[17]_i_34_n_0\,
      S(1) => \xy[17]_i_35_n_0\,
      S(0) => \xy[17]_i_36_n_0\
    );
\xy_reg[17]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[11]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_xy_reg[17]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \xy_reg[17]_i_2_n_3\,
      CO(3) => \xy_reg[17]_i_2_n_4\,
      CO(2) => \xy_reg[17]_i_2_n_5\,
      CO(1) => \xy_reg[17]_i_2_n_6\,
      CO(0) => \xy_reg[17]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \xy_reg[17]_i_3_n_13\,
      DI(3) => \xy[17]_i_4_n_0\,
      DI(2) => \xy[17]_i_5_n_0\,
      DI(1) => \xy[17]_i_6_n_0\,
      DI(0) => \xy[17]_i_7_n_0\,
      O(7 downto 6) => \NLW_xy_reg[17]_i_2_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => xy0(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \xy_reg[17]_i_3_n_12\,
      S(4) => \xy[17]_i_8_n_0\,
      S(3) => \xy[17]_i_9_n_0\,
      S(2) => \xy[17]_i_10_n_0\,
      S(1) => \xy[17]_i_11_n_0\,
      S(0) => \xy[17]_i_12_n_0\
    );
\xy_reg[17]_i_20\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[3]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xy_reg[17]_i_20_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xy_reg[17]_i_20_n_4\,
      CO(2) => \NLW_xy_reg[17]_i_20_CO_UNCONNECTED\(2),
      CO(1) => \xy_reg[17]_i_20_n_6\,
      CO(0) => \xy_reg[17]_i_20_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[17]_i_38_n_0\,
      DI(1) => \xy[17]_i_39_n_0\,
      DI(0) => \xy[17]_i_40_n_0\,
      O(7 downto 3) => \NLW_xy_reg[17]_i_20_O_UNCONNECTED\(7 downto 3),
      O(2) => \xy_reg[17]_i_20_n_13\,
      O(1) => \xy_reg[17]_i_20_n_14\,
      O(0) => \xy_reg[17]_i_20_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[17]_i_41_n_0\,
      S(1) => \xy[17]_i_42_n_0\,
      S(0) => \xy[17]_i_43_n_0\
    );
\xy_reg[17]_i_21\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[3]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xy_reg[17]_i_21_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xy_reg[17]_i_21_n_4\,
      CO(2) => \NLW_xy_reg[17]_i_21_CO_UNCONNECTED\(2),
      CO(1) => \xy_reg[17]_i_21_n_6\,
      CO(0) => \xy_reg[17]_i_21_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[17]_i_44_n_0\,
      DI(1) => \xy[17]_i_45_n_0\,
      DI(0) => \xy[17]_i_46_n_0\,
      O(7 downto 3) => \NLW_xy_reg[17]_i_21_O_UNCONNECTED\(7 downto 3),
      O(2) => \xy_reg[17]_i_21_n_13\,
      O(1) => \xy_reg[17]_i_21_n_14\,
      O(0) => \xy_reg[17]_i_21_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[17]_i_47_n_0\,
      S(1) => \xy[17]_i_48_n_0\,
      S(0) => \xy[17]_i_49_n_0\
    );
\xy_reg[17]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[17]_i_13_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xy_reg[17]_i_3_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xy_reg[17]_i_3_n_5\,
      CO(1) => \xy_reg[17]_i_3_n_6\,
      CO(0) => \xy_reg[17]_i_3_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[17]_i_14_n_0\,
      DI(1) => \xy[17]_i_15_n_0\,
      DI(0) => \xy[17]_i_16_n_0\,
      O(7 downto 4) => \NLW_xy_reg[17]_i_3_O_UNCONNECTED\(7 downto 4),
      O(3) => \xy_reg[17]_i_3_n_12\,
      O(2) => \xy_reg[17]_i_3_n_13\,
      O(1) => \xy_reg[17]_i_3_n_14\,
      O(0) => \xy_reg[17]_i_3_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[17]_i_17_n_0\,
      S(1) => \xy[17]_i_18_n_0\,
      S(0) => \xy[17]_i_19_n_0\
    );
\xy_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[18]_i_1_n_0\,
      Q => xy(18)
    );
\xy_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[19]_i_1_n_0\,
      Q => xy(19)
    );
\xy_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[1]_i_1_n_0\,
      Q => xy(1)
    );
\xy_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[20]_i_1_n_0\,
      Q => xy(20)
    );
\xy_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[21]_i_1_n_0\,
      Q => xy(21)
    );
\xy_reg[21]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[21]_i_2_n_0\,
      CO(6) => \xy_reg[21]_i_2_n_1\,
      CO(5) => \xy_reg[21]_i_2_n_2\,
      CO(4) => \xy_reg[21]_i_2_n_3\,
      CO(3) => \xy_reg[21]_i_2_n_4\,
      CO(2) => \xy_reg[21]_i_2_n_5\,
      CO(1) => \xy_reg[21]_i_2_n_6\,
      CO(0) => \xy_reg[21]_i_2_n_7\,
      DI(7) => \xy[21]_i_4_n_0\,
      DI(6) => \xy[21]_i_5_n_0\,
      DI(5) => \xy[21]_i_6_n_0\,
      DI(4) => \xy[21]_i_7_n_0\,
      DI(3) => \xy[21]_i_8_n_0\,
      DI(2) => \xy[21]_i_9_n_0\,
      DI(1) => \xy[21]_i_10_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[21]_i_2_n_8\,
      O(6) => \xy_reg[21]_i_2_n_9\,
      O(5) => \xy_reg[21]_i_2_n_10\,
      O(4) => \xy_reg[21]_i_2_n_11\,
      O(3) => \xy_reg[21]_i_2_n_12\,
      O(2 downto 0) => xy00_in(2 downto 0),
      S(7) => \xy[21]_i_11_n_0\,
      S(6) => \xy[21]_i_12_n_0\,
      S(5) => \xy[21]_i_13_n_0\,
      S(4) => \xy[21]_i_14_n_0\,
      S(3) => \xy[21]_i_15_n_0\,
      S(2) => \xy[21]_i_16_n_0\,
      S(1) => \xy[21]_i_17_n_0\,
      S(0) => \xy[21]_i_18_n_0\
    );
\xy_reg[21]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[21]_i_3_n_0\,
      CO(6) => \xy_reg[21]_i_3_n_1\,
      CO(5) => \xy_reg[21]_i_3_n_2\,
      CO(4) => \xy_reg[21]_i_3_n_3\,
      CO(3) => \xy_reg[21]_i_3_n_4\,
      CO(2) => \xy_reg[21]_i_3_n_5\,
      CO(1) => \xy_reg[21]_i_3_n_6\,
      CO(0) => \xy_reg[21]_i_3_n_7\,
      DI(7) => \xy[21]_i_19_n_0\,
      DI(6) => \xy[21]_i_20_n_0\,
      DI(5) => \xy[21]_i_21_n_0\,
      DI(4) => \xy[21]_i_22_n_0\,
      DI(3) => \xy[21]_i_23_n_0\,
      DI(2) => \xy[21]_i_24_n_0\,
      DI(1) => \xy[21]_i_25_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[21]_i_3_n_8\,
      O(6) => \xy_reg[21]_i_3_n_9\,
      O(5) => \xy_reg[21]_i_3_n_10\,
      O(4) => \xy_reg[21]_i_3_n_11\,
      O(3) => \xy_reg[21]_i_3_n_12\,
      O(2) => \xy_reg[21]_i_3_n_13\,
      O(1) => \xy_reg[21]_i_3_n_14\,
      O(0) => \xy_reg[21]_i_3_n_15\,
      S(7) => \xy[21]_i_26_n_0\,
      S(6) => \xy[21]_i_27_n_0\,
      S(5) => \xy[21]_i_28_n_0\,
      S(4) => \xy[21]_i_29_n_0\,
      S(3) => \xy[21]_i_30_n_0\,
      S(2) => \xy[21]_i_31_n_0\,
      S(1) => \xy[21]_i_32_n_0\,
      S(0) => \xy[21]_i_33_n_0\
    );
\xy_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[22]_i_1_n_0\,
      Q => xy(22)
    );
\xy_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[23]_i_1_n_0\,
      Q => xy(23)
    );
\xy_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[24]_i_1_n_0\,
      Q => xy(24)
    );
\xy_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[25]_i_1_n_0\,
      Q => xy(25)
    );
\xy_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[26]_i_1_n_0\,
      Q => xy(26)
    );
\xy_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[27]_i_1_n_0\,
      Q => xy(27)
    );
\xy_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[28]_i_1_n_0\,
      Q => xy(28)
    );
\xy_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[29]_i_1_n_0\,
      Q => xy(29)
    );
\xy_reg[29]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[29]_i_2_n_0\,
      CO(6) => \xy_reg[29]_i_2_n_1\,
      CO(5) => \xy_reg[29]_i_2_n_2\,
      CO(4) => \xy_reg[29]_i_2_n_3\,
      CO(3) => \xy_reg[29]_i_2_n_4\,
      CO(2) => \xy_reg[29]_i_2_n_5\,
      CO(1) => \xy_reg[29]_i_2_n_6\,
      CO(0) => \xy_reg[29]_i_2_n_7\,
      DI(7) => \xy[29]_i_3_n_0\,
      DI(6) => \xy[29]_i_4_n_0\,
      DI(5) => \xy[29]_i_5_n_0\,
      DI(4) => \xy[29]_i_6_n_0\,
      DI(3) => \xy[29]_i_7_n_0\,
      DI(2) => \xy[29]_i_8_n_0\,
      DI(1) => \xy[29]_i_9_n_0\,
      DI(0) => \xy[29]_i_10_n_0\,
      O(7 downto 0) => xy00_in(11 downto 4),
      S(7) => \xy[29]_i_11_n_0\,
      S(6) => \xy[29]_i_12_n_0\,
      S(5) => \xy[29]_i_13_n_0\,
      S(4) => \xy[29]_i_14_n_0\,
      S(3) => \xy[29]_i_15_n_0\,
      S(2) => \xy[29]_i_16_n_0\,
      S(1) => \xy[29]_i_17_n_0\,
      S(0) => \xy[29]_i_18_n_0\
    );
\xy_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[2]_i_1_n_0\,
      Q => xy(2)
    );
\xy_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[30]_i_1_n_0\,
      Q => xy(30)
    );
\xy_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[31]_i_1_n_0\,
      Q => xy(31)
    );
\xy_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[32]_i_1_n_0\,
      Q => xy(32)
    );
\xy_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[33]_i_1_n_0\,
      Q => xy(33)
    );
\xy_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[34]_i_1_n_0\,
      Q => xy(34)
    );
\xy_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[35]_i_1_n_0\,
      Q => xy(35)
    );
\xy_reg[35]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[35]_i_13_n_0\,
      CO(6) => \xy_reg[35]_i_13_n_1\,
      CO(5) => \xy_reg[35]_i_13_n_2\,
      CO(4) => \xy_reg[35]_i_13_n_3\,
      CO(3) => \xy_reg[35]_i_13_n_4\,
      CO(2) => \xy_reg[35]_i_13_n_5\,
      CO(1) => \xy_reg[35]_i_13_n_6\,
      CO(0) => \xy_reg[35]_i_13_n_7\,
      DI(7) => \xy[35]_i_22_n_0\,
      DI(6) => \xy[35]_i_23_n_0\,
      DI(5) => \xy[35]_i_24_n_0\,
      DI(4) => \xy[35]_i_25_n_0\,
      DI(3) => \xy[35]_i_26_n_0\,
      DI(2) => \xy[35]_i_27_n_0\,
      DI(1) => \xy[35]_i_28_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[35]_i_13_n_8\,
      O(6) => \xy_reg[35]_i_13_n_9\,
      O(5) => \xy_reg[35]_i_13_n_10\,
      O(4) => \xy_reg[35]_i_13_n_11\,
      O(3) => \xy_reg[35]_i_13_n_12\,
      O(2) => \xy_reg[35]_i_13_n_13\,
      O(1) => \xy_reg[35]_i_13_n_14\,
      O(0) => \xy_reg[35]_i_13_n_15\,
      S(7) => \xy[35]_i_29_n_0\,
      S(6) => \xy[35]_i_30_n_0\,
      S(5) => \xy[35]_i_31_n_0\,
      S(4) => \xy[35]_i_32_n_0\,
      S(3) => \xy[35]_i_33_n_0\,
      S(2) => \xy[35]_i_34_n_0\,
      S(1) => \xy[35]_i_35_n_0\,
      S(0) => \xy[35]_i_36_n_0\
    );
\xy_reg[35]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[29]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_xy_reg[35]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \xy_reg[35]_i_2_n_3\,
      CO(3) => \xy_reg[35]_i_2_n_4\,
      CO(2) => \xy_reg[35]_i_2_n_5\,
      CO(1) => \xy_reg[35]_i_2_n_6\,
      CO(0) => \xy_reg[35]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \xy_reg[35]_i_3_n_13\,
      DI(3) => \xy[35]_i_4_n_0\,
      DI(2) => \xy[35]_i_5_n_0\,
      DI(1) => \xy[35]_i_6_n_0\,
      DI(0) => \xy[35]_i_7_n_0\,
      O(7 downto 6) => \NLW_xy_reg[35]_i_2_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => xy00_in(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \xy_reg[35]_i_3_n_12\,
      S(4) => \xy[35]_i_8_n_0\,
      S(3) => \xy[35]_i_9_n_0\,
      S(2) => \xy[35]_i_10_n_0\,
      S(1) => \xy[35]_i_11_n_0\,
      S(0) => \xy[35]_i_12_n_0\
    );
\xy_reg[35]_i_20\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[21]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xy_reg[35]_i_20_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xy_reg[35]_i_20_n_4\,
      CO(2) => \NLW_xy_reg[35]_i_20_CO_UNCONNECTED\(2),
      CO(1) => \xy_reg[35]_i_20_n_6\,
      CO(0) => \xy_reg[35]_i_20_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[35]_i_38_n_0\,
      DI(1) => \xy[35]_i_39_n_0\,
      DI(0) => \xy[35]_i_40_n_0\,
      O(7 downto 3) => \NLW_xy_reg[35]_i_20_O_UNCONNECTED\(7 downto 3),
      O(2) => \xy_reg[35]_i_20_n_13\,
      O(1) => \xy_reg[35]_i_20_n_14\,
      O(0) => \xy_reg[35]_i_20_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[35]_i_41_n_0\,
      S(1) => \xy[35]_i_42_n_0\,
      S(0) => \xy[35]_i_43_n_0\
    );
\xy_reg[35]_i_21\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[21]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xy_reg[35]_i_21_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xy_reg[35]_i_21_n_4\,
      CO(2) => \NLW_xy_reg[35]_i_21_CO_UNCONNECTED\(2),
      CO(1) => \xy_reg[35]_i_21_n_6\,
      CO(0) => \xy_reg[35]_i_21_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[35]_i_44_n_0\,
      DI(1) => \xy[35]_i_45_n_0\,
      DI(0) => \xy[35]_i_46_n_0\,
      O(7 downto 3) => \NLW_xy_reg[35]_i_21_O_UNCONNECTED\(7 downto 3),
      O(2) => \xy_reg[35]_i_21_n_13\,
      O(1) => \xy_reg[35]_i_21_n_14\,
      O(0) => \xy_reg[35]_i_21_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[35]_i_47_n_0\,
      S(1) => \xy[35]_i_48_n_0\,
      S(0) => \xy[35]_i_49_n_0\
    );
\xy_reg[35]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[35]_i_13_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xy_reg[35]_i_3_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xy_reg[35]_i_3_n_5\,
      CO(1) => \xy_reg[35]_i_3_n_6\,
      CO(0) => \xy_reg[35]_i_3_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[35]_i_14_n_0\,
      DI(1) => \xy[35]_i_15_n_0\,
      DI(0) => \xy[35]_i_16_n_0\,
      O(7 downto 4) => \NLW_xy_reg[35]_i_3_O_UNCONNECTED\(7 downto 4),
      O(3) => \xy_reg[35]_i_3_n_12\,
      O(2) => \xy_reg[35]_i_3_n_13\,
      O(1) => \xy_reg[35]_i_3_n_14\,
      O(0) => \xy_reg[35]_i_3_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[35]_i_17_n_0\,
      S(1) => \xy[35]_i_18_n_0\,
      S(0) => \xy[35]_i_19_n_0\
    );
\xy_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[36]_i_1_n_0\,
      Q => xy(36)
    );
\xy_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[37]_i_1_n_0\,
      Q => xy(37)
    );
\xy_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[38]_i_1_n_0\,
      Q => xy(38)
    );
\xy_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[39]_i_1_n_0\,
      Q => xy(39)
    );
\xy_reg[39]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[39]_i_2_n_0\,
      CO(6) => \xy_reg[39]_i_2_n_1\,
      CO(5) => \xy_reg[39]_i_2_n_2\,
      CO(4) => \xy_reg[39]_i_2_n_3\,
      CO(3) => \xy_reg[39]_i_2_n_4\,
      CO(2) => \xy_reg[39]_i_2_n_5\,
      CO(1) => \xy_reg[39]_i_2_n_6\,
      CO(0) => \xy_reg[39]_i_2_n_7\,
      DI(7) => \xy[39]_i_4_n_0\,
      DI(6) => \xy[39]_i_5_n_0\,
      DI(5) => \xy[39]_i_6_n_0\,
      DI(4) => \xy[39]_i_7_n_0\,
      DI(3) => \xy[39]_i_8_n_0\,
      DI(2) => \xy[39]_i_9_n_0\,
      DI(1) => \xy[39]_i_10_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[39]_i_2_n_8\,
      O(6) => \xy_reg[39]_i_2_n_9\,
      O(5) => \xy_reg[39]_i_2_n_10\,
      O(4) => \xy_reg[39]_i_2_n_11\,
      O(3) => \xy_reg[39]_i_2_n_12\,
      O(2 downto 0) => xy01_in(2 downto 0),
      S(7) => \xy[39]_i_11_n_0\,
      S(6) => \xy[39]_i_12_n_0\,
      S(5) => \xy[39]_i_13_n_0\,
      S(4) => \xy[39]_i_14_n_0\,
      S(3) => \xy[39]_i_15_n_0\,
      S(2) => \xy[39]_i_16_n_0\,
      S(1) => \xy[39]_i_17_n_0\,
      S(0) => \xy[39]_i_18_n_0\
    );
\xy_reg[39]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[39]_i_3_n_0\,
      CO(6) => \xy_reg[39]_i_3_n_1\,
      CO(5) => \xy_reg[39]_i_3_n_2\,
      CO(4) => \xy_reg[39]_i_3_n_3\,
      CO(3) => \xy_reg[39]_i_3_n_4\,
      CO(2) => \xy_reg[39]_i_3_n_5\,
      CO(1) => \xy_reg[39]_i_3_n_6\,
      CO(0) => \xy_reg[39]_i_3_n_7\,
      DI(7) => \xy[39]_i_19_n_0\,
      DI(6) => \xy[39]_i_20_n_0\,
      DI(5) => \xy[39]_i_21_n_0\,
      DI(4) => \xy[39]_i_22_n_0\,
      DI(3) => \xy[39]_i_23_n_0\,
      DI(2) => \xy[39]_i_24_n_0\,
      DI(1) => \xy[39]_i_25_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[39]_i_3_n_8\,
      O(6) => \xy_reg[39]_i_3_n_9\,
      O(5) => \xy_reg[39]_i_3_n_10\,
      O(4) => \xy_reg[39]_i_3_n_11\,
      O(3) => \xy_reg[39]_i_3_n_12\,
      O(2) => \xy_reg[39]_i_3_n_13\,
      O(1) => \xy_reg[39]_i_3_n_14\,
      O(0) => \xy_reg[39]_i_3_n_15\,
      S(7) => \xy[39]_i_26_n_0\,
      S(6) => \xy[39]_i_27_n_0\,
      S(5) => \xy[39]_i_28_n_0\,
      S(4) => \xy[39]_i_29_n_0\,
      S(3) => \xy[39]_i_30_n_0\,
      S(2) => \xy[39]_i_31_n_0\,
      S(1) => \xy[39]_i_32_n_0\,
      S(0) => \xy[39]_i_33_n_0\
    );
\xy_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[3]_i_1_n_0\,
      Q => xy(3)
    );
\xy_reg[3]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[3]_i_2_n_0\,
      CO(6) => \xy_reg[3]_i_2_n_1\,
      CO(5) => \xy_reg[3]_i_2_n_2\,
      CO(4) => \xy_reg[3]_i_2_n_3\,
      CO(3) => \xy_reg[3]_i_2_n_4\,
      CO(2) => \xy_reg[3]_i_2_n_5\,
      CO(1) => \xy_reg[3]_i_2_n_6\,
      CO(0) => \xy_reg[3]_i_2_n_7\,
      DI(7) => \xy[3]_i_4_n_0\,
      DI(6) => \xy[3]_i_5_n_0\,
      DI(5) => \xy[3]_i_6_n_0\,
      DI(4) => \xy[3]_i_7_n_0\,
      DI(3) => \xy[3]_i_8_n_0\,
      DI(2) => \xy[3]_i_9_n_0\,
      DI(1) => \xy[3]_i_10_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[3]_i_2_n_8\,
      O(6) => \xy_reg[3]_i_2_n_9\,
      O(5) => \xy_reg[3]_i_2_n_10\,
      O(4) => \xy_reg[3]_i_2_n_11\,
      O(3) => \xy_reg[3]_i_2_n_12\,
      O(2 downto 0) => xy0(2 downto 0),
      S(7) => \xy[3]_i_11_n_0\,
      S(6) => \xy[3]_i_12_n_0\,
      S(5) => \xy[3]_i_13_n_0\,
      S(4) => \xy[3]_i_14_n_0\,
      S(3) => \xy[3]_i_15_n_0\,
      S(2) => \xy[3]_i_16_n_0\,
      S(1) => \xy[3]_i_17_n_0\,
      S(0) => \xy[3]_i_18_n_0\
    );
\xy_reg[3]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[3]_i_3_n_0\,
      CO(6) => \xy_reg[3]_i_3_n_1\,
      CO(5) => \xy_reg[3]_i_3_n_2\,
      CO(4) => \xy_reg[3]_i_3_n_3\,
      CO(3) => \xy_reg[3]_i_3_n_4\,
      CO(2) => \xy_reg[3]_i_3_n_5\,
      CO(1) => \xy_reg[3]_i_3_n_6\,
      CO(0) => \xy_reg[3]_i_3_n_7\,
      DI(7) => \xy[3]_i_19_n_0\,
      DI(6) => \xy[3]_i_20_n_0\,
      DI(5) => \xy[3]_i_21_n_0\,
      DI(4) => \xy[3]_i_22_n_0\,
      DI(3) => \xy[3]_i_23_n_0\,
      DI(2) => \xy[3]_i_24_n_0\,
      DI(1) => \xy[3]_i_25_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[3]_i_3_n_8\,
      O(6) => \xy_reg[3]_i_3_n_9\,
      O(5) => \xy_reg[3]_i_3_n_10\,
      O(4) => \xy_reg[3]_i_3_n_11\,
      O(3) => \xy_reg[3]_i_3_n_12\,
      O(2) => \xy_reg[3]_i_3_n_13\,
      O(1) => \xy_reg[3]_i_3_n_14\,
      O(0) => \xy_reg[3]_i_3_n_15\,
      S(7) => \xy[3]_i_26_n_0\,
      S(6) => \xy[3]_i_27_n_0\,
      S(5) => \xy[3]_i_28_n_0\,
      S(4) => \xy[3]_i_29_n_0\,
      S(3) => \xy[3]_i_30_n_0\,
      S(2) => \xy[3]_i_31_n_0\,
      S(1) => \xy[3]_i_32_n_0\,
      S(0) => \xy[3]_i_33_n_0\
    );
\xy_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[40]_i_1_n_0\,
      Q => xy(40)
    );
\xy_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[41]_i_1_n_0\,
      Q => xy(41)
    );
\xy_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[42]_i_1_n_0\,
      Q => xy(42)
    );
\xy_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[43]_i_1_n_0\,
      Q => xy(43)
    );
\xy_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[44]_i_1_n_0\,
      Q => xy(44)
    );
\xy_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[45]_i_1_n_0\,
      Q => xy(45)
    );
\xy_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[46]_i_1_n_0\,
      Q => xy(46)
    );
\xy_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[47]_i_1_n_0\,
      Q => xy(47)
    );
\xy_reg[47]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[47]_i_2_n_0\,
      CO(6) => \xy_reg[47]_i_2_n_1\,
      CO(5) => \xy_reg[47]_i_2_n_2\,
      CO(4) => \xy_reg[47]_i_2_n_3\,
      CO(3) => \xy_reg[47]_i_2_n_4\,
      CO(2) => \xy_reg[47]_i_2_n_5\,
      CO(1) => \xy_reg[47]_i_2_n_6\,
      CO(0) => \xy_reg[47]_i_2_n_7\,
      DI(7) => \xy[47]_i_3_n_0\,
      DI(6) => \xy[47]_i_4_n_0\,
      DI(5) => \xy[47]_i_5_n_0\,
      DI(4) => \xy[47]_i_6_n_0\,
      DI(3) => \xy[47]_i_7_n_0\,
      DI(2) => \xy[47]_i_8_n_0\,
      DI(1) => \xy[47]_i_9_n_0\,
      DI(0) => \xy[47]_i_10_n_0\,
      O(7 downto 0) => xy01_in(11 downto 4),
      S(7) => \xy[47]_i_11_n_0\,
      S(6) => \xy[47]_i_12_n_0\,
      S(5) => \xy[47]_i_13_n_0\,
      S(4) => \xy[47]_i_14_n_0\,
      S(3) => \xy[47]_i_15_n_0\,
      S(2) => \xy[47]_i_16_n_0\,
      S(1) => \xy[47]_i_17_n_0\,
      S(0) => \xy[47]_i_18_n_0\
    );
\xy_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[48]_i_1_n_0\,
      Q => xy(48)
    );
\xy_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[49]_i_1_n_0\,
      Q => xy(49)
    );
\xy_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[4]_i_1_n_0\,
      Q => xy(4)
    );
\xy_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[50]_i_1_n_0\,
      Q => xy(50)
    );
\xy_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[51]_i_1_n_0\,
      Q => xy(51)
    );
\xy_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[52]_i_1_n_0\,
      Q => xy(52)
    );
\xy_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[53]_i_1_n_0\,
      Q => xy(53)
    );
\xy_reg[53]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[53]_i_13_n_0\,
      CO(6) => \xy_reg[53]_i_13_n_1\,
      CO(5) => \xy_reg[53]_i_13_n_2\,
      CO(4) => \xy_reg[53]_i_13_n_3\,
      CO(3) => \xy_reg[53]_i_13_n_4\,
      CO(2) => \xy_reg[53]_i_13_n_5\,
      CO(1) => \xy_reg[53]_i_13_n_6\,
      CO(0) => \xy_reg[53]_i_13_n_7\,
      DI(7) => \xy[53]_i_22_n_0\,
      DI(6) => \xy[53]_i_23_n_0\,
      DI(5) => \xy[53]_i_24_n_0\,
      DI(4) => \xy[53]_i_25_n_0\,
      DI(3) => \xy[53]_i_26_n_0\,
      DI(2) => \xy[53]_i_27_n_0\,
      DI(1) => \xy[53]_i_28_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[53]_i_13_n_8\,
      O(6) => \xy_reg[53]_i_13_n_9\,
      O(5) => \xy_reg[53]_i_13_n_10\,
      O(4) => \xy_reg[53]_i_13_n_11\,
      O(3) => \xy_reg[53]_i_13_n_12\,
      O(2) => \xy_reg[53]_i_13_n_13\,
      O(1) => \xy_reg[53]_i_13_n_14\,
      O(0) => \xy_reg[53]_i_13_n_15\,
      S(7) => \xy[53]_i_29_n_0\,
      S(6) => \xy[53]_i_30_n_0\,
      S(5) => \xy[53]_i_31_n_0\,
      S(4) => \xy[53]_i_32_n_0\,
      S(3) => \xy[53]_i_33_n_0\,
      S(2) => \xy[53]_i_34_n_0\,
      S(1) => \xy[53]_i_35_n_0\,
      S(0) => \xy[53]_i_36_n_0\
    );
\xy_reg[53]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[47]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_xy_reg[53]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \xy_reg[53]_i_2_n_3\,
      CO(3) => \xy_reg[53]_i_2_n_4\,
      CO(2) => \xy_reg[53]_i_2_n_5\,
      CO(1) => \xy_reg[53]_i_2_n_6\,
      CO(0) => \xy_reg[53]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \xy_reg[53]_i_3_n_13\,
      DI(3) => \xy[53]_i_4_n_0\,
      DI(2) => \xy[53]_i_5_n_0\,
      DI(1) => \xy[53]_i_6_n_0\,
      DI(0) => \xy[53]_i_7_n_0\,
      O(7 downto 6) => \NLW_xy_reg[53]_i_2_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => xy01_in(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \xy_reg[53]_i_3_n_12\,
      S(4) => \xy[53]_i_8_n_0\,
      S(3) => \xy[53]_i_9_n_0\,
      S(2) => \xy[53]_i_10_n_0\,
      S(1) => \xy[53]_i_11_n_0\,
      S(0) => \xy[53]_i_12_n_0\
    );
\xy_reg[53]_i_20\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[39]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xy_reg[53]_i_20_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xy_reg[53]_i_20_n_4\,
      CO(2) => \NLW_xy_reg[53]_i_20_CO_UNCONNECTED\(2),
      CO(1) => \xy_reg[53]_i_20_n_6\,
      CO(0) => \xy_reg[53]_i_20_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[53]_i_38_n_0\,
      DI(1) => \xy[53]_i_39_n_0\,
      DI(0) => \xy[53]_i_40_n_0\,
      O(7 downto 3) => \NLW_xy_reg[53]_i_20_O_UNCONNECTED\(7 downto 3),
      O(2) => \xy_reg[53]_i_20_n_13\,
      O(1) => \xy_reg[53]_i_20_n_14\,
      O(0) => \xy_reg[53]_i_20_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[53]_i_41_n_0\,
      S(1) => \xy[53]_i_42_n_0\,
      S(0) => \xy[53]_i_43_n_0\
    );
\xy_reg[53]_i_21\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[39]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xy_reg[53]_i_21_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xy_reg[53]_i_21_n_4\,
      CO(2) => \NLW_xy_reg[53]_i_21_CO_UNCONNECTED\(2),
      CO(1) => \xy_reg[53]_i_21_n_6\,
      CO(0) => \xy_reg[53]_i_21_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[53]_i_44_n_0\,
      DI(1) => \xy[53]_i_45_n_0\,
      DI(0) => \xy[53]_i_46_n_0\,
      O(7 downto 3) => \NLW_xy_reg[53]_i_21_O_UNCONNECTED\(7 downto 3),
      O(2) => \xy_reg[53]_i_21_n_13\,
      O(1) => \xy_reg[53]_i_21_n_14\,
      O(0) => \xy_reg[53]_i_21_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[53]_i_47_n_0\,
      S(1) => \xy[53]_i_48_n_0\,
      S(0) => \xy[53]_i_49_n_0\
    );
\xy_reg[53]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[53]_i_13_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xy_reg[53]_i_3_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xy_reg[53]_i_3_n_5\,
      CO(1) => \xy_reg[53]_i_3_n_6\,
      CO(0) => \xy_reg[53]_i_3_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[53]_i_14_n_0\,
      DI(1) => \xy[53]_i_15_n_0\,
      DI(0) => \xy[53]_i_16_n_0\,
      O(7 downto 4) => \NLW_xy_reg[53]_i_3_O_UNCONNECTED\(7 downto 4),
      O(3) => \xy_reg[53]_i_3_n_12\,
      O(2) => \xy_reg[53]_i_3_n_13\,
      O(1) => \xy_reg[53]_i_3_n_14\,
      O(0) => \xy_reg[53]_i_3_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[53]_i_17_n_0\,
      S(1) => \xy[53]_i_18_n_0\,
      S(0) => \xy[53]_i_19_n_0\
    );
\xy_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[54]_i_1_n_0\,
      Q => xy(54)
    );
\xy_reg[55]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[55]_i_1_n_0\,
      Q => xy(55)
    );
\xy_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[56]_i_1_n_0\,
      Q => xy(56)
    );
\xy_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[57]_i_1_n_0\,
      Q => xy(57)
    );
\xy_reg[57]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[57]_i_2_n_0\,
      CO(6) => \xy_reg[57]_i_2_n_1\,
      CO(5) => \xy_reg[57]_i_2_n_2\,
      CO(4) => \xy_reg[57]_i_2_n_3\,
      CO(3) => \xy_reg[57]_i_2_n_4\,
      CO(2) => \xy_reg[57]_i_2_n_5\,
      CO(1) => \xy_reg[57]_i_2_n_6\,
      CO(0) => \xy_reg[57]_i_2_n_7\,
      DI(7) => \xy[57]_i_4_n_0\,
      DI(6) => \xy[57]_i_5_n_0\,
      DI(5) => \xy[57]_i_6_n_0\,
      DI(4) => \xy[57]_i_7_n_0\,
      DI(3) => \xy[57]_i_8_n_0\,
      DI(2) => \xy[57]_i_9_n_0\,
      DI(1) => \xy[57]_i_10_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[57]_i_2_n_8\,
      O(6) => \xy_reg[57]_i_2_n_9\,
      O(5) => \xy_reg[57]_i_2_n_10\,
      O(4) => \xy_reg[57]_i_2_n_11\,
      O(3) => \xy_reg[57]_i_2_n_12\,
      O(2 downto 0) => xy02_in(2 downto 0),
      S(7) => \xy[57]_i_11_n_0\,
      S(6) => \xy[57]_i_12_n_0\,
      S(5) => \xy[57]_i_13_n_0\,
      S(4) => \xy[57]_i_14_n_0\,
      S(3) => \xy[57]_i_15_n_0\,
      S(2) => \xy[57]_i_16_n_0\,
      S(1) => \xy[57]_i_17_n_0\,
      S(0) => \xy[57]_i_18_n_0\
    );
\xy_reg[57]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[57]_i_3_n_0\,
      CO(6) => \xy_reg[57]_i_3_n_1\,
      CO(5) => \xy_reg[57]_i_3_n_2\,
      CO(4) => \xy_reg[57]_i_3_n_3\,
      CO(3) => \xy_reg[57]_i_3_n_4\,
      CO(2) => \xy_reg[57]_i_3_n_5\,
      CO(1) => \xy_reg[57]_i_3_n_6\,
      CO(0) => \xy_reg[57]_i_3_n_7\,
      DI(7) => \xy[57]_i_19_n_0\,
      DI(6) => \xy[57]_i_20_n_0\,
      DI(5) => \xy[57]_i_21_n_0\,
      DI(4) => \xy[57]_i_22_n_0\,
      DI(3) => \xy[57]_i_23_n_0\,
      DI(2) => \xy[57]_i_24_n_0\,
      DI(1) => \xy[57]_i_25_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[57]_i_3_n_8\,
      O(6) => \xy_reg[57]_i_3_n_9\,
      O(5) => \xy_reg[57]_i_3_n_10\,
      O(4) => \xy_reg[57]_i_3_n_11\,
      O(3) => \xy_reg[57]_i_3_n_12\,
      O(2) => \xy_reg[57]_i_3_n_13\,
      O(1) => \xy_reg[57]_i_3_n_14\,
      O(0) => \xy_reg[57]_i_3_n_15\,
      S(7) => \xy[57]_i_26_n_0\,
      S(6) => \xy[57]_i_27_n_0\,
      S(5) => \xy[57]_i_28_n_0\,
      S(4) => \xy[57]_i_29_n_0\,
      S(3) => \xy[57]_i_30_n_0\,
      S(2) => \xy[57]_i_31_n_0\,
      S(1) => \xy[57]_i_32_n_0\,
      S(0) => \xy[57]_i_33_n_0\
    );
\xy_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[58]_i_1_n_0\,
      Q => xy(58)
    );
\xy_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[59]_i_1_n_0\,
      Q => xy(59)
    );
\xy_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[5]_i_1_n_0\,
      Q => xy(5)
    );
\xy_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[60]_i_1_n_0\,
      Q => xy(60)
    );
\xy_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[61]_i_1_n_0\,
      Q => xy(61)
    );
\xy_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[62]_i_1_n_0\,
      Q => xy(62)
    );
\xy_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[63]_i_1_n_0\,
      Q => xy(63)
    );
\xy_reg[64]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[64]_i_1_n_0\,
      Q => xy(64)
    );
\xy_reg[65]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[65]_i_1_n_0\,
      Q => xy(65)
    );
\xy_reg[65]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[65]_i_2_n_0\,
      CO(6) => \xy_reg[65]_i_2_n_1\,
      CO(5) => \xy_reg[65]_i_2_n_2\,
      CO(4) => \xy_reg[65]_i_2_n_3\,
      CO(3) => \xy_reg[65]_i_2_n_4\,
      CO(2) => \xy_reg[65]_i_2_n_5\,
      CO(1) => \xy_reg[65]_i_2_n_6\,
      CO(0) => \xy_reg[65]_i_2_n_7\,
      DI(7) => \xy[65]_i_3_n_0\,
      DI(6) => \xy[65]_i_4_n_0\,
      DI(5) => \xy[65]_i_5_n_0\,
      DI(4) => \xy[65]_i_6_n_0\,
      DI(3) => \xy[65]_i_7_n_0\,
      DI(2) => \xy[65]_i_8_n_0\,
      DI(1) => \xy[65]_i_9_n_0\,
      DI(0) => \xy[65]_i_10_n_0\,
      O(7 downto 0) => xy02_in(11 downto 4),
      S(7) => \xy[65]_i_11_n_0\,
      S(6) => \xy[65]_i_12_n_0\,
      S(5) => \xy[65]_i_13_n_0\,
      S(4) => \xy[65]_i_14_n_0\,
      S(3) => \xy[65]_i_15_n_0\,
      S(2) => \xy[65]_i_16_n_0\,
      S(1) => \xy[65]_i_17_n_0\,
      S(0) => \xy[65]_i_18_n_0\
    );
\xy_reg[66]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[66]_i_1_n_0\,
      Q => xy(66)
    );
\xy_reg[67]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[67]_i_1_n_0\,
      Q => xy(67)
    );
\xy_reg[68]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[68]_i_1_n_0\,
      Q => xy(68)
    );
\xy_reg[69]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[69]_i_1_n_0\,
      Q => xy(69)
    );
\xy_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[6]_i_1_n_0\,
      Q => xy(6)
    );
\xy_reg[70]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[70]_i_1_n_0\,
      Q => xy(70)
    );
\xy_reg[71]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[71]_i_1_n_0\,
      Q => xy(71)
    );
\xy_reg[71]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[71]_i_13_n_0\,
      CO(6) => \xy_reg[71]_i_13_n_1\,
      CO(5) => \xy_reg[71]_i_13_n_2\,
      CO(4) => \xy_reg[71]_i_13_n_3\,
      CO(3) => \xy_reg[71]_i_13_n_4\,
      CO(2) => \xy_reg[71]_i_13_n_5\,
      CO(1) => \xy_reg[71]_i_13_n_6\,
      CO(0) => \xy_reg[71]_i_13_n_7\,
      DI(7) => \xy[71]_i_22_n_0\,
      DI(6) => \xy[71]_i_23_n_0\,
      DI(5) => \xy[71]_i_24_n_0\,
      DI(4) => \xy[71]_i_25_n_0\,
      DI(3) => \xy[71]_i_26_n_0\,
      DI(2) => \xy[71]_i_27_n_0\,
      DI(1) => \xy[71]_i_28_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[71]_i_13_n_8\,
      O(6) => \xy_reg[71]_i_13_n_9\,
      O(5) => \xy_reg[71]_i_13_n_10\,
      O(4) => \xy_reg[71]_i_13_n_11\,
      O(3) => \xy_reg[71]_i_13_n_12\,
      O(2) => \xy_reg[71]_i_13_n_13\,
      O(1) => \xy_reg[71]_i_13_n_14\,
      O(0) => \xy_reg[71]_i_13_n_15\,
      S(7) => \xy[71]_i_29_n_0\,
      S(6) => \xy[71]_i_30_n_0\,
      S(5) => \xy[71]_i_31_n_0\,
      S(4) => \xy[71]_i_32_n_0\,
      S(3) => \xy[71]_i_33_n_0\,
      S(2) => \xy[71]_i_34_n_0\,
      S(1) => \xy[71]_i_35_n_0\,
      S(0) => \xy[71]_i_36_n_0\
    );
\xy_reg[71]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[65]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_xy_reg[71]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \xy_reg[71]_i_2_n_3\,
      CO(3) => \xy_reg[71]_i_2_n_4\,
      CO(2) => \xy_reg[71]_i_2_n_5\,
      CO(1) => \xy_reg[71]_i_2_n_6\,
      CO(0) => \xy_reg[71]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \xy_reg[71]_i_3_n_13\,
      DI(3) => \xy[71]_i_4_n_0\,
      DI(2) => \xy[71]_i_5_n_0\,
      DI(1) => \xy[71]_i_6_n_0\,
      DI(0) => \xy[71]_i_7_n_0\,
      O(7 downto 6) => \NLW_xy_reg[71]_i_2_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => xy02_in(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \xy_reg[71]_i_3_n_12\,
      S(4) => \xy[71]_i_8_n_0\,
      S(3) => \xy[71]_i_9_n_0\,
      S(2) => \xy[71]_i_10_n_0\,
      S(1) => \xy[71]_i_11_n_0\,
      S(0) => \xy[71]_i_12_n_0\
    );
\xy_reg[71]_i_20\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[57]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xy_reg[71]_i_20_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xy_reg[71]_i_20_n_4\,
      CO(2) => \NLW_xy_reg[71]_i_20_CO_UNCONNECTED\(2),
      CO(1) => \xy_reg[71]_i_20_n_6\,
      CO(0) => \xy_reg[71]_i_20_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[71]_i_38_n_0\,
      DI(1) => \xy[71]_i_39_n_0\,
      DI(0) => \xy[71]_i_40_n_0\,
      O(7 downto 3) => \NLW_xy_reg[71]_i_20_O_UNCONNECTED\(7 downto 3),
      O(2) => \xy_reg[71]_i_20_n_13\,
      O(1) => \xy_reg[71]_i_20_n_14\,
      O(0) => \xy_reg[71]_i_20_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[71]_i_41_n_0\,
      S(1) => \xy[71]_i_42_n_0\,
      S(0) => \xy[71]_i_43_n_0\
    );
\xy_reg[71]_i_21\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[57]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xy_reg[71]_i_21_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xy_reg[71]_i_21_n_4\,
      CO(2) => \NLW_xy_reg[71]_i_21_CO_UNCONNECTED\(2),
      CO(1) => \xy_reg[71]_i_21_n_6\,
      CO(0) => \xy_reg[71]_i_21_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[71]_i_44_n_0\,
      DI(1) => \xy[71]_i_45_n_0\,
      DI(0) => \xy[71]_i_46_n_0\,
      O(7 downto 3) => \NLW_xy_reg[71]_i_21_O_UNCONNECTED\(7 downto 3),
      O(2) => \xy_reg[71]_i_21_n_13\,
      O(1) => \xy_reg[71]_i_21_n_14\,
      O(0) => \xy_reg[71]_i_21_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[71]_i_47_n_0\,
      S(1) => \xy[71]_i_48_n_0\,
      S(0) => \xy[71]_i_49_n_0\
    );
\xy_reg[71]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[71]_i_13_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xy_reg[71]_i_3_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xy_reg[71]_i_3_n_5\,
      CO(1) => \xy_reg[71]_i_3_n_6\,
      CO(0) => \xy_reg[71]_i_3_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[71]_i_14_n_0\,
      DI(1) => \xy[71]_i_15_n_0\,
      DI(0) => \xy[71]_i_16_n_0\,
      O(7 downto 4) => \NLW_xy_reg[71]_i_3_O_UNCONNECTED\(7 downto 4),
      O(3) => \xy_reg[71]_i_3_n_12\,
      O(2) => \xy_reg[71]_i_3_n_13\,
      O(1) => \xy_reg[71]_i_3_n_14\,
      O(0) => \xy_reg[71]_i_3_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[71]_i_17_n_0\,
      S(1) => \xy[71]_i_18_n_0\,
      S(0) => \xy[71]_i_19_n_0\
    );
\xy_reg[72]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[72]_i_1_n_0\,
      Q => xy(72)
    );
\xy_reg[73]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[73]_i_1_n_0\,
      Q => xy(73)
    );
\xy_reg[74]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[74]_i_1_n_0\,
      Q => xy(74)
    );
\xy_reg[75]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[75]_i_1_n_0\,
      Q => xy(75)
    );
\xy_reg[75]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[75]_i_2_n_0\,
      CO(6) => \xy_reg[75]_i_2_n_1\,
      CO(5) => \xy_reg[75]_i_2_n_2\,
      CO(4) => \xy_reg[75]_i_2_n_3\,
      CO(3) => \xy_reg[75]_i_2_n_4\,
      CO(2) => \xy_reg[75]_i_2_n_5\,
      CO(1) => \xy_reg[75]_i_2_n_6\,
      CO(0) => \xy_reg[75]_i_2_n_7\,
      DI(7) => \xy[75]_i_4_n_0\,
      DI(6) => \xy[75]_i_5_n_0\,
      DI(5) => \xy[75]_i_6_n_0\,
      DI(4) => \xy[75]_i_7_n_0\,
      DI(3) => \xy[75]_i_8_n_0\,
      DI(2) => \xy[75]_i_9_n_0\,
      DI(1) => \xy[75]_i_10_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[75]_i_2_n_8\,
      O(6) => \xy_reg[75]_i_2_n_9\,
      O(5) => \xy_reg[75]_i_2_n_10\,
      O(4) => \xy_reg[75]_i_2_n_11\,
      O(3) => \xy_reg[75]_i_2_n_12\,
      O(2 downto 0) => xy03_in(2 downto 0),
      S(7) => \xy[75]_i_11_n_0\,
      S(6) => \xy[75]_i_12_n_0\,
      S(5) => \xy[75]_i_13_n_0\,
      S(4) => \xy[75]_i_14_n_0\,
      S(3) => \xy[75]_i_15_n_0\,
      S(2) => \xy[75]_i_16_n_0\,
      S(1) => \xy[75]_i_17_n_0\,
      S(0) => \xy[75]_i_18_n_0\
    );
\xy_reg[75]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[75]_i_3_n_0\,
      CO(6) => \xy_reg[75]_i_3_n_1\,
      CO(5) => \xy_reg[75]_i_3_n_2\,
      CO(4) => \xy_reg[75]_i_3_n_3\,
      CO(3) => \xy_reg[75]_i_3_n_4\,
      CO(2) => \xy_reg[75]_i_3_n_5\,
      CO(1) => \xy_reg[75]_i_3_n_6\,
      CO(0) => \xy_reg[75]_i_3_n_7\,
      DI(7) => \xy[75]_i_19_n_0\,
      DI(6) => \xy[75]_i_20_n_0\,
      DI(5) => \xy[75]_i_21_n_0\,
      DI(4) => \xy[75]_i_22_n_0\,
      DI(3) => \xy[75]_i_23_n_0\,
      DI(2) => \xy[75]_i_24_n_0\,
      DI(1) => \xy[75]_i_25_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[75]_i_3_n_8\,
      O(6) => \xy_reg[75]_i_3_n_9\,
      O(5) => \xy_reg[75]_i_3_n_10\,
      O(4) => \xy_reg[75]_i_3_n_11\,
      O(3) => \xy_reg[75]_i_3_n_12\,
      O(2) => \xy_reg[75]_i_3_n_13\,
      O(1) => \xy_reg[75]_i_3_n_14\,
      O(0) => \xy_reg[75]_i_3_n_15\,
      S(7) => \xy[75]_i_26_n_0\,
      S(6) => \xy[75]_i_27_n_0\,
      S(5) => \xy[75]_i_28_n_0\,
      S(4) => \xy[75]_i_29_n_0\,
      S(3) => \xy[75]_i_30_n_0\,
      S(2) => \xy[75]_i_31_n_0\,
      S(1) => \xy[75]_i_32_n_0\,
      S(0) => \xy[75]_i_33_n_0\
    );
\xy_reg[76]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[76]_i_1_n_0\,
      Q => xy(76)
    );
\xy_reg[77]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[77]_i_1_n_0\,
      Q => xy(77)
    );
\xy_reg[78]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[78]_i_1_n_0\,
      Q => xy(78)
    );
\xy_reg[79]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[79]_i_1_n_0\,
      Q => xy(79)
    );
\xy_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[7]_i_1_n_0\,
      Q => xy(7)
    );
\xy_reg[80]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[80]_i_1_n_0\,
      Q => xy(80)
    );
\xy_reg[81]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[81]_i_1_n_0\,
      Q => xy(81)
    );
\xy_reg[82]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[82]_i_1_n_0\,
      Q => xy(82)
    );
\xy_reg[83]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[83]_i_1_n_0\,
      Q => xy(83)
    );
\xy_reg[83]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[83]_i_2_n_0\,
      CO(6) => \xy_reg[83]_i_2_n_1\,
      CO(5) => \xy_reg[83]_i_2_n_2\,
      CO(4) => \xy_reg[83]_i_2_n_3\,
      CO(3) => \xy_reg[83]_i_2_n_4\,
      CO(2) => \xy_reg[83]_i_2_n_5\,
      CO(1) => \xy_reg[83]_i_2_n_6\,
      CO(0) => \xy_reg[83]_i_2_n_7\,
      DI(7) => \xy[83]_i_3_n_0\,
      DI(6) => \xy[83]_i_4_n_0\,
      DI(5) => \xy[83]_i_5_n_0\,
      DI(4) => \xy[83]_i_6_n_0\,
      DI(3) => \xy[83]_i_7_n_0\,
      DI(2) => \xy[83]_i_8_n_0\,
      DI(1) => \xy[83]_i_9_n_0\,
      DI(0) => \xy[83]_i_10_n_0\,
      O(7 downto 0) => xy03_in(11 downto 4),
      S(7) => \xy[83]_i_11_n_0\,
      S(6) => \xy[83]_i_12_n_0\,
      S(5) => \xy[83]_i_13_n_0\,
      S(4) => \xy[83]_i_14_n_0\,
      S(3) => \xy[83]_i_15_n_0\,
      S(2) => \xy[83]_i_16_n_0\,
      S(1) => \xy[83]_i_17_n_0\,
      S(0) => \xy[83]_i_18_n_0\
    );
\xy_reg[84]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[84]_i_1_n_0\,
      Q => xy(84)
    );
\xy_reg[85]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[85]_i_1_n_0\,
      Q => xy(85)
    );
\xy_reg[86]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[86]_i_1_n_0\,
      Q => xy(86)
    );
\xy_reg[87]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[87]_i_1_n_0\,
      Q => xy(87)
    );
\xy_reg[88]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[88]_i_1_n_0\,
      Q => xy(88)
    );
\xy_reg[89]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[89]_i_1_n_0\,
      Q => xy(89)
    );
\xy_reg[89]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \xy_reg[89]_i_13_n_0\,
      CO(6) => \xy_reg[89]_i_13_n_1\,
      CO(5) => \xy_reg[89]_i_13_n_2\,
      CO(4) => \xy_reg[89]_i_13_n_3\,
      CO(3) => \xy_reg[89]_i_13_n_4\,
      CO(2) => \xy_reg[89]_i_13_n_5\,
      CO(1) => \xy_reg[89]_i_13_n_6\,
      CO(0) => \xy_reg[89]_i_13_n_7\,
      DI(7) => \xy[89]_i_22_n_0\,
      DI(6) => \xy[89]_i_23_n_0\,
      DI(5) => \xy[89]_i_24_n_0\,
      DI(4) => \xy[89]_i_25_n_0\,
      DI(3) => \xy[89]_i_26_n_0\,
      DI(2) => \xy[89]_i_27_n_0\,
      DI(1) => \xy[89]_i_28_n_0\,
      DI(0) => '0',
      O(7) => \xy_reg[89]_i_13_n_8\,
      O(6) => \xy_reg[89]_i_13_n_9\,
      O(5) => \xy_reg[89]_i_13_n_10\,
      O(4) => \xy_reg[89]_i_13_n_11\,
      O(3) => \xy_reg[89]_i_13_n_12\,
      O(2) => \xy_reg[89]_i_13_n_13\,
      O(1) => \xy_reg[89]_i_13_n_14\,
      O(0) => \xy_reg[89]_i_13_n_15\,
      S(7) => \xy[89]_i_29_n_0\,
      S(6) => \xy[89]_i_30_n_0\,
      S(5) => \xy[89]_i_31_n_0\,
      S(4) => \xy[89]_i_32_n_0\,
      S(3) => \xy[89]_i_33_n_0\,
      S(2) => \xy[89]_i_34_n_0\,
      S(1) => \xy[89]_i_35_n_0\,
      S(0) => \xy[89]_i_36_n_0\
    );
\xy_reg[89]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[83]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_xy_reg[89]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \xy_reg[89]_i_2_n_3\,
      CO(3) => \xy_reg[89]_i_2_n_4\,
      CO(2) => \xy_reg[89]_i_2_n_5\,
      CO(1) => \xy_reg[89]_i_2_n_6\,
      CO(0) => \xy_reg[89]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \xy_reg[89]_i_3_n_13\,
      DI(3) => \xy[89]_i_4_n_0\,
      DI(2) => \xy[89]_i_5_n_0\,
      DI(1) => \xy[89]_i_6_n_0\,
      DI(0) => \xy[89]_i_7_n_0\,
      O(7 downto 6) => \NLW_xy_reg[89]_i_2_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => xy03_in(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \xy_reg[89]_i_3_n_12\,
      S(4) => \xy[89]_i_8_n_0\,
      S(3) => \xy[89]_i_9_n_0\,
      S(2) => \xy[89]_i_10_n_0\,
      S(1) => \xy[89]_i_11_n_0\,
      S(0) => \xy[89]_i_12_n_0\
    );
\xy_reg[89]_i_20\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[75]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xy_reg[89]_i_20_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xy_reg[89]_i_20_n_4\,
      CO(2) => \NLW_xy_reg[89]_i_20_CO_UNCONNECTED\(2),
      CO(1) => \xy_reg[89]_i_20_n_6\,
      CO(0) => \xy_reg[89]_i_20_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[89]_i_38_n_0\,
      DI(1) => \xy[89]_i_39_n_0\,
      DI(0) => \xy[89]_i_40_n_0\,
      O(7 downto 3) => \NLW_xy_reg[89]_i_20_O_UNCONNECTED\(7 downto 3),
      O(2) => \xy_reg[89]_i_20_n_13\,
      O(1) => \xy_reg[89]_i_20_n_14\,
      O(0) => \xy_reg[89]_i_20_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[89]_i_41_n_0\,
      S(1) => \xy[89]_i_42_n_0\,
      S(0) => \xy[89]_i_43_n_0\
    );
\xy_reg[89]_i_21\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[75]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_xy_reg[89]_i_21_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \xy_reg[89]_i_21_n_4\,
      CO(2) => \NLW_xy_reg[89]_i_21_CO_UNCONNECTED\(2),
      CO(1) => \xy_reg[89]_i_21_n_6\,
      CO(0) => \xy_reg[89]_i_21_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[89]_i_44_n_0\,
      DI(1) => \xy[89]_i_45_n_0\,
      DI(0) => \xy[89]_i_46_n_0\,
      O(7 downto 3) => \NLW_xy_reg[89]_i_21_O_UNCONNECTED\(7 downto 3),
      O(2) => \xy_reg[89]_i_21_n_13\,
      O(1) => \xy_reg[89]_i_21_n_14\,
      O(0) => \xy_reg[89]_i_21_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[89]_i_47_n_0\,
      S(1) => \xy[89]_i_48_n_0\,
      S(0) => \xy[89]_i_49_n_0\
    );
\xy_reg[89]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \xy_reg[89]_i_13_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_xy_reg[89]_i_3_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \xy_reg[89]_i_3_n_5\,
      CO(1) => \xy_reg[89]_i_3_n_6\,
      CO(0) => \xy_reg[89]_i_3_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \xy[89]_i_14_n_0\,
      DI(1) => \xy[89]_i_15_n_0\,
      DI(0) => \xy[89]_i_16_n_0\,
      O(7 downto 4) => \NLW_xy_reg[89]_i_3_O_UNCONNECTED\(7 downto 4),
      O(3) => \xy_reg[89]_i_3_n_12\,
      O(2) => \xy_reg[89]_i_3_n_13\,
      O(1) => \xy_reg[89]_i_3_n_14\,
      O(0) => \xy_reg[89]_i_3_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \xy[89]_i_17_n_0\,
      S(1) => \xy[89]_i_18_n_0\,
      S(0) => \xy[89]_i_19_n_0\
    );
\xy_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[8]_i_1_n_0\,
      Q => xy(8)
    );
\xy_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \xy[9]_i_1_n_0\,
      Q => xy(9)
    );
\ysqr4p1[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(72),
      O => \ysqr4p1[0]_i_1_n_0\
    );
\ysqr4p1[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(82),
      O => \ysqr4p1[10]_i_1_n_0\
    );
\ysqr4p1[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(83),
      O => \ysqr4p1[11]_i_1_n_0\
    );
\ysqr4p1[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(84),
      O => \ysqr4p1[12]_i_1_n_0\
    );
\ysqr4p1[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(85),
      O => \ysqr4p1[13]_i_1_n_0\
    );
\ysqr4p1[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(86),
      O => \ysqr4p1[14]_i_1_n_0\
    );
\ysqr4p1[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(87),
      O => \ysqr4p1[15]_i_1_n_0\
    );
\ysqr4p1[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => ysqr(88),
      O => \ysqr4p1[16]_i_1_n_0\
    );
\ysqr4p1[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => ysqr(89),
      O => \ysqr4p1[17]_i_1_n_0\
    );
\ysqr4p1[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(74),
      O => \ysqr4p1[2]_i_1_n_0\
    );
\ysqr4p1[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(75),
      O => \ysqr4p1[3]_i_1_n_0\
    );
\ysqr4p1[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(76),
      O => \ysqr4p1[4]_i_1_n_0\
    );
\ysqr4p1[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(77),
      O => \ysqr4p1[5]_i_1_n_0\
    );
\ysqr4p1[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(78),
      O => \ysqr4p1[6]_i_1_n_0\
    );
\ysqr4p1[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(79),
      O => \ysqr4p1[7]_i_1_n_0\
    );
\ysqr4p1[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(80),
      O => \ysqr4p1[8]_i_1_n_0\
    );
\ysqr4p1[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr(81),
      O => \ysqr4p1[9]_i_1_n_0\
    );
\ysqr4p1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[0]_i_1_n_0\,
      Q => ysqr4p1(0)
    );
\ysqr4p1_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[10]_i_1_n_0\,
      Q => ysqr4p1(10)
    );
\ysqr4p1_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[11]_i_1_n_0\,
      Q => ysqr4p1(11)
    );
\ysqr4p1_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[12]_i_1_n_0\,
      Q => ysqr4p1(12)
    );
\ysqr4p1_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[13]_i_1_n_0\,
      Q => ysqr4p1(13)
    );
\ysqr4p1_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[14]_i_1_n_0\,
      Q => ysqr4p1(14)
    );
\ysqr4p1_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[15]_i_1_n_0\,
      Q => ysqr4p1(15)
    );
\ysqr4p1_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[16]_i_1_n_0\,
      Q => ysqr4p1(16)
    );
\ysqr4p1_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[17]_i_1_n_0\,
      Q => ysqr4p1(17)
    );
\ysqr4p1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[2]_i_1_n_0\,
      Q => ysqr4p1(2)
    );
\ysqr4p1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[3]_i_1_n_0\,
      Q => ysqr4p1(3)
    );
\ysqr4p1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[4]_i_1_n_0\,
      Q => ysqr4p1(4)
    );
\ysqr4p1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[5]_i_1_n_0\,
      Q => ysqr4p1(5)
    );
\ysqr4p1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[6]_i_1_n_0\,
      Q => ysqr4p1(6)
    );
\ysqr4p1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[7]_i_1_n_0\,
      Q => ysqr4p1(7)
    );
\ysqr4p1_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[8]_i_1_n_0\,
      Q => ysqr4p1(8)
    );
\ysqr4p1_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p1[9]_i_1_n_0\,
      Q => ysqr4p1(9)
    );
\ysqr4p2[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(0),
      O => \ysqr4p2[0]_i_1_n_0\
    );
\ysqr4p2[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(10),
      O => \ysqr4p2[10]_i_1_n_0\
    );
\ysqr4p2[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(11),
      O => \ysqr4p2[11]_i_1_n_0\
    );
\ysqr4p2[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(12),
      O => \ysqr4p2[12]_i_1_n_0\
    );
\ysqr4p2[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(13),
      O => \ysqr4p2[13]_i_1_n_0\
    );
\ysqr4p2[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(14),
      O => \ysqr4p2[14]_i_1_n_0\
    );
\ysqr4p2[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(15),
      O => \ysqr4p2[15]_i_1_n_0\
    );
\ysqr4p2[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => ysqr4p1(16),
      O => \ysqr4p2[16]_i_1_n_0\
    );
\ysqr4p2[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => ysqr4p1(17),
      O => \ysqr4p2[17]_i_1_n_0\
    );
\ysqr4p2[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(2),
      O => \ysqr4p2[2]_i_1_n_0\
    );
\ysqr4p2[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(3),
      O => \ysqr4p2[3]_i_1_n_0\
    );
\ysqr4p2[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(4),
      O => \ysqr4p2[4]_i_1_n_0\
    );
\ysqr4p2[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(5),
      O => \ysqr4p2[5]_i_1_n_0\
    );
\ysqr4p2[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(6),
      O => \ysqr4p2[6]_i_1_n_0\
    );
\ysqr4p2[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(7),
      O => \ysqr4p2[7]_i_1_n_0\
    );
\ysqr4p2[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(8),
      O => \ysqr4p2[8]_i_1_n_0\
    );
\ysqr4p2[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr4p1(9),
      O => \ysqr4p2[9]_i_1_n_0\
    );
\ysqr4p2_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[0]_i_1_n_0\,
      Q => ysqr4p2(0)
    );
\ysqr4p2_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[10]_i_1_n_0\,
      Q => ysqr4p2(10)
    );
\ysqr4p2_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[11]_i_1_n_0\,
      Q => ysqr4p2(11)
    );
\ysqr4p2_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[12]_i_1_n_0\,
      Q => ysqr4p2(12)
    );
\ysqr4p2_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[13]_i_1_n_0\,
      Q => ysqr4p2(13)
    );
\ysqr4p2_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[14]_i_1_n_0\,
      Q => ysqr4p2(14)
    );
\ysqr4p2_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[15]_i_1_n_0\,
      Q => ysqr4p2(15)
    );
\ysqr4p2_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[16]_i_1_n_0\,
      Q => ysqr4p2(16)
    );
\ysqr4p2_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[17]_i_1_n_0\,
      Q => ysqr4p2(17)
    );
\ysqr4p2_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[2]_i_1_n_0\,
      Q => ysqr4p2(2)
    );
\ysqr4p2_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[3]_i_1_n_0\,
      Q => ysqr4p2(3)
    );
\ysqr4p2_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[4]_i_1_n_0\,
      Q => ysqr4p2(4)
    );
\ysqr4p2_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[5]_i_1_n_0\,
      Q => ysqr4p2(5)
    );
\ysqr4p2_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[6]_i_1_n_0\,
      Q => ysqr4p2(6)
    );
\ysqr4p2_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[7]_i_1_n_0\,
      Q => ysqr4p2(7)
    );
\ysqr4p2_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[8]_i_1_n_0\,
      Q => ysqr4p2(8)
    );
\ysqr4p2_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr4p2[9]_i_1_n_0\,
      Q => ysqr4p2(9)
    );
\ysqr[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => \dy_reg_n_0_[0]\,
      O => \ysqr[0]_i_1_n_0\
    );
\ysqr[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(10),
      O => \ysqr[10]_i_1_n_0\
    );
\ysqr[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(11),
      O => \ysqr[11]_i_1_n_0\
    );
\ysqr[11]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[3]_i_3_n_15\,
      I1 => \ysqr_reg[3]_i_2_n_13\,
      O => \ysqr[11]_i_10_n_0\
    );
\ysqr[11]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \ysqr_reg[3]_i_3_n_9\,
      I1 => \ysqr_reg[17]_i_13_n_12\,
      I2 => \ysqr_reg[17]_i_18_n_14\,
      I3 => \ysqr_reg[17]_i_13_n_11\,
      I4 => \ysqr_reg[3]_i_3_n_8\,
      I5 => \ysqr[11]_i_19_n_0\,
      O => \ysqr[11]_i_11_n_0\
    );
\ysqr[11]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \ysqr_reg[17]_i_18_n_15\,
      I1 => \ysqr_reg[3]_i_3_n_9\,
      I2 => \ysqr_reg[17]_i_13_n_12\,
      I3 => \ysqr_reg[3]_i_3_n_8\,
      I4 => \ysqr_reg[17]_i_13_n_11\,
      I5 => \ysqr_reg[17]_i_18_n_14\,
      O => \ysqr[11]_i_12_n_0\
    );
\ysqr[11]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \ysqr_reg[17]_i_18_n_15\,
      I1 => \ysqr_reg[17]_i_13_n_12\,
      I2 => \ysqr_reg[3]_i_3_n_9\,
      I3 => \ysqr_reg[3]_i_3_n_10\,
      I4 => \ysqr_reg[3]_i_2_n_8\,
      I5 => \ysqr_reg[17]_i_13_n_13\,
      O => \ysqr[11]_i_13_n_0\
    );
\ysqr[11]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr[11]_i_6_n_0\,
      I1 => \ysqr_reg[17]_i_13_n_13\,
      I2 => \ysqr_reg[3]_i_2_n_8\,
      I3 => \ysqr_reg[3]_i_3_n_10\,
      O => \ysqr[11]_i_14_n_0\
    );
\ysqr[11]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr_reg[17]_i_13_n_14\,
      I1 => \ysqr_reg[3]_i_2_n_9\,
      I2 => \ysqr_reg[3]_i_3_n_11\,
      I3 => \ysqr[11]_i_7_n_0\,
      O => \ysqr[11]_i_15_n_0\
    );
\ysqr[11]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr_reg[17]_i_13_n_15\,
      I1 => \ysqr_reg[3]_i_2_n_10\,
      I2 => \ysqr_reg[3]_i_3_n_12\,
      I3 => \ysqr[11]_i_8_n_0\,
      O => \ysqr[11]_i_16_n_0\
    );
\ysqr[11]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \ysqr_reg[3]_i_3_n_13\,
      I1 => \ysqr_reg[3]_i_2_n_11\,
      I2 => \ysqr_reg[3]_i_2_n_12\,
      I3 => \ysqr_reg[3]_i_3_n_14\,
      O => \ysqr[11]_i_17_n_0\
    );
\ysqr[11]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ysqr_reg[3]_i_2_n_13\,
      I1 => \ysqr_reg[3]_i_3_n_15\,
      I2 => \ysqr_reg[3]_i_2_n_12\,
      I3 => \ysqr_reg[3]_i_3_n_14\,
      O => \ysqr[11]_i_18_n_0\
    );
\ysqr[11]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \ysqr_reg[17]_i_17_n_15\,
      I1 => \ysqr_reg[17]_i_13_n_10\,
      I2 => \ysqr_reg[17]_i_18_n_5\,
      O => \ysqr[11]_i_19_n_0\
    );
\ysqr[11]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \ysqr_reg[3]_i_3_n_9\,
      I1 => \ysqr_reg[17]_i_13_n_12\,
      I2 => \ysqr_reg[17]_i_18_n_14\,
      I3 => \ysqr_reg[17]_i_13_n_11\,
      I4 => \ysqr_reg[3]_i_3_n_8\,
      O => \ysqr[11]_i_3_n_0\
    );
\ysqr[11]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \ysqr_reg[17]_i_18_n_15\,
      I1 => \ysqr_reg[3]_i_3_n_9\,
      I2 => \ysqr_reg[17]_i_13_n_12\,
      O => \ysqr[11]_i_4_n_0\
    );
\ysqr[11]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \ysqr_reg[3]_i_3_n_9\,
      I1 => \ysqr_reg[17]_i_13_n_12\,
      I2 => \ysqr_reg[17]_i_18_n_15\,
      O => \ysqr[11]_i_5_n_0\
    );
\ysqr[11]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ysqr_reg[17]_i_13_n_14\,
      I1 => \ysqr_reg[3]_i_2_n_9\,
      I2 => \ysqr_reg[3]_i_3_n_11\,
      O => \ysqr[11]_i_6_n_0\
    );
\ysqr[11]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ysqr_reg[17]_i_13_n_15\,
      I1 => \ysqr_reg[3]_i_2_n_10\,
      I2 => \ysqr_reg[3]_i_3_n_12\,
      O => \ysqr[11]_i_7_n_0\
    );
\ysqr[11]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[3]_i_3_n_13\,
      I1 => \ysqr_reg[3]_i_2_n_11\,
      O => \ysqr[11]_i_8_n_0\
    );
\ysqr[11]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[3]_i_3_n_14\,
      I1 => \ysqr_reg[3]_i_2_n_12\,
      O => \ysqr[11]_i_9_n_0\
    );
\ysqr[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(12),
      O => \ysqr[12]_i_1_n_0\
    );
\ysqr[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(13),
      O => \ysqr[13]_i_1_n_0\
    );
\ysqr[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(14),
      O => \ysqr[14]_i_1_n_0\
    );
\ysqr[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(15),
      O => \ysqr[15]_i_1_n_0\
    );
\ysqr[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(16),
      O => \ysqr[16]_i_1_n_0\
    );
\ysqr[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(17),
      O => \ysqr[17]_i_1_n_0\
    );
\ysqr[17]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \ysqr[17]_i_5_n_0\,
      I1 => \ysqr_reg[17]_i_3_n_15\,
      I2 => \ysqr_reg[17]_i_17_n_4\,
      I3 => \ysqr_reg[17]_i_13_n_8\,
      I4 => \ysqr_reg[17]_i_17_n_13\,
      O => \ysqr[17]_i_10_n_0\
    );
\ysqr[17]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \ysqr_reg[17]_i_17_n_14\,
      I1 => \ysqr_reg[17]_i_13_n_9\,
      I2 => \ysqr_reg[17]_i_17_n_13\,
      I3 => \ysqr_reg[17]_i_13_n_8\,
      I4 => \ysqr[17]_i_6_n_0\,
      O => \ysqr[17]_i_11_n_0\
    );
\ysqr[17]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \ysqr[17]_i_7_n_0\,
      I1 => \ysqr_reg[17]_i_17_n_15\,
      I2 => \ysqr_reg[17]_i_18_n_5\,
      I3 => \ysqr_reg[17]_i_13_n_10\,
      I4 => \ysqr_reg[17]_i_17_n_14\,
      I5 => \ysqr_reg[17]_i_13_n_9\,
      O => \ysqr[17]_i_12_n_0\
    );
\ysqr[17]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \dy_reg_n_0_[7]\,
      I1 => \dy_reg_n_0_[8]\,
      O => \ysqr[17]_i_14_n_0\
    );
\ysqr[17]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \dy_reg_n_0_[6]\,
      I1 => \dy_reg_n_0_[8]\,
      O => \ysqr[17]_i_15_n_0\
    );
\ysqr[17]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dy_reg_n_0_[7]\,
      I1 => \dy_reg_n_0_[6]\,
      O => \ysqr[17]_i_16_n_0\
    );
\ysqr[17]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7777000"
    )
        port map (
      I0 => \dy_reg_n_0_[8]\,
      I1 => \dy_reg_n_0_[4]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dy_reg_n_0_[5]\,
      I4 => \dy_reg_n_0_[6]\,
      O => \ysqr[17]_i_19_n_0\
    );
\ysqr[17]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[8]\,
      I1 => \dy_reg_n_0_[3]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dy_reg_n_0_[4]\,
      I4 => \dy_reg_n_0_[5]\,
      I5 => \dy_reg_n_0_[6]\,
      O => \ysqr[17]_i_20_n_0\
    );
\ysqr[17]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[8]\,
      I1 => \dy_reg_n_0_[2]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dy_reg_n_0_[3]\,
      I4 => \dy_reg_n_0_[4]\,
      I5 => \dy_reg_n_0_[6]\,
      O => \ysqr[17]_i_21_n_0\
    );
\ysqr[17]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[8]\,
      I1 => \dy_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dy_reg_n_0_[2]\,
      I4 => \dy_reg_n_0_[3]\,
      I5 => \dy_reg_n_0_[6]\,
      O => \ysqr[17]_i_22_n_0\
    );
\ysqr[17]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => \dy_reg_n_0_[8]\,
      I1 => \dy_reg_n_0_[0]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dy_reg_n_0_[1]\,
      O => \ysqr[17]_i_23_n_0\
    );
\ysqr[17]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[1]\,
      I1 => \dy_reg_n_0_[6]\,
      O => \ysqr[17]_i_24_n_0\
    );
\ysqr[17]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8E11F555"
    )
        port map (
      I0 => \dy_reg_n_0_[6]\,
      I1 => \dy_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[4]\,
      I3 => \dy_reg_n_0_[8]\,
      I4 => \dy_reg_n_0_[5]\,
      O => \ysqr[17]_i_25_n_0\
    );
\ysqr[17]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EB843C0C903FCF3F"
    )
        port map (
      I0 => \dy_reg_n_0_[3]\,
      I1 => \dy_reg_n_0_[5]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dy_reg_n_0_[4]\,
      I4 => \dy_reg_n_0_[8]\,
      I5 => \dy_reg_n_0_[6]\,
      O => \ysqr[17]_i_26_n_0\
    );
\ysqr[17]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F07070780F8F8F8"
    )
        port map (
      I0 => \dy_reg_n_0_[6]\,
      I1 => \dy_reg_n_0_[4]\,
      I2 => \ysqr[17]_i_43_n_0\,
      I3 => \dy_reg_n_0_[2]\,
      I4 => \dy_reg_n_0_[8]\,
      I5 => \ysqr[17]_i_44_n_0\,
      O => \ysqr[17]_i_27_n_0\
    );
\ysqr[17]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A956A956A95"
    )
        port map (
      I0 => \ysqr[17]_i_22_n_0\,
      I1 => \dy_reg_n_0_[8]\,
      I2 => \dy_reg_n_0_[2]\,
      I3 => \ysqr[17]_i_43_n_0\,
      I4 => \dy_reg_n_0_[4]\,
      I5 => \dy_reg_n_0_[6]\,
      O => \ysqr[17]_i_28_n_0\
    );
\ysqr[17]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"69C399C369336933"
    )
        port map (
      I0 => \dy_reg_n_0_[2]\,
      I1 => \ysqr[17]_i_45_n_0\,
      I2 => \dy_reg_n_0_[1]\,
      I3 => \dy_reg_n_0_[7]\,
      I4 => \dy_reg_n_0_[0]\,
      I5 => \dy_reg_n_0_[8]\,
      O => \ysqr[17]_i_29_n_0\
    );
\ysqr[17]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dy_reg_n_0_[1]\,
      I1 => \dy_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[0]\,
      I3 => \dy_reg_n_0_[8]\,
      I4 => \dy_reg_n_0_[6]\,
      I5 => \dy_reg_n_0_[2]\,
      O => \ysqr[17]_i_30_n_0\
    );
\ysqr[17]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[6]\,
      I1 => \dy_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dy_reg_n_0_[0]\,
      O => \ysqr[17]_i_31_n_0\
    );
\ysqr[17]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[0]\,
      I1 => \dy_reg_n_0_[6]\,
      O => \ysqr[17]_i_32_n_0\
    );
\ysqr[17]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[7]\,
      I1 => \dy_reg_n_0_[5]\,
      I2 => \dy_reg_n_0_[8]\,
      I3 => \dy_reg_n_0_[4]\,
      O => \ysqr[17]_i_33_n_0\
    );
\ysqr[17]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[5]\,
      I1 => \dy_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[4]\,
      I3 => \dy_reg_n_0_[8]\,
      O => \ysqr[17]_i_34_n_0\
    );
\ysqr[17]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[4]\,
      I1 => \dy_reg_n_0_[5]\,
      O => \ysqr[17]_i_35_n_0\
    );
\ysqr[17]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dy_reg_n_0_[4]\,
      I1 => \dy_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[8]\,
      I3 => \dy_reg_n_0_[5]\,
      O => \ysqr[17]_i_36_n_0\
    );
\ysqr[17]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dy_reg_n_0_[6]\,
      I1 => \dy_reg_n_0_[3]\,
      I2 => \dy_reg_n_0_[8]\,
      I3 => \dy_reg_n_0_[4]\,
      I4 => \dy_reg_n_0_[7]\,
      I5 => \dy_reg_n_0_[5]\,
      O => \ysqr[17]_i_37_n_0\
    );
\ysqr[17]_i_38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D22287772DDD8777"
    )
        port map (
      I0 => \dy_reg_n_0_[4]\,
      I1 => \dy_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[3]\,
      I3 => \dy_reg_n_0_[8]\,
      I4 => \dy_reg_n_0_[5]\,
      I5 => \dy_reg_n_0_[6]\,
      O => \ysqr[17]_i_38_n_0\
    );
\ysqr[17]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[7]\,
      I1 => \dy_reg_n_0_[2]\,
      I2 => \dy_reg_n_0_[8]\,
      I3 => \dy_reg_n_0_[1]\,
      O => \ysqr[17]_i_39_n_0\
    );
\ysqr[17]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \ysqr_reg[17]_i_17_n_13\,
      I1 => \ysqr_reg[17]_i_13_n_8\,
      I2 => \ysqr_reg[17]_i_17_n_4\,
      I3 => \ysqr_reg[17]_i_3_n_15\,
      O => \ysqr[17]_i_4_n_0\
    );
\ysqr[17]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[2]\,
      I1 => \dy_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[1]\,
      I3 => \dy_reg_n_0_[8]\,
      O => \ysqr[17]_i_40_n_0\
    );
\ysqr[17]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dy_reg_n_0_[1]\,
      I1 => \dy_reg_n_0_[7]\,
      I2 => \dy_reg_n_0_[8]\,
      I3 => \dy_reg_n_0_[2]\,
      O => \ysqr[17]_i_41_n_0\
    );
\ysqr[17]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dy_reg_n_0_[6]\,
      I1 => \dy_reg_n_0_[0]\,
      I2 => \dy_reg_n_0_[8]\,
      I3 => \dy_reg_n_0_[1]\,
      I4 => \dy_reg_n_0_[7]\,
      I5 => \dy_reg_n_0_[2]\,
      O => \ysqr[17]_i_42_n_0\
    );
\ysqr[17]_i_43\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[3]\,
      I1 => \dy_reg_n_0_[7]\,
      O => \ysqr[17]_i_43_n_0\
    );
\ysqr[17]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dy_reg_n_0_[6]\,
      I1 => \dy_reg_n_0_[5]\,
      I2 => \dy_reg_n_0_[8]\,
      I3 => \dy_reg_n_0_[3]\,
      I4 => \dy_reg_n_0_[7]\,
      I5 => \dy_reg_n_0_[4]\,
      O => \ysqr[17]_i_44_n_0\
    );
\ysqr[17]_i_45\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[3]\,
      I1 => \dy_reg_n_0_[6]\,
      O => \ysqr[17]_i_45_n_0\
    );
\ysqr[17]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \ysqr_reg[17]_i_17_n_14\,
      I1 => \ysqr_reg[17]_i_13_n_9\,
      I2 => \ysqr_reg[17]_i_17_n_13\,
      I3 => \ysqr_reg[17]_i_13_n_8\,
      O => \ysqr[17]_i_5_n_0\
    );
\ysqr[17]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \ysqr_reg[17]_i_17_n_14\,
      I1 => \ysqr_reg[17]_i_13_n_9\,
      I2 => \ysqr_reg[17]_i_17_n_15\,
      I3 => \ysqr_reg[17]_i_18_n_5\,
      I4 => \ysqr_reg[17]_i_13_n_10\,
      O => \ysqr[17]_i_6_n_0\
    );
\ysqr[17]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \ysqr_reg[3]_i_3_n_8\,
      I1 => \ysqr_reg[17]_i_18_n_14\,
      I2 => \ysqr_reg[17]_i_13_n_11\,
      I3 => \ysqr_reg[17]_i_18_n_5\,
      I4 => \ysqr_reg[17]_i_13_n_10\,
      I5 => \ysqr_reg[17]_i_17_n_15\,
      O => \ysqr[17]_i_7_n_0\
    );
\ysqr[17]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \ysqr_reg[17]_i_3_n_15\,
      I1 => \ysqr_reg[17]_i_17_n_4\,
      I2 => \ysqr_reg[17]_i_3_n_14\,
      I3 => \ysqr_reg[17]_i_3_n_13\,
      O => \ysqr[17]_i_8_n_0\
    );
\ysqr[17]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \ysqr_reg[17]_i_13_n_8\,
      I1 => \ysqr_reg[17]_i_17_n_13\,
      I2 => \ysqr_reg[17]_i_3_n_15\,
      I3 => \ysqr_reg[17]_i_17_n_4\,
      I4 => \ysqr_reg[17]_i_3_n_14\,
      O => \ysqr[17]_i_9_n_0\
    );
\ysqr[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => B(0),
      O => \ysqr[18]_i_1_n_0\
    );
\ysqr[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(2),
      O => \ysqr[20]_i_1_n_0\
    );
\ysqr[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \ysqr_reg[21]_i_2_n_13\,
      I1 => \ysqr_reg[21]_i_3_n_15\,
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \ysqr[21]_i_1_n_0\
    );
\ysqr[21]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \ysqr[21]_i_4_n_0\,
      I1 => \ysqr[21]_i_31_n_0\,
      I2 => B(2),
      I3 => B(6),
      O => \ysqr[21]_i_10_n_0\
    );
\ysqr[21]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \ysqr[21]_i_5_n_0\,
      I1 => B(5),
      I2 => B(2),
      I3 => \ysqr[21]_i_32_n_0\,
      I4 => B(0),
      I5 => B(7),
      O => \ysqr[21]_i_11_n_0\
    );
\ysqr[21]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \ysqr[21]_i_6_n_0\,
      I1 => B(4),
      I2 => B(2),
      I3 => B(5),
      I4 => B(1),
      I5 => \ysqr[21]_i_33_n_0\,
      O => \ysqr[21]_i_12_n_0\
    );
\ysqr[21]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \ysqr[21]_i_7_n_0\,
      I1 => B(4),
      I2 => B(1),
      I3 => \ysqr[21]_i_21_n_0\,
      I4 => B(0),
      I5 => B(5),
      O => \ysqr[21]_i_13_n_0\
    );
\ysqr[21]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => B(1),
      I1 => B(2),
      I2 => B(3),
      I3 => B(4),
      I4 => B(0),
      O => \ysqr[21]_i_14_n_0\
    );
\ysqr[21]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => B(3),
      I1 => B(2),
      I2 => B(0),
      O => \ysqr[21]_i_15_n_0\
    );
\ysqr[21]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => B(1),
      I1 => B(0),
      O => \ysqr[21]_i_16_n_0\
    );
\ysqr[21]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(3),
      I1 => B(7),
      O => \ysqr[21]_i_17_n_0\
    );
\ysqr[21]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(3),
      I1 => B(6),
      O => \ysqr[21]_i_18_n_0\
    );
\ysqr[21]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(2),
      I1 => B(5),
      O => \ysqr[21]_i_19_n_0\
    );
\ysqr[21]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"956A6A6A"
    )
        port map (
      I0 => B(3),
      I1 => B(1),
      I2 => B(5),
      I3 => B(2),
      I4 => B(4),
      O => \ysqr[21]_i_20_n_0\
    );
\ysqr[21]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(2),
      I1 => B(3),
      O => \ysqr[21]_i_21_n_0\
    );
\ysqr[21]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(1),
      I1 => B(3),
      O => \ysqr[21]_i_22_n_0\
    );
\ysqr[21]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => B(4),
      I1 => B(5),
      I2 => B(6),
      I3 => B(7),
      I4 => B(3),
      O => \ysqr[21]_i_23_n_0\
    );
\ysqr[21]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => B(6),
      I1 => B(5),
      I2 => B(3),
      O => \ysqr[21]_i_24_n_0\
    );
\ysqr[21]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => B(4),
      I1 => B(3),
      O => \ysqr[21]_i_25_n_0\
    );
\ysqr[21]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17A08800"
    )
        port map (
      I0 => B(3),
      I1 => B(1),
      I2 => B(4),
      I3 => B(5),
      I4 => B(2),
      O => \ysqr[21]_i_26_n_0\
    );
\ysqr[21]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"663C963C66CC66CC"
    )
        port map (
      I0 => B(2),
      I1 => B(3),
      I2 => B(1),
      I3 => B(4),
      I4 => B(0),
      I5 => B(5),
      O => \ysqr[21]_i_27_n_0\
    );
\ysqr[21]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => B(0),
      I1 => B(5),
      I2 => B(1),
      I3 => B(4),
      I4 => B(3),
      I5 => B(2),
      O => \ysqr[21]_i_28_n_0\
    );
\ysqr[21]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => B(3),
      I1 => B(1),
      I2 => B(4),
      I3 => B(0),
      O => \ysqr[21]_i_29_n_0\
    );
\ysqr[21]_i_30\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(0),
      I1 => B(3),
      O => \ysqr[21]_i_30_n_0\
    );
\ysqr[21]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => B(8),
      I1 => B(0),
      I2 => B(7),
      I3 => B(1),
      O => \ysqr[21]_i_31_n_0\
    );
\ysqr[21]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(1),
      I1 => B(6),
      O => \ysqr[21]_i_32_n_0\
    );
\ysqr[21]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(0),
      I1 => B(6),
      O => \ysqr[21]_i_33_n_0\
    );
\ysqr[21]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => B(5),
      I1 => B(2),
      I2 => B(6),
      I3 => B(1),
      I4 => B(0),
      I5 => B(7),
      O => \ysqr[21]_i_4_n_0\
    );
\ysqr[21]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => B(4),
      I1 => B(2),
      I2 => B(5),
      I3 => B(1),
      I4 => B(0),
      I5 => B(6),
      O => \ysqr[21]_i_5_n_0\
    );
\ysqr[21]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => B(4),
      I1 => B(1),
      I2 => B(3),
      I3 => B(2),
      I4 => B(0),
      I5 => B(5),
      O => \ysqr[21]_i_6_n_0\
    );
\ysqr[21]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(1),
      I1 => B(2),
      O => \ysqr[21]_i_7_n_0\
    );
\ysqr[21]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => B(3),
      I1 => B(2),
      I2 => B(1),
      O => \ysqr[21]_i_8_n_0\
    );
\ysqr[21]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(0),
      I1 => B(3),
      O => \ysqr[21]_i_9_n_0\
    );
\ysqr[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(4),
      O => \ysqr[22]_i_1_n_0\
    );
\ysqr[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(5),
      O => \ysqr[23]_i_1_n_0\
    );
\ysqr[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(6),
      O => \ysqr[24]_i_1_n_0\
    );
\ysqr[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(7),
      O => \ysqr[25]_i_1_n_0\
    );
\ysqr[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(8),
      O => \ysqr[26]_i_1_n_0\
    );
\ysqr[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(9),
      O => \ysqr[27]_i_1_n_0\
    );
\ysqr[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(10),
      O => \ysqr[28]_i_1_n_0\
    );
\ysqr[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(11),
      O => \ysqr[29]_i_1_n_0\
    );
\ysqr[29]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[21]_i_3_n_15\,
      I1 => \ysqr_reg[21]_i_2_n_13\,
      O => \ysqr[29]_i_10_n_0\
    );
\ysqr[29]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \ysqr_reg[21]_i_3_n_9\,
      I1 => \ysqr_reg[35]_i_13_n_12\,
      I2 => \ysqr_reg[35]_i_18_n_14\,
      I3 => \ysqr_reg[35]_i_13_n_11\,
      I4 => \ysqr_reg[21]_i_3_n_8\,
      I5 => \ysqr[29]_i_19_n_0\,
      O => \ysqr[29]_i_11_n_0\
    );
\ysqr[29]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \ysqr_reg[35]_i_18_n_15\,
      I1 => \ysqr_reg[21]_i_3_n_9\,
      I2 => \ysqr_reg[35]_i_13_n_12\,
      I3 => \ysqr_reg[21]_i_3_n_8\,
      I4 => \ysqr_reg[35]_i_13_n_11\,
      I5 => \ysqr_reg[35]_i_18_n_14\,
      O => \ysqr[29]_i_12_n_0\
    );
\ysqr[29]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \ysqr_reg[35]_i_18_n_15\,
      I1 => \ysqr_reg[35]_i_13_n_12\,
      I2 => \ysqr_reg[21]_i_3_n_9\,
      I3 => \ysqr_reg[21]_i_3_n_10\,
      I4 => \ysqr_reg[21]_i_2_n_8\,
      I5 => \ysqr_reg[35]_i_13_n_13\,
      O => \ysqr[29]_i_13_n_0\
    );
\ysqr[29]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr[29]_i_6_n_0\,
      I1 => \ysqr_reg[35]_i_13_n_13\,
      I2 => \ysqr_reg[21]_i_2_n_8\,
      I3 => \ysqr_reg[21]_i_3_n_10\,
      O => \ysqr[29]_i_14_n_0\
    );
\ysqr[29]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr_reg[35]_i_13_n_14\,
      I1 => \ysqr_reg[21]_i_2_n_9\,
      I2 => \ysqr_reg[21]_i_3_n_11\,
      I3 => \ysqr[29]_i_7_n_0\,
      O => \ysqr[29]_i_15_n_0\
    );
\ysqr[29]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr_reg[35]_i_13_n_15\,
      I1 => \ysqr_reg[21]_i_2_n_10\,
      I2 => \ysqr_reg[21]_i_3_n_12\,
      I3 => \ysqr[29]_i_8_n_0\,
      O => \ysqr[29]_i_16_n_0\
    );
\ysqr[29]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \ysqr_reg[21]_i_3_n_13\,
      I1 => \ysqr_reg[21]_i_2_n_11\,
      I2 => \ysqr_reg[21]_i_2_n_12\,
      I3 => \ysqr_reg[21]_i_3_n_14\,
      O => \ysqr[29]_i_17_n_0\
    );
\ysqr[29]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ysqr_reg[21]_i_2_n_13\,
      I1 => \ysqr_reg[21]_i_3_n_15\,
      I2 => \ysqr_reg[21]_i_2_n_12\,
      I3 => \ysqr_reg[21]_i_3_n_14\,
      O => \ysqr[29]_i_18_n_0\
    );
\ysqr[29]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \ysqr_reg[35]_i_17_n_15\,
      I1 => \ysqr_reg[35]_i_13_n_10\,
      I2 => \ysqr_reg[35]_i_18_n_5\,
      O => \ysqr[29]_i_19_n_0\
    );
\ysqr[29]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \ysqr_reg[21]_i_3_n_9\,
      I1 => \ysqr_reg[35]_i_13_n_12\,
      I2 => \ysqr_reg[35]_i_18_n_14\,
      I3 => \ysqr_reg[35]_i_13_n_11\,
      I4 => \ysqr_reg[21]_i_3_n_8\,
      O => \ysqr[29]_i_3_n_0\
    );
\ysqr[29]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \ysqr_reg[35]_i_18_n_15\,
      I1 => \ysqr_reg[21]_i_3_n_9\,
      I2 => \ysqr_reg[35]_i_13_n_12\,
      O => \ysqr[29]_i_4_n_0\
    );
\ysqr[29]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \ysqr_reg[21]_i_3_n_9\,
      I1 => \ysqr_reg[35]_i_13_n_12\,
      I2 => \ysqr_reg[35]_i_18_n_15\,
      O => \ysqr[29]_i_5_n_0\
    );
\ysqr[29]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ysqr_reg[35]_i_13_n_14\,
      I1 => \ysqr_reg[21]_i_2_n_9\,
      I2 => \ysqr_reg[21]_i_3_n_11\,
      O => \ysqr[29]_i_6_n_0\
    );
\ysqr[29]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ysqr_reg[35]_i_13_n_15\,
      I1 => \ysqr_reg[21]_i_2_n_10\,
      I2 => \ysqr_reg[21]_i_3_n_12\,
      O => \ysqr[29]_i_7_n_0\
    );
\ysqr[29]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[21]_i_3_n_13\,
      I1 => \ysqr_reg[21]_i_2_n_11\,
      O => \ysqr[29]_i_8_n_0\
    );
\ysqr[29]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[21]_i_3_n_14\,
      I1 => \ysqr_reg[21]_i_2_n_12\,
      O => \ysqr[29]_i_9_n_0\
    );
\ysqr[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(2),
      O => \ysqr[2]_i_1_n_0\
    );
\ysqr[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(12),
      O => \ysqr[30]_i_1_n_0\
    );
\ysqr[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(13),
      O => \ysqr[31]_i_1_n_0\
    );
\ysqr[32]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(14),
      O => \ysqr[32]_i_1_n_0\
    );
\ysqr[33]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(15),
      O => \ysqr[33]_i_1_n_0\
    );
\ysqr[34]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(16),
      O => \ysqr[34]_i_1_n_0\
    );
\ysqr[35]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr00_in(17),
      O => \ysqr[35]_i_1_n_0\
    );
\ysqr[35]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \ysqr[35]_i_5_n_0\,
      I1 => \ysqr_reg[35]_i_3_n_15\,
      I2 => \ysqr_reg[35]_i_17_n_4\,
      I3 => \ysqr_reg[35]_i_13_n_8\,
      I4 => \ysqr_reg[35]_i_17_n_13\,
      O => \ysqr[35]_i_10_n_0\
    );
\ysqr[35]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \ysqr_reg[35]_i_17_n_14\,
      I1 => \ysqr_reg[35]_i_13_n_9\,
      I2 => \ysqr_reg[35]_i_17_n_13\,
      I3 => \ysqr_reg[35]_i_13_n_8\,
      I4 => \ysqr[35]_i_6_n_0\,
      O => \ysqr[35]_i_11_n_0\
    );
\ysqr[35]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \ysqr[35]_i_7_n_0\,
      I1 => \ysqr_reg[35]_i_17_n_15\,
      I2 => \ysqr_reg[35]_i_18_n_5\,
      I3 => \ysqr_reg[35]_i_13_n_10\,
      I4 => \ysqr_reg[35]_i_17_n_14\,
      I5 => \ysqr_reg[35]_i_13_n_9\,
      O => \ysqr[35]_i_12_n_0\
    );
\ysqr[35]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => B(7),
      I1 => B(8),
      O => \ysqr[35]_i_14_n_0\
    );
\ysqr[35]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => B(6),
      I1 => B(8),
      O => \ysqr[35]_i_15_n_0\
    );
\ysqr[35]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => B(7),
      I1 => B(6),
      O => \ysqr[35]_i_16_n_0\
    );
\ysqr[35]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7777000"
    )
        port map (
      I0 => B(8),
      I1 => B(4),
      I2 => B(7),
      I3 => B(5),
      I4 => B(6),
      O => \ysqr[35]_i_19_n_0\
    );
\ysqr[35]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => B(8),
      I1 => B(3),
      I2 => B(7),
      I3 => B(4),
      I4 => B(5),
      I5 => B(6),
      O => \ysqr[35]_i_20_n_0\
    );
\ysqr[35]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => B(8),
      I1 => B(2),
      I2 => B(7),
      I3 => B(3),
      I4 => B(4),
      I5 => B(6),
      O => \ysqr[35]_i_21_n_0\
    );
\ysqr[35]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => B(8),
      I1 => B(1),
      I2 => B(7),
      I3 => B(2),
      I4 => B(3),
      I5 => B(6),
      O => \ysqr[35]_i_22_n_0\
    );
\ysqr[35]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => B(8),
      I1 => B(0),
      I2 => B(7),
      I3 => B(1),
      O => \ysqr[35]_i_23_n_0\
    );
\ysqr[35]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(1),
      I1 => B(6),
      O => \ysqr[35]_i_24_n_0\
    );
\ysqr[35]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8E11F555"
    )
        port map (
      I0 => B(6),
      I1 => B(7),
      I2 => B(4),
      I3 => B(8),
      I4 => B(5),
      O => \ysqr[35]_i_25_n_0\
    );
\ysqr[35]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EB843C0C903FCF3F"
    )
        port map (
      I0 => B(3),
      I1 => B(5),
      I2 => B(7),
      I3 => B(4),
      I4 => B(8),
      I5 => B(6),
      O => \ysqr[35]_i_26_n_0\
    );
\ysqr[35]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F07070780F8F8F8"
    )
        port map (
      I0 => B(6),
      I1 => B(4),
      I2 => \ysqr[35]_i_43_n_0\,
      I3 => B(2),
      I4 => B(8),
      I5 => \ysqr[35]_i_44_n_0\,
      O => \ysqr[35]_i_27_n_0\
    );
\ysqr[35]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A956A956A95"
    )
        port map (
      I0 => \ysqr[35]_i_22_n_0\,
      I1 => B(8),
      I2 => B(2),
      I3 => \ysqr[35]_i_43_n_0\,
      I4 => B(4),
      I5 => B(6),
      O => \ysqr[35]_i_28_n_0\
    );
\ysqr[35]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"69C399C369336933"
    )
        port map (
      I0 => B(2),
      I1 => \ysqr[35]_i_45_n_0\,
      I2 => B(1),
      I3 => B(7),
      I4 => B(0),
      I5 => B(8),
      O => \ysqr[35]_i_29_n_0\
    );
\ysqr[35]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => B(1),
      I1 => B(7),
      I2 => B(0),
      I3 => B(8),
      I4 => B(6),
      I5 => B(2),
      O => \ysqr[35]_i_30_n_0\
    );
\ysqr[35]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => B(6),
      I1 => B(1),
      I2 => B(7),
      I3 => B(0),
      O => \ysqr[35]_i_31_n_0\
    );
\ysqr[35]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(0),
      I1 => B(6),
      O => \ysqr[35]_i_32_n_0\
    );
\ysqr[35]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => B(7),
      I1 => B(5),
      I2 => B(8),
      I3 => B(4),
      O => \ysqr[35]_i_33_n_0\
    );
\ysqr[35]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => B(5),
      I1 => B(7),
      I2 => B(4),
      I3 => B(8),
      O => \ysqr[35]_i_34_n_0\
    );
\ysqr[35]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(4),
      I1 => B(5),
      O => \ysqr[35]_i_35_n_0\
    );
\ysqr[35]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => B(4),
      I1 => B(7),
      I2 => B(8),
      I3 => B(5),
      O => \ysqr[35]_i_36_n_0\
    );
\ysqr[35]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => B(6),
      I1 => B(3),
      I2 => B(8),
      I3 => B(4),
      I4 => B(7),
      I5 => B(5),
      O => \ysqr[35]_i_37_n_0\
    );
\ysqr[35]_i_38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D22287772DDD8777"
    )
        port map (
      I0 => B(4),
      I1 => B(7),
      I2 => B(3),
      I3 => B(8),
      I4 => B(5),
      I5 => B(6),
      O => \ysqr[35]_i_38_n_0\
    );
\ysqr[35]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => B(7),
      I1 => B(2),
      I2 => B(8),
      I3 => B(1),
      O => \ysqr[35]_i_39_n_0\
    );
\ysqr[35]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \ysqr_reg[35]_i_17_n_13\,
      I1 => \ysqr_reg[35]_i_13_n_8\,
      I2 => \ysqr_reg[35]_i_17_n_4\,
      I3 => \ysqr_reg[35]_i_3_n_15\,
      O => \ysqr[35]_i_4_n_0\
    );
\ysqr[35]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => B(2),
      I1 => B(7),
      I2 => B(1),
      I3 => B(8),
      O => \ysqr[35]_i_40_n_0\
    );
\ysqr[35]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => B(1),
      I1 => B(7),
      I2 => B(8),
      I3 => B(2),
      O => \ysqr[35]_i_41_n_0\
    );
\ysqr[35]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => B(6),
      I1 => B(0),
      I2 => B(8),
      I3 => B(1),
      I4 => B(7),
      I5 => B(2),
      O => \ysqr[35]_i_42_n_0\
    );
\ysqr[35]_i_43\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(3),
      I1 => B(7),
      O => \ysqr[35]_i_43_n_0\
    );
\ysqr[35]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => B(6),
      I1 => B(5),
      I2 => B(8),
      I3 => B(3),
      I4 => B(7),
      I5 => B(4),
      O => \ysqr[35]_i_44_n_0\
    );
\ysqr[35]_i_45\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => B(3),
      I1 => B(6),
      O => \ysqr[35]_i_45_n_0\
    );
\ysqr[35]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \ysqr_reg[35]_i_17_n_14\,
      I1 => \ysqr_reg[35]_i_13_n_9\,
      I2 => \ysqr_reg[35]_i_17_n_13\,
      I3 => \ysqr_reg[35]_i_13_n_8\,
      O => \ysqr[35]_i_5_n_0\
    );
\ysqr[35]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \ysqr_reg[35]_i_17_n_14\,
      I1 => \ysqr_reg[35]_i_13_n_9\,
      I2 => \ysqr_reg[35]_i_17_n_15\,
      I3 => \ysqr_reg[35]_i_18_n_5\,
      I4 => \ysqr_reg[35]_i_13_n_10\,
      O => \ysqr[35]_i_6_n_0\
    );
\ysqr[35]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \ysqr_reg[21]_i_3_n_8\,
      I1 => \ysqr_reg[35]_i_18_n_14\,
      I2 => \ysqr_reg[35]_i_13_n_11\,
      I3 => \ysqr_reg[35]_i_18_n_5\,
      I4 => \ysqr_reg[35]_i_13_n_10\,
      I5 => \ysqr_reg[35]_i_17_n_15\,
      O => \ysqr[35]_i_7_n_0\
    );
\ysqr[35]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \ysqr_reg[35]_i_3_n_15\,
      I1 => \ysqr_reg[35]_i_17_n_4\,
      I2 => \ysqr_reg[35]_i_3_n_14\,
      I3 => \ysqr_reg[35]_i_3_n_13\,
      O => \ysqr[35]_i_8_n_0\
    );
\ysqr[35]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \ysqr_reg[35]_i_13_n_8\,
      I1 => \ysqr_reg[35]_i_17_n_13\,
      I2 => \ysqr_reg[35]_i_3_n_15\,
      I3 => \ysqr_reg[35]_i_17_n_4\,
      I4 => \ysqr_reg[35]_i_3_n_14\,
      O => \ysqr[35]_i_9_n_0\
    );
\ysqr[36]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => \dy_reg_n_0_[18]\,
      O => \ysqr[36]_i_1_n_0\
    );
\ysqr[38]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(2),
      O => \ysqr[38]_i_1_n_0\
    );
\ysqr[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \ysqr_reg[39]_i_2_n_13\,
      I1 => \ysqr_reg[39]_i_3_n_15\,
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \ysqr[39]_i_1_n_0\
    );
\ysqr[39]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \ysqr[39]_i_4_n_0\,
      I1 => \ysqr[39]_i_31_n_0\,
      I2 => \dy_reg_n_0_[20]\,
      I3 => \dy_reg_n_0_[24]\,
      O => \ysqr[39]_i_10_n_0\
    );
\ysqr[39]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \ysqr[39]_i_5_n_0\,
      I1 => \dy_reg_n_0_[23]\,
      I2 => \dy_reg_n_0_[20]\,
      I3 => \ysqr[39]_i_32_n_0\,
      I4 => \dy_reg_n_0_[18]\,
      I5 => \dy_reg_n_0_[25]\,
      O => \ysqr[39]_i_11_n_0\
    );
\ysqr[39]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \ysqr[39]_i_6_n_0\,
      I1 => \dy_reg_n_0_[22]\,
      I2 => \dy_reg_n_0_[20]\,
      I3 => \dy_reg_n_0_[23]\,
      I4 => \dy_reg_n_0_[19]\,
      I5 => \ysqr[39]_i_33_n_0\,
      O => \ysqr[39]_i_12_n_0\
    );
\ysqr[39]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \ysqr[39]_i_7_n_0\,
      I1 => \dy_reg_n_0_[22]\,
      I2 => \dy_reg_n_0_[19]\,
      I3 => \ysqr[39]_i_21_n_0\,
      I4 => \dy_reg_n_0_[18]\,
      I5 => \dy_reg_n_0_[23]\,
      O => \ysqr[39]_i_13_n_0\
    );
\ysqr[39]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dy_reg_n_0_[19]\,
      I1 => \dy_reg_n_0_[20]\,
      I2 => \dy_reg_n_0_[21]\,
      I3 => \dy_reg_n_0_[22]\,
      I4 => \dy_reg_n_0_[18]\,
      O => \ysqr[39]_i_14_n_0\
    );
\ysqr[39]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dy_reg_n_0_[21]\,
      I1 => \dy_reg_n_0_[20]\,
      I2 => \dy_reg_n_0_[18]\,
      O => \ysqr[39]_i_15_n_0\
    );
\ysqr[39]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dy_reg_n_0_[19]\,
      I1 => \dy_reg_n_0_[18]\,
      O => \ysqr[39]_i_16_n_0\
    );
\ysqr[39]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[21]\,
      I1 => \dy_reg_n_0_[25]\,
      O => \ysqr[39]_i_17_n_0\
    );
\ysqr[39]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[21]\,
      I1 => \dy_reg_n_0_[24]\,
      O => \ysqr[39]_i_18_n_0\
    );
\ysqr[39]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[20]\,
      I1 => \dy_reg_n_0_[23]\,
      O => \ysqr[39]_i_19_n_0\
    );
\ysqr[39]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"956A6A6A"
    )
        port map (
      I0 => \dy_reg_n_0_[21]\,
      I1 => \dy_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[23]\,
      I3 => \dy_reg_n_0_[20]\,
      I4 => \dy_reg_n_0_[22]\,
      O => \ysqr[39]_i_20_n_0\
    );
\ysqr[39]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[20]\,
      I1 => \dy_reg_n_0_[21]\,
      O => \ysqr[39]_i_21_n_0\
    );
\ysqr[39]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[19]\,
      I1 => \dy_reg_n_0_[21]\,
      O => \ysqr[39]_i_22_n_0\
    );
\ysqr[39]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dy_reg_n_0_[22]\,
      I1 => \dy_reg_n_0_[23]\,
      I2 => \dy_reg_n_0_[24]\,
      I3 => \dy_reg_n_0_[25]\,
      I4 => \dy_reg_n_0_[21]\,
      O => \ysqr[39]_i_23_n_0\
    );
\ysqr[39]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dy_reg_n_0_[24]\,
      I1 => \dy_reg_n_0_[23]\,
      I2 => \dy_reg_n_0_[21]\,
      O => \ysqr[39]_i_24_n_0\
    );
\ysqr[39]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dy_reg_n_0_[22]\,
      I1 => \dy_reg_n_0_[21]\,
      O => \ysqr[39]_i_25_n_0\
    );
\ysqr[39]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17A08800"
    )
        port map (
      I0 => \dy_reg_n_0_[21]\,
      I1 => \dy_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[22]\,
      I3 => \dy_reg_n_0_[23]\,
      I4 => \dy_reg_n_0_[20]\,
      O => \ysqr[39]_i_26_n_0\
    );
\ysqr[39]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"663C963C66CC66CC"
    )
        port map (
      I0 => \dy_reg_n_0_[20]\,
      I1 => \dy_reg_n_0_[21]\,
      I2 => \dy_reg_n_0_[19]\,
      I3 => \dy_reg_n_0_[22]\,
      I4 => \dy_reg_n_0_[18]\,
      I5 => \dy_reg_n_0_[23]\,
      O => \ysqr[39]_i_27_n_0\
    );
\ysqr[39]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dy_reg_n_0_[18]\,
      I1 => \dy_reg_n_0_[23]\,
      I2 => \dy_reg_n_0_[19]\,
      I3 => \dy_reg_n_0_[22]\,
      I4 => \dy_reg_n_0_[21]\,
      I5 => \dy_reg_n_0_[20]\,
      O => \ysqr[39]_i_28_n_0\
    );
\ysqr[39]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[21]\,
      I1 => \dy_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[22]\,
      I3 => \dy_reg_n_0_[18]\,
      O => \ysqr[39]_i_29_n_0\
    );
\ysqr[39]_i_30\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[18]\,
      I1 => \dy_reg_n_0_[21]\,
      O => \ysqr[39]_i_30_n_0\
    );
\ysqr[39]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[26]\,
      I1 => \dy_reg_n_0_[18]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dy_reg_n_0_[19]\,
      O => \ysqr[39]_i_31_n_0\
    );
\ysqr[39]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[19]\,
      I1 => \dy_reg_n_0_[24]\,
      O => \ysqr[39]_i_32_n_0\
    );
\ysqr[39]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[18]\,
      I1 => \dy_reg_n_0_[24]\,
      O => \ysqr[39]_i_33_n_0\
    );
\ysqr[39]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[23]\,
      I1 => \dy_reg_n_0_[20]\,
      I2 => \dy_reg_n_0_[24]\,
      I3 => \dy_reg_n_0_[19]\,
      I4 => \dy_reg_n_0_[18]\,
      I5 => \dy_reg_n_0_[25]\,
      O => \ysqr[39]_i_4_n_0\
    );
\ysqr[39]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[22]\,
      I1 => \dy_reg_n_0_[20]\,
      I2 => \dy_reg_n_0_[23]\,
      I3 => \dy_reg_n_0_[19]\,
      I4 => \dy_reg_n_0_[18]\,
      I5 => \dy_reg_n_0_[24]\,
      O => \ysqr[39]_i_5_n_0\
    );
\ysqr[39]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[22]\,
      I1 => \dy_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[21]\,
      I3 => \dy_reg_n_0_[20]\,
      I4 => \dy_reg_n_0_[18]\,
      I5 => \dy_reg_n_0_[23]\,
      O => \ysqr[39]_i_6_n_0\
    );
\ysqr[39]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[19]\,
      I1 => \dy_reg_n_0_[20]\,
      O => \ysqr[39]_i_7_n_0\
    );
\ysqr[39]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \dy_reg_n_0_[21]\,
      I1 => \dy_reg_n_0_[20]\,
      I2 => \dy_reg_n_0_[19]\,
      O => \ysqr[39]_i_8_n_0\
    );
\ysqr[39]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[18]\,
      I1 => \dy_reg_n_0_[21]\,
      O => \ysqr[39]_i_9_n_0\
    );
\ysqr[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \ysqr_reg[3]_i_2_n_13\,
      I1 => \ysqr_reg[3]_i_3_n_15\,
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \ysqr[3]_i_1_n_0\
    );
\ysqr[3]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \ysqr[3]_i_4_n_0\,
      I1 => \ysqr[3]_i_31_n_0\,
      I2 => \dy_reg_n_0_[2]\,
      I3 => \dy_reg_n_0_[6]\,
      O => \ysqr[3]_i_10_n_0\
    );
\ysqr[3]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \ysqr[3]_i_5_n_0\,
      I1 => \dy_reg_n_0_[5]\,
      I2 => \dy_reg_n_0_[2]\,
      I3 => \ysqr[3]_i_32_n_0\,
      I4 => \dy_reg_n_0_[0]\,
      I5 => \dy_reg_n_0_[7]\,
      O => \ysqr[3]_i_11_n_0\
    );
\ysqr[3]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \ysqr[3]_i_6_n_0\,
      I1 => \dy_reg_n_0_[4]\,
      I2 => \dy_reg_n_0_[2]\,
      I3 => \dy_reg_n_0_[5]\,
      I4 => \dy_reg_n_0_[1]\,
      I5 => \ysqr[3]_i_33_n_0\,
      O => \ysqr[3]_i_12_n_0\
    );
\ysqr[3]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \ysqr[3]_i_7_n_0\,
      I1 => \dy_reg_n_0_[4]\,
      I2 => \dy_reg_n_0_[1]\,
      I3 => \ysqr[3]_i_21_n_0\,
      I4 => \dy_reg_n_0_[0]\,
      I5 => \dy_reg_n_0_[5]\,
      O => \ysqr[3]_i_13_n_0\
    );
\ysqr[3]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dy_reg_n_0_[1]\,
      I1 => \dy_reg_n_0_[2]\,
      I2 => \dy_reg_n_0_[3]\,
      I3 => \dy_reg_n_0_[4]\,
      I4 => \dy_reg_n_0_[0]\,
      O => \ysqr[3]_i_14_n_0\
    );
\ysqr[3]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dy_reg_n_0_[3]\,
      I1 => \dy_reg_n_0_[2]\,
      I2 => \dy_reg_n_0_[0]\,
      O => \ysqr[3]_i_15_n_0\
    );
\ysqr[3]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dy_reg_n_0_[1]\,
      I1 => \dy_reg_n_0_[0]\,
      O => \ysqr[3]_i_16_n_0\
    );
\ysqr[3]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[3]\,
      I1 => \dy_reg_n_0_[7]\,
      O => \ysqr[3]_i_17_n_0\
    );
\ysqr[3]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[3]\,
      I1 => \dy_reg_n_0_[6]\,
      O => \ysqr[3]_i_18_n_0\
    );
\ysqr[3]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[2]\,
      I1 => \dy_reg_n_0_[5]\,
      O => \ysqr[3]_i_19_n_0\
    );
\ysqr[3]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"956A6A6A"
    )
        port map (
      I0 => \dy_reg_n_0_[3]\,
      I1 => \dy_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[5]\,
      I3 => \dy_reg_n_0_[2]\,
      I4 => \dy_reg_n_0_[4]\,
      O => \ysqr[3]_i_20_n_0\
    );
\ysqr[3]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[2]\,
      I1 => \dy_reg_n_0_[3]\,
      O => \ysqr[3]_i_21_n_0\
    );
\ysqr[3]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[1]\,
      I1 => \dy_reg_n_0_[3]\,
      O => \ysqr[3]_i_22_n_0\
    );
\ysqr[3]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dy_reg_n_0_[4]\,
      I1 => \dy_reg_n_0_[5]\,
      I2 => \dy_reg_n_0_[6]\,
      I3 => \dy_reg_n_0_[7]\,
      I4 => \dy_reg_n_0_[3]\,
      O => \ysqr[3]_i_23_n_0\
    );
\ysqr[3]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dy_reg_n_0_[6]\,
      I1 => \dy_reg_n_0_[5]\,
      I2 => \dy_reg_n_0_[3]\,
      O => \ysqr[3]_i_24_n_0\
    );
\ysqr[3]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dy_reg_n_0_[4]\,
      I1 => \dy_reg_n_0_[3]\,
      O => \ysqr[3]_i_25_n_0\
    );
\ysqr[3]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17A08800"
    )
        port map (
      I0 => \dy_reg_n_0_[3]\,
      I1 => \dy_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[4]\,
      I3 => \dy_reg_n_0_[5]\,
      I4 => \dy_reg_n_0_[2]\,
      O => \ysqr[3]_i_26_n_0\
    );
\ysqr[3]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"663C963C66CC66CC"
    )
        port map (
      I0 => \dy_reg_n_0_[2]\,
      I1 => \dy_reg_n_0_[3]\,
      I2 => \dy_reg_n_0_[1]\,
      I3 => \dy_reg_n_0_[4]\,
      I4 => \dy_reg_n_0_[0]\,
      I5 => \dy_reg_n_0_[5]\,
      O => \ysqr[3]_i_27_n_0\
    );
\ysqr[3]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dy_reg_n_0_[0]\,
      I1 => \dy_reg_n_0_[5]\,
      I2 => \dy_reg_n_0_[1]\,
      I3 => \dy_reg_n_0_[4]\,
      I4 => \dy_reg_n_0_[3]\,
      I5 => \dy_reg_n_0_[2]\,
      O => \ysqr[3]_i_28_n_0\
    );
\ysqr[3]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[3]\,
      I1 => \dy_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[4]\,
      I3 => \dy_reg_n_0_[0]\,
      O => \ysqr[3]_i_29_n_0\
    );
\ysqr[3]_i_30\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[0]\,
      I1 => \dy_reg_n_0_[3]\,
      O => \ysqr[3]_i_30_n_0\
    );
\ysqr[3]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[8]\,
      I1 => \dy_reg_n_0_[0]\,
      I2 => \dy_reg_n_0_[7]\,
      I3 => \dy_reg_n_0_[1]\,
      O => \ysqr[3]_i_31_n_0\
    );
\ysqr[3]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[1]\,
      I1 => \dy_reg_n_0_[6]\,
      O => \ysqr[3]_i_32_n_0\
    );
\ysqr[3]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[0]\,
      I1 => \dy_reg_n_0_[6]\,
      O => \ysqr[3]_i_33_n_0\
    );
\ysqr[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[5]\,
      I1 => \dy_reg_n_0_[2]\,
      I2 => \dy_reg_n_0_[6]\,
      I3 => \dy_reg_n_0_[1]\,
      I4 => \dy_reg_n_0_[0]\,
      I5 => \dy_reg_n_0_[7]\,
      O => \ysqr[3]_i_4_n_0\
    );
\ysqr[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[4]\,
      I1 => \dy_reg_n_0_[2]\,
      I2 => \dy_reg_n_0_[5]\,
      I3 => \dy_reg_n_0_[1]\,
      I4 => \dy_reg_n_0_[0]\,
      I5 => \dy_reg_n_0_[6]\,
      O => \ysqr[3]_i_5_n_0\
    );
\ysqr[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[4]\,
      I1 => \dy_reg_n_0_[1]\,
      I2 => \dy_reg_n_0_[3]\,
      I3 => \dy_reg_n_0_[2]\,
      I4 => \dy_reg_n_0_[0]\,
      I5 => \dy_reg_n_0_[5]\,
      O => \ysqr[3]_i_6_n_0\
    );
\ysqr[3]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[1]\,
      I1 => \dy_reg_n_0_[2]\,
      O => \ysqr[3]_i_7_n_0\
    );
\ysqr[3]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \dy_reg_n_0_[3]\,
      I1 => \dy_reg_n_0_[2]\,
      I2 => \dy_reg_n_0_[1]\,
      O => \ysqr[3]_i_8_n_0\
    );
\ysqr[3]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[0]\,
      I1 => \dy_reg_n_0_[3]\,
      O => \ysqr[3]_i_9_n_0\
    );
\ysqr[40]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(4),
      O => \ysqr[40]_i_1_n_0\
    );
\ysqr[41]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(5),
      O => \ysqr[41]_i_1_n_0\
    );
\ysqr[42]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(6),
      O => \ysqr[42]_i_1_n_0\
    );
\ysqr[43]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(7),
      O => \ysqr[43]_i_1_n_0\
    );
\ysqr[44]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(8),
      O => \ysqr[44]_i_1_n_0\
    );
\ysqr[45]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(9),
      O => \ysqr[45]_i_1_n_0\
    );
\ysqr[46]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(10),
      O => \ysqr[46]_i_1_n_0\
    );
\ysqr[47]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(11),
      O => \ysqr[47]_i_1_n_0\
    );
\ysqr[47]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[39]_i_3_n_15\,
      I1 => \ysqr_reg[39]_i_2_n_13\,
      O => \ysqr[47]_i_10_n_0\
    );
\ysqr[47]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \ysqr_reg[39]_i_3_n_9\,
      I1 => \ysqr_reg[53]_i_13_n_12\,
      I2 => \ysqr_reg[53]_i_18_n_14\,
      I3 => \ysqr_reg[53]_i_13_n_11\,
      I4 => \ysqr_reg[39]_i_3_n_8\,
      I5 => \ysqr[47]_i_19_n_0\,
      O => \ysqr[47]_i_11_n_0\
    );
\ysqr[47]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \ysqr_reg[53]_i_18_n_15\,
      I1 => \ysqr_reg[39]_i_3_n_9\,
      I2 => \ysqr_reg[53]_i_13_n_12\,
      I3 => \ysqr_reg[39]_i_3_n_8\,
      I4 => \ysqr_reg[53]_i_13_n_11\,
      I5 => \ysqr_reg[53]_i_18_n_14\,
      O => \ysqr[47]_i_12_n_0\
    );
\ysqr[47]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \ysqr_reg[53]_i_18_n_15\,
      I1 => \ysqr_reg[53]_i_13_n_12\,
      I2 => \ysqr_reg[39]_i_3_n_9\,
      I3 => \ysqr_reg[39]_i_3_n_10\,
      I4 => \ysqr_reg[39]_i_2_n_8\,
      I5 => \ysqr_reg[53]_i_13_n_13\,
      O => \ysqr[47]_i_13_n_0\
    );
\ysqr[47]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr[47]_i_6_n_0\,
      I1 => \ysqr_reg[53]_i_13_n_13\,
      I2 => \ysqr_reg[39]_i_2_n_8\,
      I3 => \ysqr_reg[39]_i_3_n_10\,
      O => \ysqr[47]_i_14_n_0\
    );
\ysqr[47]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr_reg[53]_i_13_n_14\,
      I1 => \ysqr_reg[39]_i_2_n_9\,
      I2 => \ysqr_reg[39]_i_3_n_11\,
      I3 => \ysqr[47]_i_7_n_0\,
      O => \ysqr[47]_i_15_n_0\
    );
\ysqr[47]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr_reg[53]_i_13_n_15\,
      I1 => \ysqr_reg[39]_i_2_n_10\,
      I2 => \ysqr_reg[39]_i_3_n_12\,
      I3 => \ysqr[47]_i_8_n_0\,
      O => \ysqr[47]_i_16_n_0\
    );
\ysqr[47]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \ysqr_reg[39]_i_3_n_13\,
      I1 => \ysqr_reg[39]_i_2_n_11\,
      I2 => \ysqr_reg[39]_i_2_n_12\,
      I3 => \ysqr_reg[39]_i_3_n_14\,
      O => \ysqr[47]_i_17_n_0\
    );
\ysqr[47]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ysqr_reg[39]_i_2_n_13\,
      I1 => \ysqr_reg[39]_i_3_n_15\,
      I2 => \ysqr_reg[39]_i_2_n_12\,
      I3 => \ysqr_reg[39]_i_3_n_14\,
      O => \ysqr[47]_i_18_n_0\
    );
\ysqr[47]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \ysqr_reg[53]_i_17_n_15\,
      I1 => \ysqr_reg[53]_i_13_n_10\,
      I2 => \ysqr_reg[53]_i_18_n_5\,
      O => \ysqr[47]_i_19_n_0\
    );
\ysqr[47]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \ysqr_reg[39]_i_3_n_9\,
      I1 => \ysqr_reg[53]_i_13_n_12\,
      I2 => \ysqr_reg[53]_i_18_n_14\,
      I3 => \ysqr_reg[53]_i_13_n_11\,
      I4 => \ysqr_reg[39]_i_3_n_8\,
      O => \ysqr[47]_i_3_n_0\
    );
\ysqr[47]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \ysqr_reg[53]_i_18_n_15\,
      I1 => \ysqr_reg[39]_i_3_n_9\,
      I2 => \ysqr_reg[53]_i_13_n_12\,
      O => \ysqr[47]_i_4_n_0\
    );
\ysqr[47]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \ysqr_reg[39]_i_3_n_9\,
      I1 => \ysqr_reg[53]_i_13_n_12\,
      I2 => \ysqr_reg[53]_i_18_n_15\,
      O => \ysqr[47]_i_5_n_0\
    );
\ysqr[47]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ysqr_reg[53]_i_13_n_14\,
      I1 => \ysqr_reg[39]_i_2_n_9\,
      I2 => \ysqr_reg[39]_i_3_n_11\,
      O => \ysqr[47]_i_6_n_0\
    );
\ysqr[47]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ysqr_reg[53]_i_13_n_15\,
      I1 => \ysqr_reg[39]_i_2_n_10\,
      I2 => \ysqr_reg[39]_i_3_n_12\,
      O => \ysqr[47]_i_7_n_0\
    );
\ysqr[47]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[39]_i_3_n_13\,
      I1 => \ysqr_reg[39]_i_2_n_11\,
      O => \ysqr[47]_i_8_n_0\
    );
\ysqr[47]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[39]_i_3_n_14\,
      I1 => \ysqr_reg[39]_i_2_n_12\,
      O => \ysqr[47]_i_9_n_0\
    );
\ysqr[48]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(12),
      O => \ysqr[48]_i_1_n_0\
    );
\ysqr[49]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(13),
      O => \ysqr[49]_i_1_n_0\
    );
\ysqr[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(4),
      O => \ysqr[4]_i_1_n_0\
    );
\ysqr[50]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(14),
      O => \ysqr[50]_i_1_n_0\
    );
\ysqr[51]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(15),
      O => \ysqr[51]_i_1_n_0\
    );
\ysqr[52]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(16),
      O => \ysqr[52]_i_1_n_0\
    );
\ysqr[53]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr01_in(17),
      O => \ysqr[53]_i_1_n_0\
    );
\ysqr[53]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \ysqr[53]_i_5_n_0\,
      I1 => \ysqr_reg[53]_i_3_n_15\,
      I2 => \ysqr_reg[53]_i_17_n_4\,
      I3 => \ysqr_reg[53]_i_13_n_8\,
      I4 => \ysqr_reg[53]_i_17_n_13\,
      O => \ysqr[53]_i_10_n_0\
    );
\ysqr[53]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \ysqr_reg[53]_i_17_n_14\,
      I1 => \ysqr_reg[53]_i_13_n_9\,
      I2 => \ysqr_reg[53]_i_17_n_13\,
      I3 => \ysqr_reg[53]_i_13_n_8\,
      I4 => \ysqr[53]_i_6_n_0\,
      O => \ysqr[53]_i_11_n_0\
    );
\ysqr[53]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \ysqr[53]_i_7_n_0\,
      I1 => \ysqr_reg[53]_i_17_n_15\,
      I2 => \ysqr_reg[53]_i_18_n_5\,
      I3 => \ysqr_reg[53]_i_13_n_10\,
      I4 => \ysqr_reg[53]_i_17_n_14\,
      I5 => \ysqr_reg[53]_i_13_n_9\,
      O => \ysqr[53]_i_12_n_0\
    );
\ysqr[53]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \dy_reg_n_0_[25]\,
      I1 => \dy_reg_n_0_[26]\,
      O => \ysqr[53]_i_14_n_0\
    );
\ysqr[53]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \dy_reg_n_0_[24]\,
      I1 => \dy_reg_n_0_[26]\,
      O => \ysqr[53]_i_15_n_0\
    );
\ysqr[53]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dy_reg_n_0_[25]\,
      I1 => \dy_reg_n_0_[24]\,
      O => \ysqr[53]_i_16_n_0\
    );
\ysqr[53]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7777000"
    )
        port map (
      I0 => \dy_reg_n_0_[26]\,
      I1 => \dy_reg_n_0_[22]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dy_reg_n_0_[23]\,
      I4 => \dy_reg_n_0_[24]\,
      O => \ysqr[53]_i_19_n_0\
    );
\ysqr[53]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[26]\,
      I1 => \dy_reg_n_0_[21]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dy_reg_n_0_[22]\,
      I4 => \dy_reg_n_0_[23]\,
      I5 => \dy_reg_n_0_[24]\,
      O => \ysqr[53]_i_20_n_0\
    );
\ysqr[53]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[26]\,
      I1 => \dy_reg_n_0_[20]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dy_reg_n_0_[21]\,
      I4 => \dy_reg_n_0_[22]\,
      I5 => \dy_reg_n_0_[24]\,
      O => \ysqr[53]_i_21_n_0\
    );
\ysqr[53]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[26]\,
      I1 => \dy_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dy_reg_n_0_[20]\,
      I4 => \dy_reg_n_0_[21]\,
      I5 => \dy_reg_n_0_[24]\,
      O => \ysqr[53]_i_22_n_0\
    );
\ysqr[53]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => \dy_reg_n_0_[26]\,
      I1 => \dy_reg_n_0_[18]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dy_reg_n_0_[19]\,
      O => \ysqr[53]_i_23_n_0\
    );
\ysqr[53]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[19]\,
      I1 => \dy_reg_n_0_[24]\,
      O => \ysqr[53]_i_24_n_0\
    );
\ysqr[53]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8E11F555"
    )
        port map (
      I0 => \dy_reg_n_0_[24]\,
      I1 => \dy_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[22]\,
      I3 => \dy_reg_n_0_[26]\,
      I4 => \dy_reg_n_0_[23]\,
      O => \ysqr[53]_i_25_n_0\
    );
\ysqr[53]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EB843C0C903FCF3F"
    )
        port map (
      I0 => \dy_reg_n_0_[21]\,
      I1 => \dy_reg_n_0_[23]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dy_reg_n_0_[22]\,
      I4 => \dy_reg_n_0_[26]\,
      I5 => \dy_reg_n_0_[24]\,
      O => \ysqr[53]_i_26_n_0\
    );
\ysqr[53]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F07070780F8F8F8"
    )
        port map (
      I0 => \dy_reg_n_0_[24]\,
      I1 => \dy_reg_n_0_[22]\,
      I2 => \ysqr[53]_i_43_n_0\,
      I3 => \dy_reg_n_0_[20]\,
      I4 => \dy_reg_n_0_[26]\,
      I5 => \ysqr[53]_i_44_n_0\,
      O => \ysqr[53]_i_27_n_0\
    );
\ysqr[53]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A956A956A95"
    )
        port map (
      I0 => \ysqr[53]_i_22_n_0\,
      I1 => \dy_reg_n_0_[26]\,
      I2 => \dy_reg_n_0_[20]\,
      I3 => \ysqr[53]_i_43_n_0\,
      I4 => \dy_reg_n_0_[22]\,
      I5 => \dy_reg_n_0_[24]\,
      O => \ysqr[53]_i_28_n_0\
    );
\ysqr[53]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"69C399C369336933"
    )
        port map (
      I0 => \dy_reg_n_0_[20]\,
      I1 => \ysqr[53]_i_45_n_0\,
      I2 => \dy_reg_n_0_[19]\,
      I3 => \dy_reg_n_0_[25]\,
      I4 => \dy_reg_n_0_[18]\,
      I5 => \dy_reg_n_0_[26]\,
      O => \ysqr[53]_i_29_n_0\
    );
\ysqr[53]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dy_reg_n_0_[19]\,
      I1 => \dy_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[18]\,
      I3 => \dy_reg_n_0_[26]\,
      I4 => \dy_reg_n_0_[24]\,
      I5 => \dy_reg_n_0_[20]\,
      O => \ysqr[53]_i_30_n_0\
    );
\ysqr[53]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[24]\,
      I1 => \dy_reg_n_0_[19]\,
      I2 => \dy_reg_n_0_[25]\,
      I3 => \dy_reg_n_0_[18]\,
      O => \ysqr[53]_i_31_n_0\
    );
\ysqr[53]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[18]\,
      I1 => \dy_reg_n_0_[24]\,
      O => \ysqr[53]_i_32_n_0\
    );
\ysqr[53]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[25]\,
      I1 => \dy_reg_n_0_[23]\,
      I2 => \dy_reg_n_0_[26]\,
      I3 => \dy_reg_n_0_[22]\,
      O => \ysqr[53]_i_33_n_0\
    );
\ysqr[53]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[23]\,
      I1 => \dy_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[22]\,
      I3 => \dy_reg_n_0_[26]\,
      O => \ysqr[53]_i_34_n_0\
    );
\ysqr[53]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[22]\,
      I1 => \dy_reg_n_0_[23]\,
      O => \ysqr[53]_i_35_n_0\
    );
\ysqr[53]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dy_reg_n_0_[22]\,
      I1 => \dy_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[26]\,
      I3 => \dy_reg_n_0_[23]\,
      O => \ysqr[53]_i_36_n_0\
    );
\ysqr[53]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dy_reg_n_0_[24]\,
      I1 => \dy_reg_n_0_[21]\,
      I2 => \dy_reg_n_0_[26]\,
      I3 => \dy_reg_n_0_[22]\,
      I4 => \dy_reg_n_0_[25]\,
      I5 => \dy_reg_n_0_[23]\,
      O => \ysqr[53]_i_37_n_0\
    );
\ysqr[53]_i_38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D22287772DDD8777"
    )
        port map (
      I0 => \dy_reg_n_0_[22]\,
      I1 => \dy_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[21]\,
      I3 => \dy_reg_n_0_[26]\,
      I4 => \dy_reg_n_0_[23]\,
      I5 => \dy_reg_n_0_[24]\,
      O => \ysqr[53]_i_38_n_0\
    );
\ysqr[53]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[25]\,
      I1 => \dy_reg_n_0_[20]\,
      I2 => \dy_reg_n_0_[26]\,
      I3 => \dy_reg_n_0_[19]\,
      O => \ysqr[53]_i_39_n_0\
    );
\ysqr[53]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \ysqr_reg[53]_i_17_n_13\,
      I1 => \ysqr_reg[53]_i_13_n_8\,
      I2 => \ysqr_reg[53]_i_17_n_4\,
      I3 => \ysqr_reg[53]_i_3_n_15\,
      O => \ysqr[53]_i_4_n_0\
    );
\ysqr[53]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[20]\,
      I1 => \dy_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[19]\,
      I3 => \dy_reg_n_0_[26]\,
      O => \ysqr[53]_i_40_n_0\
    );
\ysqr[53]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dy_reg_n_0_[19]\,
      I1 => \dy_reg_n_0_[25]\,
      I2 => \dy_reg_n_0_[26]\,
      I3 => \dy_reg_n_0_[20]\,
      O => \ysqr[53]_i_41_n_0\
    );
\ysqr[53]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dy_reg_n_0_[24]\,
      I1 => \dy_reg_n_0_[18]\,
      I2 => \dy_reg_n_0_[26]\,
      I3 => \dy_reg_n_0_[19]\,
      I4 => \dy_reg_n_0_[25]\,
      I5 => \dy_reg_n_0_[20]\,
      O => \ysqr[53]_i_42_n_0\
    );
\ysqr[53]_i_43\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[21]\,
      I1 => \dy_reg_n_0_[25]\,
      O => \ysqr[53]_i_43_n_0\
    );
\ysqr[53]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dy_reg_n_0_[24]\,
      I1 => \dy_reg_n_0_[23]\,
      I2 => \dy_reg_n_0_[26]\,
      I3 => \dy_reg_n_0_[21]\,
      I4 => \dy_reg_n_0_[25]\,
      I5 => \dy_reg_n_0_[22]\,
      O => \ysqr[53]_i_44_n_0\
    );
\ysqr[53]_i_45\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[21]\,
      I1 => \dy_reg_n_0_[24]\,
      O => \ysqr[53]_i_45_n_0\
    );
\ysqr[53]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \ysqr_reg[53]_i_17_n_14\,
      I1 => \ysqr_reg[53]_i_13_n_9\,
      I2 => \ysqr_reg[53]_i_17_n_13\,
      I3 => \ysqr_reg[53]_i_13_n_8\,
      O => \ysqr[53]_i_5_n_0\
    );
\ysqr[53]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \ysqr_reg[53]_i_17_n_14\,
      I1 => \ysqr_reg[53]_i_13_n_9\,
      I2 => \ysqr_reg[53]_i_17_n_15\,
      I3 => \ysqr_reg[53]_i_18_n_5\,
      I4 => \ysqr_reg[53]_i_13_n_10\,
      O => \ysqr[53]_i_6_n_0\
    );
\ysqr[53]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \ysqr_reg[39]_i_3_n_8\,
      I1 => \ysqr_reg[53]_i_18_n_14\,
      I2 => \ysqr_reg[53]_i_13_n_11\,
      I3 => \ysqr_reg[53]_i_18_n_5\,
      I4 => \ysqr_reg[53]_i_13_n_10\,
      I5 => \ysqr_reg[53]_i_17_n_15\,
      O => \ysqr[53]_i_7_n_0\
    );
\ysqr[53]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \ysqr_reg[53]_i_3_n_15\,
      I1 => \ysqr_reg[53]_i_17_n_4\,
      I2 => \ysqr_reg[53]_i_3_n_14\,
      I3 => \ysqr_reg[53]_i_3_n_13\,
      O => \ysqr[53]_i_8_n_0\
    );
\ysqr[53]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \ysqr_reg[53]_i_13_n_8\,
      I1 => \ysqr_reg[53]_i_17_n_13\,
      I2 => \ysqr_reg[53]_i_3_n_15\,
      I3 => \ysqr_reg[53]_i_17_n_4\,
      I4 => \ysqr_reg[53]_i_3_n_14\,
      O => \ysqr[53]_i_9_n_0\
    );
\ysqr[54]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => \dy_reg_n_0_[27]\,
      O => \ysqr[54]_i_1_n_0\
    );
\ysqr[56]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(2),
      O => \ysqr[56]_i_1_n_0\
    );
\ysqr[57]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \ysqr_reg[57]_i_2_n_13\,
      I1 => \ysqr_reg[57]_i_3_n_15\,
      I2 => \stateScore_reg_rep__7_n_0\,
      O => \ysqr[57]_i_1_n_0\
    );
\ysqr[57]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \ysqr[57]_i_4_n_0\,
      I1 => \ysqr[57]_i_31_n_0\,
      I2 => \dy_reg_n_0_[29]\,
      I3 => \dy_reg_n_0_[33]\,
      O => \ysqr[57]_i_10_n_0\
    );
\ysqr[57]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \ysqr[57]_i_5_n_0\,
      I1 => \dy_reg_n_0_[32]\,
      I2 => \dy_reg_n_0_[29]\,
      I3 => \ysqr[57]_i_32_n_0\,
      I4 => \dy_reg_n_0_[27]\,
      I5 => \dy_reg_n_0_[34]\,
      O => \ysqr[57]_i_11_n_0\
    );
\ysqr[57]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \ysqr[57]_i_6_n_0\,
      I1 => \dy_reg_n_0_[31]\,
      I2 => \dy_reg_n_0_[29]\,
      I3 => \dy_reg_n_0_[32]\,
      I4 => \dy_reg_n_0_[28]\,
      I5 => \ysqr[57]_i_33_n_0\,
      O => \ysqr[57]_i_12_n_0\
    );
\ysqr[57]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \ysqr[57]_i_7_n_0\,
      I1 => \dy_reg_n_0_[31]\,
      I2 => \dy_reg_n_0_[28]\,
      I3 => \ysqr[57]_i_21_n_0\,
      I4 => \dy_reg_n_0_[27]\,
      I5 => \dy_reg_n_0_[32]\,
      O => \ysqr[57]_i_13_n_0\
    );
\ysqr[57]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dy_reg_n_0_[28]\,
      I1 => \dy_reg_n_0_[29]\,
      I2 => \dy_reg_n_0_[30]\,
      I3 => \dy_reg_n_0_[31]\,
      I4 => \dy_reg_n_0_[27]\,
      O => \ysqr[57]_i_14_n_0\
    );
\ysqr[57]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dy_reg_n_0_[30]\,
      I1 => \dy_reg_n_0_[29]\,
      I2 => \dy_reg_n_0_[27]\,
      O => \ysqr[57]_i_15_n_0\
    );
\ysqr[57]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dy_reg_n_0_[28]\,
      I1 => \dy_reg_n_0_[27]\,
      O => \ysqr[57]_i_16_n_0\
    );
\ysqr[57]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[30]\,
      I1 => \dy_reg_n_0_[34]\,
      O => \ysqr[57]_i_17_n_0\
    );
\ysqr[57]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[30]\,
      I1 => \dy_reg_n_0_[33]\,
      O => \ysqr[57]_i_18_n_0\
    );
\ysqr[57]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[29]\,
      I1 => \dy_reg_n_0_[32]\,
      O => \ysqr[57]_i_19_n_0\
    );
\ysqr[57]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"956A6A6A"
    )
        port map (
      I0 => \dy_reg_n_0_[30]\,
      I1 => \dy_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[32]\,
      I3 => \dy_reg_n_0_[29]\,
      I4 => \dy_reg_n_0_[31]\,
      O => \ysqr[57]_i_20_n_0\
    );
\ysqr[57]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[29]\,
      I1 => \dy_reg_n_0_[30]\,
      O => \ysqr[57]_i_21_n_0\
    );
\ysqr[57]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[28]\,
      I1 => \dy_reg_n_0_[30]\,
      O => \ysqr[57]_i_22_n_0\
    );
\ysqr[57]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dy_reg_n_0_[31]\,
      I1 => \dy_reg_n_0_[32]\,
      I2 => \dy_reg_n_0_[33]\,
      I3 => \dy_reg_n_0_[34]\,
      I4 => \dy_reg_n_0_[30]\,
      O => \ysqr[57]_i_23_n_0\
    );
\ysqr[57]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dy_reg_n_0_[33]\,
      I1 => \dy_reg_n_0_[32]\,
      I2 => \dy_reg_n_0_[30]\,
      O => \ysqr[57]_i_24_n_0\
    );
\ysqr[57]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dy_reg_n_0_[31]\,
      I1 => \dy_reg_n_0_[30]\,
      O => \ysqr[57]_i_25_n_0\
    );
\ysqr[57]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17A08800"
    )
        port map (
      I0 => \dy_reg_n_0_[30]\,
      I1 => \dy_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[31]\,
      I3 => \dy_reg_n_0_[32]\,
      I4 => \dy_reg_n_0_[29]\,
      O => \ysqr[57]_i_26_n_0\
    );
\ysqr[57]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"663C963C66CC66CC"
    )
        port map (
      I0 => \dy_reg_n_0_[29]\,
      I1 => \dy_reg_n_0_[30]\,
      I2 => \dy_reg_n_0_[28]\,
      I3 => \dy_reg_n_0_[31]\,
      I4 => \dy_reg_n_0_[27]\,
      I5 => \dy_reg_n_0_[32]\,
      O => \ysqr[57]_i_27_n_0\
    );
\ysqr[57]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dy_reg_n_0_[27]\,
      I1 => \dy_reg_n_0_[32]\,
      I2 => \dy_reg_n_0_[28]\,
      I3 => \dy_reg_n_0_[31]\,
      I4 => \dy_reg_n_0_[30]\,
      I5 => \dy_reg_n_0_[29]\,
      O => \ysqr[57]_i_28_n_0\
    );
\ysqr[57]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[30]\,
      I1 => \dy_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[31]\,
      I3 => \dy_reg_n_0_[27]\,
      O => \ysqr[57]_i_29_n_0\
    );
\ysqr[57]_i_30\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[27]\,
      I1 => \dy_reg_n_0_[30]\,
      O => \ysqr[57]_i_30_n_0\
    );
\ysqr[57]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[35]\,
      I1 => \dy_reg_n_0_[27]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dy_reg_n_0_[28]\,
      O => \ysqr[57]_i_31_n_0\
    );
\ysqr[57]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[28]\,
      I1 => \dy_reg_n_0_[33]\,
      O => \ysqr[57]_i_32_n_0\
    );
\ysqr[57]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[27]\,
      I1 => \dy_reg_n_0_[33]\,
      O => \ysqr[57]_i_33_n_0\
    );
\ysqr[57]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[32]\,
      I1 => \dy_reg_n_0_[29]\,
      I2 => \dy_reg_n_0_[33]\,
      I3 => \dy_reg_n_0_[28]\,
      I4 => \dy_reg_n_0_[27]\,
      I5 => \dy_reg_n_0_[34]\,
      O => \ysqr[57]_i_4_n_0\
    );
\ysqr[57]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[31]\,
      I1 => \dy_reg_n_0_[29]\,
      I2 => \dy_reg_n_0_[32]\,
      I3 => \dy_reg_n_0_[28]\,
      I4 => \dy_reg_n_0_[27]\,
      I5 => \dy_reg_n_0_[33]\,
      O => \ysqr[57]_i_5_n_0\
    );
\ysqr[57]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[31]\,
      I1 => \dy_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[30]\,
      I3 => \dy_reg_n_0_[29]\,
      I4 => \dy_reg_n_0_[27]\,
      I5 => \dy_reg_n_0_[32]\,
      O => \ysqr[57]_i_6_n_0\
    );
\ysqr[57]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[28]\,
      I1 => \dy_reg_n_0_[29]\,
      O => \ysqr[57]_i_7_n_0\
    );
\ysqr[57]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \dy_reg_n_0_[30]\,
      I1 => \dy_reg_n_0_[29]\,
      I2 => \dy_reg_n_0_[28]\,
      O => \ysqr[57]_i_8_n_0\
    );
\ysqr[57]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[27]\,
      I1 => \dy_reg_n_0_[30]\,
      O => \ysqr[57]_i_9_n_0\
    );
\ysqr[58]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(4),
      O => \ysqr[58]_i_1_n_0\
    );
\ysqr[59]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(5),
      O => \ysqr[59]_i_1_n_0\
    );
\ysqr[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(5),
      O => \ysqr[5]_i_1_n_0\
    );
\ysqr[60]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(6),
      O => \ysqr[60]_i_1_n_0\
    );
\ysqr[61]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(7),
      O => \ysqr[61]_i_1_n_0\
    );
\ysqr[62]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(8),
      O => \ysqr[62]_i_1_n_0\
    );
\ysqr[63]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(9),
      O => \ysqr[63]_i_1_n_0\
    );
\ysqr[64]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(10),
      O => \ysqr[64]_i_1_n_0\
    );
\ysqr[65]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(11),
      O => \ysqr[65]_i_1_n_0\
    );
\ysqr[65]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[57]_i_3_n_15\,
      I1 => \ysqr_reg[57]_i_2_n_13\,
      O => \ysqr[65]_i_10_n_0\
    );
\ysqr[65]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \ysqr_reg[57]_i_3_n_9\,
      I1 => \ysqr_reg[71]_i_13_n_12\,
      I2 => \ysqr_reg[71]_i_18_n_14\,
      I3 => \ysqr_reg[71]_i_13_n_11\,
      I4 => \ysqr_reg[57]_i_3_n_8\,
      I5 => \ysqr[65]_i_19_n_0\,
      O => \ysqr[65]_i_11_n_0\
    );
\ysqr[65]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \ysqr_reg[71]_i_18_n_15\,
      I1 => \ysqr_reg[57]_i_3_n_9\,
      I2 => \ysqr_reg[71]_i_13_n_12\,
      I3 => \ysqr_reg[57]_i_3_n_8\,
      I4 => \ysqr_reg[71]_i_13_n_11\,
      I5 => \ysqr_reg[71]_i_18_n_14\,
      O => \ysqr[65]_i_12_n_0\
    );
\ysqr[65]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \ysqr_reg[71]_i_18_n_15\,
      I1 => \ysqr_reg[71]_i_13_n_12\,
      I2 => \ysqr_reg[57]_i_3_n_9\,
      I3 => \ysqr_reg[57]_i_3_n_10\,
      I4 => \ysqr_reg[57]_i_2_n_8\,
      I5 => \ysqr_reg[71]_i_13_n_13\,
      O => \ysqr[65]_i_13_n_0\
    );
\ysqr[65]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr[65]_i_6_n_0\,
      I1 => \ysqr_reg[71]_i_13_n_13\,
      I2 => \ysqr_reg[57]_i_2_n_8\,
      I3 => \ysqr_reg[57]_i_3_n_10\,
      O => \ysqr[65]_i_14_n_0\
    );
\ysqr[65]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr_reg[71]_i_13_n_14\,
      I1 => \ysqr_reg[57]_i_2_n_9\,
      I2 => \ysqr_reg[57]_i_3_n_11\,
      I3 => \ysqr[65]_i_7_n_0\,
      O => \ysqr[65]_i_15_n_0\
    );
\ysqr[65]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr_reg[71]_i_13_n_15\,
      I1 => \ysqr_reg[57]_i_2_n_10\,
      I2 => \ysqr_reg[57]_i_3_n_12\,
      I3 => \ysqr[65]_i_8_n_0\,
      O => \ysqr[65]_i_16_n_0\
    );
\ysqr[65]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \ysqr_reg[57]_i_3_n_13\,
      I1 => \ysqr_reg[57]_i_2_n_11\,
      I2 => \ysqr_reg[57]_i_2_n_12\,
      I3 => \ysqr_reg[57]_i_3_n_14\,
      O => \ysqr[65]_i_17_n_0\
    );
\ysqr[65]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ysqr_reg[57]_i_2_n_13\,
      I1 => \ysqr_reg[57]_i_3_n_15\,
      I2 => \ysqr_reg[57]_i_2_n_12\,
      I3 => \ysqr_reg[57]_i_3_n_14\,
      O => \ysqr[65]_i_18_n_0\
    );
\ysqr[65]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \ysqr_reg[71]_i_17_n_15\,
      I1 => \ysqr_reg[71]_i_13_n_10\,
      I2 => \ysqr_reg[71]_i_18_n_5\,
      O => \ysqr[65]_i_19_n_0\
    );
\ysqr[65]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \ysqr_reg[57]_i_3_n_9\,
      I1 => \ysqr_reg[71]_i_13_n_12\,
      I2 => \ysqr_reg[71]_i_18_n_14\,
      I3 => \ysqr_reg[71]_i_13_n_11\,
      I4 => \ysqr_reg[57]_i_3_n_8\,
      O => \ysqr[65]_i_3_n_0\
    );
\ysqr[65]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \ysqr_reg[71]_i_18_n_15\,
      I1 => \ysqr_reg[57]_i_3_n_9\,
      I2 => \ysqr_reg[71]_i_13_n_12\,
      O => \ysqr[65]_i_4_n_0\
    );
\ysqr[65]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \ysqr_reg[57]_i_3_n_9\,
      I1 => \ysqr_reg[71]_i_13_n_12\,
      I2 => \ysqr_reg[71]_i_18_n_15\,
      O => \ysqr[65]_i_5_n_0\
    );
\ysqr[65]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ysqr_reg[71]_i_13_n_14\,
      I1 => \ysqr_reg[57]_i_2_n_9\,
      I2 => \ysqr_reg[57]_i_3_n_11\,
      O => \ysqr[65]_i_6_n_0\
    );
\ysqr[65]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ysqr_reg[71]_i_13_n_15\,
      I1 => \ysqr_reg[57]_i_2_n_10\,
      I2 => \ysqr_reg[57]_i_3_n_12\,
      O => \ysqr[65]_i_7_n_0\
    );
\ysqr[65]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[57]_i_3_n_13\,
      I1 => \ysqr_reg[57]_i_2_n_11\,
      O => \ysqr[65]_i_8_n_0\
    );
\ysqr[65]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[57]_i_3_n_14\,
      I1 => \ysqr_reg[57]_i_2_n_12\,
      O => \ysqr[65]_i_9_n_0\
    );
\ysqr[66]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(12),
      O => \ysqr[66]_i_1_n_0\
    );
\ysqr[67]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(13),
      O => \ysqr[67]_i_1_n_0\
    );
\ysqr[68]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(14),
      O => \ysqr[68]_i_1_n_0\
    );
\ysqr[69]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(15),
      O => \ysqr[69]_i_1_n_0\
    );
\ysqr[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(6),
      O => \ysqr[6]_i_1_n_0\
    );
\ysqr[70]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(16),
      O => \ysqr[70]_i_1_n_0\
    );
\ysqr[71]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr02_in(17),
      O => \ysqr[71]_i_1_n_0\
    );
\ysqr[71]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \ysqr[71]_i_5_n_0\,
      I1 => \ysqr_reg[71]_i_3_n_15\,
      I2 => \ysqr_reg[71]_i_17_n_4\,
      I3 => \ysqr_reg[71]_i_13_n_8\,
      I4 => \ysqr_reg[71]_i_17_n_13\,
      O => \ysqr[71]_i_10_n_0\
    );
\ysqr[71]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \ysqr_reg[71]_i_17_n_14\,
      I1 => \ysqr_reg[71]_i_13_n_9\,
      I2 => \ysqr_reg[71]_i_17_n_13\,
      I3 => \ysqr_reg[71]_i_13_n_8\,
      I4 => \ysqr[71]_i_6_n_0\,
      O => \ysqr[71]_i_11_n_0\
    );
\ysqr[71]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \ysqr[71]_i_7_n_0\,
      I1 => \ysqr_reg[71]_i_17_n_15\,
      I2 => \ysqr_reg[71]_i_18_n_5\,
      I3 => \ysqr_reg[71]_i_13_n_10\,
      I4 => \ysqr_reg[71]_i_17_n_14\,
      I5 => \ysqr_reg[71]_i_13_n_9\,
      O => \ysqr[71]_i_12_n_0\
    );
\ysqr[71]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \dy_reg_n_0_[34]\,
      I1 => \dy_reg_n_0_[35]\,
      O => \ysqr[71]_i_14_n_0\
    );
\ysqr[71]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \dy_reg_n_0_[33]\,
      I1 => \dy_reg_n_0_[35]\,
      O => \ysqr[71]_i_15_n_0\
    );
\ysqr[71]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dy_reg_n_0_[34]\,
      I1 => \dy_reg_n_0_[33]\,
      O => \ysqr[71]_i_16_n_0\
    );
\ysqr[71]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7777000"
    )
        port map (
      I0 => \dy_reg_n_0_[35]\,
      I1 => \dy_reg_n_0_[31]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dy_reg_n_0_[32]\,
      I4 => \dy_reg_n_0_[33]\,
      O => \ysqr[71]_i_19_n_0\
    );
\ysqr[71]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[35]\,
      I1 => \dy_reg_n_0_[30]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dy_reg_n_0_[31]\,
      I4 => \dy_reg_n_0_[32]\,
      I5 => \dy_reg_n_0_[33]\,
      O => \ysqr[71]_i_20_n_0\
    );
\ysqr[71]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[35]\,
      I1 => \dy_reg_n_0_[29]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dy_reg_n_0_[30]\,
      I4 => \dy_reg_n_0_[31]\,
      I5 => \dy_reg_n_0_[33]\,
      O => \ysqr[71]_i_21_n_0\
    );
\ysqr[71]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[35]\,
      I1 => \dy_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dy_reg_n_0_[29]\,
      I4 => \dy_reg_n_0_[30]\,
      I5 => \dy_reg_n_0_[33]\,
      O => \ysqr[71]_i_22_n_0\
    );
\ysqr[71]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => \dy_reg_n_0_[35]\,
      I1 => \dy_reg_n_0_[27]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dy_reg_n_0_[28]\,
      O => \ysqr[71]_i_23_n_0\
    );
\ysqr[71]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[28]\,
      I1 => \dy_reg_n_0_[33]\,
      O => \ysqr[71]_i_24_n_0\
    );
\ysqr[71]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8E11F555"
    )
        port map (
      I0 => \dy_reg_n_0_[33]\,
      I1 => \dy_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[31]\,
      I3 => \dy_reg_n_0_[35]\,
      I4 => \dy_reg_n_0_[32]\,
      O => \ysqr[71]_i_25_n_0\
    );
\ysqr[71]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EB843C0C903FCF3F"
    )
        port map (
      I0 => \dy_reg_n_0_[30]\,
      I1 => \dy_reg_n_0_[32]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dy_reg_n_0_[31]\,
      I4 => \dy_reg_n_0_[35]\,
      I5 => \dy_reg_n_0_[33]\,
      O => \ysqr[71]_i_26_n_0\
    );
\ysqr[71]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F07070780F8F8F8"
    )
        port map (
      I0 => \dy_reg_n_0_[33]\,
      I1 => \dy_reg_n_0_[31]\,
      I2 => \ysqr[71]_i_43_n_0\,
      I3 => \dy_reg_n_0_[29]\,
      I4 => \dy_reg_n_0_[35]\,
      I5 => \ysqr[71]_i_44_n_0\,
      O => \ysqr[71]_i_27_n_0\
    );
\ysqr[71]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A956A956A95"
    )
        port map (
      I0 => \ysqr[71]_i_22_n_0\,
      I1 => \dy_reg_n_0_[35]\,
      I2 => \dy_reg_n_0_[29]\,
      I3 => \ysqr[71]_i_43_n_0\,
      I4 => \dy_reg_n_0_[31]\,
      I5 => \dy_reg_n_0_[33]\,
      O => \ysqr[71]_i_28_n_0\
    );
\ysqr[71]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"69C399C369336933"
    )
        port map (
      I0 => \dy_reg_n_0_[29]\,
      I1 => \ysqr[71]_i_45_n_0\,
      I2 => \dy_reg_n_0_[28]\,
      I3 => \dy_reg_n_0_[34]\,
      I4 => \dy_reg_n_0_[27]\,
      I5 => \dy_reg_n_0_[35]\,
      O => \ysqr[71]_i_29_n_0\
    );
\ysqr[71]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dy_reg_n_0_[28]\,
      I1 => \dy_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[27]\,
      I3 => \dy_reg_n_0_[35]\,
      I4 => \dy_reg_n_0_[33]\,
      I5 => \dy_reg_n_0_[29]\,
      O => \ysqr[71]_i_30_n_0\
    );
\ysqr[71]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[33]\,
      I1 => \dy_reg_n_0_[28]\,
      I2 => \dy_reg_n_0_[34]\,
      I3 => \dy_reg_n_0_[27]\,
      O => \ysqr[71]_i_31_n_0\
    );
\ysqr[71]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[27]\,
      I1 => \dy_reg_n_0_[33]\,
      O => \ysqr[71]_i_32_n_0\
    );
\ysqr[71]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[34]\,
      I1 => \dy_reg_n_0_[32]\,
      I2 => \dy_reg_n_0_[35]\,
      I3 => \dy_reg_n_0_[31]\,
      O => \ysqr[71]_i_33_n_0\
    );
\ysqr[71]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[32]\,
      I1 => \dy_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[31]\,
      I3 => \dy_reg_n_0_[35]\,
      O => \ysqr[71]_i_34_n_0\
    );
\ysqr[71]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[31]\,
      I1 => \dy_reg_n_0_[32]\,
      O => \ysqr[71]_i_35_n_0\
    );
\ysqr[71]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dy_reg_n_0_[31]\,
      I1 => \dy_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[35]\,
      I3 => \dy_reg_n_0_[32]\,
      O => \ysqr[71]_i_36_n_0\
    );
\ysqr[71]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dy_reg_n_0_[33]\,
      I1 => \dy_reg_n_0_[30]\,
      I2 => \dy_reg_n_0_[35]\,
      I3 => \dy_reg_n_0_[31]\,
      I4 => \dy_reg_n_0_[34]\,
      I5 => \dy_reg_n_0_[32]\,
      O => \ysqr[71]_i_37_n_0\
    );
\ysqr[71]_i_38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D22287772DDD8777"
    )
        port map (
      I0 => \dy_reg_n_0_[31]\,
      I1 => \dy_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[30]\,
      I3 => \dy_reg_n_0_[35]\,
      I4 => \dy_reg_n_0_[32]\,
      I5 => \dy_reg_n_0_[33]\,
      O => \ysqr[71]_i_38_n_0\
    );
\ysqr[71]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[34]\,
      I1 => \dy_reg_n_0_[29]\,
      I2 => \dy_reg_n_0_[35]\,
      I3 => \dy_reg_n_0_[28]\,
      O => \ysqr[71]_i_39_n_0\
    );
\ysqr[71]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \ysqr_reg[71]_i_17_n_13\,
      I1 => \ysqr_reg[71]_i_13_n_8\,
      I2 => \ysqr_reg[71]_i_17_n_4\,
      I3 => \ysqr_reg[71]_i_3_n_15\,
      O => \ysqr[71]_i_4_n_0\
    );
\ysqr[71]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[29]\,
      I1 => \dy_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[28]\,
      I3 => \dy_reg_n_0_[35]\,
      O => \ysqr[71]_i_40_n_0\
    );
\ysqr[71]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dy_reg_n_0_[28]\,
      I1 => \dy_reg_n_0_[34]\,
      I2 => \dy_reg_n_0_[35]\,
      I3 => \dy_reg_n_0_[29]\,
      O => \ysqr[71]_i_41_n_0\
    );
\ysqr[71]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dy_reg_n_0_[33]\,
      I1 => \dy_reg_n_0_[27]\,
      I2 => \dy_reg_n_0_[35]\,
      I3 => \dy_reg_n_0_[28]\,
      I4 => \dy_reg_n_0_[34]\,
      I5 => \dy_reg_n_0_[29]\,
      O => \ysqr[71]_i_42_n_0\
    );
\ysqr[71]_i_43\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[30]\,
      I1 => \dy_reg_n_0_[34]\,
      O => \ysqr[71]_i_43_n_0\
    );
\ysqr[71]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dy_reg_n_0_[33]\,
      I1 => \dy_reg_n_0_[32]\,
      I2 => \dy_reg_n_0_[35]\,
      I3 => \dy_reg_n_0_[30]\,
      I4 => \dy_reg_n_0_[34]\,
      I5 => \dy_reg_n_0_[31]\,
      O => \ysqr[71]_i_44_n_0\
    );
\ysqr[71]_i_45\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[30]\,
      I1 => \dy_reg_n_0_[33]\,
      O => \ysqr[71]_i_45_n_0\
    );
\ysqr[71]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \ysqr_reg[71]_i_17_n_14\,
      I1 => \ysqr_reg[71]_i_13_n_9\,
      I2 => \ysqr_reg[71]_i_17_n_13\,
      I3 => \ysqr_reg[71]_i_13_n_8\,
      O => \ysqr[71]_i_5_n_0\
    );
\ysqr[71]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \ysqr_reg[71]_i_17_n_14\,
      I1 => \ysqr_reg[71]_i_13_n_9\,
      I2 => \ysqr_reg[71]_i_17_n_15\,
      I3 => \ysqr_reg[71]_i_18_n_5\,
      I4 => \ysqr_reg[71]_i_13_n_10\,
      O => \ysqr[71]_i_6_n_0\
    );
\ysqr[71]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \ysqr_reg[57]_i_3_n_8\,
      I1 => \ysqr_reg[71]_i_18_n_14\,
      I2 => \ysqr_reg[71]_i_13_n_11\,
      I3 => \ysqr_reg[71]_i_18_n_5\,
      I4 => \ysqr_reg[71]_i_13_n_10\,
      I5 => \ysqr_reg[71]_i_17_n_15\,
      O => \ysqr[71]_i_7_n_0\
    );
\ysqr[71]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \ysqr_reg[71]_i_3_n_15\,
      I1 => \ysqr_reg[71]_i_17_n_4\,
      I2 => \ysqr_reg[71]_i_3_n_14\,
      I3 => \ysqr_reg[71]_i_3_n_13\,
      O => \ysqr[71]_i_8_n_0\
    );
\ysqr[71]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \ysqr_reg[71]_i_13_n_8\,
      I1 => \ysqr_reg[71]_i_17_n_13\,
      I2 => \ysqr_reg[71]_i_3_n_15\,
      I3 => \ysqr_reg[71]_i_17_n_4\,
      I4 => \ysqr_reg[71]_i_3_n_14\,
      O => \ysqr[71]_i_9_n_0\
    );
\ysqr[72]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => \dy_reg_n_0_[36]\,
      O => \ysqr[72]_i_1_n_0\
    );
\ysqr[74]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr03_in(2),
      O => \ysqr[74]_i_1_n_0\
    );
\ysqr[75]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \ysqr_reg[75]_i_2_n_13\,
      I1 => \ysqr_reg[75]_i_3_n_15\,
      I2 => \stateScore_reg_rep__8_n_0\,
      O => \ysqr[75]_i_1_n_0\
    );
\ysqr[75]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \ysqr[75]_i_4_n_0\,
      I1 => \ysqr[75]_i_31_n_0\,
      I2 => \dy_reg_n_0_[38]\,
      I3 => \dy_reg_n_0_[42]\,
      O => \ysqr[75]_i_10_n_0\
    );
\ysqr[75]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \ysqr[75]_i_5_n_0\,
      I1 => \dy_reg_n_0_[41]\,
      I2 => \dy_reg_n_0_[38]\,
      I3 => \ysqr[75]_i_32_n_0\,
      I4 => \dy_reg_n_0_[36]\,
      I5 => \dy_reg_n_0_[43]\,
      O => \ysqr[75]_i_11_n_0\
    );
\ysqr[75]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A959595956A6A6A"
    )
        port map (
      I0 => \ysqr[75]_i_6_n_0\,
      I1 => \dy_reg_n_0_[40]\,
      I2 => \dy_reg_n_0_[38]\,
      I3 => \dy_reg_n_0_[41]\,
      I4 => \dy_reg_n_0_[37]\,
      I5 => \ysqr[75]_i_33_n_0\,
      O => \ysqr[75]_i_12_n_0\
    );
\ysqr[75]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A95956A956A956A"
    )
        port map (
      I0 => \ysqr[75]_i_7_n_0\,
      I1 => \dy_reg_n_0_[40]\,
      I2 => \dy_reg_n_0_[37]\,
      I3 => \ysqr[75]_i_21_n_0\,
      I4 => \dy_reg_n_0_[36]\,
      I5 => \dy_reg_n_0_[41]\,
      O => \ysqr[75]_i_13_n_0\
    );
\ysqr[75]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dy_reg_n_0_[37]\,
      I1 => \dy_reg_n_0_[38]\,
      I2 => \dy_reg_n_0_[39]\,
      I3 => \dy_reg_n_0_[40]\,
      I4 => \dy_reg_n_0_[36]\,
      O => \ysqr[75]_i_14_n_0\
    );
\ysqr[75]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dy_reg_n_0_[39]\,
      I1 => \dy_reg_n_0_[38]\,
      I2 => \dy_reg_n_0_[36]\,
      O => \ysqr[75]_i_15_n_0\
    );
\ysqr[75]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dy_reg_n_0_[37]\,
      I1 => \dy_reg_n_0_[36]\,
      O => \ysqr[75]_i_16_n_0\
    );
\ysqr[75]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[39]\,
      I1 => \dy_reg_n_0_[43]\,
      O => \ysqr[75]_i_17_n_0\
    );
\ysqr[75]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[39]\,
      I1 => \dy_reg_n_0_[42]\,
      O => \ysqr[75]_i_18_n_0\
    );
\ysqr[75]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[38]\,
      I1 => \dy_reg_n_0_[41]\,
      O => \ysqr[75]_i_19_n_0\
    );
\ysqr[75]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"956A6A6A"
    )
        port map (
      I0 => \dy_reg_n_0_[39]\,
      I1 => \dy_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[41]\,
      I3 => \dy_reg_n_0_[38]\,
      I4 => \dy_reg_n_0_[40]\,
      O => \ysqr[75]_i_20_n_0\
    );
\ysqr[75]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[38]\,
      I1 => \dy_reg_n_0_[39]\,
      O => \ysqr[75]_i_21_n_0\
    );
\ysqr[75]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[37]\,
      I1 => \dy_reg_n_0_[39]\,
      O => \ysqr[75]_i_22_n_0\
    );
\ysqr[75]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1BE4E4E4"
    )
        port map (
      I0 => \dy_reg_n_0_[40]\,
      I1 => \dy_reg_n_0_[41]\,
      I2 => \dy_reg_n_0_[42]\,
      I3 => \dy_reg_n_0_[43]\,
      I4 => \dy_reg_n_0_[39]\,
      O => \ysqr[75]_i_23_n_0\
    );
\ysqr[75]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \dy_reg_n_0_[42]\,
      I1 => \dy_reg_n_0_[41]\,
      I2 => \dy_reg_n_0_[39]\,
      O => \ysqr[75]_i_24_n_0\
    );
\ysqr[75]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dy_reg_n_0_[40]\,
      I1 => \dy_reg_n_0_[39]\,
      O => \ysqr[75]_i_25_n_0\
    );
\ysqr[75]_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17A0C000"
    )
        port map (
      I0 => \dy_reg_n_0_[40]\,
      I1 => \dy_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[39]\,
      I3 => \dy_reg_n_0_[41]\,
      I4 => \dy_reg_n_0_[38]\,
      O => \ysqr[75]_i_26_n_0\
    );
\ysqr[75]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"663C963C66CC66CC"
    )
        port map (
      I0 => \dy_reg_n_0_[38]\,
      I1 => \dy_reg_n_0_[39]\,
      I2 => \dy_reg_n_0_[37]\,
      I3 => \dy_reg_n_0_[40]\,
      I4 => \dy_reg_n_0_[36]\,
      I5 => \dy_reg_n_0_[41]\,
      O => \ysqr[75]_i_27_n_0\
    );
\ysqr[75]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8777788878887888"
    )
        port map (
      I0 => \dy_reg_n_0_[36]\,
      I1 => \dy_reg_n_0_[41]\,
      I2 => \dy_reg_n_0_[37]\,
      I3 => \dy_reg_n_0_[40]\,
      I4 => \dy_reg_n_0_[39]\,
      I5 => \dy_reg_n_0_[38]\,
      O => \ysqr[75]_i_28_n_0\
    );
\ysqr[75]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[39]\,
      I1 => \dy_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[40]\,
      I3 => \dy_reg_n_0_[36]\,
      O => \ysqr[75]_i_29_n_0\
    );
\ysqr[75]_i_30\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[36]\,
      I1 => \dy_reg_n_0_[39]\,
      O => \ysqr[75]_i_30_n_0\
    );
\ysqr[75]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[44]\,
      I1 => \dy_reg_n_0_[36]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dy_reg_n_0_[37]\,
      O => \ysqr[75]_i_31_n_0\
    );
\ysqr[75]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[37]\,
      I1 => \dy_reg_n_0_[42]\,
      O => \ysqr[75]_i_32_n_0\
    );
\ysqr[75]_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[36]\,
      I1 => \dy_reg_n_0_[42]\,
      O => \ysqr[75]_i_33_n_0\
    );
\ysqr[75]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[41]\,
      I1 => \dy_reg_n_0_[38]\,
      I2 => \dy_reg_n_0_[42]\,
      I3 => \dy_reg_n_0_[37]\,
      I4 => \dy_reg_n_0_[36]\,
      I5 => \dy_reg_n_0_[43]\,
      O => \ysqr[75]_i_4_n_0\
    );
\ysqr[75]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[40]\,
      I1 => \dy_reg_n_0_[38]\,
      I2 => \dy_reg_n_0_[41]\,
      I3 => \dy_reg_n_0_[37]\,
      I4 => \dy_reg_n_0_[36]\,
      I5 => \dy_reg_n_0_[42]\,
      O => \ysqr[75]_i_5_n_0\
    );
\ysqr[75]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888800080008000"
    )
        port map (
      I0 => \dy_reg_n_0_[40]\,
      I1 => \dy_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[39]\,
      I3 => \dy_reg_n_0_[38]\,
      I4 => \dy_reg_n_0_[36]\,
      I5 => \dy_reg_n_0_[41]\,
      O => \ysqr[75]_i_6_n_0\
    );
\ysqr[75]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[37]\,
      I1 => \dy_reg_n_0_[38]\,
      O => \ysqr[75]_i_7_n_0\
    );
\ysqr[75]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \dy_reg_n_0_[39]\,
      I1 => \dy_reg_n_0_[38]\,
      I2 => \dy_reg_n_0_[37]\,
      O => \ysqr[75]_i_8_n_0\
    );
\ysqr[75]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[36]\,
      I1 => \dy_reg_n_0_[39]\,
      O => \ysqr[75]_i_9_n_0\
    );
\ysqr[76]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr03_in(4),
      O => \ysqr[76]_i_1_n_0\
    );
\ysqr[77]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr03_in(5),
      O => \ysqr[77]_i_1_n_0\
    );
\ysqr[78]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr03_in(6),
      O => \ysqr[78]_i_1_n_0\
    );
\ysqr[79]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr03_in(7),
      O => \ysqr[79]_i_1_n_0\
    );
\ysqr[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(7),
      O => \ysqr[7]_i_1_n_0\
    );
\ysqr[80]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr03_in(8),
      O => \ysqr[80]_i_1_n_0\
    );
\ysqr[81]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr03_in(9),
      O => \ysqr[81]_i_1_n_0\
    );
\ysqr[82]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr03_in(10),
      O => \ysqr[82]_i_1_n_0\
    );
\ysqr[83]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr03_in(11),
      O => \ysqr[83]_i_1_n_0\
    );
\ysqr[83]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[75]_i_3_n_15\,
      I1 => \ysqr_reg[75]_i_2_n_13\,
      O => \ysqr[83]_i_10_n_0\
    );
\ysqr[83]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFEFEE0E001011F"
    )
        port map (
      I0 => \ysqr_reg[75]_i_3_n_9\,
      I1 => \ysqr_reg[89]_i_13_n_12\,
      I2 => \ysqr_reg[89]_i_18_n_14\,
      I3 => \ysqr_reg[89]_i_13_n_11\,
      I4 => \ysqr_reg[75]_i_3_n_8\,
      I5 => \ysqr[83]_i_19_n_0\,
      O => \ysqr[83]_i_11_n_0\
    );
\ysqr[83]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"817E7E817E81817E"
    )
        port map (
      I0 => \ysqr_reg[89]_i_18_n_15\,
      I1 => \ysqr_reg[75]_i_3_n_9\,
      I2 => \ysqr_reg[89]_i_13_n_12\,
      I3 => \ysqr_reg[75]_i_3_n_8\,
      I4 => \ysqr_reg[89]_i_13_n_11\,
      I5 => \ysqr_reg[89]_i_18_n_14\,
      O => \ysqr[83]_i_12_n_0\
    );
\ysqr[83]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \ysqr_reg[89]_i_18_n_15\,
      I1 => \ysqr_reg[89]_i_13_n_12\,
      I2 => \ysqr_reg[75]_i_3_n_9\,
      I3 => \ysqr_reg[75]_i_3_n_10\,
      I4 => \ysqr_reg[75]_i_2_n_8\,
      I5 => \ysqr_reg[89]_i_13_n_13\,
      O => \ysqr[83]_i_13_n_0\
    );
\ysqr[83]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr[83]_i_6_n_0\,
      I1 => \ysqr_reg[89]_i_13_n_13\,
      I2 => \ysqr_reg[75]_i_2_n_8\,
      I3 => \ysqr_reg[75]_i_3_n_10\,
      O => \ysqr[83]_i_14_n_0\
    );
\ysqr[83]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr_reg[89]_i_13_n_14\,
      I1 => \ysqr_reg[75]_i_2_n_9\,
      I2 => \ysqr_reg[75]_i_3_n_11\,
      I3 => \ysqr[83]_i_7_n_0\,
      O => \ysqr[83]_i_15_n_0\
    );
\ysqr[83]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ysqr_reg[89]_i_13_n_15\,
      I1 => \ysqr_reg[75]_i_2_n_10\,
      I2 => \ysqr_reg[75]_i_3_n_12\,
      I3 => \ysqr[83]_i_8_n_0\,
      O => \ysqr[83]_i_16_n_0\
    );
\ysqr[83]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9666"
    )
        port map (
      I0 => \ysqr_reg[75]_i_3_n_13\,
      I1 => \ysqr_reg[75]_i_2_n_11\,
      I2 => \ysqr_reg[75]_i_2_n_12\,
      I3 => \ysqr_reg[75]_i_3_n_14\,
      O => \ysqr[83]_i_17_n_0\
    );
\ysqr[83]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ysqr_reg[75]_i_2_n_13\,
      I1 => \ysqr_reg[75]_i_3_n_15\,
      I2 => \ysqr_reg[75]_i_2_n_12\,
      I3 => \ysqr_reg[75]_i_3_n_14\,
      O => \ysqr[83]_i_18_n_0\
    );
\ysqr[83]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \ysqr_reg[89]_i_17_n_15\,
      I1 => \ysqr_reg[89]_i_13_n_10\,
      I2 => \ysqr_reg[89]_i_18_n_5\,
      O => \ysqr[83]_i_19_n_0\
    );
\ysqr[83]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \ysqr_reg[75]_i_3_n_9\,
      I1 => \ysqr_reg[89]_i_13_n_12\,
      I2 => \ysqr_reg[89]_i_18_n_14\,
      I3 => \ysqr_reg[89]_i_13_n_11\,
      I4 => \ysqr_reg[75]_i_3_n_8\,
      O => \ysqr[83]_i_3_n_0\
    );
\ysqr[83]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \ysqr_reg[89]_i_18_n_15\,
      I1 => \ysqr_reg[75]_i_3_n_9\,
      I2 => \ysqr_reg[89]_i_13_n_12\,
      O => \ysqr[83]_i_4_n_0\
    );
\ysqr[83]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \ysqr_reg[75]_i_3_n_9\,
      I1 => \ysqr_reg[89]_i_13_n_12\,
      I2 => \ysqr_reg[89]_i_18_n_15\,
      O => \ysqr[83]_i_5_n_0\
    );
\ysqr[83]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ysqr_reg[89]_i_13_n_14\,
      I1 => \ysqr_reg[75]_i_2_n_9\,
      I2 => \ysqr_reg[75]_i_3_n_11\,
      O => \ysqr[83]_i_6_n_0\
    );
\ysqr[83]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ysqr_reg[89]_i_13_n_15\,
      I1 => \ysqr_reg[75]_i_2_n_10\,
      I2 => \ysqr_reg[75]_i_3_n_12\,
      O => \ysqr[83]_i_7_n_0\
    );
\ysqr[83]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[75]_i_3_n_13\,
      I1 => \ysqr_reg[75]_i_2_n_11\,
      O => \ysqr[83]_i_8_n_0\
    );
\ysqr[83]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ysqr_reg[75]_i_3_n_14\,
      I1 => \ysqr_reg[75]_i_2_n_12\,
      O => \ysqr[83]_i_9_n_0\
    );
\ysqr[84]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr03_in(12),
      O => \ysqr[84]_i_1_n_0\
    );
\ysqr[85]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr03_in(13),
      O => \ysqr[85]_i_1_n_0\
    );
\ysqr[86]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr03_in(14),
      O => \ysqr[86]_i_1_n_0\
    );
\ysqr[87]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__8_n_0\,
      I1 => ysqr03_in(15),
      O => \ysqr[87]_i_1_n_0\
    );
\ysqr[88]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => ysqr03_in(16),
      O => \ysqr[88]_i_1_n_0\
    );
\ysqr[89]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__17_n_0\,
      I1 => ysqr03_in(17),
      O => \ysqr[89]_i_1_n_0\
    );
\ysqr[89]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969696"
    )
        port map (
      I0 => \ysqr[89]_i_5_n_0\,
      I1 => \ysqr_reg[89]_i_3_n_15\,
      I2 => \ysqr_reg[89]_i_17_n_4\,
      I3 => \ysqr_reg[89]_i_13_n_8\,
      I4 => \ysqr_reg[89]_i_17_n_13\,
      O => \ysqr[89]_i_10_n_0\
    );
\ysqr[89]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78878778"
    )
        port map (
      I0 => \ysqr_reg[89]_i_17_n_14\,
      I1 => \ysqr_reg[89]_i_13_n_9\,
      I2 => \ysqr_reg[89]_i_17_n_13\,
      I3 => \ysqr_reg[89]_i_13_n_8\,
      I4 => \ysqr[89]_i_6_n_0\,
      O => \ysqr[89]_i_11_n_0\
    );
\ysqr[89]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"566AA995A995566A"
    )
        port map (
      I0 => \ysqr[89]_i_7_n_0\,
      I1 => \ysqr_reg[89]_i_17_n_15\,
      I2 => \ysqr_reg[89]_i_18_n_5\,
      I3 => \ysqr_reg[89]_i_13_n_10\,
      I4 => \ysqr_reg[89]_i_17_n_14\,
      I5 => \ysqr_reg[89]_i_13_n_9\,
      O => \ysqr[89]_i_12_n_0\
    );
\ysqr[89]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \dy_reg_n_0_[43]\,
      I1 => \dy_reg_n_0_[44]\,
      O => \ysqr[89]_i_14_n_0\
    );
\ysqr[89]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \dy_reg_n_0_[42]\,
      I1 => \dy_reg_n_0_[44]\,
      O => \ysqr[89]_i_15_n_0\
    );
\ysqr[89]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dy_reg_n_0_[43]\,
      I1 => \dy_reg_n_0_[42]\,
      O => \ysqr[89]_i_16_n_0\
    );
\ysqr[89]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7777000"
    )
        port map (
      I0 => \dy_reg_n_0_[44]\,
      I1 => \dy_reg_n_0_[40]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dy_reg_n_0_[41]\,
      I4 => \dy_reg_n_0_[42]\,
      O => \ysqr[89]_i_19_n_0\
    );
\ysqr[89]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[44]\,
      I1 => \dy_reg_n_0_[39]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dy_reg_n_0_[40]\,
      I4 => \dy_reg_n_0_[41]\,
      I5 => \dy_reg_n_0_[42]\,
      O => \ysqr[89]_i_20_n_0\
    );
\ysqr[89]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[44]\,
      I1 => \dy_reg_n_0_[38]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dy_reg_n_0_[39]\,
      I4 => \dy_reg_n_0_[40]\,
      I5 => \dy_reg_n_0_[42]\,
      O => \ysqr[89]_i_21_n_0\
    );
\ysqr[89]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777700070007000"
    )
        port map (
      I0 => \dy_reg_n_0_[44]\,
      I1 => \dy_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dy_reg_n_0_[38]\,
      I4 => \dy_reg_n_0_[39]\,
      I5 => \dy_reg_n_0_[42]\,
      O => \ysqr[89]_i_22_n_0\
    );
\ysqr[89]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => \dy_reg_n_0_[44]\,
      I1 => \dy_reg_n_0_[36]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dy_reg_n_0_[37]\,
      O => \ysqr[89]_i_23_n_0\
    );
\ysqr[89]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[37]\,
      I1 => \dy_reg_n_0_[42]\,
      O => \ysqr[89]_i_24_n_0\
    );
\ysqr[89]_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8E11F555"
    )
        port map (
      I0 => \dy_reg_n_0_[42]\,
      I1 => \dy_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[40]\,
      I3 => \dy_reg_n_0_[44]\,
      I4 => \dy_reg_n_0_[41]\,
      O => \ysqr[89]_i_25_n_0\
    );
\ysqr[89]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EB843C0C903FCF3F"
    )
        port map (
      I0 => \dy_reg_n_0_[39]\,
      I1 => \dy_reg_n_0_[41]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dy_reg_n_0_[40]\,
      I4 => \dy_reg_n_0_[44]\,
      I5 => \dy_reg_n_0_[42]\,
      O => \ysqr[89]_i_26_n_0\
    );
\ysqr[89]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F07070780F8F8F8"
    )
        port map (
      I0 => \dy_reg_n_0_[42]\,
      I1 => \dy_reg_n_0_[40]\,
      I2 => \ysqr[89]_i_43_n_0\,
      I3 => \dy_reg_n_0_[38]\,
      I4 => \dy_reg_n_0_[44]\,
      I5 => \ysqr[89]_i_44_n_0\,
      O => \ysqr[89]_i_27_n_0\
    );
\ysqr[89]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"956A6A956A956A95"
    )
        port map (
      I0 => \ysqr[89]_i_22_n_0\,
      I1 => \dy_reg_n_0_[44]\,
      I2 => \dy_reg_n_0_[38]\,
      I3 => \ysqr[89]_i_43_n_0\,
      I4 => \dy_reg_n_0_[40]\,
      I5 => \dy_reg_n_0_[42]\,
      O => \ysqr[89]_i_28_n_0\
    );
\ysqr[89]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"69C399C369336933"
    )
        port map (
      I0 => \dy_reg_n_0_[38]\,
      I1 => \ysqr[89]_i_45_n_0\,
      I2 => \dy_reg_n_0_[37]\,
      I3 => \dy_reg_n_0_[43]\,
      I4 => \dy_reg_n_0_[36]\,
      I5 => \dy_reg_n_0_[44]\,
      O => \ysqr[89]_i_29_n_0\
    );
\ysqr[89]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dy_reg_n_0_[37]\,
      I1 => \dy_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[36]\,
      I3 => \dy_reg_n_0_[44]\,
      I4 => \dy_reg_n_0_[42]\,
      I5 => \dy_reg_n_0_[38]\,
      O => \ysqr[89]_i_30_n_0\
    );
\ysqr[89]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \dy_reg_n_0_[42]\,
      I1 => \dy_reg_n_0_[37]\,
      I2 => \dy_reg_n_0_[43]\,
      I3 => \dy_reg_n_0_[36]\,
      O => \ysqr[89]_i_31_n_0\
    );
\ysqr[89]_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[36]\,
      I1 => \dy_reg_n_0_[42]\,
      O => \ysqr[89]_i_32_n_0\
    );
\ysqr[89]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[43]\,
      I1 => \dy_reg_n_0_[41]\,
      I2 => \dy_reg_n_0_[44]\,
      I3 => \dy_reg_n_0_[40]\,
      O => \ysqr[89]_i_33_n_0\
    );
\ysqr[89]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[41]\,
      I1 => \dy_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[40]\,
      I3 => \dy_reg_n_0_[44]\,
      O => \ysqr[89]_i_34_n_0\
    );
\ysqr[89]_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[40]\,
      I1 => \dy_reg_n_0_[41]\,
      O => \ysqr[89]_i_35_n_0\
    );
\ysqr[89]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dy_reg_n_0_[40]\,
      I1 => \dy_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[44]\,
      I3 => \dy_reg_n_0_[41]\,
      O => \ysqr[89]_i_36_n_0\
    );
\ysqr[89]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dy_reg_n_0_[42]\,
      I1 => \dy_reg_n_0_[39]\,
      I2 => \dy_reg_n_0_[44]\,
      I3 => \dy_reg_n_0_[40]\,
      I4 => \dy_reg_n_0_[43]\,
      I5 => \dy_reg_n_0_[41]\,
      O => \ysqr[89]_i_37_n_0\
    );
\ysqr[89]_i_38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D22287772DDD8777"
    )
        port map (
      I0 => \dy_reg_n_0_[40]\,
      I1 => \dy_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[39]\,
      I3 => \dy_reg_n_0_[44]\,
      I4 => \dy_reg_n_0_[41]\,
      I5 => \dy_reg_n_0_[42]\,
      O => \ysqr[89]_i_38_n_0\
    );
\ysqr[89]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \dy_reg_n_0_[43]\,
      I1 => \dy_reg_n_0_[38]\,
      I2 => \dy_reg_n_0_[44]\,
      I3 => \dy_reg_n_0_[37]\,
      O => \ysqr[89]_i_39_n_0\
    );
\ysqr[89]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \ysqr_reg[89]_i_17_n_13\,
      I1 => \ysqr_reg[89]_i_13_n_8\,
      I2 => \ysqr_reg[89]_i_17_n_4\,
      I3 => \ysqr_reg[89]_i_3_n_15\,
      O => \ysqr[89]_i_4_n_0\
    );
\ysqr[89]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8777"
    )
        port map (
      I0 => \dy_reg_n_0_[38]\,
      I1 => \dy_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[37]\,
      I3 => \dy_reg_n_0_[44]\,
      O => \ysqr[89]_i_40_n_0\
    );
\ysqr[89]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"43FF"
    )
        port map (
      I0 => \dy_reg_n_0_[37]\,
      I1 => \dy_reg_n_0_[43]\,
      I2 => \dy_reg_n_0_[44]\,
      I3 => \dy_reg_n_0_[38]\,
      O => \ysqr[89]_i_41_n_0\
    );
\ysqr[89]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F2A25D530FF0FFF"
    )
        port map (
      I0 => \dy_reg_n_0_[42]\,
      I1 => \dy_reg_n_0_[36]\,
      I2 => \dy_reg_n_0_[44]\,
      I3 => \dy_reg_n_0_[37]\,
      I4 => \dy_reg_n_0_[43]\,
      I5 => \dy_reg_n_0_[38]\,
      O => \ysqr[89]_i_42_n_0\
    );
\ysqr[89]_i_43\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[39]\,
      I1 => \dy_reg_n_0_[43]\,
      O => \ysqr[89]_i_43_n_0\
    );
\ysqr[89]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7888877787778777"
    )
        port map (
      I0 => \dy_reg_n_0_[42]\,
      I1 => \dy_reg_n_0_[41]\,
      I2 => \dy_reg_n_0_[44]\,
      I3 => \dy_reg_n_0_[39]\,
      I4 => \dy_reg_n_0_[43]\,
      I5 => \dy_reg_n_0_[40]\,
      O => \ysqr[89]_i_44_n_0\
    );
\ysqr[89]_i_45\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dy_reg_n_0_[39]\,
      I1 => \dy_reg_n_0_[42]\,
      O => \ysqr[89]_i_45_n_0\
    );
\ysqr[89]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0880"
    )
        port map (
      I0 => \ysqr_reg[89]_i_17_n_14\,
      I1 => \ysqr_reg[89]_i_13_n_9\,
      I2 => \ysqr_reg[89]_i_17_n_13\,
      I3 => \ysqr_reg[89]_i_13_n_8\,
      O => \ysqr[89]_i_5_n_0\
    );
\ysqr[89]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66606000"
    )
        port map (
      I0 => \ysqr_reg[89]_i_17_n_14\,
      I1 => \ysqr_reg[89]_i_13_n_9\,
      I2 => \ysqr_reg[89]_i_17_n_15\,
      I3 => \ysqr_reg[89]_i_18_n_5\,
      I4 => \ysqr_reg[89]_i_13_n_10\,
      O => \ysqr[89]_i_6_n_0\
    );
\ysqr[89]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \ysqr_reg[75]_i_3_n_8\,
      I1 => \ysqr_reg[89]_i_18_n_14\,
      I2 => \ysqr_reg[89]_i_13_n_11\,
      I3 => \ysqr_reg[89]_i_18_n_5\,
      I4 => \ysqr_reg[89]_i_13_n_10\,
      I5 => \ysqr_reg[89]_i_17_n_15\,
      O => \ysqr[89]_i_7_n_0\
    );
\ysqr[89]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \ysqr_reg[89]_i_3_n_15\,
      I1 => \ysqr_reg[89]_i_17_n_4\,
      I2 => \ysqr_reg[89]_i_3_n_14\,
      I3 => \ysqr_reg[89]_i_3_n_13\,
      O => \ysqr[89]_i_8_n_0\
    );
\ysqr[89]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"077FF880"
    )
        port map (
      I0 => \ysqr_reg[89]_i_13_n_8\,
      I1 => \ysqr_reg[89]_i_17_n_13\,
      I2 => \ysqr_reg[89]_i_3_n_15\,
      I3 => \ysqr_reg[89]_i_17_n_4\,
      I4 => \ysqr_reg[89]_i_3_n_14\,
      O => \ysqr[89]_i_9_n_0\
    );
\ysqr[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(8),
      O => \ysqr[8]_i_1_n_0\
    );
\ysqr[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateScore_reg_rep__7_n_0\,
      I1 => ysqr0(9),
      O => \ysqr[9]_i_1_n_0\
    );
\ysqr_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[0]_i_1_n_0\,
      Q => ysqr(0)
    );
\ysqr_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[10]_i_1_n_0\,
      Q => ysqr(10)
    );
\ysqr_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[11]_i_1_n_0\,
      Q => ysqr(11)
    );
\ysqr_reg[11]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[11]_i_2_n_0\,
      CO(6) => \ysqr_reg[11]_i_2_n_1\,
      CO(5) => \ysqr_reg[11]_i_2_n_2\,
      CO(4) => \ysqr_reg[11]_i_2_n_3\,
      CO(3) => \ysqr_reg[11]_i_2_n_4\,
      CO(2) => \ysqr_reg[11]_i_2_n_5\,
      CO(1) => \ysqr_reg[11]_i_2_n_6\,
      CO(0) => \ysqr_reg[11]_i_2_n_7\,
      DI(7) => \ysqr[11]_i_3_n_0\,
      DI(6) => \ysqr[11]_i_4_n_0\,
      DI(5) => \ysqr[11]_i_5_n_0\,
      DI(4) => \ysqr[11]_i_6_n_0\,
      DI(3) => \ysqr[11]_i_7_n_0\,
      DI(2) => \ysqr[11]_i_8_n_0\,
      DI(1) => \ysqr[11]_i_9_n_0\,
      DI(0) => \ysqr[11]_i_10_n_0\,
      O(7 downto 0) => ysqr0(11 downto 4),
      S(7) => \ysqr[11]_i_11_n_0\,
      S(6) => \ysqr[11]_i_12_n_0\,
      S(5) => \ysqr[11]_i_13_n_0\,
      S(4) => \ysqr[11]_i_14_n_0\,
      S(3) => \ysqr[11]_i_15_n_0\,
      S(2) => \ysqr[11]_i_16_n_0\,
      S(1) => \ysqr[11]_i_17_n_0\,
      S(0) => \ysqr[11]_i_18_n_0\
    );
\ysqr_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[12]_i_1_n_0\,
      Q => ysqr(12)
    );
\ysqr_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[13]_i_1_n_0\,
      Q => ysqr(13)
    );
\ysqr_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[14]_i_1_n_0\,
      Q => ysqr(14)
    );
\ysqr_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[15]_i_1_n_0\,
      Q => ysqr(15)
    );
\ysqr_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[16]_i_1_n_0\,
      Q => ysqr(16)
    );
\ysqr_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[17]_i_1_n_0\,
      Q => ysqr(17)
    );
\ysqr_reg[17]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[17]_i_13_n_0\,
      CO(6) => \ysqr_reg[17]_i_13_n_1\,
      CO(5) => \ysqr_reg[17]_i_13_n_2\,
      CO(4) => \ysqr_reg[17]_i_13_n_3\,
      CO(3) => \ysqr_reg[17]_i_13_n_4\,
      CO(2) => \ysqr_reg[17]_i_13_n_5\,
      CO(1) => \ysqr_reg[17]_i_13_n_6\,
      CO(0) => \ysqr_reg[17]_i_13_n_7\,
      DI(7) => \ysqr[17]_i_19_n_0\,
      DI(6) => \ysqr[17]_i_20_n_0\,
      DI(5) => \ysqr[17]_i_21_n_0\,
      DI(4) => \ysqr[17]_i_22_n_0\,
      DI(3) => \ysqr[17]_i_23_n_0\,
      DI(2) => \ysqr[3]_i_31_n_0\,
      DI(1) => \ysqr[17]_i_24_n_0\,
      DI(0) => '0',
      O(7) => \ysqr_reg[17]_i_13_n_8\,
      O(6) => \ysqr_reg[17]_i_13_n_9\,
      O(5) => \ysqr_reg[17]_i_13_n_10\,
      O(4) => \ysqr_reg[17]_i_13_n_11\,
      O(3) => \ysqr_reg[17]_i_13_n_12\,
      O(2) => \ysqr_reg[17]_i_13_n_13\,
      O(1) => \ysqr_reg[17]_i_13_n_14\,
      O(0) => \ysqr_reg[17]_i_13_n_15\,
      S(7) => \ysqr[17]_i_25_n_0\,
      S(6) => \ysqr[17]_i_26_n_0\,
      S(5) => \ysqr[17]_i_27_n_0\,
      S(4) => \ysqr[17]_i_28_n_0\,
      S(3) => \ysqr[17]_i_29_n_0\,
      S(2) => \ysqr[17]_i_30_n_0\,
      S(1) => \ysqr[17]_i_31_n_0\,
      S(0) => \ysqr[17]_i_32_n_0\
    );
\ysqr_reg[17]_i_17\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[3]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_ysqr_reg[17]_i_17_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \ysqr_reg[17]_i_17_n_4\,
      CO(2) => \NLW_ysqr_reg[17]_i_17_CO_UNCONNECTED\(2),
      CO(1) => \ysqr_reg[17]_i_17_n_6\,
      CO(0) => \ysqr_reg[17]_i_17_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \ysqr[17]_i_33_n_0\,
      DI(1) => \ysqr[17]_i_34_n_0\,
      DI(0) => \ysqr[17]_i_35_n_0\,
      O(7 downto 3) => \NLW_ysqr_reg[17]_i_17_O_UNCONNECTED\(7 downto 3),
      O(2) => \ysqr_reg[17]_i_17_n_13\,
      O(1) => \ysqr_reg[17]_i_17_n_14\,
      O(0) => \ysqr_reg[17]_i_17_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \ysqr[17]_i_36_n_0\,
      S(1) => \ysqr[17]_i_37_n_0\,
      S(0) => \ysqr[17]_i_38_n_0\
    );
\ysqr_reg[17]_i_18\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[3]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_ysqr_reg[17]_i_18_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \ysqr_reg[17]_i_18_n_5\,
      CO(1) => \NLW_ysqr_reg[17]_i_18_CO_UNCONNECTED\(1),
      CO(0) => \ysqr_reg[17]_i_18_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \ysqr[17]_i_39_n_0\,
      DI(0) => \ysqr[17]_i_40_n_0\,
      O(7 downto 2) => \NLW_ysqr_reg[17]_i_18_O_UNCONNECTED\(7 downto 2),
      O(1) => \ysqr_reg[17]_i_18_n_14\,
      O(0) => \ysqr_reg[17]_i_18_n_15\,
      S(7 downto 2) => B"000001",
      S(1) => \ysqr[17]_i_41_n_0\,
      S(0) => \ysqr[17]_i_42_n_0\
    );
\ysqr_reg[17]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[11]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_ysqr_reg[17]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \ysqr_reg[17]_i_2_n_3\,
      CO(3) => \ysqr_reg[17]_i_2_n_4\,
      CO(2) => \ysqr_reg[17]_i_2_n_5\,
      CO(1) => \ysqr_reg[17]_i_2_n_6\,
      CO(0) => \ysqr_reg[17]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \ysqr_reg[17]_i_3_n_13\,
      DI(3) => \ysqr[17]_i_4_n_0\,
      DI(2) => \ysqr[17]_i_5_n_0\,
      DI(1) => \ysqr[17]_i_6_n_0\,
      DI(0) => \ysqr[17]_i_7_n_0\,
      O(7 downto 6) => \NLW_ysqr_reg[17]_i_2_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => ysqr0(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \ysqr_reg[17]_i_3_n_12\,
      S(4) => \ysqr[17]_i_8_n_0\,
      S(3) => \ysqr[17]_i_9_n_0\,
      S(2) => \ysqr[17]_i_10_n_0\,
      S(1) => \ysqr[17]_i_11_n_0\,
      S(0) => \ysqr[17]_i_12_n_0\
    );
\ysqr_reg[17]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[17]_i_13_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_ysqr_reg[17]_i_3_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \ysqr_reg[17]_i_3_n_5\,
      CO(1) => \ysqr_reg[17]_i_3_n_6\,
      CO(0) => \ysqr_reg[17]_i_3_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \dy_reg_n_0_[8]\,
      DI(1) => '0',
      DI(0) => \dy_reg_n_0_[7]\,
      O(7 downto 4) => \NLW_ysqr_reg[17]_i_3_O_UNCONNECTED\(7 downto 4),
      O(3) => \ysqr_reg[17]_i_3_n_12\,
      O(2) => \ysqr_reg[17]_i_3_n_13\,
      O(1) => \ysqr_reg[17]_i_3_n_14\,
      O(0) => \ysqr_reg[17]_i_3_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \ysqr[17]_i_14_n_0\,
      S(1) => \ysqr[17]_i_15_n_0\,
      S(0) => \ysqr[17]_i_16_n_0\
    );
\ysqr_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[18]_i_1_n_0\,
      Q => ysqr(18)
    );
\ysqr_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[20]_i_1_n_0\,
      Q => ysqr(20)
    );
\ysqr_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[21]_i_1_n_0\,
      Q => ysqr(21)
    );
\ysqr_reg[21]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[21]_i_2_n_0\,
      CO(6) => \ysqr_reg[21]_i_2_n_1\,
      CO(5) => \ysqr_reg[21]_i_2_n_2\,
      CO(4) => \ysqr_reg[21]_i_2_n_3\,
      CO(3) => \ysqr_reg[21]_i_2_n_4\,
      CO(2) => \ysqr_reg[21]_i_2_n_5\,
      CO(1) => \ysqr_reg[21]_i_2_n_6\,
      CO(0) => \ysqr_reg[21]_i_2_n_7\,
      DI(7) => \ysqr[21]_i_4_n_0\,
      DI(6) => \ysqr[21]_i_5_n_0\,
      DI(5) => \ysqr[21]_i_6_n_0\,
      DI(4) => \ysqr[21]_i_7_n_0\,
      DI(3) => \ysqr[21]_i_8_n_0\,
      DI(2) => \ysqr[21]_i_9_n_0\,
      DI(1) => B(1),
      DI(0) => '0',
      O(7) => \ysqr_reg[21]_i_2_n_8\,
      O(6) => \ysqr_reg[21]_i_2_n_9\,
      O(5) => \ysqr_reg[21]_i_2_n_10\,
      O(4) => \ysqr_reg[21]_i_2_n_11\,
      O(3) => \ysqr_reg[21]_i_2_n_12\,
      O(2) => \ysqr_reg[21]_i_2_n_13\,
      O(1) => ysqr00_in(2),
      O(0) => \NLW_ysqr_reg[21]_i_2_O_UNCONNECTED\(0),
      S(7) => \ysqr[21]_i_10_n_0\,
      S(6) => \ysqr[21]_i_11_n_0\,
      S(5) => \ysqr[21]_i_12_n_0\,
      S(4) => \ysqr[21]_i_13_n_0\,
      S(3) => \ysqr[21]_i_14_n_0\,
      S(2) => \ysqr[21]_i_15_n_0\,
      S(1) => \ysqr[21]_i_16_n_0\,
      S(0) => '0'
    );
\ysqr_reg[21]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[21]_i_3_n_0\,
      CO(6) => \ysqr_reg[21]_i_3_n_1\,
      CO(5) => \ysqr_reg[21]_i_3_n_2\,
      CO(4) => \ysqr_reg[21]_i_3_n_3\,
      CO(3) => \ysqr_reg[21]_i_3_n_4\,
      CO(2) => \ysqr_reg[21]_i_3_n_5\,
      CO(1) => \ysqr_reg[21]_i_3_n_6\,
      CO(0) => \ysqr_reg[21]_i_3_n_7\,
      DI(7) => \ysqr[21]_i_17_n_0\,
      DI(6) => \ysqr[21]_i_18_n_0\,
      DI(5) => B(4),
      DI(4) => \ysqr[21]_i_19_n_0\,
      DI(3) => \ysqr[21]_i_20_n_0\,
      DI(2) => \ysqr[21]_i_21_n_0\,
      DI(1) => \ysqr[21]_i_22_n_0\,
      DI(0) => '0',
      O(7) => \ysqr_reg[21]_i_3_n_8\,
      O(6) => \ysqr_reg[21]_i_3_n_9\,
      O(5) => \ysqr_reg[21]_i_3_n_10\,
      O(4) => \ysqr_reg[21]_i_3_n_11\,
      O(3) => \ysqr_reg[21]_i_3_n_12\,
      O(2) => \ysqr_reg[21]_i_3_n_13\,
      O(1) => \ysqr_reg[21]_i_3_n_14\,
      O(0) => \ysqr_reg[21]_i_3_n_15\,
      S(7) => \ysqr[21]_i_23_n_0\,
      S(6) => \ysqr[21]_i_24_n_0\,
      S(5) => \ysqr[21]_i_25_n_0\,
      S(4) => \ysqr[21]_i_26_n_0\,
      S(3) => \ysqr[21]_i_27_n_0\,
      S(2) => \ysqr[21]_i_28_n_0\,
      S(1) => \ysqr[21]_i_29_n_0\,
      S(0) => \ysqr[21]_i_30_n_0\
    );
\ysqr_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[22]_i_1_n_0\,
      Q => ysqr(22)
    );
\ysqr_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[23]_i_1_n_0\,
      Q => ysqr(23)
    );
\ysqr_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[24]_i_1_n_0\,
      Q => ysqr(24)
    );
\ysqr_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[25]_i_1_n_0\,
      Q => ysqr(25)
    );
\ysqr_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[26]_i_1_n_0\,
      Q => ysqr(26)
    );
\ysqr_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[27]_i_1_n_0\,
      Q => ysqr(27)
    );
\ysqr_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[28]_i_1_n_0\,
      Q => ysqr(28)
    );
\ysqr_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[29]_i_1_n_0\,
      Q => ysqr(29)
    );
\ysqr_reg[29]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[29]_i_2_n_0\,
      CO(6) => \ysqr_reg[29]_i_2_n_1\,
      CO(5) => \ysqr_reg[29]_i_2_n_2\,
      CO(4) => \ysqr_reg[29]_i_2_n_3\,
      CO(3) => \ysqr_reg[29]_i_2_n_4\,
      CO(2) => \ysqr_reg[29]_i_2_n_5\,
      CO(1) => \ysqr_reg[29]_i_2_n_6\,
      CO(0) => \ysqr_reg[29]_i_2_n_7\,
      DI(7) => \ysqr[29]_i_3_n_0\,
      DI(6) => \ysqr[29]_i_4_n_0\,
      DI(5) => \ysqr[29]_i_5_n_0\,
      DI(4) => \ysqr[29]_i_6_n_0\,
      DI(3) => \ysqr[29]_i_7_n_0\,
      DI(2) => \ysqr[29]_i_8_n_0\,
      DI(1) => \ysqr[29]_i_9_n_0\,
      DI(0) => \ysqr[29]_i_10_n_0\,
      O(7 downto 0) => ysqr00_in(11 downto 4),
      S(7) => \ysqr[29]_i_11_n_0\,
      S(6) => \ysqr[29]_i_12_n_0\,
      S(5) => \ysqr[29]_i_13_n_0\,
      S(4) => \ysqr[29]_i_14_n_0\,
      S(3) => \ysqr[29]_i_15_n_0\,
      S(2) => \ysqr[29]_i_16_n_0\,
      S(1) => \ysqr[29]_i_17_n_0\,
      S(0) => \ysqr[29]_i_18_n_0\
    );
\ysqr_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[2]_i_1_n_0\,
      Q => ysqr(2)
    );
\ysqr_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[30]_i_1_n_0\,
      Q => ysqr(30)
    );
\ysqr_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[31]_i_1_n_0\,
      Q => ysqr(31)
    );
\ysqr_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[32]_i_1_n_0\,
      Q => ysqr(32)
    );
\ysqr_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[33]_i_1_n_0\,
      Q => ysqr(33)
    );
\ysqr_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[34]_i_1_n_0\,
      Q => ysqr(34)
    );
\ysqr_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[35]_i_1_n_0\,
      Q => ysqr(35)
    );
\ysqr_reg[35]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[35]_i_13_n_0\,
      CO(6) => \ysqr_reg[35]_i_13_n_1\,
      CO(5) => \ysqr_reg[35]_i_13_n_2\,
      CO(4) => \ysqr_reg[35]_i_13_n_3\,
      CO(3) => \ysqr_reg[35]_i_13_n_4\,
      CO(2) => \ysqr_reg[35]_i_13_n_5\,
      CO(1) => \ysqr_reg[35]_i_13_n_6\,
      CO(0) => \ysqr_reg[35]_i_13_n_7\,
      DI(7) => \ysqr[35]_i_19_n_0\,
      DI(6) => \ysqr[35]_i_20_n_0\,
      DI(5) => \ysqr[35]_i_21_n_0\,
      DI(4) => \ysqr[35]_i_22_n_0\,
      DI(3) => \ysqr[35]_i_23_n_0\,
      DI(2) => \ysqr[21]_i_31_n_0\,
      DI(1) => \ysqr[35]_i_24_n_0\,
      DI(0) => '0',
      O(7) => \ysqr_reg[35]_i_13_n_8\,
      O(6) => \ysqr_reg[35]_i_13_n_9\,
      O(5) => \ysqr_reg[35]_i_13_n_10\,
      O(4) => \ysqr_reg[35]_i_13_n_11\,
      O(3) => \ysqr_reg[35]_i_13_n_12\,
      O(2) => \ysqr_reg[35]_i_13_n_13\,
      O(1) => \ysqr_reg[35]_i_13_n_14\,
      O(0) => \ysqr_reg[35]_i_13_n_15\,
      S(7) => \ysqr[35]_i_25_n_0\,
      S(6) => \ysqr[35]_i_26_n_0\,
      S(5) => \ysqr[35]_i_27_n_0\,
      S(4) => \ysqr[35]_i_28_n_0\,
      S(3) => \ysqr[35]_i_29_n_0\,
      S(2) => \ysqr[35]_i_30_n_0\,
      S(1) => \ysqr[35]_i_31_n_0\,
      S(0) => \ysqr[35]_i_32_n_0\
    );
\ysqr_reg[35]_i_17\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[21]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_ysqr_reg[35]_i_17_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \ysqr_reg[35]_i_17_n_4\,
      CO(2) => \NLW_ysqr_reg[35]_i_17_CO_UNCONNECTED\(2),
      CO(1) => \ysqr_reg[35]_i_17_n_6\,
      CO(0) => \ysqr_reg[35]_i_17_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \ysqr[35]_i_33_n_0\,
      DI(1) => \ysqr[35]_i_34_n_0\,
      DI(0) => \ysqr[35]_i_35_n_0\,
      O(7 downto 3) => \NLW_ysqr_reg[35]_i_17_O_UNCONNECTED\(7 downto 3),
      O(2) => \ysqr_reg[35]_i_17_n_13\,
      O(1) => \ysqr_reg[35]_i_17_n_14\,
      O(0) => \ysqr_reg[35]_i_17_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \ysqr[35]_i_36_n_0\,
      S(1) => \ysqr[35]_i_37_n_0\,
      S(0) => \ysqr[35]_i_38_n_0\
    );
\ysqr_reg[35]_i_18\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[21]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_ysqr_reg[35]_i_18_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \ysqr_reg[35]_i_18_n_5\,
      CO(1) => \NLW_ysqr_reg[35]_i_18_CO_UNCONNECTED\(1),
      CO(0) => \ysqr_reg[35]_i_18_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \ysqr[35]_i_39_n_0\,
      DI(0) => \ysqr[35]_i_40_n_0\,
      O(7 downto 2) => \NLW_ysqr_reg[35]_i_18_O_UNCONNECTED\(7 downto 2),
      O(1) => \ysqr_reg[35]_i_18_n_14\,
      O(0) => \ysqr_reg[35]_i_18_n_15\,
      S(7 downto 2) => B"000001",
      S(1) => \ysqr[35]_i_41_n_0\,
      S(0) => \ysqr[35]_i_42_n_0\
    );
\ysqr_reg[35]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[29]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_ysqr_reg[35]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \ysqr_reg[35]_i_2_n_3\,
      CO(3) => \ysqr_reg[35]_i_2_n_4\,
      CO(2) => \ysqr_reg[35]_i_2_n_5\,
      CO(1) => \ysqr_reg[35]_i_2_n_6\,
      CO(0) => \ysqr_reg[35]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \ysqr_reg[35]_i_3_n_13\,
      DI(3) => \ysqr[35]_i_4_n_0\,
      DI(2) => \ysqr[35]_i_5_n_0\,
      DI(1) => \ysqr[35]_i_6_n_0\,
      DI(0) => \ysqr[35]_i_7_n_0\,
      O(7 downto 6) => \NLW_ysqr_reg[35]_i_2_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => ysqr00_in(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \ysqr_reg[35]_i_3_n_12\,
      S(4) => \ysqr[35]_i_8_n_0\,
      S(3) => \ysqr[35]_i_9_n_0\,
      S(2) => \ysqr[35]_i_10_n_0\,
      S(1) => \ysqr[35]_i_11_n_0\,
      S(0) => \ysqr[35]_i_12_n_0\
    );
\ysqr_reg[35]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[35]_i_13_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_ysqr_reg[35]_i_3_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \ysqr_reg[35]_i_3_n_5\,
      CO(1) => \ysqr_reg[35]_i_3_n_6\,
      CO(0) => \ysqr_reg[35]_i_3_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => B(8),
      DI(1) => '0',
      DI(0) => B(7),
      O(7 downto 4) => \NLW_ysqr_reg[35]_i_3_O_UNCONNECTED\(7 downto 4),
      O(3) => \ysqr_reg[35]_i_3_n_12\,
      O(2) => \ysqr_reg[35]_i_3_n_13\,
      O(1) => \ysqr_reg[35]_i_3_n_14\,
      O(0) => \ysqr_reg[35]_i_3_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \ysqr[35]_i_14_n_0\,
      S(1) => \ysqr[35]_i_15_n_0\,
      S(0) => \ysqr[35]_i_16_n_0\
    );
\ysqr_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[36]_i_1_n_0\,
      Q => ysqr(36)
    );
\ysqr_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[38]_i_1_n_0\,
      Q => ysqr(38)
    );
\ysqr_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[39]_i_1_n_0\,
      Q => ysqr(39)
    );
\ysqr_reg[39]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[39]_i_2_n_0\,
      CO(6) => \ysqr_reg[39]_i_2_n_1\,
      CO(5) => \ysqr_reg[39]_i_2_n_2\,
      CO(4) => \ysqr_reg[39]_i_2_n_3\,
      CO(3) => \ysqr_reg[39]_i_2_n_4\,
      CO(2) => \ysqr_reg[39]_i_2_n_5\,
      CO(1) => \ysqr_reg[39]_i_2_n_6\,
      CO(0) => \ysqr_reg[39]_i_2_n_7\,
      DI(7) => \ysqr[39]_i_4_n_0\,
      DI(6) => \ysqr[39]_i_5_n_0\,
      DI(5) => \ysqr[39]_i_6_n_0\,
      DI(4) => \ysqr[39]_i_7_n_0\,
      DI(3) => \ysqr[39]_i_8_n_0\,
      DI(2) => \ysqr[39]_i_9_n_0\,
      DI(1) => \dy_reg_n_0_[19]\,
      DI(0) => '0',
      O(7) => \ysqr_reg[39]_i_2_n_8\,
      O(6) => \ysqr_reg[39]_i_2_n_9\,
      O(5) => \ysqr_reg[39]_i_2_n_10\,
      O(4) => \ysqr_reg[39]_i_2_n_11\,
      O(3) => \ysqr_reg[39]_i_2_n_12\,
      O(2) => \ysqr_reg[39]_i_2_n_13\,
      O(1) => ysqr01_in(2),
      O(0) => \NLW_ysqr_reg[39]_i_2_O_UNCONNECTED\(0),
      S(7) => \ysqr[39]_i_10_n_0\,
      S(6) => \ysqr[39]_i_11_n_0\,
      S(5) => \ysqr[39]_i_12_n_0\,
      S(4) => \ysqr[39]_i_13_n_0\,
      S(3) => \ysqr[39]_i_14_n_0\,
      S(2) => \ysqr[39]_i_15_n_0\,
      S(1) => \ysqr[39]_i_16_n_0\,
      S(0) => '0'
    );
\ysqr_reg[39]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[39]_i_3_n_0\,
      CO(6) => \ysqr_reg[39]_i_3_n_1\,
      CO(5) => \ysqr_reg[39]_i_3_n_2\,
      CO(4) => \ysqr_reg[39]_i_3_n_3\,
      CO(3) => \ysqr_reg[39]_i_3_n_4\,
      CO(2) => \ysqr_reg[39]_i_3_n_5\,
      CO(1) => \ysqr_reg[39]_i_3_n_6\,
      CO(0) => \ysqr_reg[39]_i_3_n_7\,
      DI(7) => \ysqr[39]_i_17_n_0\,
      DI(6) => \ysqr[39]_i_18_n_0\,
      DI(5) => \dy_reg_n_0_[22]\,
      DI(4) => \ysqr[39]_i_19_n_0\,
      DI(3) => \ysqr[39]_i_20_n_0\,
      DI(2) => \ysqr[39]_i_21_n_0\,
      DI(1) => \ysqr[39]_i_22_n_0\,
      DI(0) => '0',
      O(7) => \ysqr_reg[39]_i_3_n_8\,
      O(6) => \ysqr_reg[39]_i_3_n_9\,
      O(5) => \ysqr_reg[39]_i_3_n_10\,
      O(4) => \ysqr_reg[39]_i_3_n_11\,
      O(3) => \ysqr_reg[39]_i_3_n_12\,
      O(2) => \ysqr_reg[39]_i_3_n_13\,
      O(1) => \ysqr_reg[39]_i_3_n_14\,
      O(0) => \ysqr_reg[39]_i_3_n_15\,
      S(7) => \ysqr[39]_i_23_n_0\,
      S(6) => \ysqr[39]_i_24_n_0\,
      S(5) => \ysqr[39]_i_25_n_0\,
      S(4) => \ysqr[39]_i_26_n_0\,
      S(3) => \ysqr[39]_i_27_n_0\,
      S(2) => \ysqr[39]_i_28_n_0\,
      S(1) => \ysqr[39]_i_29_n_0\,
      S(0) => \ysqr[39]_i_30_n_0\
    );
\ysqr_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[3]_i_1_n_0\,
      Q => ysqr(3)
    );
\ysqr_reg[3]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[3]_i_2_n_0\,
      CO(6) => \ysqr_reg[3]_i_2_n_1\,
      CO(5) => \ysqr_reg[3]_i_2_n_2\,
      CO(4) => \ysqr_reg[3]_i_2_n_3\,
      CO(3) => \ysqr_reg[3]_i_2_n_4\,
      CO(2) => \ysqr_reg[3]_i_2_n_5\,
      CO(1) => \ysqr_reg[3]_i_2_n_6\,
      CO(0) => \ysqr_reg[3]_i_2_n_7\,
      DI(7) => \ysqr[3]_i_4_n_0\,
      DI(6) => \ysqr[3]_i_5_n_0\,
      DI(5) => \ysqr[3]_i_6_n_0\,
      DI(4) => \ysqr[3]_i_7_n_0\,
      DI(3) => \ysqr[3]_i_8_n_0\,
      DI(2) => \ysqr[3]_i_9_n_0\,
      DI(1) => \dy_reg_n_0_[1]\,
      DI(0) => '0',
      O(7) => \ysqr_reg[3]_i_2_n_8\,
      O(6) => \ysqr_reg[3]_i_2_n_9\,
      O(5) => \ysqr_reg[3]_i_2_n_10\,
      O(4) => \ysqr_reg[3]_i_2_n_11\,
      O(3) => \ysqr_reg[3]_i_2_n_12\,
      O(2) => \ysqr_reg[3]_i_2_n_13\,
      O(1) => ysqr0(2),
      O(0) => \NLW_ysqr_reg[3]_i_2_O_UNCONNECTED\(0),
      S(7) => \ysqr[3]_i_10_n_0\,
      S(6) => \ysqr[3]_i_11_n_0\,
      S(5) => \ysqr[3]_i_12_n_0\,
      S(4) => \ysqr[3]_i_13_n_0\,
      S(3) => \ysqr[3]_i_14_n_0\,
      S(2) => \ysqr[3]_i_15_n_0\,
      S(1) => \ysqr[3]_i_16_n_0\,
      S(0) => '0'
    );
\ysqr_reg[3]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[3]_i_3_n_0\,
      CO(6) => \ysqr_reg[3]_i_3_n_1\,
      CO(5) => \ysqr_reg[3]_i_3_n_2\,
      CO(4) => \ysqr_reg[3]_i_3_n_3\,
      CO(3) => \ysqr_reg[3]_i_3_n_4\,
      CO(2) => \ysqr_reg[3]_i_3_n_5\,
      CO(1) => \ysqr_reg[3]_i_3_n_6\,
      CO(0) => \ysqr_reg[3]_i_3_n_7\,
      DI(7) => \ysqr[3]_i_17_n_0\,
      DI(6) => \ysqr[3]_i_18_n_0\,
      DI(5) => \dy_reg_n_0_[4]\,
      DI(4) => \ysqr[3]_i_19_n_0\,
      DI(3) => \ysqr[3]_i_20_n_0\,
      DI(2) => \ysqr[3]_i_21_n_0\,
      DI(1) => \ysqr[3]_i_22_n_0\,
      DI(0) => '0',
      O(7) => \ysqr_reg[3]_i_3_n_8\,
      O(6) => \ysqr_reg[3]_i_3_n_9\,
      O(5) => \ysqr_reg[3]_i_3_n_10\,
      O(4) => \ysqr_reg[3]_i_3_n_11\,
      O(3) => \ysqr_reg[3]_i_3_n_12\,
      O(2) => \ysqr_reg[3]_i_3_n_13\,
      O(1) => \ysqr_reg[3]_i_3_n_14\,
      O(0) => \ysqr_reg[3]_i_3_n_15\,
      S(7) => \ysqr[3]_i_23_n_0\,
      S(6) => \ysqr[3]_i_24_n_0\,
      S(5) => \ysqr[3]_i_25_n_0\,
      S(4) => \ysqr[3]_i_26_n_0\,
      S(3) => \ysqr[3]_i_27_n_0\,
      S(2) => \ysqr[3]_i_28_n_0\,
      S(1) => \ysqr[3]_i_29_n_0\,
      S(0) => \ysqr[3]_i_30_n_0\
    );
\ysqr_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[40]_i_1_n_0\,
      Q => ysqr(40)
    );
\ysqr_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[41]_i_1_n_0\,
      Q => ysqr(41)
    );
\ysqr_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[42]_i_1_n_0\,
      Q => ysqr(42)
    );
\ysqr_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[43]_i_1_n_0\,
      Q => ysqr(43)
    );
\ysqr_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[44]_i_1_n_0\,
      Q => ysqr(44)
    );
\ysqr_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[45]_i_1_n_0\,
      Q => ysqr(45)
    );
\ysqr_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[46]_i_1_n_0\,
      Q => ysqr(46)
    );
\ysqr_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[47]_i_1_n_0\,
      Q => ysqr(47)
    );
\ysqr_reg[47]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[47]_i_2_n_0\,
      CO(6) => \ysqr_reg[47]_i_2_n_1\,
      CO(5) => \ysqr_reg[47]_i_2_n_2\,
      CO(4) => \ysqr_reg[47]_i_2_n_3\,
      CO(3) => \ysqr_reg[47]_i_2_n_4\,
      CO(2) => \ysqr_reg[47]_i_2_n_5\,
      CO(1) => \ysqr_reg[47]_i_2_n_6\,
      CO(0) => \ysqr_reg[47]_i_2_n_7\,
      DI(7) => \ysqr[47]_i_3_n_0\,
      DI(6) => \ysqr[47]_i_4_n_0\,
      DI(5) => \ysqr[47]_i_5_n_0\,
      DI(4) => \ysqr[47]_i_6_n_0\,
      DI(3) => \ysqr[47]_i_7_n_0\,
      DI(2) => \ysqr[47]_i_8_n_0\,
      DI(1) => \ysqr[47]_i_9_n_0\,
      DI(0) => \ysqr[47]_i_10_n_0\,
      O(7 downto 0) => ysqr01_in(11 downto 4),
      S(7) => \ysqr[47]_i_11_n_0\,
      S(6) => \ysqr[47]_i_12_n_0\,
      S(5) => \ysqr[47]_i_13_n_0\,
      S(4) => \ysqr[47]_i_14_n_0\,
      S(3) => \ysqr[47]_i_15_n_0\,
      S(2) => \ysqr[47]_i_16_n_0\,
      S(1) => \ysqr[47]_i_17_n_0\,
      S(0) => \ysqr[47]_i_18_n_0\
    );
\ysqr_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[48]_i_1_n_0\,
      Q => ysqr(48)
    );
\ysqr_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[49]_i_1_n_0\,
      Q => ysqr(49)
    );
\ysqr_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[4]_i_1_n_0\,
      Q => ysqr(4)
    );
\ysqr_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[50]_i_1_n_0\,
      Q => ysqr(50)
    );
\ysqr_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[51]_i_1_n_0\,
      Q => ysqr(51)
    );
\ysqr_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[52]_i_1_n_0\,
      Q => ysqr(52)
    );
\ysqr_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[53]_i_1_n_0\,
      Q => ysqr(53)
    );
\ysqr_reg[53]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[53]_i_13_n_0\,
      CO(6) => \ysqr_reg[53]_i_13_n_1\,
      CO(5) => \ysqr_reg[53]_i_13_n_2\,
      CO(4) => \ysqr_reg[53]_i_13_n_3\,
      CO(3) => \ysqr_reg[53]_i_13_n_4\,
      CO(2) => \ysqr_reg[53]_i_13_n_5\,
      CO(1) => \ysqr_reg[53]_i_13_n_6\,
      CO(0) => \ysqr_reg[53]_i_13_n_7\,
      DI(7) => \ysqr[53]_i_19_n_0\,
      DI(6) => \ysqr[53]_i_20_n_0\,
      DI(5) => \ysqr[53]_i_21_n_0\,
      DI(4) => \ysqr[53]_i_22_n_0\,
      DI(3) => \ysqr[53]_i_23_n_0\,
      DI(2) => \ysqr[39]_i_31_n_0\,
      DI(1) => \ysqr[53]_i_24_n_0\,
      DI(0) => '0',
      O(7) => \ysqr_reg[53]_i_13_n_8\,
      O(6) => \ysqr_reg[53]_i_13_n_9\,
      O(5) => \ysqr_reg[53]_i_13_n_10\,
      O(4) => \ysqr_reg[53]_i_13_n_11\,
      O(3) => \ysqr_reg[53]_i_13_n_12\,
      O(2) => \ysqr_reg[53]_i_13_n_13\,
      O(1) => \ysqr_reg[53]_i_13_n_14\,
      O(0) => \ysqr_reg[53]_i_13_n_15\,
      S(7) => \ysqr[53]_i_25_n_0\,
      S(6) => \ysqr[53]_i_26_n_0\,
      S(5) => \ysqr[53]_i_27_n_0\,
      S(4) => \ysqr[53]_i_28_n_0\,
      S(3) => \ysqr[53]_i_29_n_0\,
      S(2) => \ysqr[53]_i_30_n_0\,
      S(1) => \ysqr[53]_i_31_n_0\,
      S(0) => \ysqr[53]_i_32_n_0\
    );
\ysqr_reg[53]_i_17\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[39]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_ysqr_reg[53]_i_17_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \ysqr_reg[53]_i_17_n_4\,
      CO(2) => \NLW_ysqr_reg[53]_i_17_CO_UNCONNECTED\(2),
      CO(1) => \ysqr_reg[53]_i_17_n_6\,
      CO(0) => \ysqr_reg[53]_i_17_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \ysqr[53]_i_33_n_0\,
      DI(1) => \ysqr[53]_i_34_n_0\,
      DI(0) => \ysqr[53]_i_35_n_0\,
      O(7 downto 3) => \NLW_ysqr_reg[53]_i_17_O_UNCONNECTED\(7 downto 3),
      O(2) => \ysqr_reg[53]_i_17_n_13\,
      O(1) => \ysqr_reg[53]_i_17_n_14\,
      O(0) => \ysqr_reg[53]_i_17_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \ysqr[53]_i_36_n_0\,
      S(1) => \ysqr[53]_i_37_n_0\,
      S(0) => \ysqr[53]_i_38_n_0\
    );
\ysqr_reg[53]_i_18\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[39]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_ysqr_reg[53]_i_18_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \ysqr_reg[53]_i_18_n_5\,
      CO(1) => \NLW_ysqr_reg[53]_i_18_CO_UNCONNECTED\(1),
      CO(0) => \ysqr_reg[53]_i_18_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \ysqr[53]_i_39_n_0\,
      DI(0) => \ysqr[53]_i_40_n_0\,
      O(7 downto 2) => \NLW_ysqr_reg[53]_i_18_O_UNCONNECTED\(7 downto 2),
      O(1) => \ysqr_reg[53]_i_18_n_14\,
      O(0) => \ysqr_reg[53]_i_18_n_15\,
      S(7 downto 2) => B"000001",
      S(1) => \ysqr[53]_i_41_n_0\,
      S(0) => \ysqr[53]_i_42_n_0\
    );
\ysqr_reg[53]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[47]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_ysqr_reg[53]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \ysqr_reg[53]_i_2_n_3\,
      CO(3) => \ysqr_reg[53]_i_2_n_4\,
      CO(2) => \ysqr_reg[53]_i_2_n_5\,
      CO(1) => \ysqr_reg[53]_i_2_n_6\,
      CO(0) => \ysqr_reg[53]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \ysqr_reg[53]_i_3_n_13\,
      DI(3) => \ysqr[53]_i_4_n_0\,
      DI(2) => \ysqr[53]_i_5_n_0\,
      DI(1) => \ysqr[53]_i_6_n_0\,
      DI(0) => \ysqr[53]_i_7_n_0\,
      O(7 downto 6) => \NLW_ysqr_reg[53]_i_2_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => ysqr01_in(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \ysqr_reg[53]_i_3_n_12\,
      S(4) => \ysqr[53]_i_8_n_0\,
      S(3) => \ysqr[53]_i_9_n_0\,
      S(2) => \ysqr[53]_i_10_n_0\,
      S(1) => \ysqr[53]_i_11_n_0\,
      S(0) => \ysqr[53]_i_12_n_0\
    );
\ysqr_reg[53]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[53]_i_13_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_ysqr_reg[53]_i_3_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \ysqr_reg[53]_i_3_n_5\,
      CO(1) => \ysqr_reg[53]_i_3_n_6\,
      CO(0) => \ysqr_reg[53]_i_3_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \dy_reg_n_0_[26]\,
      DI(1) => '0',
      DI(0) => \dy_reg_n_0_[25]\,
      O(7 downto 4) => \NLW_ysqr_reg[53]_i_3_O_UNCONNECTED\(7 downto 4),
      O(3) => \ysqr_reg[53]_i_3_n_12\,
      O(2) => \ysqr_reg[53]_i_3_n_13\,
      O(1) => \ysqr_reg[53]_i_3_n_14\,
      O(0) => \ysqr_reg[53]_i_3_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \ysqr[53]_i_14_n_0\,
      S(1) => \ysqr[53]_i_15_n_0\,
      S(0) => \ysqr[53]_i_16_n_0\
    );
\ysqr_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[54]_i_1_n_0\,
      Q => ysqr(54)
    );
\ysqr_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[56]_i_1_n_0\,
      Q => ysqr(56)
    );
\ysqr_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[57]_i_1_n_0\,
      Q => ysqr(57)
    );
\ysqr_reg[57]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[57]_i_2_n_0\,
      CO(6) => \ysqr_reg[57]_i_2_n_1\,
      CO(5) => \ysqr_reg[57]_i_2_n_2\,
      CO(4) => \ysqr_reg[57]_i_2_n_3\,
      CO(3) => \ysqr_reg[57]_i_2_n_4\,
      CO(2) => \ysqr_reg[57]_i_2_n_5\,
      CO(1) => \ysqr_reg[57]_i_2_n_6\,
      CO(0) => \ysqr_reg[57]_i_2_n_7\,
      DI(7) => \ysqr[57]_i_4_n_0\,
      DI(6) => \ysqr[57]_i_5_n_0\,
      DI(5) => \ysqr[57]_i_6_n_0\,
      DI(4) => \ysqr[57]_i_7_n_0\,
      DI(3) => \ysqr[57]_i_8_n_0\,
      DI(2) => \ysqr[57]_i_9_n_0\,
      DI(1) => \dy_reg_n_0_[28]\,
      DI(0) => '0',
      O(7) => \ysqr_reg[57]_i_2_n_8\,
      O(6) => \ysqr_reg[57]_i_2_n_9\,
      O(5) => \ysqr_reg[57]_i_2_n_10\,
      O(4) => \ysqr_reg[57]_i_2_n_11\,
      O(3) => \ysqr_reg[57]_i_2_n_12\,
      O(2) => \ysqr_reg[57]_i_2_n_13\,
      O(1) => ysqr02_in(2),
      O(0) => \NLW_ysqr_reg[57]_i_2_O_UNCONNECTED\(0),
      S(7) => \ysqr[57]_i_10_n_0\,
      S(6) => \ysqr[57]_i_11_n_0\,
      S(5) => \ysqr[57]_i_12_n_0\,
      S(4) => \ysqr[57]_i_13_n_0\,
      S(3) => \ysqr[57]_i_14_n_0\,
      S(2) => \ysqr[57]_i_15_n_0\,
      S(1) => \ysqr[57]_i_16_n_0\,
      S(0) => '0'
    );
\ysqr_reg[57]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[57]_i_3_n_0\,
      CO(6) => \ysqr_reg[57]_i_3_n_1\,
      CO(5) => \ysqr_reg[57]_i_3_n_2\,
      CO(4) => \ysqr_reg[57]_i_3_n_3\,
      CO(3) => \ysqr_reg[57]_i_3_n_4\,
      CO(2) => \ysqr_reg[57]_i_3_n_5\,
      CO(1) => \ysqr_reg[57]_i_3_n_6\,
      CO(0) => \ysqr_reg[57]_i_3_n_7\,
      DI(7) => \ysqr[57]_i_17_n_0\,
      DI(6) => \ysqr[57]_i_18_n_0\,
      DI(5) => \dy_reg_n_0_[31]\,
      DI(4) => \ysqr[57]_i_19_n_0\,
      DI(3) => \ysqr[57]_i_20_n_0\,
      DI(2) => \ysqr[57]_i_21_n_0\,
      DI(1) => \ysqr[57]_i_22_n_0\,
      DI(0) => '0',
      O(7) => \ysqr_reg[57]_i_3_n_8\,
      O(6) => \ysqr_reg[57]_i_3_n_9\,
      O(5) => \ysqr_reg[57]_i_3_n_10\,
      O(4) => \ysqr_reg[57]_i_3_n_11\,
      O(3) => \ysqr_reg[57]_i_3_n_12\,
      O(2) => \ysqr_reg[57]_i_3_n_13\,
      O(1) => \ysqr_reg[57]_i_3_n_14\,
      O(0) => \ysqr_reg[57]_i_3_n_15\,
      S(7) => \ysqr[57]_i_23_n_0\,
      S(6) => \ysqr[57]_i_24_n_0\,
      S(5) => \ysqr[57]_i_25_n_0\,
      S(4) => \ysqr[57]_i_26_n_0\,
      S(3) => \ysqr[57]_i_27_n_0\,
      S(2) => \ysqr[57]_i_28_n_0\,
      S(1) => \ysqr[57]_i_29_n_0\,
      S(0) => \ysqr[57]_i_30_n_0\
    );
\ysqr_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[58]_i_1_n_0\,
      Q => ysqr(58)
    );
\ysqr_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[59]_i_1_n_0\,
      Q => ysqr(59)
    );
\ysqr_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[5]_i_1_n_0\,
      Q => ysqr(5)
    );
\ysqr_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[60]_i_1_n_0\,
      Q => ysqr(60)
    );
\ysqr_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[61]_i_1_n_0\,
      Q => ysqr(61)
    );
\ysqr_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[62]_i_1_n_0\,
      Q => ysqr(62)
    );
\ysqr_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[63]_i_1_n_0\,
      Q => ysqr(63)
    );
\ysqr_reg[64]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[64]_i_1_n_0\,
      Q => ysqr(64)
    );
\ysqr_reg[65]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[65]_i_1_n_0\,
      Q => ysqr(65)
    );
\ysqr_reg[65]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[65]_i_2_n_0\,
      CO(6) => \ysqr_reg[65]_i_2_n_1\,
      CO(5) => \ysqr_reg[65]_i_2_n_2\,
      CO(4) => \ysqr_reg[65]_i_2_n_3\,
      CO(3) => \ysqr_reg[65]_i_2_n_4\,
      CO(2) => \ysqr_reg[65]_i_2_n_5\,
      CO(1) => \ysqr_reg[65]_i_2_n_6\,
      CO(0) => \ysqr_reg[65]_i_2_n_7\,
      DI(7) => \ysqr[65]_i_3_n_0\,
      DI(6) => \ysqr[65]_i_4_n_0\,
      DI(5) => \ysqr[65]_i_5_n_0\,
      DI(4) => \ysqr[65]_i_6_n_0\,
      DI(3) => \ysqr[65]_i_7_n_0\,
      DI(2) => \ysqr[65]_i_8_n_0\,
      DI(1) => \ysqr[65]_i_9_n_0\,
      DI(0) => \ysqr[65]_i_10_n_0\,
      O(7 downto 0) => ysqr02_in(11 downto 4),
      S(7) => \ysqr[65]_i_11_n_0\,
      S(6) => \ysqr[65]_i_12_n_0\,
      S(5) => \ysqr[65]_i_13_n_0\,
      S(4) => \ysqr[65]_i_14_n_0\,
      S(3) => \ysqr[65]_i_15_n_0\,
      S(2) => \ysqr[65]_i_16_n_0\,
      S(1) => \ysqr[65]_i_17_n_0\,
      S(0) => \ysqr[65]_i_18_n_0\
    );
\ysqr_reg[66]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[66]_i_1_n_0\,
      Q => ysqr(66)
    );
\ysqr_reg[67]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[67]_i_1_n_0\,
      Q => ysqr(67)
    );
\ysqr_reg[68]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[68]_i_1_n_0\,
      Q => ysqr(68)
    );
\ysqr_reg[69]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[69]_i_1_n_0\,
      Q => ysqr(69)
    );
\ysqr_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[6]_i_1_n_0\,
      Q => ysqr(6)
    );
\ysqr_reg[70]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[70]_i_1_n_0\,
      Q => ysqr(70)
    );
\ysqr_reg[71]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[71]_i_1_n_0\,
      Q => ysqr(71)
    );
\ysqr_reg[71]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[71]_i_13_n_0\,
      CO(6) => \ysqr_reg[71]_i_13_n_1\,
      CO(5) => \ysqr_reg[71]_i_13_n_2\,
      CO(4) => \ysqr_reg[71]_i_13_n_3\,
      CO(3) => \ysqr_reg[71]_i_13_n_4\,
      CO(2) => \ysqr_reg[71]_i_13_n_5\,
      CO(1) => \ysqr_reg[71]_i_13_n_6\,
      CO(0) => \ysqr_reg[71]_i_13_n_7\,
      DI(7) => \ysqr[71]_i_19_n_0\,
      DI(6) => \ysqr[71]_i_20_n_0\,
      DI(5) => \ysqr[71]_i_21_n_0\,
      DI(4) => \ysqr[71]_i_22_n_0\,
      DI(3) => \ysqr[71]_i_23_n_0\,
      DI(2) => \ysqr[57]_i_31_n_0\,
      DI(1) => \ysqr[71]_i_24_n_0\,
      DI(0) => '0',
      O(7) => \ysqr_reg[71]_i_13_n_8\,
      O(6) => \ysqr_reg[71]_i_13_n_9\,
      O(5) => \ysqr_reg[71]_i_13_n_10\,
      O(4) => \ysqr_reg[71]_i_13_n_11\,
      O(3) => \ysqr_reg[71]_i_13_n_12\,
      O(2) => \ysqr_reg[71]_i_13_n_13\,
      O(1) => \ysqr_reg[71]_i_13_n_14\,
      O(0) => \ysqr_reg[71]_i_13_n_15\,
      S(7) => \ysqr[71]_i_25_n_0\,
      S(6) => \ysqr[71]_i_26_n_0\,
      S(5) => \ysqr[71]_i_27_n_0\,
      S(4) => \ysqr[71]_i_28_n_0\,
      S(3) => \ysqr[71]_i_29_n_0\,
      S(2) => \ysqr[71]_i_30_n_0\,
      S(1) => \ysqr[71]_i_31_n_0\,
      S(0) => \ysqr[71]_i_32_n_0\
    );
\ysqr_reg[71]_i_17\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[57]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_ysqr_reg[71]_i_17_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \ysqr_reg[71]_i_17_n_4\,
      CO(2) => \NLW_ysqr_reg[71]_i_17_CO_UNCONNECTED\(2),
      CO(1) => \ysqr_reg[71]_i_17_n_6\,
      CO(0) => \ysqr_reg[71]_i_17_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \ysqr[71]_i_33_n_0\,
      DI(1) => \ysqr[71]_i_34_n_0\,
      DI(0) => \ysqr[71]_i_35_n_0\,
      O(7 downto 3) => \NLW_ysqr_reg[71]_i_17_O_UNCONNECTED\(7 downto 3),
      O(2) => \ysqr_reg[71]_i_17_n_13\,
      O(1) => \ysqr_reg[71]_i_17_n_14\,
      O(0) => \ysqr_reg[71]_i_17_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \ysqr[71]_i_36_n_0\,
      S(1) => \ysqr[71]_i_37_n_0\,
      S(0) => \ysqr[71]_i_38_n_0\
    );
\ysqr_reg[71]_i_18\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[57]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_ysqr_reg[71]_i_18_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \ysqr_reg[71]_i_18_n_5\,
      CO(1) => \NLW_ysqr_reg[71]_i_18_CO_UNCONNECTED\(1),
      CO(0) => \ysqr_reg[71]_i_18_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \ysqr[71]_i_39_n_0\,
      DI(0) => \ysqr[71]_i_40_n_0\,
      O(7 downto 2) => \NLW_ysqr_reg[71]_i_18_O_UNCONNECTED\(7 downto 2),
      O(1) => \ysqr_reg[71]_i_18_n_14\,
      O(0) => \ysqr_reg[71]_i_18_n_15\,
      S(7 downto 2) => B"000001",
      S(1) => \ysqr[71]_i_41_n_0\,
      S(0) => \ysqr[71]_i_42_n_0\
    );
\ysqr_reg[71]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[65]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_ysqr_reg[71]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \ysqr_reg[71]_i_2_n_3\,
      CO(3) => \ysqr_reg[71]_i_2_n_4\,
      CO(2) => \ysqr_reg[71]_i_2_n_5\,
      CO(1) => \ysqr_reg[71]_i_2_n_6\,
      CO(0) => \ysqr_reg[71]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \ysqr_reg[71]_i_3_n_13\,
      DI(3) => \ysqr[71]_i_4_n_0\,
      DI(2) => \ysqr[71]_i_5_n_0\,
      DI(1) => \ysqr[71]_i_6_n_0\,
      DI(0) => \ysqr[71]_i_7_n_0\,
      O(7 downto 6) => \NLW_ysqr_reg[71]_i_2_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => ysqr02_in(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \ysqr_reg[71]_i_3_n_12\,
      S(4) => \ysqr[71]_i_8_n_0\,
      S(3) => \ysqr[71]_i_9_n_0\,
      S(2) => \ysqr[71]_i_10_n_0\,
      S(1) => \ysqr[71]_i_11_n_0\,
      S(0) => \ysqr[71]_i_12_n_0\
    );
\ysqr_reg[71]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[71]_i_13_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_ysqr_reg[71]_i_3_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \ysqr_reg[71]_i_3_n_5\,
      CO(1) => \ysqr_reg[71]_i_3_n_6\,
      CO(0) => \ysqr_reg[71]_i_3_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \dy_reg_n_0_[35]\,
      DI(1) => '0',
      DI(0) => \dy_reg_n_0_[34]\,
      O(7 downto 4) => \NLW_ysqr_reg[71]_i_3_O_UNCONNECTED\(7 downto 4),
      O(3) => \ysqr_reg[71]_i_3_n_12\,
      O(2) => \ysqr_reg[71]_i_3_n_13\,
      O(1) => \ysqr_reg[71]_i_3_n_14\,
      O(0) => \ysqr_reg[71]_i_3_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \ysqr[71]_i_14_n_0\,
      S(1) => \ysqr[71]_i_15_n_0\,
      S(0) => \ysqr[71]_i_16_n_0\
    );
\ysqr_reg[72]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[72]_i_1_n_0\,
      Q => ysqr(72)
    );
\ysqr_reg[74]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[74]_i_1_n_0\,
      Q => ysqr(74)
    );
\ysqr_reg[75]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[75]_i_1_n_0\,
      Q => ysqr(75)
    );
\ysqr_reg[75]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[75]_i_2_n_0\,
      CO(6) => \ysqr_reg[75]_i_2_n_1\,
      CO(5) => \ysqr_reg[75]_i_2_n_2\,
      CO(4) => \ysqr_reg[75]_i_2_n_3\,
      CO(3) => \ysqr_reg[75]_i_2_n_4\,
      CO(2) => \ysqr_reg[75]_i_2_n_5\,
      CO(1) => \ysqr_reg[75]_i_2_n_6\,
      CO(0) => \ysqr_reg[75]_i_2_n_7\,
      DI(7) => \ysqr[75]_i_4_n_0\,
      DI(6) => \ysqr[75]_i_5_n_0\,
      DI(5) => \ysqr[75]_i_6_n_0\,
      DI(4) => \ysqr[75]_i_7_n_0\,
      DI(3) => \ysqr[75]_i_8_n_0\,
      DI(2) => \ysqr[75]_i_9_n_0\,
      DI(1) => \dy_reg_n_0_[37]\,
      DI(0) => '0',
      O(7) => \ysqr_reg[75]_i_2_n_8\,
      O(6) => \ysqr_reg[75]_i_2_n_9\,
      O(5) => \ysqr_reg[75]_i_2_n_10\,
      O(4) => \ysqr_reg[75]_i_2_n_11\,
      O(3) => \ysqr_reg[75]_i_2_n_12\,
      O(2) => \ysqr_reg[75]_i_2_n_13\,
      O(1) => ysqr03_in(2),
      O(0) => \NLW_ysqr_reg[75]_i_2_O_UNCONNECTED\(0),
      S(7) => \ysqr[75]_i_10_n_0\,
      S(6) => \ysqr[75]_i_11_n_0\,
      S(5) => \ysqr[75]_i_12_n_0\,
      S(4) => \ysqr[75]_i_13_n_0\,
      S(3) => \ysqr[75]_i_14_n_0\,
      S(2) => \ysqr[75]_i_15_n_0\,
      S(1) => \ysqr[75]_i_16_n_0\,
      S(0) => '0'
    );
\ysqr_reg[75]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[75]_i_3_n_0\,
      CO(6) => \ysqr_reg[75]_i_3_n_1\,
      CO(5) => \ysqr_reg[75]_i_3_n_2\,
      CO(4) => \ysqr_reg[75]_i_3_n_3\,
      CO(3) => \ysqr_reg[75]_i_3_n_4\,
      CO(2) => \ysqr_reg[75]_i_3_n_5\,
      CO(1) => \ysqr_reg[75]_i_3_n_6\,
      CO(0) => \ysqr_reg[75]_i_3_n_7\,
      DI(7) => \ysqr[75]_i_17_n_0\,
      DI(6) => \ysqr[75]_i_18_n_0\,
      DI(5) => \dy_reg_n_0_[40]\,
      DI(4) => \ysqr[75]_i_19_n_0\,
      DI(3) => \ysqr[75]_i_20_n_0\,
      DI(2) => \ysqr[75]_i_21_n_0\,
      DI(1) => \ysqr[75]_i_22_n_0\,
      DI(0) => '0',
      O(7) => \ysqr_reg[75]_i_3_n_8\,
      O(6) => \ysqr_reg[75]_i_3_n_9\,
      O(5) => \ysqr_reg[75]_i_3_n_10\,
      O(4) => \ysqr_reg[75]_i_3_n_11\,
      O(3) => \ysqr_reg[75]_i_3_n_12\,
      O(2) => \ysqr_reg[75]_i_3_n_13\,
      O(1) => \ysqr_reg[75]_i_3_n_14\,
      O(0) => \ysqr_reg[75]_i_3_n_15\,
      S(7) => \ysqr[75]_i_23_n_0\,
      S(6) => \ysqr[75]_i_24_n_0\,
      S(5) => \ysqr[75]_i_25_n_0\,
      S(4) => \ysqr[75]_i_26_n_0\,
      S(3) => \ysqr[75]_i_27_n_0\,
      S(2) => \ysqr[75]_i_28_n_0\,
      S(1) => \ysqr[75]_i_29_n_0\,
      S(0) => \ysqr[75]_i_30_n_0\
    );
\ysqr_reg[76]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[76]_i_1_n_0\,
      Q => ysqr(76)
    );
\ysqr_reg[77]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[77]_i_1_n_0\,
      Q => ysqr(77)
    );
\ysqr_reg[78]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[78]_i_1_n_0\,
      Q => ysqr(78)
    );
\ysqr_reg[79]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[79]_i_1_n_0\,
      Q => ysqr(79)
    );
\ysqr_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[7]_i_1_n_0\,
      Q => ysqr(7)
    );
\ysqr_reg[80]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[80]_i_1_n_0\,
      Q => ysqr(80)
    );
\ysqr_reg[81]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[81]_i_1_n_0\,
      Q => ysqr(81)
    );
\ysqr_reg[82]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[82]_i_1_n_0\,
      Q => ysqr(82)
    );
\ysqr_reg[83]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[83]_i_1_n_0\,
      Q => ysqr(83)
    );
\ysqr_reg[83]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[83]_i_2_n_0\,
      CO(6) => \ysqr_reg[83]_i_2_n_1\,
      CO(5) => \ysqr_reg[83]_i_2_n_2\,
      CO(4) => \ysqr_reg[83]_i_2_n_3\,
      CO(3) => \ysqr_reg[83]_i_2_n_4\,
      CO(2) => \ysqr_reg[83]_i_2_n_5\,
      CO(1) => \ysqr_reg[83]_i_2_n_6\,
      CO(0) => \ysqr_reg[83]_i_2_n_7\,
      DI(7) => \ysqr[83]_i_3_n_0\,
      DI(6) => \ysqr[83]_i_4_n_0\,
      DI(5) => \ysqr[83]_i_5_n_0\,
      DI(4) => \ysqr[83]_i_6_n_0\,
      DI(3) => \ysqr[83]_i_7_n_0\,
      DI(2) => \ysqr[83]_i_8_n_0\,
      DI(1) => \ysqr[83]_i_9_n_0\,
      DI(0) => \ysqr[83]_i_10_n_0\,
      O(7 downto 0) => ysqr03_in(11 downto 4),
      S(7) => \ysqr[83]_i_11_n_0\,
      S(6) => \ysqr[83]_i_12_n_0\,
      S(5) => \ysqr[83]_i_13_n_0\,
      S(4) => \ysqr[83]_i_14_n_0\,
      S(3) => \ysqr[83]_i_15_n_0\,
      S(2) => \ysqr[83]_i_16_n_0\,
      S(1) => \ysqr[83]_i_17_n_0\,
      S(0) => \ysqr[83]_i_18_n_0\
    );
\ysqr_reg[84]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[84]_i_1_n_0\,
      Q => ysqr(84)
    );
\ysqr_reg[85]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[85]_i_1_n_0\,
      Q => ysqr(85)
    );
\ysqr_reg[86]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[86]_i_1_n_0\,
      Q => ysqr(86)
    );
\ysqr_reg[87]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[87]_i_1_n_0\,
      Q => ysqr(87)
    );
\ysqr_reg[88]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[88]_i_1_n_0\,
      Q => ysqr(88)
    );
\ysqr_reg[89]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[89]_i_1_n_0\,
      Q => ysqr(89)
    );
\ysqr_reg[89]_i_13\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \ysqr_reg[89]_i_13_n_0\,
      CO(6) => \ysqr_reg[89]_i_13_n_1\,
      CO(5) => \ysqr_reg[89]_i_13_n_2\,
      CO(4) => \ysqr_reg[89]_i_13_n_3\,
      CO(3) => \ysqr_reg[89]_i_13_n_4\,
      CO(2) => \ysqr_reg[89]_i_13_n_5\,
      CO(1) => \ysqr_reg[89]_i_13_n_6\,
      CO(0) => \ysqr_reg[89]_i_13_n_7\,
      DI(7) => \ysqr[89]_i_19_n_0\,
      DI(6) => \ysqr[89]_i_20_n_0\,
      DI(5) => \ysqr[89]_i_21_n_0\,
      DI(4) => \ysqr[89]_i_22_n_0\,
      DI(3) => \ysqr[89]_i_23_n_0\,
      DI(2) => \ysqr[75]_i_31_n_0\,
      DI(1) => \ysqr[89]_i_24_n_0\,
      DI(0) => '0',
      O(7) => \ysqr_reg[89]_i_13_n_8\,
      O(6) => \ysqr_reg[89]_i_13_n_9\,
      O(5) => \ysqr_reg[89]_i_13_n_10\,
      O(4) => \ysqr_reg[89]_i_13_n_11\,
      O(3) => \ysqr_reg[89]_i_13_n_12\,
      O(2) => \ysqr_reg[89]_i_13_n_13\,
      O(1) => \ysqr_reg[89]_i_13_n_14\,
      O(0) => \ysqr_reg[89]_i_13_n_15\,
      S(7) => \ysqr[89]_i_25_n_0\,
      S(6) => \ysqr[89]_i_26_n_0\,
      S(5) => \ysqr[89]_i_27_n_0\,
      S(4) => \ysqr[89]_i_28_n_0\,
      S(3) => \ysqr[89]_i_29_n_0\,
      S(2) => \ysqr[89]_i_30_n_0\,
      S(1) => \ysqr[89]_i_31_n_0\,
      S(0) => \ysqr[89]_i_32_n_0\
    );
\ysqr_reg[89]_i_17\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[75]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_ysqr_reg[89]_i_17_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \ysqr_reg[89]_i_17_n_4\,
      CO(2) => \NLW_ysqr_reg[89]_i_17_CO_UNCONNECTED\(2),
      CO(1) => \ysqr_reg[89]_i_17_n_6\,
      CO(0) => \ysqr_reg[89]_i_17_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \ysqr[89]_i_33_n_0\,
      DI(1) => \ysqr[89]_i_34_n_0\,
      DI(0) => \ysqr[89]_i_35_n_0\,
      O(7 downto 3) => \NLW_ysqr_reg[89]_i_17_O_UNCONNECTED\(7 downto 3),
      O(2) => \ysqr_reg[89]_i_17_n_13\,
      O(1) => \ysqr_reg[89]_i_17_n_14\,
      O(0) => \ysqr_reg[89]_i_17_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \ysqr[89]_i_36_n_0\,
      S(1) => \ysqr[89]_i_37_n_0\,
      S(0) => \ysqr[89]_i_38_n_0\
    );
\ysqr_reg[89]_i_18\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[75]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_ysqr_reg[89]_i_18_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \ysqr_reg[89]_i_18_n_5\,
      CO(1) => \NLW_ysqr_reg[89]_i_18_CO_UNCONNECTED\(1),
      CO(0) => \ysqr_reg[89]_i_18_n_7\,
      DI(7 downto 2) => B"000000",
      DI(1) => \ysqr[89]_i_39_n_0\,
      DI(0) => \ysqr[89]_i_40_n_0\,
      O(7 downto 2) => \NLW_ysqr_reg[89]_i_18_O_UNCONNECTED\(7 downto 2),
      O(1) => \ysqr_reg[89]_i_18_n_14\,
      O(0) => \ysqr_reg[89]_i_18_n_15\,
      S(7 downto 2) => B"000001",
      S(1) => \ysqr[89]_i_41_n_0\,
      S(0) => \ysqr[89]_i_42_n_0\
    );
\ysqr_reg[89]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[83]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_ysqr_reg[89]_i_2_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \ysqr_reg[89]_i_2_n_3\,
      CO(3) => \ysqr_reg[89]_i_2_n_4\,
      CO(2) => \ysqr_reg[89]_i_2_n_5\,
      CO(1) => \ysqr_reg[89]_i_2_n_6\,
      CO(0) => \ysqr_reg[89]_i_2_n_7\,
      DI(7 downto 5) => B"000",
      DI(4) => \ysqr_reg[89]_i_3_n_13\,
      DI(3) => \ysqr[89]_i_4_n_0\,
      DI(2) => \ysqr[89]_i_5_n_0\,
      DI(1) => \ysqr[89]_i_6_n_0\,
      DI(0) => \ysqr[89]_i_7_n_0\,
      O(7 downto 6) => \NLW_ysqr_reg[89]_i_2_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => ysqr03_in(17 downto 12),
      S(7 downto 6) => B"00",
      S(5) => \ysqr_reg[89]_i_3_n_12\,
      S(4) => \ysqr[89]_i_8_n_0\,
      S(3) => \ysqr[89]_i_9_n_0\,
      S(2) => \ysqr[89]_i_10_n_0\,
      S(1) => \ysqr[89]_i_11_n_0\,
      S(0) => \ysqr[89]_i_12_n_0\
    );
\ysqr_reg[89]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \ysqr_reg[89]_i_13_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_ysqr_reg[89]_i_3_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \ysqr_reg[89]_i_3_n_5\,
      CO(1) => \ysqr_reg[89]_i_3_n_6\,
      CO(0) => \ysqr_reg[89]_i_3_n_7\,
      DI(7 downto 3) => B"00000",
      DI(2) => \dy_reg_n_0_[44]\,
      DI(1) => '0',
      DI(0) => \dy_reg_n_0_[43]\,
      O(7 downto 4) => \NLW_ysqr_reg[89]_i_3_O_UNCONNECTED\(7 downto 4),
      O(3) => \ysqr_reg[89]_i_3_n_12\,
      O(2) => \ysqr_reg[89]_i_3_n_13\,
      O(1) => \ysqr_reg[89]_i_3_n_14\,
      O(0) => \ysqr_reg[89]_i_3_n_15\,
      S(7 downto 3) => B"00001",
      S(2) => \ysqr[89]_i_14_n_0\,
      S(1) => \ysqr[89]_i_15_n_0\,
      S(0) => \ysqr[89]_i_16_n_0\
    );
\ysqr_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[8]_i_1_n_0\,
      Q => ysqr(8)
    );
\ysqr_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \xsqr[89]_i_1_n_0\,
      CLR => linNotLog_reg_0,
      D => \ysqr[9]_i_1_n_0\,
      Q => ysqr(9)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Cputrack is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    ackInvCputrackSelect : out STD_LOGIC;
    ackInvCputrackSet : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \FSM_onehot_stateSeq_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    seqbufCputrackToHostifAXIS_tvalid : out STD_LOGIC;
    cputrackGetInfoTixVState : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ackSeqbufCputrackToHostif : out STD_LOGIC;
    cputrackGetInfoPtr0Seqbuf : out STD_LOGIC_VECTOR ( 9 downto 0 );
    aclk_sig : in STD_LOGIC;
    AR : in STD_LOGIC_VECTOR ( 0 to 0 );
    hdrNotFix : in STD_LOGIC;
    reqInvSelect : in STD_LOGIC;
    ackInvSelect_sig_reg_0 : in STD_LOGIC;
    reqInvCputrackSet : in STD_LOGIC;
    restart_reg_0 : in STD_LOGIC;
    dneSeqbufCputrackToHostif : in STD_LOGIC;
    seqbufCputrackToHostifAXIS_tready : in STD_LOGIC;
    reqSeqbufCputrackToHostif : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 23 downto 0 );
    \tixVCapture_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \TCaptMax_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    stateOp_dbg : in STD_LOGIC_VECTOR ( 6 downto 0 );
    hostifStateOp_dbg : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Cputrack : entity is "Cputrack";
end design_1_Vsp_core_0_0_Cputrack;

architecture STRUCTURE of design_1_Vsp_core_0_0_Cputrack is
  signal \FSM_onehot_stateSeq[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[3]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[3]_i_3__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[3]_i_4__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_3__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_4__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_5__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_6__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_7__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_8__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_9_n_0\ : STD_LOGIC;
  signal \^fsm_onehot_stateseq_reg[3]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \FSM_onehot_stateSeq_reg_n_0_[4]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal TCapt : STD_LOGIC;
  signal TCaptMax : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[0]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[10]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[11]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[12]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[13]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[14]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[15]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[16]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[17]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[18]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[19]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[1]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[20]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[21]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[22]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[23]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[24]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[25]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[26]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[27]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[28]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[29]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[2]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[30]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[31]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[3]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[4]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[5]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[6]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[7]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[8]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[9]\ : STD_LOGIC;
  signal \TCapt__0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \aSeqbufB[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbufB[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbufB[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbufB[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbufB[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbufB[5]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbufB[5]_i_2__2_n_0\ : STD_LOGIC;
  signal \aSeqbufB[6]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbufB[7]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_2__2_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_3__2_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_4__2_n_0\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[0]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[1]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[2]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[3]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[4]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[5]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[6]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[7]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[8]\ : STD_LOGIC;
  signal \aSeqbuf[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[5]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[6]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[6]_i_2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[7]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[7]_i_2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[7]_i_3_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_2__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_3__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_4__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_5__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_6_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_10_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_1__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_2__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_3__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_4__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_5__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_6__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_7__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_8_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_9_n_0\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[0]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[1]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[2]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[3]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[4]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[5]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[6]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[7]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[8]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[9]\ : STD_LOGIC;
  signal \^ackinvcputrackselect\ : STD_LOGIC;
  signal \^ackinvcputrackset\ : STD_LOGIC;
  signal \ackInvSelect_sig_i_1__2_n_0\ : STD_LOGIC;
  signal \ackInvSet_sig_i_1__7_n_0\ : STD_LOGIC;
  signal \ackInvSet_sig_i_2__4_n_0\ : STD_LOGIC;
  signal ackSeqbufBToSeqClear : STD_LOGIC;
  signal \burstCnt[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[10]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[10]_i_2__1_n_0\ : STD_LOGIC;
  signal \burstCnt[11]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[11]_i_2__2_n_0\ : STD_LOGIC;
  signal \burstCnt[12]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[12]_i_2__1_n_0\ : STD_LOGIC;
  signal \burstCnt[13]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[13]_i_2__0_n_0\ : STD_LOGIC;
  signal \burstCnt[13]_i_3_n_0\ : STD_LOGIC;
  signal \burstCnt[13]_i_4_n_0\ : STD_LOGIC;
  signal \burstCnt[13]_i_5_n_0\ : STD_LOGIC;
  signal \burstCnt[14]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_10__2_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_11__2_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_12__2_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_13__1_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_14__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_15__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_16__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_17__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_18__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_19__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_20__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_21__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_22__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_23__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_24__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_25__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_2__2_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_3__1_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_4__2_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_5__2_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_6__2_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_7__2_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_8__2_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_9__2_n_0\ : STD_LOGIC;
  signal \burstCnt[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \burstCnt[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \burstCnt[5]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[5]_i_2__2_n_0\ : STD_LOGIC;
  signal \burstCnt[6]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[6]_i_2__1_n_0\ : STD_LOGIC;
  signal \burstCnt[7]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[7]_i_2__1_n_0\ : STD_LOGIC;
  signal \burstCnt[8]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[8]_i_2__1_n_0\ : STD_LOGIC;
  signal \burstCnt[9]_i_1__2_n_0\ : STD_LOGIC;
  signal \burstCnt[9]_i_2__2_n_0\ : STD_LOGIC;
  signal \burstCnt[9]_i_3__0_n_0\ : STD_LOGIC;
  signal \burstCnt[9]_i_4_n_0\ : STD_LOGIC;
  signal \burstCnt[9]_i_5_n_0\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[14]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[9]\ : STD_LOGIC;
  signal \burstState[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstState[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstState[2]_i_1_n_0\ : STD_LOGIC;
  signal \burstState[3]_i_1_n_0\ : STD_LOGIC;
  signal \burstState[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstState[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstState[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstState[7]_i_1_n_0\ : STD_LOGIC;
  signal \burstState_reg_n_0_[0]\ : STD_LOGIC;
  signal \burstState_reg_n_0_[1]\ : STD_LOGIC;
  signal \burstState_reg_n_0_[2]\ : STD_LOGIC;
  signal \burstState_reg_n_0_[3]\ : STD_LOGIC;
  signal \burstState_reg_n_0_[4]\ : STD_LOGIC;
  signal \burstState_reg_n_0_[5]\ : STD_LOGIC;
  signal \burstState_reg_n_0_[6]\ : STD_LOGIC;
  signal \burstState_reg_n_0_[7]\ : STD_LOGIC;
  signal \^cputrackgetinfotixvstate\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal dwrSeqbuf : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \dwrSeqbuf[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[10]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[10]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[11]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[11]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[12]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[12]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[13]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[13]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[14]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[14]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[14]_i_3_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[15]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[15]_i_2__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[15]_i_3__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[15]_i_4_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[15]_i_5_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[15]_i_6_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[15]_i_7_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[16]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[17]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[18]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[19]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[1]_i_3__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[20]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[21]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[22]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[23]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[23]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[24]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[25]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[26]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[27]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[28]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[29]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[2]_i_2__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[2]_i_3__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[30]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_2__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_3__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_4__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_5__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[3]_i_2__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[3]_i_3__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[5]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[5]_i_2__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[6]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[6]_i_2__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[7]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[7]_i_2__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[8]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[8]_i_2__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[9]_i_1__2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[9]_i_2__0_n_0\ : STD_LOGIC;
  signal enSeqbuf : STD_LOGIC;
  signal enSeqbuf_reg_n_0 : STD_LOGIC;
  signal first : STD_LOGIC;
  signal \first__0\ : STD_LOGIC;
  signal i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \i[1]_i_1__19_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_10__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_11__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_12__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_13__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_14__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_15__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_16__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_1__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_2__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_3__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_4__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_5__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_6__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_7__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_8__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_9__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_10__5_n_0\ : STD_LOGIC;
  signal \i__carry_i_11__4_n_0\ : STD_LOGIC;
  signal \i__carry_i_12__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_13__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_14__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_15__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_16__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_1__6_n_0\ : STD_LOGIC;
  signal \i__carry_i_2__6_n_0\ : STD_LOGIC;
  signal \i__carry_i_3__6_n_0\ : STD_LOGIC;
  signal \i__carry_i_4__6_n_0\ : STD_LOGIC;
  signal \i__carry_i_5__6_n_0\ : STD_LOGIC;
  signal \i__carry_i_6__6_n_0\ : STD_LOGIC;
  signal \i__carry_i_7__5_n_0\ : STD_LOGIC;
  signal \i__carry_i_8__5_n_0\ : STD_LOGIC;
  signal \i__carry_i_9__5_n_0\ : STD_LOGIC;
  signal \i_reg_n_0_[0]\ : STD_LOGIC;
  signal \i_reg_n_0_[1]\ : STD_LOGIC;
  signal in12 : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \plusOp_carry__0_n_0\ : STD_LOGIC;
  signal \plusOp_carry__0_n_1\ : STD_LOGIC;
  signal \plusOp_carry__0_n_2\ : STD_LOGIC;
  signal \plusOp_carry__0_n_3\ : STD_LOGIC;
  signal \plusOp_carry__0_n_4\ : STD_LOGIC;
  signal \plusOp_carry__0_n_5\ : STD_LOGIC;
  signal \plusOp_carry__0_n_6\ : STD_LOGIC;
  signal \plusOp_carry__0_n_7\ : STD_LOGIC;
  signal \plusOp_carry__1_n_0\ : STD_LOGIC;
  signal \plusOp_carry__1_n_1\ : STD_LOGIC;
  signal \plusOp_carry__1_n_2\ : STD_LOGIC;
  signal \plusOp_carry__1_n_3\ : STD_LOGIC;
  signal \plusOp_carry__1_n_4\ : STD_LOGIC;
  signal \plusOp_carry__1_n_5\ : STD_LOGIC;
  signal \plusOp_carry__1_n_6\ : STD_LOGIC;
  signal \plusOp_carry__1_n_7\ : STD_LOGIC;
  signal \plusOp_carry__2_n_2\ : STD_LOGIC;
  signal \plusOp_carry__2_n_3\ : STD_LOGIC;
  signal \plusOp_carry__2_n_4\ : STD_LOGIC;
  signal \plusOp_carry__2_n_5\ : STD_LOGIC;
  signal \plusOp_carry__2_n_6\ : STD_LOGIC;
  signal \plusOp_carry__2_n_7\ : STD_LOGIC;
  signal plusOp_carry_n_0 : STD_LOGIC;
  signal plusOp_carry_n_1 : STD_LOGIC;
  signal plusOp_carry_n_2 : STD_LOGIC;
  signal plusOp_carry_n_3 : STD_LOGIC;
  signal plusOp_carry_n_4 : STD_LOGIC;
  signal plusOp_carry_n_5 : STD_LOGIC;
  signal plusOp_carry_n_6 : STD_LOGIC;
  signal plusOp_carry_n_7 : STD_LOGIC;
  signal \ptr0SeqbufTrackNotFixed_i_1__2_n_0\ : STD_LOGIC;
  signal ptr0SeqbufTrackNotFixed_reg_n_0 : STD_LOGIC;
  signal quad : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \quad[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \quad[23]_i_1__0_n_0\ : STD_LOGIC;
  signal \quad[23]_i_3_n_0\ : STD_LOGIC;
  signal \quad[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \quad[7]_i_3_n_0\ : STD_LOGIC;
  signal \quad_reg_n_0_[0]\ : STD_LOGIC;
  signal \quad_reg_n_0_[10]\ : STD_LOGIC;
  signal \quad_reg_n_0_[11]\ : STD_LOGIC;
  signal \quad_reg_n_0_[12]\ : STD_LOGIC;
  signal \quad_reg_n_0_[13]\ : STD_LOGIC;
  signal \quad_reg_n_0_[14]\ : STD_LOGIC;
  signal \quad_reg_n_0_[15]\ : STD_LOGIC;
  signal \quad_reg_n_0_[16]\ : STD_LOGIC;
  signal \quad_reg_n_0_[17]\ : STD_LOGIC;
  signal \quad_reg_n_0_[18]\ : STD_LOGIC;
  signal \quad_reg_n_0_[19]\ : STD_LOGIC;
  signal \quad_reg_n_0_[1]\ : STD_LOGIC;
  signal \quad_reg_n_0_[20]\ : STD_LOGIC;
  signal \quad_reg_n_0_[21]\ : STD_LOGIC;
  signal \quad_reg_n_0_[22]\ : STD_LOGIC;
  signal \quad_reg_n_0_[23]\ : STD_LOGIC;
  signal \quad_reg_n_0_[24]\ : STD_LOGIC;
  signal \quad_reg_n_0_[25]\ : STD_LOGIC;
  signal \quad_reg_n_0_[26]\ : STD_LOGIC;
  signal \quad_reg_n_0_[27]\ : STD_LOGIC;
  signal \quad_reg_n_0_[28]\ : STD_LOGIC;
  signal \quad_reg_n_0_[29]\ : STD_LOGIC;
  signal \quad_reg_n_0_[2]\ : STD_LOGIC;
  signal \quad_reg_n_0_[30]\ : STD_LOGIC;
  signal \quad_reg_n_0_[31]\ : STD_LOGIC;
  signal \quad_reg_n_0_[3]\ : STD_LOGIC;
  signal \quad_reg_n_0_[4]\ : STD_LOGIC;
  signal \quad_reg_n_0_[5]\ : STD_LOGIC;
  signal \quad_reg_n_0_[6]\ : STD_LOGIC;
  signal \quad_reg_n_0_[7]\ : STD_LOGIC;
  signal \quad_reg_n_0_[8]\ : STD_LOGIC;
  signal \quad_reg_n_0_[9]\ : STD_LOGIC;
  signal rdySeq : STD_LOGIC;
  signal \restart_i_1__2_n_0\ : STD_LOGIC;
  signal restart_reg_n_0 : STD_LOGIC;
  signal rng_reg_n_0 : STD_LOGIC;
  signal staFallingNotRising : STD_LOGIC;
  signal staTixVTrigger : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal state : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal stateOp : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \stateOp[0]_i_1__12_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_1__12_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_10__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_11__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_12__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_13__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_14__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_15__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_16__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_17__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_18__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_19__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_20__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_21__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_22__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_2__4_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_3__4_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_5__4_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_6__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_7__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_8__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_9__1_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[2]_i_3__2_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[2]_i_7__2_n_0\ : STD_LOGIC;
  signal stateSeqbufB_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \state[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \state[1]_i_1_n_0\ : STD_LOGIC;
  signal \state[2]_i_1_n_0\ : STD_LOGIC;
  signal \state[3]_i_1_n_0\ : STD_LOGIC;
  signal \state[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \state[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \state[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \state[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \state[7]_i_2__0_n_0\ : STD_LOGIC;
  signal stoTixVTrigger : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \stop_lcl_i_1__2_n_0\ : STD_LOGIC;
  signal \stop_lcl_i_2__1_n_0\ : STD_LOGIC;
  signal stop_lcl_reg_n_0 : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_0\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_4\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_5\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_6\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_7\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_0\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_1\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_2\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_4\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_5\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_6\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_7\ : STD_LOGIC;
  signal \strbStop_i_1__2_n_0\ : STD_LOGIC;
  signal \strbStop_i_2__2_n_0\ : STD_LOGIC;
  signal \strbStop_i_3__1_n_0\ : STD_LOGIC;
  signal strbStop_reg_n_0 : STD_LOGIC;
  signal \tixVCapture_reg_n_0_[0]\ : STD_LOGIC;
  signal \tixVCapture_reg_n_0_[1]\ : STD_LOGIC;
  signal \tixVCapture_reg_n_0_[2]\ : STD_LOGIC;
  signal \tixVCapture_reg_n_0_[3]\ : STD_LOGIC;
  signal \tixVCapture_reg_n_0_[4]\ : STD_LOGIC;
  signal \tixVCapture_reg_n_0_[5]\ : STD_LOGIC;
  signal \tixVCapture_reg_n_0_[6]\ : STD_LOGIC;
  signal \tixVCapture_reg_n_0_[7]\ : STD_LOGIC;
  signal \NLW_plusOp_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_plusOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_strbStop5_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_strbStop5_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[2]_i_1__2\ : label is "soft_lutpair1491";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[3]_i_1__2\ : label is "soft_lutpair1491";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_2__2\ : label is "soft_lutpair1533";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_4__2\ : label is "soft_lutpair1544";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_6__2\ : label is "soft_lutpair1544";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_8__0\ : label is "soft_lutpair1530";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_9\ : label is "soft_lutpair1529";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[0]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[1]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[2]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[3]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[4]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[5]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute SOFT_HLUTNM of \TCapt[0]_i_1__2\ : label is "soft_lutpair1560";
  attribute SOFT_HLUTNM of \TCapt[10]_i_1__2\ : label is "soft_lutpair1555";
  attribute SOFT_HLUTNM of \TCapt[11]_i_1__2\ : label is "soft_lutpair1555";
  attribute SOFT_HLUTNM of \TCapt[12]_i_1__2\ : label is "soft_lutpair1554";
  attribute SOFT_HLUTNM of \TCapt[13]_i_1__2\ : label is "soft_lutpair1554";
  attribute SOFT_HLUTNM of \TCapt[14]_i_1__2\ : label is "soft_lutpair1553";
  attribute SOFT_HLUTNM of \TCapt[15]_i_1__2\ : label is "soft_lutpair1553";
  attribute SOFT_HLUTNM of \TCapt[16]_i_1__2\ : label is "soft_lutpair1552";
  attribute SOFT_HLUTNM of \TCapt[17]_i_1__2\ : label is "soft_lutpair1552";
  attribute SOFT_HLUTNM of \TCapt[18]_i_1__2\ : label is "soft_lutpair1551";
  attribute SOFT_HLUTNM of \TCapt[19]_i_1__2\ : label is "soft_lutpair1551";
  attribute SOFT_HLUTNM of \TCapt[1]_i_1__2\ : label is "soft_lutpair1560";
  attribute SOFT_HLUTNM of \TCapt[20]_i_1__2\ : label is "soft_lutpair1550";
  attribute SOFT_HLUTNM of \TCapt[21]_i_1__2\ : label is "soft_lutpair1550";
  attribute SOFT_HLUTNM of \TCapt[22]_i_1__2\ : label is "soft_lutpair1549";
  attribute SOFT_HLUTNM of \TCapt[23]_i_1__2\ : label is "soft_lutpair1549";
  attribute SOFT_HLUTNM of \TCapt[24]_i_1__2\ : label is "soft_lutpair1548";
  attribute SOFT_HLUTNM of \TCapt[25]_i_1__2\ : label is "soft_lutpair1548";
  attribute SOFT_HLUTNM of \TCapt[26]_i_1__2\ : label is "soft_lutpair1547";
  attribute SOFT_HLUTNM of \TCapt[27]_i_1__2\ : label is "soft_lutpair1547";
  attribute SOFT_HLUTNM of \TCapt[28]_i_1__2\ : label is "soft_lutpair1546";
  attribute SOFT_HLUTNM of \TCapt[29]_i_1__2\ : label is "soft_lutpair1546";
  attribute SOFT_HLUTNM of \TCapt[2]_i_1__2\ : label is "soft_lutpair1559";
  attribute SOFT_HLUTNM of \TCapt[30]_i_1__2\ : label is "soft_lutpair1545";
  attribute SOFT_HLUTNM of \TCapt[31]_i_1__2\ : label is "soft_lutpair1545";
  attribute SOFT_HLUTNM of \TCapt[3]_i_1__2\ : label is "soft_lutpair1559";
  attribute SOFT_HLUTNM of \TCapt[4]_i_1__2\ : label is "soft_lutpair1558";
  attribute SOFT_HLUTNM of \TCapt[5]_i_1__2\ : label is "soft_lutpair1558";
  attribute SOFT_HLUTNM of \TCapt[6]_i_1__2\ : label is "soft_lutpair1557";
  attribute SOFT_HLUTNM of \TCapt[7]_i_1__2\ : label is "soft_lutpair1557";
  attribute SOFT_HLUTNM of \TCapt[8]_i_1__2\ : label is "soft_lutpair1556";
  attribute SOFT_HLUTNM of \TCapt[9]_i_1__2\ : label is "soft_lutpair1556";
  attribute SOFT_HLUTNM of \aSeqbufB[1]_i_1__2\ : label is "soft_lutpair1523";
  attribute SOFT_HLUTNM of \aSeqbufB[2]_i_1__2\ : label is "soft_lutpair1523";
  attribute SOFT_HLUTNM of \aSeqbufB[5]_i_1__2\ : label is "soft_lutpair1524";
  attribute SOFT_HLUTNM of \aSeqbufB[6]_i_1__2\ : label is "soft_lutpair1490";
  attribute SOFT_HLUTNM of \aSeqbufB[7]_i_1__2\ : label is "soft_lutpair1490";
  attribute SOFT_HLUTNM of \aSeqbufB[8]_i_2__2\ : label is "soft_lutpair1486";
  attribute SOFT_HLUTNM of \aSeqbufB[8]_i_3__2\ : label is "soft_lutpair1533";
  attribute SOFT_HLUTNM of \aSeqbuf[1]_i_1__2\ : label is "soft_lutpair1538";
  attribute SOFT_HLUTNM of \aSeqbuf[2]_i_1__2\ : label is "soft_lutpair1494";
  attribute SOFT_HLUTNM of \aSeqbuf[3]_i_1__2\ : label is "soft_lutpair1494";
  attribute SOFT_HLUTNM of \aSeqbuf[6]_i_2\ : label is "soft_lutpair1538";
  attribute SOFT_HLUTNM of \aSeqbuf[7]_i_1__2\ : label is "soft_lutpair1528";
  attribute SOFT_HLUTNM of \aSeqbuf[7]_i_3\ : label is "soft_lutpair1495";
  attribute SOFT_HLUTNM of \aSeqbuf[8]_i_4__1\ : label is "soft_lutpair1496";
  attribute SOFT_HLUTNM of \aSeqbuf[8]_i_6\ : label is "soft_lutpair1496";
  attribute SOFT_HLUTNM of \aSeqbuf[9]_i_6__2\ : label is "soft_lutpair1495";
  attribute SOFT_HLUTNM of \aSeqbuf[9]_i_7__1\ : label is "soft_lutpair1489";
  attribute SOFT_HLUTNM of \aSeqbuf[9]_i_9\ : label is "soft_lutpair1489";
  attribute SOFT_HLUTNM of \ackInvSet_sig_i_2__4\ : label is "soft_lutpair1543";
  attribute SOFT_HLUTNM of \burstCnt[0]_i_1__2\ : label is "soft_lutpair1526";
  attribute SOFT_HLUTNM of \burstCnt[10]_i_1__2\ : label is "soft_lutpair1540";
  attribute SOFT_HLUTNM of \burstCnt[10]_i_2__1\ : label is "soft_lutpair1504";
  attribute SOFT_HLUTNM of \burstCnt[11]_i_1__2\ : label is "soft_lutpair1539";
  attribute SOFT_HLUTNM of \burstCnt[11]_i_2__2\ : label is "soft_lutpair1504";
  attribute SOFT_HLUTNM of \burstCnt[12]_i_1__2\ : label is "soft_lutpair1539";
  attribute SOFT_HLUTNM of \burstCnt[13]_i_1__2\ : label is "soft_lutpair1526";
  attribute SOFT_HLUTNM of \burstCnt[13]_i_5\ : label is "soft_lutpair1506";
  attribute SOFT_HLUTNM of \burstCnt[14]_i_1__2\ : label is "soft_lutpair1487";
  attribute SOFT_HLUTNM of \burstCnt[15]_i_15__0\ : label is "soft_lutpair1502";
  attribute SOFT_HLUTNM of \burstCnt[15]_i_24__0\ : label is "soft_lutpair1532";
  attribute SOFT_HLUTNM of \burstCnt[15]_i_3__1\ : label is "soft_lutpair1499";
  attribute SOFT_HLUTNM of \burstCnt[1]_i_1__2\ : label is "soft_lutpair1492";
  attribute SOFT_HLUTNM of \burstCnt[3]_i_2\ : label is "soft_lutpair1488";
  attribute SOFT_HLUTNM of \burstCnt[4]_i_1__2\ : label is "soft_lutpair1542";
  attribute SOFT_HLUTNM of \burstCnt[5]_i_1__2\ : label is "soft_lutpair1541";
  attribute SOFT_HLUTNM of \burstCnt[5]_i_2__2\ : label is "soft_lutpair1505";
  attribute SOFT_HLUTNM of \burstCnt[6]_i_1__2\ : label is "soft_lutpair1541";
  attribute SOFT_HLUTNM of \burstCnt[6]_i_2__1\ : label is "soft_lutpair1505";
  attribute SOFT_HLUTNM of \burstCnt[7]_i_1__2\ : label is "soft_lutpair1542";
  attribute SOFT_HLUTNM of \burstCnt[8]_i_1__2\ : label is "soft_lutpair1540";
  attribute SOFT_HLUTNM of \burstCnt[9]_i_1__2\ : label is "soft_lutpair1525";
  attribute SOFT_HLUTNM of \burstCnt[9]_i_4\ : label is "soft_lutpair1532";
  attribute SOFT_HLUTNM of \burstState[0]_i_1__0\ : label is "soft_lutpair1534";
  attribute SOFT_HLUTNM of \burstState[1]_i_1__0\ : label is "soft_lutpair1534";
  attribute SOFT_HLUTNM of \burstState[2]_i_1\ : label is "soft_lutpair1535";
  attribute SOFT_HLUTNM of \burstState[3]_i_1\ : label is "soft_lutpair1535";
  attribute SOFT_HLUTNM of \burstState[4]_i_1__0\ : label is "soft_lutpair1536";
  attribute SOFT_HLUTNM of \burstState[5]_i_1__0\ : label is "soft_lutpair1536";
  attribute SOFT_HLUTNM of \burstState[6]_i_1__0\ : label is "soft_lutpair1537";
  attribute SOFT_HLUTNM of \burstState[7]_i_1\ : label is "soft_lutpair1537";
  attribute SOFT_HLUTNM of \dwrSeqbuf[0]_i_2__2\ : label is "soft_lutpair1512";
  attribute SOFT_HLUTNM of \dwrSeqbuf[10]_i_2__0\ : label is "soft_lutpair1518";
  attribute SOFT_HLUTNM of \dwrSeqbuf[11]_i_2__0\ : label is "soft_lutpair1517";
  attribute SOFT_HLUTNM of \dwrSeqbuf[12]_i_2__0\ : label is "soft_lutpair1521";
  attribute SOFT_HLUTNM of \dwrSeqbuf[13]_i_2__0\ : label is "soft_lutpair1520";
  attribute SOFT_HLUTNM of \dwrSeqbuf[14]_i_2__0\ : label is "soft_lutpair1487";
  attribute SOFT_HLUTNM of \dwrSeqbuf[14]_i_3\ : label is "soft_lutpair1516";
  attribute SOFT_HLUTNM of \dwrSeqbuf[15]_i_3__1\ : label is "soft_lutpair1522";
  attribute SOFT_HLUTNM of \dwrSeqbuf[1]_i_2__2\ : label is "soft_lutpair1492";
  attribute SOFT_HLUTNM of \dwrSeqbuf[1]_i_3__2\ : label is "soft_lutpair1510";
  attribute SOFT_HLUTNM of \dwrSeqbuf[23]_i_2__0\ : label is "soft_lutpair1500";
  attribute SOFT_HLUTNM of \dwrSeqbuf[2]_i_2__2\ : label is "soft_lutpair1488";
  attribute SOFT_HLUTNM of \dwrSeqbuf[2]_i_3__2\ : label is "soft_lutpair1507";
  attribute SOFT_HLUTNM of \dwrSeqbuf[3]_i_2__2\ : label is "soft_lutpair1506";
  attribute SOFT_HLUTNM of \dwrSeqbuf[3]_i_3__2\ : label is "soft_lutpair1511";
  attribute SOFT_HLUTNM of \dwrSeqbuf[4]_i_2__2\ : label is "soft_lutpair1514";
  attribute SOFT_HLUTNM of \dwrSeqbuf[5]_i_2__2\ : label is "soft_lutpair1509";
  attribute SOFT_HLUTNM of \dwrSeqbuf[6]_i_2__1\ : label is "soft_lutpair1508";
  attribute SOFT_HLUTNM of \dwrSeqbuf[7]_i_2__2\ : label is "soft_lutpair1513";
  attribute SOFT_HLUTNM of \dwrSeqbuf[8]_i_2__1\ : label is "soft_lutpair1519";
  attribute SOFT_HLUTNM of \dwrSeqbuf[9]_i_2__0\ : label is "soft_lutpair1515";
  attribute SOFT_HLUTNM of \enSeqbuf_i_1__1\ : label is "soft_lutpair1497";
  attribute SOFT_HLUTNM of \i[0]_i_1__19\ : label is "soft_lutpair1503";
  attribute SOFT_HLUTNM of \i[1]_i_2__3\ : label is "soft_lutpair1498";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of plusOp_carry : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_carry__0\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_carry__1\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_carry__2\ : label is 35;
  attribute SOFT_HLUTNM of \quad[0]_i_1__2\ : label is "soft_lutpair1512";
  attribute SOFT_HLUTNM of \quad[10]_i_1__0\ : label is "soft_lutpair1518";
  attribute SOFT_HLUTNM of \quad[11]_i_1__0\ : label is "soft_lutpair1517";
  attribute SOFT_HLUTNM of \quad[12]_i_1__0\ : label is "soft_lutpair1521";
  attribute SOFT_HLUTNM of \quad[13]_i_1__0\ : label is "soft_lutpair1520";
  attribute SOFT_HLUTNM of \quad[14]_i_1__0\ : label is "soft_lutpair1516";
  attribute SOFT_HLUTNM of \quad[15]_i_2__0\ : label is "soft_lutpair1522";
  attribute SOFT_HLUTNM of \quad[1]_i_1__2\ : label is "soft_lutpair1510";
  attribute SOFT_HLUTNM of \quad[23]_i_3\ : label is "soft_lutpair1529";
  attribute SOFT_HLUTNM of \quad[24]_i_1__0\ : label is "soft_lutpair1497";
  attribute SOFT_HLUTNM of \quad[25]_i_1__0\ : label is "soft_lutpair1498";
  attribute SOFT_HLUTNM of \quad[26]_i_1__0\ : label is "soft_lutpair1499";
  attribute SOFT_HLUTNM of \quad[27]_i_1__0\ : label is "soft_lutpair1500";
  attribute SOFT_HLUTNM of \quad[28]_i_1__0\ : label is "soft_lutpair1501";
  attribute SOFT_HLUTNM of \quad[29]_i_1__0\ : label is "soft_lutpair1502";
  attribute SOFT_HLUTNM of \quad[2]_i_1__2\ : label is "soft_lutpair1507";
  attribute SOFT_HLUTNM of \quad[30]_i_1__0\ : label is "soft_lutpair1503";
  attribute SOFT_HLUTNM of \quad[3]_i_1__2\ : label is "soft_lutpair1511";
  attribute SOFT_HLUTNM of \quad[4]_i_1__2\ : label is "soft_lutpair1514";
  attribute SOFT_HLUTNM of \quad[5]_i_1__2\ : label is "soft_lutpair1509";
  attribute SOFT_HLUTNM of \quad[6]_i_1__1\ : label is "soft_lutpair1508";
  attribute SOFT_HLUTNM of \quad[7]_i_2__0\ : label is "soft_lutpair1513";
  attribute SOFT_HLUTNM of \quad[7]_i_3\ : label is "soft_lutpair1501";
  attribute SOFT_HLUTNM of \quad[8]_i_1__1\ : label is "soft_lutpair1519";
  attribute SOFT_HLUTNM of \quad[9]_i_1__0\ : label is "soft_lutpair1515";
  attribute SOFT_HLUTNM of \retbuf[0][0]_i_12\ : label is "soft_lutpair1527";
  attribute SOFT_HLUTNM of \retbuf[5][0]_i_6\ : label is "soft_lutpair1561";
  attribute SOFT_HLUTNM of \retbuf[5][1]_i_6\ : label is "soft_lutpair1561";
  attribute SOFT_HLUTNM of \retbuf[6][1]_i_6\ : label is "soft_lutpair1564";
  attribute SOFT_HLUTNM of \retbuf[6][2]_i_6\ : label is "soft_lutpair1564";
  attribute SOFT_HLUTNM of \retbuf[6][3]_i_6\ : label is "soft_lutpair1563";
  attribute SOFT_HLUTNM of \retbuf[6][4]_i_6\ : label is "soft_lutpair1563";
  attribute SOFT_HLUTNM of \retbuf[6][5]_i_7\ : label is "soft_lutpair1562";
  attribute SOFT_HLUTNM of \retbuf[6][6]_i_6\ : label is "soft_lutpair1528";
  attribute SOFT_HLUTNM of \retbuf[6][7]_i_10\ : label is "soft_lutpair1562";
  attribute SOFT_HLUTNM of \stateOp[0]_i_1__12\ : label is "soft_lutpair1493";
  attribute SOFT_HLUTNM of \stateOp[2]_i_4__3\ : label is "soft_lutpair1543";
  attribute SOFT_HLUTNM of \stateSeqbufB[0]_i_1__2\ : label is "soft_lutpair1530";
  attribute SOFT_HLUTNM of \stateSeqbufB[1]_i_1__2\ : label is "soft_lutpair1531";
  attribute SOFT_HLUTNM of \stateSeqbufB[2]_i_7__2\ : label is "soft_lutpair1486";
  attribute SOFT_HLUTNM of \stop_lcl_i_2__1\ : label is "soft_lutpair1525";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of \strbStop5_inferred__0/i__carry\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \strbStop5_inferred__0/i__carry__0\ : label is 11;
  attribute SOFT_HLUTNM of \strbStop_i_2__2\ : label is "soft_lutpair1493";
  attribute SOFT_HLUTNM of \strbStop_i_3__1\ : label is "soft_lutpair1527";
  attribute SOFT_HLUTNM of \txAXIS_tdata[15]_i_19\ : label is "soft_lutpair1524";
  attribute SOFT_HLUTNM of \wordcntLast[28]_i_14\ : label is "soft_lutpair1531";
begin
  \FSM_onehot_stateSeq_reg[3]_0\(0) <= \^fsm_onehot_stateseq_reg[3]_0\(0);
  Q(31 downto 0) <= \^q\(31 downto 0);
  ackInvCputrackSelect <= \^ackinvcputrackselect\;
  ackInvCputrackSet <= \^ackinvcputrackset\;
  cputrackGetInfoTixVState(1 downto 0) <= \^cputrackgetinfotixvstate\(1 downto 0);
\FSM_onehot_stateSeq[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF00010001"
    )
        port map (
      I0 => TCapt,
      I1 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I2 => first,
      I3 => rdySeq,
      I4 => \FSM_onehot_stateSeq[5]_i_8__0_n_0\,
      I5 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \FSM_onehot_stateSeq[0]_i_1__2_n_0\
    );
\FSM_onehot_stateSeq[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF8FF00"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \FSM_onehot_stateSeq[3]_i_2__1_n_0\,
      I3 => rdySeq,
      I4 => TCapt,
      O => \FSM_onehot_stateSeq[2]_i_1__2_n_0\
    );
\FSM_onehot_stateSeq[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \FSM_onehot_stateSeq[3]_i_2__1_n_0\,
      I3 => TCapt,
      O => \FSM_onehot_stateSeq[3]_i_1__2_n_0\
    );
\FSM_onehot_stateSeq[3]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FEFF"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \FSM_onehot_stateSeq[3]_i_3__1_n_0\,
      I3 => \FSM_onehot_stateSeq[5]_i_5__2_n_0\,
      I4 => strbStop_reg_n_0,
      I5 => stop_lcl_reg_n_0,
      O => \FSM_onehot_stateSeq[3]_i_2__1_n_0\
    );
\FSM_onehot_stateSeq[3]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => stoTixVTrigger(3),
      I1 => stoTixVTrigger(1),
      I2 => stoTixVTrigger(4),
      I3 => stoTixVTrigger(7),
      I4 => \FSM_onehot_stateSeq[3]_i_4__1_n_0\,
      O => \FSM_onehot_stateSeq[3]_i_3__1_n_0\
    );
\FSM_onehot_stateSeq[3]_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => stoTixVTrigger(0),
      I1 => stoTixVTrigger(2),
      I2 => stoTixVTrigger(6),
      I3 => stoTixVTrigger(5),
      O => \FSM_onehot_stateSeq[3]_i_4__1_n_0\
    );
\FSM_onehot_stateSeq[5]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55C0550055F35500"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_3__1_n_0\,
      I1 => \FSM_onehot_stateSeq[5]_i_4__2_n_0\,
      I2 => \FSM_onehot_stateSeq[5]_i_5__2_n_0\,
      I3 => \FSM_onehot_stateSeq[5]_i_6__2_n_0\,
      I4 => \FSM_onehot_stateSeq[5]_i_7__2_n_0\,
      I5 => \FSM_onehot_stateSeq[5]_i_8__0_n_0\,
      O => \FSM_onehot_stateSeq[5]_i_1__2_n_0\
    );
\FSM_onehot_stateSeq[5]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => stateSeqbufB_reg(2),
      I2 => stateSeqbufB_reg(0),
      I3 => stateSeqbufB_reg(1),
      O => \FSM_onehot_stateSeq[5]_i_2__2_n_0\
    );
\FSM_onehot_stateSeq[5]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CF55FF15"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_8__0_n_0\,
      I1 => stateOp(2),
      I2 => stateOp(1),
      I3 => \FSM_onehot_stateSeq[5]_i_7__2_n_0\,
      I4 => stateOp(0),
      I5 => \FSM_onehot_stateSeq[5]_i_9_n_0\,
      O => \FSM_onehot_stateSeq[5]_i_3__1_n_0\
    );
\FSM_onehot_stateSeq[5]_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ackSeqbufBToSeqClear,
      I1 => rdySeq,
      O => \FSM_onehot_stateSeq[5]_i_4__2_n_0\
    );
\FSM_onehot_stateSeq[5]_i_5__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[6]\,
      I1 => \aSeqbuf[8]_i_2__2_n_0\,
      I2 => \aSeqbuf_reg_n_0_[9]\,
      I3 => \aSeqbuf_reg_n_0_[7]\,
      I4 => \aSeqbuf_reg_n_0_[8]\,
      O => \FSM_onehot_stateSeq[5]_i_5__2_n_0\
    );
\FSM_onehot_stateSeq[5]_i_6__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ackSeqbufBToSeqClear,
      I1 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \FSM_onehot_stateSeq[5]_i_6__2_n_0\
    );
\FSM_onehot_stateSeq[5]_i_7__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I1 => TCapt,
      O => \FSM_onehot_stateSeq[5]_i_7__2_n_0\
    );
\FSM_onehot_stateSeq[5]_i_8__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => stateSeqbufB_reg(1),
      I1 => stateSeqbufB_reg(0),
      I2 => stateSeqbufB_reg(2),
      O => \FSM_onehot_stateSeq[5]_i_8__0_n_0\
    );
\FSM_onehot_stateSeq[5]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => rdySeq,
      I1 => ackSeqbufBToSeqClear,
      I2 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      O => \FSM_onehot_stateSeq[5]_i_9_n_0\
    );
\FSM_onehot_stateSeq_reg[0]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1__2_n_0\,
      D => \FSM_onehot_stateSeq[0]_i_1__2_n_0\,
      PRE => AR(0),
      Q => first
    );
\FSM_onehot_stateSeq_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1__2_n_0\,
      CLR => AR(0),
      D => first,
      Q => rdySeq
    );
\FSM_onehot_stateSeq_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1__2_n_0\,
      CLR => AR(0),
      D => \FSM_onehot_stateSeq[2]_i_1__2_n_0\,
      Q => TCapt
    );
\FSM_onehot_stateSeq_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1__2_n_0\,
      CLR => AR(0),
      D => \FSM_onehot_stateSeq[3]_i_1__2_n_0\,
      Q => \^fsm_onehot_stateseq_reg[3]_0\(0)
    );
\FSM_onehot_stateSeq_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1__2_n_0\,
      CLR => AR(0),
      D => \^fsm_onehot_stateseq_reg[3]_0\(0),
      Q => \FSM_onehot_stateSeq_reg_n_0_[4]\
    );
\FSM_onehot_stateSeq_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1__2_n_0\,
      CLR => AR(0),
      D => \FSM_onehot_stateSeq[5]_i_2__2_n_0\,
      Q => ackSeqbufBToSeqClear
    );
\TCaptMax[31]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FB00"
    )
        port map (
      I0 => stateOp(1),
      I1 => stateOp(0),
      I2 => stateOp(2),
      I3 => reqInvCputrackSet,
      I4 => reqInvSelect,
      O => TCaptMax
    );
\TCaptMax_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => \TCaptMax_reg[7]_0\(0),
      Q => \TCaptMax_reg_n_0_[0]\
    );
\TCaptMax_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(2),
      Q => \TCaptMax_reg_n_0_[10]\
    );
\TCaptMax_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(3),
      Q => \TCaptMax_reg_n_0_[11]\
    );
\TCaptMax_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(4),
      Q => \TCaptMax_reg_n_0_[12]\
    );
\TCaptMax_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(5),
      Q => \TCaptMax_reg_n_0_[13]\
    );
\TCaptMax_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(6),
      Q => \TCaptMax_reg_n_0_[14]\
    );
\TCaptMax_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(7),
      Q => \TCaptMax_reg_n_0_[15]\
    );
\TCaptMax_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(8),
      Q => \TCaptMax_reg_n_0_[16]\
    );
\TCaptMax_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(9),
      Q => \TCaptMax_reg_n_0_[17]\
    );
\TCaptMax_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(10),
      Q => \TCaptMax_reg_n_0_[18]\
    );
\TCaptMax_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(11),
      Q => \TCaptMax_reg_n_0_[19]\
    );
\TCaptMax_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => \TCaptMax_reg[7]_0\(1),
      Q => \TCaptMax_reg_n_0_[1]\
    );
\TCaptMax_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(12),
      Q => \TCaptMax_reg_n_0_[20]\
    );
\TCaptMax_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(13),
      Q => \TCaptMax_reg_n_0_[21]\
    );
\TCaptMax_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(14),
      Q => \TCaptMax_reg_n_0_[22]\
    );
\TCaptMax_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(15),
      Q => \TCaptMax_reg_n_0_[23]\
    );
\TCaptMax_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(16),
      Q => \TCaptMax_reg_n_0_[24]\
    );
\TCaptMax_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(17),
      Q => \TCaptMax_reg_n_0_[25]\
    );
\TCaptMax_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(18),
      Q => \TCaptMax_reg_n_0_[26]\
    );
\TCaptMax_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(19),
      Q => \TCaptMax_reg_n_0_[27]\
    );
\TCaptMax_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(20),
      Q => \TCaptMax_reg_n_0_[28]\
    );
\TCaptMax_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(21),
      Q => \TCaptMax_reg_n_0_[29]\
    );
\TCaptMax_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => \TCaptMax_reg[7]_0\(2),
      Q => \TCaptMax_reg_n_0_[2]\
    );
\TCaptMax_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(22),
      Q => \TCaptMax_reg_n_0_[30]\
    );
\TCaptMax_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(23),
      Q => \TCaptMax_reg_n_0_[31]\
    );
\TCaptMax_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => \TCaptMax_reg[7]_0\(3),
      Q => \TCaptMax_reg_n_0_[3]\
    );
\TCaptMax_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => \TCaptMax_reg[7]_0\(4),
      Q => \TCaptMax_reg_n_0_[4]\
    );
\TCaptMax_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => \TCaptMax_reg[7]_0\(5),
      Q => \TCaptMax_reg_n_0_[5]\
    );
\TCaptMax_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => \TCaptMax_reg[7]_0\(6),
      Q => \TCaptMax_reg_n_0_[6]\
    );
\TCaptMax_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => \TCaptMax_reg[7]_0\(7),
      Q => \TCaptMax_reg_n_0_[7]\
    );
\TCaptMax_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(0),
      Q => \TCaptMax_reg_n_0_[8]\
    );
\TCaptMax_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => D(1),
      Q => \TCaptMax_reg_n_0_[9]\
    );
\TCapt[0]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      I1 => first,
      O => \TCapt__0\(0)
    );
\TCapt[10]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(10),
      I1 => first,
      O => \TCapt__0\(10)
    );
\TCapt[11]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(11),
      I1 => first,
      O => \TCapt__0\(11)
    );
\TCapt[12]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(12),
      I1 => first,
      O => \TCapt__0\(12)
    );
\TCapt[13]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(13),
      I1 => first,
      O => \TCapt__0\(13)
    );
\TCapt[14]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(14),
      I1 => first,
      O => \TCapt__0\(14)
    );
\TCapt[15]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(15),
      I1 => first,
      O => \TCapt__0\(15)
    );
\TCapt[16]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(16),
      I1 => first,
      O => \TCapt__0\(16)
    );
\TCapt[17]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(17),
      I1 => first,
      O => \TCapt__0\(17)
    );
\TCapt[18]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(18),
      I1 => first,
      O => \TCapt__0\(18)
    );
\TCapt[19]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(19),
      I1 => first,
      O => \TCapt__0\(19)
    );
\TCapt[1]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(1),
      I1 => first,
      O => \TCapt__0\(1)
    );
\TCapt[20]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(20),
      I1 => first,
      O => \TCapt__0\(20)
    );
\TCapt[21]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(21),
      I1 => first,
      O => \TCapt__0\(21)
    );
\TCapt[22]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(22),
      I1 => first,
      O => \TCapt__0\(22)
    );
\TCapt[23]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(23),
      I1 => first,
      O => \TCapt__0\(23)
    );
\TCapt[24]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(24),
      I1 => first,
      O => \TCapt__0\(24)
    );
\TCapt[25]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(25),
      I1 => first,
      O => \TCapt__0\(25)
    );
\TCapt[26]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(26),
      I1 => first,
      O => \TCapt__0\(26)
    );
\TCapt[27]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(27),
      I1 => first,
      O => \TCapt__0\(27)
    );
\TCapt[28]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(28),
      I1 => first,
      O => \TCapt__0\(28)
    );
\TCapt[29]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(29),
      I1 => first,
      O => \TCapt__0\(29)
    );
\TCapt[2]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(2),
      I1 => first,
      O => \TCapt__0\(2)
    );
\TCapt[30]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(30),
      I1 => first,
      O => \TCapt__0\(30)
    );
\TCapt[31]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(31),
      I1 => first,
      O => \TCapt__0\(31)
    );
\TCapt[3]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(3),
      I1 => first,
      O => \TCapt__0\(3)
    );
\TCapt[4]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(4),
      I1 => first,
      O => \TCapt__0\(4)
    );
\TCapt[5]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(5),
      I1 => first,
      O => \TCapt__0\(5)
    );
\TCapt[6]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(6),
      I1 => first,
      O => \TCapt__0\(6)
    );
\TCapt[7]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(7),
      I1 => first,
      O => \TCapt__0\(7)
    );
\TCapt[8]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(8),
      I1 => first,
      O => \TCapt__0\(8)
    );
\TCapt[9]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(9),
      I1 => first,
      O => \TCapt__0\(9)
    );
\TCapt_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(0),
      Q => \^q\(0)
    );
\TCapt_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(10),
      Q => \^q\(10)
    );
\TCapt_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(11),
      Q => \^q\(11)
    );
\TCapt_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(12),
      Q => \^q\(12)
    );
\TCapt_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(13),
      Q => \^q\(13)
    );
\TCapt_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(14),
      Q => \^q\(14)
    );
\TCapt_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(15),
      Q => \^q\(15)
    );
\TCapt_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(16),
      Q => \^q\(16)
    );
\TCapt_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(17),
      Q => \^q\(17)
    );
\TCapt_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(18),
      Q => \^q\(18)
    );
\TCapt_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(19),
      Q => \^q\(19)
    );
\TCapt_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(1),
      Q => \^q\(1)
    );
\TCapt_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(20),
      Q => \^q\(20)
    );
\TCapt_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(21),
      Q => \^q\(21)
    );
\TCapt_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(22),
      Q => \^q\(22)
    );
\TCapt_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(23),
      Q => \^q\(23)
    );
\TCapt_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(24),
      Q => \^q\(24)
    );
\TCapt_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(25),
      Q => \^q\(25)
    );
\TCapt_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(26),
      Q => \^q\(26)
    );
\TCapt_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(27),
      Q => \^q\(27)
    );
\TCapt_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(28),
      Q => \^q\(28)
    );
\TCapt_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(29),
      Q => \^q\(29)
    );
\TCapt_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(2),
      Q => \^q\(2)
    );
\TCapt_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(30),
      Q => \^q\(30)
    );
\TCapt_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(31),
      Q => \^q\(31)
    );
\TCapt_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(3),
      Q => \^q\(3)
    );
\TCapt_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(4),
      Q => \^q\(4)
    );
\TCapt_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(5),
      Q => \^q\(5)
    );
\TCapt_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(6),
      Q => \^q\(6)
    );
\TCapt_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(7),
      Q => \^q\(7)
    );
\TCapt_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(8),
      Q => \^q\(8)
    );
\TCapt_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(9),
      Q => \^q\(9)
    );
\aSeqbufB[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[0]\,
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      O => \aSeqbufB[0]_i_1__2_n_0\
    );
\aSeqbufB[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6660"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[1]\,
      I1 => \aSeqbufB_reg_n_0_[0]\,
      I2 => stateSeqbufB_reg(1),
      I3 => stateSeqbufB_reg(0),
      O => \aSeqbufB[1]_i_1__2_n_0\
    );
\aSeqbufB[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78787800"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[0]\,
      I1 => \aSeqbufB_reg_n_0_[1]\,
      I2 => \aSeqbufB_reg_n_0_[2]\,
      I3 => stateSeqbufB_reg(1),
      I4 => stateSeqbufB_reg(0),
      O => \aSeqbufB[2]_i_1__2_n_0\
    );
\aSeqbufB[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[2]\,
      I1 => \aSeqbufB_reg_n_0_[1]\,
      I2 => \aSeqbufB_reg_n_0_[0]\,
      I3 => \aSeqbufB_reg_n_0_[3]\,
      I4 => \aSeqbufB[8]_i_3__2_n_0\,
      O => \aSeqbufB[3]_i_1__2_n_0\
    );
\aSeqbufB[4]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => \aSeqbufB[8]_i_3__2_n_0\,
      I1 => \aSeqbufB_reg_n_0_[3]\,
      I2 => \aSeqbufB_reg_n_0_[0]\,
      I3 => \aSeqbufB_reg_n_0_[1]\,
      I4 => \aSeqbufB_reg_n_0_[2]\,
      I5 => \aSeqbufB_reg_n_0_[4]\,
      O => \aSeqbufB[4]_i_1__2_n_0\
    );
\aSeqbufB[5]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0EE0"
    )
        port map (
      I0 => stateSeqbufB_reg(1),
      I1 => stateSeqbufB_reg(0),
      I2 => \aSeqbufB[5]_i_2__2_n_0\,
      I3 => \aSeqbufB_reg_n_0_[5]\,
      O => \aSeqbufB[5]_i_1__2_n_0\
    );
\aSeqbufB[5]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[4]\,
      I1 => \aSeqbufB_reg_n_0_[2]\,
      I2 => \aSeqbufB_reg_n_0_[1]\,
      I3 => \aSeqbufB_reg_n_0_[0]\,
      I4 => \aSeqbufB_reg_n_0_[3]\,
      O => \aSeqbufB[5]_i_2__2_n_0\
    );
\aSeqbufB[6]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0EE0"
    )
        port map (
      I0 => stateSeqbufB_reg(1),
      I1 => stateSeqbufB_reg(0),
      I2 => \aSeqbufB[8]_i_4__2_n_0\,
      I3 => \aSeqbufB_reg_n_0_[6]\,
      O => \aSeqbufB[6]_i_1__2_n_0\
    );
\aSeqbufB[7]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0EEEE000"
    )
        port map (
      I0 => stateSeqbufB_reg(1),
      I1 => stateSeqbufB_reg(0),
      I2 => \aSeqbufB[8]_i_4__2_n_0\,
      I3 => \aSeqbufB_reg_n_0_[6]\,
      I4 => \aSeqbufB_reg_n_0_[7]\,
      O => \aSeqbufB[7]_i_1__2_n_0\
    );
\aSeqbufB[8]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4101"
    )
        port map (
      I0 => stateSeqbufB_reg(2),
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      I3 => \stateSeqbufB[1]_i_2__2_n_0\,
      O => \aSeqbufB[8]_i_1__2_n_0\
    );
\aSeqbufB[8]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15554000"
    )
        port map (
      I0 => \aSeqbufB[8]_i_3__2_n_0\,
      I1 => \aSeqbufB_reg_n_0_[6]\,
      I2 => \aSeqbufB[8]_i_4__2_n_0\,
      I3 => \aSeqbufB_reg_n_0_[7]\,
      I4 => \aSeqbufB_reg_n_0_[8]\,
      O => \aSeqbufB[8]_i_2__2_n_0\
    );
\aSeqbufB[8]_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => stateSeqbufB_reg(0),
      I1 => stateSeqbufB_reg(2),
      I2 => stateSeqbufB_reg(1),
      O => \aSeqbufB[8]_i_3__2_n_0\
    );
\aSeqbufB[8]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[3]\,
      I1 => \aSeqbufB_reg_n_0_[0]\,
      I2 => \aSeqbufB_reg_n_0_[1]\,
      I3 => \aSeqbufB_reg_n_0_[2]\,
      I4 => \aSeqbufB_reg_n_0_[4]\,
      I5 => \aSeqbufB_reg_n_0_[5]\,
      O => \aSeqbufB[8]_i_4__2_n_0\
    );
\aSeqbufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbufB[0]_i_1__2_n_0\,
      Q => \aSeqbufB_reg_n_0_[0]\
    );
\aSeqbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbufB[1]_i_1__2_n_0\,
      Q => \aSeqbufB_reg_n_0_[1]\
    );
\aSeqbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbufB[2]_i_1__2_n_0\,
      Q => \aSeqbufB_reg_n_0_[2]\
    );
\aSeqbufB_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbufB[3]_i_1__2_n_0\,
      Q => \aSeqbufB_reg_n_0_[3]\
    );
\aSeqbufB_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbufB[4]_i_1__2_n_0\,
      Q => \aSeqbufB_reg_n_0_[4]\
    );
\aSeqbufB_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbufB[5]_i_1__2_n_0\,
      Q => \aSeqbufB_reg_n_0_[5]\
    );
\aSeqbufB_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbufB[6]_i_1__2_n_0\,
      Q => \aSeqbufB_reg_n_0_[6]\
    );
\aSeqbufB_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbufB[7]_i_1__2_n_0\,
      Q => \aSeqbufB_reg_n_0_[7]\
    );
\aSeqbufB_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbufB[8]_i_2__2_n_0\,
      Q => \aSeqbufB_reg_n_0_[8]\
    );
\aSeqbuf[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555550515150"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[0]\,
      I1 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I2 => ackSeqbufBToSeqClear,
      I3 => rdySeq,
      I4 => TCapt,
      I5 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \aSeqbuf[0]_i_1__2_n_0\
    );
\aSeqbuf[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[1]\,
      I1 => \aSeqbuf_reg_n_0_[0]\,
      I2 => \aSeqbuf[9]_i_6__2_n_0\,
      O => \aSeqbuf[1]_i_1__2_n_0\
    );
\aSeqbuf[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[0]\,
      I1 => \aSeqbuf_reg_n_0_[1]\,
      I2 => \aSeqbuf_reg_n_0_[2]\,
      I3 => \aSeqbuf[9]_i_6__2_n_0\,
      O => \aSeqbuf[2]_i_1__2_n_0\
    );
\aSeqbuf[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[2]\,
      I1 => \aSeqbuf_reg_n_0_[1]\,
      I2 => \aSeqbuf_reg_n_0_[0]\,
      I3 => \aSeqbuf_reg_n_0_[3]\,
      I4 => \aSeqbuf[9]_i_6__2_n_0\,
      O => \aSeqbuf[3]_i_1__2_n_0\
    );
\aSeqbuf[4]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[3]\,
      I1 => \aSeqbuf_reg_n_0_[0]\,
      I2 => \aSeqbuf_reg_n_0_[1]\,
      I3 => \aSeqbuf_reg_n_0_[2]\,
      I4 => \aSeqbuf_reg_n_0_[4]\,
      I5 => \aSeqbuf[9]_i_6__2_n_0\,
      O => \aSeqbuf[4]_i_1__2_n_0\
    );
\aSeqbuf[5]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \aSeqbuf[6]_i_2_n_0\,
      I1 => \aSeqbuf_reg_n_0_[3]\,
      I2 => \aSeqbuf_reg_n_0_[4]\,
      I3 => \aSeqbuf_reg_n_0_[5]\,
      I4 => \aSeqbuf[9]_i_6__2_n_0\,
      O => \aSeqbuf[5]_i_1__2_n_0\
    );
\aSeqbuf[6]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \aSeqbuf[7]_i_2_n_0\,
      I1 => \aSeqbuf[6]_i_2_n_0\,
      I2 => \aSeqbuf_reg_n_0_[3]\,
      I3 => \aSeqbuf_reg_n_0_[5]\,
      I4 => \aSeqbuf_reg_n_0_[4]\,
      I5 => \aSeqbuf_reg_n_0_[6]\,
      O => \aSeqbuf[6]_i_1__2_n_0\
    );
\aSeqbuf[6]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[2]\,
      I1 => \aSeqbuf_reg_n_0_[1]\,
      I2 => \aSeqbuf_reg_n_0_[0]\,
      O => \aSeqbuf[6]_i_2_n_0\
    );
\aSeqbuf[7]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \aSeqbuf[7]_i_2_n_0\,
      I1 => \aSeqbuf[8]_i_2__2_n_0\,
      I2 => \aSeqbuf_reg_n_0_[6]\,
      I3 => \aSeqbuf_reg_n_0_[7]\,
      O => \aSeqbuf[7]_i_1__2_n_0\
    );
\aSeqbuf[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007F55FFFF"
    )
        port map (
      I0 => \aSeqbuf[8]_i_5__0_n_0\,
      I1 => \aSeqbuf_reg_n_0_[7]\,
      I2 => \aSeqbuf_reg_n_0_[6]\,
      I3 => \aSeqbuf_reg_n_0_[8]\,
      I4 => \aSeqbuf[7]_i_3_n_0\,
      I5 => \aSeqbuf[9]_i_6__2_n_0\,
      O => \aSeqbuf[7]_i_2_n_0\
    );
\aSeqbuf[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11111101"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => ackSeqbufBToSeqClear,
      I2 => rdySeq,
      I3 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I4 => TCapt,
      O => \aSeqbuf[7]_i_3_n_0\
    );
\aSeqbuf[8]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00006CCC"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[7]\,
      I1 => \aSeqbuf_reg_n_0_[8]\,
      I2 => \aSeqbuf[8]_i_2__2_n_0\,
      I3 => \aSeqbuf_reg_n_0_[6]\,
      I4 => \aSeqbuf[8]_i_3__1_n_0\,
      I5 => \aSeqbuf[8]_i_4__1_n_0\,
      O => \aSeqbuf[8]_i_1__2_n_0\
    );
\aSeqbuf[8]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[2]\,
      I1 => \aSeqbuf_reg_n_0_[1]\,
      I2 => \aSeqbuf_reg_n_0_[0]\,
      I3 => \aSeqbuf_reg_n_0_[3]\,
      I4 => \aSeqbuf_reg_n_0_[5]\,
      I5 => \aSeqbuf_reg_n_0_[4]\,
      O => \aSeqbuf[8]_i_2__2_n_0\
    );
\aSeqbuf[8]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0033003200330003"
    )
        port map (
      I0 => \aSeqbuf[8]_i_5__0_n_0\,
      I1 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I2 => rdySeq,
      I3 => ackSeqbufBToSeqClear,
      I4 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I5 => TCapt,
      O => \aSeqbuf[8]_i_3__1_n_0\
    );
\aSeqbuf[8]_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4__2_n_0\,
      I1 => \aSeqbuf_reg_n_0_[8]\,
      I2 => \aSeqbuf_reg_n_0_[7]\,
      I3 => \aSeqbuf_reg_n_0_[9]\,
      I4 => \aSeqbuf_reg_n_0_[6]\,
      O => \aSeqbuf[8]_i_4__1_n_0\
    );
\aSeqbuf[8]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08000000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[3]\,
      I1 => \aSeqbuf[6]_i_2_n_0\,
      I2 => \aSeqbuf[8]_i_6_n_0\,
      I3 => \aSeqbuf_reg_n_0_[4]\,
      I4 => \aSeqbuf_reg_n_0_[5]\,
      O => \aSeqbuf[8]_i_5__0_n_0\
    );
\aSeqbuf[8]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[8]\,
      I1 => \aSeqbuf_reg_n_0_[7]\,
      I2 => \aSeqbuf_reg_n_0_[9]\,
      O => \aSeqbuf[8]_i_6_n_0\
    );
\aSeqbuf[9]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \aSeqbuf[7]_i_3_n_0\,
      I1 => \aSeqbuf_reg_n_0_[8]\,
      I2 => \aSeqbuf_reg_n_0_[7]\,
      I3 => \aSeqbuf_reg_n_0_[1]\,
      I4 => \aSeqbuf_reg_n_0_[4]\,
      I5 => \aSeqbuf_reg_n_0_[5]\,
      O => \aSeqbuf[9]_i_10_n_0\
    );
\aSeqbuf[9]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFAE"
    )
        port map (
      I0 => \aSeqbuf[9]_i_3__2_n_0\,
      I1 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I2 => \FSM_onehot_stateSeq[5]_i_5__2_n_0\,
      I3 => \aSeqbuf[9]_i_4__1_n_0\,
      O => \aSeqbuf[9]_i_1__2_n_0\
    );
\aSeqbuf[9]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0130110011001100"
    )
        port map (
      I0 => \aSeqbuf[9]_i_5__2_n_0\,
      I1 => \aSeqbuf[9]_i_6__2_n_0\,
      I2 => \aSeqbuf[9]_i_7__1_n_0\,
      I3 => \aSeqbuf_reg_n_0_[9]\,
      I4 => \aSeqbuf_reg_n_0_[7]\,
      I5 => \aSeqbuf_reg_n_0_[8]\,
      O => \aSeqbuf[9]_i_2__2_n_0\
    );
\aSeqbuf[9]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"008000800080AAAA"
    )
        port map (
      I0 => \quad[23]_i_3_n_0\,
      I1 => \burstCnt[3]_i_2_n_0\,
      I2 => \burstCnt[15]_i_3__1_n_0\,
      I3 => \first__0\,
      I4 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I5 => TCapt,
      O => \aSeqbuf[9]_i_3__2_n_0\
    );
\aSeqbuf[9]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0300020003000000"
    )
        port map (
      I0 => rdySeq,
      I1 => ackSeqbufBToSeqClear,
      I2 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I3 => \aSeqbuf[9]_i_8_n_0\,
      I4 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I5 => TCapt,
      O => \aSeqbuf[9]_i_4__1_n_0\
    );
\aSeqbuf[9]_i_5__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000008F0000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[7]\,
      I1 => \aSeqbuf_reg_n_0_[6]\,
      I2 => \aSeqbuf_reg_n_0_[8]\,
      I3 => \aSeqbuf[9]_i_9_n_0\,
      I4 => \aSeqbuf[6]_i_2_n_0\,
      I5 => \aSeqbuf[9]_i_10_n_0\,
      O => \aSeqbuf[9]_i_5__2_n_0\
    );
\aSeqbuf[9]_i_6__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00550041"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => TCapt,
      I2 => rdySeq,
      I3 => ackSeqbufBToSeqClear,
      I4 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      O => \aSeqbuf[9]_i_6__2_n_0\
    );
\aSeqbuf[9]_i_7__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[4]\,
      I1 => \aSeqbuf_reg_n_0_[5]\,
      I2 => \aSeqbuf_reg_n_0_[3]\,
      I3 => \aSeqbuf[6]_i_2_n_0\,
      I4 => \aSeqbuf_reg_n_0_[6]\,
      O => \aSeqbuf[9]_i_7__1_n_0\
    );
\aSeqbuf[9]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08080808FF080808"
    )
        port map (
      I0 => stateOp(1),
      I1 => stateOp(2),
      I2 => stateOp(0),
      I3 => stateSeqbufB_reg(2),
      I4 => stateSeqbufB_reg(0),
      I5 => stateSeqbufB_reg(1),
      O => \aSeqbuf[9]_i_8_n_0\
    );
\aSeqbuf[9]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[5]\,
      I1 => \aSeqbuf_reg_n_0_[3]\,
      I2 => \aSeqbuf_reg_n_0_[4]\,
      O => \aSeqbuf[9]_i_9_n_0\
    );
\aSeqbuf_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[0]_i_1__2_n_0\,
      Q => \aSeqbuf_reg_n_0_[0]\
    );
\aSeqbuf_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[1]_i_1__2_n_0\,
      Q => \aSeqbuf_reg_n_0_[1]\
    );
\aSeqbuf_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[2]_i_1__2_n_0\,
      Q => \aSeqbuf_reg_n_0_[2]\
    );
\aSeqbuf_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[3]_i_1__2_n_0\,
      Q => \aSeqbuf_reg_n_0_[3]\
    );
\aSeqbuf_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[4]_i_1__2_n_0\,
      Q => \aSeqbuf_reg_n_0_[4]\
    );
\aSeqbuf_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[5]_i_1__2_n_0\,
      Q => \aSeqbuf_reg_n_0_[5]\
    );
\aSeqbuf_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[6]_i_1__2_n_0\,
      Q => \aSeqbuf_reg_n_0_[6]\
    );
\aSeqbuf_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[7]_i_1__2_n_0\,
      Q => \aSeqbuf_reg_n_0_[7]\
    );
\aSeqbuf_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[8]_i_1__2_n_0\,
      Q => \aSeqbuf_reg_n_0_[8]\
    );
\aSeqbuf_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__2_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[9]_i_2__2_n_0\,
      Q => \aSeqbuf_reg_n_0_[9]\
    );
\ackInvSelect_sig_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF3AAAAA2A2"
    )
        port map (
      I0 => reqInvSelect,
      I1 => stateOp(0),
      I2 => stateOp(2),
      I3 => ackInvSelect_sig_reg_0,
      I4 => stateOp(1),
      I5 => \^ackinvcputrackselect\,
      O => \ackInvSelect_sig_i_1__2_n_0\
    );
ackInvSelect_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \ackInvSelect_sig_i_1__2_n_0\,
      Q => \^ackinvcputrackselect\
    );
\ackInvSet_sig_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFAAAFAAAFAAA200"
    )
        port map (
      I0 => \^ackinvcputrackset\,
      I1 => \^ackinvcputrackselect\,
      I2 => reqInvSelect,
      I3 => reqInvCputrackSet,
      I4 => \ackInvSet_sig_i_2__4_n_0\,
      I5 => stateOp(1),
      O => \ackInvSet_sig_i_1__7_n_0\
    );
\ackInvSet_sig_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(0),
      O => \ackInvSet_sig_i_2__4_n_0\
    );
ackInvSet_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \ackInvSet_sig_i_1__7_n_0\,
      Q => \^ackinvcputrackset\
    );
\burstCnt[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0D00"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[0]\,
      I1 => \burstCnt[15]_i_5__2_n_0\,
      I2 => first,
      I3 => \burstCnt[15]_i_4__2_n_0\,
      O => \burstCnt[0]_i_1__2_n_0\
    );
\burstCnt[10]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[10]_i_2__1_n_0\,
      O => \burstCnt[10]_i_1__2_n_0\
    );
\burstCnt[10]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF75"
    )
        port map (
      I0 => \burstCnt[15]_i_4__2_n_0\,
      I1 => \burstCnt[15]_i_5__2_n_0\,
      I2 => \burstCnt_reg_n_0_[10]\,
      I3 => \burstCnt[9]_i_2__2_n_0\,
      O => \burstCnt[10]_i_2__1_n_0\
    );
\burstCnt[11]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[11]_i_2__2_n_0\,
      O => \burstCnt[11]_i_1__2_n_0\
    );
\burstCnt[11]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF5DFFF7"
    )
        port map (
      I0 => \burstCnt[15]_i_4__2_n_0\,
      I1 => \burstCnt_reg_n_0_[10]\,
      I2 => \burstCnt[9]_i_2__2_n_0\,
      I3 => \burstCnt[15]_i_5__2_n_0\,
      I4 => \burstCnt_reg_n_0_[11]\,
      O => \burstCnt[11]_i_2__2_n_0\
    );
\burstCnt[12]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[12]_i_2__1_n_0\,
      O => \burstCnt[12]_i_1__2_n_0\
    );
\burstCnt[12]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7F7F7F7FDF7F7F7"
    )
        port map (
      I0 => \burstCnt[15]_i_4__2_n_0\,
      I1 => \burstCnt_reg_n_0_[12]\,
      I2 => \burstCnt[15]_i_5__2_n_0\,
      I3 => \burstCnt_reg_n_0_[11]\,
      I4 => \burstCnt_reg_n_0_[10]\,
      I5 => \burstCnt[9]_i_2__2_n_0\,
      O => \burstCnt[12]_i_2__1_n_0\
    );
\burstCnt[13]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[13]_i_2__0_n_0\,
      O => \burstCnt[13]_i_1__2_n_0\
    );
\burstCnt[13]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFD5FF7F"
    )
        port map (
      I0 => \burstCnt[15]_i_4__2_n_0\,
      I1 => \burstCnt_reg_n_0_[12]\,
      I2 => \burstCnt[13]_i_3_n_0\,
      I3 => \burstCnt[15]_i_5__2_n_0\,
      I4 => \burstCnt_reg_n_0_[13]\,
      O => \burstCnt[13]_i_2__0_n_0\
    );
\burstCnt[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[11]\,
      I1 => \burstCnt[15]_i_5__2_n_0\,
      I2 => \burstCnt_reg_n_0_[10]\,
      I3 => \burstCnt_reg_n_0_[8]\,
      I4 => \burstCnt[13]_i_4_n_0\,
      I5 => \burstCnt_reg_n_0_[9]\,
      O => \burstCnt[13]_i_3_n_0\
    );
\burstCnt[13]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFFFFFFFFFFFFF"
    )
        port map (
      I0 => \burstCnt[9]_i_4_n_0\,
      I1 => \burstCnt[13]_i_5_n_0\,
      I2 => \burstCnt[15]_i_14__0_n_0\,
      I3 => \burstCnt[15]_i_13__1_n_0\,
      I4 => \burstCnt_reg_n_0_[5]\,
      I5 => \burstCnt_reg_n_0_[4]\,
      O => \burstCnt[13]_i_4_n_0\
    );
\burstCnt[13]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[3]\,
      I1 => \burstCnt_reg_n_0_[0]\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \burstCnt_reg_n_0_[2]\,
      O => \burstCnt[13]_i_5_n_0\
    );
\burstCnt[14]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44140000"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[15]_i_6__2_n_0\,
      I2 => \burstCnt_reg_n_0_[14]\,
      I3 => \burstCnt[15]_i_5__2_n_0\,
      I4 => \burstCnt[15]_i_4__2_n_0\,
      O => \burstCnt[14]_i_1__2_n_0\
    );
\burstCnt[15]_i_10__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF12333312"
    )
        port map (
      I0 => \quad_reg_n_0_[7]\,
      I1 => \quad[7]_i_3_n_0\,
      I2 => state(7),
      I3 => \quad_reg_n_0_[0]\,
      I4 => state(0),
      I5 => \burstCnt[15]_i_19__0_n_0\,
      O => \burstCnt[15]_i_10__2_n_0\
    );
\burstCnt[15]_i_11__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABAEAFAFAFAFABAE"
    )
        port map (
      I0 => \burstCnt[15]_i_20__0_n_0\,
      I1 => \quad_reg_n_0_[8]\,
      I2 => \burstCnt[15]_i_15__0_n_0\,
      I3 => state(0),
      I4 => \quad_reg_n_0_[10]\,
      I5 => state(2),
      O => \burstCnt[15]_i_11__2_n_0\
    );
\burstCnt[15]_i_12__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF666F66F6"
    )
        port map (
      I0 => state(5),
      I1 => \dwrSeqbuf[13]_i_2__0_n_0\,
      I2 => \quad_reg_n_0_[1]\,
      I3 => \quad[7]_i_3_n_0\,
      I4 => state(1),
      I5 => \burstCnt[15]_i_21__0_n_0\,
      O => \burstCnt[15]_i_12__2_n_0\
    );
\burstCnt[15]_i_13__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF6FF6"
    )
        port map (
      I0 => state(6),
      I1 => \burstState_reg_n_0_[6]\,
      I2 => state(7),
      I3 => \burstState_reg_n_0_[7]\,
      I4 => \burstCnt[15]_i_22__0_n_0\,
      I5 => \burstCnt[15]_i_23__0_n_0\,
      O => \burstCnt[15]_i_13__1_n_0\
    );
\burstCnt[15]_i_14__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF7FFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[4]\,
      I1 => \burstCnt_reg_n_0_[5]\,
      I2 => \burstCnt_reg_n_0_[9]\,
      I3 => \burstCnt_reg_n_0_[10]\,
      I4 => \burstCnt[15]_i_24__0_n_0\,
      I5 => \burstCnt[15]_i_25__0_n_0\,
      O => \burstCnt[15]_i_14__0_n_0\
    );
\burstCnt[15]_i_15__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \i_reg_n_0_[1]\,
      O => \burstCnt[15]_i_15__0_n_0\
    );
\burstCnt[15]_i_16__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6F0F6F66F6F0F666"
    )
        port map (
      I0 => state(4),
      I1 => \quad_reg_n_0_[20]\,
      I2 => state(5),
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[1]\,
      I5 => \quad_reg_n_0_[5]\,
      O => \burstCnt[15]_i_16__0_n_0\
    );
\burstCnt[15]_i_17__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6F6F660FF6F666F0"
    )
        port map (
      I0 => state(6),
      I1 => \quad_reg_n_0_[6]\,
      I2 => state(5),
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[0]\,
      I5 => \quad_reg_n_0_[21]\,
      O => \burstCnt[15]_i_17__0_n_0\
    );
\burstCnt[15]_i_18__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6F6F660FF6F666F0"
    )
        port map (
      I0 => state(3),
      I1 => \quad_reg_n_0_[3]\,
      I2 => state(7),
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[1]\,
      I5 => \quad_reg_n_0_[15]\,
      O => \burstCnt[15]_i_18__0_n_0\
    );
\burstCnt[15]_i_19__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6F6F660FF6F666F0"
    )
        port map (
      I0 => state(4),
      I1 => \quad_reg_n_0_[4]\,
      I2 => state(0),
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[0]\,
      I5 => \quad_reg_n_0_[16]\,
      O => \burstCnt[15]_i_19__0_n_0\
    );
\burstCnt[15]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000101"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => rdySeq,
      I2 => ackSeqbufBToSeqClear,
      I3 => \burstCnt[15]_i_3__1_n_0\,
      I4 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I5 => TCapt,
      O => \burstCnt[15]_i_1__2_n_0\
    );
\burstCnt[15]_i_20__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6F0F666FF6F066F6"
    )
        port map (
      I0 => state(6),
      I1 => \quad_reg_n_0_[22]\,
      I2 => state(3),
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[1]\,
      I5 => \quad_reg_n_0_[11]\,
      O => \burstCnt[15]_i_20__0_n_0\
    );
\burstCnt[15]_i_21__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6F0F666FF6F066F6"
    )
        port map (
      I0 => state(7),
      I1 => \quad_reg_n_0_[23]\,
      I2 => state(4),
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[1]\,
      I5 => \quad_reg_n_0_[12]\,
      O => \burstCnt[15]_i_21__0_n_0\
    );
\burstCnt[15]_i_22__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \burstState_reg_n_0_[0]\,
      I1 => state(0),
      I2 => state(1),
      I3 => \burstState_reg_n_0_[1]\,
      I4 => state(2),
      I5 => \burstState_reg_n_0_[2]\,
      O => \burstCnt[15]_i_22__0_n_0\
    );
\burstCnt[15]_i_23__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \burstState_reg_n_0_[3]\,
      I1 => state(3),
      I2 => state(4),
      I3 => \burstState_reg_n_0_[4]\,
      I4 => state(5),
      I5 => \burstState_reg_n_0_[5]\,
      O => \burstCnt[15]_i_23__0_n_0\
    );
\burstCnt[15]_i_24__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[7]\,
      I1 => \burstCnt_reg_n_0_[6]\,
      I2 => \burstCnt_reg_n_0_[13]\,
      I3 => \burstCnt_reg_n_0_[12]\,
      O => \burstCnt[15]_i_24__0_n_0\
    );
\burstCnt[15]_i_25__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[15]\,
      I1 => \burstCnt_reg_n_0_[11]\,
      I2 => \burstCnt_reg_n_0_[14]\,
      I3 => \burstCnt_reg_n_0_[8]\,
      O => \burstCnt[15]_i_25__0_n_0\
    );
\burstCnt[15]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000444000004040"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[15]_i_4__2_n_0\,
      I2 => \burstCnt_reg_n_0_[15]\,
      I3 => \burstCnt_reg_n_0_[14]\,
      I4 => \burstCnt[15]_i_5__2_n_0\,
      I5 => \burstCnt[15]_i_6__2_n_0\,
      O => \burstCnt[15]_i_2__2_n_0\
    );
\burstCnt[15]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \i_reg_n_0_[1]\,
      O => \burstCnt[15]_i_3__1_n_0\
    );
\burstCnt[15]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => \burstCnt[15]_i_7__2_n_0\,
      I1 => \burstCnt[15]_i_8__2_n_0\,
      I2 => \burstCnt[15]_i_9__2_n_0\,
      I3 => \burstCnt[15]_i_10__2_n_0\,
      I4 => \burstCnt[15]_i_11__2_n_0\,
      I5 => \burstCnt[15]_i_12__2_n_0\,
      O => \burstCnt[15]_i_4__2_n_0\
    );
\burstCnt[15]_i_5__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \burstCnt[15]_i_13__1_n_0\,
      I1 => \burstCnt[15]_i_14__0_n_0\,
      I2 => \burstCnt_reg_n_0_[3]\,
      I3 => \burstCnt_reg_n_0_[0]\,
      I4 => \burstCnt_reg_n_0_[1]\,
      I5 => \burstCnt_reg_n_0_[2]\,
      O => \burstCnt[15]_i_5__2_n_0\
    );
\burstCnt[15]_i_6__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008000000"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[13]\,
      I1 => \burstCnt_reg_n_0_[12]\,
      I2 => \burstCnt[15]_i_5__2_n_0\,
      I3 => \burstCnt_reg_n_0_[11]\,
      I4 => \burstCnt_reg_n_0_[10]\,
      I5 => \burstCnt[9]_i_2__2_n_0\,
      O => \burstCnt[15]_i_6__2_n_0\
    );
\burstCnt[15]_i_7__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF12333312"
    )
        port map (
      I0 => \quad_reg_n_0_[14]\,
      I1 => \burstCnt[15]_i_15__0_n_0\,
      I2 => state(6),
      I3 => \quad_reg_n_0_[9]\,
      I4 => state(1),
      I5 => \burstCnt[15]_i_16__0_n_0\,
      O => \burstCnt[15]_i_7__2_n_0\
    );
\burstCnt[15]_i_8__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AB040857"
    )
        port map (
      I0 => \quad_reg_n_0_[2]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(2),
      I4 => \quad_reg_n_0_[18]\,
      I5 => \burstCnt[15]_i_17__0_n_0\,
      O => \burstCnt[15]_i_8__2_n_0\
    );
\burstCnt[15]_i_9__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABAEAFAFAFAFABAE"
    )
        port map (
      I0 => \burstCnt[15]_i_18__0_n_0\,
      I1 => \quad_reg_n_0_[17]\,
      I2 => \dwrSeqbuf[23]_i_2__0_n_0\,
      I3 => state(1),
      I4 => \quad_reg_n_0_[19]\,
      I5 => state(3),
      O => \burstCnt[15]_i_9__2_n_0\
    );
\burstCnt[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000D0A"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[0]\,
      I1 => \burstCnt[15]_i_5__2_n_0\,
      I2 => first,
      I3 => \burstCnt_reg_n_0_[1]\,
      I4 => \burstCnt[3]_i_2_n_0\,
      O => \burstCnt[1]_i_1__2_n_0\
    );
\burstCnt[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004040404000000"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[15]_i_4__2_n_0\,
      I2 => \burstCnt[15]_i_5__2_n_0\,
      I3 => \burstCnt_reg_n_0_[0]\,
      I4 => \burstCnt_reg_n_0_[1]\,
      I5 => \burstCnt_reg_n_0_[2]\,
      O => \burstCnt[2]_i_1__2_n_0\
    );
\burstCnt[3]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000014444444"
    )
        port map (
      I0 => first,
      I1 => \burstCnt_reg_n_0_[3]\,
      I2 => \burstCnt_reg_n_0_[0]\,
      I3 => \burstCnt_reg_n_0_[1]\,
      I4 => \burstCnt_reg_n_0_[2]\,
      I5 => \burstCnt[3]_i_2_n_0\,
      O => \burstCnt[3]_i_1__2_n_0\
    );
\burstCnt[3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \burstCnt[15]_i_5__2_n_0\,
      I1 => \burstCnt[15]_i_4__2_n_0\,
      O => \burstCnt[3]_i_2_n_0\
    );
\burstCnt[4]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[4]_i_2__2_n_0\,
      O => \burstCnt[4]_i_1__2_n_0\
    );
\burstCnt[4]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAABFFFFFFF"
    )
        port map (
      I0 => \burstCnt[3]_i_2_n_0\,
      I1 => \burstCnt_reg_n_0_[3]\,
      I2 => \burstCnt_reg_n_0_[0]\,
      I3 => \burstCnt_reg_n_0_[1]\,
      I4 => \burstCnt_reg_n_0_[2]\,
      I5 => \burstCnt_reg_n_0_[4]\,
      O => \burstCnt[4]_i_2__2_n_0\
    );
\burstCnt[5]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[5]_i_2__2_n_0\,
      O => \burstCnt[5]_i_1__2_n_0\
    );
\burstCnt[5]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7D"
    )
        port map (
      I0 => \burstCnt[15]_i_4__2_n_0\,
      I1 => \burstCnt[9]_i_5_n_0\,
      I2 => \burstCnt_reg_n_0_[5]\,
      I3 => \burstCnt[15]_i_5__2_n_0\,
      O => \burstCnt[5]_i_2__2_n_0\
    );
\burstCnt[6]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[6]_i_2__1_n_0\,
      O => \burstCnt[6]_i_1__2_n_0\
    );
\burstCnt[6]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDEDFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[6]\,
      I1 => \burstCnt[15]_i_5__2_n_0\,
      I2 => \burstCnt_reg_n_0_[5]\,
      I3 => \burstCnt[9]_i_5_n_0\,
      I4 => \burstCnt[15]_i_4__2_n_0\,
      O => \burstCnt[6]_i_2__1_n_0\
    );
\burstCnt[7]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[7]_i_2__1_n_0\,
      O => \burstCnt[7]_i_1__2_n_0\
    );
\burstCnt[7]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5F5F9F5FFFFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[7]\,
      I1 => \burstCnt_reg_n_0_[6]\,
      I2 => \burstCnt[15]_i_5__2_n_0\,
      I3 => \burstCnt_reg_n_0_[5]\,
      I4 => \burstCnt[9]_i_5_n_0\,
      I5 => \burstCnt[15]_i_4__2_n_0\,
      O => \burstCnt[7]_i_2__1_n_0\
    );
\burstCnt[8]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[8]_i_2__1_n_0\,
      O => \burstCnt[8]_i_1__2_n_0\
    );
\burstCnt[8]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFDFDFDFDFFDDFDF"
    )
        port map (
      I0 => \burstCnt[15]_i_4__2_n_0\,
      I1 => \burstCnt[15]_i_5__2_n_0\,
      I2 => \burstCnt_reg_n_0_[8]\,
      I3 => \burstCnt[9]_i_4_n_0\,
      I4 => \burstCnt_reg_n_0_[5]\,
      I5 => \burstCnt[9]_i_5_n_0\,
      O => \burstCnt[8]_i_2__1_n_0\
    );
\burstCnt[9]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \burstCnt[9]_i_2__2_n_0\,
      I1 => \burstCnt[9]_i_3__0_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => first,
      O => \burstCnt[9]_i_1__2_n_0\
    );
\burstCnt[9]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFBFFFFFFFFFF"
    )
        port map (
      I0 => \burstCnt[15]_i_5__2_n_0\,
      I1 => \burstCnt_reg_n_0_[8]\,
      I2 => \burstCnt[9]_i_4_n_0\,
      I3 => \burstCnt_reg_n_0_[5]\,
      I4 => \burstCnt[9]_i_5_n_0\,
      I5 => \burstCnt_reg_n_0_[9]\,
      O => \burstCnt[9]_i_2__2_n_0\
    );
\burstCnt[9]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000FFFFFFDF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[8]\,
      I1 => \burstCnt[9]_i_4_n_0\,
      I2 => \burstCnt_reg_n_0_[5]\,
      I3 => \burstCnt[9]_i_5_n_0\,
      I4 => \burstCnt[15]_i_5__2_n_0\,
      I5 => \burstCnt_reg_n_0_[9]\,
      O => \burstCnt[9]_i_3__0_n_0\
    );
\burstCnt[9]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[6]\,
      I1 => \burstCnt_reg_n_0_[7]\,
      O => \burstCnt[9]_i_4_n_0\
    );
\burstCnt[9]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[4]\,
      I1 => \burstCnt_reg_n_0_[2]\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \burstCnt_reg_n_0_[0]\,
      I4 => \burstCnt_reg_n_0_[3]\,
      O => \burstCnt[9]_i_5_n_0\
    );
\burstCnt_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[0]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[0]\
    );
\burstCnt_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[10]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[10]\
    );
\burstCnt_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[11]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[11]\
    );
\burstCnt_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[12]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[12]\
    );
\burstCnt_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[13]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[13]\
    );
\burstCnt_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[14]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[14]\
    );
\burstCnt_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[15]_i_2__2_n_0\,
      Q => \burstCnt_reg_n_0_[15]\
    );
\burstCnt_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[1]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[1]\
    );
\burstCnt_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[2]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[2]\
    );
\burstCnt_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[3]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[3]\
    );
\burstCnt_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[4]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[4]\
    );
\burstCnt_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[5]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[5]\
    );
\burstCnt_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[6]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[6]\
    );
\burstCnt_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[7]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[7]\
    );
\burstCnt_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[8]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[8]\
    );
\burstCnt_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => \burstCnt[9]_i_1__2_n_0\,
      Q => \burstCnt_reg_n_0_[9]\
    );
\burstState[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => first,
      I1 => state(0),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      O => \burstState[0]_i_1__0_n_0\
    );
\burstState[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => first,
      I1 => state(1),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      O => \burstState[1]_i_1__0_n_0\
    );
\burstState[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => first,
      I1 => state(2),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      O => \burstState[2]_i_1_n_0\
    );
\burstState[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => first,
      I1 => state(3),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      O => \burstState[3]_i_1_n_0\
    );
\burstState[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => first,
      I1 => state(4),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      O => \burstState[4]_i_1__0_n_0\
    );
\burstState[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => first,
      I1 => state(5),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      O => \burstState[5]_i_1__0_n_0\
    );
\burstState[6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => first,
      I1 => state(6),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      O => \burstState[6]_i_1__0_n_0\
    );
\burstState[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => first,
      I1 => state(7),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      O => \burstState[7]_i_1_n_0\
    );
\burstState_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      D => \burstState[0]_i_1__0_n_0\,
      PRE => AR(0),
      Q => \burstState_reg_n_0_[0]\
    );
\burstState_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      D => \burstState[1]_i_1__0_n_0\,
      PRE => AR(0),
      Q => \burstState_reg_n_0_[1]\
    );
\burstState_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      D => \burstState[2]_i_1_n_0\,
      PRE => AR(0),
      Q => \burstState_reg_n_0_[2]\
    );
\burstState_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      D => \burstState[3]_i_1_n_0\,
      PRE => AR(0),
      Q => \burstState_reg_n_0_[3]\
    );
\burstState_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      D => \burstState[4]_i_1__0_n_0\,
      PRE => AR(0),
      Q => \burstState_reg_n_0_[4]\
    );
\burstState_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      D => \burstState[5]_i_1__0_n_0\,
      PRE => AR(0),
      Q => \burstState_reg_n_0_[5]\
    );
\burstState_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      D => \burstState[6]_i_1__0_n_0\,
      PRE => AR(0),
      Q => \burstState_reg_n_0_[6]\
    );
\burstState_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      D => \burstState[7]_i_1_n_0\,
      PRE => AR(0),
      Q => \burstState_reg_n_0_[7]\
    );
\dwrSeqbuf[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFFFDF0F0F0F0F0"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[0]\,
      I1 => \burstCnt[15]_i_5__2_n_0\,
      I2 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I3 => \burstCnt[15]_i_4__2_n_0\,
      I4 => \dwrSeqbuf[0]_i_2__2_n_0\,
      I5 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[0]_i_1__2_n_0\
    );
\dwrSeqbuf[0]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(0),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[0]\,
      O => \dwrSeqbuf[0]_i_2__2_n_0\
    );
\dwrSeqbuf[10]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[10]_i_2__1_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[10]_i_2__0_n_0\,
      I4 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[10]_i_1__2_n_0\
    );
\dwrSeqbuf[10]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(2),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[10]\,
      O => \dwrSeqbuf[10]_i_2__0_n_0\
    );
\dwrSeqbuf[11]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[11]_i_2__2_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[11]_i_2__0_n_0\,
      I4 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[11]_i_1__2_n_0\
    );
\dwrSeqbuf[11]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(3),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[11]\,
      O => \dwrSeqbuf[11]_i_2__0_n_0\
    );
\dwrSeqbuf[12]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[12]_i_2__1_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[12]_i_2__0_n_0\,
      I4 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[12]_i_1__2_n_0\
    );
\dwrSeqbuf[12]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(4),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[12]\,
      O => \dwrSeqbuf[12]_i_2__0_n_0\
    );
\dwrSeqbuf[13]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[13]_i_2__0_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[13]_i_2__0_n_0\,
      I4 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[13]_i_1__2_n_0\
    );
\dwrSeqbuf[13]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(5),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[13]\,
      O => \dwrSeqbuf[13]_i_2__0_n_0\
    );
\dwrSeqbuf[14]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BEFFBEAAAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[15]_i_6__2_n_0\,
      I2 => \dwrSeqbuf[14]_i_2__0_n_0\,
      I3 => \burstCnt[15]_i_4__2_n_0\,
      I4 => \dwrSeqbuf[14]_i_3_n_0\,
      I5 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[14]_i_1__2_n_0\
    );
\dwrSeqbuf[14]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[14]\,
      I1 => \burstCnt[15]_i_5__2_n_0\,
      O => \dwrSeqbuf[14]_i_2__0_n_0\
    );
\dwrSeqbuf[14]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(6),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[14]\,
      O => \dwrSeqbuf[14]_i_3_n_0\
    );
\dwrSeqbuf[15]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \dwrSeqbuf[15]_i_2__1_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[15]_i_3__1_n_0\,
      I4 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[15]_i_1__2_n_0\
    );
\dwrSeqbuf[15]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0FBFFFFFFFFFF"
    )
        port map (
      I0 => \dwrSeqbuf[15]_i_4_n_0\,
      I1 => \burstCnt_reg_n_0_[13]\,
      I2 => \burstCnt[15]_i_5__2_n_0\,
      I3 => \burstCnt_reg_n_0_[14]\,
      I4 => \burstCnt_reg_n_0_[15]\,
      I5 => \burstCnt[15]_i_4__2_n_0\,
      O => \dwrSeqbuf[15]_i_2__1_n_0\
    );
\dwrSeqbuf[15]_i_3__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(7),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[15]\,
      O => \dwrSeqbuf[15]_i_3__1_n_0\
    );
\dwrSeqbuf[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFDFFFFFFFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[9]\,
      I1 => \dwrSeqbuf[15]_i_5_n_0\,
      I2 => \burstCnt_reg_n_0_[10]\,
      I3 => \burstCnt_reg_n_0_[11]\,
      I4 => \burstCnt[15]_i_5__2_n_0\,
      I5 => \burstCnt_reg_n_0_[12]\,
      O => \dwrSeqbuf[15]_i_4_n_0\
    );
\dwrSeqbuf[15]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFBFF"
    )
        port map (
      I0 => \burstCnt[9]_i_5_n_0\,
      I1 => \burstCnt_reg_n_0_[5]\,
      I2 => \burstCnt[9]_i_4_n_0\,
      I3 => \burstCnt_reg_n_0_[8]\,
      I4 => \burstCnt[15]_i_13__1_n_0\,
      I5 => \dwrSeqbuf[15]_i_6_n_0\,
      O => \dwrSeqbuf[15]_i_5_n_0\
    );
\dwrSeqbuf[15]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002000"
    )
        port map (
      I0 => \burstCnt[13]_i_5_n_0\,
      I1 => \burstCnt[15]_i_25__0_n_0\,
      I2 => \burstCnt_reg_n_0_[12]\,
      I3 => \burstCnt_reg_n_0_[13]\,
      I4 => \burstCnt[9]_i_4_n_0\,
      I5 => \dwrSeqbuf[15]_i_7_n_0\,
      O => \dwrSeqbuf[15]_i_6_n_0\
    );
\dwrSeqbuf[15]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[10]\,
      I1 => \burstCnt_reg_n_0_[9]\,
      I2 => \burstCnt_reg_n_0_[5]\,
      I3 => \burstCnt_reg_n_0_[4]\,
      O => \dwrSeqbuf[15]_i_7_n_0\
    );
\dwrSeqbuf[16]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => state(0),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[31]_i_4__2_n_0\,
      I4 => \quad_reg_n_0_[16]\,
      I5 => \dwrSeqbuf[23]_i_2__0_n_0\,
      O => \dwrSeqbuf[16]_i_1__2_n_0\
    );
\dwrSeqbuf[17]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => state(1),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[31]_i_4__2_n_0\,
      I4 => \quad_reg_n_0_[17]\,
      I5 => \dwrSeqbuf[23]_i_2__0_n_0\,
      O => \dwrSeqbuf[17]_i_1__2_n_0\
    );
\dwrSeqbuf[18]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => state(2),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[31]_i_4__2_n_0\,
      I4 => \quad_reg_n_0_[18]\,
      I5 => \dwrSeqbuf[23]_i_2__0_n_0\,
      O => \dwrSeqbuf[18]_i_1__2_n_0\
    );
\dwrSeqbuf[19]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => state(3),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[31]_i_4__2_n_0\,
      I4 => \quad_reg_n_0_[19]\,
      I5 => \dwrSeqbuf[23]_i_2__0_n_0\,
      O => \dwrSeqbuf[19]_i_1__2_n_0\
    );
\dwrSeqbuf[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \dwrSeqbuf[1]_i_2__2_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[1]_i_3__2_n_0\,
      I4 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[1]_i_1__2_n_0\
    );
\dwrSeqbuf[1]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F2F5"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[0]\,
      I1 => \burstCnt[15]_i_5__2_n_0\,
      I2 => \burstCnt[3]_i_2_n_0\,
      I3 => \burstCnt_reg_n_0_[1]\,
      O => \dwrSeqbuf[1]_i_2__2_n_0\
    );
\dwrSeqbuf[1]_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(1),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[1]\,
      O => \dwrSeqbuf[1]_i_3__2_n_0\
    );
\dwrSeqbuf[20]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => state(4),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[31]_i_4__2_n_0\,
      I4 => \quad_reg_n_0_[20]\,
      I5 => \dwrSeqbuf[23]_i_2__0_n_0\,
      O => \dwrSeqbuf[20]_i_1__2_n_0\
    );
\dwrSeqbuf[21]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => state(5),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[31]_i_4__2_n_0\,
      I4 => \quad_reg_n_0_[21]\,
      I5 => \dwrSeqbuf[23]_i_2__0_n_0\,
      O => \dwrSeqbuf[21]_i_1__2_n_0\
    );
\dwrSeqbuf[22]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => state(6),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[31]_i_4__2_n_0\,
      I4 => \quad_reg_n_0_[22]\,
      I5 => \dwrSeqbuf[23]_i_2__0_n_0\,
      O => \dwrSeqbuf[22]_i_1__1_n_0\
    );
\dwrSeqbuf[23]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => state(7),
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[31]_i_4__2_n_0\,
      I4 => \quad_reg_n_0_[23]\,
      I5 => \dwrSeqbuf[23]_i_2__0_n_0\,
      O => \dwrSeqbuf[23]_i_1__1_n_0\
    );
\dwrSeqbuf[23]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      O => \dwrSeqbuf[23]_i_2__0_n_0\
    );
\dwrSeqbuf[24]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEFEAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[15]_i_4__2_n_0\,
      I2 => \quad_reg_n_0_[24]\,
      I3 => \burstCnt[15]_i_3__1_n_0\,
      I4 => state(0),
      I5 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[24]_i_1__1_n_0\
    );
\dwrSeqbuf[25]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEFEAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[15]_i_4__2_n_0\,
      I2 => \quad_reg_n_0_[25]\,
      I3 => \burstCnt[15]_i_3__1_n_0\,
      I4 => state(1),
      I5 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[25]_i_1__0_n_0\
    );
\dwrSeqbuf[26]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEFEAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[15]_i_4__2_n_0\,
      I2 => \quad_reg_n_0_[26]\,
      I3 => \burstCnt[15]_i_3__1_n_0\,
      I4 => state(2),
      I5 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[26]_i_1__0_n_0\
    );
\dwrSeqbuf[27]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEFEAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[15]_i_4__2_n_0\,
      I2 => \quad_reg_n_0_[27]\,
      I3 => \burstCnt[15]_i_3__1_n_0\,
      I4 => state(3),
      I5 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[27]_i_1__0_n_0\
    );
\dwrSeqbuf[28]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEFEAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[15]_i_4__2_n_0\,
      I2 => \quad_reg_n_0_[28]\,
      I3 => \burstCnt[15]_i_3__1_n_0\,
      I4 => state(4),
      I5 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[28]_i_1__0_n_0\
    );
\dwrSeqbuf[29]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEFEAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[15]_i_4__2_n_0\,
      I2 => \quad_reg_n_0_[29]\,
      I3 => \burstCnt[15]_i_3__1_n_0\,
      I4 => state(5),
      I5 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[29]_i_1__0_n_0\
    );
\dwrSeqbuf[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \dwrSeqbuf[2]_i_2__2_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[2]_i_3__2_n_0\,
      I4 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[2]_i_1__2_n_0\
    );
\dwrSeqbuf[2]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF95FFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[2]\,
      I1 => \burstCnt_reg_n_0_[1]\,
      I2 => \burstCnt_reg_n_0_[0]\,
      I3 => \burstCnt[15]_i_5__2_n_0\,
      I4 => \burstCnt[15]_i_4__2_n_0\,
      O => \dwrSeqbuf[2]_i_2__2_n_0\
    );
\dwrSeqbuf[2]_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(2),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[2]\,
      O => \dwrSeqbuf[2]_i_3__2_n_0\
    );
\dwrSeqbuf[30]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEFEAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[15]_i_4__2_n_0\,
      I2 => \quad_reg_n_0_[30]\,
      I3 => \burstCnt[15]_i_3__1_n_0\,
      I4 => state(6),
      I5 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[30]_i_1__2_n_0\
    );
\dwrSeqbuf[31]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAABABAAAAABAA"
    )
        port map (
      I0 => \burstCnt[15]_i_1__2_n_0\,
      I1 => \dwrSeqbuf[31]_i_3__2_n_0\,
      I2 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I3 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I4 => ackSeqbufBToSeqClear,
      I5 => rdySeq,
      O => \dwrSeqbuf[31]_i_1__2_n_0\
    );
\dwrSeqbuf[31]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEAE0000"
    )
        port map (
      I0 => \burstCnt[15]_i_4__2_n_0\,
      I1 => \quad_reg_n_0_[31]\,
      I2 => \burstCnt[15]_i_3__1_n_0\,
      I3 => state(7),
      I4 => \dwrSeqbuf[31]_i_4__2_n_0\,
      I5 => \dwrSeqbuf[31]_i_5__0_n_0\,
      O => \dwrSeqbuf[31]_i_2__2_n_0\
    );
\dwrSeqbuf[31]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F111F1F1F1F1F1F"
    )
        port map (
      I0 => TCapt,
      I1 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I2 => \FSM_onehot_stateSeq[5]_i_8__0_n_0\,
      I3 => stateOp(0),
      I4 => stateOp(2),
      I5 => stateOp(1),
      O => \dwrSeqbuf[31]_i_3__2_n_0\
    );
\dwrSeqbuf[31]_i_4__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => rdySeq,
      I2 => ackSeqbufBToSeqClear,
      I3 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I4 => TCapt,
      O => \dwrSeqbuf[31]_i_4__2_n_0\
    );
\dwrSeqbuf[31]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BAAA"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_8__0_n_0\,
      I1 => stateOp(0),
      I2 => stateOp(2),
      I3 => stateOp(1),
      I4 => \quad[23]_i_3_n_0\,
      O => \dwrSeqbuf[31]_i_5__0_n_0\
    );
\dwrSeqbuf[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \dwrSeqbuf[3]_i_2__2_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[3]_i_3__2_n_0\,
      I4 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[3]_i_1__2_n_0\
    );
\dwrSeqbuf[3]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAABFFF"
    )
        port map (
      I0 => \burstCnt[3]_i_2_n_0\,
      I1 => \burstCnt_reg_n_0_[2]\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \burstCnt_reg_n_0_[0]\,
      I4 => \burstCnt_reg_n_0_[3]\,
      O => \dwrSeqbuf[3]_i_2__2_n_0\
    );
\dwrSeqbuf[3]_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(3),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[3]\,
      O => \dwrSeqbuf[3]_i_3__2_n_0\
    );
\dwrSeqbuf[4]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[4]_i_2__2_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[4]_i_2__2_n_0\,
      I4 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[4]_i_1__2_n_0\
    );
\dwrSeqbuf[4]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(4),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[4]\,
      O => \dwrSeqbuf[4]_i_2__2_n_0\
    );
\dwrSeqbuf[5]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[5]_i_2__2_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[5]_i_2__2_n_0\,
      I4 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[5]_i_1__2_n_0\
    );
\dwrSeqbuf[5]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(5),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[5]\,
      O => \dwrSeqbuf[5]_i_2__2_n_0\
    );
\dwrSeqbuf[6]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[6]_i_2__1_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[6]_i_2__1_n_0\,
      I4 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[6]_i_1__2_n_0\
    );
\dwrSeqbuf[6]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(6),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[6]\,
      O => \dwrSeqbuf[6]_i_2__1_n_0\
    );
\dwrSeqbuf[7]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[7]_i_2__1_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[7]_i_2__2_n_0\,
      I4 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[7]_i_1__2_n_0\
    );
\dwrSeqbuf[7]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(7),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[7]\,
      O => \dwrSeqbuf[7]_i_2__2_n_0\
    );
\dwrSeqbuf[8]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I1 => \burstCnt[8]_i_2__1_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[8]_i_2__1_n_0\,
      I4 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[8]_i_1__2_n_0\
    );
\dwrSeqbuf[8]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(0),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[8]\,
      O => \dwrSeqbuf[8]_i_2__1_n_0\
    );
\dwrSeqbuf[9]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF2FFF20FF00FF00"
    )
        port map (
      I0 => \burstCnt[9]_i_2__2_n_0\,
      I1 => \burstCnt[9]_i_3__0_n_0\,
      I2 => \burstCnt[15]_i_4__2_n_0\,
      I3 => \dwrSeqbuf[31]_i_5__0_n_0\,
      I4 => \dwrSeqbuf[9]_i_2__0_n_0\,
      I5 => \dwrSeqbuf[31]_i_4__2_n_0\,
      O => \dwrSeqbuf[9]_i_1__2_n_0\
    );
\dwrSeqbuf[9]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(1),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[9]\,
      O => \dwrSeqbuf[9]_i_2__0_n_0\
    );
\dwrSeqbuf_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[0]_i_1__2_n_0\,
      Q => dwrSeqbuf(0)
    );
\dwrSeqbuf_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[10]_i_1__2_n_0\,
      Q => dwrSeqbuf(10)
    );
\dwrSeqbuf_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[11]_i_1__2_n_0\,
      Q => dwrSeqbuf(11)
    );
\dwrSeqbuf_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[12]_i_1__2_n_0\,
      Q => dwrSeqbuf(12)
    );
\dwrSeqbuf_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[13]_i_1__2_n_0\,
      Q => dwrSeqbuf(13)
    );
\dwrSeqbuf_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[14]_i_1__2_n_0\,
      Q => dwrSeqbuf(14)
    );
\dwrSeqbuf_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[15]_i_1__2_n_0\,
      Q => dwrSeqbuf(15)
    );
\dwrSeqbuf_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[16]_i_1__2_n_0\,
      Q => dwrSeqbuf(16)
    );
\dwrSeqbuf_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[17]_i_1__2_n_0\,
      Q => dwrSeqbuf(17)
    );
\dwrSeqbuf_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[18]_i_1__2_n_0\,
      Q => dwrSeqbuf(18)
    );
\dwrSeqbuf_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[19]_i_1__2_n_0\,
      Q => dwrSeqbuf(19)
    );
\dwrSeqbuf_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[1]_i_1__2_n_0\,
      Q => dwrSeqbuf(1)
    );
\dwrSeqbuf_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[20]_i_1__2_n_0\,
      Q => dwrSeqbuf(20)
    );
\dwrSeqbuf_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[21]_i_1__2_n_0\,
      Q => dwrSeqbuf(21)
    );
\dwrSeqbuf_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[22]_i_1__1_n_0\,
      Q => dwrSeqbuf(22)
    );
\dwrSeqbuf_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[23]_i_1__1_n_0\,
      Q => dwrSeqbuf(23)
    );
\dwrSeqbuf_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[24]_i_1__1_n_0\,
      Q => dwrSeqbuf(24)
    );
\dwrSeqbuf_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[25]_i_1__0_n_0\,
      Q => dwrSeqbuf(25)
    );
\dwrSeqbuf_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[26]_i_1__0_n_0\,
      Q => dwrSeqbuf(26)
    );
\dwrSeqbuf_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[27]_i_1__0_n_0\,
      Q => dwrSeqbuf(27)
    );
\dwrSeqbuf_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[28]_i_1__0_n_0\,
      Q => dwrSeqbuf(28)
    );
\dwrSeqbuf_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[29]_i_1__0_n_0\,
      Q => dwrSeqbuf(29)
    );
\dwrSeqbuf_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[2]_i_1__2_n_0\,
      Q => dwrSeqbuf(2)
    );
\dwrSeqbuf_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[30]_i_1__2_n_0\,
      Q => dwrSeqbuf(30)
    );
\dwrSeqbuf_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[31]_i_2__2_n_0\,
      Q => dwrSeqbuf(31)
    );
\dwrSeqbuf_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[3]_i_1__2_n_0\,
      Q => dwrSeqbuf(3)
    );
\dwrSeqbuf_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[4]_i_1__2_n_0\,
      Q => dwrSeqbuf(4)
    );
\dwrSeqbuf_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[5]_i_1__2_n_0\,
      Q => dwrSeqbuf(5)
    );
\dwrSeqbuf_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[6]_i_1__2_n_0\,
      Q => dwrSeqbuf(6)
    );
\dwrSeqbuf_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[7]_i_1__2_n_0\,
      Q => dwrSeqbuf(7)
    );
\dwrSeqbuf_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[8]_i_1__2_n_0\,
      Q => dwrSeqbuf(8)
    );
\dwrSeqbuf_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__2_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[9]_i_1__2_n_0\,
      Q => dwrSeqbuf(9)
    );
\enSeqbuf_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => first,
      O => enSeqbuf
    );
enSeqbuf_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => enSeqbuf,
      Q => enSeqbuf_reg_n_0
    );
first_reg: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      D => first,
      PRE => AR(0),
      Q => \first__0\
    );
\i[0]_i_1__19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \i_reg_n_0_[0]\,
      O => i(0)
    );
\i[1]_i_1__19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => rdySeq,
      I2 => ackSeqbufBToSeqClear,
      I3 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I4 => \FSM_onehot_stateSeq[3]_i_1__2_n_0\,
      O => \i[1]_i_1__19_n_0\
    );
\i[1]_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => first,
      O => i(1)
    );
\i__carry__0_i_10__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[29]\,
      I1 => \^q\(29),
      I2 => \TCaptMax_reg_n_0_[28]\,
      I3 => \^q\(28),
      O => \i__carry__0_i_10__0_n_0\
    );
\i__carry__0_i_11__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[27]\,
      I1 => \^q\(27),
      I2 => \TCaptMax_reg_n_0_[26]\,
      I3 => \^q\(26),
      O => \i__carry__0_i_11__0_n_0\
    );
\i__carry__0_i_12__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[25]\,
      I1 => \^q\(25),
      I2 => \TCaptMax_reg_n_0_[24]\,
      I3 => \^q\(24),
      O => \i__carry__0_i_12__0_n_0\
    );
\i__carry__0_i_13__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[23]\,
      I1 => \^q\(23),
      I2 => \TCaptMax_reg_n_0_[22]\,
      I3 => \^q\(22),
      O => \i__carry__0_i_13__0_n_0\
    );
\i__carry__0_i_14__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[21]\,
      I1 => \^q\(21),
      I2 => \TCaptMax_reg_n_0_[20]\,
      I3 => \^q\(20),
      O => \i__carry__0_i_14__0_n_0\
    );
\i__carry__0_i_15__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[19]\,
      I1 => \^q\(19),
      I2 => \TCaptMax_reg_n_0_[18]\,
      I3 => \^q\(18),
      O => \i__carry__0_i_15__0_n_0\
    );
\i__carry__0_i_16__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[17]\,
      I1 => \^q\(17),
      I2 => \TCaptMax_reg_n_0_[16]\,
      I3 => \^q\(16),
      O => \i__carry__0_i_16__0_n_0\
    );
\i__carry__0_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(31),
      I1 => \TCaptMax_reg_n_0_[31]\,
      I2 => \^q\(30),
      I3 => \TCaptMax_reg_n_0_[30]\,
      O => \i__carry__0_i_1__0_n_0\
    );
\i__carry__0_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(29),
      I1 => \TCaptMax_reg_n_0_[29]\,
      I2 => \^q\(28),
      I3 => \TCaptMax_reg_n_0_[28]\,
      O => \i__carry__0_i_2__0_n_0\
    );
\i__carry__0_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(27),
      I1 => \TCaptMax_reg_n_0_[27]\,
      I2 => \^q\(26),
      I3 => \TCaptMax_reg_n_0_[26]\,
      O => \i__carry__0_i_3__0_n_0\
    );
\i__carry__0_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(25),
      I1 => \TCaptMax_reg_n_0_[25]\,
      I2 => \^q\(24),
      I3 => \TCaptMax_reg_n_0_[24]\,
      O => \i__carry__0_i_4__0_n_0\
    );
\i__carry__0_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(23),
      I1 => \TCaptMax_reg_n_0_[23]\,
      I2 => \^q\(22),
      I3 => \TCaptMax_reg_n_0_[22]\,
      O => \i__carry__0_i_5__0_n_0\
    );
\i__carry__0_i_6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(21),
      I1 => \TCaptMax_reg_n_0_[21]\,
      I2 => \^q\(20),
      I3 => \TCaptMax_reg_n_0_[20]\,
      O => \i__carry__0_i_6__0_n_0\
    );
\i__carry__0_i_7__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(19),
      I1 => \TCaptMax_reg_n_0_[19]\,
      I2 => \^q\(18),
      I3 => \TCaptMax_reg_n_0_[18]\,
      O => \i__carry__0_i_7__0_n_0\
    );
\i__carry__0_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(17),
      I1 => \TCaptMax_reg_n_0_[17]\,
      I2 => \^q\(16),
      I3 => \TCaptMax_reg_n_0_[16]\,
      O => \i__carry__0_i_8__0_n_0\
    );
\i__carry__0_i_9__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[31]\,
      I1 => \^q\(31),
      I2 => \TCaptMax_reg_n_0_[30]\,
      I3 => \^q\(30),
      O => \i__carry__0_i_9__0_n_0\
    );
\i__carry_i_10__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[13]\,
      I1 => \^q\(13),
      I2 => \TCaptMax_reg_n_0_[12]\,
      I3 => \^q\(12),
      O => \i__carry_i_10__5_n_0\
    );
\i__carry_i_11__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[11]\,
      I1 => \^q\(11),
      I2 => \TCaptMax_reg_n_0_[10]\,
      I3 => \^q\(10),
      O => \i__carry_i_11__4_n_0\
    );
\i__carry_i_12__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[9]\,
      I1 => \^q\(9),
      I2 => \TCaptMax_reg_n_0_[8]\,
      I3 => \^q\(8),
      O => \i__carry_i_12__2_n_0\
    );
\i__carry_i_13__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[7]\,
      I1 => \^q\(7),
      I2 => \TCaptMax_reg_n_0_[6]\,
      I3 => \^q\(6),
      O => \i__carry_i_13__1_n_0\
    );
\i__carry_i_14__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[5]\,
      I1 => \^q\(5),
      I2 => \TCaptMax_reg_n_0_[4]\,
      I3 => \^q\(4),
      O => \i__carry_i_14__0_n_0\
    );
\i__carry_i_15__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[3]\,
      I1 => \^q\(3),
      I2 => \TCaptMax_reg_n_0_[2]\,
      I3 => \^q\(2),
      O => \i__carry_i_15__0_n_0\
    );
\i__carry_i_16__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[1]\,
      I1 => \^q\(1),
      I2 => \TCaptMax_reg_n_0_[0]\,
      I3 => \^q\(0),
      O => \i__carry_i_16__0_n_0\
    );
\i__carry_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(15),
      I1 => \TCaptMax_reg_n_0_[15]\,
      I2 => \^q\(14),
      I3 => \TCaptMax_reg_n_0_[14]\,
      O => \i__carry_i_1__6_n_0\
    );
\i__carry_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(13),
      I1 => \TCaptMax_reg_n_0_[13]\,
      I2 => \^q\(12),
      I3 => \TCaptMax_reg_n_0_[12]\,
      O => \i__carry_i_2__6_n_0\
    );
\i__carry_i_3__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(11),
      I1 => \TCaptMax_reg_n_0_[11]\,
      I2 => \^q\(10),
      I3 => \TCaptMax_reg_n_0_[10]\,
      O => \i__carry_i_3__6_n_0\
    );
\i__carry_i_4__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(9),
      I1 => \TCaptMax_reg_n_0_[9]\,
      I2 => \^q\(8),
      I3 => \TCaptMax_reg_n_0_[8]\,
      O => \i__carry_i_4__6_n_0\
    );
\i__carry_i_5__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(7),
      I1 => \TCaptMax_reg_n_0_[7]\,
      I2 => \^q\(6),
      I3 => \TCaptMax_reg_n_0_[6]\,
      O => \i__carry_i_5__6_n_0\
    );
\i__carry_i_6__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(5),
      I1 => \TCaptMax_reg_n_0_[5]\,
      I2 => \^q\(4),
      I3 => \TCaptMax_reg_n_0_[4]\,
      O => \i__carry_i_6__6_n_0\
    );
\i__carry_i_7__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(3),
      I1 => \TCaptMax_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \TCaptMax_reg_n_0_[2]\,
      O => \i__carry_i_7__5_n_0\
    );
\i__carry_i_8__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(1),
      I1 => \TCaptMax_reg_n_0_[1]\,
      I2 => \^q\(0),
      I3 => \TCaptMax_reg_n_0_[0]\,
      O => \i__carry_i_8__5_n_0\
    );
\i__carry_i_9__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[15]\,
      I1 => \^q\(15),
      I2 => \TCaptMax_reg_n_0_[14]\,
      I3 => \^q\(14),
      O => \i__carry_i_9__5_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[1]_i_1__19_n_0\,
      CLR => AR(0),
      D => i(0),
      Q => \i_reg_n_0_[0]\
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[1]_i_1__19_n_0\,
      CLR => AR(0),
      D => i(1),
      Q => \i_reg_n_0_[1]\
    );
mySeqbuf: entity work.\design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__1\
     port map (
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(31 downto 0) => dwrSeqbuf(31 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8) => \aSeqbufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \aSeqbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \aSeqbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \aSeqbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \aSeqbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \aSeqbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \aSeqbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \aSeqbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \aSeqbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2 downto 0) => stateSeqbufB_reg(2 downto 0),
      Q(9) => \aSeqbuf_reg_n_0_[9]\,
      Q(8) => \aSeqbuf_reg_n_0_[8]\,
      Q(7) => \aSeqbuf_reg_n_0_[7]\,
      Q(6) => \aSeqbuf_reg_n_0_[6]\,
      Q(5) => \aSeqbuf_reg_n_0_[5]\,
      Q(4) => \aSeqbuf_reg_n_0_[4]\,
      Q(3) => \aSeqbuf_reg_n_0_[3]\,
      Q(2) => \aSeqbuf_reg_n_0_[2]\,
      Q(1) => \aSeqbuf_reg_n_0_[1]\,
      Q(0) => \aSeqbuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      doutb(63 downto 0) => doutb(63 downto 0),
      ena => enSeqbuf_reg_n_0
    );
plusOp_carry: unisim.vcomponents.CARRY8
     port map (
      CI => \^q\(0),
      CI_TOP => '0',
      CO(7) => plusOp_carry_n_0,
      CO(6) => plusOp_carry_n_1,
      CO(5) => plusOp_carry_n_2,
      CO(4) => plusOp_carry_n_3,
      CO(3) => plusOp_carry_n_4,
      CO(2) => plusOp_carry_n_5,
      CO(1) => plusOp_carry_n_6,
      CO(0) => plusOp_carry_n_7,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in12(8 downto 1),
      S(7 downto 0) => \^q\(8 downto 1)
    );
\plusOp_carry__0\: unisim.vcomponents.CARRY8
     port map (
      CI => plusOp_carry_n_0,
      CI_TOP => '0',
      CO(7) => \plusOp_carry__0_n_0\,
      CO(6) => \plusOp_carry__0_n_1\,
      CO(5) => \plusOp_carry__0_n_2\,
      CO(4) => \plusOp_carry__0_n_3\,
      CO(3) => \plusOp_carry__0_n_4\,
      CO(2) => \plusOp_carry__0_n_5\,
      CO(1) => \plusOp_carry__0_n_6\,
      CO(0) => \plusOp_carry__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in12(16 downto 9),
      S(7 downto 0) => \^q\(16 downto 9)
    );
\plusOp_carry__1\: unisim.vcomponents.CARRY8
     port map (
      CI => \plusOp_carry__0_n_0\,
      CI_TOP => '0',
      CO(7) => \plusOp_carry__1_n_0\,
      CO(6) => \plusOp_carry__1_n_1\,
      CO(5) => \plusOp_carry__1_n_2\,
      CO(4) => \plusOp_carry__1_n_3\,
      CO(3) => \plusOp_carry__1_n_4\,
      CO(2) => \plusOp_carry__1_n_5\,
      CO(1) => \plusOp_carry__1_n_6\,
      CO(0) => \plusOp_carry__1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in12(24 downto 17),
      S(7 downto 0) => \^q\(24 downto 17)
    );
\plusOp_carry__2\: unisim.vcomponents.CARRY8
     port map (
      CI => \plusOp_carry__1_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_plusOp_carry__2_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \plusOp_carry__2_n_2\,
      CO(4) => \plusOp_carry__2_n_3\,
      CO(3) => \plusOp_carry__2_n_4\,
      CO(2) => \plusOp_carry__2_n_5\,
      CO(1) => \plusOp_carry__2_n_6\,
      CO(0) => \plusOp_carry__2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NLW_plusOp_carry__2_O_UNCONNECTED\(7),
      O(6 downto 0) => in12(31 downto 25),
      S(7) => '0',
      S(6 downto 0) => \^q\(31 downto 25)
    );
\ptr0SeqbufTrackNotFixed_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2F2F2FFF20202000"
    )
        port map (
      I0 => \burstCnt[3]_i_2_n_0\,
      I1 => first,
      I2 => \aSeqbuf[9]_i_3__2_n_0\,
      I3 => \FSM_onehot_stateSeq[5]_i_5__2_n_0\,
      I4 => \FSM_onehot_stateSeq[5]_i_7__2_n_0\,
      I5 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => \ptr0SeqbufTrackNotFixed_i_1__2_n_0\
    );
ptr0SeqbufTrackNotFixed_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \ptr0SeqbufTrackNotFixed_i_1__2_n_0\,
      Q => ptr0SeqbufTrackNotFixed_reg_n_0
    );
\quad[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[0]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(0),
      I4 => first,
      O => quad(0)
    );
\quad[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[10]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(2),
      I4 => first,
      O => quad(10)
    );
\quad[11]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[11]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(3),
      I4 => first,
      O => quad(11)
    );
\quad[12]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[12]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(4),
      I4 => first,
      O => quad(12)
    );
\quad[13]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[13]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(5),
      I4 => first,
      O => quad(13)
    );
\quad[14]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[14]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(6),
      I4 => first,
      O => quad(14)
    );
\quad[15]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"080808AA"
    )
        port map (
      I0 => \quad[23]_i_3_n_0\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I4 => TCapt,
      O => \quad[15]_i_1__0_n_0\
    );
\quad[15]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[15]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(15)
    );
\quad[16]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[16]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(0),
      I4 => first,
      O => quad(16)
    );
\quad[17]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[17]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(1),
      I4 => first,
      O => quad(17)
    );
\quad[18]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[18]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(2),
      I4 => first,
      O => quad(18)
    );
\quad[19]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[19]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(3),
      I4 => first,
      O => quad(19)
    );
\quad[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(1),
      I4 => first,
      O => quad(1)
    );
\quad[20]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[20]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(4),
      I4 => first,
      O => quad(20)
    );
\quad[21]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[21]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(5),
      I4 => first,
      O => quad(21)
    );
\quad[22]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[22]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(6),
      I4 => first,
      O => quad(22)
    );
\quad[23]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"080808AA"
    )
        port map (
      I0 => \quad[23]_i_3_n_0\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I4 => TCapt,
      O => \quad[23]_i_1__0_n_0\
    );
\quad[23]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[23]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(7),
      I4 => first,
      O => quad(23)
    );
\quad[23]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I1 => ackSeqbufBToSeqClear,
      I2 => rdySeq,
      I3 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \quad[23]_i_3_n_0\
    );
\quad[24]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[24]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(0),
      I4 => first,
      O => quad(24)
    );
\quad[25]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[25]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(1),
      I4 => first,
      O => quad(25)
    );
\quad[26]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[26]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(2),
      I4 => first,
      O => quad(26)
    );
\quad[27]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[27]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(3),
      I4 => first,
      O => quad(27)
    );
\quad[28]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[28]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(4),
      I4 => first,
      O => quad(28)
    );
\quad[29]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[29]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(5),
      I4 => first,
      O => quad(29)
    );
\quad[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[2]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(2),
      I4 => first,
      O => quad(2)
    );
\quad[30]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[30]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(6),
      I4 => first,
      O => quad(30)
    );
\quad[31]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[31]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(31)
    );
\quad[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[3]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(3),
      I4 => first,
      O => quad(3)
    );
\quad[4]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[4]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(4),
      I4 => first,
      O => quad(4)
    );
\quad[5]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[5]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(5),
      I4 => first,
      O => quad(5)
    );
\quad[6]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[6]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(6),
      I4 => first,
      O => quad(6)
    );
\quad[7]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000101"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => rdySeq,
      I2 => ackSeqbufBToSeqClear,
      I3 => \quad[7]_i_3_n_0\,
      I4 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I5 => TCapt,
      O => \quad[7]_i_1__1_n_0\
    );
\quad[7]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[7]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(7)
    );
\quad[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \i_reg_n_0_[1]\,
      O => \quad[7]_i_3_n_0\
    );
\quad[8]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[8]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(0),
      I4 => first,
      O => quad(8)
    );
\quad[9]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[9]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(1),
      I4 => first,
      O => quad(9)
    );
\quad_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1__1_n_0\,
      CLR => AR(0),
      D => quad(0),
      Q => \quad_reg_n_0_[0]\
    );
\quad_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(10),
      Q => \quad_reg_n_0_[10]\
    );
\quad_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(11),
      Q => \quad_reg_n_0_[11]\
    );
\quad_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(12),
      Q => \quad_reg_n_0_[12]\
    );
\quad_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(13),
      Q => \quad_reg_n_0_[13]\
    );
\quad_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(14),
      Q => \quad_reg_n_0_[14]\
    );
\quad_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(15),
      Q => \quad_reg_n_0_[15]\
    );
\quad_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(16),
      Q => \quad_reg_n_0_[16]\
    );
\quad_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(17),
      Q => \quad_reg_n_0_[17]\
    );
\quad_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(18),
      Q => \quad_reg_n_0_[18]\
    );
\quad_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(19),
      Q => \quad_reg_n_0_[19]\
    );
\quad_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1__1_n_0\,
      CLR => AR(0),
      D => quad(1),
      Q => \quad_reg_n_0_[1]\
    );
\quad_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(20),
      Q => \quad_reg_n_0_[20]\
    );
\quad_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(21),
      Q => \quad_reg_n_0_[21]\
    );
\quad_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(22),
      Q => \quad_reg_n_0_[22]\
    );
\quad_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(23),
      Q => \quad_reg_n_0_[23]\
    );
\quad_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => quad(24),
      Q => \quad_reg_n_0_[24]\
    );
\quad_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => quad(25),
      Q => \quad_reg_n_0_[25]\
    );
\quad_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => quad(26),
      Q => \quad_reg_n_0_[26]\
    );
\quad_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => quad(27),
      Q => \quad_reg_n_0_[27]\
    );
\quad_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => quad(28),
      Q => \quad_reg_n_0_[28]\
    );
\quad_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => quad(29),
      Q => \quad_reg_n_0_[29]\
    );
\quad_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1__1_n_0\,
      CLR => AR(0),
      D => quad(2),
      Q => \quad_reg_n_0_[2]\
    );
\quad_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => quad(30),
      Q => \quad_reg_n_0_[30]\
    );
\quad_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__2_n_0\,
      CLR => AR(0),
      D => quad(31),
      Q => \quad_reg_n_0_[31]\
    );
\quad_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1__1_n_0\,
      CLR => AR(0),
      D => quad(3),
      Q => \quad_reg_n_0_[3]\
    );
\quad_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1__1_n_0\,
      CLR => AR(0),
      D => quad(4),
      Q => \quad_reg_n_0_[4]\
    );
\quad_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1__1_n_0\,
      CLR => AR(0),
      D => quad(5),
      Q => \quad_reg_n_0_[5]\
    );
\quad_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1__1_n_0\,
      CLR => AR(0),
      D => quad(6),
      Q => \quad_reg_n_0_[6]\
    );
\quad_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1__1_n_0\,
      CLR => AR(0),
      D => quad(7),
      Q => \quad_reg_n_0_[7]\
    );
\quad_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(8),
      Q => \quad_reg_n_0_[8]\
    );
\quad_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(9),
      Q => \quad_reg_n_0_[9]\
    );
\restart_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFCFFFF00100010"
    )
        port map (
      I0 => ackInvSelect_sig_reg_0,
      I1 => stateOp(2),
      I2 => stateOp(0),
      I3 => stateOp(1),
      I4 => restart_reg_0,
      I5 => restart_reg_n_0,
      O => \restart_i_1__2_n_0\
    );
restart_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \restart_i_1__2_n_0\,
      Q => restart_reg_n_0
    );
\retbuf[0][0]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"24"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(1),
      I2 => stateOp(2),
      O => \^cputrackgetinfotixvstate\(0)
    );
\retbuf[5][0]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[8]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => cputrackGetInfoPtr0Seqbuf(8)
    );
\retbuf[5][1]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[9]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => cputrackGetInfoPtr0Seqbuf(9)
    );
\retbuf[6][0]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[0]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => cputrackGetInfoPtr0Seqbuf(0)
    );
\retbuf[6][1]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[1]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => cputrackGetInfoPtr0Seqbuf(1)
    );
\retbuf[6][2]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[2]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => cputrackGetInfoPtr0Seqbuf(2)
    );
\retbuf[6][3]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[3]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => cputrackGetInfoPtr0Seqbuf(3)
    );
\retbuf[6][4]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[4]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => cputrackGetInfoPtr0Seqbuf(4)
    );
\retbuf[6][5]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[5]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => cputrackGetInfoPtr0Seqbuf(5)
    );
\retbuf[6][6]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[6]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => cputrackGetInfoPtr0Seqbuf(6)
    );
\retbuf[6][7]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[7]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => cputrackGetInfoPtr0Seqbuf(7)
    );
rng_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => AR(0),
      D => hdrNotFix,
      Q => rng_reg_n_0
    );
\staTixVTrigger[7]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA8A"
    )
        port map (
      I0 => reqInvSelect,
      I1 => stateOp(2),
      I2 => stateOp(0),
      I3 => stateOp(1),
      O => staFallingNotRising
    );
\staTixVTrigger_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(16),
      Q => staTixVTrigger(0)
    );
\staTixVTrigger_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(17),
      Q => staTixVTrigger(1)
    );
\staTixVTrigger_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(18),
      Q => staTixVTrigger(2)
    );
\staTixVTrigger_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(19),
      Q => staTixVTrigger(3)
    );
\staTixVTrigger_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(20),
      Q => staTixVTrigger(4)
    );
\staTixVTrigger_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(21),
      Q => staTixVTrigger(5)
    );
\staTixVTrigger_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(22),
      Q => staTixVTrigger(6)
    );
\staTixVTrigger_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(23),
      Q => staTixVTrigger(7)
    );
\stateOp[0]_i_1__12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEFEFFE"
    )
        port map (
      I0 => reqInvSelect,
      I1 => reqInvCputrackSet,
      I2 => stateOp(0),
      I3 => stateOp(1),
      I4 => stateOp(2),
      O => \stateOp[0]_i_1__12_n_0\
    );
\stateOp[1]_i_1__12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000CC008000C0008"
    )
        port map (
      I0 => rng_reg_n_0,
      I1 => restart_reg_0,
      I2 => stateOp(2),
      I3 => stateOp(0),
      I4 => stateOp(1),
      I5 => restart_reg_n_0,
      O => \stateOp[1]_i_1__12_n_0\
    );
\stateOp[2]_i_10__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEE0FEEEEEE0F"
    )
        port map (
      I0 => reqInvCputrackSet,
      I1 => reqInvSelect,
      I2 => stateOp(0),
      I3 => stateOp(2),
      I4 => stateOp(1),
      I5 => rdySeq,
      O => \stateOp[2]_i_10__3_n_0\
    );
\stateOp[2]_i_11__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[5]\,
      I1 => \TCaptMax_reg_n_0_[4]\,
      I2 => \TCaptMax_reg_n_0_[7]\,
      I3 => \TCaptMax_reg_n_0_[6]\,
      O => \stateOp[2]_i_11__2_n_0\
    );
\stateOp[2]_i_12__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[8]\,
      I1 => \TCaptMax_reg_n_0_[9]\,
      I2 => \TCaptMax_reg_n_0_[10]\,
      I3 => \TCaptMax_reg_n_0_[11]\,
      I4 => \stateOp[2]_i_18__3_n_0\,
      O => \stateOp[2]_i_12__2_n_0\
    );
\stateOp[2]_i_13__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[21]\,
      I1 => \TCaptMax_reg_n_0_[20]\,
      I2 => \TCaptMax_reg_n_0_[23]\,
      I3 => \TCaptMax_reg_n_0_[22]\,
      O => \stateOp[2]_i_13__3_n_0\
    );
\stateOp[2]_i_14__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[24]\,
      I1 => \TCaptMax_reg_n_0_[27]\,
      I2 => \TCaptMax_reg_n_0_[25]\,
      I3 => \TCaptMax_reg_n_0_[26]\,
      I4 => \stateOp[2]_i_19__3_n_0\,
      O => \stateOp[2]_i_14__2_n_0\
    );
\stateOp[2]_i_15__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^q\(15),
      I1 => \^q\(14),
      I2 => \^q\(23),
      I3 => \^q\(12),
      O => \stateOp[2]_i_15__3_n_0\
    );
\stateOp[2]_i_16__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBFFFFFFF"
    )
        port map (
      I0 => \stateOp[2]_i_20__3_n_0\,
      I1 => \^q\(11),
      I2 => \^q\(10),
      I3 => \^q\(21),
      I4 => \^q\(16),
      I5 => \stateOp[2]_i_21__2_n_0\,
      O => \stateOp[2]_i_16__3_n_0\
    );
\stateOp[2]_i_17__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => staTixVTrigger(6),
      I1 => staTixVTrigger(5),
      I2 => staTixVTrigger(2),
      I3 => staTixVTrigger(0),
      O => \stateOp[2]_i_17__3_n_0\
    );
\stateOp[2]_i_18__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[13]\,
      I1 => \TCaptMax_reg_n_0_[12]\,
      I2 => \TCaptMax_reg_n_0_[15]\,
      I3 => \TCaptMax_reg_n_0_[14]\,
      O => \stateOp[2]_i_18__3_n_0\
    );
\stateOp[2]_i_19__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[29]\,
      I1 => \TCaptMax_reg_n_0_[28]\,
      I2 => \TCaptMax_reg_n_0_[31]\,
      I3 => \TCaptMax_reg_n_0_[30]\,
      O => \stateOp[2]_i_19__3_n_0\
    );
\stateOp[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFE0E0E040"
    )
        port map (
      I0 => stateOp(0),
      I1 => \stateOp[2]_i_3__4_n_0\,
      I2 => \^cputrackgetinfotixvstate\(1),
      I3 => rdySeq,
      I4 => restart_reg_n_0,
      I5 => \stateOp[2]_i_5__4_n_0\,
      O => \stateOp[2]_i_1__3_n_0\
    );
\stateOp[2]_i_20__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^q\(31),
      I1 => \^q\(24),
      I2 => \^q\(27),
      I3 => \^q\(18),
      O => \stateOp[2]_i_20__3_n_0\
    );
\stateOp[2]_i_21__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \^q\(8),
      I1 => \^q\(25),
      I2 => \^q\(9),
      I3 => \^q\(19),
      I4 => \stateOp[2]_i_22__2_n_0\,
      O => \stateOp[2]_i_21__2_n_0\
    );
\stateOp[2]_i_22__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^q\(30),
      I1 => \^q\(17),
      I2 => \^q\(26),
      I3 => \^q\(20),
      O => \stateOp[2]_i_22__2_n_0\
    );
\stateOp[2]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00300030003023F0"
    )
        port map (
      I0 => restart_reg_n_0,
      I1 => stateOp(1),
      I2 => stateOp(0),
      I3 => stateOp(2),
      I4 => reqInvCputrackSet,
      I5 => reqInvSelect,
      O => \stateOp[2]_i_2__4_n_0\
    );
\stateOp[2]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF54545400"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[3]_i_3__1_n_0\,
      I1 => \strbStop5_inferred__0/i__carry__0_n_0\,
      I2 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I3 => \stateOp[2]_i_6__2_n_0\,
      I4 => \stateOp[2]_i_7__3_n_0\,
      I5 => \stateOp[2]_i_8__3_n_0\,
      O => \stateOp[2]_i_3__4_n_0\
    );
\stateOp[2]_i_4__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(1),
      O => \^cputrackgetinfotixvstate\(1)
    );
\stateOp[2]_i_5__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0F040000"
    )
        port map (
      I0 => ackInvSelect_sig_reg_0,
      I1 => stateOp(0),
      I2 => stateOp(2),
      I3 => stateOp(1),
      I4 => \stateOp[2]_i_9__1_n_0\,
      I5 => \stateOp[2]_i_10__3_n_0\,
      O => \stateOp[2]_i_5__4_n_0\
    );
\stateOp[2]_i_6__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \stateOp[2]_i_11__2_n_0\,
      I1 => \TCaptMax_reg_n_0_[2]\,
      I2 => \TCaptMax_reg_n_0_[1]\,
      I3 => \TCaptMax_reg_n_0_[3]\,
      I4 => \TCaptMax_reg_n_0_[0]\,
      I5 => \stateOp[2]_i_12__2_n_0\,
      O => \stateOp[2]_i_6__2_n_0\
    );
\stateOp[2]_i_7__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \stateOp[2]_i_13__3_n_0\,
      I1 => \TCaptMax_reg_n_0_[19]\,
      I2 => \TCaptMax_reg_n_0_[18]\,
      I3 => \TCaptMax_reg_n_0_[17]\,
      I4 => \TCaptMax_reg_n_0_[16]\,
      I5 => \stateOp[2]_i_14__2_n_0\,
      O => \stateOp[2]_i_7__3_n_0\
    );
\stateOp[2]_i_8__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040000000"
    )
        port map (
      I0 => \stateOp[2]_i_15__3_n_0\,
      I1 => \^q\(29),
      I2 => \^q\(28),
      I3 => \^q\(22),
      I4 => \^q\(13),
      I5 => \stateOp[2]_i_16__3_n_0\,
      O => \stateOp[2]_i_8__3_n_0\
    );
\stateOp[2]_i_9__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAAB"
    )
        port map (
      I0 => stateOp(0),
      I1 => \stateOp[2]_i_17__3_n_0\,
      I2 => staTixVTrigger(3),
      I3 => staTixVTrigger(1),
      I4 => staTixVTrigger(7),
      I5 => staTixVTrigger(4),
      O => \stateOp[2]_i_9__1_n_0\
    );
\stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[2]_i_1__3_n_0\,
      CLR => AR(0),
      D => \stateOp[0]_i_1__12_n_0\,
      Q => stateOp(0)
    );
\stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[2]_i_1__3_n_0\,
      CLR => AR(0),
      D => \stateOp[1]_i_1__12_n_0\,
      Q => stateOp(1)
    );
\stateOp_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[2]_i_1__3_n_0\,
      CLR => AR(0),
      D => \stateOp[2]_i_2__4_n_0\,
      Q => stateOp(2)
    );
\stateSeqbufB[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0705"
    )
        port map (
      I0 => stateSeqbufB_reg(2),
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      I3 => dneSeqbufCputrackToHostif,
      O => \p_0_in__0\(0)
    );
\stateSeqbufB[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00BC"
    )
        port map (
      I0 => \stateSeqbufB[1]_i_2__2_n_0\,
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      I3 => stateSeqbufB_reg(2),
      O => \p_0_in__0\(1)
    );
\stateSeqbufB[1]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAAAAAA"
    )
        port map (
      I0 => seqbufCputrackToHostifAXIS_tready,
      I1 => \aSeqbufB_reg_n_0_[8]\,
      I2 => \aSeqbufB_reg_n_0_[6]\,
      I3 => \aSeqbufB[8]_i_4__2_n_0\,
      I4 => \aSeqbufB_reg_n_0_[7]\,
      O => \stateSeqbufB[1]_i_2__2_n_0\
    );
\stateSeqbufB[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBABBABBBBABB"
    )
        port map (
      I0 => \stateSeqbufB[2]_i_3__2_n_0\,
      I1 => stateSeqbufB_reg(2),
      I2 => reqSeqbufCputrackToHostif,
      I3 => stateSeqbufB_reg(0),
      I4 => stateSeqbufB_reg(1),
      I5 => seqbufCputrackToHostifAXIS_tready,
      O => \stateSeqbufB[2]_i_1__2_n_0\
    );
\stateSeqbufB[2]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000AC000000A0000"
    )
        port map (
      I0 => dneSeqbufCputrackToHostif,
      I1 => \stateSeqbufB[2]_i_7__2_n_0\,
      I2 => stateSeqbufB_reg(1),
      I3 => stateSeqbufB_reg(0),
      I4 => stateSeqbufB_reg(2),
      I5 => seqbufCputrackToHostifAXIS_tready,
      O => \p_0_in__0\(2)
    );
\stateSeqbufB[2]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000C088CC"
    )
        port map (
      I0 => dneSeqbufCputrackToHostif,
      I1 => stateSeqbufB_reg(2),
      I2 => ackSeqbufBToSeqClear,
      I3 => reqSeqbufCputrackToHostif,
      I4 => stateSeqbufB_reg(0),
      I5 => stateSeqbufB_reg(1),
      O => \stateSeqbufB[2]_i_3__2_n_0\
    );
\stateSeqbufB[2]_i_7__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[7]\,
      I1 => \aSeqbufB[8]_i_4__2_n_0\,
      I2 => \aSeqbufB_reg_n_0_[6]\,
      I3 => \aSeqbufB_reg_n_0_[8]\,
      O => \stateSeqbufB[2]_i_7__2_n_0\
    );
\stateSeqbufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSeqbufB[2]_i_1__2_n_0\,
      CLR => AR(0),
      D => \p_0_in__0\(0),
      Q => stateSeqbufB_reg(0)
    );
\stateSeqbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSeqbufB[2]_i_1__2_n_0\,
      CLR => AR(0),
      D => \p_0_in__0\(1),
      Q => stateSeqbufB_reg(1)
    );
\stateSeqbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSeqbufB[2]_i_1__2_n_0\,
      CLR => AR(0),
      D => \p_0_in__0\(2),
      Q => stateSeqbufB_reg(2)
    );
\state[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFBEB"
    )
        port map (
      I0 => \state[7]_i_2__0_n_0\,
      I1 => \tixVCapture_reg_n_0_[0]\,
      I2 => \tixVCapture_reg_n_0_[1]\,
      I3 => stateOp_dbg(0),
      I4 => hostifStateOp_dbg(0),
      O => \state[0]_i_1__0_n_0\
    );
\state[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFBEB"
    )
        port map (
      I0 => \state[7]_i_2__0_n_0\,
      I1 => \tixVCapture_reg_n_0_[0]\,
      I2 => \tixVCapture_reg_n_0_[1]\,
      I3 => stateOp_dbg(1),
      I4 => hostifStateOp_dbg(1),
      O => \state[1]_i_1_n_0\
    );
\state[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFBEB"
    )
        port map (
      I0 => \state[7]_i_2__0_n_0\,
      I1 => \tixVCapture_reg_n_0_[0]\,
      I2 => \tixVCapture_reg_n_0_[1]\,
      I3 => stateOp_dbg(2),
      I4 => hostifStateOp_dbg(2),
      O => \state[2]_i_1_n_0\
    );
\state[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFBEB"
    )
        port map (
      I0 => \state[7]_i_2__0_n_0\,
      I1 => \tixVCapture_reg_n_0_[0]\,
      I2 => \tixVCapture_reg_n_0_[1]\,
      I3 => stateOp_dbg(6),
      I4 => hostifStateOp_dbg(3),
      O => \state[3]_i_1_n_0\
    );
\state[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFBEB"
    )
        port map (
      I0 => \state[7]_i_2__0_n_0\,
      I1 => \tixVCapture_reg_n_0_[0]\,
      I2 => \tixVCapture_reg_n_0_[1]\,
      I3 => stateOp_dbg(3),
      I4 => hostifStateOp_dbg(4),
      O => \state[4]_i_1__0_n_0\
    );
\state[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFBEB"
    )
        port map (
      I0 => \state[7]_i_2__0_n_0\,
      I1 => \tixVCapture_reg_n_0_[0]\,
      I2 => \tixVCapture_reg_n_0_[1]\,
      I3 => stateOp_dbg(4),
      I4 => hostifStateOp_dbg(5),
      O => \state[5]_i_1__0_n_0\
    );
\state[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFBEB"
    )
        port map (
      I0 => \state[7]_i_2__0_n_0\,
      I1 => \tixVCapture_reg_n_0_[0]\,
      I2 => \tixVCapture_reg_n_0_[1]\,
      I3 => stateOp_dbg(5),
      I4 => hostifStateOp_dbg(6),
      O => \state[6]_i_1__0_n_0\
    );
\state[7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFBEB"
    )
        port map (
      I0 => \state[7]_i_2__0_n_0\,
      I1 => \tixVCapture_reg_n_0_[0]\,
      I2 => \tixVCapture_reg_n_0_[1]\,
      I3 => stateOp_dbg(6),
      I4 => hostifStateOp_dbg(7),
      O => \state[7]_i_1__0_n_0\
    );
\state[7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \tixVCapture_reg_n_0_[6]\,
      I1 => \tixVCapture_reg_n_0_[7]\,
      I2 => \tixVCapture_reg_n_0_[3]\,
      I3 => \tixVCapture_reg_n_0_[2]\,
      I4 => \tixVCapture_reg_n_0_[5]\,
      I5 => \tixVCapture_reg_n_0_[4]\,
      O => \state[7]_i_2__0_n_0\
    );
\state_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \state[0]_i_1__0_n_0\,
      PRE => AR(0),
      Q => state(0)
    );
\state_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \state[1]_i_1_n_0\,
      PRE => AR(0),
      Q => state(1)
    );
\state_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \state[2]_i_1_n_0\,
      PRE => AR(0),
      Q => state(2)
    );
\state_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \state[3]_i_1_n_0\,
      PRE => AR(0),
      Q => state(3)
    );
\state_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \state[4]_i_1__0_n_0\,
      PRE => AR(0),
      Q => state(4)
    );
\state_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \state[5]_i_1__0_n_0\,
      PRE => AR(0),
      Q => state(5)
    );
\state_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \state[6]_i_1__0_n_0\,
      PRE => AR(0),
      Q => state(6)
    );
\state_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \state[7]_i_1__0_n_0\,
      PRE => AR(0),
      Q => state(7)
    );
\stoTixVTrigger_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(0),
      Q => stoTixVTrigger(0)
    );
\stoTixVTrigger_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(1),
      Q => stoTixVTrigger(1)
    );
\stoTixVTrigger_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(2),
      Q => stoTixVTrigger(2)
    );
\stoTixVTrigger_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(3),
      Q => stoTixVTrigger(3)
    );
\stoTixVTrigger_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(4),
      Q => stoTixVTrigger(4)
    );
\stoTixVTrigger_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(5),
      Q => stoTixVTrigger(5)
    );
\stoTixVTrigger_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(6),
      Q => stoTixVTrigger(6)
    );
\stoTixVTrigger_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => D(7),
      Q => stoTixVTrigger(7)
    );
\stop_lcl_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAAB"
    )
        port map (
      I0 => TCapt,
      I1 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I2 => rdySeq,
      I3 => ackSeqbufBToSeqClear,
      I4 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      O => \stop_lcl_i_1__2_n_0\
    );
\stop_lcl_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \FSM_onehot_stateSeq[3]_i_2__1_n_0\,
      O => \stop_lcl_i_2__1_n_0\
    );
stop_lcl_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__2_n_0\,
      CLR => AR(0),
      D => \stop_lcl_i_2__1_n_0\,
      Q => stop_lcl_reg_n_0
    );
\strbStop5_inferred__0/i__carry\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \strbStop5_inferred__0/i__carry_n_0\,
      CO(6) => \strbStop5_inferred__0/i__carry_n_1\,
      CO(5) => \strbStop5_inferred__0/i__carry_n_2\,
      CO(4) => \strbStop5_inferred__0/i__carry_n_3\,
      CO(3) => \strbStop5_inferred__0/i__carry_n_4\,
      CO(2) => \strbStop5_inferred__0/i__carry_n_5\,
      CO(1) => \strbStop5_inferred__0/i__carry_n_6\,
      CO(0) => \strbStop5_inferred__0/i__carry_n_7\,
      DI(7) => \i__carry_i_1__6_n_0\,
      DI(6) => \i__carry_i_2__6_n_0\,
      DI(5) => \i__carry_i_3__6_n_0\,
      DI(4) => \i__carry_i_4__6_n_0\,
      DI(3) => \i__carry_i_5__6_n_0\,
      DI(2) => \i__carry_i_6__6_n_0\,
      DI(1) => \i__carry_i_7__5_n_0\,
      DI(0) => \i__carry_i_8__5_n_0\,
      O(7 downto 0) => \NLW_strbStop5_inferred__0/i__carry_O_UNCONNECTED\(7 downto 0),
      S(7) => \i__carry_i_9__5_n_0\,
      S(6) => \i__carry_i_10__5_n_0\,
      S(5) => \i__carry_i_11__4_n_0\,
      S(4) => \i__carry_i_12__2_n_0\,
      S(3) => \i__carry_i_13__1_n_0\,
      S(2) => \i__carry_i_14__0_n_0\,
      S(1) => \i__carry_i_15__0_n_0\,
      S(0) => \i__carry_i_16__0_n_0\
    );
\strbStop5_inferred__0/i__carry__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \strbStop5_inferred__0/i__carry_n_0\,
      CI_TOP => '0',
      CO(7) => \strbStop5_inferred__0/i__carry__0_n_0\,
      CO(6) => \strbStop5_inferred__0/i__carry__0_n_1\,
      CO(5) => \strbStop5_inferred__0/i__carry__0_n_2\,
      CO(4) => \strbStop5_inferred__0/i__carry__0_n_3\,
      CO(3) => \strbStop5_inferred__0/i__carry__0_n_4\,
      CO(2) => \strbStop5_inferred__0/i__carry__0_n_5\,
      CO(1) => \strbStop5_inferred__0/i__carry__0_n_6\,
      CO(0) => \strbStop5_inferred__0/i__carry__0_n_7\,
      DI(7) => \i__carry__0_i_1__0_n_0\,
      DI(6) => \i__carry__0_i_2__0_n_0\,
      DI(5) => \i__carry__0_i_3__0_n_0\,
      DI(4) => \i__carry__0_i_4__0_n_0\,
      DI(3) => \i__carry__0_i_5__0_n_0\,
      DI(2) => \i__carry__0_i_6__0_n_0\,
      DI(1) => \i__carry__0_i_7__0_n_0\,
      DI(0) => \i__carry__0_i_8__0_n_0\,
      O(7 downto 0) => \NLW_strbStop5_inferred__0/i__carry__0_O_UNCONNECTED\(7 downto 0),
      S(7) => \i__carry__0_i_9__0_n_0\,
      S(6) => \i__carry__0_i_10__0_n_0\,
      S(5) => \i__carry__0_i_11__0_n_0\,
      S(4) => \i__carry__0_i_12__0_n_0\,
      S(3) => \i__carry__0_i_13__0_n_0\,
      S(2) => \i__carry__0_i_14__0_n_0\,
      S(1) => \i__carry__0_i_15__0_n_0\,
      S(0) => \i__carry__0_i_16__0_n_0\
    );
\strbStop_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3333131300001310"
    )
        port map (
      I0 => stateOp(2),
      I1 => \strbStop_i_2__2_n_0\,
      I2 => stateOp(0),
      I3 => \stateOp[2]_i_3__4_n_0\,
      I4 => \strbStop_i_3__1_n_0\,
      I5 => strbStop_reg_n_0,
      O => \strbStop_i_1__2_n_0\
    );
\strbStop_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEE0EF"
    )
        port map (
      I0 => reqInvSelect,
      I1 => reqInvCputrackSet,
      I2 => stateOp(2),
      I3 => stateOp(0),
      I4 => stateOp(1),
      O => \strbStop_i_2__2_n_0\
    );
\strbStop_i_3__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F0FD"
    )
        port map (
      I0 => stateOp(0),
      I1 => ackInvSelect_sig_reg_0,
      I2 => stateOp(1),
      I3 => stateOp(2),
      O => \strbStop_i_3__1_n_0\
    );
strbStop_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \strbStop_i_1__2_n_0\,
      Q => strbStop_reg_n_0
    );
\tixVCapture_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      D => \tixVCapture_reg[7]_0\(0),
      PRE => AR(0),
      Q => \tixVCapture_reg_n_0_[0]\
    );
\tixVCapture_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => \tixVCapture_reg[7]_0\(1),
      Q => \tixVCapture_reg_n_0_[1]\
    );
\tixVCapture_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => \tixVCapture_reg[7]_0\(2),
      Q => \tixVCapture_reg_n_0_[2]\
    );
\tixVCapture_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => \tixVCapture_reg[7]_0\(3),
      Q => \tixVCapture_reg_n_0_[3]\
    );
\tixVCapture_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => \tixVCapture_reg[7]_0\(4),
      Q => \tixVCapture_reg_n_0_[4]\
    );
\tixVCapture_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => \tixVCapture_reg[7]_0\(5),
      Q => \tixVCapture_reg_n_0_[5]\
    );
\tixVCapture_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => \tixVCapture_reg[7]_0\(6),
      Q => \tixVCapture_reg_n_0_[6]\
    );
\tixVCapture_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => AR(0),
      D => \tixVCapture_reg[7]_0\(7),
      Q => \tixVCapture_reg_n_0_[7]\
    );
\txAXIS_tdata[15]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => stateSeqbufB_reg(2),
      I1 => stateSeqbufB_reg(0),
      I2 => stateSeqbufB_reg(1),
      O => seqbufCputrackToHostifAXIS_tvalid
    );
\wordcntLast[28]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"34"
    )
        port map (
      I0 => stateSeqbufB_reg(0),
      I1 => stateSeqbufB_reg(2),
      I2 => stateSeqbufB_reg(1),
      O => ackSeqbufCputrackToHostif
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Decim is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    ackInvDecimConfig : out STD_LOGIC;
    ackInvDecimSet : out STD_LOGIC;
    ackInvDecimUnlock : out STD_LOGIC;
    ackInvDecimAcquire : out STD_LOGIC;
    rgbNotGray_reg_0 : out STD_LOGIC;
    rng_reg_0 : out STD_LOGIC;
    S : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \stateStream_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    enAccbuf0 : out STD_LOGIC;
    \tixVState_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateStore_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    vsync_last_reg_0 : out STD_LOGIC;
    \stateStream_reg[0]_1\ : out STD_LOGIC;
    \stateStream_reg[1]_0\ : out STD_LOGIC;
    \stateStream_reg[1]_1\ : out STD_LOGIC;
    \FSM_onehot_statePvwbufB_reg[5]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ixTExp_lcl_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \tkst_reg[31]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \acc0_lcl_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ackPvwbufDecimToHostif : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    AR : in STD_LOGIC_VECTOR ( 0 to 0 );
    ackInvSet_sig : in STD_LOGIC;
    ackInvUnlock_sig_reg_0 : in STD_LOGIC;
    hdrNotFix : in STD_LOGIC;
    rng_reg_1 : in STD_LOGIC;
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 23 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
    enAccbuf_reg_0 : in STD_LOGIC;
    vsync_last_reg_1 : in STD_LOGIC;
    vsync_last_reg_2 : in STD_LOGIC;
    reqInvDecimConfig : in STD_LOGIC;
    reqInvDecimAcquire : in STD_LOGIC;
    tixVState1 : in STD_LOGIC;
    rgbVideoinToManyAXIS_tvalid : in STD_LOGIC;
    grayVideoinToManyAXIS_tvalid : in STD_LOGIC;
    enAccbuf1 : in STD_LOGIC;
    O : in STD_LOGIC_VECTOR ( 7 downto 0 );
    NRowRaw : in STD_LOGIC_VECTOR ( 10 downto 0 );
    NColRaw : in STD_LOGIC_VECTOR ( 10 downto 0 );
    reqInvDecimSet : in STD_LOGIC;
    reqInvDecimUnlock : in STD_LOGIC;
    \tixVState_reg[1]_1\ : in STD_LOGIC;
    \tixVState_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateStream_reg[0]_2\ : in STD_LOGIC;
    grayVideoinToManyAXIS_tlast : in STD_LOGIC;
    \dwrAccbuf_reg[15]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    DI : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \state_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    videoinStateRgbegr_dbg : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \state_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateOp_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \ixTExp_lcl_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \tixVState_reg[1]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \tixVState_reg[1]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \tkst_reg[31]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \decimLast_reg[8]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \acc0_lcl_reg[7]_i_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \acc2_lcl_reg[15]_i_2\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
    pvwbufDecimToHostifAXIS_tready : in STD_LOGIC;
    reqPvwbufDecimToHostif : in STD_LOGIC;
    dnePvwbufDecimToHostif : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Decim : entity is "Decim";
end design_1_Vsp_core_0_0_Decim;

architecture STRUCTURE of design_1_Vsp_core_0_0_Decim is
  signal \FSM_onehot_statePvwbufB[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_statePvwbufB[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_statePvwbufB[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_statePvwbufB[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_statePvwbufB[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_statePvwbufB[5]_i_4_n_0\ : STD_LOGIC;
  signal \^fsm_onehot_statepvwbufb_reg[5]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \FSM_onehot_statePvwbufB_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_statePvwbufB_reg_n_0_[2]\ : STD_LOGIC;
  signal \aAccbufB[0]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbufB[1]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbufB[2]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbufB[3]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbufB[4]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbufB[5]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbufB[5]_i_2_n_0\ : STD_LOGIC;
  signal \aAccbufB[6]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbufB[7]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbufB[7]_i_2_n_0\ : STD_LOGIC;
  signal \aAccbufB[7]_i_3_n_0\ : STD_LOGIC;
  signal \aAccbufB[7]_i_4_n_0\ : STD_LOGIC;
  signal \aAccbufB_reg_n_0_[0]\ : STD_LOGIC;
  signal \aAccbufB_reg_n_0_[1]\ : STD_LOGIC;
  signal \aAccbufB_reg_n_0_[2]\ : STD_LOGIC;
  signal \aAccbufB_reg_n_0_[3]\ : STD_LOGIC;
  signal \aAccbufB_reg_n_0_[4]\ : STD_LOGIC;
  signal \aAccbufB_reg_n_0_[5]\ : STD_LOGIC;
  signal \aAccbufB_reg_n_0_[6]\ : STD_LOGIC;
  signal \aAccbufB_reg_n_0_[7]\ : STD_LOGIC;
  signal \aAccbuf[0]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbuf[1]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbuf[2]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbuf[3]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbuf[4]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbuf[5]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbuf[5]_i_2_n_0\ : STD_LOGIC;
  signal \aAccbuf[6]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbuf[7]_i_1_n_0\ : STD_LOGIC;
  signal \aAccbuf[7]_i_2_n_0\ : STD_LOGIC;
  signal \aAccbuf[7]_i_3_n_0\ : STD_LOGIC;
  signal \aAccbuf[7]_i_4_n_0\ : STD_LOGIC;
  signal \aAccbuf_reg_n_0_[0]\ : STD_LOGIC;
  signal \aAccbuf_reg_n_0_[1]\ : STD_LOGIC;
  signal \aAccbuf_reg_n_0_[2]\ : STD_LOGIC;
  signal \aAccbuf_reg_n_0_[3]\ : STD_LOGIC;
  signal \aAccbuf_reg_n_0_[4]\ : STD_LOGIC;
  signal \aAccbuf_reg_n_0_[5]\ : STD_LOGIC;
  signal \aAccbuf_reg_n_0_[6]\ : STD_LOGIC;
  signal \aAccbuf_reg_n_0_[7]\ : STD_LOGIC;
  signal aPvwbuf1 : STD_LOGIC;
  signal \aPvwbufB[0]_i_1_n_0\ : STD_LOGIC;
  signal \aPvwbufB[10]_i_1_n_0\ : STD_LOGIC;
  signal \aPvwbufB[11]_i_1_n_0\ : STD_LOGIC;
  signal \aPvwbufB[12]_i_1_n_0\ : STD_LOGIC;
  signal \aPvwbufB[12]_i_2_n_0\ : STD_LOGIC;
  signal \aPvwbufB[12]_i_3_n_0\ : STD_LOGIC;
  signal \aPvwbufB[1]_i_1_n_0\ : STD_LOGIC;
  signal \aPvwbufB[2]_i_1_n_0\ : STD_LOGIC;
  signal \aPvwbufB[3]_i_1_n_0\ : STD_LOGIC;
  signal \aPvwbufB[4]_i_1_n_0\ : STD_LOGIC;
  signal \aPvwbufB[5]_i_1_n_0\ : STD_LOGIC;
  signal \aPvwbufB[5]_i_2_n_0\ : STD_LOGIC;
  signal \aPvwbufB[6]_i_1_n_0\ : STD_LOGIC;
  signal \aPvwbufB[7]_i_1_n_0\ : STD_LOGIC;
  signal \aPvwbufB[8]_i_1_n_0\ : STD_LOGIC;
  signal \aPvwbufB[9]_i_1_n_0\ : STD_LOGIC;
  signal \aPvwbufB[9]_i_2_n_0\ : STD_LOGIC;
  signal \aPvwbufB_reg_n_0_[0]\ : STD_LOGIC;
  signal \aPvwbufB_reg_n_0_[10]\ : STD_LOGIC;
  signal \aPvwbufB_reg_n_0_[11]\ : STD_LOGIC;
  signal \aPvwbufB_reg_n_0_[12]\ : STD_LOGIC;
  signal \aPvwbufB_reg_n_0_[1]\ : STD_LOGIC;
  signal \aPvwbufB_reg_n_0_[2]\ : STD_LOGIC;
  signal \aPvwbufB_reg_n_0_[3]\ : STD_LOGIC;
  signal \aPvwbufB_reg_n_0_[4]\ : STD_LOGIC;
  signal \aPvwbufB_reg_n_0_[5]\ : STD_LOGIC;
  signal \aPvwbufB_reg_n_0_[6]\ : STD_LOGIC;
  signal \aPvwbufB_reg_n_0_[7]\ : STD_LOGIC;
  signal \aPvwbufB_reg_n_0_[8]\ : STD_LOGIC;
  signal \aPvwbufB_reg_n_0_[9]\ : STD_LOGIC;
  signal \aPvwbuf[10]_i_2_n_0\ : STD_LOGIC;
  signal \aPvwbuf[14]_i_2_n_0\ : STD_LOGIC;
  signal \aPvwbuf[15]_i_1_n_0\ : STD_LOGIC;
  signal \aPvwbuf[15]_i_3_n_0\ : STD_LOGIC;
  signal \aPvwbuf[5]_i_2_n_0\ : STD_LOGIC;
  signal \aPvwbuf[9]_i_2_n_0\ : STD_LOGIC;
  signal aPvwbuf_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal acc0 : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal \acc0_lcl[19]_i_7_n_0\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[0]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[10]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[11]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[12]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[13]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[14]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[15]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[16]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[17]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[18]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[19]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[1]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[2]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[3]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[4]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[5]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[6]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[7]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[8]\ : STD_LOGIC;
  signal \acc0_lcl_reg_n_0_[9]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[0]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[10]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[11]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[12]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[13]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[14]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[15]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[16]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[17]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[18]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[19]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[1]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[2]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[3]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[4]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[5]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[6]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[7]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[8]\ : STD_LOGIC;
  signal \acc0_reg_n_0_[9]\ : STD_LOGIC;
  signal acc1 : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal \acc1_lcl_reg_n_0_[0]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[10]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[11]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[12]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[13]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[14]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[15]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[16]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[17]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[18]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[19]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[1]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[2]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[3]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[4]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[5]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[6]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[7]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[8]\ : STD_LOGIC;
  signal \acc1_lcl_reg_n_0_[9]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[0]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[10]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[11]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[12]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[13]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[14]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[15]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[16]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[17]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[18]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[19]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[1]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[2]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[3]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[4]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[5]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[6]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[7]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[8]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[9]\ : STD_LOGIC;
  signal acc2 : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[0]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[10]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[11]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[12]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[13]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[14]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[15]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[16]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[17]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[18]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[19]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[1]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[2]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[3]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[4]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[5]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[6]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[7]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[8]\ : STD_LOGIC;
  signal \acc2_lcl_reg_n_0_[9]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[0]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[10]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[11]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[12]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[13]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[14]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[15]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[16]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[17]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[18]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[19]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[1]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[2]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[3]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[4]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[5]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[6]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[7]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[8]\ : STD_LOGIC;
  signal \acc2_reg_n_0_[9]\ : STD_LOGIC;
  signal ackInvAcquire_sig : STD_LOGIC;
  signal ackInvConfig_sig : STD_LOGIC;
  signal ackInvConfig_sig_i_4_n_0 : STD_LOGIC;
  signal ackInvConfig_sig_i_5_n_0 : STD_LOGIC;
  signal \^ackinvdecimacquire\ : STD_LOGIC;
  signal \^ackinvdecimconfig\ : STD_LOGIC;
  signal \^ackinvdecimset\ : STD_LOGIC;
  signal \^ackinvdecimunlock\ : STD_LOGIC;
  signal ackInvUnlock_sig : STD_LOGIC;
  signal col : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \col2__0\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \col[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \col[10]_i_10_n_0\ : STD_LOGIC;
  signal \col[10]_i_11_n_0\ : STD_LOGIC;
  signal \col[10]_i_12_n_0\ : STD_LOGIC;
  signal \col[10]_i_13_n_0\ : STD_LOGIC;
  signal \col[10]_i_14_n_0\ : STD_LOGIC;
  signal \col[10]_i_15_n_0\ : STD_LOGIC;
  signal \col[10]_i_16_n_0\ : STD_LOGIC;
  signal \col[10]_i_17_n_0\ : STD_LOGIC;
  signal \col[10]_i_18_n_0\ : STD_LOGIC;
  signal \col[10]_i_19_n_0\ : STD_LOGIC;
  signal \col[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \col[10]_i_20_n_0\ : STD_LOGIC;
  signal \col[10]_i_2__0_n_0\ : STD_LOGIC;
  signal \col[10]_i_3__0_n_0\ : STD_LOGIC;
  signal \col[10]_i_5_n_0\ : STD_LOGIC;
  signal \col[10]_i_6_n_0\ : STD_LOGIC;
  signal \col[10]_i_7_n_0\ : STD_LOGIC;
  signal \col[10]_i_8_n_0\ : STD_LOGIC;
  signal \col[10]_i_9_n_0\ : STD_LOGIC;
  signal \col[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \col[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \col[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \col[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \col[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \col[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \col[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \col[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \col[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \col[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \col[9]_i_2__0_n_0\ : STD_LOGIC;
  signal \col_reg[10]_i_4_n_2\ : STD_LOGIC;
  signal \col_reg[10]_i_4_n_3\ : STD_LOGIC;
  signal \col_reg[10]_i_4_n_4\ : STD_LOGIC;
  signal \col_reg[10]_i_4_n_5\ : STD_LOGIC;
  signal \col_reg[10]_i_4_n_6\ : STD_LOGIC;
  signal \col_reg[10]_i_4_n_7\ : STD_LOGIC;
  signal colacc : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal colaccLast0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \colacc[0]_i_1_n_0\ : STD_LOGIC;
  signal \colacc[1]_i_1_n_0\ : STD_LOGIC;
  signal \colacc[2]_i_1_n_0\ : STD_LOGIC;
  signal \colacc[3]_i_1_n_0\ : STD_LOGIC;
  signal \colacc[3]_i_2_n_0\ : STD_LOGIC;
  signal \colacc[3]_i_3_n_0\ : STD_LOGIC;
  signal \colacc[3]_i_4_n_0\ : STD_LOGIC;
  signal \colacc[3]_i_6_n_0\ : STD_LOGIC;
  signal decim1 : STD_LOGIC_VECTOR ( 23 downto 16 );
  signal decim10_n_100 : STD_LOGIC;
  signal decim10_n_101 : STD_LOGIC;
  signal decim10_n_102 : STD_LOGIC;
  signal decim10_n_103 : STD_LOGIC;
  signal decim10_n_104 : STD_LOGIC;
  signal decim10_n_105 : STD_LOGIC;
  signal decim10_n_75 : STD_LOGIC;
  signal decim10_n_76 : STD_LOGIC;
  signal decim10_n_77 : STD_LOGIC;
  signal decim10_n_78 : STD_LOGIC;
  signal decim10_n_79 : STD_LOGIC;
  signal decim10_n_80 : STD_LOGIC;
  signal decim10_n_81 : STD_LOGIC;
  signal decim10_n_82 : STD_LOGIC;
  signal decim10_n_83 : STD_LOGIC;
  signal decim10_n_84 : STD_LOGIC;
  signal decim10_n_85 : STD_LOGIC;
  signal decim10_n_86 : STD_LOGIC;
  signal decim10_n_87 : STD_LOGIC;
  signal decim10_n_88 : STD_LOGIC;
  signal decim10_n_89 : STD_LOGIC;
  signal decim10_n_90 : STD_LOGIC;
  signal decim10_n_91 : STD_LOGIC;
  signal decim10_n_92 : STD_LOGIC;
  signal decim10_n_93 : STD_LOGIC;
  signal decim10_n_94 : STD_LOGIC;
  signal decim10_n_95 : STD_LOGIC;
  signal decim10_n_96 : STD_LOGIC;
  signal decim10_n_97 : STD_LOGIC;
  signal decim10_n_98 : STD_LOGIC;
  signal decim10_n_99 : STD_LOGIC;
  signal \decim1[16]_i_1_n_0\ : STD_LOGIC;
  signal \decim1[17]_i_1_n_0\ : STD_LOGIC;
  signal \decim1[18]_i_1_n_0\ : STD_LOGIC;
  signal \decim1[19]_i_1_n_0\ : STD_LOGIC;
  signal \decim1[20]_i_1_n_0\ : STD_LOGIC;
  signal \decim1[21]_i_1_n_0\ : STD_LOGIC;
  signal \decim1[22]_i_1_n_0\ : STD_LOGIC;
  signal \decim1[23]_i_1_n_0\ : STD_LOGIC;
  signal decim2 : STD_LOGIC;
  signal decim20_n_100 : STD_LOGIC;
  signal decim20_n_101 : STD_LOGIC;
  signal decim20_n_102 : STD_LOGIC;
  signal decim20_n_103 : STD_LOGIC;
  signal decim20_n_104 : STD_LOGIC;
  signal decim20_n_105 : STD_LOGIC;
  signal decim20_n_75 : STD_LOGIC;
  signal decim20_n_76 : STD_LOGIC;
  signal decim20_n_77 : STD_LOGIC;
  signal decim20_n_78 : STD_LOGIC;
  signal decim20_n_79 : STD_LOGIC;
  signal decim20_n_80 : STD_LOGIC;
  signal decim20_n_81 : STD_LOGIC;
  signal decim20_n_82 : STD_LOGIC;
  signal decim20_n_83 : STD_LOGIC;
  signal decim20_n_84 : STD_LOGIC;
  signal decim20_n_85 : STD_LOGIC;
  signal decim20_n_86 : STD_LOGIC;
  signal decim20_n_87 : STD_LOGIC;
  signal decim20_n_88 : STD_LOGIC;
  signal decim20_n_89 : STD_LOGIC;
  signal decim20_n_90 : STD_LOGIC;
  signal decim20_n_91 : STD_LOGIC;
  signal decim20_n_92 : STD_LOGIC;
  signal decim20_n_93 : STD_LOGIC;
  signal decim20_n_94 : STD_LOGIC;
  signal decim20_n_95 : STD_LOGIC;
  signal decim20_n_96 : STD_LOGIC;
  signal decim20_n_97 : STD_LOGIC;
  signal decim20_n_98 : STD_LOGIC;
  signal decim20_n_99 : STD_LOGIC;
  signal \decim2[16]_i_1_n_0\ : STD_LOGIC;
  signal \decim2[17]_i_1_n_0\ : STD_LOGIC;
  signal \decim2[18]_i_1_n_0\ : STD_LOGIC;
  signal \decim2[19]_i_1_n_0\ : STD_LOGIC;
  signal \decim2[20]_i_1_n_0\ : STD_LOGIC;
  signal \decim2[21]_i_1_n_0\ : STD_LOGIC;
  signal \decim2[22]_i_1_n_0\ : STD_LOGIC;
  signal \decim2[23]_i_2_n_0\ : STD_LOGIC;
  signal \decim2_reg_n_0_[16]\ : STD_LOGIC;
  signal \decim2_reg_n_0_[17]\ : STD_LOGIC;
  signal \decim2_reg_n_0_[18]\ : STD_LOGIC;
  signal \decim2_reg_n_0_[19]\ : STD_LOGIC;
  signal \decim2_reg_n_0_[20]\ : STD_LOGIC;
  signal \decim2_reg_n_0_[21]\ : STD_LOGIC;
  signal \decim2_reg_n_0_[22]\ : STD_LOGIC;
  signal \decim2_reg_n_0_[23]\ : STD_LOGIC;
  signal decimLast : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \decimLast[15]_i_2_n_0\ : STD_LOGIC;
  signal \decimLast[15]_i_3_n_0\ : STD_LOGIC;
  signal \decimLast[15]_i_4_n_0\ : STD_LOGIC;
  signal \decimLast[15]_i_5_n_0\ : STD_LOGIC;
  signal \decimLast[15]_i_6_n_0\ : STD_LOGIC;
  signal \decimLast[15]_i_7_n_0\ : STD_LOGIC;
  signal \decimLast[15]_i_8_n_0\ : STD_LOGIC;
  signal \decimLast_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \decimLast_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \decimLast_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \decimLast_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \decimLast_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \decimLast_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal decimStateStream_dbg : STD_LOGIC_VECTOR ( 5 to 5 );
  signal dwrA : STD_LOGIC_VECTOR ( 59 downto 0 );
  signal \dwrAccbuf[59]_i_1_n_0\ : STD_LOGIC;
  signal dwrPvwbuf0_n_100 : STD_LOGIC;
  signal dwrPvwbuf0_n_101 : STD_LOGIC;
  signal dwrPvwbuf0_n_102 : STD_LOGIC;
  signal dwrPvwbuf0_n_103 : STD_LOGIC;
  signal dwrPvwbuf0_n_104 : STD_LOGIC;
  signal dwrPvwbuf0_n_105 : STD_LOGIC;
  signal dwrPvwbuf0_n_75 : STD_LOGIC;
  signal dwrPvwbuf0_n_76 : STD_LOGIC;
  signal dwrPvwbuf0_n_77 : STD_LOGIC;
  signal dwrPvwbuf0_n_78 : STD_LOGIC;
  signal dwrPvwbuf0_n_79 : STD_LOGIC;
  signal dwrPvwbuf0_n_80 : STD_LOGIC;
  signal dwrPvwbuf0_n_81 : STD_LOGIC;
  signal dwrPvwbuf0_n_82 : STD_LOGIC;
  signal dwrPvwbuf0_n_83 : STD_LOGIC;
  signal dwrPvwbuf0_n_84 : STD_LOGIC;
  signal dwrPvwbuf0_n_85 : STD_LOGIC;
  signal dwrPvwbuf0_n_86 : STD_LOGIC;
  signal dwrPvwbuf0_n_87 : STD_LOGIC;
  signal dwrPvwbuf0_n_88 : STD_LOGIC;
  signal dwrPvwbuf0_n_89 : STD_LOGIC;
  signal dwrPvwbuf0_n_90 : STD_LOGIC;
  signal dwrPvwbuf0_n_91 : STD_LOGIC;
  signal dwrPvwbuf0_n_92 : STD_LOGIC;
  signal dwrPvwbuf0_n_93 : STD_LOGIC;
  signal dwrPvwbuf0_n_94 : STD_LOGIC;
  signal dwrPvwbuf0_n_95 : STD_LOGIC;
  signal dwrPvwbuf0_n_96 : STD_LOGIC;
  signal dwrPvwbuf0_n_97 : STD_LOGIC;
  signal dwrPvwbuf0_n_98 : STD_LOGIC;
  signal dwrPvwbuf0_n_99 : STD_LOGIC;
  signal \dwrPvwbuf[7]_i_2_n_0\ : STD_LOGIC;
  signal \dwrPvwbuf_reg_n_0_[0]\ : STD_LOGIC;
  signal \dwrPvwbuf_reg_n_0_[1]\ : STD_LOGIC;
  signal \dwrPvwbuf_reg_n_0_[2]\ : STD_LOGIC;
  signal \dwrPvwbuf_reg_n_0_[3]\ : STD_LOGIC;
  signal \dwrPvwbuf_reg_n_0_[4]\ : STD_LOGIC;
  signal \dwrPvwbuf_reg_n_0_[5]\ : STD_LOGIC;
  signal \dwrPvwbuf_reg_n_0_[6]\ : STD_LOGIC;
  signal \dwrPvwbuf_reg_n_0_[7]\ : STD_LOGIC;
  signal edge2 : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \edge_reg_n_0_[0]\ : STD_LOGIC;
  signal \edge_reg_n_0_[1]\ : STD_LOGIC;
  signal \edge_reg_n_0_[2]\ : STD_LOGIC;
  signal \edge_reg_n_0_[3]\ : STD_LOGIC;
  signal \edge_reg_n_0_[4]\ : STD_LOGIC;
  signal \^enaccbuf0\ : STD_LOGIC;
  signal enAccbuf11_out : STD_LOGIC;
  signal enAccbuf_i_1_n_0 : STD_LOGIC;
  signal enAccbuf_i_3_n_0 : STD_LOGIC;
  signal enAccbuf_reg_n_0 : STD_LOGIC;
  signal enPvwbufB : STD_LOGIC;
  signal \i[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \i[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \i[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \i_reg_n_0_[0]\ : STD_LOGIC;
  signal \i_reg_n_0_[1]\ : STD_LOGIC;
  signal \ixTExp_lcl_reg_n_0_[2]\ : STD_LOGIC;
  signal \ixTExp_lcl_reg_n_0_[3]\ : STD_LOGIC;
  signal minusOp : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal myAccbuf_n_0 : STD_LOGIC;
  signal myAccbuf_n_1 : STD_LOGIC;
  signal myAccbuf_n_10 : STD_LOGIC;
  signal myAccbuf_n_11 : STD_LOGIC;
  signal myAccbuf_n_12 : STD_LOGIC;
  signal myAccbuf_n_13 : STD_LOGIC;
  signal myAccbuf_n_14 : STD_LOGIC;
  signal myAccbuf_n_15 : STD_LOGIC;
  signal myAccbuf_n_16 : STD_LOGIC;
  signal myAccbuf_n_17 : STD_LOGIC;
  signal myAccbuf_n_18 : STD_LOGIC;
  signal myAccbuf_n_19 : STD_LOGIC;
  signal myAccbuf_n_2 : STD_LOGIC;
  signal myAccbuf_n_3 : STD_LOGIC;
  signal myAccbuf_n_4 : STD_LOGIC;
  signal myAccbuf_n_5 : STD_LOGIC;
  signal myAccbuf_n_6 : STD_LOGIC;
  signal myAccbuf_n_7 : STD_LOGIC;
  signal myAccbuf_n_8 : STD_LOGIC;
  signal myAccbuf_n_9 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^rgbnotgray_reg_0\ : STD_LOGIC;
  signal \^rng_reg_0\ : STD_LOGIC;
  signal row : STD_LOGIC;
  signal \row2__0\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \row[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \row[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \row[10]_i_2_n_0\ : STD_LOGIC;
  signal \row[10]_i_3_n_0\ : STD_LOGIC;
  signal \row[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \row[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \row[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \row[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \row[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \row[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \row[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \row[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \row[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \row[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \row[9]_i_2__0_n_0\ : STD_LOGIC;
  signal \row_reg_n_0_[0]\ : STD_LOGIC;
  signal \row_reg_n_0_[10]\ : STD_LOGIC;
  signal \row_reg_n_0_[1]\ : STD_LOGIC;
  signal \row_reg_n_0_[2]\ : STD_LOGIC;
  signal \row_reg_n_0_[3]\ : STD_LOGIC;
  signal \row_reg_n_0_[4]\ : STD_LOGIC;
  signal \row_reg_n_0_[5]\ : STD_LOGIC;
  signal \row_reg_n_0_[6]\ : STD_LOGIC;
  signal \row_reg_n_0_[7]\ : STD_LOGIC;
  signal \row_reg_n_0_[8]\ : STD_LOGIC;
  signal \row_reg_n_0_[9]\ : STD_LOGIC;
  signal rowacc : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rowaccLast : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rowacc[0]_i_1_n_0\ : STD_LOGIC;
  signal \rowacc[1]_i_1_n_0\ : STD_LOGIC;
  signal \rowacc[2]_i_1_n_0\ : STD_LOGIC;
  signal \rowacc[3]_i_2_n_0\ : STD_LOGIC;
  signal \rowacc[3]_i_3_n_0\ : STD_LOGIC;
  signal \^stateop_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \stateStore[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateStore[0]_i_2_n_0\ : STD_LOGIC;
  signal \stateStore[1]_i_10_n_0\ : STD_LOGIC;
  signal \stateStore[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateStore[1]_i_2_n_0\ : STD_LOGIC;
  signal \stateStore[1]_i_3_n_0\ : STD_LOGIC;
  signal \stateStore[1]_i_4_n_0\ : STD_LOGIC;
  signal \stateStore[1]_i_5_n_0\ : STD_LOGIC;
  signal \stateStore[1]_i_6_n_0\ : STD_LOGIC;
  signal \stateStore[1]_i_7_n_0\ : STD_LOGIC;
  signal \stateStore[1]_i_8_n_0\ : STD_LOGIC;
  signal \stateStore[1]_i_9_n_0\ : STD_LOGIC;
  signal \^statestore_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal stateStream : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \stateStream[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateStream[0]_i_2_n_0\ : STD_LOGIC;
  signal \stateStream[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateStream[1]_i_2_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_10_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_11_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_12_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_13_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_14_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_15_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_16_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_17_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_18_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_19_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_1_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_20_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_21_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_22_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_2_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_3_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_4_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_6_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_7_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_8_n_0\ : STD_LOGIC;
  signal \stateStream[2]_i_9_n_0\ : STD_LOGIC;
  signal \stateStream_reg[2]_i_5_n_2\ : STD_LOGIC;
  signal \stateStream_reg[2]_i_5_n_3\ : STD_LOGIC;
  signal \stateStream_reg[2]_i_5_n_4\ : STD_LOGIC;
  signal \stateStream_reg[2]_i_5_n_5\ : STD_LOGIC;
  signal \stateStream_reg[2]_i_5_n_6\ : STD_LOGIC;
  signal \stateStream_reg[2]_i_5_n_7\ : STD_LOGIC;
  signal strbStore5_out : STD_LOGIC;
  signal strbStore_i_1_n_0 : STD_LOGIC;
  signal strbStore_reg_n_0 : STD_LOGIC;
  signal \tixVState[1]_i_5_n_0\ : STD_LOGIC;
  signal \^tixvstate_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal tkst : STD_LOGIC;
  signal \vsync_last_i_1__0_n_0\ : STD_LOGIC;
  signal vsync_last_reg_n_0 : STD_LOGIC;
  signal \NLW_col_reg[10]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_col_reg[10]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_decim10_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_decim10_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_decim10_OVERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_decim10_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_decim10_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_decim10_UNDERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_decim10_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_decim10_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_decim10_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_decim10_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 31 );
  signal NLW_decim10_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal NLW_decim10_XOROUT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_decim20_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_decim20_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_decim20_OVERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_decim20_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_decim20_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_decim20_UNDERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_decim20_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_decim20_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_decim20_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_decim20_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 31 );
  signal NLW_decim20_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal NLW_decim20_XOROUT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_decimLast_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_decimLast_reg[15]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal NLW_dwrPvwbuf0_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_dwrPvwbuf0_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_dwrPvwbuf0_OVERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_dwrPvwbuf0_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_dwrPvwbuf0_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
  signal NLW_dwrPvwbuf0_UNDERFLOW_UNCONNECTED : STD_LOGIC;
  signal NLW_dwrPvwbuf0_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_dwrPvwbuf0_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_dwrPvwbuf0_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_dwrPvwbuf0_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 31 );
  signal NLW_dwrPvwbuf0_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal NLW_dwrPvwbuf0_XOROUT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateStream_reg[2]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_stateStream_reg[2]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_statePvwbufB[2]_i_1\ : label is "soft_lutpair1663";
  attribute SOFT_HLUTNM of \FSM_onehot_statePvwbufB[3]_i_1\ : label is "soft_lutpair1663";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_statePvwbufB_reg[0]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_statePvwbufB_reg[1]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_statePvwbufB_reg[2]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_statePvwbufB_reg[3]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_statePvwbufB_reg[5]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute SOFT_HLUTNM of \aAccbufB[0]_i_1\ : label is "soft_lutpair1632";
  attribute SOFT_HLUTNM of \aAccbufB[2]_i_1\ : label is "soft_lutpair1633";
  attribute SOFT_HLUTNM of \aAccbufB[3]_i_1\ : label is "soft_lutpair1633";
  attribute SOFT_HLUTNM of \aAccbufB[7]_i_3\ : label is "soft_lutpair1661";
  attribute SOFT_HLUTNM of \aAccbuf[0]_i_1\ : label is "soft_lutpair1634";
  attribute SOFT_HLUTNM of \aAccbuf[2]_i_1\ : label is "soft_lutpair1635";
  attribute SOFT_HLUTNM of \aAccbuf[3]_i_1\ : label is "soft_lutpair1635";
  attribute SOFT_HLUTNM of \aAccbuf[7]_i_4\ : label is "soft_lutpair1632";
  attribute SOFT_HLUTNM of \aPvwbufB[10]_i_1\ : label is "soft_lutpair1630";
  attribute SOFT_HLUTNM of \aPvwbufB[11]_i_1\ : label is "soft_lutpair1630";
  attribute SOFT_HLUTNM of \aPvwbufB[12]_i_3\ : label is "soft_lutpair1664";
  attribute SOFT_HLUTNM of \aPvwbufB[1]_i_1\ : label is "soft_lutpair1665";
  attribute SOFT_HLUTNM of \aPvwbufB[2]_i_1\ : label is "soft_lutpair1628";
  attribute SOFT_HLUTNM of \aPvwbufB[3]_i_1\ : label is "soft_lutpair1628";
  attribute SOFT_HLUTNM of \aPvwbufB[5]_i_1\ : label is "soft_lutpair1665";
  attribute SOFT_HLUTNM of \aPvwbufB[6]_i_1\ : label is "soft_lutpair1664";
  attribute SOFT_HLUTNM of \aPvwbufB[7]_i_1\ : label is "soft_lutpair1629";
  attribute SOFT_HLUTNM of \aPvwbufB[8]_i_1\ : label is "soft_lutpair1629";
  attribute SOFT_HLUTNM of \aPvwbuf[0]_i_1\ : label is "soft_lutpair1649";
  attribute SOFT_HLUTNM of \aPvwbuf[13]_i_1\ : label is "soft_lutpair1648";
  attribute SOFT_HLUTNM of \aPvwbuf[15]_i_3\ : label is "soft_lutpair1648";
  attribute SOFT_HLUTNM of \aPvwbuf[1]_i_1\ : label is "soft_lutpair1649";
  attribute SOFT_HLUTNM of \aPvwbuf[5]_i_1\ : label is "soft_lutpair1647";
  attribute SOFT_HLUTNM of \acc0_lcl[0]_i_1\ : label is "soft_lutpair1638";
  attribute SOFT_HLUTNM of \acc0_lcl[1]_i_1\ : label is "soft_lutpair1639";
  attribute SOFT_HLUTNM of \acc0_lcl[2]_i_1\ : label is "soft_lutpair1640";
  attribute SOFT_HLUTNM of \acc0_lcl[3]_i_1\ : label is "soft_lutpair1641";
  attribute SOFT_HLUTNM of \ackInvAcquire_sig_i_1__0\ : label is "soft_lutpair1631";
  attribute SOFT_HLUTNM of ackInvConfig_sig_i_5 : label is "soft_lutpair1631";
  attribute SOFT_HLUTNM of \col[0]_i_1__0\ : label is "soft_lutpair1666";
  attribute SOFT_HLUTNM of \col[10]_i_19\ : label is "soft_lutpair1668";
  attribute SOFT_HLUTNM of \col[1]_i_1__0\ : label is "soft_lutpair1666";
  attribute SOFT_HLUTNM of \col[2]_i_1__0\ : label is "soft_lutpair1636";
  attribute SOFT_HLUTNM of \col[3]_i_1__0\ : label is "soft_lutpair1636";
  attribute SOFT_HLUTNM of \col[7]_i_1__0\ : label is "soft_lutpair1637";
  attribute SOFT_HLUTNM of \col[8]_i_1__0\ : label is "soft_lutpair1637";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of \col_reg[10]_i_4\ : label is 11;
  attribute SOFT_HLUTNM of \colaccLast[0]_i_1\ : label is "soft_lutpair1669";
  attribute SOFT_HLUTNM of \colaccLast[1]_i_1\ : label is "soft_lutpair1660";
  attribute SOFT_HLUTNM of \colaccLast[2]_i_1\ : label is "soft_lutpair1669";
  attribute SOFT_HLUTNM of \colaccLast[3]_i_2\ : label is "soft_lutpair1660";
  attribute SOFT_HLUTNM of \colaccLast[3]_i_3\ : label is "soft_lutpair1634";
  attribute SOFT_HLUTNM of \colacc[0]_i_1\ : label is "soft_lutpair1651";
  attribute SOFT_HLUTNM of \colacc[1]_i_1\ : label is "soft_lutpair1661";
  attribute SOFT_HLUTNM of \colacc[2]_i_1\ : label is "soft_lutpair1644";
  attribute SOFT_HLUTNM of \colacc[3]_i_2\ : label is "soft_lutpair1644";
  attribute SOFT_HLUTNM of \colacc[3]_i_3\ : label is "soft_lutpair1638";
  attribute SOFT_HLUTNM of \colacc[3]_i_6\ : label is "soft_lutpair1651";
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of decim10 : label is "yes";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of decim10 : label is "{SYNTH-13 {cell *THIS*}}";
  attribute SOFT_HLUTNM of \decim1[16]_i_1\ : label is "soft_lutpair1652";
  attribute SOFT_HLUTNM of \decim1[17]_i_1\ : label is "soft_lutpair1652";
  attribute SOFT_HLUTNM of \decim1[18]_i_1\ : label is "soft_lutpair1653";
  attribute SOFT_HLUTNM of \decim1[19]_i_1\ : label is "soft_lutpair1653";
  attribute SOFT_HLUTNM of \decim1[20]_i_1\ : label is "soft_lutpair1654";
  attribute SOFT_HLUTNM of \decim1[21]_i_1\ : label is "soft_lutpair1654";
  attribute SOFT_HLUTNM of \decim1[22]_i_1\ : label is "soft_lutpair1655";
  attribute SOFT_HLUTNM of \decim1[23]_i_1\ : label is "soft_lutpair1655";
  attribute KEEP_HIERARCHY of decim20 : label is "yes";
  attribute METHODOLOGY_DRC_VIOS of decim20 : label is "{SYNTH-13 {cell *THIS*}}";
  attribute SOFT_HLUTNM of \decim2[16]_i_1\ : label is "soft_lutpair1656";
  attribute SOFT_HLUTNM of \decim2[17]_i_1\ : label is "soft_lutpair1656";
  attribute SOFT_HLUTNM of \decim2[18]_i_1\ : label is "soft_lutpair1657";
  attribute SOFT_HLUTNM of \decim2[19]_i_1\ : label is "soft_lutpair1657";
  attribute SOFT_HLUTNM of \decim2[20]_i_1\ : label is "soft_lutpair1658";
  attribute SOFT_HLUTNM of \decim2[21]_i_1\ : label is "soft_lutpair1658";
  attribute SOFT_HLUTNM of \decim2[22]_i_1\ : label is "soft_lutpair1659";
  attribute SOFT_HLUTNM of \decim2[23]_i_2\ : label is "soft_lutpair1659";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \decimLast_reg[15]_i_1\ : label is 35;
  attribute KEEP_HIERARCHY of dwrPvwbuf0 : label is "yes";
  attribute METHODOLOGY_DRC_VIOS of dwrPvwbuf0 : label is "{SYNTH-13 {cell *THIS*}}";
  attribute SOFT_HLUTNM of \dwrPvwbuf[7]_i_2\ : label is "soft_lutpair1647";
  attribute SOFT_HLUTNM of \dwrPvwbuf[7]_i_3\ : label is "soft_lutpair1646";
  attribute SOFT_HLUTNM of enAccbuf_i_2 : label is "soft_lutpair1640";
  attribute SOFT_HLUTNM of \i[0]_i_1__4\ : label is "soft_lutpair1662";
  attribute SOFT_HLUTNM of \i[1]_i_2__1\ : label is "soft_lutpair1662";
  attribute SOFT_HLUTNM of \row[0]_i_1__0\ : label is "soft_lutpair1667";
  attribute SOFT_HLUTNM of \row[1]_i_1__0\ : label is "soft_lutpair1667";
  attribute SOFT_HLUTNM of \row[2]_i_1__0\ : label is "soft_lutpair1642";
  attribute SOFT_HLUTNM of \row[3]_i_1__0\ : label is "soft_lutpair1642";
  attribute SOFT_HLUTNM of \row[7]_i_1__0\ : label is "soft_lutpair1643";
  attribute SOFT_HLUTNM of \row[8]_i_1__0\ : label is "soft_lutpair1643";
  attribute SOFT_HLUTNM of \rowacc[0]_i_1\ : label is "soft_lutpair1650";
  attribute SOFT_HLUTNM of \rowacc[2]_i_1\ : label is "soft_lutpair1645";
  attribute SOFT_HLUTNM of \rowacc[3]_i_2\ : label is "soft_lutpair1645";
  attribute SOFT_HLUTNM of \stateStore[0]_i_1\ : label is "soft_lutpair1646";
  attribute SOFT_HLUTNM of \stateStream[0]_i_2\ : label is "soft_lutpair1641";
  attribute SOFT_HLUTNM of \stateStream[2]_i_21\ : label is "soft_lutpair1668";
  attribute SOFT_HLUTNM of \stateStream[2]_i_6\ : label is "soft_lutpair1650";
  attribute COMPARATOR_THRESHOLD of \stateStream_reg[2]_i_5\ : label is 11;
  attribute SOFT_HLUTNM of \state[7]_i_2\ : label is "soft_lutpair1639";
begin
  \FSM_onehot_statePvwbufB_reg[5]_0\(1 downto 0) <= \^fsm_onehot_statepvwbufb_reg[5]_0\(1 downto 0);
  ackInvDecimAcquire <= \^ackinvdecimacquire\;
  ackInvDecimConfig <= \^ackinvdecimconfig\;
  ackInvDecimSet <= \^ackinvdecimset\;
  ackInvDecimUnlock <= \^ackinvdecimunlock\;
  enAccbuf0 <= \^enaccbuf0\;
  rgbNotGray_reg_0 <= \^rgbnotgray_reg_0\;
  rng_reg_0 <= \^rng_reg_0\;
  \stateOp_reg[1]_0\(1 downto 0) <= \^stateop_reg[1]_0\(1 downto 0);
  \stateStore_reg[1]_0\(1 downto 0) <= \^statestore_reg[1]_0\(1 downto 0);
  \tixVState_reg[1]_0\(1 downto 0) <= \^tixvstate_reg[1]_0\(1 downto 0);
\FSM_onehot_statePvwbufB[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000100010001FF01"
    )
        port map (
      I0 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      I1 => enPvwbufB,
      I2 => \^fsm_onehot_statepvwbufb_reg[5]_0\(1),
      I3 => \^fsm_onehot_statepvwbufb_reg[5]_0\(0),
      I4 => reqPvwbufDecimToHostif,
      I5 => pvwbufDecimToHostifAXIS_tready,
      O => \FSM_onehot_statePvwbufB[0]_i_1_n_0\
    );
\FSM_onehot_statePvwbufB[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => pvwbufDecimToHostifAXIS_tready,
      I1 => \^fsm_onehot_statepvwbufb_reg[5]_0\(0),
      I2 => \FSM_onehot_statePvwbufB[3]_i_2_n_0\,
      O => \FSM_onehot_statePvwbufB[2]_i_1_n_0\
    );
\FSM_onehot_statePvwbufB[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF80"
    )
        port map (
      I0 => \^fsm_onehot_statepvwbufb_reg[5]_0\(0),
      I1 => pvwbufDecimToHostifAXIS_tready,
      I2 => \FSM_onehot_statePvwbufB[3]_i_2_n_0\,
      I3 => \^fsm_onehot_statepvwbufb_reg[5]_0\(1),
      O => \FSM_onehot_statePvwbufB[3]_i_1_n_0\
    );
\FSM_onehot_statePvwbufB[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[11]\,
      I1 => \aPvwbufB_reg_n_0_[12]\,
      I2 => \aPvwbufB_reg_n_0_[8]\,
      I3 => \aPvwbufB_reg_n_0_[10]\,
      I4 => \aPvwbufB[12]_i_3_n_0\,
      O => \FSM_onehot_statePvwbufB[3]_i_2_n_0\
    );
\FSM_onehot_statePvwbufB[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => reqPvwbufDecimToHostif,
      I1 => \^fsm_onehot_statepvwbufb_reg[5]_0\(1),
      I2 => pvwbufDecimToHostifAXIS_tready,
      I3 => \^fsm_onehot_statepvwbufb_reg[5]_0\(0),
      I4 => \FSM_onehot_statePvwbufB[5]_i_4_n_0\,
      I5 => enPvwbufB,
      O => \FSM_onehot_statePvwbufB[5]_i_1_n_0\
    );
\FSM_onehot_statePvwbufB[5]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8F8F8F88"
    )
        port map (
      I0 => \FSM_onehot_statePvwbufB_reg_n_0_[2]\,
      I1 => dnePvwbufDecimToHostif,
      I2 => reqPvwbufDecimToHostif,
      I3 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      I4 => \^fsm_onehot_statepvwbufb_reg[5]_0\(0),
      O => \FSM_onehot_statePvwbufB[5]_i_4_n_0\
    );
\FSM_onehot_statePvwbufB_reg[0]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_statePvwbufB[5]_i_1_n_0\,
      D => \FSM_onehot_statePvwbufB[0]_i_1_n_0\,
      PRE => AR(0),
      Q => \FSM_onehot_statePvwbufB_reg_n_0_[0]\
    );
\FSM_onehot_statePvwbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_statePvwbufB[5]_i_1_n_0\,
      CLR => AR(0),
      D => enPvwbufB,
      Q => \^fsm_onehot_statepvwbufb_reg[5]_0\(0)
    );
\FSM_onehot_statePvwbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_statePvwbufB[5]_i_1_n_0\,
      CLR => AR(0),
      D => \FSM_onehot_statePvwbufB[2]_i_1_n_0\,
      Q => \FSM_onehot_statePvwbufB_reg_n_0_[2]\
    );
\FSM_onehot_statePvwbufB_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_statePvwbufB[5]_i_1_n_0\,
      CLR => AR(0),
      D => \FSM_onehot_statePvwbufB[3]_i_1_n_0\,
      Q => enPvwbufB
    );
\FSM_onehot_statePvwbufB_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_statePvwbufB[5]_i_1_n_0\,
      CLR => AR(0),
      D => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      Q => \^fsm_onehot_statepvwbufb_reg[5]_0\(1)
    );
\aAccbufB[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => stateStream(1),
      I1 => stateStream(2),
      I2 => \^rng_reg_0\,
      I3 => stateStream(0),
      I4 => \aAccbufB_reg_n_0_[0]\,
      O => \aAccbufB[0]_i_1_n_0\
    );
\aAccbufB[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800080000"
    )
        port map (
      I0 => stateStream(0),
      I1 => \^rng_reg_0\,
      I2 => stateStream(2),
      I3 => stateStream(1),
      I4 => \aAccbufB_reg_n_0_[0]\,
      I5 => \aAccbufB_reg_n_0_[1]\,
      O => \aAccbufB[1]_i_1_n_0\
    );
\aAccbufB[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \aAccbuf[7]_i_4_n_0\,
      I1 => \aAccbufB_reg_n_0_[0]\,
      I2 => \aAccbufB_reg_n_0_[1]\,
      I3 => \aAccbufB_reg_n_0_[2]\,
      O => \aAccbufB[2]_i_1_n_0\
    );
\aAccbufB[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \aAccbuf[7]_i_4_n_0\,
      I1 => \aAccbufB_reg_n_0_[1]\,
      I2 => \aAccbufB_reg_n_0_[0]\,
      I3 => \aAccbufB_reg_n_0_[2]\,
      I4 => \aAccbufB_reg_n_0_[3]\,
      O => \aAccbufB[3]_i_1_n_0\
    );
\aAccbufB[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \aAccbuf[7]_i_4_n_0\,
      I1 => \aAccbufB_reg_n_0_[2]\,
      I2 => \aAccbufB_reg_n_0_[0]\,
      I3 => \aAccbufB_reg_n_0_[1]\,
      I4 => \aAccbufB_reg_n_0_[3]\,
      I5 => \aAccbufB_reg_n_0_[4]\,
      O => \aAccbufB[4]_i_1_n_0\
    );
\aAccbufB[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000002000000"
    )
        port map (
      I0 => \aAccbufB[5]_i_2_n_0\,
      I1 => stateStream(1),
      I2 => stateStream(2),
      I3 => \^rng_reg_0\,
      I4 => stateStream(0),
      I5 => \aAccbufB_reg_n_0_[5]\,
      O => \aAccbufB[5]_i_1_n_0\
    );
\aAccbufB[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aAccbufB_reg_n_0_[4]\,
      I1 => \aAccbufB_reg_n_0_[2]\,
      I2 => \aAccbufB_reg_n_0_[0]\,
      I3 => \aAccbufB_reg_n_0_[1]\,
      I4 => \aAccbufB_reg_n_0_[3]\,
      O => \aAccbufB[5]_i_2_n_0\
    );
\aAccbufB[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000001000000"
    )
        port map (
      I0 => \aAccbufB[7]_i_4_n_0\,
      I1 => stateStream(1),
      I2 => stateStream(2),
      I3 => \^rng_reg_0\,
      I4 => stateStream(0),
      I5 => \aAccbufB_reg_n_0_[6]\,
      O => \aAccbufB[6]_i_1_n_0\
    );
\aAccbufB[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF44400040"
    )
        port map (
      I0 => \colacc[3]_i_3_n_0\,
      I1 => \aAccbufB[7]_i_3_n_0\,
      I2 => grayVideoinToManyAXIS_tvalid,
      I3 => \^rgbnotgray_reg_0\,
      I4 => rgbVideoinToManyAXIS_tvalid,
      I5 => row,
      O => \aAccbufB[7]_i_1_n_0\
    );
\aAccbufB[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B040"
    )
        port map (
      I0 => \aAccbufB[7]_i_4_n_0\,
      I1 => \aAccbufB_reg_n_0_[6]\,
      I2 => \aAccbuf[7]_i_4_n_0\,
      I3 => \aAccbufB_reg_n_0_[7]\,
      O => \aAccbufB[7]_i_2_n_0\
    );
\aAccbufB[7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => colacc(1),
      I1 => colacc(0),
      I2 => colacc(3),
      I3 => colacc(2),
      O => \aAccbufB[7]_i_3_n_0\
    );
\aAccbufB[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \aAccbufB_reg_n_0_[5]\,
      I1 => \aAccbufB_reg_n_0_[3]\,
      I2 => \aAccbufB_reg_n_0_[1]\,
      I3 => \aAccbufB_reg_n_0_[0]\,
      I4 => \aAccbufB_reg_n_0_[2]\,
      I5 => \aAccbufB_reg_n_0_[4]\,
      O => \aAccbufB[7]_i_4_n_0\
    );
\aAccbufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbufB[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbufB[0]_i_1_n_0\,
      Q => \aAccbufB_reg_n_0_[0]\
    );
\aAccbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbufB[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbufB[1]_i_1_n_0\,
      Q => \aAccbufB_reg_n_0_[1]\
    );
\aAccbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbufB[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbufB[2]_i_1_n_0\,
      Q => \aAccbufB_reg_n_0_[2]\
    );
\aAccbufB_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbufB[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbufB[3]_i_1_n_0\,
      Q => \aAccbufB_reg_n_0_[3]\
    );
\aAccbufB_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbufB[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbufB[4]_i_1_n_0\,
      Q => \aAccbufB_reg_n_0_[4]\
    );
\aAccbufB_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbufB[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbufB[5]_i_1_n_0\,
      Q => \aAccbufB_reg_n_0_[5]\
    );
\aAccbufB_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbufB[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbufB[6]_i_1_n_0\,
      Q => \aAccbufB_reg_n_0_[6]\
    );
\aAccbufB_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbufB[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbufB[7]_i_2_n_0\,
      Q => \aAccbufB_reg_n_0_[7]\
    );
\aAccbuf[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => stateStream(1),
      I1 => stateStream(2),
      I2 => \^rng_reg_0\,
      I3 => stateStream(0),
      I4 => \aAccbuf_reg_n_0_[0]\,
      O => \aAccbuf[0]_i_1_n_0\
    );
\aAccbuf[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800080000"
    )
        port map (
      I0 => stateStream(0),
      I1 => \^rng_reg_0\,
      I2 => stateStream(2),
      I3 => stateStream(1),
      I4 => \aAccbuf_reg_n_0_[0]\,
      I5 => \aAccbuf_reg_n_0_[1]\,
      O => \aAccbuf[1]_i_1_n_0\
    );
\aAccbuf[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \aAccbuf[7]_i_4_n_0\,
      I1 => \aAccbuf_reg_n_0_[0]\,
      I2 => \aAccbuf_reg_n_0_[1]\,
      I3 => \aAccbuf_reg_n_0_[2]\,
      O => \aAccbuf[2]_i_1_n_0\
    );
\aAccbuf[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \aAccbuf[7]_i_4_n_0\,
      I1 => \aAccbuf_reg_n_0_[1]\,
      I2 => \aAccbuf_reg_n_0_[0]\,
      I3 => \aAccbuf_reg_n_0_[2]\,
      I4 => \aAccbuf_reg_n_0_[3]\,
      O => \aAccbuf[3]_i_1_n_0\
    );
\aAccbuf[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \aAccbuf[7]_i_4_n_0\,
      I1 => \aAccbuf_reg_n_0_[2]\,
      I2 => \aAccbuf_reg_n_0_[0]\,
      I3 => \aAccbuf_reg_n_0_[1]\,
      I4 => \aAccbuf_reg_n_0_[3]\,
      I5 => \aAccbuf_reg_n_0_[4]\,
      O => \aAccbuf[4]_i_1_n_0\
    );
\aAccbuf[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000002000000"
    )
        port map (
      I0 => \aAccbuf[5]_i_2_n_0\,
      I1 => stateStream(1),
      I2 => stateStream(2),
      I3 => \^rng_reg_0\,
      I4 => stateStream(0),
      I5 => \aAccbuf_reg_n_0_[5]\,
      O => \aAccbuf[5]_i_1_n_0\
    );
\aAccbuf[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aAccbuf_reg_n_0_[4]\,
      I1 => \aAccbuf_reg_n_0_[2]\,
      I2 => \aAccbuf_reg_n_0_[0]\,
      I3 => \aAccbuf_reg_n_0_[1]\,
      I4 => \aAccbuf_reg_n_0_[3]\,
      O => \aAccbuf[5]_i_2_n_0\
    );
\aAccbuf[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000001000000"
    )
        port map (
      I0 => \aAccbuf[7]_i_3_n_0\,
      I1 => stateStream(1),
      I2 => stateStream(2),
      I3 => \^rng_reg_0\,
      I4 => stateStream(0),
      I5 => \aAccbuf_reg_n_0_[6]\,
      O => \aAccbuf[6]_i_1_n_0\
    );
\aAccbuf[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"003BFFFF"
    )
        port map (
      I0 => enAccbuf_reg_n_0,
      I1 => stateStream(0),
      I2 => stateStream(1),
      I3 => stateStream(2),
      I4 => \^rng_reg_0\,
      O => \aAccbuf[7]_i_1_n_0\
    );
\aAccbuf[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B040"
    )
        port map (
      I0 => \aAccbuf[7]_i_3_n_0\,
      I1 => \aAccbuf_reg_n_0_[6]\,
      I2 => \aAccbuf[7]_i_4_n_0\,
      I3 => \aAccbuf_reg_n_0_[7]\,
      O => \aAccbuf[7]_i_2_n_0\
    );
\aAccbuf[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \aAccbuf_reg_n_0_[5]\,
      I1 => \aAccbuf_reg_n_0_[3]\,
      I2 => \aAccbuf_reg_n_0_[1]\,
      I3 => \aAccbuf_reg_n_0_[0]\,
      I4 => \aAccbuf_reg_n_0_[2]\,
      I5 => \aAccbuf_reg_n_0_[4]\,
      O => \aAccbuf[7]_i_3_n_0\
    );
\aAccbuf[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => stateStream(0),
      I1 => \^rng_reg_0\,
      I2 => stateStream(2),
      I3 => stateStream(1),
      O => \aAccbuf[7]_i_4_n_0\
    );
\aAccbuf_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbuf[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbuf[0]_i_1_n_0\,
      Q => \aAccbuf_reg_n_0_[0]\
    );
\aAccbuf_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbuf[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbuf[1]_i_1_n_0\,
      Q => \aAccbuf_reg_n_0_[1]\
    );
\aAccbuf_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbuf[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbuf[2]_i_1_n_0\,
      Q => \aAccbuf_reg_n_0_[2]\
    );
\aAccbuf_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbuf[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbuf[3]_i_1_n_0\,
      Q => \aAccbuf_reg_n_0_[3]\
    );
\aAccbuf_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbuf[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbuf[4]_i_1_n_0\,
      Q => \aAccbuf_reg_n_0_[4]\
    );
\aAccbuf_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbuf[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbuf[5]_i_1_n_0\,
      Q => \aAccbuf_reg_n_0_[5]\
    );
\aAccbuf_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbuf[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbuf[6]_i_1_n_0\,
      Q => \aAccbuf_reg_n_0_[6]\
    );
\aAccbuf_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aAccbuf[7]_i_1_n_0\,
      CLR => AR(0),
      D => \aAccbuf[7]_i_2_n_0\,
      Q => \aAccbuf_reg_n_0_[7]\
    );
\aPvwbufB[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[0]\,
      I1 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      O => \aPvwbufB[0]_i_1_n_0\
    );
\aPvwbufB[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A6"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[10]\,
      I1 => \aPvwbufB_reg_n_0_[8]\,
      I2 => \aPvwbufB[12]_i_3_n_0\,
      I3 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      O => \aPvwbufB[10]_i_1_n_0\
    );
\aPvwbufB[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA6A"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[11]\,
      I1 => \aPvwbufB_reg_n_0_[10]\,
      I2 => \aPvwbufB_reg_n_0_[8]\,
      I3 => \aPvwbufB[12]_i_3_n_0\,
      I4 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      O => \aPvwbufB[11]_i_1_n_0\
    );
\aPvwbufB[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF80"
    )
        port map (
      I0 => \^fsm_onehot_statepvwbufb_reg[5]_0\(0),
      I1 => pvwbufDecimToHostifAXIS_tready,
      I2 => \FSM_onehot_statePvwbufB[3]_i_2_n_0\,
      I3 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      O => \aPvwbufB[12]_i_1_n_0\
    );
\aPvwbufB[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAA6AAA"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[12]\,
      I1 => \aPvwbufB_reg_n_0_[8]\,
      I2 => \aPvwbufB_reg_n_0_[10]\,
      I3 => \aPvwbufB_reg_n_0_[11]\,
      I4 => \aPvwbufB[12]_i_3_n_0\,
      I5 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      O => \aPvwbufB[12]_i_2_n_0\
    );
\aPvwbufB[12]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[7]\,
      I1 => \aPvwbufB[9]_i_2_n_0\,
      I2 => \aPvwbufB_reg_n_0_[6]\,
      I3 => \aPvwbufB_reg_n_0_[9]\,
      O => \aPvwbufB[12]_i_3_n_0\
    );
\aPvwbufB[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[1]\,
      I1 => \aPvwbufB_reg_n_0_[0]\,
      I2 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      O => \aPvwbufB[1]_i_1_n_0\
    );
\aPvwbufB[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[2]\,
      I1 => \aPvwbufB_reg_n_0_[0]\,
      I2 => \aPvwbufB_reg_n_0_[1]\,
      I3 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      O => \aPvwbufB[2]_i_1_n_0\
    );
\aPvwbufB[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[3]\,
      I1 => \aPvwbufB_reg_n_0_[1]\,
      I2 => \aPvwbufB_reg_n_0_[0]\,
      I3 => \aPvwbufB_reg_n_0_[2]\,
      I4 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      O => \aPvwbufB[3]_i_1_n_0\
    );
\aPvwbufB[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000006AAAAAAA"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[4]\,
      I1 => \aPvwbufB_reg_n_0_[2]\,
      I2 => \aPvwbufB_reg_n_0_[0]\,
      I3 => \aPvwbufB_reg_n_0_[1]\,
      I4 => \aPvwbufB_reg_n_0_[3]\,
      I5 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      O => \aPvwbufB[4]_i_1_n_0\
    );
\aPvwbufB[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"09"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[5]\,
      I1 => \aPvwbufB[5]_i_2_n_0\,
      I2 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      O => \aPvwbufB[5]_i_1_n_0\
    );
\aPvwbufB[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[3]\,
      I1 => \aPvwbufB_reg_n_0_[1]\,
      I2 => \aPvwbufB_reg_n_0_[0]\,
      I3 => \aPvwbufB_reg_n_0_[2]\,
      I4 => \aPvwbufB_reg_n_0_[4]\,
      O => \aPvwbufB[5]_i_2_n_0\
    );
\aPvwbufB[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"09"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[6]\,
      I1 => \aPvwbufB[9]_i_2_n_0\,
      I2 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      O => \aPvwbufB[6]_i_1_n_0\
    );
\aPvwbufB[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"009A"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[7]\,
      I1 => \aPvwbufB[9]_i_2_n_0\,
      I2 => \aPvwbufB_reg_n_0_[6]\,
      I3 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      O => \aPvwbufB[7]_i_1_n_0\
    );
\aPvwbufB[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000A6AA"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[8]\,
      I1 => \aPvwbufB_reg_n_0_[6]\,
      I2 => \aPvwbufB[9]_i_2_n_0\,
      I3 => \aPvwbufB_reg_n_0_[7]\,
      I4 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      O => \aPvwbufB[8]_i_1_n_0\
    );
\aPvwbufB[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AA6AAAAA"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[9]\,
      I1 => \aPvwbufB_reg_n_0_[8]\,
      I2 => \aPvwbufB_reg_n_0_[7]\,
      I3 => \aPvwbufB[9]_i_2_n_0\,
      I4 => \aPvwbufB_reg_n_0_[6]\,
      I5 => \FSM_onehot_statePvwbufB_reg_n_0_[0]\,
      O => \aPvwbufB[9]_i_1_n_0\
    );
\aPvwbufB[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \aPvwbufB_reg_n_0_[4]\,
      I1 => \aPvwbufB_reg_n_0_[2]\,
      I2 => \aPvwbufB_reg_n_0_[0]\,
      I3 => \aPvwbufB_reg_n_0_[1]\,
      I4 => \aPvwbufB_reg_n_0_[3]\,
      I5 => \aPvwbufB_reg_n_0_[5]\,
      O => \aPvwbufB[9]_i_2_n_0\
    );
\aPvwbufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbufB[12]_i_1_n_0\,
      CLR => AR(0),
      D => \aPvwbufB[0]_i_1_n_0\,
      Q => \aPvwbufB_reg_n_0_[0]\
    );
\aPvwbufB_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbufB[12]_i_1_n_0\,
      CLR => AR(0),
      D => \aPvwbufB[10]_i_1_n_0\,
      Q => \aPvwbufB_reg_n_0_[10]\
    );
\aPvwbufB_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbufB[12]_i_1_n_0\,
      CLR => AR(0),
      D => \aPvwbufB[11]_i_1_n_0\,
      Q => \aPvwbufB_reg_n_0_[11]\
    );
\aPvwbufB_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbufB[12]_i_1_n_0\,
      CLR => AR(0),
      D => \aPvwbufB[12]_i_2_n_0\,
      Q => \aPvwbufB_reg_n_0_[12]\
    );
\aPvwbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbufB[12]_i_1_n_0\,
      CLR => AR(0),
      D => \aPvwbufB[1]_i_1_n_0\,
      Q => \aPvwbufB_reg_n_0_[1]\
    );
\aPvwbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbufB[12]_i_1_n_0\,
      CLR => AR(0),
      D => \aPvwbufB[2]_i_1_n_0\,
      Q => \aPvwbufB_reg_n_0_[2]\
    );
\aPvwbufB_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbufB[12]_i_1_n_0\,
      CLR => AR(0),
      D => \aPvwbufB[3]_i_1_n_0\,
      Q => \aPvwbufB_reg_n_0_[3]\
    );
\aPvwbufB_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbufB[12]_i_1_n_0\,
      CLR => AR(0),
      D => \aPvwbufB[4]_i_1_n_0\,
      Q => \aPvwbufB_reg_n_0_[4]\
    );
\aPvwbufB_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbufB[12]_i_1_n_0\,
      CLR => AR(0),
      D => \aPvwbufB[5]_i_1_n_0\,
      Q => \aPvwbufB_reg_n_0_[5]\
    );
\aPvwbufB_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbufB[12]_i_1_n_0\,
      CLR => AR(0),
      D => \aPvwbufB[6]_i_1_n_0\,
      Q => \aPvwbufB_reg_n_0_[6]\
    );
\aPvwbufB_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbufB[12]_i_1_n_0\,
      CLR => AR(0),
      D => \aPvwbufB[7]_i_1_n_0\,
      Q => \aPvwbufB_reg_n_0_[7]\
    );
\aPvwbufB_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbufB[12]_i_1_n_0\,
      CLR => AR(0),
      D => \aPvwbufB[8]_i_1_n_0\,
      Q => \aPvwbufB_reg_n_0_[8]\
    );
\aPvwbufB_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbufB[12]_i_1_n_0\,
      CLR => AR(0),
      D => \aPvwbufB[9]_i_1_n_0\,
      Q => \aPvwbufB_reg_n_0_[9]\
    );
\aPvwbuf[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \^statestore_reg[1]_0\(0),
      I2 => \^statestore_reg[1]_0\(1),
      I3 => aPvwbuf_reg(0),
      O => p_0_in(0)
    );
\aPvwbuf[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88804440"
    )
        port map (
      I0 => \aPvwbuf[10]_i_2_n_0\,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      I4 => aPvwbuf_reg(10),
      O => p_0_in(10)
    );
\aPvwbuf[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7FFFFFF"
    )
        port map (
      I0 => aPvwbuf_reg(9),
      I1 => aPvwbuf_reg(6),
      I2 => \aPvwbuf[9]_i_2_n_0\,
      I3 => aPvwbuf_reg(7),
      I4 => aPvwbuf_reg(8),
      O => \aPvwbuf[10]_i_2_n_0\
    );
\aPvwbuf[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88804440"
    )
        port map (
      I0 => \aPvwbuf[14]_i_2_n_0\,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      I4 => aPvwbuf_reg(11),
      O => p_0_in(11)
    );
\aPvwbuf[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0B0B00040404000"
    )
        port map (
      I0 => \aPvwbuf[14]_i_2_n_0\,
      I1 => aPvwbuf_reg(11),
      I2 => \^rng_reg_0\,
      I3 => \^statestore_reg[1]_0\(0),
      I4 => \^statestore_reg[1]_0\(1),
      I5 => aPvwbuf_reg(12),
      O => p_0_in(12)
    );
\aPvwbuf[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00F70008"
    )
        port map (
      I0 => aPvwbuf_reg(12),
      I1 => aPvwbuf_reg(11),
      I2 => \aPvwbuf[14]_i_2_n_0\,
      I3 => aPvwbuf1,
      I4 => aPvwbuf_reg(13),
      O => p_0_in(13)
    );
\aPvwbuf[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000DFFF00002000"
    )
        port map (
      I0 => aPvwbuf_reg(13),
      I1 => \aPvwbuf[14]_i_2_n_0\,
      I2 => aPvwbuf_reg(11),
      I3 => aPvwbuf_reg(12),
      I4 => aPvwbuf1,
      I5 => aPvwbuf_reg(14),
      O => p_0_in(14)
    );
\aPvwbuf[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFFFFFFF"
    )
        port map (
      I0 => aPvwbuf_reg(8),
      I1 => aPvwbuf_reg(7),
      I2 => \aPvwbuf[9]_i_2_n_0\,
      I3 => aPvwbuf_reg(6),
      I4 => aPvwbuf_reg(9),
      I5 => aPvwbuf_reg(10),
      O => \aPvwbuf[14]_i_2_n_0\
    );
\aPvwbuf[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"373F"
    )
        port map (
      I0 => \stateStore[1]_i_3_n_0\,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \aPvwbuf[15]_i_1_n_0\
    );
\aPvwbuf[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0B0B00040404000"
    )
        port map (
      I0 => \aPvwbuf[15]_i_3_n_0\,
      I1 => aPvwbuf_reg(14),
      I2 => \^rng_reg_0\,
      I3 => \^statestore_reg[1]_0\(0),
      I4 => \^statestore_reg[1]_0\(1),
      I5 => aPvwbuf_reg(15),
      O => p_0_in(15)
    );
\aPvwbuf[15]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => aPvwbuf_reg(13),
      I1 => \aPvwbuf[14]_i_2_n_0\,
      I2 => aPvwbuf_reg(11),
      I3 => aPvwbuf_reg(12),
      O => \aPvwbuf[15]_i_3_n_0\
    );
\aPvwbuf[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0E000"
    )
        port map (
      I0 => \^statestore_reg[1]_0\(1),
      I1 => \^statestore_reg[1]_0\(0),
      I2 => \^rng_reg_0\,
      I3 => aPvwbuf_reg(0),
      I4 => aPvwbuf_reg(1),
      O => p_0_in(1)
    );
\aPvwbuf[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E0E0E0E0000000"
    )
        port map (
      I0 => \^statestore_reg[1]_0\(1),
      I1 => \^statestore_reg[1]_0\(0),
      I2 => \^rng_reg_0\,
      I3 => aPvwbuf_reg(0),
      I4 => aPvwbuf_reg(1),
      I5 => aPvwbuf_reg(2),
      O => p_0_in(2)
    );
\aPvwbuf[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"007F0080"
    )
        port map (
      I0 => aPvwbuf_reg(0),
      I1 => aPvwbuf_reg(1),
      I2 => aPvwbuf_reg(2),
      I3 => aPvwbuf1,
      I4 => aPvwbuf_reg(3),
      O => p_0_in(3)
    );
\aPvwbuf[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007FFF00008000"
    )
        port map (
      I0 => aPvwbuf_reg(2),
      I1 => aPvwbuf_reg(1),
      I2 => aPvwbuf_reg(0),
      I3 => aPvwbuf_reg(3),
      I4 => aPvwbuf1,
      I5 => aPvwbuf_reg(4),
      O => p_0_in(4)
    );
\aPvwbuf[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44408880"
    )
        port map (
      I0 => \aPvwbuf[5]_i_2_n_0\,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      I4 => aPvwbuf_reg(5),
      O => p_0_in(5)
    );
\aPvwbuf[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => aPvwbuf_reg(4),
      I1 => aPvwbuf_reg(3),
      I2 => aPvwbuf_reg(0),
      I3 => aPvwbuf_reg(1),
      I4 => aPvwbuf_reg(2),
      O => \aPvwbuf[5]_i_2_n_0\
    );
\aPvwbuf[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88804440"
    )
        port map (
      I0 => \aPvwbuf[9]_i_2_n_0\,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      I4 => aPvwbuf_reg(6),
      O => p_0_in(6)
    );
\aPvwbuf[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0B0B00040404000"
    )
        port map (
      I0 => \aPvwbuf[9]_i_2_n_0\,
      I1 => aPvwbuf_reg(6),
      I2 => \^rng_reg_0\,
      I3 => \^statestore_reg[1]_0\(0),
      I4 => \^statestore_reg[1]_0\(1),
      I5 => aPvwbuf_reg(7),
      O => p_0_in(7)
    );
\aPvwbuf[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00DF0020"
    )
        port map (
      I0 => aPvwbuf_reg(6),
      I1 => \aPvwbuf[9]_i_2_n_0\,
      I2 => aPvwbuf_reg(7),
      I3 => aPvwbuf1,
      I4 => aPvwbuf_reg(8),
      O => p_0_in(8)
    );
\aPvwbuf[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000F7FF00000800"
    )
        port map (
      I0 => aPvwbuf_reg(8),
      I1 => aPvwbuf_reg(7),
      I2 => \aPvwbuf[9]_i_2_n_0\,
      I3 => aPvwbuf_reg(6),
      I4 => aPvwbuf1,
      I5 => aPvwbuf_reg(9),
      O => p_0_in(9)
    );
\aPvwbuf[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => aPvwbuf_reg(5),
      I1 => aPvwbuf_reg(2),
      I2 => aPvwbuf_reg(1),
      I3 => aPvwbuf_reg(0),
      I4 => aPvwbuf_reg(3),
      I5 => aPvwbuf_reg(4),
      O => \aPvwbuf[9]_i_2_n_0\
    );
\aPvwbuf_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(0),
      Q => aPvwbuf_reg(0)
    );
\aPvwbuf_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(10),
      Q => aPvwbuf_reg(10)
    );
\aPvwbuf_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(11),
      Q => aPvwbuf_reg(11)
    );
\aPvwbuf_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(12),
      Q => aPvwbuf_reg(12)
    );
\aPvwbuf_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(13),
      Q => aPvwbuf_reg(13)
    );
\aPvwbuf_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(14),
      Q => aPvwbuf_reg(14)
    );
\aPvwbuf_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(15),
      Q => aPvwbuf_reg(15)
    );
\aPvwbuf_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(1),
      Q => aPvwbuf_reg(1)
    );
\aPvwbuf_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(2),
      Q => aPvwbuf_reg(2)
    );
\aPvwbuf_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(3),
      Q => aPvwbuf_reg(3)
    );
\aPvwbuf_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(4),
      Q => aPvwbuf_reg(4)
    );
\aPvwbuf_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(5),
      Q => aPvwbuf_reg(5)
    );
\aPvwbuf_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(6),
      Q => aPvwbuf_reg(6)
    );
\aPvwbuf_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(7),
      Q => aPvwbuf_reg(7)
    );
\aPvwbuf_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(8),
      Q => aPvwbuf_reg(8)
    );
\aPvwbuf_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aPvwbuf[15]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_in(9),
      Q => aPvwbuf_reg(9)
    );
\acc0_lcl[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => O(0),
      I1 => \^rng_reg_0\,
      I2 => stateStream(2),
      I3 => stateStream(1),
      I4 => stateStream(0),
      O => acc0(0)
    );
\acc0_lcl[19]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \aAccbufB[7]_i_3_n_0\,
      I1 => rowacc(2),
      I2 => rowacc(3),
      I3 => rowacc(1),
      I4 => rowacc(0),
      O => \acc0_lcl[19]_i_7_n_0\
    );
\acc0_lcl[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => O(1),
      I1 => \^rng_reg_0\,
      I2 => stateStream(2),
      I3 => stateStream(1),
      I4 => stateStream(0),
      O => acc0(1)
    );
\acc0_lcl[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => O(2),
      I1 => \^rng_reg_0\,
      I2 => stateStream(2),
      I3 => stateStream(1),
      I4 => stateStream(0),
      O => acc0(2)
    );
\acc0_lcl[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => O(3),
      I1 => \^rng_reg_0\,
      I2 => stateStream(2),
      I3 => stateStream(1),
      I4 => stateStream(0),
      O => acc0(3)
    );
\acc0_lcl[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => O(4),
      I1 => \^rng_reg_0\,
      I2 => stateStream(2),
      I3 => stateStream(1),
      I4 => stateStream(0),
      O => acc0(4)
    );
\acc0_lcl[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => O(5),
      I1 => \^rng_reg_0\,
      I2 => stateStream(2),
      I3 => stateStream(1),
      I4 => stateStream(0),
      O => acc0(5)
    );
\acc0_lcl[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => O(6),
      I1 => \^rng_reg_0\,
      I2 => stateStream(2),
      I3 => stateStream(1),
      I4 => stateStream(0),
      O => acc0(6)
    );
\acc0_lcl[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888880"
    )
        port map (
      I0 => O(7),
      I1 => \^rng_reg_0\,
      I2 => stateStream(2),
      I3 => stateStream(1),
      I4 => stateStream(0),
      O => acc0(7)
    );
\acc0_lcl_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(0),
      Q => \acc0_lcl_reg_n_0_[0]\
    );
\acc0_lcl_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(10),
      Q => \acc0_lcl_reg_n_0_[10]\
    );
\acc0_lcl_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(11),
      Q => \acc0_lcl_reg_n_0_[11]\
    );
\acc0_lcl_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(12),
      Q => \acc0_lcl_reg_n_0_[12]\
    );
\acc0_lcl_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(13),
      Q => \acc0_lcl_reg_n_0_[13]\
    );
\acc0_lcl_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(14),
      Q => \acc0_lcl_reg_n_0_[14]\
    );
\acc0_lcl_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(15),
      Q => \acc0_lcl_reg_n_0_[15]\
    );
\acc0_lcl_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(16),
      Q => \acc0_lcl_reg_n_0_[16]\
    );
\acc0_lcl_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(17),
      Q => \acc0_lcl_reg_n_0_[17]\
    );
\acc0_lcl_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(18),
      Q => \acc0_lcl_reg_n_0_[18]\
    );
\acc0_lcl_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(19),
      Q => \acc0_lcl_reg_n_0_[19]\
    );
\acc0_lcl_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(1),
      Q => \acc0_lcl_reg_n_0_[1]\
    );
\acc0_lcl_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(2),
      Q => \acc0_lcl_reg_n_0_[2]\
    );
\acc0_lcl_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(3),
      Q => \acc0_lcl_reg_n_0_[3]\
    );
\acc0_lcl_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(4),
      Q => \acc0_lcl_reg_n_0_[4]\
    );
\acc0_lcl_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(5),
      Q => \acc0_lcl_reg_n_0_[5]\
    );
\acc0_lcl_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(6),
      Q => \acc0_lcl_reg_n_0_[6]\
    );
\acc0_lcl_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(7),
      Q => \acc0_lcl_reg_n_0_[7]\
    );
\acc0_lcl_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(8),
      Q => \acc0_lcl_reg_n_0_[8]\
    );
\acc0_lcl_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(9),
      Q => \acc0_lcl_reg_n_0_[9]\
    );
\acc0_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(0),
      Q => \acc0_reg_n_0_[0]\
    );
\acc0_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(10),
      Q => \acc0_reg_n_0_[10]\
    );
\acc0_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(11),
      Q => \acc0_reg_n_0_[11]\
    );
\acc0_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(12),
      Q => \acc0_reg_n_0_[12]\
    );
\acc0_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(13),
      Q => \acc0_reg_n_0_[13]\
    );
\acc0_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(14),
      Q => \acc0_reg_n_0_[14]\
    );
\acc0_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(15),
      Q => \acc0_reg_n_0_[15]\
    );
\acc0_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(16),
      Q => \acc0_reg_n_0_[16]\
    );
\acc0_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(17),
      Q => \acc0_reg_n_0_[17]\
    );
\acc0_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(18),
      Q => \acc0_reg_n_0_[18]\
    );
\acc0_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(19),
      Q => \acc0_reg_n_0_[19]\
    );
\acc0_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(1),
      Q => \acc0_reg_n_0_[1]\
    );
\acc0_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(2),
      Q => \acc0_reg_n_0_[2]\
    );
\acc0_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(3),
      Q => \acc0_reg_n_0_[3]\
    );
\acc0_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(4),
      Q => \acc0_reg_n_0_[4]\
    );
\acc0_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(5),
      Q => \acc0_reg_n_0_[5]\
    );
\acc0_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(6),
      Q => \acc0_reg_n_0_[6]\
    );
\acc0_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(7),
      Q => \acc0_reg_n_0_[7]\
    );
\acc0_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(8),
      Q => \acc0_reg_n_0_[8]\
    );
\acc0_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc0(9),
      Q => \acc0_reg_n_0_[9]\
    );
\acc1_lcl_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(0),
      Q => \acc1_lcl_reg_n_0_[0]\
    );
\acc1_lcl_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(10),
      Q => \acc1_lcl_reg_n_0_[10]\
    );
\acc1_lcl_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(11),
      Q => \acc1_lcl_reg_n_0_[11]\
    );
\acc1_lcl_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(12),
      Q => \acc1_lcl_reg_n_0_[12]\
    );
\acc1_lcl_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(13),
      Q => \acc1_lcl_reg_n_0_[13]\
    );
\acc1_lcl_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(14),
      Q => \acc1_lcl_reg_n_0_[14]\
    );
\acc1_lcl_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(15),
      Q => \acc1_lcl_reg_n_0_[15]\
    );
\acc1_lcl_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(16),
      Q => \acc1_lcl_reg_n_0_[16]\
    );
\acc1_lcl_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(17),
      Q => \acc1_lcl_reg_n_0_[17]\
    );
\acc1_lcl_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(18),
      Q => \acc1_lcl_reg_n_0_[18]\
    );
\acc1_lcl_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(19),
      Q => \acc1_lcl_reg_n_0_[19]\
    );
\acc1_lcl_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(1),
      Q => \acc1_lcl_reg_n_0_[1]\
    );
\acc1_lcl_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(2),
      Q => \acc1_lcl_reg_n_0_[2]\
    );
\acc1_lcl_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(3),
      Q => \acc1_lcl_reg_n_0_[3]\
    );
\acc1_lcl_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(4),
      Q => \acc1_lcl_reg_n_0_[4]\
    );
\acc1_lcl_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(5),
      Q => \acc1_lcl_reg_n_0_[5]\
    );
\acc1_lcl_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(6),
      Q => \acc1_lcl_reg_n_0_[6]\
    );
\acc1_lcl_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(7),
      Q => \acc1_lcl_reg_n_0_[7]\
    );
\acc1_lcl_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(8),
      Q => \acc1_lcl_reg_n_0_[8]\
    );
\acc1_lcl_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(9),
      Q => \acc1_lcl_reg_n_0_[9]\
    );
\acc1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(0),
      Q => \acc1_reg_n_0_[0]\
    );
\acc1_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(10),
      Q => \acc1_reg_n_0_[10]\
    );
\acc1_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(11),
      Q => \acc1_reg_n_0_[11]\
    );
\acc1_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(12),
      Q => \acc1_reg_n_0_[12]\
    );
\acc1_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(13),
      Q => \acc1_reg_n_0_[13]\
    );
\acc1_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(14),
      Q => \acc1_reg_n_0_[14]\
    );
\acc1_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(15),
      Q => \acc1_reg_n_0_[15]\
    );
\acc1_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(16),
      Q => \acc1_reg_n_0_[16]\
    );
\acc1_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(17),
      Q => \acc1_reg_n_0_[17]\
    );
\acc1_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(18),
      Q => \acc1_reg_n_0_[18]\
    );
\acc1_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(19),
      Q => \acc1_reg_n_0_[19]\
    );
\acc1_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(1),
      Q => \acc1_reg_n_0_[1]\
    );
\acc1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(2),
      Q => \acc1_reg_n_0_[2]\
    );
\acc1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(3),
      Q => \acc1_reg_n_0_[3]\
    );
\acc1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(4),
      Q => \acc1_reg_n_0_[4]\
    );
\acc1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(5),
      Q => \acc1_reg_n_0_[5]\
    );
\acc1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(6),
      Q => \acc1_reg_n_0_[6]\
    );
\acc1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(7),
      Q => \acc1_reg_n_0_[7]\
    );
\acc1_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(8),
      Q => \acc1_reg_n_0_[8]\
    );
\acc1_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => acc1(9),
      Q => \acc1_reg_n_0_[9]\
    );
\acc2[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F0F8F0F0F0FFF"
    )
        port map (
      I0 => enAccbuf_reg_0,
      I1 => \stateStream[2]_i_4_n_0\,
      I2 => \^rng_reg_0\,
      I3 => stateStream(2),
      I4 => stateStream(1),
      I5 => stateStream(0),
      O => acc2
    );
\acc2_lcl_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_19,
      Q => \acc2_lcl_reg_n_0_[0]\
    );
\acc2_lcl_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_9,
      Q => \acc2_lcl_reg_n_0_[10]\
    );
\acc2_lcl_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_8,
      Q => \acc2_lcl_reg_n_0_[11]\
    );
\acc2_lcl_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_7,
      Q => \acc2_lcl_reg_n_0_[12]\
    );
\acc2_lcl_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_6,
      Q => \acc2_lcl_reg_n_0_[13]\
    );
\acc2_lcl_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_5,
      Q => \acc2_lcl_reg_n_0_[14]\
    );
\acc2_lcl_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_4,
      Q => \acc2_lcl_reg_n_0_[15]\
    );
\acc2_lcl_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_3,
      Q => \acc2_lcl_reg_n_0_[16]\
    );
\acc2_lcl_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_2,
      Q => \acc2_lcl_reg_n_0_[17]\
    );
\acc2_lcl_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_1,
      Q => \acc2_lcl_reg_n_0_[18]\
    );
\acc2_lcl_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_0,
      Q => \acc2_lcl_reg_n_0_[19]\
    );
\acc2_lcl_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_18,
      Q => \acc2_lcl_reg_n_0_[1]\
    );
\acc2_lcl_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_17,
      Q => \acc2_lcl_reg_n_0_[2]\
    );
\acc2_lcl_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_16,
      Q => \acc2_lcl_reg_n_0_[3]\
    );
\acc2_lcl_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_15,
      Q => \acc2_lcl_reg_n_0_[4]\
    );
\acc2_lcl_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_14,
      Q => \acc2_lcl_reg_n_0_[5]\
    );
\acc2_lcl_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_13,
      Q => \acc2_lcl_reg_n_0_[6]\
    );
\acc2_lcl_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_12,
      Q => \acc2_lcl_reg_n_0_[7]\
    );
\acc2_lcl_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_11,
      Q => \acc2_lcl_reg_n_0_[8]\
    );
\acc2_lcl_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_10,
      Q => \acc2_lcl_reg_n_0_[9]\
    );
\acc2_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_19,
      Q => \acc2_reg_n_0_[0]\
    );
\acc2_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_9,
      Q => \acc2_reg_n_0_[10]\
    );
\acc2_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_8,
      Q => \acc2_reg_n_0_[11]\
    );
\acc2_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_7,
      Q => \acc2_reg_n_0_[12]\
    );
\acc2_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_6,
      Q => \acc2_reg_n_0_[13]\
    );
\acc2_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_5,
      Q => \acc2_reg_n_0_[14]\
    );
\acc2_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_4,
      Q => \acc2_reg_n_0_[15]\
    );
\acc2_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_3,
      Q => \acc2_reg_n_0_[16]\
    );
\acc2_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_2,
      Q => \acc2_reg_n_0_[17]\
    );
\acc2_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_1,
      Q => \acc2_reg_n_0_[18]\
    );
\acc2_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_0,
      Q => \acc2_reg_n_0_[19]\
    );
\acc2_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_18,
      Q => \acc2_reg_n_0_[1]\
    );
\acc2_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_17,
      Q => \acc2_reg_n_0_[2]\
    );
\acc2_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_16,
      Q => \acc2_reg_n_0_[3]\
    );
\acc2_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_15,
      Q => \acc2_reg_n_0_[4]\
    );
\acc2_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_14,
      Q => \acc2_reg_n_0_[5]\
    );
\acc2_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_13,
      Q => \acc2_reg_n_0_[6]\
    );
\acc2_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_12,
      Q => \acc2_reg_n_0_[7]\
    );
\acc2_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_11,
      Q => \acc2_reg_n_0_[8]\
    );
\acc2_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => acc2,
      CLR => AR(0),
      D => myAccbuf_n_10,
      Q => \acc2_reg_n_0_[9]\
    );
\ackInvAcquire_sig_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => \^stateop_reg[1]_0\(0),
      I1 => \^stateop_reg[1]_0\(1),
      I2 => reqInvDecimAcquire,
      O => ackInvAcquire_sig
    );
ackInvAcquire_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvUnlock_sig,
      CLR => AR(0),
      D => ackInvAcquire_sig,
      Q => \^ackinvdecimacquire\
    );
\ackInvConfig_sig_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0400"
    )
        port map (
      I0 => reqInvDecimConfig,
      I1 => \^ackinvdecimconfig\,
      I2 => \^stateop_reg[1]_0\(1),
      I3 => \^stateop_reg[1]_0\(0),
      I4 => ackInvConfig_sig_i_4_n_0,
      I5 => ackInvConfig_sig_i_5_n_0,
      O => ackInvUnlock_sig
    );
ackInvConfig_sig_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0D00"
    )
        port map (
      I0 => \^stateop_reg[1]_0\(0),
      I1 => \^stateop_reg[1]_0\(1),
      I2 => reqInvDecimAcquire,
      I3 => reqInvDecimConfig,
      O => ackInvConfig_sig
    );
ackInvConfig_sig_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020002000F00020"
    )
        port map (
      I0 => \^ackinvdecimset\,
      I1 => reqInvDecimSet,
      I2 => \^stateop_reg[1]_0\(0),
      I3 => \^stateop_reg[1]_0\(1),
      I4 => \^ackinvdecimunlock\,
      I5 => reqInvDecimUnlock,
      O => ackInvConfig_sig_i_4_n_0
    );
ackInvConfig_sig_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0020"
    )
        port map (
      I0 => \^stateop_reg[1]_0\(0),
      I1 => \^stateop_reg[1]_0\(1),
      I2 => \^ackinvdecimacquire\,
      I3 => reqInvDecimAcquire,
      I4 => tixVState1,
      O => ackInvConfig_sig_i_5_n_0
    );
ackInvConfig_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvUnlock_sig,
      CLR => AR(0),
      D => ackInvConfig_sig,
      Q => \^ackinvdecimconfig\
    );
ackInvSet_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvUnlock_sig,
      CLR => AR(0),
      D => ackInvSet_sig,
      Q => \^ackinvdecimset\
    );
ackInvUnlock_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvUnlock_sig,
      CLR => AR(0),
      D => ackInvUnlock_sig_reg_0,
      Q => \^ackinvdecimunlock\
    );
\col[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \col[10]_i_3__0_n_0\,
      I1 => col(0),
      O => \col[0]_i_1__0_n_0\
    );
\col[10]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3110077307733110"
    )
        port map (
      I0 => NColRaw(0),
      I1 => NColRaw(1),
      I2 => \edge_reg_n_0_[0]\,
      I3 => col(0),
      I4 => \edge_reg_n_0_[1]\,
      I5 => col(1),
      O => \col[10]_i_10_n_0\
    );
\col[10]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96999999"
    )
        port map (
      I0 => NColRaw(10),
      I1 => col(10),
      I2 => \col[10]_i_17_n_0\,
      I3 => col(8),
      I4 => col(9),
      O => \col[10]_i_11_n_0\
    );
\col[10]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82412418"
    )
        port map (
      I0 => col(9),
      I1 => col(8),
      I2 => \col[10]_i_17_n_0\,
      I3 => NColRaw(9),
      I4 => NColRaw(8),
      O => \col[10]_i_12_n_0\
    );
\col[10]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82412418"
    )
        port map (
      I0 => col(7),
      I1 => col(6),
      I2 => \col[10]_i_18_n_0\,
      I3 => NColRaw(7),
      I4 => NColRaw(6),
      O => \col[10]_i_13_n_0\
    );
\col[10]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4228811414422881"
    )
        port map (
      I0 => col(5),
      I1 => \col[10]_i_19_n_0\,
      I2 => \edge_reg_n_0_[4]\,
      I3 => col(4),
      I4 => NColRaw(5),
      I5 => NColRaw(4),
      O => \col[10]_i_14_n_0\
    );
\col[10]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669000000009669"
    )
        port map (
      I0 => NColRaw(3),
      I1 => \col[10]_i_20_n_0\,
      I2 => col(3),
      I3 => \edge_reg_n_0_[3]\,
      I4 => \col2__0\(2),
      I5 => NColRaw(2),
      O => \col[10]_i_15_n_0\
    );
\col[10]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0069690096000069"
    )
        port map (
      I0 => NColRaw(1),
      I1 => col(1),
      I2 => \edge_reg_n_0_[1]\,
      I3 => col(0),
      I4 => \edge_reg_n_0_[0]\,
      I5 => NColRaw(0),
      O => \col[10]_i_16_n_0\
    );
\col[10]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"17FFFFFFFFFFFFFF"
    )
        port map (
      I0 => col(4),
      I1 => \edge_reg_n_0_[4]\,
      I2 => \col[10]_i_19_n_0\,
      I3 => col(5),
      I4 => col(6),
      I5 => col(7),
      O => \col[10]_i_17_n_0\
    );
\col[10]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"11171777FFFFFFFF"
    )
        port map (
      I0 => col(4),
      I1 => \edge_reg_n_0_[4]\,
      I2 => \col[10]_i_20_n_0\,
      I3 => \edge_reg_n_0_[3]\,
      I4 => col(3),
      I5 => col(5),
      O => \col[10]_i_18_n_0\
    );
\col[10]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \col[10]_i_20_n_0\,
      I1 => \edge_reg_n_0_[3]\,
      I2 => col(3),
      O => \col[10]_i_19_n_0\
    );
\col[10]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF000080000000"
    )
        port map (
      I0 => \col[10]_i_2__0_n_0\,
      I1 => col(7),
      I2 => col(8),
      I3 => col(9),
      I4 => \col[10]_i_3__0_n_0\,
      I5 => col(10),
      O => \col[10]_i_1__0_n_0\
    );
\col[10]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC80EC800000"
    )
        port map (
      I0 => \edge_reg_n_0_[0]\,
      I1 => col(1),
      I2 => col(0),
      I3 => \edge_reg_n_0_[1]\,
      I4 => \edge_reg_n_0_[2]\,
      I5 => col(2),
      O => \col[10]_i_20_n_0\
    );
\col[10]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A9959955566A66AA"
    )
        port map (
      I0 => \edge_reg_n_0_[2]\,
      I1 => \edge_reg_n_0_[1]\,
      I2 => col(0),
      I3 => col(1),
      I4 => \edge_reg_n_0_[0]\,
      I5 => col(2),
      O => \col2__0\(2)
    );
\col[10]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080000000"
    )
        port map (
      I0 => col(6),
      I1 => col(5),
      I2 => col(4),
      I3 => col(3),
      I4 => col(2),
      I5 => \col[5]_i_2__0_n_0\,
      O => \col[10]_i_2__0_n_0\
    );
\col[10]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7070707070707000"
    )
        port map (
      I0 => \^enaccbuf0\,
      I1 => \col_reg[10]_i_4_n_2\,
      I2 => \^rng_reg_0\,
      I3 => stateStream(2),
      I4 => stateStream(1),
      I5 => stateStream(0),
      O => \col[10]_i_3__0_n_0\
    );
\col[10]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00009AAA"
    )
        port map (
      I0 => col(10),
      I1 => \col[10]_i_17_n_0\,
      I2 => col(8),
      I3 => col(9),
      I4 => NColRaw(10),
      O => \col[10]_i_5_n_0\
    );
\col[10]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"70371301"
    )
        port map (
      I0 => NColRaw(8),
      I1 => NColRaw(9),
      I2 => \col[10]_i_17_n_0\,
      I3 => col(8),
      I4 => col(9),
      O => \col[10]_i_6_n_0\
    );
\col[10]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"70371301"
    )
        port map (
      I0 => NColRaw(6),
      I1 => NColRaw(7),
      I2 => \col[10]_i_18_n_0\,
      I3 => col(6),
      I4 => col(7),
      O => \col[10]_i_7_n_0\
    );
\col[10]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1007077373313110"
    )
        port map (
      I0 => NColRaw(4),
      I1 => NColRaw(5),
      I2 => col(4),
      I3 => \edge_reg_n_0_[4]\,
      I4 => \col[10]_i_19_n_0\,
      I5 => col(5),
      O => \col[10]_i_8_n_0\
    );
\col[10]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0096009696FF0096"
    )
        port map (
      I0 => \col[10]_i_20_n_0\,
      I1 => col(3),
      I2 => \edge_reg_n_0_[3]\,
      I3 => NColRaw(3),
      I4 => \col2__0\(2),
      I5 => NColRaw(2),
      O => \col[10]_i_9_n_0\
    );
\col[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \col[10]_i_3__0_n_0\,
      I1 => col(0),
      I2 => col(1),
      O => \col[1]_i_1__0_n_0\
    );
\col[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \col[10]_i_3__0_n_0\,
      I1 => col(1),
      I2 => col(0),
      I3 => col(2),
      O => \col[2]_i_1__0_n_0\
    );
\col[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \col[10]_i_3__0_n_0\,
      I1 => col(0),
      I2 => col(1),
      I3 => col(2),
      I4 => col(3),
      O => \col[3]_i_1__0_n_0\
    );
\col[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \col[10]_i_3__0_n_0\,
      I1 => col(3),
      I2 => col(2),
      I3 => col(1),
      I4 => col(0),
      I5 => col(4),
      O => \col[4]_i_1__0_n_0\
    );
\col[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F000000800000"
    )
        port map (
      I0 => col(4),
      I1 => col(3),
      I2 => col(2),
      I3 => \col[5]_i_2__0_n_0\,
      I4 => \col[10]_i_3__0_n_0\,
      I5 => col(5),
      O => \col[5]_i_1__0_n_0\
    );
\col[5]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => col(0),
      I1 => col(1),
      O => \col[5]_i_2__0_n_0\
    );
\col[6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"84"
    )
        port map (
      I0 => \col[9]_i_2__0_n_0\,
      I1 => \col[10]_i_3__0_n_0\,
      I2 => col(6),
      O => \col[6]_i_1__0_n_0\
    );
\col[7]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D020"
    )
        port map (
      I0 => col(6),
      I1 => \col[9]_i_2__0_n_0\,
      I2 => \col[10]_i_3__0_n_0\,
      I3 => col(7),
      O => \col[7]_i_1__0_n_0\
    );
\col[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BF004000"
    )
        port map (
      I0 => \col[9]_i_2__0_n_0\,
      I1 => col(6),
      I2 => col(7),
      I3 => \col[10]_i_3__0_n_0\,
      I4 => col(8),
      O => \col[8]_i_1__0_n_0\
    );
\col[9]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F000000800000"
    )
        port map (
      I0 => col(8),
      I1 => col(7),
      I2 => col(6),
      I3 => \col[9]_i_2__0_n_0\,
      I4 => \col[10]_i_3__0_n_0\,
      I5 => col(9),
      O => \col[9]_i_1__0_n_0\
    );
\col[9]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => col(0),
      I1 => col(1),
      I2 => col(2),
      I3 => col(3),
      I4 => col(4),
      I5 => col(5),
      O => \col[9]_i_2__0_n_0\
    );
\col_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \col[0]_i_1__0_n_0\,
      Q => col(0)
    );
\col_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \col[10]_i_1__0_n_0\,
      Q => col(10)
    );
\col_reg[10]_i_4\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_col_reg[10]_i_4_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \col_reg[10]_i_4_n_2\,
      CO(4) => \col_reg[10]_i_4_n_3\,
      CO(3) => \col_reg[10]_i_4_n_4\,
      CO(2) => \col_reg[10]_i_4_n_5\,
      CO(1) => \col_reg[10]_i_4_n_6\,
      CO(0) => \col_reg[10]_i_4_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \col[10]_i_5_n_0\,
      DI(4) => \col[10]_i_6_n_0\,
      DI(3) => \col[10]_i_7_n_0\,
      DI(2) => \col[10]_i_8_n_0\,
      DI(1) => \col[10]_i_9_n_0\,
      DI(0) => \col[10]_i_10_n_0\,
      O(7 downto 0) => \NLW_col_reg[10]_i_4_O_UNCONNECTED\(7 downto 0),
      S(7 downto 6) => B"00",
      S(5) => \col[10]_i_11_n_0\,
      S(4) => \col[10]_i_12_n_0\,
      S(3) => \col[10]_i_13_n_0\,
      S(2) => \col[10]_i_14_n_0\,
      S(1) => \col[10]_i_15_n_0\,
      S(0) => \col[10]_i_16_n_0\
    );
\col_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \col[1]_i_1__0_n_0\,
      Q => col(1)
    );
\col_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \col[2]_i_1__0_n_0\,
      Q => col(2)
    );
\col_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \col[3]_i_1__0_n_0\,
      Q => col(3)
    );
\col_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \col[4]_i_1__0_n_0\,
      Q => col(4)
    );
\col_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \col[5]_i_1__0_n_0\,
      Q => col(5)
    );
\col_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \col[6]_i_1__0_n_0\,
      Q => col(6)
    );
\col_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \col[7]_i_1__0_n_0\,
      Q => col(7)
    );
\col_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \col[8]_i_1__0_n_0\,
      Q => col(8)
    );
\col_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \col[9]_i_1__0_n_0\,
      Q => col(9)
    );
\colaccLast[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \edge_reg_n_0_[0]\,
      O => colaccLast0(0)
    );
\colaccLast[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \edge_reg_n_0_[1]\,
      I1 => \edge_reg_n_0_[0]\,
      O => colaccLast0(1)
    );
\colaccLast[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \edge_reg_n_0_[2]\,
      I1 => \edge_reg_n_0_[0]\,
      I2 => \edge_reg_n_0_[1]\,
      O => colaccLast0(2)
    );
\colaccLast[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B0000000"
    )
        port map (
      I0 => \^tixvstate_reg[1]_0\(0),
      I1 => \^tixvstate_reg[1]_0\(1),
      I2 => vsync_last_reg_1,
      I3 => \^rng_reg_0\,
      I4 => enAccbuf11_out,
      O => tkst
    );
\colaccLast[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => \edge_reg_n_0_[2]\,
      I1 => \edge_reg_n_0_[0]\,
      I2 => \edge_reg_n_0_[1]\,
      I3 => \edge_reg_n_0_[3]\,
      O => colaccLast0(3)
    );
\colaccLast[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"01FF"
    )
        port map (
      I0 => stateStream(0),
      I1 => stateStream(1),
      I2 => stateStream(2),
      I3 => \^rng_reg_0\,
      O => enAccbuf11_out
    );
\colaccLast_reg[0]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk_sig,
      CE => tkst,
      D => colaccLast0(0),
      PRE => AR(0),
      Q => rowaccLast(0)
    );
\colaccLast_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => colaccLast0(1),
      Q => rowaccLast(1)
    );
\colaccLast_reg[2]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk_sig,
      CE => tkst,
      D => colaccLast0(2),
      PRE => AR(0),
      Q => rowaccLast(2)
    );
\colaccLast_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => colaccLast0(3),
      Q => rowaccLast(3)
    );
\colacc[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \colacc[3]_i_4_n_0\,
      I1 => colacc(0),
      O => \colacc[0]_i_1_n_0\
    );
\colacc[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \colacc[3]_i_4_n_0\,
      I1 => colacc(0),
      I2 => colacc(1),
      O => \colacc[1]_i_1_n_0\
    );
\colacc[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \colacc[3]_i_4_n_0\,
      I1 => colacc(0),
      I2 => colacc(1),
      I3 => colacc(2),
      O => \colacc[2]_i_1_n_0\
    );
\colacc[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4540"
    )
        port map (
      I0 => \colacc[3]_i_3_n_0\,
      I1 => rgbVideoinToManyAXIS_tvalid,
      I2 => \^rgbnotgray_reg_0\,
      I3 => grayVideoinToManyAXIS_tvalid,
      I4 => enAccbuf11_out,
      O => \colacc[3]_i_1_n_0\
    );
\colacc[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \colacc[3]_i_4_n_0\,
      I1 => colacc(2),
      I2 => colacc(1),
      I3 => colacc(0),
      I4 => colacc(3),
      O => \colacc[3]_i_2_n_0\
    );
\colacc[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => stateStream(2),
      I1 => stateStream(1),
      I2 => stateStream(0),
      O => \colacc[3]_i_3_n_0\
    );
\colacc[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44444440"
    )
        port map (
      I0 => \^enaccbuf0\,
      I1 => \^rng_reg_0\,
      I2 => stateStream(2),
      I3 => stateStream(1),
      I4 => stateStream(0),
      O => \colacc[3]_i_4_n_0\
    );
\colacc[3]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"90090000"
    )
        port map (
      I0 => rowaccLast(1),
      I1 => colacc(1),
      I2 => rowaccLast(2),
      I3 => colacc(2),
      I4 => \colacc[3]_i_6_n_0\,
      O => \^enaccbuf0\
    );
\colacc[3]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => colacc(3),
      I1 => rowaccLast(3),
      I2 => colacc(0),
      I3 => rowaccLast(0),
      O => \colacc[3]_i_6_n_0\
    );
\colacc_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \colacc[0]_i_1_n_0\,
      Q => colacc(0)
    );
\colacc_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \colacc[1]_i_1_n_0\,
      Q => colacc(1)
    );
\colacc_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \colacc[2]_i_1_n_0\,
      Q => colacc(2)
    );
\colacc_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colacc[3]_i_1_n_0\,
      CLR => AR(0),
      D => \colacc[3]_i_2_n_0\,
      Q => colacc(3)
    );
decim10: unisim.vcomponents.DSP48E2
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AMULTSEL => "A",
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      AUTORESET_PRIORITY => "RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BMULTSEL => "B",
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREADDINSEL => "A",
      PREG => 0,
      RND => X"000000000000",
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48",
      USE_WIDEXOR => "FALSE",
      XORSIMD => "XOR24_48_96"
    )
        port map (
      A(29 downto 20) => B"0000000000",
      A(19) => \acc1_reg_n_0_[19]\,
      A(18) => \acc1_reg_n_0_[18]\,
      A(17) => \acc1_reg_n_0_[17]\,
      A(16) => \acc1_reg_n_0_[16]\,
      A(15) => \acc1_reg_n_0_[15]\,
      A(14) => \acc1_reg_n_0_[14]\,
      A(13) => \acc1_reg_n_0_[13]\,
      A(12) => \acc1_reg_n_0_[12]\,
      A(11) => \acc1_reg_n_0_[11]\,
      A(10) => \acc1_reg_n_0_[10]\,
      A(9) => \acc1_reg_n_0_[9]\,
      A(8) => \acc1_reg_n_0_[8]\,
      A(7) => \acc1_reg_n_0_[7]\,
      A(6) => \acc1_reg_n_0_[6]\,
      A(5) => \acc1_reg_n_0_[5]\,
      A(4) => \acc1_reg_n_0_[4]\,
      A(3) => \acc1_reg_n_0_[3]\,
      A(2) => \acc1_reg_n_0_[2]\,
      A(1) => \acc1_reg_n_0_[1]\,
      A(0) => \acc1_reg_n_0_[0]\,
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => NLW_decim10_ACOUT_UNCONNECTED(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17 downto 11) => B"0000000",
      B(10 downto 0) => edge2(10 downto 0),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => NLW_decim10_BCOUT_UNCONNECTED(17 downto 0),
      C(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      CARRYCASCIN => '0',
      CARRYCASCOUT => NLW_decim10_CARRYCASCOUT_UNCONNECTED,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => NLW_decim10_CARRYOUT_UNCONNECTED(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(26 downto 0) => B"000000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => NLW_decim10_MULTSIGNOUT_UNCONNECTED,
      OPMODE(8 downto 0) => B"000000101",
      OVERFLOW => NLW_decim10_OVERFLOW_UNCONNECTED,
      P(47 downto 31) => NLW_decim10_P_UNCONNECTED(47 downto 31),
      P(30) => decim10_n_75,
      P(29) => decim10_n_76,
      P(28) => decim10_n_77,
      P(27) => decim10_n_78,
      P(26) => decim10_n_79,
      P(25) => decim10_n_80,
      P(24) => decim10_n_81,
      P(23) => decim10_n_82,
      P(22) => decim10_n_83,
      P(21) => decim10_n_84,
      P(20) => decim10_n_85,
      P(19) => decim10_n_86,
      P(18) => decim10_n_87,
      P(17) => decim10_n_88,
      P(16) => decim10_n_89,
      P(15) => decim10_n_90,
      P(14) => decim10_n_91,
      P(13) => decim10_n_92,
      P(12) => decim10_n_93,
      P(11) => decim10_n_94,
      P(10) => decim10_n_95,
      P(9) => decim10_n_96,
      P(8) => decim10_n_97,
      P(7) => decim10_n_98,
      P(6) => decim10_n_99,
      P(5) => decim10_n_100,
      P(4) => decim10_n_101,
      P(3) => decim10_n_102,
      P(2) => decim10_n_103,
      P(1) => decim10_n_104,
      P(0) => decim10_n_105,
      PATTERNBDETECT => NLW_decim10_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_decim10_PATTERNDETECT_UNCONNECTED,
      PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      PCOUT(47 downto 0) => NLW_decim10_PCOUT_UNCONNECTED(47 downto 0),
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => NLW_decim10_UNDERFLOW_UNCONNECTED,
      XOROUT(7 downto 0) => NLW_decim10_XOROUT_UNCONNECTED(7 downto 0)
    );
\decim1[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim10_n_89,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim1[16]_i_1_n_0\
    );
\decim1[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim10_n_88,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim1[17]_i_1_n_0\
    );
\decim1[18]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim10_n_87,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim1[18]_i_1_n_0\
    );
\decim1[19]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim10_n_86,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim1[19]_i_1_n_0\
    );
\decim1[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim10_n_85,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim1[20]_i_1_n_0\
    );
\decim1[21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim10_n_84,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim1[21]_i_1_n_0\
    );
\decim1[22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim10_n_83,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim1[22]_i_1_n_0\
    );
\decim1[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim10_n_82,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim1[23]_i_1_n_0\
    );
\decim1_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim1[16]_i_1_n_0\,
      Q => decim1(16)
    );
\decim1_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim1[17]_i_1_n_0\,
      Q => decim1(17)
    );
\decim1_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim1[18]_i_1_n_0\,
      Q => decim1(18)
    );
\decim1_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim1[19]_i_1_n_0\,
      Q => decim1(19)
    );
\decim1_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim1[20]_i_1_n_0\,
      Q => decim1(20)
    );
\decim1_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim1[21]_i_1_n_0\,
      Q => decim1(21)
    );
\decim1_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim1[22]_i_1_n_0\,
      Q => decim1(22)
    );
\decim1_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim1[23]_i_1_n_0\,
      Q => decim1(23)
    );
decim20: unisim.vcomponents.DSP48E2
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AMULTSEL => "A",
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      AUTORESET_PRIORITY => "RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BMULTSEL => "B",
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREADDINSEL => "A",
      PREG => 0,
      RND => X"000000000000",
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48",
      USE_WIDEXOR => "FALSE",
      XORSIMD => "XOR24_48_96"
    )
        port map (
      A(29 downto 20) => B"0000000000",
      A(19) => \acc2_reg_n_0_[19]\,
      A(18) => \acc2_reg_n_0_[18]\,
      A(17) => \acc2_reg_n_0_[17]\,
      A(16) => \acc2_reg_n_0_[16]\,
      A(15) => \acc2_reg_n_0_[15]\,
      A(14) => \acc2_reg_n_0_[14]\,
      A(13) => \acc2_reg_n_0_[13]\,
      A(12) => \acc2_reg_n_0_[12]\,
      A(11) => \acc2_reg_n_0_[11]\,
      A(10) => \acc2_reg_n_0_[10]\,
      A(9) => \acc2_reg_n_0_[9]\,
      A(8) => \acc2_reg_n_0_[8]\,
      A(7) => \acc2_reg_n_0_[7]\,
      A(6) => \acc2_reg_n_0_[6]\,
      A(5) => \acc2_reg_n_0_[5]\,
      A(4) => \acc2_reg_n_0_[4]\,
      A(3) => \acc2_reg_n_0_[3]\,
      A(2) => \acc2_reg_n_0_[2]\,
      A(1) => \acc2_reg_n_0_[1]\,
      A(0) => \acc2_reg_n_0_[0]\,
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => NLW_decim20_ACOUT_UNCONNECTED(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17 downto 11) => B"0000000",
      B(10 downto 0) => edge2(10 downto 0),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => NLW_decim20_BCOUT_UNCONNECTED(17 downto 0),
      C(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      CARRYCASCIN => '0',
      CARRYCASCOUT => NLW_decim20_CARRYCASCOUT_UNCONNECTED,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => NLW_decim20_CARRYOUT_UNCONNECTED(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(26 downto 0) => B"000000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => NLW_decim20_MULTSIGNOUT_UNCONNECTED,
      OPMODE(8 downto 0) => B"000000101",
      OVERFLOW => NLW_decim20_OVERFLOW_UNCONNECTED,
      P(47 downto 31) => NLW_decim20_P_UNCONNECTED(47 downto 31),
      P(30) => decim20_n_75,
      P(29) => decim20_n_76,
      P(28) => decim20_n_77,
      P(27) => decim20_n_78,
      P(26) => decim20_n_79,
      P(25) => decim20_n_80,
      P(24) => decim20_n_81,
      P(23) => decim20_n_82,
      P(22) => decim20_n_83,
      P(21) => decim20_n_84,
      P(20) => decim20_n_85,
      P(19) => decim20_n_86,
      P(18) => decim20_n_87,
      P(17) => decim20_n_88,
      P(16) => decim20_n_89,
      P(15) => decim20_n_90,
      P(14) => decim20_n_91,
      P(13) => decim20_n_92,
      P(12) => decim20_n_93,
      P(11) => decim20_n_94,
      P(10) => decim20_n_95,
      P(9) => decim20_n_96,
      P(8) => decim20_n_97,
      P(7) => decim20_n_98,
      P(6) => decim20_n_99,
      P(5) => decim20_n_100,
      P(4) => decim20_n_101,
      P(3) => decim20_n_102,
      P(2) => decim20_n_103,
      P(1) => decim20_n_104,
      P(0) => decim20_n_105,
      PATTERNBDETECT => NLW_decim20_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_decim20_PATTERNDETECT_UNCONNECTED,
      PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      PCOUT(47 downto 0) => NLW_decim20_PCOUT_UNCONNECTED(47 downto 0),
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => NLW_decim20_UNDERFLOW_UNCONNECTED,
      XOROUT(7 downto 0) => NLW_decim20_XOROUT_UNCONNECTED(7 downto 0)
    );
\decim2[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim20_n_89,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim2[16]_i_1_n_0\
    );
\decim2[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim20_n_88,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim2[17]_i_1_n_0\
    );
\decim2[18]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim20_n_87,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim2[18]_i_1_n_0\
    );
\decim2[19]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim20_n_86,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim2[19]_i_1_n_0\
    );
\decim2[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim20_n_85,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim2[20]_i_1_n_0\
    );
\decim2[21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim20_n_84,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim2[21]_i_1_n_0\
    );
\decim2[22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim20_n_83,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim2[22]_i_1_n_0\
    );
\decim2[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"33BF"
    )
        port map (
      I0 => strbStore_reg_n_0,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => decim2
    );
\decim2[23]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8880"
    )
        port map (
      I0 => decim20_n_82,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^statestore_reg[1]_0\(1),
      O => \decim2[23]_i_2_n_0\
    );
\decim2_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim2[16]_i_1_n_0\,
      Q => \decim2_reg_n_0_[16]\
    );
\decim2_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim2[17]_i_1_n_0\,
      Q => \decim2_reg_n_0_[17]\
    );
\decim2_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim2[18]_i_1_n_0\,
      Q => \decim2_reg_n_0_[18]\
    );
\decim2_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim2[19]_i_1_n_0\,
      Q => \decim2_reg_n_0_[19]\
    );
\decim2_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim2[20]_i_1_n_0\,
      Q => \decim2_reg_n_0_[20]\
    );
\decim2_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim2[21]_i_1_n_0\,
      Q => \decim2_reg_n_0_[21]\
    );
\decim2_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim2[22]_i_1_n_0\,
      Q => \decim2_reg_n_0_[22]\
    );
\decim2_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => decim2,
      CLR => AR(0),
      D => \decim2[23]_i_2_n_0\,
      Q => \decim2_reg_n_0_[23]\
    );
\decimLast[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => Q(0),
      O => minusOp(0)
    );
\decimLast[15]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D(7),
      O => \decimLast[15]_i_2_n_0\
    );
\decimLast[15]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D(6),
      O => \decimLast[15]_i_3_n_0\
    );
\decimLast[15]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D(5),
      O => \decimLast[15]_i_4_n_0\
    );
\decimLast[15]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D(4),
      O => \decimLast[15]_i_5_n_0\
    );
\decimLast[15]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D(3),
      O => \decimLast[15]_i_6_n_0\
    );
\decimLast[15]_i_7\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D(2),
      O => \decimLast[15]_i_7_n_0\
    );
\decimLast[15]_i_8\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D(1),
      O => \decimLast[15]_i_8_n_0\
    );
\decimLast[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => D(0),
      O => S(7)
    );
\decimLast[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => Q(7),
      O => S(6)
    );
\decimLast[8]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => Q(6),
      O => S(5)
    );
\decimLast[8]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => Q(5),
      O => S(4)
    );
\decimLast[8]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => Q(4),
      O => S(3)
    );
\decimLast[8]_i_7\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => Q(3),
      O => S(2)
    );
\decimLast[8]_i_8\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => Q(2),
      O => S(1)
    );
\decimLast[8]_i_9\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => Q(1),
      O => S(0)
    );
\decimLast_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => minusOp(0),
      Q => decimLast(0)
    );
\decimLast_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => minusOp(10),
      Q => decimLast(10)
    );
\decimLast_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => minusOp(11),
      Q => decimLast(11)
    );
\decimLast_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => minusOp(12),
      Q => decimLast(12)
    );
\decimLast_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => minusOp(13),
      Q => decimLast(13)
    );
\decimLast_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => minusOp(14),
      Q => decimLast(14)
    );
\decimLast_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => minusOp(15),
      Q => decimLast(15)
    );
\decimLast_reg[15]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => CO(0),
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_decimLast_reg[15]_i_1_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \decimLast_reg[15]_i_1_n_2\,
      CO(4) => \decimLast_reg[15]_i_1_n_3\,
      CO(3) => \decimLast_reg[15]_i_1_n_4\,
      CO(2) => \decimLast_reg[15]_i_1_n_5\,
      CO(1) => \decimLast_reg[15]_i_1_n_6\,
      CO(0) => \decimLast_reg[15]_i_1_n_7\,
      DI(7 downto 6) => B"00",
      DI(5 downto 0) => D(6 downto 1),
      O(7) => \NLW_decimLast_reg[15]_i_1_O_UNCONNECTED\(7),
      O(6 downto 0) => minusOp(15 downto 9),
      S(7) => '0',
      S(6) => \decimLast[15]_i_2_n_0\,
      S(5) => \decimLast[15]_i_3_n_0\,
      S(4) => \decimLast[15]_i_4_n_0\,
      S(3) => \decimLast[15]_i_5_n_0\,
      S(2) => \decimLast[15]_i_6_n_0\,
      S(1) => \decimLast[15]_i_7_n_0\,
      S(0) => \decimLast[15]_i_8_n_0\
    );
\decimLast_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => \decimLast_reg[8]_0\(0),
      Q => decimLast(1)
    );
\decimLast_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => \decimLast_reg[8]_0\(1),
      Q => decimLast(2)
    );
\decimLast_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => \decimLast_reg[8]_0\(2),
      Q => decimLast(3)
    );
\decimLast_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => \decimLast_reg[8]_0\(3),
      Q => decimLast(4)
    );
\decimLast_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => \decimLast_reg[8]_0\(4),
      Q => decimLast(5)
    );
\decimLast_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => \decimLast_reg[8]_0\(5),
      Q => decimLast(6)
    );
\decimLast_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => \decimLast_reg[8]_0\(6),
      Q => decimLast(7)
    );
\decimLast_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => \decimLast_reg[8]_0\(7),
      Q => decimLast(8)
    );
\decimLast_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => minusOp(9),
      Q => decimLast(9)
    );
\dwrAccbuf[59]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F0F2F0F0F0FFF"
    )
        port map (
      I0 => enAccbuf_reg_0,
      I1 => \stateStream[2]_i_4_n_0\,
      I2 => \^rng_reg_0\,
      I3 => stateStream(2),
      I4 => stateStream(1),
      I5 => stateStream(0),
      O => \dwrAccbuf[59]_i_1_n_0\
    );
\dwrAccbuf_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(0),
      Q => dwrA(0)
    );
\dwrAccbuf_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(10),
      Q => dwrA(10)
    );
\dwrAccbuf_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(11),
      Q => dwrA(11)
    );
\dwrAccbuf_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(12),
      Q => dwrA(12)
    );
\dwrAccbuf_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(13),
      Q => dwrA(13)
    );
\dwrAccbuf_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(14),
      Q => dwrA(14)
    );
\dwrAccbuf_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(15),
      Q => dwrA(15)
    );
\dwrAccbuf_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(16),
      Q => dwrA(16)
    );
\dwrAccbuf_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(17),
      Q => dwrA(17)
    );
\dwrAccbuf_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(18),
      Q => dwrA(18)
    );
\dwrAccbuf_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(19),
      Q => dwrA(19)
    );
\dwrAccbuf_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(1),
      Q => dwrA(1)
    );
\dwrAccbuf_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(0),
      Q => dwrA(20)
    );
\dwrAccbuf_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(1),
      Q => dwrA(21)
    );
\dwrAccbuf_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(2),
      Q => dwrA(22)
    );
\dwrAccbuf_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(3),
      Q => dwrA(23)
    );
\dwrAccbuf_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(4),
      Q => dwrA(24)
    );
\dwrAccbuf_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(5),
      Q => dwrA(25)
    );
\dwrAccbuf_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(6),
      Q => dwrA(26)
    );
\dwrAccbuf_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(7),
      Q => dwrA(27)
    );
\dwrAccbuf_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(8),
      Q => dwrA(28)
    );
\dwrAccbuf_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(9),
      Q => dwrA(29)
    );
\dwrAccbuf_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(2),
      Q => dwrA(2)
    );
\dwrAccbuf_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(10),
      Q => dwrA(30)
    );
\dwrAccbuf_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(11),
      Q => dwrA(31)
    );
\dwrAccbuf_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(12),
      Q => dwrA(32)
    );
\dwrAccbuf_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(13),
      Q => dwrA(33)
    );
\dwrAccbuf_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(14),
      Q => dwrA(34)
    );
\dwrAccbuf_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(15),
      Q => dwrA(35)
    );
\dwrAccbuf_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(16),
      Q => dwrA(36)
    );
\dwrAccbuf_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(17),
      Q => dwrA(37)
    );
\dwrAccbuf_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(18),
      Q => dwrA(38)
    );
\dwrAccbuf_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc1(19),
      Q => dwrA(39)
    );
\dwrAccbuf_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(3),
      Q => dwrA(3)
    );
\dwrAccbuf_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_19,
      Q => dwrA(40)
    );
\dwrAccbuf_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_18,
      Q => dwrA(41)
    );
\dwrAccbuf_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_17,
      Q => dwrA(42)
    );
\dwrAccbuf_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_16,
      Q => dwrA(43)
    );
\dwrAccbuf_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_15,
      Q => dwrA(44)
    );
\dwrAccbuf_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_14,
      Q => dwrA(45)
    );
\dwrAccbuf_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_13,
      Q => dwrA(46)
    );
\dwrAccbuf_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_12,
      Q => dwrA(47)
    );
\dwrAccbuf_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_11,
      Q => dwrA(48)
    );
\dwrAccbuf_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_10,
      Q => dwrA(49)
    );
\dwrAccbuf_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(4),
      Q => dwrA(4)
    );
\dwrAccbuf_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_9,
      Q => dwrA(50)
    );
\dwrAccbuf_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_8,
      Q => dwrA(51)
    );
\dwrAccbuf_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_7,
      Q => dwrA(52)
    );
\dwrAccbuf_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_6,
      Q => dwrA(53)
    );
\dwrAccbuf_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_5,
      Q => dwrA(54)
    );
\dwrAccbuf_reg[55]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_4,
      Q => dwrA(55)
    );
\dwrAccbuf_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_3,
      Q => dwrA(56)
    );
\dwrAccbuf_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_2,
      Q => dwrA(57)
    );
\dwrAccbuf_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_1,
      Q => dwrA(58)
    );
\dwrAccbuf_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => myAccbuf_n_0,
      Q => dwrA(59)
    );
\dwrAccbuf_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(5),
      Q => dwrA(5)
    );
\dwrAccbuf_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(6),
      Q => dwrA(6)
    );
\dwrAccbuf_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(7),
      Q => dwrA(7)
    );
\dwrAccbuf_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(8),
      Q => dwrA(8)
    );
\dwrAccbuf_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrAccbuf[59]_i_1_n_0\,
      CLR => AR(0),
      D => acc0(9),
      Q => dwrA(9)
    );
dwrPvwbuf0: unisim.vcomponents.DSP48E2
    generic map(
      ACASCREG => 0,
      ADREG => 1,
      ALUMODEREG => 0,
      AMULTSEL => "A",
      AREG => 0,
      AUTORESET_PATDET => "NO_RESET",
      AUTORESET_PRIORITY => "RESET",
      A_INPUT => "DIRECT",
      BCASCREG => 0,
      BMULTSEL => "B",
      BREG => 0,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 0,
      CREG => 1,
      DREG => 1,
      INMODEREG => 0,
      MASK => X"3FFFFFFFFFFF",
      MREG => 0,
      OPMODEREG => 0,
      PATTERN => X"000000000000",
      PREADDINSEL => "A",
      PREG => 0,
      RND => X"000000000000",
      SEL_MASK => "MASK",
      SEL_PATTERN => "PATTERN",
      USE_MULT => "MULTIPLY",
      USE_PATTERN_DETECT => "NO_PATDET",
      USE_SIMD => "ONE48",
      USE_WIDEXOR => "FALSE",
      XORSIMD => "XOR24_48_96"
    )
        port map (
      A(29 downto 20) => B"0000000000",
      A(19) => \acc0_reg_n_0_[19]\,
      A(18) => \acc0_reg_n_0_[18]\,
      A(17) => \acc0_reg_n_0_[17]\,
      A(16) => \acc0_reg_n_0_[16]\,
      A(15) => \acc0_reg_n_0_[15]\,
      A(14) => \acc0_reg_n_0_[14]\,
      A(13) => \acc0_reg_n_0_[13]\,
      A(12) => \acc0_reg_n_0_[12]\,
      A(11) => \acc0_reg_n_0_[11]\,
      A(10) => \acc0_reg_n_0_[10]\,
      A(9) => \acc0_reg_n_0_[9]\,
      A(8) => \acc0_reg_n_0_[8]\,
      A(7) => \acc0_reg_n_0_[7]\,
      A(6) => \acc0_reg_n_0_[6]\,
      A(5) => \acc0_reg_n_0_[5]\,
      A(4) => \acc0_reg_n_0_[4]\,
      A(3) => \acc0_reg_n_0_[3]\,
      A(2) => \acc0_reg_n_0_[2]\,
      A(1) => \acc0_reg_n_0_[1]\,
      A(0) => \acc0_reg_n_0_[0]\,
      ACIN(29 downto 0) => B"000000000000000000000000000000",
      ACOUT(29 downto 0) => NLW_dwrPvwbuf0_ACOUT_UNCONNECTED(29 downto 0),
      ALUMODE(3 downto 0) => B"0000",
      B(17 downto 11) => B"0000000",
      B(10 downto 0) => edge2(10 downto 0),
      BCIN(17 downto 0) => B"000000000000000000",
      BCOUT(17 downto 0) => NLW_dwrPvwbuf0_BCOUT_UNCONNECTED(17 downto 0),
      C(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      CARRYCASCIN => '0',
      CARRYCASCOUT => NLW_dwrPvwbuf0_CARRYCASCOUT_UNCONNECTED,
      CARRYIN => '0',
      CARRYINSEL(2 downto 0) => B"000",
      CARRYOUT(3 downto 0) => NLW_dwrPvwbuf0_CARRYOUT_UNCONNECTED(3 downto 0),
      CEA1 => '0',
      CEA2 => '0',
      CEAD => '0',
      CEALUMODE => '0',
      CEB1 => '0',
      CEB2 => '0',
      CEC => '0',
      CECARRYIN => '0',
      CECTRL => '0',
      CED => '0',
      CEINMODE => '0',
      CEM => '0',
      CEP => '0',
      CLK => '0',
      D(26 downto 0) => B"000000000000000000000000000",
      INMODE(4 downto 0) => B"00000",
      MULTSIGNIN => '0',
      MULTSIGNOUT => NLW_dwrPvwbuf0_MULTSIGNOUT_UNCONNECTED,
      OPMODE(8 downto 0) => B"000000101",
      OVERFLOW => NLW_dwrPvwbuf0_OVERFLOW_UNCONNECTED,
      P(47 downto 31) => NLW_dwrPvwbuf0_P_UNCONNECTED(47 downto 31),
      P(30) => dwrPvwbuf0_n_75,
      P(29) => dwrPvwbuf0_n_76,
      P(28) => dwrPvwbuf0_n_77,
      P(27) => dwrPvwbuf0_n_78,
      P(26) => dwrPvwbuf0_n_79,
      P(25) => dwrPvwbuf0_n_80,
      P(24) => dwrPvwbuf0_n_81,
      P(23) => dwrPvwbuf0_n_82,
      P(22) => dwrPvwbuf0_n_83,
      P(21) => dwrPvwbuf0_n_84,
      P(20) => dwrPvwbuf0_n_85,
      P(19) => dwrPvwbuf0_n_86,
      P(18) => dwrPvwbuf0_n_87,
      P(17) => dwrPvwbuf0_n_88,
      P(16) => dwrPvwbuf0_n_89,
      P(15) => dwrPvwbuf0_n_90,
      P(14) => dwrPvwbuf0_n_91,
      P(13) => dwrPvwbuf0_n_92,
      P(12) => dwrPvwbuf0_n_93,
      P(11) => dwrPvwbuf0_n_94,
      P(10) => dwrPvwbuf0_n_95,
      P(9) => dwrPvwbuf0_n_96,
      P(8) => dwrPvwbuf0_n_97,
      P(7) => dwrPvwbuf0_n_98,
      P(6) => dwrPvwbuf0_n_99,
      P(5) => dwrPvwbuf0_n_100,
      P(4) => dwrPvwbuf0_n_101,
      P(3) => dwrPvwbuf0_n_102,
      P(2) => dwrPvwbuf0_n_103,
      P(1) => dwrPvwbuf0_n_104,
      P(0) => dwrPvwbuf0_n_105,
      PATTERNBDETECT => NLW_dwrPvwbuf0_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_dwrPvwbuf0_PATTERNDETECT_UNCONNECTED,
      PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      PCOUT(47 downto 0) => NLW_dwrPvwbuf0_PCOUT_UNCONNECTED(47 downto 0),
      RSTA => '0',
      RSTALLCARRYIN => '0',
      RSTALUMODE => '0',
      RSTB => '0',
      RSTC => '0',
      RSTCTRL => '0',
      RSTD => '0',
      RSTINMODE => '0',
      RSTM => '0',
      RSTP => '0',
      UNDERFLOW => NLW_dwrPvwbuf0_UNDERFLOW_UNCONNECTED,
      XOROUT(7 downto 0) => NLW_dwrPvwbuf0_XOROUT_UNCONNECTED(7 downto 0)
    );
\dwrPvwbuf[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00E4E4"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => decim1(16),
      I2 => \decim2_reg_n_0_[16]\,
      I3 => dwrPvwbuf0_n_89,
      I4 => \dwrPvwbuf[7]_i_2_n_0\,
      I5 => aPvwbuf1,
      O => p_1_in(0)
    );
\dwrPvwbuf[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00E4E4"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => decim1(17),
      I2 => \decim2_reg_n_0_[17]\,
      I3 => dwrPvwbuf0_n_88,
      I4 => \dwrPvwbuf[7]_i_2_n_0\,
      I5 => aPvwbuf1,
      O => p_1_in(1)
    );
\dwrPvwbuf[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00E4E4"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => decim1(18),
      I2 => \decim2_reg_n_0_[18]\,
      I3 => dwrPvwbuf0_n_87,
      I4 => \dwrPvwbuf[7]_i_2_n_0\,
      I5 => aPvwbuf1,
      O => p_1_in(2)
    );
\dwrPvwbuf[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00E4E4"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => decim1(19),
      I2 => \decim2_reg_n_0_[19]\,
      I3 => dwrPvwbuf0_n_86,
      I4 => \dwrPvwbuf[7]_i_2_n_0\,
      I5 => aPvwbuf1,
      O => p_1_in(3)
    );
\dwrPvwbuf[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00E4E4"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => decim1(20),
      I2 => \decim2_reg_n_0_[20]\,
      I3 => dwrPvwbuf0_n_85,
      I4 => \dwrPvwbuf[7]_i_2_n_0\,
      I5 => aPvwbuf1,
      O => p_1_in(4)
    );
\dwrPvwbuf[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00E4E4"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => decim1(21),
      I2 => \decim2_reg_n_0_[21]\,
      I3 => dwrPvwbuf0_n_84,
      I4 => \dwrPvwbuf[7]_i_2_n_0\,
      I5 => aPvwbuf1,
      O => p_1_in(5)
    );
\dwrPvwbuf[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00E4E4"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => decim1(22),
      I2 => \decim2_reg_n_0_[22]\,
      I3 => dwrPvwbuf0_n_83,
      I4 => \dwrPvwbuf[7]_i_2_n_0\,
      I5 => aPvwbuf1,
      O => p_1_in(6)
    );
\dwrPvwbuf[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF00E4E4"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => decim1(23),
      I2 => \decim2_reg_n_0_[23]\,
      I3 => dwrPvwbuf0_n_82,
      I4 => \dwrPvwbuf[7]_i_2_n_0\,
      I5 => aPvwbuf1,
      O => p_1_in(7)
    );
\dwrPvwbuf[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^statestore_reg[1]_0\(0),
      I1 => \^statestore_reg[1]_0\(1),
      O => \dwrPvwbuf[7]_i_2_n_0\
    );
\dwrPvwbuf[7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1F"
    )
        port map (
      I0 => \^statestore_reg[1]_0\(1),
      I1 => \^statestore_reg[1]_0\(0),
      I2 => \^rng_reg_0\,
      O => aPvwbuf1
    );
\dwrPvwbuf_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i[1]_i_1__2_n_0\,
      CLR => AR(0),
      D => p_1_in(0),
      Q => \dwrPvwbuf_reg_n_0_[0]\
    );
\dwrPvwbuf_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i[1]_i_1__2_n_0\,
      CLR => AR(0),
      D => p_1_in(1),
      Q => \dwrPvwbuf_reg_n_0_[1]\
    );
\dwrPvwbuf_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i[1]_i_1__2_n_0\,
      CLR => AR(0),
      D => p_1_in(2),
      Q => \dwrPvwbuf_reg_n_0_[2]\
    );
\dwrPvwbuf_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i[1]_i_1__2_n_0\,
      CLR => AR(0),
      D => p_1_in(3),
      Q => \dwrPvwbuf_reg_n_0_[3]\
    );
\dwrPvwbuf_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i[1]_i_1__2_n_0\,
      CLR => AR(0),
      D => p_1_in(4),
      Q => \dwrPvwbuf_reg_n_0_[4]\
    );
\dwrPvwbuf_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i[1]_i_1__2_n_0\,
      CLR => AR(0),
      D => p_1_in(5),
      Q => \dwrPvwbuf_reg_n_0_[5]\
    );
\dwrPvwbuf_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i[1]_i_1__2_n_0\,
      CLR => AR(0),
      D => p_1_in(6),
      Q => \dwrPvwbuf_reg_n_0_[6]\
    );
\dwrPvwbuf_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i[1]_i_1__2_n_0\,
      CLR => AR(0),
      D => p_1_in(7),
      Q => \dwrPvwbuf_reg_n_0_[7]\
    );
\edge2_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => D(8),
      Q => edge2(0)
    );
\edge2_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => D(18),
      Q => edge2(10)
    );
\edge2_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => D(9),
      Q => edge2(1)
    );
\edge2_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => D(10),
      PRE => AR(0),
      Q => edge2(2)
    );
\edge2_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => D(11),
      Q => edge2(3)
    );
\edge2_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => D(12),
      Q => edge2(4)
    );
\edge2_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => D(13),
      PRE => AR(0),
      Q => edge2(5)
    );
\edge2_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => D(14),
      Q => edge2(6)
    );
\edge2_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => D(15),
      Q => edge2(7)
    );
\edge2_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => D(16),
      Q => edge2(8)
    );
\edge2_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => D(17),
      Q => edge2(9)
    );
\edge_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => D(19),
      Q => \edge_reg_n_0_[0]\
    );
\edge_reg[1]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => D(20),
      PRE => AR(0),
      Q => \edge_reg_n_0_[1]\
    );
\edge_reg[2]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      D => D(21),
      PRE => AR(0),
      Q => \edge_reg_n_0_[2]\
    );
\edge_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => D(22),
      Q => \edge_reg_n_0_[3]\
    );
\edge_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => D(23),
      Q => \edge_reg_n_0_[4]\
    );
enAccbuf_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000FFFF40000000"
    )
        port map (
      I0 => decimStateStream_dbg(5),
      I1 => \^rng_reg_0\,
      I2 => stateStream(0),
      I3 => enAccbuf_reg_0,
      I4 => enAccbuf_i_3_n_0,
      I5 => enAccbuf_reg_n_0,
      O => enAccbuf_i_1_n_0
    );
enAccbuf_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => stateStream(1),
      I1 => stateStream(2),
      O => decimStateStream_dbg(5)
    );
enAccbuf_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ABABAFAB"
    )
        port map (
      I0 => row,
      I1 => enAccbuf1,
      I2 => \colacc[3]_i_3_n_0\,
      I3 => \^enaccbuf0\,
      I4 => \stateStream[2]_i_4_n_0\,
      O => enAccbuf_i_3_n_0
    );
enAccbuf_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => enAccbuf_i_1_n_0,
      Q => enAccbuf_reg_n_0
    );
\i[0]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^statestore_reg[1]_0\(1),
      I1 => \^rng_reg_0\,
      I2 => \i_reg_n_0_[0]\,
      O => \i[0]_i_1__4_n_0\
    );
\i[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"37FF07FF"
    )
        port map (
      I0 => \stateStore[0]_i_2_n_0\,
      I1 => \^statestore_reg[1]_0\(1),
      I2 => \^statestore_reg[1]_0\(0),
      I3 => \^rng_reg_0\,
      I4 => strbStore_reg_n_0,
      O => \i[1]_i_1__2_n_0\
    );
\i[1]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4080"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \^statestore_reg[1]_0\(1),
      I2 => \^rng_reg_0\,
      I3 => \i_reg_n_0_[0]\,
      O => \i[1]_i_2__1_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[1]_i_1__2_n_0\,
      CLR => AR(0),
      D => \i[0]_i_1__4_n_0\,
      Q => \i_reg_n_0_[0]\
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[1]_i_1__2_n_0\,
      CLR => AR(0),
      D => \i[1]_i_2__1_n_0\,
      Q => \i_reg_n_0_[1]\
    );
\ixTExp_lcl_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => AR(0),
      D => \ixTExp_lcl_reg[3]_0\(0),
      Q => \ixTExp_lcl_reg[1]_0\(0)
    );
\ixTExp_lcl_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => AR(0),
      D => \ixTExp_lcl_reg[3]_0\(1),
      Q => \ixTExp_lcl_reg[1]_0\(1)
    );
\ixTExp_lcl_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => AR(0),
      D => \ixTExp_lcl_reg[3]_0\(2),
      Q => \ixTExp_lcl_reg_n_0_[2]\
    );
\ixTExp_lcl_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => AR(0),
      D => \ixTExp_lcl_reg[3]_0\(3),
      Q => \ixTExp_lcl_reg_n_0_[3]\
    );
myAccbuf: entity work.design_1_Vsp_core_0_0_Dpbram_size2kB_a64b64
     port map (
      D(51) => myAccbuf_n_0,
      D(50) => myAccbuf_n_1,
      D(49) => myAccbuf_n_2,
      D(48) => myAccbuf_n_3,
      D(47) => myAccbuf_n_4,
      D(46) => myAccbuf_n_5,
      D(45) => myAccbuf_n_6,
      D(44) => myAccbuf_n_7,
      D(43) => myAccbuf_n_8,
      D(42) => myAccbuf_n_9,
      D(41) => myAccbuf_n_10,
      D(40) => myAccbuf_n_11,
      D(39) => myAccbuf_n_12,
      D(38) => myAccbuf_n_13,
      D(37) => myAccbuf_n_14,
      D(36) => myAccbuf_n_15,
      D(35) => myAccbuf_n_16,
      D(34) => myAccbuf_n_17,
      D(33) => myAccbuf_n_18,
      D(32) => myAccbuf_n_19,
      D(31 downto 12) => acc1(19 downto 0),
      D(11 downto 0) => acc0(19 downto 8),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(59 downto 0) => dwrA(59 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \aAccbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \aAccbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \aAccbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \aAccbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \aAccbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \aAccbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \aAccbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \aAccbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2 downto 0) => stateStream(2 downto 0),
      DI(3 downto 0) => DI(3 downto 0),
      Q(7) => \aAccbuf_reg_n_0_[7]\,
      Q(6) => \aAccbuf_reg_n_0_[6]\,
      Q(5) => \aAccbuf_reg_n_0_[5]\,
      Q(4) => \aAccbuf_reg_n_0_[4]\,
      Q(3) => \aAccbuf_reg_n_0_[3]\,
      Q(2) => \aAccbuf_reg_n_0_[2]\,
      Q(1) => \aAccbuf_reg_n_0_[1]\,
      Q(0) => \aAccbuf_reg_n_0_[0]\,
      \acc0_lcl_reg[19]_i_2_0\ => \acc0_lcl[19]_i_7_n_0\,
      \acc0_lcl_reg[19]_i_2_1\ => \aAccbufB[7]_i_3_n_0\,
      \acc0_lcl_reg[19]_i_2_2\(19) => \acc0_lcl_reg_n_0_[19]\,
      \acc0_lcl_reg[19]_i_2_2\(18) => \acc0_lcl_reg_n_0_[18]\,
      \acc0_lcl_reg[19]_i_2_2\(17) => \acc0_lcl_reg_n_0_[17]\,
      \acc0_lcl_reg[19]_i_2_2\(16) => \acc0_lcl_reg_n_0_[16]\,
      \acc0_lcl_reg[19]_i_2_2\(15) => \acc0_lcl_reg_n_0_[15]\,
      \acc0_lcl_reg[19]_i_2_2\(14) => \acc0_lcl_reg_n_0_[14]\,
      \acc0_lcl_reg[19]_i_2_2\(13) => \acc0_lcl_reg_n_0_[13]\,
      \acc0_lcl_reg[19]_i_2_2\(12) => \acc0_lcl_reg_n_0_[12]\,
      \acc0_lcl_reg[19]_i_2_2\(11) => \acc0_lcl_reg_n_0_[11]\,
      \acc0_lcl_reg[19]_i_2_2\(10) => \acc0_lcl_reg_n_0_[10]\,
      \acc0_lcl_reg[19]_i_2_2\(9) => \acc0_lcl_reg_n_0_[9]\,
      \acc0_lcl_reg[19]_i_2_2\(8) => \acc0_lcl_reg_n_0_[8]\,
      \acc0_lcl_reg[19]_i_2_2\(7) => \acc0_lcl_reg_n_0_[7]\,
      \acc0_lcl_reg[19]_i_2_2\(6) => \acc0_lcl_reg_n_0_[6]\,
      \acc0_lcl_reg[19]_i_2_2\(5) => \acc0_lcl_reg_n_0_[5]\,
      \acc0_lcl_reg[19]_i_2_2\(4) => \acc0_lcl_reg_n_0_[4]\,
      \acc0_lcl_reg[19]_i_2_2\(3) => \acc0_lcl_reg_n_0_[3]\,
      \acc0_lcl_reg[19]_i_2_2\(2) => \acc0_lcl_reg_n_0_[2]\,
      \acc0_lcl_reg[19]_i_2_2\(1) => \acc0_lcl_reg_n_0_[1]\,
      \acc0_lcl_reg[19]_i_2_2\(0) => \acc0_lcl_reg_n_0_[0]\,
      \acc0_lcl_reg[7]\(7 downto 0) => \acc0_lcl_reg[7]_0\(7 downto 0),
      \acc0_lcl_reg[7]_i_2\(7 downto 0) => \acc0_lcl_reg[7]_i_2\(7 downto 0),
      \acc1_lcl_reg[19]_i_2_0\(19) => \acc1_lcl_reg_n_0_[19]\,
      \acc1_lcl_reg[19]_i_2_0\(18) => \acc1_lcl_reg_n_0_[18]\,
      \acc1_lcl_reg[19]_i_2_0\(17) => \acc1_lcl_reg_n_0_[17]\,
      \acc1_lcl_reg[19]_i_2_0\(16) => \acc1_lcl_reg_n_0_[16]\,
      \acc1_lcl_reg[19]_i_2_0\(15) => \acc1_lcl_reg_n_0_[15]\,
      \acc1_lcl_reg[19]_i_2_0\(14) => \acc1_lcl_reg_n_0_[14]\,
      \acc1_lcl_reg[19]_i_2_0\(13) => \acc1_lcl_reg_n_0_[13]\,
      \acc1_lcl_reg[19]_i_2_0\(12) => \acc1_lcl_reg_n_0_[12]\,
      \acc1_lcl_reg[19]_i_2_0\(11) => \acc1_lcl_reg_n_0_[11]\,
      \acc1_lcl_reg[19]_i_2_0\(10) => \acc1_lcl_reg_n_0_[10]\,
      \acc1_lcl_reg[19]_i_2_0\(9) => \acc1_lcl_reg_n_0_[9]\,
      \acc1_lcl_reg[19]_i_2_0\(8) => \acc1_lcl_reg_n_0_[8]\,
      \acc1_lcl_reg[19]_i_2_0\(7) => \acc1_lcl_reg_n_0_[7]\,
      \acc1_lcl_reg[19]_i_2_0\(6) => \acc1_lcl_reg_n_0_[6]\,
      \acc1_lcl_reg[19]_i_2_0\(5) => \acc1_lcl_reg_n_0_[5]\,
      \acc1_lcl_reg[19]_i_2_0\(4) => \acc1_lcl_reg_n_0_[4]\,
      \acc1_lcl_reg[19]_i_2_0\(3) => \acc1_lcl_reg_n_0_[3]\,
      \acc1_lcl_reg[19]_i_2_0\(2) => \acc1_lcl_reg_n_0_[2]\,
      \acc1_lcl_reg[19]_i_2_0\(1) => \acc1_lcl_reg_n_0_[1]\,
      \acc1_lcl_reg[19]_i_2_0\(0) => \acc1_lcl_reg_n_0_[0]\,
      \acc1_lcl_reg[7]_i_2_0\ => \^rgbnotgray_reg_0\,
      \acc2_lcl_reg[15]_i_2_0\(23 downto 0) => \acc2_lcl_reg[15]_i_2\(23 downto 0),
      \acc2_lcl_reg[19]_i_2_0\(19) => \acc2_lcl_reg_n_0_[19]\,
      \acc2_lcl_reg[19]_i_2_0\(18) => \acc2_lcl_reg_n_0_[18]\,
      \acc2_lcl_reg[19]_i_2_0\(17) => \acc2_lcl_reg_n_0_[17]\,
      \acc2_lcl_reg[19]_i_2_0\(16) => \acc2_lcl_reg_n_0_[16]\,
      \acc2_lcl_reg[19]_i_2_0\(15) => \acc2_lcl_reg_n_0_[15]\,
      \acc2_lcl_reg[19]_i_2_0\(14) => \acc2_lcl_reg_n_0_[14]\,
      \acc2_lcl_reg[19]_i_2_0\(13) => \acc2_lcl_reg_n_0_[13]\,
      \acc2_lcl_reg[19]_i_2_0\(12) => \acc2_lcl_reg_n_0_[12]\,
      \acc2_lcl_reg[19]_i_2_0\(11) => \acc2_lcl_reg_n_0_[11]\,
      \acc2_lcl_reg[19]_i_2_0\(10) => \acc2_lcl_reg_n_0_[10]\,
      \acc2_lcl_reg[19]_i_2_0\(9) => \acc2_lcl_reg_n_0_[9]\,
      \acc2_lcl_reg[19]_i_2_0\(8) => \acc2_lcl_reg_n_0_[8]\,
      \acc2_lcl_reg[19]_i_2_0\(7) => \acc2_lcl_reg_n_0_[7]\,
      \acc2_lcl_reg[19]_i_2_0\(6) => \acc2_lcl_reg_n_0_[6]\,
      \acc2_lcl_reg[19]_i_2_0\(5) => \acc2_lcl_reg_n_0_[5]\,
      \acc2_lcl_reg[19]_i_2_0\(4) => \acc2_lcl_reg_n_0_[4]\,
      \acc2_lcl_reg[19]_i_2_0\(3) => \acc2_lcl_reg_n_0_[3]\,
      \acc2_lcl_reg[19]_i_2_0\(2) => \acc2_lcl_reg_n_0_[2]\,
      \acc2_lcl_reg[19]_i_2_0\(1) => \acc2_lcl_reg_n_0_[1]\,
      \acc2_lcl_reg[19]_i_2_0\(0) => \acc2_lcl_reg_n_0_[0]\,
      \acc2_reg[19]\ => \^rng_reg_0\,
      aclk_sig => aclk_sig,
      \dwrAccbuf_reg[15]\(0) => \dwrAccbuf_reg[15]_0\(0),
      ena => enAccbuf_reg_n_0
    );
myPvwbuf: entity work.\design_1_Vsp_core_0_0_Dpbram_size38kB_a8b64__xdcDup__1\
     port map (
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \dwrPvwbuf_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \dwrPvwbuf_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \dwrPvwbuf_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \dwrPvwbuf_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \dwrPvwbuf_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \dwrPvwbuf_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \dwrPvwbuf_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \dwrPvwbuf_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1 downto 0) => \^statestore_reg[1]_0\(1 downto 0),
      Q(15 downto 0) => aPvwbuf_reg(15 downto 0),
      aclk_sig => aclk_sig,
      doutb(63 downto 0) => doutb(63 downto 0),
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\(0) => enPvwbufB,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(12) => \aPvwbufB_reg_n_0_[12]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(11) => \aPvwbufB_reg_n_0_[11]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(10) => \aPvwbufB_reg_n_0_[10]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(9) => \aPvwbufB_reg_n_0_[9]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(8) => \aPvwbufB_reg_n_0_[8]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(7) => \aPvwbufB_reg_n_0_[7]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(6) => \aPvwbufB_reg_n_0_[6]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(5) => \aPvwbufB_reg_n_0_[5]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(4) => \aPvwbufB_reg_n_0_[4]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(3) => \aPvwbufB_reg_n_0_[3]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(2) => \aPvwbufB_reg_n_0_[2]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(1) => \aPvwbufB_reg_n_0_[1]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(0) => \aPvwbufB_reg_n_0_[0]\
    );
rgbNotGray_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ackInvConfig_sig,
      CLR => AR(0),
      D => hdrNotFix,
      Q => \^rgbnotgray_reg_0\
    );
rng_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => rng_reg_1,
      Q => \^rng_reg_0\
    );
\row[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \row[10]_i_3_n_0\,
      I1 => \row_reg_n_0_[0]\,
      O => \row[0]_i_1__0_n_0\
    );
\row[10]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF000080000000"
    )
        port map (
      I0 => \row[10]_i_2_n_0\,
      I1 => \row_reg_n_0_[7]\,
      I2 => \row_reg_n_0_[8]\,
      I3 => \row_reg_n_0_[9]\,
      I4 => \row[10]_i_3_n_0\,
      I5 => \row_reg_n_0_[10]\,
      O => \row[10]_i_1__0_n_0\
    );
\row[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080000000"
    )
        port map (
      I0 => \row_reg_n_0_[6]\,
      I1 => \row_reg_n_0_[5]\,
      I2 => \row_reg_n_0_[4]\,
      I3 => \row_reg_n_0_[3]\,
      I4 => \row_reg_n_0_[2]\,
      I5 => \row[5]_i_2__0_n_0\,
      O => \row[10]_i_2_n_0\
    );
\row[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7070707070707000"
    )
        port map (
      I0 => \stateStream[2]_i_4_n_0\,
      I1 => \stateStream_reg[2]_i_5_n_2\,
      I2 => \^rng_reg_0\,
      I3 => stateStream(2),
      I4 => stateStream(1),
      I5 => stateStream(0),
      O => \row[10]_i_3_n_0\
    );
\row[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \row[10]_i_3_n_0\,
      I1 => \row_reg_n_0_[0]\,
      I2 => \row_reg_n_0_[1]\,
      O => \row[1]_i_1__0_n_0\
    );
\row[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \row[10]_i_3_n_0\,
      I1 => \row_reg_n_0_[1]\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \row_reg_n_0_[2]\,
      O => \row[2]_i_1__0_n_0\
    );
\row[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \row[10]_i_3_n_0\,
      I1 => \row_reg_n_0_[0]\,
      I2 => \row_reg_n_0_[1]\,
      I3 => \row_reg_n_0_[2]\,
      I4 => \row_reg_n_0_[3]\,
      O => \row[3]_i_1__0_n_0\
    );
\row[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \row[10]_i_3_n_0\,
      I1 => \row_reg_n_0_[3]\,
      I2 => \row_reg_n_0_[2]\,
      I3 => \row_reg_n_0_[1]\,
      I4 => \row_reg_n_0_[0]\,
      I5 => \row_reg_n_0_[4]\,
      O => \row[4]_i_1__0_n_0\
    );
\row[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F000000800000"
    )
        port map (
      I0 => \row_reg_n_0_[4]\,
      I1 => \row_reg_n_0_[3]\,
      I2 => \row_reg_n_0_[2]\,
      I3 => \row[5]_i_2__0_n_0\,
      I4 => \row[10]_i_3_n_0\,
      I5 => \row_reg_n_0_[5]\,
      O => \row[5]_i_1__0_n_0\
    );
\row[5]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \row_reg_n_0_[0]\,
      I1 => \row_reg_n_0_[1]\,
      O => \row[5]_i_2__0_n_0\
    );
\row[6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"84"
    )
        port map (
      I0 => \row[9]_i_2__0_n_0\,
      I1 => \row[10]_i_3_n_0\,
      I2 => \row_reg_n_0_[6]\,
      O => \row[6]_i_1__0_n_0\
    );
\row[7]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D020"
    )
        port map (
      I0 => \row_reg_n_0_[6]\,
      I1 => \row[9]_i_2__0_n_0\,
      I2 => \row[10]_i_3_n_0\,
      I3 => \row_reg_n_0_[7]\,
      O => \row[7]_i_1__0_n_0\
    );
\row[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BF004000"
    )
        port map (
      I0 => \row[9]_i_2__0_n_0\,
      I1 => \row_reg_n_0_[6]\,
      I2 => \row_reg_n_0_[7]\,
      I3 => \row[10]_i_3_n_0\,
      I4 => \row_reg_n_0_[8]\,
      O => \row[8]_i_1__0_n_0\
    );
\row[9]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F000000800000"
    )
        port map (
      I0 => \row_reg_n_0_[8]\,
      I1 => \row_reg_n_0_[7]\,
      I2 => \row_reg_n_0_[6]\,
      I3 => \row[9]_i_2__0_n_0\,
      I4 => \row[10]_i_3_n_0\,
      I5 => \row_reg_n_0_[9]\,
      O => \row[9]_i_1__0_n_0\
    );
\row[9]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \row_reg_n_0_[0]\,
      I1 => \row_reg_n_0_[1]\,
      I2 => \row_reg_n_0_[2]\,
      I3 => \row_reg_n_0_[3]\,
      I4 => \row_reg_n_0_[4]\,
      I5 => \row_reg_n_0_[5]\,
      O => \row[9]_i_2__0_n_0\
    );
\row_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \row[0]_i_1__0_n_0\,
      Q => \row_reg_n_0_[0]\
    );
\row_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \row[10]_i_1__0_n_0\,
      Q => \row_reg_n_0_[10]\
    );
\row_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \row[1]_i_1__0_n_0\,
      Q => \row_reg_n_0_[1]\
    );
\row_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \row[2]_i_1__0_n_0\,
      Q => \row_reg_n_0_[2]\
    );
\row_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \row[3]_i_1__0_n_0\,
      Q => \row_reg_n_0_[3]\
    );
\row_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \row[4]_i_1__0_n_0\,
      Q => \row_reg_n_0_[4]\
    );
\row_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \row[5]_i_1__0_n_0\,
      Q => \row_reg_n_0_[5]\
    );
\row_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \row[6]_i_1__0_n_0\,
      Q => \row_reg_n_0_[6]\
    );
\row_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \row[7]_i_1__0_n_0\,
      Q => \row_reg_n_0_[7]\
    );
\row_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \row[8]_i_1__0_n_0\,
      Q => \row_reg_n_0_[8]\
    );
\row_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \row[9]_i_1__0_n_0\,
      Q => \row_reg_n_0_[9]\
    );
\rowacc[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rowacc[3]_i_3_n_0\,
      I1 => rowacc(0),
      O => \rowacc[0]_i_1_n_0\
    );
\rowacc[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \rowacc[3]_i_3_n_0\,
      I1 => rowacc(0),
      I2 => rowacc(1),
      O => \rowacc[1]_i_1_n_0\
    );
\rowacc[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \rowacc[3]_i_3_n_0\,
      I1 => rowacc(0),
      I2 => rowacc(1),
      I3 => rowacc(2),
      O => \rowacc[2]_i_1_n_0\
    );
\rowacc[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"57"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => stateStream(2),
      I2 => stateStream(0),
      O => row
    );
\rowacc[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \rowacc[3]_i_3_n_0\,
      I1 => rowacc(2),
      I2 => rowacc(1),
      I3 => rowacc(0),
      I4 => rowacc(3),
      O => \rowacc[3]_i_2_n_0\
    );
\rowacc[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44444440"
    )
        port map (
      I0 => \stateStream[2]_i_4_n_0\,
      I1 => \^rng_reg_0\,
      I2 => stateStream(2),
      I3 => stateStream(1),
      I4 => stateStream(0),
      O => \rowacc[3]_i_3_n_0\
    );
\rowacc_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \rowacc[0]_i_1_n_0\,
      Q => rowacc(0)
    );
\rowacc_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \rowacc[1]_i_1_n_0\,
      Q => rowacc(1)
    );
\rowacc_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \rowacc[2]_i_1_n_0\,
      Q => rowacc(2)
    );
\rowacc_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => row,
      CLR => AR(0),
      D => \rowacc[3]_i_2_n_0\,
      Q => rowacc(3)
    );
\stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvUnlock_sig,
      CLR => AR(0),
      D => \stateOp_reg[1]_1\(0),
      Q => \^stateop_reg[1]_0\(0)
    );
\stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => ackInvUnlock_sig,
      CLR => AR(0),
      D => \stateOp_reg[1]_1\(1),
      Q => \^stateop_reg[1]_0\(1)
    );
\stateStore[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00C000A0"
    )
        port map (
      I0 => vsync_last_reg_1,
      I1 => \stateStore[0]_i_2_n_0\,
      I2 => \^rng_reg_0\,
      I3 => \^statestore_reg[1]_0\(0),
      I4 => \^statestore_reg[1]_0\(1),
      O => \stateStore[0]_i_1_n_0\
    );
\stateStore[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \^rgbnotgray_reg_0\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \stateStore[1]_i_3_n_0\,
      O => \stateStore[0]_i_2_n_0\
    );
\stateStore[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF3FBFBF"
    )
        port map (
      I0 => strbStore_reg_n_0,
      I1 => \^rng_reg_0\,
      I2 => \^statestore_reg[1]_0\(0),
      I3 => vsync_last_reg_1,
      I4 => \^statestore_reg[1]_0\(1),
      O => \stateStore[1]_i_1_n_0\
    );
\stateStore[1]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => aPvwbuf_reg(5),
      I1 => decimLast(5),
      I2 => aPvwbuf_reg(2),
      I3 => decimLast(2),
      O => \stateStore[1]_i_10_n_0\
    );
\stateStore[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FFAE0000000000"
    )
        port map (
      I0 => \stateStore[1]_i_3_n_0\,
      I1 => \^rgbnotgray_reg_0\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \^statestore_reg[1]_0\(1),
      I4 => \^statestore_reg[1]_0\(0),
      I5 => \^rng_reg_0\,
      O => \stateStore[1]_i_2_n_0\
    );
\stateStore[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004004"
    )
        port map (
      I0 => \stateStore[1]_i_4_n_0\,
      I1 => \stateStore[1]_i_5_n_0\,
      I2 => aPvwbuf_reg(15),
      I3 => decimLast(15),
      I4 => \stateStore[1]_i_6_n_0\,
      O => \stateStore[1]_i_3_n_0\
    );
\stateStore[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBEFFFFBE"
    )
        port map (
      I0 => \stateStore[1]_i_7_n_0\,
      I1 => aPvwbuf_reg(7),
      I2 => decimLast(7),
      I3 => aPvwbuf_reg(6),
      I4 => decimLast(6),
      I5 => \stateStore[1]_i_8_n_0\,
      O => \stateStore[1]_i_4_n_0\
    );
\stateStore[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => decimLast(12),
      I1 => aPvwbuf_reg(12),
      I2 => decimLast(13),
      I3 => aPvwbuf_reg(13),
      I4 => aPvwbuf_reg(14),
      I5 => decimLast(14),
      O => \stateStore[1]_i_5_n_0\
    );
\stateStore[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBEFFFFBE"
    )
        port map (
      I0 => \stateStore[1]_i_9_n_0\,
      I1 => aPvwbuf_reg(1),
      I2 => decimLast(1),
      I3 => aPvwbuf_reg(0),
      I4 => decimLast(0),
      I5 => \stateStore[1]_i_10_n_0\,
      O => \stateStore[1]_i_6_n_0\
    );
\stateStore[1]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => aPvwbuf_reg(10),
      I1 => decimLast(10),
      I2 => aPvwbuf_reg(9),
      I3 => decimLast(9),
      O => \stateStore[1]_i_7_n_0\
    );
\stateStore[1]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => aPvwbuf_reg(11),
      I1 => decimLast(11),
      I2 => aPvwbuf_reg(8),
      I3 => decimLast(8),
      O => \stateStore[1]_i_8_n_0\
    );
\stateStore[1]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => aPvwbuf_reg(4),
      I1 => decimLast(4),
      I2 => aPvwbuf_reg(3),
      I3 => decimLast(3),
      O => \stateStore[1]_i_9_n_0\
    );
\stateStore_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateStore[1]_i_1_n_0\,
      CLR => AR(0),
      D => \stateStore[0]_i_1_n_0\,
      Q => \^statestore_reg[1]_0\(0)
    );
\stateStore_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateStore[1]_i_1_n_0\,
      CLR => AR(0),
      D => \stateStore[1]_i_2_n_0\,
      Q => \^statestore_reg[1]_0\(1)
    );
\stateStream[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBAAABABABAAA"
    )
        port map (
      I0 => tkst,
      I1 => stateStream(2),
      I2 => stateStream(1),
      I3 => \row[10]_i_3_n_0\,
      I4 => \stateStream[0]_i_2_n_0\,
      I5 => \stateStream[1]_i_2_n_0\,
      O => \stateStream[0]_i_1_n_0\
    );
\stateStream[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => stateStream(0),
      O => \stateStream[0]_i_2_n_0\
    );
\stateStream[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000A0A00003000"
    )
        port map (
      I0 => \row[10]_i_3_n_0\,
      I1 => \stateStream[1]_i_2_n_0\,
      I2 => stateStream(0),
      I3 => \^rng_reg_0\,
      I4 => stateStream(2),
      I5 => stateStream(1),
      O => \stateStream[1]_i_1_n_0\
    );
\stateStream[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"777FFF7F"
    )
        port map (
      I0 => \^enaccbuf0\,
      I1 => \col_reg[10]_i_4_n_2\,
      I2 => grayVideoinToManyAXIS_tvalid,
      I3 => \^rgbnotgray_reg_0\,
      I4 => rgbVideoinToManyAXIS_tvalid,
      O => \stateStream[1]_i_2_n_0\
    );
\stateStream[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF577F5777"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => stateStream(2),
      I2 => stateStream(1),
      I3 => stateStream(0),
      I4 => vsync_last_reg_1,
      I5 => \stateStream[2]_i_3_n_0\,
      O => \stateStream[2]_i_1_n_0\
    );
\stateStream[2]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1007077373313110"
    )
        port map (
      I0 => NRowRaw(4),
      I1 => NRowRaw(5),
      I2 => \row_reg_n_0_[4]\,
      I3 => \edge_reg_n_0_[4]\,
      I4 => \stateStream[2]_i_21_n_0\,
      I5 => \row_reg_n_0_[5]\,
      O => \stateStream[2]_i_10_n_0\
    );
\stateStream[2]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0096009696FF0096"
    )
        port map (
      I0 => \stateStream[2]_i_22_n_0\,
      I1 => \row_reg_n_0_[3]\,
      I2 => \edge_reg_n_0_[3]\,
      I3 => NRowRaw(3),
      I4 => \row2__0\(2),
      I5 => NRowRaw(2),
      O => \stateStream[2]_i_11_n_0\
    );
\stateStream[2]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3110077307733110"
    )
        port map (
      I0 => NRowRaw(0),
      I1 => NRowRaw(1),
      I2 => \row_reg_n_0_[0]\,
      I3 => \edge_reg_n_0_[0]\,
      I4 => \edge_reg_n_0_[1]\,
      I5 => \row_reg_n_0_[1]\,
      O => \stateStream[2]_i_12_n_0\
    );
\stateStream[2]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96999999"
    )
        port map (
      I0 => NRowRaw(10),
      I1 => \row_reg_n_0_[10]\,
      I2 => \stateStream[2]_i_19_n_0\,
      I3 => \row_reg_n_0_[8]\,
      I4 => \row_reg_n_0_[9]\,
      O => \stateStream[2]_i_13_n_0\
    );
\stateStream[2]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82412418"
    )
        port map (
      I0 => \row_reg_n_0_[9]\,
      I1 => \row_reg_n_0_[8]\,
      I2 => \stateStream[2]_i_19_n_0\,
      I3 => NRowRaw(9),
      I4 => NRowRaw(8),
      O => \stateStream[2]_i_14_n_0\
    );
\stateStream[2]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82412418"
    )
        port map (
      I0 => \row_reg_n_0_[7]\,
      I1 => \row_reg_n_0_[6]\,
      I2 => \stateStream[2]_i_20_n_0\,
      I3 => NRowRaw(7),
      I4 => NRowRaw(6),
      O => \stateStream[2]_i_15_n_0\
    );
\stateStream[2]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4228811414422881"
    )
        port map (
      I0 => \row_reg_n_0_[5]\,
      I1 => \stateStream[2]_i_21_n_0\,
      I2 => \edge_reg_n_0_[4]\,
      I3 => \row_reg_n_0_[4]\,
      I4 => NRowRaw(5),
      I5 => NRowRaw(4),
      O => \stateStream[2]_i_16_n_0\
    );
\stateStream[2]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669000000009669"
    )
        port map (
      I0 => NRowRaw(3),
      I1 => \stateStream[2]_i_22_n_0\,
      I2 => \row_reg_n_0_[3]\,
      I3 => \edge_reg_n_0_[3]\,
      I4 => \row2__0\(2),
      I5 => NRowRaw(2),
      O => \stateStream[2]_i_17_n_0\
    );
\stateStream[2]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0069690096000069"
    )
        port map (
      I0 => NRowRaw(1),
      I1 => \row_reg_n_0_[1]\,
      I2 => \edge_reg_n_0_[1]\,
      I3 => \edge_reg_n_0_[0]\,
      I4 => \row_reg_n_0_[0]\,
      I5 => NRowRaw(0),
      O => \stateStream[2]_i_18_n_0\
    );
\stateStream[2]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"17FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \row_reg_n_0_[4]\,
      I1 => \edge_reg_n_0_[4]\,
      I2 => \stateStream[2]_i_21_n_0\,
      I3 => \row_reg_n_0_[5]\,
      I4 => \row_reg_n_0_[6]\,
      I5 => \row_reg_n_0_[7]\,
      O => \stateStream[2]_i_19_n_0\
    );
\stateStream[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400000000000000"
    )
        port map (
      I0 => stateStream(0),
      I1 => stateStream(1),
      I2 => stateStream(2),
      I3 => \^rng_reg_0\,
      I4 => \stateStream[2]_i_4_n_0\,
      I5 => \stateStream_reg[2]_i_5_n_2\,
      O => \stateStream[2]_i_2_n_0\
    );
\stateStream[2]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"11171777FFFFFFFF"
    )
        port map (
      I0 => \row_reg_n_0_[4]\,
      I1 => \edge_reg_n_0_[4]\,
      I2 => \stateStream[2]_i_22_n_0\,
      I3 => \edge_reg_n_0_[3]\,
      I4 => \row_reg_n_0_[3]\,
      I5 => \row_reg_n_0_[5]\,
      O => \stateStream[2]_i_20_n_0\
    );
\stateStream[2]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \stateStream[2]_i_22_n_0\,
      I1 => \edge_reg_n_0_[3]\,
      I2 => \row_reg_n_0_[3]\,
      O => \stateStream[2]_i_21_n_0\
    );
\stateStream[2]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEC80EC800000"
    )
        port map (
      I0 => \edge_reg_n_0_[0]\,
      I1 => \row_reg_n_0_[1]\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \edge_reg_n_0_[1]\,
      I4 => \edge_reg_n_0_[2]\,
      I5 => \row_reg_n_0_[2]\,
      O => \stateStream[2]_i_22_n_0\
    );
\stateStream[2]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E8A0175F175FE8A0"
    )
        port map (
      I0 => \edge_reg_n_0_[1]\,
      I1 => \row_reg_n_0_[0]\,
      I2 => \row_reg_n_0_[1]\,
      I3 => \edge_reg_n_0_[0]\,
      I4 => \edge_reg_n_0_[2]\,
      I5 => \row_reg_n_0_[2]\,
      O => \row2__0\(2)
    );
\stateStream[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08080C00"
    )
        port map (
      I0 => \stateStream_reg[0]_2\,
      I1 => stateStream(1),
      I2 => stateStream(2),
      I3 => grayVideoinToManyAXIS_tlast,
      I4 => \^rgbnotgray_reg_0\,
      O => \stateStream[2]_i_3_n_0\
    );
\stateStream[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"90090000"
    )
        port map (
      I0 => rowacc(1),
      I1 => rowaccLast(1),
      I2 => rowacc(2),
      I3 => rowaccLast(2),
      I4 => \stateStream[2]_i_6_n_0\,
      O => \stateStream[2]_i_4_n_0\
    );
\stateStream[2]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => rowacc(3),
      I1 => rowaccLast(3),
      I2 => rowacc(0),
      I3 => rowaccLast(0),
      O => \stateStream[2]_i_6_n_0\
    );
\stateStream[2]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00009AAA"
    )
        port map (
      I0 => \row_reg_n_0_[10]\,
      I1 => \stateStream[2]_i_19_n_0\,
      I2 => \row_reg_n_0_[8]\,
      I3 => \row_reg_n_0_[9]\,
      I4 => NRowRaw(10),
      O => \stateStream[2]_i_7_n_0\
    );
\stateStream[2]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"70371301"
    )
        port map (
      I0 => NRowRaw(8),
      I1 => NRowRaw(9),
      I2 => \stateStream[2]_i_19_n_0\,
      I3 => \row_reg_n_0_[8]\,
      I4 => \row_reg_n_0_[9]\,
      O => \stateStream[2]_i_8_n_0\
    );
\stateStream[2]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"70371301"
    )
        port map (
      I0 => NRowRaw(6),
      I1 => NRowRaw(7),
      I2 => \stateStream[2]_i_20_n_0\,
      I3 => \row_reg_n_0_[6]\,
      I4 => \row_reg_n_0_[7]\,
      O => \stateStream[2]_i_9_n_0\
    );
\stateStream_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateStream[2]_i_1_n_0\,
      CLR => AR(0),
      D => \stateStream[0]_i_1_n_0\,
      Q => stateStream(0)
    );
\stateStream_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateStream[2]_i_1_n_0\,
      CLR => AR(0),
      D => \stateStream[1]_i_1_n_0\,
      Q => stateStream(1)
    );
\stateStream_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateStream[2]_i_1_n_0\,
      CLR => AR(0),
      D => \stateStream[2]_i_2_n_0\,
      Q => stateStream(2)
    );
\stateStream_reg[2]_i_5\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_stateStream_reg[2]_i_5_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \stateStream_reg[2]_i_5_n_2\,
      CO(4) => \stateStream_reg[2]_i_5_n_3\,
      CO(3) => \stateStream_reg[2]_i_5_n_4\,
      CO(2) => \stateStream_reg[2]_i_5_n_5\,
      CO(1) => \stateStream_reg[2]_i_5_n_6\,
      CO(0) => \stateStream_reg[2]_i_5_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \stateStream[2]_i_7_n_0\,
      DI(4) => \stateStream[2]_i_8_n_0\,
      DI(3) => \stateStream[2]_i_9_n_0\,
      DI(2) => \stateStream[2]_i_10_n_0\,
      DI(1) => \stateStream[2]_i_11_n_0\,
      DI(0) => \stateStream[2]_i_12_n_0\,
      O(7 downto 0) => \NLW_stateStream_reg[2]_i_5_O_UNCONNECTED\(7 downto 0),
      S(7 downto 6) => B"00",
      S(5) => \stateStream[2]_i_13_n_0\,
      S(4) => \stateStream[2]_i_14_n_0\,
      S(3) => \stateStream[2]_i_15_n_0\,
      S(2) => \stateStream[2]_i_16_n_0\,
      S(1) => \stateStream[2]_i_17_n_0\,
      S(0) => \stateStream[2]_i_18_n_0\
    );
\state[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E8FFE800"
    )
        port map (
      I0 => stateStream(0),
      I1 => stateStream(1),
      I2 => stateStream(2),
      I3 => \state_reg[5]\(0),
      I4 => videoinStateRgbegr_dbg(2),
      O => \stateStream_reg[0]_1\
    );
\state[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F4FFF400"
    )
        port map (
      I0 => stateStream(1),
      I1 => stateStream(0),
      I2 => stateStream(2),
      I3 => \state_reg[5]\(0),
      I4 => videoinStateRgbegr_dbg(0),
      O => \stateStream_reg[1]_0\
    );
\state[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEFFEE00F0FFF0FF"
    )
        port map (
      I0 => stateStream(1),
      I1 => stateStream(2),
      I2 => videoinStateRgbegr_dbg(1),
      I3 => \state_reg[5]\(1),
      I4 => \state_reg[5]_0\(0),
      I5 => \state_reg[5]\(0),
      O => \stateStream_reg[1]_1\
    );
\state[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateStream(0),
      I1 => stateStream(1),
      I2 => stateStream(2),
      O => \stateStream_reg[0]_0\(0)
    );
strbStore_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEAAA22222AAA"
    )
        port map (
      I0 => strbStore5_out,
      I1 => \^rng_reg_0\,
      I2 => stateStream(0),
      I3 => stateStream(1),
      I4 => stateStream(2),
      I5 => strbStore_reg_n_0,
      O => strbStore_i_1_n_0
    );
strbStore_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000008000000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => stateStream(0),
      I2 => enAccbuf_reg_0,
      I3 => stateStream(1),
      I4 => stateStream(2),
      I5 => \stateStream[2]_i_4_n_0\,
      O => strbStore5_out
    );
strbStore_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => strbStore_i_1_n_0,
      Q => strbStore_reg_n_0
    );
\tixVState[1]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000000000002"
    )
        port map (
      I0 => \tixVState[1]_i_5_n_0\,
      I1 => \tixVState_reg[1]_1\,
      I2 => vsync_last_reg_n_0,
      I3 => \ixTExp_lcl_reg_n_0_[3]\,
      I4 => \tixVState_reg[1]_2\(0),
      I5 => \ixTExp_lcl_reg_n_0_[2]\,
      O => vsync_last_reg_0
    );
\tixVState[1]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02000000"
    )
        port map (
      I0 => \^tixvstate_reg[1]_0\(0),
      I1 => \^tixvstate_reg[1]_0\(1),
      I2 => \^stateop_reg[1]_0\(0),
      I3 => vsync_last_reg_1,
      I4 => \^stateop_reg[1]_0\(1),
      O => \tixVState[1]_i_5_n_0\
    );
\tixVState_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tixVState_reg[1]_3\(0),
      CLR => AR(0),
      D => ackInvAcquire_sig,
      Q => \^tixvstate_reg[1]_0\(0)
    );
\tixVState_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tixVState_reg[1]_3\(0),
      CLR => AR(0),
      D => \tixVState_reg[1]_4\(0),
      Q => \^tixvstate_reg[1]_0\(1)
    );
\tkst_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(0),
      Q => \tkst_reg[31]_0\(0)
    );
\tkst_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(10),
      Q => \tkst_reg[31]_0\(10)
    );
\tkst_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(11),
      Q => \tkst_reg[31]_0\(11)
    );
\tkst_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(12),
      Q => \tkst_reg[31]_0\(12)
    );
\tkst_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(13),
      Q => \tkst_reg[31]_0\(13)
    );
\tkst_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(14),
      Q => \tkst_reg[31]_0\(14)
    );
\tkst_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(15),
      Q => \tkst_reg[31]_0\(15)
    );
\tkst_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(16),
      Q => \tkst_reg[31]_0\(16)
    );
\tkst_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(17),
      Q => \tkst_reg[31]_0\(17)
    );
\tkst_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(18),
      Q => \tkst_reg[31]_0\(18)
    );
\tkst_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(19),
      Q => \tkst_reg[31]_0\(19)
    );
\tkst_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(1),
      Q => \tkst_reg[31]_0\(1)
    );
\tkst_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(20),
      Q => \tkst_reg[31]_0\(20)
    );
\tkst_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(21),
      Q => \tkst_reg[31]_0\(21)
    );
\tkst_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(22),
      Q => \tkst_reg[31]_0\(22)
    );
\tkst_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(23),
      Q => \tkst_reg[31]_0\(23)
    );
\tkst_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(24),
      Q => \tkst_reg[31]_0\(24)
    );
\tkst_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(25),
      Q => \tkst_reg[31]_0\(25)
    );
\tkst_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(26),
      Q => \tkst_reg[31]_0\(26)
    );
\tkst_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(27),
      Q => \tkst_reg[31]_0\(27)
    );
\tkst_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(28),
      Q => \tkst_reg[31]_0\(28)
    );
\tkst_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(29),
      Q => \tkst_reg[31]_0\(29)
    );
\tkst_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(2),
      Q => \tkst_reg[31]_0\(2)
    );
\tkst_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(30),
      Q => \tkst_reg[31]_0\(30)
    );
\tkst_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(31),
      Q => \tkst_reg[31]_0\(31)
    );
\tkst_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(3),
      Q => \tkst_reg[31]_0\(3)
    );
\tkst_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(4),
      Q => \tkst_reg[31]_0\(4)
    );
\tkst_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(5),
      Q => \tkst_reg[31]_0\(5)
    );
\tkst_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(6),
      Q => \tkst_reg[31]_0\(6)
    );
\tkst_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(7),
      Q => \tkst_reg[31]_0\(7)
    );
\tkst_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(8),
      Q => \tkst_reg[31]_0\(8)
    );
\tkst_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => tkst,
      CLR => AR(0),
      D => \tkst_reg[31]_1\(9),
      Q => \tkst_reg[31]_0\(9)
    );
\vsync_last_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => vsync_last_reg_1,
      I1 => vsync_last_reg_2,
      I2 => \^stateop_reg[1]_0\(0),
      I3 => vsync_last_reg_n_0,
      O => \vsync_last_i_1__0_n_0\
    );
vsync_last_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => AR(0),
      D => \vsync_last_i_1__0_n_0\,
      Q => vsync_last_reg_n_0
    );
\wordcntLast[28]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => enPvwbufB,
      I1 => \FSM_onehot_statePvwbufB_reg_n_0_[2]\,
      I2 => \^fsm_onehot_statepvwbufb_reg[5]_0\(0),
      O => ackPvwbufDecimToHostif
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Hdreng is
  port (
    web : out STD_LOGIC_VECTOR ( 0 to 0 );
    stateOp_reg_0 : out STD_LOGIC;
    ackInvHdrengSet : out STD_LOGIC;
    ackInvHdrengAssign : out STD_LOGIC;
    rng_reg_0 : out STD_LOGIC;
    egrAXIS_tlast : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateSwap_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ddrAXI_rvalid_0 : out STD_LOGIC;
    \FSM_sequential_stateIgrstr_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \row_lcl_reg[10]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    ddrAXI_rready : out STD_LOGIC;
    ddrAXI_arvalid : out STD_LOGIC;
    \FSM_onehot_stateWrite_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddrAXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    ddrAXI_awaddr : out STD_LOGIC_VECTOR ( 19 downto 0 );
    rdAAXI_araddr : out STD_LOGIC_VECTOR ( 19 downto 0 );
    ddrAXI_awvalid : out STD_LOGIC;
    ddrAXI_wvalid : out STD_LOGIC;
    \FSM_sequential_stateEgrstr_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \ixMemAcq_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \ixMem_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    wrAAXI_wlast : out STD_LOGIC;
    wrAAXI_awvalid : out STD_LOGIC;
    probe : out STD_LOGIC_VECTOR ( 0 to 0 );
    \tixVState_reg[7]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \tkst_reg[31]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    aclk_sig : in STD_LOGIC;
    memclk : in STD_LOGIC;
    ddrAXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    AR : in STD_LOGIC_VECTOR ( 0 to 0 );
    stateOp_reg_1 : in STD_LOGIC;
    \dwrRowbuf_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    ackInvSet_sig_reg_0 : in STD_LOGIC;
    ackInvAssign_sig : in STD_LOGIC;
    rgbVideoinToManyAXIS_tvalid : in STD_LOGIC;
    rng_reg_1 : in STD_LOGIC;
    \dwrRowbuf_reg[0]_1\ : in STD_LOGIC;
    rgbFromVideoinAXIS_tlast_sig_to_memclk_reg_0 : in STD_LOGIC;
    ddrAXI_rvalid : in STD_LOGIC;
    ddrAXI_rready_0 : in STD_LOGIC;
    ddrAXI_rlast : in STD_LOGIC;
    \capt_reg[5]\ : in STD_LOGIC;
    \stateStream_reg[1]_0\ : in STD_LOGIC;
    \stateStream_reg[0]_0\ : in STD_LOGIC;
    hdrmemAXI_rlast : in STD_LOGIC;
    \burstIgrstr_reg[0]_0\ : in STD_LOGIC;
    ddrAXI_arvalid_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateSwap[3]_i_5_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ddrAXI_wdata_0_sp_1 : in STD_LOGIC;
    \ddrAXI_awaddr[27]\ : in STD_LOGIC;
    reqInvAssign : in STD_LOGIC;
    reqInvHdrengSet : in STD_LOGIC;
    \dwrRowbuf[2]_i_19_0\ : in STD_LOGIC;
    \tixVState_reg[7]_1\ : in STD_LOGIC;
    \tkstAcq_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \stateStream_reg[0]_1\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    ddrAXI_arready : in STD_LOGIC;
    \stateSwap[3]_i_3_0\ : in STD_LOGIC;
    \stateSwap[3]_i_3_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \aRowbufBEgrstr_reg[0]_0\ : in STD_LOGIC;
    ddrAXI_wready : in STD_LOGIC;
    ddrAXI_awready : in STD_LOGIC;
    \stateSwap_reg[2]_0\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \ixMemNext_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \rgbFromVideoinAXIS_tdatam1_reg[35]_0\ : in STD_LOGIC_VECTOR ( 35 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Hdreng : entity is "Hdreng";
end design_1_Vsp_core_0_0_Hdreng;

architecture STRUCTURE of design_1_Vsp_core_0_0_Hdreng is
  signal \FSM_sequential_stateEgrstr[0]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateEgrstr[2]_i_1_n_0\ : STD_LOGIC;
  signal \^fsm_sequential_stateegrstr_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FSM_sequential_stateIgrstr[0]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateIgrstr[0]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateIgrstr[0]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateIgrstr[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateIgrstr[0]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateIgrstr[0]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateIgrstr[0]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateIgrstr[0]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateIgrstr[0]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateIgrstr[0]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateIgrstr[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateIgrstr[1]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateIgrstr[1]_i_5_n_0\ : STD_LOGIC;
  signal \^fsm_sequential_stateigrstr_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal a0Egrstr : STD_LOGIC;
  signal \a0Egrstr_reg_n_0_[4]\ : STD_LOGIC;
  signal \a0Egrstr_reg_n_0_[5]\ : STD_LOGIC;
  signal \a0Egrstr_reg_n_0_[6]\ : STD_LOGIC;
  signal \a0Egrstr_reg_n_0_[7]\ : STD_LOGIC;
  signal \a0Egrstr_reg_n_0_[8]\ : STD_LOGIC;
  signal \a0[0]_i_1_n_0\ : STD_LOGIC;
  signal \a0[1]_i_1_n_0\ : STD_LOGIC;
  signal \a0[2]_i_1_n_0\ : STD_LOGIC;
  signal \a0[3]_i_1_n_0\ : STD_LOGIC;
  signal \a0[4]_i_1_n_0\ : STD_LOGIC;
  signal \a0[4]_i_2_n_0\ : STD_LOGIC;
  signal \a0[4]_i_3_n_0\ : STD_LOGIC;
  signal \a0[4]_i_4_n_0\ : STD_LOGIC;
  signal a0_i : STD_LOGIC;
  signal \a0_i[0]_i_1_n_0\ : STD_LOGIC;
  signal a0_memclk0 : STD_LOGIC;
  signal \a0_memclk[4]_i_2_n_0\ : STD_LOGIC;
  signal \a0_reg_n_0_[0]\ : STD_LOGIC;
  signal \a0_reg_n_0_[1]\ : STD_LOGIC;
  signal \a0_reg_n_0_[2]\ : STD_LOGIC;
  signal \a0_reg_n_0_[3]\ : STD_LOGIC;
  signal \a0_reg_n_0_[4]\ : STD_LOGIC;
  signal a0_to_memclk : STD_LOGIC;
  signal \a0_to_memclk[4]_i_2_n_0\ : STD_LOGIC;
  signal \a0_to_memclk_reg_n_0_[0]\ : STD_LOGIC;
  signal \a0_to_memclk_reg_n_0_[1]\ : STD_LOGIC;
  signal \a0_to_memclk_reg_n_0_[2]\ : STD_LOGIC;
  signal \a0_to_memclk_reg_n_0_[3]\ : STD_LOGIC;
  signal \a0_to_memclk_reg_n_0_[4]\ : STD_LOGIC;
  signal a0_to_memclkm1 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal a0_to_memclkm2 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal aB : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal aRowbufBEgrstr : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \aRowbufBEgrstr[0]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufBEgrstr[1]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufBEgrstr[2]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufBEgrstr[3]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufBEgrstr[4]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufBEgrstr[4]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufBEgrstr[5]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufBEgrstr[6]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufBEgrstr[6]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufBEgrstr[6]_i_3_n_0\ : STD_LOGIC;
  signal \aRowbufBEgrstr[7]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufBEgrstr[7]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufBEgrstr[8]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufBEgrstr[8]_i_2_n_0\ : STD_LOGIC;
  signal aRowbufBIgrstr : STD_LOGIC_VECTOR ( 30 downto 0 );
  signal \aRowbufBIgrstr[30]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[16]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[16]_i_2_n_1\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[16]_i_2_n_2\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[16]_i_2_n_3\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[16]_i_2_n_4\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[16]_i_2_n_5\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[16]_i_2_n_6\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[16]_i_2_n_7\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[24]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[24]_i_2_n_1\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[24]_i_2_n_2\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[24]_i_2_n_3\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[24]_i_2_n_4\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[24]_i_2_n_5\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[24]_i_2_n_6\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[24]_i_2_n_7\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[30]_i_3_n_3\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[30]_i_3_n_4\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[30]_i_3_n_5\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[30]_i_3_n_6\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[30]_i_3_n_7\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[8]_i_2_n_1\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[8]_i_2_n_2\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[8]_i_2_n_3\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[8]_i_2_n_4\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[8]_i_2_n_5\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[8]_i_2_n_6\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg[8]_i_2_n_7\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[0]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[10]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[11]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[12]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[13]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[14]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[15]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[16]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[17]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[18]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[19]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[1]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[20]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[21]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[22]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[23]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[24]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[25]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[26]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[27]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[28]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[29]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[2]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[30]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[3]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[4]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[5]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[6]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[7]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[8]\ : STD_LOGIC;
  signal \aRowbufBIgrstr_reg_n_0_[9]\ : STD_LOGIC;
  signal aRowbufStockrls : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \aRowbufStockrls[0]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[10]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[10]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[10]_i_3_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[1]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[2]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[3]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[4]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[5]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[5]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[6]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[7]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[8]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[9]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[9]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufStockrls[9]_i_3_n_0\ : STD_LOGIC;
  signal \aRowbufStream[0]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStream[10]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStream[10]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufStream[10]_i_3_n_0\ : STD_LOGIC;
  signal \aRowbufStream[10]_i_4_n_0\ : STD_LOGIC;
  signal \aRowbufStream[10]_i_5_n_0\ : STD_LOGIC;
  signal \aRowbufStream[10]_i_6_n_0\ : STD_LOGIC;
  signal \aRowbufStream[1]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStream[2]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStream[3]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStream[4]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStream[5]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStream[5]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufStream[6]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStream[7]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStream[8]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStream[9]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufStream[9]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufStream__0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \^ackinvhdrengassign\ : STD_LOGIC;
  signal \^ackinvhdrengset\ : STD_LOGIC;
  signal addrEgr : STD_LOGIC;
  signal \addrEgr[10]_i_2_n_0\ : STD_LOGIC;
  signal \addrEgr[14]_i_3_n_0\ : STD_LOGIC;
  signal \addrEgr[14]_i_4_n_0\ : STD_LOGIC;
  signal \addrEgr[5]_i_2_n_0\ : STD_LOGIC;
  signal \addrEgr[8]_i_2_n_0\ : STD_LOGIC;
  signal \addrEgr[9]_i_2_n_0\ : STD_LOGIC;
  signal addrIgr : STD_LOGIC;
  signal \addrIgr[10]_i_2_n_0\ : STD_LOGIC;
  signal \addrIgr[14]_i_3_n_0\ : STD_LOGIC;
  signal \addrIgr[5]_i_2_n_0\ : STD_LOGIC;
  signal \addrIgr[8]_i_2_n_0\ : STD_LOGIC;
  signal \addrIgr[9]_i_2_n_0\ : STD_LOGIC;
  signal burstIgrstr : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \burstIgrstr[4]_i_1_n_0\ : STD_LOGIC;
  signal \burstIgrstr[4]_i_3_n_0\ : STD_LOGIC;
  signal \burstIgrstr_reg_n_0_[0]\ : STD_LOGIC;
  signal \burstIgrstr_reg_n_0_[1]\ : STD_LOGIC;
  signal \burstIgrstr_reg_n_0_[2]\ : STD_LOGIC;
  signal \burstIgrstr_reg_n_0_[3]\ : STD_LOGIC;
  signal \burstIgrstr_reg_n_0_[4]\ : STD_LOGIC;
  signal burstSwapLast : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \burstSwap[0]_i_1_n_0\ : STD_LOGIC;
  signal \burstSwap[0]_i_2_n_0\ : STD_LOGIC;
  signal \burstSwap[1]_i_1_n_0\ : STD_LOGIC;
  signal \burstSwap[2]_i_1_n_0\ : STD_LOGIC;
  signal \burstSwap[3]_i_1_n_0\ : STD_LOGIC;
  signal \burstSwap[4]_i_1_n_0\ : STD_LOGIC;
  signal \burstSwap[4]_i_2_n_0\ : STD_LOGIC;
  signal \burstSwap[4]_i_3_n_0\ : STD_LOGIC;
  signal \burstSwap[4]_i_4_n_0\ : STD_LOGIC;
  signal \burstSwap[4]_i_5_n_0\ : STD_LOGIC;
  signal \burstSwap[4]_i_6_n_0\ : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal col_lcl : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \col_lcl[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[10]_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[10]_i_2__0_n_0\ : STD_LOGIC;
  signal \col_lcl[10]_i_3__0_n_0\ : STD_LOGIC;
  signal \col_lcl[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[5]_i_2_n_0\ : STD_LOGIC;
  signal \col_lcl[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[8]_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[9]_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[9]_i_2_n_0\ : STD_LOGIC;
  signal \col_lcl[9]_i_3_n_0\ : STD_LOGIC;
  signal data : STD_LOGIC_VECTOR ( 12 downto 8 );
  signal data5 : STD_LOGIC;
  signal ddrAXI_wdata_0_sn_1 : STD_LOGIC;
  signal ddrAXI_wlast_INST_0_i_2_n_0 : STD_LOGIC;
  signal drdA : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal drdRowBbuf : STD_LOGIC_VECTOR ( 30 downto 0 );
  signal drdRowBbufB : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal dwrRowbuf : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \dwrRowbuf[10]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[10]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[11]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[11]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[12]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[12]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[13]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[13]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[14]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[14]_i_3_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[14]_i_5_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[14]_i_6_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[14]_i_7_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[14]_i_8_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[15]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[15]_i_3_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[16]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[16]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[17]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[17]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[18]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[18]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[19]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[19]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[1]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[1]_i_6_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[1]_i_7_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[20]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[20]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[21]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[21]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[22]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[22]_i_3_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[22]_i_5_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[22]_i_6_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[22]_i_7_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[22]_i_8_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[23]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[24]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[24]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[24]_i_5_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[25]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[25]_i_3_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[25]_i_5_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[25]_i_6_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[25]_i_7_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[26]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[27]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[27]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[28]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[28]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[28]_i_5_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[29]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[29]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_10_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_11_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_12_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_13_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_14_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_15_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_16_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_17_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_18_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_19_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_20_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_21_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_22_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_23_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_24_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_25_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_26_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_27_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_28_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_29_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_30_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_31_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_32_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_33_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_34_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_35_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_36_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_37_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_38_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_39_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_40_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_41_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_42_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_43_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_44_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_9_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[30]_i_10_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[30]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[30]_i_3_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[30]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[30]_i_6_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[30]_i_7_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[30]_i_8_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[30]_i_9_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_3_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_5_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[8]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[8]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[9]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[9]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_6_n_3\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_6_n_4\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_6_n_5\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_6_n_6\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_6_n_7\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_7_n_3\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_7_n_4\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_7_n_5\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_7_n_6\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_7_n_7\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_8_n_3\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_8_n_4\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_8_n_5\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_8_n_6\ : STD_LOGIC;
  signal \dwrRowbuf_reg[2]_i_8_n_7\ : STD_LOGIC;
  signal egrAXIS_tdata : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal \egrAXIS_tdata[127]_i_1_n_0\ : STD_LOGIC;
  signal \egrAXIS_tdata[127]_i_3_n_0\ : STD_LOGIC;
  signal \egrAXIS_tdata[127]_i_4_n_0\ : STD_LOGIC;
  signal \egrAXIS_tdata[127]_i_5_n_0\ : STD_LOGIC;
  signal \^egraxis_tlast\ : STD_LOGIC;
  signal egrAXIS_tlast_i_1_n_0 : STD_LOGIC;
  signal egrAXIS_tlast_i_2_n_0 : STD_LOGIC;
  signal egrAXIS_tlast_i_3_n_0 : STD_LOGIC;
  signal \egrfifo[0][127]_i_1_n_0\ : STD_LOGIC;
  signal \egrfifo[1][127]_i_1_n_0\ : STD_LOGIC;
  signal \egrfifo[2][127]_i_1_n_0\ : STD_LOGIC;
  signal \egrfifo[2][127]_i_3_n_0\ : STD_LOGIC;
  signal \egrfifo[2][127]_i_4_n_0\ : STD_LOGIC;
  signal \egrfifo[2][127]_i_5_n_0\ : STD_LOGIC;
  signal \egrfifo[2]_44\ : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal \egrfifo_reg[0]_43\ : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal \egrfifo_reg[1]_42\ : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal \egrfifo_reg[2]_41\ : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal enRowbufBEgrstr : STD_LOGIC;
  signal enRowbufBEgrstr_i_1_n_0 : STD_LOGIC;
  signal enRowbufBEgrstr_i_2_n_0 : STD_LOGIC;
  signal enRowbufBEgrstrm1 : STD_LOGIC;
  signal enRowbufBEgrstrm1_i_1_n_0 : STD_LOGIC;
  signal enRowbufStream_i_1_n_0 : STD_LOGIC;
  signal enRowbufStream_reg_n_0 : STD_LOGIC;
  signal i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \i[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \i[1]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \i[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \i[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \i_reg[0]__0_n_0\ : STD_LOGIC;
  signal \i_reg_n_0_[0]\ : STD_LOGIC;
  signal \i_reg_n_0_[1]\ : STD_LOGIC;
  signal in30 : STD_LOGIC_VECTOR ( 8 to 8 );
  signal in8 : STD_LOGIC_VECTOR ( 30 downto 1 );
  signal ixMem : STD_LOGIC;
  signal \ixMemAcq[0]_i_1_n_0\ : STD_LOGIC;
  signal \ixMemAcq[1]_i_1_n_0\ : STD_LOGIC;
  signal \ixMemAcq[2]_i_1_n_0\ : STD_LOGIC;
  signal \ixMemAcq[3]_i_1_n_0\ : STD_LOGIC;
  signal \ixMemAcq[4]_i_1_n_0\ : STD_LOGIC;
  signal \ixMemAcq[5]_i_1_n_0\ : STD_LOGIC;
  signal \ixMemAcq[6]_i_1_n_0\ : STD_LOGIC;
  signal \ixMemAcq[7]_i_1_n_0\ : STD_LOGIC;
  signal \^ixmemacq_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \ixMemNext_reg_n_0_[0]\ : STD_LOGIC;
  signal \ixMemNext_reg_n_0_[1]\ : STD_LOGIC;
  signal \ixMemNext_reg_n_0_[2]\ : STD_LOGIC;
  signal \ixMemNext_reg_n_0_[3]\ : STD_LOGIC;
  signal \ixMemNext_reg_n_0_[4]\ : STD_LOGIC;
  signal \ixMemNext_reg_n_0_[5]\ : STD_LOGIC;
  signal \ixMemNext_reg_n_0_[6]\ : STD_LOGIC;
  signal \ixMemNext_reg_n_0_[7]\ : STD_LOGIC;
  signal \ixMem[0]_i_1_n_0\ : STD_LOGIC;
  signal \ixMem[1]_i_1_n_0\ : STD_LOGIC;
  signal \ixMem[2]_i_1_n_0\ : STD_LOGIC;
  signal \ixMem[3]_i_1_n_0\ : STD_LOGIC;
  signal \ixMem[4]_i_1_n_0\ : STD_LOGIC;
  signal \ixMem[5]_i_1_n_0\ : STD_LOGIC;
  signal \ixMem[6]_i_1_n_0\ : STD_LOGIC;
  signal \ixMem[7]_i_2_n_0\ : STD_LOGIC;
  signal \^ixmem_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal ixRdEgrfifo : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ixRdEgrfifo[0]_i_1_n_0\ : STD_LOGIC;
  signal \ixRdEgrfifo[1]_i_1_n_0\ : STD_LOGIC;
  signal \ixRdEgrfifo[1]_i_2_n_0\ : STD_LOGIC;
  signal ixWrEgrfifo : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ixWrEgrfifo[0]_i_1_n_0\ : STD_LOGIC;
  signal \ixWrEgrfifo[1]_i_1_n_0\ : STD_LOGIC;
  signal \ixWrEgrfifo[1]_i_2_n_0\ : STD_LOGIC;
  signal liveBNotA_i : STD_LOGIC;
  signal \liveBNotA_i[0]_i_1_n_0\ : STD_LOGIC;
  signal liveBNotA_i_1_n_0 : STD_LOGIC;
  signal liveBNotA_memclk : STD_LOGIC;
  signal liveBNotA_memclk_i_1_n_0 : STD_LOGIC;
  signal liveBNotA_reg_n_0 : STD_LOGIC;
  signal liveBNotA_to_memclk_i_1_n_0 : STD_LOGIC;
  signal liveBNotA_to_memclk_reg_n_0 : STD_LOGIC;
  signal liveBNotA_to_memclkm1 : STD_LOGIC;
  signal liveBNotA_to_memclkm2 : STD_LOGIC;
  signal myRowAbuf_n_30 : STD_LOGIC;
  signal myRowAbuf_n_31 : STD_LOGIC;
  signal myRowAbuf_n_32 : STD_LOGIC;
  signal myRowAbuf_n_33 : STD_LOGIC;
  signal myRowAbuf_n_34 : STD_LOGIC;
  signal myRowAbuf_n_35 : STD_LOGIC;
  signal myRowAbuf_n_36 : STD_LOGIC;
  signal myRowAbuf_n_37 : STD_LOGIC;
  signal myRowAbuf_n_38 : STD_LOGIC;
  signal myRowAbuf_n_39 : STD_LOGIC;
  signal myRowAbuf_n_40 : STD_LOGIC;
  signal myRowAbuf_n_41 : STD_LOGIC;
  signal myRowAbuf_n_42 : STD_LOGIC;
  signal myRowAbuf_n_43 : STD_LOGIC;
  signal myRowAbuf_n_44 : STD_LOGIC;
  signal myRowAbuf_n_45 : STD_LOGIC;
  signal myRowAbuf_n_46 : STD_LOGIC;
  signal myRowAbuf_n_47 : STD_LOGIC;
  signal myRowAbuf_n_48 : STD_LOGIC;
  signal myRowAbuf_n_49 : STD_LOGIC;
  signal myRowAbuf_n_50 : STD_LOGIC;
  signal myRowAbuf_n_51 : STD_LOGIC;
  signal myRowAbuf_n_52 : STD_LOGIC;
  signal myRowAbuf_n_53 : STD_LOGIC;
  signal myRowAbuf_n_54 : STD_LOGIC;
  signal myRowAbuf_n_55 : STD_LOGIC;
  signal myRowAbuf_n_56 : STD_LOGIC;
  signal myRowAbuf_n_57 : STD_LOGIC;
  signal myRowAbuf_n_58 : STD_LOGIC;
  signal myRowAbuf_n_59 : STD_LOGIC;
  signal myRowAbuf_n_60 : STD_LOGIC;
  signal myRowBbuf_n_166 : STD_LOGIC;
  signal myRowBbuf_n_167 : STD_LOGIC;
  signal myRowBbuf_n_168 : STD_LOGIC;
  signal myRowBbuf_n_169 : STD_LOGIC;
  signal myRowBbuf_n_170 : STD_LOGIC;
  signal myRowBbuf_n_171 : STD_LOGIC;
  signal myRowBbuf_n_172 : STD_LOGIC;
  signal myRowBbuf_n_173 : STD_LOGIC;
  signal myRowBbuf_n_174 : STD_LOGIC;
  signal myRowBbuf_n_175 : STD_LOGIC;
  signal myRowBbuf_n_176 : STD_LOGIC;
  signal myRowBbuf_n_177 : STD_LOGIC;
  signal myRowBbuf_n_178 : STD_LOGIC;
  signal myRowBbuf_n_179 : STD_LOGIC;
  signal myRowBbuf_n_180 : STD_LOGIC;
  signal myRowBbuf_n_181 : STD_LOGIC;
  signal myRowBbuf_n_182 : STD_LOGIC;
  signal myRowBbuf_n_183 : STD_LOGIC;
  signal myRowBbuf_n_184 : STD_LOGIC;
  signal myRowBbuf_n_185 : STD_LOGIC;
  signal myRowBbuf_n_186 : STD_LOGIC;
  signal myRowBbuf_n_187 : STD_LOGIC;
  signal myRowBbuf_n_188 : STD_LOGIC;
  signal myRowBbuf_n_189 : STD_LOGIC;
  signal myRowBbuf_n_190 : STD_LOGIC;
  signal myRowBbuf_n_191 : STD_LOGIC;
  signal myRowBbuf_n_192 : STD_LOGIC;
  signal myRowBbuf_n_193 : STD_LOGIC;
  signal myRowBbuf_n_194 : STD_LOGIC;
  signal myRowBbuf_n_195 : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pvt2 : STD_LOGIC;
  signal pvt29_in : STD_LOGIC;
  signal \^rdaaxi_araddr\ : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal rgbFromVideoinAXIS_tdatam1 : STD_LOGIC_VECTOR ( 35 downto 0 );
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[0]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[10]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[11]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[12]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[13]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[14]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[15]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[16]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[17]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[18]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[19]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[1]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[20]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[21]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[22]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[23]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[24]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[25]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[26]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[27]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[28]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[29]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[2]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[30]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[31]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[32]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[33]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[34]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[35]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[3]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[4]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[5]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[6]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[7]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[8]\ : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tdatam2_reg_n_0_[9]\ : STD_LOGIC;
  signal rgbFromVideoinAXIS_tlast_sig_i : STD_LOGIC;
  signal \rgbFromVideoinAXIS_tlast_sig_i[0]_i_1_n_0\ : STD_LOGIC;
  signal rgbFromVideoinAXIS_tlast_sig_memclk : STD_LOGIC;
  signal rgbFromVideoinAXIS_tlast_sig_memclk_i_1_n_0 : STD_LOGIC;
  signal rgbFromVideoinAXIS_tlast_sig_to_memclk_i_1_n_0 : STD_LOGIC;
  signal rgbFromVideoinAXIS_tlast_sig_to_memclk_reg_n_0 : STD_LOGIC;
  signal rgbFromVideoinAXIS_tlast_sig_to_memclkm1 : STD_LOGIC;
  signal rgbFromVideoinAXIS_tlast_sig_to_memclkm2 : STD_LOGIC;
  signal rgbFromVideoinAXIS_tvalidm1 : STD_LOGIC;
  signal rgbFromVideoinAXIS_tvalidm2 : STD_LOGIC;
  signal rng_i : STD_LOGIC;
  signal \rng_i[0]_i_1_n_0\ : STD_LOGIC;
  signal rng_memclk : STD_LOGIC;
  signal rng_memclk_i_1_n_0 : STD_LOGIC;
  signal \^rng_reg_0\ : STD_LOGIC;
  signal rng_to_memclk_i_1_n_0 : STD_LOGIC;
  signal rng_to_memclk_reg_n_0 : STD_LOGIC;
  signal rng_to_memclkm1 : STD_LOGIC;
  signal rng_to_memclkm2 : STD_LOGIC;
  signal \row_lcl[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \row_lcl[10]_i_3__0_n_0\ : STD_LOGIC;
  signal \row_lcl[10]_i_4_n_0\ : STD_LOGIC;
  signal \row_lcl[10]_i_5_n_0\ : STD_LOGIC;
  signal \row_lcl[10]_i_6_n_0\ : STD_LOGIC;
  signal \row_lcl[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \row_lcl[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \row_lcl[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \row_lcl[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \row_lcl[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \row_lcl[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \row_lcl[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \row_lcl[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \row_lcl[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \^row_lcl_reg[10]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal sel : STD_LOGIC;
  signal stateIgrstr : STD_LOGIC_VECTOR ( 1 to 1 );
  signal stateOp : STD_LOGIC;
  signal \^stateop_reg_0\ : STD_LOGIC;
  signal stateStockrls : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \stateStockrls[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateStockrls[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateStockrls[1]_i_2_n_0\ : STD_LOGIC;
  signal \stateStream[0]_i_10_n_0\ : STD_LOGIC;
  signal \stateStream[0]_i_11_n_0\ : STD_LOGIC;
  signal \stateStream[0]_i_12_n_0\ : STD_LOGIC;
  signal \stateStream[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \stateStream[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \stateStream[0]_i_4_n_0\ : STD_LOGIC;
  signal \stateStream[0]_i_5_n_0\ : STD_LOGIC;
  signal \stateStream[0]_i_6_n_0\ : STD_LOGIC;
  signal \stateStream[0]_i_7_n_0\ : STD_LOGIC;
  signal \stateStream[0]_i_8_n_0\ : STD_LOGIC;
  signal \stateStream[0]_i_9_n_0\ : STD_LOGIC;
  signal \stateStream[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \stateStream[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \stateStream[1]_i_3_n_0\ : STD_LOGIC;
  signal \stateStream[1]_i_4_n_0\ : STD_LOGIC;
  signal \stateStream[1]_i_5_n_0\ : STD_LOGIC;
  signal \stateStream[1]_i_7_n_0\ : STD_LOGIC;
  signal \stateStream[1]_i_8_n_0\ : STD_LOGIC;
  signal \stateSwap[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateSwap[0]_i_2_n_0\ : STD_LOGIC;
  signal \stateSwap[0]_i_3_n_0\ : STD_LOGIC;
  signal \stateSwap[0]_i_4_n_0\ : STD_LOGIC;
  signal \stateSwap[0]_i_5_n_0\ : STD_LOGIC;
  signal \stateSwap[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateSwap[1]_i_2_n_0\ : STD_LOGIC;
  signal \stateSwap[1]_i_3_n_0\ : STD_LOGIC;
  signal \stateSwap[1]_i_4_n_0\ : STD_LOGIC;
  signal \stateSwap[1]_i_5_n_0\ : STD_LOGIC;
  signal \stateSwap[1]_i_6_n_0\ : STD_LOGIC;
  signal \stateSwap[1]_i_7_n_0\ : STD_LOGIC;
  signal \stateSwap[2]_i_1_n_0\ : STD_LOGIC;
  signal \stateSwap[2]_i_2_n_0\ : STD_LOGIC;
  signal \stateSwap[2]_i_3_n_0\ : STD_LOGIC;
  signal \stateSwap[2]_i_4_n_0\ : STD_LOGIC;
  signal \stateSwap[2]_i_6_n_0\ : STD_LOGIC;
  signal \stateSwap[3]_i_1_n_0\ : STD_LOGIC;
  signal \stateSwap[3]_i_2_n_0\ : STD_LOGIC;
  signal \stateSwap[3]_i_3_n_0\ : STD_LOGIC;
  signal \stateSwap[3]_i_4_n_0\ : STD_LOGIC;
  signal \stateSwap[3]_i_5_n_0\ : STD_LOGIC;
  signal \stateSwap[3]_i_6_n_0\ : STD_LOGIC;
  signal \stateSwap[3]_i_7_n_0\ : STD_LOGIC;
  signal \^stateswap_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \tixVState[0]_i_1_n_0\ : STD_LOGIC;
  signal \tixVState[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \tixVState[7]_i_1_n_0\ : STD_LOGIC;
  signal \tixVState[7]_i_2_n_0\ : STD_LOGIC;
  signal tkstAcq : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \tkstAcq[0]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[10]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[11]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[12]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[13]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[14]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[15]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[16]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[17]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[18]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[19]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[1]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[20]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[21]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[22]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[23]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[24]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[25]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[26]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[27]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[28]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[29]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[2]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[30]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[31]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[3]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[4]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[5]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[6]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[7]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[8]_i_1_n_0\ : STD_LOGIC;
  signal \tkstAcq[9]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[0]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[10]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[11]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[12]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[13]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[14]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[15]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[16]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[17]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[18]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[19]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[1]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[20]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[21]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[22]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[23]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[24]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[25]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[26]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[27]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[28]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[29]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[2]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[30]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[31]_i_1__0_n_0\ : STD_LOGIC;
  signal \tkst[3]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[4]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[5]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[6]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[7]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[8]_i_1_n_0\ : STD_LOGIC;
  signal \tkst[9]_i_1_n_0\ : STD_LOGIC;
  signal vsync_sig_i : STD_LOGIC;
  signal \vsync_sig_i[0]_i_1_n_0\ : STD_LOGIC;
  signal vsync_sig_memclk : STD_LOGIC;
  signal vsync_sig_memclk_i_1_n_0 : STD_LOGIC;
  signal vsync_sig_to_memclk_i_1_n_0 : STD_LOGIC;
  signal vsync_sig_to_memclk_reg_n_0 : STD_LOGIC;
  signal vsync_sig_to_memclkm1 : STD_LOGIC;
  signal vsync_sig_to_memclkm2 : STD_LOGIC;
  signal \^web\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \wordEgrLast[2]_i_1_n_0\ : STD_LOGIC;
  signal \wordEgrLast_reg_n_0_[2]\ : STD_LOGIC;
  signal wordEgrRd : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \wordEgrRd[0]_i_1_n_0\ : STD_LOGIC;
  signal \wordEgrRd[1]_i_1_n_0\ : STD_LOGIC;
  signal \wordEgrRd[2]_i_1_n_0\ : STD_LOGIC;
  signal \wordEgrRd[3]_i_1_n_0\ : STD_LOGIC;
  signal \wordEgrRd[3]_i_2_n_0\ : STD_LOGIC;
  signal \wordEgrRd[3]_i_3_n_0\ : STD_LOGIC;
  signal \wordEgrRd[3]_i_4_n_0\ : STD_LOGIC;
  signal \wordEgrRd[3]_i_5_n_0\ : STD_LOGIC;
  signal \wordEgrWr[0]_i_1_n_0\ : STD_LOGIC;
  signal \wordEgrWr[1]_i_1_n_0\ : STD_LOGIC;
  signal \wordEgrWr[2]_i_1_n_0\ : STD_LOGIC;
  signal \wordEgrWr[3]_i_1_n_0\ : STD_LOGIC;
  signal \wordEgrWr[3]_i_2_n_0\ : STD_LOGIC;
  signal \wordEgrWr[3]_i_3_n_0\ : STD_LOGIC;
  signal \wordEgrWr[3]_i_4_n_0\ : STD_LOGIC;
  signal \wordEgrWr[3]_i_5_n_0\ : STD_LOGIC;
  signal \wordEgrWr__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal wrAAXI_awaddr : STD_LOGIC_VECTOR ( 19 downto 5 );
  signal wrAAXI_wdata : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal wrAAXI_wvalid : STD_LOGIC;
  signal \NLW_aRowbufBIgrstr_reg[30]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_aRowbufBIgrstr_reg[30]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_dwrRowbuf_reg[2]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_dwrRowbuf_reg[2]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_dwrRowbuf_reg[2]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_dwrRowbuf_reg[2]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_dwrRowbuf_reg[2]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_dwrRowbuf_reg[2]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_stateEgrstr[0]_i_2\ : label is "soft_lutpair1800";
  attribute SOFT_HLUTNM of \FSM_sequential_stateEgrstr[0]_i_3\ : label is "soft_lutpair1799";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateEgrstr_reg[0]\ : label is "iSTATE:001,iSTATE0:010,iSTATE1:011,iSTATE2:100,iSTATE3:000";
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateEgrstr_reg[1]\ : label is "iSTATE:001,iSTATE0:010,iSTATE1:011,iSTATE2:100,iSTATE3:000";
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateEgrstr_reg[2]\ : label is "iSTATE:001,iSTATE0:010,iSTATE1:011,iSTATE2:100,iSTATE3:000";
  attribute SOFT_HLUTNM of \FSM_sequential_stateIgrstr[0]_i_1\ : label is "soft_lutpair1715";
  attribute SOFT_HLUTNM of \FSM_sequential_stateIgrstr[1]_i_2\ : label is "soft_lutpair1735";
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateIgrstr_reg[0]\ : label is "iSTATE:01,iSTATE0:10,iSTATE1:11,iSTATE2:00";
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateIgrstr_reg[1]\ : label is "iSTATE:01,iSTATE0:10,iSTATE1:11,iSTATE2:00";
  attribute SOFT_HLUTNM of \a0[0]_i_1\ : label is "soft_lutpair1726";
  attribute SOFT_HLUTNM of \a0[1]_i_1\ : label is "soft_lutpair1726";
  attribute SOFT_HLUTNM of \a0[3]_i_1\ : label is "soft_lutpair1727";
  attribute SOFT_HLUTNM of \a0[4]_i_2\ : label is "soft_lutpair1727";
  attribute SOFT_HLUTNM of \a0[4]_i_4\ : label is "soft_lutpair1722";
  attribute SOFT_HLUTNM of \aRowbufBEgrstr[0]_i_1\ : label is "soft_lutpair1841";
  attribute SOFT_HLUTNM of \aRowbufBEgrstr[1]_i_1\ : label is "soft_lutpair1841";
  attribute SOFT_HLUTNM of \aRowbufBEgrstr[2]_i_1\ : label is "soft_lutpair1746";
  attribute SOFT_HLUTNM of \aRowbufBEgrstr[3]_i_1\ : label is "soft_lutpair1746";
  attribute SOFT_HLUTNM of \aRowbufBEgrstr[4]_i_2\ : label is "soft_lutpair1745";
  attribute SOFT_HLUTNM of \aRowbufBEgrstr[6]_i_2\ : label is "soft_lutpair1745";
  attribute SOFT_HLUTNM of \aRowbufBEgrstr[7]_i_1\ : label is "soft_lutpair1803";
  attribute SOFT_HLUTNM of \aRowbufBEgrstr[8]_i_2\ : label is "soft_lutpair1802";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[0]_i_1\ : label is "soft_lutpair1749";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[10]_i_1\ : label is "soft_lutpair1829";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[11]_i_1\ : label is "soft_lutpair1830";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[12]_i_1\ : label is "soft_lutpair1830";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[13]_i_1\ : label is "soft_lutpair1831";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[14]_i_1\ : label is "soft_lutpair1831";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[15]_i_1\ : label is "soft_lutpair1832";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[16]_i_1\ : label is "soft_lutpair1832";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[17]_i_1\ : label is "soft_lutpair1833";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[18]_i_1\ : label is "soft_lutpair1833";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[19]_i_1\ : label is "soft_lutpair1834";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[1]_i_1\ : label is "soft_lutpair1825";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[20]_i_1\ : label is "soft_lutpair1834";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[21]_i_1\ : label is "soft_lutpair1835";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[22]_i_1\ : label is "soft_lutpair1835";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[23]_i_1\ : label is "soft_lutpair1836";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[24]_i_1\ : label is "soft_lutpair1836";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[25]_i_1\ : label is "soft_lutpair1837";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[26]_i_1\ : label is "soft_lutpair1837";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[27]_i_1\ : label is "soft_lutpair1838";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[28]_i_1\ : label is "soft_lutpair1838";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[29]_i_1\ : label is "soft_lutpair1839";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[2]_i_1\ : label is "soft_lutpair1825";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[30]_i_2\ : label is "soft_lutpair1839";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[3]_i_1\ : label is "soft_lutpair1826";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[4]_i_1\ : label is "soft_lutpair1826";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[5]_i_1\ : label is "soft_lutpair1827";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[6]_i_1\ : label is "soft_lutpair1827";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[7]_i_1\ : label is "soft_lutpair1828";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[8]_i_1\ : label is "soft_lutpair1828";
  attribute SOFT_HLUTNM of \aRowbufBIgrstr[9]_i_1\ : label is "soft_lutpair1829";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \aRowbufBIgrstr_reg[16]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \aRowbufBIgrstr_reg[24]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \aRowbufBIgrstr_reg[30]_i_3\ : label is 35;
  attribute ADDER_THRESHOLD of \aRowbufBIgrstr_reg[8]_i_2\ : label is 35;
  attribute SOFT_HLUTNM of \aRowbufStockrls[0]_i_1\ : label is "soft_lutpair1729";
  attribute SOFT_HLUTNM of \aRowbufStockrls[10]_i_2\ : label is "soft_lutpair1728";
  attribute SOFT_HLUTNM of \aRowbufStockrls[1]_i_1\ : label is "soft_lutpair1729";
  attribute SOFT_HLUTNM of \aRowbufStockrls[9]_i_2\ : label is "soft_lutpair1728";
  attribute SOFT_HLUTNM of \aRowbufStream[0]_i_1\ : label is "soft_lutpair1720";
  attribute SOFT_HLUTNM of \aRowbufStream[10]_i_2\ : label is "soft_lutpair1719";
  attribute SOFT_HLUTNM of \aRowbufStream[10]_i_4\ : label is "soft_lutpair1721";
  attribute SOFT_HLUTNM of \aRowbufStream[10]_i_6\ : label is "soft_lutpair1792";
  attribute SOFT_HLUTNM of \aRowbufStream[1]_i_1\ : label is "soft_lutpair1720";
  attribute SOFT_HLUTNM of \aRowbufStream[5]_i_1\ : label is "soft_lutpair1721";
  attribute SOFT_HLUTNM of \aRowbufStream[6]_i_1\ : label is "soft_lutpair1722";
  attribute SOFT_HLUTNM of \addrEgr[0]_i_1\ : label is "soft_lutpair1733";
  attribute SOFT_HLUTNM of \addrEgr[10]_i_1\ : label is "soft_lutpair1797";
  attribute SOFT_HLUTNM of \addrEgr[10]_i_2\ : label is "soft_lutpair1739";
  attribute SOFT_HLUTNM of \addrEgr[11]_i_1\ : label is "soft_lutpair1798";
  attribute SOFT_HLUTNM of \addrEgr[2]_i_1\ : label is "soft_lutpair1734";
  attribute SOFT_HLUTNM of \addrEgr[3]_i_1\ : label is "soft_lutpair1734";
  attribute SOFT_HLUTNM of \addrEgr[7]_i_1\ : label is "soft_lutpair1795";
  attribute SOFT_HLUTNM of \addrEgr[9]_i_1\ : label is "soft_lutpair1796";
  attribute SOFT_HLUTNM of \addrEgr[9]_i_2\ : label is "soft_lutpair1739";
  attribute SOFT_HLUTNM of \addrIgr[0]_i_1\ : label is "soft_lutpair1731";
  attribute SOFT_HLUTNM of \addrIgr[10]_i_2\ : label is "soft_lutpair1740";
  attribute SOFT_HLUTNM of \addrIgr[2]_i_1\ : label is "soft_lutpair1732";
  attribute SOFT_HLUTNM of \addrIgr[3]_i_1\ : label is "soft_lutpair1732";
  attribute SOFT_HLUTNM of \addrIgr[9]_i_2\ : label is "soft_lutpair1740";
  attribute SOFT_HLUTNM of awdone_i_2 : label is "soft_lutpair1718";
  attribute SOFT_HLUTNM of \burstIgrstr[1]_i_1\ : label is "soft_lutpair1744";
  attribute SOFT_HLUTNM of \burstIgrstr[2]_i_1\ : label is "soft_lutpair1744";
  attribute SOFT_HLUTNM of \burstIgrstr[4]_i_3\ : label is "soft_lutpair1715";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \burstSwapLast_reg[1]\ : label is "LD";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \burstSwapLast_reg[1]\ : label is "VCC:GE GND:CLR";
  attribute SOFT_HLUTNM of \burstSwap[1]_i_1\ : label is "soft_lutpair1820";
  attribute SOFT_HLUTNM of \burstSwap[2]_i_1\ : label is "soft_lutpair1736";
  attribute SOFT_HLUTNM of \burstSwap[3]_i_1\ : label is "soft_lutpair1736";
  attribute SOFT_HLUTNM of \burstSwap[4]_i_4\ : label is "soft_lutpair1752";
  attribute SOFT_HLUTNM of \burstSwap[4]_i_5\ : label is "soft_lutpair1737";
  attribute SOFT_HLUTNM of \burstSwap[4]_i_6\ : label is "soft_lutpair1821";
  attribute SOFT_HLUTNM of \capt[5]_i_1\ : label is "soft_lutpair1749";
  attribute SOFT_HLUTNM of \col_lcl[0]_i_1__0\ : label is "soft_lutpair1723";
  attribute SOFT_HLUTNM of \col_lcl[10]_i_2__0\ : label is "soft_lutpair1751";
  attribute SOFT_HLUTNM of \col_lcl[1]_i_1__0\ : label is "soft_lutpair1723";
  attribute SOFT_HLUTNM of \col_lcl[3]_i_1__0\ : label is "soft_lutpair1713";
  attribute SOFT_HLUTNM of \col_lcl[5]_i_1__0\ : label is "soft_lutpair1747";
  attribute SOFT_HLUTNM of \col_lcl[6]_i_1__0\ : label is "soft_lutpair1712";
  attribute SOFT_HLUTNM of \col_lcl[8]_i_1\ : label is "soft_lutpair1711";
  attribute SOFT_HLUTNM of \col_lcl[9]_i_3\ : label is "soft_lutpair1719";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[10]_INST_0\ : label is "soft_lutpair1906";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[11]_INST_0\ : label is "soft_lutpair1907";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[12]_INST_0\ : label is "soft_lutpair1907";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[13]_INST_0\ : label is "soft_lutpair1908";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[14]_INST_0\ : label is "soft_lutpair1908";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[15]_INST_0\ : label is "soft_lutpair1909";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[16]_INST_0\ : label is "soft_lutpair1909";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[17]_INST_0\ : label is "soft_lutpair1910";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[18]_INST_0\ : label is "soft_lutpair1910";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[19]_INST_0\ : label is "soft_lutpair1911";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[20]_INST_0\ : label is "soft_lutpair1795";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[21]_INST_0\ : label is "soft_lutpair1911";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[22]_INST_0\ : label is "soft_lutpair1796";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[23]_INST_0\ : label is "soft_lutpair1797";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[24]_INST_0\ : label is "soft_lutpair1798";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[25]_INST_0\ : label is "soft_lutpair1912";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[26]_INST_0\ : label is "soft_lutpair1912";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[8]_INST_0\ : label is "soft_lutpair1906";
  attribute SOFT_HLUTNM of \ddrAXI_awaddr[9]_INST_0\ : label is "soft_lutpair1820";
  attribute SOFT_HLUTNM of ddrAXI_awvalid_INST_0 : label is "soft_lutpair1718";
  attribute SOFT_HLUTNM of ddrAXI_rready_INST_0 : label is "soft_lutpair1714";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[0]_INST_0\ : label is "soft_lutpair1842";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[100]_INST_0\ : label is "soft_lutpair1892";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[101]_INST_0\ : label is "soft_lutpair1892";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[102]_INST_0\ : label is "soft_lutpair1893";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[103]_INST_0\ : label is "soft_lutpair1893";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[104]_INST_0\ : label is "soft_lutpair1894";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[105]_INST_0\ : label is "soft_lutpair1894";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[106]_INST_0\ : label is "soft_lutpair1895";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[107]_INST_0\ : label is "soft_lutpair1895";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[108]_INST_0\ : label is "soft_lutpair1896";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[109]_INST_0\ : label is "soft_lutpair1896";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[10]_INST_0\ : label is "soft_lutpair1847";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[110]_INST_0\ : label is "soft_lutpair1897";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[111]_INST_0\ : label is "soft_lutpair1897";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[112]_INST_0\ : label is "soft_lutpair1898";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[113]_INST_0\ : label is "soft_lutpair1898";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[114]_INST_0\ : label is "soft_lutpair1899";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[115]_INST_0\ : label is "soft_lutpair1899";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[116]_INST_0\ : label is "soft_lutpair1900";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[117]_INST_0\ : label is "soft_lutpair1900";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[118]_INST_0\ : label is "soft_lutpair1901";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[119]_INST_0\ : label is "soft_lutpair1901";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[11]_INST_0\ : label is "soft_lutpair1847";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[120]_INST_0\ : label is "soft_lutpair1902";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[121]_INST_0\ : label is "soft_lutpair1902";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[122]_INST_0\ : label is "soft_lutpair1903";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[123]_INST_0\ : label is "soft_lutpair1903";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[124]_INST_0\ : label is "soft_lutpair1904";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[125]_INST_0\ : label is "soft_lutpair1904";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[126]_INST_0\ : label is "soft_lutpair1905";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[127]_INST_0\ : label is "soft_lutpair1905";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[12]_INST_0\ : label is "soft_lutpair1848";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[13]_INST_0\ : label is "soft_lutpair1848";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[14]_INST_0\ : label is "soft_lutpair1849";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[15]_INST_0\ : label is "soft_lutpair1849";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[16]_INST_0\ : label is "soft_lutpair1850";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[17]_INST_0\ : label is "soft_lutpair1850";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[18]_INST_0\ : label is "soft_lutpair1851";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[19]_INST_0\ : label is "soft_lutpair1851";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[1]_INST_0\ : label is "soft_lutpair1842";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[20]_INST_0\ : label is "soft_lutpair1852";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[21]_INST_0\ : label is "soft_lutpair1852";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[22]_INST_0\ : label is "soft_lutpair1853";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[23]_INST_0\ : label is "soft_lutpair1853";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[24]_INST_0\ : label is "soft_lutpair1854";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[25]_INST_0\ : label is "soft_lutpair1854";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[26]_INST_0\ : label is "soft_lutpair1855";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[27]_INST_0\ : label is "soft_lutpair1855";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[28]_INST_0\ : label is "soft_lutpair1856";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[29]_INST_0\ : label is "soft_lutpair1856";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[2]_INST_0\ : label is "soft_lutpair1843";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[30]_INST_0\ : label is "soft_lutpair1857";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[31]_INST_0\ : label is "soft_lutpair1857";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[32]_INST_0\ : label is "soft_lutpair1858";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[33]_INST_0\ : label is "soft_lutpair1858";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[34]_INST_0\ : label is "soft_lutpair1859";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[35]_INST_0\ : label is "soft_lutpair1859";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[36]_INST_0\ : label is "soft_lutpair1860";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[37]_INST_0\ : label is "soft_lutpair1860";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[38]_INST_0\ : label is "soft_lutpair1861";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[39]_INST_0\ : label is "soft_lutpair1861";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[3]_INST_0\ : label is "soft_lutpair1843";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[40]_INST_0\ : label is "soft_lutpair1862";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[41]_INST_0\ : label is "soft_lutpair1862";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[42]_INST_0\ : label is "soft_lutpair1863";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[43]_INST_0\ : label is "soft_lutpair1863";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[44]_INST_0\ : label is "soft_lutpair1864";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[45]_INST_0\ : label is "soft_lutpair1864";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[46]_INST_0\ : label is "soft_lutpair1865";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[47]_INST_0\ : label is "soft_lutpair1865";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[48]_INST_0\ : label is "soft_lutpair1866";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[49]_INST_0\ : label is "soft_lutpair1866";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[4]_INST_0\ : label is "soft_lutpair1844";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[50]_INST_0\ : label is "soft_lutpair1867";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[51]_INST_0\ : label is "soft_lutpair1867";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[52]_INST_0\ : label is "soft_lutpair1868";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[53]_INST_0\ : label is "soft_lutpair1868";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[54]_INST_0\ : label is "soft_lutpair1869";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[55]_INST_0\ : label is "soft_lutpair1869";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[56]_INST_0\ : label is "soft_lutpair1870";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[57]_INST_0\ : label is "soft_lutpair1870";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[58]_INST_0\ : label is "soft_lutpair1871";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[59]_INST_0\ : label is "soft_lutpair1871";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[5]_INST_0\ : label is "soft_lutpair1844";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[60]_INST_0\ : label is "soft_lutpair1872";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[61]_INST_0\ : label is "soft_lutpair1872";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[62]_INST_0\ : label is "soft_lutpair1873";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[63]_INST_0\ : label is "soft_lutpair1873";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[64]_INST_0\ : label is "soft_lutpair1874";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[65]_INST_0\ : label is "soft_lutpair1874";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[66]_INST_0\ : label is "soft_lutpair1875";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[67]_INST_0\ : label is "soft_lutpair1875";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[68]_INST_0\ : label is "soft_lutpair1876";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[69]_INST_0\ : label is "soft_lutpair1876";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[6]_INST_0\ : label is "soft_lutpair1845";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[70]_INST_0\ : label is "soft_lutpair1877";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[71]_INST_0\ : label is "soft_lutpair1877";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[72]_INST_0\ : label is "soft_lutpair1878";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[73]_INST_0\ : label is "soft_lutpair1878";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[74]_INST_0\ : label is "soft_lutpair1879";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[75]_INST_0\ : label is "soft_lutpair1879";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[76]_INST_0\ : label is "soft_lutpair1880";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[77]_INST_0\ : label is "soft_lutpair1880";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[78]_INST_0\ : label is "soft_lutpair1881";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[79]_INST_0\ : label is "soft_lutpair1881";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[7]_INST_0\ : label is "soft_lutpair1845";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[80]_INST_0\ : label is "soft_lutpair1882";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[81]_INST_0\ : label is "soft_lutpair1882";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[82]_INST_0\ : label is "soft_lutpair1883";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[83]_INST_0\ : label is "soft_lutpair1883";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[84]_INST_0\ : label is "soft_lutpair1884";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[85]_INST_0\ : label is "soft_lutpair1884";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[86]_INST_0\ : label is "soft_lutpair1885";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[87]_INST_0\ : label is "soft_lutpair1885";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[88]_INST_0\ : label is "soft_lutpair1886";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[89]_INST_0\ : label is "soft_lutpair1886";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[8]_INST_0\ : label is "soft_lutpair1846";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[90]_INST_0\ : label is "soft_lutpair1887";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[91]_INST_0\ : label is "soft_lutpair1887";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[92]_INST_0\ : label is "soft_lutpair1888";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[93]_INST_0\ : label is "soft_lutpair1888";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[94]_INST_0\ : label is "soft_lutpair1889";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[95]_INST_0\ : label is "soft_lutpair1889";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[96]_INST_0\ : label is "soft_lutpair1890";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[97]_INST_0\ : label is "soft_lutpair1890";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[98]_INST_0\ : label is "soft_lutpair1891";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[99]_INST_0\ : label is "soft_lutpair1891";
  attribute SOFT_HLUTNM of \ddrAXI_wdata[9]_INST_0\ : label is "soft_lutpair1846";
  attribute SOFT_HLUTNM of ddrAXI_wlast_INST_0_i_2 : label is "soft_lutpair1737";
  attribute SOFT_HLUTNM of ddrAXI_wvalid_INST_0 : label is "soft_lutpair1752";
  attribute SOFT_HLUTNM of \dwrRowbuf[10]_i_4\ : label is "soft_lutpair1810";
  attribute SOFT_HLUTNM of \dwrRowbuf[11]_i_4\ : label is "soft_lutpair1810";
  attribute SOFT_HLUTNM of \dwrRowbuf[12]_i_4\ : label is "soft_lutpair1809";
  attribute SOFT_HLUTNM of \dwrRowbuf[13]_i_4\ : label is "soft_lutpair1809";
  attribute SOFT_HLUTNM of \dwrRowbuf[14]_i_3\ : label is "soft_lutpair1724";
  attribute SOFT_HLUTNM of \dwrRowbuf[14]_i_5\ : label is "soft_lutpair1808";
  attribute SOFT_HLUTNM of \dwrRowbuf[14]_i_6\ : label is "soft_lutpair1808";
  attribute SOFT_HLUTNM of \dwrRowbuf[15]_i_3\ : label is "soft_lutpair1724";
  attribute SOFT_HLUTNM of \dwrRowbuf[16]_i_4\ : label is "soft_lutpair1815";
  attribute SOFT_HLUTNM of \dwrRowbuf[17]_i_4\ : label is "soft_lutpair1815";
  attribute SOFT_HLUTNM of \dwrRowbuf[18]_i_4\ : label is "soft_lutpair1814";
  attribute SOFT_HLUTNM of \dwrRowbuf[19]_i_4\ : label is "soft_lutpair1814";
  attribute SOFT_HLUTNM of \dwrRowbuf[20]_i_4\ : label is "soft_lutpair1813";
  attribute SOFT_HLUTNM of \dwrRowbuf[21]_i_4\ : label is "soft_lutpair1813";
  attribute SOFT_HLUTNM of \dwrRowbuf[22]_i_5\ : label is "soft_lutpair1812";
  attribute SOFT_HLUTNM of \dwrRowbuf[22]_i_6\ : label is "soft_lutpair1812";
  attribute SOFT_HLUTNM of \dwrRowbuf[24]_i_4\ : label is "soft_lutpair1819";
  attribute SOFT_HLUTNM of \dwrRowbuf[24]_i_5\ : label is "soft_lutpair1818";
  attribute SOFT_HLUTNM of \dwrRowbuf[25]_i_7\ : label is "soft_lutpair1819";
  attribute SOFT_HLUTNM of \dwrRowbuf[27]_i_4\ : label is "soft_lutpair1818";
  attribute SOFT_HLUTNM of \dwrRowbuf[28]_i_4\ : label is "soft_lutpair1817";
  attribute SOFT_HLUTNM of \dwrRowbuf[28]_i_5\ : label is "soft_lutpair1793";
  attribute SOFT_HLUTNM of \dwrRowbuf[29]_i_4\ : label is "soft_lutpair1817";
  attribute SOFT_HLUTNM of \dwrRowbuf[30]_i_10\ : label is "soft_lutpair1816";
  attribute SOFT_HLUTNM of \dwrRowbuf[30]_i_3\ : label is "soft_lutpair1793";
  attribute SOFT_HLUTNM of \dwrRowbuf[30]_i_4\ : label is "soft_lutpair1725";
  attribute SOFT_HLUTNM of \dwrRowbuf[30]_i_6\ : label is "soft_lutpair1816";
  attribute SOFT_HLUTNM of \dwrRowbuf[31]_i_5\ : label is "soft_lutpair1725";
  attribute SOFT_HLUTNM of \dwrRowbuf[8]_i_4\ : label is "soft_lutpair1811";
  attribute SOFT_HLUTNM of \dwrRowbuf[9]_i_4\ : label is "soft_lutpair1811";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of \dwrRowbuf_reg[2]_i_6\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \dwrRowbuf_reg[2]_i_7\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \dwrRowbuf_reg[2]_i_8\ : label is 11;
  attribute SOFT_HLUTNM of \egrfifo[2][127]_i_4\ : label is "soft_lutpair1800";
  attribute SOFT_HLUTNM of \egrfifo[2][127]_i_5\ : label is "soft_lutpair1799";
  attribute SOFT_HLUTNM of \i[0]__0_i_1__0\ : label is "soft_lutpair1840";
  attribute SOFT_HLUTNM of \i[1]__0_i_2\ : label is "soft_lutpair1840";
  attribute SOFT_HLUTNM of \ixMemAcq[0]_i_1\ : label is "soft_lutpair1788";
  attribute SOFT_HLUTNM of \ixMemAcq[1]_i_1\ : label is "soft_lutpair1789";
  attribute SOFT_HLUTNM of \ixMemAcq[2]_i_1\ : label is "soft_lutpair1748";
  attribute SOFT_HLUTNM of \ixMemAcq[3]_i_1\ : label is "soft_lutpair1789";
  attribute SOFT_HLUTNM of \ixMemAcq[4]_i_1\ : label is "soft_lutpair1790";
  attribute SOFT_HLUTNM of \ixMemAcq[5]_i_1\ : label is "soft_lutpair1790";
  attribute SOFT_HLUTNM of \ixMemAcq[6]_i_1\ : label is "soft_lutpair1791";
  attribute SOFT_HLUTNM of \ixMemAcq[7]_i_1\ : label is "soft_lutpair1791";
  attribute SOFT_HLUTNM of \ixMem[0]_i_1\ : label is "soft_lutpair1748";
  attribute SOFT_HLUTNM of \ixMem[1]_i_1\ : label is "soft_lutpair1785";
  attribute SOFT_HLUTNM of \ixMem[2]_i_1\ : label is "soft_lutpair1785";
  attribute SOFT_HLUTNM of \ixMem[3]_i_1\ : label is "soft_lutpair1786";
  attribute SOFT_HLUTNM of \ixMem[4]_i_1\ : label is "soft_lutpair1786";
  attribute SOFT_HLUTNM of \ixMem[5]_i_1\ : label is "soft_lutpair1787";
  attribute SOFT_HLUTNM of \ixMem[6]_i_1\ : label is "soft_lutpair1787";
  attribute SOFT_HLUTNM of \ixMem[7]_i_2\ : label is "soft_lutpair1788";
  attribute SOFT_HLUTNM of \ixRdEgrfifo[0]_i_1\ : label is "soft_lutpair1801";
  attribute SOFT_HLUTNM of \ixRdEgrfifo[1]_i_2\ : label is "soft_lutpair1801";
  attribute SOFT_HLUTNM of \liveBNotA_i[0]_i_1\ : label is "soft_lutpair1807";
  attribute SOFT_HLUTNM of liveBNotA_to_memclk_i_1 : label is "soft_lutpair1807";
  attribute SOFT_HLUTNM of \probe[2]_INST_0\ : label is "soft_lutpair1733";
  attribute SOFT_HLUTNM of \rdid[1][0]_i_4\ : label is "soft_lutpair1714";
  attribute SOFT_HLUTNM of \rgbFromVideoinAXIS_tlast_sig_i[0]_i_1\ : label is "soft_lutpair1805";
  attribute SOFT_HLUTNM of rgbFromVideoinAXIS_tlast_sig_to_memclk_i_1 : label is "soft_lutpair1805";
  attribute SOFT_HLUTNM of \rng_i[0]_i_1\ : label is "soft_lutpair1804";
  attribute SOFT_HLUTNM of rng_memclk_i_1 : label is "soft_lutpair1823";
  attribute SOFT_HLUTNM of rng_to_memclk_i_1 : label is "soft_lutpair1804";
  attribute SOFT_HLUTNM of \row_lcl[0]_i_1__0\ : label is "soft_lutpair1824";
  attribute SOFT_HLUTNM of \row_lcl[10]_i_4\ : label is "soft_lutpair1731";
  attribute SOFT_HLUTNM of \row_lcl[10]_i_5\ : label is "soft_lutpair1735";
  attribute SOFT_HLUTNM of \row_lcl[1]_i_1__0\ : label is "soft_lutpair1741";
  attribute SOFT_HLUTNM of \row_lcl[2]_i_1__0\ : label is "soft_lutpair1824";
  attribute SOFT_HLUTNM of \row_lcl[3]_i_1__0\ : label is "soft_lutpair1742";
  attribute SOFT_HLUTNM of \row_lcl[4]_i_1__0\ : label is "soft_lutpair1742";
  attribute SOFT_HLUTNM of \row_lcl[7]_i_1__0\ : label is "soft_lutpair1750";
  attribute SOFT_HLUTNM of \row_lcl[8]_i_1__0\ : label is "soft_lutpair1750";
  attribute SOFT_HLUTNM of \row_lcl[9]_i_1__0\ : label is "soft_lutpair1716";
  attribute SOFT_HLUTNM of \stateStream[0]_i_11\ : label is "soft_lutpair1713";
  attribute SOFT_HLUTNM of \stateStream[0]_i_5\ : label is "soft_lutpair1711";
  attribute SOFT_HLUTNM of \stateStream[0]_i_7\ : label is "soft_lutpair1792";
  attribute SOFT_HLUTNM of \stateSwap[0]_i_2\ : label is "soft_lutpair1822";
  attribute SOFT_HLUTNM of \stateSwap[1]_i_3\ : label is "soft_lutpair1822";
  attribute SOFT_HLUTNM of \stateSwap[1]_i_4\ : label is "soft_lutpair1794";
  attribute SOFT_HLUTNM of \stateSwap[1]_i_5\ : label is "soft_lutpair1741";
  attribute SOFT_HLUTNM of \stateSwap[1]_i_6\ : label is "soft_lutpair1716";
  attribute SOFT_HLUTNM of \stateSwap[2]_i_3\ : label is "soft_lutpair1821";
  attribute SOFT_HLUTNM of \stateSwap[2]_i_4\ : label is "soft_lutpair1794";
  attribute SOFT_HLUTNM of \stateSwap[2]_i_6\ : label is "soft_lutpair1823";
  attribute SOFT_HLUTNM of \tixVState[0]_i_1\ : label is "soft_lutpair1747";
  attribute SOFT_HLUTNM of \tixVState[1]_i_1__1\ : label is "soft_lutpair1751";
  attribute SOFT_HLUTNM of \tixVState[7]_i_2\ : label is "soft_lutpair1712";
  attribute SOFT_HLUTNM of \tkstAcq[0]_i_1\ : label is "soft_lutpair1769";
  attribute SOFT_HLUTNM of \tkstAcq[10]_i_1\ : label is "soft_lutpair1774";
  attribute SOFT_HLUTNM of \tkstAcq[11]_i_1\ : label is "soft_lutpair1774";
  attribute SOFT_HLUTNM of \tkstAcq[12]_i_1\ : label is "soft_lutpair1775";
  attribute SOFT_HLUTNM of \tkstAcq[13]_i_1\ : label is "soft_lutpair1775";
  attribute SOFT_HLUTNM of \tkstAcq[14]_i_1\ : label is "soft_lutpair1776";
  attribute SOFT_HLUTNM of \tkstAcq[15]_i_1\ : label is "soft_lutpair1776";
  attribute SOFT_HLUTNM of \tkstAcq[16]_i_1\ : label is "soft_lutpair1777";
  attribute SOFT_HLUTNM of \tkstAcq[17]_i_1\ : label is "soft_lutpair1777";
  attribute SOFT_HLUTNM of \tkstAcq[18]_i_1\ : label is "soft_lutpair1778";
  attribute SOFT_HLUTNM of \tkstAcq[19]_i_1\ : label is "soft_lutpair1778";
  attribute SOFT_HLUTNM of \tkstAcq[1]_i_1\ : label is "soft_lutpair1769";
  attribute SOFT_HLUTNM of \tkstAcq[20]_i_1\ : label is "soft_lutpair1779";
  attribute SOFT_HLUTNM of \tkstAcq[21]_i_1\ : label is "soft_lutpair1779";
  attribute SOFT_HLUTNM of \tkstAcq[22]_i_1\ : label is "soft_lutpair1780";
  attribute SOFT_HLUTNM of \tkstAcq[23]_i_1\ : label is "soft_lutpair1780";
  attribute SOFT_HLUTNM of \tkstAcq[24]_i_1\ : label is "soft_lutpair1781";
  attribute SOFT_HLUTNM of \tkstAcq[25]_i_1\ : label is "soft_lutpair1781";
  attribute SOFT_HLUTNM of \tkstAcq[26]_i_1\ : label is "soft_lutpair1782";
  attribute SOFT_HLUTNM of \tkstAcq[27]_i_1\ : label is "soft_lutpair1782";
  attribute SOFT_HLUTNM of \tkstAcq[28]_i_1\ : label is "soft_lutpair1783";
  attribute SOFT_HLUTNM of \tkstAcq[29]_i_1\ : label is "soft_lutpair1783";
  attribute SOFT_HLUTNM of \tkstAcq[2]_i_1\ : label is "soft_lutpair1770";
  attribute SOFT_HLUTNM of \tkstAcq[30]_i_1\ : label is "soft_lutpair1784";
  attribute SOFT_HLUTNM of \tkstAcq[31]_i_1\ : label is "soft_lutpair1784";
  attribute SOFT_HLUTNM of \tkstAcq[3]_i_1\ : label is "soft_lutpair1770";
  attribute SOFT_HLUTNM of \tkstAcq[4]_i_1\ : label is "soft_lutpair1771";
  attribute SOFT_HLUTNM of \tkstAcq[5]_i_1\ : label is "soft_lutpair1771";
  attribute SOFT_HLUTNM of \tkstAcq[6]_i_1\ : label is "soft_lutpair1772";
  attribute SOFT_HLUTNM of \tkstAcq[7]_i_1\ : label is "soft_lutpair1772";
  attribute SOFT_HLUTNM of \tkstAcq[8]_i_1\ : label is "soft_lutpair1773";
  attribute SOFT_HLUTNM of \tkstAcq[9]_i_1\ : label is "soft_lutpair1773";
  attribute SOFT_HLUTNM of \tkst[0]_i_1\ : label is "soft_lutpair1753";
  attribute SOFT_HLUTNM of \tkst[10]_i_1\ : label is "soft_lutpair1758";
  attribute SOFT_HLUTNM of \tkst[11]_i_1\ : label is "soft_lutpair1758";
  attribute SOFT_HLUTNM of \tkst[12]_i_1\ : label is "soft_lutpair1759";
  attribute SOFT_HLUTNM of \tkst[13]_i_1\ : label is "soft_lutpair1759";
  attribute SOFT_HLUTNM of \tkst[14]_i_1\ : label is "soft_lutpair1760";
  attribute SOFT_HLUTNM of \tkst[15]_i_1\ : label is "soft_lutpair1760";
  attribute SOFT_HLUTNM of \tkst[16]_i_1\ : label is "soft_lutpair1761";
  attribute SOFT_HLUTNM of \tkst[17]_i_1\ : label is "soft_lutpair1761";
  attribute SOFT_HLUTNM of \tkst[18]_i_1\ : label is "soft_lutpair1762";
  attribute SOFT_HLUTNM of \tkst[19]_i_1\ : label is "soft_lutpair1762";
  attribute SOFT_HLUTNM of \tkst[1]_i_1\ : label is "soft_lutpair1753";
  attribute SOFT_HLUTNM of \tkst[20]_i_1\ : label is "soft_lutpair1763";
  attribute SOFT_HLUTNM of \tkst[21]_i_1\ : label is "soft_lutpair1763";
  attribute SOFT_HLUTNM of \tkst[22]_i_1\ : label is "soft_lutpair1764";
  attribute SOFT_HLUTNM of \tkst[23]_i_1\ : label is "soft_lutpair1764";
  attribute SOFT_HLUTNM of \tkst[24]_i_1\ : label is "soft_lutpair1765";
  attribute SOFT_HLUTNM of \tkst[25]_i_1\ : label is "soft_lutpair1765";
  attribute SOFT_HLUTNM of \tkst[26]_i_1\ : label is "soft_lutpair1766";
  attribute SOFT_HLUTNM of \tkst[27]_i_1\ : label is "soft_lutpair1766";
  attribute SOFT_HLUTNM of \tkst[28]_i_1\ : label is "soft_lutpair1767";
  attribute SOFT_HLUTNM of \tkst[29]_i_1\ : label is "soft_lutpair1767";
  attribute SOFT_HLUTNM of \tkst[2]_i_1\ : label is "soft_lutpair1754";
  attribute SOFT_HLUTNM of \tkst[30]_i_1\ : label is "soft_lutpair1768";
  attribute SOFT_HLUTNM of \tkst[31]_i_1__0\ : label is "soft_lutpair1768";
  attribute SOFT_HLUTNM of \tkst[3]_i_1\ : label is "soft_lutpair1754";
  attribute SOFT_HLUTNM of \tkst[4]_i_1\ : label is "soft_lutpair1755";
  attribute SOFT_HLUTNM of \tkst[5]_i_1\ : label is "soft_lutpair1755";
  attribute SOFT_HLUTNM of \tkst[6]_i_1\ : label is "soft_lutpair1756";
  attribute SOFT_HLUTNM of \tkst[7]_i_1\ : label is "soft_lutpair1756";
  attribute SOFT_HLUTNM of \tkst[8]_i_1\ : label is "soft_lutpair1757";
  attribute SOFT_HLUTNM of \tkst[9]_i_1\ : label is "soft_lutpair1757";
  attribute SOFT_HLUTNM of \vsync_sig_i[0]_i_1\ : label is "soft_lutpair1806";
  attribute SOFT_HLUTNM of vsync_sig_to_memclk_i_1 : label is "soft_lutpair1806";
  attribute SOFT_HLUTNM of \wordEgrRd[0]_i_1\ : label is "soft_lutpair1743";
  attribute SOFT_HLUTNM of \wordEgrRd[1]_i_1\ : label is "soft_lutpair1743";
  attribute SOFT_HLUTNM of \wordEgrRd[3]_i_3\ : label is "soft_lutpair1730";
  attribute SOFT_HLUTNM of \wordEgrRd[3]_i_5\ : label is "soft_lutpair1802";
  attribute SOFT_HLUTNM of \wordEgrWr[0]_i_1\ : label is "soft_lutpair1738";
  attribute SOFT_HLUTNM of \wordEgrWr[1]_i_1\ : label is "soft_lutpair1738";
  attribute SOFT_HLUTNM of \wordEgrWr[3]_i_3\ : label is "soft_lutpair1730";
  attribute SOFT_HLUTNM of \wordEgrWr[3]_i_4\ : label is "soft_lutpair1803";
  attribute SOFT_HLUTNM of \wrmutex[0]_i_1\ : label is "soft_lutpair1717";
  attribute SOFT_HLUTNM of \wrmutex[1]_i_1\ : label is "soft_lutpair1717";
begin
  \FSM_sequential_stateEgrstr_reg[2]_0\(2 downto 0) <= \^fsm_sequential_stateegrstr_reg[2]_0\(2 downto 0);
  \FSM_sequential_stateIgrstr_reg[0]_0\(0) <= \^fsm_sequential_stateigrstr_reg[0]_0\(0);
  Q(1 downto 0) <= \^q\(1 downto 0);
  ackInvHdrengAssign <= \^ackinvhdrengassign\;
  ackInvHdrengSet <= \^ackinvhdrengset\;
  ddrAXI_wdata_0_sn_1 <= ddrAXI_wdata_0_sp_1;
  egrAXIS_tlast <= \^egraxis_tlast\;
  \ixMemAcq_reg[7]_0\(7 downto 0) <= \^ixmemacq_reg[7]_0\(7 downto 0);
  \ixMem_reg[7]_0\(7 downto 0) <= \^ixmem_reg[7]_0\(7 downto 0);
  rdAAXI_araddr(19 downto 0) <= \^rdaaxi_araddr\(19 downto 0);
  rng_reg_0 <= \^rng_reg_0\;
  \row_lcl_reg[10]_0\(10 downto 0) <= \^row_lcl_reg[10]_0\(10 downto 0);
  stateOp_reg_0 <= \^stateop_reg_0\;
  \stateSwap_reg[3]_0\(3 downto 0) <= \^stateswap_reg[3]_0\(3 downto 0);
  web(0) <= \^web\(0);
\FSM_sequential_stateEgrstr[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFA2AA"
    )
        port map (
      I0 => wrAAXI_wvalid,
      I1 => \^egraxis_tlast\,
      I2 => ddrAXI_wdata_0_sn_1,
      I3 => ddrAXI_wready,
      I4 => \FSM_sequential_stateEgrstr[0]_i_3_n_0\,
      O => p_3_out(0)
    );
\FSM_sequential_stateEgrstr[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      O => wrAAXI_wvalid
    );
\FSM_sequential_stateEgrstr[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000B"
    )
        port map (
      I0 => p_0_in,
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      O => \FSM_sequential_stateEgrstr[0]_i_3_n_0\
    );
\FSM_sequential_stateEgrstr[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0E0E060E0E0E0E0E"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I3 => \^egraxis_tlast\,
      I4 => ddrAXI_wdata_0_sn_1,
      I5 => ddrAXI_wready,
      O => p_3_out(1)
    );
\FSM_sequential_stateEgrstr[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1D1D1D1D1D1D0F1D"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I3 => \^stateswap_reg[3]_0\(2),
      I4 => \^stateswap_reg[3]_0\(1),
      I5 => \^stateswap_reg[3]_0\(3),
      O => \FSM_sequential_stateEgrstr[2]_i_1_n_0\
    );
\FSM_sequential_stateEgrstr[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000000000"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I3 => ddrAXI_wready,
      I4 => ddrAXI_wdata_0_sn_1,
      I5 => \^egraxis_tlast\,
      O => p_3_out(2)
    );
\FSM_sequential_stateEgrstr_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_sequential_stateEgrstr[2]_i_1_n_0\,
      CLR => AR(0),
      D => p_3_out(0),
      Q => \^fsm_sequential_stateegrstr_reg[2]_0\(0)
    );
\FSM_sequential_stateEgrstr_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_sequential_stateEgrstr[2]_i_1_n_0\,
      CLR => AR(0),
      D => p_3_out(1),
      Q => \^fsm_sequential_stateegrstr_reg[2]_0\(1)
    );
\FSM_sequential_stateEgrstr_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_sequential_stateEgrstr[2]_i_1_n_0\,
      CLR => AR(0),
      D => p_3_out(2),
      Q => \^fsm_sequential_stateegrstr_reg[2]_0\(2)
    );
\FSM_sequential_stateIgrstr[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004FFF"
    )
        port map (
      I0 => \FSM_sequential_stateIgrstr[0]_i_2_n_0\,
      I1 => hdrmemAXI_rlast,
      I2 => stateIgrstr(1),
      I3 => \FSM_sequential_stateIgrstr[0]_i_4_n_0\,
      I4 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      O => p_0_out(0)
    );
\FSM_sequential_stateIgrstr[0]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \aRowbufBIgrstr_reg_n_0_[11]\,
      I1 => \aRowbufBIgrstr_reg_n_0_[12]\,
      I2 => \aRowbufBIgrstr_reg_n_0_[9]\,
      I3 => \aRowbufBIgrstr_reg_n_0_[10]\,
      I4 => \FSM_sequential_stateIgrstr[0]_i_12_n_0\,
      O => \FSM_sequential_stateIgrstr[0]_i_10_n_0\
    );
\FSM_sequential_stateIgrstr[0]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \aRowbufBIgrstr_reg_n_0_[22]\,
      I1 => \aRowbufBIgrstr_reg_n_0_[21]\,
      I2 => \aRowbufBIgrstr_reg_n_0_[24]\,
      I3 => \aRowbufBIgrstr_reg_n_0_[23]\,
      O => \FSM_sequential_stateIgrstr[0]_i_11_n_0\
    );
\FSM_sequential_stateIgrstr[0]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \aRowbufBIgrstr_reg_n_0_[14]\,
      I1 => \aRowbufBIgrstr_reg_n_0_[13]\,
      I2 => \aRowbufBIgrstr_reg_n_0_[16]\,
      I3 => \aRowbufBIgrstr_reg_n_0_[15]\,
      O => \FSM_sequential_stateIgrstr[0]_i_12_n_0\
    );
\FSM_sequential_stateIgrstr[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BEFFFFBE"
    )
        port map (
      I0 => \FSM_sequential_stateIgrstr[0]_i_5_n_0\,
      I1 => \burstIgrstr_reg_n_0_[2]\,
      I2 => \^rdaaxi_araddr\(2),
      I3 => \burstIgrstr_reg_n_0_[1]\,
      I4 => \^rdaaxi_araddr\(1),
      O => \FSM_sequential_stateIgrstr[0]_i_2_n_0\
    );
\FSM_sequential_stateIgrstr[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFEF"
    )
        port map (
      I0 => \FSM_sequential_stateIgrstr[0]_i_6_n_0\,
      I1 => \FSM_sequential_stateIgrstr[0]_i_7_n_0\,
      I2 => \aRowbufBIgrstr_reg_n_0_[0]\,
      I3 => \aRowbufBIgrstr_reg_n_0_[29]\,
      I4 => \aRowbufBIgrstr_reg_n_0_[30]\,
      I5 => \FSM_sequential_stateIgrstr[0]_i_8_n_0\,
      O => \FSM_sequential_stateIgrstr[0]_i_4_n_0\
    );
\FSM_sequential_stateIgrstr[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \burstIgrstr_reg_n_0_[4]\,
      I1 => \^rdaaxi_araddr\(4),
      I2 => \burstIgrstr_reg_n_0_[3]\,
      I3 => \^rdaaxi_araddr\(3),
      I4 => \^rdaaxi_araddr\(0),
      I5 => \burstIgrstr_reg_n_0_[0]\,
      O => \FSM_sequential_stateIgrstr[0]_i_5_n_0\
    );
\FSM_sequential_stateIgrstr[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBFFFFFFF"
    )
        port map (
      I0 => \FSM_sequential_stateIgrstr[0]_i_9_n_0\,
      I1 => \aRowbufBIgrstr_reg_n_0_[2]\,
      I2 => \aRowbufBIgrstr_reg_n_0_[1]\,
      I3 => \aRowbufBIgrstr_reg_n_0_[4]\,
      I4 => \aRowbufBIgrstr_reg_n_0_[3]\,
      I5 => \FSM_sequential_stateIgrstr[0]_i_10_n_0\,
      O => \FSM_sequential_stateIgrstr[0]_i_6_n_0\
    );
\FSM_sequential_stateIgrstr[0]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \aRowbufBIgrstr_reg_n_0_[26]\,
      I1 => \aRowbufBIgrstr_reg_n_0_[25]\,
      I2 => \aRowbufBIgrstr_reg_n_0_[28]\,
      I3 => \aRowbufBIgrstr_reg_n_0_[27]\,
      O => \FSM_sequential_stateIgrstr[0]_i_7_n_0\
    );
\FSM_sequential_stateIgrstr[0]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \aRowbufBIgrstr_reg_n_0_[19]\,
      I1 => \aRowbufBIgrstr_reg_n_0_[20]\,
      I2 => \aRowbufBIgrstr_reg_n_0_[17]\,
      I3 => \aRowbufBIgrstr_reg_n_0_[18]\,
      I4 => \FSM_sequential_stateIgrstr[0]_i_11_n_0\,
      O => \FSM_sequential_stateIgrstr[0]_i_8_n_0\
    );
\FSM_sequential_stateIgrstr[0]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \aRowbufBIgrstr_reg_n_0_[6]\,
      I1 => \aRowbufBIgrstr_reg_n_0_[5]\,
      I2 => \aRowbufBIgrstr_reg_n_0_[8]\,
      I3 => \aRowbufBIgrstr_reg_n_0_[7]\,
      O => \FSM_sequential_stateIgrstr[0]_i_9_n_0\
    );
\FSM_sequential_stateIgrstr[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEEEF"
    )
        port map (
      I0 => \FSM_sequential_stateIgrstr[1]_i_3_n_0\,
      I1 => \burstIgrstr_reg[0]_0\,
      I2 => stateIgrstr(1),
      I3 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I4 => \FSM_sequential_stateIgrstr[1]_i_5_n_0\,
      O => \FSM_sequential_stateIgrstr[1]_i_1_n_0\
    );
\FSM_sequential_stateIgrstr[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I1 => stateIgrstr(1),
      O => p_0_out(1)
    );
\FSM_sequential_stateIgrstr[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA00220000030000"
    )
        port map (
      I0 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I1 => \^stateswap_reg[3]_0\(2),
      I2 => \^stateswap_reg[3]_0\(0),
      I3 => \^stateswap_reg[3]_0\(1),
      I4 => \^stateswap_reg[3]_0\(3),
      I5 => stateIgrstr(1),
      O => \FSM_sequential_stateIgrstr[1]_i_3_n_0\
    );
\FSM_sequential_stateIgrstr[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0E0F000000C000C0"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(0),
      I1 => \^stateswap_reg[3]_0\(2),
      I2 => \^stateswap_reg[3]_0\(1),
      I3 => \^stateswap_reg[3]_0\(3),
      I4 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I5 => stateIgrstr(1),
      O => \FSM_sequential_stateIgrstr[1]_i_5_n_0\
    );
\FSM_sequential_stateIgrstr_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_sequential_stateIgrstr[1]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_out(0),
      Q => \^fsm_sequential_stateigrstr_reg[0]_0\(0)
    );
\FSM_sequential_stateIgrstr_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_sequential_stateIgrstr[1]_i_1_n_0\,
      CLR => AR(0),
      D => p_0_out(1),
      Q => stateIgrstr(1)
    );
\a0Egrstr[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => rng_memclk,
      I1 => \^stateswap_reg[3]_0\(1),
      I2 => \^stateswap_reg[3]_0\(3),
      I3 => \^stateswap_reg[3]_0\(0),
      I4 => \^stateswap_reg[3]_0\(2),
      O => a0Egrstr
    );
\a0Egrstr_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => a0Egrstr,
      CLR => AR(0),
      D => \^rdaaxi_araddr\(0),
      Q => \a0Egrstr_reg_n_0_[4]\
    );
\a0Egrstr_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => a0Egrstr,
      CLR => AR(0),
      D => \^rdaaxi_araddr\(1),
      Q => \a0Egrstr_reg_n_0_[5]\
    );
\a0Egrstr_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => a0Egrstr,
      CLR => AR(0),
      D => \^rdaaxi_araddr\(2),
      Q => \a0Egrstr_reg_n_0_[6]\
    );
\a0Egrstr_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => a0Egrstr,
      CLR => AR(0),
      D => \^rdaaxi_araddr\(3),
      Q => \a0Egrstr_reg_n_0_[7]\
    );
\a0Egrstr_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => a0Egrstr,
      CLR => AR(0),
      D => \^rdaaxi_araddr\(4),
      Q => \a0Egrstr_reg_n_0_[8]\
    );
\a0[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \ixMemNext_reg_n_0_[0]\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \a0[0]_i_1_n_0\
    );
\a0[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0E000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^rng_reg_0\,
      I3 => \ixMemNext_reg_n_0_[1]\,
      I4 => \ixMemNext_reg_n_0_[0]\,
      O => \a0[1]_i_1_n_0\
    );
\a0[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E0E000E00000E000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^rng_reg_0\,
      I3 => \ixMemNext_reg_n_0_[1]\,
      I4 => \ixMemNext_reg_n_0_[0]\,
      I5 => \ixMemNext_reg_n_0_[2]\,
      O => \a0[2]_i_1_n_0\
    );
\a0[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"822882A0"
    )
        port map (
      I0 => \a0[4]_i_4_n_0\,
      I1 => \ixMemNext_reg_n_0_[1]\,
      I2 => \ixMemNext_reg_n_0_[3]\,
      I3 => \ixMemNext_reg_n_0_[2]\,
      I4 => \ixMemNext_reg_n_0_[0]\,
      O => \a0[3]_i_1_n_0\
    );
\a0[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"23FF"
    )
        port map (
      I0 => \a0[4]_i_3_n_0\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \a0[4]_i_1_n_0\
    );
\a0[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20082808"
    )
        port map (
      I0 => \a0[4]_i_4_n_0\,
      I1 => \ixMemNext_reg_n_0_[3]\,
      I2 => \ixMemNext_reg_n_0_[2]\,
      I3 => \ixMemNext_reg_n_0_[1]\,
      I4 => \ixMemNext_reg_n_0_[0]\,
      O => \a0[4]_i_2_n_0\
    );
\a0[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \stateStream[1]_i_4_n_0\,
      I1 => \stateStream[1]_i_3_n_0\,
      O => \a0[4]_i_3_n_0\
    );
\a0[4]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => \a0[4]_i_4_n_0\
    );
\a0_i[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"09000009FFFFFFFF"
    )
        port map (
      I0 => \a0_reg_n_0_[4]\,
      I1 => \a0_to_memclk_reg_n_0_[4]\,
      I2 => \a0_to_memclk[4]_i_2_n_0\,
      I3 => \a0_to_memclk_reg_n_0_[3]\,
      I4 => \a0_reg_n_0_[3]\,
      I5 => a0_i,
      O => \a0_i[0]_i_1_n_0\
    );
\a0_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \a0_i[0]_i_1_n_0\,
      Q => a0_i
    );
\a0_memclk[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"90000090"
    )
        port map (
      I0 => a0_to_memclkm1(3),
      I1 => a0_to_memclkm2(3),
      I2 => \a0_memclk[4]_i_2_n_0\,
      I3 => a0_to_memclkm2(4),
      I4 => a0_to_memclkm1(4),
      O => a0_memclk0
    );
\a0_memclk[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => a0_to_memclkm1(0),
      I1 => a0_to_memclkm2(0),
      I2 => a0_to_memclkm2(2),
      I3 => a0_to_memclkm1(2),
      I4 => a0_to_memclkm2(1),
      I5 => a0_to_memclkm1(1),
      O => \a0_memclk[4]_i_2_n_0\
    );
\a0_memclk_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => a0_memclk0,
      CLR => AR(0),
      D => a0_to_memclkm2(0),
      Q => data(8)
    );
\a0_memclk_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => a0_memclk0,
      CLR => AR(0),
      D => a0_to_memclkm2(1),
      Q => data(9)
    );
\a0_memclk_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => a0_memclk0,
      CLR => AR(0),
      D => a0_to_memclkm2(2),
      Q => data(10)
    );
\a0_memclk_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => a0_memclk0,
      CLR => AR(0),
      D => a0_to_memclkm2(3),
      Q => data(11)
    );
\a0_memclk_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => a0_memclk0,
      CLR => AR(0),
      D => a0_to_memclkm2(4),
      Q => data(12)
    );
\a0_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \a0[0]_i_1_n_0\,
      Q => \a0_reg_n_0_[0]\
    );
\a0_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \a0[1]_i_1_n_0\,
      Q => \a0_reg_n_0_[1]\
    );
\a0_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \a0[2]_i_1_n_0\,
      Q => \a0_reg_n_0_[2]\
    );
\a0_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \a0[3]_i_1_n_0\,
      Q => \a0_reg_n_0_[3]\
    );
\a0_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \a0[4]_i_2_n_0\,
      Q => \a0_reg_n_0_[4]\
    );
\a0_to_memclk[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA28AAAAAAAAAA28"
    )
        port map (
      I0 => a0_i,
      I1 => \a0_reg_n_0_[4]\,
      I2 => \a0_to_memclk_reg_n_0_[4]\,
      I3 => \a0_to_memclk[4]_i_2_n_0\,
      I4 => \a0_to_memclk_reg_n_0_[3]\,
      I5 => \a0_reg_n_0_[3]\,
      O => a0_to_memclk
    );
\a0_to_memclk[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \a0_reg_n_0_[0]\,
      I1 => \a0_to_memclk_reg_n_0_[0]\,
      I2 => \a0_to_memclk_reg_n_0_[2]\,
      I3 => \a0_reg_n_0_[2]\,
      I4 => \a0_to_memclk_reg_n_0_[1]\,
      I5 => \a0_reg_n_0_[1]\,
      O => \a0_to_memclk[4]_i_2_n_0\
    );
\a0_to_memclk_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => a0_to_memclk,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \a0_reg_n_0_[0]\,
      Q => \a0_to_memclk_reg_n_0_[0]\
    );
\a0_to_memclk_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => a0_to_memclk,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \a0_reg_n_0_[1]\,
      Q => \a0_to_memclk_reg_n_0_[1]\
    );
\a0_to_memclk_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => a0_to_memclk,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \a0_reg_n_0_[2]\,
      Q => \a0_to_memclk_reg_n_0_[2]\
    );
\a0_to_memclk_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => a0_to_memclk,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \a0_reg_n_0_[3]\,
      Q => \a0_to_memclk_reg_n_0_[3]\
    );
\a0_to_memclk_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => a0_to_memclk,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \a0_reg_n_0_[4]\,
      Q => \a0_to_memclk_reg_n_0_[4]\
    );
\a0_to_memclkm1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \a0_to_memclk_reg_n_0_[0]\,
      Q => a0_to_memclkm1(0)
    );
\a0_to_memclkm1_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \a0_to_memclk_reg_n_0_[1]\,
      Q => a0_to_memclkm1(1)
    );
\a0_to_memclkm1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \a0_to_memclk_reg_n_0_[2]\,
      Q => a0_to_memclkm1(2)
    );
\a0_to_memclkm1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \a0_to_memclk_reg_n_0_[3]\,
      Q => a0_to_memclkm1(3)
    );
\a0_to_memclkm1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \a0_to_memclk_reg_n_0_[4]\,
      Q => a0_to_memclkm1(4)
    );
\a0_to_memclkm2_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => a0_to_memclkm1(0),
      Q => a0_to_memclkm2(0)
    );
\a0_to_memclkm2_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => a0_to_memclkm1(1),
      Q => a0_to_memclkm2(1)
    );
\a0_to_memclkm2_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => a0_to_memclkm1(2),
      Q => a0_to_memclkm2(2)
    );
\a0_to_memclkm2_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => a0_to_memclkm1(3),
      Q => a0_to_memclkm2(3)
    );
\a0_to_memclkm2_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => a0_to_memclkm1(4),
      Q => a0_to_memclkm2(4)
    );
\aRowbufBEgrstr[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I1 => aRowbufBEgrstr(0),
      O => \aRowbufBEgrstr[0]_i_1_n_0\
    );
\aRowbufBEgrstr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I1 => aRowbufBEgrstr(1),
      I2 => aRowbufBEgrstr(0),
      O => \aRowbufBEgrstr[1]_i_1_n_0\
    );
\aRowbufBEgrstr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2888"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I1 => aRowbufBEgrstr(2),
      I2 => aRowbufBEgrstr(0),
      I3 => aRowbufBEgrstr(1),
      O => \aRowbufBEgrstr[2]_i_1_n_0\
    );
\aRowbufBEgrstr[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I1 => aRowbufBEgrstr(3),
      I2 => aRowbufBEgrstr(1),
      I3 => aRowbufBEgrstr(0),
      I4 => aRowbufBEgrstr(2),
      O => \aRowbufBEgrstr[3]_i_1_n_0\
    );
\aRowbufBEgrstr[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6666F000"
    )
        port map (
      I0 => \aRowbufBEgrstr[4]_i_2_n_0\,
      I1 => aRowbufBEgrstr(4),
      I2 => \a0Egrstr_reg_n_0_[4]\,
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      O => \aRowbufBEgrstr[4]_i_1_n_0\
    );
\aRowbufBEgrstr[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => aRowbufBEgrstr(2),
      I1 => aRowbufBEgrstr(0),
      I2 => aRowbufBEgrstr(1),
      I3 => aRowbufBEgrstr(3),
      O => \aRowbufBEgrstr[4]_i_2_n_0\
    );
\aRowbufBEgrstr[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6666F000"
    )
        port map (
      I0 => \aRowbufBEgrstr[6]_i_2_n_0\,
      I1 => aRowbufBEgrstr(5),
      I2 => \a0Egrstr_reg_n_0_[5]\,
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      O => \aRowbufBEgrstr[5]_i_1_n_0\
    );
\aRowbufBEgrstr[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"78787878FF000000"
    )
        port map (
      I0 => aRowbufBEgrstr(5),
      I1 => \aRowbufBEgrstr[6]_i_2_n_0\,
      I2 => aRowbufBEgrstr(6),
      I3 => \a0Egrstr_reg_n_0_[6]\,
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I5 => \aRowbufBEgrstr[6]_i_3_n_0\,
      O => \aRowbufBEgrstr[6]_i_1_n_0\
    );
\aRowbufBEgrstr[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => aRowbufBEgrstr(3),
      I1 => aRowbufBEgrstr(1),
      I2 => aRowbufBEgrstr(0),
      I3 => aRowbufBEgrstr(2),
      I4 => aRowbufBEgrstr(4),
      O => \aRowbufBEgrstr[6]_i_2_n_0\
    );
\aRowbufBEgrstr[6]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      O => \aRowbufBEgrstr[6]_i_3_n_0\
    );
\aRowbufBEgrstr[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAEA"
    )
        port map (
      I0 => \aRowbufBEgrstr[7]_i_2_n_0\,
      I1 => \a0Egrstr_reg_n_0_[7]\,
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      O => \aRowbufBEgrstr[7]_i_1_n_0\
    );
\aRowbufBEgrstr[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0EE0E0E0E0E0E0E0"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I2 => aRowbufBEgrstr(7),
      I3 => aRowbufBEgrstr(6),
      I4 => aRowbufBEgrstr(5),
      I5 => \aRowbufBEgrstr[6]_i_2_n_0\,
      O => \aRowbufBEgrstr[7]_i_2_n_0\
    );
\aRowbufBEgrstr[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000F55500007777"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I1 => \wordEgrRd[3]_i_3_n_0\,
      I2 => \wordEgrWr[3]_i_5_n_0\,
      I3 => \aRowbufBEgrstr_reg[0]_0\,
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I5 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      O => \aRowbufBEgrstr[8]_i_1_n_0\
    );
\aRowbufBEgrstr[8]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAC0"
    )
        port map (
      I0 => in30(8),
      I1 => \a0Egrstr_reg_n_0_[8]\,
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      O => \aRowbufBEgrstr[8]_i_2_n_0\
    );
\aRowbufBEgrstr[8]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \aRowbufBEgrstr[6]_i_2_n_0\,
      I1 => aRowbufBEgrstr(7),
      I2 => aRowbufBEgrstr(6),
      I3 => aRowbufBEgrstr(5),
      I4 => aRowbufBEgrstr(8),
      O => in30(8)
    );
\aRowbufBEgrstr_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBEgrstr[8]_i_1_n_0\,
      CLR => AR(0),
      D => \aRowbufBEgrstr[0]_i_1_n_0\,
      Q => aRowbufBEgrstr(0)
    );
\aRowbufBEgrstr_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBEgrstr[8]_i_1_n_0\,
      CLR => AR(0),
      D => \aRowbufBEgrstr[1]_i_1_n_0\,
      Q => aRowbufBEgrstr(1)
    );
\aRowbufBEgrstr_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBEgrstr[8]_i_1_n_0\,
      CLR => AR(0),
      D => \aRowbufBEgrstr[2]_i_1_n_0\,
      Q => aRowbufBEgrstr(2)
    );
\aRowbufBEgrstr_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBEgrstr[8]_i_1_n_0\,
      CLR => AR(0),
      D => \aRowbufBEgrstr[3]_i_1_n_0\,
      Q => aRowbufBEgrstr(3)
    );
\aRowbufBEgrstr_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBEgrstr[8]_i_1_n_0\,
      CLR => AR(0),
      D => \aRowbufBEgrstr[4]_i_1_n_0\,
      Q => aRowbufBEgrstr(4)
    );
\aRowbufBEgrstr_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBEgrstr[8]_i_1_n_0\,
      CLR => AR(0),
      D => \aRowbufBEgrstr[5]_i_1_n_0\,
      Q => aRowbufBEgrstr(5)
    );
\aRowbufBEgrstr_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBEgrstr[8]_i_1_n_0\,
      CLR => AR(0),
      D => \aRowbufBEgrstr[6]_i_1_n_0\,
      Q => aRowbufBEgrstr(6)
    );
\aRowbufBEgrstr_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBEgrstr[8]_i_1_n_0\,
      CLR => AR(0),
      D => \aRowbufBEgrstr[7]_i_1_n_0\,
      Q => aRowbufBEgrstr(7)
    );
\aRowbufBEgrstr_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBEgrstr[8]_i_1_n_0\,
      CLR => AR(0),
      D => \aRowbufBEgrstr[8]_i_2_n_0\,
      Q => aRowbufBEgrstr(8)
    );
\aRowbufBIgrstr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => \aRowbufBIgrstr_reg_n_0_[0]\,
      O => aRowbufBIgrstr(0)
    );
\aRowbufBIgrstr[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(10),
      O => aRowbufBIgrstr(10)
    );
\aRowbufBIgrstr[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(11),
      O => aRowbufBIgrstr(11)
    );
\aRowbufBIgrstr[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(12),
      O => aRowbufBIgrstr(12)
    );
\aRowbufBIgrstr[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(13),
      O => aRowbufBIgrstr(13)
    );
\aRowbufBIgrstr[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(14),
      O => aRowbufBIgrstr(14)
    );
\aRowbufBIgrstr[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(15),
      O => aRowbufBIgrstr(15)
    );
\aRowbufBIgrstr[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(16),
      O => aRowbufBIgrstr(16)
    );
\aRowbufBIgrstr[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(17),
      O => aRowbufBIgrstr(17)
    );
\aRowbufBIgrstr[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(18),
      O => aRowbufBIgrstr(18)
    );
\aRowbufBIgrstr[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(19),
      O => aRowbufBIgrstr(19)
    );
\aRowbufBIgrstr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(1),
      O => aRowbufBIgrstr(1)
    );
\aRowbufBIgrstr[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(20),
      O => aRowbufBIgrstr(20)
    );
\aRowbufBIgrstr[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(21),
      O => aRowbufBIgrstr(21)
    );
\aRowbufBIgrstr[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(22),
      O => aRowbufBIgrstr(22)
    );
\aRowbufBIgrstr[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(23),
      O => aRowbufBIgrstr(23)
    );
\aRowbufBIgrstr[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(24),
      O => aRowbufBIgrstr(24)
    );
\aRowbufBIgrstr[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(25),
      O => aRowbufBIgrstr(25)
    );
\aRowbufBIgrstr[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(26),
      O => aRowbufBIgrstr(26)
    );
\aRowbufBIgrstr[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(27),
      O => aRowbufBIgrstr(27)
    );
\aRowbufBIgrstr[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(28),
      O => aRowbufBIgrstr(28)
    );
\aRowbufBIgrstr[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(29),
      O => aRowbufBIgrstr(29)
    );
\aRowbufBIgrstr[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(2),
      O => aRowbufBIgrstr(2)
    );
\aRowbufBIgrstr[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B000B000B000FFFF"
    )
        port map (
      I0 => \FSM_sequential_stateIgrstr[0]_i_2_n_0\,
      I1 => hdrmemAXI_rlast,
      I2 => \burstIgrstr_reg[0]_0\,
      I3 => \FSM_sequential_stateIgrstr[0]_i_4_n_0\,
      I4 => stateIgrstr(1),
      I5 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      O => \aRowbufBIgrstr[30]_i_1_n_0\
    );
\aRowbufBIgrstr[30]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(30),
      O => aRowbufBIgrstr(30)
    );
\aRowbufBIgrstr[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(3),
      O => aRowbufBIgrstr(3)
    );
\aRowbufBIgrstr[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(4),
      O => aRowbufBIgrstr(4)
    );
\aRowbufBIgrstr[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(5),
      O => aRowbufBIgrstr(5)
    );
\aRowbufBIgrstr[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(6),
      O => aRowbufBIgrstr(6)
    );
\aRowbufBIgrstr[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(7),
      O => aRowbufBIgrstr(7)
    );
\aRowbufBIgrstr[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(8),
      O => aRowbufBIgrstr(8)
    );
\aRowbufBIgrstr[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => in8(9),
      O => aRowbufBIgrstr(9)
    );
\aRowbufBIgrstr_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(0),
      Q => \aRowbufBIgrstr_reg_n_0_[0]\
    );
\aRowbufBIgrstr_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(10),
      Q => \aRowbufBIgrstr_reg_n_0_[10]\
    );
\aRowbufBIgrstr_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(11),
      Q => \aRowbufBIgrstr_reg_n_0_[11]\
    );
\aRowbufBIgrstr_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(12),
      Q => \aRowbufBIgrstr_reg_n_0_[12]\
    );
\aRowbufBIgrstr_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(13),
      Q => \aRowbufBIgrstr_reg_n_0_[13]\
    );
\aRowbufBIgrstr_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(14),
      Q => \aRowbufBIgrstr_reg_n_0_[14]\
    );
\aRowbufBIgrstr_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(15),
      Q => \aRowbufBIgrstr_reg_n_0_[15]\
    );
\aRowbufBIgrstr_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(16),
      Q => \aRowbufBIgrstr_reg_n_0_[16]\
    );
\aRowbufBIgrstr_reg[16]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \aRowbufBIgrstr_reg[8]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \aRowbufBIgrstr_reg[16]_i_2_n_0\,
      CO(6) => \aRowbufBIgrstr_reg[16]_i_2_n_1\,
      CO(5) => \aRowbufBIgrstr_reg[16]_i_2_n_2\,
      CO(4) => \aRowbufBIgrstr_reg[16]_i_2_n_3\,
      CO(3) => \aRowbufBIgrstr_reg[16]_i_2_n_4\,
      CO(2) => \aRowbufBIgrstr_reg[16]_i_2_n_5\,
      CO(1) => \aRowbufBIgrstr_reg[16]_i_2_n_6\,
      CO(0) => \aRowbufBIgrstr_reg[16]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in8(16 downto 9),
      S(7) => \aRowbufBIgrstr_reg_n_0_[16]\,
      S(6) => \aRowbufBIgrstr_reg_n_0_[15]\,
      S(5) => \aRowbufBIgrstr_reg_n_0_[14]\,
      S(4) => \aRowbufBIgrstr_reg_n_0_[13]\,
      S(3) => \aRowbufBIgrstr_reg_n_0_[12]\,
      S(2) => \aRowbufBIgrstr_reg_n_0_[11]\,
      S(1) => \aRowbufBIgrstr_reg_n_0_[10]\,
      S(0) => \aRowbufBIgrstr_reg_n_0_[9]\
    );
\aRowbufBIgrstr_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(17),
      Q => \aRowbufBIgrstr_reg_n_0_[17]\
    );
\aRowbufBIgrstr_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(18),
      Q => \aRowbufBIgrstr_reg_n_0_[18]\
    );
\aRowbufBIgrstr_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(19),
      Q => \aRowbufBIgrstr_reg_n_0_[19]\
    );
\aRowbufBIgrstr_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(1),
      Q => \aRowbufBIgrstr_reg_n_0_[1]\
    );
\aRowbufBIgrstr_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(20),
      Q => \aRowbufBIgrstr_reg_n_0_[20]\
    );
\aRowbufBIgrstr_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(21),
      Q => \aRowbufBIgrstr_reg_n_0_[21]\
    );
\aRowbufBIgrstr_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(22),
      Q => \aRowbufBIgrstr_reg_n_0_[22]\
    );
\aRowbufBIgrstr_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(23),
      Q => \aRowbufBIgrstr_reg_n_0_[23]\
    );
\aRowbufBIgrstr_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(24),
      Q => \aRowbufBIgrstr_reg_n_0_[24]\
    );
\aRowbufBIgrstr_reg[24]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \aRowbufBIgrstr_reg[16]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \aRowbufBIgrstr_reg[24]_i_2_n_0\,
      CO(6) => \aRowbufBIgrstr_reg[24]_i_2_n_1\,
      CO(5) => \aRowbufBIgrstr_reg[24]_i_2_n_2\,
      CO(4) => \aRowbufBIgrstr_reg[24]_i_2_n_3\,
      CO(3) => \aRowbufBIgrstr_reg[24]_i_2_n_4\,
      CO(2) => \aRowbufBIgrstr_reg[24]_i_2_n_5\,
      CO(1) => \aRowbufBIgrstr_reg[24]_i_2_n_6\,
      CO(0) => \aRowbufBIgrstr_reg[24]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in8(24 downto 17),
      S(7) => \aRowbufBIgrstr_reg_n_0_[24]\,
      S(6) => \aRowbufBIgrstr_reg_n_0_[23]\,
      S(5) => \aRowbufBIgrstr_reg_n_0_[22]\,
      S(4) => \aRowbufBIgrstr_reg_n_0_[21]\,
      S(3) => \aRowbufBIgrstr_reg_n_0_[20]\,
      S(2) => \aRowbufBIgrstr_reg_n_0_[19]\,
      S(1) => \aRowbufBIgrstr_reg_n_0_[18]\,
      S(0) => \aRowbufBIgrstr_reg_n_0_[17]\
    );
\aRowbufBIgrstr_reg[25]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(25),
      Q => \aRowbufBIgrstr_reg_n_0_[25]\
    );
\aRowbufBIgrstr_reg[26]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(26),
      Q => \aRowbufBIgrstr_reg_n_0_[26]\
    );
\aRowbufBIgrstr_reg[27]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(27),
      Q => \aRowbufBIgrstr_reg_n_0_[27]\
    );
\aRowbufBIgrstr_reg[28]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(28),
      Q => \aRowbufBIgrstr_reg_n_0_[28]\
    );
\aRowbufBIgrstr_reg[29]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(29),
      Q => \aRowbufBIgrstr_reg_n_0_[29]\
    );
\aRowbufBIgrstr_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(2),
      Q => \aRowbufBIgrstr_reg_n_0_[2]\
    );
\aRowbufBIgrstr_reg[30]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(30),
      Q => \aRowbufBIgrstr_reg_n_0_[30]\
    );
\aRowbufBIgrstr_reg[30]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \aRowbufBIgrstr_reg[24]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_aRowbufBIgrstr_reg[30]_i_3_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \aRowbufBIgrstr_reg[30]_i_3_n_3\,
      CO(3) => \aRowbufBIgrstr_reg[30]_i_3_n_4\,
      CO(2) => \aRowbufBIgrstr_reg[30]_i_3_n_5\,
      CO(1) => \aRowbufBIgrstr_reg[30]_i_3_n_6\,
      CO(0) => \aRowbufBIgrstr_reg[30]_i_3_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 6) => \NLW_aRowbufBIgrstr_reg[30]_i_3_O_UNCONNECTED\(7 downto 6),
      O(5 downto 0) => in8(30 downto 25),
      S(7 downto 6) => B"00",
      S(5) => \aRowbufBIgrstr_reg_n_0_[30]\,
      S(4) => \aRowbufBIgrstr_reg_n_0_[29]\,
      S(3) => \aRowbufBIgrstr_reg_n_0_[28]\,
      S(2) => \aRowbufBIgrstr_reg_n_0_[27]\,
      S(1) => \aRowbufBIgrstr_reg_n_0_[26]\,
      S(0) => \aRowbufBIgrstr_reg_n_0_[25]\
    );
\aRowbufBIgrstr_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(3),
      Q => \aRowbufBIgrstr_reg_n_0_[3]\
    );
\aRowbufBIgrstr_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(4),
      Q => \aRowbufBIgrstr_reg_n_0_[4]\
    );
\aRowbufBIgrstr_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(5),
      Q => \aRowbufBIgrstr_reg_n_0_[5]\
    );
\aRowbufBIgrstr_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(6),
      Q => \aRowbufBIgrstr_reg_n_0_[6]\
    );
\aRowbufBIgrstr_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(7),
      Q => \aRowbufBIgrstr_reg_n_0_[7]\
    );
\aRowbufBIgrstr_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(8),
      Q => \aRowbufBIgrstr_reg_n_0_[8]\
    );
\aRowbufBIgrstr_reg[8]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \aRowbufBIgrstr_reg_n_0_[0]\,
      CI_TOP => '0',
      CO(7) => \aRowbufBIgrstr_reg[8]_i_2_n_0\,
      CO(6) => \aRowbufBIgrstr_reg[8]_i_2_n_1\,
      CO(5) => \aRowbufBIgrstr_reg[8]_i_2_n_2\,
      CO(4) => \aRowbufBIgrstr_reg[8]_i_2_n_3\,
      CO(3) => \aRowbufBIgrstr_reg[8]_i_2_n_4\,
      CO(2) => \aRowbufBIgrstr_reg[8]_i_2_n_5\,
      CO(1) => \aRowbufBIgrstr_reg[8]_i_2_n_6\,
      CO(0) => \aRowbufBIgrstr_reg[8]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in8(8 downto 1),
      S(7) => \aRowbufBIgrstr_reg_n_0_[8]\,
      S(6) => \aRowbufBIgrstr_reg_n_0_[7]\,
      S(5) => \aRowbufBIgrstr_reg_n_0_[6]\,
      S(4) => \aRowbufBIgrstr_reg_n_0_[5]\,
      S(3) => \aRowbufBIgrstr_reg_n_0_[4]\,
      S(2) => \aRowbufBIgrstr_reg_n_0_[3]\,
      S(1) => \aRowbufBIgrstr_reg_n_0_[2]\,
      S(0) => \aRowbufBIgrstr_reg_n_0_[1]\
    );
\aRowbufBIgrstr_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aRowbufBIgrstr[30]_i_1_n_0\,
      CLR => AR(0),
      D => aRowbufBIgrstr(9),
      Q => \aRowbufBIgrstr_reg_n_0_[9]\
    );
\aRowbufStockrls[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => stateStockrls(0),
      I2 => stateStockrls(1),
      I3 => aRowbufStockrls(0),
      O => \aRowbufStockrls[0]_i_1_n_0\
    );
\aRowbufStockrls[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"05FFDDFF"
    )
        port map (
      I0 => stateStockrls(0),
      I1 => rgbVideoinToManyAXIS_tvalid,
      I2 => \stateStream_reg[1]_0\,
      I3 => \^rng_reg_0\,
      I4 => stateStockrls(1),
      O => \aRowbufStockrls[10]_i_1_n_0\
    );
\aRowbufStockrls[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00404000"
    )
        port map (
      I0 => stateStockrls(1),
      I1 => stateStockrls(0),
      I2 => \^rng_reg_0\,
      I3 => aRowbufStockrls(10),
      I4 => \aRowbufStockrls[10]_i_3_n_0\,
      O => \aRowbufStockrls[10]_i_2_n_0\
    );
\aRowbufStockrls[10]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => aRowbufStockrls(8),
      I1 => aRowbufStockrls(6),
      I2 => \aRowbufStockrls[9]_i_3_n_0\,
      I3 => aRowbufStockrls(7),
      I4 => aRowbufStockrls(9),
      O => \aRowbufStockrls[10]_i_3_n_0\
    );
\aRowbufStockrls[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => stateStockrls(0),
      I2 => stateStockrls(1),
      I3 => aRowbufStockrls(1),
      I4 => aRowbufStockrls(0),
      O => \aRowbufStockrls[1]_i_1_n_0\
    );
\aRowbufStockrls[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040404040000000"
    )
        port map (
      I0 => stateStockrls(1),
      I1 => stateStockrls(0),
      I2 => \^rng_reg_0\,
      I3 => aRowbufStockrls(0),
      I4 => aRowbufStockrls(1),
      I5 => aRowbufStockrls(2),
      O => \aRowbufStockrls[2]_i_1_n_0\
    );
\aRowbufStockrls[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \aRowbufStockrls[9]_i_2_n_0\,
      I1 => aRowbufStockrls(3),
      I2 => aRowbufStockrls(2),
      I3 => aRowbufStockrls(1),
      I4 => aRowbufStockrls(0),
      O => \aRowbufStockrls[3]_i_1_n_0\
    );
\aRowbufStockrls[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \aRowbufStockrls[9]_i_2_n_0\,
      I1 => aRowbufStockrls(4),
      I2 => aRowbufStockrls(0),
      I3 => aRowbufStockrls(1),
      I4 => aRowbufStockrls(2),
      I5 => aRowbufStockrls(3),
      O => \aRowbufStockrls[4]_i_1_n_0\
    );
\aRowbufStockrls[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00404000"
    )
        port map (
      I0 => stateStockrls(1),
      I1 => stateStockrls(0),
      I2 => \^rng_reg_0\,
      I3 => aRowbufStockrls(5),
      I4 => \aRowbufStockrls[5]_i_2_n_0\,
      O => \aRowbufStockrls[5]_i_1_n_0\
    );
\aRowbufStockrls[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => aRowbufStockrls(3),
      I1 => aRowbufStockrls(2),
      I2 => aRowbufStockrls(1),
      I3 => aRowbufStockrls(0),
      I4 => aRowbufStockrls(4),
      O => \aRowbufStockrls[5]_i_2_n_0\
    );
\aRowbufStockrls[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00404000"
    )
        port map (
      I0 => stateStockrls(1),
      I1 => stateStockrls(0),
      I2 => \^rng_reg_0\,
      I3 => aRowbufStockrls(6),
      I4 => \aRowbufStockrls[9]_i_3_n_0\,
      O => \aRowbufStockrls[6]_i_1_n_0\
    );
\aRowbufStockrls[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040400040004000"
    )
        port map (
      I0 => stateStockrls(1),
      I1 => stateStockrls(0),
      I2 => \^rng_reg_0\,
      I3 => aRowbufStockrls(7),
      I4 => \aRowbufStockrls[9]_i_3_n_0\,
      I5 => aRowbufStockrls(6),
      O => \aRowbufStockrls[7]_i_1_n_0\
    );
\aRowbufStockrls[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \aRowbufStockrls[9]_i_2_n_0\,
      I1 => aRowbufStockrls(8),
      I2 => aRowbufStockrls(6),
      I3 => \aRowbufStockrls[9]_i_3_n_0\,
      I4 => aRowbufStockrls(7),
      O => \aRowbufStockrls[8]_i_1_n_0\
    );
\aRowbufStockrls[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \aRowbufStockrls[9]_i_2_n_0\,
      I1 => aRowbufStockrls(9),
      I2 => aRowbufStockrls(7),
      I3 => \aRowbufStockrls[9]_i_3_n_0\,
      I4 => aRowbufStockrls(6),
      I5 => aRowbufStockrls(8),
      O => \aRowbufStockrls[9]_i_1_n_0\
    );
\aRowbufStockrls[9]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => stateStockrls(1),
      I1 => stateStockrls(0),
      I2 => \^rng_reg_0\,
      O => \aRowbufStockrls[9]_i_2_n_0\
    );
\aRowbufStockrls[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => aRowbufStockrls(4),
      I1 => aRowbufStockrls(0),
      I2 => aRowbufStockrls(1),
      I3 => aRowbufStockrls(2),
      I4 => aRowbufStockrls(3),
      I5 => aRowbufStockrls(5),
      O => \aRowbufStockrls[9]_i_3_n_0\
    );
\aRowbufStockrls_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStockrls[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStockrls[0]_i_1_n_0\,
      Q => aRowbufStockrls(0)
    );
\aRowbufStockrls_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStockrls[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStockrls[10]_i_2_n_0\,
      Q => aRowbufStockrls(10)
    );
\aRowbufStockrls_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStockrls[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStockrls[1]_i_1_n_0\,
      Q => aRowbufStockrls(1)
    );
\aRowbufStockrls_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStockrls[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStockrls[2]_i_1_n_0\,
      Q => aRowbufStockrls(2)
    );
\aRowbufStockrls_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStockrls[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStockrls[3]_i_1_n_0\,
      Q => aRowbufStockrls(3)
    );
\aRowbufStockrls_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStockrls[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStockrls[4]_i_1_n_0\,
      Q => aRowbufStockrls(4)
    );
\aRowbufStockrls_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStockrls[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStockrls[5]_i_1_n_0\,
      Q => aRowbufStockrls(5)
    );
\aRowbufStockrls_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStockrls[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStockrls[6]_i_1_n_0\,
      Q => aRowbufStockrls(6)
    );
\aRowbufStockrls_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStockrls[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStockrls[7]_i_1_n_0\,
      Q => aRowbufStockrls(7)
    );
\aRowbufStockrls_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStockrls[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStockrls[8]_i_1_n_0\,
      Q => aRowbufStockrls(8)
    );
\aRowbufStockrls_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStockrls[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStockrls[9]_i_1_n_0\,
      Q => aRowbufStockrls(9)
    );
\aRowbufStream[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^rng_reg_0\,
      I3 => \aRowbufStream__0\(0),
      O => \aRowbufStream[0]_i_1_n_0\
    );
\aRowbufStream[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA8AAAAAAAA"
    )
        port map (
      I0 => \col_lcl[10]_i_1_n_0\,
      I1 => col_lcl(3),
      I2 => col_lcl(10),
      I3 => col_lcl(5),
      I4 => \aRowbufStream[10]_i_3_n_0\,
      I5 => \aRowbufStream[10]_i_4_n_0\,
      O => \aRowbufStream[10]_i_1_n_0\
    );
\aRowbufStream[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \aRowbufStream__0\(10),
      I4 => \aRowbufStream[10]_i_5_n_0\,
      O => \aRowbufStream[10]_i_2_n_0\
    );
\aRowbufStream[10]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => col_lcl(8),
      I1 => col_lcl(9),
      I2 => col_lcl(4),
      I3 => col_lcl(7),
      I4 => \aRowbufStream[10]_i_6_n_0\,
      O => \aRowbufStream[10]_i_3_n_0\
    );
\aRowbufStream[10]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => \aRowbufStream[10]_i_4_n_0\
    );
\aRowbufStream[10]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aRowbufStream__0\(8),
      I1 => \aRowbufStream__0\(6),
      I2 => \aRowbufStream[9]_i_2_n_0\,
      I3 => \aRowbufStream__0\(7),
      I4 => \aRowbufStream__0\(9),
      O => \aRowbufStream[10]_i_5_n_0\
    );
\aRowbufStream[10]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => col_lcl(1),
      I1 => col_lcl(0),
      I2 => col_lcl(6),
      I3 => col_lcl(2),
      O => \aRowbufStream[10]_i_6_n_0\
    );
\aRowbufStream[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00404000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^rng_reg_0\,
      I3 => \aRowbufStream__0\(1),
      I4 => \aRowbufStream__0\(0),
      O => \aRowbufStream[1]_i_1_n_0\
    );
\aRowbufStream[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008080808000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \aRowbufStream__0\(0),
      I4 => \aRowbufStream__0\(1),
      I5 => \aRowbufStream__0\(2),
      O => \aRowbufStream[2]_i_1_n_0\
    );
\aRowbufStream[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \col_lcl[9]_i_3_n_0\,
      I1 => \aRowbufStream__0\(3),
      I2 => \aRowbufStream__0\(2),
      I3 => \aRowbufStream__0\(1),
      I4 => \aRowbufStream__0\(0),
      O => \aRowbufStream[3]_i_1_n_0\
    );
\aRowbufStream[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \col_lcl[9]_i_3_n_0\,
      I1 => \aRowbufStream__0\(4),
      I2 => \aRowbufStream__0\(0),
      I3 => \aRowbufStream__0\(1),
      I4 => \aRowbufStream__0\(2),
      I5 => \aRowbufStream__0\(3),
      O => \aRowbufStream[4]_i_1_n_0\
    );
\aRowbufStream[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \aRowbufStream__0\(5),
      I4 => \aRowbufStream[5]_i_2_n_0\,
      O => \aRowbufStream[5]_i_1_n_0\
    );
\aRowbufStream[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aRowbufStream__0\(3),
      I1 => \aRowbufStream__0\(2),
      I2 => \aRowbufStream__0\(1),
      I3 => \aRowbufStream__0\(0),
      I4 => \aRowbufStream__0\(4),
      O => \aRowbufStream[5]_i_2_n_0\
    );
\aRowbufStream[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \aRowbufStream__0\(6),
      I4 => \aRowbufStream[9]_i_2_n_0\,
      O => \aRowbufStream[6]_i_1_n_0\
    );
\aRowbufStream[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008080008000800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \aRowbufStream__0\(7),
      I4 => \aRowbufStream[9]_i_2_n_0\,
      I5 => \aRowbufStream__0\(6),
      O => \aRowbufStream[7]_i_1_n_0\
    );
\aRowbufStream[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \col_lcl[9]_i_3_n_0\,
      I1 => \aRowbufStream__0\(8),
      I2 => \aRowbufStream__0\(6),
      I3 => \aRowbufStream[9]_i_2_n_0\,
      I4 => \aRowbufStream__0\(7),
      O => \aRowbufStream[8]_i_1_n_0\
    );
\aRowbufStream[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \col_lcl[9]_i_3_n_0\,
      I1 => \aRowbufStream__0\(9),
      I2 => \aRowbufStream__0\(7),
      I3 => \aRowbufStream[9]_i_2_n_0\,
      I4 => \aRowbufStream__0\(6),
      I5 => \aRowbufStream__0\(8),
      O => \aRowbufStream[9]_i_1_n_0\
    );
\aRowbufStream[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aRowbufStream__0\(4),
      I1 => \aRowbufStream__0\(0),
      I2 => \aRowbufStream__0\(1),
      I3 => \aRowbufStream__0\(2),
      I4 => \aRowbufStream__0\(3),
      I5 => \aRowbufStream__0\(5),
      O => \aRowbufStream[9]_i_2_n_0\
    );
\aRowbufStream_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStream[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStream[0]_i_1_n_0\,
      Q => \aRowbufStream__0\(0)
    );
\aRowbufStream_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStream[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStream[10]_i_2_n_0\,
      Q => \aRowbufStream__0\(10)
    );
\aRowbufStream_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStream[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStream[1]_i_1_n_0\,
      Q => \aRowbufStream__0\(1)
    );
\aRowbufStream_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStream[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStream[2]_i_1_n_0\,
      Q => \aRowbufStream__0\(2)
    );
\aRowbufStream_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStream[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStream[3]_i_1_n_0\,
      Q => \aRowbufStream__0\(3)
    );
\aRowbufStream_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStream[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStream[4]_i_1_n_0\,
      Q => \aRowbufStream__0\(4)
    );
\aRowbufStream_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStream[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStream[5]_i_1_n_0\,
      Q => \aRowbufStream__0\(5)
    );
\aRowbufStream_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStream[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStream[6]_i_1_n_0\,
      Q => \aRowbufStream__0\(6)
    );
\aRowbufStream_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStream[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStream[7]_i_1_n_0\,
      Q => \aRowbufStream__0\(7)
    );
\aRowbufStream_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStream[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStream[8]_i_1_n_0\,
      Q => \aRowbufStream__0\(8)
    );
\aRowbufStream_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufStream[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \aRowbufStream[9]_i_1_n_0\,
      Q => \aRowbufStream__0\(9)
    );
ackInvAssign_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stateOp,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => ackInvAssign_sig,
      Q => \^ackinvhdrengassign\
    );
ackInvSet_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stateOp,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => ackInvSet_sig_reg_0,
      Q => \^ackinvhdrengset\
    );
\addrEgr[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FEFF"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(1),
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => \^stateswap_reg[3]_0\(0),
      I4 => wrAAXI_awaddr(5),
      O => \p_0_in__0\(0)
    );
\addrEgr[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6F60"
    )
        port map (
      I0 => \addrEgr[10]_i_2_n_0\,
      I1 => wrAAXI_awaddr(15),
      I2 => \row_lcl[10]_i_4_n_0\,
      I3 => data(10),
      O => \p_0_in__0\(10)
    );
\addrEgr[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => wrAAXI_awaddr(13),
      I1 => wrAAXI_awaddr(11),
      I2 => \addrEgr[8]_i_2_n_0\,
      I3 => wrAAXI_awaddr(12),
      I4 => wrAAXI_awaddr(14),
      O => \addrEgr[10]_i_2_n_0\
    );
\addrEgr[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6F60"
    )
        port map (
      I0 => \addrEgr[14]_i_4_n_0\,
      I1 => wrAAXI_awaddr(16),
      I2 => \row_lcl[10]_i_4_n_0\,
      I3 => data(11),
      O => \p_0_in__0\(11)
    );
\addrEgr[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78FF7800"
    )
        port map (
      I0 => wrAAXI_awaddr(16),
      I1 => \addrEgr[14]_i_4_n_0\,
      I2 => wrAAXI_awaddr(17),
      I3 => \row_lcl[10]_i_4_n_0\,
      I4 => data(12),
      O => \p_0_in__0\(12)
    );
\addrEgr[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \row_lcl[10]_i_4_n_0\,
      I1 => wrAAXI_awaddr(18),
      I2 => wrAAXI_awaddr(17),
      I3 => wrAAXI_awaddr(16),
      I4 => \addrEgr[14]_i_4_n_0\,
      O => \p_0_in__0\(13)
    );
\addrEgr[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0040"
    )
        port map (
      I0 => \row_lcl[10]_i_4_n_0\,
      I1 => rng_memclk,
      I2 => \i_reg_n_0_[1]\,
      I3 => \i_reg_n_0_[0]\,
      I4 => \addrEgr[14]_i_3_n_0\,
      O => addrEgr
    );
\addrEgr[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \row_lcl[10]_i_4_n_0\,
      I1 => wrAAXI_awaddr(19),
      I2 => wrAAXI_awaddr(16),
      I3 => wrAAXI_awaddr(17),
      I4 => wrAAXI_awaddr(18),
      I5 => \addrEgr[14]_i_4_n_0\,
      O => \p_0_in__0\(14)
    );
\addrEgr[14]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(1),
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I5 => \stateSwap[1]_i_3_n_0\,
      O => \addrEgr[14]_i_3_n_0\
    );
\addrEgr[14]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => wrAAXI_awaddr(14),
      I1 => wrAAXI_awaddr(12),
      I2 => \addrEgr[8]_i_2_n_0\,
      I3 => wrAAXI_awaddr(11),
      I4 => wrAAXI_awaddr(13),
      I5 => wrAAXI_awaddr(15),
      O => \addrEgr[14]_i_4_n_0\
    );
\addrEgr[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FEFFFEFF0000"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(1),
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => \^stateswap_reg[3]_0\(0),
      I4 => wrAAXI_awaddr(6),
      I5 => wrAAXI_awaddr(5),
      O => \p_0_in__0\(1)
    );
\addrEgr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2888"
    )
        port map (
      I0 => \row_lcl[10]_i_4_n_0\,
      I1 => wrAAXI_awaddr(7),
      I2 => wrAAXI_awaddr(5),
      I3 => wrAAXI_awaddr(6),
      O => \p_0_in__0\(2)
    );
\addrEgr[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \row_lcl[10]_i_4_n_0\,
      I1 => wrAAXI_awaddr(8),
      I2 => wrAAXI_awaddr(6),
      I3 => wrAAXI_awaddr(5),
      I4 => wrAAXI_awaddr(7),
      O => \p_0_in__0\(3)
    );
\addrEgr[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \row_lcl[10]_i_4_n_0\,
      I1 => wrAAXI_awaddr(9),
      I2 => wrAAXI_awaddr(7),
      I3 => wrAAXI_awaddr(5),
      I4 => wrAAXI_awaddr(6),
      I5 => wrAAXI_awaddr(8),
      O => \p_0_in__0\(4)
    );
\addrEgr[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FEFFFEFF0000"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(1),
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => \^stateswap_reg[3]_0\(0),
      I4 => wrAAXI_awaddr(10),
      I5 => \addrEgr[5]_i_2_n_0\,
      O => \p_0_in__0\(5)
    );
\addrEgr[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => wrAAXI_awaddr(8),
      I1 => wrAAXI_awaddr(6),
      I2 => wrAAXI_awaddr(5),
      I3 => wrAAXI_awaddr(7),
      I4 => wrAAXI_awaddr(9),
      O => \addrEgr[5]_i_2_n_0\
    );
\addrEgr[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FEFFFEFF0000"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(1),
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => \^stateswap_reg[3]_0\(0),
      I4 => wrAAXI_awaddr(11),
      I5 => \addrEgr[8]_i_2_n_0\,
      O => \p_0_in__0\(6)
    );
\addrEgr[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2888"
    )
        port map (
      I0 => \row_lcl[10]_i_4_n_0\,
      I1 => wrAAXI_awaddr(12),
      I2 => \addrEgr[8]_i_2_n_0\,
      I3 => wrAAXI_awaddr(11),
      O => \p_0_in__0\(7)
    );
\addrEgr[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F80FFFF7F800000"
    )
        port map (
      I0 => wrAAXI_awaddr(12),
      I1 => \addrEgr[8]_i_2_n_0\,
      I2 => wrAAXI_awaddr(11),
      I3 => wrAAXI_awaddr(13),
      I4 => \row_lcl[10]_i_4_n_0\,
      I5 => data(8),
      O => \p_0_in__0\(8)
    );
\addrEgr[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => wrAAXI_awaddr(9),
      I1 => wrAAXI_awaddr(7),
      I2 => wrAAXI_awaddr(5),
      I3 => wrAAXI_awaddr(6),
      I4 => wrAAXI_awaddr(8),
      I5 => wrAAXI_awaddr(10),
      O => \addrEgr[8]_i_2_n_0\
    );
\addrEgr[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6F60"
    )
        port map (
      I0 => \addrEgr[9]_i_2_n_0\,
      I1 => wrAAXI_awaddr(14),
      I2 => \row_lcl[10]_i_4_n_0\,
      I3 => data(9),
      O => \p_0_in__0\(9)
    );
\addrEgr[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => wrAAXI_awaddr(12),
      I1 => \addrEgr[8]_i_2_n_0\,
      I2 => wrAAXI_awaddr(11),
      I3 => wrAAXI_awaddr(13),
      O => \addrEgr[9]_i_2_n_0\
    );
\addrEgr_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(0),
      Q => wrAAXI_awaddr(5)
    );
\addrEgr_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(10),
      Q => wrAAXI_awaddr(15)
    );
\addrEgr_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(11),
      Q => wrAAXI_awaddr(16)
    );
\addrEgr_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(12),
      Q => wrAAXI_awaddr(17)
    );
\addrEgr_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(13),
      Q => wrAAXI_awaddr(18)
    );
\addrEgr_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(14),
      Q => wrAAXI_awaddr(19)
    );
\addrEgr_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(1),
      Q => wrAAXI_awaddr(6)
    );
\addrEgr_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(2),
      Q => wrAAXI_awaddr(7)
    );
\addrEgr_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(3),
      Q => wrAAXI_awaddr(8)
    );
\addrEgr_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(4),
      Q => wrAAXI_awaddr(9)
    );
\addrEgr_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(5),
      Q => wrAAXI_awaddr(10)
    );
\addrEgr_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(6),
      Q => wrAAXI_awaddr(11)
    );
\addrEgr_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(7),
      Q => wrAAXI_awaddr(12)
    );
\addrEgr_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(8),
      Q => wrAAXI_awaddr(13)
    );
\addrEgr_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrEgr,
      CLR => AR(0),
      D => \p_0_in__0\(9),
      Q => wrAAXI_awaddr(14)
    );
\addrIgr[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FEFF"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(1),
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => \^stateswap_reg[3]_0\(0),
      I4 => \^rdaaxi_araddr\(5),
      O => \p_0_in__0__0\(0)
    );
\addrIgr[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6F60"
    )
        port map (
      I0 => \addrIgr[10]_i_2_n_0\,
      I1 => \^rdaaxi_araddr\(15),
      I2 => \row_lcl[10]_i_4_n_0\,
      I3 => data(10),
      O => \p_0_in__0__0\(10)
    );
\addrIgr[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^rdaaxi_araddr\(13),
      I1 => \^rdaaxi_araddr\(11),
      I2 => \addrIgr[8]_i_2_n_0\,
      I3 => \^rdaaxi_araddr\(12),
      I4 => \^rdaaxi_araddr\(14),
      O => \addrIgr[10]_i_2_n_0\
    );
\addrIgr[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6F60"
    )
        port map (
      I0 => \addrIgr[14]_i_3_n_0\,
      I1 => \^rdaaxi_araddr\(16),
      I2 => \row_lcl[10]_i_4_n_0\,
      I3 => data(11),
      O => \p_0_in__0__0\(11)
    );
\addrIgr[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78FF7800"
    )
        port map (
      I0 => \^rdaaxi_araddr\(16),
      I1 => \addrIgr[14]_i_3_n_0\,
      I2 => \^rdaaxi_araddr\(17),
      I3 => \row_lcl[10]_i_4_n_0\,
      I4 => data(12),
      O => \p_0_in__0__0\(12)
    );
\addrIgr[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \row_lcl[10]_i_4_n_0\,
      I1 => \^rdaaxi_araddr\(18),
      I2 => \^rdaaxi_araddr\(17),
      I3 => \^rdaaxi_araddr\(16),
      I4 => \addrIgr[14]_i_3_n_0\,
      O => \p_0_in__0__0\(13)
    );
\addrIgr[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF04000004040000"
    )
        port map (
      I0 => \row_lcl[10]_i_4_n_0\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => \^stateswap_reg[3]_0\(3),
      I4 => rng_memclk,
      I5 => \row_lcl[10]_i_5_n_0\,
      O => addrIgr
    );
\addrIgr[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \row_lcl[10]_i_4_n_0\,
      I1 => \^rdaaxi_araddr\(19),
      I2 => \^rdaaxi_araddr\(16),
      I3 => \^rdaaxi_araddr\(17),
      I4 => \^rdaaxi_araddr\(18),
      I5 => \addrIgr[14]_i_3_n_0\,
      O => \p_0_in__0__0\(14)
    );
\addrIgr[14]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^rdaaxi_araddr\(14),
      I1 => \^rdaaxi_araddr\(12),
      I2 => \addrIgr[8]_i_2_n_0\,
      I3 => \^rdaaxi_araddr\(11),
      I4 => \^rdaaxi_araddr\(13),
      I5 => \^rdaaxi_araddr\(15),
      O => \addrIgr[14]_i_3_n_0\
    );
\addrIgr[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FEFFFEFF0000"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(1),
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => \^stateswap_reg[3]_0\(0),
      I4 => \^rdaaxi_araddr\(6),
      I5 => \^rdaaxi_araddr\(5),
      O => \p_0_in__0__0\(1)
    );
\addrIgr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2888"
    )
        port map (
      I0 => \row_lcl[10]_i_4_n_0\,
      I1 => \^rdaaxi_araddr\(7),
      I2 => \^rdaaxi_araddr\(5),
      I3 => \^rdaaxi_araddr\(6),
      O => \p_0_in__0__0\(2)
    );
\addrIgr[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \row_lcl[10]_i_4_n_0\,
      I1 => \^rdaaxi_araddr\(8),
      I2 => \^rdaaxi_araddr\(6),
      I3 => \^rdaaxi_araddr\(5),
      I4 => \^rdaaxi_araddr\(7),
      O => \p_0_in__0__0\(3)
    );
\addrIgr[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \row_lcl[10]_i_4_n_0\,
      I1 => \^rdaaxi_araddr\(9),
      I2 => \^rdaaxi_araddr\(7),
      I3 => \^rdaaxi_araddr\(5),
      I4 => \^rdaaxi_araddr\(6),
      I5 => \^rdaaxi_araddr\(8),
      O => \p_0_in__0__0\(4)
    );
\addrIgr[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FEFFFEFF0000"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(1),
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => \^stateswap_reg[3]_0\(0),
      I4 => \^rdaaxi_araddr\(10),
      I5 => \addrIgr[5]_i_2_n_0\,
      O => \p_0_in__0__0\(5)
    );
\addrIgr[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^rdaaxi_araddr\(8),
      I1 => \^rdaaxi_araddr\(6),
      I2 => \^rdaaxi_araddr\(5),
      I3 => \^rdaaxi_araddr\(7),
      I4 => \^rdaaxi_araddr\(9),
      O => \addrIgr[5]_i_2_n_0\
    );
\addrIgr[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FEFFFEFF0000"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(1),
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => \^stateswap_reg[3]_0\(0),
      I4 => \^rdaaxi_araddr\(11),
      I5 => \addrIgr[8]_i_2_n_0\,
      O => \p_0_in__0__0\(6)
    );
\addrIgr[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2888"
    )
        port map (
      I0 => \row_lcl[10]_i_4_n_0\,
      I1 => \^rdaaxi_araddr\(12),
      I2 => \addrIgr[8]_i_2_n_0\,
      I3 => \^rdaaxi_araddr\(11),
      O => \p_0_in__0__0\(7)
    );
\addrIgr[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F80FFFF7F800000"
    )
        port map (
      I0 => \^rdaaxi_araddr\(12),
      I1 => \addrIgr[8]_i_2_n_0\,
      I2 => \^rdaaxi_araddr\(11),
      I3 => \^rdaaxi_araddr\(13),
      I4 => \row_lcl[10]_i_4_n_0\,
      I5 => data(8),
      O => \p_0_in__0__0\(8)
    );
\addrIgr[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^rdaaxi_araddr\(9),
      I1 => \^rdaaxi_araddr\(7),
      I2 => \^rdaaxi_araddr\(5),
      I3 => \^rdaaxi_araddr\(6),
      I4 => \^rdaaxi_araddr\(8),
      I5 => \^rdaaxi_araddr\(10),
      O => \addrIgr[8]_i_2_n_0\
    );
\addrIgr[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6F60"
    )
        port map (
      I0 => \addrIgr[9]_i_2_n_0\,
      I1 => \^rdaaxi_araddr\(14),
      I2 => \row_lcl[10]_i_4_n_0\,
      I3 => data(9),
      O => \p_0_in__0__0\(9)
    );
\addrIgr[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^rdaaxi_araddr\(12),
      I1 => \addrIgr[8]_i_2_n_0\,
      I2 => \^rdaaxi_araddr\(11),
      I3 => \^rdaaxi_araddr\(13),
      O => \addrIgr[9]_i_2_n_0\
    );
\addrIgr_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(0),
      Q => \^rdaaxi_araddr\(5)
    );
\addrIgr_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(10),
      Q => \^rdaaxi_araddr\(15)
    );
\addrIgr_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(11),
      Q => \^rdaaxi_araddr\(16)
    );
\addrIgr_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(12),
      Q => \^rdaaxi_araddr\(17)
    );
\addrIgr_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(13),
      Q => \^rdaaxi_araddr\(18)
    );
\addrIgr_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(14),
      Q => \^rdaaxi_araddr\(19)
    );
\addrIgr_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(1),
      Q => \^rdaaxi_araddr\(6)
    );
\addrIgr_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(2),
      Q => \^rdaaxi_araddr\(7)
    );
\addrIgr_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(3),
      Q => \^rdaaxi_araddr\(8)
    );
\addrIgr_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(4),
      Q => \^rdaaxi_araddr\(9)
    );
\addrIgr_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(5),
      Q => \^rdaaxi_araddr\(10)
    );
\addrIgr_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(6),
      Q => \^rdaaxi_araddr\(11)
    );
\addrIgr_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(7),
      Q => \^rdaaxi_araddr\(12)
    );
\addrIgr_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(8),
      Q => \^rdaaxi_araddr\(13)
    );
\addrIgr_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => addrIgr,
      CLR => AR(0),
      D => \p_0_in__0__0\(9),
      Q => \^rdaaxi_araddr\(14)
    );
awdone_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(2),
      I1 => \^stateswap_reg[3]_0\(1),
      I2 => \^stateswap_reg[3]_0\(3),
      I3 => \^stateswap_reg[3]_0\(0),
      O => wrAAXI_awvalid
    );
\burstIgrstr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => \burstIgrstr_reg_n_0_[0]\,
      O => burstIgrstr(0)
    );
\burstIgrstr[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0EE0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => \burstIgrstr_reg_n_0_[1]\,
      I3 => \burstIgrstr_reg_n_0_[0]\,
      O => burstIgrstr(1)
    );
\burstIgrstr[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0EE0E0E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => \burstIgrstr_reg_n_0_[2]\,
      I3 => \burstIgrstr_reg_n_0_[0]\,
      I4 => \burstIgrstr_reg_n_0_[1]\,
      O => burstIgrstr(2)
    );
\burstIgrstr[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0EE0E0E0E0E0E0E0"
    )
        port map (
      I0 => stateIgrstr(1),
      I1 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I2 => \burstIgrstr_reg_n_0_[3]\,
      I3 => \burstIgrstr_reg_n_0_[2]\,
      I4 => \burstIgrstr_reg_n_0_[1]\,
      I5 => \burstIgrstr_reg_n_0_[0]\,
      O => burstIgrstr(3)
    );
\burstIgrstr[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"800080008000FFFF"
    )
        port map (
      I0 => hdrmemAXI_rlast,
      I1 => \burstIgrstr_reg[0]_0\,
      I2 => \FSM_sequential_stateIgrstr[0]_i_2_n_0\,
      I3 => \FSM_sequential_stateIgrstr[0]_i_4_n_0\,
      I4 => stateIgrstr(1),
      I5 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      O => \burstIgrstr[4]_i_1_n_0\
    );
\burstIgrstr[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \burstIgrstr[4]_i_3_n_0\,
      I1 => \burstIgrstr_reg_n_0_[4]\,
      I2 => \burstIgrstr_reg_n_0_[1]\,
      I3 => \burstIgrstr_reg_n_0_[0]\,
      I4 => \burstIgrstr_reg_n_0_[3]\,
      I5 => \burstIgrstr_reg_n_0_[2]\,
      O => burstIgrstr(4)
    );
\burstIgrstr[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I1 => stateIgrstr(1),
      O => \burstIgrstr[4]_i_3_n_0\
    );
\burstIgrstr_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstIgrstr[4]_i_1_n_0\,
      CLR => AR(0),
      D => burstIgrstr(0),
      Q => \burstIgrstr_reg_n_0_[0]\
    );
\burstIgrstr_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstIgrstr[4]_i_1_n_0\,
      CLR => AR(0),
      D => burstIgrstr(1),
      Q => \burstIgrstr_reg_n_0_[1]\
    );
\burstIgrstr_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstIgrstr[4]_i_1_n_0\,
      CLR => AR(0),
      D => burstIgrstr(2),
      Q => \burstIgrstr_reg_n_0_[2]\
    );
\burstIgrstr_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstIgrstr[4]_i_1_n_0\,
      CLR => AR(0),
      D => burstIgrstr(3),
      Q => \burstIgrstr_reg_n_0_[3]\
    );
\burstIgrstr_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstIgrstr[4]_i_1_n_0\,
      CLR => AR(0),
      D => burstIgrstr(4),
      Q => \burstIgrstr_reg_n_0_[4]\
    );
\burstSwapLast_reg[1]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => '1',
      G => AR(0),
      GE => '1',
      Q => burstSwapLast(1)
    );
\burstSwap[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000032000000"
    )
        port map (
      I0 => \burstSwap[0]_i_2_n_0\,
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^stateswap_reg[3]_0\(1),
      I3 => \^stateswap_reg[3]_0\(2),
      I4 => \^stateswap_reg[3]_0\(0),
      I5 => \^rdaaxi_araddr\(0),
      O => \burstSwap[0]_i_1_n_0\
    );
\burstSwap[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => burstSwapLast(1),
      I1 => \^rdaaxi_araddr\(1),
      I2 => \^rdaaxi_araddr\(4),
      I3 => \^rdaaxi_araddr\(3),
      I4 => \^rdaaxi_araddr\(2),
      O => \burstSwap[0]_i_2_n_0\
    );
\burstSwap[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \burstSwap[4]_i_5_n_0\,
      I1 => \^rdaaxi_araddr\(1),
      I2 => \^rdaaxi_araddr\(0),
      O => \burstSwap[1]_i_1_n_0\
    );
\burstSwap[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2888"
    )
        port map (
      I0 => \burstSwap[4]_i_5_n_0\,
      I1 => \^rdaaxi_araddr\(2),
      I2 => \^rdaaxi_araddr\(0),
      I3 => \^rdaaxi_araddr\(1),
      O => \burstSwap[2]_i_1_n_0\
    );
\burstSwap[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \burstSwap[4]_i_5_n_0\,
      I1 => \^rdaaxi_araddr\(3),
      I2 => \^rdaaxi_araddr\(2),
      I3 => \^rdaaxi_araddr\(1),
      I4 => \^rdaaxi_araddr\(0),
      O => \burstSwap[3]_i_1_n_0\
    );
\burstSwap[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFAEAAAAABAAAAAA"
    )
        port map (
      I0 => \burstSwap[4]_i_3_n_0\,
      I1 => \^stateswap_reg[3]_0\(1),
      I2 => \^stateswap_reg[3]_0\(3),
      I3 => \burstSwap[4]_i_4_n_0\,
      I4 => \stateSwap[1]_i_3_n_0\,
      I5 => \stateSwap[3]_i_4_n_0\,
      O => \burstSwap[4]_i_1_n_0\
    );
\burstSwap[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \burstSwap[4]_i_5_n_0\,
      I1 => \^rdaaxi_araddr\(4),
      I2 => \^rdaaxi_araddr\(1),
      I3 => \^rdaaxi_araddr\(0),
      I4 => \^rdaaxi_araddr\(3),
      I5 => \^rdaaxi_araddr\(2),
      O => \burstSwap[4]_i_2_n_0\
    );
\burstSwap[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I1 => stateIgrstr(1),
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => \^stateswap_reg[3]_0\(0),
      I4 => \^stateswap_reg[3]_0\(1),
      I5 => \burstSwap[4]_i_6_n_0\,
      O => \burstSwap[4]_i_3_n_0\
    );
\burstSwap[4]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      O => \burstSwap[4]_i_4_n_0\
    );
\burstSwap[4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00880080"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(2),
      I1 => \^stateswap_reg[3]_0\(0),
      I2 => \^stateswap_reg[3]_0\(1),
      I3 => \^stateswap_reg[3]_0\(3),
      I4 => \stateSwap[3]_i_4_n_0\,
      O => \burstSwap[4]_i_5_n_0\
    );
\burstSwap[4]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(3),
      I1 => rng_memclk,
      O => \burstSwap[4]_i_6_n_0\
    );
\burstSwap_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstSwap[4]_i_1_n_0\,
      CLR => AR(0),
      D => \burstSwap[0]_i_1_n_0\,
      Q => \^rdaaxi_araddr\(0)
    );
\burstSwap_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstSwap[4]_i_1_n_0\,
      CLR => AR(0),
      D => \burstSwap[1]_i_1_n_0\,
      Q => \^rdaaxi_araddr\(1)
    );
\burstSwap_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstSwap[4]_i_1_n_0\,
      CLR => AR(0),
      D => \burstSwap[2]_i_1_n_0\,
      Q => \^rdaaxi_araddr\(2)
    );
\burstSwap_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstSwap[4]_i_1_n_0\,
      CLR => AR(0),
      D => \burstSwap[3]_i_1_n_0\,
      Q => \^rdaaxi_araddr\(3)
    );
\burstSwap_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstSwap[4]_i_1_n_0\,
      CLR => AR(0),
      D => \burstSwap[4]_i_2_n_0\,
      Q => \^rdaaxi_araddr\(4)
    );
\capt[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I1 => stateIgrstr(1),
      I2 => ddrAXI_rready_0,
      I3 => \capt_reg[5]\,
      O => D(0)
    );
\col_lcl[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^rng_reg_0\,
      I3 => col_lcl(0),
      O => \col_lcl[0]_i_1__0_n_0\
    );
\col_lcl[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CBFF"
    )
        port map (
      I0 => rgbFromVideoinAXIS_tvalidm2,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \col_lcl[10]_i_1_n_0\
    );
\col_lcl[10]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^rng_reg_0\,
      I3 => \col_lcl[10]_i_3__0_n_0\,
      O => \col_lcl[10]_i_2__0_n_0\
    );
\col_lcl[10]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555555"
    )
        port map (
      I0 => col_lcl(10),
      I1 => col_lcl(8),
      I2 => col_lcl(6),
      I3 => \col_lcl[9]_i_2_n_0\,
      I4 => col_lcl(7),
      I5 => col_lcl(9),
      O => \col_lcl[10]_i_3__0_n_0\
    );
\col_lcl[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00404000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^rng_reg_0\,
      I3 => col_lcl(1),
      I4 => col_lcl(0),
      O => \col_lcl[1]_i_1__0_n_0\
    );
\col_lcl[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040404040000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^rng_reg_0\,
      I3 => col_lcl(0),
      I4 => col_lcl(1),
      I5 => col_lcl(2),
      O => \col_lcl[2]_i_1__0_n_0\
    );
\col_lcl[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F800000"
    )
        port map (
      I0 => col_lcl(2),
      I1 => col_lcl(1),
      I2 => col_lcl(0),
      I3 => col_lcl(3),
      I4 => \col_lcl[9]_i_3_n_0\,
      O => \col_lcl[3]_i_1__0_n_0\
    );
\col_lcl[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF800000000000"
    )
        port map (
      I0 => col_lcl(3),
      I1 => col_lcl(0),
      I2 => col_lcl(1),
      I3 => col_lcl(2),
      I4 => col_lcl(4),
      I5 => \col_lcl[9]_i_3_n_0\,
      O => \col_lcl[4]_i_1__0_n_0\
    );
\col_lcl[5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => \col_lcl[5]_i_2_n_0\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^rng_reg_0\,
      O => \col_lcl[5]_i_1__0_n_0\
    );
\col_lcl[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => col_lcl(5),
      I1 => col_lcl(3),
      I2 => col_lcl(0),
      I3 => col_lcl(1),
      I4 => col_lcl(2),
      I5 => col_lcl(4),
      O => \col_lcl[5]_i_2_n_0\
    );
\col_lcl[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"06000000"
    )
        port map (
      I0 => \col_lcl[9]_i_2_n_0\,
      I1 => col_lcl(6),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^rng_reg_0\,
      O => \col_lcl[6]_i_1__0_n_0\
    );
\col_lcl[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0078000000000000"
    )
        port map (
      I0 => col_lcl(6),
      I1 => \col_lcl[9]_i_2_n_0\,
      I2 => col_lcl(7),
      I3 => \^q\(0),
      I4 => \^q\(1),
      I5 => \^rng_reg_0\,
      O => \col_lcl[7]_i_1__0_n_0\
    );
\col_lcl[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F800000"
    )
        port map (
      I0 => col_lcl(7),
      I1 => \col_lcl[9]_i_2_n_0\,
      I2 => col_lcl(6),
      I3 => col_lcl(8),
      I4 => \col_lcl[9]_i_3_n_0\,
      O => \col_lcl[8]_i_1_n_0\
    );
\col_lcl[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF800000000000"
    )
        port map (
      I0 => col_lcl(8),
      I1 => col_lcl(6),
      I2 => \col_lcl[9]_i_2_n_0\,
      I3 => col_lcl(7),
      I4 => col_lcl(9),
      I5 => \col_lcl[9]_i_3_n_0\,
      O => \col_lcl[9]_i_1_n_0\
    );
\col_lcl[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => col_lcl(5),
      I1 => col_lcl(3),
      I2 => col_lcl(0),
      I3 => col_lcl(1),
      I4 => col_lcl(2),
      I5 => col_lcl(4),
      O => \col_lcl[9]_i_2_n_0\
    );
\col_lcl[9]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \col_lcl[9]_i_3_n_0\
    );
\col_lcl_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \col_lcl[0]_i_1__0_n_0\,
      Q => col_lcl(0)
    );
\col_lcl_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \col_lcl[10]_i_2__0_n_0\,
      Q => col_lcl(10)
    );
\col_lcl_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \col_lcl[1]_i_1__0_n_0\,
      Q => col_lcl(1)
    );
\col_lcl_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \col_lcl[2]_i_1__0_n_0\,
      Q => col_lcl(2)
    );
\col_lcl_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \col_lcl[3]_i_1__0_n_0\,
      Q => col_lcl(3)
    );
\col_lcl_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \col_lcl[4]_i_1__0_n_0\,
      Q => col_lcl(4)
    );
\col_lcl_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \col_lcl[5]_i_1__0_n_0\,
      Q => col_lcl(5)
    );
\col_lcl_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \col_lcl[6]_i_1__0_n_0\,
      Q => col_lcl(6)
    );
\col_lcl_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \col_lcl[7]_i_1__0_n_0\,
      Q => col_lcl(7)
    );
\col_lcl_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \col_lcl[8]_i_1_n_0\,
      Q => col_lcl(8)
    );
\col_lcl_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \col_lcl[9]_i_1_n_0\,
      Q => col_lcl(9)
    );
ddrAXI_arvalid_INST_0: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(0),
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^stateswap_reg[3]_0\(1),
      I3 => \^stateswap_reg[3]_0\(2),
      I4 => ddrAXI_arvalid_0(0),
      I5 => ddrAXI_arvalid_0(1),
      O => ddrAXI_arvalid
    );
\ddrAXI_awaddr[10]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^rdaaxi_araddr\(2),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(2)
    );
\ddrAXI_awaddr[11]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^rdaaxi_araddr\(3),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(3)
    );
\ddrAXI_awaddr[12]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^rdaaxi_araddr\(4),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(4)
    );
\ddrAXI_awaddr[13]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(5),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(5)
    );
\ddrAXI_awaddr[14]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(6),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(6)
    );
\ddrAXI_awaddr[15]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(7),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(7)
    );
\ddrAXI_awaddr[16]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(8),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(8)
    );
\ddrAXI_awaddr[17]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(9),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(9)
    );
\ddrAXI_awaddr[18]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(10),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(10)
    );
\ddrAXI_awaddr[19]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(11),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(11)
    );
\ddrAXI_awaddr[20]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(12),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(12)
    );
\ddrAXI_awaddr[21]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(13),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(13)
    );
\ddrAXI_awaddr[22]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(14),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(14)
    );
\ddrAXI_awaddr[23]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(15),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(15)
    );
\ddrAXI_awaddr[24]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(16),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(16)
    );
\ddrAXI_awaddr[25]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(17),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(17)
    );
\ddrAXI_awaddr[26]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(18),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(18)
    );
\ddrAXI_awaddr[27]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_awaddr(19),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(19)
    );
\ddrAXI_awaddr[8]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^rdaaxi_araddr\(0),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(0)
    );
\ddrAXI_awaddr[9]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^rdaaxi_araddr\(1),
      I1 => \ddrAXI_awaddr[27]\,
      O => ddrAXI_awaddr(1)
    );
ddrAXI_awvalid_INST_0: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(0),
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^stateswap_reg[3]_0\(1),
      I3 => \^stateswap_reg[3]_0\(2),
      I4 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_awvalid
    );
ddrAXI_rready_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      I1 => stateIgrstr(1),
      I2 => ddrAXI_rready_0,
      O => ddrAXI_rready
    );
\ddrAXI_wdata[0]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(0),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(0)
    );
\ddrAXI_wdata[100]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(100),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(100)
    );
\ddrAXI_wdata[101]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(101),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(101)
    );
\ddrAXI_wdata[102]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(102),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(102)
    );
\ddrAXI_wdata[103]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(103),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(103)
    );
\ddrAXI_wdata[104]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(104),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(104)
    );
\ddrAXI_wdata[105]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(105),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(105)
    );
\ddrAXI_wdata[106]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(106),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(106)
    );
\ddrAXI_wdata[107]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(107),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(107)
    );
\ddrAXI_wdata[108]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(108),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(108)
    );
\ddrAXI_wdata[109]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(109),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(109)
    );
\ddrAXI_wdata[10]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(10),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(10)
    );
\ddrAXI_wdata[110]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(110),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(110)
    );
\ddrAXI_wdata[111]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(111),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(111)
    );
\ddrAXI_wdata[112]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(112),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(112)
    );
\ddrAXI_wdata[113]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(113),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(113)
    );
\ddrAXI_wdata[114]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(114),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(114)
    );
\ddrAXI_wdata[115]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(115),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(115)
    );
\ddrAXI_wdata[116]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(116),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(116)
    );
\ddrAXI_wdata[117]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(117),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(117)
    );
\ddrAXI_wdata[118]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(118),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(118)
    );
\ddrAXI_wdata[119]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(119),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(119)
    );
\ddrAXI_wdata[11]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(11),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(11)
    );
\ddrAXI_wdata[120]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(120),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(120)
    );
\ddrAXI_wdata[121]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(121),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(121)
    );
\ddrAXI_wdata[122]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(122),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(122)
    );
\ddrAXI_wdata[123]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(123),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(123)
    );
\ddrAXI_wdata[124]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(124),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(124)
    );
\ddrAXI_wdata[125]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(125),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(125)
    );
\ddrAXI_wdata[126]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(126),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(126)
    );
\ddrAXI_wdata[127]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(127),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(127)
    );
\ddrAXI_wdata[12]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(12),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(12)
    );
\ddrAXI_wdata[13]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(13),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(13)
    );
\ddrAXI_wdata[14]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(14),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(14)
    );
\ddrAXI_wdata[15]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(15),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(15)
    );
\ddrAXI_wdata[16]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(16),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(16)
    );
\ddrAXI_wdata[17]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(17),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(17)
    );
\ddrAXI_wdata[18]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(18),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(18)
    );
\ddrAXI_wdata[19]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(19),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(19)
    );
\ddrAXI_wdata[1]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(1),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(1)
    );
\ddrAXI_wdata[20]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(20),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(20)
    );
\ddrAXI_wdata[21]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(21),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(21)
    );
\ddrAXI_wdata[22]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(22),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(22)
    );
\ddrAXI_wdata[23]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(23),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(23)
    );
\ddrAXI_wdata[24]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(24),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(24)
    );
\ddrAXI_wdata[25]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(25),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(25)
    );
\ddrAXI_wdata[26]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(26),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(26)
    );
\ddrAXI_wdata[27]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(27),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(27)
    );
\ddrAXI_wdata[28]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(28),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(28)
    );
\ddrAXI_wdata[29]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(29),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(29)
    );
\ddrAXI_wdata[2]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(2),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(2)
    );
\ddrAXI_wdata[30]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(30),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(30)
    );
\ddrAXI_wdata[31]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(31),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(31)
    );
\ddrAXI_wdata[32]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(32),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(32)
    );
\ddrAXI_wdata[33]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(33),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(33)
    );
\ddrAXI_wdata[34]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(34),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(34)
    );
\ddrAXI_wdata[35]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(35),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(35)
    );
\ddrAXI_wdata[36]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(36),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(36)
    );
\ddrAXI_wdata[37]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(37),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(37)
    );
\ddrAXI_wdata[38]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(38),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(38)
    );
\ddrAXI_wdata[39]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(39),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(39)
    );
\ddrAXI_wdata[3]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(3),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(3)
    );
\ddrAXI_wdata[40]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(40),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(40)
    );
\ddrAXI_wdata[41]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(41),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(41)
    );
\ddrAXI_wdata[42]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(42),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(42)
    );
\ddrAXI_wdata[43]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(43),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(43)
    );
\ddrAXI_wdata[44]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(44),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(44)
    );
\ddrAXI_wdata[45]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(45),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(45)
    );
\ddrAXI_wdata[46]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(46),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(46)
    );
\ddrAXI_wdata[47]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(47),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(47)
    );
\ddrAXI_wdata[48]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(48),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(48)
    );
\ddrAXI_wdata[49]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(49),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(49)
    );
\ddrAXI_wdata[4]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(4),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(4)
    );
\ddrAXI_wdata[50]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(50),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(50)
    );
\ddrAXI_wdata[51]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(51),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(51)
    );
\ddrAXI_wdata[52]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(52),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(52)
    );
\ddrAXI_wdata[53]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(53),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(53)
    );
\ddrAXI_wdata[54]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(54),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(54)
    );
\ddrAXI_wdata[55]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(55),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(55)
    );
\ddrAXI_wdata[56]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(56),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(56)
    );
\ddrAXI_wdata[57]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(57),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(57)
    );
\ddrAXI_wdata[58]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(58),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(58)
    );
\ddrAXI_wdata[59]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(59),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(59)
    );
\ddrAXI_wdata[5]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(5),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(5)
    );
\ddrAXI_wdata[60]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(60),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(60)
    );
\ddrAXI_wdata[61]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(61),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(61)
    );
\ddrAXI_wdata[62]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(62),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(62)
    );
\ddrAXI_wdata[63]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(63),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(63)
    );
\ddrAXI_wdata[64]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(64),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(64)
    );
\ddrAXI_wdata[65]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(65),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(65)
    );
\ddrAXI_wdata[66]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(66),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(66)
    );
\ddrAXI_wdata[67]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(67),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(67)
    );
\ddrAXI_wdata[68]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(68),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(68)
    );
\ddrAXI_wdata[69]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(69),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(69)
    );
\ddrAXI_wdata[6]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(6),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(6)
    );
\ddrAXI_wdata[70]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(70),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(70)
    );
\ddrAXI_wdata[71]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(71),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(71)
    );
\ddrAXI_wdata[72]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(72),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(72)
    );
\ddrAXI_wdata[73]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(73),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(73)
    );
\ddrAXI_wdata[74]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(74),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(74)
    );
\ddrAXI_wdata[75]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(75),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(75)
    );
\ddrAXI_wdata[76]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(76),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(76)
    );
\ddrAXI_wdata[77]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(77),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(77)
    );
\ddrAXI_wdata[78]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(78),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(78)
    );
\ddrAXI_wdata[79]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(79),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(79)
    );
\ddrAXI_wdata[7]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(7),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(7)
    );
\ddrAXI_wdata[80]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(80),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(80)
    );
\ddrAXI_wdata[81]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(81),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(81)
    );
\ddrAXI_wdata[82]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(82),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(82)
    );
\ddrAXI_wdata[83]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(83),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(83)
    );
\ddrAXI_wdata[84]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(84),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(84)
    );
\ddrAXI_wdata[85]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(85),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(85)
    );
\ddrAXI_wdata[86]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(86),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(86)
    );
\ddrAXI_wdata[87]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(87),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(87)
    );
\ddrAXI_wdata[88]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(88),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(88)
    );
\ddrAXI_wdata[89]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(89),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(89)
    );
\ddrAXI_wdata[8]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(8),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(8)
    );
\ddrAXI_wdata[90]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(90),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(90)
    );
\ddrAXI_wdata[91]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(91),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(91)
    );
\ddrAXI_wdata[92]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(92),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(92)
    );
\ddrAXI_wdata[93]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(93),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(93)
    );
\ddrAXI_wdata[94]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(94),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(94)
    );
\ddrAXI_wdata[95]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(95),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(95)
    );
\ddrAXI_wdata[96]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(96),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(96)
    );
\ddrAXI_wdata[97]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(97),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(97)
    );
\ddrAXI_wdata[98]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(98),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(98)
    );
\ddrAXI_wdata[99]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(99),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(99)
    );
\ddrAXI_wdata[9]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => wrAAXI_wdata(9),
      I1 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wdata(9)
    );
ddrAXI_wlast_INST_0_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF001800FF00FF00"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I3 => \^egraxis_tlast\,
      I4 => ddrAXI_wlast_INST_0_i_2_n_0,
      I5 => \^stateswap_reg[3]_0\(2),
      O => wrAAXI_wlast
    );
ddrAXI_wlast_INST_0_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(1),
      I1 => \^stateswap_reg[3]_0\(3),
      O => ddrAXI_wlast_INST_0_i_2_n_0
    );
ddrAXI_wvalid_INST_0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I3 => ddrAXI_wdata_0_sn_1,
      O => ddrAXI_wvalid
    );
\dwrRowbuf[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03F35555"
    )
        port map (
      I0 => \dwrRowbuf[12]_i_4_n_0\,
      I1 => \dwrRowbuf[14]_i_5_n_0\,
      I2 => \dwrRowbuf[2]_i_2_n_0\,
      I3 => \dwrRowbuf[10]_i_4_n_0\,
      I4 => \dwrRowbuf[1]_i_2_n_0\,
      O => \dwrRowbuf[10]_i_2_n_0\
    );
\dwrRowbuf[10]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[14]_i_7_n_0\,
      I1 => \dwrRowbuf[14]_i_8_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[2]\,
      O => \dwrRowbuf[10]_i_4_n_0\
    );
\dwrRowbuf[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"470047FF"
    )
        port map (
      I0 => \dwrRowbuf[11]_i_4_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \dwrRowbuf[14]_i_6_n_0\,
      I3 => \dwrRowbuf[1]_i_2_n_0\,
      I4 => \dwrRowbuf[13]_i_4_n_0\,
      O => \dwrRowbuf[11]_i_2_n_0\
    );
\dwrRowbuf[11]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[14]_i_7_n_0\,
      I1 => \dwrRowbuf[14]_i_8_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[3]\,
      O => \dwrRowbuf[11]_i_4_n_0\
    );
\dwrRowbuf[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EE0EEE0E0000EE0E"
    )
        port map (
      I0 => \dwrRowbuf[2]_i_2_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[8]\,
      I2 => \dwrRowbuf[12]_i_4_n_0\,
      I3 => \dwrRowbuf[28]_i_5_n_0\,
      I4 => \dwrRowbuf[14]_i_5_n_0\,
      I5 => \dwrRowbuf[1]_i_2_n_0\,
      O => \dwrRowbuf[12]_i_2_n_0\
    );
\dwrRowbuf[12]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[14]_i_7_n_0\,
      I1 => \dwrRowbuf[14]_i_8_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[4]\,
      O => \dwrRowbuf[12]_i_4_n_0\
    );
\dwrRowbuf[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505FCFCF505FC0C0"
    )
        port map (
      I0 => \dwrRowbuf[13]_i_4_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[9]\,
      I2 => \dwrRowbuf[1]_i_2_n_0\,
      I3 => \dwrRowbuf[14]_i_6_n_0\,
      I4 => \dwrRowbuf[2]_i_2_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[11]\,
      O => \dwrRowbuf[13]_i_2_n_0\
    );
\dwrRowbuf[13]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[14]_i_7_n_0\,
      I1 => \dwrRowbuf[14]_i_8_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[5]\,
      O => \dwrRowbuf[13]_i_4_n_0\
    );
\dwrRowbuf[14]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"74FF7400"
    )
        port map (
      I0 => \dwrRowbuf[14]_i_5_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[10]\,
      I3 => \dwrRowbuf[1]_i_2_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[8]\,
      O => \dwrRowbuf[14]_i_2_n_0\
    );
\dwrRowbuf[14]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"74FF7400"
    )
        port map (
      I0 => \dwrRowbuf[14]_i_6_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[11]\,
      I3 => \dwrRowbuf[1]_i_2_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[9]\,
      O => \dwrRowbuf[14]_i_3_n_0\
    );
\dwrRowbuf[14]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[14]_i_7_n_0\,
      I1 => \dwrRowbuf[14]_i_8_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[6]\,
      O => \dwrRowbuf[14]_i_5_n_0\
    );
\dwrRowbuf[14]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[14]_i_7_n_0\,
      I1 => \dwrRowbuf[14]_i_8_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[7]\,
      O => \dwrRowbuf[14]_i_6_n_0\
    );
\dwrRowbuf[14]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \dwrRowbuf[2]_i_19_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[8]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[10]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[9]\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[11]\,
      O => \dwrRowbuf[14]_i_7_n_0\
    );
\dwrRowbuf[14]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \dwrRowbuf_reg[0]_1\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[9]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[11]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[8]\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[10]\,
      O => \dwrRowbuf[14]_i_8_n_0\
    );
\dwrRowbuf[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[8]\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[10]\,
      I2 => \dwrRowbuf[30]_i_3_n_0\,
      I3 => \dwrRowbuf[15]_i_3_n_0\,
      I4 => \dwrRowbuf[1]_i_2_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[9]\,
      O => \dwrRowbuf[15]_i_2_n_0\
    );
\dwrRowbuf[15]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => \dwrRowbuf[14]_i_6_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[11]\,
      O => \dwrRowbuf[15]_i_3_n_0\
    );
\dwrRowbuf[16]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \dwrRowbuf[16]_i_4_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \dwrRowbuf[20]_i_4_n_0\,
      I3 => \dwrRowbuf[1]_i_2_n_0\,
      I4 => \dwrRowbuf[18]_i_4_n_0\,
      O => \dwrRowbuf[16]_i_2_n_0\
    );
\dwrRowbuf[16]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[22]_i_7_n_0\,
      I1 => \dwrRowbuf[22]_i_8_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[12]\,
      O => \dwrRowbuf[16]_i_4_n_0\
    );
\dwrRowbuf[17]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \dwrRowbuf[17]_i_4_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \dwrRowbuf[21]_i_4_n_0\,
      I3 => \dwrRowbuf[1]_i_2_n_0\,
      I4 => \dwrRowbuf[19]_i_4_n_0\,
      O => \dwrRowbuf[17]_i_2_n_0\
    );
\dwrRowbuf[17]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0B"
    )
        port map (
      I0 => \dwrRowbuf[22]_i_8_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[13]\,
      I2 => \dwrRowbuf[22]_i_7_n_0\,
      O => \dwrRowbuf[17]_i_4_n_0\
    );
\dwrRowbuf[18]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DD0DDD0D0000DD0D"
    )
        port map (
      I0 => \dwrRowbuf[22]_i_5_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \dwrRowbuf[18]_i_4_n_0\,
      I3 => \dwrRowbuf[28]_i_5_n_0\,
      I4 => \dwrRowbuf[20]_i_4_n_0\,
      I5 => \dwrRowbuf[1]_i_2_n_0\,
      O => \dwrRowbuf[18]_i_2_n_0\
    );
\dwrRowbuf[18]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[22]_i_7_n_0\,
      I1 => \dwrRowbuf[22]_i_8_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[14]\,
      O => \dwrRowbuf[18]_i_4_n_0\
    );
\dwrRowbuf[19]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DD0DDD0D0000DD0D"
    )
        port map (
      I0 => \dwrRowbuf[22]_i_6_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \dwrRowbuf[19]_i_4_n_0\,
      I3 => \dwrRowbuf[28]_i_5_n_0\,
      I4 => \dwrRowbuf[21]_i_4_n_0\,
      I5 => \dwrRowbuf[1]_i_2_n_0\,
      O => \dwrRowbuf[19]_i_2_n_0\
    );
\dwrRowbuf[19]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[22]_i_7_n_0\,
      I1 => \dwrRowbuf[22]_i_8_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[15]\,
      O => \dwrRowbuf[19]_i_4_n_0\
    );
\dwrRowbuf[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \dwrRowbuf[2]_i_2_n_0\,
      I1 => \dwrRowbuf[1]_i_6_n_0\,
      O => \dwrRowbuf[1]_i_2_n_0\
    );
\dwrRowbuf[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFE200E2"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[10]\,
      I1 => data5,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[22]\,
      I3 => \dwrRowbuf[1]_i_7_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[34]\,
      I5 => \dwrRowbuf[30]_i_8_n_0\,
      O => \dwrRowbuf[1]_i_6_n_0\
    );
\dwrRowbuf[1]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => pvt2,
      I1 => pvt29_in,
      O => \dwrRowbuf[1]_i_7_n_0\
    );
\dwrRowbuf[20]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"303FAFAF303FA0A0"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[20]\,
      I1 => \dwrRowbuf[20]_i_4_n_0\,
      I2 => \dwrRowbuf[1]_i_2_n_0\,
      I3 => \dwrRowbuf[22]_i_5_n_0\,
      I4 => \dwrRowbuf[2]_i_2_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[22]\,
      O => \dwrRowbuf[20]_i_2_n_0\
    );
\dwrRowbuf[20]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[22]_i_7_n_0\,
      I1 => \dwrRowbuf[22]_i_8_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[16]\,
      O => \dwrRowbuf[20]_i_4_n_0\
    );
\dwrRowbuf[21]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2E002EFF"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[21]\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \dwrRowbuf[21]_i_4_n_0\,
      I3 => \dwrRowbuf[1]_i_2_n_0\,
      I4 => \dwrRowbuf[22]_i_6_n_0\,
      O => \dwrRowbuf[21]_i_2_n_0\
    );
\dwrRowbuf[21]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[22]_i_7_n_0\,
      I1 => \dwrRowbuf[22]_i_8_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[17]\,
      O => \dwrRowbuf[21]_i_4_n_0\
    );
\dwrRowbuf[22]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"74FF7400"
    )
        port map (
      I0 => \dwrRowbuf[22]_i_5_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[22]\,
      I3 => \dwrRowbuf[1]_i_2_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[20]\,
      O => \dwrRowbuf[22]_i_2_n_0\
    );
\dwrRowbuf[22]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"74FF7400"
    )
        port map (
      I0 => \dwrRowbuf[22]_i_6_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[23]\,
      I3 => \dwrRowbuf[1]_i_2_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[21]\,
      O => \dwrRowbuf[22]_i_3_n_0\
    );
\dwrRowbuf[22]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[22]_i_7_n_0\,
      I1 => \dwrRowbuf[22]_i_8_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[18]\,
      O => \dwrRowbuf[22]_i_5_n_0\
    );
\dwrRowbuf[22]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[22]_i_7_n_0\,
      I1 => \dwrRowbuf[22]_i_8_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[19]\,
      O => \dwrRowbuf[22]_i_6_n_0\
    );
\dwrRowbuf[22]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \dwrRowbuf[2]_i_19_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[20]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[22]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[21]\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[23]\,
      O => \dwrRowbuf[22]_i_7_n_0\
    );
\dwrRowbuf[22]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \dwrRowbuf_reg[0]_1\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[21]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[23]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[20]\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[22]\,
      O => \dwrRowbuf[22]_i_8_n_0\
    );
\dwrRowbuf[23]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[20]\,
      I1 => \dwrRowbuf[1]_i_2_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[22]\,
      I3 => \dwrRowbuf[30]_i_3_n_0\,
      I4 => \dwrRowbuf[22]_i_3_n_0\,
      O => \dwrRowbuf[23]_i_2_n_0\
    );
\dwrRowbuf[24]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \dwrRowbuf[24]_i_4_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \dwrRowbuf[28]_i_4_n_0\,
      I3 => \dwrRowbuf[1]_i_2_n_0\,
      I4 => \dwrRowbuf[24]_i_5_n_0\,
      O => \dwrRowbuf[24]_i_2_n_0\
    );
\dwrRowbuf[24]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[25]_i_5_n_0\,
      I1 => \dwrRowbuf[25]_i_6_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[24]\,
      O => \dwrRowbuf[24]_i_4_n_0\
    );
\dwrRowbuf[24]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[25]_i_5_n_0\,
      I1 => \dwrRowbuf[25]_i_6_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[26]\,
      O => \dwrRowbuf[24]_i_5_n_0\
    );
\dwrRowbuf[25]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"005F0011005F001F"
    )
        port map (
      I0 => \dwrRowbuf[1]_i_2_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[28]\,
      I2 => \dwrRowbuf[28]_i_5_n_0\,
      I3 => \dwrRowbuf[25]_i_5_n_0\,
      I4 => \dwrRowbuf[25]_i_6_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[26]\,
      O => \dwrRowbuf[25]_i_2_n_0\
    );
\dwrRowbuf[25]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \dwrRowbuf[25]_i_7_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \dwrRowbuf[29]_i_4_n_0\,
      I3 => \dwrRowbuf[1]_i_2_n_0\,
      I4 => \dwrRowbuf[27]_i_4_n_0\,
      O => \dwrRowbuf[25]_i_3_n_0\
    );
\dwrRowbuf[25]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \dwrRowbuf[2]_i_19_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[32]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[34]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[33]\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[35]\,
      O => \dwrRowbuf[25]_i_5_n_0\
    );
\dwrRowbuf[25]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \dwrRowbuf_reg[0]_1\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[33]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[35]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[32]\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[34]\,
      O => \dwrRowbuf[25]_i_6_n_0\
    );
\dwrRowbuf[25]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0B"
    )
        port map (
      I0 => \dwrRowbuf[25]_i_6_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[25]\,
      I2 => \dwrRowbuf[25]_i_5_n_0\,
      O => \dwrRowbuf[25]_i_7_n_0\
    );
\dwrRowbuf[26]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888BB8B"
    )
        port map (
      I0 => \dwrRowbuf[27]_i_2_n_0\,
      I1 => \dwrRowbuf[30]_i_3_n_0\,
      I2 => \dwrRowbuf[30]_i_6_n_0\,
      I3 => \dwrRowbuf[2]_i_2_n_0\,
      I4 => \dwrRowbuf[25]_i_2_n_0\,
      O => \dwrRowbuf[26]_i_2_n_0\
    );
\dwrRowbuf[27]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DD0DDD0D0000DD0D"
    )
        port map (
      I0 => \dwrRowbuf[30]_i_10_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \dwrRowbuf[27]_i_4_n_0\,
      I3 => \dwrRowbuf[28]_i_5_n_0\,
      I4 => \dwrRowbuf[29]_i_4_n_0\,
      I5 => \dwrRowbuf[1]_i_2_n_0\,
      O => \dwrRowbuf[27]_i_2_n_0\
    );
\dwrRowbuf[27]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[25]_i_5_n_0\,
      I1 => \dwrRowbuf[25]_i_6_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[27]\,
      O => \dwrRowbuf[27]_i_4_n_0\
    );
\dwrRowbuf[28]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EE0EEE0E0000EE0E"
    )
        port map (
      I0 => \dwrRowbuf[2]_i_2_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[32]\,
      I2 => \dwrRowbuf[28]_i_4_n_0\,
      I3 => \dwrRowbuf[28]_i_5_n_0\,
      I4 => \dwrRowbuf[30]_i_6_n_0\,
      I5 => \dwrRowbuf[1]_i_2_n_0\,
      O => \dwrRowbuf[28]_i_2_n_0\
    );
\dwrRowbuf[28]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[25]_i_5_n_0\,
      I1 => \dwrRowbuf[25]_i_6_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[28]\,
      O => \dwrRowbuf[28]_i_4_n_0\
    );
\dwrRowbuf[28]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \dwrRowbuf[1]_i_6_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      O => \dwrRowbuf[28]_i_5_n_0\
    );
\dwrRowbuf[29]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505FCFCF505FC0C0"
    )
        port map (
      I0 => \dwrRowbuf[29]_i_4_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[33]\,
      I2 => \dwrRowbuf[1]_i_2_n_0\,
      I3 => \dwrRowbuf[30]_i_10_n_0\,
      I4 => \dwrRowbuf[2]_i_2_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[35]\,
      O => \dwrRowbuf[29]_i_2_n_0\
    );
\dwrRowbuf[29]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[25]_i_5_n_0\,
      I1 => \dwrRowbuf[25]_i_6_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[29]\,
      O => \dwrRowbuf[29]_i_4_n_0\
    );
\dwrRowbuf[2]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[33]\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[9]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[32]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[8]\,
      O => \dwrRowbuf[2]_i_10_n_0\
    );
\dwrRowbuf[2]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0051005100F100F7"
    )
        port map (
      I0 => \dwrRowbuf[30]_i_10_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[7]\,
      I2 => \dwrRowbuf[14]_i_8_n_0\,
      I3 => \dwrRowbuf[14]_i_7_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[6]\,
      I5 => \dwrRowbuf[30]_i_6_n_0\,
      O => \dwrRowbuf[2]_i_11_n_0\
    );
\dwrRowbuf[2]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0051005100F100F7"
    )
        port map (
      I0 => \dwrRowbuf[29]_i_4_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[5]\,
      I2 => \dwrRowbuf[14]_i_8_n_0\,
      I3 => \dwrRowbuf[14]_i_7_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[4]\,
      I5 => \dwrRowbuf[28]_i_4_n_0\,
      O => \dwrRowbuf[2]_i_12_n_0\
    );
\dwrRowbuf[2]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F3F2F200F2F0F200"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[27]\,
      I1 => \dwrRowbuf[25]_i_6_n_0\,
      I2 => \dwrRowbuf[25]_i_5_n_0\,
      I3 => \dwrRowbuf[11]_i_4_n_0\,
      I4 => \dwrRowbuf[10]_i_4_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[26]\,
      O => \dwrRowbuf[2]_i_13_n_0\
    );
\dwrRowbuf[2]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFAEAE00AEAAAE00"
    )
        port map (
      I0 => \dwrRowbuf[25]_i_5_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[25]\,
      I2 => \dwrRowbuf[25]_i_6_n_0\,
      I3 => \dwrRowbuf[9]_i_4_n_0\,
      I4 => \dwrRowbuf[8]_i_4_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[24]\,
      O => \dwrRowbuf[2]_i_14_n_0\
    );
\dwrRowbuf[2]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[11]\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[35]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[10]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[34]\,
      O => \dwrRowbuf[2]_i_15_n_0\
    );
\dwrRowbuf[2]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[9]\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[33]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[8]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[32]\,
      O => \dwrRowbuf[2]_i_16_n_0\
    );
\dwrRowbuf[2]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C000C0630363030"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[7]\,
      I1 => \dwrRowbuf[30]_i_10_n_0\,
      I2 => \dwrRowbuf[14]_i_7_n_0\,
      I3 => \dwrRowbuf[14]_i_8_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[6]\,
      I5 => \dwrRowbuf[30]_i_6_n_0\,
      O => \dwrRowbuf[2]_i_17_n_0\
    );
\dwrRowbuf[2]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C000C0630363030"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[5]\,
      I1 => \dwrRowbuf[29]_i_4_n_0\,
      I2 => \dwrRowbuf[14]_i_7_n_0\,
      I3 => \dwrRowbuf[14]_i_8_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[4]\,
      I5 => \dwrRowbuf[28]_i_4_n_0\,
      O => \dwrRowbuf[2]_i_18_n_0\
    );
\dwrRowbuf[2]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05A0050605A00560"
    )
        port map (
      I0 => \dwrRowbuf[11]_i_4_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[27]\,
      I2 => \dwrRowbuf[10]_i_4_n_0\,
      I3 => \dwrRowbuf[25]_i_5_n_0\,
      I4 => \dwrRowbuf[25]_i_6_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[26]\,
      O => \dwrRowbuf[2]_i_19_n_0\
    );
\dwrRowbuf[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"407F4040407F7F7F"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[35]\,
      I1 => pvt2,
      I2 => pvt29_in,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[23]\,
      I4 => data5,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[11]\,
      O => \dwrRowbuf[2]_i_2_n_0\
    );
\dwrRowbuf[2]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05A0050605A00560"
    )
        port map (
      I0 => \dwrRowbuf[9]_i_4_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[25]\,
      I2 => \dwrRowbuf[8]_i_4_n_0\,
      I3 => \dwrRowbuf[25]_i_5_n_0\,
      I4 => \dwrRowbuf[25]_i_6_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[24]\,
      O => \dwrRowbuf[2]_i_20_n_0\
    );
\dwrRowbuf[2]_i_21\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[35]\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[23]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[34]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[22]\,
      O => \dwrRowbuf[2]_i_21_n_0\
    );
\dwrRowbuf[2]_i_22\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[33]\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[21]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[32]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[20]\,
      O => \dwrRowbuf[2]_i_22_n_0\
    );
\dwrRowbuf[2]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0051005100F100F7"
    )
        port map (
      I0 => \dwrRowbuf[30]_i_10_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[19]\,
      I2 => \dwrRowbuf[22]_i_8_n_0\,
      I3 => \dwrRowbuf[22]_i_7_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[18]\,
      I5 => \dwrRowbuf[30]_i_6_n_0\,
      O => \dwrRowbuf[2]_i_23_n_0\
    );
\dwrRowbuf[2]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F3F2F200F2F0F200"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[29]\,
      I1 => \dwrRowbuf[25]_i_6_n_0\,
      I2 => \dwrRowbuf[25]_i_5_n_0\,
      I3 => \dwrRowbuf[21]_i_4_n_0\,
      I4 => \dwrRowbuf[20]_i_4_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[28]\,
      O => \dwrRowbuf[2]_i_24_n_0\
    );
\dwrRowbuf[2]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F3F2F200F2F0F200"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[27]\,
      I1 => \dwrRowbuf[25]_i_6_n_0\,
      I2 => \dwrRowbuf[25]_i_5_n_0\,
      I3 => \dwrRowbuf[19]_i_4_n_0\,
      I4 => \dwrRowbuf[18]_i_4_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[26]\,
      O => \dwrRowbuf[2]_i_25_n_0\
    );
\dwrRowbuf[2]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFAEAE00AEAAAE00"
    )
        port map (
      I0 => \dwrRowbuf[25]_i_5_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[25]\,
      I2 => \dwrRowbuf[25]_i_6_n_0\,
      I3 => \dwrRowbuf[17]_i_4_n_0\,
      I4 => \dwrRowbuf[16]_i_4_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[24]\,
      O => \dwrRowbuf[2]_i_26_n_0\
    );
\dwrRowbuf[2]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[23]\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[35]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[22]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[34]\,
      O => \dwrRowbuf[2]_i_27_n_0\
    );
\dwrRowbuf[2]_i_28\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[21]\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[33]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[20]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[32]\,
      O => \dwrRowbuf[2]_i_28_n_0\
    );
\dwrRowbuf[2]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C000C0630363030"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[19]\,
      I1 => \dwrRowbuf[30]_i_10_n_0\,
      I2 => \dwrRowbuf[22]_i_7_n_0\,
      I3 => \dwrRowbuf[22]_i_8_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[18]\,
      I5 => \dwrRowbuf[30]_i_6_n_0\,
      O => \dwrRowbuf[2]_i_29_n_0\
    );
\dwrRowbuf[2]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05A0050605A00560"
    )
        port map (
      I0 => \dwrRowbuf[21]_i_4_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[29]\,
      I2 => \dwrRowbuf[20]_i_4_n_0\,
      I3 => \dwrRowbuf[25]_i_5_n_0\,
      I4 => \dwrRowbuf[25]_i_6_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[28]\,
      O => \dwrRowbuf[2]_i_30_n_0\
    );
\dwrRowbuf[2]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05A0050605A00560"
    )
        port map (
      I0 => \dwrRowbuf[19]_i_4_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[27]\,
      I2 => \dwrRowbuf[18]_i_4_n_0\,
      I3 => \dwrRowbuf[25]_i_5_n_0\,
      I4 => \dwrRowbuf[25]_i_6_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[26]\,
      O => \dwrRowbuf[2]_i_31_n_0\
    );
\dwrRowbuf[2]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05A0050605A00560"
    )
        port map (
      I0 => \dwrRowbuf[17]_i_4_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[25]\,
      I2 => \dwrRowbuf[16]_i_4_n_0\,
      I3 => \dwrRowbuf[25]_i_5_n_0\,
      I4 => \dwrRowbuf[25]_i_6_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[24]\,
      O => \dwrRowbuf[2]_i_32_n_0\
    );
\dwrRowbuf[2]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[11]\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[23]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[22]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[10]\,
      O => \dwrRowbuf[2]_i_33_n_0\
    );
\dwrRowbuf[2]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[9]\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[21]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[20]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[8]\,
      O => \dwrRowbuf[2]_i_34_n_0\
    );
\dwrRowbuf[2]_i_35\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000D000D0C0D0D0F"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[7]\,
      I1 => \dwrRowbuf[14]_i_8_n_0\,
      I2 => \dwrRowbuf[14]_i_7_n_0\,
      I3 => \dwrRowbuf[22]_i_6_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[6]\,
      I5 => \dwrRowbuf[22]_i_5_n_0\,
      O => \dwrRowbuf[2]_i_35_n_0\
    );
\dwrRowbuf[2]_i_36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000D000D0C0D0D0F"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[5]\,
      I1 => \dwrRowbuf[14]_i_8_n_0\,
      I2 => \dwrRowbuf[14]_i_7_n_0\,
      I3 => \dwrRowbuf[21]_i_4_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[4]\,
      I5 => \dwrRowbuf[20]_i_4_n_0\,
      O => \dwrRowbuf[2]_i_36_n_0\
    );
\dwrRowbuf[2]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000D000D0C0D0D0F"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[3]\,
      I1 => \dwrRowbuf[14]_i_8_n_0\,
      I2 => \dwrRowbuf[14]_i_7_n_0\,
      I3 => \dwrRowbuf[19]_i_4_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[2]\,
      I5 => \dwrRowbuf[18]_i_4_n_0\,
      O => \dwrRowbuf[2]_i_37_n_0\
    );
\dwrRowbuf[2]_i_38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0051005150515155"
    )
        port map (
      I0 => \dwrRowbuf[14]_i_7_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[1]\,
      I2 => \dwrRowbuf[14]_i_8_n_0\,
      I3 => \dwrRowbuf[17]_i_4_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[0]\,
      I5 => \dwrRowbuf[16]_i_4_n_0\,
      O => \dwrRowbuf[2]_i_38_n_0\
    );
\dwrRowbuf[2]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[23]\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[11]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[22]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[10]\,
      O => \dwrRowbuf[2]_i_39_n_0\
    );
\dwrRowbuf[2]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[21]\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[9]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[20]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[8]\,
      O => \dwrRowbuf[2]_i_40_n_0\
    );
\dwrRowbuf[2]_i_41\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05A0050605A00560"
    )
        port map (
      I0 => \dwrRowbuf[22]_i_6_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[7]\,
      I2 => \dwrRowbuf[22]_i_5_n_0\,
      I3 => \dwrRowbuf[14]_i_7_n_0\,
      I4 => \dwrRowbuf[14]_i_8_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[6]\,
      O => \dwrRowbuf[2]_i_41_n_0\
    );
\dwrRowbuf[2]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05A0050605A00560"
    )
        port map (
      I0 => \dwrRowbuf[21]_i_4_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[5]\,
      I2 => \dwrRowbuf[20]_i_4_n_0\,
      I3 => \dwrRowbuf[14]_i_7_n_0\,
      I4 => \dwrRowbuf[14]_i_8_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[4]\,
      O => \dwrRowbuf[2]_i_42_n_0\
    );
\dwrRowbuf[2]_i_43\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05A0050605A00560"
    )
        port map (
      I0 => \dwrRowbuf[19]_i_4_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[3]\,
      I2 => \dwrRowbuf[18]_i_4_n_0\,
      I3 => \dwrRowbuf[14]_i_7_n_0\,
      I4 => \dwrRowbuf[14]_i_8_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[2]\,
      O => \dwrRowbuf[2]_i_43_n_0\
    );
\dwrRowbuf[2]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05A0050605A00560"
    )
        port map (
      I0 => \dwrRowbuf[17]_i_4_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[1]\,
      I2 => \dwrRowbuf[16]_i_4_n_0\,
      I3 => \dwrRowbuf[14]_i_7_n_0\,
      I4 => \dwrRowbuf[14]_i_8_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[0]\,
      O => \dwrRowbuf[2]_i_44_n_0\
    );
\dwrRowbuf[2]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[35]\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[11]\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[34]\,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[10]\,
      O => \dwrRowbuf[2]_i_9_n_0\
    );
\dwrRowbuf[30]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[25]_i_5_n_0\,
      I1 => \dwrRowbuf[25]_i_6_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[31]\,
      O => \dwrRowbuf[30]_i_10_n_0\
    );
\dwrRowbuf[30]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2EFF2E00"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[34]\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \dwrRowbuf[30]_i_6_n_0\,
      I3 => \dwrRowbuf[1]_i_2_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[32]\,
      O => \dwrRowbuf[30]_i_2_n_0\
    );
\dwrRowbuf[30]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA08"
    )
        port map (
      I0 => \dwrRowbuf[2]_i_2_n_0\,
      I1 => \dwrRowbuf[30]_i_7_n_0\,
      I2 => \dwrRowbuf[30]_i_8_n_0\,
      I3 => \dwrRowbuf[30]_i_9_n_0\,
      O => \dwrRowbuf[30]_i_3_n_0\
    );
\dwrRowbuf[30]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"74FF7400"
    )
        port map (
      I0 => \dwrRowbuf[30]_i_10_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[35]\,
      I3 => \dwrRowbuf[1]_i_2_n_0\,
      I4 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[33]\,
      O => \dwrRowbuf[30]_i_4_n_0\
    );
\dwrRowbuf[30]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[25]_i_5_n_0\,
      I1 => \dwrRowbuf[25]_i_6_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[30]\,
      O => \dwrRowbuf[30]_i_6_n_0\
    );
\dwrRowbuf[30]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BF80BFBFBF808080"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[32]\,
      I1 => pvt2,
      I2 => pvt29_in,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[20]\,
      I4 => data5,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[8]\,
      O => \dwrRowbuf[30]_i_7_n_0\
    );
\dwrRowbuf[30]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BF80BFBFBF808080"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[33]\,
      I1 => pvt2,
      I2 => pvt29_in,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[21]\,
      I4 => data5,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[9]\,
      O => \dwrRowbuf[30]_i_8_n_0\
    );
\dwrRowbuf[30]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BF80BFBFBF808080"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[34]\,
      I1 => pvt2,
      I2 => pvt29_in,
      I3 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[22]\,
      I4 => data5,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[10]\,
      O => \dwrRowbuf[30]_i_9_n_0\
    );
\dwrRowbuf[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0BFF"
    )
        port map (
      I0 => rgbFromVideoinAXIS_tvalidm2,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \dwrRowbuf[31]_i_1_n_0\
    );
\dwrRowbuf[31]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[32]\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[34]\,
      I2 => \dwrRowbuf[30]_i_3_n_0\,
      I3 => \dwrRowbuf[31]_i_5_n_0\,
      I4 => \dwrRowbuf[1]_i_2_n_0\,
      I5 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[33]\,
      O => \dwrRowbuf[31]_i_3_n_0\
    );
\dwrRowbuf[31]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => \dwrRowbuf[30]_i_10_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[35]\,
      O => \dwrRowbuf[31]_i_5_n_0\
    );
\dwrRowbuf[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"111F111F111FFFFF"
    )
        port map (
      I0 => \dwrRowbuf[12]_i_4_n_0\,
      I1 => \dwrRowbuf[2]_i_2_n_0\,
      I2 => \dwrRowbuf[1]_i_2_n_0\,
      I3 => \dwrRowbuf[10]_i_4_n_0\,
      I4 => \dwrRowbuf[8]_i_4_n_0\,
      I5 => \dwrRowbuf[28]_i_5_n_0\,
      O => \dwrRowbuf[8]_i_2_n_0\
    );
\dwrRowbuf[8]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => \dwrRowbuf[14]_i_7_n_0\,
      I1 => \dwrRowbuf[14]_i_8_n_0\,
      I2 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[0]\,
      O => \dwrRowbuf[8]_i_4_n_0\
    );
\dwrRowbuf[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"111F111F111FFFFF"
    )
        port map (
      I0 => \dwrRowbuf[9]_i_4_n_0\,
      I1 => \dwrRowbuf[28]_i_5_n_0\,
      I2 => \dwrRowbuf[1]_i_2_n_0\,
      I3 => \dwrRowbuf[11]_i_4_n_0\,
      I4 => \dwrRowbuf[13]_i_4_n_0\,
      I5 => \dwrRowbuf[2]_i_2_n_0\,
      O => \dwrRowbuf[9]_i_2_n_0\
    );
\dwrRowbuf[9]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0B"
    )
        port map (
      I0 => \dwrRowbuf[14]_i_8_n_0\,
      I1 => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[1]\,
      I2 => \dwrRowbuf[14]_i_7_n_0\,
      O => \dwrRowbuf[9]_i_4_n_0\
    );
\dwrRowbuf_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowAbuf_n_36,
      Q => dwrRowbuf(0)
    );
\dwrRowbuf_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_187,
      Q => dwrRowbuf(10)
    );
\dwrRowbuf_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_186,
      Q => dwrRowbuf(11)
    );
\dwrRowbuf_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_185,
      Q => dwrRowbuf(12)
    );
\dwrRowbuf_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_184,
      Q => dwrRowbuf(13)
    );
\dwrRowbuf_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_183,
      Q => dwrRowbuf(14)
    );
\dwrRowbuf_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_182,
      Q => dwrRowbuf(15)
    );
\dwrRowbuf_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_181,
      Q => dwrRowbuf(16)
    );
\dwrRowbuf_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_180,
      Q => dwrRowbuf(17)
    );
\dwrRowbuf_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_179,
      Q => dwrRowbuf(18)
    );
\dwrRowbuf_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_178,
      Q => dwrRowbuf(19)
    );
\dwrRowbuf_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowAbuf_n_35,
      Q => dwrRowbuf(1)
    );
\dwrRowbuf_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_177,
      Q => dwrRowbuf(20)
    );
\dwrRowbuf_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_176,
      Q => dwrRowbuf(21)
    );
\dwrRowbuf_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_175,
      Q => dwrRowbuf(22)
    );
\dwrRowbuf_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_174,
      Q => dwrRowbuf(23)
    );
\dwrRowbuf_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_173,
      Q => dwrRowbuf(24)
    );
\dwrRowbuf_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_172,
      Q => dwrRowbuf(25)
    );
\dwrRowbuf_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_171,
      Q => dwrRowbuf(26)
    );
\dwrRowbuf_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_170,
      Q => dwrRowbuf(27)
    );
\dwrRowbuf_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_169,
      Q => dwrRowbuf(28)
    );
\dwrRowbuf_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_168,
      Q => dwrRowbuf(29)
    );
\dwrRowbuf_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_190,
      Q => dwrRowbuf(2)
    );
\dwrRowbuf_reg[2]_i_6\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_dwrRowbuf_reg[2]_i_6_CO_UNCONNECTED\(7 downto 6),
      CO(5) => pvt2,
      CO(4) => \dwrRowbuf_reg[2]_i_6_n_3\,
      CO(3) => \dwrRowbuf_reg[2]_i_6_n_4\,
      CO(2) => \dwrRowbuf_reg[2]_i_6_n_5\,
      CO(1) => \dwrRowbuf_reg[2]_i_6_n_6\,
      CO(0) => \dwrRowbuf_reg[2]_i_6_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \dwrRowbuf[2]_i_9_n_0\,
      DI(4) => \dwrRowbuf[2]_i_10_n_0\,
      DI(3) => \dwrRowbuf[2]_i_11_n_0\,
      DI(2) => \dwrRowbuf[2]_i_12_n_0\,
      DI(1) => \dwrRowbuf[2]_i_13_n_0\,
      DI(0) => \dwrRowbuf[2]_i_14_n_0\,
      O(7 downto 0) => \NLW_dwrRowbuf_reg[2]_i_6_O_UNCONNECTED\(7 downto 0),
      S(7 downto 6) => B"00",
      S(5) => \dwrRowbuf[2]_i_15_n_0\,
      S(4) => \dwrRowbuf[2]_i_16_n_0\,
      S(3) => \dwrRowbuf[2]_i_17_n_0\,
      S(2) => \dwrRowbuf[2]_i_18_n_0\,
      S(1) => \dwrRowbuf[2]_i_19_n_0\,
      S(0) => \dwrRowbuf[2]_i_20_n_0\
    );
\dwrRowbuf_reg[2]_i_7\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_dwrRowbuf_reg[2]_i_7_CO_UNCONNECTED\(7 downto 6),
      CO(5) => pvt29_in,
      CO(4) => \dwrRowbuf_reg[2]_i_7_n_3\,
      CO(3) => \dwrRowbuf_reg[2]_i_7_n_4\,
      CO(2) => \dwrRowbuf_reg[2]_i_7_n_5\,
      CO(1) => \dwrRowbuf_reg[2]_i_7_n_6\,
      CO(0) => \dwrRowbuf_reg[2]_i_7_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \dwrRowbuf[2]_i_21_n_0\,
      DI(4) => \dwrRowbuf[2]_i_22_n_0\,
      DI(3) => \dwrRowbuf[2]_i_23_n_0\,
      DI(2) => \dwrRowbuf[2]_i_24_n_0\,
      DI(1) => \dwrRowbuf[2]_i_25_n_0\,
      DI(0) => \dwrRowbuf[2]_i_26_n_0\,
      O(7 downto 0) => \NLW_dwrRowbuf_reg[2]_i_7_O_UNCONNECTED\(7 downto 0),
      S(7 downto 6) => B"00",
      S(5) => \dwrRowbuf[2]_i_27_n_0\,
      S(4) => \dwrRowbuf[2]_i_28_n_0\,
      S(3) => \dwrRowbuf[2]_i_29_n_0\,
      S(2) => \dwrRowbuf[2]_i_30_n_0\,
      S(1) => \dwrRowbuf[2]_i_31_n_0\,
      S(0) => \dwrRowbuf[2]_i_32_n_0\
    );
\dwrRowbuf_reg[2]_i_8\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_dwrRowbuf_reg[2]_i_8_CO_UNCONNECTED\(7 downto 6),
      CO(5) => data5,
      CO(4) => \dwrRowbuf_reg[2]_i_8_n_3\,
      CO(3) => \dwrRowbuf_reg[2]_i_8_n_4\,
      CO(2) => \dwrRowbuf_reg[2]_i_8_n_5\,
      CO(1) => \dwrRowbuf_reg[2]_i_8_n_6\,
      CO(0) => \dwrRowbuf_reg[2]_i_8_n_7\,
      DI(7 downto 6) => B"00",
      DI(5) => \dwrRowbuf[2]_i_33_n_0\,
      DI(4) => \dwrRowbuf[2]_i_34_n_0\,
      DI(3) => \dwrRowbuf[2]_i_35_n_0\,
      DI(2) => \dwrRowbuf[2]_i_36_n_0\,
      DI(1) => \dwrRowbuf[2]_i_37_n_0\,
      DI(0) => \dwrRowbuf[2]_i_38_n_0\,
      O(7 downto 0) => \NLW_dwrRowbuf_reg[2]_i_8_O_UNCONNECTED\(7 downto 0),
      S(7 downto 6) => B"00",
      S(5) => \dwrRowbuf[2]_i_39_n_0\,
      S(4) => \dwrRowbuf[2]_i_40_n_0\,
      S(3) => \dwrRowbuf[2]_i_41_n_0\,
      S(2) => \dwrRowbuf[2]_i_42_n_0\,
      S(1) => \dwrRowbuf[2]_i_43_n_0\,
      S(0) => \dwrRowbuf[2]_i_44_n_0\
    );
\dwrRowbuf_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_167,
      Q => dwrRowbuf(30)
    );
\dwrRowbuf_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_166,
      Q => dwrRowbuf(31)
    );
\dwrRowbuf_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowAbuf_n_34,
      Q => dwrRowbuf(3)
    );
\dwrRowbuf_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowAbuf_n_33,
      Q => dwrRowbuf(4)
    );
\dwrRowbuf_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowAbuf_n_32,
      Q => dwrRowbuf(5)
    );
\dwrRowbuf_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowAbuf_n_31,
      Q => dwrRowbuf(6)
    );
\dwrRowbuf_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowAbuf_n_30,
      Q => dwrRowbuf(7)
    );
\dwrRowbuf_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_189,
      Q => dwrRowbuf(8)
    );
\dwrRowbuf_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => myRowBbuf_n_188,
      Q => dwrRowbuf(9)
    );
\egrAXIS_tdata[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(0),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(0),
      I4 => \egrfifo_reg[2]_41\(0),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(0)
    );
\egrAXIS_tdata[100]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(100),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(100),
      I4 => \egrfifo_reg[2]_41\(100),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(100)
    );
\egrAXIS_tdata[101]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(101),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(101),
      I4 => \egrfifo_reg[2]_41\(101),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(101)
    );
\egrAXIS_tdata[102]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(102),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(102),
      I4 => \egrfifo_reg[2]_41\(102),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(102)
    );
\egrAXIS_tdata[103]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(103),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(103),
      I4 => \egrfifo_reg[2]_41\(103),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(103)
    );
\egrAXIS_tdata[104]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(104),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(104),
      I4 => \egrfifo_reg[2]_41\(104),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(104)
    );
\egrAXIS_tdata[105]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(105),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(105),
      I4 => \egrfifo_reg[2]_41\(105),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(105)
    );
\egrAXIS_tdata[106]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(106),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(106),
      I4 => \egrfifo_reg[2]_41\(106),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(106)
    );
\egrAXIS_tdata[107]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(107),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(107),
      I4 => \egrfifo_reg[2]_41\(107),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(107)
    );
\egrAXIS_tdata[108]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(108),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(108),
      I4 => \egrfifo_reg[2]_41\(108),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(108)
    );
\egrAXIS_tdata[109]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(109),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(109),
      I4 => \egrfifo_reg[2]_41\(109),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(109)
    );
\egrAXIS_tdata[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(10),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(10),
      I4 => \egrfifo_reg[2]_41\(10),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(10)
    );
\egrAXIS_tdata[110]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(110),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(110),
      I4 => \egrfifo_reg[2]_41\(110),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(110)
    );
\egrAXIS_tdata[111]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(111),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(111),
      I4 => \egrfifo_reg[2]_41\(111),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(111)
    );
\egrAXIS_tdata[112]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(112),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(112),
      I4 => \egrfifo_reg[2]_41\(112),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(112)
    );
\egrAXIS_tdata[113]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(113),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(113),
      I4 => \egrfifo_reg[2]_41\(113),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(113)
    );
\egrAXIS_tdata[114]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(114),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(114),
      I4 => \egrfifo_reg[2]_41\(114),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(114)
    );
\egrAXIS_tdata[115]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(115),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(115),
      I4 => \egrfifo_reg[2]_41\(115),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(115)
    );
\egrAXIS_tdata[116]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(116),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(116),
      I4 => \egrfifo_reg[2]_41\(116),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(116)
    );
\egrAXIS_tdata[117]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(117),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(117),
      I4 => \egrfifo_reg[2]_41\(117),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(117)
    );
\egrAXIS_tdata[118]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(118),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(118),
      I4 => \egrfifo_reg[2]_41\(118),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(118)
    );
\egrAXIS_tdata[119]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(119),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(119),
      I4 => \egrfifo_reg[2]_41\(119),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(119)
    );
\egrAXIS_tdata[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(11),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(11),
      I4 => \egrfifo_reg[2]_41\(11),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(11)
    );
\egrAXIS_tdata[120]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(120),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(120),
      I4 => \egrfifo_reg[2]_41\(120),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(120)
    );
\egrAXIS_tdata[121]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(121),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(121),
      I4 => \egrfifo_reg[2]_41\(121),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(121)
    );
\egrAXIS_tdata[122]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(122),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(122),
      I4 => \egrfifo_reg[2]_41\(122),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(122)
    );
\egrAXIS_tdata[123]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(123),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(123),
      I4 => \egrfifo_reg[2]_41\(123),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(123)
    );
\egrAXIS_tdata[124]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(124),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(124),
      I4 => \egrfifo_reg[2]_41\(124),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(124)
    );
\egrAXIS_tdata[125]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(125),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(125),
      I4 => \egrfifo_reg[2]_41\(125),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(125)
    );
\egrAXIS_tdata[126]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(126),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(126),
      I4 => \egrfifo_reg[2]_41\(126),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(126)
    );
\egrAXIS_tdata[127]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ABABAAAB"
    )
        port map (
      I0 => \wordEgrRd[3]_i_4_n_0\,
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I4 => p_0_in,
      O => \egrAXIS_tdata[127]_i_1_n_0\
    );
\egrAXIS_tdata[127]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(127),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(127),
      I4 => \egrfifo_reg[2]_41\(127),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(127)
    );
\egrAXIS_tdata[127]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00005554"
    )
        port map (
      I0 => ixRdEgrfifo(0),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I4 => ixRdEgrfifo(1),
      O => \egrAXIS_tdata[127]_i_3_n_0\
    );
\egrAXIS_tdata[127]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44444440"
    )
        port map (
      I0 => ixRdEgrfifo(1),
      I1 => ixRdEgrfifo(0),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      O => \egrAXIS_tdata[127]_i_4_n_0\
    );
\egrAXIS_tdata[127]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55540000"
    )
        port map (
      I0 => ixRdEgrfifo(0),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I4 => ixRdEgrfifo(1),
      O => \egrAXIS_tdata[127]_i_5_n_0\
    );
\egrAXIS_tdata[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(12),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(12),
      I4 => \egrfifo_reg[2]_41\(12),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(12)
    );
\egrAXIS_tdata[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(13),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(13),
      I4 => \egrfifo_reg[2]_41\(13),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(13)
    );
\egrAXIS_tdata[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(14),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(14),
      I4 => \egrfifo_reg[2]_41\(14),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(14)
    );
\egrAXIS_tdata[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(15),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(15),
      I4 => \egrfifo_reg[2]_41\(15),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(15)
    );
\egrAXIS_tdata[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(16),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(16),
      I4 => \egrfifo_reg[2]_41\(16),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(16)
    );
\egrAXIS_tdata[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(17),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(17),
      I4 => \egrfifo_reg[2]_41\(17),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(17)
    );
\egrAXIS_tdata[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(18),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(18),
      I4 => \egrfifo_reg[2]_41\(18),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(18)
    );
\egrAXIS_tdata[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(19),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(19),
      I4 => \egrfifo_reg[2]_41\(19),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(19)
    );
\egrAXIS_tdata[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(1),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(1),
      I4 => \egrfifo_reg[2]_41\(1),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(1)
    );
\egrAXIS_tdata[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(20),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(20),
      I4 => \egrfifo_reg[2]_41\(20),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(20)
    );
\egrAXIS_tdata[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(21),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(21),
      I4 => \egrfifo_reg[2]_41\(21),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(21)
    );
\egrAXIS_tdata[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(22),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(22),
      I4 => \egrfifo_reg[2]_41\(22),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(22)
    );
\egrAXIS_tdata[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(23),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(23),
      I4 => \egrfifo_reg[2]_41\(23),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(23)
    );
\egrAXIS_tdata[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(24),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(24),
      I4 => \egrfifo_reg[2]_41\(24),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(24)
    );
\egrAXIS_tdata[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(25),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(25),
      I4 => \egrfifo_reg[2]_41\(25),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(25)
    );
\egrAXIS_tdata[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(26),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(26),
      I4 => \egrfifo_reg[2]_41\(26),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(26)
    );
\egrAXIS_tdata[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(27),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(27),
      I4 => \egrfifo_reg[2]_41\(27),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(27)
    );
\egrAXIS_tdata[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(28),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(28),
      I4 => \egrfifo_reg[2]_41\(28),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(28)
    );
\egrAXIS_tdata[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(29),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(29),
      I4 => \egrfifo_reg[2]_41\(29),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(29)
    );
\egrAXIS_tdata[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(2),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(2),
      I4 => \egrfifo_reg[2]_41\(2),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(2)
    );
\egrAXIS_tdata[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(30),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(30),
      I4 => \egrfifo_reg[2]_41\(30),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(30)
    );
\egrAXIS_tdata[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(31),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(31),
      I4 => \egrfifo_reg[2]_41\(31),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(31)
    );
\egrAXIS_tdata[32]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(32),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(32),
      I4 => \egrfifo_reg[2]_41\(32),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(32)
    );
\egrAXIS_tdata[33]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(33),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(33),
      I4 => \egrfifo_reg[2]_41\(33),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(33)
    );
\egrAXIS_tdata[34]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(34),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(34),
      I4 => \egrfifo_reg[2]_41\(34),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(34)
    );
\egrAXIS_tdata[35]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(35),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(35),
      I4 => \egrfifo_reg[2]_41\(35),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(35)
    );
\egrAXIS_tdata[36]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(36),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(36),
      I4 => \egrfifo_reg[2]_41\(36),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(36)
    );
\egrAXIS_tdata[37]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(37),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(37),
      I4 => \egrfifo_reg[2]_41\(37),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(37)
    );
\egrAXIS_tdata[38]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(38),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(38),
      I4 => \egrfifo_reg[2]_41\(38),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(38)
    );
\egrAXIS_tdata[39]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(39),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(39),
      I4 => \egrfifo_reg[2]_41\(39),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(39)
    );
\egrAXIS_tdata[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(3),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(3),
      I4 => \egrfifo_reg[2]_41\(3),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(3)
    );
\egrAXIS_tdata[40]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(40),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(40),
      I4 => \egrfifo_reg[2]_41\(40),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(40)
    );
\egrAXIS_tdata[41]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(41),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(41),
      I4 => \egrfifo_reg[2]_41\(41),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(41)
    );
\egrAXIS_tdata[42]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(42),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(42),
      I4 => \egrfifo_reg[2]_41\(42),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(42)
    );
\egrAXIS_tdata[43]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(43),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(43),
      I4 => \egrfifo_reg[2]_41\(43),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(43)
    );
\egrAXIS_tdata[44]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(44),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(44),
      I4 => \egrfifo_reg[2]_41\(44),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(44)
    );
\egrAXIS_tdata[45]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(45),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(45),
      I4 => \egrfifo_reg[2]_41\(45),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(45)
    );
\egrAXIS_tdata[46]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(46),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(46),
      I4 => \egrfifo_reg[2]_41\(46),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(46)
    );
\egrAXIS_tdata[47]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(47),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(47),
      I4 => \egrfifo_reg[2]_41\(47),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(47)
    );
\egrAXIS_tdata[48]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(48),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(48),
      I4 => \egrfifo_reg[2]_41\(48),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(48)
    );
\egrAXIS_tdata[49]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(49),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(49),
      I4 => \egrfifo_reg[2]_41\(49),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(49)
    );
\egrAXIS_tdata[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(4),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(4),
      I4 => \egrfifo_reg[2]_41\(4),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(4)
    );
\egrAXIS_tdata[50]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(50),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(50),
      I4 => \egrfifo_reg[2]_41\(50),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(50)
    );
\egrAXIS_tdata[51]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(51),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(51),
      I4 => \egrfifo_reg[2]_41\(51),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(51)
    );
\egrAXIS_tdata[52]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(52),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(52),
      I4 => \egrfifo_reg[2]_41\(52),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(52)
    );
\egrAXIS_tdata[53]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(53),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(53),
      I4 => \egrfifo_reg[2]_41\(53),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(53)
    );
\egrAXIS_tdata[54]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(54),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(54),
      I4 => \egrfifo_reg[2]_41\(54),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(54)
    );
\egrAXIS_tdata[55]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(55),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(55),
      I4 => \egrfifo_reg[2]_41\(55),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(55)
    );
\egrAXIS_tdata[56]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(56),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(56),
      I4 => \egrfifo_reg[2]_41\(56),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(56)
    );
\egrAXIS_tdata[57]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(57),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(57),
      I4 => \egrfifo_reg[2]_41\(57),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(57)
    );
\egrAXIS_tdata[58]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(58),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(58),
      I4 => \egrfifo_reg[2]_41\(58),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(58)
    );
\egrAXIS_tdata[59]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(59),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(59),
      I4 => \egrfifo_reg[2]_41\(59),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(59)
    );
\egrAXIS_tdata[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(5),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(5),
      I4 => \egrfifo_reg[2]_41\(5),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(5)
    );
\egrAXIS_tdata[60]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(60),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(60),
      I4 => \egrfifo_reg[2]_41\(60),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(60)
    );
\egrAXIS_tdata[61]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(61),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(61),
      I4 => \egrfifo_reg[2]_41\(61),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(61)
    );
\egrAXIS_tdata[62]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(62),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(62),
      I4 => \egrfifo_reg[2]_41\(62),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(62)
    );
\egrAXIS_tdata[63]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(63),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(63),
      I4 => \egrfifo_reg[2]_41\(63),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(63)
    );
\egrAXIS_tdata[64]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(64),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(64),
      I4 => \egrfifo_reg[2]_41\(64),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(64)
    );
\egrAXIS_tdata[65]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(65),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(65),
      I4 => \egrfifo_reg[2]_41\(65),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(65)
    );
\egrAXIS_tdata[66]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(66),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(66),
      I4 => \egrfifo_reg[2]_41\(66),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(66)
    );
\egrAXIS_tdata[67]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(67),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(67),
      I4 => \egrfifo_reg[2]_41\(67),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(67)
    );
\egrAXIS_tdata[68]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(68),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(68),
      I4 => \egrfifo_reg[2]_41\(68),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(68)
    );
\egrAXIS_tdata[69]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(69),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(69),
      I4 => \egrfifo_reg[2]_41\(69),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(69)
    );
\egrAXIS_tdata[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(6),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(6),
      I4 => \egrfifo_reg[2]_41\(6),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(6)
    );
\egrAXIS_tdata[70]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(70),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(70),
      I4 => \egrfifo_reg[2]_41\(70),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(70)
    );
\egrAXIS_tdata[71]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(71),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(71),
      I4 => \egrfifo_reg[2]_41\(71),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(71)
    );
\egrAXIS_tdata[72]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(72),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(72),
      I4 => \egrfifo_reg[2]_41\(72),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(72)
    );
\egrAXIS_tdata[73]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(73),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(73),
      I4 => \egrfifo_reg[2]_41\(73),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(73)
    );
\egrAXIS_tdata[74]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(74),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(74),
      I4 => \egrfifo_reg[2]_41\(74),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(74)
    );
\egrAXIS_tdata[75]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(75),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(75),
      I4 => \egrfifo_reg[2]_41\(75),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(75)
    );
\egrAXIS_tdata[76]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(76),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(76),
      I4 => \egrfifo_reg[2]_41\(76),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(76)
    );
\egrAXIS_tdata[77]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(77),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(77),
      I4 => \egrfifo_reg[2]_41\(77),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(77)
    );
\egrAXIS_tdata[78]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(78),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(78),
      I4 => \egrfifo_reg[2]_41\(78),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(78)
    );
\egrAXIS_tdata[79]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(79),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(79),
      I4 => \egrfifo_reg[2]_41\(79),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(79)
    );
\egrAXIS_tdata[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(7),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(7),
      I4 => \egrfifo_reg[2]_41\(7),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(7)
    );
\egrAXIS_tdata[80]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(80),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(80),
      I4 => \egrfifo_reg[2]_41\(80),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(80)
    );
\egrAXIS_tdata[81]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(81),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(81),
      I4 => \egrfifo_reg[2]_41\(81),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(81)
    );
\egrAXIS_tdata[82]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(82),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(82),
      I4 => \egrfifo_reg[2]_41\(82),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(82)
    );
\egrAXIS_tdata[83]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(83),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(83),
      I4 => \egrfifo_reg[2]_41\(83),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(83)
    );
\egrAXIS_tdata[84]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(84),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(84),
      I4 => \egrfifo_reg[2]_41\(84),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(84)
    );
\egrAXIS_tdata[85]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(85),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(85),
      I4 => \egrfifo_reg[2]_41\(85),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(85)
    );
\egrAXIS_tdata[86]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(86),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(86),
      I4 => \egrfifo_reg[2]_41\(86),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(86)
    );
\egrAXIS_tdata[87]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(87),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(87),
      I4 => \egrfifo_reg[2]_41\(87),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(87)
    );
\egrAXIS_tdata[88]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(88),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(88),
      I4 => \egrfifo_reg[2]_41\(88),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(88)
    );
\egrAXIS_tdata[89]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(89),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(89),
      I4 => \egrfifo_reg[2]_41\(89),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(89)
    );
\egrAXIS_tdata[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(8),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(8),
      I4 => \egrfifo_reg[2]_41\(8),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(8)
    );
\egrAXIS_tdata[90]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(90),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(90),
      I4 => \egrfifo_reg[2]_41\(90),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(90)
    );
\egrAXIS_tdata[91]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(91),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(91),
      I4 => \egrfifo_reg[2]_41\(91),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(91)
    );
\egrAXIS_tdata[92]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(92),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(92),
      I4 => \egrfifo_reg[2]_41\(92),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(92)
    );
\egrAXIS_tdata[93]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(93),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(93),
      I4 => \egrfifo_reg[2]_41\(93),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(93)
    );
\egrAXIS_tdata[94]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(94),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(94),
      I4 => \egrfifo_reg[2]_41\(94),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(94)
    );
\egrAXIS_tdata[95]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(95),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(95),
      I4 => \egrfifo_reg[2]_41\(95),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(95)
    );
\egrAXIS_tdata[96]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(96),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(96),
      I4 => \egrfifo_reg[2]_41\(96),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(96)
    );
\egrAXIS_tdata[97]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(97),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(97),
      I4 => \egrfifo_reg[2]_41\(97),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(97)
    );
\egrAXIS_tdata[98]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(98),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(98),
      I4 => \egrfifo_reg[2]_41\(98),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(98)
    );
\egrAXIS_tdata[99]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(99),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(99),
      I4 => \egrfifo_reg[2]_41\(99),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(99)
    );
\egrAXIS_tdata[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \egrAXIS_tdata[127]_i_3_n_0\,
      I1 => \egrfifo_reg[0]_43\(9),
      I2 => \egrAXIS_tdata[127]_i_4_n_0\,
      I3 => \egrfifo_reg[1]_42\(9),
      I4 => \egrfifo_reg[2]_41\(9),
      I5 => \egrAXIS_tdata[127]_i_5_n_0\,
      O => egrAXIS_tdata(9)
    );
\egrAXIS_tdata_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(0),
      Q => wrAAXI_wdata(0)
    );
\egrAXIS_tdata_reg[100]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(100),
      Q => wrAAXI_wdata(100)
    );
\egrAXIS_tdata_reg[101]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(101),
      Q => wrAAXI_wdata(101)
    );
\egrAXIS_tdata_reg[102]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(102),
      Q => wrAAXI_wdata(102)
    );
\egrAXIS_tdata_reg[103]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(103),
      Q => wrAAXI_wdata(103)
    );
\egrAXIS_tdata_reg[104]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(104),
      Q => wrAAXI_wdata(104)
    );
\egrAXIS_tdata_reg[105]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(105),
      Q => wrAAXI_wdata(105)
    );
\egrAXIS_tdata_reg[106]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(106),
      Q => wrAAXI_wdata(106)
    );
\egrAXIS_tdata_reg[107]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(107),
      Q => wrAAXI_wdata(107)
    );
\egrAXIS_tdata_reg[108]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(108),
      Q => wrAAXI_wdata(108)
    );
\egrAXIS_tdata_reg[109]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(109),
      Q => wrAAXI_wdata(109)
    );
\egrAXIS_tdata_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(10),
      Q => wrAAXI_wdata(10)
    );
\egrAXIS_tdata_reg[110]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(110),
      Q => wrAAXI_wdata(110)
    );
\egrAXIS_tdata_reg[111]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(111),
      Q => wrAAXI_wdata(111)
    );
\egrAXIS_tdata_reg[112]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(112),
      Q => wrAAXI_wdata(112)
    );
\egrAXIS_tdata_reg[113]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(113),
      Q => wrAAXI_wdata(113)
    );
\egrAXIS_tdata_reg[114]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(114),
      Q => wrAAXI_wdata(114)
    );
\egrAXIS_tdata_reg[115]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(115),
      Q => wrAAXI_wdata(115)
    );
\egrAXIS_tdata_reg[116]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(116),
      Q => wrAAXI_wdata(116)
    );
\egrAXIS_tdata_reg[117]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(117),
      Q => wrAAXI_wdata(117)
    );
\egrAXIS_tdata_reg[118]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(118),
      Q => wrAAXI_wdata(118)
    );
\egrAXIS_tdata_reg[119]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(119),
      Q => wrAAXI_wdata(119)
    );
\egrAXIS_tdata_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(11),
      Q => wrAAXI_wdata(11)
    );
\egrAXIS_tdata_reg[120]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(120),
      Q => wrAAXI_wdata(120)
    );
\egrAXIS_tdata_reg[121]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(121),
      Q => wrAAXI_wdata(121)
    );
\egrAXIS_tdata_reg[122]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(122),
      Q => wrAAXI_wdata(122)
    );
\egrAXIS_tdata_reg[123]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(123),
      Q => wrAAXI_wdata(123)
    );
\egrAXIS_tdata_reg[124]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(124),
      Q => wrAAXI_wdata(124)
    );
\egrAXIS_tdata_reg[125]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(125),
      Q => wrAAXI_wdata(125)
    );
\egrAXIS_tdata_reg[126]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(126),
      Q => wrAAXI_wdata(126)
    );
\egrAXIS_tdata_reg[127]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(127),
      Q => wrAAXI_wdata(127)
    );
\egrAXIS_tdata_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(12),
      Q => wrAAXI_wdata(12)
    );
\egrAXIS_tdata_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(13),
      Q => wrAAXI_wdata(13)
    );
\egrAXIS_tdata_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(14),
      Q => wrAAXI_wdata(14)
    );
\egrAXIS_tdata_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(15),
      Q => wrAAXI_wdata(15)
    );
\egrAXIS_tdata_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(16),
      Q => wrAAXI_wdata(16)
    );
\egrAXIS_tdata_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(17),
      Q => wrAAXI_wdata(17)
    );
\egrAXIS_tdata_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(18),
      Q => wrAAXI_wdata(18)
    );
\egrAXIS_tdata_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(19),
      Q => wrAAXI_wdata(19)
    );
\egrAXIS_tdata_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(1),
      Q => wrAAXI_wdata(1)
    );
\egrAXIS_tdata_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(20),
      Q => wrAAXI_wdata(20)
    );
\egrAXIS_tdata_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(21),
      Q => wrAAXI_wdata(21)
    );
\egrAXIS_tdata_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(22),
      Q => wrAAXI_wdata(22)
    );
\egrAXIS_tdata_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(23),
      Q => wrAAXI_wdata(23)
    );
\egrAXIS_tdata_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(24),
      Q => wrAAXI_wdata(24)
    );
\egrAXIS_tdata_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(25),
      Q => wrAAXI_wdata(25)
    );
\egrAXIS_tdata_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(26),
      Q => wrAAXI_wdata(26)
    );
\egrAXIS_tdata_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(27),
      Q => wrAAXI_wdata(27)
    );
\egrAXIS_tdata_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(28),
      Q => wrAAXI_wdata(28)
    );
\egrAXIS_tdata_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(29),
      Q => wrAAXI_wdata(29)
    );
\egrAXIS_tdata_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(2),
      Q => wrAAXI_wdata(2)
    );
\egrAXIS_tdata_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(30),
      Q => wrAAXI_wdata(30)
    );
\egrAXIS_tdata_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(31),
      Q => wrAAXI_wdata(31)
    );
\egrAXIS_tdata_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(32),
      Q => wrAAXI_wdata(32)
    );
\egrAXIS_tdata_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(33),
      Q => wrAAXI_wdata(33)
    );
\egrAXIS_tdata_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(34),
      Q => wrAAXI_wdata(34)
    );
\egrAXIS_tdata_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(35),
      Q => wrAAXI_wdata(35)
    );
\egrAXIS_tdata_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(36),
      Q => wrAAXI_wdata(36)
    );
\egrAXIS_tdata_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(37),
      Q => wrAAXI_wdata(37)
    );
\egrAXIS_tdata_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(38),
      Q => wrAAXI_wdata(38)
    );
\egrAXIS_tdata_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(39),
      Q => wrAAXI_wdata(39)
    );
\egrAXIS_tdata_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(3),
      Q => wrAAXI_wdata(3)
    );
\egrAXIS_tdata_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(40),
      Q => wrAAXI_wdata(40)
    );
\egrAXIS_tdata_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(41),
      Q => wrAAXI_wdata(41)
    );
\egrAXIS_tdata_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(42),
      Q => wrAAXI_wdata(42)
    );
\egrAXIS_tdata_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(43),
      Q => wrAAXI_wdata(43)
    );
\egrAXIS_tdata_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(44),
      Q => wrAAXI_wdata(44)
    );
\egrAXIS_tdata_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(45),
      Q => wrAAXI_wdata(45)
    );
\egrAXIS_tdata_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(46),
      Q => wrAAXI_wdata(46)
    );
\egrAXIS_tdata_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(47),
      Q => wrAAXI_wdata(47)
    );
\egrAXIS_tdata_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(48),
      Q => wrAAXI_wdata(48)
    );
\egrAXIS_tdata_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(49),
      Q => wrAAXI_wdata(49)
    );
\egrAXIS_tdata_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(4),
      Q => wrAAXI_wdata(4)
    );
\egrAXIS_tdata_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(50),
      Q => wrAAXI_wdata(50)
    );
\egrAXIS_tdata_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(51),
      Q => wrAAXI_wdata(51)
    );
\egrAXIS_tdata_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(52),
      Q => wrAAXI_wdata(52)
    );
\egrAXIS_tdata_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(53),
      Q => wrAAXI_wdata(53)
    );
\egrAXIS_tdata_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(54),
      Q => wrAAXI_wdata(54)
    );
\egrAXIS_tdata_reg[55]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(55),
      Q => wrAAXI_wdata(55)
    );
\egrAXIS_tdata_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(56),
      Q => wrAAXI_wdata(56)
    );
\egrAXIS_tdata_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(57),
      Q => wrAAXI_wdata(57)
    );
\egrAXIS_tdata_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(58),
      Q => wrAAXI_wdata(58)
    );
\egrAXIS_tdata_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(59),
      Q => wrAAXI_wdata(59)
    );
\egrAXIS_tdata_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(5),
      Q => wrAAXI_wdata(5)
    );
\egrAXIS_tdata_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(60),
      Q => wrAAXI_wdata(60)
    );
\egrAXIS_tdata_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(61),
      Q => wrAAXI_wdata(61)
    );
\egrAXIS_tdata_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(62),
      Q => wrAAXI_wdata(62)
    );
\egrAXIS_tdata_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(63),
      Q => wrAAXI_wdata(63)
    );
\egrAXIS_tdata_reg[64]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(64),
      Q => wrAAXI_wdata(64)
    );
\egrAXIS_tdata_reg[65]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(65),
      Q => wrAAXI_wdata(65)
    );
\egrAXIS_tdata_reg[66]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(66),
      Q => wrAAXI_wdata(66)
    );
\egrAXIS_tdata_reg[67]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(67),
      Q => wrAAXI_wdata(67)
    );
\egrAXIS_tdata_reg[68]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(68),
      Q => wrAAXI_wdata(68)
    );
\egrAXIS_tdata_reg[69]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(69),
      Q => wrAAXI_wdata(69)
    );
\egrAXIS_tdata_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(6),
      Q => wrAAXI_wdata(6)
    );
\egrAXIS_tdata_reg[70]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(70),
      Q => wrAAXI_wdata(70)
    );
\egrAXIS_tdata_reg[71]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(71),
      Q => wrAAXI_wdata(71)
    );
\egrAXIS_tdata_reg[72]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(72),
      Q => wrAAXI_wdata(72)
    );
\egrAXIS_tdata_reg[73]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(73),
      Q => wrAAXI_wdata(73)
    );
\egrAXIS_tdata_reg[74]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(74),
      Q => wrAAXI_wdata(74)
    );
\egrAXIS_tdata_reg[75]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(75),
      Q => wrAAXI_wdata(75)
    );
\egrAXIS_tdata_reg[76]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(76),
      Q => wrAAXI_wdata(76)
    );
\egrAXIS_tdata_reg[77]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(77),
      Q => wrAAXI_wdata(77)
    );
\egrAXIS_tdata_reg[78]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(78),
      Q => wrAAXI_wdata(78)
    );
\egrAXIS_tdata_reg[79]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(79),
      Q => wrAAXI_wdata(79)
    );
\egrAXIS_tdata_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(7),
      Q => wrAAXI_wdata(7)
    );
\egrAXIS_tdata_reg[80]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(80),
      Q => wrAAXI_wdata(80)
    );
\egrAXIS_tdata_reg[81]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(81),
      Q => wrAAXI_wdata(81)
    );
\egrAXIS_tdata_reg[82]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(82),
      Q => wrAAXI_wdata(82)
    );
\egrAXIS_tdata_reg[83]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(83),
      Q => wrAAXI_wdata(83)
    );
\egrAXIS_tdata_reg[84]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(84),
      Q => wrAAXI_wdata(84)
    );
\egrAXIS_tdata_reg[85]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(85),
      Q => wrAAXI_wdata(85)
    );
\egrAXIS_tdata_reg[86]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(86),
      Q => wrAAXI_wdata(86)
    );
\egrAXIS_tdata_reg[87]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(87),
      Q => wrAAXI_wdata(87)
    );
\egrAXIS_tdata_reg[88]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(88),
      Q => wrAAXI_wdata(88)
    );
\egrAXIS_tdata_reg[89]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(89),
      Q => wrAAXI_wdata(89)
    );
\egrAXIS_tdata_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(8),
      Q => wrAAXI_wdata(8)
    );
\egrAXIS_tdata_reg[90]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(90),
      Q => wrAAXI_wdata(90)
    );
\egrAXIS_tdata_reg[91]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(91),
      Q => wrAAXI_wdata(91)
    );
\egrAXIS_tdata_reg[92]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(92),
      Q => wrAAXI_wdata(92)
    );
\egrAXIS_tdata_reg[93]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(93),
      Q => wrAAXI_wdata(93)
    );
\egrAXIS_tdata_reg[94]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(94),
      Q => wrAAXI_wdata(94)
    );
\egrAXIS_tdata_reg[95]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(95),
      Q => wrAAXI_wdata(95)
    );
\egrAXIS_tdata_reg[96]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(96),
      Q => wrAAXI_wdata(96)
    );
\egrAXIS_tdata_reg[97]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(97),
      Q => wrAAXI_wdata(97)
    );
\egrAXIS_tdata_reg[98]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(98),
      Q => wrAAXI_wdata(98)
    );
\egrAXIS_tdata_reg[99]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(99),
      Q => wrAAXI_wdata(99)
    );
\egrAXIS_tdata_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrAXIS_tdata[127]_i_1_n_0\,
      CLR => AR(0),
      D => egrAXIS_tdata(9),
      Q => wrAAXI_wdata(9)
    );
egrAXIS_tlast_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABFBBBF8A8F888F"
    )
        port map (
      I0 => egrAXIS_tlast_i_2_n_0,
      I1 => egrAXIS_tlast_i_3_n_0,
      I2 => \wordEgrWr[3]_i_4_n_0\,
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I4 => p_0_in,
      I5 => \^egraxis_tlast\,
      O => egrAXIS_tlast_i_1_n_0
    );
egrAXIS_tlast_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4800000000000000"
    )
        port map (
      I0 => wordEgrRd(0),
      I1 => wordEgrRd(1),
      I2 => \wordEgrLast_reg_n_0_[2]\,
      I3 => \wordEgrWr[3]_i_4_n_0\,
      I4 => wordEgrRd(2),
      I5 => wordEgrRd(3),
      O => egrAXIS_tlast_i_2_n_0
    );
egrAXIS_tlast_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2800000000000000"
    )
        port map (
      I0 => \wordEgrRd[3]_i_4_n_0\,
      I1 => \wordEgrLast_reg_n_0_[2]\,
      I2 => wordEgrRd(0),
      I3 => wordEgrRd(1),
      I4 => wordEgrRd(2),
      I5 => wordEgrRd(3),
      O => egrAXIS_tlast_i_3_n_0
    );
egrAXIS_tlast_reg: unisim.vcomponents.FDPE
     port map (
      C => memclk,
      CE => '1',
      D => egrAXIS_tlast_i_1_n_0,
      PRE => AR(0),
      Q => \^egraxis_tlast\
    );
\egrfifo[0][127]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02020202020202FF"
    )
        port map (
      I0 => \egrfifo[2][127]_i_3_n_0\,
      I1 => ixWrEgrfifo(0),
      I2 => ixWrEgrfifo(1),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I5 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      O => \egrfifo[0][127]_i_1_n_0\
    );
\egrfifo[1][127]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08080808080808FF"
    )
        port map (
      I0 => \egrfifo[2][127]_i_3_n_0\,
      I1 => ixWrEgrfifo(0),
      I2 => ixWrEgrfifo(1),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I5 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      O => \egrfifo[1][127]_i_1_n_0\
    );
\egrfifo[2][127]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40404040404040FF"
    )
        port map (
      I0 => ixWrEgrfifo(0),
      I1 => ixWrEgrfifo(1),
      I2 => \egrfifo[2][127]_i_3_n_0\,
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I5 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      O => \egrfifo[2][127]_i_1_n_0\
    );
\egrfifo[2][127]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F0000000EE00EE"
    )
        port map (
      I0 => \i_reg[0]__0_n_0\,
      I1 => p_0_in,
      I2 => enRowbufBEgrstrm1,
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I5 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      O => \egrfifo[2][127]_i_3_n_0\
    );
\egrfifo[2][127]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE00"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I3 => liveBNotA_memclk,
      O => \egrfifo[2][127]_i_4_n_0\
    );
\egrfifo[2][127]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I3 => liveBNotA_memclk,
      O => \egrfifo[2][127]_i_5_n_0\
    );
\egrfifo_reg[0][0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(0),
      Q => \egrfifo_reg[0]_43\(0)
    );
\egrfifo_reg[0][100]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(100),
      Q => \egrfifo_reg[0]_43\(100)
    );
\egrfifo_reg[0][101]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(101),
      Q => \egrfifo_reg[0]_43\(101)
    );
\egrfifo_reg[0][102]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(102),
      Q => \egrfifo_reg[0]_43\(102)
    );
\egrfifo_reg[0][103]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(103),
      Q => \egrfifo_reg[0]_43\(103)
    );
\egrfifo_reg[0][104]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(104),
      Q => \egrfifo_reg[0]_43\(104)
    );
\egrfifo_reg[0][105]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(105),
      Q => \egrfifo_reg[0]_43\(105)
    );
\egrfifo_reg[0][106]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(106),
      Q => \egrfifo_reg[0]_43\(106)
    );
\egrfifo_reg[0][107]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(107),
      Q => \egrfifo_reg[0]_43\(107)
    );
\egrfifo_reg[0][108]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(108),
      Q => \egrfifo_reg[0]_43\(108)
    );
\egrfifo_reg[0][109]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(109),
      Q => \egrfifo_reg[0]_43\(109)
    );
\egrfifo_reg[0][10]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(10),
      Q => \egrfifo_reg[0]_43\(10)
    );
\egrfifo_reg[0][110]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(110),
      Q => \egrfifo_reg[0]_43\(110)
    );
\egrfifo_reg[0][111]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(111),
      Q => \egrfifo_reg[0]_43\(111)
    );
\egrfifo_reg[0][112]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(112),
      Q => \egrfifo_reg[0]_43\(112)
    );
\egrfifo_reg[0][113]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(113),
      Q => \egrfifo_reg[0]_43\(113)
    );
\egrfifo_reg[0][114]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(114),
      Q => \egrfifo_reg[0]_43\(114)
    );
\egrfifo_reg[0][115]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(115),
      Q => \egrfifo_reg[0]_43\(115)
    );
\egrfifo_reg[0][116]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(116),
      Q => \egrfifo_reg[0]_43\(116)
    );
\egrfifo_reg[0][117]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(117),
      Q => \egrfifo_reg[0]_43\(117)
    );
\egrfifo_reg[0][118]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(118),
      Q => \egrfifo_reg[0]_43\(118)
    );
\egrfifo_reg[0][119]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(119),
      Q => \egrfifo_reg[0]_43\(119)
    );
\egrfifo_reg[0][11]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(11),
      Q => \egrfifo_reg[0]_43\(11)
    );
\egrfifo_reg[0][120]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(120),
      Q => \egrfifo_reg[0]_43\(120)
    );
\egrfifo_reg[0][121]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(121),
      Q => \egrfifo_reg[0]_43\(121)
    );
\egrfifo_reg[0][122]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(122),
      Q => \egrfifo_reg[0]_43\(122)
    );
\egrfifo_reg[0][123]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(123),
      Q => \egrfifo_reg[0]_43\(123)
    );
\egrfifo_reg[0][124]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(124),
      Q => \egrfifo_reg[0]_43\(124)
    );
\egrfifo_reg[0][125]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(125),
      Q => \egrfifo_reg[0]_43\(125)
    );
\egrfifo_reg[0][126]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(126),
      Q => \egrfifo_reg[0]_43\(126)
    );
\egrfifo_reg[0][127]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(127),
      Q => \egrfifo_reg[0]_43\(127)
    );
\egrfifo_reg[0][12]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(12),
      Q => \egrfifo_reg[0]_43\(12)
    );
\egrfifo_reg[0][13]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(13),
      Q => \egrfifo_reg[0]_43\(13)
    );
\egrfifo_reg[0][14]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(14),
      Q => \egrfifo_reg[0]_43\(14)
    );
\egrfifo_reg[0][15]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(15),
      Q => \egrfifo_reg[0]_43\(15)
    );
\egrfifo_reg[0][16]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(16),
      Q => \egrfifo_reg[0]_43\(16)
    );
\egrfifo_reg[0][17]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(17),
      Q => \egrfifo_reg[0]_43\(17)
    );
\egrfifo_reg[0][18]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(18),
      Q => \egrfifo_reg[0]_43\(18)
    );
\egrfifo_reg[0][19]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(19),
      Q => \egrfifo_reg[0]_43\(19)
    );
\egrfifo_reg[0][1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(1),
      Q => \egrfifo_reg[0]_43\(1)
    );
\egrfifo_reg[0][20]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(20),
      Q => \egrfifo_reg[0]_43\(20)
    );
\egrfifo_reg[0][21]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(21),
      Q => \egrfifo_reg[0]_43\(21)
    );
\egrfifo_reg[0][22]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(22),
      Q => \egrfifo_reg[0]_43\(22)
    );
\egrfifo_reg[0][23]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(23),
      Q => \egrfifo_reg[0]_43\(23)
    );
\egrfifo_reg[0][24]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(24),
      Q => \egrfifo_reg[0]_43\(24)
    );
\egrfifo_reg[0][25]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(25),
      Q => \egrfifo_reg[0]_43\(25)
    );
\egrfifo_reg[0][26]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(26),
      Q => \egrfifo_reg[0]_43\(26)
    );
\egrfifo_reg[0][27]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(27),
      Q => \egrfifo_reg[0]_43\(27)
    );
\egrfifo_reg[0][28]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(28),
      Q => \egrfifo_reg[0]_43\(28)
    );
\egrfifo_reg[0][29]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(29),
      Q => \egrfifo_reg[0]_43\(29)
    );
\egrfifo_reg[0][2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(2),
      Q => \egrfifo_reg[0]_43\(2)
    );
\egrfifo_reg[0][30]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(30),
      Q => \egrfifo_reg[0]_43\(30)
    );
\egrfifo_reg[0][31]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(31),
      Q => \egrfifo_reg[0]_43\(31)
    );
\egrfifo_reg[0][32]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(32),
      Q => \egrfifo_reg[0]_43\(32)
    );
\egrfifo_reg[0][33]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(33),
      Q => \egrfifo_reg[0]_43\(33)
    );
\egrfifo_reg[0][34]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(34),
      Q => \egrfifo_reg[0]_43\(34)
    );
\egrfifo_reg[0][35]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(35),
      Q => \egrfifo_reg[0]_43\(35)
    );
\egrfifo_reg[0][36]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(36),
      Q => \egrfifo_reg[0]_43\(36)
    );
\egrfifo_reg[0][37]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(37),
      Q => \egrfifo_reg[0]_43\(37)
    );
\egrfifo_reg[0][38]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(38),
      Q => \egrfifo_reg[0]_43\(38)
    );
\egrfifo_reg[0][39]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(39),
      Q => \egrfifo_reg[0]_43\(39)
    );
\egrfifo_reg[0][3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(3),
      Q => \egrfifo_reg[0]_43\(3)
    );
\egrfifo_reg[0][40]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(40),
      Q => \egrfifo_reg[0]_43\(40)
    );
\egrfifo_reg[0][41]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(41),
      Q => \egrfifo_reg[0]_43\(41)
    );
\egrfifo_reg[0][42]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(42),
      Q => \egrfifo_reg[0]_43\(42)
    );
\egrfifo_reg[0][43]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(43),
      Q => \egrfifo_reg[0]_43\(43)
    );
\egrfifo_reg[0][44]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(44),
      Q => \egrfifo_reg[0]_43\(44)
    );
\egrfifo_reg[0][45]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(45),
      Q => \egrfifo_reg[0]_43\(45)
    );
\egrfifo_reg[0][46]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(46),
      Q => \egrfifo_reg[0]_43\(46)
    );
\egrfifo_reg[0][47]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(47),
      Q => \egrfifo_reg[0]_43\(47)
    );
\egrfifo_reg[0][48]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(48),
      Q => \egrfifo_reg[0]_43\(48)
    );
\egrfifo_reg[0][49]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(49),
      Q => \egrfifo_reg[0]_43\(49)
    );
\egrfifo_reg[0][4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(4),
      Q => \egrfifo_reg[0]_43\(4)
    );
\egrfifo_reg[0][50]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(50),
      Q => \egrfifo_reg[0]_43\(50)
    );
\egrfifo_reg[0][51]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(51),
      Q => \egrfifo_reg[0]_43\(51)
    );
\egrfifo_reg[0][52]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(52),
      Q => \egrfifo_reg[0]_43\(52)
    );
\egrfifo_reg[0][53]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(53),
      Q => \egrfifo_reg[0]_43\(53)
    );
\egrfifo_reg[0][54]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(54),
      Q => \egrfifo_reg[0]_43\(54)
    );
\egrfifo_reg[0][55]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(55),
      Q => \egrfifo_reg[0]_43\(55)
    );
\egrfifo_reg[0][56]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(56),
      Q => \egrfifo_reg[0]_43\(56)
    );
\egrfifo_reg[0][57]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(57),
      Q => \egrfifo_reg[0]_43\(57)
    );
\egrfifo_reg[0][58]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(58),
      Q => \egrfifo_reg[0]_43\(58)
    );
\egrfifo_reg[0][59]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(59),
      Q => \egrfifo_reg[0]_43\(59)
    );
\egrfifo_reg[0][5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(5),
      Q => \egrfifo_reg[0]_43\(5)
    );
\egrfifo_reg[0][60]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(60),
      Q => \egrfifo_reg[0]_43\(60)
    );
\egrfifo_reg[0][61]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(61),
      Q => \egrfifo_reg[0]_43\(61)
    );
\egrfifo_reg[0][62]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(62),
      Q => \egrfifo_reg[0]_43\(62)
    );
\egrfifo_reg[0][63]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(63),
      Q => \egrfifo_reg[0]_43\(63)
    );
\egrfifo_reg[0][64]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(64),
      Q => \egrfifo_reg[0]_43\(64)
    );
\egrfifo_reg[0][65]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(65),
      Q => \egrfifo_reg[0]_43\(65)
    );
\egrfifo_reg[0][66]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(66),
      Q => \egrfifo_reg[0]_43\(66)
    );
\egrfifo_reg[0][67]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(67),
      Q => \egrfifo_reg[0]_43\(67)
    );
\egrfifo_reg[0][68]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(68),
      Q => \egrfifo_reg[0]_43\(68)
    );
\egrfifo_reg[0][69]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(69),
      Q => \egrfifo_reg[0]_43\(69)
    );
\egrfifo_reg[0][6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(6),
      Q => \egrfifo_reg[0]_43\(6)
    );
\egrfifo_reg[0][70]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(70),
      Q => \egrfifo_reg[0]_43\(70)
    );
\egrfifo_reg[0][71]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(71),
      Q => \egrfifo_reg[0]_43\(71)
    );
\egrfifo_reg[0][72]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(72),
      Q => \egrfifo_reg[0]_43\(72)
    );
\egrfifo_reg[0][73]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(73),
      Q => \egrfifo_reg[0]_43\(73)
    );
\egrfifo_reg[0][74]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(74),
      Q => \egrfifo_reg[0]_43\(74)
    );
\egrfifo_reg[0][75]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(75),
      Q => \egrfifo_reg[0]_43\(75)
    );
\egrfifo_reg[0][76]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(76),
      Q => \egrfifo_reg[0]_43\(76)
    );
\egrfifo_reg[0][77]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(77),
      Q => \egrfifo_reg[0]_43\(77)
    );
\egrfifo_reg[0][78]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(78),
      Q => \egrfifo_reg[0]_43\(78)
    );
\egrfifo_reg[0][79]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(79),
      Q => \egrfifo_reg[0]_43\(79)
    );
\egrfifo_reg[0][7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(7),
      Q => \egrfifo_reg[0]_43\(7)
    );
\egrfifo_reg[0][80]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(80),
      Q => \egrfifo_reg[0]_43\(80)
    );
\egrfifo_reg[0][81]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(81),
      Q => \egrfifo_reg[0]_43\(81)
    );
\egrfifo_reg[0][82]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(82),
      Q => \egrfifo_reg[0]_43\(82)
    );
\egrfifo_reg[0][83]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(83),
      Q => \egrfifo_reg[0]_43\(83)
    );
\egrfifo_reg[0][84]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(84),
      Q => \egrfifo_reg[0]_43\(84)
    );
\egrfifo_reg[0][85]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(85),
      Q => \egrfifo_reg[0]_43\(85)
    );
\egrfifo_reg[0][86]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(86),
      Q => \egrfifo_reg[0]_43\(86)
    );
\egrfifo_reg[0][87]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(87),
      Q => \egrfifo_reg[0]_43\(87)
    );
\egrfifo_reg[0][88]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(88),
      Q => \egrfifo_reg[0]_43\(88)
    );
\egrfifo_reg[0][89]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(89),
      Q => \egrfifo_reg[0]_43\(89)
    );
\egrfifo_reg[0][8]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(8),
      Q => \egrfifo_reg[0]_43\(8)
    );
\egrfifo_reg[0][90]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(90),
      Q => \egrfifo_reg[0]_43\(90)
    );
\egrfifo_reg[0][91]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(91),
      Q => \egrfifo_reg[0]_43\(91)
    );
\egrfifo_reg[0][92]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(92),
      Q => \egrfifo_reg[0]_43\(92)
    );
\egrfifo_reg[0][93]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(93),
      Q => \egrfifo_reg[0]_43\(93)
    );
\egrfifo_reg[0][94]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(94),
      Q => \egrfifo_reg[0]_43\(94)
    );
\egrfifo_reg[0][95]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(95),
      Q => \egrfifo_reg[0]_43\(95)
    );
\egrfifo_reg[0][96]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(96),
      Q => \egrfifo_reg[0]_43\(96)
    );
\egrfifo_reg[0][97]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(97),
      Q => \egrfifo_reg[0]_43\(97)
    );
\egrfifo_reg[0][98]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(98),
      Q => \egrfifo_reg[0]_43\(98)
    );
\egrfifo_reg[0][99]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(99),
      Q => \egrfifo_reg[0]_43\(99)
    );
\egrfifo_reg[0][9]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[0][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(9),
      Q => \egrfifo_reg[0]_43\(9)
    );
\egrfifo_reg[1][0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(0),
      Q => \egrfifo_reg[1]_42\(0)
    );
\egrfifo_reg[1][100]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(100),
      Q => \egrfifo_reg[1]_42\(100)
    );
\egrfifo_reg[1][101]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(101),
      Q => \egrfifo_reg[1]_42\(101)
    );
\egrfifo_reg[1][102]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(102),
      Q => \egrfifo_reg[1]_42\(102)
    );
\egrfifo_reg[1][103]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(103),
      Q => \egrfifo_reg[1]_42\(103)
    );
\egrfifo_reg[1][104]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(104),
      Q => \egrfifo_reg[1]_42\(104)
    );
\egrfifo_reg[1][105]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(105),
      Q => \egrfifo_reg[1]_42\(105)
    );
\egrfifo_reg[1][106]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(106),
      Q => \egrfifo_reg[1]_42\(106)
    );
\egrfifo_reg[1][107]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(107),
      Q => \egrfifo_reg[1]_42\(107)
    );
\egrfifo_reg[1][108]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(108),
      Q => \egrfifo_reg[1]_42\(108)
    );
\egrfifo_reg[1][109]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(109),
      Q => \egrfifo_reg[1]_42\(109)
    );
\egrfifo_reg[1][10]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(10),
      Q => \egrfifo_reg[1]_42\(10)
    );
\egrfifo_reg[1][110]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(110),
      Q => \egrfifo_reg[1]_42\(110)
    );
\egrfifo_reg[1][111]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(111),
      Q => \egrfifo_reg[1]_42\(111)
    );
\egrfifo_reg[1][112]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(112),
      Q => \egrfifo_reg[1]_42\(112)
    );
\egrfifo_reg[1][113]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(113),
      Q => \egrfifo_reg[1]_42\(113)
    );
\egrfifo_reg[1][114]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(114),
      Q => \egrfifo_reg[1]_42\(114)
    );
\egrfifo_reg[1][115]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(115),
      Q => \egrfifo_reg[1]_42\(115)
    );
\egrfifo_reg[1][116]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(116),
      Q => \egrfifo_reg[1]_42\(116)
    );
\egrfifo_reg[1][117]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(117),
      Q => \egrfifo_reg[1]_42\(117)
    );
\egrfifo_reg[1][118]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(118),
      Q => \egrfifo_reg[1]_42\(118)
    );
\egrfifo_reg[1][119]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(119),
      Q => \egrfifo_reg[1]_42\(119)
    );
\egrfifo_reg[1][11]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(11),
      Q => \egrfifo_reg[1]_42\(11)
    );
\egrfifo_reg[1][120]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(120),
      Q => \egrfifo_reg[1]_42\(120)
    );
\egrfifo_reg[1][121]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(121),
      Q => \egrfifo_reg[1]_42\(121)
    );
\egrfifo_reg[1][122]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(122),
      Q => \egrfifo_reg[1]_42\(122)
    );
\egrfifo_reg[1][123]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(123),
      Q => \egrfifo_reg[1]_42\(123)
    );
\egrfifo_reg[1][124]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(124),
      Q => \egrfifo_reg[1]_42\(124)
    );
\egrfifo_reg[1][125]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(125),
      Q => \egrfifo_reg[1]_42\(125)
    );
\egrfifo_reg[1][126]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(126),
      Q => \egrfifo_reg[1]_42\(126)
    );
\egrfifo_reg[1][127]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(127),
      Q => \egrfifo_reg[1]_42\(127)
    );
\egrfifo_reg[1][12]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(12),
      Q => \egrfifo_reg[1]_42\(12)
    );
\egrfifo_reg[1][13]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(13),
      Q => \egrfifo_reg[1]_42\(13)
    );
\egrfifo_reg[1][14]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(14),
      Q => \egrfifo_reg[1]_42\(14)
    );
\egrfifo_reg[1][15]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(15),
      Q => \egrfifo_reg[1]_42\(15)
    );
\egrfifo_reg[1][16]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(16),
      Q => \egrfifo_reg[1]_42\(16)
    );
\egrfifo_reg[1][17]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(17),
      Q => \egrfifo_reg[1]_42\(17)
    );
\egrfifo_reg[1][18]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(18),
      Q => \egrfifo_reg[1]_42\(18)
    );
\egrfifo_reg[1][19]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(19),
      Q => \egrfifo_reg[1]_42\(19)
    );
\egrfifo_reg[1][1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(1),
      Q => \egrfifo_reg[1]_42\(1)
    );
\egrfifo_reg[1][20]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(20),
      Q => \egrfifo_reg[1]_42\(20)
    );
\egrfifo_reg[1][21]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(21),
      Q => \egrfifo_reg[1]_42\(21)
    );
\egrfifo_reg[1][22]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(22),
      Q => \egrfifo_reg[1]_42\(22)
    );
\egrfifo_reg[1][23]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(23),
      Q => \egrfifo_reg[1]_42\(23)
    );
\egrfifo_reg[1][24]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(24),
      Q => \egrfifo_reg[1]_42\(24)
    );
\egrfifo_reg[1][25]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(25),
      Q => \egrfifo_reg[1]_42\(25)
    );
\egrfifo_reg[1][26]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(26),
      Q => \egrfifo_reg[1]_42\(26)
    );
\egrfifo_reg[1][27]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(27),
      Q => \egrfifo_reg[1]_42\(27)
    );
\egrfifo_reg[1][28]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(28),
      Q => \egrfifo_reg[1]_42\(28)
    );
\egrfifo_reg[1][29]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(29),
      Q => \egrfifo_reg[1]_42\(29)
    );
\egrfifo_reg[1][2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(2),
      Q => \egrfifo_reg[1]_42\(2)
    );
\egrfifo_reg[1][30]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(30),
      Q => \egrfifo_reg[1]_42\(30)
    );
\egrfifo_reg[1][31]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(31),
      Q => \egrfifo_reg[1]_42\(31)
    );
\egrfifo_reg[1][32]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(32),
      Q => \egrfifo_reg[1]_42\(32)
    );
\egrfifo_reg[1][33]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(33),
      Q => \egrfifo_reg[1]_42\(33)
    );
\egrfifo_reg[1][34]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(34),
      Q => \egrfifo_reg[1]_42\(34)
    );
\egrfifo_reg[1][35]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(35),
      Q => \egrfifo_reg[1]_42\(35)
    );
\egrfifo_reg[1][36]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(36),
      Q => \egrfifo_reg[1]_42\(36)
    );
\egrfifo_reg[1][37]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(37),
      Q => \egrfifo_reg[1]_42\(37)
    );
\egrfifo_reg[1][38]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(38),
      Q => \egrfifo_reg[1]_42\(38)
    );
\egrfifo_reg[1][39]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(39),
      Q => \egrfifo_reg[1]_42\(39)
    );
\egrfifo_reg[1][3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(3),
      Q => \egrfifo_reg[1]_42\(3)
    );
\egrfifo_reg[1][40]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(40),
      Q => \egrfifo_reg[1]_42\(40)
    );
\egrfifo_reg[1][41]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(41),
      Q => \egrfifo_reg[1]_42\(41)
    );
\egrfifo_reg[1][42]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(42),
      Q => \egrfifo_reg[1]_42\(42)
    );
\egrfifo_reg[1][43]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(43),
      Q => \egrfifo_reg[1]_42\(43)
    );
\egrfifo_reg[1][44]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(44),
      Q => \egrfifo_reg[1]_42\(44)
    );
\egrfifo_reg[1][45]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(45),
      Q => \egrfifo_reg[1]_42\(45)
    );
\egrfifo_reg[1][46]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(46),
      Q => \egrfifo_reg[1]_42\(46)
    );
\egrfifo_reg[1][47]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(47),
      Q => \egrfifo_reg[1]_42\(47)
    );
\egrfifo_reg[1][48]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(48),
      Q => \egrfifo_reg[1]_42\(48)
    );
\egrfifo_reg[1][49]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(49),
      Q => \egrfifo_reg[1]_42\(49)
    );
\egrfifo_reg[1][4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(4),
      Q => \egrfifo_reg[1]_42\(4)
    );
\egrfifo_reg[1][50]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(50),
      Q => \egrfifo_reg[1]_42\(50)
    );
\egrfifo_reg[1][51]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(51),
      Q => \egrfifo_reg[1]_42\(51)
    );
\egrfifo_reg[1][52]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(52),
      Q => \egrfifo_reg[1]_42\(52)
    );
\egrfifo_reg[1][53]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(53),
      Q => \egrfifo_reg[1]_42\(53)
    );
\egrfifo_reg[1][54]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(54),
      Q => \egrfifo_reg[1]_42\(54)
    );
\egrfifo_reg[1][55]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(55),
      Q => \egrfifo_reg[1]_42\(55)
    );
\egrfifo_reg[1][56]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(56),
      Q => \egrfifo_reg[1]_42\(56)
    );
\egrfifo_reg[1][57]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(57),
      Q => \egrfifo_reg[1]_42\(57)
    );
\egrfifo_reg[1][58]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(58),
      Q => \egrfifo_reg[1]_42\(58)
    );
\egrfifo_reg[1][59]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(59),
      Q => \egrfifo_reg[1]_42\(59)
    );
\egrfifo_reg[1][5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(5),
      Q => \egrfifo_reg[1]_42\(5)
    );
\egrfifo_reg[1][60]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(60),
      Q => \egrfifo_reg[1]_42\(60)
    );
\egrfifo_reg[1][61]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(61),
      Q => \egrfifo_reg[1]_42\(61)
    );
\egrfifo_reg[1][62]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(62),
      Q => \egrfifo_reg[1]_42\(62)
    );
\egrfifo_reg[1][63]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(63),
      Q => \egrfifo_reg[1]_42\(63)
    );
\egrfifo_reg[1][64]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(64),
      Q => \egrfifo_reg[1]_42\(64)
    );
\egrfifo_reg[1][65]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(65),
      Q => \egrfifo_reg[1]_42\(65)
    );
\egrfifo_reg[1][66]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(66),
      Q => \egrfifo_reg[1]_42\(66)
    );
\egrfifo_reg[1][67]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(67),
      Q => \egrfifo_reg[1]_42\(67)
    );
\egrfifo_reg[1][68]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(68),
      Q => \egrfifo_reg[1]_42\(68)
    );
\egrfifo_reg[1][69]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(69),
      Q => \egrfifo_reg[1]_42\(69)
    );
\egrfifo_reg[1][6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(6),
      Q => \egrfifo_reg[1]_42\(6)
    );
\egrfifo_reg[1][70]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(70),
      Q => \egrfifo_reg[1]_42\(70)
    );
\egrfifo_reg[1][71]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(71),
      Q => \egrfifo_reg[1]_42\(71)
    );
\egrfifo_reg[1][72]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(72),
      Q => \egrfifo_reg[1]_42\(72)
    );
\egrfifo_reg[1][73]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(73),
      Q => \egrfifo_reg[1]_42\(73)
    );
\egrfifo_reg[1][74]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(74),
      Q => \egrfifo_reg[1]_42\(74)
    );
\egrfifo_reg[1][75]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(75),
      Q => \egrfifo_reg[1]_42\(75)
    );
\egrfifo_reg[1][76]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(76),
      Q => \egrfifo_reg[1]_42\(76)
    );
\egrfifo_reg[1][77]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(77),
      Q => \egrfifo_reg[1]_42\(77)
    );
\egrfifo_reg[1][78]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(78),
      Q => \egrfifo_reg[1]_42\(78)
    );
\egrfifo_reg[1][79]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(79),
      Q => \egrfifo_reg[1]_42\(79)
    );
\egrfifo_reg[1][7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(7),
      Q => \egrfifo_reg[1]_42\(7)
    );
\egrfifo_reg[1][80]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(80),
      Q => \egrfifo_reg[1]_42\(80)
    );
\egrfifo_reg[1][81]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(81),
      Q => \egrfifo_reg[1]_42\(81)
    );
\egrfifo_reg[1][82]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(82),
      Q => \egrfifo_reg[1]_42\(82)
    );
\egrfifo_reg[1][83]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(83),
      Q => \egrfifo_reg[1]_42\(83)
    );
\egrfifo_reg[1][84]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(84),
      Q => \egrfifo_reg[1]_42\(84)
    );
\egrfifo_reg[1][85]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(85),
      Q => \egrfifo_reg[1]_42\(85)
    );
\egrfifo_reg[1][86]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(86),
      Q => \egrfifo_reg[1]_42\(86)
    );
\egrfifo_reg[1][87]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(87),
      Q => \egrfifo_reg[1]_42\(87)
    );
\egrfifo_reg[1][88]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(88),
      Q => \egrfifo_reg[1]_42\(88)
    );
\egrfifo_reg[1][89]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(89),
      Q => \egrfifo_reg[1]_42\(89)
    );
\egrfifo_reg[1][8]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(8),
      Q => \egrfifo_reg[1]_42\(8)
    );
\egrfifo_reg[1][90]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(90),
      Q => \egrfifo_reg[1]_42\(90)
    );
\egrfifo_reg[1][91]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(91),
      Q => \egrfifo_reg[1]_42\(91)
    );
\egrfifo_reg[1][92]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(92),
      Q => \egrfifo_reg[1]_42\(92)
    );
\egrfifo_reg[1][93]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(93),
      Q => \egrfifo_reg[1]_42\(93)
    );
\egrfifo_reg[1][94]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(94),
      Q => \egrfifo_reg[1]_42\(94)
    );
\egrfifo_reg[1][95]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(95),
      Q => \egrfifo_reg[1]_42\(95)
    );
\egrfifo_reg[1][96]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(96),
      Q => \egrfifo_reg[1]_42\(96)
    );
\egrfifo_reg[1][97]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(97),
      Q => \egrfifo_reg[1]_42\(97)
    );
\egrfifo_reg[1][98]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(98),
      Q => \egrfifo_reg[1]_42\(98)
    );
\egrfifo_reg[1][99]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(99),
      Q => \egrfifo_reg[1]_42\(99)
    );
\egrfifo_reg[1][9]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[1][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(9),
      Q => \egrfifo_reg[1]_42\(9)
    );
\egrfifo_reg[2][0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(0),
      Q => \egrfifo_reg[2]_41\(0)
    );
\egrfifo_reg[2][100]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(100),
      Q => \egrfifo_reg[2]_41\(100)
    );
\egrfifo_reg[2][101]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(101),
      Q => \egrfifo_reg[2]_41\(101)
    );
\egrfifo_reg[2][102]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(102),
      Q => \egrfifo_reg[2]_41\(102)
    );
\egrfifo_reg[2][103]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(103),
      Q => \egrfifo_reg[2]_41\(103)
    );
\egrfifo_reg[2][104]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(104),
      Q => \egrfifo_reg[2]_41\(104)
    );
\egrfifo_reg[2][105]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(105),
      Q => \egrfifo_reg[2]_41\(105)
    );
\egrfifo_reg[2][106]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(106),
      Q => \egrfifo_reg[2]_41\(106)
    );
\egrfifo_reg[2][107]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(107),
      Q => \egrfifo_reg[2]_41\(107)
    );
\egrfifo_reg[2][108]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(108),
      Q => \egrfifo_reg[2]_41\(108)
    );
\egrfifo_reg[2][109]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(109),
      Q => \egrfifo_reg[2]_41\(109)
    );
\egrfifo_reg[2][10]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(10),
      Q => \egrfifo_reg[2]_41\(10)
    );
\egrfifo_reg[2][110]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(110),
      Q => \egrfifo_reg[2]_41\(110)
    );
\egrfifo_reg[2][111]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(111),
      Q => \egrfifo_reg[2]_41\(111)
    );
\egrfifo_reg[2][112]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(112),
      Q => \egrfifo_reg[2]_41\(112)
    );
\egrfifo_reg[2][113]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(113),
      Q => \egrfifo_reg[2]_41\(113)
    );
\egrfifo_reg[2][114]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(114),
      Q => \egrfifo_reg[2]_41\(114)
    );
\egrfifo_reg[2][115]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(115),
      Q => \egrfifo_reg[2]_41\(115)
    );
\egrfifo_reg[2][116]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(116),
      Q => \egrfifo_reg[2]_41\(116)
    );
\egrfifo_reg[2][117]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(117),
      Q => \egrfifo_reg[2]_41\(117)
    );
\egrfifo_reg[2][118]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(118),
      Q => \egrfifo_reg[2]_41\(118)
    );
\egrfifo_reg[2][119]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(119),
      Q => \egrfifo_reg[2]_41\(119)
    );
\egrfifo_reg[2][11]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(11),
      Q => \egrfifo_reg[2]_41\(11)
    );
\egrfifo_reg[2][120]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(120),
      Q => \egrfifo_reg[2]_41\(120)
    );
\egrfifo_reg[2][121]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(121),
      Q => \egrfifo_reg[2]_41\(121)
    );
\egrfifo_reg[2][122]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(122),
      Q => \egrfifo_reg[2]_41\(122)
    );
\egrfifo_reg[2][123]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(123),
      Q => \egrfifo_reg[2]_41\(123)
    );
\egrfifo_reg[2][124]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(124),
      Q => \egrfifo_reg[2]_41\(124)
    );
\egrfifo_reg[2][125]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(125),
      Q => \egrfifo_reg[2]_41\(125)
    );
\egrfifo_reg[2][126]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(126),
      Q => \egrfifo_reg[2]_41\(126)
    );
\egrfifo_reg[2][127]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(127),
      Q => \egrfifo_reg[2]_41\(127)
    );
\egrfifo_reg[2][12]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(12),
      Q => \egrfifo_reg[2]_41\(12)
    );
\egrfifo_reg[2][13]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(13),
      Q => \egrfifo_reg[2]_41\(13)
    );
\egrfifo_reg[2][14]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(14),
      Q => \egrfifo_reg[2]_41\(14)
    );
\egrfifo_reg[2][15]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(15),
      Q => \egrfifo_reg[2]_41\(15)
    );
\egrfifo_reg[2][16]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(16),
      Q => \egrfifo_reg[2]_41\(16)
    );
\egrfifo_reg[2][17]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(17),
      Q => \egrfifo_reg[2]_41\(17)
    );
\egrfifo_reg[2][18]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(18),
      Q => \egrfifo_reg[2]_41\(18)
    );
\egrfifo_reg[2][19]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(19),
      Q => \egrfifo_reg[2]_41\(19)
    );
\egrfifo_reg[2][1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(1),
      Q => \egrfifo_reg[2]_41\(1)
    );
\egrfifo_reg[2][20]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(20),
      Q => \egrfifo_reg[2]_41\(20)
    );
\egrfifo_reg[2][21]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(21),
      Q => \egrfifo_reg[2]_41\(21)
    );
\egrfifo_reg[2][22]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(22),
      Q => \egrfifo_reg[2]_41\(22)
    );
\egrfifo_reg[2][23]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(23),
      Q => \egrfifo_reg[2]_41\(23)
    );
\egrfifo_reg[2][24]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(24),
      Q => \egrfifo_reg[2]_41\(24)
    );
\egrfifo_reg[2][25]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(25),
      Q => \egrfifo_reg[2]_41\(25)
    );
\egrfifo_reg[2][26]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(26),
      Q => \egrfifo_reg[2]_41\(26)
    );
\egrfifo_reg[2][27]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(27),
      Q => \egrfifo_reg[2]_41\(27)
    );
\egrfifo_reg[2][28]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(28),
      Q => \egrfifo_reg[2]_41\(28)
    );
\egrfifo_reg[2][29]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(29),
      Q => \egrfifo_reg[2]_41\(29)
    );
\egrfifo_reg[2][2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(2),
      Q => \egrfifo_reg[2]_41\(2)
    );
\egrfifo_reg[2][30]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(30),
      Q => \egrfifo_reg[2]_41\(30)
    );
\egrfifo_reg[2][31]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(31),
      Q => \egrfifo_reg[2]_41\(31)
    );
\egrfifo_reg[2][32]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(32),
      Q => \egrfifo_reg[2]_41\(32)
    );
\egrfifo_reg[2][33]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(33),
      Q => \egrfifo_reg[2]_41\(33)
    );
\egrfifo_reg[2][34]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(34),
      Q => \egrfifo_reg[2]_41\(34)
    );
\egrfifo_reg[2][35]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(35),
      Q => \egrfifo_reg[2]_41\(35)
    );
\egrfifo_reg[2][36]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(36),
      Q => \egrfifo_reg[2]_41\(36)
    );
\egrfifo_reg[2][37]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(37),
      Q => \egrfifo_reg[2]_41\(37)
    );
\egrfifo_reg[2][38]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(38),
      Q => \egrfifo_reg[2]_41\(38)
    );
\egrfifo_reg[2][39]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(39),
      Q => \egrfifo_reg[2]_41\(39)
    );
\egrfifo_reg[2][3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(3),
      Q => \egrfifo_reg[2]_41\(3)
    );
\egrfifo_reg[2][40]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(40),
      Q => \egrfifo_reg[2]_41\(40)
    );
\egrfifo_reg[2][41]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(41),
      Q => \egrfifo_reg[2]_41\(41)
    );
\egrfifo_reg[2][42]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(42),
      Q => \egrfifo_reg[2]_41\(42)
    );
\egrfifo_reg[2][43]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(43),
      Q => \egrfifo_reg[2]_41\(43)
    );
\egrfifo_reg[2][44]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(44),
      Q => \egrfifo_reg[2]_41\(44)
    );
\egrfifo_reg[2][45]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(45),
      Q => \egrfifo_reg[2]_41\(45)
    );
\egrfifo_reg[2][46]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(46),
      Q => \egrfifo_reg[2]_41\(46)
    );
\egrfifo_reg[2][47]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(47),
      Q => \egrfifo_reg[2]_41\(47)
    );
\egrfifo_reg[2][48]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(48),
      Q => \egrfifo_reg[2]_41\(48)
    );
\egrfifo_reg[2][49]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(49),
      Q => \egrfifo_reg[2]_41\(49)
    );
\egrfifo_reg[2][4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(4),
      Q => \egrfifo_reg[2]_41\(4)
    );
\egrfifo_reg[2][50]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(50),
      Q => \egrfifo_reg[2]_41\(50)
    );
\egrfifo_reg[2][51]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(51),
      Q => \egrfifo_reg[2]_41\(51)
    );
\egrfifo_reg[2][52]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(52),
      Q => \egrfifo_reg[2]_41\(52)
    );
\egrfifo_reg[2][53]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(53),
      Q => \egrfifo_reg[2]_41\(53)
    );
\egrfifo_reg[2][54]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(54),
      Q => \egrfifo_reg[2]_41\(54)
    );
\egrfifo_reg[2][55]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(55),
      Q => \egrfifo_reg[2]_41\(55)
    );
\egrfifo_reg[2][56]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(56),
      Q => \egrfifo_reg[2]_41\(56)
    );
\egrfifo_reg[2][57]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(57),
      Q => \egrfifo_reg[2]_41\(57)
    );
\egrfifo_reg[2][58]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(58),
      Q => \egrfifo_reg[2]_41\(58)
    );
\egrfifo_reg[2][59]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(59),
      Q => \egrfifo_reg[2]_41\(59)
    );
\egrfifo_reg[2][5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(5),
      Q => \egrfifo_reg[2]_41\(5)
    );
\egrfifo_reg[2][60]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(60),
      Q => \egrfifo_reg[2]_41\(60)
    );
\egrfifo_reg[2][61]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(61),
      Q => \egrfifo_reg[2]_41\(61)
    );
\egrfifo_reg[2][62]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(62),
      Q => \egrfifo_reg[2]_41\(62)
    );
\egrfifo_reg[2][63]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(63),
      Q => \egrfifo_reg[2]_41\(63)
    );
\egrfifo_reg[2][64]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(64),
      Q => \egrfifo_reg[2]_41\(64)
    );
\egrfifo_reg[2][65]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(65),
      Q => \egrfifo_reg[2]_41\(65)
    );
\egrfifo_reg[2][66]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(66),
      Q => \egrfifo_reg[2]_41\(66)
    );
\egrfifo_reg[2][67]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(67),
      Q => \egrfifo_reg[2]_41\(67)
    );
\egrfifo_reg[2][68]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(68),
      Q => \egrfifo_reg[2]_41\(68)
    );
\egrfifo_reg[2][69]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(69),
      Q => \egrfifo_reg[2]_41\(69)
    );
\egrfifo_reg[2][6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(6),
      Q => \egrfifo_reg[2]_41\(6)
    );
\egrfifo_reg[2][70]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(70),
      Q => \egrfifo_reg[2]_41\(70)
    );
\egrfifo_reg[2][71]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(71),
      Q => \egrfifo_reg[2]_41\(71)
    );
\egrfifo_reg[2][72]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(72),
      Q => \egrfifo_reg[2]_41\(72)
    );
\egrfifo_reg[2][73]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(73),
      Q => \egrfifo_reg[2]_41\(73)
    );
\egrfifo_reg[2][74]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(74),
      Q => \egrfifo_reg[2]_41\(74)
    );
\egrfifo_reg[2][75]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(75),
      Q => \egrfifo_reg[2]_41\(75)
    );
\egrfifo_reg[2][76]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(76),
      Q => \egrfifo_reg[2]_41\(76)
    );
\egrfifo_reg[2][77]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(77),
      Q => \egrfifo_reg[2]_41\(77)
    );
\egrfifo_reg[2][78]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(78),
      Q => \egrfifo_reg[2]_41\(78)
    );
\egrfifo_reg[2][79]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(79),
      Q => \egrfifo_reg[2]_41\(79)
    );
\egrfifo_reg[2][7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(7),
      Q => \egrfifo_reg[2]_41\(7)
    );
\egrfifo_reg[2][80]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(80),
      Q => \egrfifo_reg[2]_41\(80)
    );
\egrfifo_reg[2][81]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(81),
      Q => \egrfifo_reg[2]_41\(81)
    );
\egrfifo_reg[2][82]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(82),
      Q => \egrfifo_reg[2]_41\(82)
    );
\egrfifo_reg[2][83]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(83),
      Q => \egrfifo_reg[2]_41\(83)
    );
\egrfifo_reg[2][84]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(84),
      Q => \egrfifo_reg[2]_41\(84)
    );
\egrfifo_reg[2][85]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(85),
      Q => \egrfifo_reg[2]_41\(85)
    );
\egrfifo_reg[2][86]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(86),
      Q => \egrfifo_reg[2]_41\(86)
    );
\egrfifo_reg[2][87]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(87),
      Q => \egrfifo_reg[2]_41\(87)
    );
\egrfifo_reg[2][88]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(88),
      Q => \egrfifo_reg[2]_41\(88)
    );
\egrfifo_reg[2][89]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(89),
      Q => \egrfifo_reg[2]_41\(89)
    );
\egrfifo_reg[2][8]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(8),
      Q => \egrfifo_reg[2]_41\(8)
    );
\egrfifo_reg[2][90]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(90),
      Q => \egrfifo_reg[2]_41\(90)
    );
\egrfifo_reg[2][91]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(91),
      Q => \egrfifo_reg[2]_41\(91)
    );
\egrfifo_reg[2][92]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(92),
      Q => \egrfifo_reg[2]_41\(92)
    );
\egrfifo_reg[2][93]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(93),
      Q => \egrfifo_reg[2]_41\(93)
    );
\egrfifo_reg[2][94]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(94),
      Q => \egrfifo_reg[2]_41\(94)
    );
\egrfifo_reg[2][95]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(95),
      Q => \egrfifo_reg[2]_41\(95)
    );
\egrfifo_reg[2][96]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(96),
      Q => \egrfifo_reg[2]_41\(96)
    );
\egrfifo_reg[2][97]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(97),
      Q => \egrfifo_reg[2]_41\(97)
    );
\egrfifo_reg[2][98]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(98),
      Q => \egrfifo_reg[2]_41\(98)
    );
\egrfifo_reg[2][99]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(99),
      Q => \egrfifo_reg[2]_41\(99)
    );
\egrfifo_reg[2][9]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \egrfifo[2][127]_i_1_n_0\,
      CLR => AR(0),
      D => \egrfifo[2]_44\(9),
      Q => \egrfifo_reg[2]_41\(9)
    );
enRowbufBEgrstr_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBBFFEE008B00EE"
    )
        port map (
      I0 => enRowbufBEgrstr_i_2_n_0,
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I2 => \wordEgrRd[3]_i_3_n_0\,
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I5 => enRowbufBEgrstr,
      O => enRowbufBEgrstr_i_1_n_0
    );
enRowbufBEgrstr_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000E0000000000"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I2 => ddrAXI_wdata_0_sn_1,
      I3 => ddrAXI_wready,
      I4 => \^egraxis_tlast\,
      I5 => \wordEgrWr[3]_i_5_n_0\,
      O => enRowbufBEgrstr_i_2_n_0
    );
enRowbufBEgrstr_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => enRowbufBEgrstr_i_1_n_0,
      Q => enRowbufBEgrstr
    );
enRowbufBEgrstrm1_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABA8FFFFABA80000"
    )
        port map (
      I0 => enRowbufBEgrstr,
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I4 => p_3_out(0),
      I5 => enRowbufBEgrstrm1,
      O => enRowbufBEgrstrm1_i_1_n_0
    );
enRowbufBEgrstrm1_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => enRowbufBEgrstrm1_i_1_n_0,
      Q => enRowbufBEgrstrm1
    );
enRowbufStream_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2C002000"
    )
        port map (
      I0 => rgbFromVideoinAXIS_tvalidm2,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^rng_reg_0\,
      I4 => enRowbufStream_reg_n_0,
      O => enRowbufStream_i_1_n_0
    );
enRowbufStream_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => enRowbufStream_i_1_n_0,
      Q => enRowbufStream_reg_n_0
    );
\i[0]__0_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I1 => p_0_in,
      I2 => \i_reg[0]__0_n_0\,
      O => i(0)
    );
\i[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CCCCCCC8"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(2),
      I1 => rng_memclk,
      I2 => \^stateswap_reg[3]_0\(0),
      I3 => \^stateswap_reg[3]_0\(1),
      I4 => \^stateswap_reg[3]_0\(3),
      I5 => \i_reg_n_0_[0]\,
      O => \i[0]_i_1__5_n_0\
    );
\i[1]__0_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0015001F00150015"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I1 => p_0_in,
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I4 => ddrAXI_wlast_INST_0_i_2_n_0,
      I5 => \^stateswap_reg[3]_0\(2),
      O => \i[1]__0_i_1__0_n_0\
    );
\i[1]__0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => p_0_in,
      I1 => \i_reg[0]__0_n_0\,
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      O => i(1)
    );
\i[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555555555F5F575F"
    )
        port map (
      I0 => rng_memclk,
      I1 => \^stateswap_reg[3]_0\(0),
      I2 => ddrAXI_wlast_INST_0_i_2_n_0,
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[0]\,
      I5 => \^stateswap_reg[3]_0\(2),
      O => \i[1]_i_1__3_n_0\
    );
\i[1]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000CCC8CCC80000"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(2),
      I1 => rng_memclk,
      I2 => \^stateswap_reg[3]_0\(0),
      I3 => ddrAXI_wlast_INST_0_i_2_n_0,
      I4 => \i_reg_n_0_[1]\,
      I5 => \i_reg_n_0_[0]\,
      O => \i[1]_i_2__2_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \i[1]_i_1__3_n_0\,
      CLR => AR(0),
      D => \i[0]_i_1__5_n_0\,
      Q => \i_reg_n_0_[0]\
    );
\i_reg[0]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \i[1]__0_i_1__0_n_0\,
      CLR => AR(0),
      D => i(0),
      Q => \i_reg[0]__0_n_0\
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \i[1]_i_1__3_n_0\,
      CLR => AR(0),
      D => \i[1]_i_2__2_n_0\,
      Q => \i_reg_n_0_[1]\
    );
\i_reg[1]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \i[1]__0_i_1__0_n_0\,
      CLR => AR(0),
      D => i(1),
      Q => p_0_in
    );
\ixMemAcq[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \ixMemNext_reg_n_0_[0]\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMemAcq[0]_i_1_n_0\
    );
\ixMemAcq[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \ixMemNext_reg_n_0_[1]\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMemAcq[1]_i_1_n_0\
    );
\ixMemAcq[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \ixMemNext_reg_n_0_[2]\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMemAcq[2]_i_1_n_0\
    );
\ixMemAcq[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \ixMemNext_reg_n_0_[3]\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMemAcq[3]_i_1_n_0\
    );
\ixMemAcq[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \ixMemNext_reg_n_0_[4]\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMemAcq[4]_i_1_n_0\
    );
\ixMemAcq[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \ixMemNext_reg_n_0_[5]\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMemAcq[5]_i_1_n_0\
    );
\ixMemAcq[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \ixMemNext_reg_n_0_[6]\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMemAcq[6]_i_1_n_0\
    );
\ixMemAcq[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \ixMemNext_reg_n_0_[7]\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMemAcq[7]_i_1_n_0\
    );
\ixMemAcq_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      D => \ixMemAcq[0]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmemacq_reg[7]_0\(0)
    );
\ixMemAcq_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      D => \ixMemAcq[1]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmemacq_reg[7]_0\(1)
    );
\ixMemAcq_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      D => \ixMemAcq[2]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmemacq_reg[7]_0\(2)
    );
\ixMemAcq_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      D => \ixMemAcq[3]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmemacq_reg[7]_0\(3)
    );
\ixMemAcq_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      D => \ixMemAcq[4]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmemacq_reg[7]_0\(4)
    );
\ixMemAcq_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      D => \ixMemAcq[5]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmemacq_reg[7]_0\(5)
    );
\ixMemAcq_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      D => \ixMemAcq[6]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmemacq_reg[7]_0\(6)
    );
\ixMemAcq_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      D => \ixMemAcq[7]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmemacq_reg[7]_0\(7)
    );
\ixMemNext_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => E(0),
      D => \ixMemNext_reg[7]_0\(0),
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \ixMemNext_reg_n_0_[0]\
    );
\ixMemNext_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => E(0),
      D => \ixMemNext_reg[7]_0\(1),
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \ixMemNext_reg_n_0_[1]\
    );
\ixMemNext_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => E(0),
      D => \ixMemNext_reg[7]_0\(2),
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \ixMemNext_reg_n_0_[2]\
    );
\ixMemNext_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => E(0),
      D => \ixMemNext_reg[7]_0\(3),
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \ixMemNext_reg_n_0_[3]\
    );
\ixMemNext_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => E(0),
      D => \ixMemNext_reg[7]_0\(4),
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \ixMemNext_reg_n_0_[4]\
    );
\ixMemNext_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => E(0),
      D => \ixMemNext_reg[7]_0\(5),
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \ixMemNext_reg_n_0_[5]\
    );
\ixMemNext_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => E(0),
      D => \ixMemNext_reg[7]_0\(6),
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \ixMemNext_reg_n_0_[6]\
    );
\ixMemNext_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => E(0),
      D => \ixMemNext_reg[7]_0\(7),
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \ixMemNext_reg_n_0_[7]\
    );
\ixMem[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \^ixmemacq_reg[7]_0\(0),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMem[0]_i_1_n_0\
    );
\ixMem[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \^ixmemacq_reg[7]_0\(1),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMem[1]_i_1_n_0\
    );
\ixMem[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \^ixmemacq_reg[7]_0\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMem[2]_i_1_n_0\
    );
\ixMem[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \^ixmemacq_reg[7]_0\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMem[3]_i_1_n_0\
    );
\ixMem[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \^ixmemacq_reg[7]_0\(4),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMem[4]_i_1_n_0\
    );
\ixMem[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \^ixmemacq_reg[7]_0\(5),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMem[5]_i_1_n_0\
    );
\ixMem[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \^ixmemacq_reg[7]_0\(6),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMem[6]_i_1_n_0\
    );
\ixMem[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"400FFFFF"
    )
        port map (
      I0 => \dwrRowbuf_reg[0]_1\,
      I1 => \stateStream_reg[1]_0\,
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^rng_reg_0\,
      O => ixMem
    );
\ixMem[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => \^ixmemacq_reg[7]_0\(7),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \ixMem[7]_i_2_n_0\
    );
\ixMem_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => ixMem,
      D => \ixMem[0]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmem_reg[7]_0\(0)
    );
\ixMem_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => ixMem,
      D => \ixMem[1]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmem_reg[7]_0\(1)
    );
\ixMem_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => ixMem,
      D => \ixMem[2]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmem_reg[7]_0\(2)
    );
\ixMem_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => ixMem,
      D => \ixMem[3]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmem_reg[7]_0\(3)
    );
\ixMem_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => ixMem,
      D => \ixMem[4]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmem_reg[7]_0\(4)
    );
\ixMem_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => ixMem,
      D => \ixMem[5]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmem_reg[7]_0\(5)
    );
\ixMem_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => ixMem,
      D => \ixMem[6]_i_1_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmem_reg[7]_0\(6)
    );
\ixMem_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => ixMem,
      D => \ixMem[7]_i_2_n_0\,
      PRE => \dwrRowbuf_reg[0]_0\(0),
      Q => \^ixmem_reg[7]_0\(7)
    );
\ixRdEgrfifo[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1F10"
    )
        port map (
      I0 => ixRdEgrfifo(0),
      I1 => ixRdEgrfifo(1),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      O => \ixRdEgrfifo[0]_i_1_n_0\
    );
\ixRdEgrfifo[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"020F000F0200000F"
    )
        port map (
      I0 => ddrAXI_wready,
      I1 => ddrAXI_wdata_0_sn_1,
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I5 => p_0_in,
      O => \ixRdEgrfifo[1]_i_1_n_0\
    );
\ixRdEgrfifo[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I1 => ixRdEgrfifo(1),
      I2 => ixRdEgrfifo(0),
      O => \ixRdEgrfifo[1]_i_2_n_0\
    );
\ixRdEgrfifo_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ixRdEgrfifo[1]_i_1_n_0\,
      CLR => AR(0),
      D => \ixRdEgrfifo[0]_i_1_n_0\,
      Q => ixRdEgrfifo(0)
    );
\ixRdEgrfifo_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ixRdEgrfifo[1]_i_1_n_0\,
      CLR => AR(0),
      D => \ixRdEgrfifo[1]_i_2_n_0\,
      Q => ixRdEgrfifo(1)
    );
\ixWrEgrfifo[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"111111110F000000"
    )
        port map (
      I0 => ixWrEgrfifo(0),
      I1 => ixWrEgrfifo(1),
      I2 => p_0_in,
      I3 => \i_reg[0]__0_n_0\,
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I5 => \wordEgrWr[3]_i_4_n_0\,
      O => \ixWrEgrfifo[0]_i_1_n_0\
    );
\ixWrEgrfifo[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AA00FCFF"
    )
        port map (
      I0 => enRowbufBEgrstrm1,
      I1 => p_0_in,
      I2 => \i_reg[0]__0_n_0\,
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I5 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      O => \ixWrEgrfifo[1]_i_1_n_0\
    );
\ixWrEgrfifo[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22F0220022F022F0"
    )
        port map (
      I0 => ixWrEgrfifo(0),
      I1 => ixWrEgrfifo(1),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I3 => \wordEgrWr[3]_i_4_n_0\,
      I4 => p_0_in,
      I5 => \i_reg[0]__0_n_0\,
      O => \ixWrEgrfifo[1]_i_2_n_0\
    );
\ixWrEgrfifo_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ixWrEgrfifo[1]_i_1_n_0\,
      CLR => AR(0),
      D => \ixWrEgrfifo[0]_i_1_n_0\,
      Q => ixWrEgrfifo(0)
    );
\ixWrEgrfifo_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ixWrEgrfifo[1]_i_1_n_0\,
      CLR => AR(0),
      D => \ixWrEgrfifo[1]_i_2_n_0\,
      Q => ixWrEgrfifo(1)
    );
\liveBNotA_i[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9F"
    )
        port map (
      I0 => liveBNotA_reg_n_0,
      I1 => liveBNotA_to_memclk_reg_n_0,
      I2 => liveBNotA_i,
      O => \liveBNotA_i[0]_i_1_n_0\
    );
liveBNotA_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28002880"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => liveBNotA_reg_n_0,
      I4 => \stateStream_reg[1]_0\,
      O => liveBNotA_i_1_n_0
    );
\liveBNotA_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \liveBNotA_i[0]_i_1_n_0\,
      Q => liveBNotA_i
    );
liveBNotA_memclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => liveBNotA_to_memclkm2,
      I1 => liveBNotA_to_memclkm1,
      I2 => liveBNotA_memclk,
      O => liveBNotA_memclk_i_1_n_0
    );
liveBNotA_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => liveBNotA_memclk_i_1_n_0,
      Q => liveBNotA_memclk
    );
liveBNotA_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => liveBNotA_i_1_n_0,
      Q => liveBNotA_reg_n_0
    );
liveBNotA_to_memclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => liveBNotA_i,
      I1 => liveBNotA_to_memclk_reg_n_0,
      I2 => liveBNotA_reg_n_0,
      O => liveBNotA_to_memclk_i_1_n_0
    );
liveBNotA_to_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => liveBNotA_to_memclk_i_1_n_0,
      Q => liveBNotA_to_memclk_reg_n_0
    );
liveBNotA_to_memclkm1_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => liveBNotA_to_memclk_reg_n_0,
      Q => liveBNotA_to_memclkm1
    );
liveBNotA_to_memclkm2_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => liveBNotA_to_memclkm1,
      Q => liveBNotA_to_memclkm2
    );
myRowAbuf: entity work.\design_1_Vsp_core_0_0_Dpbram_size8kB_a32b128__xdcDup__1\
     port map (
      D(6) => myRowAbuf_n_30,
      D(5) => myRowAbuf_n_31,
      D(4) => myRowAbuf_n_32,
      D(3) => myRowAbuf_n_33,
      D(2) => myRowAbuf_n_34,
      D(1) => myRowAbuf_n_35,
      D(0) => myRowAbuf_n_36,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ => myRowAbuf_n_38,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ => myRowAbuf_n_39,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ => myRowAbuf_n_40,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_10\ => myRowAbuf_n_49,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_11\ => myRowAbuf_n_50,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\ => myRowAbuf_n_51,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_13\ => myRowAbuf_n_52,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\ => myRowAbuf_n_53,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_15\ => myRowAbuf_n_54,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_16\ => myRowAbuf_n_55,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_17\ => myRowAbuf_n_56,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_18\ => myRowAbuf_n_57,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_19\ => myRowAbuf_n_58,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ => myRowAbuf_n_41,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_20\ => myRowAbuf_n_59,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_21\(127 downto 0) => \egrfifo[2]_44\(127 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_22\(3 downto 0) => \^stateswap_reg[3]_0\(3 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_23\ => liveBNotA_reg_n_0,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_24\(1 downto 0) => stateStockrls(1 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_25\ => enRowbufStream_reg_n_0,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_26\(10 downto 0) => aRowbufStockrls(10 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_27\(10 downto 0) => \aRowbufStream__0\(10 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_28\(1) => stateIgrstr(1),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_28\(0) => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ => myRowAbuf_n_42,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\ => myRowAbuf_n_43,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_5\ => myRowAbuf_n_44,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_6\ => myRowAbuf_n_45,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\ => myRowAbuf_n_46,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\ => myRowAbuf_n_47,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_9\ => myRowAbuf_n_48,
      Q(31 downto 0) => dwrRowbuf(31 downto 0),
      aclk_sig => aclk_sig,
      addrb(8 downto 0) => aB(8 downto 0),
      ddrAXI_rdata(127 downto 0) => ddrAXI_rdata(127 downto 0),
      douta(29 downto 16) => drdA(31 downto 18),
      douta(15 downto 7) => drdA(16 downto 8),
      douta(6 downto 0) => drdA(6 downto 0),
      doutb(127 downto 0) => drdRowBbufB(127 downto 0),
      \dwrRowbuf_reg[0]\ => \dwrRowbuf_reg[0]_1\,
      \dwrRowbuf_reg[0]_0\ => \dwrRowbuf[30]_i_3_n_0\,
      \dwrRowbuf_reg[1]\ => \dwrRowbuf[1]_i_2_n_0\,
      \dwrRowbuf_reg[1]_0\ => myRowBbuf_n_191,
      \dwrRowbuf_reg[1]_1\ => \a0[4]_i_4_n_0\,
      \dwrRowbuf_reg[30]\(27 downto 24) => drdRowBbuf(30 downto 27),
      \dwrRowbuf_reg[30]\(23 downto 22) => drdRowBbuf(25 downto 24),
      \dwrRowbuf_reg[30]\(21 downto 15) => drdRowBbuf(22 downto 16),
      \dwrRowbuf_reg[30]\(14 downto 0) => drdRowBbuf(14 downto 0),
      \dwrRowbuf_reg[3]\ => \dwrRowbuf[2]_i_2_n_0\,
      \dwrRowbuf_reg[3]_0\ => myRowBbuf_n_192,
      \dwrRowbuf_reg[4]\ => myRowBbuf_n_195,
      \dwrRowbuf_reg[6]\ => myRowBbuf_n_194,
      \dwrRowbuf_reg[7]\ => myRowBbuf_n_193,
      \egrfifo_reg[0][0]\ => \egrfifo[2][127]_i_4_n_0\,
      \egrfifo_reg[0][0]_0\ => \egrfifo[2][127]_i_5_n_0\,
      enRowbufBEgrstr => enRowbufBEgrstr,
      liveBNotA_memclk => liveBNotA_memclk,
      memclk => memclk,
      \stateSwap_reg[0]\ => myRowAbuf_n_37,
      \stateSwap_reg[2]\ => myRowAbuf_n_60,
      web(0) => \^web\(0)
    );
myRowBbuf: entity work.design_1_Vsp_core_0_0_Dpbram_size8kB_a32b128
     port map (
      D(24) => myRowBbuf_n_166,
      D(23) => myRowBbuf_n_167,
      D(22) => myRowBbuf_n_168,
      D(21) => myRowBbuf_n_169,
      D(20) => myRowBbuf_n_170,
      D(19) => myRowBbuf_n_171,
      D(18) => myRowBbuf_n_172,
      D(17) => myRowBbuf_n_173,
      D(16) => myRowBbuf_n_174,
      D(15) => myRowBbuf_n_175,
      D(14) => myRowBbuf_n_176,
      D(13) => myRowBbuf_n_177,
      D(12) => myRowBbuf_n_178,
      D(11) => myRowBbuf_n_179,
      D(10) => myRowBbuf_n_180,
      D(9) => myRowBbuf_n_181,
      D(8) => myRowBbuf_n_182,
      D(7) => myRowBbuf_n_183,
      D(6) => myRowBbuf_n_184,
      D(5) => myRowBbuf_n_185,
      D(4) => myRowBbuf_n_186,
      D(3) => myRowBbuf_n_187,
      D(2) => myRowBbuf_n_188,
      D(1) => myRowBbuf_n_189,
      D(0) => myRowBbuf_n_190,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ => myRowBbuf_n_191,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ => myRowBbuf_n_192,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ => myRowBbuf_n_193,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_10\ => myRowAbuf_n_60,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_11\(1) => stateIgrstr(1),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_11\(0) => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(8) => \aRowbufBIgrstr_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(7) => \aRowbufBIgrstr_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(6) => \aRowbufBIgrstr_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(5) => \aRowbufBIgrstr_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(4) => \aRowbufBIgrstr_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(3) => \aRowbufBIgrstr_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(2) => \aRowbufBIgrstr_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(1) => \aRowbufBIgrstr_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_12\(0) => \aRowbufBIgrstr_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_13\(8 downto 0) => aRowbufBEgrstr(8 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_14\(3 downto 0) => \^stateswap_reg[3]_0\(3 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ => myRowBbuf_n_194,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ => myRowBbuf_n_195,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\ => liveBNotA_reg_n_0,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_5\ => enRowbufStream_reg_n_0,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_6\(1 downto 0) => stateStockrls(1 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_7\(10 downto 0) => \aRowbufStream__0\(10 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_8\(10 downto 0) => aRowbufStockrls(10 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_9\ => myRowAbuf_n_37,
      Q(31 downto 0) => dwrRowbuf(31 downto 0),
      aclk_sig => aclk_sig,
      addrb(8 downto 0) => aB(8 downto 0),
      ddrAXI_rdata(127 downto 0) => ddrAXI_rdata(127 downto 0),
      douta(27 downto 24) => drdRowBbuf(30 downto 27),
      douta(23 downto 22) => drdRowBbuf(25 downto 24),
      douta(21 downto 15) => drdRowBbuf(22 downto 16),
      douta(14 downto 0) => drdRowBbuf(14 downto 0),
      doutb(127 downto 0) => drdRowBbufB(127 downto 0),
      \dwrRowbuf_reg[10]\ => \dwrRowbuf[11]_i_2_n_0\,
      \dwrRowbuf_reg[10]_0\ => myRowAbuf_n_47,
      \dwrRowbuf_reg[11]\ => \dwrRowbuf[12]_i_2_n_0\,
      \dwrRowbuf_reg[11]_0\ => myRowAbuf_n_48,
      \dwrRowbuf_reg[12]\ => \dwrRowbuf[13]_i_2_n_0\,
      \dwrRowbuf_reg[12]_0\ => myRowAbuf_n_46,
      \dwrRowbuf_reg[13]\ => \dwrRowbuf[14]_i_2_n_0\,
      \dwrRowbuf_reg[13]_0\ => myRowAbuf_n_50,
      \dwrRowbuf_reg[14]\ => \dwrRowbuf[14]_i_3_n_0\,
      \dwrRowbuf_reg[14]_0\ => myRowAbuf_n_52,
      \dwrRowbuf_reg[15]\ => \dwrRowbuf[15]_i_2_n_0\,
      \dwrRowbuf_reg[16]\ => \dwrRowbuf[17]_i_2_n_0\,
      \dwrRowbuf_reg[16]_0\ => \dwrRowbuf[16]_i_2_n_0\,
      \dwrRowbuf_reg[16]_1\ => myRowAbuf_n_45,
      \dwrRowbuf_reg[17]\ => \dwrRowbuf[18]_i_2_n_0\,
      \dwrRowbuf_reg[17]_0\ => myRowAbuf_n_44,
      \dwrRowbuf_reg[18]\ => \dwrRowbuf[19]_i_2_n_0\,
      \dwrRowbuf_reg[18]_0\ => myRowAbuf_n_42,
      \dwrRowbuf_reg[19]\ => \dwrRowbuf[20]_i_2_n_0\,
      \dwrRowbuf_reg[19]_0\ => myRowAbuf_n_43,
      \dwrRowbuf_reg[20]\ => \dwrRowbuf[21]_i_2_n_0\,
      \dwrRowbuf_reg[20]_0\ => myRowAbuf_n_40,
      \dwrRowbuf_reg[21]\ => \dwrRowbuf[22]_i_2_n_0\,
      \dwrRowbuf_reg[21]_0\ => myRowAbuf_n_39,
      \dwrRowbuf_reg[22]\ => \dwrRowbuf[22]_i_3_n_0\,
      \dwrRowbuf_reg[22]_0\ => myRowAbuf_n_41,
      \dwrRowbuf_reg[23]\ => \dwrRowbuf[23]_i_2_n_0\,
      \dwrRowbuf_reg[24]\ => \dwrRowbuf[25]_i_3_n_0\,
      \dwrRowbuf_reg[24]_0\ => \dwrRowbuf[24]_i_2_n_0\,
      \dwrRowbuf_reg[24]_1\ => myRowAbuf_n_56,
      \dwrRowbuf_reg[25]\ => \dwrRowbuf[25]_i_2_n_0\,
      \dwrRowbuf_reg[25]_0\ => myRowAbuf_n_58,
      \dwrRowbuf_reg[26]\ => \dwrRowbuf[26]_i_2_n_0\,
      \dwrRowbuf_reg[27]\ => \dwrRowbuf[27]_i_2_n_0\,
      \dwrRowbuf_reg[27]_0\ => \dwrRowbuf[28]_i_2_n_0\,
      \dwrRowbuf_reg[27]_1\ => myRowAbuf_n_53,
      \dwrRowbuf_reg[28]\ => \dwrRowbuf[29]_i_2_n_0\,
      \dwrRowbuf_reg[28]_0\ => myRowAbuf_n_57,
      \dwrRowbuf_reg[29]\ => \dwrRowbuf[30]_i_2_n_0\,
      \dwrRowbuf_reg[29]_0\ => myRowAbuf_n_55,
      \dwrRowbuf_reg[2]\ => \dwrRowbuf[2]_i_2_n_0\,
      \dwrRowbuf_reg[2]_0\ => myRowAbuf_n_38,
      \dwrRowbuf_reg[2]_1\ => myRowAbuf_n_59,
      \dwrRowbuf_reg[30]\ => \dwrRowbuf[30]_i_4_n_0\,
      \dwrRowbuf_reg[30]_0\ => myRowAbuf_n_54,
      \dwrRowbuf_reg[31]\(29 downto 16) => drdA(31 downto 18),
      \dwrRowbuf_reg[31]\(15 downto 7) => drdA(16 downto 8),
      \dwrRowbuf_reg[31]\(6 downto 0) => drdA(6 downto 0),
      \dwrRowbuf_reg[31]_0\ => \dwrRowbuf[31]_i_3_n_0\,
      \dwrRowbuf_reg[8]\ => \dwrRowbuf[8]_i_2_n_0\,
      \dwrRowbuf_reg[8]_0\ => myRowAbuf_n_49,
      \dwrRowbuf_reg[9]\ => \dwrRowbuf[9]_i_2_n_0\,
      \dwrRowbuf_reg[9]_0\ => \dwrRowbuf[30]_i_3_n_0\,
      \dwrRowbuf_reg[9]_1\ => \dwrRowbuf[10]_i_2_n_0\,
      \dwrRowbuf_reg[9]_2\ => myRowAbuf_n_51,
      \dwrRowbuf_reg[9]_3\ => \a0[4]_i_4_n_0\,
      \dwrRowbuf_reg[9]_4\ => \dwrRowbuf_reg[0]_1\,
      enRowbufBEgrstr => enRowbufBEgrstr,
      liveBNotA_memclk => liveBNotA_memclk,
      memclk => memclk,
      web(0) => \^web\(0)
    );
\probe[2]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(2),
      I1 => \^stateswap_reg[3]_0\(1),
      I2 => \^stateswap_reg[3]_0\(3),
      I3 => \^stateswap_reg[3]_0\(0),
      O => probe(0)
    );
\rdid[1][0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => ddrAXI_rvalid,
      I1 => ddrAXI_rready_0,
      I2 => ddrAXI_rlast,
      I3 => stateIgrstr(1),
      I4 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      O => ddrAXI_rvalid_0
    );
\rgbFromVideoinAXIS_tdatam1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(0),
      Q => rgbFromVideoinAXIS_tdatam1(0)
    );
\rgbFromVideoinAXIS_tdatam1_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(10),
      Q => rgbFromVideoinAXIS_tdatam1(10)
    );
\rgbFromVideoinAXIS_tdatam1_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(11),
      Q => rgbFromVideoinAXIS_tdatam1(11)
    );
\rgbFromVideoinAXIS_tdatam1_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(12),
      Q => rgbFromVideoinAXIS_tdatam1(12)
    );
\rgbFromVideoinAXIS_tdatam1_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(13),
      Q => rgbFromVideoinAXIS_tdatam1(13)
    );
\rgbFromVideoinAXIS_tdatam1_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(14),
      Q => rgbFromVideoinAXIS_tdatam1(14)
    );
\rgbFromVideoinAXIS_tdatam1_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(15),
      Q => rgbFromVideoinAXIS_tdatam1(15)
    );
\rgbFromVideoinAXIS_tdatam1_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(16),
      Q => rgbFromVideoinAXIS_tdatam1(16)
    );
\rgbFromVideoinAXIS_tdatam1_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(17),
      Q => rgbFromVideoinAXIS_tdatam1(17)
    );
\rgbFromVideoinAXIS_tdatam1_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(18),
      Q => rgbFromVideoinAXIS_tdatam1(18)
    );
\rgbFromVideoinAXIS_tdatam1_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(19),
      Q => rgbFromVideoinAXIS_tdatam1(19)
    );
\rgbFromVideoinAXIS_tdatam1_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(1),
      Q => rgbFromVideoinAXIS_tdatam1(1)
    );
\rgbFromVideoinAXIS_tdatam1_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(20),
      Q => rgbFromVideoinAXIS_tdatam1(20)
    );
\rgbFromVideoinAXIS_tdatam1_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(21),
      Q => rgbFromVideoinAXIS_tdatam1(21)
    );
\rgbFromVideoinAXIS_tdatam1_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(22),
      Q => rgbFromVideoinAXIS_tdatam1(22)
    );
\rgbFromVideoinAXIS_tdatam1_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(23),
      Q => rgbFromVideoinAXIS_tdatam1(23)
    );
\rgbFromVideoinAXIS_tdatam1_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(24),
      Q => rgbFromVideoinAXIS_tdatam1(24)
    );
\rgbFromVideoinAXIS_tdatam1_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(25),
      Q => rgbFromVideoinAXIS_tdatam1(25)
    );
\rgbFromVideoinAXIS_tdatam1_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(26),
      Q => rgbFromVideoinAXIS_tdatam1(26)
    );
\rgbFromVideoinAXIS_tdatam1_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(27),
      Q => rgbFromVideoinAXIS_tdatam1(27)
    );
\rgbFromVideoinAXIS_tdatam1_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(28),
      Q => rgbFromVideoinAXIS_tdatam1(28)
    );
\rgbFromVideoinAXIS_tdatam1_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(29),
      Q => rgbFromVideoinAXIS_tdatam1(29)
    );
\rgbFromVideoinAXIS_tdatam1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(2),
      Q => rgbFromVideoinAXIS_tdatam1(2)
    );
\rgbFromVideoinAXIS_tdatam1_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(30),
      Q => rgbFromVideoinAXIS_tdatam1(30)
    );
\rgbFromVideoinAXIS_tdatam1_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(31),
      Q => rgbFromVideoinAXIS_tdatam1(31)
    );
\rgbFromVideoinAXIS_tdatam1_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(32),
      Q => rgbFromVideoinAXIS_tdatam1(32)
    );
\rgbFromVideoinAXIS_tdatam1_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(33),
      Q => rgbFromVideoinAXIS_tdatam1(33)
    );
\rgbFromVideoinAXIS_tdatam1_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(34),
      Q => rgbFromVideoinAXIS_tdatam1(34)
    );
\rgbFromVideoinAXIS_tdatam1_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(35),
      Q => rgbFromVideoinAXIS_tdatam1(35)
    );
\rgbFromVideoinAXIS_tdatam1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(3),
      Q => rgbFromVideoinAXIS_tdatam1(3)
    );
\rgbFromVideoinAXIS_tdatam1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(4),
      Q => rgbFromVideoinAXIS_tdatam1(4)
    );
\rgbFromVideoinAXIS_tdatam1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(5),
      Q => rgbFromVideoinAXIS_tdatam1(5)
    );
\rgbFromVideoinAXIS_tdatam1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(6),
      Q => rgbFromVideoinAXIS_tdatam1(6)
    );
\rgbFromVideoinAXIS_tdatam1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(7),
      Q => rgbFromVideoinAXIS_tdatam1(7)
    );
\rgbFromVideoinAXIS_tdatam1_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(8),
      Q => rgbFromVideoinAXIS_tdatam1(8)
    );
\rgbFromVideoinAXIS_tdatam1_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(9),
      Q => rgbFromVideoinAXIS_tdatam1(9)
    );
\rgbFromVideoinAXIS_tdatam2_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(0),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[0]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(10),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[10]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(11),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[11]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(12),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[12]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(13),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[13]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(14),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[14]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(15),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[15]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(16),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[16]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(17),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[17]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(18),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[18]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(19),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[19]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(1),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[1]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(20),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[20]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(21),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[21]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(22),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[22]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(23),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[23]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(24),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[24]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(25),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[25]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(26),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[26]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(27),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[27]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(28),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[28]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(29),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[29]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(2),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[2]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(30),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[30]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(31),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[31]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(32),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[32]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(33),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[33]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(34),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[34]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(35),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[35]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(3),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[3]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(4),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[4]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(5),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[5]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(6),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[6]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(7),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[7]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(8),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[8]\
    );
\rgbFromVideoinAXIS_tdatam2_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tdatam1(9),
      Q => \rgbFromVideoinAXIS_tdatam2_reg_n_0_[9]\
    );
\rgbFromVideoinAXIS_tlast_sig_i[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9F"
    )
        port map (
      I0 => rgbFromVideoinAXIS_tlast_sig_to_memclk_reg_0,
      I1 => rgbFromVideoinAXIS_tlast_sig_to_memclk_reg_n_0,
      I2 => rgbFromVideoinAXIS_tlast_sig_i,
      O => \rgbFromVideoinAXIS_tlast_sig_i[0]_i_1_n_0\
    );
\rgbFromVideoinAXIS_tlast_sig_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rgbFromVideoinAXIS_tlast_sig_i[0]_i_1_n_0\,
      Q => rgbFromVideoinAXIS_tlast_sig_i
    );
rgbFromVideoinAXIS_tlast_sig_memclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => rgbFromVideoinAXIS_tlast_sig_to_memclkm2,
      I1 => rgbFromVideoinAXIS_tlast_sig_to_memclkm1,
      I2 => rgbFromVideoinAXIS_tlast_sig_memclk,
      O => rgbFromVideoinAXIS_tlast_sig_memclk_i_1_n_0
    );
rgbFromVideoinAXIS_tlast_sig_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => rgbFromVideoinAXIS_tlast_sig_memclk_i_1_n_0,
      Q => rgbFromVideoinAXIS_tlast_sig_memclk
    );
rgbFromVideoinAXIS_tlast_sig_to_memclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => rgbFromVideoinAXIS_tlast_sig_i,
      I1 => rgbFromVideoinAXIS_tlast_sig_to_memclk_reg_n_0,
      I2 => rgbFromVideoinAXIS_tlast_sig_to_memclk_reg_0,
      O => rgbFromVideoinAXIS_tlast_sig_to_memclk_i_1_n_0
    );
rgbFromVideoinAXIS_tlast_sig_to_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tlast_sig_to_memclk_i_1_n_0,
      Q => rgbFromVideoinAXIS_tlast_sig_to_memclk_reg_n_0
    );
rgbFromVideoinAXIS_tlast_sig_to_memclkm1_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => rgbFromVideoinAXIS_tlast_sig_to_memclk_reg_n_0,
      Q => rgbFromVideoinAXIS_tlast_sig_to_memclkm1
    );
rgbFromVideoinAXIS_tlast_sig_to_memclkm2_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => rgbFromVideoinAXIS_tlast_sig_to_memclkm1,
      Q => rgbFromVideoinAXIS_tlast_sig_to_memclkm2
    );
rgbFromVideoinAXIS_tvalidm1_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbVideoinToManyAXIS_tvalid,
      Q => rgbFromVideoinAXIS_tvalidm1
    );
rgbFromVideoinAXIS_tvalidm2_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rgbFromVideoinAXIS_tvalidm1,
      Q => rgbFromVideoinAXIS_tvalidm2
    );
\rng_i[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9F"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => rng_to_memclk_reg_n_0,
      I2 => rng_i,
      O => \rng_i[0]_i_1_n_0\
    );
\rng_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \rng_i[0]_i_1_n_0\,
      Q => rng_i
    );
rng_memclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => rng_to_memclkm2,
      I1 => rng_to_memclkm1,
      I2 => rng_memclk,
      O => rng_memclk_i_1_n_0
    );
rng_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => rng_memclk_i_1_n_0,
      Q => rng_memclk
    );
rng_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rng_reg_1,
      Q => \^rng_reg_0\
    );
rng_to_memclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => rng_i,
      I1 => rng_to_memclk_reg_n_0,
      I2 => \^rng_reg_0\,
      O => rng_to_memclk_i_1_n_0
    );
rng_to_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => rng_to_memclk_i_1_n_0,
      Q => rng_to_memclk_reg_n_0
    );
rng_to_memclkm1_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => rng_to_memclk_reg_n_0,
      Q => rng_to_memclkm1
    );
rng_to_memclkm2_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => rng_to_memclkm1,
      Q => rng_to_memclkm2
    );
\row_lcl[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^row_lcl_reg[10]_0\(0),
      O => \row_lcl[0]_i_1__0_n_0\
    );
\row_lcl[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01000000"
    )
        port map (
      I0 => AR(0),
      I1 => \row_lcl[10]_i_4_n_0\,
      I2 => \i_reg_n_0_[0]\,
      I3 => \i_reg_n_0_[1]\,
      I4 => rng_memclk,
      O => clear
    );
\row_lcl[10]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => AR(0),
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => rng_memclk,
      I3 => \row_lcl[10]_i_5_n_0\,
      O => sel
    );
\row_lcl[10]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \row_lcl[10]_i_6_n_0\,
      I1 => \^row_lcl_reg[10]_0\(6),
      I2 => \^row_lcl_reg[10]_0\(9),
      I3 => \^row_lcl_reg[10]_0\(8),
      I4 => \^row_lcl_reg[10]_0\(7),
      I5 => \^row_lcl_reg[10]_0\(10),
      O => \row_lcl[10]_i_3__0_n_0\
    );
\row_lcl[10]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(0),
      I1 => \^stateswap_reg[3]_0\(2),
      I2 => \^stateswap_reg[3]_0\(3),
      I3 => \^stateswap_reg[3]_0\(1),
      O => \row_lcl[10]_i_4_n_0\
    );
\row_lcl[10]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01000000"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(1),
      I1 => \^stateswap_reg[3]_0\(0),
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => stateIgrstr(1),
      I4 => \^fsm_sequential_stateigrstr_reg[0]_0\(0),
      O => \row_lcl[10]_i_5_n_0\
    );
\row_lcl[10]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^row_lcl_reg[10]_0\(4),
      I1 => \^row_lcl_reg[10]_0\(2),
      I2 => \^row_lcl_reg[10]_0\(0),
      I3 => \^row_lcl_reg[10]_0\(1),
      I4 => \^row_lcl_reg[10]_0\(3),
      I5 => \^row_lcl_reg[10]_0\(5),
      O => \row_lcl[10]_i_6_n_0\
    );
\row_lcl[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^row_lcl_reg[10]_0\(0),
      I1 => \^row_lcl_reg[10]_0\(1),
      O => \row_lcl[1]_i_1__0_n_0\
    );
\row_lcl[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^row_lcl_reg[10]_0\(1),
      I1 => \^row_lcl_reg[10]_0\(0),
      I2 => \^row_lcl_reg[10]_0\(2),
      O => \row_lcl[2]_i_1__0_n_0\
    );
\row_lcl[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^row_lcl_reg[10]_0\(2),
      I1 => \^row_lcl_reg[10]_0\(0),
      I2 => \^row_lcl_reg[10]_0\(1),
      I3 => \^row_lcl_reg[10]_0\(3),
      O => \row_lcl[3]_i_1__0_n_0\
    );
\row_lcl[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^row_lcl_reg[10]_0\(3),
      I1 => \^row_lcl_reg[10]_0\(1),
      I2 => \^row_lcl_reg[10]_0\(0),
      I3 => \^row_lcl_reg[10]_0\(2),
      I4 => \^row_lcl_reg[10]_0\(4),
      O => \row_lcl[4]_i_1__0_n_0\
    );
\row_lcl[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^row_lcl_reg[10]_0\(4),
      I1 => \^row_lcl_reg[10]_0\(2),
      I2 => \^row_lcl_reg[10]_0\(0),
      I3 => \^row_lcl_reg[10]_0\(1),
      I4 => \^row_lcl_reg[10]_0\(3),
      I5 => \^row_lcl_reg[10]_0\(5),
      O => \row_lcl[5]_i_1__0_n_0\
    );
\row_lcl[6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \row_lcl[10]_i_6_n_0\,
      I1 => \^row_lcl_reg[10]_0\(6),
      O => \row_lcl[6]_i_1__0_n_0\
    );
\row_lcl[7]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \row_lcl[10]_i_6_n_0\,
      I1 => \^row_lcl_reg[10]_0\(6),
      I2 => \^row_lcl_reg[10]_0\(7),
      O => \row_lcl[7]_i_1__0_n_0\
    );
\row_lcl[8]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \row_lcl[10]_i_6_n_0\,
      I1 => \^row_lcl_reg[10]_0\(6),
      I2 => \^row_lcl_reg[10]_0\(7),
      I3 => \^row_lcl_reg[10]_0\(8),
      O => \row_lcl[8]_i_1__0_n_0\
    );
\row_lcl[9]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \row_lcl[10]_i_6_n_0\,
      I1 => \^row_lcl_reg[10]_0\(6),
      I2 => \^row_lcl_reg[10]_0\(7),
      I3 => \^row_lcl_reg[10]_0\(8),
      I4 => \^row_lcl_reg[10]_0\(9),
      O => \row_lcl[9]_i_1__0_n_0\
    );
\row_lcl_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => sel,
      D => \row_lcl[0]_i_1__0_n_0\,
      Q => \^row_lcl_reg[10]_0\(0),
      R => clear
    );
\row_lcl_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => sel,
      D => \row_lcl[10]_i_3__0_n_0\,
      Q => \^row_lcl_reg[10]_0\(10),
      R => clear
    );
\row_lcl_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => sel,
      D => \row_lcl[1]_i_1__0_n_0\,
      Q => \^row_lcl_reg[10]_0\(1),
      R => clear
    );
\row_lcl_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => sel,
      D => \row_lcl[2]_i_1__0_n_0\,
      Q => \^row_lcl_reg[10]_0\(2),
      R => clear
    );
\row_lcl_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => sel,
      D => \row_lcl[3]_i_1__0_n_0\,
      Q => \^row_lcl_reg[10]_0\(3),
      R => clear
    );
\row_lcl_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => sel,
      D => \row_lcl[4]_i_1__0_n_0\,
      Q => \^row_lcl_reg[10]_0\(4),
      R => clear
    );
\row_lcl_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => sel,
      D => \row_lcl[5]_i_1__0_n_0\,
      Q => \^row_lcl_reg[10]_0\(5),
      R => clear
    );
\row_lcl_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => sel,
      D => \row_lcl[6]_i_1__0_n_0\,
      Q => \^row_lcl_reg[10]_0\(6),
      R => clear
    );
\row_lcl_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => sel,
      D => \row_lcl[7]_i_1__0_n_0\,
      Q => \^row_lcl_reg[10]_0\(7),
      R => clear
    );
\row_lcl_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => sel,
      D => \row_lcl[8]_i_1__0_n_0\,
      Q => \^row_lcl_reg[10]_0\(8),
      R => clear
    );
\row_lcl_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => sel,
      D => \row_lcl[9]_i_1__0_n_0\,
      Q => \^row_lcl_reg[10]_0\(9),
      R => clear
    );
\stateOp_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F4FFF4F"
    )
        port map (
      I0 => reqInvAssign,
      I1 => \^ackinvhdrengassign\,
      I2 => \^stateop_reg_0\,
      I3 => \^ackinvhdrengset\,
      I4 => reqInvHdrengSet,
      O => stateOp
    );
stateOp_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stateOp,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => stateOp_reg_1,
      Q => \^stateop_reg_0\
    );
\stateStockrls[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"040C0400C4C0C4C0"
    )
        port map (
      I0 => rgbFromVideoinAXIS_tlast_sig_to_memclk_reg_0,
      I1 => \^rng_reg_0\,
      I2 => stateStockrls(1),
      I3 => stateStockrls(0),
      I4 => \dwrRowbuf_reg[0]_1\,
      I5 => \stateStream_reg[1]_0\,
      O => \stateStockrls[0]_i_1_n_0\
    );
\stateStockrls[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4FFF"
    )
        port map (
      I0 => stateStockrls(1),
      I1 => rgbVideoinToManyAXIS_tvalid,
      I2 => stateStockrls(0),
      I3 => \^rng_reg_0\,
      O => \stateStockrls[1]_i_1_n_0\
    );
\stateStockrls[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => stateStockrls(0),
      I2 => stateStockrls(1),
      I3 => rgbFromVideoinAXIS_tlast_sig_to_memclk_reg_0,
      O => \stateStockrls[1]_i_2_n_0\
    );
\stateStockrls_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateStockrls[1]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \stateStockrls[0]_i_1_n_0\,
      Q => stateStockrls(0)
    );
\stateStockrls_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateStockrls[1]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \stateStockrls[1]_i_2_n_0\,
      Q => stateStockrls(1)
    );
\stateStream[0]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF956A"
    )
        port map (
      I0 => col_lcl(2),
      I1 => col_lcl(1),
      I2 => col_lcl(0),
      I3 => \stateStream_reg[0]_1\(2),
      I4 => \stateStream[0]_i_12_n_0\,
      O => \stateStream[0]_i_10_n_0\
    );
\stateStream[0]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => col_lcl(2),
      I1 => col_lcl(1),
      I2 => col_lcl(0),
      O => \stateStream[0]_i_11_n_0\
    );
\stateStream[0]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F69FFFFF"
    )
        port map (
      I0 => col_lcl(1),
      I1 => \stateStream_reg[0]_1\(1),
      I2 => col_lcl(0),
      I3 => \stateStream_reg[0]_1\(0),
      I4 => rgbFromVideoinAXIS_tvalidm2,
      O => \stateStream[0]_i_12_n_0\
    );
\stateStream[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FF0037000700"
    )
        port map (
      I0 => \a0[4]_i_3_n_0\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^rng_reg_0\,
      I4 => \stateStream[0]_i_2__0_n_0\,
      I5 => \stateStream_reg[0]_0\,
      O => \stateStream[0]_i_1__0_n_0\
    );
\stateStream[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0006090009000009"
    )
        port map (
      I0 => col_lcl(10),
      I1 => \stateStream_reg[0]_1\(10),
      I2 => \stateStream[0]_i_4_n_0\,
      I3 => \stateStream_reg[0]_1\(9),
      I4 => \stateStream[0]_i_5_n_0\,
      I5 => col_lcl(9),
      O => \stateStream[0]_i_2__0_n_0\
    );
\stateStream[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF9F6FFF6FFFFF6"
    )
        port map (
      I0 => col_lcl(8),
      I1 => \stateStream_reg[0]_1\(8),
      I2 => \stateStream[0]_i_6_n_0\,
      I3 => \stateStream_reg[0]_1\(7),
      I4 => \stateStream[0]_i_7_n_0\,
      I5 => col_lcl(7),
      O => \stateStream[0]_i_4_n_0\
    );
\stateStream[0]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => col_lcl(8),
      I1 => col_lcl(6),
      I2 => \col_lcl[9]_i_2_n_0\,
      I3 => col_lcl(7),
      O => \stateStream[0]_i_5_n_0\
    );
\stateStream[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF9F6FFF6FFFFF6"
    )
        port map (
      I0 => col_lcl(6),
      I1 => \stateStream_reg[0]_1\(6),
      I2 => \stateStream[0]_i_8_n_0\,
      I3 => \stateStream_reg[0]_1\(5),
      I4 => \stateStream[0]_i_9_n_0\,
      I5 => col_lcl(5),
      O => \stateStream[0]_i_6_n_0\
    );
\stateStream[0]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => col_lcl(6),
      I1 => \col_lcl[9]_i_2_n_0\,
      O => \stateStream[0]_i_7_n_0\
    );
\stateStream[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF9F6FFF6FFFFF6"
    )
        port map (
      I0 => col_lcl(4),
      I1 => \stateStream_reg[0]_1\(4),
      I2 => \stateStream[0]_i_10_n_0\,
      I3 => \stateStream_reg[0]_1\(3),
      I4 => \stateStream[0]_i_11_n_0\,
      I5 => col_lcl(3),
      O => \stateStream[0]_i_8_n_0\
    );
\stateStream[0]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => col_lcl(4),
      I1 => col_lcl(2),
      I2 => col_lcl(1),
      I3 => col_lcl(0),
      I4 => col_lcl(3),
      O => \stateStream[0]_i_9_n_0\
    );
\stateStream[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFDFFFFF"
    )
        port map (
      I0 => \stateStream[1]_i_3_n_0\,
      I1 => \stateStream[1]_i_4_n_0\,
      I2 => \^rng_reg_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \stateStream[1]_i_1__0_n_0\
    );
\stateStream[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F838F8F800000000"
    )
        port map (
      I0 => \a0[4]_i_3_n_0\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \dwrRowbuf_reg[0]_1\,
      I4 => \stateStream_reg[1]_0\,
      I5 => \^rng_reg_0\,
      O => \stateStream[1]_i_2__0_n_0\
    );
\stateStream[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000FFFFFFFF"
    )
        port map (
      I0 => \stateStream[1]_i_5_n_0\,
      I1 => \ixMemNext_reg_n_0_[1]\,
      I2 => \ixMemNext_reg_n_0_[0]\,
      I3 => \ixMemNext_reg_n_0_[3]\,
      I4 => \ixMemNext_reg_n_0_[2]\,
      I5 => \tixVState_reg[7]_1\,
      O => \stateStream[1]_i_3_n_0\
    );
\stateStream[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000009009"
    )
        port map (
      I0 => \ixMemNext_reg_n_0_[6]\,
      I1 => \^ixmem_reg[7]_0\(6),
      I2 => \ixMemNext_reg_n_0_[7]\,
      I3 => \^ixmem_reg[7]_0\(7),
      I4 => \stateStream[1]_i_7_n_0\,
      I5 => \stateStream[1]_i_8_n_0\,
      O => \stateStream[1]_i_4_n_0\
    );
\stateStream[1]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \ixMemNext_reg_n_0_[6]\,
      I1 => \ixMemNext_reg_n_0_[7]\,
      I2 => \ixMemNext_reg_n_0_[5]\,
      I3 => \ixMemNext_reg_n_0_[4]\,
      O => \stateStream[1]_i_5_n_0\
    );
\stateStream[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \ixMemNext_reg_n_0_[1]\,
      I1 => \^ixmem_reg[7]_0\(1),
      I2 => \ixMemNext_reg_n_0_[2]\,
      I3 => \^ixmem_reg[7]_0\(2),
      I4 => \^ixmem_reg[7]_0\(0),
      I5 => \ixMemNext_reg_n_0_[0]\,
      O => \stateStream[1]_i_7_n_0\
    );
\stateStream[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \^ixmem_reg[7]_0\(3),
      I1 => \ixMemNext_reg_n_0_[3]\,
      I2 => \ixMemNext_reg_n_0_[4]\,
      I3 => \^ixmem_reg[7]_0\(4),
      I4 => \ixMemNext_reg_n_0_[5]\,
      I5 => \^ixmem_reg[7]_0\(5),
      O => \stateStream[1]_i_8_n_0\
    );
\stateStream_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateStream[1]_i_1__0_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \stateStream[0]_i_1__0_n_0\,
      Q => \^q\(0)
    );
\stateStream_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateStream[1]_i_1__0_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \stateStream[1]_i_2__0_n_0\,
      Q => \^q\(1)
    );
\stateSwap[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF4F444444"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(0),
      I1 => \stateSwap[2]_i_3_n_0\,
      I2 => ddrAXI_wlast_INST_0_i_2_n_0,
      I3 => \stateSwap[0]_i_2_n_0\,
      I4 => \stateSwap[3]_i_4_n_0\,
      I5 => \stateSwap[0]_i_3_n_0\,
      O => \stateSwap[0]_i_1_n_0\
    );
\stateSwap[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(2),
      I1 => rng_memclk,
      O => \stateSwap[0]_i_2_n_0\
    );
\stateSwap[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEFEEEFEFE"
    )
        port map (
      I0 => \stateSwap[0]_i_4_n_0\,
      I1 => \stateSwap[0]_i_5_n_0\,
      I2 => rng_memclk,
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[1]\,
      I5 => \row_lcl[10]_i_4_n_0\,
      O => \stateSwap[0]_i_3_n_0\
    );
\stateSwap[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(3),
      I1 => rng_memclk,
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => \^stateswap_reg[3]_0\(0),
      I4 => \^stateswap_reg[3]_0\(1),
      I5 => \stateSwap[1]_i_5_n_0\,
      O => \stateSwap[0]_i_4_n_0\
    );
\stateSwap[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1100100010001000"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(3),
      I1 => \^stateswap_reg[3]_0\(0),
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => rng_memclk,
      I4 => rgbFromVideoinAXIS_tlast_sig_memclk,
      I5 => vsync_sig_memclk,
      O => \stateSwap[0]_i_5_n_0\
    );
\stateSwap[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEEFEAAAA"
    )
        port map (
      I0 => \stateSwap[1]_i_2_n_0\,
      I1 => \stateSwap[3]_i_4_n_0\,
      I2 => \stateSwap_reg[2]_0\,
      I3 => \^stateswap_reg[3]_0\(1),
      I4 => \stateSwap[1]_i_3_n_0\,
      I5 => \stateSwap[1]_i_4_n_0\,
      O => \stateSwap[1]_i_1_n_0\
    );
\stateSwap[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAA10AA10001000"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(1),
      I1 => \^stateswap_reg[3]_0\(2),
      I2 => \stateSwap[2]_i_6_n_0\,
      I3 => \^stateswap_reg[3]_0\(0),
      I4 => \^stateswap_reg[3]_0\(3),
      I5 => rng_memclk,
      O => \stateSwap[1]_i_2_n_0\
    );
\stateSwap[1]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => rng_memclk,
      I1 => \^stateswap_reg[3]_0\(2),
      I2 => \^stateswap_reg[3]_0\(0),
      O => \stateSwap[1]_i_3_n_0\
    );
\stateSwap[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C800"
    )
        port map (
      I0 => \stateSwap[1]_i_5_n_0\,
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => rng_memclk,
      O => \stateSwap[1]_i_4_n_0\
    );
\stateSwap[1]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \row_lcl[10]_i_3__0_n_0\,
      I1 => \^row_lcl_reg[10]_0\(1),
      I2 => \^row_lcl_reg[10]_0\(0),
      I3 => \stateSwap[1]_i_6_n_0\,
      I4 => \stateSwap[1]_i_7_n_0\,
      O => \stateSwap[1]_i_5_n_0\
    );
\stateSwap[1]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFE"
    )
        port map (
      I0 => \row_lcl[10]_i_6_n_0\,
      I1 => \^row_lcl_reg[10]_0\(6),
      I2 => \^row_lcl_reg[10]_0\(7),
      I3 => \^row_lcl_reg[10]_0\(8),
      I4 => \^row_lcl_reg[10]_0\(9),
      O => \stateSwap[1]_i_6_n_0\
    );
\stateSwap[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFEEE"
    )
        port map (
      I0 => \^row_lcl_reg[10]_0\(4),
      I1 => \^row_lcl_reg[10]_0\(2),
      I2 => \^row_lcl_reg[10]_0\(0),
      I3 => \^row_lcl_reg[10]_0\(1),
      I4 => \^row_lcl_reg[10]_0\(3),
      I5 => \^row_lcl_reg[10]_0\(5),
      O => \stateSwap[1]_i_7_n_0\
    );
\stateSwap[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAEAFFAAEAEAAAAA"
    )
        port map (
      I0 => \stateSwap[2]_i_2_n_0\,
      I1 => \^stateswap_reg[3]_0\(0),
      I2 => \stateSwap[2]_i_3_n_0\,
      I3 => \stateSwap[2]_i_4_n_0\,
      I4 => \stateSwap[3]_i_4_n_0\,
      I5 => \stateSwap_reg[2]_0\,
      O => \stateSwap[2]_i_1_n_0\
    );
\stateSwap[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"003C002C00200020"
    )
        port map (
      I0 => \stateSwap[2]_i_6_n_0\,
      I1 => \^stateswap_reg[3]_0\(2),
      I2 => \^stateswap_reg[3]_0\(0),
      I3 => \^stateswap_reg[3]_0\(3),
      I4 => \^stateswap_reg[3]_0\(1),
      I5 => rng_memclk,
      O => \stateSwap[2]_i_2_n_0\
    );
\stateSwap[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(3),
      I1 => \^stateswap_reg[3]_0\(1),
      I2 => rng_memclk,
      O => \stateSwap[2]_i_3_n_0\
    );
\stateSwap[2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => rng_memclk,
      I1 => \^stateswap_reg[3]_0\(2),
      I2 => \^stateswap_reg[3]_0\(3),
      I3 => \^stateswap_reg[3]_0\(1),
      O => \stateSwap[2]_i_4_n_0\
    );
\stateSwap[2]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rng_memclk,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      O => \stateSwap[2]_i_6_n_0\
    );
\stateSwap[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABAAABAABFAABB"
    )
        port map (
      I0 => \stateSwap[3]_i_3_n_0\,
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^stateswap_reg[3]_0\(1),
      I3 => \^stateswap_reg[3]_0\(2),
      I4 => \^stateswap_reg[3]_0\(0),
      I5 => rgbFromVideoinAXIS_tlast_sig_memclk,
      O => \stateSwap[3]_i_1_n_0\
    );
\stateSwap[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000040000F000000"
    )
        port map (
      I0 => \stateSwap[3]_i_4_n_0\,
      I1 => \^stateswap_reg[3]_0\(0),
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => rng_memclk,
      I4 => \^stateswap_reg[3]_0\(3),
      I5 => \^stateswap_reg[3]_0\(1),
      O => \stateSwap[3]_i_2_n_0\
    );
\stateSwap[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEFEEEFFFFFFFF"
    )
        port map (
      I0 => \stateSwap[3]_i_5_n_0\,
      I1 => \row_lcl[10]_i_5_n_0\,
      I2 => \^stateswap_reg[3]_0\(0),
      I3 => \^stateswap_reg[3]_0\(1),
      I4 => \^stateswap_reg[3]_0\(3),
      I5 => rng_memclk,
      O => \stateSwap[3]_i_3_n_0\
    );
\stateSwap[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF7FFE"
    )
        port map (
      I0 => burstSwapLast(1),
      I1 => \^rdaaxi_araddr\(1),
      I2 => \^rdaaxi_araddr\(4),
      I3 => \^rdaaxi_araddr\(0),
      I4 => \^rdaaxi_araddr\(3),
      I5 => \^rdaaxi_araddr\(2),
      O => \stateSwap[3]_i_4_n_0\
    );
\stateSwap[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAEAAAAAA"
    )
        port map (
      I0 => \stateSwap[3]_i_6_n_0\,
      I1 => ddrAXI_arready,
      I2 => \stateSwap[3]_i_3_0\,
      I3 => \stateSwap[3]_i_3_1\(0),
      I4 => \^web\(0),
      I5 => \stateSwap[3]_i_7_n_0\,
      O => \stateSwap[3]_i_5_n_0\
    );
\stateSwap[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => ddrAXI_awready,
      I1 => ddrAXI_wdata_0_sn_1,
      I2 => \stateSwap[3]_i_5_0\(1),
      I3 => \^stateswap_reg[3]_0\(0),
      I4 => \^stateswap_reg[3]_0\(1),
      I5 => \^stateswap_reg[3]_0\(3),
      O => \stateSwap[3]_i_6_n_0\
    );
\stateSwap[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0300000088888888"
    )
        port map (
      I0 => \burstSwap[4]_i_4_n_0\,
      I1 => \^stateswap_reg[3]_0\(0),
      I2 => \^stateswap_reg[3]_0\(2),
      I3 => rgbFromVideoinAXIS_tlast_sig_memclk,
      I4 => \^stateswap_reg[3]_0\(1),
      I5 => \^stateswap_reg[3]_0\(3),
      O => \stateSwap[3]_i_7_n_0\
    );
\stateSwap_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \stateSwap[3]_i_1_n_0\,
      CLR => AR(0),
      D => \stateSwap[0]_i_1_n_0\,
      Q => \^stateswap_reg[3]_0\(0)
    );
\stateSwap_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \stateSwap[3]_i_1_n_0\,
      CLR => AR(0),
      D => \stateSwap[1]_i_1_n_0\,
      Q => \^stateswap_reg[3]_0\(1)
    );
\stateSwap_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \stateSwap[3]_i_1_n_0\,
      CLR => AR(0),
      D => \stateSwap[2]_i_1_n_0\,
      Q => \^stateswap_reg[3]_0\(2)
    );
\stateSwap_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \stateSwap[3]_i_1_n_0\,
      CLR => AR(0),
      D => \stateSwap[3]_i_2_n_0\,
      Q => \^stateswap_reg[3]_0\(3)
    );
\tixVState[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AB00"
    )
        port map (
      I0 => \a0[4]_i_3_n_0\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tixVState[0]_i_1_n_0\
    );
\tixVState[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5700"
    )
        port map (
      I0 => \a0[4]_i_3_n_0\,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tixVState[1]_i_1__1_n_0\
    );
\tixVState[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0D00FFFF"
    )
        port map (
      I0 => \stateStream[1]_i_3_n_0\,
      I1 => \stateStream[1]_i_4_n_0\,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^rng_reg_0\,
      O => \tixVState[7]_i_1_n_0\
    );
\tixVState[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^rng_reg_0\,
      O => \tixVState[7]_i_2_n_0\
    );
\tixVState_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tixVState[7]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tixVState[0]_i_1_n_0\,
      Q => \tixVState_reg[7]_0\(0)
    );
\tixVState_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tixVState[7]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tixVState[1]_i_1__1_n_0\,
      Q => \tixVState_reg[7]_0\(1)
    );
\tixVState_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \tixVState[7]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tixVState[7]_i_2_n_0\,
      Q => \tixVState_reg[7]_0\(2)
    );
\tkstAcq[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(0),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[0]_i_1_n_0\
    );
\tkstAcq[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(10),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[10]_i_1_n_0\
    );
\tkstAcq[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(11),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[11]_i_1_n_0\
    );
\tkstAcq[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(12),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[12]_i_1_n_0\
    );
\tkstAcq[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(13),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[13]_i_1_n_0\
    );
\tkstAcq[14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(14),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[14]_i_1_n_0\
    );
\tkstAcq[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(15),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[15]_i_1_n_0\
    );
\tkstAcq[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(16),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[16]_i_1_n_0\
    );
\tkstAcq[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(17),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[17]_i_1_n_0\
    );
\tkstAcq[18]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(18),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[18]_i_1_n_0\
    );
\tkstAcq[19]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(19),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[19]_i_1_n_0\
    );
\tkstAcq[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(1),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[1]_i_1_n_0\
    );
\tkstAcq[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(20),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[20]_i_1_n_0\
    );
\tkstAcq[21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(21),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[21]_i_1_n_0\
    );
\tkstAcq[22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(22),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[22]_i_1_n_0\
    );
\tkstAcq[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(23),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[23]_i_1_n_0\
    );
\tkstAcq[24]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(24),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[24]_i_1_n_0\
    );
\tkstAcq[25]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(25),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[25]_i_1_n_0\
    );
\tkstAcq[26]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(26),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[26]_i_1_n_0\
    );
\tkstAcq[27]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(27),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[27]_i_1_n_0\
    );
\tkstAcq[28]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(28),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[28]_i_1_n_0\
    );
\tkstAcq[29]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(29),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[29]_i_1_n_0\
    );
\tkstAcq[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[2]_i_1_n_0\
    );
\tkstAcq[30]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(30),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[30]_i_1_n_0\
    );
\tkstAcq[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(31),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[31]_i_1_n_0\
    );
\tkstAcq[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[3]_i_1_n_0\
    );
\tkstAcq[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(4),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[4]_i_1_n_0\
    );
\tkstAcq[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(5),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[5]_i_1_n_0\
    );
\tkstAcq[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(6),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[6]_i_1_n_0\
    );
\tkstAcq[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(7),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[7]_i_1_n_0\
    );
\tkstAcq[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(8),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[8]_i_1_n_0\
    );
\tkstAcq[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \tkstAcq_reg[31]_0\(9),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkstAcq[9]_i_1_n_0\
    );
\tkstAcq_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[0]_i_1_n_0\,
      Q => tkstAcq(0)
    );
\tkstAcq_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[10]_i_1_n_0\,
      Q => tkstAcq(10)
    );
\tkstAcq_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[11]_i_1_n_0\,
      Q => tkstAcq(11)
    );
\tkstAcq_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[12]_i_1_n_0\,
      Q => tkstAcq(12)
    );
\tkstAcq_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[13]_i_1_n_0\,
      Q => tkstAcq(13)
    );
\tkstAcq_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[14]_i_1_n_0\,
      Q => tkstAcq(14)
    );
\tkstAcq_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[15]_i_1_n_0\,
      Q => tkstAcq(15)
    );
\tkstAcq_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[16]_i_1_n_0\,
      Q => tkstAcq(16)
    );
\tkstAcq_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[17]_i_1_n_0\,
      Q => tkstAcq(17)
    );
\tkstAcq_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[18]_i_1_n_0\,
      Q => tkstAcq(18)
    );
\tkstAcq_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[19]_i_1_n_0\,
      Q => tkstAcq(19)
    );
\tkstAcq_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[1]_i_1_n_0\,
      Q => tkstAcq(1)
    );
\tkstAcq_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[20]_i_1_n_0\,
      Q => tkstAcq(20)
    );
\tkstAcq_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[21]_i_1_n_0\,
      Q => tkstAcq(21)
    );
\tkstAcq_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[22]_i_1_n_0\,
      Q => tkstAcq(22)
    );
\tkstAcq_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[23]_i_1_n_0\,
      Q => tkstAcq(23)
    );
\tkstAcq_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[24]_i_1_n_0\,
      Q => tkstAcq(24)
    );
\tkstAcq_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[25]_i_1_n_0\,
      Q => tkstAcq(25)
    );
\tkstAcq_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[26]_i_1_n_0\,
      Q => tkstAcq(26)
    );
\tkstAcq_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[27]_i_1_n_0\,
      Q => tkstAcq(27)
    );
\tkstAcq_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[28]_i_1_n_0\,
      Q => tkstAcq(28)
    );
\tkstAcq_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[29]_i_1_n_0\,
      Q => tkstAcq(29)
    );
\tkstAcq_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[2]_i_1_n_0\,
      Q => tkstAcq(2)
    );
\tkstAcq_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[30]_i_1_n_0\,
      Q => tkstAcq(30)
    );
\tkstAcq_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[31]_i_1_n_0\,
      Q => tkstAcq(31)
    );
\tkstAcq_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[3]_i_1_n_0\,
      Q => tkstAcq(3)
    );
\tkstAcq_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[4]_i_1_n_0\,
      Q => tkstAcq(4)
    );
\tkstAcq_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[5]_i_1_n_0\,
      Q => tkstAcq(5)
    );
\tkstAcq_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[6]_i_1_n_0\,
      Q => tkstAcq(6)
    );
\tkstAcq_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[7]_i_1_n_0\,
      Q => tkstAcq(7)
    );
\tkstAcq_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[8]_i_1_n_0\,
      Q => tkstAcq(8)
    );
\tkstAcq_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \a0[4]_i_1_n_0\,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkstAcq[9]_i_1_n_0\,
      Q => tkstAcq(9)
    );
\tkst[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(0),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[0]_i_1_n_0\
    );
\tkst[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(10),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[10]_i_1_n_0\
    );
\tkst[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(11),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[11]_i_1_n_0\
    );
\tkst[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(12),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[12]_i_1_n_0\
    );
\tkst[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(13),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[13]_i_1_n_0\
    );
\tkst[14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(14),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[14]_i_1_n_0\
    );
\tkst[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(15),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[15]_i_1_n_0\
    );
\tkst[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(16),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[16]_i_1_n_0\
    );
\tkst[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(17),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[17]_i_1_n_0\
    );
\tkst[18]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(18),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[18]_i_1_n_0\
    );
\tkst[19]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(19),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[19]_i_1_n_0\
    );
\tkst[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(1),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[1]_i_1_n_0\
    );
\tkst[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(20),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[20]_i_1_n_0\
    );
\tkst[21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(21),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[21]_i_1_n_0\
    );
\tkst[22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(22),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[22]_i_1_n_0\
    );
\tkst[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(23),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[23]_i_1_n_0\
    );
\tkst[24]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(24),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[24]_i_1_n_0\
    );
\tkst[25]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(25),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[25]_i_1_n_0\
    );
\tkst[26]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(26),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[26]_i_1_n_0\
    );
\tkst[27]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(27),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[27]_i_1_n_0\
    );
\tkst[28]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(28),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[28]_i_1_n_0\
    );
\tkst[29]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(29),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[29]_i_1_n_0\
    );
\tkst[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[2]_i_1_n_0\
    );
\tkst[30]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(30),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[30]_i_1_n_0\
    );
\tkst[31]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(31),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[31]_i_1__0_n_0\
    );
\tkst[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[3]_i_1_n_0\
    );
\tkst[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(4),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[4]_i_1_n_0\
    );
\tkst[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(5),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[5]_i_1_n_0\
    );
\tkst[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(6),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[6]_i_1_n_0\
    );
\tkst[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(7),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[7]_i_1_n_0\
    );
\tkst[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(8),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[8]_i_1_n_0\
    );
\tkst[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => tkstAcq(9),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^rng_reg_0\,
      O => \tkst[9]_i_1_n_0\
    );
\tkst_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[0]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(0)
    );
\tkst_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[10]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(10)
    );
\tkst_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[11]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(11)
    );
\tkst_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[12]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(12)
    );
\tkst_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[13]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(13)
    );
\tkst_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[14]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(14)
    );
\tkst_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[15]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(15)
    );
\tkst_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[16]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(16)
    );
\tkst_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[17]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(17)
    );
\tkst_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[18]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(18)
    );
\tkst_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[19]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(19)
    );
\tkst_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[1]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(1)
    );
\tkst_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[20]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(20)
    );
\tkst_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[21]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(21)
    );
\tkst_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[22]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(22)
    );
\tkst_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[23]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(23)
    );
\tkst_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[24]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(24)
    );
\tkst_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[25]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(25)
    );
\tkst_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[26]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(26)
    );
\tkst_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[27]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(27)
    );
\tkst_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[28]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(28)
    );
\tkst_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[29]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(29)
    );
\tkst_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[2]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(2)
    );
\tkst_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[30]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(30)
    );
\tkst_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[31]_i_1__0_n_0\,
      Q => \tkst_reg[31]_0\(31)
    );
\tkst_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[3]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(3)
    );
\tkst_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[4]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(4)
    );
\tkst_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[5]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(5)
    );
\tkst_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[6]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(6)
    );
\tkst_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[7]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(7)
    );
\tkst_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[8]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(8)
    );
\tkst_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => ixMem,
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \tkst[9]_i_1_n_0\,
      Q => \tkst_reg[31]_0\(9)
    );
\vsync_sig_i[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9F"
    )
        port map (
      I0 => \stateStream_reg[1]_0\,
      I1 => vsync_sig_to_memclk_reg_n_0,
      I2 => vsync_sig_i,
      O => \vsync_sig_i[0]_i_1_n_0\
    );
\vsync_sig_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => \vsync_sig_i[0]_i_1_n_0\,
      Q => vsync_sig_i
    );
vsync_sig_memclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => vsync_sig_to_memclkm2,
      I1 => vsync_sig_to_memclkm1,
      I2 => vsync_sig_memclk,
      O => vsync_sig_memclk_i_1_n_0
    );
vsync_sig_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => vsync_sig_memclk_i_1_n_0,
      Q => vsync_sig_memclk
    );
vsync_sig_to_memclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => vsync_sig_i,
      I1 => vsync_sig_to_memclk_reg_n_0,
      I2 => \stateStream_reg[1]_0\,
      O => vsync_sig_to_memclk_i_1_n_0
    );
vsync_sig_to_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \dwrRowbuf_reg[0]_0\(0),
      D => vsync_sig_to_memclk_i_1_n_0,
      Q => vsync_sig_to_memclk_reg_n_0
    );
vsync_sig_to_memclkm1_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => vsync_sig_to_memclk_reg_n_0,
      Q => vsync_sig_to_memclkm1
    );
vsync_sig_to_memclkm2_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => vsync_sig_to_memclkm1,
      Q => vsync_sig_to_memclkm2
    );
\wordEgrLast[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF000000400"
    )
        port map (
      I0 => ddrAXI_wlast_INST_0_i_2_n_0,
      I1 => \^stateswap_reg[3]_0\(2),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I5 => \wordEgrLast_reg_n_0_[2]\,
      O => \wordEgrLast[2]_i_1_n_0\
    );
\wordEgrLast_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \wordEgrLast[2]_i_1_n_0\,
      Q => \wordEgrLast_reg_n_0_[2]\
    );
\wordEgrRd[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00EA"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I3 => wordEgrRd(0),
      O => \wordEgrRd[0]_i_1_n_0\
    );
\wordEgrRd[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00EAEA00"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I3 => wordEgrRd(1),
      I4 => wordEgrRd(0),
      O => \wordEgrRd[1]_i_1_n_0\
    );
\wordEgrRd[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EAEA00EA00EA00"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I3 => wordEgrRd(2),
      I4 => wordEgrRd(0),
      I5 => wordEgrRd(1),
      O => \wordEgrRd[2]_i_1_n_0\
    );
\wordEgrRd[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCFCDCFCCCCCDCF"
    )
        port map (
      I0 => \wordEgrRd[3]_i_3_n_0\,
      I1 => \wordEgrRd[3]_i_4_n_0\,
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I5 => p_0_in,
      O => \wordEgrRd[3]_i_1_n_0\
    );
\wordEgrRd[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \wordEgrRd[3]_i_5_n_0\,
      I1 => wordEgrRd(3),
      I2 => wordEgrRd(2),
      I3 => wordEgrRd(1),
      I4 => wordEgrRd(0),
      O => \wordEgrRd[3]_i_2_n_0\
    );
\wordEgrRd[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(3),
      I1 => \^stateswap_reg[3]_0\(1),
      I2 => \^stateswap_reg[3]_0\(2),
      O => \wordEgrRd[3]_i_3_n_0\
    );
\wordEgrRd[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000004000000"
    )
        port map (
      I0 => \^egraxis_tlast\,
      I1 => ddrAXI_wready,
      I2 => ddrAXI_wdata_0_sn_1,
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I5 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      O => \wordEgrRd[3]_i_4_n_0\
    );
\wordEgrRd[3]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      O => \wordEgrRd[3]_i_5_n_0\
    );
\wordEgrRd_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \wordEgrRd[3]_i_1_n_0\,
      CLR => AR(0),
      D => \wordEgrRd[0]_i_1_n_0\,
      Q => wordEgrRd(0)
    );
\wordEgrRd_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \wordEgrRd[3]_i_1_n_0\,
      CLR => AR(0),
      D => \wordEgrRd[1]_i_1_n_0\,
      Q => wordEgrRd(1)
    );
\wordEgrRd_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \wordEgrRd[3]_i_1_n_0\,
      CLR => AR(0),
      D => \wordEgrRd[2]_i_1_n_0\,
      Q => wordEgrRd(2)
    );
\wordEgrRd_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \wordEgrRd[3]_i_1_n_0\,
      CLR => AR(0),
      D => \wordEgrRd[3]_i_2_n_0\,
      Q => wordEgrRd(3)
    );
\wordEgrWr[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5750"
    )
        port map (
      I0 => \wordEgrWr__0\(0),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      O => \wordEgrWr[0]_i_1_n_0\
    );
\wordEgrWr[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"666F6600"
    )
        port map (
      I0 => \wordEgrWr__0\(0),
      I1 => \wordEgrWr__0\(1),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      O => \wordEgrWr[1]_i_1_n_0\
    );
\wordEgrWr[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EAEA00EA00EA00"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I3 => \wordEgrWr__0\(2),
      I4 => \wordEgrWr__0\(0),
      I5 => \wordEgrWr__0\(1),
      O => \wordEgrWr[2]_i_1_n_0\
    );
\wordEgrWr[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAAEFAAEFAAEF"
    )
        port map (
      I0 => \wordEgrWr[3]_i_3_n_0\,
      I1 => p_0_in,
      I2 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      I3 => \wordEgrWr[3]_i_4_n_0\,
      I4 => \wordEgrWr[3]_i_5_n_0\,
      I5 => \wordEgrRd[3]_i_4_n_0\,
      O => \wordEgrWr[3]_i_1_n_0\
    );
\wordEgrWr[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \wordEgrRd[3]_i_5_n_0\,
      I1 => \wordEgrWr__0\(3),
      I2 => \wordEgrWr__0\(2),
      I3 => \wordEgrWr__0\(1),
      I4 => \wordEgrWr__0\(0),
      O => \wordEgrWr[3]_i_2_n_0\
    );
\wordEgrWr[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(2),
      I1 => \^stateswap_reg[3]_0\(1),
      I2 => \^stateswap_reg[3]_0\(3),
      I3 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      I4 => \^fsm_sequential_stateegrstr_reg[2]_0\(1),
      O => \wordEgrWr[3]_i_3_n_0\
    );
\wordEgrWr[3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^fsm_sequential_stateegrstr_reg[2]_0\(0),
      I1 => \^fsm_sequential_stateegrstr_reg[2]_0\(2),
      O => \wordEgrWr[3]_i_4_n_0\
    );
\wordEgrWr[3]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFE"
    )
        port map (
      I0 => \wordEgrWr__0\(0),
      I1 => \wordEgrWr__0\(3),
      I2 => \wordEgrLast_reg_n_0_[2]\,
      I3 => \wordEgrWr__0\(2),
      I4 => \wordEgrWr__0\(1),
      O => \wordEgrWr[3]_i_5_n_0\
    );
\wordEgrWr_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \wordEgrWr[3]_i_1_n_0\,
      CLR => AR(0),
      D => \wordEgrWr[0]_i_1_n_0\,
      Q => \wordEgrWr__0\(0)
    );
\wordEgrWr_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \wordEgrWr[3]_i_1_n_0\,
      CLR => AR(0),
      D => \wordEgrWr[1]_i_1_n_0\,
      Q => \wordEgrWr__0\(1)
    );
\wordEgrWr_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \wordEgrWr[3]_i_1_n_0\,
      CLR => AR(0),
      D => \wordEgrWr[2]_i_1_n_0\,
      Q => \wordEgrWr__0\(2)
    );
\wordEgrWr_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \wordEgrWr[3]_i_1_n_0\,
      CLR => AR(0),
      D => \wordEgrWr[3]_i_2_n_0\,
      Q => \wordEgrWr__0\(3)
    );
\wrmutex[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01000000"
    )
        port map (
      I0 => \^stateswap_reg[3]_0\(0),
      I1 => \^stateswap_reg[3]_0\(3),
      I2 => \^stateswap_reg[3]_0\(1),
      I3 => \^stateswap_reg[3]_0\(2),
      I4 => \stateSwap[3]_i_5_0\(0),
      O => \FSM_onehot_stateWrite_reg[1]\(0)
    );
\wrmutex[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA8AAAA"
    )
        port map (
      I0 => \stateSwap[3]_i_5_0\(0),
      I1 => \^stateswap_reg[3]_0\(0),
      I2 => \^stateswap_reg[3]_0\(3),
      I3 => \^stateswap_reg[3]_0\(1),
      I4 => \^stateswap_reg[3]_0\(2),
      O => \FSM_onehot_stateWrite_reg[1]\(1)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Hshktrack is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    ackInvHshktrackSet : out STD_LOGIC;
    ackInvHshktrackSelect : out STD_LOGIC;
    ackInvHshktrackSetMask : out STD_LOGIC;
    rng_reg_0 : out STD_LOGIC;
    ackInvHshktrackClearMask : out STD_LOGIC;
    \mask_reg[5]_0\ : out STD_LOGIC;
    \mask_reg[4]_0\ : out STD_LOGIC;
    \mask_reg[3]_0\ : out STD_LOGIC;
    \mask_reg[2]_0\ : out STD_LOGIC;
    \mask_reg[1]_0\ : out STD_LOGIC;
    \mask_reg[0]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \stateOp_reg[0]_0\ : out STD_LOGIC;
    \FSM_onehot_stateSeq_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    seqbufHshktrackToHostifAXIS_tvalid : out STD_LOGIC;
    hshktrackGetInfoTixVState : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ackSeqbufHshktrackToHostif : out STD_LOGIC;
    hshktrackGetInfoPtr0Seqbuf : out STD_LOGIC_VECTOR ( 9 downto 0 );
    aclk_sig : in STD_LOGIC;
    enSeqbuf_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    rng_reg_1 : in STD_LOGIC;
    \mask_reg[5]_1\ : in STD_LOGIC;
    \mask_reg[4]_1\ : in STD_LOGIC;
    \mask_reg[3]_1\ : in STD_LOGIC;
    \mask_reg[2]_1\ : in STD_LOGIC;
    \mask_reg[1]_1\ : in STD_LOGIC;
    \mask_reg[0]_1\ : in STD_LOGIC;
    reqInvHshktrackSelect : in STD_LOGIC;
    reqInvHshktrackClearMask : in STD_LOGIC;
    reqInvHshktrackSet : in STD_LOGIC;
    reqInvHshktrackSetMask : in STD_LOGIC;
    ackInvSetMask_sig_reg_0 : in STD_LOGIC;
    restart_reg_0 : in STD_LOGIC;
    restart_reg_1 : in STD_LOGIC;
    \ackInvSet_sig_i_2__3_0\ : in STD_LOGIC;
    dneSeqbufHshktrackToHostif : in STD_LOGIC;
    seqbufHshktrackToHostifAXIS_tready : in STD_LOGIC;
    reqSeqbufHshktrackToHostif : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \capt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \TCaptMax_reg[31]_0\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
    \TCaptMax_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \TCaptMax_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Hshktrack : entity is "Hshktrack";
end design_1_Vsp_core_0_0_Hshktrack;

architecture STRUCTURE of design_1_Vsp_core_0_0_Hshktrack is
  signal \FSM_onehot_stateSeq[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[3]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_3__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_4__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_5__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_6__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_7__1_n_0\ : STD_LOGIC;
  signal \^fsm_onehot_stateseq_reg[3]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \FSM_onehot_stateSeq_reg_n_0_[4]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal TCapt : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[0]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[10]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[11]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[12]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[13]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[14]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[15]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[16]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[17]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[18]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[19]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[1]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[20]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[21]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[22]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[23]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[24]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[25]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[26]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[27]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[28]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[29]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[2]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[30]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[31]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[3]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[4]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[5]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[6]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[7]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[8]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[9]\ : STD_LOGIC;
  signal \TCapt__0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \aSeqbufB[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[5]_i_2__1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_2__1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_3__1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_4__1_n_0\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[0]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[1]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[2]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[3]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[4]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[5]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[6]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[7]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[8]\ : STD_LOGIC;
  signal \aSeqbuf[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[5]_i_2__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[7]_i_3__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_2__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_3__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_4__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_5__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_1__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_2__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_3__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_4__2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_5__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_6__1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_7__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[0]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[1]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[2]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[3]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[4]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[5]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[6]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[7]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[8]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[9]\ : STD_LOGIC;
  signal \ackInvClearMask_sig_i_1__0_n_0\ : STD_LOGIC;
  signal \^ackinvhshktrackclearmask\ : STD_LOGIC;
  signal \^ackinvhshktrackselect\ : STD_LOGIC;
  signal \^ackinvhshktrackset\ : STD_LOGIC;
  signal \^ackinvhshktracksetmask\ : STD_LOGIC;
  signal \ackInvSelect_sig_i_1__1_n_0\ : STD_LOGIC;
  signal \ackInvSetMask_sig_i_1__0_n_0\ : STD_LOGIC;
  signal \ackInvSet_sig_i_1__6_n_0\ : STD_LOGIC;
  signal \ackInvSet_sig_i_2__3_n_0\ : STD_LOGIC;
  signal ackSeqbufBToSeqClear : STD_LOGIC;
  signal burstCapt : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \burstCapt_reg_n_0_[0]\ : STD_LOGIC;
  signal \burstCapt_reg_n_0_[1]\ : STD_LOGIC;
  signal \burstCapt_reg_n_0_[2]\ : STD_LOGIC;
  signal \burstCapt_reg_n_0_[3]\ : STD_LOGIC;
  signal \burstCapt_reg_n_0_[4]\ : STD_LOGIC;
  signal \burstCapt_reg_n_0_[5]\ : STD_LOGIC;
  signal burstCnt : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \burstCnt[10]_i_1__1_n_0\ : STD_LOGIC;
  signal \burstCnt[10]_i_2__2_n_0\ : STD_LOGIC;
  signal \burstCnt[11]_i_1__1_n_0\ : STD_LOGIC;
  signal \burstCnt[11]_i_2__1_n_0\ : STD_LOGIC;
  signal \burstCnt[12]_i_1__1_n_0\ : STD_LOGIC;
  signal \burstCnt[13]_i_1__1_n_0\ : STD_LOGIC;
  signal \burstCnt[14]_i_1__1_n_0\ : STD_LOGIC;
  signal \burstCnt[14]_i_2__1_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_10__1_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_11__1_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_12__1_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_13__2_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_1__1_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_2__1_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_3__2_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_4__1_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_5__1_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_6__1_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_7__1_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_8__1_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_9__1_n_0\ : STD_LOGIC;
  signal \burstCnt[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \burstCnt[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \burstCnt[2]_i_2_n_0\ : STD_LOGIC;
  signal \burstCnt[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \burstCnt[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \burstCnt[5]_i_2__1_n_0\ : STD_LOGIC;
  signal \burstCnt[5]_i_3_n_0\ : STD_LOGIC;
  signal \burstCnt[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \burstCnt[7]_i_2__2_n_0\ : STD_LOGIC;
  signal \burstCnt[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \burstCnt[8]_i_2__2_n_0\ : STD_LOGIC;
  signal \burstCnt[9]_i_1__1_n_0\ : STD_LOGIC;
  signal \burstCnt[9]_i_2__1_n_0\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[14]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[9]\ : STD_LOGIC;
  signal capt : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal dwrSeqbuf : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \dwrSeqbuf[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[10]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[11]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[12]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[13]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[14]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[15]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[16]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[17]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[18]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[19]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[1]_i_3__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[20]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[20]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[20]_i_3_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[20]_i_4_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[21]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[2]_i_3__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[30]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[30]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_2__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_3__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_4__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[3]_i_2__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[3]_i_3__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[5]_i_2__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[7]_i_2__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[9]_i_1__1_n_0\ : STD_LOGIC;
  signal enSeqbuf : STD_LOGIC;
  signal enSeqbuf_reg_n_0 : STD_LOGIC;
  signal first : STD_LOGIC;
  signal \first__0\ : STD_LOGIC;
  signal \^hshktrackgetinfotixvstate\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \i[0]_i_1__20_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_10_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_11_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_12_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_13_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_14_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_15_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_16_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_5_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_6_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_7_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_8_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_9_n_0\ : STD_LOGIC;
  signal \i__carry_i_10__4_n_0\ : STD_LOGIC;
  signal \i__carry_i_11__3_n_0\ : STD_LOGIC;
  signal \i__carry_i_12__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_13__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_14_n_0\ : STD_LOGIC;
  signal \i__carry_i_15_n_0\ : STD_LOGIC;
  signal \i__carry_i_16_n_0\ : STD_LOGIC;
  signal \i__carry_i_1__5_n_0\ : STD_LOGIC;
  signal \i__carry_i_2__5_n_0\ : STD_LOGIC;
  signal \i__carry_i_3__5_n_0\ : STD_LOGIC;
  signal \i__carry_i_4__5_n_0\ : STD_LOGIC;
  signal \i__carry_i_5__5_n_0\ : STD_LOGIC;
  signal \i__carry_i_6__5_n_0\ : STD_LOGIC;
  signal \i__carry_i_7__4_n_0\ : STD_LOGIC;
  signal \i__carry_i_8__4_n_0\ : STD_LOGIC;
  signal \i__carry_i_9__4_n_0\ : STD_LOGIC;
  signal \i_reg_n_0_[0]\ : STD_LOGIC;
  signal in12 : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \plusOp_carry__0_n_0\ : STD_LOGIC;
  signal \plusOp_carry__0_n_1\ : STD_LOGIC;
  signal \plusOp_carry__0_n_2\ : STD_LOGIC;
  signal \plusOp_carry__0_n_3\ : STD_LOGIC;
  signal \plusOp_carry__0_n_4\ : STD_LOGIC;
  signal \plusOp_carry__0_n_5\ : STD_LOGIC;
  signal \plusOp_carry__0_n_6\ : STD_LOGIC;
  signal \plusOp_carry__0_n_7\ : STD_LOGIC;
  signal \plusOp_carry__1_n_0\ : STD_LOGIC;
  signal \plusOp_carry__1_n_1\ : STD_LOGIC;
  signal \plusOp_carry__1_n_2\ : STD_LOGIC;
  signal \plusOp_carry__1_n_3\ : STD_LOGIC;
  signal \plusOp_carry__1_n_4\ : STD_LOGIC;
  signal \plusOp_carry__1_n_5\ : STD_LOGIC;
  signal \plusOp_carry__1_n_6\ : STD_LOGIC;
  signal \plusOp_carry__1_n_7\ : STD_LOGIC;
  signal \plusOp_carry__2_n_2\ : STD_LOGIC;
  signal \plusOp_carry__2_n_3\ : STD_LOGIC;
  signal \plusOp_carry__2_n_4\ : STD_LOGIC;
  signal \plusOp_carry__2_n_5\ : STD_LOGIC;
  signal \plusOp_carry__2_n_6\ : STD_LOGIC;
  signal \plusOp_carry__2_n_7\ : STD_LOGIC;
  signal plusOp_carry_n_0 : STD_LOGIC;
  signal plusOp_carry_n_1 : STD_LOGIC;
  signal plusOp_carry_n_2 : STD_LOGIC;
  signal plusOp_carry_n_3 : STD_LOGIC;
  signal plusOp_carry_n_4 : STD_LOGIC;
  signal plusOp_carry_n_5 : STD_LOGIC;
  signal plusOp_carry_n_6 : STD_LOGIC;
  signal plusOp_carry_n_7 : STD_LOGIC;
  signal \ptr0SeqbufTrackNotFixed_i_1__1_n_0\ : STD_LOGIC;
  signal ptr0SeqbufTrackNotFixed_reg_n_0 : STD_LOGIC;
  signal quad : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal \quad[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \quad_reg_n_0_[0]\ : STD_LOGIC;
  signal \quad_reg_n_0_[1]\ : STD_LOGIC;
  signal \quad_reg_n_0_[20]\ : STD_LOGIC;
  signal \quad_reg_n_0_[2]\ : STD_LOGIC;
  signal \quad_reg_n_0_[3]\ : STD_LOGIC;
  signal \quad_reg_n_0_[4]\ : STD_LOGIC;
  signal \quad_reg_n_0_[5]\ : STD_LOGIC;
  signal rdySeq : STD_LOGIC;
  signal \restart_i_1__1_n_0\ : STD_LOGIC;
  signal restart_reg_n_0 : STD_LOGIC;
  signal \^rng_reg_0\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[0]\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[1]\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[2]\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[3]\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[4]\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[5]\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[6]\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[7]\ : STD_LOGIC;
  signal stateOp : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \stateOp[0]_i_1__11_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_1__11_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_10__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_11__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_12__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_13__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_14__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_15__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_16__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_17__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_18__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_19__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_20__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_21__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_22__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_2__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_3__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_5__3_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_6__1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_7__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_8__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_9__0_n_0\ : STD_LOGIC;
  signal \^stateop_reg[0]_0\ : STD_LOGIC;
  signal \stateSeqbufB[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[2]_i_3__1_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[2]_i_7__1_n_0\ : STD_LOGIC;
  signal stateSeqbufB_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal stoTixVTrigger : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \stop_lcl_i_1__1_n_0\ : STD_LOGIC;
  signal \stop_lcl_i_2__2_n_0\ : STD_LOGIC;
  signal stop_lcl_i_3_n_0 : STD_LOGIC;
  signal stop_lcl_i_4_n_0 : STD_LOGIC;
  signal stop_lcl_reg_n_0 : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_0\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_4\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_5\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_6\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry__0_n_7\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_0\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_1\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_2\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_4\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_5\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_6\ : STD_LOGIC;
  signal \strbStop5_inferred__0/i__carry_n_7\ : STD_LOGIC;
  signal \strbStop_i_1__1_n_0\ : STD_LOGIC;
  signal \strbStop_i_2__1_n_0\ : STD_LOGIC;
  signal strbStop_reg_n_0 : STD_LOGIC;
  signal \NLW_plusOp_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_plusOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_strbStop5_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_strbStop5_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[0]_i_2__0\ : label is "soft_lutpair2441";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[2]_i_1__1\ : label is "soft_lutpair2454";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[3]_i_1__1\ : label is "soft_lutpair2454";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_2__1\ : label is "soft_lutpair2450";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_5__1\ : label is "soft_lutpair2460";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_6__1\ : label is "soft_lutpair2460";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[0]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[1]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[2]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[3]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[4]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[5]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute SOFT_HLUTNM of \TCapt[0]_i_1__1\ : label is "soft_lutpair2481";
  attribute SOFT_HLUTNM of \TCapt[10]_i_1__1\ : label is "soft_lutpair2476";
  attribute SOFT_HLUTNM of \TCapt[11]_i_1__1\ : label is "soft_lutpair2476";
  attribute SOFT_HLUTNM of \TCapt[12]_i_1__1\ : label is "soft_lutpair2475";
  attribute SOFT_HLUTNM of \TCapt[13]_i_1__1\ : label is "soft_lutpair2475";
  attribute SOFT_HLUTNM of \TCapt[14]_i_1__1\ : label is "soft_lutpair2474";
  attribute SOFT_HLUTNM of \TCapt[15]_i_1__1\ : label is "soft_lutpair2474";
  attribute SOFT_HLUTNM of \TCapt[16]_i_1__1\ : label is "soft_lutpair2473";
  attribute SOFT_HLUTNM of \TCapt[17]_i_1__1\ : label is "soft_lutpair2473";
  attribute SOFT_HLUTNM of \TCapt[18]_i_1__1\ : label is "soft_lutpair2472";
  attribute SOFT_HLUTNM of \TCapt[19]_i_1__1\ : label is "soft_lutpair2472";
  attribute SOFT_HLUTNM of \TCapt[1]_i_1__1\ : label is "soft_lutpair2481";
  attribute SOFT_HLUTNM of \TCapt[20]_i_1__1\ : label is "soft_lutpair2471";
  attribute SOFT_HLUTNM of \TCapt[21]_i_1__1\ : label is "soft_lutpair2471";
  attribute SOFT_HLUTNM of \TCapt[22]_i_1__1\ : label is "soft_lutpair2470";
  attribute SOFT_HLUTNM of \TCapt[23]_i_1__1\ : label is "soft_lutpair2470";
  attribute SOFT_HLUTNM of \TCapt[24]_i_1__1\ : label is "soft_lutpair2469";
  attribute SOFT_HLUTNM of \TCapt[25]_i_1__1\ : label is "soft_lutpair2469";
  attribute SOFT_HLUTNM of \TCapt[26]_i_1__1\ : label is "soft_lutpair2468";
  attribute SOFT_HLUTNM of \TCapt[27]_i_1__1\ : label is "soft_lutpair2468";
  attribute SOFT_HLUTNM of \TCapt[28]_i_1__1\ : label is "soft_lutpair2467";
  attribute SOFT_HLUTNM of \TCapt[29]_i_1__1\ : label is "soft_lutpair2467";
  attribute SOFT_HLUTNM of \TCapt[2]_i_1__1\ : label is "soft_lutpair2480";
  attribute SOFT_HLUTNM of \TCapt[30]_i_1__1\ : label is "soft_lutpair2466";
  attribute SOFT_HLUTNM of \TCapt[31]_i_1__1\ : label is "soft_lutpair2466";
  attribute SOFT_HLUTNM of \TCapt[3]_i_1__1\ : label is "soft_lutpair2480";
  attribute SOFT_HLUTNM of \TCapt[4]_i_1__1\ : label is "soft_lutpair2479";
  attribute SOFT_HLUTNM of \TCapt[5]_i_1__1\ : label is "soft_lutpair2479";
  attribute SOFT_HLUTNM of \TCapt[6]_i_1__1\ : label is "soft_lutpair2478";
  attribute SOFT_HLUTNM of \TCapt[7]_i_1__1\ : label is "soft_lutpair2478";
  attribute SOFT_HLUTNM of \TCapt[8]_i_1__1\ : label is "soft_lutpair2477";
  attribute SOFT_HLUTNM of \TCapt[9]_i_1__1\ : label is "soft_lutpair2477";
  attribute SOFT_HLUTNM of \aSeqbufB[1]_i_1__1\ : label is "soft_lutpair2437";
  attribute SOFT_HLUTNM of \aSeqbufB[2]_i_1__1\ : label is "soft_lutpair2437";
  attribute SOFT_HLUTNM of \aSeqbufB[5]_i_1__1\ : label is "soft_lutpair2438";
  attribute SOFT_HLUTNM of \aSeqbufB[6]_i_1__1\ : label is "soft_lutpair2426";
  attribute SOFT_HLUTNM of \aSeqbufB[7]_i_1__1\ : label is "soft_lutpair2426";
  attribute SOFT_HLUTNM of \aSeqbufB[8]_i_2__1\ : label is "soft_lutpair2423";
  attribute SOFT_HLUTNM of \aSeqbufB[8]_i_3__1\ : label is "soft_lutpair2450";
  attribute SOFT_HLUTNM of \aSeqbuf[1]_i_1__1\ : label is "soft_lutpair2459";
  attribute SOFT_HLUTNM of \aSeqbuf[2]_i_1__1\ : label is "soft_lutpair2430";
  attribute SOFT_HLUTNM of \aSeqbuf[3]_i_1__1\ : label is "soft_lutpair2430";
  attribute SOFT_HLUTNM of \aSeqbuf[5]_i_1__1\ : label is "soft_lutpair2459";
  attribute SOFT_HLUTNM of \aSeqbuf[6]_i_1__1\ : label is "soft_lutpair2458";
  attribute SOFT_HLUTNM of \aSeqbuf[7]_i_1__1\ : label is "soft_lutpair2440";
  attribute SOFT_HLUTNM of \aSeqbuf[7]_i_3__0\ : label is "soft_lutpair2436";
  attribute SOFT_HLUTNM of \aSeqbuf[8]_i_2__1\ : label is "soft_lutpair2431";
  attribute SOFT_HLUTNM of \aSeqbuf[8]_i_3__2\ : label is "soft_lutpair2440";
  attribute SOFT_HLUTNM of \aSeqbuf[8]_i_4__2\ : label is "soft_lutpair2452";
  attribute SOFT_HLUTNM of \aSeqbuf[8]_i_5__1\ : label is "soft_lutpair2422";
  attribute SOFT_HLUTNM of \aSeqbuf[9]_i_4__2\ : label is "soft_lutpair2436";
  attribute SOFT_HLUTNM of \aSeqbuf[9]_i_6__1\ : label is "soft_lutpair2422";
  attribute SOFT_HLUTNM of \ackInvSet_sig_i_2__3\ : label is "soft_lutpair2453";
  attribute SOFT_HLUTNM of \burstCapt[0]_i_1__0\ : label is "soft_lutpair2464";
  attribute SOFT_HLUTNM of \burstCapt[1]_i_1__0\ : label is "soft_lutpair2464";
  attribute SOFT_HLUTNM of \burstCapt[2]_i_1__0\ : label is "soft_lutpair2465";
  attribute SOFT_HLUTNM of \burstCapt[3]_i_1__0\ : label is "soft_lutpair2465";
  attribute SOFT_HLUTNM of \burstCapt[4]_i_1__0\ : label is "soft_lutpair2451";
  attribute SOFT_HLUTNM of \burstCapt[5]_i_1__0\ : label is "soft_lutpair2448";
  attribute SOFT_HLUTNM of \burstCnt[0]_i_1__1\ : label is "soft_lutpair2461";
  attribute SOFT_HLUTNM of \burstCnt[10]_i_1__1\ : label is "soft_lutpair2463";
  attribute SOFT_HLUTNM of \burstCnt[11]_i_1__1\ : label is "soft_lutpair2461";
  attribute SOFT_HLUTNM of \burstCnt[12]_i_1__1\ : label is "soft_lutpair2424";
  attribute SOFT_HLUTNM of \burstCnt[13]_i_1__1\ : label is "soft_lutpair2424";
  attribute SOFT_HLUTNM of \burstCnt[15]_i_5__1\ : label is "soft_lutpair2462";
  attribute SOFT_HLUTNM of \burstCnt[1]_i_1__1\ : label is "soft_lutpair2425";
  attribute SOFT_HLUTNM of \burstCnt[2]_i_1__1\ : label is "soft_lutpair2425";
  attribute SOFT_HLUTNM of \burstCnt[4]_i_1__1\ : label is "soft_lutpair2462";
  attribute SOFT_HLUTNM of \burstCnt[5]_i_3\ : label is "soft_lutpair2434";
  attribute SOFT_HLUTNM of \burstCnt[8]_i_1__1\ : label is "soft_lutpair2463";
  attribute SOFT_HLUTNM of \burstCnt[9]_i_2__1\ : label is "soft_lutpair2435";
  attribute SOFT_HLUTNM of \dwrSeqbuf[0]_i_2__1\ : label is "soft_lutpair2446";
  attribute SOFT_HLUTNM of \dwrSeqbuf[10]_i_1__1\ : label is "soft_lutpair2457";
  attribute SOFT_HLUTNM of \dwrSeqbuf[11]_i_1__1\ : label is "soft_lutpair2456";
  attribute SOFT_HLUTNM of \dwrSeqbuf[14]_i_1__1\ : label is "soft_lutpair2428";
  attribute SOFT_HLUTNM of \dwrSeqbuf[17]_i_1__1\ : label is "soft_lutpair2456";
  attribute SOFT_HLUTNM of \dwrSeqbuf[19]_i_1__1\ : label is "soft_lutpair2455";
  attribute SOFT_HLUTNM of \dwrSeqbuf[1]_i_2__1\ : label is "soft_lutpair2444";
  attribute SOFT_HLUTNM of \dwrSeqbuf[1]_i_3__1\ : label is "soft_lutpair2443";
  attribute SOFT_HLUTNM of \dwrSeqbuf[20]_i_3\ : label is "soft_lutpair2433";
  attribute SOFT_HLUTNM of \dwrSeqbuf[20]_i_4\ : label is "soft_lutpair2432";
  attribute SOFT_HLUTNM of \dwrSeqbuf[21]_i_1__1\ : label is "soft_lutpair2455";
  attribute SOFT_HLUTNM of \dwrSeqbuf[2]_i_2__1\ : label is "soft_lutpair2444";
  attribute SOFT_HLUTNM of \dwrSeqbuf[2]_i_3__1\ : label is "soft_lutpair2432";
  attribute SOFT_HLUTNM of \dwrSeqbuf[30]_i_1__1\ : label is "soft_lutpair2429";
  attribute SOFT_HLUTNM of \dwrSeqbuf[30]_i_2\ : label is "soft_lutpair2431";
  attribute SOFT_HLUTNM of \dwrSeqbuf[31]_i_2__1\ : label is "soft_lutpair2428";
  attribute SOFT_HLUTNM of \dwrSeqbuf[3]_i_2__1\ : label is "soft_lutpair2449";
  attribute SOFT_HLUTNM of \dwrSeqbuf[3]_i_3__1\ : label is "soft_lutpair2434";
  attribute SOFT_HLUTNM of \dwrSeqbuf[4]_i_2__1\ : label is "soft_lutpair2447";
  attribute SOFT_HLUTNM of \dwrSeqbuf[5]_i_2__1\ : label is "soft_lutpair2433";
  attribute SOFT_HLUTNM of \dwrSeqbuf[7]_i_2__1\ : label is "soft_lutpair2435";
  attribute SOFT_HLUTNM of \dwrSeqbuf[8]_i_1__1\ : label is "soft_lutpair2457";
  attribute SOFT_HLUTNM of \enSeqbuf_i_1__2\ : label is "soft_lutpair2445";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of plusOp_carry : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_carry__0\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_carry__1\ : label is 35;
  attribute ADDER_THRESHOLD of \plusOp_carry__2\ : label is 35;
  attribute SOFT_HLUTNM of \quad[0]_i_1__1\ : label is "soft_lutpair2446";
  attribute SOFT_HLUTNM of \quad[1]_i_1__1\ : label is "soft_lutpair2443";
  attribute SOFT_HLUTNM of \quad[20]_i_1__0\ : label is "soft_lutpair2451";
  attribute SOFT_HLUTNM of \quad[2]_i_1__1\ : label is "soft_lutpair2445";
  attribute SOFT_HLUTNM of \quad[3]_i_1__1\ : label is "soft_lutpair2449";
  attribute SOFT_HLUTNM of \quad[4]_i_1__1\ : label is "soft_lutpair2447";
  attribute SOFT_HLUTNM of \quad[5]_i_2\ : label is "soft_lutpair2448";
  attribute SOFT_HLUTNM of \retbuf[0][0]_i_11\ : label is "soft_lutpair2429";
  attribute SOFT_HLUTNM of \retbuf[5][0]_i_7\ : label is "soft_lutpair2452";
  attribute SOFT_HLUTNM of \retbuf[5][1]_i_7\ : label is "soft_lutpair2482";
  attribute SOFT_HLUTNM of \retbuf[6][0]_i_7\ : label is "soft_lutpair2485";
  attribute SOFT_HLUTNM of \retbuf[6][1]_i_7\ : label is "soft_lutpair2485";
  attribute SOFT_HLUTNM of \retbuf[6][2]_i_7\ : label is "soft_lutpair2484";
  attribute SOFT_HLUTNM of \retbuf[6][3]_i_7\ : label is "soft_lutpair2484";
  attribute SOFT_HLUTNM of \retbuf[6][4]_i_7\ : label is "soft_lutpair2483";
  attribute SOFT_HLUTNM of \retbuf[6][5]_i_8\ : label is "soft_lutpair2483";
  attribute SOFT_HLUTNM of \retbuf[6][6]_i_7\ : label is "soft_lutpair2458";
  attribute SOFT_HLUTNM of \retbuf[6][7]_i_11\ : label is "soft_lutpair2482";
  attribute SOFT_HLUTNM of \staTixVTrigger[7]_i_2__2\ : label is "soft_lutpair2439";
  attribute SOFT_HLUTNM of \stateOp[0]_i_1__11\ : label is "soft_lutpair2439";
  attribute SOFT_HLUTNM of \stateOp[2]_i_11__3\ : label is "soft_lutpair2427";
  attribute SOFT_HLUTNM of \stateOp[2]_i_2__3\ : label is "soft_lutpair2427";
  attribute SOFT_HLUTNM of \stateSeqbufB[0]_i_1__1\ : label is "soft_lutpair2441";
  attribute SOFT_HLUTNM of \stateSeqbufB[1]_i_1__1\ : label is "soft_lutpair2442";
  attribute SOFT_HLUTNM of \stateSeqbufB[2]_i_7__1\ : label is "soft_lutpair2423";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of \strbStop5_inferred__0/i__carry\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \strbStop5_inferred__0/i__carry__0\ : label is 11;
  attribute SOFT_HLUTNM of \strbStop_i_2__1\ : label is "soft_lutpair2453";
  attribute SOFT_HLUTNM of \txAXIS_tdata[15]_i_13\ : label is "soft_lutpair2438";
  attribute SOFT_HLUTNM of \wordcntLast[28]_i_11\ : label is "soft_lutpair2442";
begin
  \FSM_onehot_stateSeq_reg[3]_0\(0) <= \^fsm_onehot_stateseq_reg[3]_0\(0);
  Q(31 downto 0) <= \^q\(31 downto 0);
  ackInvHshktrackClearMask <= \^ackinvhshktrackclearmask\;
  ackInvHshktrackSelect <= \^ackinvhshktrackselect\;
  ackInvHshktrackSet <= \^ackinvhshktrackset\;
  ackInvHshktrackSetMask <= \^ackinvhshktracksetmask\;
  hshktrackGetInfoTixVState(1 downto 0) <= \^hshktrackgetinfotixvstate\(1 downto 0);
  rng_reg_0 <= \^rng_reg_0\;
  \stateOp_reg[0]_0\ <= \^stateop_reg[0]_0\;
\FSM_onehot_stateSeq[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF00010001"
    )
        port map (
      I0 => TCapt,
      I1 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I2 => first,
      I3 => rdySeq,
      I4 => \FSM_onehot_stateSeq[0]_i_2__0_n_0\,
      I5 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \FSM_onehot_stateSeq[0]_i_1__1_n_0\
    );
\FSM_onehot_stateSeq[0]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => stateSeqbufB_reg(1),
      I1 => stateSeqbufB_reg(0),
      I2 => stateSeqbufB_reg(2),
      O => \FSM_onehot_stateSeq[0]_i_2__0_n_0\
    );
\FSM_onehot_stateSeq[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => rdySeq,
      I1 => \FSM_onehot_stateSeq[3]_i_2__2_n_0\,
      I2 => TCapt,
      O => \FSM_onehot_stateSeq[2]_i_1__1_n_0\
    );
\FSM_onehot_stateSeq[3]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[3]_i_2__2_n_0\,
      I1 => TCapt,
      O => \FSM_onehot_stateSeq[3]_i_1__1_n_0\
    );
\FSM_onehot_stateSeq[3]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55555510"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => stop_lcl_i_3_n_0,
      I2 => \aSeqbuf[9]_i_4__2_n_0\,
      I3 => strbStop_reg_n_0,
      I4 => stop_lcl_reg_n_0,
      O => \FSM_onehot_stateSeq[3]_i_2__2_n_0\
    );
\FSM_onehot_stateSeq[5]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"505050505050FF53"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_3__2_n_0\,
      I1 => \FSM_onehot_stateSeq[5]_i_4__1_n_0\,
      I2 => \FSM_onehot_stateSeq[5]_i_5__1_n_0\,
      I3 => \FSM_onehot_stateSeq[5]_i_6__1_n_0\,
      I4 => ackSeqbufBToSeqClear,
      I5 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \FSM_onehot_stateSeq[5]_i_1__1_n_0\
    );
\FSM_onehot_stateSeq[5]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => stateSeqbufB_reg(2),
      I2 => stateSeqbufB_reg(0),
      I3 => stateSeqbufB_reg(1),
      O => \FSM_onehot_stateSeq[5]_i_2__1_n_0\
    );
\FSM_onehot_stateSeq[5]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA2AAAA"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_7__1_n_0\,
      I1 => stateOp(0),
      I2 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I3 => ackSeqbufBToSeqClear,
      I4 => stateOp(1),
      I5 => stateOp(2),
      O => \FSM_onehot_stateSeq[5]_i_3__2_n_0\
    );
\FSM_onehot_stateSeq[5]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7F7F7F700F7F7F7"
    )
        port map (
      I0 => stateOp(1),
      I1 => stateOp(2),
      I2 => stateOp(0),
      I3 => stateSeqbufB_reg(2),
      I4 => stateSeqbufB_reg(0),
      I5 => stateSeqbufB_reg(1),
      O => \FSM_onehot_stateSeq[5]_i_4__1_n_0\
    );
\FSM_onehot_stateSeq[5]_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I1 => TCapt,
      O => \FSM_onehot_stateSeq[5]_i_5__1_n_0\
    );
\FSM_onehot_stateSeq[5]_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I1 => rdySeq,
      I2 => ackSeqbufBToSeqClear,
      O => \FSM_onehot_stateSeq[5]_i_6__1_n_0\
    );
\FSM_onehot_stateSeq[5]_i_7__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF31113FFFF11FF"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_5__1_n_0\,
      I1 => \aSeqbuf[9]_i_4__2_n_0\,
      I2 => rdySeq,
      I3 => ackSeqbufBToSeqClear,
      I4 => \FSM_onehot_stateSeq[0]_i_2__0_n_0\,
      I5 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \FSM_onehot_stateSeq[5]_i_7__1_n_0\
    );
\FSM_onehot_stateSeq_reg[0]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1__1_n_0\,
      D => \FSM_onehot_stateSeq[0]_i_1__1_n_0\,
      PRE => enSeqbuf_reg_0(0),
      Q => first
    );
\FSM_onehot_stateSeq_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => first,
      Q => rdySeq
    );
\FSM_onehot_stateSeq_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \FSM_onehot_stateSeq[2]_i_1__1_n_0\,
      Q => TCapt
    );
\FSM_onehot_stateSeq_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \FSM_onehot_stateSeq[3]_i_1__1_n_0\,
      Q => \^fsm_onehot_stateseq_reg[3]_0\(0)
    );
\FSM_onehot_stateSeq_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \^fsm_onehot_stateseq_reg[3]_0\(0),
      Q => \FSM_onehot_stateSeq_reg_n_0_[4]\
    );
\FSM_onehot_stateSeq_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \FSM_onehot_stateSeq[5]_i_2__1_n_0\,
      Q => ackSeqbufBToSeqClear
    );
\TCaptMax_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[7]_0\(0),
      Q => \TCaptMax_reg_n_0_[0]\
    );
\TCaptMax_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(2),
      Q => \TCaptMax_reg_n_0_[10]\
    );
\TCaptMax_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(3),
      Q => \TCaptMax_reg_n_0_[11]\
    );
\TCaptMax_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(4),
      Q => \TCaptMax_reg_n_0_[12]\
    );
\TCaptMax_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(5),
      Q => \TCaptMax_reg_n_0_[13]\
    );
\TCaptMax_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(6),
      Q => \TCaptMax_reg_n_0_[14]\
    );
\TCaptMax_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(7),
      Q => \TCaptMax_reg_n_0_[15]\
    );
\TCaptMax_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(8),
      Q => \TCaptMax_reg_n_0_[16]\
    );
\TCaptMax_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(9),
      Q => \TCaptMax_reg_n_0_[17]\
    );
\TCaptMax_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(10),
      Q => \TCaptMax_reg_n_0_[18]\
    );
\TCaptMax_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(11),
      Q => \TCaptMax_reg_n_0_[19]\
    );
\TCaptMax_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[7]_0\(1),
      Q => \TCaptMax_reg_n_0_[1]\
    );
\TCaptMax_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(12),
      Q => \TCaptMax_reg_n_0_[20]\
    );
\TCaptMax_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(13),
      Q => \TCaptMax_reg_n_0_[21]\
    );
\TCaptMax_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(14),
      Q => \TCaptMax_reg_n_0_[22]\
    );
\TCaptMax_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(15),
      Q => \TCaptMax_reg_n_0_[23]\
    );
\TCaptMax_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(16),
      Q => \TCaptMax_reg_n_0_[24]\
    );
\TCaptMax_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(17),
      Q => \TCaptMax_reg_n_0_[25]\
    );
\TCaptMax_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(18),
      Q => \TCaptMax_reg_n_0_[26]\
    );
\TCaptMax_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(19),
      Q => \TCaptMax_reg_n_0_[27]\
    );
\TCaptMax_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(20),
      Q => \TCaptMax_reg_n_0_[28]\
    );
\TCaptMax_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(21),
      Q => \TCaptMax_reg_n_0_[29]\
    );
\TCaptMax_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[7]_0\(2),
      Q => \TCaptMax_reg_n_0_[2]\
    );
\TCaptMax_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(22),
      Q => \TCaptMax_reg_n_0_[30]\
    );
\TCaptMax_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(23),
      Q => \TCaptMax_reg_n_0_[31]\
    );
\TCaptMax_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[7]_0\(3),
      Q => \TCaptMax_reg_n_0_[3]\
    );
\TCaptMax_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[7]_0\(4),
      Q => \TCaptMax_reg_n_0_[4]\
    );
\TCaptMax_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[7]_0\(5),
      Q => \TCaptMax_reg_n_0_[5]\
    );
\TCaptMax_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[7]_0\(6),
      Q => \TCaptMax_reg_n_0_[6]\
    );
\TCaptMax_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[7]_0\(7),
      Q => \TCaptMax_reg_n_0_[7]\
    );
\TCaptMax_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(0),
      Q => \TCaptMax_reg_n_0_[8]\
    );
\TCaptMax_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_1\(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(1),
      Q => \TCaptMax_reg_n_0_[9]\
    );
\TCapt[0]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      I1 => first,
      O => \TCapt__0\(0)
    );
\TCapt[10]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(10),
      I1 => first,
      O => \TCapt__0\(10)
    );
\TCapt[11]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(11),
      I1 => first,
      O => \TCapt__0\(11)
    );
\TCapt[12]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(12),
      I1 => first,
      O => \TCapt__0\(12)
    );
\TCapt[13]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(13),
      I1 => first,
      O => \TCapt__0\(13)
    );
\TCapt[14]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(14),
      I1 => first,
      O => \TCapt__0\(14)
    );
\TCapt[15]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(15),
      I1 => first,
      O => \TCapt__0\(15)
    );
\TCapt[16]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(16),
      I1 => first,
      O => \TCapt__0\(16)
    );
\TCapt[17]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(17),
      I1 => first,
      O => \TCapt__0\(17)
    );
\TCapt[18]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(18),
      I1 => first,
      O => \TCapt__0\(18)
    );
\TCapt[19]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(19),
      I1 => first,
      O => \TCapt__0\(19)
    );
\TCapt[1]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(1),
      I1 => first,
      O => \TCapt__0\(1)
    );
\TCapt[20]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(20),
      I1 => first,
      O => \TCapt__0\(20)
    );
\TCapt[21]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(21),
      I1 => first,
      O => \TCapt__0\(21)
    );
\TCapt[22]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(22),
      I1 => first,
      O => \TCapt__0\(22)
    );
\TCapt[23]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(23),
      I1 => first,
      O => \TCapt__0\(23)
    );
\TCapt[24]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(24),
      I1 => first,
      O => \TCapt__0\(24)
    );
\TCapt[25]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(25),
      I1 => first,
      O => \TCapt__0\(25)
    );
\TCapt[26]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(26),
      I1 => first,
      O => \TCapt__0\(26)
    );
\TCapt[27]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(27),
      I1 => first,
      O => \TCapt__0\(27)
    );
\TCapt[28]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(28),
      I1 => first,
      O => \TCapt__0\(28)
    );
\TCapt[29]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(29),
      I1 => first,
      O => \TCapt__0\(29)
    );
\TCapt[2]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(2),
      I1 => first,
      O => \TCapt__0\(2)
    );
\TCapt[30]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(30),
      I1 => first,
      O => \TCapt__0\(30)
    );
\TCapt[31]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(31),
      I1 => first,
      O => \TCapt__0\(31)
    );
\TCapt[3]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(3),
      I1 => first,
      O => \TCapt__0\(3)
    );
\TCapt[4]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(4),
      I1 => first,
      O => \TCapt__0\(4)
    );
\TCapt[5]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(5),
      I1 => first,
      O => \TCapt__0\(5)
    );
\TCapt[6]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(6),
      I1 => first,
      O => \TCapt__0\(6)
    );
\TCapt[7]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(7),
      I1 => first,
      O => \TCapt__0\(7)
    );
\TCapt[8]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(8),
      I1 => first,
      O => \TCapt__0\(8)
    );
\TCapt[9]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(9),
      I1 => first,
      O => \TCapt__0\(9)
    );
\TCapt_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(0),
      Q => \^q\(0)
    );
\TCapt_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(10),
      Q => \^q\(10)
    );
\TCapt_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(11),
      Q => \^q\(11)
    );
\TCapt_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(12),
      Q => \^q\(12)
    );
\TCapt_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(13),
      Q => \^q\(13)
    );
\TCapt_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(14),
      Q => \^q\(14)
    );
\TCapt_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(15),
      Q => \^q\(15)
    );
\TCapt_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(16),
      Q => \^q\(16)
    );
\TCapt_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(17),
      Q => \^q\(17)
    );
\TCapt_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(18),
      Q => \^q\(18)
    );
\TCapt_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(19),
      Q => \^q\(19)
    );
\TCapt_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(1),
      Q => \^q\(1)
    );
\TCapt_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(20),
      Q => \^q\(20)
    );
\TCapt_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(21),
      Q => \^q\(21)
    );
\TCapt_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(22),
      Q => \^q\(22)
    );
\TCapt_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(23),
      Q => \^q\(23)
    );
\TCapt_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(24),
      Q => \^q\(24)
    );
\TCapt_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(25),
      Q => \^q\(25)
    );
\TCapt_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(26),
      Q => \^q\(26)
    );
\TCapt_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(27),
      Q => \^q\(27)
    );
\TCapt_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(28),
      Q => \^q\(28)
    );
\TCapt_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(29),
      Q => \^q\(29)
    );
\TCapt_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(2),
      Q => \^q\(2)
    );
\TCapt_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(30),
      Q => \^q\(30)
    );
\TCapt_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(31),
      Q => \^q\(31)
    );
\TCapt_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(3),
      Q => \^q\(3)
    );
\TCapt_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(4),
      Q => \^q\(4)
    );
\TCapt_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(5),
      Q => \^q\(5)
    );
\TCapt_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(6),
      Q => \^q\(6)
    );
\TCapt_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(7),
      Q => \^q\(7)
    );
\TCapt_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(8),
      Q => \^q\(8)
    );
\TCapt_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \TCapt__0\(9),
      Q => \^q\(9)
    );
\aSeqbufB[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[0]\,
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      O => \aSeqbufB[0]_i_1__1_n_0\
    );
\aSeqbufB[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6660"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[1]\,
      I1 => \aSeqbufB_reg_n_0_[0]\,
      I2 => stateSeqbufB_reg(1),
      I3 => stateSeqbufB_reg(0),
      O => \aSeqbufB[1]_i_1__1_n_0\
    );
\aSeqbufB[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78787800"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[0]\,
      I1 => \aSeqbufB_reg_n_0_[1]\,
      I2 => \aSeqbufB_reg_n_0_[2]\,
      I3 => stateSeqbufB_reg(1),
      I4 => stateSeqbufB_reg(0),
      O => \aSeqbufB[2]_i_1__1_n_0\
    );
\aSeqbufB[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[2]\,
      I1 => \aSeqbufB_reg_n_0_[1]\,
      I2 => \aSeqbufB_reg_n_0_[0]\,
      I3 => \aSeqbufB_reg_n_0_[3]\,
      I4 => \aSeqbufB[8]_i_3__1_n_0\,
      O => \aSeqbufB[3]_i_1__1_n_0\
    );
\aSeqbufB[4]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => \aSeqbufB[8]_i_3__1_n_0\,
      I1 => \aSeqbufB_reg_n_0_[3]\,
      I2 => \aSeqbufB_reg_n_0_[0]\,
      I3 => \aSeqbufB_reg_n_0_[1]\,
      I4 => \aSeqbufB_reg_n_0_[2]\,
      I5 => \aSeqbufB_reg_n_0_[4]\,
      O => \aSeqbufB[4]_i_1__1_n_0\
    );
\aSeqbufB[5]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0EE0"
    )
        port map (
      I0 => stateSeqbufB_reg(1),
      I1 => stateSeqbufB_reg(0),
      I2 => \aSeqbufB[5]_i_2__1_n_0\,
      I3 => \aSeqbufB_reg_n_0_[5]\,
      O => \aSeqbufB[5]_i_1__1_n_0\
    );
\aSeqbufB[5]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[4]\,
      I1 => \aSeqbufB_reg_n_0_[2]\,
      I2 => \aSeqbufB_reg_n_0_[1]\,
      I3 => \aSeqbufB_reg_n_0_[0]\,
      I4 => \aSeqbufB_reg_n_0_[3]\,
      O => \aSeqbufB[5]_i_2__1_n_0\
    );
\aSeqbufB[6]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0EE0"
    )
        port map (
      I0 => stateSeqbufB_reg(1),
      I1 => stateSeqbufB_reg(0),
      I2 => \aSeqbufB[8]_i_4__1_n_0\,
      I3 => \aSeqbufB_reg_n_0_[6]\,
      O => \aSeqbufB[6]_i_1__1_n_0\
    );
\aSeqbufB[7]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0EEEE000"
    )
        port map (
      I0 => stateSeqbufB_reg(1),
      I1 => stateSeqbufB_reg(0),
      I2 => \aSeqbufB[8]_i_4__1_n_0\,
      I3 => \aSeqbufB_reg_n_0_[6]\,
      I4 => \aSeqbufB_reg_n_0_[7]\,
      O => \aSeqbufB[7]_i_1__1_n_0\
    );
\aSeqbufB[8]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4101"
    )
        port map (
      I0 => stateSeqbufB_reg(2),
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      I3 => \stateSeqbufB[1]_i_2__1_n_0\,
      O => \aSeqbufB[8]_i_1__1_n_0\
    );
\aSeqbufB[8]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15554000"
    )
        port map (
      I0 => \aSeqbufB[8]_i_3__1_n_0\,
      I1 => \aSeqbufB_reg_n_0_[6]\,
      I2 => \aSeqbufB[8]_i_4__1_n_0\,
      I3 => \aSeqbufB_reg_n_0_[7]\,
      I4 => \aSeqbufB_reg_n_0_[8]\,
      O => \aSeqbufB[8]_i_2__1_n_0\
    );
\aSeqbufB[8]_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => stateSeqbufB_reg(0),
      I1 => stateSeqbufB_reg(2),
      I2 => stateSeqbufB_reg(1),
      O => \aSeqbufB[8]_i_3__1_n_0\
    );
\aSeqbufB[8]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[3]\,
      I1 => \aSeqbufB_reg_n_0_[0]\,
      I2 => \aSeqbufB_reg_n_0_[1]\,
      I3 => \aSeqbufB_reg_n_0_[2]\,
      I4 => \aSeqbufB_reg_n_0_[4]\,
      I5 => \aSeqbufB_reg_n_0_[5]\,
      O => \aSeqbufB[8]_i_4__1_n_0\
    );
\aSeqbufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbufB[0]_i_1__1_n_0\,
      Q => \aSeqbufB_reg_n_0_[0]\
    );
\aSeqbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbufB[1]_i_1__1_n_0\,
      Q => \aSeqbufB_reg_n_0_[1]\
    );
\aSeqbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbufB[2]_i_1__1_n_0\,
      Q => \aSeqbufB_reg_n_0_[2]\
    );
\aSeqbufB_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbufB[3]_i_1__1_n_0\,
      Q => \aSeqbufB_reg_n_0_[3]\
    );
\aSeqbufB_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbufB[4]_i_1__1_n_0\,
      Q => \aSeqbufB_reg_n_0_[4]\
    );
\aSeqbufB_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbufB[5]_i_1__1_n_0\,
      Q => \aSeqbufB_reg_n_0_[5]\
    );
\aSeqbufB_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbufB[6]_i_1__1_n_0\,
      Q => \aSeqbufB_reg_n_0_[6]\
    );
\aSeqbufB_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbufB[7]_i_1__1_n_0\,
      Q => \aSeqbufB_reg_n_0_[7]\
    );
\aSeqbufB_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbufB[8]_i_2__1_n_0\,
      Q => \aSeqbufB_reg_n_0_[8]\
    );
\aSeqbuf[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555544454454"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[0]\,
      I1 => ackSeqbufBToSeqClear,
      I2 => rdySeq,
      I3 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I4 => TCapt,
      I5 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \aSeqbuf[0]_i_1__1_n_0\
    );
\aSeqbuf[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[1]\,
      I1 => \aSeqbuf_reg_n_0_[0]\,
      I2 => \aSeqbuf[9]_i_6__1_n_0\,
      O => \aSeqbuf[1]_i_1__1_n_0\
    );
\aSeqbuf[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[0]\,
      I1 => \aSeqbuf_reg_n_0_[1]\,
      I2 => \aSeqbuf_reg_n_0_[2]\,
      I3 => \aSeqbuf[9]_i_6__1_n_0\,
      O => \aSeqbuf[2]_i_1__1_n_0\
    );
\aSeqbuf[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[2]\,
      I1 => \aSeqbuf_reg_n_0_[1]\,
      I2 => \aSeqbuf_reg_n_0_[0]\,
      I3 => \aSeqbuf_reg_n_0_[3]\,
      I4 => \aSeqbuf[9]_i_6__1_n_0\,
      O => \aSeqbuf[3]_i_1__1_n_0\
    );
\aSeqbuf[4]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[3]\,
      I1 => \aSeqbuf_reg_n_0_[0]\,
      I2 => \aSeqbuf_reg_n_0_[1]\,
      I3 => \aSeqbuf_reg_n_0_[2]\,
      I4 => \aSeqbuf_reg_n_0_[4]\,
      I5 => \aSeqbuf[9]_i_6__1_n_0\,
      O => \aSeqbuf[4]_i_1__1_n_0\
    );
\aSeqbuf[5]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"14"
    )
        port map (
      I0 => \aSeqbuf[9]_i_6__1_n_0\,
      I1 => \aSeqbuf_reg_n_0_[5]\,
      I2 => \aSeqbuf[5]_i_2__1_n_0\,
      O => \aSeqbuf[5]_i_1__1_n_0\
    );
\aSeqbuf[5]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[4]\,
      I1 => \aSeqbuf_reg_n_0_[2]\,
      I2 => \aSeqbuf_reg_n_0_[1]\,
      I3 => \aSeqbuf_reg_n_0_[0]\,
      I4 => \aSeqbuf_reg_n_0_[3]\,
      O => \aSeqbuf[5]_i_2__1_n_0\
    );
\aSeqbuf[6]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \aSeqbuf[7]_i_2__0_n_0\,
      I1 => \aSeqbuf[9]_i_7__0_n_0\,
      I2 => \aSeqbuf_reg_n_0_[6]\,
      O => \aSeqbuf[6]_i_1__1_n_0\
    );
\aSeqbuf[7]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7800"
    )
        port map (
      I0 => \aSeqbuf[9]_i_7__0_n_0\,
      I1 => \aSeqbuf_reg_n_0_[6]\,
      I2 => \aSeqbuf_reg_n_0_[7]\,
      I3 => \aSeqbuf[7]_i_2__0_n_0\,
      O => \aSeqbuf[7]_i_1__1_n_0\
    );
\aSeqbuf[7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1500555555555555"
    )
        port map (
      I0 => \aSeqbuf[9]_i_6__1_n_0\,
      I1 => \aSeqbuf_reg_n_0_[7]\,
      I2 => \aSeqbuf_reg_n_0_[6]\,
      I3 => \aSeqbuf_reg_n_0_[8]\,
      I4 => \aSeqbuf[8]_i_2__1_n_0\,
      I5 => \aSeqbuf[7]_i_3__0_n_0\,
      O => \aSeqbuf[7]_i_2__0_n_0\
    );
\aSeqbuf[7]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \aSeqbuf[9]_i_7__0_n_0\,
      I1 => \aSeqbuf_reg_n_0_[9]\,
      I2 => \aSeqbuf_reg_n_0_[7]\,
      I3 => \aSeqbuf_reg_n_0_[8]\,
      O => \aSeqbuf[7]_i_3__0_n_0\
    );
\aSeqbuf[8]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F070FF50505050"
    )
        port map (
      I0 => \aSeqbuf[8]_i_2__1_n_0\,
      I1 => \aSeqbuf[9]_i_7__0_n_0\,
      I2 => \aSeqbuf[8]_i_3__2_n_0\,
      I3 => \aSeqbuf_reg_n_0_[6]\,
      I4 => \aSeqbuf[8]_i_4__2_n_0\,
      I5 => \aSeqbuf[8]_i_5__1_n_0\,
      O => \aSeqbuf[8]_i_1__1_n_0\
    );
\aSeqbuf[8]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00540055"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I2 => TCapt,
      I3 => ackSeqbufBToSeqClear,
      I4 => rdySeq,
      O => \aSeqbuf[8]_i_2__1_n_0\
    );
\aSeqbuf[8]_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[8]\,
      I1 => \aSeqbuf[9]_i_7__0_n_0\,
      I2 => \aSeqbuf_reg_n_0_[6]\,
      I3 => \aSeqbuf_reg_n_0_[7]\,
      O => \aSeqbuf[8]_i_3__2_n_0\
    );
\aSeqbuf[8]_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[8]\,
      I1 => \aSeqbuf_reg_n_0_[7]\,
      I2 => \aSeqbuf_reg_n_0_[9]\,
      O => \aSeqbuf[8]_i_4__2_n_0\
    );
\aSeqbuf[8]_i_5__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => TCapt,
      I1 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I2 => rdySeq,
      I3 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I4 => ackSeqbufBToSeqClear,
      O => \aSeqbuf[8]_i_5__1_n_0\
    );
\aSeqbuf[9]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFAE"
    )
        port map (
      I0 => \aSeqbuf[9]_i_3__1_n_0\,
      I1 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I2 => \aSeqbuf[9]_i_4__2_n_0\,
      I3 => \aSeqbuf[9]_i_5__1_n_0\,
      O => \aSeqbuf[9]_i_1__1_n_0\
    );
\aSeqbuf[9]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => \aSeqbuf[9]_i_6__1_n_0\,
      I1 => \aSeqbuf_reg_n_0_[6]\,
      I2 => \aSeqbuf[9]_i_7__0_n_0\,
      I3 => \aSeqbuf_reg_n_0_[8]\,
      I4 => \aSeqbuf_reg_n_0_[7]\,
      I5 => \aSeqbuf_reg_n_0_[9]\,
      O => \aSeqbuf[9]_i_2__1_n_0\
    );
\aSeqbuf[9]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"008000800080AAAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_2_n_0\,
      I1 => \burstCnt[2]_i_2_n_0\,
      I2 => \i_reg_n_0_[0]\,
      I3 => \first__0\,
      I4 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I5 => TCapt,
      O => \aSeqbuf[9]_i_3__1_n_0\
    );
\aSeqbuf[9]_i_4__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[6]\,
      I1 => \aSeqbuf[9]_i_7__0_n_0\,
      I2 => \aSeqbuf_reg_n_0_[9]\,
      I3 => \aSeqbuf_reg_n_0_[7]\,
      I4 => \aSeqbuf_reg_n_0_[8]\,
      O => \aSeqbuf[9]_i_4__2_n_0\
    );
\aSeqbuf[9]_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0003000200030000"
    )
        port map (
      I0 => rdySeq,
      I1 => ackSeqbufBToSeqClear,
      I2 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I3 => \FSM_onehot_stateSeq[5]_i_4__1_n_0\,
      I4 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I5 => TCapt,
      O => \aSeqbuf[9]_i_5__1_n_0\
    );
\aSeqbuf[9]_i_6__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00005451"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => TCapt,
      I2 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I3 => rdySeq,
      I4 => ackSeqbufBToSeqClear,
      O => \aSeqbuf[9]_i_6__1_n_0\
    );
\aSeqbuf[9]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[3]\,
      I1 => \aSeqbuf_reg_n_0_[0]\,
      I2 => \aSeqbuf_reg_n_0_[1]\,
      I3 => \aSeqbuf_reg_n_0_[2]\,
      I4 => \aSeqbuf_reg_n_0_[4]\,
      I5 => \aSeqbuf_reg_n_0_[5]\,
      O => \aSeqbuf[9]_i_7__0_n_0\
    );
\aSeqbuf_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbuf[0]_i_1__1_n_0\,
      Q => \aSeqbuf_reg_n_0_[0]\
    );
\aSeqbuf_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbuf[1]_i_1__1_n_0\,
      Q => \aSeqbuf_reg_n_0_[1]\
    );
\aSeqbuf_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbuf[2]_i_1__1_n_0\,
      Q => \aSeqbuf_reg_n_0_[2]\
    );
\aSeqbuf_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbuf[3]_i_1__1_n_0\,
      Q => \aSeqbuf_reg_n_0_[3]\
    );
\aSeqbuf_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbuf[4]_i_1__1_n_0\,
      Q => \aSeqbuf_reg_n_0_[4]\
    );
\aSeqbuf_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbuf[5]_i_1__1_n_0\,
      Q => \aSeqbuf_reg_n_0_[5]\
    );
\aSeqbuf_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbuf[6]_i_1__1_n_0\,
      Q => \aSeqbuf_reg_n_0_[6]\
    );
\aSeqbuf_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbuf[7]_i_1__1_n_0\,
      Q => \aSeqbuf_reg_n_0_[7]\
    );
\aSeqbuf_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbuf[8]_i_1__1_n_0\,
      Q => \aSeqbuf_reg_n_0_[8]\
    );
\aSeqbuf_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \aSeqbuf[9]_i_2__1_n_0\,
      Q => \aSeqbuf_reg_n_0_[9]\
    );
\ackInvClearMask_sig_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D5C0"
    )
        port map (
      I0 => \ackInvSet_sig_i_2__3_n_0\,
      I1 => reqInvHshktrackClearMask,
      I2 => \^stateop_reg[0]_0\,
      I3 => \^ackinvhshktrackclearmask\,
      O => \ackInvClearMask_sig_i_1__0_n_0\
    );
ackInvClearMask_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \ackInvClearMask_sig_i_1__0_n_0\,
      Q => \^ackinvhshktrackclearmask\
    );
\ackInvSelect_sig_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F555B000"
    )
        port map (
      I0 => \ackInvSet_sig_i_2__3_n_0\,
      I1 => reqInvHshktrackClearMask,
      I2 => reqInvHshktrackSelect,
      I3 => \^stateop_reg[0]_0\,
      I4 => \^ackinvhshktrackselect\,
      O => \ackInvSelect_sig_i_1__1_n_0\
    );
ackInvSelect_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \ackInvSelect_sig_i_1__1_n_0\,
      Q => \^ackinvhshktrackselect\
    );
\ackInvSetMask_sig_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D5D5D5D58080C080"
    )
        port map (
      I0 => \ackInvSet_sig_i_2__3_n_0\,
      I1 => reqInvHshktrackSetMask,
      I2 => \^stateop_reg[0]_0\,
      I3 => ackInvSetMask_sig_reg_0,
      I4 => reqInvHshktrackClearMask,
      I5 => \^ackinvhshktracksetmask\,
      O => \ackInvSetMask_sig_i_1__0_n_0\
    );
ackInvSetMask_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \ackInvSetMask_sig_i_1__0_n_0\,
      Q => \^ackinvhshktracksetmask\
    );
\ackInvSet_sig_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF555555AB000000"
    )
        port map (
      I0 => \ackInvSet_sig_i_2__3_n_0\,
      I1 => reqInvHshktrackSelect,
      I2 => reqInvHshktrackClearMask,
      I3 => reqInvHshktrackSet,
      I4 => \^stateop_reg[0]_0\,
      I5 => \^ackinvhshktrackset\,
      O => \ackInvSet_sig_i_1__6_n_0\
    );
\ackInvSet_sig_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(1),
      I2 => \stateOp[2]_i_10__2_n_0\,
      O => \ackInvSet_sig_i_2__3_n_0\
    );
ackInvSet_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \ackInvSet_sig_i_1__6_n_0\,
      Q => \^ackinvhshktrackset\
    );
\burstCapt[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(0),
      I1 => \burstCnt[15]_i_5__1_n_0\,
      O => burstCapt(0)
    );
\burstCapt[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(1),
      I1 => \burstCnt[15]_i_5__1_n_0\,
      O => burstCapt(1)
    );
\burstCapt[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(2),
      I1 => \burstCnt[15]_i_5__1_n_0\,
      O => burstCapt(2)
    );
\burstCapt[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(3),
      I1 => \burstCnt[15]_i_5__1_n_0\,
      O => burstCapt(3)
    );
\burstCapt[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(4),
      I1 => \burstCnt[15]_i_5__1_n_0\,
      O => burstCapt(4)
    );
\burstCapt[5]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(5),
      I1 => \burstCnt[15]_i_5__1_n_0\,
      O => burstCapt(5)
    );
\burstCapt_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => burstCapt(0),
      Q => \burstCapt_reg_n_0_[0]\
    );
\burstCapt_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => burstCapt(1),
      Q => \burstCapt_reg_n_0_[1]\
    );
\burstCapt_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => burstCapt(2),
      Q => \burstCapt_reg_n_0_[2]\
    );
\burstCapt_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => burstCapt(3),
      Q => \burstCapt_reg_n_0_[3]\
    );
\burstCapt_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => burstCapt(4),
      Q => \burstCapt_reg_n_0_[4]\
    );
\burstCapt_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => burstCapt(5),
      Q => \burstCapt_reg_n_0_[5]\
    );
\burstCnt[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A2"
    )
        port map (
      I0 => \burstCnt[15]_i_5__1_n_0\,
      I1 => \burstCnt_reg_n_0_[0]\,
      I2 => \burstCnt[15]_i_3__2_n_0\,
      O => burstCnt(0)
    );
\burstCnt[10]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \burstCnt[10]_i_2__2_n_0\,
      I1 => \burstCnt[15]_i_5__1_n_0\,
      O => \burstCnt[10]_i_1__1_n_0\
    );
\burstCnt[10]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00A600AA"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[10]\,
      I1 => \burstCnt_reg_n_0_[9]\,
      I2 => \burstCnt[9]_i_2__1_n_0\,
      I3 => \burstCnt[15]_i_3__2_n_0\,
      I4 => \burstCnt_reg_n_0_[8]\,
      O => \burstCnt[10]_i_2__2_n_0\
    );
\burstCnt[11]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \burstCnt[11]_i_2__1_n_0\,
      I1 => \burstCnt[15]_i_5__1_n_0\,
      O => \burstCnt[11]_i_1__1_n_0\
    );
\burstCnt[11]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2212222222222222"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[11]\,
      I1 => \burstCnt[15]_i_3__2_n_0\,
      I2 => \burstCnt_reg_n_0_[9]\,
      I3 => \burstCnt[9]_i_2__1_n_0\,
      I4 => \burstCnt_reg_n_0_[8]\,
      I5 => \burstCnt_reg_n_0_[10]\,
      O => \burstCnt[11]_i_2__1_n_0\
    );
\burstCnt[12]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A600"
    )
        port map (
      I0 => \burstCnt[14]_i_2__1_n_0\,
      I1 => \burstCnt_reg_n_0_[12]\,
      I2 => \burstCnt[15]_i_3__2_n_0\,
      I3 => \burstCnt[15]_i_5__1_n_0\,
      O => \burstCnt[12]_i_1__1_n_0\
    );
\burstCnt[13]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"07080000"
    )
        port map (
      I0 => \burstCnt[14]_i_2__1_n_0\,
      I1 => \burstCnt_reg_n_0_[12]\,
      I2 => \burstCnt[15]_i_3__2_n_0\,
      I3 => \burstCnt_reg_n_0_[13]\,
      I4 => \burstCnt[15]_i_5__1_n_0\,
      O => \burstCnt[13]_i_1__1_n_0\
    );
\burstCnt[14]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"007F008000000000"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[13]\,
      I1 => \burstCnt[14]_i_2__1_n_0\,
      I2 => \burstCnt_reg_n_0_[12]\,
      I3 => \burstCnt[15]_i_3__2_n_0\,
      I4 => \burstCnt_reg_n_0_[14]\,
      I5 => \burstCnt[15]_i_5__1_n_0\,
      O => \burstCnt[14]_i_1__1_n_0\
    );
\burstCnt[14]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000000000"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[11]\,
      I1 => \burstCnt_reg_n_0_[10]\,
      I2 => \burstCnt[15]_i_3__2_n_0\,
      I3 => \burstCnt_reg_n_0_[8]\,
      I4 => \burstCnt[9]_i_2__1_n_0\,
      I5 => \burstCnt_reg_n_0_[9]\,
      O => \burstCnt[14]_i_2__1_n_0\
    );
\burstCnt[15]_i_10__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[5]\,
      I1 => \burstCnt_reg_n_0_[2]\,
      I2 => \burstCnt_reg_n_0_[12]\,
      I3 => \burstCnt_reg_n_0_[9]\,
      O => \burstCnt[15]_i_10__1_n_0\
    );
\burstCnt[15]_i_11__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[1]\,
      I1 => \burstCnt_reg_n_0_[0]\,
      I2 => \burstCnt_reg_n_0_[13]\,
      I3 => \burstCnt_reg_n_0_[6]\,
      O => \burstCnt[15]_i_11__1_n_0\
    );
\burstCnt[15]_i_12__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFFFFFFFFFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[8]\,
      I1 => \burstCnt[15]_i_3__2_n_0\,
      I2 => \burstCnt_reg_n_0_[7]\,
      I3 => \burstCnt[15]_i_13__2_n_0\,
      I4 => \burstCnt_reg_n_0_[6]\,
      I5 => \burstCnt_reg_n_0_[9]\,
      O => \burstCnt[15]_i_12__1_n_0\
    );
\burstCnt[15]_i_13__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF7FFFFFFFFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[4]\,
      I1 => \burstCnt_reg_n_0_[2]\,
      I2 => \burstCnt[5]_i_3_n_0\,
      I3 => \burstCnt[15]_i_3__2_n_0\,
      I4 => \burstCnt_reg_n_0_[3]\,
      I5 => \burstCnt_reg_n_0_[5]\,
      O => \burstCnt[15]_i_13__2_n_0\
    );
\burstCnt[15]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000100000001"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => rdySeq,
      I2 => ackSeqbufBToSeqClear,
      I3 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I4 => TCapt,
      I5 => \i_reg_n_0_[0]\,
      O => \burstCnt[15]_i_1__1_n_0\
    );
\burstCnt[15]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55400000"
    )
        port map (
      I0 => \burstCnt[15]_i_3__2_n_0\,
      I1 => \burstCnt_reg_n_0_[14]\,
      I2 => \burstCnt[15]_i_4__1_n_0\,
      I3 => \burstCnt_reg_n_0_[15]\,
      I4 => \burstCnt[15]_i_5__1_n_0\,
      O => \burstCnt[15]_i_2__1_n_0\
    );
\burstCnt[15]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEEEFEEEE"
    )
        port map (
      I0 => \burstCnt[15]_i_6__1_n_0\,
      I1 => \burstCnt[15]_i_7__1_n_0\,
      I2 => \burstCnt[15]_i_8__1_n_0\,
      I3 => \burstCnt[15]_i_9__1_n_0\,
      I4 => \burstCnt[15]_i_10__1_n_0\,
      I5 => \burstCnt[15]_i_11__1_n_0\,
      O => \burstCnt[15]_i_3__2_n_0\
    );
\burstCnt[15]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000008000000000"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[13]\,
      I1 => \burstCnt_reg_n_0_[11]\,
      I2 => \burstCnt_reg_n_0_[10]\,
      I3 => \burstCnt[15]_i_3__2_n_0\,
      I4 => \burstCnt[15]_i_12__1_n_0\,
      I5 => \burstCnt_reg_n_0_[12]\,
      O => \burstCnt[15]_i_4__1_n_0\
    );
\burstCnt[15]_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dwrSeqbuf[20]_i_2_n_0\,
      I1 => first,
      O => \burstCnt[15]_i_5__1_n_0\
    );
\burstCnt[15]_i_6__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \burstCapt_reg_n_0_[0]\,
      I1 => capt(0),
      I2 => capt(1),
      I3 => \burstCapt_reg_n_0_[1]\,
      I4 => capt(2),
      I5 => \burstCapt_reg_n_0_[2]\,
      O => \burstCnt[15]_i_6__1_n_0\
    );
\burstCnt[15]_i_7__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \burstCapt_reg_n_0_[3]\,
      I1 => capt(3),
      I2 => capt(5),
      I3 => \burstCapt_reg_n_0_[5]\,
      I4 => capt(4),
      I5 => \burstCapt_reg_n_0_[4]\,
      O => \burstCnt[15]_i_7__1_n_0\
    );
\burstCnt[15]_i_8__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[10]\,
      I1 => \burstCnt_reg_n_0_[4]\,
      I2 => \burstCnt_reg_n_0_[15]\,
      I3 => \burstCnt_reg_n_0_[11]\,
      O => \burstCnt[15]_i_8__1_n_0\
    );
\burstCnt[15]_i_9__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[8]\,
      I1 => \burstCnt_reg_n_0_[7]\,
      I2 => \burstCnt_reg_n_0_[14]\,
      I3 => \burstCnt_reg_n_0_[3]\,
      O => \burstCnt[15]_i_9__1_n_0\
    );
\burstCnt[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0014"
    )
        port map (
      I0 => first,
      I1 => \burstCnt_reg_n_0_[0]\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \burstCnt[2]_i_2_n_0\,
      O => \burstCnt[1]_i_1__1_n_0\
    );
\burstCnt[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001444"
    )
        port map (
      I0 => first,
      I1 => \burstCnt_reg_n_0_[2]\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \burstCnt_reg_n_0_[0]\,
      I4 => \burstCnt[2]_i_2_n_0\,
      O => \burstCnt[2]_i_1__1_n_0\
    );
\burstCnt[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \burstCnt[15]_i_3__2_n_0\,
      I1 => \dwrSeqbuf[20]_i_2_n_0\,
      O => \burstCnt[2]_i_2_n_0\
    );
\burstCnt[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000028888888"
    )
        port map (
      I0 => \burstCnt[15]_i_5__1_n_0\,
      I1 => \burstCnt_reg_n_0_[3]\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \burstCnt_reg_n_0_[0]\,
      I4 => \burstCnt_reg_n_0_[2]\,
      I5 => \burstCnt[15]_i_3__2_n_0\,
      O => burstCnt(3)
    );
\burstCnt[4]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[4]_i_2__1_n_0\,
      O => \burstCnt[4]_i_1__1_n_0\
    );
\burstCnt[4]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF20DFFFFFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[3]\,
      I1 => \burstCnt[5]_i_3_n_0\,
      I2 => \burstCnt_reg_n_0_[2]\,
      I3 => \burstCnt_reg_n_0_[4]\,
      I4 => \burstCnt[15]_i_3__2_n_0\,
      I5 => \dwrSeqbuf[20]_i_2_n_0\,
      O => \burstCnt[4]_i_2__1_n_0\
    );
\burstCnt[5]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \burstCnt[15]_i_5__1_n_0\,
      I1 => \burstCnt[5]_i_2__1_n_0\,
      O => burstCnt(5)
    );
\burstCnt[5]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CECCCCCCFDFFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[3]\,
      I1 => \burstCnt[15]_i_3__2_n_0\,
      I2 => \burstCnt[5]_i_3_n_0\,
      I3 => \burstCnt_reg_n_0_[2]\,
      I4 => \burstCnt_reg_n_0_[4]\,
      I5 => \burstCnt_reg_n_0_[5]\,
      O => \burstCnt[5]_i_2__1_n_0\
    );
\burstCnt[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[0]\,
      I1 => \burstCnt_reg_n_0_[1]\,
      O => \burstCnt[5]_i_3_n_0\
    );
\burstCnt[6]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4B440000"
    )
        port map (
      I0 => \burstCnt[7]_i_2__2_n_0\,
      I1 => \burstCnt_reg_n_0_[5]\,
      I2 => \burstCnt[15]_i_3__2_n_0\,
      I3 => \burstCnt_reg_n_0_[6]\,
      I4 => \burstCnt[15]_i_5__1_n_0\,
      O => \burstCnt[6]_i_1__1_n_0\
    );
\burstCnt[7]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008AAA00002000"
    )
        port map (
      I0 => \burstCnt[15]_i_5__1_n_0\,
      I1 => \burstCnt[7]_i_2__2_n_0\,
      I2 => \burstCnt_reg_n_0_[5]\,
      I3 => \burstCnt_reg_n_0_[6]\,
      I4 => \burstCnt[15]_i_3__2_n_0\,
      I5 => \burstCnt_reg_n_0_[7]\,
      O => burstCnt(7)
    );
\burstCnt[7]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[3]\,
      I1 => \burstCnt[15]_i_3__2_n_0\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \burstCnt_reg_n_0_[0]\,
      I4 => \burstCnt_reg_n_0_[2]\,
      I5 => \burstCnt_reg_n_0_[4]\,
      O => \burstCnt[7]_i_2__2_n_0\
    );
\burstCnt[8]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \burstCnt[8]_i_2__2_n_0\,
      I1 => \burstCnt[15]_i_5__1_n_0\,
      O => \burstCnt[8]_i_1__1_n_0\
    );
\burstCnt[8]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A0A060A0A0A0A0A"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[8]\,
      I1 => \burstCnt_reg_n_0_[6]\,
      I2 => \burstCnt[15]_i_3__2_n_0\,
      I3 => \burstCnt_reg_n_0_[5]\,
      I4 => \burstCnt[7]_i_2__2_n_0\,
      I5 => \burstCnt_reg_n_0_[7]\,
      O => \burstCnt[8]_i_2__2_n_0\
    );
\burstCnt[9]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"23100000"
    )
        port map (
      I0 => \burstCnt[9]_i_2__1_n_0\,
      I1 => \burstCnt[15]_i_3__2_n_0\,
      I2 => \burstCnt_reg_n_0_[8]\,
      I3 => \burstCnt_reg_n_0_[9]\,
      I4 => \burstCnt[15]_i_5__1_n_0\,
      O => \burstCnt[9]_i_1__1_n_0\
    );
\burstCnt[9]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFDFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[7]\,
      I1 => \burstCnt[7]_i_2__2_n_0\,
      I2 => \burstCnt_reg_n_0_[5]\,
      I3 => \burstCnt[15]_i_3__2_n_0\,
      I4 => \burstCnt_reg_n_0_[6]\,
      O => \burstCnt[9]_i_2__1_n_0\
    );
\burstCnt_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => burstCnt(0),
      Q => \burstCnt_reg_n_0_[0]\
    );
\burstCnt_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \burstCnt[10]_i_1__1_n_0\,
      Q => \burstCnt_reg_n_0_[10]\
    );
\burstCnt_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \burstCnt[11]_i_1__1_n_0\,
      Q => \burstCnt_reg_n_0_[11]\
    );
\burstCnt_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \burstCnt[12]_i_1__1_n_0\,
      Q => \burstCnt_reg_n_0_[12]\
    );
\burstCnt_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \burstCnt[13]_i_1__1_n_0\,
      Q => \burstCnt_reg_n_0_[13]\
    );
\burstCnt_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \burstCnt[14]_i_1__1_n_0\,
      Q => \burstCnt_reg_n_0_[14]\
    );
\burstCnt_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \burstCnt[15]_i_2__1_n_0\,
      Q => \burstCnt_reg_n_0_[15]\
    );
\burstCnt_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \burstCnt[1]_i_1__1_n_0\,
      Q => \burstCnt_reg_n_0_[1]\
    );
\burstCnt_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \burstCnt[2]_i_1__1_n_0\,
      Q => \burstCnt_reg_n_0_[2]\
    );
\burstCnt_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => burstCnt(3),
      Q => \burstCnt_reg_n_0_[3]\
    );
\burstCnt_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \burstCnt[4]_i_1__1_n_0\,
      Q => \burstCnt_reg_n_0_[4]\
    );
\burstCnt_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => burstCnt(5),
      Q => \burstCnt_reg_n_0_[5]\
    );
\burstCnt_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \burstCnt[6]_i_1__1_n_0\,
      Q => \burstCnt_reg_n_0_[6]\
    );
\burstCnt_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => burstCnt(7),
      Q => \burstCnt_reg_n_0_[7]\
    );
\burstCnt_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \burstCnt[8]_i_1__1_n_0\,
      Q => \burstCnt_reg_n_0_[8]\
    );
\burstCnt_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \burstCnt[9]_i_1__1_n_0\,
      Q => \burstCnt_reg_n_0_[9]\
    );
\capt_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \capt_reg[5]_0\(0),
      Q => capt(0)
    );
\capt_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \capt_reg[5]_0\(1),
      Q => capt(1)
    );
\capt_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \capt_reg[5]_0\(2),
      Q => capt(2)
    );
\capt_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \capt_reg[5]_0\(3),
      Q => capt(3)
    );
\capt_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \capt_reg[5]_0\(4),
      Q => capt(4)
    );
\capt_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \capt_reg[5]_0\(5),
      Q => capt(5)
    );
\dwrSeqbuf[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEAAFEAABAAAFEAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[20]_i_2_n_0\,
      I2 => \dwrSeqbuf[0]_i_2__1_n_0\,
      I3 => \aSeqbuf[8]_i_5__1_n_0\,
      I4 => \burstCnt_reg_n_0_[0]\,
      I5 => \burstCnt[15]_i_3__2_n_0\,
      O => \dwrSeqbuf[0]_i_1__1_n_0\
    );
\dwrSeqbuf[0]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[0]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(0),
      O => \dwrSeqbuf[0]_i_2__1_n_0\
    );
\dwrSeqbuf[10]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[31]_i_4__1_n_0\,
      I2 => \burstCnt[10]_i_2__2_n_0\,
      O => \dwrSeqbuf[10]_i_1__1_n_0\
    );
\dwrSeqbuf[11]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[31]_i_4__1_n_0\,
      I2 => \burstCnt[11]_i_2__1_n_0\,
      O => \dwrSeqbuf[11]_i_1__1_n_0\
    );
\dwrSeqbuf[12]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEEAEAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[31]_i_4__1_n_0\,
      I2 => \burstCnt[15]_i_3__2_n_0\,
      I3 => \burstCnt_reg_n_0_[12]\,
      I4 => \burstCnt[14]_i_2__1_n_0\,
      O => \dwrSeqbuf[12]_i_1__1_n_0\
    );
\dwrSeqbuf[13]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAEAAEAAAEAAAEA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[31]_i_4__1_n_0\,
      I2 => \burstCnt_reg_n_0_[13]\,
      I3 => \burstCnt[15]_i_3__2_n_0\,
      I4 => \burstCnt_reg_n_0_[12]\,
      I5 => \burstCnt[14]_i_2__1_n_0\,
      O => \dwrSeqbuf[13]_i_1__1_n_0\
    );
\dwrSeqbuf[14]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEEAEAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[31]_i_4__1_n_0\,
      I2 => \burstCnt[15]_i_3__2_n_0\,
      I3 => \burstCnt_reg_n_0_[14]\,
      I4 => \burstCnt[15]_i_4__1_n_0\,
      O => \dwrSeqbuf[14]_i_1__1_n_0\
    );
\dwrSeqbuf[15]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAEEEAEAEA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[31]_i_4__1_n_0\,
      I2 => \burstCnt_reg_n_0_[15]\,
      I3 => \burstCnt[15]_i_4__1_n_0\,
      I4 => \burstCnt_reg_n_0_[14]\,
      I5 => \burstCnt[15]_i_3__2_n_0\,
      O => \dwrSeqbuf[15]_i_1__1_n_0\
    );
\dwrSeqbuf[16]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAEAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \FSM_onehot_stateSeq[5]_i_6__1_n_0\,
      I2 => \FSM_onehot_stateSeq[5]_i_5__1_n_0\,
      I3 => capt(0),
      I4 => ackSeqbufBToSeqClear,
      I5 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \dwrSeqbuf[16]_i_1__1_n_0\
    );
\dwrSeqbuf[17]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \aSeqbuf[8]_i_5__1_n_0\,
      I2 => capt(1),
      O => \dwrSeqbuf[17]_i_1__1_n_0\
    );
\dwrSeqbuf[18]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAEAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \FSM_onehot_stateSeq[5]_i_6__1_n_0\,
      I2 => \FSM_onehot_stateSeq[5]_i_5__1_n_0\,
      I3 => capt(2),
      I4 => ackSeqbufBToSeqClear,
      I5 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \dwrSeqbuf[18]_i_1__1_n_0\
    );
\dwrSeqbuf[19]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \aSeqbuf[8]_i_5__1_n_0\,
      I2 => capt(3),
      O => \dwrSeqbuf[19]_i_1__1_n_0\
    );
\dwrSeqbuf[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[1]_i_2__1_n_0\,
      I2 => \dwrSeqbuf[20]_i_2_n_0\,
      I3 => \dwrSeqbuf[1]_i_3__1_n_0\,
      I4 => \aSeqbuf[8]_i_5__1_n_0\,
      O => \dwrSeqbuf[1]_i_1__1_n_0\
    );
\dwrSeqbuf[1]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EB"
    )
        port map (
      I0 => \burstCnt[2]_i_2_n_0\,
      I1 => \burstCnt_reg_n_0_[1]\,
      I2 => \burstCnt_reg_n_0_[0]\,
      O => \dwrSeqbuf[1]_i_2__1_n_0\
    );
\dwrSeqbuf[1]_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(1),
      O => \dwrSeqbuf[1]_i_3__1_n_0\
    );
\dwrSeqbuf[20]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => capt(4),
      I2 => \dwrSeqbuf[20]_i_2_n_0\,
      I3 => \aSeqbuf[8]_i_5__1_n_0\,
      I4 => \quad_reg_n_0_[20]\,
      I5 => \i_reg_n_0_[0]\,
      O => \dwrSeqbuf[20]_i_1__1_n_0\
    );
\dwrSeqbuf[20]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041000000000041"
    )
        port map (
      I0 => \dwrSeqbuf[20]_i_3_n_0\,
      I1 => capt(3),
      I2 => \dwrSeqbuf[3]_i_2__1_n_0\,
      I3 => \dwrSeqbuf[20]_i_4_n_0\,
      I4 => capt(0),
      I5 => \dwrSeqbuf[0]_i_2__1_n_0\,
      O => \dwrSeqbuf[20]_i_2_n_0\
    );
\dwrSeqbuf[20]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6F00F600"
    )
        port map (
      I0 => \quad_reg_n_0_[5]\,
      I1 => capt(5),
      I2 => \quad_reg_n_0_[4]\,
      I3 => \i_reg_n_0_[0]\,
      I4 => capt(4),
      O => \dwrSeqbuf[20]_i_3_n_0\
    );
\dwrSeqbuf[20]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6F00F600"
    )
        port map (
      I0 => \quad_reg_n_0_[2]\,
      I1 => capt(2),
      I2 => \quad_reg_n_0_[1]\,
      I3 => \i_reg_n_0_[0]\,
      I4 => capt(1),
      O => \dwrSeqbuf[20]_i_4_n_0\
    );
\dwrSeqbuf[21]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \aSeqbuf[8]_i_5__1_n_0\,
      I2 => capt(5),
      O => \dwrSeqbuf[21]_i_1__1_n_0\
    );
\dwrSeqbuf[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[2]_i_2__1_n_0\,
      I2 => \dwrSeqbuf[20]_i_2_n_0\,
      I3 => \dwrSeqbuf[2]_i_3__1_n_0\,
      I4 => \aSeqbuf[8]_i_5__1_n_0\,
      O => \dwrSeqbuf[2]_i_1__1_n_0\
    );
\dwrSeqbuf[2]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EABF"
    )
        port map (
      I0 => \burstCnt[2]_i_2_n_0\,
      I1 => \burstCnt_reg_n_0_[0]\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \burstCnt_reg_n_0_[2]\,
      O => \dwrSeqbuf[2]_i_2__1_n_0\
    );
\dwrSeqbuf[2]_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[2]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(2),
      O => \dwrSeqbuf[2]_i_3__1_n_0\
    );
\dwrSeqbuf[30]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"45444444"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_2_n_0\,
      I1 => \FSM_onehot_stateSeq[0]_i_2__0_n_0\,
      I2 => stateOp(0),
      I3 => stateOp(2),
      I4 => stateOp(1),
      O => \dwrSeqbuf[30]_i_1__1_n_0\
    );
\dwrSeqbuf[30]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => ackSeqbufBToSeqClear,
      I1 => rdySeq,
      I2 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I3 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \dwrSeqbuf[30]_i_2_n_0\
    );
\dwrSeqbuf[31]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABAAABAAABAAAA"
    )
        port map (
      I0 => \burstCnt[15]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[31]_i_3__1_n_0\,
      I2 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I3 => ackSeqbufBToSeqClear,
      I4 => rdySeq,
      I5 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      O => \dwrSeqbuf[31]_i_1__1_n_0\
    );
\dwrSeqbuf[31]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4__1_n_0\,
      I1 => \dwrSeqbuf[30]_i_1__1_n_0\,
      O => \dwrSeqbuf[31]_i_2__1_n_0\
    );
\dwrSeqbuf[31]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F111F1F1F1F1F1F"
    )
        port map (
      I0 => TCapt,
      I1 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I2 => \FSM_onehot_stateSeq[0]_i_2__0_n_0\,
      I3 => stateOp(0),
      I4 => stateOp(2),
      I5 => stateOp(1),
      O => \dwrSeqbuf[31]_i_3__1_n_0\
    );
\dwrSeqbuf[31]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \dwrSeqbuf[20]_i_2_n_0\,
      I1 => ackSeqbufBToSeqClear,
      I2 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I3 => rdySeq,
      I4 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I5 => TCapt,
      O => \dwrSeqbuf[31]_i_4__1_n_0\
    );
\dwrSeqbuf[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BAAAFEAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[20]_i_2_n_0\,
      I2 => \dwrSeqbuf[3]_i_2__1_n_0\,
      I3 => \aSeqbuf[8]_i_5__1_n_0\,
      I4 => \dwrSeqbuf[3]_i_3__1_n_0\,
      O => \dwrSeqbuf[3]_i_1__1_n_0\
    );
\dwrSeqbuf[3]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[3]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(3),
      O => \dwrSeqbuf[3]_i_2__1_n_0\
    );
\dwrSeqbuf[3]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAABFFF"
    )
        port map (
      I0 => \burstCnt[15]_i_3__2_n_0\,
      I1 => \burstCnt_reg_n_0_[2]\,
      I2 => \burstCnt_reg_n_0_[0]\,
      I3 => \burstCnt_reg_n_0_[1]\,
      I4 => \burstCnt_reg_n_0_[3]\,
      O => \dwrSeqbuf[3]_i_3__1_n_0\
    );
\dwrSeqbuf[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \burstCnt[4]_i_2__1_n_0\,
      I2 => \dwrSeqbuf[20]_i_2_n_0\,
      I3 => \dwrSeqbuf[4]_i_2__1_n_0\,
      I4 => \aSeqbuf[8]_i_5__1_n_0\,
      O => \dwrSeqbuf[4]_i_1__1_n_0\
    );
\dwrSeqbuf[4]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[4]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(4),
      O => \dwrSeqbuf[4]_i_2__1_n_0\
    );
\dwrSeqbuf[5]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BAAAFEAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[20]_i_2_n_0\,
      I2 => \dwrSeqbuf[5]_i_2__1_n_0\,
      I3 => \aSeqbuf[8]_i_5__1_n_0\,
      I4 => \burstCnt[5]_i_2__1_n_0\,
      O => \dwrSeqbuf[5]_i_1__1_n_0\
    );
\dwrSeqbuf[5]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[5]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(5),
      O => \dwrSeqbuf[5]_i_2__1_n_0\
    );
\dwrSeqbuf[6]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAEAAAEAEEAEAAEA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[31]_i_4__1_n_0\,
      I2 => \burstCnt_reg_n_0_[6]\,
      I3 => \burstCnt[15]_i_3__2_n_0\,
      I4 => \burstCnt_reg_n_0_[5]\,
      I5 => \burstCnt[7]_i_2__2_n_0\,
      O => \dwrSeqbuf[6]_i_1__1_n_0\
    );
\dwrSeqbuf[7]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[7]_i_2__1_n_0\,
      I2 => \dwrSeqbuf[31]_i_4__1_n_0\,
      O => \dwrSeqbuf[7]_i_1__1_n_0\
    );
\dwrSeqbuf[7]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDDEDDD"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[7]\,
      I1 => \burstCnt[15]_i_3__2_n_0\,
      I2 => \burstCnt_reg_n_0_[6]\,
      I3 => \burstCnt_reg_n_0_[5]\,
      I4 => \burstCnt[7]_i_2__2_n_0\,
      O => \dwrSeqbuf[7]_i_2__1_n_0\
    );
\dwrSeqbuf[8]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I1 => \dwrSeqbuf[31]_i_4__1_n_0\,
      I2 => \burstCnt[8]_i_2__2_n_0\,
      O => \dwrSeqbuf[8]_i_1__1_n_0\
    );
\dwrSeqbuf[9]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF2310FFFF0000"
    )
        port map (
      I0 => \burstCnt[9]_i_2__1_n_0\,
      I1 => \burstCnt[15]_i_3__2_n_0\,
      I2 => \burstCnt_reg_n_0_[8]\,
      I3 => \burstCnt_reg_n_0_[9]\,
      I4 => \dwrSeqbuf[30]_i_1__1_n_0\,
      I5 => \dwrSeqbuf[31]_i_4__1_n_0\,
      O => \dwrSeqbuf[9]_i_1__1_n_0\
    );
\dwrSeqbuf_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[0]_i_1__1_n_0\,
      Q => dwrSeqbuf(0)
    );
\dwrSeqbuf_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[10]_i_1__1_n_0\,
      Q => dwrSeqbuf(10)
    );
\dwrSeqbuf_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[11]_i_1__1_n_0\,
      Q => dwrSeqbuf(11)
    );
\dwrSeqbuf_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[12]_i_1__1_n_0\,
      Q => dwrSeqbuf(12)
    );
\dwrSeqbuf_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[13]_i_1__1_n_0\,
      Q => dwrSeqbuf(13)
    );
\dwrSeqbuf_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[14]_i_1__1_n_0\,
      Q => dwrSeqbuf(14)
    );
\dwrSeqbuf_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[15]_i_1__1_n_0\,
      Q => dwrSeqbuf(15)
    );
\dwrSeqbuf_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[16]_i_1__1_n_0\,
      Q => dwrSeqbuf(16)
    );
\dwrSeqbuf_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[17]_i_1__1_n_0\,
      Q => dwrSeqbuf(17)
    );
\dwrSeqbuf_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[18]_i_1__1_n_0\,
      Q => dwrSeqbuf(18)
    );
\dwrSeqbuf_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[19]_i_1__1_n_0\,
      Q => dwrSeqbuf(19)
    );
\dwrSeqbuf_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[1]_i_1__1_n_0\,
      Q => dwrSeqbuf(1)
    );
\dwrSeqbuf_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[20]_i_1__1_n_0\,
      Q => dwrSeqbuf(20)
    );
\dwrSeqbuf_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[21]_i_1__1_n_0\,
      Q => dwrSeqbuf(21)
    );
\dwrSeqbuf_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[2]_i_1__1_n_0\,
      Q => dwrSeqbuf(2)
    );
\dwrSeqbuf_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[30]_i_1__1_n_0\,
      Q => dwrSeqbuf(30)
    );
\dwrSeqbuf_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[31]_i_2__1_n_0\,
      Q => dwrSeqbuf(31)
    );
\dwrSeqbuf_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[3]_i_1__1_n_0\,
      Q => dwrSeqbuf(3)
    );
\dwrSeqbuf_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[4]_i_1__1_n_0\,
      Q => dwrSeqbuf(4)
    );
\dwrSeqbuf_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[5]_i_1__1_n_0\,
      Q => dwrSeqbuf(5)
    );
\dwrSeqbuf_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[6]_i_1__1_n_0\,
      Q => dwrSeqbuf(6)
    );
\dwrSeqbuf_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[7]_i_1__1_n_0\,
      Q => dwrSeqbuf(7)
    );
\dwrSeqbuf_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[8]_i_1__1_n_0\,
      Q => dwrSeqbuf(8)
    );
\dwrSeqbuf_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \dwrSeqbuf[9]_i_1__1_n_0\,
      Q => dwrSeqbuf(9)
    );
\enSeqbuf_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => first,
      O => enSeqbuf
    );
enSeqbuf_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => enSeqbuf,
      Q => enSeqbuf_reg_n_0
    );
first_reg: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      D => first,
      PRE => enSeqbuf_reg_0(0),
      Q => \first__0\
    );
\i[0]_i_1__20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88FF0700"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[3]_i_2__2_n_0\,
      I1 => TCapt,
      I2 => first,
      I3 => \dwrSeqbuf[30]_i_2_n_0\,
      I4 => \i_reg_n_0_[0]\,
      O => \i[0]_i_1__20_n_0\
    );
\i__carry__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(31),
      I1 => \TCaptMax_reg_n_0_[31]\,
      I2 => \^q\(30),
      I3 => \TCaptMax_reg_n_0_[30]\,
      O => \i__carry__0_i_1_n_0\
    );
\i__carry__0_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[29]\,
      I1 => \^q\(29),
      I2 => \TCaptMax_reg_n_0_[28]\,
      I3 => \^q\(28),
      O => \i__carry__0_i_10_n_0\
    );
\i__carry__0_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[27]\,
      I1 => \^q\(27),
      I2 => \TCaptMax_reg_n_0_[26]\,
      I3 => \^q\(26),
      O => \i__carry__0_i_11_n_0\
    );
\i__carry__0_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[25]\,
      I1 => \^q\(25),
      I2 => \TCaptMax_reg_n_0_[24]\,
      I3 => \^q\(24),
      O => \i__carry__0_i_12_n_0\
    );
\i__carry__0_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[23]\,
      I1 => \^q\(23),
      I2 => \TCaptMax_reg_n_0_[22]\,
      I3 => \^q\(22),
      O => \i__carry__0_i_13_n_0\
    );
\i__carry__0_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[21]\,
      I1 => \^q\(21),
      I2 => \TCaptMax_reg_n_0_[20]\,
      I3 => \^q\(20),
      O => \i__carry__0_i_14_n_0\
    );
\i__carry__0_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[19]\,
      I1 => \^q\(19),
      I2 => \TCaptMax_reg_n_0_[18]\,
      I3 => \^q\(18),
      O => \i__carry__0_i_15_n_0\
    );
\i__carry__0_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[17]\,
      I1 => \^q\(17),
      I2 => \TCaptMax_reg_n_0_[16]\,
      I3 => \^q\(16),
      O => \i__carry__0_i_16_n_0\
    );
\i__carry__0_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(29),
      I1 => \TCaptMax_reg_n_0_[29]\,
      I2 => \^q\(28),
      I3 => \TCaptMax_reg_n_0_[28]\,
      O => \i__carry__0_i_2_n_0\
    );
\i__carry__0_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(27),
      I1 => \TCaptMax_reg_n_0_[27]\,
      I2 => \^q\(26),
      I3 => \TCaptMax_reg_n_0_[26]\,
      O => \i__carry__0_i_3_n_0\
    );
\i__carry__0_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(25),
      I1 => \TCaptMax_reg_n_0_[25]\,
      I2 => \^q\(24),
      I3 => \TCaptMax_reg_n_0_[24]\,
      O => \i__carry__0_i_4_n_0\
    );
\i__carry__0_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(23),
      I1 => \TCaptMax_reg_n_0_[23]\,
      I2 => \^q\(22),
      I3 => \TCaptMax_reg_n_0_[22]\,
      O => \i__carry__0_i_5_n_0\
    );
\i__carry__0_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(21),
      I1 => \TCaptMax_reg_n_0_[21]\,
      I2 => \^q\(20),
      I3 => \TCaptMax_reg_n_0_[20]\,
      O => \i__carry__0_i_6_n_0\
    );
\i__carry__0_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(19),
      I1 => \TCaptMax_reg_n_0_[19]\,
      I2 => \^q\(18),
      I3 => \TCaptMax_reg_n_0_[18]\,
      O => \i__carry__0_i_7_n_0\
    );
\i__carry__0_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(17),
      I1 => \TCaptMax_reg_n_0_[17]\,
      I2 => \^q\(16),
      I3 => \TCaptMax_reg_n_0_[16]\,
      O => \i__carry__0_i_8_n_0\
    );
\i__carry__0_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[31]\,
      I1 => \^q\(31),
      I2 => \TCaptMax_reg_n_0_[30]\,
      I3 => \^q\(30),
      O => \i__carry__0_i_9_n_0\
    );
\i__carry_i_10__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[13]\,
      I1 => \^q\(13),
      I2 => \TCaptMax_reg_n_0_[12]\,
      I3 => \^q\(12),
      O => \i__carry_i_10__4_n_0\
    );
\i__carry_i_11__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[11]\,
      I1 => \^q\(11),
      I2 => \TCaptMax_reg_n_0_[10]\,
      I3 => \^q\(10),
      O => \i__carry_i_11__3_n_0\
    );
\i__carry_i_12__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[9]\,
      I1 => \^q\(9),
      I2 => \TCaptMax_reg_n_0_[8]\,
      I3 => \^q\(8),
      O => \i__carry_i_12__1_n_0\
    );
\i__carry_i_13__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[7]\,
      I1 => \^q\(7),
      I2 => \TCaptMax_reg_n_0_[6]\,
      I3 => \^q\(6),
      O => \i__carry_i_13__0_n_0\
    );
\i__carry_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[5]\,
      I1 => \^q\(5),
      I2 => \TCaptMax_reg_n_0_[4]\,
      I3 => \^q\(4),
      O => \i__carry_i_14_n_0\
    );
\i__carry_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[3]\,
      I1 => \^q\(3),
      I2 => \TCaptMax_reg_n_0_[2]\,
      I3 => \^q\(2),
      O => \i__carry_i_15_n_0\
    );
\i__carry_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[1]\,
      I1 => \^q\(1),
      I2 => \TCaptMax_reg_n_0_[0]\,
      I3 => \^q\(0),
      O => \i__carry_i_16_n_0\
    );
\i__carry_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(15),
      I1 => \TCaptMax_reg_n_0_[15]\,
      I2 => \^q\(14),
      I3 => \TCaptMax_reg_n_0_[14]\,
      O => \i__carry_i_1__5_n_0\
    );
\i__carry_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(13),
      I1 => \TCaptMax_reg_n_0_[13]\,
      I2 => \^q\(12),
      I3 => \TCaptMax_reg_n_0_[12]\,
      O => \i__carry_i_2__5_n_0\
    );
\i__carry_i_3__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(11),
      I1 => \TCaptMax_reg_n_0_[11]\,
      I2 => \^q\(10),
      I3 => \TCaptMax_reg_n_0_[10]\,
      O => \i__carry_i_3__5_n_0\
    );
\i__carry_i_4__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(9),
      I1 => \TCaptMax_reg_n_0_[9]\,
      I2 => \^q\(8),
      I3 => \TCaptMax_reg_n_0_[8]\,
      O => \i__carry_i_4__5_n_0\
    );
\i__carry_i_5__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(7),
      I1 => \TCaptMax_reg_n_0_[7]\,
      I2 => \^q\(6),
      I3 => \TCaptMax_reg_n_0_[6]\,
      O => \i__carry_i_5__5_n_0\
    );
\i__carry_i_6__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(5),
      I1 => \TCaptMax_reg_n_0_[5]\,
      I2 => \^q\(4),
      I3 => \TCaptMax_reg_n_0_[4]\,
      O => \i__carry_i_6__5_n_0\
    );
\i__carry_i_7__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(3),
      I1 => \TCaptMax_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \TCaptMax_reg_n_0_[2]\,
      O => \i__carry_i_7__4_n_0\
    );
\i__carry_i_8__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(1),
      I1 => \TCaptMax_reg_n_0_[1]\,
      I2 => \^q\(0),
      I3 => \TCaptMax_reg_n_0_[0]\,
      O => \i__carry_i_8__4_n_0\
    );
\i__carry_i_9__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[15]\,
      I1 => \^q\(15),
      I2 => \TCaptMax_reg_n_0_[14]\,
      I3 => \^q\(14),
      O => \i__carry_i_9__4_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \i[0]_i_1__20_n_0\,
      Q => \i_reg_n_0_[0]\
    );
\mask_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \mask_reg[0]_1\,
      Q => \mask_reg[0]_0\
    );
\mask_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \mask_reg[1]_1\,
      Q => \mask_reg[1]_0\
    );
\mask_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \mask_reg[2]_1\,
      Q => \mask_reg[2]_0\
    );
\mask_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \mask_reg[3]_1\,
      Q => \mask_reg[3]_0\
    );
\mask_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \mask_reg[4]_1\,
      Q => \mask_reg[4]_0\
    );
\mask_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \mask_reg[5]_1\,
      Q => \mask_reg[5]_0\
    );
mySeqbuf: entity work.\design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__2\
     port map (
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(23 downto 22) => dwrSeqbuf(31 downto 30),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(21 downto 0) => dwrSeqbuf(21 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8) => \aSeqbufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \aSeqbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \aSeqbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \aSeqbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \aSeqbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \aSeqbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \aSeqbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \aSeqbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \aSeqbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2 downto 0) => stateSeqbufB_reg(2 downto 0),
      Q(9) => \aSeqbuf_reg_n_0_[9]\,
      Q(8) => \aSeqbuf_reg_n_0_[8]\,
      Q(7) => \aSeqbuf_reg_n_0_[7]\,
      Q(6) => \aSeqbuf_reg_n_0_[6]\,
      Q(5) => \aSeqbuf_reg_n_0_[5]\,
      Q(4) => \aSeqbuf_reg_n_0_[4]\,
      Q(3) => \aSeqbuf_reg_n_0_[3]\,
      Q(2) => \aSeqbuf_reg_n_0_[2]\,
      Q(1) => \aSeqbuf_reg_n_0_[1]\,
      Q(0) => \aSeqbuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      doutb(63 downto 0) => doutb(63 downto 0),
      ena => enSeqbuf_reg_n_0
    );
plusOp_carry: unisim.vcomponents.CARRY8
     port map (
      CI => \^q\(0),
      CI_TOP => '0',
      CO(7) => plusOp_carry_n_0,
      CO(6) => plusOp_carry_n_1,
      CO(5) => plusOp_carry_n_2,
      CO(4) => plusOp_carry_n_3,
      CO(3) => plusOp_carry_n_4,
      CO(2) => plusOp_carry_n_5,
      CO(1) => plusOp_carry_n_6,
      CO(0) => plusOp_carry_n_7,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in12(8 downto 1),
      S(7 downto 0) => \^q\(8 downto 1)
    );
\plusOp_carry__0\: unisim.vcomponents.CARRY8
     port map (
      CI => plusOp_carry_n_0,
      CI_TOP => '0',
      CO(7) => \plusOp_carry__0_n_0\,
      CO(6) => \plusOp_carry__0_n_1\,
      CO(5) => \plusOp_carry__0_n_2\,
      CO(4) => \plusOp_carry__0_n_3\,
      CO(3) => \plusOp_carry__0_n_4\,
      CO(2) => \plusOp_carry__0_n_5\,
      CO(1) => \plusOp_carry__0_n_6\,
      CO(0) => \plusOp_carry__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in12(16 downto 9),
      S(7 downto 0) => \^q\(16 downto 9)
    );
\plusOp_carry__1\: unisim.vcomponents.CARRY8
     port map (
      CI => \plusOp_carry__0_n_0\,
      CI_TOP => '0',
      CO(7) => \plusOp_carry__1_n_0\,
      CO(6) => \plusOp_carry__1_n_1\,
      CO(5) => \plusOp_carry__1_n_2\,
      CO(4) => \plusOp_carry__1_n_3\,
      CO(3) => \plusOp_carry__1_n_4\,
      CO(2) => \plusOp_carry__1_n_5\,
      CO(1) => \plusOp_carry__1_n_6\,
      CO(0) => \plusOp_carry__1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in12(24 downto 17),
      S(7 downto 0) => \^q\(24 downto 17)
    );
\plusOp_carry__2\: unisim.vcomponents.CARRY8
     port map (
      CI => \plusOp_carry__1_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_plusOp_carry__2_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \plusOp_carry__2_n_2\,
      CO(4) => \plusOp_carry__2_n_3\,
      CO(3) => \plusOp_carry__2_n_4\,
      CO(2) => \plusOp_carry__2_n_5\,
      CO(1) => \plusOp_carry__2_n_6\,
      CO(0) => \plusOp_carry__2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NLW_plusOp_carry__2_O_UNCONNECTED\(7),
      O(6 downto 0) => in12(31 downto 25),
      S(7) => '0',
      S(6 downto 0) => \^q\(31 downto 25)
    );
\ptr0SeqbufTrackNotFixed_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2F2F2FFF20202000"
    )
        port map (
      I0 => \burstCnt[2]_i_2_n_0\,
      I1 => first,
      I2 => \aSeqbuf[9]_i_3__1_n_0\,
      I3 => \aSeqbuf[9]_i_4__2_n_0\,
      I4 => \FSM_onehot_stateSeq[5]_i_5__1_n_0\,
      I5 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => \ptr0SeqbufTrackNotFixed_i_1__1_n_0\
    );
ptr0SeqbufTrackNotFixed_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \ptr0SeqbufTrackNotFixed_i_1__1_n_0\,
      Q => ptr0SeqbufTrackNotFixed_reg_n_0
    );
\quad[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(0),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[0]\,
      I3 => first,
      O => quad(0)
    );
\quad[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(1),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[1]\,
      I3 => first,
      O => quad(1)
    );
\quad[20]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => \quad_reg_n_0_[20]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(4),
      I3 => first,
      O => quad(20)
    );
\quad[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(2),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[2]\,
      I3 => first,
      O => quad(2)
    );
\quad[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(3),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[3]\,
      I3 => first,
      O => quad(3)
    );
\quad[4]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(4),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[4]\,
      I3 => first,
      O => quad(4)
    );
\quad[5]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010001"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => rdySeq,
      I2 => ackSeqbufBToSeqClear,
      I3 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I4 => TCapt,
      I5 => \i_reg_n_0_[0]\,
      O => \quad[5]_i_1__1_n_0\
    );
\quad[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(5),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[5]\,
      I3 => first,
      O => quad(5)
    );
\quad_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[5]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => quad(0),
      Q => \quad_reg_n_0_[0]\
    );
\quad_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[5]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => quad(1),
      Q => \quad_reg_n_0_[1]\
    );
\quad_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => quad(20),
      Q => \quad_reg_n_0_[20]\
    );
\quad_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[5]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => quad(2),
      Q => \quad_reg_n_0_[2]\
    );
\quad_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[5]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => quad(3),
      Q => \quad_reg_n_0_[3]\
    );
\quad_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[5]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => quad(4),
      Q => \quad_reg_n_0_[4]\
    );
\quad_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[5]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => quad(5),
      Q => \quad_reg_n_0_[5]\
    );
\restart_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF300000050"
    )
        port map (
      I0 => restart_reg_0,
      I1 => restart_reg_1,
      I2 => stateOp(0),
      I3 => stateOp(1),
      I4 => stateOp(2),
      I5 => restart_reg_n_0,
      O => \restart_i_1__1_n_0\
    );
restart_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \restart_i_1__1_n_0\,
      Q => restart_reg_n_0
    );
\retbuf[0][0]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"24"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(1),
      I2 => stateOp(2),
      O => \^hshktrackgetinfotixvstate\(0)
    );
\retbuf[5][0]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[8]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => hshktrackGetInfoPtr0Seqbuf(8)
    );
\retbuf[5][1]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[9]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => hshktrackGetInfoPtr0Seqbuf(9)
    );
\retbuf[6][0]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[0]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => hshktrackGetInfoPtr0Seqbuf(0)
    );
\retbuf[6][1]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[1]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => hshktrackGetInfoPtr0Seqbuf(1)
    );
\retbuf[6][2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[2]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => hshktrackGetInfoPtr0Seqbuf(2)
    );
\retbuf[6][3]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[3]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => hshktrackGetInfoPtr0Seqbuf(3)
    );
\retbuf[6][4]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[4]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => hshktrackGetInfoPtr0Seqbuf(4)
    );
\retbuf[6][5]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[5]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => hshktrackGetInfoPtr0Seqbuf(5)
    );
\retbuf[6][6]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[6]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => hshktrackGetInfoPtr0Seqbuf(6)
    );
\retbuf[6][7]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[7]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => hshktrackGetInfoPtr0Seqbuf(7)
    );
rng_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => rng_reg_1,
      Q => \^rng_reg_0\
    );
\staTixVTrigger[7]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"01FD"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(1),
      I2 => stateOp(2),
      I3 => restart_reg_1,
      O => \^stateop_reg[0]_0\
    );
\staTixVTrigger_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => D(0),
      Q => \staTixVTrigger_reg_n_0_[0]\
    );
\staTixVTrigger_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => D(1),
      Q => \staTixVTrigger_reg_n_0_[1]\
    );
\staTixVTrigger_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => D(2),
      Q => \staTixVTrigger_reg_n_0_[2]\
    );
\staTixVTrigger_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => D(3),
      Q => \staTixVTrigger_reg_n_0_[3]\
    );
\staTixVTrigger_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => D(4),
      Q => \staTixVTrigger_reg_n_0_[4]\
    );
\staTixVTrigger_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => D(5),
      Q => \staTixVTrigger_reg_n_0_[5]\
    );
\staTixVTrigger_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => D(6),
      Q => \staTixVTrigger_reg_n_0_[6]\
    );
\staTixVTrigger_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => D(7),
      Q => \staTixVTrigger_reg_n_0_[7]\
    );
\stateOp[0]_i_1__11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"577D"
    )
        port map (
      I0 => restart_reg_1,
      I1 => stateOp(1),
      I2 => stateOp(2),
      I3 => stateOp(0),
      O => \stateOp[0]_i_1__11_n_0\
    );
\stateOp[1]_i_1__11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C32000000320000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => stateOp(0),
      I2 => stateOp(1),
      I3 => stateOp(2),
      I4 => restart_reg_1,
      I5 => restart_reg_n_0,
      O => \stateOp[1]_i_1__11_n_0\
    );
\stateOp[2]_i_10__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A88AAAA8A888A88"
    )
        port map (
      I0 => stateOp(0),
      I1 => \ackInvSet_sig_i_2__3_0\,
      I2 => reqInvHshktrackSet,
      I3 => \^ackinvhshktrackset\,
      I4 => reqInvHshktrackClearMask,
      I5 => \^ackinvhshktrackclearmask\,
      O => \stateOp[2]_i_10__2_n_0\
    );
\stateOp[2]_i_11__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(2),
      I2 => stateOp(1),
      O => \stateOp[2]_i_11__3_n_0\
    );
\stateOp[2]_i_12__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[21]\,
      I1 => \TCaptMax_reg_n_0_[20]\,
      I2 => \TCaptMax_reg_n_0_[23]\,
      I3 => \TCaptMax_reg_n_0_[22]\,
      O => \stateOp[2]_i_12__1_n_0\
    );
\stateOp[2]_i_13__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[24]\,
      I1 => \TCaptMax_reg_n_0_[27]\,
      I2 => \TCaptMax_reg_n_0_[25]\,
      I3 => \TCaptMax_reg_n_0_[26]\,
      I4 => \stateOp[2]_i_21__1_n_0\,
      O => \stateOp[2]_i_13__2_n_0\
    );
\stateOp[2]_i_14__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[5]\,
      I1 => \TCaptMax_reg_n_0_[4]\,
      I2 => \TCaptMax_reg_n_0_[7]\,
      I3 => \TCaptMax_reg_n_0_[6]\,
      O => \stateOp[2]_i_14__1_n_0\
    );
\stateOp[2]_i_15__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[8]\,
      I1 => \TCaptMax_reg_n_0_[11]\,
      I2 => \TCaptMax_reg_n_0_[9]\,
      I3 => \TCaptMax_reg_n_0_[10]\,
      I4 => \stateOp[2]_i_22__1_n_0\,
      O => \stateOp[2]_i_15__2_n_0\
    );
\stateOp[2]_i_16__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \^q\(30),
      I1 => \^q\(31),
      I2 => \^q\(28),
      I3 => \^q\(29),
      I4 => \^q\(27),
      I5 => \^q\(24),
      O => \stateOp[2]_i_16__2_n_0\
    );
\stateOp[2]_i_17__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(20),
      I1 => \^q\(23),
      I2 => \^q\(21),
      I3 => \^q\(22),
      I4 => \^q\(19),
      I5 => \^q\(16),
      O => \stateOp[2]_i_17__2_n_0\
    );
\stateOp[2]_i_18__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \^q\(10),
      I1 => \^q\(9),
      I2 => \^q\(17),
      I3 => \^q\(18),
      I4 => \^q\(25),
      I5 => \^q\(26),
      O => \stateOp[2]_i_18__2_n_0\
    );
\stateOp[2]_i_19__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \^q\(14),
      I1 => \^q\(15),
      I2 => \^q\(12),
      I3 => \^q\(13),
      I4 => \^q\(11),
      I5 => \^q\(8),
      O => \stateOp[2]_i_19__2_n_0\
    );
\stateOp[2]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFE0E0E040"
    )
        port map (
      I0 => stateOp(0),
      I1 => \stateOp[2]_i_3__3_n_0\,
      I2 => \^hshktrackgetinfotixvstate\(1),
      I3 => rdySeq,
      I4 => restart_reg_n_0,
      I5 => \stateOp[2]_i_5__3_n_0\,
      O => \stateOp[2]_i_1__4_n_0\
    );
\stateOp[2]_i_20__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \staTixVTrigger_reg_n_0_[5]\,
      I1 => \staTixVTrigger_reg_n_0_[2]\,
      I2 => \staTixVTrigger_reg_n_0_[1]\,
      I3 => \staTixVTrigger_reg_n_0_[6]\,
      I4 => \staTixVTrigger_reg_n_0_[3]\,
      I5 => \staTixVTrigger_reg_n_0_[4]\,
      O => \stateOp[2]_i_20__2_n_0\
    );
\stateOp[2]_i_21__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[29]\,
      I1 => \TCaptMax_reg_n_0_[28]\,
      I2 => \TCaptMax_reg_n_0_[31]\,
      I3 => \TCaptMax_reg_n_0_[30]\,
      O => \stateOp[2]_i_21__1_n_0\
    );
\stateOp[2]_i_22__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[13]\,
      I1 => \TCaptMax_reg_n_0_[12]\,
      I2 => \TCaptMax_reg_n_0_[15]\,
      I3 => \TCaptMax_reg_n_0_[14]\,
      O => \stateOp[2]_i_22__1_n_0\
    );
\stateOp[2]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004E46"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(0),
      I2 => stateOp(1),
      I3 => restart_reg_n_0,
      I4 => \^stateop_reg[0]_0\,
      O => \stateOp[2]_i_2__3_n_0\
    );
\stateOp[2]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF54545400"
    )
        port map (
      I0 => stop_lcl_i_3_n_0,
      I1 => \strbStop5_inferred__0/i__carry__0_n_0\,
      I2 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I3 => \stateOp[2]_i_6__1_n_0\,
      I4 => \stateOp[2]_i_7__2_n_0\,
      I5 => \stateOp[2]_i_8__2_n_0\,
      O => \stateOp[2]_i_3__3_n_0\
    );
\stateOp[2]_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(1),
      O => \^hshktrackgetinfotixvstate\(1)
    );
\stateOp[2]_i_5__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF545454"
    )
        port map (
      I0 => \stateOp[2]_i_9__0_n_0\,
      I1 => stateOp(1),
      I2 => \stateOp[2]_i_10__2_n_0\,
      I3 => rdySeq,
      I4 => \stateOp[2]_i_11__3_n_0\,
      I5 => \^stateop_reg[0]_0\,
      O => \stateOp[2]_i_5__3_n_0\
    );
\stateOp[2]_i_6__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \stateOp[2]_i_12__1_n_0\,
      I1 => \TCaptMax_reg_n_0_[19]\,
      I2 => \TCaptMax_reg_n_0_[18]\,
      I3 => \TCaptMax_reg_n_0_[17]\,
      I4 => \TCaptMax_reg_n_0_[16]\,
      I5 => \stateOp[2]_i_13__2_n_0\,
      O => \stateOp[2]_i_6__1_n_0\
    );
\stateOp[2]_i_7__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \stateOp[2]_i_14__1_n_0\,
      I1 => \TCaptMax_reg_n_0_[2]\,
      I2 => \TCaptMax_reg_n_0_[1]\,
      I3 => \TCaptMax_reg_n_0_[3]\,
      I4 => \TCaptMax_reg_n_0_[0]\,
      I5 => \stateOp[2]_i_15__2_n_0\,
      O => \stateOp[2]_i_7__2_n_0\
    );
\stateOp[2]_i_8__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \stateOp[2]_i_16__2_n_0\,
      I1 => \stateOp[2]_i_17__2_n_0\,
      I2 => \stateOp[2]_i_18__2_n_0\,
      I3 => \stateOp[2]_i_19__2_n_0\,
      O => \stateOp[2]_i_8__2_n_0\
    );
\stateOp[2]_i_9__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF55FF54"
    )
        port map (
      I0 => stateOp(0),
      I1 => \stateOp[2]_i_20__2_n_0\,
      I2 => \staTixVTrigger_reg_n_0_[7]\,
      I3 => stateOp(2),
      I4 => \staTixVTrigger_reg_n_0_[0]\,
      O => \stateOp[2]_i_9__0_n_0\
    );
\stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[2]_i_1__4_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \stateOp[0]_i_1__11_n_0\,
      Q => stateOp(0)
    );
\stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[2]_i_1__4_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \stateOp[1]_i_1__11_n_0\,
      Q => stateOp(1)
    );
\stateOp_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[2]_i_1__4_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \stateOp[2]_i_2__3_n_0\,
      Q => stateOp(2)
    );
\stateSeqbufB[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0705"
    )
        port map (
      I0 => stateSeqbufB_reg(2),
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      I3 => dneSeqbufHshktrackToHostif,
      O => \p_0_in__0\(0)
    );
\stateSeqbufB[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00BC"
    )
        port map (
      I0 => \stateSeqbufB[1]_i_2__1_n_0\,
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      I3 => stateSeqbufB_reg(2),
      O => \p_0_in__0\(1)
    );
\stateSeqbufB[1]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAAAAAA"
    )
        port map (
      I0 => seqbufHshktrackToHostifAXIS_tready,
      I1 => \aSeqbufB_reg_n_0_[8]\,
      I2 => \aSeqbufB_reg_n_0_[6]\,
      I3 => \aSeqbufB[8]_i_4__1_n_0\,
      I4 => \aSeqbufB_reg_n_0_[7]\,
      O => \stateSeqbufB[1]_i_2__1_n_0\
    );
\stateSeqbufB[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBABBABBBBABB"
    )
        port map (
      I0 => \stateSeqbufB[2]_i_3__1_n_0\,
      I1 => stateSeqbufB_reg(2),
      I2 => reqSeqbufHshktrackToHostif,
      I3 => stateSeqbufB_reg(0),
      I4 => stateSeqbufB_reg(1),
      I5 => seqbufHshktrackToHostifAXIS_tready,
      O => \stateSeqbufB[2]_i_1__1_n_0\
    );
\stateSeqbufB[2]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000AC000000A0000"
    )
        port map (
      I0 => dneSeqbufHshktrackToHostif,
      I1 => \stateSeqbufB[2]_i_7__1_n_0\,
      I2 => stateSeqbufB_reg(1),
      I3 => stateSeqbufB_reg(0),
      I4 => stateSeqbufB_reg(2),
      I5 => seqbufHshktrackToHostifAXIS_tready,
      O => \p_0_in__0\(2)
    );
\stateSeqbufB[2]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000C088CC"
    )
        port map (
      I0 => dneSeqbufHshktrackToHostif,
      I1 => stateSeqbufB_reg(2),
      I2 => ackSeqbufBToSeqClear,
      I3 => reqSeqbufHshktrackToHostif,
      I4 => stateSeqbufB_reg(0),
      I5 => stateSeqbufB_reg(1),
      O => \stateSeqbufB[2]_i_3__1_n_0\
    );
\stateSeqbufB[2]_i_7__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[7]\,
      I1 => \aSeqbufB[8]_i_4__1_n_0\,
      I2 => \aSeqbufB_reg_n_0_[6]\,
      I3 => \aSeqbufB_reg_n_0_[8]\,
      O => \stateSeqbufB[2]_i_7__1_n_0\
    );
\stateSeqbufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSeqbufB[2]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \p_0_in__0\(0),
      Q => stateSeqbufB_reg(0)
    );
\stateSeqbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSeqbufB[2]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \p_0_in__0\(1),
      Q => stateSeqbufB_reg(1)
    );
\stateSeqbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSeqbufB[2]_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \p_0_in__0\(2),
      Q => stateSeqbufB_reg(2)
    );
\stoTixVTrigger_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(8),
      Q => stoTixVTrigger(0)
    );
\stoTixVTrigger_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(9),
      Q => stoTixVTrigger(1)
    );
\stoTixVTrigger_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(10),
      Q => stoTixVTrigger(2)
    );
\stoTixVTrigger_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(11),
      Q => stoTixVTrigger(3)
    );
\stoTixVTrigger_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(12),
      Q => stoTixVTrigger(4)
    );
\stoTixVTrigger_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(13),
      Q => stoTixVTrigger(5)
    );
\stoTixVTrigger_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(14),
      Q => stoTixVTrigger(6)
    );
\stoTixVTrigger_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enSeqbuf_reg_0(0),
      D => \TCaptMax_reg[31]_0\(15),
      Q => stoTixVTrigger(7)
    );
\stop_lcl_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAAB"
    )
        port map (
      I0 => TCapt,
      I1 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I2 => \^fsm_onehot_stateseq_reg[3]_0\(0),
      I3 => rdySeq,
      I4 => ackSeqbufBToSeqClear,
      O => \stop_lcl_i_1__1_n_0\
    );
\stop_lcl_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFF10"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => stop_lcl_i_3_n_0,
      I2 => \aSeqbuf[9]_i_4__2_n_0\,
      I3 => strbStop_reg_n_0,
      I4 => stop_lcl_reg_n_0,
      I5 => first,
      O => \stop_lcl_i_2__2_n_0\
    );
stop_lcl_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => stoTixVTrigger(3),
      I1 => stoTixVTrigger(1),
      I2 => stoTixVTrigger(4),
      I3 => stoTixVTrigger(7),
      I4 => stop_lcl_i_4_n_0,
      O => stop_lcl_i_3_n_0
    );
stop_lcl_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => stoTixVTrigger(0),
      I1 => stoTixVTrigger(2),
      I2 => stoTixVTrigger(6),
      I3 => stoTixVTrigger(5),
      O => stop_lcl_i_4_n_0
    );
stop_lcl_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \stop_lcl_i_1__1_n_0\,
      CLR => enSeqbuf_reg_0(0),
      D => \stop_lcl_i_2__2_n_0\,
      Q => stop_lcl_reg_n_0
    );
\strbStop5_inferred__0/i__carry\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \strbStop5_inferred__0/i__carry_n_0\,
      CO(6) => \strbStop5_inferred__0/i__carry_n_1\,
      CO(5) => \strbStop5_inferred__0/i__carry_n_2\,
      CO(4) => \strbStop5_inferred__0/i__carry_n_3\,
      CO(3) => \strbStop5_inferred__0/i__carry_n_4\,
      CO(2) => \strbStop5_inferred__0/i__carry_n_5\,
      CO(1) => \strbStop5_inferred__0/i__carry_n_6\,
      CO(0) => \strbStop5_inferred__0/i__carry_n_7\,
      DI(7) => \i__carry_i_1__5_n_0\,
      DI(6) => \i__carry_i_2__5_n_0\,
      DI(5) => \i__carry_i_3__5_n_0\,
      DI(4) => \i__carry_i_4__5_n_0\,
      DI(3) => \i__carry_i_5__5_n_0\,
      DI(2) => \i__carry_i_6__5_n_0\,
      DI(1) => \i__carry_i_7__4_n_0\,
      DI(0) => \i__carry_i_8__4_n_0\,
      O(7 downto 0) => \NLW_strbStop5_inferred__0/i__carry_O_UNCONNECTED\(7 downto 0),
      S(7) => \i__carry_i_9__4_n_0\,
      S(6) => \i__carry_i_10__4_n_0\,
      S(5) => \i__carry_i_11__3_n_0\,
      S(4) => \i__carry_i_12__1_n_0\,
      S(3) => \i__carry_i_13__0_n_0\,
      S(2) => \i__carry_i_14_n_0\,
      S(1) => \i__carry_i_15_n_0\,
      S(0) => \i__carry_i_16_n_0\
    );
\strbStop5_inferred__0/i__carry__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \strbStop5_inferred__0/i__carry_n_0\,
      CI_TOP => '0',
      CO(7) => \strbStop5_inferred__0/i__carry__0_n_0\,
      CO(6) => \strbStop5_inferred__0/i__carry__0_n_1\,
      CO(5) => \strbStop5_inferred__0/i__carry__0_n_2\,
      CO(4) => \strbStop5_inferred__0/i__carry__0_n_3\,
      CO(3) => \strbStop5_inferred__0/i__carry__0_n_4\,
      CO(2) => \strbStop5_inferred__0/i__carry__0_n_5\,
      CO(1) => \strbStop5_inferred__0/i__carry__0_n_6\,
      CO(0) => \strbStop5_inferred__0/i__carry__0_n_7\,
      DI(7) => \i__carry__0_i_1_n_0\,
      DI(6) => \i__carry__0_i_2_n_0\,
      DI(5) => \i__carry__0_i_3_n_0\,
      DI(4) => \i__carry__0_i_4_n_0\,
      DI(3) => \i__carry__0_i_5_n_0\,
      DI(2) => \i__carry__0_i_6_n_0\,
      DI(1) => \i__carry__0_i_7_n_0\,
      DI(0) => \i__carry__0_i_8_n_0\,
      O(7 downto 0) => \NLW_strbStop5_inferred__0/i__carry__0_O_UNCONNECTED\(7 downto 0),
      S(7) => \i__carry__0_i_9_n_0\,
      S(6) => \i__carry__0_i_10_n_0\,
      S(5) => \i__carry__0_i_11_n_0\,
      S(4) => \i__carry__0_i_12_n_0\,
      S(3) => \i__carry__0_i_13_n_0\,
      S(2) => \i__carry__0_i_14_n_0\,
      S(1) => \i__carry__0_i_15_n_0\,
      S(0) => \i__carry__0_i_16_n_0\
    );
\strbStop_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3333131300001310"
    )
        port map (
      I0 => stateOp(2),
      I1 => \^stateop_reg[0]_0\,
      I2 => stateOp(0),
      I3 => \stateOp[2]_i_3__3_n_0\,
      I4 => \strbStop_i_2__1_n_0\,
      I5 => strbStop_reg_n_0,
      O => \strbStop_i_1__1_n_0\
    );
\strbStop_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => \stateOp[2]_i_10__2_n_0\,
      I1 => stateOp(1),
      I2 => stateOp(2),
      O => \strbStop_i_2__1_n_0\
    );
strbStop_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enSeqbuf_reg_0(0),
      D => \strbStop_i_1__1_n_0\,
      Q => strbStop_reg_n_0
    );
\txAXIS_tdata[15]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => stateSeqbufB_reg(2),
      I1 => stateSeqbufB_reg(0),
      I2 => stateSeqbufB_reg(1),
      O => seqbufHshktrackToHostifAXIS_tvalid
    );
\wordcntLast[28]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"34"
    )
        port map (
      I0 => stateSeqbufB_reg(0),
      I1 => stateSeqbufB_reg(2),
      I2 => stateSeqbufB_reg(1),
      O => ackSeqbufHshktrackToHostif
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Memtrack is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \mask_reg[7]_0\ : out STD_LOGIC;
    \mask_reg[6]_0\ : out STD_LOGIC;
    \mask_reg[5]_0\ : out STD_LOGIC;
    \mask_reg[4]_0\ : out STD_LOGIC;
    \mask_reg[3]_0\ : out STD_LOGIC;
    \mask_reg[2]_0\ : out STD_LOGIC;
    \mask_reg[1]_0\ : out STD_LOGIC;
    \mask_reg[0]_0\ : out STD_LOGIC;
    ackInvMemtrackSet : out STD_LOGIC;
    ackInvMemtrackSelect : out STD_LOGIC;
    ackInvMemtrackSetMask : out STD_LOGIC;
    avllenSeqbufMemtrackToHostif : out STD_LOGIC_VECTOR ( 0 to 0 );
    rng_reg_0 : out STD_LOGIC;
    ackInvMemtrackClearMask : out STD_LOGIC;
    seqbufMemtrackToHostifAXIS_tvalid : out STD_LOGIC;
    memtrackGetInfoTixVState : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \stateOp_reg[2]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ackSeqbufMemtrackToHostif : out STD_LOGIC;
    \ptr0Seqbuf_mclk_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    memclk : in STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    \ptr0Seqbuf_to_mclkm2_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    AR : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \mask_reg[7]_1\ : in STD_LOGIC;
    \mask_reg[6]_1\ : in STD_LOGIC;
    \mask_reg[5]_1\ : in STD_LOGIC;
    \mask_reg[4]_1\ : in STD_LOGIC;
    \mask_reg[3]_1\ : in STD_LOGIC;
    \mask_reg[2]_1\ : in STD_LOGIC;
    \mask_reg[1]_1\ : in STD_LOGIC;
    \mask_reg[0]_1\ : in STD_LOGIC;
    rng_reg_1 : in STD_LOGIC;
    restart_reg_0 : in STD_LOGIC;
    reqInvMemtrackClearMask : in STD_LOGIC;
    \mask_reg[8]_0\ : in STD_LOGIC;
    strb_last_reg_0 : in STD_LOGIC;
    reqInvMemtrackSetMask : in STD_LOGIC;
    \staTixVTrigger_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    reqSeqbufMemtrackToHostif : in STD_LOGIC;
    seqbufMemtrackToHostifAXIS_tready : in STD_LOGIC;
    dneSeqbufMemtrackToHostif : in STD_LOGIC;
    reqInvMemtrackSelect : in STD_LOGIC;
    reqInvMemtrackSet : in STD_LOGIC;
    \capt_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \capt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \capt_reg[3]_0\ : in STD_LOGIC;
    \capt_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \capt_reg[8]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \capt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    ddrAXI_rvalid : in STD_LOGIC;
    ddrAXI_wready : in STD_LOGIC;
    ddrAXI_bvalid : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 23 downto 0 );
    \capt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \TCaptMax_reg[31]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \TCaptMax_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    start_reg_0 : in STD_LOGIC;
    stop_reg_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Memtrack : entity is "Memtrack";
end design_1_Vsp_core_0_0_Memtrack;

architecture STRUCTURE of design_1_Vsp_core_0_0_Memtrack is
  signal \FSM_onehot_stateSeq[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_4__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_5__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_6__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_7__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq_reg_n_0_[4]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal TCapt : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[0]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[10]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[11]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[12]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[13]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[14]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[15]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[16]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[17]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[18]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[19]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[1]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[20]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[21]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[22]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[23]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[24]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[25]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[26]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[27]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[28]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[29]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[2]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[30]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[31]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[3]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[4]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[5]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[6]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[7]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[8]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[9]\ : STD_LOGIC;
  signal \TCapt__0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal TCapt_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \TCapt_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \TCapt_i[1]_i_10_n_0\ : STD_LOGIC;
  signal \TCapt_i[1]_i_11_n_0\ : STD_LOGIC;
  signal \TCapt_i[1]_i_12_n_0\ : STD_LOGIC;
  signal \TCapt_i[1]_i_13_n_0\ : STD_LOGIC;
  signal \TCapt_i[1]_i_14_n_0\ : STD_LOGIC;
  signal \TCapt_i[1]_i_1_n_0\ : STD_LOGIC;
  signal \TCapt_i[1]_i_4_n_0\ : STD_LOGIC;
  signal \TCapt_i[1]_i_5_n_0\ : STD_LOGIC;
  signal \TCapt_i[1]_i_6_n_0\ : STD_LOGIC;
  signal \TCapt_i[1]_i_7_n_0\ : STD_LOGIC;
  signal \TCapt_i[1]_i_8_n_0\ : STD_LOGIC;
  signal \TCapt_i[1]_i_9_n_0\ : STD_LOGIC;
  signal \TCapt_i_reg[1]_i_2_n_5\ : STD_LOGIC;
  signal \TCapt_i_reg[1]_i_2_n_6\ : STD_LOGIC;
  signal \TCapt_i_reg[1]_i_2_n_7\ : STD_LOGIC;
  signal \TCapt_i_reg[1]_i_3_n_0\ : STD_LOGIC;
  signal \TCapt_i_reg[1]_i_3_n_1\ : STD_LOGIC;
  signal \TCapt_i_reg[1]_i_3_n_2\ : STD_LOGIC;
  signal \TCapt_i_reg[1]_i_3_n_3\ : STD_LOGIC;
  signal \TCapt_i_reg[1]_i_3_n_4\ : STD_LOGIC;
  signal \TCapt_i_reg[1]_i_3_n_5\ : STD_LOGIC;
  signal \TCapt_i_reg[1]_i_3_n_6\ : STD_LOGIC;
  signal \TCapt_i_reg[1]_i_3_n_7\ : STD_LOGIC;
  signal \TCapt_mclk[31]_i_10_n_0\ : STD_LOGIC;
  signal \TCapt_mclk[31]_i_11_n_0\ : STD_LOGIC;
  signal \TCapt_mclk[31]_i_12_n_0\ : STD_LOGIC;
  signal \TCapt_mclk[31]_i_13_n_0\ : STD_LOGIC;
  signal \TCapt_mclk[31]_i_1_n_0\ : STD_LOGIC;
  signal \TCapt_mclk[31]_i_2_n_0\ : STD_LOGIC;
  signal \TCapt_mclk[31]_i_3_n_0\ : STD_LOGIC;
  signal \TCapt_mclk[31]_i_4_n_0\ : STD_LOGIC;
  signal \TCapt_mclk[31]_i_5_n_0\ : STD_LOGIC;
  signal \TCapt_mclk[31]_i_6_n_0\ : STD_LOGIC;
  signal \TCapt_mclk[31]_i_7_n_0\ : STD_LOGIC;
  signal \TCapt_mclk[31]_i_8_n_0\ : STD_LOGIC;
  signal \TCapt_mclk[31]_i_9_n_0\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2__0_n_0\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2__0_n_1\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2__0_n_2\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2__0_n_3\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2__0_n_4\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2__0_n_5\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2__0_n_6\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2__0_n_7\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2__0_n_0\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2__0_n_1\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2__0_n_2\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2__0_n_3\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2__0_n_4\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2__0_n_5\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2__0_n_6\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2__0_n_7\ : STD_LOGIC;
  signal \TCapt_reg[31]_i_2__0_n_2\ : STD_LOGIC;
  signal \TCapt_reg[31]_i_2__0_n_3\ : STD_LOGIC;
  signal \TCapt_reg[31]_i_2__0_n_4\ : STD_LOGIC;
  signal \TCapt_reg[31]_i_2__0_n_5\ : STD_LOGIC;
  signal \TCapt_reg[31]_i_2__0_n_6\ : STD_LOGIC;
  signal \TCapt_reg[31]_i_2__0_n_7\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2__0_n_1\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2__0_n_2\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2__0_n_3\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2__0_n_4\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2__0_n_5\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2__0_n_6\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2__0_n_7\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[0]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[10]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[11]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[12]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[13]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[14]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[15]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[16]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[17]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[18]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[19]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[1]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[20]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[21]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[22]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[23]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[24]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[25]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[26]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[27]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[28]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[29]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[2]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[30]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[31]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[3]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[4]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[5]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[6]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[7]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[8]\ : STD_LOGIC;
  signal \TCapt_reg_n_0_[9]\ : STD_LOGIC;
  signal TCapt_to_mclk : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \TCapt_to_mclk[31]_i_1_n_0\ : STD_LOGIC;
  signal TCapt_to_mclkm1 : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal TCapt_to_mclkm2 : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \aSeqbufB[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbufB[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbufB[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbufB[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbufB[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbufB[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbufB[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \aSeqbufB[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbufB[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_3__0_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_4__0_n_0\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[0]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[1]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[2]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[3]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[4]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[5]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[6]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[7]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[8]\ : STD_LOGIC;
  signal \aSeqbuf[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_3__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_4__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_5_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_2__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_3__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_4__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_5__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_6__0_n_0\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[0]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[1]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[2]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[3]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[4]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[5]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[6]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[7]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[8]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[9]\ : STD_LOGIC;
  signal ackInvClearMask_sig_i_1_n_0 : STD_LOGIC;
  signal \^ackinvmemtrackclearmask\ : STD_LOGIC;
  signal \^ackinvmemtrackselect\ : STD_LOGIC;
  signal \^ackinvmemtrackset\ : STD_LOGIC;
  signal \^ackinvmemtracksetmask\ : STD_LOGIC;
  signal \ackInvSelect_sig_i_1__0_n_0\ : STD_LOGIC;
  signal ackInvSetMask_sig : STD_LOGIC;
  signal ackInvSetMask_sig_i_1_n_0 : STD_LOGIC;
  signal \ackInvSet_sig_i_1__2_n_0\ : STD_LOGIC;
  signal \ackInvSet_sig_i_2__0_n_0\ : STD_LOGIC;
  signal ackSeqbufBToSeqClear : STD_LOGIC;
  signal \^avllenseqbufmemtracktohostif\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal burstCapt : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \burstCapt_reg_n_0_[0]\ : STD_LOGIC;
  signal \burstCapt_reg_n_0_[1]\ : STD_LOGIC;
  signal \burstCapt_reg_n_0_[2]\ : STD_LOGIC;
  signal \burstCapt_reg_n_0_[3]\ : STD_LOGIC;
  signal \burstCapt_reg_n_0_[4]\ : STD_LOGIC;
  signal \burstCapt_reg_n_0_[5]\ : STD_LOGIC;
  signal \burstCapt_reg_n_0_[6]\ : STD_LOGIC;
  signal \burstCapt_reg_n_0_[7]\ : STD_LOGIC;
  signal \burstCapt_reg_n_0_[8]\ : STD_LOGIC;
  signal burstCnt : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \burstCnt[10]_i_2__0_n_0\ : STD_LOGIC;
  signal \burstCnt[11]_i_2__0_n_0\ : STD_LOGIC;
  signal \burstCnt[12]_i_2__0_n_0\ : STD_LOGIC;
  signal \burstCnt[14]_i_2__0_n_0\ : STD_LOGIC;
  signal \burstCnt[14]_i_3__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_10__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_11__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_12__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_13__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_3__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_4__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_5__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_6_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_7__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_8__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_9__0_n_0\ : STD_LOGIC;
  signal \burstCnt[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \burstCnt[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \burstCnt[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[6]_i_2__0_n_0\ : STD_LOGIC;
  signal \burstCnt[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \burstCnt[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \burstCnt[9]_i_2__0_n_0\ : STD_LOGIC;
  signal \burstCnt[9]_i_3_n_0\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[14]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[9]\ : STD_LOGIC;
  signal capt : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \capt[0]_i_1_n_0\ : STD_LOGIC;
  signal \capt[1]_i_1_n_0\ : STD_LOGIC;
  signal \capt[2]_i_1_n_0\ : STD_LOGIC;
  signal \capt[3]_i_1_n_0\ : STD_LOGIC;
  signal \capt[4]_i_1_n_0\ : STD_LOGIC;
  signal \capt[6]_i_1_n_0\ : STD_LOGIC;
  signal \capt[7]_i_1_n_0\ : STD_LOGIC;
  signal \capt[8]_i_1_n_0\ : STD_LOGIC;
  signal dneSeq : STD_LOGIC;
  signal dneSeq_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \dneSeq_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \dneSeq_i[1]_i_1_n_0\ : STD_LOGIC;
  signal dneSeq_mclk_i_1_n_0 : STD_LOGIC;
  signal dneSeq_to_mclk : STD_LOGIC;
  signal dneSeq_to_mclk_i_1_n_0 : STD_LOGIC;
  signal dneSeq_to_mclkm1 : STD_LOGIC;
  signal dneSeq_to_mclkm2 : STD_LOGIC;
  signal dwrSeqbuf : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \dwrSeqbuf[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[13]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[14]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[15]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[15]_i_3__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[16]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[17]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[18]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[19]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[1]_i_3__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[20]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[21]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[22]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[23]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[24]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[30]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_3_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_4__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_5_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_6_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_7_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[5]_i_3__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[6]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[8]_i_3_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[9]_i_1__0_n_0\ : STD_LOGIC;
  signal enSeqbuf : STD_LOGIC;
  signal enSeqbuf_reg_n_0 : STD_LOGIC;
  signal first : STD_LOGIC;
  signal \first__0\ : STD_LOGIC;
  signal \i[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \i_reg_n_0_[0]\ : STD_LOGIC;
  signal in15 : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal \mask[8]_i_1_n_0\ : STD_LOGIC;
  signal \mask[8]_i_2_n_0\ : STD_LOGIC;
  signal \^mask_reg[0]_0\ : STD_LOGIC;
  signal \^mask_reg[1]_0\ : STD_LOGIC;
  signal \^mask_reg[2]_0\ : STD_LOGIC;
  signal \^mask_reg[3]_0\ : STD_LOGIC;
  signal \^mask_reg[4]_0\ : STD_LOGIC;
  signal \^mask_reg[6]_0\ : STD_LOGIC;
  signal \^mask_reg[7]_0\ : STD_LOGIC;
  signal \mask_reg_n_0_[8]\ : STD_LOGIC;
  signal \^memtrackgetinfotixvstate\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal ptr0Seqbuf : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \ptr0SeqbufTrackNotFixed_i_1__0_n_0\ : STD_LOGIC;
  signal ptr0SeqbufTrackNotFixed_i_2_n_0 : STD_LOGIC;
  signal ptr0SeqbufTrackNotFixed_reg_n_0 : STD_LOGIC;
  signal ptr0Seqbuf_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ptr0Seqbuf_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \ptr0Seqbuf_i[1]_i_1_n_0\ : STD_LOGIC;
  signal \ptr0Seqbuf_i[1]_i_2_n_0\ : STD_LOGIC;
  signal \ptr0Seqbuf_i[1]_i_3_n_0\ : STD_LOGIC;
  signal \ptr0Seqbuf_i[1]_i_4_n_0\ : STD_LOGIC;
  signal \ptr0Seqbuf_i[1]_i_5_n_0\ : STD_LOGIC;
  signal \ptr0Seqbuf_i[1]_i_6_n_0\ : STD_LOGIC;
  signal \ptr0Seqbuf_i[1]_i_7_n_0\ : STD_LOGIC;
  signal \ptr0Seqbuf_mclk[9]_i_1_n_0\ : STD_LOGIC;
  signal \ptr0Seqbuf_mclk[9]_i_2_n_0\ : STD_LOGIC;
  signal \ptr0Seqbuf_mclk[9]_i_3_n_0\ : STD_LOGIC;
  signal \ptr0Seqbuf_mclk[9]_i_4_n_0\ : STD_LOGIC;
  signal ptr0Seqbuf_to_mclk : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \ptr0Seqbuf_to_mclk[9]_i_1_n_0\ : STD_LOGIC;
  signal ptr0Seqbuf_to_mclkm1 : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal ptr0Seqbuf_to_mclkm2 : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal quad : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \quad[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \quad_reg_n_0_[0]\ : STD_LOGIC;
  signal \quad_reg_n_0_[1]\ : STD_LOGIC;
  signal \quad_reg_n_0_[2]\ : STD_LOGIC;
  signal \quad_reg_n_0_[3]\ : STD_LOGIC;
  signal \quad_reg_n_0_[4]\ : STD_LOGIC;
  signal \quad_reg_n_0_[5]\ : STD_LOGIC;
  signal \quad_reg_n_0_[6]\ : STD_LOGIC;
  signal \quad_reg_n_0_[7]\ : STD_LOGIC;
  signal \quad_reg_n_0_[8]\ : STD_LOGIC;
  signal rdySeq : STD_LOGIC;
  signal rdySeq_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rdySeq_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \rdySeq_i[1]_i_1_n_0\ : STD_LOGIC;
  signal rdySeq_mclk : STD_LOGIC;
  signal rdySeq_mclk_i_1_n_0 : STD_LOGIC;
  signal rdySeq_to_mclk : STD_LOGIC;
  signal rdySeq_to_mclk_i_1_n_0 : STD_LOGIC;
  signal rdySeq_to_mclkm1 : STD_LOGIC;
  signal rdySeq_to_mclkm2 : STD_LOGIC;
  signal reqOpToSeqClear_i : STD_LOGIC;
  signal \reqOpToSeqClear_i[0]_i_1_n_0\ : STD_LOGIC;
  signal reqOpToSeqClear_memclk : STD_LOGIC;
  signal reqOpToSeqClear_memclk_i_1_n_0 : STD_LOGIC;
  signal reqOpToSeqClear_to_memclk_i_1_n_0 : STD_LOGIC;
  signal reqOpToSeqClear_to_memclk_reg_n_0 : STD_LOGIC;
  signal reqOpToSeqClear_to_memclkm1 : STD_LOGIC;
  signal reqOpToSeqClear_to_memclkm2 : STD_LOGIC;
  signal reqSeqbufBToSeqClear_i : STD_LOGIC;
  signal \reqSeqbufBToSeqClear_i[0]_i_1_n_0\ : STD_LOGIC;
  signal reqSeqbufBToSeqClear_memclk : STD_LOGIC;
  signal reqSeqbufBToSeqClear_memclk_i_1_n_0 : STD_LOGIC;
  signal reqSeqbufBToSeqClear_to_memclk_i_1_n_0 : STD_LOGIC;
  signal reqSeqbufBToSeqClear_to_memclk_reg_n_0 : STD_LOGIC;
  signal reqSeqbufBToSeqClear_to_memclkm1 : STD_LOGIC;
  signal reqSeqbufBToSeqClear_to_memclkm2 : STD_LOGIC;
  signal \restart_i_1__0_n_0\ : STD_LOGIC;
  signal restart_reg_n_0 : STD_LOGIC;
  signal \^rng_reg_0\ : STD_LOGIC;
  signal staFallingNotRising_i_1_n_0 : STD_LOGIC;
  signal staFallingNotRising_i_2_n_0 : STD_LOGIC;
  signal staFallingNotRising_reg_n_0 : STD_LOGIC;
  signal staTixVTrigger_i : STD_LOGIC;
  signal \staTixVTrigger_i[0]_i_1_n_0\ : STD_LOGIC;
  signal staTixVTrigger_memclk : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal staTixVTrigger_memclk0 : STD_LOGIC;
  signal \staTixVTrigger_memclk[7]_i_2_n_0\ : STD_LOGIC;
  signal \staTixVTrigger_memclk[7]_i_3_n_0\ : STD_LOGIC;
  signal \staTixVTrigger_memclk__0\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \staTixVTrigger_reg_n_0_[0]\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[1]\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[2]\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[3]\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[4]\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[5]\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[6]\ : STD_LOGIC;
  signal \staTixVTrigger_reg_n_0_[7]\ : STD_LOGIC;
  signal staTixVTrigger_to_memclk : STD_LOGIC;
  signal \staTixVTrigger_to_memclk[7]_i_2_n_0\ : STD_LOGIC;
  signal \staTixVTrigger_to_memclk[7]_i_3_n_0\ : STD_LOGIC;
  signal \staTixVTrigger_to_memclk[7]_i_4_n_0\ : STD_LOGIC;
  signal \staTixVTrigger_to_memclk_reg_n_0_[0]\ : STD_LOGIC;
  signal \staTixVTrigger_to_memclk_reg_n_0_[1]\ : STD_LOGIC;
  signal \staTixVTrigger_to_memclk_reg_n_0_[2]\ : STD_LOGIC;
  signal \staTixVTrigger_to_memclk_reg_n_0_[3]\ : STD_LOGIC;
  signal \staTixVTrigger_to_memclk_reg_n_0_[4]\ : STD_LOGIC;
  signal \staTixVTrigger_to_memclk_reg_n_0_[5]\ : STD_LOGIC;
  signal \staTixVTrigger_to_memclk_reg_n_0_[6]\ : STD_LOGIC;
  signal \staTixVTrigger_to_memclk_reg_n_0_[7]\ : STD_LOGIC;
  signal staTixVTrigger_to_memclkm1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal staTixVTrigger_to_memclkm2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal start : STD_LOGIC;
  signal start_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \start_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \start_i[1]_i_1_n_0\ : STD_LOGIC;
  signal start_i_1_n_0 : STD_LOGIC;
  signal start_i_2_n_0 : STD_LOGIC;
  signal start_mclk : STD_LOGIC;
  signal start_mclk_i_1_n_0 : STD_LOGIC;
  signal start_to_mclk : STD_LOGIC;
  signal start_to_mclk_i_1_n_0 : STD_LOGIC;
  signal start_to_mclkm1 : STD_LOGIC;
  signal start_to_mclkm2 : STD_LOGIC;
  signal stateOp : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \stateOp[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_10__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_11__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_13__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_14_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_15__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_16__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_17__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_18__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_19__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_20__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_21__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_22__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_23__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_24__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_25__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_26__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_27__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_28__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_29__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_30__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_31__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_32__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_33__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_34__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_35__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_36__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_37__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_38__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_39__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_40__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_41__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_42__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_43__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_44__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_45__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_46__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_47__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_48__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_49__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_50__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_51__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_52__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_53__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_54__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_55__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_56__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_57__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_58_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_5__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_7_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_8__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_9_n_0\ : STD_LOGIC;
  signal \^stateop_reg[2]_0\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_12_n_0\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_12_n_1\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_12_n_2\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_12_n_3\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_12_n_4\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_12_n_5\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_12_n_6\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_12_n_7\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_6_n_0\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_6_n_1\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_6_n_2\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_6_n_3\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_6_n_4\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_6_n_5\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_6_n_6\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_6_n_7\ : STD_LOGIC;
  signal \stateSeqbufB[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[2]_i_6_n_0\ : STD_LOGIC;
  signal stateSeqbufB_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal stoFallingNotRising : STD_LOGIC;
  signal stoFallingNotRising_i_1_n_0 : STD_LOGIC;
  signal stoFallingNotRising_i_2_n_0 : STD_LOGIC;
  signal stoTixVTrigger : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal stoTixVTrigger_i : STD_LOGIC;
  signal \stoTixVTrigger_i[0]_i_1_n_0\ : STD_LOGIC;
  signal stoTixVTrigger_memclk : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal stoTixVTrigger_memclk0 : STD_LOGIC;
  signal \stoTixVTrigger_memclk[7]_i_2_n_0\ : STD_LOGIC;
  signal \stoTixVTrigger_memclk[7]_i_3_n_0\ : STD_LOGIC;
  signal \stoTixVTrigger_memclk__0\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal stoTixVTrigger_to_memclk : STD_LOGIC;
  signal \stoTixVTrigger_to_memclk[7]_i_2_n_0\ : STD_LOGIC;
  signal \stoTixVTrigger_to_memclk[7]_i_3_n_0\ : STD_LOGIC;
  signal \stoTixVTrigger_to_memclk[7]_i_4_n_0\ : STD_LOGIC;
  signal \stoTixVTrigger_to_memclk_reg_n_0_[0]\ : STD_LOGIC;
  signal \stoTixVTrigger_to_memclk_reg_n_0_[1]\ : STD_LOGIC;
  signal \stoTixVTrigger_to_memclk_reg_n_0_[2]\ : STD_LOGIC;
  signal \stoTixVTrigger_to_memclk_reg_n_0_[3]\ : STD_LOGIC;
  signal \stoTixVTrigger_to_memclk_reg_n_0_[4]\ : STD_LOGIC;
  signal \stoTixVTrigger_to_memclk_reg_n_0_[5]\ : STD_LOGIC;
  signal \stoTixVTrigger_to_memclk_reg_n_0_[6]\ : STD_LOGIC;
  signal \stoTixVTrigger_to_memclk_reg_n_0_[7]\ : STD_LOGIC;
  signal stoTixVTrigger_to_memclkm1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal stoTixVTrigger_to_memclkm2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal stop : STD_LOGIC;
  signal stop_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \stop_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \stop_i[1]_i_1_n_0\ : STD_LOGIC;
  signal stop_i_1_n_0 : STD_LOGIC;
  signal stop_i_2_n_0 : STD_LOGIC;
  signal \stop_lcl_i_1__0_n_0\ : STD_LOGIC;
  signal \stop_lcl_i_2__0_n_0\ : STD_LOGIC;
  signal stop_lcl_reg_n_0 : STD_LOGIC;
  signal stop_mclk : STD_LOGIC;
  signal stop_mclk_i_1_n_0 : STD_LOGIC;
  signal stop_to_mclk : STD_LOGIC;
  signal stop_to_mclk_i_1_n_0 : STD_LOGIC;
  signal stop_to_mclkm1 : STD_LOGIC;
  signal stop_to_mclkm2 : STD_LOGIC;
  signal strbStart_i : STD_LOGIC;
  signal \strbStart_i[0]_i_1_n_0\ : STD_LOGIC;
  signal strbStart_memclk_i_1_n_0 : STD_LOGIC;
  signal strbStart_memclk_reg_n_0 : STD_LOGIC;
  signal strbStart_to_memclk : STD_LOGIC;
  signal strbStart_to_memclk_i_1_n_0 : STD_LOGIC;
  signal strbStart_to_memclkm1 : STD_LOGIC;
  signal strbStart_to_memclkm2 : STD_LOGIC;
  signal strbStart_wait13_out : STD_LOGIC;
  signal strbStart_wait_reg_n_0 : STD_LOGIC;
  signal strbStop_i : STD_LOGIC;
  signal \strbStop_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \strbStop_i_1__0_n_0\ : STD_LOGIC;
  signal \strbStop_i_2__0_n_0\ : STD_LOGIC;
  signal \strbStop_i_3__0_n_0\ : STD_LOGIC;
  signal strbStop_memclk_i_1_n_0 : STD_LOGIC;
  signal strbStop_memclk_reg_n_0 : STD_LOGIC;
  signal strbStop_reg_n_0 : STD_LOGIC;
  signal strbStop_to_memclk : STD_LOGIC;
  signal strbStop_to_memclk_i_1_n_0 : STD_LOGIC;
  signal strbStop_to_memclkm1 : STD_LOGIC;
  signal strbStop_to_memclkm2 : STD_LOGIC;
  signal strbStop_wait17_out : STD_LOGIC;
  signal strbStop_wait_reg_n_0 : STD_LOGIC;
  signal strb_last_i_1_n_0 : STD_LOGIC;
  signal strb_last_i_2_n_0 : STD_LOGIC;
  signal strb_last_i_3_n_0 : STD_LOGIC;
  signal strb_last_reg_n_0 : STD_LOGIC;
  signal \NLW_TCapt_i_reg[1]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal \NLW_TCapt_i_reg[1]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_TCapt_i_reg[1]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_TCapt_reg[31]_i_2__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_TCapt_reg[31]_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_stateOp_reg[2]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateOp_reg[2]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[2]_i_1__0\ : label is "soft_lutpair2536";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[3]_i_1__0\ : label is "soft_lutpair2536";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_2__0\ : label is "soft_lutpair2579";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_4__0\ : label is "soft_lutpair2560";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_5__0\ : label is "soft_lutpair2579";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_6__0\ : label is "soft_lutpair2521";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_7__0\ : label is "soft_lutpair2532";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_8\ : label is "soft_lutpair2511";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[0]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[1]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[2]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[3]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[4]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[5]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute SOFT_HLUTNM of \TCapt[10]_i_1__0\ : label is "soft_lutpair2590";
  attribute SOFT_HLUTNM of \TCapt[11]_i_1__0\ : label is "soft_lutpair2589";
  attribute SOFT_HLUTNM of \TCapt[12]_i_1__0\ : label is "soft_lutpair2589";
  attribute SOFT_HLUTNM of \TCapt[13]_i_1__0\ : label is "soft_lutpair2588";
  attribute SOFT_HLUTNM of \TCapt[14]_i_1__0\ : label is "soft_lutpair2588";
  attribute SOFT_HLUTNM of \TCapt[15]_i_1__0\ : label is "soft_lutpair2587";
  attribute SOFT_HLUTNM of \TCapt[16]_i_1__0\ : label is "soft_lutpair2587";
  attribute SOFT_HLUTNM of \TCapt[17]_i_1__0\ : label is "soft_lutpair2586";
  attribute SOFT_HLUTNM of \TCapt[18]_i_1__0\ : label is "soft_lutpair2586";
  attribute SOFT_HLUTNM of \TCapt[19]_i_1__0\ : label is "soft_lutpair2585";
  attribute SOFT_HLUTNM of \TCapt[1]_i_1__0\ : label is "soft_lutpair2594";
  attribute SOFT_HLUTNM of \TCapt[20]_i_1__0\ : label is "soft_lutpair2585";
  attribute SOFT_HLUTNM of \TCapt[21]_i_1__0\ : label is "soft_lutpair2584";
  attribute SOFT_HLUTNM of \TCapt[22]_i_1__0\ : label is "soft_lutpair2584";
  attribute SOFT_HLUTNM of \TCapt[23]_i_1__0\ : label is "soft_lutpair2583";
  attribute SOFT_HLUTNM of \TCapt[24]_i_1__0\ : label is "soft_lutpair2583";
  attribute SOFT_HLUTNM of \TCapt[25]_i_1__0\ : label is "soft_lutpair2582";
  attribute SOFT_HLUTNM of \TCapt[26]_i_1__0\ : label is "soft_lutpair2582";
  attribute SOFT_HLUTNM of \TCapt[27]_i_1__0\ : label is "soft_lutpair2581";
  attribute SOFT_HLUTNM of \TCapt[28]_i_1__0\ : label is "soft_lutpair2581";
  attribute SOFT_HLUTNM of \TCapt[29]_i_1__0\ : label is "soft_lutpair2580";
  attribute SOFT_HLUTNM of \TCapt[2]_i_1__0\ : label is "soft_lutpair2594";
  attribute SOFT_HLUTNM of \TCapt[30]_i_1__0\ : label is "soft_lutpair2580";
  attribute SOFT_HLUTNM of \TCapt[31]_i_1__0\ : label is "soft_lutpair2576";
  attribute SOFT_HLUTNM of \TCapt[3]_i_1__0\ : label is "soft_lutpair2593";
  attribute SOFT_HLUTNM of \TCapt[4]_i_1__0\ : label is "soft_lutpair2593";
  attribute SOFT_HLUTNM of \TCapt[5]_i_1__0\ : label is "soft_lutpair2592";
  attribute SOFT_HLUTNM of \TCapt[6]_i_1__0\ : label is "soft_lutpair2592";
  attribute SOFT_HLUTNM of \TCapt[7]_i_1__0\ : label is "soft_lutpair2591";
  attribute SOFT_HLUTNM of \TCapt[8]_i_1__0\ : label is "soft_lutpair2591";
  attribute SOFT_HLUTNM of \TCapt[9]_i_1__0\ : label is "soft_lutpair2590";
  attribute SOFT_HLUTNM of \TCapt_i[0]_i_1\ : label is "soft_lutpair2566";
  attribute SOFT_HLUTNM of \TCapt_i[1]_i_1\ : label is "soft_lutpair2566";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \TCapt_reg[16]_i_2__0\ : label is 35;
  attribute ADDER_THRESHOLD of \TCapt_reg[24]_i_2__0\ : label is 35;
  attribute ADDER_THRESHOLD of \TCapt_reg[31]_i_2__0\ : label is 35;
  attribute ADDER_THRESHOLD of \TCapt_reg[8]_i_2__0\ : label is 35;
  attribute SOFT_HLUTNM of \aSeqbufB[1]_i_1__0\ : label is "soft_lutpair2531";
  attribute SOFT_HLUTNM of \aSeqbufB[2]_i_1__0\ : label is "soft_lutpair2531";
  attribute SOFT_HLUTNM of \aSeqbufB[5]_i_1__0\ : label is "soft_lutpair2535";
  attribute SOFT_HLUTNM of \aSeqbufB[6]_i_1__0\ : label is "soft_lutpair2530";
  attribute SOFT_HLUTNM of \aSeqbufB[7]_i_1__0\ : label is "soft_lutpair2530";
  attribute SOFT_HLUTNM of \aSeqbufB[8]_i_2__0\ : label is "soft_lutpair2510";
  attribute SOFT_HLUTNM of \aSeqbufB[8]_i_3__0\ : label is "soft_lutpair2565";
  attribute SOFT_HLUTNM of \aSeqbuf[1]_i_1__0\ : label is "soft_lutpair2562";
  attribute SOFT_HLUTNM of \aSeqbuf[2]_i_1__0\ : label is "soft_lutpair2520";
  attribute SOFT_HLUTNM of \aSeqbuf[3]_i_1__0\ : label is "soft_lutpair2520";
  attribute SOFT_HLUTNM of \aSeqbuf[3]_i_2__0\ : label is "soft_lutpair2509";
  attribute SOFT_HLUTNM of \aSeqbuf[6]_i_1__0\ : label is "soft_lutpair2540";
  attribute SOFT_HLUTNM of \aSeqbuf[7]_i_1__0\ : label is "soft_lutpair2540";
  attribute SOFT_HLUTNM of \aSeqbuf[8]_i_4__0\ : label is "soft_lutpair2511";
  attribute SOFT_HLUTNM of \aSeqbuf[8]_i_5\ : label is "soft_lutpair2521";
  attribute SOFT_HLUTNM of \aSeqbuf[9]_i_3__0\ : label is "soft_lutpair2544";
  attribute SOFT_HLUTNM of \ackInvSet_sig_i_2__0\ : label is "soft_lutpair2514";
  attribute SOFT_HLUTNM of \burstCapt[0]_i_1\ : label is "soft_lutpair2548";
  attribute SOFT_HLUTNM of \burstCapt[1]_i_1\ : label is "soft_lutpair2573";
  attribute SOFT_HLUTNM of \burstCapt[2]_i_1\ : label is "soft_lutpair2573";
  attribute SOFT_HLUTNM of \burstCapt[3]_i_1\ : label is "soft_lutpair2574";
  attribute SOFT_HLUTNM of \burstCapt[4]_i_1\ : label is "soft_lutpair2550";
  attribute SOFT_HLUTNM of \burstCapt[5]_i_1\ : label is "soft_lutpair2574";
  attribute SOFT_HLUTNM of \burstCapt[6]_i_1\ : label is "soft_lutpair2575";
  attribute SOFT_HLUTNM of \burstCapt[7]_i_1\ : label is "soft_lutpair2553";
  attribute SOFT_HLUTNM of \burstCapt[8]_i_1\ : label is "soft_lutpair2575";
  attribute SOFT_HLUTNM of \burstCnt[0]_i_1\ : label is "soft_lutpair2567";
  attribute SOFT_HLUTNM of \burstCnt[10]_i_1\ : label is "soft_lutpair2572";
  attribute SOFT_HLUTNM of \burstCnt[11]_i_1\ : label is "soft_lutpair2571";
  attribute SOFT_HLUTNM of \burstCnt[12]_i_1\ : label is "soft_lutpair2572";
  attribute SOFT_HLUTNM of \burstCnt[15]_i_12__0\ : label is "soft_lutpair2545";
  attribute SOFT_HLUTNM of \burstCnt[15]_i_13__0\ : label is "soft_lutpair2534";
  attribute SOFT_HLUTNM of \burstCnt[15]_i_3__0\ : label is "soft_lutpair2576";
  attribute SOFT_HLUTNM of \burstCnt[1]_i_1__0\ : label is "soft_lutpair2513";
  attribute SOFT_HLUTNM of \burstCnt[2]_i_1__0\ : label is "soft_lutpair2513";
  attribute SOFT_HLUTNM of \burstCnt[4]_i_1__0\ : label is "soft_lutpair2569";
  attribute SOFT_HLUTNM of \burstCnt[4]_i_2__0\ : label is "soft_lutpair2544";
  attribute SOFT_HLUTNM of \burstCnt[5]_i_1__0\ : label is "soft_lutpair2512";
  attribute SOFT_HLUTNM of \burstCnt[5]_i_2__0\ : label is "soft_lutpair2522";
  attribute SOFT_HLUTNM of \burstCnt[6]_i_1__0\ : label is "soft_lutpair2570";
  attribute SOFT_HLUTNM of \burstCnt[7]_i_1__0\ : label is "soft_lutpair2567";
  attribute SOFT_HLUTNM of \burstCnt[8]_i_1__0\ : label is "soft_lutpair2570";
  attribute SOFT_HLUTNM of \burstCnt[9]_i_1\ : label is "soft_lutpair2571";
  attribute SOFT_HLUTNM of \dneSeq_i[0]_i_1\ : label is "soft_lutpair2542";
  attribute SOFT_HLUTNM of \dneSeq_i[1]_i_1\ : label is "soft_lutpair2542";
  attribute SOFT_HLUTNM of dneSeq_to_mclk_i_1 : label is "soft_lutpair2560";
  attribute SOFT_HLUTNM of \dwrSeqbuf[0]_i_2__0\ : label is "soft_lutpair2523";
  attribute SOFT_HLUTNM of \dwrSeqbuf[10]_i_1__0\ : label is "soft_lutpair2564";
  attribute SOFT_HLUTNM of \dwrSeqbuf[11]_i_1__0\ : label is "soft_lutpair2563";
  attribute SOFT_HLUTNM of \dwrSeqbuf[12]_i_1__0\ : label is "soft_lutpair2563";
  attribute SOFT_HLUTNM of \dwrSeqbuf[15]_i_2__0\ : label is "soft_lutpair2545";
  attribute SOFT_HLUTNM of \dwrSeqbuf[19]_i_1__0\ : label is "soft_lutpair2557";
  attribute SOFT_HLUTNM of \dwrSeqbuf[1]_i_3__0\ : label is "soft_lutpair2524";
  attribute SOFT_HLUTNM of \dwrSeqbuf[20]_i_1__0\ : label is "soft_lutpair2557";
  attribute SOFT_HLUTNM of \dwrSeqbuf[22]_i_1__0\ : label is "soft_lutpair2532";
  attribute SOFT_HLUTNM of \dwrSeqbuf[23]_i_1__0\ : label is "soft_lutpair2556";
  attribute SOFT_HLUTNM of \dwrSeqbuf[24]_i_1__0\ : label is "soft_lutpair2556";
  attribute SOFT_HLUTNM of \dwrSeqbuf[2]_i_2__0\ : label is "soft_lutpair2534";
  attribute SOFT_HLUTNM of \dwrSeqbuf[2]_i_3__0\ : label is "soft_lutpair2546";
  attribute SOFT_HLUTNM of \dwrSeqbuf[31]_i_3\ : label is "soft_lutpair2523";
  attribute SOFT_HLUTNM of \dwrSeqbuf[31]_i_5\ : label is "soft_lutpair2524";
  attribute SOFT_HLUTNM of \dwrSeqbuf[31]_i_6\ : label is "soft_lutpair2526";
  attribute SOFT_HLUTNM of \dwrSeqbuf[31]_i_7\ : label is "soft_lutpair2525";
  attribute SOFT_HLUTNM of \dwrSeqbuf[3]_i_2__0\ : label is "soft_lutpair2551";
  attribute SOFT_HLUTNM of \dwrSeqbuf[3]_i_3__0\ : label is "soft_lutpair2522";
  attribute SOFT_HLUTNM of \dwrSeqbuf[4]_i_2__0\ : label is "soft_lutpair2525";
  attribute SOFT_HLUTNM of \dwrSeqbuf[5]_i_2__0\ : label is "soft_lutpair2549";
  attribute SOFT_HLUTNM of \dwrSeqbuf[5]_i_3__0\ : label is "soft_lutpair2512";
  attribute SOFT_HLUTNM of \dwrSeqbuf[6]_i_2__0\ : label is "soft_lutpair2552";
  attribute SOFT_HLUTNM of \dwrSeqbuf[7]_i_2__0\ : label is "soft_lutpair2526";
  attribute SOFT_HLUTNM of \dwrSeqbuf[8]_i_2__0\ : label is "soft_lutpair2554";
  attribute SOFT_HLUTNM of \dwrSeqbuf[8]_i_3\ : label is "soft_lutpair2509";
  attribute SOFT_HLUTNM of \dwrSeqbuf[9]_i_1__0\ : label is "soft_lutpair2564";
  attribute SOFT_HLUTNM of \enSeqbuf_i_1__0\ : label is "soft_lutpair2547";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_i[0]_i_1\ : label is "soft_lutpair2561";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_i[1]_i_1\ : label is "soft_lutpair2561";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_i[1]_i_4\ : label is "soft_lutpair2555";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_i[1]_i_5\ : label is "soft_lutpair2528";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_i[1]_i_6\ : label is "soft_lutpair2529";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_i[1]_i_7\ : label is "soft_lutpair2527";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_to_mclk[0]_i_1\ : label is "soft_lutpair2529";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_to_mclk[1]_i_1\ : label is "soft_lutpair2562";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_to_mclk[3]_i_1\ : label is "soft_lutpair2555";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_to_mclk[4]_i_1\ : label is "soft_lutpair2577";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_to_mclk[5]_i_1\ : label is "soft_lutpair2527";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_to_mclk[6]_i_1\ : label is "soft_lutpair2577";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_to_mclk[7]_i_1\ : label is "soft_lutpair2578";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_to_mclk[8]_i_1\ : label is "soft_lutpair2528";
  attribute SOFT_HLUTNM of \ptr0Seqbuf_to_mclk[9]_i_2\ : label is "soft_lutpair2578";
  attribute SOFT_HLUTNM of \quad[0]_i_1__0\ : label is "soft_lutpair2548";
  attribute SOFT_HLUTNM of \quad[1]_i_1__0\ : label is "soft_lutpair2547";
  attribute SOFT_HLUTNM of \quad[2]_i_1__0\ : label is "soft_lutpair2546";
  attribute SOFT_HLUTNM of \quad[3]_i_1__0\ : label is "soft_lutpair2551";
  attribute SOFT_HLUTNM of \quad[4]_i_1__0\ : label is "soft_lutpair2550";
  attribute SOFT_HLUTNM of \quad[5]_i_1__0\ : label is "soft_lutpair2549";
  attribute SOFT_HLUTNM of \quad[6]_i_1__0\ : label is "soft_lutpair2552";
  attribute SOFT_HLUTNM of \quad[7]_i_1__0\ : label is "soft_lutpair2553";
  attribute SOFT_HLUTNM of \quad[8]_i_2\ : label is "soft_lutpair2554";
  attribute SOFT_HLUTNM of \rdySeq_i[0]_i_1\ : label is "soft_lutpair2543";
  attribute SOFT_HLUTNM of \rdySeq_i[1]_i_1\ : label is "soft_lutpair2543";
  attribute SOFT_HLUTNM of \reqOpToSeqClear_i[0]_i_1\ : label is "soft_lutpair2519";
  attribute SOFT_HLUTNM of reqOpToSeqClear_to_memclk_i_1 : label is "soft_lutpair2519";
  attribute SOFT_HLUTNM of \reqSeqbufBToSeqClear_i[0]_i_1\ : label is "soft_lutpair2518";
  attribute SOFT_HLUTNM of reqSeqbufBToSeqClear_to_memclk_i_1 : label is "soft_lutpair2518";
  attribute SOFT_HLUTNM of \retbuf[0][0]_i_10\ : label is "soft_lutpair2516";
  attribute SOFT_HLUTNM of \staTixVTrigger[7]_i_2\ : label is "soft_lutpair2537";
  attribute SOFT_HLUTNM of \start_i[1]_i_1\ : label is "soft_lutpair2558";
  attribute SOFT_HLUTNM of start_to_mclk_i_1 : label is "soft_lutpair2558";
  attribute SOFT_HLUTNM of \stateOp[0]_i_1__2\ : label is "soft_lutpair2537";
  attribute SOFT_HLUTNM of \stateOp[2]_i_11__0\ : label is "soft_lutpair2516";
  attribute SOFT_HLUTNM of \stateOp[2]_i_2__0\ : label is "soft_lutpair2515";
  attribute SOFT_HLUTNM of \stateOp[2]_i_4\ : label is "soft_lutpair2533";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of \stateOp_reg[2]_i_12\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \stateOp_reg[2]_i_6\ : label is 11;
  attribute SOFT_HLUTNM of \stateSeqbufB[0]_i_1__0\ : label is "soft_lutpair2541";
  attribute SOFT_HLUTNM of \stateSeqbufB[1]_i_1__0\ : label is "soft_lutpair2541";
  attribute SOFT_HLUTNM of \stateSeqbufB[2]_i_6\ : label is "soft_lutpair2510";
  attribute SOFT_HLUTNM of \stop_i[1]_i_1\ : label is "soft_lutpair2559";
  attribute SOFT_HLUTNM of \stop_lcl_i_2__0\ : label is "soft_lutpair2569";
  attribute SOFT_HLUTNM of stop_to_mclk_i_1 : label is "soft_lutpair2559";
  attribute SOFT_HLUTNM of \strbStart_i[0]_i_1\ : label is "soft_lutpair2517";
  attribute SOFT_HLUTNM of strbStart_memclk_i_1 : label is "soft_lutpair2539";
  attribute SOFT_HLUTNM of strbStart_to_memclk_i_1 : label is "soft_lutpair2533";
  attribute SOFT_HLUTNM of strbStart_wait_i_1 : label is "soft_lutpair2539";
  attribute SOFT_HLUTNM of \strbStop_i[0]_i_1\ : label is "soft_lutpair2568";
  attribute SOFT_HLUTNM of \strbStop_i_2__0\ : label is "soft_lutpair2515";
  attribute SOFT_HLUTNM of \strbStop_i_3__0\ : label is "soft_lutpair2514";
  attribute SOFT_HLUTNM of strbStop_memclk_i_1 : label is "soft_lutpair2538";
  attribute SOFT_HLUTNM of strbStop_to_memclk_i_1 : label is "soft_lutpair2568";
  attribute SOFT_HLUTNM of strbStop_wait_i_1 : label is "soft_lutpair2538";
  attribute SOFT_HLUTNM of strb_last_i_3 : label is "soft_lutpair2517";
  attribute SOFT_HLUTNM of \txAXIS_tdata[15]_i_20\ : label is "soft_lutpair2535";
  attribute SOFT_HLUTNM of \wordcntLast[28]_i_15\ : label is "soft_lutpair2565";
begin
  Q(31 downto 0) <= \^q\(31 downto 0);
  ackInvMemtrackClearMask <= \^ackinvmemtrackclearmask\;
  ackInvMemtrackSelect <= \^ackinvmemtrackselect\;
  ackInvMemtrackSet <= \^ackinvmemtrackset\;
  ackInvMemtrackSetMask <= \^ackinvmemtracksetmask\;
  avllenSeqbufMemtrackToHostif(0) <= \^avllenseqbufmemtracktohostif\(0);
  \mask_reg[0]_0\ <= \^mask_reg[0]_0\;
  \mask_reg[1]_0\ <= \^mask_reg[1]_0\;
  \mask_reg[2]_0\ <= \^mask_reg[2]_0\;
  \mask_reg[3]_0\ <= \^mask_reg[3]_0\;
  \mask_reg[4]_0\ <= \^mask_reg[4]_0\;
  \mask_reg[6]_0\ <= \^mask_reg[6]_0\;
  \mask_reg[7]_0\ <= \^mask_reg[7]_0\;
  memtrackGetInfoTixVState(1 downto 0) <= \^memtrackgetinfotixvstate\(1 downto 0);
  rng_reg_0 <= \^rng_reg_0\;
  \stateOp_reg[2]_0\ <= \^stateop_reg[2]_0\;
\FSM_onehot_stateSeq[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444444447"
    )
        port map (
      I0 => reqSeqbufBToSeqClear_memclk,
      I1 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I2 => TCapt,
      I3 => dneSeq,
      I4 => first,
      I5 => rdySeq,
      O => \FSM_onehot_stateSeq[0]_i_1__0_n_0\
    );
\FSM_onehot_stateSeq[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEF0"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \FSM_onehot_stateSeq[3]_i_2__0_n_0\,
      I2 => rdySeq,
      I3 => TCapt,
      O => \FSM_onehot_stateSeq[2]_i_1__0_n_0\
    );
\FSM_onehot_stateSeq[3]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \FSM_onehot_stateSeq[3]_i_2__0_n_0\,
      I2 => TCapt,
      O => \FSM_onehot_stateSeq[3]_i_1__0_n_0\
    );
\FSM_onehot_stateSeq[3]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11101111"
    )
        port map (
      I0 => stop_lcl_reg_n_0,
      I1 => strbStop_memclk_reg_n_0,
      I2 => \i_reg_n_0_[0]\,
      I3 => \FSM_onehot_stateSeq[3]_i_3__0_n_0\,
      I4 => \FSM_onehot_stateSeq[5]_i_8_n_0\,
      O => \FSM_onehot_stateSeq[3]_i_2__0_n_0\
    );
\FSM_onehot_stateSeq[3]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => stoTixVTrigger(0),
      I1 => stoTixVTrigger(4),
      I2 => stoTixVTrigger(2),
      I3 => stoTixVTrigger(7),
      I4 => \FSM_onehot_stateSeq[3]_i_4__0_n_0\,
      O => \FSM_onehot_stateSeq[3]_i_3__0_n_0\
    );
\FSM_onehot_stateSeq[3]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => stoTixVTrigger(6),
      I1 => stoTixVTrigger(5),
      I2 => stoTixVTrigger(1),
      I3 => stoTixVTrigger(3),
      O => \FSM_onehot_stateSeq[3]_i_4__0_n_0\
    );
\FSM_onehot_stateSeq[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAAF3AAFFAAC0AA"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_3__0_n_0\,
      I1 => \FSM_onehot_stateSeq[5]_i_4__0_n_0\,
      I2 => strbStart_memclk_reg_n_0,
      I3 => \FSM_onehot_stateSeq[5]_i_5__0_n_0\,
      I4 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I5 => \FSM_onehot_stateSeq[5]_i_7__0_n_0\,
      O => \FSM_onehot_stateSeq[5]_i_1__0_n_0\
    );
\FSM_onehot_stateSeq[5]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => reqSeqbufBToSeqClear_memclk,
      I1 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \FSM_onehot_stateSeq[5]_i_2__0_n_0\
    );
\FSM_onehot_stateSeq[5]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000203030302"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_8_n_0\,
      I1 => dneSeq,
      I2 => TCapt,
      I3 => rdySeq,
      I4 => ackSeqbufBToSeqClear,
      I5 => reqSeqbufBToSeqClear_memclk,
      O => \FSM_onehot_stateSeq[5]_i_3__0_n_0\
    );
\FSM_onehot_stateSeq[5]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => dneSeq,
      I1 => TCapt,
      O => \FSM_onehot_stateSeq[5]_i_4__0_n_0\
    );
\FSM_onehot_stateSeq[5]_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ackSeqbufBToSeqClear,
      I1 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \FSM_onehot_stateSeq[5]_i_5__0_n_0\
    );
\FSM_onehot_stateSeq[5]_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => dneSeq,
      I1 => rdySeq,
      I2 => ackSeqbufBToSeqClear,
      O => \FSM_onehot_stateSeq[5]_i_6__0_n_0\
    );
\FSM_onehot_stateSeq[5]_i_7__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => reqSeqbufBToSeqClear_memclk,
      I1 => reqOpToSeqClear_memclk,
      O => \FSM_onehot_stateSeq[5]_i_7__0_n_0\
    );
\FSM_onehot_stateSeq[5]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aSeqbuf[9]_i_6__0_n_0\,
      I1 => \aSeqbuf_reg_n_0_[6]\,
      I2 => \aSeqbuf_reg_n_0_[7]\,
      I3 => \aSeqbuf_reg_n_0_[8]\,
      I4 => \aSeqbuf_reg_n_0_[9]\,
      O => \FSM_onehot_stateSeq[5]_i_8_n_0\
    );
\FSM_onehot_stateSeq_reg[0]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '1'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateSeq[5]_i_1__0_n_0\,
      D => \FSM_onehot_stateSeq[0]_i_1__0_n_0\,
      PRE => AR(0),
      Q => first
    );
\FSM_onehot_stateSeq_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateSeq[5]_i_1__0_n_0\,
      CLR => AR(0),
      D => first,
      Q => rdySeq
    );
\FSM_onehot_stateSeq_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateSeq[5]_i_1__0_n_0\,
      CLR => AR(0),
      D => \FSM_onehot_stateSeq[2]_i_1__0_n_0\,
      Q => TCapt
    );
\FSM_onehot_stateSeq_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateSeq[5]_i_1__0_n_0\,
      CLR => AR(0),
      D => \FSM_onehot_stateSeq[3]_i_1__0_n_0\,
      Q => dneSeq
    );
\FSM_onehot_stateSeq_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateSeq[5]_i_1__0_n_0\,
      CLR => AR(0),
      D => dneSeq,
      Q => \FSM_onehot_stateSeq_reg_n_0_[4]\
    );
\FSM_onehot_stateSeq_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \FSM_onehot_stateSeq[5]_i_1__0_n_0\,
      CLR => AR(0),
      D => \FSM_onehot_stateSeq[5]_i_2__0_n_0\,
      Q => ackSeqbufBToSeqClear
    );
\TCaptMax_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \TCaptMax_reg[7]_0\(0),
      Q => \TCaptMax_reg_n_0_[0]\
    );
\TCaptMax_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(2),
      Q => \TCaptMax_reg_n_0_[10]\
    );
\TCaptMax_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(3),
      Q => \TCaptMax_reg_n_0_[11]\
    );
\TCaptMax_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(4),
      Q => \TCaptMax_reg_n_0_[12]\
    );
\TCaptMax_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(5),
      Q => \TCaptMax_reg_n_0_[13]\
    );
\TCaptMax_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(6),
      Q => \TCaptMax_reg_n_0_[14]\
    );
\TCaptMax_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(7),
      Q => \TCaptMax_reg_n_0_[15]\
    );
\TCaptMax_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(8),
      Q => \TCaptMax_reg_n_0_[16]\
    );
\TCaptMax_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(9),
      Q => \TCaptMax_reg_n_0_[17]\
    );
\TCaptMax_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(10),
      Q => \TCaptMax_reg_n_0_[18]\
    );
\TCaptMax_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(11),
      Q => \TCaptMax_reg_n_0_[19]\
    );
\TCaptMax_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \TCaptMax_reg[7]_0\(1),
      Q => \TCaptMax_reg_n_0_[1]\
    );
\TCaptMax_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(12),
      Q => \TCaptMax_reg_n_0_[20]\
    );
\TCaptMax_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(13),
      Q => \TCaptMax_reg_n_0_[21]\
    );
\TCaptMax_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(14),
      Q => \TCaptMax_reg_n_0_[22]\
    );
\TCaptMax_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(15),
      Q => \TCaptMax_reg_n_0_[23]\
    );
\TCaptMax_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(16),
      Q => \TCaptMax_reg_n_0_[24]\
    );
\TCaptMax_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(17),
      Q => \TCaptMax_reg_n_0_[25]\
    );
\TCaptMax_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(18),
      Q => \TCaptMax_reg_n_0_[26]\
    );
\TCaptMax_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(19),
      Q => \TCaptMax_reg_n_0_[27]\
    );
\TCaptMax_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(20),
      Q => \TCaptMax_reg_n_0_[28]\
    );
\TCaptMax_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(21),
      Q => \TCaptMax_reg_n_0_[29]\
    );
\TCaptMax_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \TCaptMax_reg[7]_0\(2),
      Q => \TCaptMax_reg_n_0_[2]\
    );
\TCaptMax_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(22),
      Q => \TCaptMax_reg_n_0_[30]\
    );
\TCaptMax_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(23),
      Q => \TCaptMax_reg_n_0_[31]\
    );
\TCaptMax_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \TCaptMax_reg[7]_0\(3),
      Q => \TCaptMax_reg_n_0_[3]\
    );
\TCaptMax_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \TCaptMax_reg[7]_0\(4),
      Q => \TCaptMax_reg_n_0_[4]\
    );
\TCaptMax_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \TCaptMax_reg[7]_0\(5),
      Q => \TCaptMax_reg_n_0_[5]\
    );
\TCaptMax_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \TCaptMax_reg[7]_0\(6),
      Q => \TCaptMax_reg_n_0_[6]\
    );
\TCaptMax_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \TCaptMax_reg[7]_0\(7),
      Q => \TCaptMax_reg_n_0_[7]\
    );
\TCaptMax_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(0),
      Q => \TCaptMax_reg_n_0_[8]\
    );
\TCaptMax_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCaptMax_reg[31]_0\(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(1),
      Q => \TCaptMax_reg_n_0_[9]\
    );
\TCapt[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \TCapt_reg_n_0_[0]\,
      I1 => first,
      O => \TCapt__0\(0)
    );
\TCapt[10]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(10),
      I1 => first,
      O => \TCapt__0\(10)
    );
\TCapt[11]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(11),
      I1 => first,
      O => \TCapt__0\(11)
    );
\TCapt[12]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(12),
      I1 => first,
      O => \TCapt__0\(12)
    );
\TCapt[13]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(13),
      I1 => first,
      O => \TCapt__0\(13)
    );
\TCapt[14]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(14),
      I1 => first,
      O => \TCapt__0\(14)
    );
\TCapt[15]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(15),
      I1 => first,
      O => \TCapt__0\(15)
    );
\TCapt[16]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(16),
      I1 => first,
      O => \TCapt__0\(16)
    );
\TCapt[17]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(17),
      I1 => first,
      O => \TCapt__0\(17)
    );
\TCapt[18]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(18),
      I1 => first,
      O => \TCapt__0\(18)
    );
\TCapt[19]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(19),
      I1 => first,
      O => \TCapt__0\(19)
    );
\TCapt[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(1),
      I1 => first,
      O => \TCapt__0\(1)
    );
\TCapt[20]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(20),
      I1 => first,
      O => \TCapt__0\(20)
    );
\TCapt[21]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(21),
      I1 => first,
      O => \TCapt__0\(21)
    );
\TCapt[22]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(22),
      I1 => first,
      O => \TCapt__0\(22)
    );
\TCapt[23]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(23),
      I1 => first,
      O => \TCapt__0\(23)
    );
\TCapt[24]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(24),
      I1 => first,
      O => \TCapt__0\(24)
    );
\TCapt[25]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(25),
      I1 => first,
      O => \TCapt__0\(25)
    );
\TCapt[26]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(26),
      I1 => first,
      O => \TCapt__0\(26)
    );
\TCapt[27]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(27),
      I1 => first,
      O => \TCapt__0\(27)
    );
\TCapt[28]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(28),
      I1 => first,
      O => \TCapt__0\(28)
    );
\TCapt[29]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(29),
      I1 => first,
      O => \TCapt__0\(29)
    );
\TCapt[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(2),
      I1 => first,
      O => \TCapt__0\(2)
    );
\TCapt[30]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(30),
      I1 => first,
      O => \TCapt__0\(30)
    );
\TCapt[31]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(31),
      I1 => first,
      O => \TCapt__0\(31)
    );
\TCapt[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(3),
      I1 => first,
      O => \TCapt__0\(3)
    );
\TCapt[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(4),
      I1 => first,
      O => \TCapt__0\(4)
    );
\TCapt[5]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(5),
      I1 => first,
      O => \TCapt__0\(5)
    );
\TCapt[6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(6),
      I1 => first,
      O => \TCapt__0\(6)
    );
\TCapt[7]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(7),
      I1 => first,
      O => \TCapt__0\(7)
    );
\TCapt[8]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(8),
      I1 => first,
      O => \TCapt__0\(8)
    );
\TCapt[9]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in15(9),
      I1 => first,
      O => \TCapt__0\(9)
    );
\TCapt_i[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"5D"
    )
        port map (
      I0 => TCapt_i(0),
      I1 => TCapt_i(1),
      I2 => \TCapt_i_reg[1]_i_2_n_5\,
      O => \TCapt_i[0]_i_1_n_0\
    );
\TCapt_i[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7C"
    )
        port map (
      I0 => \TCapt_i_reg[1]_i_2_n_5\,
      I1 => TCapt_i(1),
      I2 => TCapt_i(0),
      O => \TCapt_i[1]_i_1_n_0\
    );
\TCapt_i[1]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \TCapt_reg_n_0_[12]\,
      I1 => TCapt_to_mclk(12),
      I2 => \TCapt_reg_n_0_[13]\,
      I3 => TCapt_to_mclk(13),
      I4 => TCapt_to_mclk(14),
      I5 => \TCapt_reg_n_0_[14]\,
      O => \TCapt_i[1]_i_10_n_0\
    );
\TCapt_i[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \TCapt_reg_n_0_[10]\,
      I1 => TCapt_to_mclk(10),
      I2 => \TCapt_reg_n_0_[9]\,
      I3 => TCapt_to_mclk(9),
      I4 => TCapt_to_mclk(11),
      I5 => \TCapt_reg_n_0_[11]\,
      O => \TCapt_i[1]_i_11_n_0\
    );
\TCapt_i[1]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \TCapt_reg_n_0_[7]\,
      I1 => TCapt_to_mclk(7),
      I2 => \TCapt_reg_n_0_[6]\,
      I3 => TCapt_to_mclk(6),
      I4 => TCapt_to_mclk(8),
      I5 => \TCapt_reg_n_0_[8]\,
      O => \TCapt_i[1]_i_12_n_0\
    );
\TCapt_i[1]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \TCapt_reg_n_0_[5]\,
      I1 => TCapt_to_mclk(5),
      I2 => \TCapt_reg_n_0_[3]\,
      I3 => TCapt_to_mclk(3),
      I4 => TCapt_to_mclk(4),
      I5 => \TCapt_reg_n_0_[4]\,
      O => \TCapt_i[1]_i_13_n_0\
    );
\TCapt_i[1]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \TCapt_reg_n_0_[1]\,
      I1 => TCapt_to_mclk(1),
      I2 => \TCapt_reg_n_0_[0]\,
      I3 => TCapt_to_mclk(0),
      I4 => TCapt_to_mclk(2),
      I5 => \TCapt_reg_n_0_[2]\,
      O => \TCapt_i[1]_i_14_n_0\
    );
\TCapt_i[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => TCapt_to_mclk(31),
      I1 => \TCapt_reg_n_0_[31]\,
      I2 => TCapt_to_mclk(30),
      I3 => \TCapt_reg_n_0_[30]\,
      O => \TCapt_i[1]_i_4_n_0\
    );
\TCapt_i[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \TCapt_reg_n_0_[27]\,
      I1 => TCapt_to_mclk(27),
      I2 => \TCapt_reg_n_0_[28]\,
      I3 => TCapt_to_mclk(28),
      I4 => TCapt_to_mclk(29),
      I5 => \TCapt_reg_n_0_[29]\,
      O => \TCapt_i[1]_i_5_n_0\
    );
\TCapt_i[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \TCapt_reg_n_0_[24]\,
      I1 => TCapt_to_mclk(24),
      I2 => \TCapt_reg_n_0_[25]\,
      I3 => TCapt_to_mclk(25),
      I4 => TCapt_to_mclk(26),
      I5 => \TCapt_reg_n_0_[26]\,
      O => \TCapt_i[1]_i_6_n_0\
    );
\TCapt_i[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \TCapt_reg_n_0_[23]\,
      I1 => TCapt_to_mclk(23),
      I2 => \TCapt_reg_n_0_[21]\,
      I3 => TCapt_to_mclk(21),
      I4 => TCapt_to_mclk(22),
      I5 => \TCapt_reg_n_0_[22]\,
      O => \TCapt_i[1]_i_7_n_0\
    );
\TCapt_i[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \TCapt_reg_n_0_[18]\,
      I1 => TCapt_to_mclk(18),
      I2 => \TCapt_reg_n_0_[19]\,
      I3 => TCapt_to_mclk(19),
      I4 => TCapt_to_mclk(20),
      I5 => \TCapt_reg_n_0_[20]\,
      O => \TCapt_i[1]_i_8_n_0\
    );
\TCapt_i[1]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \TCapt_reg_n_0_[15]\,
      I1 => TCapt_to_mclk(15),
      I2 => \TCapt_reg_n_0_[16]\,
      I3 => TCapt_to_mclk(16),
      I4 => TCapt_to_mclk(17),
      I5 => \TCapt_reg_n_0_[17]\,
      O => \TCapt_i[1]_i_9_n_0\
    );
\TCapt_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \TCapt_i[0]_i_1_n_0\,
      Q => TCapt_i(0)
    );
\TCapt_i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \TCapt_i[1]_i_1_n_0\,
      Q => TCapt_i(1)
    );
\TCapt_i_reg[1]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \TCapt_i_reg[1]_i_3_n_0\,
      CI_TOP => '0',
      CO(7 downto 3) => \NLW_TCapt_i_reg[1]_i_2_CO_UNCONNECTED\(7 downto 3),
      CO(2) => \TCapt_i_reg[1]_i_2_n_5\,
      CO(1) => \TCapt_i_reg[1]_i_2_n_6\,
      CO(0) => \TCapt_i_reg[1]_i_2_n_7\,
      DI(7 downto 0) => B"00000111",
      O(7 downto 0) => \NLW_TCapt_i_reg[1]_i_2_O_UNCONNECTED\(7 downto 0),
      S(7 downto 3) => B"00000",
      S(2) => \TCapt_i[1]_i_4_n_0\,
      S(1) => \TCapt_i[1]_i_5_n_0\,
      S(0) => \TCapt_i[1]_i_6_n_0\
    );
\TCapt_i_reg[1]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \TCapt_i_reg[1]_i_3_n_0\,
      CO(6) => \TCapt_i_reg[1]_i_3_n_1\,
      CO(5) => \TCapt_i_reg[1]_i_3_n_2\,
      CO(4) => \TCapt_i_reg[1]_i_3_n_3\,
      CO(3) => \TCapt_i_reg[1]_i_3_n_4\,
      CO(2) => \TCapt_i_reg[1]_i_3_n_5\,
      CO(1) => \TCapt_i_reg[1]_i_3_n_6\,
      CO(0) => \TCapt_i_reg[1]_i_3_n_7\,
      DI(7 downto 0) => B"11111111",
      O(7 downto 0) => \NLW_TCapt_i_reg[1]_i_3_O_UNCONNECTED\(7 downto 0),
      S(7) => \TCapt_i[1]_i_7_n_0\,
      S(6) => \TCapt_i[1]_i_8_n_0\,
      S(5) => \TCapt_i[1]_i_9_n_0\,
      S(4) => \TCapt_i[1]_i_10_n_0\,
      S(3) => \TCapt_i[1]_i_11_n_0\,
      S(2) => \TCapt_i[1]_i_12_n_0\,
      S(1) => \TCapt_i[1]_i_13_n_0\,
      S(0) => \TCapt_i[1]_i_14_n_0\
    );
\TCapt_mclk[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \TCapt_mclk[31]_i_2_n_0\,
      I1 => \TCapt_mclk[31]_i_3_n_0\,
      I2 => \TCapt_mclk[31]_i_4_n_0\,
      I3 => \TCapt_mclk[31]_i_5_n_0\,
      O => \TCapt_mclk[31]_i_1_n_0\
    );
\TCapt_mclk[31]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => TCapt_to_mclkm1(12),
      I1 => TCapt_to_mclkm2(12),
      I2 => TCapt_to_mclkm2(14),
      I3 => TCapt_to_mclkm1(14),
      I4 => TCapt_to_mclkm2(13),
      I5 => TCapt_to_mclkm1(13),
      O => \TCapt_mclk[31]_i_10_n_0\
    );
\TCapt_mclk[31]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => TCapt_to_mclkm1(15),
      I1 => TCapt_to_mclkm2(15),
      I2 => TCapt_to_mclkm2(17),
      I3 => TCapt_to_mclkm1(17),
      I4 => TCapt_to_mclkm2(16),
      I5 => TCapt_to_mclkm1(16),
      O => \TCapt_mclk[31]_i_11_n_0\
    );
\TCapt_mclk[31]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => TCapt_to_mclkm1(3),
      I1 => TCapt_to_mclkm2(3),
      I2 => TCapt_to_mclkm2(5),
      I3 => TCapt_to_mclkm1(5),
      I4 => TCapt_to_mclkm2(4),
      I5 => TCapt_to_mclkm1(4),
      O => \TCapt_mclk[31]_i_12_n_0\
    );
\TCapt_mclk[31]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => TCapt_to_mclkm1(0),
      I1 => TCapt_to_mclkm2(0),
      I2 => TCapt_to_mclkm2(2),
      I3 => TCapt_to_mclkm1(2),
      I4 => TCapt_to_mclkm2(1),
      I5 => TCapt_to_mclkm1(1),
      O => \TCapt_mclk[31]_i_13_n_0\
    );
\TCapt_mclk[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => TCapt_to_mclkm1(27),
      I1 => TCapt_to_mclkm2(27),
      I2 => TCapt_to_mclkm2(29),
      I3 => TCapt_to_mclkm1(29),
      I4 => TCapt_to_mclkm2(28),
      I5 => TCapt_to_mclkm1(28),
      O => \TCapt_mclk[31]_i_2_n_0\
    );
\TCapt_mclk[31]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => TCapt_to_mclkm1(24),
      I1 => TCapt_to_mclkm2(24),
      I2 => TCapt_to_mclkm2(26),
      I3 => TCapt_to_mclkm1(26),
      I4 => TCapt_to_mclkm2(25),
      I5 => TCapt_to_mclkm1(25),
      O => \TCapt_mclk[31]_i_3_n_0\
    );
\TCapt_mclk[31]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \TCapt_mclk[31]_i_6_n_0\,
      I1 => \TCapt_mclk[31]_i_7_n_0\,
      I2 => \TCapt_mclk[31]_i_8_n_0\,
      I3 => \TCapt_mclk[31]_i_9_n_0\,
      I4 => \TCapt_mclk[31]_i_10_n_0\,
      I5 => \TCapt_mclk[31]_i_11_n_0\,
      O => \TCapt_mclk[31]_i_4_n_0\
    );
\TCapt_mclk[31]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000000000"
    )
        port map (
      I0 => TCapt_to_mclkm2(31),
      I1 => TCapt_to_mclkm1(31),
      I2 => TCapt_to_mclkm2(30),
      I3 => TCapt_to_mclkm1(30),
      I4 => \TCapt_mclk[31]_i_12_n_0\,
      I5 => \TCapt_mclk[31]_i_13_n_0\,
      O => \TCapt_mclk[31]_i_5_n_0\
    );
\TCapt_mclk[31]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => TCapt_to_mclkm1(9),
      I1 => TCapt_to_mclkm2(9),
      I2 => TCapt_to_mclkm2(11),
      I3 => TCapt_to_mclkm1(11),
      I4 => TCapt_to_mclkm2(10),
      I5 => TCapt_to_mclkm1(10),
      O => \TCapt_mclk[31]_i_6_n_0\
    );
\TCapt_mclk[31]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => TCapt_to_mclkm1(6),
      I1 => TCapt_to_mclkm2(6),
      I2 => TCapt_to_mclkm2(8),
      I3 => TCapt_to_mclkm1(8),
      I4 => TCapt_to_mclkm2(7),
      I5 => TCapt_to_mclkm1(7),
      O => \TCapt_mclk[31]_i_7_n_0\
    );
\TCapt_mclk[31]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => TCapt_to_mclkm1(18),
      I1 => TCapt_to_mclkm2(18),
      I2 => TCapt_to_mclkm2(20),
      I3 => TCapt_to_mclkm1(20),
      I4 => TCapt_to_mclkm2(19),
      I5 => TCapt_to_mclkm1(19),
      O => \TCapt_mclk[31]_i_8_n_0\
    );
\TCapt_mclk[31]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => TCapt_to_mclkm1(21),
      I1 => TCapt_to_mclkm2(21),
      I2 => TCapt_to_mclkm2(23),
      I3 => TCapt_to_mclkm1(23),
      I4 => TCapt_to_mclkm2(22),
      I5 => TCapt_to_mclkm1(22),
      O => \TCapt_mclk[31]_i_9_n_0\
    );
\TCapt_mclk_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(0),
      Q => \^q\(0)
    );
\TCapt_mclk_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(10),
      Q => \^q\(10)
    );
\TCapt_mclk_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(11),
      Q => \^q\(11)
    );
\TCapt_mclk_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(12),
      Q => \^q\(12)
    );
\TCapt_mclk_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(13),
      Q => \^q\(13)
    );
\TCapt_mclk_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(14),
      Q => \^q\(14)
    );
\TCapt_mclk_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(15),
      Q => \^q\(15)
    );
\TCapt_mclk_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(16),
      Q => \^q\(16)
    );
\TCapt_mclk_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(17),
      Q => \^q\(17)
    );
\TCapt_mclk_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(18),
      Q => \^q\(18)
    );
\TCapt_mclk_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(19),
      Q => \^q\(19)
    );
\TCapt_mclk_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(1),
      Q => \^q\(1)
    );
\TCapt_mclk_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(20),
      Q => \^q\(20)
    );
\TCapt_mclk_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(21),
      Q => \^q\(21)
    );
\TCapt_mclk_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(22),
      Q => \^q\(22)
    );
\TCapt_mclk_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(23),
      Q => \^q\(23)
    );
\TCapt_mclk_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(24),
      Q => \^q\(24)
    );
\TCapt_mclk_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(25),
      Q => \^q\(25)
    );
\TCapt_mclk_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(26),
      Q => \^q\(26)
    );
\TCapt_mclk_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(27),
      Q => \^q\(27)
    );
\TCapt_mclk_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(28),
      Q => \^q\(28)
    );
\TCapt_mclk_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(29),
      Q => \^q\(29)
    );
\TCapt_mclk_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(2),
      Q => \^q\(2)
    );
\TCapt_mclk_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(30),
      Q => \^q\(30)
    );
\TCapt_mclk_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(31),
      Q => \^q\(31)
    );
\TCapt_mclk_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(3),
      Q => \^q\(3)
    );
\TCapt_mclk_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(4),
      Q => \^q\(4)
    );
\TCapt_mclk_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(5),
      Q => \^q\(5)
    );
\TCapt_mclk_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(6),
      Q => \^q\(6)
    );
\TCapt_mclk_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(7),
      Q => \^q\(7)
    );
\TCapt_mclk_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(8),
      Q => \^q\(8)
    );
\TCapt_mclk_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \TCapt_mclk[31]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm2(9),
      Q => \^q\(9)
    );
\TCapt_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(0),
      Q => \TCapt_reg_n_0_[0]\
    );
\TCapt_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(10),
      Q => \TCapt_reg_n_0_[10]\
    );
\TCapt_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(11),
      Q => \TCapt_reg_n_0_[11]\
    );
\TCapt_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(12),
      Q => \TCapt_reg_n_0_[12]\
    );
\TCapt_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(13),
      Q => \TCapt_reg_n_0_[13]\
    );
\TCapt_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(14),
      Q => \TCapt_reg_n_0_[14]\
    );
\TCapt_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(15),
      Q => \TCapt_reg_n_0_[15]\
    );
\TCapt_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(16),
      Q => \TCapt_reg_n_0_[16]\
    );
\TCapt_reg[16]_i_2__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \TCapt_reg[8]_i_2__0_n_0\,
      CI_TOP => '0',
      CO(7) => \TCapt_reg[16]_i_2__0_n_0\,
      CO(6) => \TCapt_reg[16]_i_2__0_n_1\,
      CO(5) => \TCapt_reg[16]_i_2__0_n_2\,
      CO(4) => \TCapt_reg[16]_i_2__0_n_3\,
      CO(3) => \TCapt_reg[16]_i_2__0_n_4\,
      CO(2) => \TCapt_reg[16]_i_2__0_n_5\,
      CO(1) => \TCapt_reg[16]_i_2__0_n_6\,
      CO(0) => \TCapt_reg[16]_i_2__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in15(16 downto 9),
      S(7) => \TCapt_reg_n_0_[16]\,
      S(6) => \TCapt_reg_n_0_[15]\,
      S(5) => \TCapt_reg_n_0_[14]\,
      S(4) => \TCapt_reg_n_0_[13]\,
      S(3) => \TCapt_reg_n_0_[12]\,
      S(2) => \TCapt_reg_n_0_[11]\,
      S(1) => \TCapt_reg_n_0_[10]\,
      S(0) => \TCapt_reg_n_0_[9]\
    );
\TCapt_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(17),
      Q => \TCapt_reg_n_0_[17]\
    );
\TCapt_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(18),
      Q => \TCapt_reg_n_0_[18]\
    );
\TCapt_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(19),
      Q => \TCapt_reg_n_0_[19]\
    );
\TCapt_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(1),
      Q => \TCapt_reg_n_0_[1]\
    );
\TCapt_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(20),
      Q => \TCapt_reg_n_0_[20]\
    );
\TCapt_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(21),
      Q => \TCapt_reg_n_0_[21]\
    );
\TCapt_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(22),
      Q => \TCapt_reg_n_0_[22]\
    );
\TCapt_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(23),
      Q => \TCapt_reg_n_0_[23]\
    );
\TCapt_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(24),
      Q => \TCapt_reg_n_0_[24]\
    );
\TCapt_reg[24]_i_2__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \TCapt_reg[16]_i_2__0_n_0\,
      CI_TOP => '0',
      CO(7) => \TCapt_reg[24]_i_2__0_n_0\,
      CO(6) => \TCapt_reg[24]_i_2__0_n_1\,
      CO(5) => \TCapt_reg[24]_i_2__0_n_2\,
      CO(4) => \TCapt_reg[24]_i_2__0_n_3\,
      CO(3) => \TCapt_reg[24]_i_2__0_n_4\,
      CO(2) => \TCapt_reg[24]_i_2__0_n_5\,
      CO(1) => \TCapt_reg[24]_i_2__0_n_6\,
      CO(0) => \TCapt_reg[24]_i_2__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in15(24 downto 17),
      S(7) => \TCapt_reg_n_0_[24]\,
      S(6) => \TCapt_reg_n_0_[23]\,
      S(5) => \TCapt_reg_n_0_[22]\,
      S(4) => \TCapt_reg_n_0_[21]\,
      S(3) => \TCapt_reg_n_0_[20]\,
      S(2) => \TCapt_reg_n_0_[19]\,
      S(1) => \TCapt_reg_n_0_[18]\,
      S(0) => \TCapt_reg_n_0_[17]\
    );
\TCapt_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(25),
      Q => \TCapt_reg_n_0_[25]\
    );
\TCapt_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(26),
      Q => \TCapt_reg_n_0_[26]\
    );
\TCapt_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(27),
      Q => \TCapt_reg_n_0_[27]\
    );
\TCapt_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(28),
      Q => \TCapt_reg_n_0_[28]\
    );
\TCapt_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(29),
      Q => \TCapt_reg_n_0_[29]\
    );
\TCapt_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(2),
      Q => \TCapt_reg_n_0_[2]\
    );
\TCapt_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(30),
      Q => \TCapt_reg_n_0_[30]\
    );
\TCapt_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(31),
      Q => \TCapt_reg_n_0_[31]\
    );
\TCapt_reg[31]_i_2__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \TCapt_reg[24]_i_2__0_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_TCapt_reg[31]_i_2__0_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \TCapt_reg[31]_i_2__0_n_2\,
      CO(4) => \TCapt_reg[31]_i_2__0_n_3\,
      CO(3) => \TCapt_reg[31]_i_2__0_n_4\,
      CO(2) => \TCapt_reg[31]_i_2__0_n_5\,
      CO(1) => \TCapt_reg[31]_i_2__0_n_6\,
      CO(0) => \TCapt_reg[31]_i_2__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NLW_TCapt_reg[31]_i_2__0_O_UNCONNECTED\(7),
      O(6 downto 0) => in15(31 downto 25),
      S(7) => '0',
      S(6) => \TCapt_reg_n_0_[31]\,
      S(5) => \TCapt_reg_n_0_[30]\,
      S(4) => \TCapt_reg_n_0_[29]\,
      S(3) => \TCapt_reg_n_0_[28]\,
      S(2) => \TCapt_reg_n_0_[27]\,
      S(1) => \TCapt_reg_n_0_[26]\,
      S(0) => \TCapt_reg_n_0_[25]\
    );
\TCapt_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(3),
      Q => \TCapt_reg_n_0_[3]\
    );
\TCapt_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(4),
      Q => \TCapt_reg_n_0_[4]\
    );
\TCapt_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(5),
      Q => \TCapt_reg_n_0_[5]\
    );
\TCapt_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(6),
      Q => \TCapt_reg_n_0_[6]\
    );
\TCapt_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(7),
      Q => \TCapt_reg_n_0_[7]\
    );
\TCapt_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(8),
      Q => \TCapt_reg_n_0_[8]\
    );
\TCapt_reg[8]_i_2__0\: unisim.vcomponents.CARRY8
     port map (
      CI => \TCapt_reg_n_0_[0]\,
      CI_TOP => '0',
      CO(7) => \TCapt_reg[8]_i_2__0_n_0\,
      CO(6) => \TCapt_reg[8]_i_2__0_n_1\,
      CO(5) => \TCapt_reg[8]_i_2__0_n_2\,
      CO(4) => \TCapt_reg[8]_i_2__0_n_3\,
      CO(3) => \TCapt_reg[8]_i_2__0_n_4\,
      CO(2) => \TCapt_reg[8]_i_2__0_n_5\,
      CO(1) => \TCapt_reg[8]_i_2__0_n_6\,
      CO(0) => \TCapt_reg[8]_i_2__0_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in15(8 downto 1),
      S(7) => \TCapt_reg_n_0_[8]\,
      S(6) => \TCapt_reg_n_0_[7]\,
      S(5) => \TCapt_reg_n_0_[6]\,
      S(4) => \TCapt_reg_n_0_[5]\,
      S(3) => \TCapt_reg_n_0_[4]\,
      S(2) => \TCapt_reg_n_0_[3]\,
      S(1) => \TCapt_reg_n_0_[2]\,
      S(0) => \TCapt_reg_n_0_[1]\
    );
\TCapt_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \TCapt__0\(9),
      Q => \TCapt_reg_n_0_[9]\
    );
\TCapt_to_mclk[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => TCapt_i(1),
      I1 => \TCapt_i_reg[1]_i_2_n_5\,
      I2 => TCapt_i(0),
      O => \TCapt_to_mclk[31]_i_1_n_0\
    );
\TCapt_to_mclk_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[0]\,
      Q => TCapt_to_mclk(0)
    );
\TCapt_to_mclk_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[10]\,
      Q => TCapt_to_mclk(10)
    );
\TCapt_to_mclk_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[11]\,
      Q => TCapt_to_mclk(11)
    );
\TCapt_to_mclk_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[12]\,
      Q => TCapt_to_mclk(12)
    );
\TCapt_to_mclk_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[13]\,
      Q => TCapt_to_mclk(13)
    );
\TCapt_to_mclk_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[14]\,
      Q => TCapt_to_mclk(14)
    );
\TCapt_to_mclk_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[15]\,
      Q => TCapt_to_mclk(15)
    );
\TCapt_to_mclk_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[16]\,
      Q => TCapt_to_mclk(16)
    );
\TCapt_to_mclk_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[17]\,
      Q => TCapt_to_mclk(17)
    );
\TCapt_to_mclk_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[18]\,
      Q => TCapt_to_mclk(18)
    );
\TCapt_to_mclk_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[19]\,
      Q => TCapt_to_mclk(19)
    );
\TCapt_to_mclk_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[1]\,
      Q => TCapt_to_mclk(1)
    );
\TCapt_to_mclk_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[20]\,
      Q => TCapt_to_mclk(20)
    );
\TCapt_to_mclk_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[21]\,
      Q => TCapt_to_mclk(21)
    );
\TCapt_to_mclk_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[22]\,
      Q => TCapt_to_mclk(22)
    );
\TCapt_to_mclk_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[23]\,
      Q => TCapt_to_mclk(23)
    );
\TCapt_to_mclk_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[24]\,
      Q => TCapt_to_mclk(24)
    );
\TCapt_to_mclk_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[25]\,
      Q => TCapt_to_mclk(25)
    );
\TCapt_to_mclk_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[26]\,
      Q => TCapt_to_mclk(26)
    );
\TCapt_to_mclk_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[27]\,
      Q => TCapt_to_mclk(27)
    );
\TCapt_to_mclk_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[28]\,
      Q => TCapt_to_mclk(28)
    );
\TCapt_to_mclk_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[29]\,
      Q => TCapt_to_mclk(29)
    );
\TCapt_to_mclk_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[2]\,
      Q => TCapt_to_mclk(2)
    );
\TCapt_to_mclk_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[30]\,
      Q => TCapt_to_mclk(30)
    );
\TCapt_to_mclk_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[31]\,
      Q => TCapt_to_mclk(31)
    );
\TCapt_to_mclk_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[3]\,
      Q => TCapt_to_mclk(3)
    );
\TCapt_to_mclk_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[4]\,
      Q => TCapt_to_mclk(4)
    );
\TCapt_to_mclk_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[5]\,
      Q => TCapt_to_mclk(5)
    );
\TCapt_to_mclk_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[6]\,
      Q => TCapt_to_mclk(6)
    );
\TCapt_to_mclk_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[7]\,
      Q => TCapt_to_mclk(7)
    );
\TCapt_to_mclk_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[8]\,
      Q => TCapt_to_mclk(8)
    );
\TCapt_to_mclk_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \TCapt_to_mclk[31]_i_1_n_0\,
      CLR => AR(0),
      D => \TCapt_reg_n_0_[9]\,
      Q => TCapt_to_mclk(9)
    );
\TCapt_to_mclkm1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(0),
      Q => TCapt_to_mclkm1(0)
    );
\TCapt_to_mclkm1_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(10),
      Q => TCapt_to_mclkm1(10)
    );
\TCapt_to_mclkm1_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(11),
      Q => TCapt_to_mclkm1(11)
    );
\TCapt_to_mclkm1_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(12),
      Q => TCapt_to_mclkm1(12)
    );
\TCapt_to_mclkm1_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(13),
      Q => TCapt_to_mclkm1(13)
    );
\TCapt_to_mclkm1_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(14),
      Q => TCapt_to_mclkm1(14)
    );
\TCapt_to_mclkm1_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(15),
      Q => TCapt_to_mclkm1(15)
    );
\TCapt_to_mclkm1_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(16),
      Q => TCapt_to_mclkm1(16)
    );
\TCapt_to_mclkm1_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(17),
      Q => TCapt_to_mclkm1(17)
    );
\TCapt_to_mclkm1_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(18),
      Q => TCapt_to_mclkm1(18)
    );
\TCapt_to_mclkm1_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(19),
      Q => TCapt_to_mclkm1(19)
    );
\TCapt_to_mclkm1_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(1),
      Q => TCapt_to_mclkm1(1)
    );
\TCapt_to_mclkm1_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(20),
      Q => TCapt_to_mclkm1(20)
    );
\TCapt_to_mclkm1_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(21),
      Q => TCapt_to_mclkm1(21)
    );
\TCapt_to_mclkm1_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(22),
      Q => TCapt_to_mclkm1(22)
    );
\TCapt_to_mclkm1_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(23),
      Q => TCapt_to_mclkm1(23)
    );
\TCapt_to_mclkm1_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(24),
      Q => TCapt_to_mclkm1(24)
    );
\TCapt_to_mclkm1_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(25),
      Q => TCapt_to_mclkm1(25)
    );
\TCapt_to_mclkm1_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(26),
      Q => TCapt_to_mclkm1(26)
    );
\TCapt_to_mclkm1_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(27),
      Q => TCapt_to_mclkm1(27)
    );
\TCapt_to_mclkm1_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(28),
      Q => TCapt_to_mclkm1(28)
    );
\TCapt_to_mclkm1_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(29),
      Q => TCapt_to_mclkm1(29)
    );
\TCapt_to_mclkm1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(2),
      Q => TCapt_to_mclkm1(2)
    );
\TCapt_to_mclkm1_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(30),
      Q => TCapt_to_mclkm1(30)
    );
\TCapt_to_mclkm1_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(31),
      Q => TCapt_to_mclkm1(31)
    );
\TCapt_to_mclkm1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(3),
      Q => TCapt_to_mclkm1(3)
    );
\TCapt_to_mclkm1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(4),
      Q => TCapt_to_mclkm1(4)
    );
\TCapt_to_mclkm1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(5),
      Q => TCapt_to_mclkm1(5)
    );
\TCapt_to_mclkm1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(6),
      Q => TCapt_to_mclkm1(6)
    );
\TCapt_to_mclkm1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(7),
      Q => TCapt_to_mclkm1(7)
    );
\TCapt_to_mclkm1_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(8),
      Q => TCapt_to_mclkm1(8)
    );
\TCapt_to_mclkm1_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclk(9),
      Q => TCapt_to_mclkm1(9)
    );
\TCapt_to_mclkm2_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(0),
      Q => TCapt_to_mclkm2(0)
    );
\TCapt_to_mclkm2_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(10),
      Q => TCapt_to_mclkm2(10)
    );
\TCapt_to_mclkm2_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(11),
      Q => TCapt_to_mclkm2(11)
    );
\TCapt_to_mclkm2_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(12),
      Q => TCapt_to_mclkm2(12)
    );
\TCapt_to_mclkm2_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(13),
      Q => TCapt_to_mclkm2(13)
    );
\TCapt_to_mclkm2_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(14),
      Q => TCapt_to_mclkm2(14)
    );
\TCapt_to_mclkm2_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(15),
      Q => TCapt_to_mclkm2(15)
    );
\TCapt_to_mclkm2_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(16),
      Q => TCapt_to_mclkm2(16)
    );
\TCapt_to_mclkm2_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(17),
      Q => TCapt_to_mclkm2(17)
    );
\TCapt_to_mclkm2_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(18),
      Q => TCapt_to_mclkm2(18)
    );
\TCapt_to_mclkm2_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(19),
      Q => TCapt_to_mclkm2(19)
    );
\TCapt_to_mclkm2_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(1),
      Q => TCapt_to_mclkm2(1)
    );
\TCapt_to_mclkm2_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(20),
      Q => TCapt_to_mclkm2(20)
    );
\TCapt_to_mclkm2_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(21),
      Q => TCapt_to_mclkm2(21)
    );
\TCapt_to_mclkm2_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(22),
      Q => TCapt_to_mclkm2(22)
    );
\TCapt_to_mclkm2_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(23),
      Q => TCapt_to_mclkm2(23)
    );
\TCapt_to_mclkm2_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(24),
      Q => TCapt_to_mclkm2(24)
    );
\TCapt_to_mclkm2_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(25),
      Q => TCapt_to_mclkm2(25)
    );
\TCapt_to_mclkm2_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(26),
      Q => TCapt_to_mclkm2(26)
    );
\TCapt_to_mclkm2_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(27),
      Q => TCapt_to_mclkm2(27)
    );
\TCapt_to_mclkm2_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(28),
      Q => TCapt_to_mclkm2(28)
    );
\TCapt_to_mclkm2_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(29),
      Q => TCapt_to_mclkm2(29)
    );
\TCapt_to_mclkm2_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(2),
      Q => TCapt_to_mclkm2(2)
    );
\TCapt_to_mclkm2_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(30),
      Q => TCapt_to_mclkm2(30)
    );
\TCapt_to_mclkm2_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(31),
      Q => TCapt_to_mclkm2(31)
    );
\TCapt_to_mclkm2_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(3),
      Q => TCapt_to_mclkm2(3)
    );
\TCapt_to_mclkm2_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(4),
      Q => TCapt_to_mclkm2(4)
    );
\TCapt_to_mclkm2_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(5),
      Q => TCapt_to_mclkm2(5)
    );
\TCapt_to_mclkm2_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(6),
      Q => TCapt_to_mclkm2(6)
    );
\TCapt_to_mclkm2_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(7),
      Q => TCapt_to_mclkm2(7)
    );
\TCapt_to_mclkm2_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(8),
      Q => TCapt_to_mclkm2(8)
    );
\TCapt_to_mclkm2_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => TCapt_to_mclkm1(9),
      Q => TCapt_to_mclkm2(9)
    );
\aSeqbufB[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[0]\,
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      O => \aSeqbufB[0]_i_1__0_n_0\
    );
\aSeqbufB[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6660"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[1]\,
      I1 => \aSeqbufB_reg_n_0_[0]\,
      I2 => stateSeqbufB_reg(1),
      I3 => stateSeqbufB_reg(0),
      O => \aSeqbufB[1]_i_1__0_n_0\
    );
\aSeqbufB[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78787800"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[0]\,
      I1 => \aSeqbufB_reg_n_0_[1]\,
      I2 => \aSeqbufB_reg_n_0_[2]\,
      I3 => stateSeqbufB_reg(1),
      I4 => stateSeqbufB_reg(0),
      O => \aSeqbufB[2]_i_1__0_n_0\
    );
\aSeqbufB[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[2]\,
      I1 => \aSeqbufB_reg_n_0_[1]\,
      I2 => \aSeqbufB_reg_n_0_[0]\,
      I3 => \aSeqbufB_reg_n_0_[3]\,
      I4 => \aSeqbufB[8]_i_3__0_n_0\,
      O => \aSeqbufB[3]_i_1__0_n_0\
    );
\aSeqbufB[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => \aSeqbufB[8]_i_3__0_n_0\,
      I1 => \aSeqbufB_reg_n_0_[3]\,
      I2 => \aSeqbufB_reg_n_0_[0]\,
      I3 => \aSeqbufB_reg_n_0_[1]\,
      I4 => \aSeqbufB_reg_n_0_[2]\,
      I5 => \aSeqbufB_reg_n_0_[4]\,
      O => \aSeqbufB[4]_i_1__0_n_0\
    );
\aSeqbufB[5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0EE0"
    )
        port map (
      I0 => stateSeqbufB_reg(1),
      I1 => stateSeqbufB_reg(0),
      I2 => \aSeqbufB[5]_i_2__0_n_0\,
      I3 => \aSeqbufB_reg_n_0_[5]\,
      O => \aSeqbufB[5]_i_1__0_n_0\
    );
\aSeqbufB[5]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[4]\,
      I1 => \aSeqbufB_reg_n_0_[2]\,
      I2 => \aSeqbufB_reg_n_0_[1]\,
      I3 => \aSeqbufB_reg_n_0_[0]\,
      I4 => \aSeqbufB_reg_n_0_[3]\,
      O => \aSeqbufB[5]_i_2__0_n_0\
    );
\aSeqbufB[6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0EE0"
    )
        port map (
      I0 => stateSeqbufB_reg(1),
      I1 => stateSeqbufB_reg(0),
      I2 => \aSeqbufB[8]_i_4__0_n_0\,
      I3 => \aSeqbufB_reg_n_0_[6]\,
      O => \aSeqbufB[6]_i_1__0_n_0\
    );
\aSeqbufB[7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78787800"
    )
        port map (
      I0 => \aSeqbufB[8]_i_4__0_n_0\,
      I1 => \aSeqbufB_reg_n_0_[6]\,
      I2 => \aSeqbufB_reg_n_0_[7]\,
      I3 => stateSeqbufB_reg(1),
      I4 => stateSeqbufB_reg(0),
      O => \aSeqbufB[7]_i_1__0_n_0\
    );
\aSeqbufB[8]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4101"
    )
        port map (
      I0 => stateSeqbufB_reg(2),
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      I3 => \stateSeqbufB[1]_i_2__0_n_0\,
      O => \aSeqbufB[8]_i_1__0_n_0\
    );
\aSeqbufB[8]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15554000"
    )
        port map (
      I0 => \aSeqbufB[8]_i_3__0_n_0\,
      I1 => \aSeqbufB_reg_n_0_[7]\,
      I2 => \aSeqbufB_reg_n_0_[6]\,
      I3 => \aSeqbufB[8]_i_4__0_n_0\,
      I4 => \aSeqbufB_reg_n_0_[8]\,
      O => \aSeqbufB[8]_i_2__0_n_0\
    );
\aSeqbufB[8]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => stateSeqbufB_reg(0),
      I1 => stateSeqbufB_reg(2),
      I2 => stateSeqbufB_reg(1),
      O => \aSeqbufB[8]_i_3__0_n_0\
    );
\aSeqbufB[8]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[3]\,
      I1 => \aSeqbufB_reg_n_0_[0]\,
      I2 => \aSeqbufB_reg_n_0_[1]\,
      I3 => \aSeqbufB_reg_n_0_[2]\,
      I4 => \aSeqbufB_reg_n_0_[4]\,
      I5 => \aSeqbufB_reg_n_0_[5]\,
      O => \aSeqbufB[8]_i_4__0_n_0\
    );
\aSeqbufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \aSeqbufB[0]_i_1__0_n_0\,
      Q => \aSeqbufB_reg_n_0_[0]\
    );
\aSeqbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \aSeqbufB[1]_i_1__0_n_0\,
      Q => \aSeqbufB_reg_n_0_[1]\
    );
\aSeqbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \aSeqbufB[2]_i_1__0_n_0\,
      Q => \aSeqbufB_reg_n_0_[2]\
    );
\aSeqbufB_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \aSeqbufB[3]_i_1__0_n_0\,
      Q => \aSeqbufB_reg_n_0_[3]\
    );
\aSeqbufB_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \aSeqbufB[4]_i_1__0_n_0\,
      Q => \aSeqbufB_reg_n_0_[4]\
    );
\aSeqbufB_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \aSeqbufB[5]_i_1__0_n_0\,
      Q => \aSeqbufB_reg_n_0_[5]\
    );
\aSeqbufB_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \aSeqbufB[6]_i_1__0_n_0\,
      Q => \aSeqbufB_reg_n_0_[6]\
    );
\aSeqbufB_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \aSeqbufB[7]_i_1__0_n_0\,
      Q => \aSeqbufB_reg_n_0_[7]\
    );
\aSeqbufB_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \aSeqbufB[8]_i_2__0_n_0\,
      Q => \aSeqbufB_reg_n_0_[8]\
    );
\aSeqbuf[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555544454454"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[0]\,
      I1 => ackSeqbufBToSeqClear,
      I2 => rdySeq,
      I3 => dneSeq,
      I4 => TCapt,
      I5 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \aSeqbuf[0]_i_1__0_n_0\
    );
\aSeqbuf[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[0]\,
      I1 => \aSeqbuf_reg_n_0_[1]\,
      I2 => \aSeqbuf[3]_i_2__0_n_0\,
      O => \aSeqbuf[1]_i_1__0_n_0\
    );
\aSeqbuf[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[1]\,
      I1 => \aSeqbuf_reg_n_0_[0]\,
      I2 => \aSeqbuf_reg_n_0_[2]\,
      I3 => \aSeqbuf[3]_i_2__0_n_0\,
      O => \aSeqbuf[2]_i_1__0_n_0\
    );
\aSeqbuf[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[2]\,
      I1 => \aSeqbuf_reg_n_0_[0]\,
      I2 => \aSeqbuf_reg_n_0_[1]\,
      I3 => \aSeqbuf_reg_n_0_[3]\,
      I4 => \aSeqbuf[3]_i_2__0_n_0\,
      O => \aSeqbuf[3]_i_1__0_n_0\
    );
\aSeqbuf[3]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00005451"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => TCapt,
      I2 => dneSeq,
      I3 => rdySeq,
      I4 => ackSeqbufBToSeqClear,
      O => \aSeqbuf[3]_i_2__0_n_0\
    );
\aSeqbuf[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \aSeqbuf[9]_i_5__0_n_0\,
      I1 => \aSeqbuf_reg_n_0_[3]\,
      I2 => \aSeqbuf_reg_n_0_[1]\,
      I3 => \aSeqbuf_reg_n_0_[0]\,
      I4 => \aSeqbuf_reg_n_0_[2]\,
      I5 => \aSeqbuf_reg_n_0_[4]\,
      O => \aSeqbuf[4]_i_1__0_n_0\
    );
\aSeqbuf[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \aSeqbuf[9]_i_5__0_n_0\,
      I1 => \aSeqbuf[5]_i_2__0_n_0\,
      I2 => \aSeqbuf_reg_n_0_[5]\,
      O => \aSeqbuf[5]_i_1__0_n_0\
    );
\aSeqbuf[5]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[4]\,
      I1 => \aSeqbuf_reg_n_0_[2]\,
      I2 => \aSeqbuf_reg_n_0_[0]\,
      I3 => \aSeqbuf_reg_n_0_[1]\,
      I4 => \aSeqbuf_reg_n_0_[3]\,
      O => \aSeqbuf[5]_i_2__0_n_0\
    );
\aSeqbuf[6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \aSeqbuf[9]_i_5__0_n_0\,
      I1 => \aSeqbuf[9]_i_6__0_n_0\,
      I2 => \aSeqbuf_reg_n_0_[6]\,
      O => \aSeqbuf[6]_i_1__0_n_0\
    );
\aSeqbuf[7]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \aSeqbuf[9]_i_5__0_n_0\,
      I1 => \aSeqbuf[9]_i_6__0_n_0\,
      I2 => \aSeqbuf_reg_n_0_[6]\,
      I3 => \aSeqbuf_reg_n_0_[7]\,
      O => \aSeqbuf[7]_i_1__0_n_0\
    );
\aSeqbuf[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF6AAA0000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[8]\,
      I1 => \aSeqbuf[9]_i_6__0_n_0\,
      I2 => \aSeqbuf_reg_n_0_[6]\,
      I3 => \aSeqbuf_reg_n_0_[7]\,
      I4 => \aSeqbuf[8]_i_2__0_n_0\,
      I5 => \aSeqbuf[8]_i_3__0_n_0\,
      O => \aSeqbuf[8]_i_1__0_n_0\
    );
\aSeqbuf[8]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DF000000FFFFFFFF"
    )
        port map (
      I0 => \aSeqbuf[9]_i_6__0_n_0\,
      I1 => \aSeqbuf[8]_i_4__0_n_0\,
      I2 => \aSeqbuf_reg_n_0_[4]\,
      I3 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I4 => TCapt,
      I5 => \aSeqbuf[8]_i_5_n_0\,
      O => \aSeqbuf[8]_i_2__0_n_0\
    );
\aSeqbuf[8]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \dwrSeqbuf[8]_i_3_n_0\,
      I1 => \aSeqbuf_reg_n_0_[8]\,
      I2 => \aSeqbuf_reg_n_0_[7]\,
      I3 => \aSeqbuf_reg_n_0_[9]\,
      I4 => \aSeqbuf_reg_n_0_[6]\,
      O => \aSeqbuf[8]_i_3__0_n_0\
    );
\aSeqbuf[8]_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[8]\,
      I1 => \aSeqbuf_reg_n_0_[7]\,
      I2 => \aSeqbuf_reg_n_0_[9]\,
      O => \aSeqbuf[8]_i_4__0_n_0\
    );
\aSeqbuf[8]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00540055"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => dneSeq,
      I2 => TCapt,
      I3 => ackSeqbufBToSeqClear,
      I4 => rdySeq,
      O => \aSeqbuf[8]_i_5_n_0\
    );
\aSeqbuf[9]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0020"
    )
        port map (
      I0 => TCapt,
      I1 => \aSeqbuf[9]_i_3__0_n_0\,
      I2 => \i_reg_n_0_[0]\,
      I3 => \first__0\,
      I4 => \aSeqbuf[9]_i_4__0_n_0\,
      O => \aSeqbuf[9]_i_1__0_n_0\
    );
\aSeqbuf[9]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \aSeqbuf[9]_i_5__0_n_0\,
      I1 => \aSeqbuf_reg_n_0_[9]\,
      I2 => \aSeqbuf_reg_n_0_[8]\,
      I3 => \aSeqbuf_reg_n_0_[7]\,
      I4 => \aSeqbuf_reg_n_0_[6]\,
      I5 => \aSeqbuf[9]_i_6__0_n_0\,
      O => \aSeqbuf[9]_i_2__0_n_0\
    );
\aSeqbuf[9]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_3_n_0\,
      I1 => \burstCnt[15]_i_4__0_n_0\,
      O => \aSeqbuf[9]_i_3__0_n_0\
    );
\aSeqbuf[9]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE0FFFFFFE0FFE0"
    )
        port map (
      I0 => reqOpToSeqClear_memclk,
      I1 => reqSeqbufBToSeqClear_memclk,
      I2 => dneSeq,
      I3 => first,
      I4 => \FSM_onehot_stateSeq[5]_i_8_n_0\,
      I5 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \aSeqbuf[9]_i_4__0_n_0\
    );
\aSeqbuf[9]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAEAAAEAAAEAAA"
    )
        port map (
      I0 => \aSeqbuf[8]_i_2__0_n_0\,
      I1 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I2 => TCapt,
      I3 => \aSeqbuf_reg_n_0_[8]\,
      I4 => \aSeqbuf_reg_n_0_[6]\,
      I5 => \aSeqbuf_reg_n_0_[7]\,
      O => \aSeqbuf[9]_i_5__0_n_0\
    );
\aSeqbuf[9]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[3]\,
      I1 => \aSeqbuf_reg_n_0_[1]\,
      I2 => \aSeqbuf_reg_n_0_[0]\,
      I3 => \aSeqbuf_reg_n_0_[2]\,
      I4 => \aSeqbuf_reg_n_0_[4]\,
      I5 => \aSeqbuf_reg_n_0_[5]\,
      O => \aSeqbuf[9]_i_6__0_n_0\
    );
\aSeqbuf_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aSeqbuf[9]_i_1__0_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[0]_i_1__0_n_0\,
      Q => \aSeqbuf_reg_n_0_[0]\
    );
\aSeqbuf_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aSeqbuf[9]_i_1__0_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[1]_i_1__0_n_0\,
      Q => \aSeqbuf_reg_n_0_[1]\
    );
\aSeqbuf_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aSeqbuf[9]_i_1__0_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[2]_i_1__0_n_0\,
      Q => \aSeqbuf_reg_n_0_[2]\
    );
\aSeqbuf_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aSeqbuf[9]_i_1__0_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[3]_i_1__0_n_0\,
      Q => \aSeqbuf_reg_n_0_[3]\
    );
\aSeqbuf_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aSeqbuf[9]_i_1__0_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[4]_i_1__0_n_0\,
      Q => \aSeqbuf_reg_n_0_[4]\
    );
\aSeqbuf_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aSeqbuf[9]_i_1__0_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[5]_i_1__0_n_0\,
      Q => \aSeqbuf_reg_n_0_[5]\
    );
\aSeqbuf_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aSeqbuf[9]_i_1__0_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[6]_i_1__0_n_0\,
      Q => \aSeqbuf_reg_n_0_[6]\
    );
\aSeqbuf_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aSeqbuf[9]_i_1__0_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[7]_i_1__0_n_0\,
      Q => \aSeqbuf_reg_n_0_[7]\
    );
\aSeqbuf_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aSeqbuf[9]_i_1__0_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[8]_i_1__0_n_0\,
      Q => \aSeqbuf_reg_n_0_[8]\
    );
\aSeqbuf_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \aSeqbuf[9]_i_1__0_n_0\,
      CLR => AR(0),
      D => \aSeqbuf[9]_i_2__0_n_0\,
      Q => \aSeqbuf_reg_n_0_[9]\
    );
ackInvClearMask_sig_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D5C0"
    )
        port map (
      I0 => \ackInvSet_sig_i_2__0_n_0\,
      I1 => reqInvMemtrackClearMask,
      I2 => \^stateop_reg[2]_0\,
      I3 => \^ackinvmemtrackclearmask\,
      O => ackInvClearMask_sig_i_1_n_0
    );
ackInvClearMask_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ackInvClearMask_sig_i_1_n_0,
      Q => \^ackinvmemtrackclearmask\
    );
\ackInvSelect_sig_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F555B000"
    )
        port map (
      I0 => \ackInvSet_sig_i_2__0_n_0\,
      I1 => reqInvMemtrackClearMask,
      I2 => reqInvMemtrackSelect,
      I3 => \^stateop_reg[2]_0\,
      I4 => \^ackinvmemtrackselect\,
      O => \ackInvSelect_sig_i_1__0_n_0\
    );
ackInvSelect_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \ackInvSelect_sig_i_1__0_n_0\,
      Q => \^ackinvmemtrackselect\
    );
ackInvSetMask_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDDDD8888888C"
    )
        port map (
      I0 => \ackInvSet_sig_i_2__0_n_0\,
      I1 => ackInvSetMask_sig,
      I2 => reqInvMemtrackSelect,
      I3 => reqInvMemtrackSet,
      I4 => reqInvMemtrackClearMask,
      I5 => \^ackinvmemtracksetmask\,
      O => ackInvSetMask_sig_i_1_n_0
    );
ackInvSetMask_sig_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA8A"
    )
        port map (
      I0 => reqInvMemtrackSetMask,
      I1 => stateOp(2),
      I2 => stateOp(0),
      I3 => stateOp(1),
      O => ackInvSetMask_sig
    );
ackInvSetMask_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ackInvSetMask_sig_i_1_n_0,
      Q => \^ackinvmemtracksetmask\
    );
\ackInvSet_sig_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF555555AB000000"
    )
        port map (
      I0 => \ackInvSet_sig_i_2__0_n_0\,
      I1 => reqInvMemtrackSelect,
      I2 => reqInvMemtrackClearMask,
      I3 => reqInvMemtrackSet,
      I4 => \^stateop_reg[2]_0\,
      I5 => \^ackinvmemtrackset\,
      O => \ackInvSet_sig_i_1__2_n_0\
    );
\ackInvSet_sig_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(0),
      I2 => stateOp(1),
      I3 => restart_reg_0,
      O => \ackInvSet_sig_i_2__0_n_0\
    );
ackInvSet_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \ackInvSet_sig_i_1__2_n_0\,
      Q => \^ackinvmemtrackset\
    );
\burstCapt[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(0),
      I1 => \burstCnt[15]_i_3__0_n_0\,
      O => burstCapt(0)
    );
\burstCapt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(1),
      I1 => \burstCnt[15]_i_3__0_n_0\,
      O => burstCapt(1)
    );
\burstCapt[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(2),
      I1 => \burstCnt[15]_i_3__0_n_0\,
      O => burstCapt(2)
    );
\burstCapt[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(3),
      I1 => \burstCnt[15]_i_3__0_n_0\,
      O => burstCapt(3)
    );
\burstCapt[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(4),
      I1 => \burstCnt[15]_i_3__0_n_0\,
      O => burstCapt(4)
    );
\burstCapt[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(5),
      I1 => \burstCnt[15]_i_3__0_n_0\,
      O => burstCapt(5)
    );
\burstCapt[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(6),
      I1 => \burstCnt[15]_i_3__0_n_0\,
      O => burstCapt(6)
    );
\burstCapt[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(7),
      I1 => \burstCnt[15]_i_3__0_n_0\,
      O => burstCapt(7)
    );
\burstCapt[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => capt(8),
      I1 => \burstCnt[15]_i_3__0_n_0\,
      O => burstCapt(8)
    );
\burstCapt_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCapt(0),
      Q => \burstCapt_reg_n_0_[0]\
    );
\burstCapt_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCapt(1),
      Q => \burstCapt_reg_n_0_[1]\
    );
\burstCapt_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCapt(2),
      Q => \burstCapt_reg_n_0_[2]\
    );
\burstCapt_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCapt(3),
      Q => \burstCapt_reg_n_0_[3]\
    );
\burstCapt_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCapt(4),
      Q => \burstCapt_reg_n_0_[4]\
    );
\burstCapt_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCapt(5),
      Q => \burstCapt_reg_n_0_[5]\
    );
\burstCapt_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCapt(6),
      Q => \burstCapt_reg_n_0_[6]\
    );
\burstCapt_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCapt(7),
      Q => \burstCapt_reg_n_0_[7]\
    );
\burstCapt_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCapt(8),
      Q => \burstCapt_reg_n_0_[8]\
    );
\burstCnt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \burstCnt[15]_i_3__0_n_0\,
      I1 => \burstCnt[15]_i_4__0_n_0\,
      I2 => \burstCnt_reg_n_0_[0]\,
      O => burstCnt(0)
    );
\burstCnt[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \burstCnt[15]_i_3__0_n_0\,
      I1 => \burstCnt[10]_i_2__0_n_0\,
      O => burstCnt(10)
    );
\burstCnt[10]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF20FFDF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[9]\,
      I1 => \burstCnt[14]_i_3__0_n_0\,
      I2 => \burstCnt_reg_n_0_[8]\,
      I3 => \burstCnt[15]_i_4__0_n_0\,
      I4 => \burstCnt_reg_n_0_[10]\,
      O => \burstCnt[10]_i_2__0_n_0\
    );
\burstCnt[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \burstCnt[15]_i_3__0_n_0\,
      I1 => \burstCnt[11]_i_2__0_n_0\,
      O => burstCnt(11)
    );
\burstCnt[11]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF20FF00FFDFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[9]\,
      I1 => \burstCnt[14]_i_3__0_n_0\,
      I2 => \burstCnt_reg_n_0_[8]\,
      I3 => \burstCnt[15]_i_4__0_n_0\,
      I4 => \burstCnt_reg_n_0_[10]\,
      I5 => \burstCnt_reg_n_0_[11]\,
      O => \burstCnt[11]_i_2__0_n_0\
    );
\burstCnt[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \burstCnt[15]_i_3__0_n_0\,
      I1 => \burstCnt[12]_i_2__0_n_0\,
      O => burstCnt(12)
    );
\burstCnt[12]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FFFFF7FF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[11]\,
      I1 => \burstCnt_reg_n_0_[9]\,
      I2 => \burstCnt[15]_i_11__0_n_0\,
      I3 => \burstCnt_reg_n_0_[10]\,
      I4 => \burstCnt[15]_i_4__0_n_0\,
      I5 => \burstCnt_reg_n_0_[12]\,
      O => \burstCnt[12]_i_2__0_n_0\
    );
\burstCnt[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008288"
    )
        port map (
      I0 => \burstCnt[15]_i_3__0_n_0\,
      I1 => \burstCnt_reg_n_0_[13]\,
      I2 => \burstCnt[14]_i_2__0_n_0\,
      I3 => \burstCnt_reg_n_0_[12]\,
      I4 => \burstCnt[15]_i_4__0_n_0\,
      O => burstCnt(13)
    );
\burstCnt[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808020808080808"
    )
        port map (
      I0 => \burstCnt[15]_i_3__0_n_0\,
      I1 => \burstCnt_reg_n_0_[14]\,
      I2 => \burstCnt[15]_i_4__0_n_0\,
      I3 => \burstCnt_reg_n_0_[13]\,
      I4 => \burstCnt[14]_i_2__0_n_0\,
      I5 => \burstCnt_reg_n_0_[12]\,
      O => burstCnt(14)
    );
\burstCnt[14]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFFFFFFFFFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[10]\,
      I1 => \burstCnt[15]_i_4__0_n_0\,
      I2 => \burstCnt_reg_n_0_[8]\,
      I3 => \burstCnt[14]_i_3__0_n_0\,
      I4 => \burstCnt_reg_n_0_[9]\,
      I5 => \burstCnt_reg_n_0_[11]\,
      O => \burstCnt[14]_i_2__0_n_0\
    );
\burstCnt[14]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBFFFFFFFFFFF"
    )
        port map (
      I0 => \burstCnt[5]_i_2__0_n_0\,
      I1 => \burstCnt_reg_n_0_[4]\,
      I2 => \burstCnt_reg_n_0_[5]\,
      I3 => \burstCnt_reg_n_0_[6]\,
      I4 => \burstCnt[15]_i_4__0_n_0\,
      I5 => \burstCnt_reg_n_0_[7]\,
      O => \burstCnt[14]_i_3__0_n_0\
    );
\burstCnt[15]_i_10__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \burstCapt_reg_n_0_[2]\,
      I1 => capt(2),
      I2 => capt(0),
      I3 => \burstCapt_reg_n_0_[0]\,
      I4 => capt(1),
      I5 => \burstCapt_reg_n_0_[1]\,
      O => \burstCnt[15]_i_10__0_n_0\
    );
\burstCnt[15]_i_11__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[7]\,
      I1 => \burstCnt[9]_i_3_n_0\,
      I2 => \burstCnt_reg_n_0_[6]\,
      I3 => \burstCnt_reg_n_0_[8]\,
      I4 => \burstCnt[15]_i_4__0_n_0\,
      O => \burstCnt[15]_i_11__0_n_0\
    );
\burstCnt[15]_i_12__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[14]\,
      I1 => \burstCnt_reg_n_0_[15]\,
      I2 => \burstCnt_reg_n_0_[13]\,
      I3 => \burstCnt_reg_n_0_[12]\,
      O => \burstCnt[15]_i_12__0_n_0\
    );
\burstCnt[15]_i_13__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[0]\,
      I1 => \burstCnt_reg_n_0_[1]\,
      I2 => \burstCnt_reg_n_0_[2]\,
      I3 => \burstCnt_reg_n_0_[3]\,
      O => \burstCnt[15]_i_13__0_n_0\
    );
\burstCnt[15]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000010001"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => dneSeq,
      I2 => rdySeq,
      I3 => ackSeqbufBToSeqClear,
      I4 => \i_reg_n_0_[0]\,
      I5 => TCapt,
      O => \burstCnt[15]_i_1__0_n_0\
    );
\burstCnt[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A08080808080808"
    )
        port map (
      I0 => \burstCnt[15]_i_3__0_n_0\,
      I1 => \burstCnt_reg_n_0_[15]\,
      I2 => \burstCnt[15]_i_4__0_n_0\,
      I3 => \burstCnt[15]_i_5__0_n_0\,
      I4 => \burstCnt_reg_n_0_[13]\,
      I5 => \burstCnt_reg_n_0_[14]\,
      O => burstCnt(15)
    );
\burstCnt[15]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_3_n_0\,
      I1 => first,
      O => \burstCnt[15]_i_3__0_n_0\
    );
\burstCnt[15]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFF4"
    )
        port map (
      I0 => \burstCnt[15]_i_6_n_0\,
      I1 => \burstCnt[15]_i_7__0_n_0\,
      I2 => \burstCnt[15]_i_8__0_n_0\,
      I3 => \burstCnt[15]_i_9__0_n_0\,
      I4 => \burstCnt[15]_i_10__0_n_0\,
      O => \burstCnt[15]_i_4__0_n_0\
    );
\burstCnt[15]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000008000000000"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[12]\,
      I1 => \burstCnt_reg_n_0_[11]\,
      I2 => \burstCnt_reg_n_0_[9]\,
      I3 => \burstCnt[15]_i_11__0_n_0\,
      I4 => \burstCnt[15]_i_4__0_n_0\,
      I5 => \burstCnt_reg_n_0_[10]\,
      O => \burstCnt[15]_i_5__0_n_0\
    );
\burstCnt[15]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[10]\,
      I1 => \burstCnt_reg_n_0_[11]\,
      I2 => \burstCnt_reg_n_0_[8]\,
      I3 => \burstCnt_reg_n_0_[9]\,
      I4 => \burstCnt[15]_i_12__0_n_0\,
      O => \burstCnt[15]_i_6_n_0\
    );
\burstCnt[15]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \burstCnt[15]_i_13__0_n_0\,
      I1 => \burstCnt_reg_n_0_[6]\,
      I2 => \burstCnt_reg_n_0_[7]\,
      I3 => \burstCnt_reg_n_0_[4]\,
      I4 => \burstCnt_reg_n_0_[5]\,
      O => \burstCnt[15]_i_7__0_n_0\
    );
\burstCnt[15]_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \burstCapt_reg_n_0_[6]\,
      I1 => capt(6),
      I2 => capt(8),
      I3 => \burstCapt_reg_n_0_[8]\,
      I4 => capt(7),
      I5 => \burstCapt_reg_n_0_[7]\,
      O => \burstCnt[15]_i_8__0_n_0\
    );
\burstCnt[15]_i_9__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \burstCapt_reg_n_0_[3]\,
      I1 => capt(3),
      I2 => capt(5),
      I3 => \burstCapt_reg_n_0_[5]\,
      I4 => capt(4),
      I5 => \burstCapt_reg_n_0_[4]\,
      O => \burstCnt[15]_i_9__0_n_0\
    );
\burstCnt[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1400"
    )
        port map (
      I0 => first,
      I1 => \burstCnt_reg_n_0_[0]\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \aSeqbuf[9]_i_3__0_n_0\,
      O => \burstCnt[1]_i_1__0_n_0\
    );
\burstCnt[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04404040"
    )
        port map (
      I0 => first,
      I1 => \aSeqbuf[9]_i_3__0_n_0\,
      I2 => \burstCnt_reg_n_0_[2]\,
      I3 => \burstCnt_reg_n_0_[1]\,
      I4 => \burstCnt_reg_n_0_[0]\,
      O => \burstCnt[2]_i_1__0_n_0\
    );
\burstCnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0222222220000000"
    )
        port map (
      I0 => \burstCnt[15]_i_3__0_n_0\,
      I1 => \burstCnt[15]_i_4__0_n_0\,
      I2 => \burstCnt_reg_n_0_[2]\,
      I3 => \burstCnt_reg_n_0_[1]\,
      I4 => \burstCnt_reg_n_0_[0]\,
      I5 => \burstCnt_reg_n_0_[3]\,
      O => burstCnt(3)
    );
\burstCnt[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[4]_i_2__0_n_0\,
      O => \burstCnt[4]_i_1__0_n_0\
    );
\burstCnt[4]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7DD"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_3_n_0\,
      I1 => \burstCnt[5]_i_2__0_n_0\,
      I2 => \burstCnt[15]_i_4__0_n_0\,
      I3 => \burstCnt_reg_n_0_[4]\,
      O => \burstCnt[4]_i_2__0_n_0\
    );
\burstCnt[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"25220000"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[5]\,
      I1 => \burstCnt[15]_i_4__0_n_0\,
      I2 => \burstCnt[5]_i_2__0_n_0\,
      I3 => \burstCnt_reg_n_0_[4]\,
      I4 => \burstCnt[15]_i_3__0_n_0\,
      O => \burstCnt[5]_i_1__0_n_0\
    );
\burstCnt[5]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFFFFFF"
    )
        port map (
      I0 => \burstCnt[15]_i_4__0_n_0\,
      I1 => \burstCnt_reg_n_0_[3]\,
      I2 => \burstCnt_reg_n_0_[2]\,
      I3 => \burstCnt_reg_n_0_[1]\,
      I4 => \burstCnt_reg_n_0_[0]\,
      O => \burstCnt[5]_i_2__0_n_0\
    );
\burstCnt[6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[6]_i_2__0_n_0\,
      O => \burstCnt[6]_i_1__0_n_0\
    );
\burstCnt[6]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFBF40BFFFFFFFFF"
    )
        port map (
      I0 => \burstCnt[5]_i_2__0_n_0\,
      I1 => \burstCnt_reg_n_0_[4]\,
      I2 => \burstCnt_reg_n_0_[5]\,
      I3 => \burstCnt_reg_n_0_[6]\,
      I4 => \burstCnt[15]_i_4__0_n_0\,
      I5 => \dwrSeqbuf[31]_i_3_n_0\,
      O => \burstCnt[6]_i_2__0_n_0\
    );
\burstCnt[7]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \burstCnt[7]_i_2__0_n_0\,
      I1 => \burstCnt[15]_i_3__0_n_0\,
      O => \burstCnt[7]_i_1__0_n_0\
    );
\burstCnt[7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2122222222222222"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[7]\,
      I1 => \burstCnt[15]_i_4__0_n_0\,
      I2 => \burstCnt[5]_i_2__0_n_0\,
      I3 => \burstCnt_reg_n_0_[4]\,
      I4 => \burstCnt_reg_n_0_[5]\,
      I5 => \burstCnt_reg_n_0_[6]\,
      O => \burstCnt[7]_i_2__0_n_0\
    );
\burstCnt[8]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[8]_i_2__0_n_0\,
      O => \burstCnt[8]_i_1__0_n_0\
    );
\burstCnt[8]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF20DFFFFFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[7]\,
      I1 => \burstCnt[9]_i_3_n_0\,
      I2 => \burstCnt_reg_n_0_[6]\,
      I3 => \burstCnt_reg_n_0_[8]\,
      I4 => \burstCnt[15]_i_4__0_n_0\,
      I5 => \dwrSeqbuf[31]_i_3_n_0\,
      O => \burstCnt[8]_i_2__0_n_0\
    );
\burstCnt[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \burstCnt[15]_i_3__0_n_0\,
      I1 => \burstCnt[9]_i_2__0_n_0\,
      O => burstCnt(9)
    );
\burstCnt[9]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF2000FFFFDFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[7]\,
      I1 => \burstCnt[9]_i_3_n_0\,
      I2 => \burstCnt_reg_n_0_[6]\,
      I3 => \burstCnt_reg_n_0_[8]\,
      I4 => \burstCnt[15]_i_4__0_n_0\,
      I5 => \burstCnt_reg_n_0_[9]\,
      O => \burstCnt[9]_i_2__0_n_0\
    );
\burstCnt[9]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F7"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[5]\,
      I1 => \burstCnt_reg_n_0_[4]\,
      I2 => \burstCnt[5]_i_2__0_n_0\,
      O => \burstCnt[9]_i_3_n_0\
    );
\burstCnt_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCnt(0),
      Q => \burstCnt_reg_n_0_[0]\
    );
\burstCnt_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCnt(10),
      Q => \burstCnt_reg_n_0_[10]\
    );
\burstCnt_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCnt(11),
      Q => \burstCnt_reg_n_0_[11]\
    );
\burstCnt_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCnt(12),
      Q => \burstCnt_reg_n_0_[12]\
    );
\burstCnt_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCnt(13),
      Q => \burstCnt_reg_n_0_[13]\
    );
\burstCnt_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCnt(14),
      Q => \burstCnt_reg_n_0_[14]\
    );
\burstCnt_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCnt(15),
      Q => \burstCnt_reg_n_0_[15]\
    );
\burstCnt_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => \burstCnt[1]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[1]\
    );
\burstCnt_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => \burstCnt[2]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[2]\
    );
\burstCnt_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCnt(3),
      Q => \burstCnt_reg_n_0_[3]\
    );
\burstCnt_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => \burstCnt[4]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[4]\
    );
\burstCnt_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => \burstCnt[5]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[5]\
    );
\burstCnt_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => \burstCnt[6]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[6]\
    );
\burstCnt_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => \burstCnt[7]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[7]\
    );
\burstCnt_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => \burstCnt[8]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[8]\
    );
\burstCnt_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      CLR => AR(0),
      D => burstCnt(9),
      Q => \burstCnt_reg_n_0_[9]\
    );
\capt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => \capt_reg[0]_0\(0),
      I1 => \capt_reg[0]_0\(3),
      I2 => \capt_reg[0]_0\(1),
      I3 => \capt_reg[0]_0\(2),
      I4 => \^mask_reg[0]_0\,
      O => \capt[0]_i_1_n_0\
    );
\capt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \capt_reg[1]_0\(1),
      I1 => \capt_reg[1]_0\(0),
      I2 => \capt_reg[1]_1\(0),
      I3 => \^mask_reg[1]_0\,
      O => \capt[1]_i_1_n_0\
    );
\capt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000100"
    )
        port map (
      I0 => \capt_reg[0]_0\(0),
      I1 => \capt_reg[0]_0\(3),
      I2 => \capt_reg[0]_0\(1),
      I3 => \capt_reg[0]_0\(2),
      I4 => \^mask_reg[2]_0\,
      O => \capt[2]_i_1_n_0\
    );
\capt[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \capt_reg[3]_0\,
      I1 => \capt_reg[3]_1\(0),
      I2 => \^mask_reg[3]_0\,
      O => \capt[3]_i_1_n_0\
    );
\capt[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => ddrAXI_rvalid,
      I1 => \^mask_reg[4]_0\,
      O => \capt[4]_i_1_n_0\
    );
\capt[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => ddrAXI_wready,
      I1 => \^mask_reg[6]_0\,
      O => \capt[6]_i_1_n_0\
    );
\capt[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => ddrAXI_bvalid,
      I1 => \^mask_reg[7]_0\,
      O => \capt[7]_i_1_n_0\
    );
\capt[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => \capt_reg[3]_0\,
      I1 => \capt_reg[8]_0\(2),
      I2 => \capt_reg[8]_0\(1),
      I3 => \capt_reg[8]_0\(0),
      I4 => \mask_reg_n_0_[8]\,
      O => \capt[8]_i_1_n_0\
    );
\capt_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \capt[0]_i_1_n_0\,
      Q => capt(0)
    );
\capt_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \capt[1]_i_1_n_0\,
      Q => capt(1)
    );
\capt_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \capt[2]_i_1_n_0\,
      Q => capt(2)
    );
\capt_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \capt[3]_i_1_n_0\,
      Q => capt(3)
    );
\capt_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \capt[4]_i_1_n_0\,
      Q => capt(4)
    );
\capt_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \capt_reg[5]_0\(0),
      Q => capt(5)
    );
\capt_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \capt[6]_i_1_n_0\,
      Q => capt(6)
    );
\capt_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \capt[7]_i_1_n_0\,
      Q => capt(7)
    );
\capt_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \capt[8]_i_1_n_0\,
      Q => capt(8)
    );
\dneSeq_i[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"90FF"
    )
        port map (
      I0 => dneSeq,
      I1 => dneSeq_to_mclk,
      I2 => dneSeq_i(1),
      I3 => dneSeq_i(0),
      O => \dneSeq_i[0]_i_1_n_0\
    );
\dneSeq_i[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9FF0"
    )
        port map (
      I0 => dneSeq,
      I1 => dneSeq_to_mclk,
      I2 => dneSeq_i(1),
      I3 => dneSeq_i(0),
      O => \dneSeq_i[1]_i_1_n_0\
    );
\dneSeq_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \dneSeq_i[0]_i_1_n_0\,
      Q => dneSeq_i(0)
    );
\dneSeq_i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \dneSeq_i[1]_i_1_n_0\,
      Q => dneSeq_i(1)
    );
dneSeq_mclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => dneSeq_to_mclkm2,
      I1 => dneSeq_to_mclkm1,
      I2 => \^avllenseqbufmemtracktohostif\(0),
      O => dneSeq_mclk_i_1_n_0
    );
dneSeq_mclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => dneSeq_mclk_i_1_n_0,
      Q => \^avllenseqbufmemtracktohostif\(0)
    );
dneSeq_to_mclk_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CAAA"
    )
        port map (
      I0 => dneSeq_to_mclk,
      I1 => dneSeq,
      I2 => dneSeq_i(0),
      I3 => dneSeq_i(1),
      O => dneSeq_to_mclk_i_1_n_0
    );
dneSeq_to_mclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => dneSeq_to_mclk_i_1_n_0,
      Q => dneSeq_to_mclk
    );
dneSeq_to_mclkm1_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => dneSeq_to_mclk,
      Q => dneSeq_to_mclkm1
    );
dneSeq_to_mclkm2_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => dneSeq_to_mclkm1,
      Q => dneSeq_to_mclkm2
    );
\dwrSeqbuf[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FAEAAAEAFAEAFAEA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I1 => \dwrSeqbuf[0]_i_2__0_n_0\,
      I2 => \dwrSeqbuf[8]_i_3_n_0\,
      I3 => \dwrSeqbuf[31]_i_3_n_0\,
      I4 => \burstCnt[15]_i_4__0_n_0\,
      I5 => \burstCnt_reg_n_0_[0]\,
      O => \dwrSeqbuf[0]_i_1__0_n_0\
    );
\dwrSeqbuf[0]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[0]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(0),
      O => \dwrSeqbuf[0]_i_2__0_n_0\
    );
\dwrSeqbuf[10]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_2__0_n_0\,
      I1 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I2 => \burstCnt[10]_i_2__0_n_0\,
      O => \dwrSeqbuf[10]_i_1__0_n_0\
    );
\dwrSeqbuf[11]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_2__0_n_0\,
      I1 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I2 => \burstCnt[11]_i_2__0_n_0\,
      O => \dwrSeqbuf[11]_i_1__0_n_0\
    );
\dwrSeqbuf[12]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_2__0_n_0\,
      I1 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I2 => \burstCnt[12]_i_2__0_n_0\,
      O => \dwrSeqbuf[12]_i_1__0_n_0\
    );
\dwrSeqbuf[13]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8A888A88888A88"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_2__0_n_0\,
      I1 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I2 => \burstCnt[15]_i_4__0_n_0\,
      I3 => \burstCnt_reg_n_0_[12]\,
      I4 => \burstCnt[14]_i_2__0_n_0\,
      I5 => \burstCnt_reg_n_0_[13]\,
      O => \dwrSeqbuf[13]_i_1__0_n_0\
    );
\dwrSeqbuf[14]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8888AAAA888A888"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_2__0_n_0\,
      I1 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I2 => \burstCnt[15]_i_5__0_n_0\,
      I3 => \burstCnt_reg_n_0_[13]\,
      I4 => \burstCnt[15]_i_4__0_n_0\,
      I5 => \burstCnt_reg_n_0_[14]\,
      O => \dwrSeqbuf[14]_i_1__0_n_0\
    );
\dwrSeqbuf[15]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAA8888888"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_2__0_n_0\,
      I1 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I2 => \dwrSeqbuf[15]_i_2__0_n_0\,
      I3 => \burstCnt_reg_n_0_[13]\,
      I4 => \burstCnt[15]_i_5__0_n_0\,
      I5 => \dwrSeqbuf[15]_i_3__0_n_0\,
      O => \dwrSeqbuf[15]_i_1__0_n_0\
    );
\dwrSeqbuf[15]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[14]\,
      I1 => \burstCnt[15]_i_4__0_n_0\,
      O => \dwrSeqbuf[15]_i_2__0_n_0\
    );
\dwrSeqbuf[15]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[15]\,
      I1 => \burstCnt[15]_i_4__0_n_0\,
      O => \dwrSeqbuf[15]_i_3__0_n_0\
    );
\dwrSeqbuf[16]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => capt(0),
      I1 => \FSM_onehot_stateSeq[5]_i_4__0_n_0\,
      I2 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I3 => \FSM_onehot_stateSeq[5]_i_7__0_n_0\,
      O => \dwrSeqbuf[16]_i_1__0_n_0\
    );
\dwrSeqbuf[17]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FE0E0E0E"
    )
        port map (
      I0 => reqSeqbufBToSeqClear_memclk,
      I1 => reqOpToSeqClear_memclk,
      I2 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I3 => TCapt,
      I4 => capt(1),
      O => \dwrSeqbuf[17]_i_1__0_n_0\
    );
\dwrSeqbuf[18]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FE0E0E0E"
    )
        port map (
      I0 => reqSeqbufBToSeqClear_memclk,
      I1 => reqOpToSeqClear_memclk,
      I2 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I3 => TCapt,
      I4 => capt(2),
      O => \dwrSeqbuf[18]_i_1__0_n_0\
    );
\dwrSeqbuf[19]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => capt(3),
      I1 => \FSM_onehot_stateSeq[5]_i_4__0_n_0\,
      I2 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I3 => \FSM_onehot_stateSeq[5]_i_7__0_n_0\,
      O => \dwrSeqbuf[19]_i_1__0_n_0\
    );
\dwrSeqbuf[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I1 => \dwrSeqbuf[1]_i_2__0_n_0\,
      I2 => \dwrSeqbuf[31]_i_3_n_0\,
      I3 => \dwrSeqbuf[1]_i_3__0_n_0\,
      I4 => \dwrSeqbuf[8]_i_3_n_0\,
      O => \dwrSeqbuf[1]_i_1__0_n_0\
    );
\dwrSeqbuf[1]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D7"
    )
        port map (
      I0 => \aSeqbuf[9]_i_3__0_n_0\,
      I1 => \burstCnt_reg_n_0_[1]\,
      I2 => \burstCnt_reg_n_0_[0]\,
      O => \dwrSeqbuf[1]_i_2__0_n_0\
    );
\dwrSeqbuf[1]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(1),
      O => \dwrSeqbuf[1]_i_3__0_n_0\
    );
\dwrSeqbuf[20]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => capt(4),
      I1 => \FSM_onehot_stateSeq[5]_i_4__0_n_0\,
      I2 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I3 => \FSM_onehot_stateSeq[5]_i_7__0_n_0\,
      O => \dwrSeqbuf[20]_i_1__0_n_0\
    );
\dwrSeqbuf[21]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FE0E0E0E"
    )
        port map (
      I0 => reqSeqbufBToSeqClear_memclk,
      I1 => reqOpToSeqClear_memclk,
      I2 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I3 => TCapt,
      I4 => capt(5),
      O => \dwrSeqbuf[21]_i_1__0_n_0\
    );
\dwrSeqbuf[22]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FE0E0E0E"
    )
        port map (
      I0 => reqSeqbufBToSeqClear_memclk,
      I1 => reqOpToSeqClear_memclk,
      I2 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I3 => TCapt,
      I4 => capt(6),
      O => \dwrSeqbuf[22]_i_1__0_n_0\
    );
\dwrSeqbuf[23]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => capt(7),
      I1 => \FSM_onehot_stateSeq[5]_i_4__0_n_0\,
      I2 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I3 => \FSM_onehot_stateSeq[5]_i_7__0_n_0\,
      O => \dwrSeqbuf[23]_i_1__0_n_0\
    );
\dwrSeqbuf[24]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => capt(8),
      I1 => \FSM_onehot_stateSeq[5]_i_4__0_n_0\,
      I2 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I3 => \FSM_onehot_stateSeq[5]_i_7__0_n_0\,
      O => \dwrSeqbuf[24]_i_1__0_n_0\
    );
\dwrSeqbuf[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I1 => \dwrSeqbuf[2]_i_2__0_n_0\,
      I2 => \dwrSeqbuf[31]_i_3_n_0\,
      I3 => \dwrSeqbuf[2]_i_3__0_n_0\,
      I4 => \dwrSeqbuf[8]_i_3_n_0\,
      O => \dwrSeqbuf[2]_i_1__0_n_0\
    );
\dwrSeqbuf[2]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"87FF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[0]\,
      I1 => \burstCnt_reg_n_0_[1]\,
      I2 => \burstCnt_reg_n_0_[2]\,
      I3 => \aSeqbuf[9]_i_3__0_n_0\,
      O => \dwrSeqbuf[2]_i_2__0_n_0\
    );
\dwrSeqbuf[2]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[2]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(2),
      O => \dwrSeqbuf[2]_i_3__0_n_0\
    );
\dwrSeqbuf[30]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEEEEEEE0"
    )
        port map (
      I0 => reqOpToSeqClear_memclk,
      I1 => reqSeqbufBToSeqClear_memclk,
      I2 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I3 => dneSeq,
      I4 => rdySeq,
      I5 => ackSeqbufBToSeqClear,
      O => \dwrSeqbuf[30]_i_1__0_n_0\
    );
\dwrSeqbuf[31]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F4A4"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_4__0_n_0\,
      I1 => \FSM_onehot_stateSeq[5]_i_7__0_n_0\,
      I2 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I3 => \i_reg_n_0_[0]\,
      I4 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I5 => ackSeqbufBToSeqClear,
      O => \dwrSeqbuf[31]_i_1__0_n_0\
    );
\dwrSeqbuf[31]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF8FFF8FFF8F0080"
    )
        port map (
      I0 => TCapt,
      I1 => \dwrSeqbuf[31]_i_3_n_0\,
      I2 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I3 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I4 => reqSeqbufBToSeqClear_memclk,
      I5 => reqOpToSeqClear_memclk,
      O => \dwrSeqbuf[31]_i_2__0_n_0\
    );
\dwrSeqbuf[31]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20220222"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4__0_n_0\,
      I1 => \dwrSeqbuf[31]_i_5_n_0\,
      I2 => capt(0),
      I3 => \i_reg_n_0_[0]\,
      I4 => \quad_reg_n_0_[0]\,
      O => \dwrSeqbuf[31]_i_3_n_0\
    );
\dwrSeqbuf[31]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0041000000000041"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_6_n_0\,
      I1 => capt(8),
      I2 => \dwrSeqbuf[8]_i_2__0_n_0\,
      I3 => \dwrSeqbuf[31]_i_7_n_0\,
      I4 => capt(3),
      I5 => \dwrSeqbuf[3]_i_2__0_n_0\,
      O => \dwrSeqbuf[31]_i_4__0_n_0\
    );
\dwrSeqbuf[31]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6F00F600"
    )
        port map (
      I0 => \quad_reg_n_0_[1]\,
      I1 => capt(1),
      I2 => \quad_reg_n_0_[2]\,
      I3 => \i_reg_n_0_[0]\,
      I4 => capt(2),
      O => \dwrSeqbuf[31]_i_5_n_0\
    );
\dwrSeqbuf[31]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6F00F600"
    )
        port map (
      I0 => \quad_reg_n_0_[7]\,
      I1 => capt(7),
      I2 => \quad_reg_n_0_[6]\,
      I3 => \i_reg_n_0_[0]\,
      I4 => capt(6),
      O => \dwrSeqbuf[31]_i_6_n_0\
    );
\dwrSeqbuf[31]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6F00F600"
    )
        port map (
      I0 => \quad_reg_n_0_[4]\,
      I1 => capt(4),
      I2 => \quad_reg_n_0_[5]\,
      I3 => \i_reg_n_0_[0]\,
      I4 => capt(5),
      O => \dwrSeqbuf[31]_i_7_n_0\
    );
\dwrSeqbuf[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEAABAAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I1 => \dwrSeqbuf[31]_i_3_n_0\,
      I2 => \dwrSeqbuf[3]_i_2__0_n_0\,
      I3 => \dwrSeqbuf[8]_i_3_n_0\,
      I4 => \dwrSeqbuf[3]_i_3__0_n_0\,
      O => \dwrSeqbuf[3]_i_1__0_n_0\
    );
\dwrSeqbuf[3]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[3]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(3),
      O => \dwrSeqbuf[3]_i_2__0_n_0\
    );
\dwrSeqbuf[3]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[3]\,
      I1 => \burstCnt_reg_n_0_[0]\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \burstCnt_reg_n_0_[2]\,
      I4 => \burstCnt[15]_i_4__0_n_0\,
      O => \dwrSeqbuf[3]_i_3__0_n_0\
    );
\dwrSeqbuf[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I1 => \burstCnt[4]_i_2__0_n_0\,
      I2 => \dwrSeqbuf[31]_i_3_n_0\,
      I3 => \dwrSeqbuf[4]_i_2__0_n_0\,
      I4 => \dwrSeqbuf[8]_i_3_n_0\,
      O => \dwrSeqbuf[4]_i_1__0_n_0\
    );
\dwrSeqbuf[4]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[4]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(4),
      O => \dwrSeqbuf[4]_i_2__0_n_0\
    );
\dwrSeqbuf[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEAABAAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I1 => \dwrSeqbuf[31]_i_3_n_0\,
      I2 => \dwrSeqbuf[5]_i_2__0_n_0\,
      I3 => \dwrSeqbuf[8]_i_3_n_0\,
      I4 => \dwrSeqbuf[5]_i_3__0_n_0\,
      O => \dwrSeqbuf[5]_i_1__0_n_0\
    );
\dwrSeqbuf[5]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[5]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(5),
      O => \dwrSeqbuf[5]_i_2__0_n_0\
    );
\dwrSeqbuf[5]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0D22"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[4]\,
      I1 => \burstCnt[5]_i_2__0_n_0\,
      I2 => \burstCnt[15]_i_4__0_n_0\,
      I3 => \burstCnt_reg_n_0_[5]\,
      O => \dwrSeqbuf[5]_i_3__0_n_0\
    );
\dwrSeqbuf[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I1 => \burstCnt[6]_i_2__0_n_0\,
      I2 => \dwrSeqbuf[31]_i_3_n_0\,
      I3 => \dwrSeqbuf[6]_i_2__0_n_0\,
      I4 => \dwrSeqbuf[8]_i_3_n_0\,
      O => \dwrSeqbuf[6]_i_1__0_n_0\
    );
\dwrSeqbuf[6]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[6]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(6),
      O => \dwrSeqbuf[6]_i_2__0_n_0\
    );
\dwrSeqbuf[7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEAABAAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I1 => \dwrSeqbuf[31]_i_3_n_0\,
      I2 => \dwrSeqbuf[7]_i_2__0_n_0\,
      I3 => \dwrSeqbuf[8]_i_3_n_0\,
      I4 => \burstCnt[7]_i_2__0_n_0\,
      O => \dwrSeqbuf[7]_i_1__0_n_0\
    );
\dwrSeqbuf[7]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[7]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(7),
      O => \dwrSeqbuf[7]_i_2__0_n_0\
    );
\dwrSeqbuf[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I1 => \burstCnt[8]_i_2__0_n_0\,
      I2 => \dwrSeqbuf[31]_i_3_n_0\,
      I3 => \dwrSeqbuf[8]_i_2__0_n_0\,
      I4 => \dwrSeqbuf[8]_i_3_n_0\,
      O => \dwrSeqbuf[8]_i_1__0_n_0\
    );
\dwrSeqbuf[8]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \quad_reg_n_0_[8]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => capt(8),
      O => \dwrSeqbuf[8]_i_2__0_n_0\
    );
\dwrSeqbuf[8]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => dneSeq,
      I2 => rdySeq,
      I3 => ackSeqbufBToSeqClear,
      I4 => TCapt,
      O => \dwrSeqbuf[8]_i_3_n_0\
    );
\dwrSeqbuf[9]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_2__0_n_0\,
      I1 => \dwrSeqbuf[30]_i_1__0_n_0\,
      I2 => \burstCnt[9]_i_2__0_n_0\,
      O => \dwrSeqbuf[9]_i_1__0_n_0\
    );
\dwrSeqbuf_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[0]_i_1__0_n_0\,
      Q => dwrSeqbuf(0)
    );
\dwrSeqbuf_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[10]_i_1__0_n_0\,
      Q => dwrSeqbuf(10)
    );
\dwrSeqbuf_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[11]_i_1__0_n_0\,
      Q => dwrSeqbuf(11)
    );
\dwrSeqbuf_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[12]_i_1__0_n_0\,
      Q => dwrSeqbuf(12)
    );
\dwrSeqbuf_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[13]_i_1__0_n_0\,
      Q => dwrSeqbuf(13)
    );
\dwrSeqbuf_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[14]_i_1__0_n_0\,
      Q => dwrSeqbuf(14)
    );
\dwrSeqbuf_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[15]_i_1__0_n_0\,
      Q => dwrSeqbuf(15)
    );
\dwrSeqbuf_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[16]_i_1__0_n_0\,
      Q => dwrSeqbuf(16)
    );
\dwrSeqbuf_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[17]_i_1__0_n_0\,
      Q => dwrSeqbuf(17)
    );
\dwrSeqbuf_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[18]_i_1__0_n_0\,
      Q => dwrSeqbuf(18)
    );
\dwrSeqbuf_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[19]_i_1__0_n_0\,
      Q => dwrSeqbuf(19)
    );
\dwrSeqbuf_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[1]_i_1__0_n_0\,
      Q => dwrSeqbuf(1)
    );
\dwrSeqbuf_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[20]_i_1__0_n_0\,
      Q => dwrSeqbuf(20)
    );
\dwrSeqbuf_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[21]_i_1__0_n_0\,
      Q => dwrSeqbuf(21)
    );
\dwrSeqbuf_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[22]_i_1__0_n_0\,
      Q => dwrSeqbuf(22)
    );
\dwrSeqbuf_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[23]_i_1__0_n_0\,
      Q => dwrSeqbuf(23)
    );
\dwrSeqbuf_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[24]_i_1__0_n_0\,
      Q => dwrSeqbuf(24)
    );
\dwrSeqbuf_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[2]_i_1__0_n_0\,
      Q => dwrSeqbuf(2)
    );
\dwrSeqbuf_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[30]_i_1__0_n_0\,
      Q => dwrSeqbuf(30)
    );
\dwrSeqbuf_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[31]_i_2__0_n_0\,
      Q => dwrSeqbuf(31)
    );
\dwrSeqbuf_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[3]_i_1__0_n_0\,
      Q => dwrSeqbuf(3)
    );
\dwrSeqbuf_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[4]_i_1__0_n_0\,
      Q => dwrSeqbuf(4)
    );
\dwrSeqbuf_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[5]_i_1__0_n_0\,
      Q => dwrSeqbuf(5)
    );
\dwrSeqbuf_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[6]_i_1__0_n_0\,
      Q => dwrSeqbuf(6)
    );
\dwrSeqbuf_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[7]_i_1__0_n_0\,
      Q => dwrSeqbuf(7)
    );
\dwrSeqbuf_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[8]_i_1__0_n_0\,
      Q => dwrSeqbuf(8)
    );
\dwrSeqbuf_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \dwrSeqbuf[31]_i_1__0_n_0\,
      CLR => AR(0),
      D => \dwrSeqbuf[9]_i_1__0_n_0\,
      Q => dwrSeqbuf(9)
    );
\enSeqbuf_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => first,
      O => enSeqbuf
    );
enSeqbuf_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => enSeqbuf,
      Q => enSeqbuf_reg_n_0
    );
first_reg: unisim.vcomponents.FDPE
     port map (
      C => memclk,
      CE => \burstCnt[15]_i_1__0_n_0\,
      D => first,
      PRE => AR(0),
      Q => \first__0\
    );
\i[0]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0045AAAAAAAA"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \FSM_onehot_stateSeq[3]_i_2__0_n_0\,
      I2 => TCapt,
      I3 => first,
      I4 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I5 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      O => \i[0]_i_1__6_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \i[0]_i_1__6_n_0\,
      Q => \i_reg_n_0_[0]\
    );
\mask[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"75770500"
    )
        port map (
      I0 => reqInvMemtrackClearMask,
      I1 => \^stateop_reg[2]_0\,
      I2 => \mask[8]_i_2_n_0\,
      I3 => \mask_reg[8]_0\,
      I4 => \mask_reg_n_0_[8]\,
      O => \mask[8]_i_1_n_0\
    );
\mask[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF04FFFFFFFFFF"
    )
        port map (
      I0 => stateOp(1),
      I1 => stateOp(0),
      I2 => stateOp(2),
      I3 => reqInvMemtrackSetMask,
      I4 => \staTixVTrigger_reg[7]_0\(2),
      I5 => \staTixVTrigger_reg[7]_0\(3),
      O => \mask[8]_i_2_n_0\
    );
\mask_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \mask_reg[0]_1\,
      Q => \^mask_reg[0]_0\
    );
\mask_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \mask_reg[1]_1\,
      Q => \^mask_reg[1]_0\
    );
\mask_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \mask_reg[2]_1\,
      Q => \^mask_reg[2]_0\
    );
\mask_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \mask_reg[3]_1\,
      Q => \^mask_reg[3]_0\
    );
\mask_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \mask_reg[4]_1\,
      Q => \^mask_reg[4]_0\
    );
\mask_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \mask_reg[5]_1\,
      Q => \mask_reg[5]_0\
    );
\mask_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \mask_reg[6]_1\,
      Q => \^mask_reg[6]_0\
    );
\mask_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \mask_reg[7]_1\,
      Q => \^mask_reg[7]_0\
    );
\mask_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \mask[8]_i_1_n_0\,
      Q => \mask_reg_n_0_[8]\
    );
mySeqbuf: entity work.\design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64__xdcDup__3\
     port map (
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(26 downto 25) => dwrSeqbuf(31 downto 30),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(24 downto 0) => dwrSeqbuf(24 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8) => \aSeqbufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \aSeqbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \aSeqbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \aSeqbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \aSeqbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \aSeqbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \aSeqbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \aSeqbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \aSeqbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2 downto 0) => stateSeqbufB_reg(2 downto 0),
      Q(9) => \aSeqbuf_reg_n_0_[9]\,
      Q(8) => \aSeqbuf_reg_n_0_[8]\,
      Q(7) => \aSeqbuf_reg_n_0_[7]\,
      Q(6) => \aSeqbuf_reg_n_0_[6]\,
      Q(5) => \aSeqbuf_reg_n_0_[5]\,
      Q(4) => \aSeqbuf_reg_n_0_[4]\,
      Q(3) => \aSeqbuf_reg_n_0_[3]\,
      Q(2) => \aSeqbuf_reg_n_0_[2]\,
      Q(1) => \aSeqbuf_reg_n_0_[1]\,
      Q(0) => \aSeqbuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      doutb(63 downto 0) => doutb(63 downto 0),
      ena => enSeqbuf_reg_n_0,
      memclk => memclk
    );
\ptr0SeqbufTrackNotFixed_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF1FF00000100"
    )
        port map (
      I0 => first,
      I1 => \aSeqbuf[9]_i_3__0_n_0\,
      I2 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I3 => \FSM_onehot_stateSeq[5]_i_6__0_n_0\,
      I4 => ptr0SeqbufTrackNotFixed_i_2_n_0,
      I5 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => \ptr0SeqbufTrackNotFixed_i_1__0_n_0\
    );
ptr0SeqbufTrackNotFixed_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEE0EEEEE"
    )
        port map (
      I0 => TCapt,
      I1 => dneSeq,
      I2 => \FSM_onehot_stateSeq[5]_i_8_n_0\,
      I3 => \aSeqbuf[9]_i_3__0_n_0\,
      I4 => \i_reg_n_0_[0]\,
      I5 => \first__0\,
      O => ptr0SeqbufTrackNotFixed_i_2_n_0
    );
ptr0SeqbufTrackNotFixed_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \ptr0SeqbufTrackNotFixed_i_1__0_n_0\,
      Q => ptr0SeqbufTrackNotFixed_reg_n_0
    );
\ptr0Seqbuf_i[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B3"
    )
        port map (
      I0 => \ptr0Seqbuf_i[1]_i_2_n_0\,
      I1 => ptr0Seqbuf_i(0),
      I2 => ptr0Seqbuf_i(1),
      O => \ptr0Seqbuf_i[0]_i_1_n_0\
    );
\ptr0Seqbuf_i[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BC"
    )
        port map (
      I0 => \ptr0Seqbuf_i[1]_i_2_n_0\,
      I1 => ptr0Seqbuf_i(0),
      I2 => ptr0Seqbuf_i(1),
      O => \ptr0Seqbuf_i[1]_i_1_n_0\
    );
\ptr0Seqbuf_i[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000000020202"
    )
        port map (
      I0 => \ptr0Seqbuf_i[1]_i_3_n_0\,
      I1 => \ptr0Seqbuf_i[1]_i_4_n_0\,
      I2 => \ptr0Seqbuf_i[1]_i_5_n_0\,
      I3 => \aSeqbuf_reg_n_0_[6]\,
      I4 => ptr0SeqbufTrackNotFixed_reg_n_0,
      I5 => ptr0Seqbuf_to_mclk(6),
      O => \ptr0Seqbuf_i[1]_i_2_n_0\
    );
\ptr0Seqbuf_i[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000084110095"
    )
        port map (
      I0 => ptr0Seqbuf_to_mclk(1),
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      I2 => \aSeqbuf_reg_n_0_[1]\,
      I3 => ptr0Seqbuf_to_mclk(2),
      I4 => \aSeqbuf_reg_n_0_[2]\,
      I5 => \ptr0Seqbuf_i[1]_i_6_n_0\,
      O => \ptr0Seqbuf_i[1]_i_3_n_0\
    );
\ptr0Seqbuf_i[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF78"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[3]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      I2 => ptr0Seqbuf_to_mclk(3),
      I3 => \ptr0Seqbuf_i[1]_i_7_n_0\,
      O => \ptr0Seqbuf_i[1]_i_4_n_0\
    );
\ptr0Seqbuf_i[1]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6FFFF6CC"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[7]\,
      I1 => ptr0Seqbuf_to_mclk(7),
      I2 => \aSeqbuf_reg_n_0_[8]\,
      I3 => ptr0SeqbufTrackNotFixed_reg_n_0,
      I4 => ptr0Seqbuf_to_mclk(8),
      O => \ptr0Seqbuf_i[1]_i_5_n_0\
    );
\ptr0Seqbuf_i[1]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6FFFF6CC"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[9]\,
      I1 => ptr0Seqbuf_to_mclk(9),
      I2 => \aSeqbuf_reg_n_0_[0]\,
      I3 => ptr0SeqbufTrackNotFixed_reg_n_0,
      I4 => ptr0Seqbuf_to_mclk(0),
      O => \ptr0Seqbuf_i[1]_i_6_n_0\
    );
\ptr0Seqbuf_i[1]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6FFFF6CC"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[4]\,
      I1 => ptr0Seqbuf_to_mclk(4),
      I2 => \aSeqbuf_reg_n_0_[5]\,
      I3 => ptr0SeqbufTrackNotFixed_reg_n_0,
      I4 => ptr0Seqbuf_to_mclk(5),
      O => \ptr0Seqbuf_i[1]_i_7_n_0\
    );
\ptr0Seqbuf_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \ptr0Seqbuf_i[0]_i_1_n_0\,
      Q => ptr0Seqbuf_i(0)
    );
\ptr0Seqbuf_i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \ptr0Seqbuf_i[1]_i_1_n_0\,
      Q => ptr0Seqbuf_i(1)
    );
\ptr0Seqbuf_mclk[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82000000"
    )
        port map (
      I0 => \ptr0Seqbuf_mclk[9]_i_2_n_0\,
      I1 => ptr0Seqbuf_to_mclkm2(9),
      I2 => ptr0Seqbuf_to_mclkm1(9),
      I3 => \ptr0Seqbuf_mclk[9]_i_3_n_0\,
      I4 => \ptr0Seqbuf_mclk[9]_i_4_n_0\,
      O => \ptr0Seqbuf_mclk[9]_i_1_n_0\
    );
\ptr0Seqbuf_mclk[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => ptr0Seqbuf_to_mclkm1(0),
      I1 => ptr0Seqbuf_to_mclkm2(0),
      I2 => ptr0Seqbuf_to_mclkm2(2),
      I3 => ptr0Seqbuf_to_mclkm1(2),
      I4 => ptr0Seqbuf_to_mclkm2(1),
      I5 => ptr0Seqbuf_to_mclkm1(1),
      O => \ptr0Seqbuf_mclk[9]_i_2_n_0\
    );
\ptr0Seqbuf_mclk[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => ptr0Seqbuf_to_mclkm1(6),
      I1 => ptr0Seqbuf_to_mclkm2(6),
      I2 => ptr0Seqbuf_to_mclkm2(8),
      I3 => ptr0Seqbuf_to_mclkm1(8),
      I4 => ptr0Seqbuf_to_mclkm2(7),
      I5 => ptr0Seqbuf_to_mclkm1(7),
      O => \ptr0Seqbuf_mclk[9]_i_3_n_0\
    );
\ptr0Seqbuf_mclk[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => ptr0Seqbuf_to_mclkm1(3),
      I1 => ptr0Seqbuf_to_mclkm2(3),
      I2 => ptr0Seqbuf_to_mclkm2(5),
      I3 => ptr0Seqbuf_to_mclkm1(5),
      I4 => ptr0Seqbuf_to_mclkm2(4),
      I5 => ptr0Seqbuf_to_mclkm1(4),
      O => \ptr0Seqbuf_mclk[9]_i_4_n_0\
    );
\ptr0Seqbuf_mclk_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ptr0Seqbuf_mclk[9]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm2(0),
      Q => \ptr0Seqbuf_mclk_reg[9]_0\(0)
    );
\ptr0Seqbuf_mclk_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ptr0Seqbuf_mclk[9]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm2(1),
      Q => \ptr0Seqbuf_mclk_reg[9]_0\(1)
    );
\ptr0Seqbuf_mclk_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ptr0Seqbuf_mclk[9]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm2(2),
      Q => \ptr0Seqbuf_mclk_reg[9]_0\(2)
    );
\ptr0Seqbuf_mclk_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ptr0Seqbuf_mclk[9]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm2(3),
      Q => \ptr0Seqbuf_mclk_reg[9]_0\(3)
    );
\ptr0Seqbuf_mclk_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ptr0Seqbuf_mclk[9]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm2(4),
      Q => \ptr0Seqbuf_mclk_reg[9]_0\(4)
    );
\ptr0Seqbuf_mclk_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ptr0Seqbuf_mclk[9]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm2(5),
      Q => \ptr0Seqbuf_mclk_reg[9]_0\(5)
    );
\ptr0Seqbuf_mclk_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ptr0Seqbuf_mclk[9]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm2(6),
      Q => \ptr0Seqbuf_mclk_reg[9]_0\(6)
    );
\ptr0Seqbuf_mclk_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ptr0Seqbuf_mclk[9]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm2(7),
      Q => \ptr0Seqbuf_mclk_reg[9]_0\(7)
    );
\ptr0Seqbuf_mclk_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ptr0Seqbuf_mclk[9]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm2(8),
      Q => \ptr0Seqbuf_mclk_reg[9]_0\(8)
    );
\ptr0Seqbuf_mclk_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ptr0Seqbuf_mclk[9]_i_1_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm2(9),
      Q => \ptr0Seqbuf_mclk_reg[9]_0\(9)
    );
\ptr0Seqbuf_to_mclk[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[0]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => ptr0Seqbuf(0)
    );
\ptr0Seqbuf_to_mclk[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[1]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => ptr0Seqbuf(1)
    );
\ptr0Seqbuf_to_mclk[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[2]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => ptr0Seqbuf(2)
    );
\ptr0Seqbuf_to_mclk[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[3]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => ptr0Seqbuf(3)
    );
\ptr0Seqbuf_to_mclk[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[4]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => ptr0Seqbuf(4)
    );
\ptr0Seqbuf_to_mclk[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[5]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => ptr0Seqbuf(5)
    );
\ptr0Seqbuf_to_mclk[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[6]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => ptr0Seqbuf(6)
    );
\ptr0Seqbuf_to_mclk[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[7]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => ptr0Seqbuf(7)
    );
\ptr0Seqbuf_to_mclk[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[8]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => ptr0Seqbuf(8)
    );
\ptr0Seqbuf_to_mclk[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \ptr0Seqbuf_i[1]_i_2_n_0\,
      I1 => ptr0Seqbuf_i(0),
      I2 => ptr0Seqbuf_i(1),
      O => \ptr0Seqbuf_to_mclk[9]_i_1_n_0\
    );
\ptr0Seqbuf_to_mclk[9]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[9]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => ptr0Seqbuf(9)
    );
\ptr0Seqbuf_to_mclk_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ptr0Seqbuf_to_mclk[9]_i_1_n_0\,
      CLR => AR(0),
      D => ptr0Seqbuf(0),
      Q => ptr0Seqbuf_to_mclk(0)
    );
\ptr0Seqbuf_to_mclk_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ptr0Seqbuf_to_mclk[9]_i_1_n_0\,
      CLR => AR(0),
      D => ptr0Seqbuf(1),
      Q => ptr0Seqbuf_to_mclk(1)
    );
\ptr0Seqbuf_to_mclk_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ptr0Seqbuf_to_mclk[9]_i_1_n_0\,
      CLR => AR(0),
      D => ptr0Seqbuf(2),
      Q => ptr0Seqbuf_to_mclk(2)
    );
\ptr0Seqbuf_to_mclk_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ptr0Seqbuf_to_mclk[9]_i_1_n_0\,
      CLR => AR(0),
      D => ptr0Seqbuf(3),
      Q => ptr0Seqbuf_to_mclk(3)
    );
\ptr0Seqbuf_to_mclk_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ptr0Seqbuf_to_mclk[9]_i_1_n_0\,
      CLR => AR(0),
      D => ptr0Seqbuf(4),
      Q => ptr0Seqbuf_to_mclk(4)
    );
\ptr0Seqbuf_to_mclk_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ptr0Seqbuf_to_mclk[9]_i_1_n_0\,
      CLR => AR(0),
      D => ptr0Seqbuf(5),
      Q => ptr0Seqbuf_to_mclk(5)
    );
\ptr0Seqbuf_to_mclk_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ptr0Seqbuf_to_mclk[9]_i_1_n_0\,
      CLR => AR(0),
      D => ptr0Seqbuf(6),
      Q => ptr0Seqbuf_to_mclk(6)
    );
\ptr0Seqbuf_to_mclk_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ptr0Seqbuf_to_mclk[9]_i_1_n_0\,
      CLR => AR(0),
      D => ptr0Seqbuf(7),
      Q => ptr0Seqbuf_to_mclk(7)
    );
\ptr0Seqbuf_to_mclk_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ptr0Seqbuf_to_mclk[9]_i_1_n_0\,
      CLR => AR(0),
      D => ptr0Seqbuf(8),
      Q => ptr0Seqbuf_to_mclk(8)
    );
\ptr0Seqbuf_to_mclk_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \ptr0Seqbuf_to_mclk[9]_i_1_n_0\,
      CLR => AR(0),
      D => ptr0Seqbuf(9),
      Q => ptr0Seqbuf_to_mclk(9)
    );
\ptr0Seqbuf_to_mclkm1_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclk(0),
      Q => ptr0Seqbuf_to_mclkm1(0)
    );
\ptr0Seqbuf_to_mclkm1_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclk(1),
      Q => ptr0Seqbuf_to_mclkm1(1)
    );
\ptr0Seqbuf_to_mclkm1_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclk(2),
      Q => ptr0Seqbuf_to_mclkm1(2)
    );
\ptr0Seqbuf_to_mclkm1_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclk(3),
      Q => ptr0Seqbuf_to_mclkm1(3)
    );
\ptr0Seqbuf_to_mclkm1_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclk(4),
      Q => ptr0Seqbuf_to_mclkm1(4)
    );
\ptr0Seqbuf_to_mclkm1_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclk(5),
      Q => ptr0Seqbuf_to_mclkm1(5)
    );
\ptr0Seqbuf_to_mclkm1_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclk(6),
      Q => ptr0Seqbuf_to_mclkm1(6)
    );
\ptr0Seqbuf_to_mclkm1_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclk(7),
      Q => ptr0Seqbuf_to_mclkm1(7)
    );
\ptr0Seqbuf_to_mclkm1_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclk(8),
      Q => ptr0Seqbuf_to_mclkm1(8)
    );
\ptr0Seqbuf_to_mclkm1_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclk(9),
      Q => ptr0Seqbuf_to_mclkm1(9)
    );
\ptr0Seqbuf_to_mclkm2_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm1(0),
      Q => ptr0Seqbuf_to_mclkm2(0)
    );
\ptr0Seqbuf_to_mclkm2_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm1(1),
      Q => ptr0Seqbuf_to_mclkm2(1)
    );
\ptr0Seqbuf_to_mclkm2_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm1(2),
      Q => ptr0Seqbuf_to_mclkm2(2)
    );
\ptr0Seqbuf_to_mclkm2_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm1(3),
      Q => ptr0Seqbuf_to_mclkm2(3)
    );
\ptr0Seqbuf_to_mclkm2_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm1(4),
      Q => ptr0Seqbuf_to_mclkm2(4)
    );
\ptr0Seqbuf_to_mclkm2_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm1(5),
      Q => ptr0Seqbuf_to_mclkm2(5)
    );
\ptr0Seqbuf_to_mclkm2_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm1(6),
      Q => ptr0Seqbuf_to_mclkm2(6)
    );
\ptr0Seqbuf_to_mclkm2_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm1(7),
      Q => ptr0Seqbuf_to_mclkm2(7)
    );
\ptr0Seqbuf_to_mclkm2_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm1(8),
      Q => ptr0Seqbuf_to_mclkm2(8)
    );
\ptr0Seqbuf_to_mclkm2_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => ptr0Seqbuf_to_mclkm1(9),
      Q => ptr0Seqbuf_to_mclkm2(9)
    );
\quad[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(0),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[0]\,
      I3 => first,
      O => quad(0)
    );
\quad[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(1),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[1]\,
      I3 => first,
      O => quad(1)
    );
\quad[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(2),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[2]\,
      I3 => first,
      O => quad(2)
    );
\quad[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(3),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[3]\,
      I3 => first,
      O => quad(3)
    );
\quad[4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(4),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[4]\,
      I3 => first,
      O => quad(4)
    );
\quad[5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(5),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[5]\,
      I3 => first,
      O => quad(5)
    );
\quad[6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(6),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[6]\,
      I3 => first,
      O => quad(6)
    );
\quad[7]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(7),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[7]\,
      I3 => first,
      O => quad(7)
    );
\quad[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010001"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => rdySeq,
      I2 => ackSeqbufBToSeqClear,
      I3 => dneSeq,
      I4 => TCapt,
      I5 => \i_reg_n_0_[0]\,
      O => \quad[8]_i_1__0_n_0\
    );
\quad[8]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => capt(8),
      I1 => \i_reg_n_0_[0]\,
      I2 => \quad_reg_n_0_[8]\,
      I3 => first,
      O => quad(8)
    );
\quad_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \quad[8]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(0),
      Q => \quad_reg_n_0_[0]\
    );
\quad_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \quad[8]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(1),
      Q => \quad_reg_n_0_[1]\
    );
\quad_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \quad[8]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(2),
      Q => \quad_reg_n_0_[2]\
    );
\quad_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \quad[8]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(3),
      Q => \quad_reg_n_0_[3]\
    );
\quad_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \quad[8]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(4),
      Q => \quad_reg_n_0_[4]\
    );
\quad_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \quad[8]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(5),
      Q => \quad_reg_n_0_[5]\
    );
\quad_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \quad[8]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(6),
      Q => \quad_reg_n_0_[6]\
    );
\quad_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \quad[8]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(7),
      Q => \quad_reg_n_0_[7]\
    );
\quad_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \quad[8]_i_1__0_n_0\,
      CLR => AR(0),
      D => quad(8),
      Q => \quad_reg_n_0_[8]\
    );
\rdySeq_i[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"90FF"
    )
        port map (
      I0 => rdySeq,
      I1 => rdySeq_to_mclk,
      I2 => rdySeq_i(1),
      I3 => rdySeq_i(0),
      O => \rdySeq_i[0]_i_1_n_0\
    );
\rdySeq_i[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9FF0"
    )
        port map (
      I0 => rdySeq,
      I1 => rdySeq_to_mclk,
      I2 => rdySeq_i(1),
      I3 => rdySeq_i(0),
      O => \rdySeq_i[1]_i_1_n_0\
    );
\rdySeq_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \rdySeq_i[0]_i_1_n_0\,
      Q => rdySeq_i(0)
    );
\rdySeq_i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \rdySeq_i[1]_i_1_n_0\,
      Q => rdySeq_i(1)
    );
rdySeq_mclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => rdySeq_to_mclkm2,
      I1 => rdySeq_to_mclkm1,
      I2 => rdySeq_mclk,
      O => rdySeq_mclk_i_1_n_0
    );
rdySeq_mclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => rdySeq_mclk_i_1_n_0,
      Q => rdySeq_mclk
    );
rdySeq_to_mclk_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CAAA"
    )
        port map (
      I0 => rdySeq_to_mclk,
      I1 => rdySeq,
      I2 => rdySeq_i(0),
      I3 => rdySeq_i(1),
      O => rdySeq_to_mclk_i_1_n_0
    );
rdySeq_to_mclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => rdySeq_to_mclk_i_1_n_0,
      Q => rdySeq_to_mclk
    );
rdySeq_to_mclkm1_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => rdySeq_to_mclk,
      Q => rdySeq_to_mclkm1
    );
rdySeq_to_mclkm2_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => rdySeq_to_mclkm1,
      Q => rdySeq_to_mclkm2
    );
\reqOpToSeqClear_i[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5595FFFF"
    )
        port map (
      I0 => reqOpToSeqClear_to_memclk_reg_n_0,
      I1 => stateOp(1),
      I2 => stateOp(2),
      I3 => stateOp(0),
      I4 => reqOpToSeqClear_i,
      O => \reqOpToSeqClear_i[0]_i_1_n_0\
    );
\reqOpToSeqClear_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \reqOpToSeqClear_i[0]_i_1_n_0\,
      Q => reqOpToSeqClear_i
    );
reqOpToSeqClear_memclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => reqOpToSeqClear_to_memclkm2,
      I1 => reqOpToSeqClear_to_memclkm1,
      I2 => reqOpToSeqClear_memclk,
      O => reqOpToSeqClear_memclk_i_1_n_0
    );
reqOpToSeqClear_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => reqOpToSeqClear_memclk_i_1_n_0,
      Q => reqOpToSeqClear_memclk
    );
reqOpToSeqClear_to_memclk_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"75552000"
    )
        port map (
      I0 => reqOpToSeqClear_i,
      I1 => stateOp(0),
      I2 => stateOp(2),
      I3 => stateOp(1),
      I4 => reqOpToSeqClear_to_memclk_reg_n_0,
      O => reqOpToSeqClear_to_memclk_i_1_n_0
    );
reqOpToSeqClear_to_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => reqOpToSeqClear_to_memclk_i_1_n_0,
      Q => reqOpToSeqClear_to_memclk_reg_n_0
    );
reqOpToSeqClear_to_memclkm1_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => reqOpToSeqClear_to_memclk_reg_n_0,
      Q => reqOpToSeqClear_to_memclkm1
    );
reqOpToSeqClear_to_memclkm2_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => reqOpToSeqClear_to_memclkm1,
      Q => reqOpToSeqClear_to_memclkm2
    );
\reqSeqbufBToSeqClear_i[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5595FFFF"
    )
        port map (
      I0 => reqSeqbufBToSeqClear_to_memclk_reg_n_0,
      I1 => stateSeqbufB_reg(2),
      I2 => stateSeqbufB_reg(0),
      I3 => stateSeqbufB_reg(1),
      I4 => reqSeqbufBToSeqClear_i,
      O => \reqSeqbufBToSeqClear_i[0]_i_1_n_0\
    );
\reqSeqbufBToSeqClear_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \reqSeqbufBToSeqClear_i[0]_i_1_n_0\,
      Q => reqSeqbufBToSeqClear_i
    );
reqSeqbufBToSeqClear_memclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => reqSeqbufBToSeqClear_to_memclkm2,
      I1 => reqSeqbufBToSeqClear_to_memclkm1,
      I2 => reqSeqbufBToSeqClear_memclk,
      O => reqSeqbufBToSeqClear_memclk_i_1_n_0
    );
reqSeqbufBToSeqClear_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => reqSeqbufBToSeqClear_memclk_i_1_n_0,
      Q => reqSeqbufBToSeqClear_memclk
    );
reqSeqbufBToSeqClear_to_memclk_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"75552000"
    )
        port map (
      I0 => reqSeqbufBToSeqClear_i,
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      I3 => stateSeqbufB_reg(2),
      I4 => reqSeqbufBToSeqClear_to_memclk_reg_n_0,
      O => reqSeqbufBToSeqClear_to_memclk_i_1_n_0
    );
reqSeqbufBToSeqClear_to_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => reqSeqbufBToSeqClear_to_memclk_i_1_n_0,
      Q => reqSeqbufBToSeqClear_to_memclk_reg_n_0
    );
reqSeqbufBToSeqClear_to_memclkm1_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => reqSeqbufBToSeqClear_to_memclk_reg_n_0,
      Q => reqSeqbufBToSeqClear_to_memclkm1
    );
reqSeqbufBToSeqClear_to_memclkm2_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => reqSeqbufBToSeqClear_to_memclkm1,
      Q => reqSeqbufBToSeqClear_to_memclkm2
    );
\restart_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF300000500"
    )
        port map (
      I0 => restart_reg_0,
      I1 => strb_last_reg_0,
      I2 => stateOp(2),
      I3 => stateOp(0),
      I4 => stateOp(1),
      I5 => restart_reg_n_0,
      O => \restart_i_1__0_n_0\
    );
restart_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \restart_i_1__0_n_0\,
      Q => restart_reg_n_0
    );
\retbuf[0][0]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"42"
    )
        port map (
      I0 => stateOp(1),
      I1 => stateOp(2),
      I2 => stateOp(0),
      O => \^memtrackgetinfotixvstate\(0)
    );
rng_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => rng_reg_1,
      Q => \^rng_reg_0\
    );
staFallingNotRising_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => D(17),
      I1 => D(19),
      I2 => D(21),
      I3 => D(23),
      I4 => staFallingNotRising_i_2_n_0,
      O => staFallingNotRising_i_1_n_0
    );
staFallingNotRising_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => D(18),
      I1 => D(16),
      I2 => D(22),
      I3 => D(20),
      O => staFallingNotRising_i_2_n_0
    );
staFallingNotRising_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => staFallingNotRising_i_1_n_0,
      Q => staFallingNotRising_reg_n_0
    );
\staTixVTrigger[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5547"
    )
        port map (
      I0 => strb_last_reg_0,
      I1 => stateOp(2),
      I2 => stateOp(0),
      I3 => stateOp(1),
      O => \^stateop_reg[2]_0\
    );
\staTixVTrigger_i[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5755"
    )
        port map (
      I0 => staTixVTrigger_i,
      I1 => \staTixVTrigger_to_memclk[7]_i_2_n_0\,
      I2 => \staTixVTrigger_to_memclk[7]_i_3_n_0\,
      I3 => \staTixVTrigger_to_memclk[7]_i_4_n_0\,
      O => \staTixVTrigger_i[0]_i_1_n_0\
    );
\staTixVTrigger_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_i[0]_i_1_n_0\,
      Q => staTixVTrigger_i
    );
\staTixVTrigger_memclk[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000000000"
    )
        port map (
      I0 => staTixVTrigger_to_memclkm2(7),
      I1 => staTixVTrigger_to_memclkm1(7),
      I2 => staTixVTrigger_to_memclkm2(6),
      I3 => staTixVTrigger_to_memclkm1(6),
      I4 => \staTixVTrigger_memclk[7]_i_2_n_0\,
      I5 => \staTixVTrigger_memclk[7]_i_3_n_0\,
      O => staTixVTrigger_memclk0
    );
\staTixVTrigger_memclk[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => staTixVTrigger_to_memclkm1(3),
      I1 => staTixVTrigger_to_memclkm2(3),
      I2 => staTixVTrigger_to_memclkm2(5),
      I3 => staTixVTrigger_to_memclkm1(5),
      I4 => staTixVTrigger_to_memclkm2(4),
      I5 => staTixVTrigger_to_memclkm1(4),
      O => \staTixVTrigger_memclk[7]_i_2_n_0\
    );
\staTixVTrigger_memclk[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => staTixVTrigger_to_memclkm1(0),
      I1 => staTixVTrigger_to_memclkm2(0),
      I2 => staTixVTrigger_to_memclkm2(2),
      I3 => staTixVTrigger_to_memclkm1(2),
      I4 => staTixVTrigger_to_memclkm2(1),
      I5 => staTixVTrigger_to_memclkm1(1),
      O => \staTixVTrigger_memclk[7]_i_3_n_0\
    );
\staTixVTrigger_memclk_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => staTixVTrigger_memclk0,
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm2(0),
      Q => staTixVTrigger_memclk(0)
    );
\staTixVTrigger_memclk_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => staTixVTrigger_memclk0,
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm2(1),
      Q => staTixVTrigger_memclk(1)
    );
\staTixVTrigger_memclk_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => staTixVTrigger_memclk0,
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm2(2),
      Q => \staTixVTrigger_memclk__0\(2)
    );
\staTixVTrigger_memclk_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => staTixVTrigger_memclk0,
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm2(3),
      Q => \staTixVTrigger_memclk__0\(3)
    );
\staTixVTrigger_memclk_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => staTixVTrigger_memclk0,
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm2(4),
      Q => \staTixVTrigger_memclk__0\(4)
    );
\staTixVTrigger_memclk_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => staTixVTrigger_memclk0,
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm2(5),
      Q => \staTixVTrigger_memclk__0\(5)
    );
\staTixVTrigger_memclk_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => staTixVTrigger_memclk0,
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm2(6),
      Q => \staTixVTrigger_memclk__0\(6)
    );
\staTixVTrigger_memclk_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => staTixVTrigger_memclk0,
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm2(7),
      Q => \staTixVTrigger_memclk__0\(7)
    );
\staTixVTrigger_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg[7]_0\(0),
      Q => \staTixVTrigger_reg_n_0_[0]\
    );
\staTixVTrigger_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg[7]_0\(1),
      Q => \staTixVTrigger_reg_n_0_[1]\
    );
\staTixVTrigger_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg[7]_0\(2),
      Q => \staTixVTrigger_reg_n_0_[2]\
    );
\staTixVTrigger_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg[7]_0\(3),
      Q => \staTixVTrigger_reg_n_0_[3]\
    );
\staTixVTrigger_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg[7]_0\(4),
      Q => \staTixVTrigger_reg_n_0_[4]\
    );
\staTixVTrigger_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg[7]_0\(5),
      Q => \staTixVTrigger_reg_n_0_[5]\
    );
\staTixVTrigger_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg[7]_0\(6),
      Q => \staTixVTrigger_reg_n_0_[6]\
    );
\staTixVTrigger_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg[7]_0\(7),
      Q => \staTixVTrigger_reg_n_0_[7]\
    );
\staTixVTrigger_to_memclk[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A8AA"
    )
        port map (
      I0 => staTixVTrigger_i,
      I1 => \staTixVTrigger_to_memclk[7]_i_2_n_0\,
      I2 => \staTixVTrigger_to_memclk[7]_i_3_n_0\,
      I3 => \staTixVTrigger_to_memclk[7]_i_4_n_0\,
      O => staTixVTrigger_to_memclk
    );
\staTixVTrigger_to_memclk[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \staTixVTrigger_to_memclk_reg_n_0_[3]\,
      I1 => \staTixVTrigger_reg_n_0_[3]\,
      I2 => \staTixVTrigger_reg_n_0_[5]\,
      I3 => \staTixVTrigger_to_memclk_reg_n_0_[5]\,
      I4 => \staTixVTrigger_reg_n_0_[4]\,
      I5 => \staTixVTrigger_to_memclk_reg_n_0_[4]\,
      O => \staTixVTrigger_to_memclk[7]_i_2_n_0\
    );
\staTixVTrigger_to_memclk[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \staTixVTrigger_to_memclk_reg_n_0_[0]\,
      I1 => \staTixVTrigger_reg_n_0_[0]\,
      I2 => \staTixVTrigger_reg_n_0_[1]\,
      I3 => \staTixVTrigger_to_memclk_reg_n_0_[1]\,
      I4 => \staTixVTrigger_reg_n_0_[2]\,
      I5 => \staTixVTrigger_to_memclk_reg_n_0_[2]\,
      O => \staTixVTrigger_to_memclk[7]_i_3_n_0\
    );
\staTixVTrigger_to_memclk[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \staTixVTrigger_to_memclk_reg_n_0_[7]\,
      I1 => \staTixVTrigger_reg_n_0_[7]\,
      I2 => \staTixVTrigger_to_memclk_reg_n_0_[6]\,
      I3 => \staTixVTrigger_reg_n_0_[6]\,
      O => \staTixVTrigger_to_memclk[7]_i_4_n_0\
    );
\staTixVTrigger_to_memclk_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg_n_0_[0]\,
      Q => \staTixVTrigger_to_memclk_reg_n_0_[0]\
    );
\staTixVTrigger_to_memclk_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg_n_0_[1]\,
      Q => \staTixVTrigger_to_memclk_reg_n_0_[1]\
    );
\staTixVTrigger_to_memclk_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg_n_0_[2]\,
      Q => \staTixVTrigger_to_memclk_reg_n_0_[2]\
    );
\staTixVTrigger_to_memclk_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg_n_0_[3]\,
      Q => \staTixVTrigger_to_memclk_reg_n_0_[3]\
    );
\staTixVTrigger_to_memclk_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg_n_0_[4]\,
      Q => \staTixVTrigger_to_memclk_reg_n_0_[4]\
    );
\staTixVTrigger_to_memclk_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg_n_0_[5]\,
      Q => \staTixVTrigger_to_memclk_reg_n_0_[5]\
    );
\staTixVTrigger_to_memclk_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg_n_0_[6]\,
      Q => \staTixVTrigger_to_memclk_reg_n_0_[6]\
    );
\staTixVTrigger_to_memclk_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \staTixVTrigger_reg_n_0_[7]\,
      Q => \staTixVTrigger_to_memclk_reg_n_0_[7]\
    );
\staTixVTrigger_to_memclkm1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \staTixVTrigger_to_memclk_reg_n_0_[0]\,
      Q => staTixVTrigger_to_memclkm1(0)
    );
\staTixVTrigger_to_memclkm1_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \staTixVTrigger_to_memclk_reg_n_0_[1]\,
      Q => staTixVTrigger_to_memclkm1(1)
    );
\staTixVTrigger_to_memclkm1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \staTixVTrigger_to_memclk_reg_n_0_[2]\,
      Q => staTixVTrigger_to_memclkm1(2)
    );
\staTixVTrigger_to_memclkm1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \staTixVTrigger_to_memclk_reg_n_0_[3]\,
      Q => staTixVTrigger_to_memclkm1(3)
    );
\staTixVTrigger_to_memclkm1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \staTixVTrigger_to_memclk_reg_n_0_[4]\,
      Q => staTixVTrigger_to_memclkm1(4)
    );
\staTixVTrigger_to_memclkm1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \staTixVTrigger_to_memclk_reg_n_0_[5]\,
      Q => staTixVTrigger_to_memclkm1(5)
    );
\staTixVTrigger_to_memclkm1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \staTixVTrigger_to_memclk_reg_n_0_[6]\,
      Q => staTixVTrigger_to_memclkm1(6)
    );
\staTixVTrigger_to_memclkm1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \staTixVTrigger_to_memclk_reg_n_0_[7]\,
      Q => staTixVTrigger_to_memclkm1(7)
    );
\staTixVTrigger_to_memclkm2_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm1(0),
      Q => staTixVTrigger_to_memclkm2(0)
    );
\staTixVTrigger_to_memclkm2_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm1(1),
      Q => staTixVTrigger_to_memclkm2(1)
    );
\staTixVTrigger_to_memclkm2_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm1(2),
      Q => staTixVTrigger_to_memclkm2(2)
    );
\staTixVTrigger_to_memclkm2_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm1(3),
      Q => staTixVTrigger_to_memclkm2(3)
    );
\staTixVTrigger_to_memclkm2_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm1(4),
      Q => staTixVTrigger_to_memclkm2(4)
    );
\staTixVTrigger_to_memclkm2_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm1(5),
      Q => staTixVTrigger_to_memclkm2(5)
    );
\staTixVTrigger_to_memclkm2_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm1(6),
      Q => staTixVTrigger_to_memclkm2(6)
    );
\staTixVTrigger_to_memclkm2_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => staTixVTrigger_to_memclkm1(7),
      Q => staTixVTrigger_to_memclkm2(7)
    );
\start_i[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9F0F"
    )
        port map (
      I0 => start_to_mclk,
      I1 => start,
      I2 => start_i(0),
      I3 => start_i(1),
      O => \start_i[0]_i_1_n_0\
    );
\start_i[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9FF0"
    )
        port map (
      I0 => start_to_mclk,
      I1 => start,
      I2 => start_i(0),
      I3 => start_i(1),
      O => \start_i[1]_i_1_n_0\
    );
start_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003808"
    )
        port map (
      I0 => start_reg_0,
      I1 => staTixVTrigger_memclk(1),
      I2 => staTixVTrigger_memclk(0),
      I3 => stop_reg_0,
      I4 => start_i_2_n_0,
      O => start_i_1_n_0
    );
start_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \staTixVTrigger_memclk__0\(6),
      I1 => \staTixVTrigger_memclk__0\(7),
      I2 => \staTixVTrigger_memclk__0\(3),
      I3 => \staTixVTrigger_memclk__0\(2),
      I4 => \staTixVTrigger_memclk__0\(5),
      I5 => \staTixVTrigger_memclk__0\(4),
      O => start_i_2_n_0
    );
\start_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \start_i[0]_i_1_n_0\,
      Q => start_i(0)
    );
\start_i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \start_i[1]_i_1_n_0\,
      Q => start_i(1)
    );
start_mclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => start_to_mclkm2,
      I1 => start_to_mclkm1,
      I2 => start_mclk,
      O => start_mclk_i_1_n_0
    );
start_mclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => start_mclk_i_1_n_0,
      Q => start_mclk
    );
start_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => start_i_1_n_0,
      Q => start
    );
start_to_mclk_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E4CC"
    )
        port map (
      I0 => start_i(1),
      I1 => start_to_mclk,
      I2 => start,
      I3 => start_i(0),
      O => start_to_mclk_i_1_n_0
    );
start_to_mclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => start_to_mclk_i_1_n_0,
      Q => start_to_mclk
    );
start_to_mclkm1_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => start_to_mclk,
      Q => start_to_mclkm1
    );
start_to_mclkm2_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => start_to_mclkm1,
      Q => start_to_mclkm2
    );
\stateOp[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"577D"
    )
        port map (
      I0 => strb_last_reg_0,
      I1 => stateOp(1),
      I2 => stateOp(0),
      I3 => stateOp(2),
      O => \stateOp[0]_i_1__2_n_0\
    );
\stateOp[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C0000FA00000000"
    )
        port map (
      I0 => \^rng_reg_0\,
      I1 => restart_reg_n_0,
      I2 => stateOp(1),
      I3 => stateOp(2),
      I4 => stateOp(0),
      I5 => strb_last_reg_0,
      O => \stateOp[1]_i_1__2_n_0\
    );
\stateOp[2]_i_10__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BB0BB0BB"
    )
        port map (
      I0 => \stateOp[2]_i_36__0_n_0\,
      I1 => \stateOp[2]_i_37__0_n_0\,
      I2 => staFallingNotRising_reg_n_0,
      I3 => start_mclk,
      I4 => strb_last_reg_n_0,
      O => \stateOp[2]_i_10__0_n_0\
    );
\stateOp[2]_i_11__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BAAAAAAA"
    )
        port map (
      I0 => \^stateop_reg[2]_0\,
      I1 => stateOp(0),
      I2 => stateOp(2),
      I3 => stateOp(1),
      I4 => rdySeq_mclk,
      O => \stateOp[2]_i_11__0_n_0\
    );
\stateOp[2]_i_13__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(31),
      I1 => \TCaptMax_reg_n_0_[31]\,
      I2 => \^q\(30),
      I3 => \TCaptMax_reg_n_0_[30]\,
      O => \stateOp[2]_i_13__0_n_0\
    );
\stateOp[2]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(29),
      I1 => \TCaptMax_reg_n_0_[29]\,
      I2 => \^q\(28),
      I3 => \TCaptMax_reg_n_0_[28]\,
      O => \stateOp[2]_i_14_n_0\
    );
\stateOp[2]_i_15__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(27),
      I1 => \TCaptMax_reg_n_0_[27]\,
      I2 => \^q\(26),
      I3 => \TCaptMax_reg_n_0_[26]\,
      O => \stateOp[2]_i_15__0_n_0\
    );
\stateOp[2]_i_16__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(25),
      I1 => \TCaptMax_reg_n_0_[25]\,
      I2 => \^q\(24),
      I3 => \TCaptMax_reg_n_0_[24]\,
      O => \stateOp[2]_i_16__0_n_0\
    );
\stateOp[2]_i_17__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(23),
      I1 => \TCaptMax_reg_n_0_[23]\,
      I2 => \^q\(22),
      I3 => \TCaptMax_reg_n_0_[22]\,
      O => \stateOp[2]_i_17__0_n_0\
    );
\stateOp[2]_i_18__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(21),
      I1 => \TCaptMax_reg_n_0_[21]\,
      I2 => \^q\(20),
      I3 => \TCaptMax_reg_n_0_[20]\,
      O => \stateOp[2]_i_18__0_n_0\
    );
\stateOp[2]_i_19__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(19),
      I1 => \TCaptMax_reg_n_0_[19]\,
      I2 => \^q\(18),
      I3 => \TCaptMax_reg_n_0_[18]\,
      O => \stateOp[2]_i_19__0_n_0\
    );
\stateOp[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEEE40000"
    )
        port map (
      I0 => stateOp(0),
      I1 => \stateOp[2]_i_3__0_n_0\,
      I2 => rdySeq_mclk,
      I3 => restart_reg_n_0,
      I4 => \^memtrackgetinfotixvstate\(1),
      I5 => \stateOp[2]_i_5__0_n_0\,
      O => \stateOp[2]_i_1__0_n_0\
    );
\stateOp[2]_i_20__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(17),
      I1 => \TCaptMax_reg_n_0_[17]\,
      I2 => \^q\(16),
      I3 => \TCaptMax_reg_n_0_[16]\,
      O => \stateOp[2]_i_20__0_n_0\
    );
\stateOp[2]_i_21__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[31]\,
      I1 => \^q\(31),
      I2 => \TCaptMax_reg_n_0_[30]\,
      I3 => \^q\(30),
      O => \stateOp[2]_i_21__0_n_0\
    );
\stateOp[2]_i_22__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[29]\,
      I1 => \^q\(29),
      I2 => \TCaptMax_reg_n_0_[28]\,
      I3 => \^q\(28),
      O => \stateOp[2]_i_22__0_n_0\
    );
\stateOp[2]_i_23__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[27]\,
      I1 => \^q\(27),
      I2 => \TCaptMax_reg_n_0_[26]\,
      I3 => \^q\(26),
      O => \stateOp[2]_i_23__0_n_0\
    );
\stateOp[2]_i_24__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[25]\,
      I1 => \^q\(25),
      I2 => \TCaptMax_reg_n_0_[24]\,
      I3 => \^q\(24),
      O => \stateOp[2]_i_24__0_n_0\
    );
\stateOp[2]_i_25__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[23]\,
      I1 => \^q\(23),
      I2 => \TCaptMax_reg_n_0_[22]\,
      I3 => \^q\(22),
      O => \stateOp[2]_i_25__0_n_0\
    );
\stateOp[2]_i_26__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[21]\,
      I1 => \^q\(21),
      I2 => \TCaptMax_reg_n_0_[20]\,
      I3 => \^q\(20),
      O => \stateOp[2]_i_26__0_n_0\
    );
\stateOp[2]_i_27__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[19]\,
      I1 => \^q\(19),
      I2 => \TCaptMax_reg_n_0_[18]\,
      I3 => \^q\(18),
      O => \stateOp[2]_i_27__0_n_0\
    );
\stateOp[2]_i_28__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[17]\,
      I1 => \^q\(17),
      I2 => \TCaptMax_reg_n_0_[16]\,
      I3 => \^q\(16),
      O => \stateOp[2]_i_28__0_n_0\
    );
\stateOp[2]_i_29__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[5]\,
      I1 => \TCaptMax_reg_n_0_[4]\,
      I2 => \TCaptMax_reg_n_0_[7]\,
      I3 => \TCaptMax_reg_n_0_[6]\,
      O => \stateOp[2]_i_29__0_n_0\
    );
\stateOp[2]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004E46"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(0),
      I2 => stateOp(1),
      I3 => restart_reg_n_0,
      I4 => \^stateop_reg[2]_0\,
      O => \stateOp[2]_i_2__0_n_0\
    );
\stateOp[2]_i_30__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[8]\,
      I1 => \TCaptMax_reg_n_0_[11]\,
      I2 => \TCaptMax_reg_n_0_[9]\,
      I3 => \TCaptMax_reg_n_0_[10]\,
      I4 => \stateOp[2]_i_54__0_n_0\,
      O => \stateOp[2]_i_30__0_n_0\
    );
\stateOp[2]_i_31__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[21]\,
      I1 => \TCaptMax_reg_n_0_[20]\,
      I2 => \TCaptMax_reg_n_0_[23]\,
      I3 => \TCaptMax_reg_n_0_[22]\,
      O => \stateOp[2]_i_31__0_n_0\
    );
\stateOp[2]_i_32__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[24]\,
      I1 => \TCaptMax_reg_n_0_[27]\,
      I2 => \TCaptMax_reg_n_0_[25]\,
      I3 => \TCaptMax_reg_n_0_[26]\,
      I4 => \stateOp[2]_i_55__0_n_0\,
      O => \stateOp[2]_i_32__0_n_0\
    );
\stateOp[2]_i_33__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \^q\(8),
      I1 => \^q\(29),
      I2 => \^q\(9),
      I3 => \^q\(13),
      I4 => \stateOp[2]_i_56__0_n_0\,
      O => \stateOp[2]_i_33__0_n_0\
    );
\stateOp[2]_i_34__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \^q\(17),
      I1 => \^q\(20),
      I2 => \^q\(18),
      I3 => \^q\(19),
      I4 => \stateOp[2]_i_57__0_n_0\,
      O => \stateOp[2]_i_34__0_n_0\
    );
\stateOp[2]_i_35__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \^q\(25),
      I1 => \^q\(31),
      I2 => \^q\(27),
      I3 => \^q\(28),
      I4 => \stateOp[2]_i_58_n_0\,
      O => \stateOp[2]_i_35__0_n_0\
    );
\stateOp[2]_i_36__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \staTixVTrigger_reg_n_0_[6]\,
      I1 => \staTixVTrigger_reg_n_0_[5]\,
      I2 => \staTixVTrigger_reg_n_0_[7]\,
      I3 => \staTixVTrigger_reg_n_0_[4]\,
      O => \stateOp[2]_i_36__0_n_0\
    );
\stateOp[2]_i_37__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \staTixVTrigger_reg_n_0_[3]\,
      I1 => \staTixVTrigger_reg_n_0_[0]\,
      I2 => \staTixVTrigger_reg_n_0_[2]\,
      I3 => \staTixVTrigger_reg_n_0_[1]\,
      O => \stateOp[2]_i_37__0_n_0\
    );
\stateOp[2]_i_38__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(15),
      I1 => \TCaptMax_reg_n_0_[15]\,
      I2 => \^q\(14),
      I3 => \TCaptMax_reg_n_0_[14]\,
      O => \stateOp[2]_i_38__0_n_0\
    );
\stateOp[2]_i_39__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(13),
      I1 => \TCaptMax_reg_n_0_[13]\,
      I2 => \^q\(12),
      I3 => \TCaptMax_reg_n_0_[12]\,
      O => \stateOp[2]_i_39__0_n_0\
    );
\stateOp[2]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF54545400"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[3]_i_3__0_n_0\,
      I1 => \stateOp_reg[2]_i_6_n_0\,
      I2 => \^avllenseqbufmemtracktohostif\(0),
      I3 => \stateOp[2]_i_7_n_0\,
      I4 => \stateOp[2]_i_8__0_n_0\,
      I5 => \stateOp[2]_i_9_n_0\,
      O => \stateOp[2]_i_3__0_n_0\
    );
\stateOp[2]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(1),
      O => \^memtrackgetinfotixvstate\(1)
    );
\stateOp[2]_i_40__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(11),
      I1 => \TCaptMax_reg_n_0_[11]\,
      I2 => \^q\(10),
      I3 => \TCaptMax_reg_n_0_[10]\,
      O => \stateOp[2]_i_40__0_n_0\
    );
\stateOp[2]_i_41__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(9),
      I1 => \TCaptMax_reg_n_0_[9]\,
      I2 => \^q\(8),
      I3 => \TCaptMax_reg_n_0_[8]\,
      O => \stateOp[2]_i_41__0_n_0\
    );
\stateOp[2]_i_42__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(7),
      I1 => \TCaptMax_reg_n_0_[7]\,
      I2 => \^q\(6),
      I3 => \TCaptMax_reg_n_0_[6]\,
      O => \stateOp[2]_i_42__0_n_0\
    );
\stateOp[2]_i_43__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(5),
      I1 => \TCaptMax_reg_n_0_[5]\,
      I2 => \^q\(4),
      I3 => \TCaptMax_reg_n_0_[4]\,
      O => \stateOp[2]_i_43__0_n_0\
    );
\stateOp[2]_i_44__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(3),
      I1 => \TCaptMax_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \TCaptMax_reg_n_0_[2]\,
      O => \stateOp[2]_i_44__0_n_0\
    );
\stateOp[2]_i_45__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^q\(1),
      I1 => \TCaptMax_reg_n_0_[1]\,
      I2 => \^q\(0),
      I3 => \TCaptMax_reg_n_0_[0]\,
      O => \stateOp[2]_i_45__0_n_0\
    );
\stateOp[2]_i_46__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[15]\,
      I1 => \^q\(15),
      I2 => \TCaptMax_reg_n_0_[14]\,
      I3 => \^q\(14),
      O => \stateOp[2]_i_46__0_n_0\
    );
\stateOp[2]_i_47__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[13]\,
      I1 => \^q\(13),
      I2 => \TCaptMax_reg_n_0_[12]\,
      I3 => \^q\(12),
      O => \stateOp[2]_i_47__0_n_0\
    );
\stateOp[2]_i_48__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[11]\,
      I1 => \^q\(11),
      I2 => \TCaptMax_reg_n_0_[10]\,
      I3 => \^q\(10),
      O => \stateOp[2]_i_48__0_n_0\
    );
\stateOp[2]_i_49__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[9]\,
      I1 => \^q\(9),
      I2 => \TCaptMax_reg_n_0_[8]\,
      I3 => \^q\(8),
      O => \stateOp[2]_i_49__0_n_0\
    );
\stateOp[2]_i_50__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[7]\,
      I1 => \^q\(7),
      I2 => \TCaptMax_reg_n_0_[6]\,
      I3 => \^q\(6),
      O => \stateOp[2]_i_50__0_n_0\
    );
\stateOp[2]_i_51__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[5]\,
      I1 => \^q\(5),
      I2 => \TCaptMax_reg_n_0_[4]\,
      I3 => \^q\(4),
      O => \stateOp[2]_i_51__0_n_0\
    );
\stateOp[2]_i_52__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[3]\,
      I1 => \^q\(3),
      I2 => \TCaptMax_reg_n_0_[2]\,
      I3 => \^q\(2),
      O => \stateOp[2]_i_52__0_n_0\
    );
\stateOp[2]_i_53__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[1]\,
      I1 => \^q\(1),
      I2 => \TCaptMax_reg_n_0_[0]\,
      I3 => \^q\(0),
      O => \stateOp[2]_i_53__0_n_0\
    );
\stateOp[2]_i_54__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[13]\,
      I1 => \TCaptMax_reg_n_0_[12]\,
      I2 => \TCaptMax_reg_n_0_[15]\,
      I3 => \TCaptMax_reg_n_0_[14]\,
      O => \stateOp[2]_i_54__0_n_0\
    );
\stateOp[2]_i_55__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[29]\,
      I1 => \TCaptMax_reg_n_0_[28]\,
      I2 => \TCaptMax_reg_n_0_[31]\,
      I3 => \TCaptMax_reg_n_0_[30]\,
      O => \stateOp[2]_i_55__0_n_0\
    );
\stateOp[2]_i_56__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^q\(23),
      I1 => \^q\(10),
      I2 => \^q\(24),
      I3 => \^q\(22),
      O => \stateOp[2]_i_56__0_n_0\
    );
\stateOp[2]_i_57__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^q\(26),
      I1 => \^q\(11),
      I2 => \^q\(21),
      I3 => \^q\(12),
      O => \stateOp[2]_i_57__0_n_0\
    );
\stateOp[2]_i_58\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^q\(15),
      I1 => \^q\(14),
      I2 => \^q\(30),
      I3 => \^q\(16),
      O => \stateOp[2]_i_58_n_0\
    );
\stateOp[2]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000AF22"
    )
        port map (
      I0 => stateOp(1),
      I1 => \stateOp[2]_i_10__0_n_0\,
      I2 => restart_reg_0,
      I3 => stateOp(0),
      I4 => stateOp(2),
      I5 => \stateOp[2]_i_11__0_n_0\,
      O => \stateOp[2]_i_5__0_n_0\
    );
\stateOp[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \stateOp[2]_i_29__0_n_0\,
      I1 => \TCaptMax_reg_n_0_[3]\,
      I2 => \TCaptMax_reg_n_0_[2]\,
      I3 => \TCaptMax_reg_n_0_[1]\,
      I4 => \TCaptMax_reg_n_0_[0]\,
      I5 => \stateOp[2]_i_30__0_n_0\,
      O => \stateOp[2]_i_7_n_0\
    );
\stateOp[2]_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \stateOp[2]_i_31__0_n_0\,
      I1 => \TCaptMax_reg_n_0_[17]\,
      I2 => \TCaptMax_reg_n_0_[16]\,
      I3 => \TCaptMax_reg_n_0_[19]\,
      I4 => \TCaptMax_reg_n_0_[18]\,
      I5 => \stateOp[2]_i_32__0_n_0\,
      O => \stateOp[2]_i_8__0_n_0\
    );
\stateOp[2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"242424FF24242424"
    )
        port map (
      I0 => stoFallingNotRising,
      I1 => stop_mclk,
      I2 => strb_last_reg_n_0,
      I3 => \stateOp[2]_i_33__0_n_0\,
      I4 => \stateOp[2]_i_34__0_n_0\,
      I5 => \stateOp[2]_i_35__0_n_0\,
      O => \stateOp[2]_i_9_n_0\
    );
\stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[2]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \stateOp[0]_i_1__2_n_0\,
      Q => stateOp(0)
    );
\stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[2]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \stateOp[1]_i_1__2_n_0\,
      Q => stateOp(1)
    );
\stateOp_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[2]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \stateOp[2]_i_2__0_n_0\,
      Q => stateOp(2)
    );
\stateOp_reg[2]_i_12\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \stateOp_reg[2]_i_12_n_0\,
      CO(6) => \stateOp_reg[2]_i_12_n_1\,
      CO(5) => \stateOp_reg[2]_i_12_n_2\,
      CO(4) => \stateOp_reg[2]_i_12_n_3\,
      CO(3) => \stateOp_reg[2]_i_12_n_4\,
      CO(2) => \stateOp_reg[2]_i_12_n_5\,
      CO(1) => \stateOp_reg[2]_i_12_n_6\,
      CO(0) => \stateOp_reg[2]_i_12_n_7\,
      DI(7) => \stateOp[2]_i_38__0_n_0\,
      DI(6) => \stateOp[2]_i_39__0_n_0\,
      DI(5) => \stateOp[2]_i_40__0_n_0\,
      DI(4) => \stateOp[2]_i_41__0_n_0\,
      DI(3) => \stateOp[2]_i_42__0_n_0\,
      DI(2) => \stateOp[2]_i_43__0_n_0\,
      DI(1) => \stateOp[2]_i_44__0_n_0\,
      DI(0) => \stateOp[2]_i_45__0_n_0\,
      O(7 downto 0) => \NLW_stateOp_reg[2]_i_12_O_UNCONNECTED\(7 downto 0),
      S(7) => \stateOp[2]_i_46__0_n_0\,
      S(6) => \stateOp[2]_i_47__0_n_0\,
      S(5) => \stateOp[2]_i_48__0_n_0\,
      S(4) => \stateOp[2]_i_49__0_n_0\,
      S(3) => \stateOp[2]_i_50__0_n_0\,
      S(2) => \stateOp[2]_i_51__0_n_0\,
      S(1) => \stateOp[2]_i_52__0_n_0\,
      S(0) => \stateOp[2]_i_53__0_n_0\
    );
\stateOp_reg[2]_i_6\: unisim.vcomponents.CARRY8
     port map (
      CI => \stateOp_reg[2]_i_12_n_0\,
      CI_TOP => '0',
      CO(7) => \stateOp_reg[2]_i_6_n_0\,
      CO(6) => \stateOp_reg[2]_i_6_n_1\,
      CO(5) => \stateOp_reg[2]_i_6_n_2\,
      CO(4) => \stateOp_reg[2]_i_6_n_3\,
      CO(3) => \stateOp_reg[2]_i_6_n_4\,
      CO(2) => \stateOp_reg[2]_i_6_n_5\,
      CO(1) => \stateOp_reg[2]_i_6_n_6\,
      CO(0) => \stateOp_reg[2]_i_6_n_7\,
      DI(7) => \stateOp[2]_i_13__0_n_0\,
      DI(6) => \stateOp[2]_i_14_n_0\,
      DI(5) => \stateOp[2]_i_15__0_n_0\,
      DI(4) => \stateOp[2]_i_16__0_n_0\,
      DI(3) => \stateOp[2]_i_17__0_n_0\,
      DI(2) => \stateOp[2]_i_18__0_n_0\,
      DI(1) => \stateOp[2]_i_19__0_n_0\,
      DI(0) => \stateOp[2]_i_20__0_n_0\,
      O(7 downto 0) => \NLW_stateOp_reg[2]_i_6_O_UNCONNECTED\(7 downto 0),
      S(7) => \stateOp[2]_i_21__0_n_0\,
      S(6) => \stateOp[2]_i_22__0_n_0\,
      S(5) => \stateOp[2]_i_23__0_n_0\,
      S(4) => \stateOp[2]_i_24__0_n_0\,
      S(3) => \stateOp[2]_i_25__0_n_0\,
      S(2) => \stateOp[2]_i_26__0_n_0\,
      S(1) => \stateOp[2]_i_27__0_n_0\,
      S(0) => \stateOp[2]_i_28__0_n_0\
    );
\stateSeqbufB[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0705"
    )
        port map (
      I0 => stateSeqbufB_reg(2),
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      I3 => dneSeqbufMemtrackToHostif,
      O => \p_0_in__0\(0)
    );
\stateSeqbufB[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00BC"
    )
        port map (
      I0 => \stateSeqbufB[1]_i_2__0_n_0\,
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      I3 => stateSeqbufB_reg(2),
      O => \p_0_in__0\(1)
    );
\stateSeqbufB[1]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAAAAAA"
    )
        port map (
      I0 => seqbufMemtrackToHostifAXIS_tready,
      I1 => \aSeqbufB_reg_n_0_[7]\,
      I2 => \aSeqbufB_reg_n_0_[6]\,
      I3 => \aSeqbufB[8]_i_4__0_n_0\,
      I4 => \aSeqbufB_reg_n_0_[8]\,
      O => \stateSeqbufB[1]_i_2__0_n_0\
    );
\stateSeqbufB[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBABBABBBBABB"
    )
        port map (
      I0 => \stateSeqbufB[2]_i_3__0_n_0\,
      I1 => stateSeqbufB_reg(2),
      I2 => reqSeqbufMemtrackToHostif,
      I3 => stateSeqbufB_reg(0),
      I4 => stateSeqbufB_reg(1),
      I5 => seqbufMemtrackToHostifAXIS_tready,
      O => \stateSeqbufB[2]_i_1__0_n_0\
    );
\stateSeqbufB[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00800F0000800000"
    )
        port map (
      I0 => \stateSeqbufB[2]_i_6_n_0\,
      I1 => seqbufMemtrackToHostifAXIS_tready,
      I2 => stateSeqbufB_reg(1),
      I3 => stateSeqbufB_reg(2),
      I4 => stateSeqbufB_reg(0),
      I5 => dneSeqbufMemtrackToHostif,
      O => \p_0_in__0\(2)
    );
\stateSeqbufB[2]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000C088CC"
    )
        port map (
      I0 => dneSeqbufMemtrackToHostif,
      I1 => stateSeqbufB_reg(2),
      I2 => ackSeqbufBToSeqClear,
      I3 => reqSeqbufMemtrackToHostif,
      I4 => stateSeqbufB_reg(0),
      I5 => stateSeqbufB_reg(1),
      O => \stateSeqbufB[2]_i_3__0_n_0\
    );
\stateSeqbufB[2]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[8]\,
      I1 => \aSeqbufB[8]_i_4__0_n_0\,
      I2 => \aSeqbufB_reg_n_0_[6]\,
      I3 => \aSeqbufB_reg_n_0_[7]\,
      O => \stateSeqbufB[2]_i_6_n_0\
    );
\stateSeqbufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSeqbufB[2]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \p_0_in__0\(0),
      Q => stateSeqbufB_reg(0)
    );
\stateSeqbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSeqbufB[2]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \p_0_in__0\(1),
      Q => stateSeqbufB_reg(1)
    );
\stateSeqbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSeqbufB[2]_i_1__0_n_0\,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \p_0_in__0\(2),
      Q => stateSeqbufB_reg(2)
    );
stoFallingNotRising_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => D(1),
      I1 => D(3),
      I2 => D(5),
      I3 => D(7),
      I4 => stoFallingNotRising_i_2_n_0,
      O => stoFallingNotRising_i_1_n_0
    );
stoFallingNotRising_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => D(2),
      I1 => D(0),
      I2 => D(6),
      I3 => D(4),
      O => stoFallingNotRising_i_2_n_0
    );
stoFallingNotRising_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => stoFallingNotRising_i_1_n_0,
      Q => stoFallingNotRising
    );
\stoTixVTrigger_i[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5755"
    )
        port map (
      I0 => stoTixVTrigger_i,
      I1 => \stoTixVTrigger_to_memclk[7]_i_2_n_0\,
      I2 => \stoTixVTrigger_to_memclk[7]_i_3_n_0\,
      I3 => \stoTixVTrigger_to_memclk[7]_i_4_n_0\,
      O => \stoTixVTrigger_i[0]_i_1_n_0\
    );
\stoTixVTrigger_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \stoTixVTrigger_i[0]_i_1_n_0\,
      Q => stoTixVTrigger_i
    );
\stoTixVTrigger_memclk[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000000000"
    )
        port map (
      I0 => stoTixVTrigger_to_memclkm2(7),
      I1 => stoTixVTrigger_to_memclkm1(7),
      I2 => stoTixVTrigger_to_memclkm2(6),
      I3 => stoTixVTrigger_to_memclkm1(6),
      I4 => \stoTixVTrigger_memclk[7]_i_2_n_0\,
      I5 => \stoTixVTrigger_memclk[7]_i_3_n_0\,
      O => stoTixVTrigger_memclk0
    );
\stoTixVTrigger_memclk[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => stoTixVTrigger_to_memclkm1(3),
      I1 => stoTixVTrigger_to_memclkm2(3),
      I2 => stoTixVTrigger_to_memclkm2(5),
      I3 => stoTixVTrigger_to_memclkm1(5),
      I4 => stoTixVTrigger_to_memclkm2(4),
      I5 => stoTixVTrigger_to_memclkm1(4),
      O => \stoTixVTrigger_memclk[7]_i_2_n_0\
    );
\stoTixVTrigger_memclk[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => stoTixVTrigger_to_memclkm1(0),
      I1 => stoTixVTrigger_to_memclkm2(0),
      I2 => stoTixVTrigger_to_memclkm2(2),
      I3 => stoTixVTrigger_to_memclkm1(2),
      I4 => stoTixVTrigger_to_memclkm2(1),
      I5 => stoTixVTrigger_to_memclkm1(1),
      O => \stoTixVTrigger_memclk[7]_i_3_n_0\
    );
\stoTixVTrigger_memclk_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => stoTixVTrigger_memclk0,
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm2(0),
      Q => stoTixVTrigger_memclk(0)
    );
\stoTixVTrigger_memclk_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => stoTixVTrigger_memclk0,
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm2(1),
      Q => stoTixVTrigger_memclk(1)
    );
\stoTixVTrigger_memclk_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => stoTixVTrigger_memclk0,
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm2(2),
      Q => \stoTixVTrigger_memclk__0\(2)
    );
\stoTixVTrigger_memclk_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => stoTixVTrigger_memclk0,
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm2(3),
      Q => \stoTixVTrigger_memclk__0\(3)
    );
\stoTixVTrigger_memclk_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => stoTixVTrigger_memclk0,
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm2(4),
      Q => \stoTixVTrigger_memclk__0\(4)
    );
\stoTixVTrigger_memclk_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => stoTixVTrigger_memclk0,
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm2(5),
      Q => \stoTixVTrigger_memclk__0\(5)
    );
\stoTixVTrigger_memclk_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => stoTixVTrigger_memclk0,
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm2(6),
      Q => \stoTixVTrigger_memclk__0\(6)
    );
\stoTixVTrigger_memclk_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => stoTixVTrigger_memclk0,
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm2(7),
      Q => \stoTixVTrigger_memclk__0\(7)
    );
\stoTixVTrigger_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(8),
      Q => stoTixVTrigger(0)
    );
\stoTixVTrigger_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(9),
      Q => stoTixVTrigger(1)
    );
\stoTixVTrigger_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(10),
      Q => stoTixVTrigger(2)
    );
\stoTixVTrigger_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(11),
      Q => stoTixVTrigger(3)
    );
\stoTixVTrigger_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(12),
      Q => stoTixVTrigger(4)
    );
\stoTixVTrigger_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(13),
      Q => stoTixVTrigger(5)
    );
\stoTixVTrigger_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(14),
      Q => stoTixVTrigger(6)
    );
\stoTixVTrigger_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => D(15),
      Q => stoTixVTrigger(7)
    );
\stoTixVTrigger_to_memclk[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A8AA"
    )
        port map (
      I0 => stoTixVTrigger_i,
      I1 => \stoTixVTrigger_to_memclk[7]_i_2_n_0\,
      I2 => \stoTixVTrigger_to_memclk[7]_i_3_n_0\,
      I3 => \stoTixVTrigger_to_memclk[7]_i_4_n_0\,
      O => stoTixVTrigger_to_memclk
    );
\stoTixVTrigger_to_memclk[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \stoTixVTrigger_to_memclk_reg_n_0_[3]\,
      I1 => stoTixVTrigger(3),
      I2 => stoTixVTrigger(5),
      I3 => \stoTixVTrigger_to_memclk_reg_n_0_[5]\,
      I4 => stoTixVTrigger(4),
      I5 => \stoTixVTrigger_to_memclk_reg_n_0_[4]\,
      O => \stoTixVTrigger_to_memclk[7]_i_2_n_0\
    );
\stoTixVTrigger_to_memclk[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \stoTixVTrigger_to_memclk_reg_n_0_[0]\,
      I1 => stoTixVTrigger(0),
      I2 => stoTixVTrigger(1),
      I3 => \stoTixVTrigger_to_memclk_reg_n_0_[1]\,
      I4 => stoTixVTrigger(2),
      I5 => \stoTixVTrigger_to_memclk_reg_n_0_[2]\,
      O => \stoTixVTrigger_to_memclk[7]_i_3_n_0\
    );
\stoTixVTrigger_to_memclk[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \stoTixVTrigger_to_memclk_reg_n_0_[7]\,
      I1 => stoTixVTrigger(7),
      I2 => \stoTixVTrigger_to_memclk_reg_n_0_[6]\,
      I3 => stoTixVTrigger(6),
      O => \stoTixVTrigger_to_memclk[7]_i_4_n_0\
    );
\stoTixVTrigger_to_memclk_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stoTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => stoTixVTrigger(0),
      Q => \stoTixVTrigger_to_memclk_reg_n_0_[0]\
    );
\stoTixVTrigger_to_memclk_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stoTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => stoTixVTrigger(1),
      Q => \stoTixVTrigger_to_memclk_reg_n_0_[1]\
    );
\stoTixVTrigger_to_memclk_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stoTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => stoTixVTrigger(2),
      Q => \stoTixVTrigger_to_memclk_reg_n_0_[2]\
    );
\stoTixVTrigger_to_memclk_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stoTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => stoTixVTrigger(3),
      Q => \stoTixVTrigger_to_memclk_reg_n_0_[3]\
    );
\stoTixVTrigger_to_memclk_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stoTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => stoTixVTrigger(4),
      Q => \stoTixVTrigger_to_memclk_reg_n_0_[4]\
    );
\stoTixVTrigger_to_memclk_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stoTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => stoTixVTrigger(5),
      Q => \stoTixVTrigger_to_memclk_reg_n_0_[5]\
    );
\stoTixVTrigger_to_memclk_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stoTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => stoTixVTrigger(6),
      Q => \stoTixVTrigger_to_memclk_reg_n_0_[6]\
    );
\stoTixVTrigger_to_memclk_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stoTixVTrigger_to_memclk,
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => stoTixVTrigger(7),
      Q => \stoTixVTrigger_to_memclk_reg_n_0_[7]\
    );
\stoTixVTrigger_to_memclkm1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \stoTixVTrigger_to_memclk_reg_n_0_[0]\,
      Q => stoTixVTrigger_to_memclkm1(0)
    );
\stoTixVTrigger_to_memclkm1_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \stoTixVTrigger_to_memclk_reg_n_0_[1]\,
      Q => stoTixVTrigger_to_memclkm1(1)
    );
\stoTixVTrigger_to_memclkm1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \stoTixVTrigger_to_memclk_reg_n_0_[2]\,
      Q => stoTixVTrigger_to_memclkm1(2)
    );
\stoTixVTrigger_to_memclkm1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \stoTixVTrigger_to_memclk_reg_n_0_[3]\,
      Q => stoTixVTrigger_to_memclkm1(3)
    );
\stoTixVTrigger_to_memclkm1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \stoTixVTrigger_to_memclk_reg_n_0_[4]\,
      Q => stoTixVTrigger_to_memclkm1(4)
    );
\stoTixVTrigger_to_memclkm1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \stoTixVTrigger_to_memclk_reg_n_0_[5]\,
      Q => stoTixVTrigger_to_memclkm1(5)
    );
\stoTixVTrigger_to_memclkm1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \stoTixVTrigger_to_memclk_reg_n_0_[6]\,
      Q => stoTixVTrigger_to_memclkm1(6)
    );
\stoTixVTrigger_to_memclkm1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \stoTixVTrigger_to_memclk_reg_n_0_[7]\,
      Q => stoTixVTrigger_to_memclkm1(7)
    );
\stoTixVTrigger_to_memclkm2_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm1(0),
      Q => stoTixVTrigger_to_memclkm2(0)
    );
\stoTixVTrigger_to_memclkm2_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm1(1),
      Q => stoTixVTrigger_to_memclkm2(1)
    );
\stoTixVTrigger_to_memclkm2_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm1(2),
      Q => stoTixVTrigger_to_memclkm2(2)
    );
\stoTixVTrigger_to_memclkm2_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm1(3),
      Q => stoTixVTrigger_to_memclkm2(3)
    );
\stoTixVTrigger_to_memclkm2_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm1(4),
      Q => stoTixVTrigger_to_memclkm2(4)
    );
\stoTixVTrigger_to_memclkm2_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm1(5),
      Q => stoTixVTrigger_to_memclkm2(5)
    );
\stoTixVTrigger_to_memclkm2_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm1(6),
      Q => stoTixVTrigger_to_memclkm2(6)
    );
\stoTixVTrigger_to_memclkm2_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => stoTixVTrigger_to_memclkm1(7),
      Q => stoTixVTrigger_to_memclkm2(7)
    );
\stop_i[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9F0F"
    )
        port map (
      I0 => stop_to_mclk,
      I1 => stop,
      I2 => stop_i(0),
      I3 => stop_i(1),
      O => \stop_i[0]_i_1_n_0\
    );
\stop_i[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9FF0"
    )
        port map (
      I0 => stop_to_mclk,
      I1 => stop,
      I2 => stop_i(0),
      I3 => stop_i(1),
      O => \stop_i[1]_i_1_n_0\
    );
stop_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003808"
    )
        port map (
      I0 => start_reg_0,
      I1 => stoTixVTrigger_memclk(1),
      I2 => stoTixVTrigger_memclk(0),
      I3 => stop_reg_0,
      I4 => stop_i_2_n_0,
      O => stop_i_1_n_0
    );
stop_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \stoTixVTrigger_memclk__0\(6),
      I1 => \stoTixVTrigger_memclk__0\(7),
      I2 => \stoTixVTrigger_memclk__0\(3),
      I3 => \stoTixVTrigger_memclk__0\(2),
      I4 => \stoTixVTrigger_memclk__0\(5),
      I5 => \stoTixVTrigger_memclk__0\(4),
      O => stop_i_2_n_0
    );
\stop_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \stop_i[0]_i_1_n_0\,
      Q => stop_i(0)
    );
\stop_i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => \stop_i[1]_i_1_n_0\,
      Q => stop_i(1)
    );
\stop_lcl_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAAB"
    )
        port map (
      I0 => TCapt,
      I1 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I2 => dneSeq,
      I3 => rdySeq,
      I4 => ackSeqbufBToSeqClear,
      O => \stop_lcl_i_1__0_n_0\
    );
\stop_lcl_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \FSM_onehot_stateSeq[3]_i_2__0_n_0\,
      O => \stop_lcl_i_2__0_n_0\
    );
stop_lcl_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => \stop_lcl_i_1__0_n_0\,
      CLR => AR(0),
      D => \stop_lcl_i_2__0_n_0\,
      Q => stop_lcl_reg_n_0
    );
stop_mclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => stop_to_mclkm2,
      I1 => stop_to_mclkm1,
      I2 => stop_mclk,
      O => stop_mclk_i_1_n_0
    );
stop_mclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => stop_mclk_i_1_n_0,
      Q => stop_mclk
    );
stop_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => stop_i_1_n_0,
      Q => stop
    );
stop_to_mclk_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E4CC"
    )
        port map (
      I0 => stop_i(1),
      I1 => stop_to_mclk,
      I2 => stop,
      I3 => stop_i(0),
      O => stop_to_mclk_i_1_n_0
    );
stop_to_mclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => stop_to_mclk_i_1_n_0,
      Q => stop_to_mclk
    );
stop_to_mclkm1_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => stop_to_mclk,
      Q => stop_to_mclkm1
    );
stop_to_mclkm2_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => stop_to_mclkm1,
      Q => stop_to_mclkm2
    );
\strbStart_i[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(0),
      I2 => stateOp(1),
      O => \strbStart_i[0]_i_1_n_0\
    );
\strbStart_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \strbStart_i[0]_i_1_n_0\,
      Q => strbStart_i
    );
strbStart_memclk_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => strbStart_memclk_reg_n_0,
      I1 => strbStart_to_memclkm2,
      I2 => strbStart_to_memclkm1,
      I3 => strbStart_wait_reg_n_0,
      O => strbStart_memclk_i_1_n_0
    );
strbStart_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => strbStart_memclk_i_1_n_0,
      Q => strbStart_memclk_reg_n_0
    );
strbStart_to_memclk_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"75553000"
    )
        port map (
      I0 => strbStart_i,
      I1 => stateOp(2),
      I2 => stateOp(0),
      I3 => stateOp(1),
      I4 => strbStart_to_memclk,
      O => strbStart_to_memclk_i_1_n_0
    );
strbStart_to_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => strbStart_to_memclk_i_1_n_0,
      Q => strbStart_to_memclk
    );
strbStart_to_memclkm1_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => strbStart_to_memclk,
      Q => strbStart_to_memclkm1
    );
strbStart_to_memclkm2_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => strbStart_to_memclkm1,
      Q => strbStart_to_memclkm2
    );
strbStart_wait_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BAA0"
    )
        port map (
      I0 => strbStart_wait_reg_n_0,
      I1 => strbStart_memclk_reg_n_0,
      I2 => strbStart_to_memclkm1,
      I3 => strbStart_to_memclkm2,
      O => strbStart_wait13_out
    );
strbStart_wait_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => strbStart_wait13_out,
      Q => strbStart_wait_reg_n_0
    );
\strbStop_i[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => strbStop_reg_n_0,
      O => \strbStop_i[0]_i_1_n_0\
    );
\strbStop_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAFFAABAAA00"
    )
        port map (
      I0 => \ackInvSet_sig_i_2__0_n_0\,
      I1 => \strbStop_i_2__0_n_0\,
      I2 => \stateOp[2]_i_3__0_n_0\,
      I3 => \^stateop_reg[2]_0\,
      I4 => \strbStop_i_3__0_n_0\,
      I5 => strbStop_reg_n_0,
      O => \strbStop_i_1__0_n_0\
    );
\strbStop_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(1),
      I2 => stateOp(2),
      O => \strbStop_i_2__0_n_0\
    );
\strbStop_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000E0EA"
    )
        port map (
      I0 => stateOp(0),
      I1 => \stateOp[2]_i_3__0_n_0\,
      I2 => stateOp(2),
      I3 => restart_reg_0,
      I4 => stateOp(1),
      O => \strbStop_i_3__0_n_0\
    );
\strbStop_i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \strbStop_i[0]_i_1_n_0\,
      Q => strbStop_i
    );
strbStop_memclk_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => strbStop_memclk_reg_n_0,
      I1 => strbStop_to_memclkm1,
      I2 => strbStop_to_memclkm2,
      I3 => strbStop_wait_reg_n_0,
      O => strbStop_memclk_i_1_n_0
    );
strbStop_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => strbStop_memclk_i_1_n_0,
      Q => strbStop_memclk_reg_n_0
    );
strbStop_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => \strbStop_i_1__0_n_0\,
      Q => strbStop_reg_n_0
    );
strbStop_to_memclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => strbStop_reg_n_0,
      I1 => strbStop_i,
      I2 => strbStop_to_memclk,
      O => strbStop_to_memclk_i_1_n_0
    );
strbStop_to_memclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => strbStop_to_memclk_i_1_n_0,
      Q => strbStop_to_memclk
    );
strbStop_to_memclkm1_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => strbStop_to_memclk,
      Q => strbStop_to_memclkm1
    );
strbStop_to_memclkm2_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => strbStop_to_memclkm1,
      Q => strbStop_to_memclkm2
    );
strbStop_wait_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BAA0"
    )
        port map (
      I0 => strbStop_wait_reg_n_0,
      I1 => strbStop_memclk_reg_n_0,
      I2 => strbStop_to_memclkm2,
      I3 => strbStop_to_memclkm1,
      O => strbStop_wait17_out
    );
strbStop_wait_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => AR(0),
      D => strbStop_wait17_out,
      Q => strbStop_wait_reg_n_0
    );
strb_last_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFBBFFBBA0880088"
    )
        port map (
      I0 => strb_last_i_2_n_0,
      I1 => strb_last_i_3_n_0,
      I2 => strb_last_reg_0,
      I3 => \^stateop_reg[2]_0\,
      I4 => \^rng_reg_0\,
      I5 => strb_last_reg_n_0,
      O => strb_last_i_1_n_0
    );
strb_last_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAAAE0000AAA2"
    )
        port map (
      I0 => stop_mclk,
      I1 => stateOp(1),
      I2 => stateOp(2),
      I3 => stateOp(0),
      I4 => \^stateop_reg[2]_0\,
      I5 => start_mclk,
      O => strb_last_i_2_n_0
    );
strb_last_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E003E0"
    )
        port map (
      I0 => \stateOp[2]_i_10__0_n_0\,
      I1 => stateOp(0),
      I2 => stateOp(1),
      I3 => stateOp(2),
      I4 => \stateOp[2]_i_3__0_n_0\,
      O => strb_last_i_3_n_0
    );
strb_last_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0),
      D => strb_last_i_1_n_0,
      Q => strb_last_reg_n_0
    );
\txAXIS_tdata[15]_i_20\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => stateSeqbufB_reg(2),
      I1 => stateSeqbufB_reg(0),
      I2 => stateSeqbufB_reg(1),
      O => seqbufMemtrackToHostifAXIS_tvalid
    );
\wordcntLast[28]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"34"
    )
        port map (
      I0 => stateSeqbufB_reg(0),
      I1 => stateSeqbufB_reg(2),
      I2 => stateSeqbufB_reg(1),
      O => ackSeqbufMemtrackToHostif
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Trace is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    stateOp_reg_0 : out STD_LOGIC;
    ackInvTraceConfig : out STD_LOGIC;
    ackInvTraceAcquire : out STD_LOGIC;
    traceGetInfoTixVState : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ackFlgbufTraceToHostif : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    stateOp5_out : in STD_LOGIC;
    \tixVState_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    ackInvConfig_sig : in STD_LOGIC;
    ackInvAcquire_sig3_out : in STD_LOGIC;
    reqInvTraceConfig : in STD_LOGIC;
    reqInvTraceAcquire : in STD_LOGIC;
    flgbufTraceToHostifAXIS_tready : in STD_LOGIC;
    dneFlgbufTraceToHostif : in STD_LOGIC;
    reqFlgbufTraceToHostif : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Trace : entity is "Trace";
end design_1_Vsp_core_0_0_Trace;

architecture STRUCTURE of design_1_Vsp_core_0_0_Trace is
  signal \FSM_onehot_stateFlgbufB[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateFlgbufB[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateFlgbufB[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateFlgbufB[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateFlgbufB[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateFlgbufB[5]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateFlgbufB_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_stateFlgbufB_reg_n_0_[2]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \aFlgbufB[0]_i_1_n_0\ : STD_LOGIC;
  signal \aFlgbufB[10]_i_1_n_0\ : STD_LOGIC;
  signal \aFlgbufB[11]_i_1_n_0\ : STD_LOGIC;
  signal \aFlgbufB[12]_i_1_n_0\ : STD_LOGIC;
  signal \aFlgbufB[12]_i_2_n_0\ : STD_LOGIC;
  signal \aFlgbufB[12]_i_3_n_0\ : STD_LOGIC;
  signal \aFlgbufB[1]_i_1_n_0\ : STD_LOGIC;
  signal \aFlgbufB[2]_i_1_n_0\ : STD_LOGIC;
  signal \aFlgbufB[3]_i_1_n_0\ : STD_LOGIC;
  signal \aFlgbufB[4]_i_1_n_0\ : STD_LOGIC;
  signal \aFlgbufB[5]_i_1_n_0\ : STD_LOGIC;
  signal \aFlgbufB[5]_i_2_n_0\ : STD_LOGIC;
  signal \aFlgbufB[6]_i_1_n_0\ : STD_LOGIC;
  signal \aFlgbufB[7]_i_1_n_0\ : STD_LOGIC;
  signal \aFlgbufB[8]_i_1_n_0\ : STD_LOGIC;
  signal \aFlgbufB[9]_i_1_n_0\ : STD_LOGIC;
  signal \aFlgbufB[9]_i_2_n_0\ : STD_LOGIC;
  signal \aFlgbufB_reg_n_0_[0]\ : STD_LOGIC;
  signal \aFlgbufB_reg_n_0_[10]\ : STD_LOGIC;
  signal \aFlgbufB_reg_n_0_[11]\ : STD_LOGIC;
  signal \aFlgbufB_reg_n_0_[12]\ : STD_LOGIC;
  signal \aFlgbufB_reg_n_0_[1]\ : STD_LOGIC;
  signal \aFlgbufB_reg_n_0_[2]\ : STD_LOGIC;
  signal \aFlgbufB_reg_n_0_[3]\ : STD_LOGIC;
  signal \aFlgbufB_reg_n_0_[4]\ : STD_LOGIC;
  signal \aFlgbufB_reg_n_0_[5]\ : STD_LOGIC;
  signal \aFlgbufB_reg_n_0_[6]\ : STD_LOGIC;
  signal \aFlgbufB_reg_n_0_[7]\ : STD_LOGIC;
  signal \aFlgbufB_reg_n_0_[8]\ : STD_LOGIC;
  signal \aFlgbufB_reg_n_0_[9]\ : STD_LOGIC;
  signal \^ackinvtraceacquire\ : STD_LOGIC;
  signal \^ackinvtraceconfig\ : STD_LOGIC;
  signal enFlgbufB : STD_LOGIC;
  signal stateOp : STD_LOGIC;
  signal \^stateop_reg_0\ : STD_LOGIC;
  signal \tixVState[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \^tracegetinfotixvstate\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_stateFlgbufB[2]_i_1\ : label is "soft_lutpair2891";
  attribute SOFT_HLUTNM of \FSM_onehot_stateFlgbufB[3]_i_1\ : label is "soft_lutpair2891";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateFlgbufB_reg[0]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateFlgbufB_reg[1]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateFlgbufB_reg[2]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateFlgbufB_reg[3]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateFlgbufB_reg[5]\ : label is "iSTATE:100000,iSTATE0:000010,iSTATE1:001000,iSTATE2:000100,iSTATE3:000001,iSTATE4:010000";
  attribute SOFT_HLUTNM of \aFlgbufB[10]_i_1\ : label is "soft_lutpair2890";
  attribute SOFT_HLUTNM of \aFlgbufB[11]_i_1\ : label is "soft_lutpair2890";
  attribute SOFT_HLUTNM of \aFlgbufB[12]_i_3\ : label is "soft_lutpair2892";
  attribute SOFT_HLUTNM of \aFlgbufB[1]_i_1\ : label is "soft_lutpair2893";
  attribute SOFT_HLUTNM of \aFlgbufB[2]_i_1\ : label is "soft_lutpair2888";
  attribute SOFT_HLUTNM of \aFlgbufB[3]_i_1\ : label is "soft_lutpair2888";
  attribute SOFT_HLUTNM of \aFlgbufB[5]_i_1\ : label is "soft_lutpair2893";
  attribute SOFT_HLUTNM of \aFlgbufB[6]_i_1\ : label is "soft_lutpair2892";
  attribute SOFT_HLUTNM of \aFlgbufB[7]_i_1\ : label is "soft_lutpair2889";
  attribute SOFT_HLUTNM of \aFlgbufB[8]_i_1\ : label is "soft_lutpair2889";
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
  ackInvTraceAcquire <= \^ackinvtraceacquire\;
  ackInvTraceConfig <= \^ackinvtraceconfig\;
  stateOp_reg_0 <= \^stateop_reg_0\;
  traceGetInfoTixVState(0) <= \^tracegetinfotixvstate\(0);
\FSM_onehot_stateFlgbufB[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000100010001FF01"
    )
        port map (
      I0 => enFlgbufB,
      I1 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => reqFlgbufTraceToHostif,
      I5 => flgbufTraceToHostifAXIS_tready,
      O => \FSM_onehot_stateFlgbufB[0]_i_1_n_0\
    );
\FSM_onehot_stateFlgbufB[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => flgbufTraceToHostifAXIS_tready,
      I1 => \^q\(0),
      I2 => \FSM_onehot_stateFlgbufB[3]_i_2_n_0\,
      O => \FSM_onehot_stateFlgbufB[2]_i_1_n_0\
    );
\FSM_onehot_stateFlgbufB[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF80"
    )
        port map (
      I0 => \^q\(0),
      I1 => flgbufTraceToHostifAXIS_tready,
      I2 => \FSM_onehot_stateFlgbufB[3]_i_2_n_0\,
      I3 => \^q\(1),
      O => \FSM_onehot_stateFlgbufB[3]_i_1_n_0\
    );
\FSM_onehot_stateFlgbufB[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[11]\,
      I1 => \aFlgbufB_reg_n_0_[12]\,
      I2 => \aFlgbufB_reg_n_0_[8]\,
      I3 => \aFlgbufB_reg_n_0_[10]\,
      I4 => \aFlgbufB[12]_i_3_n_0\,
      O => \FSM_onehot_stateFlgbufB[3]_i_2_n_0\
    );
\FSM_onehot_stateFlgbufB[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF8"
    )
        port map (
      I0 => \^q\(0),
      I1 => flgbufTraceToHostifAXIS_tready,
      I2 => enFlgbufB,
      I3 => \FSM_onehot_stateFlgbufB[5]_i_3_n_0\,
      O => \FSM_onehot_stateFlgbufB[5]_i_1_n_0\
    );
\FSM_onehot_stateFlgbufB[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAEAFFFFEAEAFFC0"
    )
        port map (
      I0 => \^q\(1),
      I1 => dneFlgbufTraceToHostif,
      I2 => \FSM_onehot_stateFlgbufB_reg_n_0_[2]\,
      I3 => \^q\(0),
      I4 => reqFlgbufTraceToHostif,
      I5 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \FSM_onehot_stateFlgbufB[5]_i_3_n_0\
    );
\FSM_onehot_stateFlgbufB_reg[0]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateFlgbufB[5]_i_1_n_0\,
      D => \FSM_onehot_stateFlgbufB[0]_i_1_n_0\,
      PRE => \tixVState_reg[0]_0\(0),
      Q => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\
    );
\FSM_onehot_stateFlgbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateFlgbufB[5]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => enFlgbufB,
      Q => \^q\(0)
    );
\FSM_onehot_stateFlgbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateFlgbufB[5]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \FSM_onehot_stateFlgbufB[2]_i_1_n_0\,
      Q => \FSM_onehot_stateFlgbufB_reg_n_0_[2]\
    );
\FSM_onehot_stateFlgbufB_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateFlgbufB[5]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \FSM_onehot_stateFlgbufB[3]_i_1_n_0\,
      Q => enFlgbufB
    );
\FSM_onehot_stateFlgbufB_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateFlgbufB[5]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      Q => \^q\(1)
    );
\aFlgbufB[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[0]\,
      I1 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \aFlgbufB[0]_i_1_n_0\
    );
\aFlgbufB[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A6"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[10]\,
      I1 => \aFlgbufB_reg_n_0_[8]\,
      I2 => \aFlgbufB[12]_i_3_n_0\,
      I3 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \aFlgbufB[10]_i_1_n_0\
    );
\aFlgbufB[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AA6A"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[11]\,
      I1 => \aFlgbufB_reg_n_0_[10]\,
      I2 => \aFlgbufB_reg_n_0_[8]\,
      I3 => \aFlgbufB[12]_i_3_n_0\,
      I4 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \aFlgbufB[11]_i_1_n_0\
    );
\aFlgbufB[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF80"
    )
        port map (
      I0 => \^q\(0),
      I1 => flgbufTraceToHostifAXIS_tready,
      I2 => \FSM_onehot_stateFlgbufB[3]_i_2_n_0\,
      I3 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \aFlgbufB[12]_i_1_n_0\
    );
\aFlgbufB[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAA6AAA"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[12]\,
      I1 => \aFlgbufB_reg_n_0_[8]\,
      I2 => \aFlgbufB_reg_n_0_[10]\,
      I3 => \aFlgbufB_reg_n_0_[11]\,
      I4 => \aFlgbufB[12]_i_3_n_0\,
      I5 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \aFlgbufB[12]_i_2_n_0\
    );
\aFlgbufB[12]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[7]\,
      I1 => \aFlgbufB[9]_i_2_n_0\,
      I2 => \aFlgbufB_reg_n_0_[6]\,
      I3 => \aFlgbufB_reg_n_0_[9]\,
      O => \aFlgbufB[12]_i_3_n_0\
    );
\aFlgbufB[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[1]\,
      I1 => \aFlgbufB_reg_n_0_[0]\,
      I2 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \aFlgbufB[1]_i_1_n_0\
    );
\aFlgbufB[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[2]\,
      I1 => \aFlgbufB_reg_n_0_[0]\,
      I2 => \aFlgbufB_reg_n_0_[1]\,
      I3 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \aFlgbufB[2]_i_1_n_0\
    );
\aFlgbufB[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[3]\,
      I1 => \aFlgbufB_reg_n_0_[1]\,
      I2 => \aFlgbufB_reg_n_0_[0]\,
      I3 => \aFlgbufB_reg_n_0_[2]\,
      I4 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \aFlgbufB[3]_i_1_n_0\
    );
\aFlgbufB[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000006AAAAAAA"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[4]\,
      I1 => \aFlgbufB_reg_n_0_[2]\,
      I2 => \aFlgbufB_reg_n_0_[0]\,
      I3 => \aFlgbufB_reg_n_0_[1]\,
      I4 => \aFlgbufB_reg_n_0_[3]\,
      I5 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \aFlgbufB[4]_i_1_n_0\
    );
\aFlgbufB[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"09"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[5]\,
      I1 => \aFlgbufB[5]_i_2_n_0\,
      I2 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \aFlgbufB[5]_i_1_n_0\
    );
\aFlgbufB[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[3]\,
      I1 => \aFlgbufB_reg_n_0_[1]\,
      I2 => \aFlgbufB_reg_n_0_[0]\,
      I3 => \aFlgbufB_reg_n_0_[2]\,
      I4 => \aFlgbufB_reg_n_0_[4]\,
      O => \aFlgbufB[5]_i_2_n_0\
    );
\aFlgbufB[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"09"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[6]\,
      I1 => \aFlgbufB[9]_i_2_n_0\,
      I2 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \aFlgbufB[6]_i_1_n_0\
    );
\aFlgbufB[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"009A"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[7]\,
      I1 => \aFlgbufB[9]_i_2_n_0\,
      I2 => \aFlgbufB_reg_n_0_[6]\,
      I3 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \aFlgbufB[7]_i_1_n_0\
    );
\aFlgbufB[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000A6AA"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[8]\,
      I1 => \aFlgbufB_reg_n_0_[6]\,
      I2 => \aFlgbufB[9]_i_2_n_0\,
      I3 => \aFlgbufB_reg_n_0_[7]\,
      I4 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \aFlgbufB[8]_i_1_n_0\
    );
\aFlgbufB[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AA6AAAAA"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[9]\,
      I1 => \aFlgbufB_reg_n_0_[8]\,
      I2 => \aFlgbufB_reg_n_0_[7]\,
      I3 => \aFlgbufB[9]_i_2_n_0\,
      I4 => \aFlgbufB_reg_n_0_[6]\,
      I5 => \FSM_onehot_stateFlgbufB_reg_n_0_[0]\,
      O => \aFlgbufB[9]_i_1_n_0\
    );
\aFlgbufB[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \aFlgbufB_reg_n_0_[4]\,
      I1 => \aFlgbufB_reg_n_0_[2]\,
      I2 => \aFlgbufB_reg_n_0_[0]\,
      I3 => \aFlgbufB_reg_n_0_[1]\,
      I4 => \aFlgbufB_reg_n_0_[3]\,
      I5 => \aFlgbufB_reg_n_0_[5]\,
      O => \aFlgbufB[9]_i_2_n_0\
    );
\aFlgbufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aFlgbufB[12]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \aFlgbufB[0]_i_1_n_0\,
      Q => \aFlgbufB_reg_n_0_[0]\
    );
\aFlgbufB_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aFlgbufB[12]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \aFlgbufB[10]_i_1_n_0\,
      Q => \aFlgbufB_reg_n_0_[10]\
    );
\aFlgbufB_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aFlgbufB[12]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \aFlgbufB[11]_i_1_n_0\,
      Q => \aFlgbufB_reg_n_0_[11]\
    );
\aFlgbufB_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aFlgbufB[12]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \aFlgbufB[12]_i_2_n_0\,
      Q => \aFlgbufB_reg_n_0_[12]\
    );
\aFlgbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aFlgbufB[12]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \aFlgbufB[1]_i_1_n_0\,
      Q => \aFlgbufB_reg_n_0_[1]\
    );
\aFlgbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aFlgbufB[12]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \aFlgbufB[2]_i_1_n_0\,
      Q => \aFlgbufB_reg_n_0_[2]\
    );
\aFlgbufB_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aFlgbufB[12]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \aFlgbufB[3]_i_1_n_0\,
      Q => \aFlgbufB_reg_n_0_[3]\
    );
\aFlgbufB_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aFlgbufB[12]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \aFlgbufB[4]_i_1_n_0\,
      Q => \aFlgbufB_reg_n_0_[4]\
    );
\aFlgbufB_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aFlgbufB[12]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \aFlgbufB[5]_i_1_n_0\,
      Q => \aFlgbufB_reg_n_0_[5]\
    );
\aFlgbufB_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aFlgbufB[12]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \aFlgbufB[6]_i_1_n_0\,
      Q => \aFlgbufB_reg_n_0_[6]\
    );
\aFlgbufB_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aFlgbufB[12]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \aFlgbufB[7]_i_1_n_0\,
      Q => \aFlgbufB_reg_n_0_[7]\
    );
\aFlgbufB_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aFlgbufB[12]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \aFlgbufB[8]_i_1_n_0\,
      Q => \aFlgbufB_reg_n_0_[8]\
    );
\aFlgbufB_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aFlgbufB[12]_i_1_n_0\,
      CLR => \tixVState_reg[0]_0\(0),
      D => \aFlgbufB[9]_i_1_n_0\,
      Q => \aFlgbufB_reg_n_0_[9]\
    );
ackInvAcquire_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stateOp,
      CLR => \tixVState_reg[0]_0\(0),
      D => ackInvAcquire_sig3_out,
      Q => \^ackinvtraceacquire\
    );
ackInvConfig_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stateOp,
      CLR => \tixVState_reg[0]_0\(0),
      D => ackInvConfig_sig,
      Q => \^ackinvtraceconfig\
    );
myFlgbuf: entity work.design_1_Vsp_core_0_0_Dpbram_size38kB_a8b64
     port map (
      Q(0) => enFlgbufB,
      aclk_sig => aclk_sig,
      doutb(63 downto 0) => doutb(63 downto 0),
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(12) => \aFlgbufB_reg_n_0_[12]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(11) => \aFlgbufB_reg_n_0_[11]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(10) => \aFlgbufB_reg_n_0_[10]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(9) => \aFlgbufB_reg_n_0_[9]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(8) => \aFlgbufB_reg_n_0_[8]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(7) => \aFlgbufB_reg_n_0_[7]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(6) => \aFlgbufB_reg_n_0_[6]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(5) => \aFlgbufB_reg_n_0_[5]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(4) => \aFlgbufB_reg_n_0_[4]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(3) => \aFlgbufB_reg_n_0_[3]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(2) => \aFlgbufB_reg_n_0_[2]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(1) => \aFlgbufB_reg_n_0_[1]\,
      \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\(0) => \aFlgbufB_reg_n_0_[0]\
    );
\stateOp_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5D5DFF5D"
    )
        port map (
      I0 => \^stateop_reg_0\,
      I1 => \^ackinvtraceconfig\,
      I2 => reqInvTraceConfig,
      I3 => \^ackinvtraceacquire\,
      I4 => reqInvTraceAcquire,
      O => stateOp
    );
stateOp_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stateOp,
      CLR => \tixVState_reg[0]_0\(0),
      D => stateOp5_out,
      Q => \^stateop_reg_0\
    );
\tixVState[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DC"
    )
        port map (
      I0 => \^stateop_reg_0\,
      I1 => \^tracegetinfotixvstate\(0),
      I2 => reqInvTraceAcquire,
      O => \tixVState[0]_i_1__0_n_0\
    );
\tixVState_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => \tixVState_reg[0]_0\(0),
      D => \tixVState[0]_i_1__0_n_0\,
      Q => \^tracegetinfotixvstate\(0)
    );
\wordcntLast[28]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => enFlgbufB,
      I1 => \^q\(0),
      I2 => \FSM_onehot_stateFlgbufB_reg_n_0_[2]\,
      O => ackFlgbufTraceToHostif
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Videoin is
  port (
    rgbVideoinToManyAXIS_tvalid : out STD_LOGIC;
    grayVideoinToManyAXIS_tvalid : out STD_LOGIC;
    grayVideoinToManyAXIS_tlast : out STD_LOGIC;
    rgbToManyAXIS_tlast_sig_reg_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \col_lcl_reg[5]_0\ : out STD_LOGIC;
    \FSM_sequential_stateRgbegr_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \col_lcl_reg[5]_1\ : out STD_LOGIC;
    \klm_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateIgr_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rgbToManyAXIS_tdata_sig_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \rgbToManyAXIS_tdata_sig_reg[35]_0\ : out STD_LOGIC_VECTOR ( 35 downto 0 );
    grayToManyAXIS_tvalid_sig_reg_0 : out STD_LOGIC;
    enAccbuf1 : out STD_LOGIC;
    DI : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \abcde_reg[0]_0\ : out STD_LOGIC_VECTOR ( 39 downto 0 );
    \rgbToManyAXIS_tdata_sig_reg[7]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    O : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \abcde_reg[0]_1\ : out STD_LOGIC_VECTOR ( 44 downto 0 );
    videoinStateIgr_dbg : out STD_LOGIC_VECTOR ( 1 downto 0 );
    videoinStateRgbegr_dbg : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \NColRaw_sig_reg[4]\ : out STD_LOGIC;
    \col_lcl_reg[4]_0\ : out STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    enRowbufB_lcl_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dwrEobuf_reg[63]_0\ : in STD_LOGIC;
    camifToVideoinAXIS_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
    \dwrEobuf_reg[62]_0\ : in STD_LOGIC;
    \dwrEobuf_reg[61]_0\ : in STD_LOGIC;
    \dwrEobuf_reg[60]_0\ : in STD_LOGIC;
    \dwrEobuf_reg[59]_0\ : in STD_LOGIC;
    \dwrEobuf_reg[58]_0\ : in STD_LOGIC;
    \dwrEobuf_reg[57]_0\ : in STD_LOGIC;
    \dwrEobuf_reg[56]_0\ : in STD_LOGIC;
    \dwrEobuf_reg[36]_0\ : in STD_LOGIC;
    enAccbuf_reg : in STD_LOGIC;
    enAccbuf0 : in STD_LOGIC;
    \dwrAccbuf_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \dy_reg[8]\ : in STD_LOGIC;
    oddNotEven_reg_0 : in STD_LOGIC;
    enRowbuf_reg_0 : in STD_LOGIC_VECTOR ( 10 downto 0 );
    enEobufB_reg_0 : in STD_LOGIC;
    camifToVideoinAXIS_tvalid : in STD_LOGIC;
    \dwrEobuf_reg[63]_1\ : in STD_LOGIC;
    camifToVideoinAXIS_tlast : in STD_LOGIC;
    enEobufB_reg_1 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stateIgr_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Videoin : entity is "Videoin";
end design_1_Vsp_core_0_0_Videoin;

architecture STRUCTURE of design_1_Vsp_core_0_0_Videoin is
  signal \FSM_sequential_stateGrayegr[2]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateGrayegr[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateGrayegr[2]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateGrayegr[2]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateGrayegr[2]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateGrayegr[2]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateGrayegr[2]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateGrayegr[2]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateGrayegr[2]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateRgbegr[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_stateRgbegr[2]_i_2_n_0\ : STD_LOGIC;
  signal \^fsm_sequential_statergbegr_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \aEobufB[0]_i_1_n_0\ : STD_LOGIC;
  signal \aEobufB[1]_i_1_n_0\ : STD_LOGIC;
  signal \aEobufB[2]_i_1_n_0\ : STD_LOGIC;
  signal \aEobufB[3]_i_1_n_0\ : STD_LOGIC;
  signal \aEobufB[4]_i_1_n_0\ : STD_LOGIC;
  signal \aEobufB[4]_i_2_n_0\ : STD_LOGIC;
  signal \aEobufB[5]_i_1_n_0\ : STD_LOGIC;
  signal \aEobufB[5]_i_2_n_0\ : STD_LOGIC;
  signal \aEobufB[6]_i_1_n_0\ : STD_LOGIC;
  signal \aEobufB[7]_i_1_n_0\ : STD_LOGIC;
  signal \aEobufB[8]_i_1_n_0\ : STD_LOGIC;
  signal \aEobufB[8]_i_2_n_0\ : STD_LOGIC;
  signal \aEobufB[9]_i_1_n_0\ : STD_LOGIC;
  signal \aEobufB[9]_i_2_n_0\ : STD_LOGIC;
  signal \aEobufB[9]_i_3_n_0\ : STD_LOGIC;
  signal \aEobufB[9]_i_4_n_0\ : STD_LOGIC;
  signal \aEobufB[9]_i_5_n_0\ : STD_LOGIC;
  signal \aEobufB[9]_i_6_n_0\ : STD_LOGIC;
  signal \aEobufB_reg_n_0_[0]\ : STD_LOGIC;
  signal \aEobufB_reg_n_0_[1]\ : STD_LOGIC;
  signal \aEobufB_reg_n_0_[2]\ : STD_LOGIC;
  signal \aEobufB_reg_n_0_[3]\ : STD_LOGIC;
  signal \aEobufB_reg_n_0_[4]\ : STD_LOGIC;
  signal \aEobufB_reg_n_0_[5]\ : STD_LOGIC;
  signal \aEobufB_reg_n_0_[6]\ : STD_LOGIC;
  signal \aEobufB_reg_n_0_[7]\ : STD_LOGIC;
  signal \aEobufB_reg_n_0_[8]\ : STD_LOGIC;
  signal \aEobufB_reg_n_0_[9]\ : STD_LOGIC;
  signal \aEobuf[0]_i_1_n_0\ : STD_LOGIC;
  signal \aEobuf[1]_i_1_n_0\ : STD_LOGIC;
  signal \aEobuf[2]_i_1_n_0\ : STD_LOGIC;
  signal \aEobuf[3]_i_1_n_0\ : STD_LOGIC;
  signal \aEobuf[4]_i_1_n_0\ : STD_LOGIC;
  signal \aEobuf[5]_i_1_n_0\ : STD_LOGIC;
  signal \aEobuf[5]_i_2_n_0\ : STD_LOGIC;
  signal \aEobuf[6]_i_1_n_0\ : STD_LOGIC;
  signal \aEobuf[7]_i_1_n_0\ : STD_LOGIC;
  signal \aEobuf[8]_i_1_n_0\ : STD_LOGIC;
  signal \aEobuf[9]_i_1_n_0\ : STD_LOGIC;
  signal \aEobuf[9]_i_2_n_0\ : STD_LOGIC;
  signal \aEobuf[9]_i_3_n_0\ : STD_LOGIC;
  signal \aEobuf[9]_i_4_n_0\ : STD_LOGIC;
  signal \aEobuf[9]_i_5_n_0\ : STD_LOGIC;
  signal \aEobuf[9]_i_6_n_0\ : STD_LOGIC;
  signal \aEobuf_reg_n_0_[0]\ : STD_LOGIC;
  signal \aEobuf_reg_n_0_[1]\ : STD_LOGIC;
  signal \aEobuf_reg_n_0_[2]\ : STD_LOGIC;
  signal \aEobuf_reg_n_0_[3]\ : STD_LOGIC;
  signal \aEobuf_reg_n_0_[4]\ : STD_LOGIC;
  signal \aEobuf_reg_n_0_[5]\ : STD_LOGIC;
  signal \aEobuf_reg_n_0_[6]\ : STD_LOGIC;
  signal \aEobuf_reg_n_0_[7]\ : STD_LOGIC;
  signal \aEobuf_reg_n_0_[8]\ : STD_LOGIC;
  signal \aEobuf_reg_n_0_[9]\ : STD_LOGIC;
  signal aRowbuf : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \aRowbufB[0]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufB[1]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufB[2]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufB[3]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufB[4]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufB[4]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufB[5]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufB[5]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufB[6]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufB[7]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufB[8]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbufB[8]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbufB[8]_i_3_n_0\ : STD_LOGIC;
  signal \aRowbufB[8]_i_4_n_0\ : STD_LOGIC;
  signal \aRowbufB_reg_n_0_[0]\ : STD_LOGIC;
  signal \aRowbufB_reg_n_0_[1]\ : STD_LOGIC;
  signal \aRowbufB_reg_n_0_[2]\ : STD_LOGIC;
  signal \aRowbufB_reg_n_0_[3]\ : STD_LOGIC;
  signal \aRowbufB_reg_n_0_[4]\ : STD_LOGIC;
  signal \aRowbufB_reg_n_0_[5]\ : STD_LOGIC;
  signal \aRowbufB_reg_n_0_[6]\ : STD_LOGIC;
  signal \aRowbufB_reg_n_0_[7]\ : STD_LOGIC;
  signal \aRowbufB_reg_n_0_[8]\ : STD_LOGIC;
  signal \aRowbuf[1]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbuf[2]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbuf[3]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbuf[4]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbuf[4]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbuf[5]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbuf[5]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbuf[6]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbuf[7]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbuf[8]_i_1_n_0\ : STD_LOGIC;
  signal \aRowbuf[8]_i_2_n_0\ : STD_LOGIC;
  signal \aRowbuf[8]_i_3_n_0\ : STD_LOGIC;
  signal \aRowbuf[8]_i_4_n_0\ : STD_LOGIC;
  signal \aRowbuf[8]_i_5_n_0\ : STD_LOGIC;
  signal \aRowbuf[8]_i_6_n_0\ : STD_LOGIC;
  signal \aRowbuf[8]_i_7_n_0\ : STD_LOGIC;
  signal \aRowbuf_reg_n_0_[0]\ : STD_LOGIC;
  signal \aRowbuf_reg_n_0_[1]\ : STD_LOGIC;
  signal \aRowbuf_reg_n_0_[2]\ : STD_LOGIC;
  signal \aRowbuf_reg_n_0_[3]\ : STD_LOGIC;
  signal \aRowbuf_reg_n_0_[4]\ : STD_LOGIC;
  signal \aRowbuf_reg_n_0_[5]\ : STD_LOGIC;
  signal \aRowbuf_reg_n_0_[6]\ : STD_LOGIC;
  signal \aRowbuf_reg_n_0_[7]\ : STD_LOGIC;
  signal \aRowbuf_reg_n_0_[8]\ : STD_LOGIC;
  signal abcde : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \abcde[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \abcde[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \abcde[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \^abcde_reg[0]_0\ : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal \abcde_reg_n_0_[0]\ : STD_LOGIC;
  signal \abcde_reg_n_0_[1]\ : STD_LOGIC;
  signal \abcde_reg_n_0_[2]\ : STD_LOGIC;
  signal \acc0_lcl_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \acc0_lcl_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \acc0_lcl_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \acc0_lcl_reg[7]_i_2_n_4\ : STD_LOGIC;
  signal \acc0_lcl_reg[7]_i_2_n_5\ : STD_LOGIC;
  signal \acc0_lcl_reg[7]_i_2_n_6\ : STD_LOGIC;
  signal \acc0_lcl_reg[7]_i_2_n_7\ : STD_LOGIC;
  signal col_lcl : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \col_lcl[0]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__0_i_2__0_n_0\ : STD_LOGIC;
  signal \col_lcl[10]__1_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[10]_i_1__1_n_0\ : STD_LOGIC;
  signal \col_lcl[10]_i_2__1_n_0\ : STD_LOGIC;
  signal \col_lcl[1]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \col_lcl[2]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[2]__1_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \col_lcl[3]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[3]__1_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \col_lcl[4]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[4]__1_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[4]__1_i_2_n_0\ : STD_LOGIC;
  signal \col_lcl[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \col_lcl[5]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[5]__0_i_2__0_n_0\ : STD_LOGIC;
  signal \col_lcl[5]__1_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[5]__1_i_2_n_0\ : STD_LOGIC;
  signal \col_lcl[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \col_lcl[6]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[6]__1_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \col_lcl[7]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[7]__1_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \col_lcl[8]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[8]__1_i_2_n_0\ : STD_LOGIC;
  signal \col_lcl[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \col_lcl[9]__0_i_1__0_n_0\ : STD_LOGIC;
  signal \col_lcl[9]__0_i_2__0_n_0\ : STD_LOGIC;
  signal \col_lcl[9]__1_i_1_n_0\ : STD_LOGIC;
  signal \col_lcl[9]__1_i_2_n_0\ : STD_LOGIC;
  signal \col_lcl[9]_i_1__1_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[0]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[0]__1_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[10]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[10]__1_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[1]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[1]__1_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[2]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[2]__1_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[3]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[3]__1_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[4]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[4]__1_n_0\ : STD_LOGIC;
  signal \^col_lcl_reg[5]_0\ : STD_LOGIC;
  signal \^col_lcl_reg[5]_1\ : STD_LOGIC;
  signal \col_lcl_reg[5]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[5]__1_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[6]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[6]__1_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[7]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[7]__1_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[8]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[8]__1_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[9]__0_n_0\ : STD_LOGIC;
  signal \col_lcl_reg[9]__1_n_0\ : STD_LOGIC;
  signal \col_lcl_reg_n_0_[10]\ : STD_LOGIC;
  signal \col_lcl_reg_n_0_[3]\ : STD_LOGIC;
  signal \col_lcl_reg_n_0_[4]\ : STD_LOGIC;
  signal \col_lcl_reg_n_0_[5]\ : STD_LOGIC;
  signal \col_lcl_reg_n_0_[8]\ : STD_LOGIC;
  signal \col_lcl_reg_n_0_[9]\ : STD_LOGIC;
  signal \dIgrm1[16]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[17]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[18]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[19]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[20]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[21]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[22]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[23]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[24]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[24]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[25]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[25]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[26]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[26]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[27]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[27]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[28]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[28]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[29]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[29]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[30]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[30]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[31]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[31]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[32]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[32]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[33]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[33]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[34]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[34]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[35]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[35]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[36]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[36]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[37]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[37]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[38]_i_3_n_0\ : STD_LOGIC;
  signal \dIgrm1[38]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[39]_i_4_n_0\ : STD_LOGIC;
  signal \dIgrm1[39]_i_5_n_0\ : STD_LOGIC;
  signal data10 : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \data10__0\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \data10__1\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \data10__2\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \data10__3\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal data2 : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal drdB : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal drdEvenAbufB : STD_LOGIC_VECTOR ( 63 downto 48 );
  signal drdEvenbufBm1 : STD_LOGIC_VECTOR ( 63 downto 48 );
  signal \drdEvenbufBm1[63]_i_1_n_0\ : STD_LOGIC;
  signal \drdEvenbufBm1_reg_n_0_[60]\ : STD_LOGIC;
  signal \drdEvenbufBm1_reg_n_0_[61]\ : STD_LOGIC;
  signal \drdEvenbufBm1_reg_n_0_[62]\ : STD_LOGIC;
  signal \drdEvenbufBm1_reg_n_0_[63]\ : STD_LOGIC;
  signal drdOddbufBm1 : STD_LOGIC_VECTOR ( 63 downto 48 );
  signal \drdOddbufBm1_reg_n_0_[48]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[49]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[50]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[51]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[52]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[53]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[54]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[55]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[56]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[57]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[58]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[59]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[60]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[61]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[62]\ : STD_LOGIC;
  signal \drdOddbufBm1_reg_n_0_[63]\ : STD_LOGIC;
  signal drdRow0bufBm1 : STD_LOGIC_VECTOR ( 63 downto 60 );
  signal drdRow1bufBm1 : STD_LOGIC_VECTOR ( 63 downto 60 );
  signal drdRow2bufBm1 : STD_LOGIC_VECTOR ( 63 downto 60 );
  signal drdRow3bufBm1 : STD_LOGIC_VECTOR ( 63 downto 60 );
  signal drdRow4bufBm1 : STD_LOGIC_VECTOR ( 63 downto 60 );
  signal \drdRow4bufBm1[63]_i_1_n_0\ : STD_LOGIC;
  signal \drdRow4bufBm1[63]_i_3_n_0\ : STD_LOGIC;
  signal dwrEobuf : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \dwrEobuf[0]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[10]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[10]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[11]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[11]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[12]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[12]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[13]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[13]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[14]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[14]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[15]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[15]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[16]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[17]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[18]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[19]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[1]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[20]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[21]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[22]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[23]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[23]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[24]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[25]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[26]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[27]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[28]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[29]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[2]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[30]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[31]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[31]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[32]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[32]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[33]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[33]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[34]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[34]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[35]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[35]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[36]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[36]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[37]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[37]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[38]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[38]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[39]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[39]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[39]_i_4_n_0\ : STD_LOGIC;
  signal \dwrEobuf[3]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[40]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[41]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[42]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[43]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[44]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[45]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[46]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[47]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[47]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[48]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[48]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[49]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[49]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[4]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[50]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[50]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[51]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[51]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[52]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[52]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[53]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[53]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[54]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[54]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[55]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[55]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[55]_i_3_n_0\ : STD_LOGIC;
  signal \dwrEobuf[56]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[57]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[58]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[59]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[5]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[60]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[61]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[62]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[63]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[63]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[6]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[7]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[8]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[8]_i_2_n_0\ : STD_LOGIC;
  signal \dwrEobuf[9]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobuf[9]_i_2_n_0\ : STD_LOGIC;
  signal dwrEobufp1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal dwrEobufp10_out : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \dwrEobufp1[15]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobufp1[7]_i_1_n_0\ : STD_LOGIC;
  signal \dwrEobufp1[7]_i_4_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[19]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[23]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[27]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[31]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[35]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[39]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[43]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[47]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[48]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[49]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[50]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[51]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[51]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[52]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[53]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[54]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[55]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[55]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[56]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[57]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[58]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[59]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[59]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[60]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[61]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[62]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[63]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[63]_i_2_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrRowbuf[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[0]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[10]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[11]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[12]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[13]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[14]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[15]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[16]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[17]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[18]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[19]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[1]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[20]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[21]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[22]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[23]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[24]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[25]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[26]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[27]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[28]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[29]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[2]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[30]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[31]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[32]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[33]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[34]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[35]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[36]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[37]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[38]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[39]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[3]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[40]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[41]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[42]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[43]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[44]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[45]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[46]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[47]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[48]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[49]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[4]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[50]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[51]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[52]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[53]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[54]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[55]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[56]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[57]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[58]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[59]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[5]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[60]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[61]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[62]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[63]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[6]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[7]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[8]\ : STD_LOGIC;
  signal \dwrRowbuf_reg_n_0_[9]\ : STD_LOGIC;
  signal dwrRowbufp1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal dwrRowbufp10_out : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \dwrRowbufp1[3]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbufp1[3]_i_3_n_0\ : STD_LOGIC;
  signal \dwrRowbufp1[7]_i_1_n_0\ : STD_LOGIC;
  signal \dwrRowbufp1[7]_i_3_n_0\ : STD_LOGIC;
  signal \dwrRowbufp1[7]_i_4_n_0\ : STD_LOGIC;
  signal \dy[11]_i_2_n_0\ : STD_LOGIC;
  signal \dy[13]_i_2_n_0\ : STD_LOGIC;
  signal \dy[15]_i_2_n_0\ : STD_LOGIC;
  signal \dy[17]_i_2_n_0\ : STD_LOGIC;
  signal \dy[20]_i_2_n_0\ : STD_LOGIC;
  signal \dy[22]_i_2_n_0\ : STD_LOGIC;
  signal \dy[24]_i_2_n_0\ : STD_LOGIC;
  signal \dy[26]_i_2_n_0\ : STD_LOGIC;
  signal \dy[29]_i_2_n_0\ : STD_LOGIC;
  signal \dy[2]_i_2_n_0\ : STD_LOGIC;
  signal \dy[31]_i_2_n_0\ : STD_LOGIC;
  signal \dy[33]_i_2_n_0\ : STD_LOGIC;
  signal \dy[35]_i_2_n_0\ : STD_LOGIC;
  signal \dy[38]_i_3_n_0\ : STD_LOGIC;
  signal \dy[40]_i_4_n_0\ : STD_LOGIC;
  signal \dy[42]_i_4_n_0\ : STD_LOGIC;
  signal \dy[44]_i_3_n_0\ : STD_LOGIC;
  signal \dy[4]_i_2_n_0\ : STD_LOGIC;
  signal \dy[6]_i_2_n_0\ : STD_LOGIC;
  signal \dy[8]_i_2_n_0\ : STD_LOGIC;
  signal enEobuf : STD_LOGIC;
  signal enEobufB : STD_LOGIC;
  signal enEobufB_i_1_n_0 : STD_LOGIC;
  signal enEobufB_i_2_n_0 : STD_LOGIC;
  signal enEobufB_i_4_n_0 : STD_LOGIC;
  signal enEobufB_i_5_n_0 : STD_LOGIC;
  signal enEobufB_i_6_n_0 : STD_LOGIC;
  signal enEobufB_lcl : STD_LOGIC;
  signal enEobufB_lcl_reg_n_0 : STD_LOGIC;
  signal enEobuf_i_1_n_0 : STD_LOGIC;
  signal enRowbuf : STD_LOGIC;
  signal enRowbufB_i_1_n_0 : STD_LOGIC;
  signal enRowbufB_i_2_n_0 : STD_LOGIC;
  signal enRowbufB_i_3_n_0 : STD_LOGIC;
  signal enRowbufB_i_4_n_0 : STD_LOGIC;
  signal enRowbufB_lcl_i_1_n_0 : STD_LOGIC;
  signal enRowbufB_lcl_i_2_n_0 : STD_LOGIC;
  signal enRowbufB_lcl_reg_n_0 : STD_LOGIC;
  signal enRowbufB_reg_n_0 : STD_LOGIC;
  signal enRowbuf_i_2_n_0 : STD_LOGIC;
  signal enRowbuf_i_3_n_0 : STD_LOGIC;
  signal enRowbuf_i_4_n_0 : STD_LOGIC;
  signal enRowbuf_i_5_n_0 : STD_LOGIC;
  signal enRowbuf_reg_n_0 : STD_LOGIC;
  signal fillBNotA_i_1_n_0 : STD_LOGIC;
  signal fillBNotA_reg_n_0 : STD_LOGIC;
  signal gr : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \gr0_reg_n_0_[10]\ : STD_LOGIC;
  signal \gr0_reg_n_0_[11]\ : STD_LOGIC;
  signal \gr0_reg_n_0_[4]\ : STD_LOGIC;
  signal \gr0_reg_n_0_[5]\ : STD_LOGIC;
  signal \gr0_reg_n_0_[6]\ : STD_LOGIC;
  signal \gr0_reg_n_0_[7]\ : STD_LOGIC;
  signal \gr0_reg_n_0_[8]\ : STD_LOGIC;
  signal \gr0_reg_n_0_[9]\ : STD_LOGIC;
  signal gr1 : STD_LOGIC_VECTOR ( 11 downto 4 );
  signal \gr1_reg_n_0_[10]\ : STD_LOGIC;
  signal \gr1_reg_n_0_[11]\ : STD_LOGIC;
  signal \gr1_reg_n_0_[4]\ : STD_LOGIC;
  signal \gr1_reg_n_0_[5]\ : STD_LOGIC;
  signal \gr1_reg_n_0_[6]\ : STD_LOGIC;
  signal \gr1_reg_n_0_[7]\ : STD_LOGIC;
  signal \gr1_reg_n_0_[8]\ : STD_LOGIC;
  signal \gr1_reg_n_0_[9]\ : STD_LOGIC;
  signal gr2 : STD_LOGIC_VECTOR ( 11 downto 4 );
  signal \gr2_reg_n_0_[10]\ : STD_LOGIC;
  signal \gr2_reg_n_0_[11]\ : STD_LOGIC;
  signal \gr2_reg_n_0_[4]\ : STD_LOGIC;
  signal \gr2_reg_n_0_[5]\ : STD_LOGIC;
  signal \gr2_reg_n_0_[6]\ : STD_LOGIC;
  signal \gr2_reg_n_0_[7]\ : STD_LOGIC;
  signal \gr2_reg_n_0_[8]\ : STD_LOGIC;
  signal \gr2_reg_n_0_[9]\ : STD_LOGIC;
  signal gr3 : STD_LOGIC_VECTOR ( 11 downto 4 );
  signal \gr3_reg_n_0_[10]\ : STD_LOGIC;
  signal \gr3_reg_n_0_[11]\ : STD_LOGIC;
  signal \gr3_reg_n_0_[4]\ : STD_LOGIC;
  signal \gr3_reg_n_0_[5]\ : STD_LOGIC;
  signal \gr3_reg_n_0_[6]\ : STD_LOGIC;
  signal \gr3_reg_n_0_[7]\ : STD_LOGIC;
  signal \gr3_reg_n_0_[8]\ : STD_LOGIC;
  signal \gr3_reg_n_0_[9]\ : STD_LOGIC;
  signal gr4 : STD_LOGIC_VECTOR ( 11 downto 4 );
  signal \gr4[11]_i_1_n_0\ : STD_LOGIC;
  signal \gr4_reg_n_0_[10]\ : STD_LOGIC;
  signal \gr4_reg_n_0_[11]\ : STD_LOGIC;
  signal \gr4_reg_n_0_[4]\ : STD_LOGIC;
  signal \gr4_reg_n_0_[5]\ : STD_LOGIC;
  signal \gr4_reg_n_0_[6]\ : STD_LOGIC;
  signal \gr4_reg_n_0_[7]\ : STD_LOGIC;
  signal \gr4_reg_n_0_[8]\ : STD_LOGIC;
  signal \gr4_reg_n_0_[9]\ : STD_LOGIC;
  signal \gr[11]_i_1_n_0\ : STD_LOGIC;
  signal grayToManyAXIS_tlast_sig_i_1_n_0 : STD_LOGIC;
  signal grayToManyAXIS_tvalid_sig : STD_LOGIC;
  signal grayToManyAXIS_tvalid_sig_i_1_n_0 : STD_LOGIC;
  signal grayVideoinToManyAXIS_tdata : STD_LOGIC_VECTOR ( 71 downto 64 );
  signal \^grayvideointomanyaxis_tlast\ : STD_LOGIC;
  signal \^grayvideointomanyaxis_tvalid\ : STD_LOGIC;
  signal klm : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal \klm[0]_i_1_n_0\ : STD_LOGIC;
  signal \klm[1]_i_1_n_0\ : STD_LOGIC;
  signal \klm[2]_i_2_n_0\ : STD_LOGIC;
  signal \^klm_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal myEvenAbuf_n_28 : STD_LOGIC;
  signal myEvenAbuf_n_29 : STD_LOGIC;
  signal myEvenAbuf_n_32 : STD_LOGIC;
  signal myEvenAbuf_n_33 : STD_LOGIC;
  signal myEvenAbuf_n_34 : STD_LOGIC;
  signal myEvenAbuf_n_35 : STD_LOGIC;
  signal myEvenAbuf_n_36 : STD_LOGIC;
  signal myEvenAbuf_n_37 : STD_LOGIC;
  signal myEvenAbuf_n_38 : STD_LOGIC;
  signal myEvenAbuf_n_39 : STD_LOGIC;
  signal myEvenAbuf_n_40 : STD_LOGIC;
  signal myOddbuf_n_0 : STD_LOGIC;
  signal myOddbuf_n_1 : STD_LOGIC;
  signal myOddbuf_n_2 : STD_LOGIC;
  signal myOddbuf_n_22 : STD_LOGIC;
  signal myOddbuf_n_23 : STD_LOGIC;
  signal myOddbuf_n_24 : STD_LOGIC;
  signal myOddbuf_n_25 : STD_LOGIC;
  signal myOddbuf_n_3 : STD_LOGIC;
  signal myOddbuf_n_4 : STD_LOGIC;
  signal myOddbuf_n_5 : STD_LOGIC;
  signal myOddbuf_n_6 : STD_LOGIC;
  signal myOddbuf_n_9 : STD_LOGIC;
  signal myRow0buf_n_0 : STD_LOGIC;
  signal myRow0buf_n_1 : STD_LOGIC;
  signal myRow0buf_n_2 : STD_LOGIC;
  signal myRow0buf_n_3 : STD_LOGIC;
  signal myRow0buf_n_4 : STD_LOGIC;
  signal myRow0buf_n_5 : STD_LOGIC;
  signal myRow0buf_n_6 : STD_LOGIC;
  signal myRow0buf_n_7 : STD_LOGIC;
  signal nop : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \nop[3]_i_1_n_0\ : STD_LOGIC;
  signal \nop[3]_i_3_n_0\ : STD_LOGIC;
  signal \nop_reg_n_0_[0]\ : STD_LOGIC;
  signal \nop_reg_n_0_[1]\ : STD_LOGIC;
  signal \nop_reg_n_0_[2]\ : STD_LOGIC;
  signal \nop_reg_n_0_[3]\ : STD_LOGIC;
  signal oddNotEven : STD_LOGIC;
  signal oddNotEven_i_1_n_0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal p_14_in : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal p_1_in : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal p_3_in : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal p_3_out : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal qrs : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \qrs[2]_i_1_n_0\ : STD_LOGIC;
  signal \qrs_reg_n_0_[0]\ : STD_LOGIC;
  signal \qrs_reg_n_0_[1]\ : STD_LOGIC;
  signal \qrs_reg_n_0_[2]\ : STD_LOGIC;
  signal rawcolEgrstart : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \rawcolEgrstart[3]_i_1_n_0\ : STD_LOGIC;
  signal rawcol_lcl : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \rawcol_lcl[0]_i_1_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[10]_i_1_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[11]_i_1_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[11]_i_2_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[1]_i_1_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[2]_i_1_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[3]_i_1_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[4]_i_1_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[4]_i_2_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[5]_i_1_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[6]_i_1_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[6]_i_2_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[7]_i_1_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[8]_i_1_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[8]_i_2_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[9]_i_1_n_0\ : STD_LOGIC;
  signal \rawcol_lcl[9]_i_2_n_0\ : STD_LOGIC;
  signal rgbToManyAXIS_tdata_sig : STD_LOGIC_VECTOR ( 35 downto 0 );
  signal \^rgbtomanyaxis_tdata_sig_reg[35]_0\ : STD_LOGIC_VECTOR ( 35 downto 0 );
  signal \^rgbtomanyaxis_tdata_sig_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rgbToManyAXIS_tlast_sig_i_1_n_0 : STD_LOGIC;
  signal rgbToManyAXIS_tlast_sig_i_2_n_0 : STD_LOGIC;
  signal rgbToManyAXIS_tlast_sig_i_3_n_0 : STD_LOGIC;
  signal rgbToManyAXIS_tlast_sig_i_5_n_0 : STD_LOGIC;
  signal \^rgbtomanyaxis_tlast_sig_reg_0\ : STD_LOGIC;
  signal rgbToManyAXIS_tvalid_sig_i_1_n_0 : STD_LOGIC;
  signal \^rgbvideointomanyaxis_tvalid\ : STD_LOGIC;
  signal stateGrayegr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal stateGraypack : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \stateGraypack[0]_i_10_n_0\ : STD_LOGIC;
  signal \stateGraypack[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateGraypack[0]_i_2_n_0\ : STD_LOGIC;
  signal \stateGraypack[0]_i_3_n_0\ : STD_LOGIC;
  signal \stateGraypack[0]_i_4_n_0\ : STD_LOGIC;
  signal \stateGraypack[0]_i_5_n_0\ : STD_LOGIC;
  signal \stateGraypack[0]_i_6_n_0\ : STD_LOGIC;
  signal \stateGraypack[0]_i_7_n_0\ : STD_LOGIC;
  signal \stateGraypack[0]_i_8_n_0\ : STD_LOGIC;
  signal \stateGraypack[0]_i_9_n_0\ : STD_LOGIC;
  signal \stateGraypack[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateGraypack[1]_i_2_n_0\ : STD_LOGIC;
  signal \stateIgr[0]_i_2_n_0\ : STD_LOGIC;
  signal \^stateigr_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal strbEgrstart_i_1_n_0 : STD_LOGIC;
  signal strbEgrstart_i_2_n_0 : STD_LOGIC;
  signal strbEgrstart_i_3_n_0 : STD_LOGIC;
  signal strbEgrstart_i_4_n_0 : STD_LOGIC;
  signal strbEgrstart_reg_n_0 : STD_LOGIC;
  signal tuv : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \tuv[2]_i_1_n_0\ : STD_LOGIC;
  signal \tuv[3]_i_1_n_0\ : STD_LOGIC;
  signal \tuv_reg_n_0_[0]\ : STD_LOGIC;
  signal \tuv_reg_n_0_[1]\ : STD_LOGIC;
  signal \tuv_reg_n_0_[2]\ : STD_LOGIC;
  signal \tuv_reg_n_0_[3]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_stateGrayegr[1]_i_1\ : label is "soft_lutpair2995";
  attribute SOFT_HLUTNM of \FSM_sequential_stateGrayegr[2]_i_2\ : label is "soft_lutpair2995";
  attribute SOFT_HLUTNM of \FSM_sequential_stateGrayegr[2]_i_6\ : label is "soft_lutpair2959";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateGrayegr_reg[0]\ : label is "iSTATE:010,iSTATE0:011,iSTATE1:100,iSTATE2:000,iSTATE3:001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateGrayegr_reg[1]\ : label is "iSTATE:010,iSTATE0:011,iSTATE1:100,iSTATE2:000,iSTATE3:001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateGrayegr_reg[2]\ : label is "iSTATE:010,iSTATE0:011,iSTATE1:100,iSTATE2:000,iSTATE3:001";
  attribute SOFT_HLUTNM of \FSM_sequential_stateRgbegr[0]_i_1\ : label is "soft_lutpair2992";
  attribute SOFT_HLUTNM of \FSM_sequential_stateRgbegr[1]_i_1\ : label is "soft_lutpair3019";
  attribute SOFT_HLUTNM of \FSM_sequential_stateRgbegr[2]_i_2\ : label is "soft_lutpair2958";
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateRgbegr_reg[0]\ : label is "iSTATE:010,iSTATE0:011,iSTATE1:101,iSTATE2:100,iSTATE3:000,iSTATE4:001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateRgbegr_reg[1]\ : label is "iSTATE:010,iSTATE0:011,iSTATE1:101,iSTATE2:100,iSTATE3:000,iSTATE4:001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_stateRgbegr_reg[2]\ : label is "iSTATE:010,iSTATE0:011,iSTATE1:101,iSTATE2:100,iSTATE3:000,iSTATE4:001";
  attribute SOFT_HLUTNM of \aEobufB[0]_i_1\ : label is "soft_lutpair3018";
  attribute SOFT_HLUTNM of \aEobufB[1]_i_1\ : label is "soft_lutpair2979";
  attribute SOFT_HLUTNM of \aEobufB[2]_i_1\ : label is "soft_lutpair2979";
  attribute SOFT_HLUTNM of \aEobufB[4]_i_1\ : label is "soft_lutpair3018";
  attribute SOFT_HLUTNM of \aEobufB[4]_i_2\ : label is "soft_lutpair2978";
  attribute SOFT_HLUTNM of \aEobufB[5]_i_1\ : label is "soft_lutpair3019";
  attribute SOFT_HLUTNM of \aEobufB[5]_i_2\ : label is "soft_lutpair2978";
  attribute SOFT_HLUTNM of \aEobufB[6]_i_1\ : label is "soft_lutpair2976";
  attribute SOFT_HLUTNM of \aEobufB[7]_i_1\ : label is "soft_lutpair2976";
  attribute SOFT_HLUTNM of \aEobufB[9]_i_2\ : label is "soft_lutpair2977";
  attribute SOFT_HLUTNM of \aEobufB[9]_i_3\ : label is "soft_lutpair2977";
  attribute SOFT_HLUTNM of \aEobufB[9]_i_4\ : label is "soft_lutpair2992";
  attribute SOFT_HLUTNM of \aEobufB[9]_i_5\ : label is "soft_lutpair3040";
  attribute SOFT_HLUTNM of \aEobuf[1]_i_1\ : label is "soft_lutpair3002";
  attribute SOFT_HLUTNM of \aEobuf[2]_i_1\ : label is "soft_lutpair3002";
  attribute SOFT_HLUTNM of \aEobuf[5]_i_1\ : label is "soft_lutpair3033";
  attribute SOFT_HLUTNM of \aEobuf[6]_i_1\ : label is "soft_lutpair3003";
  attribute SOFT_HLUTNM of \aEobuf[7]_i_1\ : label is "soft_lutpair3003";
  attribute SOFT_HLUTNM of \aEobuf[9]_i_4\ : label is "soft_lutpair2973";
  attribute SOFT_HLUTNM of \aRowbufB[0]_i_1\ : label is "soft_lutpair3020";
  attribute SOFT_HLUTNM of \aRowbufB[1]_i_1\ : label is "soft_lutpair2983";
  attribute SOFT_HLUTNM of \aRowbufB[2]_i_1\ : label is "soft_lutpair2983";
  attribute SOFT_HLUTNM of \aRowbufB[4]_i_1\ : label is "soft_lutpair3020";
  attribute SOFT_HLUTNM of \aRowbufB[4]_i_2\ : label is "soft_lutpair2982";
  attribute SOFT_HLUTNM of \aRowbufB[5]_i_1\ : label is "soft_lutpair3021";
  attribute SOFT_HLUTNM of \aRowbufB[5]_i_2\ : label is "soft_lutpair2982";
  attribute SOFT_HLUTNM of \aRowbufB[6]_i_1\ : label is "soft_lutpair2981";
  attribute SOFT_HLUTNM of \aRowbufB[7]_i_1\ : label is "soft_lutpair2981";
  attribute SOFT_HLUTNM of \aRowbuf[0]_i_1\ : label is "soft_lutpair3051";
  attribute SOFT_HLUTNM of \aRowbuf[1]_i_1\ : label is "soft_lutpair2986";
  attribute SOFT_HLUTNM of \aRowbuf[2]_i_1\ : label is "soft_lutpair2986";
  attribute SOFT_HLUTNM of \aRowbuf[4]_i_1\ : label is "soft_lutpair3022";
  attribute SOFT_HLUTNM of \aRowbuf[4]_i_2\ : label is "soft_lutpair2985";
  attribute SOFT_HLUTNM of \aRowbuf[5]_i_1\ : label is "soft_lutpair3023";
  attribute SOFT_HLUTNM of \aRowbuf[5]_i_2\ : label is "soft_lutpair2985";
  attribute SOFT_HLUTNM of \aRowbuf[6]_i_1\ : label is "soft_lutpair2984";
  attribute SOFT_HLUTNM of \aRowbuf[7]_i_1\ : label is "soft_lutpair2984";
  attribute SOFT_HLUTNM of \aRowbuf[8]_i_7\ : label is "soft_lutpair3000";
  attribute SOFT_HLUTNM of \abcde[0]_i_1__0\ : label is "soft_lutpair3024";
  attribute SOFT_HLUTNM of \abcde[2]_i_2__0\ : label is "soft_lutpair3024";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \acc0_lcl_reg[7]_i_2\ : label is 35;
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of \acc0_lcl_reg[7]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}";
  attribute SOFT_HLUTNM of \acc2[19]_i_2\ : label is "soft_lutpair3026";
  attribute SOFT_HLUTNM of \col_lcl[0]__0_i_1__0\ : label is "soft_lutpair2998";
  attribute SOFT_HLUTNM of \col_lcl[0]__1_i_1\ : label is "soft_lutpair3052";
  attribute SOFT_HLUTNM of \col_lcl[0]_i_1__1\ : label is "soft_lutpair2993";
  attribute SOFT_HLUTNM of \col_lcl[10]__0_i_1__0\ : label is "soft_lutpair3016";
  attribute SOFT_HLUTNM of \col_lcl[10]__1_i_2\ : label is "soft_lutpair3051";
  attribute SOFT_HLUTNM of \col_lcl[10]_i_1__1\ : label is "soft_lutpair3015";
  attribute SOFT_HLUTNM of \col_lcl[1]__0_i_1__0\ : label is "soft_lutpair2998";
  attribute SOFT_HLUTNM of \col_lcl[1]__1_i_1\ : label is "soft_lutpair2969";
  attribute SOFT_HLUTNM of \col_lcl[1]_i_1__1\ : label is "soft_lutpair2993";
  attribute SOFT_HLUTNM of \col_lcl[2]__1_i_1\ : label is "soft_lutpair2969";
  attribute SOFT_HLUTNM of \col_lcl[4]__1_i_2\ : label is "soft_lutpair3011";
  attribute SOFT_HLUTNM of \col_lcl[5]__0_i_1__0\ : label is "soft_lutpair3016";
  attribute SOFT_HLUTNM of \col_lcl[5]__1_i_1\ : label is "soft_lutpair3022";
  attribute SOFT_HLUTNM of \col_lcl[5]_i_1__1\ : label is "soft_lutpair3015";
  attribute SOFT_HLUTNM of \col_lcl[6]__0_i_1__0\ : label is "soft_lutpair2960";
  attribute SOFT_HLUTNM of \col_lcl[6]__1_i_1\ : label is "soft_lutpair2970";
  attribute SOFT_HLUTNM of \col_lcl[6]_i_1__1\ : label is "soft_lutpair2958";
  attribute SOFT_HLUTNM of \col_lcl[7]__1_i_1\ : label is "soft_lutpair2970";
  attribute SOFT_HLUTNM of \col_lcl[8]__0_i_1__0\ : label is "soft_lutpair2959";
  attribute SOFT_HLUTNM of \col_lcl[8]_i_1__1\ : label is "soft_lutpair2957";
  attribute SOFT_HLUTNM of \col_lcl[9]__1_i_1\ : label is "soft_lutpair3023";
  attribute SOFT_HLUTNM of \col_lcl[9]__1_i_2\ : label is "soft_lutpair2999";
  attribute SOFT_HLUTNM of \dIgrm1[0]_i_2\ : label is "soft_lutpair3035";
  attribute SOFT_HLUTNM of \dIgrm1[16]_i_3\ : label is "soft_lutpair3069";
  attribute SOFT_HLUTNM of \dIgrm1[17]_i_3\ : label is "soft_lutpair3067";
  attribute SOFT_HLUTNM of \dIgrm1[18]_i_3\ : label is "soft_lutpair3065";
  attribute SOFT_HLUTNM of \dIgrm1[19]_i_3\ : label is "soft_lutpair3062";
  attribute SOFT_HLUTNM of \dIgrm1[1]_i_2\ : label is "soft_lutpair3035";
  attribute SOFT_HLUTNM of \dIgrm1[20]_i_3\ : label is "soft_lutpair3061";
  attribute SOFT_HLUTNM of \dIgrm1[21]_i_3\ : label is "soft_lutpair3058";
  attribute SOFT_HLUTNM of \dIgrm1[22]_i_3\ : label is "soft_lutpair3056";
  attribute SOFT_HLUTNM of \dIgrm1[23]_i_3\ : label is "soft_lutpair3055";
  attribute SOFT_HLUTNM of \dIgrm1[24]_i_3\ : label is "soft_lutpair3068";
  attribute SOFT_HLUTNM of \dIgrm1[24]_i_4\ : label is "soft_lutpair3073";
  attribute SOFT_HLUTNM of \dIgrm1[25]_i_3\ : label is "soft_lutpair3066";
  attribute SOFT_HLUTNM of \dIgrm1[25]_i_4\ : label is "soft_lutpair3073";
  attribute SOFT_HLUTNM of \dIgrm1[26]_i_3\ : label is "soft_lutpair3064";
  attribute SOFT_HLUTNM of \dIgrm1[26]_i_4\ : label is "soft_lutpair3072";
  attribute SOFT_HLUTNM of \dIgrm1[27]_i_3\ : label is "soft_lutpair3072";
  attribute SOFT_HLUTNM of \dIgrm1[27]_i_4\ : label is "soft_lutpair3063";
  attribute SOFT_HLUTNM of \dIgrm1[28]_i_3\ : label is "soft_lutpair3071";
  attribute SOFT_HLUTNM of \dIgrm1[28]_i_4\ : label is "soft_lutpair3060";
  attribute SOFT_HLUTNM of \dIgrm1[29]_i_3\ : label is "soft_lutpair3071";
  attribute SOFT_HLUTNM of \dIgrm1[29]_i_4\ : label is "soft_lutpair3059";
  attribute SOFT_HLUTNM of \dIgrm1[2]_i_2\ : label is "soft_lutpair3036";
  attribute SOFT_HLUTNM of \dIgrm1[30]_i_3\ : label is "soft_lutpair3070";
  attribute SOFT_HLUTNM of \dIgrm1[30]_i_4\ : label is "soft_lutpair3057";
  attribute SOFT_HLUTNM of \dIgrm1[31]_i_3\ : label is "soft_lutpair3070";
  attribute SOFT_HLUTNM of \dIgrm1[31]_i_4\ : label is "soft_lutpair3054";
  attribute SOFT_HLUTNM of \dIgrm1[32]_i_3\ : label is "soft_lutpair3068";
  attribute SOFT_HLUTNM of \dIgrm1[32]_i_4\ : label is "soft_lutpair3069";
  attribute SOFT_HLUTNM of \dIgrm1[33]_i_3\ : label is "soft_lutpair3067";
  attribute SOFT_HLUTNM of \dIgrm1[33]_i_4\ : label is "soft_lutpair3066";
  attribute SOFT_HLUTNM of \dIgrm1[34]_i_3\ : label is "soft_lutpair3065";
  attribute SOFT_HLUTNM of \dIgrm1[34]_i_4\ : label is "soft_lutpair3064";
  attribute SOFT_HLUTNM of \dIgrm1[35]_i_3\ : label is "soft_lutpair3063";
  attribute SOFT_HLUTNM of \dIgrm1[35]_i_4\ : label is "soft_lutpair3062";
  attribute SOFT_HLUTNM of \dIgrm1[36]_i_3\ : label is "soft_lutpair3061";
  attribute SOFT_HLUTNM of \dIgrm1[36]_i_4\ : label is "soft_lutpair3060";
  attribute SOFT_HLUTNM of \dIgrm1[37]_i_3\ : label is "soft_lutpair3059";
  attribute SOFT_HLUTNM of \dIgrm1[37]_i_4\ : label is "soft_lutpair3058";
  attribute SOFT_HLUTNM of \dIgrm1[38]_i_3\ : label is "soft_lutpair3056";
  attribute SOFT_HLUTNM of \dIgrm1[38]_i_4\ : label is "soft_lutpair3057";
  attribute SOFT_HLUTNM of \dIgrm1[39]_i_4\ : label is "soft_lutpair3054";
  attribute SOFT_HLUTNM of \dIgrm1[39]_i_5\ : label is "soft_lutpair3055";
  attribute SOFT_HLUTNM of \dIgrm1[3]_i_2\ : label is "soft_lutpair3036";
  attribute SOFT_HLUTNM of \dIgrm1[4]_i_2\ : label is "soft_lutpair3037";
  attribute SOFT_HLUTNM of \dIgrm1[5]_i_2\ : label is "soft_lutpair3037";
  attribute SOFT_HLUTNM of \dIgrm1[6]_i_2\ : label is "soft_lutpair3038";
  attribute SOFT_HLUTNM of \dIgrm1[7]_i_2\ : label is "soft_lutpair3038";
  attribute SOFT_HLUTNM of \drdRow4bufBm1[63]_i_3\ : label is "soft_lutpair3005";
  attribute SOFT_HLUTNM of \drdRow4bufBm1[63]_i_4\ : label is "soft_lutpair3012";
  attribute SOFT_HLUTNM of \dwrEobuf[10]_i_1\ : label is "soft_lutpair3043";
  attribute SOFT_HLUTNM of \dwrEobuf[11]_i_1\ : label is "soft_lutpair3042";
  attribute SOFT_HLUTNM of \dwrEobuf[12]_i_1\ : label is "soft_lutpair3042";
  attribute SOFT_HLUTNM of \dwrEobuf[13]_i_1\ : label is "soft_lutpair3041";
  attribute SOFT_HLUTNM of \dwrEobuf[14]_i_1\ : label is "soft_lutpair3041";
  attribute SOFT_HLUTNM of \dwrEobuf[15]_i_1\ : label is "soft_lutpair3033";
  attribute SOFT_HLUTNM of \dwrEobuf[16]_i_1\ : label is "soft_lutpair2968";
  attribute SOFT_HLUTNM of \dwrEobuf[17]_i_1\ : label is "soft_lutpair2967";
  attribute SOFT_HLUTNM of \dwrEobuf[18]_i_1\ : label is "soft_lutpair2966";
  attribute SOFT_HLUTNM of \dwrEobuf[19]_i_1\ : label is "soft_lutpair2965";
  attribute SOFT_HLUTNM of \dwrEobuf[20]_i_1\ : label is "soft_lutpair2964";
  attribute SOFT_HLUTNM of \dwrEobuf[21]_i_1\ : label is "soft_lutpair2963";
  attribute SOFT_HLUTNM of \dwrEobuf[22]_i_1\ : label is "soft_lutpair2962";
  attribute SOFT_HLUTNM of \dwrEobuf[23]_i_2\ : label is "soft_lutpair2961";
  attribute SOFT_HLUTNM of \dwrEobuf[39]_i_2\ : label is "soft_lutpair3025";
  attribute SOFT_HLUTNM of \dwrEobuf[39]_i_4\ : label is "soft_lutpair3039";
  attribute SOFT_HLUTNM of \dwrEobuf[48]_i_1\ : label is "soft_lutpair2968";
  attribute SOFT_HLUTNM of \dwrEobuf[49]_i_1\ : label is "soft_lutpair2967";
  attribute SOFT_HLUTNM of \dwrEobuf[50]_i_1\ : label is "soft_lutpair2966";
  attribute SOFT_HLUTNM of \dwrEobuf[51]_i_1\ : label is "soft_lutpair2965";
  attribute SOFT_HLUTNM of \dwrEobuf[52]_i_1\ : label is "soft_lutpair2964";
  attribute SOFT_HLUTNM of \dwrEobuf[53]_i_1\ : label is "soft_lutpair2963";
  attribute SOFT_HLUTNM of \dwrEobuf[54]_i_1\ : label is "soft_lutpair2962";
  attribute SOFT_HLUTNM of \dwrEobuf[55]_i_2\ : label is "soft_lutpair2961";
  attribute SOFT_HLUTNM of \dwrEobuf[8]_i_1\ : label is "soft_lutpair3044";
  attribute SOFT_HLUTNM of \dwrEobuf[9]_i_1\ : label is "soft_lutpair3043";
  attribute SOFT_HLUTNM of \dwrEobufp1[10]_i_1\ : label is "soft_lutpair3049";
  attribute SOFT_HLUTNM of \dwrEobufp1[11]_i_1\ : label is "soft_lutpair3048";
  attribute SOFT_HLUTNM of \dwrEobufp1[12]_i_1\ : label is "soft_lutpair3048";
  attribute SOFT_HLUTNM of \dwrEobufp1[13]_i_1\ : label is "soft_lutpair3047";
  attribute SOFT_HLUTNM of \dwrEobufp1[14]_i_1\ : label is "soft_lutpair3047";
  attribute SOFT_HLUTNM of \dwrEobufp1[15]_i_2\ : label is "soft_lutpair3044";
  attribute SOFT_HLUTNM of \dwrEobufp1[8]_i_1\ : label is "soft_lutpair3050";
  attribute SOFT_HLUTNM of \dwrEobufp1[9]_i_1\ : label is "soft_lutpair3049";
  attribute SOFT_HLUTNM of \dwrRowbuf[0]_i_1__0\ : label is "soft_lutpair3010";
  attribute SOFT_HLUTNM of \dwrRowbuf[1]_i_1__0\ : label is "soft_lutpair3011";
  attribute SOFT_HLUTNM of \dwrRowbufp1[0]_i_1\ : label is "soft_lutpair3009";
  attribute SOFT_HLUTNM of \dwrRowbufp1[1]_i_1\ : label is "soft_lutpair3008";
  attribute SOFT_HLUTNM of \dwrRowbufp1[2]_i_1\ : label is "soft_lutpair3007";
  attribute SOFT_HLUTNM of \dwrRowbufp1[3]_i_2\ : label is "soft_lutpair3006";
  attribute SOFT_HLUTNM of \dwrRowbufp1[3]_i_3\ : label is "soft_lutpair3017";
  attribute SOFT_HLUTNM of \dwrRowbufp1[4]_i_1\ : label is "soft_lutpair3009";
  attribute SOFT_HLUTNM of \dwrRowbufp1[5]_i_1\ : label is "soft_lutpair3008";
  attribute SOFT_HLUTNM of \dwrRowbufp1[6]_i_1\ : label is "soft_lutpair3007";
  attribute SOFT_HLUTNM of \dwrRowbufp1[7]_i_2\ : label is "soft_lutpair3006";
  attribute SOFT_HLUTNM of \dwrRowbufp1[7]_i_4\ : label is "soft_lutpair3053";
  attribute SOFT_HLUTNM of \dy[0]_i_1\ : label is "soft_lutpair3045";
  attribute SOFT_HLUTNM of \dy[10]_i_1\ : label is "soft_lutpair2988";
  attribute SOFT_HLUTNM of \dy[11]_i_2\ : label is "soft_lutpair2988";
  attribute SOFT_HLUTNM of \dy[16]_i_1\ : label is "soft_lutpair3028";
  attribute SOFT_HLUTNM of \dy[17]_i_1\ : label is "soft_lutpair3028";
  attribute SOFT_HLUTNM of \dy[18]_i_1\ : label is "soft_lutpair3046";
  attribute SOFT_HLUTNM of \dy[19]_i_1\ : label is "soft_lutpair2989";
  attribute SOFT_HLUTNM of \dy[1]_i_1\ : label is "soft_lutpair2987";
  attribute SOFT_HLUTNM of \dy[20]_i_2\ : label is "soft_lutpair2989";
  attribute SOFT_HLUTNM of \dy[25]_i_1\ : label is "soft_lutpair3029";
  attribute SOFT_HLUTNM of \dy[26]_i_1\ : label is "soft_lutpair3029";
  attribute SOFT_HLUTNM of \dy[27]_i_1\ : label is "soft_lutpair3046";
  attribute SOFT_HLUTNM of \dy[28]_i_1\ : label is "soft_lutpair2990";
  attribute SOFT_HLUTNM of \dy[29]_i_2\ : label is "soft_lutpair2990";
  attribute SOFT_HLUTNM of \dy[2]_i_2\ : label is "soft_lutpair2987";
  attribute SOFT_HLUTNM of \dy[34]_i_1\ : label is "soft_lutpair3030";
  attribute SOFT_HLUTNM of \dy[35]_i_1\ : label is "soft_lutpair3030";
  attribute SOFT_HLUTNM of \dy[37]_i_1\ : label is "soft_lutpair2991";
  attribute SOFT_HLUTNM of \dy[38]_i_3\ : label is "soft_lutpair2991";
  attribute SOFT_HLUTNM of \dy[43]_i_1\ : label is "soft_lutpair3031";
  attribute SOFT_HLUTNM of \dy[44]_i_1\ : label is "soft_lutpair3031";
  attribute SOFT_HLUTNM of \dy[7]_i_1\ : label is "soft_lutpair3027";
  attribute SOFT_HLUTNM of \dy[8]_i_1\ : label is "soft_lutpair3027";
  attribute SOFT_HLUTNM of \dy[9]_i_1\ : label is "soft_lutpair3045";
  attribute SOFT_HLUTNM of enAccbuf_i_4 : label is "soft_lutpair3026";
  attribute SOFT_HLUTNM of enEobufB_i_2 : label is "soft_lutpair3004";
  attribute SOFT_HLUTNM of enEobufB_i_4 : label is "soft_lutpair3004";
  attribute SOFT_HLUTNM of enRowbufB_i_3 : label is "soft_lutpair3021";
  attribute SOFT_HLUTNM of enRowbufB_i_4 : label is "soft_lutpair3005";
  attribute SOFT_HLUTNM of enRowbufB_lcl_i_2 : label is "soft_lutpair2996";
  attribute SOFT_HLUTNM of enRowbuf_i_2 : label is "soft_lutpair3017";
  attribute SOFT_HLUTNM of enRowbuf_i_5 : label is "soft_lutpair3032";
  attribute SOFT_HLUTNM of fillBNotA_i_1 : label is "soft_lutpair3013";
  attribute SOFT_HLUTNM of grayToManyAXIS_tvalid_sig_i_1 : label is "soft_lutpair3012";
  attribute SOFT_HLUTNM of \klm[0]_i_1\ : label is "soft_lutpair3025";
  attribute SOFT_HLUTNM of \klm[1]_i_1\ : label is "soft_lutpair2971";
  attribute SOFT_HLUTNM of \klm[2]_i_2\ : label is "soft_lutpair2971";
  attribute SOFT_HLUTNM of \nop[0]_i_1\ : label is "soft_lutpair2997";
  attribute SOFT_HLUTNM of \nop[1]_i_1\ : label is "soft_lutpair2997";
  attribute SOFT_HLUTNM of \nop[3]_i_2\ : label is "soft_lutpair2996";
  attribute SOFT_HLUTNM of \nop[3]_i_3\ : label is "soft_lutpair2960";
  attribute SOFT_HLUTNM of oddNotEven_i_1 : label is "soft_lutpair3013";
  attribute SOFT_HLUTNM of \qrs[0]_i_1\ : label is "soft_lutpair2994";
  attribute SOFT_HLUTNM of \qrs[1]_i_1\ : label is "soft_lutpair2994";
  attribute SOFT_HLUTNM of \rawcol_lcl[0]_i_1\ : label is "soft_lutpair3050";
  attribute SOFT_HLUTNM of \rawcol_lcl[10]_i_1\ : label is "soft_lutpair2974";
  attribute SOFT_HLUTNM of \rawcol_lcl[1]_i_1\ : label is "soft_lutpair2980";
  attribute SOFT_HLUTNM of \rawcol_lcl[2]_i_1\ : label is "soft_lutpair2980";
  attribute SOFT_HLUTNM of \rawcol_lcl[4]_i_2\ : label is "soft_lutpair3034";
  attribute SOFT_HLUTNM of \rawcol_lcl[5]_i_1\ : label is "soft_lutpair2972";
  attribute SOFT_HLUTNM of \rawcol_lcl[7]_i_1\ : label is "soft_lutpair2973";
  attribute SOFT_HLUTNM of rgbToManyAXIS_tlast_sig_i_1 : label is "soft_lutpair3014";
  attribute SOFT_HLUTNM of rgbToManyAXIS_tlast_sig_i_5 : label is "soft_lutpair2957";
  attribute SOFT_HLUTNM of rgbToManyAXIS_tvalid_sig_i_1 : label is "soft_lutpair3040";
  attribute SOFT_HLUTNM of \stateGraypack[0]_i_4\ : label is "soft_lutpair3032";
  attribute SOFT_HLUTNM of \stateGraypack[0]_i_6\ : label is "soft_lutpair2999";
  attribute SOFT_HLUTNM of \stateGraypack[0]_i_8\ : label is "soft_lutpair3000";
  attribute SOFT_HLUTNM of \stateGraypack[0]_i_9\ : label is "soft_lutpair3052";
  attribute SOFT_HLUTNM of \stateGraypack[1]_i_2\ : label is "soft_lutpair3010";
  attribute SOFT_HLUTNM of \stateIgr[0]_i_1\ : label is "soft_lutpair3001";
  attribute SOFT_HLUTNM of \stateIgr[0]_i_2\ : label is "soft_lutpair3039";
  attribute SOFT_HLUTNM of \stateIgr[1]_i_2\ : label is "soft_lutpair3001";
  attribute SOFT_HLUTNM of \state[0]_i_3\ : label is "soft_lutpair2974";
  attribute SOFT_HLUTNM of \state[4]_i_3\ : label is "soft_lutpair2972";
  attribute SOFT_HLUTNM of \state[4]_i_5\ : label is "soft_lutpair3014";
  attribute SOFT_HLUTNM of strbEgrstart_i_4 : label is "soft_lutpair3034";
  attribute SOFT_HLUTNM of \tuv[0]_i_1\ : label is "soft_lutpair3053";
  attribute SOFT_HLUTNM of \tuv[1]_i_1\ : label is "soft_lutpair2975";
  attribute SOFT_HLUTNM of \tuv[2]_i_1\ : label is "soft_lutpair2975";
begin
  \FSM_sequential_stateRgbegr_reg[2]_0\(2 downto 0) <= \^fsm_sequential_statergbegr_reg[2]_0\(2 downto 0);
  Q(4 downto 0) <= \^q\(4 downto 0);
  \abcde_reg[0]_0\(39 downto 0) <= \^abcde_reg[0]_0\(39 downto 0);
  \col_lcl_reg[5]_0\ <= \^col_lcl_reg[5]_0\;
  \col_lcl_reg[5]_1\ <= \^col_lcl_reg[5]_1\;
  grayVideoinToManyAXIS_tlast <= \^grayvideointomanyaxis_tlast\;
  grayVideoinToManyAXIS_tvalid <= \^grayvideointomanyaxis_tvalid\;
  \klm_reg[0]_0\(0) <= \^klm_reg[0]_0\(0);
  \rgbToManyAXIS_tdata_sig_reg[35]_0\(35 downto 0) <= \^rgbtomanyaxis_tdata_sig_reg[35]_0\(35 downto 0);
  \rgbToManyAXIS_tdata_sig_reg[7]_0\(7 downto 0) <= \^rgbtomanyaxis_tdata_sig_reg[7]_0\(7 downto 0);
  rgbToManyAXIS_tlast_sig_reg_0 <= \^rgbtomanyaxis_tlast_sig_reg_0\;
  rgbVideoinToManyAXIS_tvalid <= \^rgbvideointomanyaxis_tvalid\;
  \stateIgr_reg[1]_0\(1 downto 0) <= \^stateigr_reg[1]_0\(1 downto 0);
\FSM_sequential_stateGrayegr[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555555C0CCDDDD"
    )
        port map (
      I0 => oddNotEven_reg_0,
      I1 => stateGrayegr(1),
      I2 => \FSM_sequential_stateGrayegr[2]_i_3_n_0\,
      I3 => \^rgbvideointomanyaxis_tvalid\,
      I4 => stateGrayegr(0),
      I5 => stateGrayegr(2),
      O => \p_0_out__0\(0)
    );
\FSM_sequential_stateGrayegr[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BFF0"
    )
        port map (
      I0 => \FSM_sequential_stateGrayegr[2]_i_3_n_0\,
      I1 => \^rgbvideointomanyaxis_tvalid\,
      I2 => stateGrayegr(0),
      I3 => stateGrayegr(1),
      I4 => stateGrayegr(2),
      O => \p_0_out__0\(1)
    );
\FSM_sequential_stateGrayegr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"05FD"
    )
        port map (
      I0 => stateGrayegr(0),
      I1 => strbEgrstart_reg_n_0,
      I2 => stateGrayegr(1),
      I3 => stateGrayegr(2),
      O => \FSM_sequential_stateGrayegr[2]_i_1_n_0\
    );
\FSM_sequential_stateGrayegr[2]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \col_lcl_reg[4]__0_n_0\,
      I1 => \col_lcl_reg[2]__0_n_0\,
      I2 => \col_lcl_reg[1]__0_n_0\,
      I3 => \col_lcl_reg[0]__0_n_0\,
      I4 => \col_lcl_reg[3]__0_n_0\,
      O => \FSM_sequential_stateGrayegr[2]_i_10_n_0\
    );
\FSM_sequential_stateGrayegr[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000080"
    )
        port map (
      I0 => \^rgbvideointomanyaxis_tvalid\,
      I1 => stateGrayegr(1),
      I2 => stateGrayegr(0),
      I3 => stateGrayegr(2),
      I4 => \FSM_sequential_stateGrayegr[2]_i_3_n_0\,
      O => \p_0_out__0\(2)
    );
\FSM_sequential_stateGrayegr[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFEEFFEFFFF"
    )
        port map (
      I0 => \FSM_sequential_stateGrayegr[2]_i_4_n_0\,
      I1 => \FSM_sequential_stateGrayegr[2]_i_5_n_0\,
      I2 => \FSM_sequential_stateGrayegr[2]_i_6_n_0\,
      I3 => enRowbuf_reg_0(8),
      I4 => \col_lcl[10]__0_i_2__0_n_0\,
      I5 => enRowbuf_reg_0(10),
      O => \FSM_sequential_stateGrayegr[2]_i_3_n_0\
    );
\FSM_sequential_stateGrayegr[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"955555556AAAAAAA"
    )
        port map (
      I0 => enRowbuf_reg_0(9),
      I1 => \col_lcl_reg[8]__0_n_0\,
      I2 => \col_lcl_reg[6]__0_n_0\,
      I3 => \col_lcl[9]__0_i_2__0_n_0\,
      I4 => \col_lcl_reg[7]__0_n_0\,
      I5 => \col_lcl_reg[9]__0_n_0\,
      O => \FSM_sequential_stateGrayegr[2]_i_4_n_0\
    );
\FSM_sequential_stateGrayegr[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEDFDFEFEFFDFDFE"
    )
        port map (
      I0 => enRowbuf_reg_0(6),
      I1 => \FSM_sequential_stateGrayegr[2]_i_7_n_0\,
      I2 => \col_lcl_reg[7]__0_n_0\,
      I3 => \col_lcl[9]__0_i_2__0_n_0\,
      I4 => \col_lcl_reg[6]__0_n_0\,
      I5 => enRowbuf_reg_0(7),
      O => \FSM_sequential_stateGrayegr[2]_i_5_n_0\
    );
\FSM_sequential_stateGrayegr[2]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \col_lcl_reg[8]__0_n_0\,
      I1 => \col_lcl_reg[6]__0_n_0\,
      I2 => \col_lcl[9]__0_i_2__0_n_0\,
      I3 => \col_lcl_reg[7]__0_n_0\,
      O => \FSM_sequential_stateGrayegr[2]_i_6_n_0\
    );
\FSM_sequential_stateGrayegr[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF6FFFFFFFFFFF6"
    )
        port map (
      I0 => \col_lcl[5]__0_i_2__0_n_0\,
      I1 => enRowbuf_reg_0(5),
      I2 => \FSM_sequential_stateGrayegr[2]_i_8_n_0\,
      I3 => \FSM_sequential_stateGrayegr[2]_i_9_n_0\,
      I4 => enRowbuf_reg_0(4),
      I5 => \FSM_sequential_stateGrayegr[2]_i_10_n_0\,
      O => \FSM_sequential_stateGrayegr[2]_i_7_n_0\
    );
\FSM_sequential_stateGrayegr[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF6FF6F96FFFFF"
    )
        port map (
      I0 => \col_lcl_reg[2]__0_n_0\,
      I1 => enRowbuf_reg_0(2),
      I2 => enRowbuf_reg_0(1),
      I3 => \col_lcl_reg[1]__0_n_0\,
      I4 => \col_lcl_reg[0]__0_n_0\,
      I5 => enRowbuf_reg_0(0),
      O => \FSM_sequential_stateGrayegr[2]_i_8_n_0\
    );
\FSM_sequential_stateGrayegr[2]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"95556AAA"
    )
        port map (
      I0 => enRowbuf_reg_0(3),
      I1 => \col_lcl_reg[2]__0_n_0\,
      I2 => \col_lcl_reg[1]__0_n_0\,
      I3 => \col_lcl_reg[0]__0_n_0\,
      I4 => \col_lcl_reg[3]__0_n_0\,
      O => \FSM_sequential_stateGrayegr[2]_i_9_n_0\
    );
\FSM_sequential_stateGrayegr_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_sequential_stateGrayegr[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \p_0_out__0\(0),
      Q => stateGrayegr(0)
    );
\FSM_sequential_stateGrayegr_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_sequential_stateGrayegr[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \p_0_out__0\(1),
      Q => stateGrayegr(1)
    );
\FSM_sequential_stateGrayegr_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_sequential_stateGrayegr[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \p_0_out__0\(2),
      Q => stateGrayegr(2)
    );
\FSM_sequential_stateRgbegr[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1D3FCC0F"
    )
        port map (
      I0 => rgbToManyAXIS_tlast_sig_i_2_n_0,
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I2 => oddNotEven_reg_0,
      I3 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I4 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      O => p_0_out(0)
    );
\FSM_sequential_stateRgbegr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"26"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      O => p_0_out(1)
    );
\FSM_sequential_stateRgbegr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0FFD"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I1 => strbEgrstart_reg_n_0,
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I3 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      O => \FSM_sequential_stateRgbegr[2]_i_1_n_0\
    );
\FSM_sequential_stateRgbegr[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      O => \FSM_sequential_stateRgbegr[2]_i_2_n_0\
    );
\FSM_sequential_stateRgbegr_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_sequential_stateRgbegr[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => p_0_out(0),
      Q => \^fsm_sequential_statergbegr_reg[2]_0\(0)
    );
\FSM_sequential_stateRgbegr_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_sequential_stateRgbegr[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => p_0_out(1),
      Q => \^fsm_sequential_statergbegr_reg[2]_0\(1)
    );
\FSM_sequential_stateRgbegr_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_sequential_stateRgbegr[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \FSM_sequential_stateRgbegr[2]_i_2_n_0\,
      Q => \^fsm_sequential_statergbegr_reg[2]_0\(2)
    );
\aEobufB[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \aEobufB_reg_n_0_[0]\,
      O => \aEobufB[0]_i_1_n_0\
    );
\aEobufB[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1400"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I1 => \aEobufB_reg_n_0_[0]\,
      I2 => \aEobufB_reg_n_0_[1]\,
      I3 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      O => \aEobufB[1]_i_1_n_0\
    );
\aEobufB[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04404040"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \aEobufB_reg_n_0_[2]\,
      I3 => \aEobufB_reg_n_0_[1]\,
      I4 => \aEobufB_reg_n_0_[0]\,
      O => \aEobufB[2]_i_1_n_0\
    );
\aEobufB[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0440404040404040"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \aEobufB_reg_n_0_[3]\,
      I3 => \aEobufB_reg_n_0_[2]\,
      I4 => \aEobufB_reg_n_0_[0]\,
      I5 => \aEobufB_reg_n_0_[1]\,
      O => \aEobufB[3]_i_1_n_0\
    );
\aEobufB[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0440"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \aEobufB_reg_n_0_[4]\,
      I3 => \aEobufB[4]_i_2_n_0\,
      O => \aEobufB[4]_i_1_n_0\
    );
\aEobufB[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \aEobufB_reg_n_0_[2]\,
      I1 => \aEobufB_reg_n_0_[0]\,
      I2 => \aEobufB_reg_n_0_[1]\,
      I3 => \aEobufB_reg_n_0_[3]\,
      O => \aEobufB[4]_i_2_n_0\
    );
\aEobufB[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0440"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \aEobufB_reg_n_0_[5]\,
      I3 => \aEobufB[5]_i_2_n_0\,
      O => \aEobufB[5]_i_1_n_0\
    );
\aEobufB[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aEobufB_reg_n_0_[3]\,
      I1 => \aEobufB_reg_n_0_[1]\,
      I2 => \aEobufB_reg_n_0_[0]\,
      I3 => \aEobufB_reg_n_0_[2]\,
      I4 => \aEobufB_reg_n_0_[4]\,
      O => \aEobufB[5]_i_2_n_0\
    );
\aEobufB[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0440"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \aEobufB_reg_n_0_[6]\,
      I3 => \aEobufB[8]_i_2_n_0\,
      O => \aEobufB[6]_i_1_n_0\
    );
\aEobufB[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04404040"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \aEobufB_reg_n_0_[7]\,
      I3 => \aEobufB_reg_n_0_[6]\,
      I4 => \aEobufB[8]_i_2_n_0\,
      O => \aEobufB[7]_i_1_n_0\
    );
\aEobufB[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1444444400000000"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I1 => \aEobufB_reg_n_0_[8]\,
      I2 => \aEobufB_reg_n_0_[7]\,
      I3 => \aEobufB[8]_i_2_n_0\,
      I4 => \aEobufB_reg_n_0_[6]\,
      I5 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      O => \aEobufB[8]_i_1_n_0\
    );
\aEobufB[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aEobufB_reg_n_0_[4]\,
      I1 => \aEobufB_reg_n_0_[2]\,
      I2 => \aEobufB_reg_n_0_[0]\,
      I3 => \aEobufB_reg_n_0_[1]\,
      I4 => \aEobufB_reg_n_0_[3]\,
      I5 => \aEobufB_reg_n_0_[5]\,
      O => \aEobufB[8]_i_2_n_0\
    );
\aEobufB[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF9200"
    )
        port map (
      I0 => \qrs_reg_n_0_[2]\,
      I1 => \qrs_reg_n_0_[1]\,
      I2 => \qrs_reg_n_0_[0]\,
      I3 => \aEobufB[9]_i_3_n_0\,
      I4 => \aEobufB[9]_i_4_n_0\,
      I5 => \aEobufB[9]_i_5_n_0\,
      O => \aEobufB[9]_i_1_n_0\
    );
\aEobufB[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04404040"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \aEobufB_reg_n_0_[9]\,
      I3 => \aEobufB[9]_i_6_n_0\,
      I4 => \aEobufB_reg_n_0_[8]\,
      O => \aEobufB[9]_i_2_n_0\
    );
\aEobufB[9]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      O => \aEobufB[9]_i_3_n_0\
    );
\aEobufB[9]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I3 => oddNotEven_reg_0,
      O => \aEobufB[9]_i_4_n_0\
    );
\aEobufB[9]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      O => \aEobufB[9]_i_5_n_0\
    );
\aEobufB[9]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \aEobufB_reg_n_0_[6]\,
      I1 => \aEobufB[8]_i_2_n_0\,
      I2 => \aEobufB_reg_n_0_[7]\,
      O => \aEobufB[9]_i_6_n_0\
    );
\aEobufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobufB[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobufB[0]_i_1_n_0\,
      Q => \aEobufB_reg_n_0_[0]\
    );
\aEobufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobufB[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobufB[1]_i_1_n_0\,
      Q => \aEobufB_reg_n_0_[1]\
    );
\aEobufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobufB[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobufB[2]_i_1_n_0\,
      Q => \aEobufB_reg_n_0_[2]\
    );
\aEobufB_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobufB[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobufB[3]_i_1_n_0\,
      Q => \aEobufB_reg_n_0_[3]\
    );
\aEobufB_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobufB[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobufB[4]_i_1_n_0\,
      Q => \aEobufB_reg_n_0_[4]\
    );
\aEobufB_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobufB[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobufB[5]_i_1_n_0\,
      Q => \aEobufB_reg_n_0_[5]\
    );
\aEobufB_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobufB[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobufB[6]_i_1_n_0\,
      Q => \aEobufB_reg_n_0_[6]\
    );
\aEobufB_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobufB[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobufB[7]_i_1_n_0\,
      Q => \aEobufB_reg_n_0_[7]\
    );
\aEobufB_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobufB[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobufB[8]_i_1_n_0\,
      Q => \aEobufB_reg_n_0_[8]\
    );
\aEobufB_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobufB[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobufB[9]_i_2_n_0\,
      Q => \aEobufB_reg_n_0_[9]\
    );
\aEobuf[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \aEobuf_reg_n_0_[0]\,
      O => \aEobuf[0]_i_1_n_0\
    );
\aEobuf[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0660"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \aEobuf_reg_n_0_[0]\,
      I3 => \aEobuf_reg_n_0_[1]\,
      O => \aEobuf[1]_i_1_n_0\
    );
\aEobuf[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"06666000"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \aEobuf_reg_n_0_[1]\,
      I3 => \aEobuf_reg_n_0_[0]\,
      I4 => \aEobuf_reg_n_0_[2]\,
      O => \aEobuf[2]_i_1_n_0\
    );
\aEobuf[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0666666660000000"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \aEobuf_reg_n_0_[0]\,
      I3 => \aEobuf_reg_n_0_[1]\,
      I4 => \aEobuf_reg_n_0_[2]\,
      I5 => \aEobuf_reg_n_0_[3]\,
      O => \aEobuf[3]_i_1_n_0\
    );
\aEobuf[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \aEobuf[9]_i_4_n_0\,
      I1 => \aEobuf_reg_n_0_[2]\,
      I2 => \aEobuf_reg_n_0_[1]\,
      I3 => \aEobuf_reg_n_0_[0]\,
      I4 => \aEobuf_reg_n_0_[3]\,
      I5 => \aEobuf_reg_n_0_[4]\,
      O => \aEobuf[4]_i_1_n_0\
    );
\aEobuf[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0660"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \aEobuf[5]_i_2_n_0\,
      I3 => \aEobuf_reg_n_0_[5]\,
      O => \aEobuf[5]_i_1_n_0\
    );
\aEobuf[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aEobuf_reg_n_0_[3]\,
      I1 => \aEobuf_reg_n_0_[0]\,
      I2 => \aEobuf_reg_n_0_[1]\,
      I3 => \aEobuf_reg_n_0_[2]\,
      I4 => \aEobuf_reg_n_0_[4]\,
      O => \aEobuf[5]_i_2_n_0\
    );
\aEobuf[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0660"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \aEobuf[9]_i_5_n_0\,
      I3 => \aEobuf_reg_n_0_[6]\,
      O => \aEobuf[6]_i_1_n_0\
    );
\aEobuf[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"06666000"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \aEobuf[9]_i_5_n_0\,
      I3 => \aEobuf_reg_n_0_[6]\,
      I4 => \aEobuf_reg_n_0_[7]\,
      O => \aEobuf[7]_i_1_n_0\
    );
\aEobuf[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0666666660000000"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \aEobuf_reg_n_0_[6]\,
      I3 => \aEobuf[9]_i_5_n_0\,
      I4 => \aEobuf_reg_n_0_[7]\,
      I5 => \aEobuf_reg_n_0_[8]\,
      O => \aEobuf[8]_i_1_n_0\
    );
\aEobuf[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FD0088"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => camifToVideoinAXIS_tvalid,
      I3 => oddNotEven_reg_0,
      I4 => \aEobuf[9]_i_3_n_0\,
      O => \aEobuf[9]_i_1_n_0\
    );
\aEobuf[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \aEobuf[9]_i_4_n_0\,
      I1 => \aEobuf_reg_n_0_[8]\,
      I2 => \aEobuf_reg_n_0_[7]\,
      I3 => \aEobuf[9]_i_5_n_0\,
      I4 => \aEobuf_reg_n_0_[6]\,
      I5 => \aEobuf_reg_n_0_[9]\,
      O => \aEobuf[9]_i_2_n_0\
    );
\aEobuf[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0101FF01FF010155"
    )
        port map (
      I0 => \aEobuf[9]_i_6_n_0\,
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => \^stateigr_reg[1]_0\(1),
      I3 => klm(1),
      I4 => \^klm_reg[0]_0\(0),
      I5 => klm(2),
      O => \aEobuf[9]_i_3_n_0\
    );
\aEobuf[9]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      O => \aEobuf[9]_i_4_n_0\
    );
\aEobuf[9]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aEobuf_reg_n_0_[4]\,
      I1 => \aEobuf_reg_n_0_[2]\,
      I2 => \aEobuf_reg_n_0_[1]\,
      I3 => \aEobuf_reg_n_0_[0]\,
      I4 => \aEobuf_reg_n_0_[3]\,
      I5 => \aEobuf_reg_n_0_[5]\,
      O => \aEobuf[9]_i_5_n_0\
    );
\aEobuf[9]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => strbEgrstart_i_3_n_0,
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => rawcol_lcl(3),
      I3 => rawcol_lcl(2),
      I4 => strbEgrstart_i_4_n_0,
      O => \aEobuf[9]_i_6_n_0\
    );
\aEobuf_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobuf[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobuf[0]_i_1_n_0\,
      Q => \aEobuf_reg_n_0_[0]\
    );
\aEobuf_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobuf[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobuf[1]_i_1_n_0\,
      Q => \aEobuf_reg_n_0_[1]\
    );
\aEobuf_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobuf[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobuf[2]_i_1_n_0\,
      Q => \aEobuf_reg_n_0_[2]\
    );
\aEobuf_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobuf[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobuf[3]_i_1_n_0\,
      Q => \aEobuf_reg_n_0_[3]\
    );
\aEobuf_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobuf[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobuf[4]_i_1_n_0\,
      Q => \aEobuf_reg_n_0_[4]\
    );
\aEobuf_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobuf[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobuf[5]_i_1_n_0\,
      Q => \aEobuf_reg_n_0_[5]\
    );
\aEobuf_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobuf[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobuf[6]_i_1_n_0\,
      Q => \aEobuf_reg_n_0_[6]\
    );
\aEobuf_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobuf[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobuf[7]_i_1_n_0\,
      Q => \aEobuf_reg_n_0_[7]\
    );
\aEobuf_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobuf[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobuf[8]_i_1_n_0\,
      Q => \aEobuf_reg_n_0_[8]\
    );
\aEobuf_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aEobuf[9]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aEobuf[9]_i_2_n_0\,
      Q => \aEobuf_reg_n_0_[9]\
    );
\aRowbufB[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => stateGrayegr(2),
      I1 => stateGrayegr(1),
      I2 => \aRowbufB_reg_n_0_[0]\,
      O => \aRowbufB[0]_i_1_n_0\
    );
\aRowbufB[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1400"
    )
        port map (
      I0 => stateGrayegr(2),
      I1 => \aRowbufB_reg_n_0_[0]\,
      I2 => \aRowbufB_reg_n_0_[1]\,
      I3 => stateGrayegr(1),
      O => \aRowbufB[1]_i_1_n_0\
    );
\aRowbufB[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04404040"
    )
        port map (
      I0 => stateGrayegr(2),
      I1 => stateGrayegr(1),
      I2 => \aRowbufB_reg_n_0_[2]\,
      I3 => \aRowbufB_reg_n_0_[1]\,
      I4 => \aRowbufB_reg_n_0_[0]\,
      O => \aRowbufB[2]_i_1_n_0\
    );
\aRowbufB[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0440404040404040"
    )
        port map (
      I0 => stateGrayegr(2),
      I1 => stateGrayegr(1),
      I2 => \aRowbufB_reg_n_0_[3]\,
      I3 => \aRowbufB_reg_n_0_[2]\,
      I4 => \aRowbufB_reg_n_0_[0]\,
      I5 => \aRowbufB_reg_n_0_[1]\,
      O => \aRowbufB[3]_i_1_n_0\
    );
\aRowbufB[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0440"
    )
        port map (
      I0 => stateGrayegr(2),
      I1 => stateGrayegr(1),
      I2 => \aRowbufB_reg_n_0_[4]\,
      I3 => \aRowbufB[4]_i_2_n_0\,
      O => \aRowbufB[4]_i_1_n_0\
    );
\aRowbufB[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \aRowbufB_reg_n_0_[2]\,
      I1 => \aRowbufB_reg_n_0_[0]\,
      I2 => \aRowbufB_reg_n_0_[1]\,
      I3 => \aRowbufB_reg_n_0_[3]\,
      O => \aRowbufB[4]_i_2_n_0\
    );
\aRowbufB[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0440"
    )
        port map (
      I0 => stateGrayegr(2),
      I1 => stateGrayegr(1),
      I2 => \aRowbufB_reg_n_0_[5]\,
      I3 => \aRowbufB[5]_i_2_n_0\,
      O => \aRowbufB[5]_i_1_n_0\
    );
\aRowbufB[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aRowbufB_reg_n_0_[3]\,
      I1 => \aRowbufB_reg_n_0_[1]\,
      I2 => \aRowbufB_reg_n_0_[0]\,
      I3 => \aRowbufB_reg_n_0_[2]\,
      I4 => \aRowbufB_reg_n_0_[4]\,
      O => \aRowbufB[5]_i_2_n_0\
    );
\aRowbufB[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0440"
    )
        port map (
      I0 => stateGrayegr(2),
      I1 => stateGrayegr(1),
      I2 => \aRowbufB_reg_n_0_[6]\,
      I3 => \aRowbufB[8]_i_4_n_0\,
      O => \aRowbufB[6]_i_1_n_0\
    );
\aRowbufB[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"14440000"
    )
        port map (
      I0 => stateGrayegr(2),
      I1 => \aRowbufB_reg_n_0_[7]\,
      I2 => \aRowbufB_reg_n_0_[6]\,
      I3 => \aRowbufB[8]_i_4_n_0\,
      I4 => stateGrayegr(1),
      O => \aRowbufB[7]_i_1_n_0\
    );
\aRowbufB[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0300000003035353"
    )
        port map (
      I0 => oddNotEven_reg_0,
      I1 => \aRowbufB[8]_i_3_n_0\,
      I2 => stateGrayegr(2),
      I3 => \^rgbvideointomanyaxis_tvalid\,
      I4 => stateGrayegr(1),
      I5 => stateGrayegr(0),
      O => \aRowbufB[8]_i_1_n_0\
    );
\aRowbufB[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0440404040404040"
    )
        port map (
      I0 => stateGrayegr(2),
      I1 => stateGrayegr(1),
      I2 => \aRowbufB_reg_n_0_[8]\,
      I3 => \aRowbufB[8]_i_4_n_0\,
      I4 => \aRowbufB_reg_n_0_[6]\,
      I5 => \aRowbufB_reg_n_0_[7]\,
      O => \aRowbufB[8]_i_2_n_0\
    );
\aRowbufB[8]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AA2A8AA"
    )
        port map (
      I0 => stateGrayegr(0),
      I1 => \nop_reg_n_0_[0]\,
      I2 => \nop_reg_n_0_[1]\,
      I3 => \nop_reg_n_0_[2]\,
      I4 => \nop_reg_n_0_[3]\,
      O => \aRowbufB[8]_i_3_n_0\
    );
\aRowbufB[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aRowbufB_reg_n_0_[4]\,
      I1 => \aRowbufB_reg_n_0_[2]\,
      I2 => \aRowbufB_reg_n_0_[0]\,
      I3 => \aRowbufB_reg_n_0_[1]\,
      I4 => \aRowbufB_reg_n_0_[3]\,
      I5 => \aRowbufB_reg_n_0_[5]\,
      O => \aRowbufB[8]_i_4_n_0\
    );
\aRowbufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufB[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbufB[0]_i_1_n_0\,
      Q => \aRowbufB_reg_n_0_[0]\
    );
\aRowbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufB[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbufB[1]_i_1_n_0\,
      Q => \aRowbufB_reg_n_0_[1]\
    );
\aRowbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufB[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbufB[2]_i_1_n_0\,
      Q => \aRowbufB_reg_n_0_[2]\
    );
\aRowbufB_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufB[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbufB[3]_i_1_n_0\,
      Q => \aRowbufB_reg_n_0_[3]\
    );
\aRowbufB_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufB[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbufB[4]_i_1_n_0\,
      Q => \aRowbufB_reg_n_0_[4]\
    );
\aRowbufB_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufB[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbufB[5]_i_1_n_0\,
      Q => \aRowbufB_reg_n_0_[5]\
    );
\aRowbufB_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufB[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbufB[6]_i_1_n_0\,
      Q => \aRowbufB_reg_n_0_[6]\
    );
\aRowbufB_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufB[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbufB[7]_i_1_n_0\,
      Q => \aRowbufB_reg_n_0_[7]\
    );
\aRowbufB_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbufB[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbufB[8]_i_2_n_0\,
      Q => \aRowbufB_reg_n_0_[8]\
    );
\aRowbuf[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => stateGraypack(1),
      I2 => \aRowbuf_reg_n_0_[0]\,
      O => aRowbuf(0)
    );
\aRowbuf[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1400"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => \aRowbuf_reg_n_0_[0]\,
      I2 => \aRowbuf_reg_n_0_[1]\,
      I3 => stateGraypack(1),
      O => \aRowbuf[1]_i_1_n_0\
    );
\aRowbuf[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04404040"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => stateGraypack(1),
      I2 => \aRowbuf_reg_n_0_[2]\,
      I3 => \aRowbuf_reg_n_0_[1]\,
      I4 => \aRowbuf_reg_n_0_[0]\,
      O => \aRowbuf[2]_i_1_n_0\
    );
\aRowbuf[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0440404040404040"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => stateGraypack(1),
      I2 => \aRowbuf_reg_n_0_[3]\,
      I3 => \aRowbuf_reg_n_0_[2]\,
      I4 => \aRowbuf_reg_n_0_[0]\,
      I5 => \aRowbuf_reg_n_0_[1]\,
      O => \aRowbuf[3]_i_1_n_0\
    );
\aRowbuf[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0440"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => stateGraypack(1),
      I2 => \aRowbuf_reg_n_0_[4]\,
      I3 => \aRowbuf[4]_i_2_n_0\,
      O => \aRowbuf[4]_i_1_n_0\
    );
\aRowbuf[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \aRowbuf_reg_n_0_[2]\,
      I1 => \aRowbuf_reg_n_0_[0]\,
      I2 => \aRowbuf_reg_n_0_[1]\,
      I3 => \aRowbuf_reg_n_0_[3]\,
      O => \aRowbuf[4]_i_2_n_0\
    );
\aRowbuf[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0440"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => stateGraypack(1),
      I2 => \aRowbuf_reg_n_0_[5]\,
      I3 => \aRowbuf[5]_i_2_n_0\,
      O => \aRowbuf[5]_i_1_n_0\
    );
\aRowbuf[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aRowbuf_reg_n_0_[3]\,
      I1 => \aRowbuf_reg_n_0_[1]\,
      I2 => \aRowbuf_reg_n_0_[0]\,
      I3 => \aRowbuf_reg_n_0_[2]\,
      I4 => \aRowbuf_reg_n_0_[4]\,
      O => \aRowbuf[5]_i_2_n_0\
    );
\aRowbuf[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0440"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => stateGraypack(1),
      I2 => \aRowbuf_reg_n_0_[6]\,
      I3 => \aRowbuf[8]_i_5_n_0\,
      O => \aRowbuf[6]_i_1_n_0\
    );
\aRowbuf[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"14440000"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => \aRowbuf_reg_n_0_[7]\,
      I2 => \aRowbuf_reg_n_0_[6]\,
      I3 => \aRowbuf[8]_i_5_n_0\,
      I4 => stateGraypack(1),
      O => \aRowbuf[7]_i_1_n_0\
    );
\aRowbuf[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF25FF25252525"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => oddNotEven_reg_0,
      I2 => stateGraypack(1),
      I3 => \stateGraypack[0]_i_2_n_0\,
      I4 => \aRowbuf[8]_i_3_n_0\,
      I5 => \aRowbuf[8]_i_4_n_0\,
      O => \aRowbuf[8]_i_1_n_0\
    );
\aRowbuf[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0440404040404040"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => stateGraypack(1),
      I2 => \aRowbuf_reg_n_0_[8]\,
      I3 => \aRowbuf[8]_i_5_n_0\,
      I4 => \aRowbuf_reg_n_0_[6]\,
      I5 => \aRowbuf_reg_n_0_[7]\,
      O => \aRowbuf[8]_i_2_n_0\
    );
\aRowbuf[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFB"
    )
        port map (
      I0 => \col_lcl_reg[9]__1_n_0\,
      I1 => \aRowbuf[8]_i_6_n_0\,
      I2 => \col_lcl_reg[6]__1_n_0\,
      I3 => \col_lcl[8]__1_i_2_n_0\,
      I4 => \col_lcl_reg[7]__1_n_0\,
      I5 => \col_lcl_reg[8]__1_n_0\,
      O => \aRowbuf[8]_i_3_n_0\
    );
\aRowbuf[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400000000004004"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => \^rgbvideointomanyaxis_tvalid\,
      I2 => \tuv_reg_n_0_[2]\,
      I3 => \tuv_reg_n_0_[1]\,
      I4 => \tuv_reg_n_0_[0]\,
      I5 => \tuv_reg_n_0_[3]\,
      O => \aRowbuf[8]_i_4_n_0\
    );
\aRowbuf[8]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aRowbuf_reg_n_0_[4]\,
      I1 => \aRowbuf_reg_n_0_[2]\,
      I2 => \aRowbuf_reg_n_0_[0]\,
      I3 => \aRowbuf_reg_n_0_[1]\,
      I4 => \aRowbuf_reg_n_0_[3]\,
      I5 => \aRowbuf_reg_n_0_[5]\,
      O => \aRowbuf[8]_i_5_n_0\
    );
\aRowbuf[8]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000045555155"
    )
        port map (
      I0 => \aRowbuf[8]_i_7_n_0\,
      I1 => \tuv_reg_n_0_[2]\,
      I2 => \tuv_reg_n_0_[0]\,
      I3 => \tuv_reg_n_0_[1]\,
      I4 => \tuv_reg_n_0_[3]\,
      I5 => \col_lcl[5]__1_i_2_n_0\,
      O => \aRowbuf[8]_i_6_n_0\
    );
\aRowbuf[8]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \col_lcl_reg[1]__1_n_0\,
      I1 => \col_lcl_reg[0]__1_n_0\,
      I2 => \col_lcl_reg[3]__1_n_0\,
      I3 => \col_lcl_reg[4]__1_n_0\,
      I4 => \col_lcl_reg[2]__1_n_0\,
      O => \aRowbuf[8]_i_7_n_0\
    );
\aRowbuf_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbuf[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => aRowbuf(0),
      Q => \aRowbuf_reg_n_0_[0]\
    );
\aRowbuf_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbuf[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbuf[1]_i_1_n_0\,
      Q => \aRowbuf_reg_n_0_[1]\
    );
\aRowbuf_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbuf[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbuf[2]_i_1_n_0\,
      Q => \aRowbuf_reg_n_0_[2]\
    );
\aRowbuf_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbuf[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbuf[3]_i_1_n_0\,
      Q => \aRowbuf_reg_n_0_[3]\
    );
\aRowbuf_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbuf[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbuf[4]_i_1_n_0\,
      Q => \aRowbuf_reg_n_0_[4]\
    );
\aRowbuf_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbuf[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbuf[5]_i_1_n_0\,
      Q => \aRowbuf_reg_n_0_[5]\
    );
\aRowbuf_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbuf[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbuf[6]_i_1_n_0\,
      Q => \aRowbuf_reg_n_0_[6]\
    );
\aRowbuf_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbuf[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbuf[7]_i_1_n_0\,
      Q => \aRowbuf_reg_n_0_[7]\
    );
\aRowbuf_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aRowbuf[8]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \aRowbuf[8]_i_2_n_0\,
      Q => \aRowbuf_reg_n_0_[8]\
    );
\abcde[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"080A"
    )
        port map (
      I0 => stateGrayegr(2),
      I1 => \abcde_reg_n_0_[1]\,
      I2 => \abcde_reg_n_0_[0]\,
      I3 => \abcde_reg_n_0_[2]\,
      O => \abcde[0]_i_1__0_n_0\
    );
\abcde[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \abcde_reg_n_0_[1]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => stateGrayegr(2),
      O => abcde(1)
    );
\abcde[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0103"
    )
        port map (
      I0 => oddNotEven_reg_0,
      I1 => stateGrayegr(1),
      I2 => stateGrayegr(0),
      I3 => stateGrayegr(2),
      O => \abcde[2]_i_1__0_n_0\
    );
\abcde[2]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2880"
    )
        port map (
      I0 => stateGrayegr(2),
      I1 => \abcde_reg_n_0_[2]\,
      I2 => \abcde_reg_n_0_[1]\,
      I3 => \abcde_reg_n_0_[0]\,
      O => \abcde[2]_i_2__0_n_0\
    );
\abcde_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \abcde[2]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \abcde[0]_i_1__0_n_0\,
      Q => \abcde_reg_n_0_[0]\
    );
\abcde_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \abcde[2]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => abcde(1),
      Q => \abcde_reg_n_0_[1]\
    );
\abcde_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \abcde[2]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \abcde[2]_i_2__0_n_0\,
      Q => \abcde_reg_n_0_[2]\
    );
\acc0_lcl[15]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(11),
      I1 => enAccbuf_reg,
      I2 => \^abcde_reg[0]_0\(7),
      O => DI(3)
    );
\acc0_lcl[15]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(10),
      I1 => enAccbuf_reg,
      I2 => \^abcde_reg[0]_0\(6),
      O => DI(2)
    );
\acc0_lcl[15]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(9),
      I1 => enAccbuf_reg,
      I2 => \^abcde_reg[0]_0\(5),
      O => DI(1)
    );
\acc0_lcl[15]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(8),
      I1 => enAccbuf_reg,
      I2 => \^abcde_reg[0]_0\(4),
      O => DI(0)
    );
\acc0_lcl[7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF000002AA02AA"
    )
        port map (
      I0 => p_14_in(0),
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \abcde_reg_n_0_[1]\,
      I3 => \abcde_reg_n_0_[2]\,
      I4 => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(0),
      I5 => enAccbuf_reg,
      O => \^rgbtomanyaxis_tdata_sig_reg[7]_0\(0)
    );
\acc0_lcl[7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(7),
      I1 => enAccbuf_reg,
      I2 => \^abcde_reg[0]_0\(3),
      O => \^rgbtomanyaxis_tdata_sig_reg[7]_0\(7)
    );
\acc0_lcl[7]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(6),
      I1 => enAccbuf_reg,
      I2 => \^abcde_reg[0]_0\(2),
      O => \^rgbtomanyaxis_tdata_sig_reg[7]_0\(6)
    );
\acc0_lcl[7]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(5),
      I1 => enAccbuf_reg,
      I2 => \^abcde_reg[0]_0\(1),
      O => \^rgbtomanyaxis_tdata_sig_reg[7]_0\(5)
    );
\acc0_lcl[7]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(4),
      I1 => enAccbuf_reg,
      I2 => \^abcde_reg[0]_0\(0),
      O => \^rgbtomanyaxis_tdata_sig_reg[7]_0\(4)
    );
\acc0_lcl[7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF000002AA02AA"
    )
        port map (
      I0 => p_14_in(3),
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \abcde_reg_n_0_[1]\,
      I3 => \abcde_reg_n_0_[2]\,
      I4 => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(3),
      I5 => enAccbuf_reg,
      O => \^rgbtomanyaxis_tdata_sig_reg[7]_0\(3)
    );
\acc0_lcl[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF000002AA02AA"
    )
        port map (
      I0 => p_14_in(2),
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \abcde_reg_n_0_[1]\,
      I3 => \abcde_reg_n_0_[2]\,
      I4 => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(2),
      I5 => enAccbuf_reg,
      O => \^rgbtomanyaxis_tdata_sig_reg[7]_0\(2)
    );
\acc0_lcl[7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF000002AA02AA"
    )
        port map (
      I0 => p_14_in(1),
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \abcde_reg_n_0_[1]\,
      I3 => \abcde_reg_n_0_[2]\,
      I4 => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(1),
      I5 => enAccbuf_reg,
      O => \^rgbtomanyaxis_tdata_sig_reg[7]_0\(1)
    );
\acc0_lcl_reg[7]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7) => \rgbToManyAXIS_tdata_sig_reg[7]_1\(0),
      CO(6) => \acc0_lcl_reg[7]_i_2_n_1\,
      CO(5) => \acc0_lcl_reg[7]_i_2_n_2\,
      CO(4) => \acc0_lcl_reg[7]_i_2_n_3\,
      CO(3) => \acc0_lcl_reg[7]_i_2_n_4\,
      CO(2) => \acc0_lcl_reg[7]_i_2_n_5\,
      CO(1) => \acc0_lcl_reg[7]_i_2_n_6\,
      CO(0) => \acc0_lcl_reg[7]_i_2_n_7\,
      DI(7 downto 0) => \^rgbtomanyaxis_tdata_sig_reg[7]_0\(7 downto 0),
      O(7 downto 0) => O(7 downto 0),
      S(7 downto 0) => \dwrAccbuf_reg[7]\(7 downto 0)
    );
\acc2[19]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E200"
    )
        port map (
      I0 => \^grayvideointomanyaxis_tvalid\,
      I1 => enAccbuf_reg,
      I2 => \^rgbvideointomanyaxis_tvalid\,
      I3 => enAccbuf0,
      O => grayToManyAXIS_tvalid_sig_reg_0
    );
\col_lcl[0]__0_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => stateGrayegr(1),
      I1 => stateGrayegr(0),
      I2 => stateGrayegr(2),
      I3 => \col_lcl_reg[0]__0_n_0\,
      O => \col_lcl[0]__0_i_1__0_n_0\
    );
\col_lcl[0]__1_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => stateGraypack(1),
      I2 => \col_lcl_reg[0]__1_n_0\,
      O => col_lcl(0)
    );
\col_lcl[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I3 => \^q\(0),
      O => \col_lcl[0]_i_1__1_n_0\
    );
\col_lcl[10]__0_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => stateGrayegr(1),
      I1 => stateGrayegr(0),
      I2 => stateGrayegr(2),
      I3 => \col_lcl[10]__0_i_2__0_n_0\,
      O => \col_lcl[10]__0_i_1__0_n_0\
    );
\col_lcl[10]__0_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555555"
    )
        port map (
      I0 => \col_lcl_reg[10]__0_n_0\,
      I1 => \col_lcl_reg[8]__0_n_0\,
      I2 => \col_lcl_reg[6]__0_n_0\,
      I3 => \col_lcl[9]__0_i_2__0_n_0\,
      I4 => \col_lcl_reg[7]__0_n_0\,
      I5 => \col_lcl_reg[9]__0_n_0\,
      O => \col_lcl[10]__0_i_2__0_n_0\
    );
\col_lcl[10]__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0CBB"
    )
        port map (
      I0 => \^rgbvideointomanyaxis_tvalid\,
      I1 => stateGraypack(1),
      I2 => oddNotEven_reg_0,
      I3 => stateGraypack(0),
      O => \col_lcl[10]__1_i_1_n_0\
    );
\col_lcl[10]__1_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => stateGraypack(1),
      I2 => \stateGraypack[0]_i_2_n_0\,
      O => col_lcl(10)
    );
\col_lcl[10]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I3 => \col_lcl[10]_i_2__1_n_0\,
      O => \col_lcl[10]_i_1__1_n_0\
    );
\col_lcl[10]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555555"
    )
        port map (
      I0 => \col_lcl_reg_n_0_[10]\,
      I1 => \col_lcl_reg_n_0_[8]\,
      I2 => \^q\(3),
      I3 => \^col_lcl_reg[5]_0\,
      I4 => \^q\(4),
      I5 => \col_lcl_reg_n_0_[9]\,
      O => \col_lcl[10]_i_2__1_n_0\
    );
\col_lcl[1]__0_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080800"
    )
        port map (
      I0 => stateGrayegr(1),
      I1 => stateGrayegr(0),
      I2 => stateGrayegr(2),
      I3 => \col_lcl_reg[1]__0_n_0\,
      I4 => \col_lcl_reg[0]__0_n_0\,
      O => \col_lcl[1]__0_i_1__0_n_0\
    );
\col_lcl[1]__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0440"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => stateGraypack(1),
      I2 => \col_lcl_reg[1]__1_n_0\,
      I3 => \col_lcl_reg[0]__1_n_0\,
      O => col_lcl(1)
    );
\col_lcl[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080800"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \col_lcl[1]_i_1__1_n_0\
    );
\col_lcl[2]__0_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008080808000000"
    )
        port map (
      I0 => stateGrayegr(1),
      I1 => stateGrayegr(0),
      I2 => stateGrayegr(2),
      I3 => \col_lcl_reg[0]__0_n_0\,
      I4 => \col_lcl_reg[1]__0_n_0\,
      I5 => \col_lcl_reg[2]__0_n_0\,
      O => \col_lcl[2]__0_i_1__0_n_0\
    );
\col_lcl[2]__1_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00780000"
    )
        port map (
      I0 => \col_lcl_reg[0]__1_n_0\,
      I1 => \col_lcl_reg[1]__1_n_0\,
      I2 => \col_lcl_reg[2]__1_n_0\,
      I3 => stateGraypack(0),
      I4 => stateGraypack(1),
      O => \col_lcl[2]__1_i_1_n_0\
    );
\col_lcl[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008080808000000"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \col_lcl[2]_i_1__1_n_0\
    );
\col_lcl[3]__0_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F800000"
    )
        port map (
      I0 => \col_lcl_reg[2]__0_n_0\,
      I1 => \col_lcl_reg[1]__0_n_0\,
      I2 => \col_lcl_reg[0]__0_n_0\,
      I3 => \col_lcl_reg[3]__0_n_0\,
      I4 => \nop[3]_i_3_n_0\,
      O => \col_lcl[3]__0_i_1__0_n_0\
    );
\col_lcl[3]__1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007F8000000000"
    )
        port map (
      I0 => \col_lcl_reg[2]__1_n_0\,
      I1 => \col_lcl_reg[1]__1_n_0\,
      I2 => \col_lcl_reg[0]__1_n_0\,
      I3 => \col_lcl_reg[3]__1_n_0\,
      I4 => stateGraypack(0),
      I5 => stateGraypack(1),
      O => \col_lcl[3]__1_i_1_n_0\
    );
\col_lcl[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F800000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \col_lcl_reg_n_0_[3]\,
      I4 => \FSM_sequential_stateRgbegr[2]_i_2_n_0\,
      O => \col_lcl[3]_i_1__1_n_0\
    );
\col_lcl[4]__0_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF800000000000"
    )
        port map (
      I0 => \col_lcl_reg[3]__0_n_0\,
      I1 => \col_lcl_reg[0]__0_n_0\,
      I2 => \col_lcl_reg[1]__0_n_0\,
      I3 => \col_lcl_reg[2]__0_n_0\,
      I4 => \col_lcl_reg[4]__0_n_0\,
      I5 => \nop[3]_i_3_n_0\,
      O => \col_lcl[4]__0_i_1__0_n_0\
    );
\col_lcl[4]__1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF800000000000"
    )
        port map (
      I0 => \col_lcl_reg[3]__1_n_0\,
      I1 => \col_lcl_reg[0]__1_n_0\,
      I2 => \col_lcl_reg[1]__1_n_0\,
      I3 => \col_lcl_reg[2]__1_n_0\,
      I4 => \col_lcl_reg[4]__1_n_0\,
      I5 => \col_lcl[4]__1_i_2_n_0\,
      O => \col_lcl[4]__1_i_1_n_0\
    );
\col_lcl[4]__1_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => stateGraypack(1),
      I1 => stateGraypack(0),
      O => \col_lcl[4]__1_i_2_n_0\
    );
\col_lcl[4]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF800000000000"
    )
        port map (
      I0 => \col_lcl_reg_n_0_[3]\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \col_lcl_reg_n_0_[4]\,
      I5 => \FSM_sequential_stateRgbegr[2]_i_2_n_0\,
      O => \col_lcl[4]_i_1__1_n_0\
    );
\col_lcl[5]__0_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \col_lcl[5]__0_i_2__0_n_0\,
      I1 => stateGrayegr(1),
      I2 => stateGrayegr(0),
      I3 => stateGrayegr(2),
      O => \col_lcl[5]__0_i_1__0_n_0\
    );
\col_lcl[5]__0_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \col_lcl_reg[5]__0_n_0\,
      I1 => \col_lcl_reg[3]__0_n_0\,
      I2 => \col_lcl_reg[0]__0_n_0\,
      I3 => \col_lcl_reg[1]__0_n_0\,
      I4 => \col_lcl_reg[2]__0_n_0\,
      I5 => \col_lcl_reg[4]__0_n_0\,
      O => \col_lcl[5]__0_i_2__0_n_0\
    );
\col_lcl[5]__1_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \col_lcl[5]__1_i_2_n_0\,
      I1 => stateGraypack(0),
      I2 => stateGraypack(1),
      O => \col_lcl[5]__1_i_1_n_0\
    );
\col_lcl[5]__1_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \col_lcl_reg[5]__1_n_0\,
      I1 => \col_lcl_reg[3]__1_n_0\,
      I2 => \col_lcl_reg[0]__1_n_0\,
      I3 => \col_lcl_reg[1]__1_n_0\,
      I4 => \col_lcl_reg[2]__1_n_0\,
      I5 => \col_lcl_reg[4]__1_n_0\,
      O => \col_lcl[5]__1_i_2_n_0\
    );
\col_lcl[5]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \^col_lcl_reg[5]_1\,
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I3 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      O => \col_lcl[5]_i_1__1_n_0\
    );
\col_lcl[5]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \col_lcl_reg_n_0_[5]\,
      I1 => \col_lcl_reg_n_0_[3]\,
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \col_lcl_reg_n_0_[4]\,
      O => \^col_lcl_reg[5]_1\
    );
\col_lcl[6]__0_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006000"
    )
        port map (
      I0 => \col_lcl[9]__0_i_2__0_n_0\,
      I1 => \col_lcl_reg[6]__0_n_0\,
      I2 => stateGrayegr(1),
      I3 => stateGrayegr(0),
      I4 => stateGrayegr(2),
      O => \col_lcl[6]__0_i_1__0_n_0\
    );
\col_lcl[6]__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0600"
    )
        port map (
      I0 => \col_lcl[8]__1_i_2_n_0\,
      I1 => \col_lcl_reg[6]__1_n_0\,
      I2 => stateGraypack(0),
      I3 => stateGraypack(1),
      O => \col_lcl[6]__1_i_1_n_0\
    );
\col_lcl[6]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006000"
    )
        port map (
      I0 => \^col_lcl_reg[5]_0\,
      I1 => \^q\(3),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I3 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I4 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      O => \col_lcl[6]_i_1__1_n_0\
    );
\col_lcl[7]__0_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000078000000"
    )
        port map (
      I0 => \col_lcl_reg[6]__0_n_0\,
      I1 => \col_lcl[9]__0_i_2__0_n_0\,
      I2 => \col_lcl_reg[7]__0_n_0\,
      I3 => stateGrayegr(1),
      I4 => stateGrayegr(0),
      I5 => stateGrayegr(2),
      O => \col_lcl[7]__0_i_1__0_n_0\
    );
\col_lcl[7]__1_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00780000"
    )
        port map (
      I0 => \col_lcl_reg[6]__1_n_0\,
      I1 => \col_lcl[8]__1_i_2_n_0\,
      I2 => \col_lcl_reg[7]__1_n_0\,
      I3 => stateGraypack(0),
      I4 => stateGraypack(1),
      O => \col_lcl[7]__1_i_1_n_0\
    );
\col_lcl[7]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000078000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^col_lcl_reg[5]_0\,
      I2 => \^q\(4),
      I3 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I4 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I5 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      O => \col_lcl[7]_i_1__1_n_0\
    );
\col_lcl[8]__0_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F800000"
    )
        port map (
      I0 => \col_lcl_reg[7]__0_n_0\,
      I1 => \col_lcl[9]__0_i_2__0_n_0\,
      I2 => \col_lcl_reg[6]__0_n_0\,
      I3 => \col_lcl_reg[8]__0_n_0\,
      I4 => \nop[3]_i_3_n_0\,
      O => \col_lcl[8]__0_i_1__0_n_0\
    );
\col_lcl[8]__1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0444444440000000"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => stateGraypack(1),
      I2 => \col_lcl_reg[7]__1_n_0\,
      I3 => \col_lcl[8]__1_i_2_n_0\,
      I4 => \col_lcl_reg[6]__1_n_0\,
      I5 => \col_lcl_reg[8]__1_n_0\,
      O => col_lcl(8)
    );
\col_lcl[8]__1_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \col_lcl_reg[5]__1_n_0\,
      I1 => \col_lcl_reg[3]__1_n_0\,
      I2 => \col_lcl_reg[0]__1_n_0\,
      I3 => \col_lcl_reg[1]__1_n_0\,
      I4 => \col_lcl_reg[2]__1_n_0\,
      I5 => \col_lcl_reg[4]__1_n_0\,
      O => \col_lcl[8]__1_i_2_n_0\
    );
\col_lcl[8]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F800000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^col_lcl_reg[5]_0\,
      I2 => \^q\(3),
      I3 => \col_lcl_reg_n_0_[8]\,
      I4 => \FSM_sequential_stateRgbegr[2]_i_2_n_0\,
      O => \col_lcl[8]_i_1__1_n_0\
    );
\col_lcl[9]__0_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF800000000000"
    )
        port map (
      I0 => \col_lcl_reg[8]__0_n_0\,
      I1 => \col_lcl_reg[6]__0_n_0\,
      I2 => \col_lcl[9]__0_i_2__0_n_0\,
      I3 => \col_lcl_reg[7]__0_n_0\,
      I4 => \col_lcl_reg[9]__0_n_0\,
      I5 => \nop[3]_i_3_n_0\,
      O => \col_lcl[9]__0_i_1__0_n_0\
    );
\col_lcl[9]__0_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \col_lcl_reg[5]__0_n_0\,
      I1 => \col_lcl_reg[3]__0_n_0\,
      I2 => \col_lcl_reg[0]__0_n_0\,
      I3 => \col_lcl_reg[1]__0_n_0\,
      I4 => \col_lcl_reg[2]__0_n_0\,
      I5 => \col_lcl_reg[4]__0_n_0\,
      O => \col_lcl[9]__0_i_2__0_n_0\
    );
\col_lcl[9]__1_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \col_lcl[9]__1_i_2_n_0\,
      I1 => stateGraypack(0),
      I2 => stateGraypack(1),
      O => \col_lcl[9]__1_i_1_n_0\
    );
\col_lcl[9]__1_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \col_lcl_reg[9]__1_n_0\,
      I1 => \col_lcl_reg[7]__1_n_0\,
      I2 => \col_lcl[8]__1_i_2_n_0\,
      I3 => \col_lcl_reg[6]__1_n_0\,
      I4 => \col_lcl_reg[8]__1_n_0\,
      O => \col_lcl[9]__1_i_2_n_0\
    );
\col_lcl[9]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFF800000000000"
    )
        port map (
      I0 => \col_lcl_reg_n_0_[8]\,
      I1 => \^q\(3),
      I2 => \^col_lcl_reg[5]_0\,
      I3 => \^q\(4),
      I4 => \col_lcl_reg_n_0_[9]\,
      I5 => \FSM_sequential_stateRgbegr[2]_i_2_n_0\,
      O => \col_lcl[9]_i_1__1_n_0\
    );
\col_lcl[9]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \col_lcl_reg_n_0_[5]\,
      I1 => \col_lcl_reg_n_0_[3]\,
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \col_lcl_reg_n_0_[4]\,
      O => \^col_lcl_reg[5]_0\
    );
\col_lcl_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \qrs[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[0]_i_1__1_n_0\,
      Q => \^q\(0)
    );
\col_lcl_reg[0]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[0]__0_i_1__0_n_0\,
      Q => \col_lcl_reg[0]__0_n_0\
    );
\col_lcl_reg[0]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => col_lcl(0),
      Q => \col_lcl_reg[0]__1_n_0\
    );
\col_lcl_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \qrs[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[10]_i_1__1_n_0\,
      Q => \col_lcl_reg_n_0_[10]\
    );
\col_lcl_reg[10]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[10]__0_i_1__0_n_0\,
      Q => \col_lcl_reg[10]__0_n_0\
    );
\col_lcl_reg[10]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => col_lcl(10),
      Q => \col_lcl_reg[10]__1_n_0\
    );
\col_lcl_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \qrs[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[1]_i_1__1_n_0\,
      Q => \^q\(1)
    );
\col_lcl_reg[1]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[1]__0_i_1__0_n_0\,
      Q => \col_lcl_reg[1]__0_n_0\
    );
\col_lcl_reg[1]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => col_lcl(1),
      Q => \col_lcl_reg[1]__1_n_0\
    );
\col_lcl_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \qrs[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[2]_i_1__1_n_0\,
      Q => \^q\(2)
    );
\col_lcl_reg[2]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[2]__0_i_1__0_n_0\,
      Q => \col_lcl_reg[2]__0_n_0\
    );
\col_lcl_reg[2]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[2]__1_i_1_n_0\,
      Q => \col_lcl_reg[2]__1_n_0\
    );
\col_lcl_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \qrs[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[3]_i_1__1_n_0\,
      Q => \col_lcl_reg_n_0_[3]\
    );
\col_lcl_reg[3]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[3]__0_i_1__0_n_0\,
      Q => \col_lcl_reg[3]__0_n_0\
    );
\col_lcl_reg[3]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[3]__1_i_1_n_0\,
      Q => \col_lcl_reg[3]__1_n_0\
    );
\col_lcl_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \qrs[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[4]_i_1__1_n_0\,
      Q => \col_lcl_reg_n_0_[4]\
    );
\col_lcl_reg[4]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[4]__0_i_1__0_n_0\,
      Q => \col_lcl_reg[4]__0_n_0\
    );
\col_lcl_reg[4]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[4]__1_i_1_n_0\,
      Q => \col_lcl_reg[4]__1_n_0\
    );
\col_lcl_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \qrs[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[5]_i_1__1_n_0\,
      Q => \col_lcl_reg_n_0_[5]\
    );
\col_lcl_reg[5]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[5]__0_i_1__0_n_0\,
      Q => \col_lcl_reg[5]__0_n_0\
    );
\col_lcl_reg[5]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[5]__1_i_1_n_0\,
      Q => \col_lcl_reg[5]__1_n_0\
    );
\col_lcl_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \qrs[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[6]_i_1__1_n_0\,
      Q => \^q\(3)
    );
\col_lcl_reg[6]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[6]__0_i_1__0_n_0\,
      Q => \col_lcl_reg[6]__0_n_0\
    );
\col_lcl_reg[6]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[6]__1_i_1_n_0\,
      Q => \col_lcl_reg[6]__1_n_0\
    );
\col_lcl_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \qrs[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[7]_i_1__1_n_0\,
      Q => \^q\(4)
    );
\col_lcl_reg[7]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[7]__0_i_1__0_n_0\,
      Q => \col_lcl_reg[7]__0_n_0\
    );
\col_lcl_reg[7]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[7]__1_i_1_n_0\,
      Q => \col_lcl_reg[7]__1_n_0\
    );
\col_lcl_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \qrs[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[8]_i_1__1_n_0\,
      Q => \col_lcl_reg_n_0_[8]\
    );
\col_lcl_reg[8]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[8]__0_i_1__0_n_0\,
      Q => \col_lcl_reg[8]__0_n_0\
    );
\col_lcl_reg[8]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => col_lcl(8),
      Q => \col_lcl_reg[8]__1_n_0\
    );
\col_lcl_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \qrs[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[9]_i_1__1_n_0\,
      Q => \col_lcl_reg_n_0_[9]\
    );
\col_lcl_reg[9]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[9]__0_i_1__0_n_0\,
      Q => \col_lcl_reg[9]__0_n_0\
    );
\col_lcl_reg[9]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \col_lcl[9]__1_i_1_n_0\,
      Q => \col_lcl_reg[9]__1_n_0\
    );
\dIgrm1[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"02AA"
    )
        port map (
      I0 => p_14_in(4),
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \abcde_reg_n_0_[1]\,
      I3 => \abcde_reg_n_0_[2]\,
      O => \^abcde_reg[0]_0\(0)
    );
\dIgrm1[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr3_reg_n_0_[6]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[34]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[26]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(10)
    );
\dIgrm1[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr3_reg_n_0_[7]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[35]_i_4_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[27]_i_3_n_0\,
      O => \^abcde_reg[0]_0\(11)
    );
\dIgrm1[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr3_reg_n_0_[8]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[36]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[28]_i_3_n_0\,
      O => \^abcde_reg[0]_0\(12)
    );
\dIgrm1[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr3_reg_n_0_[9]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[29]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[37]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(13)
    );
\dIgrm1[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr3_reg_n_0_[10]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[30]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[38]_i_3_n_0\,
      O => \^abcde_reg[0]_0\(14)
    );
\dIgrm1[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr3_reg_n_0_[11]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[39]_i_5_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[31]_i_3_n_0\,
      O => \^abcde_reg[0]_0\(15)
    );
\dIgrm1[16]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr2_reg_n_0_[4]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[16]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[32]_i_3_n_0\,
      O => \^abcde_reg[0]_0\(16)
    );
\dIgrm1[16]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr1_reg_n_0_[4]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr0_reg_n_0_[4]\,
      O => \dIgrm1[16]_i_3_n_0\
    );
\dIgrm1[17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr2_reg_n_0_[5]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[17]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[33]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(17)
    );
\dIgrm1[17]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr1_reg_n_0_[5]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr0_reg_n_0_[5]\,
      O => \dIgrm1[17]_i_3_n_0\
    );
\dIgrm1[18]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr2_reg_n_0_[6]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[18]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[34]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(18)
    );
\dIgrm1[18]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr1_reg_n_0_[6]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr0_reg_n_0_[6]\,
      O => \dIgrm1[18]_i_3_n_0\
    );
\dIgrm1[19]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr2_reg_n_0_[7]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[35]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[19]_i_3_n_0\,
      O => \^abcde_reg[0]_0\(19)
    );
\dIgrm1[19]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr1_reg_n_0_[7]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr0_reg_n_0_[7]\,
      O => \dIgrm1[19]_i_3_n_0\
    );
\dIgrm1[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"02AA"
    )
        port map (
      I0 => p_14_in(5),
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \abcde_reg_n_0_[1]\,
      I3 => \abcde_reg_n_0_[2]\,
      O => \^abcde_reg[0]_0\(1)
    );
\dIgrm1[20]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr2_reg_n_0_[8]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[20]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[36]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(20)
    );
\dIgrm1[20]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr1_reg_n_0_[8]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr0_reg_n_0_[8]\,
      O => \dIgrm1[20]_i_3_n_0\
    );
\dIgrm1[21]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr2_reg_n_0_[9]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[37]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[21]_i_3_n_0\,
      O => \^abcde_reg[0]_0\(21)
    );
\dIgrm1[21]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr1_reg_n_0_[9]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr0_reg_n_0_[9]\,
      O => \dIgrm1[21]_i_3_n_0\
    );
\dIgrm1[22]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr2_reg_n_0_[10]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[22]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[38]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(22)
    );
\dIgrm1[22]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr1_reg_n_0_[10]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr0_reg_n_0_[10]\,
      O => \dIgrm1[22]_i_3_n_0\
    );
\dIgrm1[23]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr2_reg_n_0_[11]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[39]_i_4_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[23]_i_3_n_0\,
      O => \^abcde_reg[0]_0\(23)
    );
\dIgrm1[23]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr1_reg_n_0_[11]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr0_reg_n_0_[11]\,
      O => \dIgrm1[23]_i_3_n_0\
    );
\dIgrm1[24]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr1_reg_n_0_[4]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[24]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[24]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(24)
    );
\dIgrm1[24]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr3_reg_n_0_[4]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr2_reg_n_0_[4]\,
      O => \dIgrm1[24]_i_3_n_0\
    );
\dIgrm1[24]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr0_reg_n_0_[4]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr4_reg_n_0_[4]\,
      O => \dIgrm1[24]_i_4_n_0\
    );
\dIgrm1[25]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr1_reg_n_0_[5]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[25]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[25]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(25)
    );
\dIgrm1[25]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr3_reg_n_0_[5]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr2_reg_n_0_[5]\,
      O => \dIgrm1[25]_i_3_n_0\
    );
\dIgrm1[25]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr0_reg_n_0_[5]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr4_reg_n_0_[5]\,
      O => \dIgrm1[25]_i_4_n_0\
    );
\dIgrm1[26]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr1_reg_n_0_[6]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[26]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[26]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(26)
    );
\dIgrm1[26]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr3_reg_n_0_[6]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr2_reg_n_0_[6]\,
      O => \dIgrm1[26]_i_3_n_0\
    );
\dIgrm1[26]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr0_reg_n_0_[6]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr4_reg_n_0_[6]\,
      O => \dIgrm1[26]_i_4_n_0\
    );
\dIgrm1[27]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr1_reg_n_0_[7]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[27]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[27]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(27)
    );
\dIgrm1[27]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr0_reg_n_0_[7]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr4_reg_n_0_[7]\,
      O => \dIgrm1[27]_i_3_n_0\
    );
\dIgrm1[27]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr3_reg_n_0_[7]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr2_reg_n_0_[7]\,
      O => \dIgrm1[27]_i_4_n_0\
    );
\dIgrm1[28]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr1_reg_n_0_[8]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[28]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[28]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(28)
    );
\dIgrm1[28]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr0_reg_n_0_[8]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr4_reg_n_0_[8]\,
      O => \dIgrm1[28]_i_3_n_0\
    );
\dIgrm1[28]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr3_reg_n_0_[8]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr2_reg_n_0_[8]\,
      O => \dIgrm1[28]_i_4_n_0\
    );
\dIgrm1[29]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr1_reg_n_0_[9]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[29]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[29]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(29)
    );
\dIgrm1[29]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr0_reg_n_0_[9]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr4_reg_n_0_[9]\,
      O => \dIgrm1[29]_i_3_n_0\
    );
\dIgrm1[29]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr3_reg_n_0_[9]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr2_reg_n_0_[9]\,
      O => \dIgrm1[29]_i_4_n_0\
    );
\dIgrm1[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"02AA"
    )
        port map (
      I0 => p_14_in(6),
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \abcde_reg_n_0_[1]\,
      I3 => \abcde_reg_n_0_[2]\,
      O => \^abcde_reg[0]_0\(2)
    );
\dIgrm1[30]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr1_reg_n_0_[10]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[30]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[30]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(30)
    );
\dIgrm1[30]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr0_reg_n_0_[10]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr4_reg_n_0_[10]\,
      O => \dIgrm1[30]_i_3_n_0\
    );
\dIgrm1[30]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr3_reg_n_0_[10]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr2_reg_n_0_[10]\,
      O => \dIgrm1[30]_i_4_n_0\
    );
\dIgrm1[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr1_reg_n_0_[11]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[31]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[31]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(31)
    );
\dIgrm1[31]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr0_reg_n_0_[11]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr4_reg_n_0_[11]\,
      O => \dIgrm1[31]_i_3_n_0\
    );
\dIgrm1[31]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr3_reg_n_0_[11]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr2_reg_n_0_[11]\,
      O => \dIgrm1[31]_i_4_n_0\
    );
\dIgrm1[32]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr0_reg_n_0_[4]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[32]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[32]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(32)
    );
\dIgrm1[32]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr4_reg_n_0_[4]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr3_reg_n_0_[4]\,
      O => \dIgrm1[32]_i_3_n_0\
    );
\dIgrm1[32]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr2_reg_n_0_[4]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr1_reg_n_0_[4]\,
      O => \dIgrm1[32]_i_4_n_0\
    );
\dIgrm1[33]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr0_reg_n_0_[5]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[33]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[33]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(33)
    );
\dIgrm1[33]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr2_reg_n_0_[5]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr1_reg_n_0_[5]\,
      O => \dIgrm1[33]_i_3_n_0\
    );
\dIgrm1[33]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr4_reg_n_0_[5]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr3_reg_n_0_[5]\,
      O => \dIgrm1[33]_i_4_n_0\
    );
\dIgrm1[34]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr0_reg_n_0_[6]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[34]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[34]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(34)
    );
\dIgrm1[34]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr2_reg_n_0_[6]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr1_reg_n_0_[6]\,
      O => \dIgrm1[34]_i_3_n_0\
    );
\dIgrm1[34]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr4_reg_n_0_[6]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr3_reg_n_0_[6]\,
      O => \dIgrm1[34]_i_4_n_0\
    );
\dIgrm1[35]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr0_reg_n_0_[7]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[35]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[35]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(35)
    );
\dIgrm1[35]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr4_reg_n_0_[7]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr3_reg_n_0_[7]\,
      O => \dIgrm1[35]_i_3_n_0\
    );
\dIgrm1[35]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr2_reg_n_0_[7]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr1_reg_n_0_[7]\,
      O => \dIgrm1[35]_i_4_n_0\
    );
\dIgrm1[36]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr0_reg_n_0_[8]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[36]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[36]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(36)
    );
\dIgrm1[36]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr2_reg_n_0_[8]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr1_reg_n_0_[8]\,
      O => \dIgrm1[36]_i_3_n_0\
    );
\dIgrm1[36]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr4_reg_n_0_[8]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr3_reg_n_0_[8]\,
      O => \dIgrm1[36]_i_4_n_0\
    );
\dIgrm1[37]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr0_reg_n_0_[9]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[37]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[37]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(37)
    );
\dIgrm1[37]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr4_reg_n_0_[9]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr3_reg_n_0_[9]\,
      O => \dIgrm1[37]_i_3_n_0\
    );
\dIgrm1[37]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr2_reg_n_0_[9]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr1_reg_n_0_[9]\,
      O => \dIgrm1[37]_i_4_n_0\
    );
\dIgrm1[38]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr0_reg_n_0_[10]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[38]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[38]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(38)
    );
\dIgrm1[38]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr2_reg_n_0_[10]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr1_reg_n_0_[10]\,
      O => \dIgrm1[38]_i_3_n_0\
    );
\dIgrm1[38]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr4_reg_n_0_[10]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr3_reg_n_0_[10]\,
      O => \dIgrm1[38]_i_4_n_0\
    );
\dIgrm1[39]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr0_reg_n_0_[11]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[39]_i_4_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[39]_i_5_n_0\,
      O => \^abcde_reg[0]_0\(39)
    );
\dIgrm1[39]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr4_reg_n_0_[11]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr3_reg_n_0_[11]\,
      O => \dIgrm1[39]_i_4_n_0\
    );
\dIgrm1[39]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \gr2_reg_n_0_[11]\,
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \gr1_reg_n_0_[11]\,
      O => \dIgrm1[39]_i_5_n_0\
    );
\dIgrm1[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"02AA"
    )
        port map (
      I0 => p_14_in(7),
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \abcde_reg_n_0_[1]\,
      I3 => \abcde_reg_n_0_[2]\,
      O => \^abcde_reg[0]_0\(3)
    );
\dIgrm1[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"02AA"
    )
        port map (
      I0 => p_14_in(8),
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \abcde_reg_n_0_[1]\,
      I3 => \abcde_reg_n_0_[2]\,
      O => \^abcde_reg[0]_0\(4)
    );
\dIgrm1[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"02AA"
    )
        port map (
      I0 => p_14_in(9),
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \abcde_reg_n_0_[1]\,
      I3 => \abcde_reg_n_0_[2]\,
      O => \^abcde_reg[0]_0\(5)
    );
\dIgrm1[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"02AA"
    )
        port map (
      I0 => p_14_in(10),
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \abcde_reg_n_0_[1]\,
      I3 => \abcde_reg_n_0_[2]\,
      O => \^abcde_reg[0]_0\(6)
    );
\dIgrm1[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"02AA"
    )
        port map (
      I0 => p_14_in(11),
      I1 => \abcde_reg_n_0_[0]\,
      I2 => \abcde_reg_n_0_[1]\,
      I3 => \abcde_reg_n_0_[2]\,
      O => \^abcde_reg[0]_0\(7)
    );
\dIgrm1[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr3_reg_n_0_[4]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[24]_i_4_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[32]_i_4_n_0\,
      O => \^abcde_reg[0]_0\(8)
    );
\dIgrm1[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr3_reg_n_0_[5]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[25]_i_4_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[33]_i_3_n_0\,
      O => \^abcde_reg[0]_0\(9)
    );
\drdEvenbufBm1[63]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0141410101010141"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I3 => \qrs_reg_n_0_[2]\,
      I4 => \qrs_reg_n_0_[0]\,
      I5 => \qrs_reg_n_0_[1]\,
      O => \drdEvenbufBm1[63]_i_1_n_0\
    );
\drdEvenbufBm1_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(48),
      Q => data2(0)
    );
\drdEvenbufBm1_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(49),
      Q => data2(1)
    );
\drdEvenbufBm1_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(50),
      Q => data2(2)
    );
\drdEvenbufBm1_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(51),
      Q => data2(3)
    );
\drdEvenbufBm1_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(52),
      Q => data2(4)
    );
\drdEvenbufBm1_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(53),
      Q => data2(5)
    );
\drdEvenbufBm1_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(54),
      Q => data2(6)
    );
\drdEvenbufBm1_reg[55]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(55),
      Q => data2(7)
    );
\drdEvenbufBm1_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(56),
      Q => data2(8)
    );
\drdEvenbufBm1_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(57),
      Q => data2(9)
    );
\drdEvenbufBm1_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(58),
      Q => data2(10)
    );
\drdEvenbufBm1_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(59),
      Q => data2(11)
    );
\drdEvenbufBm1_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(60),
      Q => \drdEvenbufBm1_reg_n_0_[60]\
    );
\drdEvenbufBm1_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(61),
      Q => \drdEvenbufBm1_reg_n_0_[61]\
    );
\drdEvenbufBm1_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(62),
      Q => \drdEvenbufBm1_reg_n_0_[62]\
    );
\drdEvenbufBm1_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdEvenbufBm1(63),
      Q => \drdEvenbufBm1_reg_n_0_[63]\
    );
\drdOddbufBm1_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(48),
      Q => \drdOddbufBm1_reg_n_0_[48]\
    );
\drdOddbufBm1_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(49),
      Q => \drdOddbufBm1_reg_n_0_[49]\
    );
\drdOddbufBm1_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(50),
      Q => \drdOddbufBm1_reg_n_0_[50]\
    );
\drdOddbufBm1_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(51),
      Q => \drdOddbufBm1_reg_n_0_[51]\
    );
\drdOddbufBm1_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(52),
      Q => \drdOddbufBm1_reg_n_0_[52]\
    );
\drdOddbufBm1_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(53),
      Q => \drdOddbufBm1_reg_n_0_[53]\
    );
\drdOddbufBm1_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(54),
      Q => \drdOddbufBm1_reg_n_0_[54]\
    );
\drdOddbufBm1_reg[55]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(55),
      Q => \drdOddbufBm1_reg_n_0_[55]\
    );
\drdOddbufBm1_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(56),
      Q => \drdOddbufBm1_reg_n_0_[56]\
    );
\drdOddbufBm1_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(57),
      Q => \drdOddbufBm1_reg_n_0_[57]\
    );
\drdOddbufBm1_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(58),
      Q => \drdOddbufBm1_reg_n_0_[58]\
    );
\drdOddbufBm1_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(59),
      Q => \drdOddbufBm1_reg_n_0_[59]\
    );
\drdOddbufBm1_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(60),
      Q => \drdOddbufBm1_reg_n_0_[60]\
    );
\drdOddbufBm1_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(61),
      Q => \drdOddbufBm1_reg_n_0_[61]\
    );
\drdOddbufBm1_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(62),
      Q => \drdOddbufBm1_reg_n_0_[62]\
    );
\drdOddbufBm1_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdEvenbufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdOddbufBm1(63),
      Q => \drdOddbufBm1_reg_n_0_[63]\
    );
\drdRow0bufBm1_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow0bufBm1(60),
      Q => \data10__3\(4)
    );
\drdRow0bufBm1_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow0bufBm1(61),
      Q => \data10__3\(5)
    );
\drdRow0bufBm1_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow0bufBm1(62),
      Q => \data10__3\(6)
    );
\drdRow0bufBm1_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow0bufBm1(63),
      Q => \data10__3\(7)
    );
\drdRow1bufBm1_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow1bufBm1(60),
      Q => \data10__2\(4)
    );
\drdRow1bufBm1_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow1bufBm1(61),
      Q => \data10__2\(5)
    );
\drdRow1bufBm1_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow1bufBm1(62),
      Q => \data10__2\(6)
    );
\drdRow1bufBm1_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow1bufBm1(63),
      Q => \data10__2\(7)
    );
\drdRow2bufBm1_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow2bufBm1(60),
      Q => \data10__1\(4)
    );
\drdRow2bufBm1_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow2bufBm1(61),
      Q => \data10__1\(5)
    );
\drdRow2bufBm1_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow2bufBm1(62),
      Q => \data10__1\(6)
    );
\drdRow2bufBm1_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow2bufBm1(63),
      Q => \data10__1\(7)
    );
\drdRow3bufBm1_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow3bufBm1(60),
      Q => \data10__0\(4)
    );
\drdRow3bufBm1_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow3bufBm1(61),
      Q => \data10__0\(5)
    );
\drdRow3bufBm1_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow3bufBm1(62),
      Q => \data10__0\(6)
    );
\drdRow3bufBm1_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow3bufBm1(63),
      Q => \data10__0\(7)
    );
\drdRow4bufBm1[63]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAEAAEAAAAAAAA"
    )
        port map (
      I0 => \drdRow4bufBm1[63]_i_3_n_0\,
      I1 => \nop_reg_n_0_[3]\,
      I2 => \nop_reg_n_0_[1]\,
      I3 => \nop_reg_n_0_[2]\,
      I4 => \nop_reg_n_0_[0]\,
      I5 => grayToManyAXIS_tvalid_sig,
      O => \drdRow4bufBm1[63]_i_1_n_0\
    );
\drdRow4bufBm1[63]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => stateGrayegr(0),
      I1 => stateGrayegr(2),
      I2 => stateGrayegr(1),
      O => \drdRow4bufBm1[63]_i_3_n_0\
    );
\drdRow4bufBm1[63]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => stateGrayegr(2),
      I1 => stateGrayegr(0),
      I2 => stateGrayegr(1),
      I3 => \^rgbvideointomanyaxis_tvalid\,
      O => grayToManyAXIS_tvalid_sig
    );
\drdRow4bufBm1_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow4bufBm1(60),
      Q => data10(4)
    );
\drdRow4bufBm1_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow4bufBm1(61),
      Q => data10(5)
    );
\drdRow4bufBm1_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow4bufBm1(62),
      Q => data10(6)
    );
\drdRow4bufBm1_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \drdRow4bufBm1[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => drdRow4bufBm1(63),
      Q => data10(7)
    );
\dwrEobuf[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(0),
      I1 => klm(1),
      I2 => dwrEobufp1(0),
      I3 => \^stateigr_reg[1]_0\(0),
      I4 => \^stateigr_reg[1]_0\(1),
      O => \dwrEobuf[0]_i_1_n_0\
    );
\dwrEobuf[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \dwrEobuf[10]_i_2_n_0\,
      O => \dwrEobuf[10]_i_1_n_0\
    );
\dwrEobuf[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0777077700000777"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(2),
      I1 => \^klm_reg[0]_0\(0),
      I2 => klm(2),
      I3 => dwrEobufp1(10),
      I4 => camifToVideoinAXIS_tdata(10),
      I5 => klm(1),
      O => \dwrEobuf[10]_i_2_n_0\
    );
\dwrEobuf[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \dwrEobuf[11]_i_2_n_0\,
      O => \dwrEobuf[11]_i_1_n_0\
    );
\dwrEobuf[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0777077700000777"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(3),
      I1 => \^klm_reg[0]_0\(0),
      I2 => klm(2),
      I3 => dwrEobufp1(11),
      I4 => camifToVideoinAXIS_tdata(11),
      I5 => klm(1),
      O => \dwrEobuf[11]_i_2_n_0\
    );
\dwrEobuf[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \dwrEobuf[12]_i_2_n_0\,
      O => \dwrEobuf[12]_i_1_n_0\
    );
\dwrEobuf[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0777077700000777"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(4),
      I1 => \^klm_reg[0]_0\(0),
      I2 => klm(2),
      I3 => dwrEobufp1(12),
      I4 => camifToVideoinAXIS_tdata(12),
      I5 => klm(1),
      O => \dwrEobuf[12]_i_2_n_0\
    );
\dwrEobuf[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \dwrEobuf[13]_i_2_n_0\,
      O => \dwrEobuf[13]_i_1_n_0\
    );
\dwrEobuf[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0777077700000777"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(5),
      I1 => \^klm_reg[0]_0\(0),
      I2 => klm(2),
      I3 => dwrEobufp1(13),
      I4 => camifToVideoinAXIS_tdata(13),
      I5 => klm(1),
      O => \dwrEobuf[13]_i_2_n_0\
    );
\dwrEobuf[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \dwrEobuf[14]_i_2_n_0\,
      O => \dwrEobuf[14]_i_1_n_0\
    );
\dwrEobuf[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0777077700000777"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(6),
      I1 => \^klm_reg[0]_0\(0),
      I2 => klm(2),
      I3 => dwrEobufp1(14),
      I4 => camifToVideoinAXIS_tdata(14),
      I5 => klm(1),
      O => \dwrEobuf[14]_i_2_n_0\
    );
\dwrEobuf[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \dwrEobuf[15]_i_2_n_0\,
      O => \dwrEobuf[15]_i_1_n_0\
    );
\dwrEobuf[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0777077700000777"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(7),
      I1 => \^klm_reg[0]_0\(0),
      I2 => klm(2),
      I3 => dwrEobufp1(15),
      I4 => camifToVideoinAXIS_tdata(15),
      I5 => klm(1),
      O => \dwrEobuf[15]_i_2_n_0\
    );
\dwrEobuf[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E000EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(0),
      I4 => \dwrEobuf[48]_i_2_n_0\,
      O => \dwrEobuf[16]_i_1_n_0\
    );
\dwrEobuf[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E000EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(1),
      I4 => \dwrEobuf[49]_i_2_n_0\,
      O => \dwrEobuf[17]_i_1_n_0\
    );
\dwrEobuf[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E000EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(2),
      I4 => \dwrEobuf[50]_i_2_n_0\,
      O => \dwrEobuf[18]_i_1_n_0\
    );
\dwrEobuf[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E000EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(3),
      I4 => \dwrEobuf[51]_i_2_n_0\,
      O => \dwrEobuf[19]_i_1_n_0\
    );
\dwrEobuf[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(1),
      I1 => klm(1),
      I2 => dwrEobufp1(1),
      I3 => \^stateigr_reg[1]_0\(0),
      I4 => \^stateigr_reg[1]_0\(1),
      O => \dwrEobuf[1]_i_1_n_0\
    );
\dwrEobuf[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E000EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(4),
      I4 => \dwrEobuf[52]_i_2_n_0\,
      O => \dwrEobuf[20]_i_1_n_0\
    );
\dwrEobuf[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E000EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(5),
      I4 => \dwrEobuf[53]_i_2_n_0\,
      O => \dwrEobuf[21]_i_1_n_0\
    );
\dwrEobuf[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E000EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(6),
      I4 => \dwrEobuf[54]_i_2_n_0\,
      O => \dwrEobuf[22]_i_1_n_0\
    );
\dwrEobuf[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FF1111F11111111"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => klm(2),
      I3 => \^klm_reg[0]_0\(0),
      I4 => klm(1),
      I5 => \dwrEobuf_reg[63]_1\,
      O => \dwrEobuf[23]_i_1_n_0\
    );
\dwrEobuf[23]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E000EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(7),
      I4 => \dwrEobuf[55]_i_3_n_0\,
      O => \dwrEobuf[23]_i_2_n_0\
    );
\dwrEobuf[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555500005404"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(0),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(16),
      I4 => klm(2),
      I5 => \dwrEobuf_reg[56]_0\,
      O => \dwrEobuf[24]_i_1_n_0\
    );
\dwrEobuf[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555500005404"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(1),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(17),
      I4 => klm(2),
      I5 => \dwrEobuf_reg[57]_0\,
      O => \dwrEobuf[25]_i_1_n_0\
    );
\dwrEobuf[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555500005404"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(2),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(18),
      I4 => klm(2),
      I5 => \dwrEobuf_reg[58]_0\,
      O => \dwrEobuf[26]_i_1_n_0\
    );
\dwrEobuf[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555500005404"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(3),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(19),
      I4 => klm(2),
      I5 => \dwrEobuf_reg[59]_0\,
      O => \dwrEobuf[27]_i_1_n_0\
    );
\dwrEobuf[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555500005404"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(4),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(20),
      I4 => klm(2),
      I5 => \dwrEobuf_reg[60]_0\,
      O => \dwrEobuf[28]_i_1_n_0\
    );
\dwrEobuf[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555500005404"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(5),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(21),
      I4 => klm(2),
      I5 => \dwrEobuf_reg[61]_0\,
      O => \dwrEobuf[29]_i_1_n_0\
    );
\dwrEobuf[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(2),
      I1 => klm(1),
      I2 => dwrEobufp1(2),
      I3 => \^stateigr_reg[1]_0\(0),
      I4 => \^stateigr_reg[1]_0\(1),
      O => \dwrEobuf[2]_i_1_n_0\
    );
\dwrEobuf[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555500005404"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(6),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(22),
      I4 => klm(2),
      I5 => \dwrEobuf_reg[62]_0\,
      O => \dwrEobuf[30]_i_1_n_0\
    );
\dwrEobuf[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"11F1FF1111111111"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => klm(1),
      I3 => \^klm_reg[0]_0\(0),
      I4 => klm(2),
      I5 => \dwrEobuf_reg[63]_1\,
      O => \dwrEobuf[31]_i_1_n_0\
    );
\dwrEobuf[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555500005404"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(7),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(23),
      I4 => klm(2),
      I5 => \dwrEobuf_reg[63]_0\,
      O => \dwrEobuf[31]_i_2_n_0\
    );
\dwrEobuf[32]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80AA"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^klm_reg[0]_0\(0),
      I2 => camifToVideoinAXIS_tdata(8),
      I3 => \dwrEobuf[32]_i_2_n_0\,
      O => \dwrEobuf[32]_i_1_n_0\
    );
\dwrEobuf[32]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"57F7"
    )
        port map (
      I0 => klm(2),
      I1 => camifToVideoinAXIS_tdata(0),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(16),
      O => \dwrEobuf[32]_i_2_n_0\
    );
\dwrEobuf[33]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80AA"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^klm_reg[0]_0\(0),
      I2 => camifToVideoinAXIS_tdata(9),
      I3 => \dwrEobuf[33]_i_2_n_0\,
      O => \dwrEobuf[33]_i_1_n_0\
    );
\dwrEobuf[33]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"57F7"
    )
        port map (
      I0 => klm(2),
      I1 => camifToVideoinAXIS_tdata(1),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(17),
      O => \dwrEobuf[33]_i_2_n_0\
    );
\dwrEobuf[34]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80AA"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^klm_reg[0]_0\(0),
      I2 => camifToVideoinAXIS_tdata(10),
      I3 => \dwrEobuf[34]_i_2_n_0\,
      O => \dwrEobuf[34]_i_1_n_0\
    );
\dwrEobuf[34]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"57F7"
    )
        port map (
      I0 => klm(2),
      I1 => camifToVideoinAXIS_tdata(2),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(18),
      O => \dwrEobuf[34]_i_2_n_0\
    );
\dwrEobuf[35]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80AA"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^klm_reg[0]_0\(0),
      I2 => camifToVideoinAXIS_tdata(11),
      I3 => \dwrEobuf[35]_i_2_n_0\,
      O => \dwrEobuf[35]_i_1_n_0\
    );
\dwrEobuf[35]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"57F7"
    )
        port map (
      I0 => klm(2),
      I1 => camifToVideoinAXIS_tdata(3),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(19),
      O => \dwrEobuf[35]_i_2_n_0\
    );
\dwrEobuf[36]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80AA"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^klm_reg[0]_0\(0),
      I2 => camifToVideoinAXIS_tdata(12),
      I3 => \dwrEobuf[36]_i_2_n_0\,
      O => \dwrEobuf[36]_i_1_n_0\
    );
\dwrEobuf[36]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"57F7"
    )
        port map (
      I0 => klm(2),
      I1 => camifToVideoinAXIS_tdata(4),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(20),
      O => \dwrEobuf[36]_i_2_n_0\
    );
\dwrEobuf[37]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80AA"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^klm_reg[0]_0\(0),
      I2 => camifToVideoinAXIS_tdata(13),
      I3 => \dwrEobuf[37]_i_2_n_0\,
      O => \dwrEobuf[37]_i_1_n_0\
    );
\dwrEobuf[37]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"57F7"
    )
        port map (
      I0 => klm(2),
      I1 => camifToVideoinAXIS_tdata(5),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(21),
      O => \dwrEobuf[37]_i_2_n_0\
    );
\dwrEobuf[38]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80AA"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^klm_reg[0]_0\(0),
      I2 => camifToVideoinAXIS_tdata(14),
      I3 => \dwrEobuf[38]_i_2_n_0\,
      O => \dwrEobuf[38]_i_1_n_0\
    );
\dwrEobuf[38]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"57F7"
    )
        port map (
      I0 => klm(2),
      I1 => camifToVideoinAXIS_tdata(6),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(22),
      O => \dwrEobuf[38]_i_2_n_0\
    );
\dwrEobuf[39]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010500055555555"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => klm(1),
      I2 => \dwrEobuf_reg[36]_0\,
      I3 => klm(2),
      I4 => \^klm_reg[0]_0\(0),
      I5 => \^stateigr_reg[1]_0\(0),
      O => \dwrEobuf[39]_i_1_n_0\
    );
\dwrEobuf[39]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"80AA"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^klm_reg[0]_0\(0),
      I2 => camifToVideoinAXIS_tdata(15),
      I3 => \dwrEobuf[39]_i_4_n_0\,
      O => \dwrEobuf[39]_i_2_n_0\
    );
\dwrEobuf[39]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"57F7"
    )
        port map (
      I0 => klm(2),
      I1 => camifToVideoinAXIS_tdata(7),
      I2 => klm(1),
      I3 => camifToVideoinAXIS_tdata(23),
      O => \dwrEobuf[39]_i_4_n_0\
    );
\dwrEobuf[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(3),
      I1 => klm(1),
      I2 => dwrEobufp1(3),
      I3 => \^stateigr_reg[1]_0\(0),
      I4 => \^stateigr_reg[1]_0\(1),
      O => \dwrEobuf[3]_i_1_n_0\
    );
\dwrEobuf[40]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555540554040"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(0),
      I2 => klm(1),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(16),
      I5 => \dwrEobuf_reg[56]_0\,
      O => \dwrEobuf[40]_i_1_n_0\
    );
\dwrEobuf[41]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555540554040"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(1),
      I2 => klm(1),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(17),
      I5 => \dwrEobuf_reg[57]_0\,
      O => \dwrEobuf[41]_i_1_n_0\
    );
\dwrEobuf[42]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555540554040"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(2),
      I2 => klm(1),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(18),
      I5 => \dwrEobuf_reg[58]_0\,
      O => \dwrEobuf[42]_i_1_n_0\
    );
\dwrEobuf[43]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555540554040"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(3),
      I2 => klm(1),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(19),
      I5 => \dwrEobuf_reg[59]_0\,
      O => \dwrEobuf[43]_i_1_n_0\
    );
\dwrEobuf[44]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555540554040"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(4),
      I2 => klm(1),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(20),
      I5 => \dwrEobuf_reg[60]_0\,
      O => \dwrEobuf[44]_i_1_n_0\
    );
\dwrEobuf[45]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555540554040"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(5),
      I2 => klm(1),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(21),
      I5 => \dwrEobuf_reg[61]_0\,
      O => \dwrEobuf[45]_i_1_n_0\
    );
\dwrEobuf[46]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555540554040"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(6),
      I2 => klm(1),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(22),
      I5 => \dwrEobuf_reg[62]_0\,
      O => \dwrEobuf[46]_i_1_n_0\
    );
\dwrEobuf[47]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F11F1F1111111111"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => klm(1),
      I3 => klm(2),
      I4 => \^klm_reg[0]_0\(0),
      I5 => \dwrEobuf_reg[63]_1\,
      O => \dwrEobuf[47]_i_1_n_0\
    );
\dwrEobuf[47]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555540554040"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => camifToVideoinAXIS_tdata(7),
      I2 => klm(1),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(23),
      I5 => \dwrEobuf_reg[63]_0\,
      O => \dwrEobuf[47]_i_2_n_0\
    );
\dwrEobuf[48]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => camifToVideoinAXIS_tdata(0),
      I3 => klm(2),
      I4 => \dwrEobuf[48]_i_2_n_0\,
      O => \dwrEobuf[48]_i_1_n_0\
    );
\dwrEobuf[48]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0BBB"
    )
        port map (
      I0 => klm(1),
      I1 => camifToVideoinAXIS_tdata(16),
      I2 => camifToVideoinAXIS_tdata(8),
      I3 => \^klm_reg[0]_0\(0),
      O => \dwrEobuf[48]_i_2_n_0\
    );
\dwrEobuf[49]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => camifToVideoinAXIS_tdata(1),
      I3 => klm(2),
      I4 => \dwrEobuf[49]_i_2_n_0\,
      O => \dwrEobuf[49]_i_1_n_0\
    );
\dwrEobuf[49]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0BBB"
    )
        port map (
      I0 => klm(1),
      I1 => camifToVideoinAXIS_tdata(17),
      I2 => camifToVideoinAXIS_tdata(9),
      I3 => \^klm_reg[0]_0\(0),
      O => \dwrEobuf[49]_i_2_n_0\
    );
\dwrEobuf[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(4),
      I1 => klm(1),
      I2 => dwrEobufp1(4),
      I3 => \^stateigr_reg[1]_0\(0),
      I4 => \^stateigr_reg[1]_0\(1),
      O => \dwrEobuf[4]_i_1_n_0\
    );
\dwrEobuf[50]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => camifToVideoinAXIS_tdata(2),
      I3 => klm(2),
      I4 => \dwrEobuf[50]_i_2_n_0\,
      O => \dwrEobuf[50]_i_1_n_0\
    );
\dwrEobuf[50]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0BBB"
    )
        port map (
      I0 => klm(1),
      I1 => camifToVideoinAXIS_tdata(18),
      I2 => camifToVideoinAXIS_tdata(10),
      I3 => \^klm_reg[0]_0\(0),
      O => \dwrEobuf[50]_i_2_n_0\
    );
\dwrEobuf[51]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => camifToVideoinAXIS_tdata(3),
      I3 => klm(2),
      I4 => \dwrEobuf[51]_i_2_n_0\,
      O => \dwrEobuf[51]_i_1_n_0\
    );
\dwrEobuf[51]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0BBB"
    )
        port map (
      I0 => klm(1),
      I1 => camifToVideoinAXIS_tdata(19),
      I2 => camifToVideoinAXIS_tdata(11),
      I3 => \^klm_reg[0]_0\(0),
      O => \dwrEobuf[51]_i_2_n_0\
    );
\dwrEobuf[52]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => camifToVideoinAXIS_tdata(4),
      I3 => klm(2),
      I4 => \dwrEobuf[52]_i_2_n_0\,
      O => \dwrEobuf[52]_i_1_n_0\
    );
\dwrEobuf[52]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0BBB"
    )
        port map (
      I0 => klm(1),
      I1 => camifToVideoinAXIS_tdata(20),
      I2 => camifToVideoinAXIS_tdata(12),
      I3 => \^klm_reg[0]_0\(0),
      O => \dwrEobuf[52]_i_2_n_0\
    );
\dwrEobuf[53]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => camifToVideoinAXIS_tdata(5),
      I3 => klm(2),
      I4 => \dwrEobuf[53]_i_2_n_0\,
      O => \dwrEobuf[53]_i_1_n_0\
    );
\dwrEobuf[53]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0BBB"
    )
        port map (
      I0 => klm(1),
      I1 => camifToVideoinAXIS_tdata(21),
      I2 => camifToVideoinAXIS_tdata(13),
      I3 => \^klm_reg[0]_0\(0),
      O => \dwrEobuf[53]_i_2_n_0\
    );
\dwrEobuf[54]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => camifToVideoinAXIS_tdata(6),
      I3 => klm(2),
      I4 => \dwrEobuf[54]_i_2_n_0\,
      O => \dwrEobuf[54]_i_1_n_0\
    );
\dwrEobuf[54]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0BBB"
    )
        port map (
      I0 => klm(1),
      I1 => camifToVideoinAXIS_tdata(22),
      I2 => camifToVideoinAXIS_tdata(14),
      I3 => \^klm_reg[0]_0\(0),
      O => \dwrEobuf[54]_i_2_n_0\
    );
\dwrEobuf[55]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F11111F11111F111"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \dwrEobuf_reg[63]_1\,
      I3 => klm(2),
      I4 => \^klm_reg[0]_0\(0),
      I5 => klm(1),
      O => \dwrEobuf[55]_i_1_n_0\
    );
\dwrEobuf[55]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0EEEE"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => camifToVideoinAXIS_tdata(7),
      I3 => klm(2),
      I4 => \dwrEobuf[55]_i_3_n_0\,
      O => \dwrEobuf[55]_i_2_n_0\
    );
\dwrEobuf[55]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0BBB"
    )
        port map (
      I0 => klm(1),
      I1 => camifToVideoinAXIS_tdata(23),
      I2 => camifToVideoinAXIS_tdata(15),
      I3 => \^klm_reg[0]_0\(0),
      O => \dwrEobuf[55]_i_3_n_0\
    );
\dwrEobuf[56]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5454544444445444"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => \dwrEobuf_reg[56]_0\,
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(0),
      I4 => klm(1),
      I5 => camifToVideoinAXIS_tdata(16),
      O => \dwrEobuf[56]_i_1_n_0\
    );
\dwrEobuf[57]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5454544444445444"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => \dwrEobuf_reg[57]_0\,
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(1),
      I4 => klm(1),
      I5 => camifToVideoinAXIS_tdata(17),
      O => \dwrEobuf[57]_i_1_n_0\
    );
\dwrEobuf[58]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5454544444445444"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => \dwrEobuf_reg[58]_0\,
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(2),
      I4 => klm(1),
      I5 => camifToVideoinAXIS_tdata(18),
      O => \dwrEobuf[58]_i_1_n_0\
    );
\dwrEobuf[59]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5454544444445444"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => \dwrEobuf_reg[59]_0\,
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(3),
      I4 => klm(1),
      I5 => camifToVideoinAXIS_tdata(19),
      O => \dwrEobuf[59]_i_1_n_0\
    );
\dwrEobuf[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(5),
      I1 => klm(1),
      I2 => dwrEobufp1(5),
      I3 => \^stateigr_reg[1]_0\(0),
      I4 => \^stateigr_reg[1]_0\(1),
      O => \dwrEobuf[5]_i_1_n_0\
    );
\dwrEobuf[60]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5454544444445444"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => \dwrEobuf_reg[60]_0\,
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(4),
      I4 => klm(1),
      I5 => camifToVideoinAXIS_tdata(20),
      O => \dwrEobuf[60]_i_1_n_0\
    );
\dwrEobuf[61]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5454544444445444"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => \dwrEobuf_reg[61]_0\,
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(5),
      I4 => klm(1),
      I5 => camifToVideoinAXIS_tdata(21),
      O => \dwrEobuf[61]_i_1_n_0\
    );
\dwrEobuf[62]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5454544444445444"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => \dwrEobuf_reg[62]_0\,
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(6),
      I4 => klm(1),
      I5 => camifToVideoinAXIS_tdata(22),
      O => \dwrEobuf[62]_i_1_n_0\
    );
\dwrEobuf[63]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F11FF11111111111"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => klm(2),
      I3 => \^klm_reg[0]_0\(0),
      I4 => klm(1),
      I5 => \dwrEobuf_reg[63]_1\,
      O => \dwrEobuf[63]_i_1_n_0\
    );
\dwrEobuf[63]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5454544444445444"
    )
        port map (
      I0 => \dwrEobufp1[7]_i_4_n_0\,
      I1 => \dwrEobuf_reg[63]_0\,
      I2 => klm(2),
      I3 => camifToVideoinAXIS_tdata(7),
      I4 => klm(1),
      I5 => camifToVideoinAXIS_tdata(23),
      O => \dwrEobuf[63]_i_2_n_0\
    );
\dwrEobuf[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(6),
      I1 => klm(1),
      I2 => dwrEobufp1(6),
      I3 => \^stateigr_reg[1]_0\(0),
      I4 => \^stateigr_reg[1]_0\(1),
      O => \dwrEobuf[6]_i_1_n_0\
    );
\dwrEobuf[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(7),
      I1 => klm(1),
      I2 => dwrEobufp1(7),
      I3 => \^stateigr_reg[1]_0\(0),
      I4 => \^stateigr_reg[1]_0\(1),
      O => \dwrEobuf[7]_i_1_n_0\
    );
\dwrEobuf[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \dwrEobuf[8]_i_2_n_0\,
      O => \dwrEobuf[8]_i_1_n_0\
    );
\dwrEobuf[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0777077700000777"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(0),
      I1 => \^klm_reg[0]_0\(0),
      I2 => klm(2),
      I3 => dwrEobufp1(8),
      I4 => camifToVideoinAXIS_tdata(8),
      I5 => klm(1),
      O => \dwrEobuf[8]_i_2_n_0\
    );
\dwrEobuf[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \dwrEobuf[9]_i_2_n_0\,
      O => \dwrEobuf[9]_i_1_n_0\
    );
\dwrEobuf[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0777077700000777"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(1),
      I1 => \^klm_reg[0]_0\(0),
      I2 => klm(2),
      I3 => dwrEobufp1(9),
      I4 => camifToVideoinAXIS_tdata(9),
      I5 => klm(1),
      O => \dwrEobuf[9]_i_2_n_0\
    );
\dwrEobuf_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[0]_i_1_n_0\,
      Q => dwrEobuf(0)
    );
\dwrEobuf_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[10]_i_1_n_0\,
      Q => dwrEobuf(10)
    );
\dwrEobuf_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[11]_i_1_n_0\,
      Q => dwrEobuf(11)
    );
\dwrEobuf_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[12]_i_1_n_0\,
      Q => dwrEobuf(12)
    );
\dwrEobuf_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[13]_i_1_n_0\,
      Q => dwrEobuf(13)
    );
\dwrEobuf_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[14]_i_1_n_0\,
      Q => dwrEobuf(14)
    );
\dwrEobuf_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[15]_i_1_n_0\,
      Q => dwrEobuf(15)
    );
\dwrEobuf_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[16]_i_1_n_0\,
      Q => dwrEobuf(16)
    );
\dwrEobuf_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[17]_i_1_n_0\,
      Q => dwrEobuf(17)
    );
\dwrEobuf_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[18]_i_1_n_0\,
      Q => dwrEobuf(18)
    );
\dwrEobuf_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[19]_i_1_n_0\,
      Q => dwrEobuf(19)
    );
\dwrEobuf_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[1]_i_1_n_0\,
      Q => dwrEobuf(1)
    );
\dwrEobuf_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[20]_i_1_n_0\,
      Q => dwrEobuf(20)
    );
\dwrEobuf_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[21]_i_1_n_0\,
      Q => dwrEobuf(21)
    );
\dwrEobuf_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[22]_i_1_n_0\,
      Q => dwrEobuf(22)
    );
\dwrEobuf_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[23]_i_2_n_0\,
      Q => dwrEobuf(23)
    );
\dwrEobuf_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[31]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[24]_i_1_n_0\,
      Q => dwrEobuf(24)
    );
\dwrEobuf_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[31]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[25]_i_1_n_0\,
      Q => dwrEobuf(25)
    );
\dwrEobuf_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[31]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[26]_i_1_n_0\,
      Q => dwrEobuf(26)
    );
\dwrEobuf_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[31]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[27]_i_1_n_0\,
      Q => dwrEobuf(27)
    );
\dwrEobuf_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[31]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[28]_i_1_n_0\,
      Q => dwrEobuf(28)
    );
\dwrEobuf_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[31]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[29]_i_1_n_0\,
      Q => dwrEobuf(29)
    );
\dwrEobuf_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[2]_i_1_n_0\,
      Q => dwrEobuf(2)
    );
\dwrEobuf_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[31]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[30]_i_1_n_0\,
      Q => dwrEobuf(30)
    );
\dwrEobuf_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[31]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[31]_i_2_n_0\,
      Q => dwrEobuf(31)
    );
\dwrEobuf_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[39]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[32]_i_1_n_0\,
      Q => dwrEobuf(32)
    );
\dwrEobuf_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[39]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[33]_i_1_n_0\,
      Q => dwrEobuf(33)
    );
\dwrEobuf_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[39]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[34]_i_1_n_0\,
      Q => dwrEobuf(34)
    );
\dwrEobuf_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[39]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[35]_i_1_n_0\,
      Q => dwrEobuf(35)
    );
\dwrEobuf_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[39]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[36]_i_1_n_0\,
      Q => dwrEobuf(36)
    );
\dwrEobuf_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[39]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[37]_i_1_n_0\,
      Q => dwrEobuf(37)
    );
\dwrEobuf_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[39]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[38]_i_1_n_0\,
      Q => dwrEobuf(38)
    );
\dwrEobuf_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[39]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[39]_i_2_n_0\,
      Q => dwrEobuf(39)
    );
\dwrEobuf_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[3]_i_1_n_0\,
      Q => dwrEobuf(3)
    );
\dwrEobuf_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[47]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[40]_i_1_n_0\,
      Q => dwrEobuf(40)
    );
\dwrEobuf_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[47]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[41]_i_1_n_0\,
      Q => dwrEobuf(41)
    );
\dwrEobuf_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[47]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[42]_i_1_n_0\,
      Q => dwrEobuf(42)
    );
\dwrEobuf_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[47]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[43]_i_1_n_0\,
      Q => dwrEobuf(43)
    );
\dwrEobuf_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[47]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[44]_i_1_n_0\,
      Q => dwrEobuf(44)
    );
\dwrEobuf_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[47]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[45]_i_1_n_0\,
      Q => dwrEobuf(45)
    );
\dwrEobuf_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[47]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[46]_i_1_n_0\,
      Q => dwrEobuf(46)
    );
\dwrEobuf_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[47]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[47]_i_2_n_0\,
      Q => dwrEobuf(47)
    );
\dwrEobuf_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[55]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[48]_i_1_n_0\,
      Q => dwrEobuf(48)
    );
\dwrEobuf_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[55]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[49]_i_1_n_0\,
      Q => dwrEobuf(49)
    );
\dwrEobuf_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[4]_i_1_n_0\,
      Q => dwrEobuf(4)
    );
\dwrEobuf_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[55]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[50]_i_1_n_0\,
      Q => dwrEobuf(50)
    );
\dwrEobuf_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[55]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[51]_i_1_n_0\,
      Q => dwrEobuf(51)
    );
\dwrEobuf_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[55]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[52]_i_1_n_0\,
      Q => dwrEobuf(52)
    );
\dwrEobuf_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[55]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[53]_i_1_n_0\,
      Q => dwrEobuf(53)
    );
\dwrEobuf_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[55]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[54]_i_1_n_0\,
      Q => dwrEobuf(54)
    );
\dwrEobuf_reg[55]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[55]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[55]_i_2_n_0\,
      Q => dwrEobuf(55)
    );
\dwrEobuf_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[56]_i_1_n_0\,
      Q => dwrEobuf(56)
    );
\dwrEobuf_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[57]_i_1_n_0\,
      Q => dwrEobuf(57)
    );
\dwrEobuf_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[58]_i_1_n_0\,
      Q => dwrEobuf(58)
    );
\dwrEobuf_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[59]_i_1_n_0\,
      Q => dwrEobuf(59)
    );
\dwrEobuf_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[5]_i_1_n_0\,
      Q => dwrEobuf(5)
    );
\dwrEobuf_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[60]_i_1_n_0\,
      Q => dwrEobuf(60)
    );
\dwrEobuf_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[61]_i_1_n_0\,
      Q => dwrEobuf(61)
    );
\dwrEobuf_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[62]_i_1_n_0\,
      Q => dwrEobuf(62)
    );
\dwrEobuf_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[63]_i_2_n_0\,
      Q => dwrEobuf(63)
    );
\dwrEobuf_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[6]_i_1_n_0\,
      Q => dwrEobuf(6)
    );
\dwrEobuf_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[7]_i_1_n_0\,
      Q => dwrEobuf(7)
    );
\dwrEobuf_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[8]_i_1_n_0\,
      Q => dwrEobuf(8)
    );
\dwrEobuf_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobuf[23]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrEobuf[9]_i_1_n_0\,
      Q => dwrEobuf(9)
    );
\dwrEobufp1[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFB0008"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(16),
      I1 => klm(1),
      I2 => \^klm_reg[0]_0\(0),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(8),
      I5 => \dwrEobufp1[7]_i_4_n_0\,
      O => dwrEobufp10_out(0)
    );
\dwrEobufp1[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(18),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => \^stateigr_reg[1]_0\(1),
      O => dwrEobufp10_out(10)
    );
\dwrEobufp1[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(19),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => \^stateigr_reg[1]_0\(1),
      O => dwrEobufp10_out(11)
    );
\dwrEobufp1[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(20),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => \^stateigr_reg[1]_0\(1),
      O => dwrEobufp10_out(12)
    );
\dwrEobufp1[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(21),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => \^stateigr_reg[1]_0\(1),
      O => dwrEobufp10_out(13)
    );
\dwrEobufp1[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(22),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => \^stateigr_reg[1]_0\(1),
      O => dwrEobufp10_out(14)
    );
\dwrEobufp1[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111F11111111111"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => \^klm_reg[0]_0\(0),
      I3 => klm(2),
      I4 => klm(1),
      I5 => \dwrEobuf_reg[63]_1\,
      O => \dwrEobufp1[15]_i_1_n_0\
    );
\dwrEobufp1[15]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(23),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => \^stateigr_reg[1]_0\(1),
      O => dwrEobufp10_out(15)
    );
\dwrEobufp1[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFB0008"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(17),
      I1 => klm(1),
      I2 => \^klm_reg[0]_0\(0),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(9),
      I5 => \dwrEobufp1[7]_i_4_n_0\,
      O => dwrEobufp10_out(1)
    );
\dwrEobufp1[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFB0008"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(18),
      I1 => klm(1),
      I2 => \^klm_reg[0]_0\(0),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(10),
      I5 => \dwrEobufp1[7]_i_4_n_0\,
      O => dwrEobufp10_out(2)
    );
\dwrEobufp1[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFB0008"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(19),
      I1 => klm(1),
      I2 => \^klm_reg[0]_0\(0),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(11),
      I5 => \dwrEobufp1[7]_i_4_n_0\,
      O => dwrEobufp10_out(3)
    );
\dwrEobufp1[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFB0008"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(20),
      I1 => klm(1),
      I2 => \^klm_reg[0]_0\(0),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(12),
      I5 => \dwrEobufp1[7]_i_4_n_0\,
      O => dwrEobufp10_out(4)
    );
\dwrEobufp1[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFB0008"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(21),
      I1 => klm(1),
      I2 => \^klm_reg[0]_0\(0),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(13),
      I5 => \dwrEobufp1[7]_i_4_n_0\,
      O => dwrEobufp10_out(5)
    );
\dwrEobufp1[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFB0008"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(22),
      I1 => klm(1),
      I2 => \^klm_reg[0]_0\(0),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(14),
      I5 => \dwrEobufp1[7]_i_4_n_0\,
      O => dwrEobufp10_out(6)
    );
\dwrEobufp1[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F1111F111111111"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => klm(1),
      I3 => \^klm_reg[0]_0\(0),
      I4 => klm(2),
      I5 => \dwrEobuf_reg[63]_1\,
      O => \dwrEobufp1[7]_i_1_n_0\
    );
\dwrEobufp1[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFB0008"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(23),
      I1 => klm(1),
      I2 => \^klm_reg[0]_0\(0),
      I3 => klm(2),
      I4 => camifToVideoinAXIS_tdata(15),
      I5 => \dwrEobufp1[7]_i_4_n_0\,
      O => dwrEobufp10_out(7)
    );
\dwrEobufp1[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      O => \dwrEobufp1[7]_i_4_n_0\
    );
\dwrEobufp1[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(16),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => \^stateigr_reg[1]_0\(1),
      O => dwrEobufp10_out(8)
    );
\dwrEobufp1[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => camifToVideoinAXIS_tdata(17),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => \^stateigr_reg[1]_0\(1),
      O => dwrEobufp10_out(9)
    );
\dwrEobufp1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[7]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(0),
      Q => dwrEobufp1(0)
    );
\dwrEobufp1_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[15]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(10),
      Q => dwrEobufp1(10)
    );
\dwrEobufp1_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[15]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(11),
      Q => dwrEobufp1(11)
    );
\dwrEobufp1_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[15]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(12),
      Q => dwrEobufp1(12)
    );
\dwrEobufp1_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[15]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(13),
      Q => dwrEobufp1(13)
    );
\dwrEobufp1_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[15]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(14),
      Q => dwrEobufp1(14)
    );
\dwrEobufp1_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[15]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(15),
      Q => dwrEobufp1(15)
    );
\dwrEobufp1_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[7]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(1),
      Q => dwrEobufp1(1)
    );
\dwrEobufp1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[7]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(2),
      Q => dwrEobufp1(2)
    );
\dwrEobufp1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[7]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(3),
      Q => dwrEobufp1(3)
    );
\dwrEobufp1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[7]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(4),
      Q => dwrEobufp1(4)
    );
\dwrEobufp1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[7]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(5),
      Q => dwrEobufp1(5)
    );
\dwrEobufp1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[7]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(6),
      Q => dwrEobufp1(6)
    );
\dwrEobufp1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[7]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(7),
      Q => dwrEobufp1(7)
    );
\dwrEobufp1_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[15]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(8),
      Q => dwrEobufp1(8)
    );
\dwrEobufp1_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrEobufp1[15]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrEobufp10_out(9),
      Q => dwrEobufp1(9)
    );
\dwrRowbuf[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => p_14_in(0),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => dwrRowbufp1(0),
      I3 => stateGraypack(0),
      I4 => stateGraypack(1),
      O => \dwrRowbuf[0]_i_1__0_n_0\
    );
\dwrRowbuf[11]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF10810000"
    )
        port map (
      I0 => \tuv_reg_n_0_[3]\,
      I1 => \tuv_reg_n_0_[0]\,
      I2 => \tuv_reg_n_0_[1]\,
      I3 => \tuv_reg_n_0_[2]\,
      I4 => \dwrRowbufp1[7]_i_4_n_0\,
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[11]_i_1__0_n_0\
    );
\dwrRowbuf[15]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAEBAAAAAAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \tuv_reg_n_0_[3]\,
      I2 => \tuv_reg_n_0_[1]\,
      I3 => \tuv_reg_n_0_[0]\,
      I4 => \tuv_reg_n_0_[2]\,
      I5 => \dwrRowbufp1[7]_i_4_n_0\,
      O => \dwrRowbuf[15]_i_1__0_n_0\
    );
\dwrRowbuf[19]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABEABAAAAAAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \tuv_reg_n_0_[3]\,
      I2 => \tuv_reg_n_0_[1]\,
      I3 => \tuv_reg_n_0_[0]\,
      I4 => \tuv_reg_n_0_[2]\,
      I5 => \dwrRowbufp1[7]_i_4_n_0\,
      O => \dwrRowbuf[19]_i_1__0_n_0\
    );
\dwrRowbuf[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => p_14_in(1),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => dwrRowbufp1(1),
      I3 => stateGraypack(0),
      I4 => stateGraypack(1),
      O => \dwrRowbuf[1]_i_1__0_n_0\
    );
\dwrRowbuf[23]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAEABAAAAAAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \tuv_reg_n_0_[3]\,
      I2 => \tuv_reg_n_0_[1]\,
      I3 => \tuv_reg_n_0_[0]\,
      I4 => \tuv_reg_n_0_[2]\,
      I5 => \dwrRowbufp1[7]_i_4_n_0\,
      O => \dwrRowbuf[23]_i_1__0_n_0\
    );
\dwrRowbuf[27]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAEABAAAAAAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \tuv_reg_n_0_[3]\,
      I2 => \tuv_reg_n_0_[0]\,
      I3 => \tuv_reg_n_0_[1]\,
      I4 => \tuv_reg_n_0_[2]\,
      I5 => \dwrRowbufp1[7]_i_4_n_0\,
      O => \dwrRowbuf[27]_i_1__0_n_0\
    );
\dwrRowbuf[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => p_14_in(2),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => dwrRowbufp1(2),
      I3 => stateGraypack(0),
      I4 => stateGraypack(1),
      O => \dwrRowbuf[2]_i_1__0_n_0\
    );
\dwrRowbuf[31]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAEAABAAAAAAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \tuv_reg_n_0_[3]\,
      I2 => \tuv_reg_n_0_[0]\,
      I3 => \tuv_reg_n_0_[1]\,
      I4 => \tuv_reg_n_0_[2]\,
      I5 => \dwrRowbufp1[7]_i_4_n_0\,
      O => \dwrRowbuf[31]_i_1__0_n_0\
    );
\dwrRowbuf[35]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAEAABAEAAAAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \tuv_reg_n_0_[3]\,
      I2 => \tuv_reg_n_0_[2]\,
      I3 => \tuv_reg_n_0_[1]\,
      I4 => \tuv_reg_n_0_[0]\,
      I5 => \dwrRowbufp1[7]_i_4_n_0\,
      O => \dwrRowbuf[35]_i_1_n_0\
    );
\dwrRowbuf[39]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAEBBAAAAAAAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \tuv_reg_n_0_[2]\,
      I2 => \tuv_reg_n_0_[0]\,
      I3 => \tuv_reg_n_0_[1]\,
      I4 => \tuv_reg_n_0_[3]\,
      I5 => \dwrRowbufp1[7]_i_4_n_0\,
      O => \dwrRowbuf[39]_i_1_n_0\
    );
\dwrRowbuf[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => p_14_in(3),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => dwrRowbufp1(3),
      I3 => stateGraypack(0),
      I4 => stateGraypack(1),
      O => \dwrRowbuf[3]_i_1__0_n_0\
    );
\dwrRowbuf[43]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABEAAAAEAAAAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \tuv_reg_n_0_[3]\,
      I2 => \tuv_reg_n_0_[2]\,
      I3 => \tuv_reg_n_0_[0]\,
      I4 => \tuv_reg_n_0_[1]\,
      I5 => \dwrRowbufp1[7]_i_4_n_0\,
      O => \dwrRowbuf[43]_i_1_n_0\
    );
\dwrRowbuf[47]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEBABAAAAAAAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \tuv_reg_n_0_[2]\,
      I2 => \tuv_reg_n_0_[0]\,
      I3 => \tuv_reg_n_0_[1]\,
      I4 => \tuv_reg_n_0_[3]\,
      I5 => \dwrRowbufp1[7]_i_4_n_0\,
      O => \dwrRowbuf[47]_i_1_n_0\
    );
\dwrRowbuf[48]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => p_14_in(0),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => p_14_in(8),
      I3 => \tuv_reg_n_0_[0]\,
      I4 => p_14_in(4),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[48]_i_1_n_0\
    );
\dwrRowbuf[49]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => p_14_in(1),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => p_14_in(9),
      I3 => \tuv_reg_n_0_[0]\,
      I4 => p_14_in(5),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[49]_i_1_n_0\
    );
\dwrRowbuf[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => p_14_in(4),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => dwrRowbufp1(4),
      I3 => \tuv_reg_n_0_[0]\,
      I4 => p_14_in(0),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[4]_i_1__0_n_0\
    );
\dwrRowbuf[50]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => p_14_in(2),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => p_14_in(10),
      I3 => \tuv_reg_n_0_[0]\,
      I4 => p_14_in(6),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[50]_i_1_n_0\
    );
\dwrRowbuf[51]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEBAABAAAAAAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \tuv_reg_n_0_[1]\,
      I2 => \tuv_reg_n_0_[0]\,
      I3 => \tuv_reg_n_0_[2]\,
      I4 => \tuv_reg_n_0_[3]\,
      I5 => \dwrRowbufp1[7]_i_4_n_0\,
      O => \dwrRowbuf[51]_i_1_n_0\
    );
\dwrRowbuf[51]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => p_14_in(3),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => p_14_in(11),
      I3 => \tuv_reg_n_0_[0]\,
      I4 => p_14_in(7),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[51]_i_2_n_0\
    );
\dwrRowbuf[52]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => p_14_in(4),
      I1 => \tuv_reg_n_0_[0]\,
      I2 => p_14_in(8),
      I3 => \tuv_reg_n_0_[1]\,
      I4 => p_14_in(0),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[52]_i_1_n_0\
    );
\dwrRowbuf[53]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => p_14_in(5),
      I1 => \tuv_reg_n_0_[0]\,
      I2 => p_14_in(9),
      I3 => \tuv_reg_n_0_[1]\,
      I4 => p_14_in(1),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[53]_i_1_n_0\
    );
\dwrRowbuf[54]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => p_14_in(6),
      I1 => \tuv_reg_n_0_[0]\,
      I2 => p_14_in(10),
      I3 => \tuv_reg_n_0_[1]\,
      I4 => p_14_in(2),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[54]_i_1_n_0\
    );
\dwrRowbuf[55]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAABAAEAAAAAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \tuv_reg_n_0_[3]\,
      I2 => \tuv_reg_n_0_[0]\,
      I3 => \tuv_reg_n_0_[1]\,
      I4 => \tuv_reg_n_0_[2]\,
      I5 => \dwrRowbufp1[7]_i_4_n_0\,
      O => \dwrRowbuf[55]_i_1_n_0\
    );
\dwrRowbuf[55]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => p_14_in(7),
      I1 => \tuv_reg_n_0_[0]\,
      I2 => p_14_in(11),
      I3 => \tuv_reg_n_0_[1]\,
      I4 => p_14_in(3),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[55]_i_2_n_0\
    );
\dwrRowbuf[56]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => p_14_in(8),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => p_14_in(0),
      I3 => \tuv_reg_n_0_[0]\,
      I4 => p_14_in(4),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[56]_i_1_n_0\
    );
\dwrRowbuf[57]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => p_14_in(9),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => p_14_in(1),
      I3 => \tuv_reg_n_0_[0]\,
      I4 => p_14_in(5),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[57]_i_1_n_0\
    );
\dwrRowbuf[58]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => p_14_in(10),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => p_14_in(2),
      I3 => \tuv_reg_n_0_[0]\,
      I4 => p_14_in(6),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[58]_i_1_n_0\
    );
\dwrRowbuf[59]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EABAABAAAAAAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \tuv_reg_n_0_[0]\,
      I2 => \tuv_reg_n_0_[1]\,
      I3 => \tuv_reg_n_0_[2]\,
      I4 => \tuv_reg_n_0_[3]\,
      I5 => \dwrRowbufp1[7]_i_4_n_0\,
      O => \dwrRowbuf[59]_i_1_n_0\
    );
\dwrRowbuf[59]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => p_14_in(11),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => p_14_in(3),
      I3 => \tuv_reg_n_0_[0]\,
      I4 => p_14_in(7),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[59]_i_2_n_0\
    );
\dwrRowbuf[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => p_14_in(5),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => dwrRowbufp1(5),
      I3 => \tuv_reg_n_0_[0]\,
      I4 => p_14_in(1),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[5]_i_1__0_n_0\
    );
\dwrRowbuf[60]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => p_14_in(4),
      I1 => \tuv_reg_n_0_[0]\,
      I2 => p_14_in(0),
      I3 => \tuv_reg_n_0_[1]\,
      I4 => p_14_in(8),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[60]_i_1_n_0\
    );
\dwrRowbuf[61]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => p_14_in(5),
      I1 => \tuv_reg_n_0_[0]\,
      I2 => p_14_in(1),
      I3 => \tuv_reg_n_0_[1]\,
      I4 => p_14_in(9),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[61]_i_1_n_0\
    );
\dwrRowbuf[62]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => p_14_in(6),
      I1 => \tuv_reg_n_0_[0]\,
      I2 => p_14_in(2),
      I3 => \tuv_reg_n_0_[1]\,
      I4 => p_14_in(10),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[62]_i_1_n_0\
    );
\dwrRowbuf[63]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAEAAAAEAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \dwrRowbufp1[7]_i_4_n_0\,
      I2 => \tuv_reg_n_0_[0]\,
      I3 => \tuv_reg_n_0_[1]\,
      I4 => \tuv_reg_n_0_[2]\,
      I5 => \tuv_reg_n_0_[3]\,
      O => \dwrRowbuf[63]_i_1_n_0\
    );
\dwrRowbuf[63]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE222E2"
    )
        port map (
      I0 => p_14_in(7),
      I1 => \tuv_reg_n_0_[0]\,
      I2 => p_14_in(3),
      I3 => \tuv_reg_n_0_[1]\,
      I4 => p_14_in(11),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[63]_i_2_n_0\
    );
\dwrRowbuf[6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => p_14_in(6),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => dwrRowbufp1(6),
      I3 => \tuv_reg_n_0_[0]\,
      I4 => p_14_in(2),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[6]_i_1__0_n_0\
    );
\dwrRowbuf[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFE200E2"
    )
        port map (
      I0 => p_14_in(7),
      I1 => \tuv_reg_n_0_[1]\,
      I2 => dwrRowbufp1(7),
      I3 => \tuv_reg_n_0_[0]\,
      I4 => p_14_in(3),
      I5 => \dwrRowbufp1[7]_i_3_n_0\,
      O => \dwrRowbuf[7]_i_1__0_n_0\
    );
\dwrRowbuf_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[11]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[0]_i_1__0_n_0\,
      Q => \dwrRowbuf_reg_n_0_[0]\
    );
\dwrRowbuf_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[11]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[58]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[10]\
    );
\dwrRowbuf_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[11]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[59]_i_2_n_0\,
      Q => \dwrRowbuf_reg_n_0_[11]\
    );
\dwrRowbuf_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[15]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[60]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[12]\
    );
\dwrRowbuf_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[15]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[61]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[13]\
    );
\dwrRowbuf_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[15]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[62]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[14]\
    );
\dwrRowbuf_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[15]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[63]_i_2_n_0\,
      Q => \dwrRowbuf_reg_n_0_[15]\
    );
\dwrRowbuf_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[19]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[48]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[16]\
    );
\dwrRowbuf_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[19]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[49]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[17]\
    );
\dwrRowbuf_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[19]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[50]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[18]\
    );
\dwrRowbuf_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[19]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[51]_i_2_n_0\,
      Q => \dwrRowbuf_reg_n_0_[19]\
    );
\dwrRowbuf_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[11]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[1]_i_1__0_n_0\,
      Q => \dwrRowbuf_reg_n_0_[1]\
    );
\dwrRowbuf_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[23]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[52]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[20]\
    );
\dwrRowbuf_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[23]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[53]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[21]\
    );
\dwrRowbuf_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[23]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[54]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[22]\
    );
\dwrRowbuf_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[23]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[55]_i_2_n_0\,
      Q => \dwrRowbuf_reg_n_0_[23]\
    );
\dwrRowbuf_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[27]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[56]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[24]\
    );
\dwrRowbuf_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[27]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[57]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[25]\
    );
\dwrRowbuf_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[27]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[58]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[26]\
    );
\dwrRowbuf_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[27]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[59]_i_2_n_0\,
      Q => \dwrRowbuf_reg_n_0_[27]\
    );
\dwrRowbuf_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[60]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[28]\
    );
\dwrRowbuf_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[61]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[29]\
    );
\dwrRowbuf_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[11]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[2]_i_1__0_n_0\,
      Q => \dwrRowbuf_reg_n_0_[2]\
    );
\dwrRowbuf_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[62]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[30]\
    );
\dwrRowbuf_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[31]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[63]_i_2_n_0\,
      Q => \dwrRowbuf_reg_n_0_[31]\
    );
\dwrRowbuf_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[35]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[48]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[32]\
    );
\dwrRowbuf_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[35]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[49]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[33]\
    );
\dwrRowbuf_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[35]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[50]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[34]\
    );
\dwrRowbuf_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[35]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[51]_i_2_n_0\,
      Q => \dwrRowbuf_reg_n_0_[35]\
    );
\dwrRowbuf_reg[36]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[39]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[52]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[36]\
    );
\dwrRowbuf_reg[37]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[39]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[53]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[37]\
    );
\dwrRowbuf_reg[38]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[39]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[54]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[38]\
    );
\dwrRowbuf_reg[39]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[39]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[55]_i_2_n_0\,
      Q => \dwrRowbuf_reg_n_0_[39]\
    );
\dwrRowbuf_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[11]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[3]_i_1__0_n_0\,
      Q => \dwrRowbuf_reg_n_0_[3]\
    );
\dwrRowbuf_reg[40]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[43]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[56]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[40]\
    );
\dwrRowbuf_reg[41]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[43]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[57]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[41]\
    );
\dwrRowbuf_reg[42]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[43]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[58]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[42]\
    );
\dwrRowbuf_reg[43]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[43]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[59]_i_2_n_0\,
      Q => \dwrRowbuf_reg_n_0_[43]\
    );
\dwrRowbuf_reg[44]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[47]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[60]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[44]\
    );
\dwrRowbuf_reg[45]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[47]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[61]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[45]\
    );
\dwrRowbuf_reg[46]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[47]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[62]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[46]\
    );
\dwrRowbuf_reg[47]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[47]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[63]_i_2_n_0\,
      Q => \dwrRowbuf_reg_n_0_[47]\
    );
\dwrRowbuf_reg[48]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[51]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[48]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[48]\
    );
\dwrRowbuf_reg[49]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[51]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[49]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[49]\
    );
\dwrRowbuf_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[11]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[4]_i_1__0_n_0\,
      Q => \dwrRowbuf_reg_n_0_[4]\
    );
\dwrRowbuf_reg[50]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[51]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[50]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[50]\
    );
\dwrRowbuf_reg[51]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[51]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[51]_i_2_n_0\,
      Q => \dwrRowbuf_reg_n_0_[51]\
    );
\dwrRowbuf_reg[52]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[55]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[52]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[52]\
    );
\dwrRowbuf_reg[53]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[55]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[53]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[53]\
    );
\dwrRowbuf_reg[54]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[55]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[54]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[54]\
    );
\dwrRowbuf_reg[55]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[55]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[55]_i_2_n_0\,
      Q => \dwrRowbuf_reg_n_0_[55]\
    );
\dwrRowbuf_reg[56]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[59]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[56]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[56]\
    );
\dwrRowbuf_reg[57]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[59]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[57]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[57]\
    );
\dwrRowbuf_reg[58]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[59]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[58]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[58]\
    );
\dwrRowbuf_reg[59]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[59]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[59]_i_2_n_0\,
      Q => \dwrRowbuf_reg_n_0_[59]\
    );
\dwrRowbuf_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[11]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[5]_i_1__0_n_0\,
      Q => \dwrRowbuf_reg_n_0_[5]\
    );
\dwrRowbuf_reg[60]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[60]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[60]\
    );
\dwrRowbuf_reg[61]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[61]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[61]\
    );
\dwrRowbuf_reg[62]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[62]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[62]\
    );
\dwrRowbuf_reg[63]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[63]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[63]_i_2_n_0\,
      Q => \dwrRowbuf_reg_n_0_[63]\
    );
\dwrRowbuf_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[11]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[6]_i_1__0_n_0\,
      Q => \dwrRowbuf_reg_n_0_[6]\
    );
\dwrRowbuf_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[11]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[7]_i_1__0_n_0\,
      Q => \dwrRowbuf_reg_n_0_[7]\
    );
\dwrRowbuf_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[11]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[56]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[8]\
    );
\dwrRowbuf_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbuf[11]_i_1__0_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \dwrRowbuf[57]_i_1_n_0\,
      Q => \dwrRowbuf_reg_n_0_[9]\
    );
\dwrRowbufp1[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => p_14_in(8),
      I1 => \dwrRowbufp1[3]_i_3_n_0\,
      I2 => p_14_in(4),
      I3 => stateGraypack(0),
      I4 => stateGraypack(1),
      O => dwrRowbufp10_out(0)
    );
\dwrRowbufp1[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => p_14_in(9),
      I1 => \dwrRowbufp1[3]_i_3_n_0\,
      I2 => p_14_in(5),
      I3 => stateGraypack(0),
      I4 => stateGraypack(1),
      O => dwrRowbufp10_out(1)
    );
\dwrRowbufp1[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => p_14_in(10),
      I1 => \dwrRowbufp1[3]_i_3_n_0\,
      I2 => p_14_in(6),
      I3 => stateGraypack(0),
      I4 => stateGraypack(1),
      O => dwrRowbufp10_out(2)
    );
\dwrRowbufp1[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAABAAAAAEAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \tuv_reg_n_0_[3]\,
      I2 => \dwrRowbufp1[7]_i_4_n_0\,
      I3 => \tuv_reg_n_0_[2]\,
      I4 => \tuv_reg_n_0_[1]\,
      I5 => \tuv_reg_n_0_[0]\,
      O => \dwrRowbufp1[3]_i_1_n_0\
    );
\dwrRowbufp1[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2E2E200"
    )
        port map (
      I0 => p_14_in(11),
      I1 => \dwrRowbufp1[3]_i_3_n_0\,
      I2 => p_14_in(7),
      I3 => stateGraypack(0),
      I4 => stateGraypack(1),
      O => dwrRowbufp10_out(3)
    );
\dwrRowbufp1[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \tuv_reg_n_0_[3]\,
      I1 => \tuv_reg_n_0_[2]\,
      I2 => \tuv_reg_n_0_[1]\,
      I3 => \tuv_reg_n_0_[0]\,
      O => \dwrRowbufp1[3]_i_3_n_0\
    );
\dwrRowbufp1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => p_14_in(8),
      I1 => stateGraypack(0),
      I2 => stateGraypack(1),
      O => dwrRowbufp10_out(4)
    );
\dwrRowbufp1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => p_14_in(9),
      I1 => stateGraypack(0),
      I2 => stateGraypack(1),
      O => dwrRowbufp10_out(5)
    );
\dwrRowbufp1[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => p_14_in(10),
      I1 => stateGraypack(0),
      I2 => stateGraypack(1),
      O => dwrRowbufp10_out(6)
    );
\dwrRowbufp1[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAEAAAAAAAAAA"
    )
        port map (
      I0 => \dwrRowbufp1[7]_i_3_n_0\,
      I1 => \dwrRowbufp1[7]_i_4_n_0\,
      I2 => \tuv_reg_n_0_[3]\,
      I3 => \tuv_reg_n_0_[2]\,
      I4 => \tuv_reg_n_0_[1]\,
      I5 => \tuv_reg_n_0_[0]\,
      O => \dwrRowbufp1[7]_i_1_n_0\
    );
\dwrRowbufp1[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => p_14_in(11),
      I1 => stateGraypack(0),
      I2 => stateGraypack(1),
      O => dwrRowbufp10_out(7)
    );
\dwrRowbufp1[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => stateGraypack(1),
      I1 => stateGraypack(0),
      O => \dwrRowbufp1[7]_i_3_n_0\
    );
\dwrRowbufp1[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^rgbvideointomanyaxis_tvalid\,
      I1 => stateGraypack(0),
      O => \dwrRowbufp1[7]_i_4_n_0\
    );
\dwrRowbufp1_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbufp1[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrRowbufp10_out(0),
      Q => dwrRowbufp1(0)
    );
\dwrRowbufp1_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbufp1[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrRowbufp10_out(1),
      Q => dwrRowbufp1(1)
    );
\dwrRowbufp1_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbufp1[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrRowbufp10_out(2),
      Q => dwrRowbufp1(2)
    );
\dwrRowbufp1_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbufp1[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrRowbufp10_out(3),
      Q => dwrRowbufp1(3)
    );
\dwrRowbufp1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbufp1[7]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrRowbufp10_out(4),
      Q => dwrRowbufp1(4)
    );
\dwrRowbufp1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbufp1[7]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrRowbufp10_out(5),
      Q => dwrRowbufp1(5)
    );
\dwrRowbufp1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbufp1[7]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrRowbufp10_out(6),
      Q => dwrRowbufp1(6)
    );
\dwrRowbufp1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrRowbufp1[7]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => dwrRowbufp10_out(7),
      Q => dwrRowbufp1(7)
    );
\dy[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(8),
      I2 => \^abcde_reg[0]_0\(0),
      O => \abcde_reg[0]_1\(0)
    );
\dy[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28228288"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(9),
      I2 => \^abcde_reg[0]_0\(8),
      I3 => \^abcde_reg[0]_0\(16),
      I4 => \^abcde_reg[0]_0\(17),
      O => \abcde_reg[0]_1\(10)
    );
\dy[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(10),
      I2 => \^abcde_reg[0]_0\(18),
      I3 => \dy[11]_i_2_n_0\,
      O => \abcde_reg[0]_1\(11)
    );
\dy[11]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8AEF"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(9),
      I1 => \^abcde_reg[0]_0\(8),
      I2 => \^abcde_reg[0]_0\(16),
      I3 => \^abcde_reg[0]_0\(17),
      O => \dy[11]_i_2_n_0\
    );
\dy[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(11),
      I2 => \^abcde_reg[0]_0\(19),
      I3 => \dy[13]_i_2_n_0\,
      O => \abcde_reg[0]_1\(12)
    );
\dy[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2882828228282882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(12),
      I2 => \^abcde_reg[0]_0\(20),
      I3 => \dy[13]_i_2_n_0\,
      I4 => \^abcde_reg[0]_0\(11),
      I5 => \^abcde_reg[0]_0\(19),
      O => \abcde_reg[0]_1\(13)
    );
\dy[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7510000FFFFF751"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(17),
      I1 => \^abcde_reg[0]_0\(16),
      I2 => \^abcde_reg[0]_0\(8),
      I3 => \^abcde_reg[0]_0\(9),
      I4 => \^abcde_reg[0]_0\(10),
      I5 => \^abcde_reg[0]_0\(18),
      O => \dy[13]_i_2_n_0\
    );
\dy[14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(13),
      I2 => \^abcde_reg[0]_0\(21),
      I3 => \dy[15]_i_2_n_0\,
      O => \abcde_reg[0]_1\(14)
    );
\dy[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2882828228282882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(14),
      I2 => \^abcde_reg[0]_0\(22),
      I3 => \dy[15]_i_2_n_0\,
      I4 => \^abcde_reg[0]_0\(13),
      I5 => \^abcde_reg[0]_0\(21),
      O => \abcde_reg[0]_1\(15)
    );
\dy[15]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D400FFD4"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(19),
      I1 => \^abcde_reg[0]_0\(11),
      I2 => \dy[13]_i_2_n_0\,
      I3 => \^abcde_reg[0]_0\(12),
      I4 => \^abcde_reg[0]_0\(20),
      O => \dy[15]_i_2_n_0\
    );
\dy[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(15),
      I2 => \^abcde_reg[0]_0\(23),
      I3 => \dy[17]_i_2_n_0\,
      O => \abcde_reg[0]_1\(16)
    );
\dy[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7010"
    )
        port map (
      I0 => \dy[17]_i_2_n_0\,
      I1 => \^abcde_reg[0]_0\(15),
      I2 => \dy_reg[8]\,
      I3 => \^abcde_reg[0]_0\(23),
      O => \abcde_reg[0]_1\(17)
    );
\dy[17]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D400FFD4"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(21),
      I1 => \^abcde_reg[0]_0\(13),
      I2 => \dy[15]_i_2_n_0\,
      I3 => \^abcde_reg[0]_0\(14),
      I4 => \^abcde_reg[0]_0\(22),
      O => \dy[17]_i_2_n_0\
    );
\dy[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(24),
      I2 => \^abcde_reg[0]_0\(16),
      O => \abcde_reg[0]_1\(18)
    );
\dy[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28228288"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(17),
      I2 => \^abcde_reg[0]_0\(16),
      I3 => \^abcde_reg[0]_0\(24),
      I4 => \^abcde_reg[0]_0\(25),
      O => \abcde_reg[0]_1\(19)
    );
\dy[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28228288"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(1),
      I2 => \^abcde_reg[0]_0\(0),
      I3 => \^abcde_reg[0]_0\(8),
      I4 => \^abcde_reg[0]_0\(9),
      O => \abcde_reg[0]_1\(1)
    );
\dy[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(18),
      I2 => \^abcde_reg[0]_0\(26),
      I3 => \dy[20]_i_2_n_0\,
      O => \abcde_reg[0]_1\(20)
    );
\dy[20]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8AEF"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(17),
      I1 => \^abcde_reg[0]_0\(16),
      I2 => \^abcde_reg[0]_0\(24),
      I3 => \^abcde_reg[0]_0\(25),
      O => \dy[20]_i_2_n_0\
    );
\dy[21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(19),
      I2 => \^abcde_reg[0]_0\(27),
      I3 => \dy[22]_i_2_n_0\,
      O => \abcde_reg[0]_1\(21)
    );
\dy[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2882828228282882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(20),
      I2 => \^abcde_reg[0]_0\(28),
      I3 => \dy[22]_i_2_n_0\,
      I4 => \^abcde_reg[0]_0\(19),
      I5 => \^abcde_reg[0]_0\(27),
      O => \abcde_reg[0]_1\(22)
    );
\dy[22]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7510000FFFFF751"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(25),
      I1 => \^abcde_reg[0]_0\(24),
      I2 => \^abcde_reg[0]_0\(16),
      I3 => \^abcde_reg[0]_0\(17),
      I4 => \^abcde_reg[0]_0\(18),
      I5 => \^abcde_reg[0]_0\(26),
      O => \dy[22]_i_2_n_0\
    );
\dy[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(21),
      I2 => \^abcde_reg[0]_0\(29),
      I3 => \dy[24]_i_2_n_0\,
      O => \abcde_reg[0]_1\(23)
    );
\dy[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2882828228282882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(22),
      I2 => \^abcde_reg[0]_0\(30),
      I3 => \dy[24]_i_2_n_0\,
      I4 => \^abcde_reg[0]_0\(21),
      I5 => \^abcde_reg[0]_0\(29),
      O => \abcde_reg[0]_1\(24)
    );
\dy[24]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D400FFD4"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(27),
      I1 => \^abcde_reg[0]_0\(19),
      I2 => \dy[22]_i_2_n_0\,
      I3 => \^abcde_reg[0]_0\(20),
      I4 => \^abcde_reg[0]_0\(28),
      O => \dy[24]_i_2_n_0\
    );
\dy[25]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(23),
      I2 => \^abcde_reg[0]_0\(31),
      I3 => \dy[26]_i_2_n_0\,
      O => \abcde_reg[0]_1\(25)
    );
\dy[26]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7010"
    )
        port map (
      I0 => \dy[26]_i_2_n_0\,
      I1 => \^abcde_reg[0]_0\(23),
      I2 => \dy_reg[8]\,
      I3 => \^abcde_reg[0]_0\(31),
      O => \abcde_reg[0]_1\(26)
    );
\dy[26]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D400FFD4"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(29),
      I1 => \^abcde_reg[0]_0\(21),
      I2 => \dy[24]_i_2_n_0\,
      I3 => \^abcde_reg[0]_0\(22),
      I4 => \^abcde_reg[0]_0\(30),
      O => \dy[26]_i_2_n_0\
    );
\dy[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(32),
      I2 => \^abcde_reg[0]_0\(24),
      O => \abcde_reg[0]_1\(27)
    );
\dy[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28228288"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(25),
      I2 => \^abcde_reg[0]_0\(24),
      I3 => \^abcde_reg[0]_0\(32),
      I4 => \^abcde_reg[0]_0\(33),
      O => \abcde_reg[0]_1\(28)
    );
\dy[29]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(26),
      I2 => \^abcde_reg[0]_0\(34),
      I3 => \dy[29]_i_2_n_0\,
      O => \abcde_reg[0]_1\(29)
    );
\dy[29]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8AEF"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(25),
      I1 => \^abcde_reg[0]_0\(24),
      I2 => \^abcde_reg[0]_0\(32),
      I3 => \^abcde_reg[0]_0\(33),
      O => \dy[29]_i_2_n_0\
    );
\dy[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(2),
      I2 => \^abcde_reg[0]_0\(10),
      I3 => \dy[2]_i_2_n_0\,
      O => \abcde_reg[0]_1\(2)
    );
\dy[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8AEF"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(1),
      I1 => \^abcde_reg[0]_0\(0),
      I2 => \^abcde_reg[0]_0\(8),
      I3 => \^abcde_reg[0]_0\(9),
      O => \dy[2]_i_2_n_0\
    );
\dy[30]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(27),
      I2 => \^abcde_reg[0]_0\(35),
      I3 => \dy[31]_i_2_n_0\,
      O => \abcde_reg[0]_1\(30)
    );
\dy[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2882828228282882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(28),
      I2 => \^abcde_reg[0]_0\(36),
      I3 => \dy[31]_i_2_n_0\,
      I4 => \^abcde_reg[0]_0\(27),
      I5 => \^abcde_reg[0]_0\(35),
      O => \abcde_reg[0]_1\(31)
    );
\dy[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7510000FFFFF751"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(33),
      I1 => \^abcde_reg[0]_0\(32),
      I2 => \^abcde_reg[0]_0\(24),
      I3 => \^abcde_reg[0]_0\(25),
      I4 => \^abcde_reg[0]_0\(26),
      I5 => \^abcde_reg[0]_0\(34),
      O => \dy[31]_i_2_n_0\
    );
\dy[32]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(29),
      I2 => \^abcde_reg[0]_0\(37),
      I3 => \dy[33]_i_2_n_0\,
      O => \abcde_reg[0]_1\(32)
    );
\dy[33]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2882828228282882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(30),
      I2 => \^abcde_reg[0]_0\(38),
      I3 => \dy[33]_i_2_n_0\,
      I4 => \^abcde_reg[0]_0\(29),
      I5 => \^abcde_reg[0]_0\(37),
      O => \abcde_reg[0]_1\(33)
    );
\dy[33]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D400FFD4"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(35),
      I1 => \^abcde_reg[0]_0\(27),
      I2 => \dy[31]_i_2_n_0\,
      I3 => \^abcde_reg[0]_0\(28),
      I4 => \^abcde_reg[0]_0\(36),
      O => \dy[33]_i_2_n_0\
    );
\dy[34]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(31),
      I2 => \^abcde_reg[0]_0\(39),
      I3 => \dy[35]_i_2_n_0\,
      O => \abcde_reg[0]_1\(34)
    );
\dy[35]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7010"
    )
        port map (
      I0 => \dy[35]_i_2_n_0\,
      I1 => \^abcde_reg[0]_0\(31),
      I2 => \dy_reg[8]\,
      I3 => \^abcde_reg[0]_0\(39),
      O => \abcde_reg[0]_1\(35)
    );
\dy[35]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D400FFD4"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(37),
      I1 => \^abcde_reg[0]_0\(29),
      I2 => \dy[33]_i_2_n_0\,
      I3 => \^abcde_reg[0]_0\(30),
      I4 => \^abcde_reg[0]_0\(38),
      O => \dy[35]_i_2_n_0\
    );
\dy[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => grayVideoinToManyAXIS_tdata(64),
      I2 => \^abcde_reg[0]_0\(32),
      O => \abcde_reg[0]_1\(36)
    );
\dy[37]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28288228"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(33),
      I2 => grayVideoinToManyAXIS_tdata(65),
      I3 => grayVideoinToManyAXIS_tdata(64),
      I4 => \^abcde_reg[0]_0\(32),
      O => \abcde_reg[0]_1\(37)
    );
\dy[37]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr4_reg_n_0_[5]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[25]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[17]_i_3_n_0\,
      O => grayVideoinToManyAXIS_tdata(65)
    );
\dy[37]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr4_reg_n_0_[4]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[24]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[16]_i_3_n_0\,
      O => grayVideoinToManyAXIS_tdata(64)
    );
\dy[38]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(34),
      I2 => grayVideoinToManyAXIS_tdata(66),
      I3 => \dy[38]_i_3_n_0\,
      O => \abcde_reg[0]_1\(38)
    );
\dy[38]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr4_reg_n_0_[6]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[26]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[18]_i_3_n_0\,
      O => grayVideoinToManyAXIS_tdata(66)
    );
\dy[38]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2B22"
    )
        port map (
      I0 => grayVideoinToManyAXIS_tdata(65),
      I1 => \^abcde_reg[0]_0\(33),
      I2 => \^abcde_reg[0]_0\(32),
      I3 => grayVideoinToManyAXIS_tdata(64),
      O => \dy[38]_i_3_n_0\
    );
\dy[39]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(35),
      I2 => grayVideoinToManyAXIS_tdata(67),
      I3 => \dy[40]_i_4_n_0\,
      O => \abcde_reg[0]_1\(39)
    );
\dy[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(3),
      I2 => \^abcde_reg[0]_0\(11),
      I3 => \dy[4]_i_2_n_0\,
      O => \abcde_reg[0]_1\(3)
    );
\dy[40]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228828228288228"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(36),
      I2 => grayVideoinToManyAXIS_tdata(68),
      I3 => grayVideoinToManyAXIS_tdata(67),
      I4 => \^abcde_reg[0]_0\(35),
      I5 => \dy[40]_i_4_n_0\,
      O => \abcde_reg[0]_1\(40)
    );
\dy[40]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr4_reg_n_0_[8]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[28]_i_4_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[20]_i_3_n_0\,
      O => grayVideoinToManyAXIS_tdata(68)
    );
\dy[40]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr4_reg_n_0_[7]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[19]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[27]_i_4_n_0\,
      O => grayVideoinToManyAXIS_tdata(67)
    );
\dy[40]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22B2BBBB222222B2"
    )
        port map (
      I0 => grayVideoinToManyAXIS_tdata(66),
      I1 => \^abcde_reg[0]_0\(34),
      I2 => grayVideoinToManyAXIS_tdata(64),
      I3 => \^abcde_reg[0]_0\(32),
      I4 => \^abcde_reg[0]_0\(33),
      I5 => grayVideoinToManyAXIS_tdata(65),
      O => \dy[40]_i_4_n_0\
    );
\dy[41]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(37),
      I2 => grayVideoinToManyAXIS_tdata(69),
      I3 => \dy[42]_i_4_n_0\,
      O => \abcde_reg[0]_1\(41)
    );
\dy[42]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8228828228288228"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(38),
      I2 => grayVideoinToManyAXIS_tdata(70),
      I3 => grayVideoinToManyAXIS_tdata(69),
      I4 => \^abcde_reg[0]_0\(37),
      I5 => \dy[42]_i_4_n_0\,
      O => \abcde_reg[0]_1\(42)
    );
\dy[42]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr4_reg_n_0_[10]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[22]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[30]_i_4_n_0\,
      O => grayVideoinToManyAXIS_tdata(70)
    );
\dy[42]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F4F4000004F40"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr4_reg_n_0_[9]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[21]_i_3_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[29]_i_4_n_0\,
      O => grayVideoinToManyAXIS_tdata(69)
    );
\dy[42]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B2BB22B2"
    )
        port map (
      I0 => grayVideoinToManyAXIS_tdata(68),
      I1 => \^abcde_reg[0]_0\(36),
      I2 => \dy[40]_i_4_n_0\,
      I3 => \^abcde_reg[0]_0\(35),
      I4 => grayVideoinToManyAXIS_tdata(67),
      O => \dy[42]_i_4_n_0\
    );
\dy[43]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8228"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(39),
      I2 => grayVideoinToManyAXIS_tdata(71),
      I3 => \dy[44]_i_3_n_0\,
      O => \abcde_reg[0]_1\(43)
    );
\dy[44]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8C08"
    )
        port map (
      I0 => grayVideoinToManyAXIS_tdata(71),
      I1 => \dy_reg[8]\,
      I2 => \^abcde_reg[0]_0\(39),
      I3 => \dy[44]_i_3_n_0\,
      O => \abcde_reg[0]_1\(44)
    );
\dy[44]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F004040"
    )
        port map (
      I0 => \abcde_reg_n_0_[0]\,
      I1 => \gr4_reg_n_0_[11]\,
      I2 => \abcde_reg_n_0_[2]\,
      I3 => \dIgrm1[31]_i_4_n_0\,
      I4 => \abcde_reg_n_0_[1]\,
      I5 => \dIgrm1[23]_i_3_n_0\,
      O => grayVideoinToManyAXIS_tdata(71)
    );
\dy[44]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B2BB22B2"
    )
        port map (
      I0 => grayVideoinToManyAXIS_tdata(70),
      I1 => \^abcde_reg[0]_0\(38),
      I2 => \dy[42]_i_4_n_0\,
      I3 => \^abcde_reg[0]_0\(37),
      I4 => grayVideoinToManyAXIS_tdata(69),
      O => \dy[44]_i_3_n_0\
    );
\dy[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2882828228282882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(4),
      I2 => \^abcde_reg[0]_0\(12),
      I3 => \dy[4]_i_2_n_0\,
      I4 => \^abcde_reg[0]_0\(3),
      I5 => \^abcde_reg[0]_0\(11),
      O => \abcde_reg[0]_1\(4)
    );
\dy[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7510000FFFFF751"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(9),
      I1 => \^abcde_reg[0]_0\(8),
      I2 => \^abcde_reg[0]_0\(0),
      I3 => \^abcde_reg[0]_0\(1),
      I4 => \^abcde_reg[0]_0\(2),
      I5 => \^abcde_reg[0]_0\(10),
      O => \dy[4]_i_2_n_0\
    );
\dy[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(5),
      I2 => \^abcde_reg[0]_0\(13),
      I3 => \dy[6]_i_2_n_0\,
      O => \abcde_reg[0]_1\(5)
    );
\dy[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2882828228282882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(6),
      I2 => \^abcde_reg[0]_0\(14),
      I3 => \dy[6]_i_2_n_0\,
      I4 => \^abcde_reg[0]_0\(5),
      I5 => \^abcde_reg[0]_0\(13),
      O => \abcde_reg[0]_1\(6)
    );
\dy[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D400FFD4"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(11),
      I1 => \^abcde_reg[0]_0\(3),
      I2 => \dy[4]_i_2_n_0\,
      I3 => \^abcde_reg[0]_0\(4),
      I4 => \^abcde_reg[0]_0\(12),
      O => \dy[6]_i_2_n_0\
    );
\dy[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(7),
      I2 => \^abcde_reg[0]_0\(15),
      I3 => \dy[8]_i_2_n_0\,
      O => \abcde_reg[0]_1\(7)
    );
\dy[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7010"
    )
        port map (
      I0 => \dy[8]_i_2_n_0\,
      I1 => \^abcde_reg[0]_0\(7),
      I2 => \dy_reg[8]\,
      I3 => \^abcde_reg[0]_0\(15),
      O => \abcde_reg[0]_1\(8)
    );
\dy[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D400FFD4"
    )
        port map (
      I0 => \^abcde_reg[0]_0\(13),
      I1 => \^abcde_reg[0]_0\(5),
      I2 => \dy[6]_i_2_n_0\,
      I3 => \^abcde_reg[0]_0\(6),
      I4 => \^abcde_reg[0]_0\(14),
      O => \dy[8]_i_2_n_0\
    );
\dy[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \dy_reg[8]\,
      I1 => \^abcde_reg[0]_0\(16),
      I2 => \^abcde_reg[0]_0\(8),
      O => \abcde_reg[0]_1\(9)
    );
enAccbuf_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^rgbvideointomanyaxis_tvalid\,
      I1 => enAccbuf_reg,
      I2 => \^grayvideointomanyaxis_tvalid\,
      O => enAccbuf1
    );
enEobufB_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABABABB8A8A8A88"
    )
        port map (
      I0 => enEobufB_i_2_n_0,
      I1 => \aEobufB[9]_i_5_n_0\,
      I2 => enEobufB_reg_1,
      I3 => enEobufB_i_4_n_0,
      I4 => enEobufB_i_5_n_0,
      I5 => enEobufB,
      O => enEobufB_i_1_n_0
    );
enEobufB_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44400040"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I2 => strbEgrstart_reg_n_0,
      I3 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I4 => enEobufB_lcl_reg_n_0,
      O => enEobufB_i_2_n_0
    );
enEobufB_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I2 => strbEgrstart_reg_n_0,
      O => enEobufB_i_4_n_0
    );
enEobufB_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA82AAAA"
    )
        port map (
      I0 => \aEobufB[9]_i_3_n_0\,
      I1 => enRowbuf_reg_0(10),
      I2 => \col_lcl[10]_i_2__1_n_0\,
      I3 => enEobufB_i_6_n_0,
      I4 => enEobufB_reg_0,
      I5 => rgbToManyAXIS_tlast_sig_i_3_n_0,
      O => enEobufB_i_5_n_0
    );
enEobufB_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"95556AAA"
    )
        port map (
      I0 => enRowbuf_reg_0(8),
      I1 => \^q\(4),
      I2 => \^col_lcl_reg[5]_0\,
      I3 => \^q\(3),
      I4 => \col_lcl_reg_n_0_[8]\,
      O => enEobufB_i_6_n_0
    );
enEobufB_lcl_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E0E00E"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I2 => \qrs_reg_n_0_[1]\,
      I3 => \qrs_reg_n_0_[0]\,
      I4 => \qrs_reg_n_0_[2]\,
      O => enEobufB_lcl
    );
enEobufB_lcl_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => enEobufB_lcl,
      Q => enEobufB_lcl_reg_n_0
    );
enEobufB_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enRowbufB_lcl_reg_0(0),
      D => enEobufB_i_1_n_0,
      Q => enEobufB
    );
enEobuf_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCC23CC00CC20CC"
    )
        port map (
      I0 => \stateIgr[0]_i_2_n_0\,
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => camifToVideoinAXIS_tvalid,
      I3 => \^stateigr_reg[1]_0\(0),
      I4 => oddNotEven_reg_0,
      I5 => enEobuf,
      O => enEobuf_i_1_n_0
    );
enEobuf_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enRowbufB_lcl_reg_0(0),
      D => enEobuf_i_1_n_0,
      Q => enEobuf
    );
enRowbufB_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAEAA0000A2AA"
    )
        port map (
      I0 => enRowbufB_i_2_n_0,
      I1 => stateGrayegr(0),
      I2 => \FSM_sequential_stateGrayegr[2]_i_3_n_0\,
      I3 => enRowbufB_i_3_n_0,
      I4 => enRowbufB_i_4_n_0,
      I5 => enRowbufB_reg_n_0,
      O => enRowbufB_i_1_n_0
    );
enRowbufB_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0022000030220000"
    )
        port map (
      I0 => strbEgrstart_reg_n_0,
      I1 => stateGrayegr(2),
      I2 => enRowbufB_lcl_reg_n_0,
      I3 => stateGrayegr(1),
      I4 => stateGrayegr(0),
      I5 => \^rgbvideointomanyaxis_tvalid\,
      O => enRowbufB_i_2_n_0
    );
enRowbufB_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^rgbvideointomanyaxis_tvalid\,
      I1 => stateGrayegr(1),
      O => enRowbufB_i_3_n_0
    );
enRowbufB_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEE000C"
    )
        port map (
      I0 => oddNotEven_reg_0,
      I1 => stateGrayegr(0),
      I2 => strbEgrstart_reg_n_0,
      I3 => stateGrayegr(1),
      I4 => stateGrayegr(2),
      O => enRowbufB_i_4_n_0
    );
enRowbufB_lcl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFFFCCCC10000000"
    )
        port map (
      I0 => enRowbufB_lcl_i_2_n_0,
      I1 => stateGrayegr(2),
      I2 => \^rgbvideointomanyaxis_tvalid\,
      I3 => stateGrayegr(1),
      I4 => stateGrayegr(0),
      I5 => enRowbufB_lcl_reg_n_0,
      O => enRowbufB_lcl_i_1_n_0
    );
enRowbufB_lcl_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB7D"
    )
        port map (
      I0 => \nop_reg_n_0_[3]\,
      I1 => \nop_reg_n_0_[1]\,
      I2 => \nop_reg_n_0_[2]\,
      I3 => \nop_reg_n_0_[0]\,
      O => enRowbufB_lcl_i_2_n_0
    );
enRowbufB_lcl_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enRowbufB_lcl_reg_0(0),
      D => enRowbufB_lcl_i_1_n_0,
      Q => enRowbufB_lcl_reg_n_0
    );
enRowbufB_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enRowbufB_lcl_reg_0(0),
      D => enRowbufB_i_1_n_0,
      Q => enRowbufB_reg_n_0
    );
enRowbuf_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888888888AA8"
    )
        port map (
      I0 => \col_lcl[4]__1_i_2_n_0\,
      I1 => enRowbuf_i_2_n_0,
      I2 => \stateGraypack[0]_i_2_n_0\,
      I3 => enRowbuf_reg_0(10),
      I4 => enRowbuf_i_3_n_0,
      I5 => enRowbuf_i_4_n_0,
      O => enRowbuf
    );
enRowbuf_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8420"
    )
        port map (
      I0 => \tuv_reg_n_0_[0]\,
      I1 => \tuv_reg_n_0_[1]\,
      I2 => \tuv_reg_n_0_[2]\,
      I3 => \tuv_reg_n_0_[3]\,
      O => enRowbuf_i_2_n_0
    );
enRowbuf_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF9F6FFF6FFFFF6"
    )
        port map (
      I0 => \col_lcl_reg[8]__1_n_0\,
      I1 => enRowbuf_reg_0(8),
      I2 => \stateGraypack[0]_i_5_n_0\,
      I3 => enRowbuf_reg_0(7),
      I4 => enRowbuf_i_5_n_0,
      I5 => \col_lcl_reg[7]__1_n_0\,
      O => enRowbuf_i_3_n_0
    );
enRowbuf_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"955555556AAAAAAA"
    )
        port map (
      I0 => enRowbuf_reg_0(9),
      I1 => \col_lcl_reg[8]__1_n_0\,
      I2 => \col_lcl_reg[6]__1_n_0\,
      I3 => \col_lcl[8]__1_i_2_n_0\,
      I4 => \col_lcl_reg[7]__1_n_0\,
      I5 => \col_lcl_reg[9]__1_n_0\,
      O => enRowbuf_i_4_n_0
    );
enRowbuf_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \col_lcl_reg[6]__1_n_0\,
      I1 => \col_lcl[8]__1_i_2_n_0\,
      O => enRowbuf_i_5_n_0
    );
enRowbuf_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => enRowbuf,
      Q => enRowbuf_reg_n_0
    );
fillBNotA_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FADA0020"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => oddNotEven_reg_0,
      I2 => \^stateigr_reg[1]_0\(0),
      I3 => oddNotEven,
      I4 => fillBNotA_reg_n_0,
      O => fillBNotA_i_1_n_0
    );
fillBNotA_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enRowbufB_lcl_reg_0(0),
      D => fillBNotA_i_1_n_0,
      Q => fillBNotA_reg_n_0
    );
\gr0_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => myRow0buf_n_1,
      Q => \gr0_reg_n_0_[10]\
    );
\gr0_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => myRow0buf_n_0,
      Q => \gr0_reg_n_0_[11]\
    );
\gr0_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => myRow0buf_n_7,
      Q => \gr0_reg_n_0_[4]\
    );
\gr0_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => myRow0buf_n_6,
      Q => \gr0_reg_n_0_[5]\
    );
\gr0_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => myRow0buf_n_5,
      Q => \gr0_reg_n_0_[6]\
    );
\gr0_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => myRow0buf_n_4,
      Q => \gr0_reg_n_0_[7]\
    );
\gr0_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => myRow0buf_n_3,
      Q => \gr0_reg_n_0_[8]\
    );
\gr0_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => myRow0buf_n_2,
      Q => \gr0_reg_n_0_[9]\
    );
\gr1_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr1(10),
      Q => \gr1_reg_n_0_[10]\
    );
\gr1_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr1(11),
      Q => \gr1_reg_n_0_[11]\
    );
\gr1_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr1(4),
      Q => \gr1_reg_n_0_[4]\
    );
\gr1_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr1(5),
      Q => \gr1_reg_n_0_[5]\
    );
\gr1_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr1(6),
      Q => \gr1_reg_n_0_[6]\
    );
\gr1_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr1(7),
      Q => \gr1_reg_n_0_[7]\
    );
\gr1_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr1(8),
      Q => \gr1_reg_n_0_[8]\
    );
\gr1_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr1(9),
      Q => \gr1_reg_n_0_[9]\
    );
\gr2_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr2(10),
      Q => \gr2_reg_n_0_[10]\
    );
\gr2_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr2(11),
      Q => \gr2_reg_n_0_[11]\
    );
\gr2_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr2(4),
      Q => \gr2_reg_n_0_[4]\
    );
\gr2_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr2(5),
      Q => \gr2_reg_n_0_[5]\
    );
\gr2_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr2(6),
      Q => \gr2_reg_n_0_[6]\
    );
\gr2_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr2(7),
      Q => \gr2_reg_n_0_[7]\
    );
\gr2_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr2(8),
      Q => \gr2_reg_n_0_[8]\
    );
\gr2_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr2(9),
      Q => \gr2_reg_n_0_[9]\
    );
\gr3_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr3(10),
      Q => \gr3_reg_n_0_[10]\
    );
\gr3_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr3(11),
      Q => \gr3_reg_n_0_[11]\
    );
\gr3_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr3(4),
      Q => \gr3_reg_n_0_[4]\
    );
\gr3_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr3(5),
      Q => \gr3_reg_n_0_[5]\
    );
\gr3_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr3(6),
      Q => \gr3_reg_n_0_[6]\
    );
\gr3_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr3(7),
      Q => \gr3_reg_n_0_[7]\
    );
\gr3_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr3(8),
      Q => \gr3_reg_n_0_[8]\
    );
\gr3_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr3(9),
      Q => \gr3_reg_n_0_[9]\
    );
\gr4[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0803"
    )
        port map (
      I0 => \^rgbvideointomanyaxis_tvalid\,
      I1 => stateGrayegr(1),
      I2 => stateGrayegr(2),
      I3 => stateGrayegr(0),
      O => \gr4[11]_i_1_n_0\
    );
\gr4_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr4(10),
      Q => \gr4_reg_n_0_[10]\
    );
\gr4_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr4(11),
      Q => \gr4_reg_n_0_[11]\
    );
\gr4_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr4(4),
      Q => \gr4_reg_n_0_[4]\
    );
\gr4_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr4(5),
      Q => \gr4_reg_n_0_[5]\
    );
\gr4_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr4(6),
      Q => \gr4_reg_n_0_[6]\
    );
\gr4_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr4(7),
      Q => \gr4_reg_n_0_[7]\
    );
\gr4_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr4(8),
      Q => \gr4_reg_n_0_[8]\
    );
\gr4_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr4[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr4(9),
      Q => \gr4_reg_n_0_[9]\
    );
\gr[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"21"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      O => \gr[11]_i_1_n_0\
    );
\gr_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr(0),
      Q => p_14_in(0)
    );
\gr_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr(10),
      Q => p_14_in(10)
    );
\gr_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr(11),
      Q => p_14_in(11)
    );
\gr_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr(1),
      Q => p_14_in(1)
    );
\gr_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr(2),
      Q => p_14_in(2)
    );
\gr_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr(3),
      Q => p_14_in(3)
    );
\gr_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr(4),
      Q => p_14_in(4)
    );
\gr_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr(5),
      Q => p_14_in(5)
    );
\gr_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr(6),
      Q => p_14_in(6)
    );
\gr_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr(7),
      Q => p_14_in(7)
    );
\gr_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr(8),
      Q => p_14_in(8)
    );
\gr_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => gr(9),
      Q => p_14_in(9)
    );
grayToManyAXIS_tlast_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEFFEEFF04110011"
    )
        port map (
      I0 => stateGrayegr(2),
      I1 => stateGrayegr(0),
      I2 => \FSM_sequential_stateGrayegr[2]_i_3_n_0\,
      I3 => stateGrayegr(1),
      I4 => \^rgbvideointomanyaxis_tvalid\,
      I5 => \^grayvideointomanyaxis_tlast\,
      O => grayToManyAXIS_tlast_sig_i_1_n_0
    );
grayToManyAXIS_tlast_sig_reg: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => grayToManyAXIS_tlast_sig_i_1_n_0,
      PRE => enRowbufB_lcl_reg_0(0),
      Q => \^grayvideointomanyaxis_tlast\
    );
grayToManyAXIS_tvalid_sig_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBCC0800"
    )
        port map (
      I0 => \^rgbvideointomanyaxis_tvalid\,
      I1 => stateGrayegr(0),
      I2 => stateGrayegr(2),
      I3 => stateGrayegr(1),
      I4 => \^grayvideointomanyaxis_tvalid\,
      O => grayToManyAXIS_tvalid_sig_i_1_n_0
    );
grayToManyAXIS_tvalid_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enRowbufB_lcl_reg_0(0),
      D => grayToManyAXIS_tvalid_sig_i_1_n_0,
      Q => \^grayvideointomanyaxis_tvalid\
    );
\klm[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => \^klm_reg[0]_0\(0),
      O => \klm[0]_i_1_n_0\
    );
\klm[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0060"
    )
        port map (
      I0 => klm(1),
      I1 => \^klm_reg[0]_0\(0),
      I2 => \^stateigr_reg[1]_0\(0),
      I3 => \^stateigr_reg[1]_0\(1),
      O => \klm[1]_i_1_n_0\
    );
\klm[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04444000"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => klm(1),
      I3 => \^klm_reg[0]_0\(0),
      I4 => klm(2),
      O => \klm[2]_i_2_n_0\
    );
\klm_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \klm[0]_i_1_n_0\,
      Q => \^klm_reg[0]_0\(0)
    );
\klm_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \klm[1]_i_1_n_0\,
      Q => klm(1)
    );
\klm_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \klm[2]_i_2_n_0\,
      Q => klm(2)
    );
myEvenAbuf: entity work.\design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64__xdcDup__1\
     port map (
      D(23 downto 0) => rgbToManyAXIS_tdata_sig(35 downto 12),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(63 downto 0) => dwrEobuf(63 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(9) => \aEobufB_reg_n_0_[9]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8) => \aEobufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \aEobufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \aEobufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \aEobufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \aEobufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \aEobufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \aEobufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \aEobufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \aEobufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ => fillBNotA_reg_n_0,
      Q(9) => \aEobuf_reg_n_0_[9]\,
      Q(8) => \aEobuf_reg_n_0_[8]\,
      Q(7) => \aEobuf_reg_n_0_[7]\,
      Q(6) => \aEobuf_reg_n_0_[6]\,
      Q(5) => \aEobuf_reg_n_0_[5]\,
      Q(4) => \aEobuf_reg_n_0_[4]\,
      Q(3) => \aEobuf_reg_n_0_[3]\,
      Q(2) => \aEobuf_reg_n_0_[2]\,
      Q(1) => \aEobuf_reg_n_0_[1]\,
      Q(0) => \aEobuf_reg_n_0_[0]\,
      S(0) => myEvenAbuf_n_28,
      aclk_sig => aclk_sig,
      doutb(15 downto 0) => drdEvenAbufB(63 downto 48),
      enEobuf => enEobuf,
      enEobufB => enEobufB,
      \gr_reg[5]_i_2\ => myOddbuf_n_5,
      \gr_reg[5]_i_2_0\ => myOddbuf_n_4,
      \gr_reg[5]_i_2_1\ => myOddbuf_n_6,
      oddNotEven => oddNotEven,
      p_0_in(11 downto 0) => p_0_in(11 downto 0),
      p_1_in(1 downto 0) => p_1_in(3 downto 2),
      p_3_in(1 downto 0) => p_3_in(1 downto 0),
      \qrs_reg[1]\ => myEvenAbuf_n_32,
      \qrs_reg[1]_0\ => myEvenAbuf_n_33,
      \qrs_reg[1]_1\ => myEvenAbuf_n_34,
      \qrs_reg[1]_2\ => myEvenAbuf_n_36,
      \qrs_reg[1]_3\ => myEvenAbuf_n_37,
      \qrs_reg[1]_4\ => myEvenAbuf_n_38,
      \qrs_reg[1]_5\ => myEvenAbuf_n_40,
      \qrs_reg[2]\ => myEvenAbuf_n_29,
      \qrs_reg[2]_0\ => myEvenAbuf_n_35,
      \qrs_reg[2]_1\ => myEvenAbuf_n_39,
      \rgbToManyAXIS_tdata_sig[18]_i_3_0\(15) => \drdEvenbufBm1_reg_n_0_[63]\,
      \rgbToManyAXIS_tdata_sig[18]_i_3_0\(14) => \drdEvenbufBm1_reg_n_0_[62]\,
      \rgbToManyAXIS_tdata_sig[18]_i_3_0\(13) => \drdEvenbufBm1_reg_n_0_[61]\,
      \rgbToManyAXIS_tdata_sig[18]_i_3_0\(12) => \drdEvenbufBm1_reg_n_0_[60]\,
      \rgbToManyAXIS_tdata_sig[18]_i_3_0\(11 downto 0) => data2(11 downto 0),
      \rgbToManyAXIS_tdata_sig[35]_i_2_0\(63 downto 0) => drdB(63 downto 0),
      \rgbToManyAXIS_tdata_sig_reg[18]\(0) => myOddbuf_n_0,
      \rgbToManyAXIS_tdata_sig_reg[18]_i_2_0\ => myOddbuf_n_2,
      \rgbToManyAXIS_tdata_sig_reg[18]_i_2_1\ => myOddbuf_n_23,
      \rgbToManyAXIS_tdata_sig_reg[18]_i_2_2\ => myOddbuf_n_25,
      \rgbToManyAXIS_tdata_sig_reg[18]_i_2_3\ => myOddbuf_n_22,
      \rgbToManyAXIS_tdata_sig_reg[23]_i_2_0\ => myOddbuf_n_1,
      \rgbToManyAXIS_tdata_sig_reg[23]_i_2_1\ => myOddbuf_n_3,
      \rgbToManyAXIS_tdata_sig_reg[23]_i_2_2\ => myOddbuf_n_24,
      \rgbToManyAXIS_tdata_sig_reg[23]_i_2_3\ => myOddbuf_n_9,
      \rgbToManyAXIS_tdata_sig_reg[28]\(2) => \qrs_reg_n_0_[2]\,
      \rgbToManyAXIS_tdata_sig_reg[28]\(1) => \qrs_reg_n_0_[1]\,
      \rgbToManyAXIS_tdata_sig_reg[28]\(0) => \qrs_reg_n_0_[0]\,
      \rgbToManyAXIS_tdata_sig_reg[35]\(1 downto 0) => \^fsm_sequential_statergbegr_reg[2]_0\(1 downto 0)
    );
myEvenBbuf: entity work.\design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64__xdcDup__2\
     port map (
      D(15 downto 0) => drdEvenbufBm1(63 downto 48),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(63 downto 0) => dwrEobuf(63 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(9) => \aEobufB_reg_n_0_[9]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8) => \aEobufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \aEobufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \aEobufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \aEobufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \aEobufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \aEobufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \aEobufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \aEobufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \aEobufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ => fillBNotA_reg_n_0,
      Q(9) => \aEobuf_reg_n_0_[9]\,
      Q(8) => \aEobuf_reg_n_0_[8]\,
      Q(7) => \aEobuf_reg_n_0_[7]\,
      Q(6) => \aEobuf_reg_n_0_[6]\,
      Q(5) => \aEobuf_reg_n_0_[5]\,
      Q(4) => \aEobuf_reg_n_0_[4]\,
      Q(3) => \aEobuf_reg_n_0_[3]\,
      Q(2) => \aEobuf_reg_n_0_[2]\,
      Q(1) => \aEobuf_reg_n_0_[1]\,
      Q(0) => \aEobuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      doutb(63 downto 0) => drdB(63 downto 0),
      \drdEvenbufBm1_reg[63]\(15 downto 0) => drdEvenAbufB(63 downto 48),
      \drdEvenbufBm1_reg[63]_0\(1 downto 0) => \^fsm_sequential_statergbegr_reg[2]_0\(1 downto 0),
      enEobuf => enEobuf,
      enEobufB => enEobufB,
      oddNotEven => oddNotEven
    );
myOddbuf: entity work.design_1_Vsp_core_0_0_Dpbram_size6kB_a64b64
     port map (
      D(11 downto 0) => rgbToManyAXIS_tdata_sig(11 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(15 downto 0) => drdOddbufBm1(63 downto 48),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(63 downto 0) => dwrEobuf(63 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(9) => \aEobufB_reg_n_0_[9]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(8) => \aEobufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \aEobufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \aEobufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \aEobufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \aEobufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \aEobufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \aEobufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \aEobufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \aEobufB_reg_n_0_[0]\,
      \FSM_sequential_stateRgbegr_reg[1]\(11 downto 0) => gr(11 downto 0),
      Q(9) => \aEobuf_reg_n_0_[9]\,
      Q(8) => \aEobuf_reg_n_0_[8]\,
      Q(7) => \aEobuf_reg_n_0_[7]\,
      Q(6) => \aEobuf_reg_n_0_[6]\,
      Q(5) => \aEobuf_reg_n_0_[5]\,
      Q(4) => \aEobuf_reg_n_0_[4]\,
      Q(3) => \aEobuf_reg_n_0_[3]\,
      Q(2) => \aEobuf_reg_n_0_[2]\,
      Q(1) => \aEobuf_reg_n_0_[1]\,
      Q(0) => \aEobuf_reg_n_0_[0]\,
      S(0) => myEvenAbuf_n_28,
      aclk_sig => aclk_sig,
      \drdOddbufBm1_reg[63]\(1 downto 0) => \^fsm_sequential_statergbegr_reg[2]_0\(1 downto 0),
      enEobuf => enEobuf,
      enEobufB => enEobufB,
      \gr_reg[11]_i_3_0\ => myEvenAbuf_n_35,
      \gr_reg[11]_i_3_1\ => myEvenAbuf_n_34,
      \gr_reg[11]_i_3_2\ => myEvenAbuf_n_37,
      \gr_reg[11]_i_3_3\ => myEvenAbuf_n_40,
      \gr_reg[5]_i_2_0\ => myEvenAbuf_n_33,
      \gr_reg[5]_i_2_1\ => myEvenAbuf_n_32,
      \gr_reg[5]_i_2_2\ => myEvenAbuf_n_29,
      \gr_reg[5]_i_2_3\ => myEvenAbuf_n_36,
      \gr_reg[5]_i_2_4\ => myEvenAbuf_n_38,
      \gr_reg[5]_i_2_5\ => myEvenAbuf_n_39,
      oddNotEven => oddNotEven,
      p_0_in(11 downto 0) => p_0_in(11 downto 0),
      p_1_in(1 downto 0) => p_1_in(3 downto 2),
      p_3_in(1 downto 0) => p_3_in(1 downto 0),
      \qrs_reg[1]\ => myOddbuf_n_1,
      \qrs_reg[1]_0\ => myOddbuf_n_2,
      \qrs_reg[1]_1\ => myOddbuf_n_3,
      \qrs_reg[1]_2\ => myOddbuf_n_9,
      \qrs_reg[1]_3\ => myOddbuf_n_22,
      \qrs_reg[1]_4\ => myOddbuf_n_23,
      \qrs_reg[1]_5\ => myOddbuf_n_24,
      \qrs_reg[1]_6\ => myOddbuf_n_25,
      \qrs_reg[2]\(0) => myOddbuf_n_0,
      \qrs_reg[2]_0\ => myOddbuf_n_4,
      \qrs_reg[2]_1\ => myOddbuf_n_5,
      \qrs_reg[2]_2\ => myOddbuf_n_6,
      \rgbToManyAXIS_tdata_sig_reg[7]\(2) => \qrs_reg_n_0_[2]\,
      \rgbToManyAXIS_tdata_sig_reg[7]\(1) => \qrs_reg_n_0_[1]\,
      \rgbToManyAXIS_tdata_sig_reg[7]\(0) => \qrs_reg_n_0_[0]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(15) => \drdOddbufBm1_reg_n_0_[63]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(14) => \drdOddbufBm1_reg_n_0_[62]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(13) => \drdOddbufBm1_reg_n_0_[61]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(12) => \drdOddbufBm1_reg_n_0_[60]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(11) => \drdOddbufBm1_reg_n_0_[59]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(10) => \drdOddbufBm1_reg_n_0_[58]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(9) => \drdOddbufBm1_reg_n_0_[57]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(8) => \drdOddbufBm1_reg_n_0_[56]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(7) => \drdOddbufBm1_reg_n_0_[55]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(6) => \drdOddbufBm1_reg_n_0_[54]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(5) => \drdOddbufBm1_reg_n_0_[53]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(4) => \drdOddbufBm1_reg_n_0_[52]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(3) => \drdOddbufBm1_reg_n_0_[51]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(2) => \drdOddbufBm1_reg_n_0_[50]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(1) => \drdOddbufBm1_reg_n_0_[49]\,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(0) => \drdOddbufBm1_reg_n_0_[48]\
    );
myRow0buf: entity work.\design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__1\
     port map (
      D(7) => myRow0buf_n_0,
      D(6) => myRow0buf_n_1,
      D(5) => myRow0buf_n_2,
      D(4) => myRow0buf_n_3,
      D(3) => myRow0buf_n_4,
      D(2) => myRow0buf_n_5,
      D(1) => myRow0buf_n_6,
      D(0) => myRow0buf_n_7,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3 downto 0) => drdRow0bufBm1(63 downto 60),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(63) => \dwrRowbuf_reg_n_0_[63]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(62) => \dwrRowbuf_reg_n_0_[62]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(61) => \dwrRowbuf_reg_n_0_[61]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(60) => \dwrRowbuf_reg_n_0_[60]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(59) => \dwrRowbuf_reg_n_0_[59]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(58) => \dwrRowbuf_reg_n_0_[58]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(57) => \dwrRowbuf_reg_n_0_[57]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(56) => \dwrRowbuf_reg_n_0_[56]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(55) => \dwrRowbuf_reg_n_0_[55]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(54) => \dwrRowbuf_reg_n_0_[54]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(53) => \dwrRowbuf_reg_n_0_[53]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(52) => \dwrRowbuf_reg_n_0_[52]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(51) => \dwrRowbuf_reg_n_0_[51]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(50) => \dwrRowbuf_reg_n_0_[50]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(49) => \dwrRowbuf_reg_n_0_[49]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(48) => \dwrRowbuf_reg_n_0_[48]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(47) => \dwrRowbuf_reg_n_0_[47]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(46) => \dwrRowbuf_reg_n_0_[46]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(45) => \dwrRowbuf_reg_n_0_[45]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(44) => \dwrRowbuf_reg_n_0_[44]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(43) => \dwrRowbuf_reg_n_0_[43]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(42) => \dwrRowbuf_reg_n_0_[42]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(41) => \dwrRowbuf_reg_n_0_[41]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(40) => \dwrRowbuf_reg_n_0_[40]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(39) => \dwrRowbuf_reg_n_0_[39]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(38) => \dwrRowbuf_reg_n_0_[38]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(37) => \dwrRowbuf_reg_n_0_[37]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(36) => \dwrRowbuf_reg_n_0_[36]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(35) => \dwrRowbuf_reg_n_0_[35]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(34) => \dwrRowbuf_reg_n_0_[34]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(33) => \dwrRowbuf_reg_n_0_[33]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(32) => \dwrRowbuf_reg_n_0_[32]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(31) => \dwrRowbuf_reg_n_0_[31]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(30) => \dwrRowbuf_reg_n_0_[30]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(29) => \dwrRowbuf_reg_n_0_[29]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(28) => \dwrRowbuf_reg_n_0_[28]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(27) => \dwrRowbuf_reg_n_0_[27]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(26) => \dwrRowbuf_reg_n_0_[26]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(25) => \dwrRowbuf_reg_n_0_[25]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(24) => \dwrRowbuf_reg_n_0_[24]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(23) => \dwrRowbuf_reg_n_0_[23]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(22) => \dwrRowbuf_reg_n_0_[22]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(21) => \dwrRowbuf_reg_n_0_[21]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(20) => \dwrRowbuf_reg_n_0_[20]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(19) => \dwrRowbuf_reg_n_0_[19]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(18) => \dwrRowbuf_reg_n_0_[18]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(17) => \dwrRowbuf_reg_n_0_[17]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(16) => \dwrRowbuf_reg_n_0_[16]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(15) => \dwrRowbuf_reg_n_0_[15]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(14) => \dwrRowbuf_reg_n_0_[14]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(13) => \dwrRowbuf_reg_n_0_[13]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(12) => \dwrRowbuf_reg_n_0_[12]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(11) => \dwrRowbuf_reg_n_0_[11]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(10) => \dwrRowbuf_reg_n_0_[10]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(9) => \dwrRowbuf_reg_n_0_[9]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8) => \dwrRowbuf_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \dwrRowbuf_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \dwrRowbuf_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \dwrRowbuf_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \dwrRowbuf_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \dwrRowbuf_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \dwrRowbuf_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \dwrRowbuf_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \dwrRowbuf_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(8) => \aRowbufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \aRowbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \aRowbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \aRowbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \aRowbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \aRowbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \aRowbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \aRowbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \aRowbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(2) => \abcde_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(1) => \abcde_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0) => \abcde_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ => enRowbuf_reg_n_0,
      Q(8) => \aRowbuf_reg_n_0_[8]\,
      Q(7) => \aRowbuf_reg_n_0_[7]\,
      Q(6) => \aRowbuf_reg_n_0_[6]\,
      Q(5) => \aRowbuf_reg_n_0_[5]\,
      Q(4) => \aRowbuf_reg_n_0_[4]\,
      Q(3) => \aRowbuf_reg_n_0_[3]\,
      Q(2) => \aRowbuf_reg_n_0_[2]\,
      Q(1) => \aRowbuf_reg_n_0_[1]\,
      Q(0) => \aRowbuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      \drdRow0bufBm1_reg[60]\(2 downto 0) => stateGrayegr(2 downto 0),
      enb => enRowbufB_reg_n_0,
      \gr0_reg[4]\(3) => \nop_reg_n_0_[3]\,
      \gr0_reg[4]\(2) => \nop_reg_n_0_[2]\,
      \gr0_reg[4]\(1) => \nop_reg_n_0_[1]\,
      \gr0_reg[4]\(0) => \nop_reg_n_0_[0]\,
      \gr0_reg[4]_0\ => \drdRow4bufBm1[63]_i_3_n_0\,
      \gr0_reg[7]\(3 downto 0) => \data10__3\(7 downto 4)
    );
myRow1buf: entity work.\design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__2\
     port map (
      D(7 downto 0) => gr1(11 downto 4),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3 downto 0) => drdRow1bufBm1(63 downto 60),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(63) => \dwrRowbuf_reg_n_0_[63]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(62) => \dwrRowbuf_reg_n_0_[62]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(61) => \dwrRowbuf_reg_n_0_[61]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(60) => \dwrRowbuf_reg_n_0_[60]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(59) => \dwrRowbuf_reg_n_0_[59]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(58) => \dwrRowbuf_reg_n_0_[58]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(57) => \dwrRowbuf_reg_n_0_[57]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(56) => \dwrRowbuf_reg_n_0_[56]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(55) => \dwrRowbuf_reg_n_0_[55]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(54) => \dwrRowbuf_reg_n_0_[54]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(53) => \dwrRowbuf_reg_n_0_[53]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(52) => \dwrRowbuf_reg_n_0_[52]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(51) => \dwrRowbuf_reg_n_0_[51]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(50) => \dwrRowbuf_reg_n_0_[50]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(49) => \dwrRowbuf_reg_n_0_[49]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(48) => \dwrRowbuf_reg_n_0_[48]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(47) => \dwrRowbuf_reg_n_0_[47]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(46) => \dwrRowbuf_reg_n_0_[46]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(45) => \dwrRowbuf_reg_n_0_[45]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(44) => \dwrRowbuf_reg_n_0_[44]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(43) => \dwrRowbuf_reg_n_0_[43]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(42) => \dwrRowbuf_reg_n_0_[42]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(41) => \dwrRowbuf_reg_n_0_[41]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(40) => \dwrRowbuf_reg_n_0_[40]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(39) => \dwrRowbuf_reg_n_0_[39]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(38) => \dwrRowbuf_reg_n_0_[38]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(37) => \dwrRowbuf_reg_n_0_[37]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(36) => \dwrRowbuf_reg_n_0_[36]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(35) => \dwrRowbuf_reg_n_0_[35]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(34) => \dwrRowbuf_reg_n_0_[34]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(33) => \dwrRowbuf_reg_n_0_[33]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(32) => \dwrRowbuf_reg_n_0_[32]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(31) => \dwrRowbuf_reg_n_0_[31]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(30) => \dwrRowbuf_reg_n_0_[30]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(29) => \dwrRowbuf_reg_n_0_[29]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(28) => \dwrRowbuf_reg_n_0_[28]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(27) => \dwrRowbuf_reg_n_0_[27]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(26) => \dwrRowbuf_reg_n_0_[26]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(25) => \dwrRowbuf_reg_n_0_[25]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(24) => \dwrRowbuf_reg_n_0_[24]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(23) => \dwrRowbuf_reg_n_0_[23]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(22) => \dwrRowbuf_reg_n_0_[22]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(21) => \dwrRowbuf_reg_n_0_[21]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(20) => \dwrRowbuf_reg_n_0_[20]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(19) => \dwrRowbuf_reg_n_0_[19]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(18) => \dwrRowbuf_reg_n_0_[18]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(17) => \dwrRowbuf_reg_n_0_[17]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(16) => \dwrRowbuf_reg_n_0_[16]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(15) => \dwrRowbuf_reg_n_0_[15]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(14) => \dwrRowbuf_reg_n_0_[14]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(13) => \dwrRowbuf_reg_n_0_[13]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(12) => \dwrRowbuf_reg_n_0_[12]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(11) => \dwrRowbuf_reg_n_0_[11]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(10) => \dwrRowbuf_reg_n_0_[10]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(9) => \dwrRowbuf_reg_n_0_[9]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8) => \dwrRowbuf_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \dwrRowbuf_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \dwrRowbuf_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \dwrRowbuf_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \dwrRowbuf_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \dwrRowbuf_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \dwrRowbuf_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \dwrRowbuf_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \dwrRowbuf_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(8) => \aRowbufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \aRowbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \aRowbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \aRowbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \aRowbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \aRowbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \aRowbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \aRowbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \aRowbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(2) => \abcde_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(1) => \abcde_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0) => \abcde_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ => enRowbuf_reg_n_0,
      Q(8) => \aRowbuf_reg_n_0_[8]\,
      Q(7) => \aRowbuf_reg_n_0_[7]\,
      Q(6) => \aRowbuf_reg_n_0_[6]\,
      Q(5) => \aRowbuf_reg_n_0_[5]\,
      Q(4) => \aRowbuf_reg_n_0_[4]\,
      Q(3) => \aRowbuf_reg_n_0_[3]\,
      Q(2) => \aRowbuf_reg_n_0_[2]\,
      Q(1) => \aRowbuf_reg_n_0_[1]\,
      Q(0) => \aRowbuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      \drdRow1bufBm1_reg[60]\(2 downto 0) => stateGrayegr(2 downto 0),
      enb => enRowbufB_reg_n_0,
      \gr1_reg[4]\(3) => \nop_reg_n_0_[3]\,
      \gr1_reg[4]\(2) => \nop_reg_n_0_[2]\,
      \gr1_reg[4]\(1) => \nop_reg_n_0_[1]\,
      \gr1_reg[4]\(0) => \nop_reg_n_0_[0]\,
      \gr1_reg[4]_0\ => \drdRow4bufBm1[63]_i_3_n_0\,
      \gr1_reg[7]\(3 downto 0) => \data10__2\(7 downto 4)
    );
myRow2buf: entity work.\design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__3\
     port map (
      D(7 downto 0) => gr2(11 downto 4),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3 downto 0) => drdRow2bufBm1(63 downto 60),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(63) => \dwrRowbuf_reg_n_0_[63]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(62) => \dwrRowbuf_reg_n_0_[62]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(61) => \dwrRowbuf_reg_n_0_[61]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(60) => \dwrRowbuf_reg_n_0_[60]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(59) => \dwrRowbuf_reg_n_0_[59]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(58) => \dwrRowbuf_reg_n_0_[58]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(57) => \dwrRowbuf_reg_n_0_[57]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(56) => \dwrRowbuf_reg_n_0_[56]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(55) => \dwrRowbuf_reg_n_0_[55]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(54) => \dwrRowbuf_reg_n_0_[54]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(53) => \dwrRowbuf_reg_n_0_[53]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(52) => \dwrRowbuf_reg_n_0_[52]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(51) => \dwrRowbuf_reg_n_0_[51]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(50) => \dwrRowbuf_reg_n_0_[50]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(49) => \dwrRowbuf_reg_n_0_[49]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(48) => \dwrRowbuf_reg_n_0_[48]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(47) => \dwrRowbuf_reg_n_0_[47]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(46) => \dwrRowbuf_reg_n_0_[46]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(45) => \dwrRowbuf_reg_n_0_[45]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(44) => \dwrRowbuf_reg_n_0_[44]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(43) => \dwrRowbuf_reg_n_0_[43]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(42) => \dwrRowbuf_reg_n_0_[42]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(41) => \dwrRowbuf_reg_n_0_[41]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(40) => \dwrRowbuf_reg_n_0_[40]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(39) => \dwrRowbuf_reg_n_0_[39]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(38) => \dwrRowbuf_reg_n_0_[38]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(37) => \dwrRowbuf_reg_n_0_[37]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(36) => \dwrRowbuf_reg_n_0_[36]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(35) => \dwrRowbuf_reg_n_0_[35]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(34) => \dwrRowbuf_reg_n_0_[34]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(33) => \dwrRowbuf_reg_n_0_[33]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(32) => \dwrRowbuf_reg_n_0_[32]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(31) => \dwrRowbuf_reg_n_0_[31]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(30) => \dwrRowbuf_reg_n_0_[30]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(29) => \dwrRowbuf_reg_n_0_[29]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(28) => \dwrRowbuf_reg_n_0_[28]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(27) => \dwrRowbuf_reg_n_0_[27]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(26) => \dwrRowbuf_reg_n_0_[26]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(25) => \dwrRowbuf_reg_n_0_[25]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(24) => \dwrRowbuf_reg_n_0_[24]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(23) => \dwrRowbuf_reg_n_0_[23]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(22) => \dwrRowbuf_reg_n_0_[22]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(21) => \dwrRowbuf_reg_n_0_[21]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(20) => \dwrRowbuf_reg_n_0_[20]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(19) => \dwrRowbuf_reg_n_0_[19]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(18) => \dwrRowbuf_reg_n_0_[18]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(17) => \dwrRowbuf_reg_n_0_[17]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(16) => \dwrRowbuf_reg_n_0_[16]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(15) => \dwrRowbuf_reg_n_0_[15]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(14) => \dwrRowbuf_reg_n_0_[14]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(13) => \dwrRowbuf_reg_n_0_[13]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(12) => \dwrRowbuf_reg_n_0_[12]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(11) => \dwrRowbuf_reg_n_0_[11]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(10) => \dwrRowbuf_reg_n_0_[10]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(9) => \dwrRowbuf_reg_n_0_[9]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8) => \dwrRowbuf_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \dwrRowbuf_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \dwrRowbuf_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \dwrRowbuf_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \dwrRowbuf_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \dwrRowbuf_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \dwrRowbuf_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \dwrRowbuf_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \dwrRowbuf_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(8) => \aRowbufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \aRowbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \aRowbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \aRowbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \aRowbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \aRowbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \aRowbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \aRowbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \aRowbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(2) => \abcde_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(1) => \abcde_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0) => \abcde_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ => enRowbuf_reg_n_0,
      Q(8) => \aRowbuf_reg_n_0_[8]\,
      Q(7) => \aRowbuf_reg_n_0_[7]\,
      Q(6) => \aRowbuf_reg_n_0_[6]\,
      Q(5) => \aRowbuf_reg_n_0_[5]\,
      Q(4) => \aRowbuf_reg_n_0_[4]\,
      Q(3) => \aRowbuf_reg_n_0_[3]\,
      Q(2) => \aRowbuf_reg_n_0_[2]\,
      Q(1) => \aRowbuf_reg_n_0_[1]\,
      Q(0) => \aRowbuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      \drdRow2bufBm1_reg[60]\(2 downto 0) => stateGrayegr(2 downto 0),
      enb => enRowbufB_reg_n_0,
      \gr2_reg[4]\(3) => \nop_reg_n_0_[3]\,
      \gr2_reg[4]\(2) => \nop_reg_n_0_[2]\,
      \gr2_reg[4]\(1) => \nop_reg_n_0_[1]\,
      \gr2_reg[4]\(0) => \nop_reg_n_0_[0]\,
      \gr2_reg[4]_0\ => \drdRow4bufBm1[63]_i_3_n_0\,
      \gr2_reg[7]\(3 downto 0) => \data10__1\(7 downto 4)
    );
myRow3buf: entity work.\design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64__xdcDup__4\
     port map (
      D(7 downto 0) => gr3(11 downto 4),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3 downto 0) => drdRow3bufBm1(63 downto 60),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(63) => \dwrRowbuf_reg_n_0_[63]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(62) => \dwrRowbuf_reg_n_0_[62]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(61) => \dwrRowbuf_reg_n_0_[61]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(60) => \dwrRowbuf_reg_n_0_[60]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(59) => \dwrRowbuf_reg_n_0_[59]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(58) => \dwrRowbuf_reg_n_0_[58]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(57) => \dwrRowbuf_reg_n_0_[57]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(56) => \dwrRowbuf_reg_n_0_[56]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(55) => \dwrRowbuf_reg_n_0_[55]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(54) => \dwrRowbuf_reg_n_0_[54]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(53) => \dwrRowbuf_reg_n_0_[53]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(52) => \dwrRowbuf_reg_n_0_[52]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(51) => \dwrRowbuf_reg_n_0_[51]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(50) => \dwrRowbuf_reg_n_0_[50]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(49) => \dwrRowbuf_reg_n_0_[49]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(48) => \dwrRowbuf_reg_n_0_[48]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(47) => \dwrRowbuf_reg_n_0_[47]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(46) => \dwrRowbuf_reg_n_0_[46]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(45) => \dwrRowbuf_reg_n_0_[45]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(44) => \dwrRowbuf_reg_n_0_[44]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(43) => \dwrRowbuf_reg_n_0_[43]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(42) => \dwrRowbuf_reg_n_0_[42]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(41) => \dwrRowbuf_reg_n_0_[41]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(40) => \dwrRowbuf_reg_n_0_[40]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(39) => \dwrRowbuf_reg_n_0_[39]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(38) => \dwrRowbuf_reg_n_0_[38]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(37) => \dwrRowbuf_reg_n_0_[37]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(36) => \dwrRowbuf_reg_n_0_[36]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(35) => \dwrRowbuf_reg_n_0_[35]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(34) => \dwrRowbuf_reg_n_0_[34]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(33) => \dwrRowbuf_reg_n_0_[33]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(32) => \dwrRowbuf_reg_n_0_[32]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(31) => \dwrRowbuf_reg_n_0_[31]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(30) => \dwrRowbuf_reg_n_0_[30]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(29) => \dwrRowbuf_reg_n_0_[29]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(28) => \dwrRowbuf_reg_n_0_[28]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(27) => \dwrRowbuf_reg_n_0_[27]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(26) => \dwrRowbuf_reg_n_0_[26]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(25) => \dwrRowbuf_reg_n_0_[25]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(24) => \dwrRowbuf_reg_n_0_[24]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(23) => \dwrRowbuf_reg_n_0_[23]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(22) => \dwrRowbuf_reg_n_0_[22]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(21) => \dwrRowbuf_reg_n_0_[21]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(20) => \dwrRowbuf_reg_n_0_[20]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(19) => \dwrRowbuf_reg_n_0_[19]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(18) => \dwrRowbuf_reg_n_0_[18]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(17) => \dwrRowbuf_reg_n_0_[17]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(16) => \dwrRowbuf_reg_n_0_[16]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(15) => \dwrRowbuf_reg_n_0_[15]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(14) => \dwrRowbuf_reg_n_0_[14]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(13) => \dwrRowbuf_reg_n_0_[13]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(12) => \dwrRowbuf_reg_n_0_[12]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(11) => \dwrRowbuf_reg_n_0_[11]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(10) => \dwrRowbuf_reg_n_0_[10]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(9) => \dwrRowbuf_reg_n_0_[9]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8) => \dwrRowbuf_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \dwrRowbuf_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \dwrRowbuf_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \dwrRowbuf_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \dwrRowbuf_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \dwrRowbuf_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \dwrRowbuf_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \dwrRowbuf_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \dwrRowbuf_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(8) => \aRowbufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \aRowbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \aRowbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \aRowbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \aRowbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \aRowbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \aRowbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \aRowbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \aRowbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(2) => \abcde_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(1) => \abcde_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0) => \abcde_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ => enRowbuf_reg_n_0,
      Q(8) => \aRowbuf_reg_n_0_[8]\,
      Q(7) => \aRowbuf_reg_n_0_[7]\,
      Q(6) => \aRowbuf_reg_n_0_[6]\,
      Q(5) => \aRowbuf_reg_n_0_[5]\,
      Q(4) => \aRowbuf_reg_n_0_[4]\,
      Q(3) => \aRowbuf_reg_n_0_[3]\,
      Q(2) => \aRowbuf_reg_n_0_[2]\,
      Q(1) => \aRowbuf_reg_n_0_[1]\,
      Q(0) => \aRowbuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      \drdRow3bufBm1_reg[60]\(2 downto 0) => stateGrayegr(2 downto 0),
      enb => enRowbufB_reg_n_0,
      \gr3_reg[4]\(3) => \nop_reg_n_0_[3]\,
      \gr3_reg[4]\(2) => \nop_reg_n_0_[2]\,
      \gr3_reg[4]\(1) => \nop_reg_n_0_[1]\,
      \gr3_reg[4]\(0) => \nop_reg_n_0_[0]\,
      \gr3_reg[4]_0\ => \drdRow4bufBm1[63]_i_3_n_0\,
      \gr3_reg[7]\(3 downto 0) => \data10__0\(7 downto 4)
    );
myRow4buf: entity work.design_1_Vsp_core_0_0_Dpbram_size4kB_a64b64
     port map (
      D(7 downto 0) => gr4(11 downto 4),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3 downto 0) => drdRow4bufBm1(63 downto 60),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(63) => \dwrRowbuf_reg_n_0_[63]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(62) => \dwrRowbuf_reg_n_0_[62]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(61) => \dwrRowbuf_reg_n_0_[61]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(60) => \dwrRowbuf_reg_n_0_[60]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(59) => \dwrRowbuf_reg_n_0_[59]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(58) => \dwrRowbuf_reg_n_0_[58]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(57) => \dwrRowbuf_reg_n_0_[57]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(56) => \dwrRowbuf_reg_n_0_[56]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(55) => \dwrRowbuf_reg_n_0_[55]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(54) => \dwrRowbuf_reg_n_0_[54]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(53) => \dwrRowbuf_reg_n_0_[53]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(52) => \dwrRowbuf_reg_n_0_[52]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(51) => \dwrRowbuf_reg_n_0_[51]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(50) => \dwrRowbuf_reg_n_0_[50]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(49) => \dwrRowbuf_reg_n_0_[49]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(48) => \dwrRowbuf_reg_n_0_[48]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(47) => \dwrRowbuf_reg_n_0_[47]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(46) => \dwrRowbuf_reg_n_0_[46]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(45) => \dwrRowbuf_reg_n_0_[45]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(44) => \dwrRowbuf_reg_n_0_[44]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(43) => \dwrRowbuf_reg_n_0_[43]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(42) => \dwrRowbuf_reg_n_0_[42]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(41) => \dwrRowbuf_reg_n_0_[41]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(40) => \dwrRowbuf_reg_n_0_[40]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(39) => \dwrRowbuf_reg_n_0_[39]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(38) => \dwrRowbuf_reg_n_0_[38]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(37) => \dwrRowbuf_reg_n_0_[37]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(36) => \dwrRowbuf_reg_n_0_[36]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(35) => \dwrRowbuf_reg_n_0_[35]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(34) => \dwrRowbuf_reg_n_0_[34]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(33) => \dwrRowbuf_reg_n_0_[33]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(32) => \dwrRowbuf_reg_n_0_[32]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(31) => \dwrRowbuf_reg_n_0_[31]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(30) => \dwrRowbuf_reg_n_0_[30]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(29) => \dwrRowbuf_reg_n_0_[29]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(28) => \dwrRowbuf_reg_n_0_[28]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(27) => \dwrRowbuf_reg_n_0_[27]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(26) => \dwrRowbuf_reg_n_0_[26]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(25) => \dwrRowbuf_reg_n_0_[25]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(24) => \dwrRowbuf_reg_n_0_[24]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(23) => \dwrRowbuf_reg_n_0_[23]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(22) => \dwrRowbuf_reg_n_0_[22]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(21) => \dwrRowbuf_reg_n_0_[21]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(20) => \dwrRowbuf_reg_n_0_[20]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(19) => \dwrRowbuf_reg_n_0_[19]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(18) => \dwrRowbuf_reg_n_0_[18]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(17) => \dwrRowbuf_reg_n_0_[17]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(16) => \dwrRowbuf_reg_n_0_[16]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(15) => \dwrRowbuf_reg_n_0_[15]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(14) => \dwrRowbuf_reg_n_0_[14]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(13) => \dwrRowbuf_reg_n_0_[13]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(12) => \dwrRowbuf_reg_n_0_[12]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(11) => \dwrRowbuf_reg_n_0_[11]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(10) => \dwrRowbuf_reg_n_0_[10]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(9) => \dwrRowbuf_reg_n_0_[9]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8) => \dwrRowbuf_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \dwrRowbuf_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \dwrRowbuf_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \dwrRowbuf_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \dwrRowbuf_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \dwrRowbuf_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \dwrRowbuf_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \dwrRowbuf_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \dwrRowbuf_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(8) => \aRowbufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \aRowbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \aRowbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \aRowbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \aRowbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \aRowbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \aRowbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \aRowbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \aRowbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ => enRowbuf_reg_n_0,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(2) => \abcde_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(1) => \abcde_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0) => \abcde_reg_n_0_[0]\,
      Q(8) => \aRowbuf_reg_n_0_[8]\,
      Q(7) => \aRowbuf_reg_n_0_[7]\,
      Q(6) => \aRowbuf_reg_n_0_[6]\,
      Q(5) => \aRowbuf_reg_n_0_[5]\,
      Q(4) => \aRowbuf_reg_n_0_[4]\,
      Q(3) => \aRowbuf_reg_n_0_[3]\,
      Q(2) => \aRowbuf_reg_n_0_[2]\,
      Q(1) => \aRowbuf_reg_n_0_[1]\,
      Q(0) => \aRowbuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      \drdRow4bufBm1_reg[60]\(2 downto 0) => stateGrayegr(2 downto 0),
      enb => enRowbufB_reg_n_0,
      \gr4_reg[4]\(3) => \nop_reg_n_0_[3]\,
      \gr4_reg[4]\(2) => \nop_reg_n_0_[2]\,
      \gr4_reg[4]\(1) => \nop_reg_n_0_[1]\,
      \gr4_reg[4]\(0) => \nop_reg_n_0_[0]\,
      \gr4_reg[4]_0\ => \drdRow4bufBm1[63]_i_3_n_0\,
      \gr4_reg[7]\(3 downto 0) => data10(7 downto 4)
    );
\nop[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => stateGrayegr(1),
      I1 => stateGrayegr(0),
      I2 => stateGrayegr(2),
      I3 => \nop_reg_n_0_[0]\,
      O => nop(0)
    );
\nop[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080800"
    )
        port map (
      I0 => stateGrayegr(1),
      I1 => stateGrayegr(0),
      I2 => stateGrayegr(2),
      I3 => \nop_reg_n_0_[0]\,
      I4 => \nop_reg_n_0_[1]\,
      O => nop(1)
    );
\nop[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008080808000000"
    )
        port map (
      I0 => stateGrayegr(1),
      I1 => stateGrayegr(0),
      I2 => stateGrayegr(2),
      I3 => \nop_reg_n_0_[1]\,
      I4 => \nop_reg_n_0_[0]\,
      I5 => \nop_reg_n_0_[2]\,
      O => nop(2)
    );
\nop[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0003A00F"
    )
        port map (
      I0 => \^rgbvideointomanyaxis_tvalid\,
      I1 => oddNotEven_reg_0,
      I2 => stateGrayegr(1),
      I3 => stateGrayegr(0),
      I4 => stateGrayegr(2),
      O => \nop[3]_i_1_n_0\
    );
\nop[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \nop[3]_i_3_n_0\,
      I1 => \nop_reg_n_0_[0]\,
      I2 => \nop_reg_n_0_[1]\,
      I3 => \nop_reg_n_0_[2]\,
      I4 => \nop_reg_n_0_[3]\,
      O => nop(3)
    );
\nop[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => stateGrayegr(2),
      I1 => stateGrayegr(0),
      I2 => stateGrayegr(1),
      O => \nop[3]_i_3_n_0\
    );
\nop_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => nop(0),
      Q => \nop_reg_n_0_[0]\
    );
\nop_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => nop(1),
      Q => \nop_reg_n_0_[1]\
    );
\nop_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => nop(2),
      Q => \nop_reg_n_0_[2]\
    );
\nop_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \nop[3]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => nop(3),
      Q => \nop_reg_n_0_[3]\
    );
oddNotEven_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BC40"
    )
        port map (
      I0 => oddNotEven_reg_0,
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => \^stateigr_reg[1]_0\(1),
      I3 => oddNotEven,
      O => oddNotEven_i_1_n_0
    );
oddNotEven_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enRowbufB_lcl_reg_0(0),
      D => oddNotEven_i_1_n_0,
      Q => oddNotEven
    );
\qrs[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I3 => \qrs_reg_n_0_[0]\,
      O => qrs(0)
    );
\qrs[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080800"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I3 => \qrs_reg_n_0_[1]\,
      I4 => \qrs_reg_n_0_[0]\,
      O => qrs(1)
    );
\qrs[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3007"
    )
        port map (
      I0 => oddNotEven_reg_0,
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I3 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      O => \qrs[2]_i_1_n_0\
    );
\qrs[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008080808000000"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I3 => \qrs_reg_n_0_[0]\,
      I4 => \qrs_reg_n_0_[1]\,
      I5 => \qrs_reg_n_0_[2]\,
      O => qrs(2)
    );
\qrs_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \qrs[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => qrs(0),
      Q => \qrs_reg_n_0_[0]\
    );
\qrs_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \qrs[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => qrs(1),
      Q => \qrs_reg_n_0_[1]\
    );
\qrs_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \qrs[2]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => qrs(2),
      Q => \qrs_reg_n_0_[2]\
    );
\rawcolEgrstart[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F1"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => rawcolEgrstart(3),
      O => \rawcolEgrstart[3]_i_1_n_0\
    );
\rawcolEgrstart_reg[3]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      D => \rawcolEgrstart[3]_i_1_n_0\,
      PRE => enRowbufB_lcl_reg_0(0),
      Q => rawcolEgrstart(3)
    );
\rawcol_lcl[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => rawcol_lcl(0),
      O => \rawcol_lcl[0]_i_1_n_0\
    );
\rawcol_lcl[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"14440000"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => rawcol_lcl(10),
      I2 => rawcol_lcl(9),
      I3 => \rawcol_lcl[11]_i_2_n_0\,
      I4 => \^stateigr_reg[1]_0\(0),
      O => \rawcol_lcl[10]_i_1_n_0\
    );
\rawcol_lcl[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0440404040404040"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => rawcol_lcl(11),
      I3 => \rawcol_lcl[11]_i_2_n_0\,
      I4 => rawcol_lcl(9),
      I5 => rawcol_lcl(10),
      O => \rawcol_lcl[11]_i_1_n_0\
    );
\rawcol_lcl[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => rawcol_lcl(7),
      I1 => rawcol_lcl(5),
      I2 => \rawcol_lcl[6]_i_2_n_0\,
      I3 => rawcol_lcl(4),
      I4 => rawcol_lcl(6),
      I5 => rawcol_lcl(8),
      O => \rawcol_lcl[11]_i_2_n_0\
    );
\rawcol_lcl[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0220"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => rawcol_lcl(0),
      I3 => rawcol_lcl(1),
      O => \rawcol_lcl[1]_i_1_n_0\
    );
\rawcol_lcl[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04404040"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => rawcol_lcl(2),
      I3 => rawcol_lcl(1),
      I4 => rawcol_lcl(0),
      O => \rawcol_lcl[2]_i_1_n_0\
    );
\rawcol_lcl[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0220202020202020"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => rawcol_lcl(3),
      I3 => rawcol_lcl(2),
      I4 => rawcol_lcl(1),
      I5 => rawcol_lcl(0),
      O => \rawcol_lcl[3]_i_1_n_0\
    );
\rawcol_lcl[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4004404040404040"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => rawcol_lcl(4),
      I3 => \rawcol_lcl[4]_i_2_n_0\,
      I4 => rawcol_lcl(2),
      I5 => rawcol_lcl(3),
      O => \rawcol_lcl[4]_i_1_n_0\
    );
\rawcol_lcl[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => rawcol_lcl(0),
      I1 => rawcol_lcl(1),
      O => \rawcol_lcl[4]_i_2_n_0\
    );
\rawcol_lcl[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04404040"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => rawcol_lcl(5),
      I3 => rawcol_lcl(4),
      I4 => \rawcol_lcl[6]_i_2_n_0\,
      O => \rawcol_lcl[5]_i_1_n_0\
    );
\rawcol_lcl[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0440404040404040"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => rawcol_lcl(6),
      I3 => rawcol_lcl(5),
      I4 => \rawcol_lcl[6]_i_2_n_0\,
      I5 => rawcol_lcl(4),
      O => \rawcol_lcl[6]_i_1_n_0\
    );
\rawcol_lcl[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => rawcol_lcl(3),
      I1 => rawcol_lcl(2),
      I2 => rawcol_lcl(1),
      I3 => rawcol_lcl(0),
      O => \rawcol_lcl[6]_i_2_n_0\
    );
\rawcol_lcl[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04404040"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => rawcol_lcl(7),
      I3 => rawcol_lcl(6),
      I4 => \rawcol_lcl[8]_i_2_n_0\,
      O => \rawcol_lcl[7]_i_1_n_0\
    );
\rawcol_lcl[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0440404040404040"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => rawcol_lcl(8),
      I3 => rawcol_lcl(7),
      I4 => \rawcol_lcl[8]_i_2_n_0\,
      I5 => rawcol_lcl(6),
      O => \rawcol_lcl[8]_i_1_n_0\
    );
\rawcol_lcl[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => rawcol_lcl(4),
      I1 => rawcol_lcl(3),
      I2 => rawcol_lcl(2),
      I3 => rawcol_lcl(1),
      I4 => rawcol_lcl(0),
      I5 => rawcol_lcl(5),
      O => \rawcol_lcl[8]_i_2_n_0\
    );
\rawcol_lcl[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0440404040404040"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      I2 => rawcol_lcl(9),
      I3 => rawcol_lcl(8),
      I4 => \rawcol_lcl[9]_i_2_n_0\,
      I5 => rawcol_lcl(7),
      O => \rawcol_lcl[9]_i_1_n_0\
    );
\rawcol_lcl[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000000000000000"
    )
        port map (
      I0 => rawcol_lcl(5),
      I1 => \rawcol_lcl[4]_i_2_n_0\,
      I2 => rawcol_lcl(2),
      I3 => rawcol_lcl(3),
      I4 => rawcol_lcl(4),
      I5 => rawcol_lcl(6),
      O => \rawcol_lcl[9]_i_2_n_0\
    );
\rawcol_lcl_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \rawcol_lcl[0]_i_1_n_0\,
      Q => rawcol_lcl(0)
    );
\rawcol_lcl_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \rawcol_lcl[10]_i_1_n_0\,
      Q => rawcol_lcl(10)
    );
\rawcol_lcl_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \rawcol_lcl[11]_i_1_n_0\,
      Q => rawcol_lcl(11)
    );
\rawcol_lcl_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \rawcol_lcl[1]_i_1_n_0\,
      Q => rawcol_lcl(1)
    );
\rawcol_lcl_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \rawcol_lcl[2]_i_1_n_0\,
      Q => rawcol_lcl(2)
    );
\rawcol_lcl_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \rawcol_lcl[3]_i_1_n_0\,
      Q => rawcol_lcl(3)
    );
\rawcol_lcl_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \rawcol_lcl[4]_i_1_n_0\,
      Q => rawcol_lcl(4)
    );
\rawcol_lcl_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \rawcol_lcl[5]_i_1_n_0\,
      Q => rawcol_lcl(5)
    );
\rawcol_lcl_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \rawcol_lcl[6]_i_1_n_0\,
      Q => rawcol_lcl(6)
    );
\rawcol_lcl_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \rawcol_lcl[7]_i_1_n_0\,
      Q => rawcol_lcl(7)
    );
\rawcol_lcl_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \rawcol_lcl[8]_i_1_n_0\,
      Q => rawcol_lcl(8)
    );
\rawcol_lcl_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => E(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => \rawcol_lcl[9]_i_1_n_0\,
      Q => rawcol_lcl(9)
    );
\rgbToManyAXIS_tdata_sig_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(0),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(0)
    );
\rgbToManyAXIS_tdata_sig_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(10),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(10)
    );
\rgbToManyAXIS_tdata_sig_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(11),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(11)
    );
\rgbToManyAXIS_tdata_sig_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(12),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(12)
    );
\rgbToManyAXIS_tdata_sig_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(13),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(13)
    );
\rgbToManyAXIS_tdata_sig_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(14),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(14)
    );
\rgbToManyAXIS_tdata_sig_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(15),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(15)
    );
\rgbToManyAXIS_tdata_sig_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(16),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(16)
    );
\rgbToManyAXIS_tdata_sig_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(17),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(17)
    );
\rgbToManyAXIS_tdata_sig_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(18),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(18)
    );
\rgbToManyAXIS_tdata_sig_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(19),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(19)
    );
\rgbToManyAXIS_tdata_sig_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(1),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(1)
    );
\rgbToManyAXIS_tdata_sig_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(20),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(20)
    );
\rgbToManyAXIS_tdata_sig_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(21),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(21)
    );
\rgbToManyAXIS_tdata_sig_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(22),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(22)
    );
\rgbToManyAXIS_tdata_sig_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(23),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(23)
    );
\rgbToManyAXIS_tdata_sig_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(24),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(24)
    );
\rgbToManyAXIS_tdata_sig_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(25),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(25)
    );
\rgbToManyAXIS_tdata_sig_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(26),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(26)
    );
\rgbToManyAXIS_tdata_sig_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(27),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(27)
    );
\rgbToManyAXIS_tdata_sig_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(28),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(28)
    );
\rgbToManyAXIS_tdata_sig_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(29),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(29)
    );
\rgbToManyAXIS_tdata_sig_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(2),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(2)
    );
\rgbToManyAXIS_tdata_sig_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(30),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(30)
    );
\rgbToManyAXIS_tdata_sig_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(31),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(31)
    );
\rgbToManyAXIS_tdata_sig_reg[32]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(32),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(32)
    );
\rgbToManyAXIS_tdata_sig_reg[33]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(33),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(33)
    );
\rgbToManyAXIS_tdata_sig_reg[34]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(34),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(34)
    );
\rgbToManyAXIS_tdata_sig_reg[35]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(35),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(35)
    );
\rgbToManyAXIS_tdata_sig_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(3),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(3)
    );
\rgbToManyAXIS_tdata_sig_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(4),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(4)
    );
\rgbToManyAXIS_tdata_sig_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(5),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(5)
    );
\rgbToManyAXIS_tdata_sig_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(6),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(6)
    );
\rgbToManyAXIS_tdata_sig_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(7),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(7)
    );
\rgbToManyAXIS_tdata_sig_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(8),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(8)
    );
\rgbToManyAXIS_tdata_sig_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \gr[11]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tdata_sig(9),
      Q => \^rgbtomanyaxis_tdata_sig_reg[35]_0\(9)
    );
rgbToManyAXIS_tlast_sig_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBFB0901"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I3 => rgbToManyAXIS_tlast_sig_i_2_n_0,
      I4 => \^rgbtomanyaxis_tlast_sig_reg_0\,
      O => rgbToManyAXIS_tlast_sig_i_1_n_0
    );
rgbToManyAXIS_tlast_sig_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000400440040000"
    )
        port map (
      I0 => rgbToManyAXIS_tlast_sig_i_3_n_0,
      I1 => enEobufB_reg_0,
      I2 => rgbToManyAXIS_tlast_sig_i_5_n_0,
      I3 => enRowbuf_reg_0(8),
      I4 => \col_lcl[10]_i_2__1_n_0\,
      I5 => enRowbuf_reg_0(10),
      O => rgbToManyAXIS_tlast_sig_i_2_n_0
    );
rgbToManyAXIS_tlast_sig_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"955555556AAAAAAA"
    )
        port map (
      I0 => enRowbuf_reg_0(9),
      I1 => \col_lcl_reg_n_0_[8]\,
      I2 => \^q\(3),
      I3 => \^col_lcl_reg[5]_0\,
      I4 => \^q\(4),
      I5 => \col_lcl_reg_n_0_[9]\,
      O => rgbToManyAXIS_tlast_sig_i_3_n_0
    );
rgbToManyAXIS_tlast_sig_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \col_lcl_reg_n_0_[8]\,
      I1 => \^q\(3),
      I2 => \^col_lcl_reg[5]_0\,
      I3 => \^q\(4),
      O => rgbToManyAXIS_tlast_sig_i_5_n_0
    );
rgbToManyAXIS_tlast_sig_i_8: unisim.vcomponents.LUT5
    generic map(
      INIT => X"95556AAA"
    )
        port map (
      I0 => enRowbuf_reg_0(3),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \col_lcl_reg_n_0_[3]\,
      O => \NColRaw_sig_reg[4]\
    );
rgbToManyAXIS_tlast_sig_i_9: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \col_lcl_reg_n_0_[4]\,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \col_lcl_reg_n_0_[3]\,
      O => \col_lcl_reg[4]_0\
    );
rgbToManyAXIS_tlast_sig_reg: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => rgbToManyAXIS_tlast_sig_i_1_n_0,
      PRE => enRowbufB_lcl_reg_0(0),
      Q => \^rgbtomanyaxis_tlast_sig_reg_0\
    );
rgbToManyAXIS_tvalid_sig_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CE08"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I3 => \^rgbvideointomanyaxis_tvalid\,
      O => rgbToManyAXIS_tvalid_sig_i_1_n_0
    );
rgbToManyAXIS_tvalid_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enRowbufB_lcl_reg_0(0),
      D => rgbToManyAXIS_tvalid_sig_i_1_n_0,
      Q => \^rgbvideointomanyaxis_tvalid\
    );
\stateGraypack[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000600FF0006FF"
    )
        port map (
      I0 => \stateGraypack[0]_i_2_n_0\,
      I1 => enRowbuf_reg_0(10),
      I2 => \stateGraypack[0]_i_3_n_0\,
      I3 => stateGraypack(1),
      I4 => stateGraypack(0),
      I5 => oddNotEven_reg_0,
      O => \stateGraypack[0]_i_1_n_0\
    );
\stateGraypack[0]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF6FF6F96FFFFF"
    )
        port map (
      I0 => \col_lcl_reg[2]__1_n_0\,
      I1 => enRowbuf_reg_0(2),
      I2 => enRowbuf_reg_0(1),
      I3 => \col_lcl_reg[1]__1_n_0\,
      I4 => \col_lcl_reg[0]__1_n_0\,
      I5 => enRowbuf_reg_0(0),
      O => \stateGraypack[0]_i_10_n_0\
    );
\stateGraypack[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555555"
    )
        port map (
      I0 => \col_lcl_reg[10]__1_n_0\,
      I1 => \col_lcl_reg[8]__1_n_0\,
      I2 => \col_lcl_reg[6]__1_n_0\,
      I3 => \col_lcl[8]__1_i_2_n_0\,
      I4 => \col_lcl_reg[7]__1_n_0\,
      I5 => \col_lcl_reg[9]__1_n_0\,
      O => \stateGraypack[0]_i_2_n_0\
    );
\stateGraypack[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF6FFF6FFFF"
    )
        port map (
      I0 => \col_lcl[9]__1_i_2_n_0\,
      I1 => enRowbuf_reg_0(9),
      I2 => \stateGraypack[0]_i_4_n_0\,
      I3 => \stateGraypack[0]_i_5_n_0\,
      I4 => enRowbuf_reg_0(8),
      I5 => \stateGraypack[0]_i_6_n_0\,
      O => \stateGraypack[0]_i_3_n_0\
    );
\stateGraypack[0]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"956A"
    )
        port map (
      I0 => enRowbuf_reg_0(7),
      I1 => \col_lcl_reg[6]__1_n_0\,
      I2 => \col_lcl[8]__1_i_2_n_0\,
      I3 => \col_lcl_reg[7]__1_n_0\,
      O => \stateGraypack[0]_i_4_n_0\
    );
\stateGraypack[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEBFBFEFEFFBFBFE"
    )
        port map (
      I0 => \stateGraypack[0]_i_7_n_0\,
      I1 => enRowbuf_reg_0(5),
      I2 => \col_lcl_reg[6]__1_n_0\,
      I3 => \stateGraypack[0]_i_8_n_0\,
      I4 => \col_lcl_reg[5]__1_n_0\,
      I5 => enRowbuf_reg_0(6),
      O => \stateGraypack[0]_i_5_n_0\
    );
\stateGraypack[0]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9555"
    )
        port map (
      I0 => \col_lcl_reg[8]__1_n_0\,
      I1 => \col_lcl_reg[6]__1_n_0\,
      I2 => \col_lcl[8]__1_i_2_n_0\,
      I3 => \col_lcl_reg[7]__1_n_0\,
      O => \stateGraypack[0]_i_6_n_0\
    );
\stateGraypack[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF96F6FF6"
    )
        port map (
      I0 => \col_lcl_reg[4]__1_n_0\,
      I1 => enRowbuf_reg_0(4),
      I2 => enRowbuf_reg_0(3),
      I3 => \stateGraypack[0]_i_9_n_0\,
      I4 => \col_lcl_reg[3]__1_n_0\,
      I5 => \stateGraypack[0]_i_10_n_0\,
      O => \stateGraypack[0]_i_7_n_0\
    );
\stateGraypack[0]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \col_lcl_reg[4]__1_n_0\,
      I1 => \col_lcl_reg[2]__1_n_0\,
      I2 => \col_lcl_reg[1]__1_n_0\,
      I3 => \col_lcl_reg[0]__1_n_0\,
      I4 => \col_lcl_reg[3]__1_n_0\,
      O => \stateGraypack[0]_i_8_n_0\
    );
\stateGraypack[0]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \col_lcl_reg[2]__1_n_0\,
      I1 => \col_lcl_reg[1]__1_n_0\,
      I2 => \col_lcl_reg[0]__1_n_0\,
      O => \stateGraypack[0]_i_9_n_0\
    );
\stateGraypack[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FCAF"
    )
        port map (
      I0 => strbEgrstart_reg_n_0,
      I1 => \^rgbvideointomanyaxis_tvalid\,
      I2 => stateGraypack(0),
      I3 => stateGraypack(1),
      O => \stateGraypack[1]_i_1_n_0\
    );
\stateGraypack[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => stateGraypack(1),
      I1 => stateGraypack(0),
      O => \stateGraypack[1]_i_2_n_0\
    );
\stateGraypack_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateGraypack[1]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \stateGraypack[0]_i_1_n_0\,
      Q => stateGraypack(0)
    );
\stateGraypack_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateGraypack[1]_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \stateGraypack[1]_i_2_n_0\,
      Q => stateGraypack(1)
    );
\stateIgr[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FDDFFF0"
    )
        port map (
      I0 => camifToVideoinAXIS_tlast,
      I1 => \stateIgr[0]_i_2_n_0\,
      I2 => oddNotEven_reg_0,
      I3 => \^stateigr_reg[1]_0\(1),
      I4 => \^stateigr_reg[1]_0\(0),
      O => p_3_out(0)
    );
\stateIgr[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"98"
    )
        port map (
      I0 => klm(2),
      I1 => \^klm_reg[0]_0\(0),
      I2 => klm(1),
      O => \stateIgr[0]_i_2_n_0\
    );
\stateIgr[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"64"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      I2 => camifToVideoinAXIS_tlast,
      O => p_3_out(1)
    );
\stateIgr_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateIgr_reg[1]_1\(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => p_3_out(0),
      Q => \^stateigr_reg[1]_0\(0)
    );
\stateIgr_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateIgr_reg[1]_1\(0),
      CLR => enRowbufB_lcl_reg_0(0),
      D => p_3_out(1),
      Q => \^stateigr_reg[1]_0\(1)
    );
\state[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => \^stateigr_reg[1]_0\(0),
      O => videoinStateIgr_dbg(0)
    );
\state[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(0),
      I1 => \^stateigr_reg[1]_0\(1),
      O => videoinStateIgr_dbg(1)
    );
\state[4]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E6"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(0),
      I2 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      O => videoinStateRgbegr_dbg(0)
    );
\state[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^fsm_sequential_statergbegr_reg[2]_0\(1),
      I1 => \^fsm_sequential_statergbegr_reg[2]_0\(2),
      O => videoinStateRgbegr_dbg(1)
    );
strbEgrstart_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA40"
    )
        port map (
      I0 => \^stateigr_reg[1]_0\(1),
      I1 => strbEgrstart_i_2_n_0,
      I2 => \^stateigr_reg[1]_0\(0),
      I3 => strbEgrstart_reg_n_0,
      O => strbEgrstart_i_1_n_0
    );
strbEgrstart_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000000200000000"
    )
        port map (
      I0 => strbEgrstart_i_3_n_0,
      I1 => strbEgrstart_i_4_n_0,
      I2 => rawcol_lcl(2),
      I3 => rawcol_lcl(3),
      I4 => rawcolEgrstart(3),
      I5 => oddNotEven,
      O => strbEgrstart_i_2_n_0
    );
strbEgrstart_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => rawcol_lcl(10),
      I1 => rawcol_lcl(11),
      I2 => rawcol_lcl(6),
      I3 => rawcol_lcl(8),
      I4 => rawcol_lcl(7),
      I5 => rawcol_lcl(9),
      O => strbEgrstart_i_3_n_0
    );
strbEgrstart_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => rawcol_lcl(1),
      I1 => rawcol_lcl(0),
      I2 => rawcol_lcl(5),
      I3 => rawcol_lcl(4),
      O => strbEgrstart_i_4_n_0
    );
strbEgrstart_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => enRowbufB_lcl_reg_0(0),
      D => strbEgrstart_i_1_n_0,
      Q => strbEgrstart_reg_n_0
    );
\tuv[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => stateGraypack(1),
      I2 => \tuv_reg_n_0_[0]\,
      O => tuv(0)
    );
\tuv[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0220"
    )
        port map (
      I0 => stateGraypack(1),
      I1 => stateGraypack(0),
      I2 => \tuv_reg_n_0_[1]\,
      I3 => \tuv_reg_n_0_[0]\,
      O => tuv(1)
    );
\tuv[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04404040"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => stateGraypack(1),
      I2 => \tuv_reg_n_0_[2]\,
      I3 => \tuv_reg_n_0_[0]\,
      I4 => \tuv_reg_n_0_[1]\,
      O => \tuv[2]_i_1_n_0\
    );
\tuv[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0440404040404040"
    )
        port map (
      I0 => stateGraypack(0),
      I1 => stateGraypack(1),
      I2 => \tuv_reg_n_0_[3]\,
      I3 => \tuv_reg_n_0_[2]\,
      I4 => \tuv_reg_n_0_[1]\,
      I5 => \tuv_reg_n_0_[0]\,
      O => \tuv[3]_i_1_n_0\
    );
\tuv_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => tuv(0),
      Q => \tuv_reg_n_0_[0]\
    );
\tuv_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => tuv(1),
      Q => \tuv_reg_n_0_[1]\
    );
\tuv_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \tuv[2]_i_1_n_0\,
      Q => \tuv_reg_n_0_[2]\
    );
\tuv_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \col_lcl[10]__1_i_1_n_0\,
      CLR => enRowbufB_lcl_reg_0(0),
      D => \tuv[3]_i_1_n_0\,
      Q => \tuv_reg_n_0_[3]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Vidtrack is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    ackInvVidtrackSelect : out STD_LOGIC;
    ackInvVidtrackSet : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    seqbufVidtrackToHostifAXIS_tvalid : out STD_LOGIC;
    vidtrackGetInfoTixVState : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \TCapt_reg[31]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ackSeqbufVidtrackToHostif : out STD_LOGIC;
    vidtrackGetInfoPtr0Seqbuf : out STD_LOGIC_VECTOR ( 9 downto 0 );
    \tixVCapture_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    aclk_sig : in STD_LOGIC;
    first_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    hdrNotFix : in STD_LOGIC;
    reqInvVidtrackSet : in STD_LOGIC;
    reqInvVidtrackSelect : in STD_LOGIC;
    restart_reg_0 : in STD_LOGIC;
    dneSeqbufVidtrackToHostif : in STD_LOGIC;
    seqbufVidtrackToHostifAXIS_tready : in STD_LOGIC;
    reqSeqbufVidtrackToHostif : in STD_LOGIC;
    \state_reg[7]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    videoinStateRgbegr_dbg : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \state_reg[5]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \state_reg[5]_1\ : in STD_LOGIC;
    \state_reg[0]_0\ : in STD_LOGIC;
    videoinStateIgr_dbg : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \state_reg[4]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 23 downto 0 );
    \tixVCapture_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \TCaptMax_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Vidtrack : entity is "Vidtrack";
end design_1_Vsp_core_0_0_Vidtrack;

architecture STRUCTURE of design_1_Vsp_core_0_0_Vidtrack is
  signal \FSM_onehot_stateSeq[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[3]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[3]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq[5]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_stateSeq_reg_n_0_[4]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal TCapt : STD_LOGIC;
  signal TCaptMax : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[0]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[10]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[11]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[12]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[13]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[14]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[15]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[16]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[17]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[18]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[19]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[1]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[20]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[21]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[22]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[23]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[24]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[25]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[26]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[27]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[28]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[29]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[2]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[30]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[31]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[3]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[4]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[5]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[6]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[7]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[8]\ : STD_LOGIC;
  signal \TCaptMax_reg_n_0_[9]\ : STD_LOGIC;
  signal \TCapt__0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \TCapt_reg[16]_i_2_n_0\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2_n_1\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2_n_2\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2_n_3\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2_n_4\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2_n_5\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2_n_6\ : STD_LOGIC;
  signal \TCapt_reg[16]_i_2_n_7\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2_n_0\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2_n_1\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2_n_2\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2_n_3\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2_n_4\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2_n_5\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2_n_6\ : STD_LOGIC;
  signal \TCapt_reg[24]_i_2_n_7\ : STD_LOGIC;
  signal \^tcapt_reg[31]_0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \TCapt_reg[31]_i_2_n_2\ : STD_LOGIC;
  signal \TCapt_reg[31]_i_2_n_3\ : STD_LOGIC;
  signal \TCapt_reg[31]_i_2_n_4\ : STD_LOGIC;
  signal \TCapt_reg[31]_i_2_n_5\ : STD_LOGIC;
  signal \TCapt_reg[31]_i_2_n_6\ : STD_LOGIC;
  signal \TCapt_reg[31]_i_2_n_7\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2_n_1\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2_n_2\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2_n_3\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2_n_4\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2_n_5\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2_n_6\ : STD_LOGIC;
  signal \TCapt_reg[8]_i_2_n_7\ : STD_LOGIC;
  signal \aSeqbufB[0]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[1]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[2]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[3]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[4]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[5]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[5]_i_2_n_0\ : STD_LOGIC;
  signal \aSeqbufB[6]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[7]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_2_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_3_n_0\ : STD_LOGIC;
  signal \aSeqbufB[8]_i_4_n_0\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[0]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[1]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[2]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[3]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[4]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[5]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[6]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[7]\ : STD_LOGIC;
  signal \aSeqbufB_reg_n_0_[8]\ : STD_LOGIC;
  signal \aSeqbuf[0]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[1]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[2]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[3]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[3]_i_2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[4]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[5]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[5]_i_2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[6]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[7]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_3_n_0\ : STD_LOGIC;
  signal \aSeqbuf[8]_i_4_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_1_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_2_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_3_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_4_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_5_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_6_n_0\ : STD_LOGIC;
  signal \aSeqbuf[9]_i_7_n_0\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[0]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[1]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[2]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[3]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[4]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[5]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[6]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[7]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[8]\ : STD_LOGIC;
  signal \aSeqbuf_reg_n_0_[9]\ : STD_LOGIC;
  signal ackInvSelect_sig_i_1_n_0 : STD_LOGIC;
  signal ackInvSelect_sig_i_2_n_0 : STD_LOGIC;
  signal \ackInvSet_sig_i_1__0_n_0\ : STD_LOGIC;
  signal \^ackinvvidtrackselect\ : STD_LOGIC;
  signal \^ackinvvidtrackset\ : STD_LOGIC;
  signal ackSeqbufBToSeqClear : STD_LOGIC;
  signal \burstCnt[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[10]_i_2_n_0\ : STD_LOGIC;
  signal \burstCnt[10]_i_3_n_0\ : STD_LOGIC;
  signal \burstCnt[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[11]_i_2_n_0\ : STD_LOGIC;
  signal \burstCnt[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[12]_i_2_n_0\ : STD_LOGIC;
  signal \burstCnt[13]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[13]_i_2_n_0\ : STD_LOGIC;
  signal \burstCnt[14]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[14]_i_2_n_0\ : STD_LOGIC;
  signal \burstCnt[14]_i_3_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_10_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_11_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_12_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_13_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_14_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_15_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_16_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_17_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_18_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_19_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_1_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_20_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_21_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_22_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_23_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_24_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_25_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_26_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_27_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_28_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_2__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_3_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_4_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_5_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_6__0_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_7_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_8_n_0\ : STD_LOGIC;
  signal \burstCnt[15]_i_9_n_0\ : STD_LOGIC;
  signal \burstCnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \burstCnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \burstCnt[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \burstCnt[4]_i_2_n_0\ : STD_LOGIC;
  signal \burstCnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \burstCnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \burstCnt[6]_i_1_n_0\ : STD_LOGIC;
  signal \burstCnt[6]_i_2_n_0\ : STD_LOGIC;
  signal \burstCnt[7]_i_1_n_0\ : STD_LOGIC;
  signal \burstCnt[7]_i_2_n_0\ : STD_LOGIC;
  signal \burstCnt[7]_i_3_n_0\ : STD_LOGIC;
  signal \burstCnt[8]_i_1_n_0\ : STD_LOGIC;
  signal \burstCnt[8]_i_2_n_0\ : STD_LOGIC;
  signal \burstCnt[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \burstCnt[9]_i_2_n_0\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[14]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \burstCnt_reg_n_0_[9]\ : STD_LOGIC;
  signal \burstState[0]_i_1_n_0\ : STD_LOGIC;
  signal \burstState[1]_i_1_n_0\ : STD_LOGIC;
  signal \burstState[4]_i_1_n_0\ : STD_LOGIC;
  signal \burstState[5]_i_1_n_0\ : STD_LOGIC;
  signal \burstState[6]_i_1_n_0\ : STD_LOGIC;
  signal \burstState_reg_n_0_[0]\ : STD_LOGIC;
  signal \burstState_reg_n_0_[1]\ : STD_LOGIC;
  signal \burstState_reg_n_0_[4]\ : STD_LOGIC;
  signal \burstState_reg_n_0_[5]\ : STD_LOGIC;
  signal \burstState_reg_n_0_[6]\ : STD_LOGIC;
  signal dwrSeqbuf : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \dwrSeqbuf[0]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[0]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[10]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[10]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[11]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[11]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[12]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[12]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[13]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[13]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[14]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[14]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[15]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[15]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[15]_i_3_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[16]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[17]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[18]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[19]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[1]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[1]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[1]_i_3_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[20]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[21]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[22]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[23]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[23]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[24]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[25]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[26]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[27]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[28]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[29]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[2]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[2]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[2]_i_3_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[30]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_3__0_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[31]_i_4_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[3]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[3]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[3]_i_3_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[4]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[4]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[4]_i_3_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[5]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[5]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[5]_i_3_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[6]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[6]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[7]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[7]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[8]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[8]_i_2_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[9]_i_1_n_0\ : STD_LOGIC;
  signal \dwrSeqbuf[9]_i_2_n_0\ : STD_LOGIC;
  signal enSeqbuf : STD_LOGIC;
  signal enSeqbuf_reg_n_0 : STD_LOGIC;
  signal first : STD_LOGIC;
  signal \first__0\ : STD_LOGIC;
  signal i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \i[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \i_reg_n_0_[0]\ : STD_LOGIC;
  signal \i_reg_n_0_[1]\ : STD_LOGIC;
  signal in12 : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal ptr0SeqbufTrackNotFixed_i_1_n_0 : STD_LOGIC;
  signal ptr0SeqbufTrackNotFixed_reg_n_0 : STD_LOGIC;
  signal quad : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \quad[15]_i_1_n_0\ : STD_LOGIC;
  signal \quad[23]_i_1_n_0\ : STD_LOGIC;
  signal \quad[7]_i_1_n_0\ : STD_LOGIC;
  signal \quad_reg_n_0_[0]\ : STD_LOGIC;
  signal \quad_reg_n_0_[10]\ : STD_LOGIC;
  signal \quad_reg_n_0_[11]\ : STD_LOGIC;
  signal \quad_reg_n_0_[12]\ : STD_LOGIC;
  signal \quad_reg_n_0_[13]\ : STD_LOGIC;
  signal \quad_reg_n_0_[14]\ : STD_LOGIC;
  signal \quad_reg_n_0_[15]\ : STD_LOGIC;
  signal \quad_reg_n_0_[16]\ : STD_LOGIC;
  signal \quad_reg_n_0_[17]\ : STD_LOGIC;
  signal \quad_reg_n_0_[18]\ : STD_LOGIC;
  signal \quad_reg_n_0_[19]\ : STD_LOGIC;
  signal \quad_reg_n_0_[1]\ : STD_LOGIC;
  signal \quad_reg_n_0_[20]\ : STD_LOGIC;
  signal \quad_reg_n_0_[21]\ : STD_LOGIC;
  signal \quad_reg_n_0_[22]\ : STD_LOGIC;
  signal \quad_reg_n_0_[23]\ : STD_LOGIC;
  signal \quad_reg_n_0_[24]\ : STD_LOGIC;
  signal \quad_reg_n_0_[25]\ : STD_LOGIC;
  signal \quad_reg_n_0_[26]\ : STD_LOGIC;
  signal \quad_reg_n_0_[27]\ : STD_LOGIC;
  signal \quad_reg_n_0_[28]\ : STD_LOGIC;
  signal \quad_reg_n_0_[29]\ : STD_LOGIC;
  signal \quad_reg_n_0_[2]\ : STD_LOGIC;
  signal \quad_reg_n_0_[30]\ : STD_LOGIC;
  signal \quad_reg_n_0_[31]\ : STD_LOGIC;
  signal \quad_reg_n_0_[3]\ : STD_LOGIC;
  signal \quad_reg_n_0_[4]\ : STD_LOGIC;
  signal \quad_reg_n_0_[5]\ : STD_LOGIC;
  signal \quad_reg_n_0_[6]\ : STD_LOGIC;
  signal \quad_reg_n_0_[7]\ : STD_LOGIC;
  signal \quad_reg_n_0_[8]\ : STD_LOGIC;
  signal \quad_reg_n_0_[9]\ : STD_LOGIC;
  signal rdySeq : STD_LOGIC;
  signal restart_i_1_n_0 : STD_LOGIC;
  signal restart_i_2_n_0 : STD_LOGIC;
  signal restart_reg_n_0 : STD_LOGIC;
  signal rng_reg_n_0 : STD_LOGIC;
  signal staFallingNotRising : STD_LOGIC;
  signal staTixVTrigger : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal state : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal stateOp : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \stateOp[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \stateOp[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_10_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_11_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_12_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_13_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_15_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_16_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_17_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_18_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_19_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_1_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_20_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_21_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_22_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_23_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_24_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_25_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_26_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_27_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_28_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_29_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_2_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_30_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_31_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_32_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_33_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_34_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_35_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_36_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_37_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_38_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_39_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_40_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_41_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_42_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_43_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_44_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_45_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_46_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_47_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_48_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_49_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_4__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_50_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_51_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_52_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_53_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_54_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_55_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_56_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_57_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_5_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_6_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_7__0_n_0\ : STD_LOGIC;
  signal \stateOp[2]_i_8_n_0\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_14_n_0\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_14_n_1\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_14_n_2\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_14_n_3\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_14_n_4\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_14_n_5\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_14_n_6\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_14_n_7\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9_n_0\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9_n_1\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9_n_2\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9_n_3\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9_n_4\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9_n_5\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9_n_6\ : STD_LOGIC;
  signal \stateOp_reg[2]_i_9_n_7\ : STD_LOGIC;
  signal \stateSeqbufB[1]_i_2_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[2]_i_1_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[2]_i_3_n_0\ : STD_LOGIC;
  signal \stateSeqbufB[2]_i_7_n_0\ : STD_LOGIC;
  signal stateSeqbufB_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \state[0]_i_1_n_0\ : STD_LOGIC;
  signal \state[4]_i_1_n_0\ : STD_LOGIC;
  signal \state[4]_i_2_n_0\ : STD_LOGIC;
  signal \state[5]_i_1_n_0\ : STD_LOGIC;
  signal \state[6]_i_1_n_0\ : STD_LOGIC;
  signal \state[7]_i_1_n_0\ : STD_LOGIC;
  signal \state[7]_i_4_n_0\ : STD_LOGIC;
  signal stoTixVTrigger : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal stop_lcl_i_1_n_0 : STD_LOGIC;
  signal stop_lcl_i_2_n_0 : STD_LOGIC;
  signal stop_lcl_reg_n_0 : STD_LOGIC;
  signal strbStop_i_1_n_0 : STD_LOGIC;
  signal strbStop_i_2_n_0 : STD_LOGIC;
  signal strbStop_i_3_n_0 : STD_LOGIC;
  signal strbStop_i_4_n_0 : STD_LOGIC;
  signal strbStop_i_5_n_0 : STD_LOGIC;
  signal strbStop_reg_n_0 : STD_LOGIC;
  signal \^tixvcapture_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \tixVCapture_reg_n_0_[2]\ : STD_LOGIC;
  signal \tixVCapture_reg_n_0_[3]\ : STD_LOGIC;
  signal \tixVCapture_reg_n_0_[4]\ : STD_LOGIC;
  signal \tixVCapture_reg_n_0_[5]\ : STD_LOGIC;
  signal \tixVCapture_reg_n_0_[6]\ : STD_LOGIC;
  signal \tixVCapture_reg_n_0_[7]\ : STD_LOGIC;
  signal \^vidtrackgetinfotixvstate\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_TCapt_reg[31]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_TCapt_reg[31]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \NLW_stateOp_reg[2]_i_14_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_stateOp_reg[2]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[0]_i_2\ : label is "soft_lutpair3117";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[2]_i_1\ : label is "soft_lutpair3076";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[3]_i_1\ : label is "soft_lutpair3076";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_2\ : label is "soft_lutpair3119";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_5\ : label is "soft_lutpair3116";
  attribute SOFT_HLUTNM of \FSM_onehot_stateSeq[5]_i_6\ : label is "soft_lutpair3116";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[0]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[1]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[2]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[3]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[4]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_stateSeq_reg[5]\ : label is "iSTATE:000010,iSTATE0:010000,iSTATE1:000100,iSTATE2:001000,iSTATE3:100000,iSTATE4:000001";
  attribute SOFT_HLUTNM of \TCapt[10]_i_1\ : label is "soft_lutpair3139";
  attribute SOFT_HLUTNM of \TCapt[11]_i_1\ : label is "soft_lutpair3138";
  attribute SOFT_HLUTNM of \TCapt[12]_i_1\ : label is "soft_lutpair3138";
  attribute SOFT_HLUTNM of \TCapt[13]_i_1\ : label is "soft_lutpair3137";
  attribute SOFT_HLUTNM of \TCapt[14]_i_1\ : label is "soft_lutpair3137";
  attribute SOFT_HLUTNM of \TCapt[15]_i_1\ : label is "soft_lutpair3136";
  attribute SOFT_HLUTNM of \TCapt[16]_i_1\ : label is "soft_lutpair3136";
  attribute SOFT_HLUTNM of \TCapt[17]_i_1\ : label is "soft_lutpair3135";
  attribute SOFT_HLUTNM of \TCapt[18]_i_1\ : label is "soft_lutpair3135";
  attribute SOFT_HLUTNM of \TCapt[19]_i_1\ : label is "soft_lutpair3134";
  attribute SOFT_HLUTNM of \TCapt[1]_i_1\ : label is "soft_lutpair3143";
  attribute SOFT_HLUTNM of \TCapt[20]_i_1\ : label is "soft_lutpair3134";
  attribute SOFT_HLUTNM of \TCapt[21]_i_1\ : label is "soft_lutpair3133";
  attribute SOFT_HLUTNM of \TCapt[22]_i_1\ : label is "soft_lutpair3133";
  attribute SOFT_HLUTNM of \TCapt[23]_i_1\ : label is "soft_lutpair3132";
  attribute SOFT_HLUTNM of \TCapt[24]_i_1\ : label is "soft_lutpair3132";
  attribute SOFT_HLUTNM of \TCapt[25]_i_1\ : label is "soft_lutpair3131";
  attribute SOFT_HLUTNM of \TCapt[26]_i_1\ : label is "soft_lutpair3131";
  attribute SOFT_HLUTNM of \TCapt[27]_i_1\ : label is "soft_lutpair3130";
  attribute SOFT_HLUTNM of \TCapt[28]_i_1\ : label is "soft_lutpair3130";
  attribute SOFT_HLUTNM of \TCapt[29]_i_1\ : label is "soft_lutpair3129";
  attribute SOFT_HLUTNM of \TCapt[2]_i_1\ : label is "soft_lutpair3143";
  attribute SOFT_HLUTNM of \TCapt[30]_i_1\ : label is "soft_lutpair3129";
  attribute SOFT_HLUTNM of \TCapt[31]_i_1\ : label is "soft_lutpair3128";
  attribute SOFT_HLUTNM of \TCapt[3]_i_1\ : label is "soft_lutpair3142";
  attribute SOFT_HLUTNM of \TCapt[4]_i_1\ : label is "soft_lutpair3142";
  attribute SOFT_HLUTNM of \TCapt[5]_i_1\ : label is "soft_lutpair3141";
  attribute SOFT_HLUTNM of \TCapt[6]_i_1\ : label is "soft_lutpair3141";
  attribute SOFT_HLUTNM of \TCapt[7]_i_1\ : label is "soft_lutpair3140";
  attribute SOFT_HLUTNM of \TCapt[8]_i_1\ : label is "soft_lutpair3140";
  attribute SOFT_HLUTNM of \TCapt[9]_i_1\ : label is "soft_lutpair3139";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \TCapt_reg[16]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \TCapt_reg[24]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \TCapt_reg[31]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \TCapt_reg[8]_i_2\ : label is 35;
  attribute SOFT_HLUTNM of \aSeqbufB[1]_i_1\ : label is "soft_lutpair3110";
  attribute SOFT_HLUTNM of \aSeqbufB[2]_i_1\ : label is "soft_lutpair3110";
  attribute SOFT_HLUTNM of \aSeqbufB[5]_i_1\ : label is "soft_lutpair3113";
  attribute SOFT_HLUTNM of \aSeqbufB[6]_i_1\ : label is "soft_lutpair3109";
  attribute SOFT_HLUTNM of \aSeqbufB[7]_i_1\ : label is "soft_lutpair3109";
  attribute SOFT_HLUTNM of \aSeqbufB[8]_i_2\ : label is "soft_lutpair3074";
  attribute SOFT_HLUTNM of \aSeqbufB[8]_i_3\ : label is "soft_lutpair3119";
  attribute SOFT_HLUTNM of \aSeqbuf[1]_i_1\ : label is "soft_lutpair3123";
  attribute SOFT_HLUTNM of \aSeqbuf[2]_i_1\ : label is "soft_lutpair3079";
  attribute SOFT_HLUTNM of \aSeqbuf[3]_i_1\ : label is "soft_lutpair3079";
  attribute SOFT_HLUTNM of \aSeqbuf[3]_i_2\ : label is "soft_lutpair3080";
  attribute SOFT_HLUTNM of \aSeqbuf[6]_i_1\ : label is "soft_lutpair3115";
  attribute SOFT_HLUTNM of \aSeqbuf[7]_i_1\ : label is "soft_lutpair3115";
  attribute SOFT_HLUTNM of \aSeqbuf[8]_i_2\ : label is "soft_lutpair3080";
  attribute SOFT_HLUTNM of \aSeqbuf[8]_i_3\ : label is "soft_lutpair3108";
  attribute SOFT_HLUTNM of \aSeqbuf[9]_i_4\ : label is "soft_lutpair3108";
  attribute SOFT_HLUTNM of ackInvSelect_sig_i_1 : label is "soft_lutpair3077";
  attribute SOFT_HLUTNM of ackInvSelect_sig_i_2 : label is "soft_lutpair3114";
  attribute SOFT_HLUTNM of \ackInvSet_sig_i_1__0\ : label is "soft_lutpair3111";
  attribute SOFT_HLUTNM of \burstCnt[0]_i_1__0\ : label is "soft_lutpair3075";
  attribute SOFT_HLUTNM of \burstCnt[10]_i_1__0\ : label is "soft_lutpair3126";
  attribute SOFT_HLUTNM of \burstCnt[11]_i_1__0\ : label is "soft_lutpair3125";
  attribute SOFT_HLUTNM of \burstCnt[12]_i_1__0\ : label is "soft_lutpair3125";
  attribute SOFT_HLUTNM of \burstCnt[13]_i_1__0\ : label is "soft_lutpair3124";
  attribute SOFT_HLUTNM of \burstCnt[13]_i_2\ : label is "soft_lutpair3088";
  attribute SOFT_HLUTNM of \burstCnt[14]_i_1__0\ : label is "soft_lutpair3124";
  attribute SOFT_HLUTNM of \burstCnt[15]_i_16\ : label is "soft_lutpair3086";
  attribute SOFT_HLUTNM of \burstCnt[15]_i_19\ : label is "soft_lutpair3097";
  attribute SOFT_HLUTNM of \burstCnt[15]_i_27\ : label is "soft_lutpair3085";
  attribute SOFT_HLUTNM of \burstCnt[15]_i_3\ : label is "soft_lutpair3083";
  attribute SOFT_HLUTNM of \burstCnt[1]_i_1\ : label is "soft_lutpair3075";
  attribute SOFT_HLUTNM of \burstCnt[4]_i_1\ : label is "soft_lutpair3112";
  attribute SOFT_HLUTNM of \burstCnt[4]_i_2\ : label is "soft_lutpair3088";
  attribute SOFT_HLUTNM of \burstCnt[5]_i_2\ : label is "soft_lutpair3091";
  attribute SOFT_HLUTNM of \burstCnt[6]_i_1\ : label is "soft_lutpair3127";
  attribute SOFT_HLUTNM of \burstCnt[7]_i_1\ : label is "soft_lutpair3128";
  attribute SOFT_HLUTNM of \burstCnt[8]_i_1\ : label is "soft_lutpair3127";
  attribute SOFT_HLUTNM of \burstCnt[8]_i_2\ : label is "soft_lutpair3089";
  attribute SOFT_HLUTNM of \burstCnt[9]_i_1__0\ : label is "soft_lutpair3126";
  attribute SOFT_HLUTNM of \burstCnt[9]_i_2\ : label is "soft_lutpair3089";
  attribute SOFT_HLUTNM of \burstState[0]_i_1\ : label is "soft_lutpair3120";
  attribute SOFT_HLUTNM of \burstState[1]_i_1\ : label is "soft_lutpair3120";
  attribute SOFT_HLUTNM of \burstState[4]_i_1\ : label is "soft_lutpair3121";
  attribute SOFT_HLUTNM of \burstState[5]_i_1\ : label is "soft_lutpair3121";
  attribute SOFT_HLUTNM of \dwrSeqbuf[0]_i_2\ : label is "soft_lutpair3098";
  attribute SOFT_HLUTNM of \dwrSeqbuf[10]_i_2\ : label is "soft_lutpair3104";
  attribute SOFT_HLUTNM of \dwrSeqbuf[11]_i_2\ : label is "soft_lutpair3103";
  attribute SOFT_HLUTNM of \dwrSeqbuf[12]_i_2\ : label is "soft_lutpair3107";
  attribute SOFT_HLUTNM of \dwrSeqbuf[13]_i_2\ : label is "soft_lutpair3106";
  attribute SOFT_HLUTNM of \dwrSeqbuf[14]_i_2\ : label is "soft_lutpair3102";
  attribute SOFT_HLUTNM of \dwrSeqbuf[15]_i_3\ : label is "soft_lutpair3097";
  attribute SOFT_HLUTNM of \dwrSeqbuf[1]_i_2\ : label is "soft_lutpair3090";
  attribute SOFT_HLUTNM of \dwrSeqbuf[1]_i_3\ : label is "soft_lutpair3095";
  attribute SOFT_HLUTNM of \dwrSeqbuf[23]_i_2\ : label is "soft_lutpair3084";
  attribute SOFT_HLUTNM of \dwrSeqbuf[2]_i_2\ : label is "soft_lutpair3090";
  attribute SOFT_HLUTNM of \dwrSeqbuf[2]_i_3\ : label is "soft_lutpair3092";
  attribute SOFT_HLUTNM of \dwrSeqbuf[3]_i_2\ : label is "soft_lutpair3091";
  attribute SOFT_HLUTNM of \dwrSeqbuf[3]_i_3\ : label is "soft_lutpair3096";
  attribute SOFT_HLUTNM of \dwrSeqbuf[4]_i_3\ : label is "soft_lutpair3100";
  attribute SOFT_HLUTNM of \dwrSeqbuf[5]_i_3\ : label is "soft_lutpair3094";
  attribute SOFT_HLUTNM of \dwrSeqbuf[6]_i_2\ : label is "soft_lutpair3093";
  attribute SOFT_HLUTNM of \dwrSeqbuf[7]_i_2\ : label is "soft_lutpair3099";
  attribute SOFT_HLUTNM of \dwrSeqbuf[8]_i_2\ : label is "soft_lutpair3105";
  attribute SOFT_HLUTNM of \dwrSeqbuf[9]_i_2\ : label is "soft_lutpair3101";
  attribute SOFT_HLUTNM of enSeqbuf_i_1 : label is "soft_lutpair3081";
  attribute SOFT_HLUTNM of \i[0]_i_1__2\ : label is "soft_lutpair3087";
  attribute SOFT_HLUTNM of \i[1]_i_2__0\ : label is "soft_lutpair3082";
  attribute SOFT_HLUTNM of \quad[0]_i_1\ : label is "soft_lutpair3098";
  attribute SOFT_HLUTNM of \quad[10]_i_1\ : label is "soft_lutpair3104";
  attribute SOFT_HLUTNM of \quad[11]_i_1\ : label is "soft_lutpair3103";
  attribute SOFT_HLUTNM of \quad[12]_i_1\ : label is "soft_lutpair3107";
  attribute SOFT_HLUTNM of \quad[13]_i_1\ : label is "soft_lutpair3106";
  attribute SOFT_HLUTNM of \quad[14]_i_1\ : label is "soft_lutpair3102";
  attribute SOFT_HLUTNM of \quad[1]_i_1\ : label is "soft_lutpair3095";
  attribute SOFT_HLUTNM of \quad[24]_i_1\ : label is "soft_lutpair3081";
  attribute SOFT_HLUTNM of \quad[25]_i_1\ : label is "soft_lutpair3082";
  attribute SOFT_HLUTNM of \quad[26]_i_1\ : label is "soft_lutpair3083";
  attribute SOFT_HLUTNM of \quad[27]_i_1\ : label is "soft_lutpair3084";
  attribute SOFT_HLUTNM of \quad[28]_i_1\ : label is "soft_lutpair3085";
  attribute SOFT_HLUTNM of \quad[29]_i_1\ : label is "soft_lutpair3086";
  attribute SOFT_HLUTNM of \quad[2]_i_1\ : label is "soft_lutpair3092";
  attribute SOFT_HLUTNM of \quad[30]_i_1\ : label is "soft_lutpair3087";
  attribute SOFT_HLUTNM of \quad[3]_i_1\ : label is "soft_lutpair3096";
  attribute SOFT_HLUTNM of \quad[4]_i_1\ : label is "soft_lutpair3100";
  attribute SOFT_HLUTNM of \quad[5]_i_1\ : label is "soft_lutpair3094";
  attribute SOFT_HLUTNM of \quad[6]_i_1\ : label is "soft_lutpair3093";
  attribute SOFT_HLUTNM of \quad[7]_i_2\ : label is "soft_lutpair3099";
  attribute SOFT_HLUTNM of \quad[8]_i_1\ : label is "soft_lutpair3105";
  attribute SOFT_HLUTNM of \quad[9]_i_1\ : label is "soft_lutpair3101";
  attribute SOFT_HLUTNM of restart_i_2 : label is "soft_lutpair3111";
  attribute SOFT_HLUTNM of \retbuf[0][0]_i_4\ : label is "soft_lutpair3122";
  attribute SOFT_HLUTNM of \retbuf[5][0]_i_5\ : label is "soft_lutpair3144";
  attribute SOFT_HLUTNM of \retbuf[5][1]_i_5\ : label is "soft_lutpair3144";
  attribute SOFT_HLUTNM of \retbuf[6][1]_i_5\ : label is "soft_lutpair3123";
  attribute SOFT_HLUTNM of \retbuf[6][2]_i_5\ : label is "soft_lutpair3147";
  attribute SOFT_HLUTNM of \retbuf[6][3]_i_5\ : label is "soft_lutpair3147";
  attribute SOFT_HLUTNM of \retbuf[6][4]_i_5\ : label is "soft_lutpair3146";
  attribute SOFT_HLUTNM of \retbuf[6][5]_i_3\ : label is "soft_lutpair3146";
  attribute SOFT_HLUTNM of \retbuf[6][6]_i_5\ : label is "soft_lutpair3145";
  attribute SOFT_HLUTNM of \retbuf[6][7]_i_9\ : label is "soft_lutpair3145";
  attribute SOFT_HLUTNM of \stateOp[0]_i_1__0\ : label is "soft_lutpair3078";
  attribute SOFT_HLUTNM of \stateOp[2]_i_3\ : label is "soft_lutpair3122";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of \stateOp_reg[2]_i_14\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \stateOp_reg[2]_i_9\ : label is 11;
  attribute SOFT_HLUTNM of \stateSeqbufB[0]_i_1\ : label is "soft_lutpair3117";
  attribute SOFT_HLUTNM of \stateSeqbufB[1]_i_1\ : label is "soft_lutpair3118";
  attribute SOFT_HLUTNM of \stateSeqbufB[2]_i_7\ : label is "soft_lutpair3074";
  attribute SOFT_HLUTNM of stop_lcl_i_2 : label is "soft_lutpair3112";
  attribute SOFT_HLUTNM of strbStop_i_2 : label is "soft_lutpair3077";
  attribute SOFT_HLUTNM of strbStop_i_4 : label is "soft_lutpair3078";
  attribute SOFT_HLUTNM of strbStop_i_5 : label is "soft_lutpair3114";
  attribute SOFT_HLUTNM of \txAXIS_tdata[15]_i_18\ : label is "soft_lutpair3113";
  attribute SOFT_HLUTNM of \wordcntLast[28]_i_13\ : label is "soft_lutpair3118";
begin
  Q(0) <= \^q\(0);
  \TCapt_reg[31]_0\(31 downto 0) <= \^tcapt_reg[31]_0\(31 downto 0);
  ackInvVidtrackSelect <= \^ackinvvidtrackselect\;
  ackInvVidtrackSet <= \^ackinvvidtrackset\;
  \tixVCapture_reg[1]_0\(1 downto 0) <= \^tixvcapture_reg[1]_0\(1 downto 0);
  vidtrackGetInfoTixVState(1 downto 0) <= \^vidtrackgetinfotixvstate\(1 downto 0);
\FSM_onehot_stateSeq[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF00010001"
    )
        port map (
      I0 => TCapt,
      I1 => \^q\(0),
      I2 => first,
      I3 => rdySeq,
      I4 => \FSM_onehot_stateSeq[0]_i_2_n_0\,
      I5 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \FSM_onehot_stateSeq[0]_i_1_n_0\
    );
\FSM_onehot_stateSeq[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => stateSeqbufB_reg(1),
      I1 => stateSeqbufB_reg(0),
      I2 => stateSeqbufB_reg(2),
      O => \FSM_onehot_stateSeq[0]_i_2_n_0\
    );
\FSM_onehot_stateSeq[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF8FF00"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \FSM_onehot_stateSeq[3]_i_2_n_0\,
      I3 => rdySeq,
      I4 => TCapt,
      O => \FSM_onehot_stateSeq[2]_i_1_n_0\
    );
\FSM_onehot_stateSeq[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \FSM_onehot_stateSeq[3]_i_2_n_0\,
      I3 => TCapt,
      O => \FSM_onehot_stateSeq[3]_i_1_n_0\
    );
\FSM_onehot_stateSeq[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FEFF"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \FSM_onehot_stateSeq[3]_i_3_n_0\,
      I3 => \aSeqbuf[9]_i_4_n_0\,
      I4 => strbStop_reg_n_0,
      I5 => stop_lcl_reg_n_0,
      O => \FSM_onehot_stateSeq[3]_i_2_n_0\
    );
\FSM_onehot_stateSeq[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[3]_i_4_n_0\,
      I1 => stoTixVTrigger(2),
      I2 => stoTixVTrigger(1),
      I3 => stoTixVTrigger(0),
      O => \FSM_onehot_stateSeq[3]_i_3_n_0\
    );
\FSM_onehot_stateSeq[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => stoTixVTrigger(5),
      I1 => stoTixVTrigger(3),
      I2 => stoTixVTrigger(6),
      I3 => stoTixVTrigger(7),
      I4 => stoTixVTrigger(4),
      O => \FSM_onehot_stateSeq[3]_i_4_n_0\
    );
\FSM_onehot_stateSeq[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55550300"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_3_n_0\,
      I1 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I2 => ackSeqbufBToSeqClear,
      I3 => \FSM_onehot_stateSeq[5]_i_4_n_0\,
      I4 => \FSM_onehot_stateSeq[5]_i_5_n_0\,
      I5 => \FSM_onehot_stateSeq[5]_i_6_n_0\,
      O => \FSM_onehot_stateSeq[5]_i_1_n_0\
    );
\FSM_onehot_stateSeq[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => stateSeqbufB_reg(2),
      I2 => stateSeqbufB_reg(0),
      I3 => stateSeqbufB_reg(1),
      O => \FSM_onehot_stateSeq[5]_i_2_n_0\
    );
\FSM_onehot_stateSeq[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA2AAAA"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_7_n_0\,
      I1 => stateOp(0),
      I2 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I3 => ackSeqbufBToSeqClear,
      I4 => stateOp(1),
      I5 => stateOp(2),
      O => \FSM_onehot_stateSeq[5]_i_3_n_0\
    );
\FSM_onehot_stateSeq[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08080808FF080808"
    )
        port map (
      I0 => stateOp(1),
      I1 => stateOp(2),
      I2 => stateOp(0),
      I3 => stateSeqbufB_reg(2),
      I4 => stateSeqbufB_reg(0),
      I5 => stateSeqbufB_reg(1),
      O => \FSM_onehot_stateSeq[5]_i_4_n_0\
    );
\FSM_onehot_stateSeq[5]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      I1 => TCapt,
      O => \FSM_onehot_stateSeq[5]_i_5_n_0\
    );
\FSM_onehot_stateSeq[5]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => ackSeqbufBToSeqClear,
      I1 => rdySeq,
      I2 => \^q\(0),
      I3 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \FSM_onehot_stateSeq[5]_i_6_n_0\
    );
\FSM_onehot_stateSeq[5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF31113FFFF11FF"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_5_n_0\,
      I1 => \aSeqbuf[9]_i_4_n_0\,
      I2 => rdySeq,
      I3 => ackSeqbufBToSeqClear,
      I4 => \FSM_onehot_stateSeq[0]_i_2_n_0\,
      I5 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \FSM_onehot_stateSeq[5]_i_7_n_0\
    );
\FSM_onehot_stateSeq_reg[0]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '1'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1_n_0\,
      D => \FSM_onehot_stateSeq[0]_i_1_n_0\,
      PRE => first_reg_0(0),
      Q => first
    );
\FSM_onehot_stateSeq_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => first,
      Q => rdySeq
    );
\FSM_onehot_stateSeq_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \FSM_onehot_stateSeq[2]_i_1_n_0\,
      Q => TCapt
    );
\FSM_onehot_stateSeq_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \FSM_onehot_stateSeq[3]_i_1_n_0\,
      Q => \^q\(0)
    );
\FSM_onehot_stateSeq_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \^q\(0),
      Q => \FSM_onehot_stateSeq_reg_n_0_[4]\
    );
\FSM_onehot_stateSeq_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \FSM_onehot_stateSeq[5]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \FSM_onehot_stateSeq[5]_i_2_n_0\,
      Q => ackSeqbufBToSeqClear
    );
\TCaptMax[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FB00"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(0),
      I2 => stateOp(1),
      I3 => reqInvVidtrackSet,
      I4 => reqInvVidtrackSelect,
      O => TCaptMax
    );
\TCaptMax_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => \TCaptMax_reg[7]_0\(0),
      Q => \TCaptMax_reg_n_0_[0]\
    );
\TCaptMax_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(2),
      Q => \TCaptMax_reg_n_0_[10]\
    );
\TCaptMax_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(3),
      Q => \TCaptMax_reg_n_0_[11]\
    );
\TCaptMax_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(4),
      Q => \TCaptMax_reg_n_0_[12]\
    );
\TCaptMax_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(5),
      Q => \TCaptMax_reg_n_0_[13]\
    );
\TCaptMax_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(6),
      Q => \TCaptMax_reg_n_0_[14]\
    );
\TCaptMax_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(7),
      Q => \TCaptMax_reg_n_0_[15]\
    );
\TCaptMax_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(8),
      Q => \TCaptMax_reg_n_0_[16]\
    );
\TCaptMax_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(9),
      Q => \TCaptMax_reg_n_0_[17]\
    );
\TCaptMax_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(10),
      Q => \TCaptMax_reg_n_0_[18]\
    );
\TCaptMax_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(11),
      Q => \TCaptMax_reg_n_0_[19]\
    );
\TCaptMax_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => \TCaptMax_reg[7]_0\(1),
      Q => \TCaptMax_reg_n_0_[1]\
    );
\TCaptMax_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(12),
      Q => \TCaptMax_reg_n_0_[20]\
    );
\TCaptMax_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(13),
      Q => \TCaptMax_reg_n_0_[21]\
    );
\TCaptMax_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(14),
      Q => \TCaptMax_reg_n_0_[22]\
    );
\TCaptMax_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(15),
      Q => \TCaptMax_reg_n_0_[23]\
    );
\TCaptMax_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(16),
      Q => \TCaptMax_reg_n_0_[24]\
    );
\TCaptMax_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(17),
      Q => \TCaptMax_reg_n_0_[25]\
    );
\TCaptMax_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(18),
      Q => \TCaptMax_reg_n_0_[26]\
    );
\TCaptMax_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(19),
      Q => \TCaptMax_reg_n_0_[27]\
    );
\TCaptMax_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(20),
      Q => \TCaptMax_reg_n_0_[28]\
    );
\TCaptMax_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(21),
      Q => \TCaptMax_reg_n_0_[29]\
    );
\TCaptMax_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => \TCaptMax_reg[7]_0\(2),
      Q => \TCaptMax_reg_n_0_[2]\
    );
\TCaptMax_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(22),
      Q => \TCaptMax_reg_n_0_[30]\
    );
\TCaptMax_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(23),
      Q => \TCaptMax_reg_n_0_[31]\
    );
\TCaptMax_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => \TCaptMax_reg[7]_0\(3),
      Q => \TCaptMax_reg_n_0_[3]\
    );
\TCaptMax_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => \TCaptMax_reg[7]_0\(4),
      Q => \TCaptMax_reg_n_0_[4]\
    );
\TCaptMax_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => \TCaptMax_reg[7]_0\(5),
      Q => \TCaptMax_reg_n_0_[5]\
    );
\TCaptMax_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => \TCaptMax_reg[7]_0\(6),
      Q => \TCaptMax_reg_n_0_[6]\
    );
\TCaptMax_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => \TCaptMax_reg[7]_0\(7),
      Q => \TCaptMax_reg_n_0_[7]\
    );
\TCaptMax_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(0),
      Q => \TCaptMax_reg_n_0_[8]\
    );
\TCaptMax_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => D(1),
      Q => \TCaptMax_reg_n_0_[9]\
    );
\TCapt[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(0),
      I1 => first,
      O => \TCapt__0\(0)
    );
\TCapt[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(10),
      I1 => first,
      O => \TCapt__0\(10)
    );
\TCapt[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(11),
      I1 => first,
      O => \TCapt__0\(11)
    );
\TCapt[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(12),
      I1 => first,
      O => \TCapt__0\(12)
    );
\TCapt[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(13),
      I1 => first,
      O => \TCapt__0\(13)
    );
\TCapt[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(14),
      I1 => first,
      O => \TCapt__0\(14)
    );
\TCapt[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(15),
      I1 => first,
      O => \TCapt__0\(15)
    );
\TCapt[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(16),
      I1 => first,
      O => \TCapt__0\(16)
    );
\TCapt[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(17),
      I1 => first,
      O => \TCapt__0\(17)
    );
\TCapt[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(18),
      I1 => first,
      O => \TCapt__0\(18)
    );
\TCapt[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(19),
      I1 => first,
      O => \TCapt__0\(19)
    );
\TCapt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(1),
      I1 => first,
      O => \TCapt__0\(1)
    );
\TCapt[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(20),
      I1 => first,
      O => \TCapt__0\(20)
    );
\TCapt[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(21),
      I1 => first,
      O => \TCapt__0\(21)
    );
\TCapt[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(22),
      I1 => first,
      O => \TCapt__0\(22)
    );
\TCapt[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(23),
      I1 => first,
      O => \TCapt__0\(23)
    );
\TCapt[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(24),
      I1 => first,
      O => \TCapt__0\(24)
    );
\TCapt[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(25),
      I1 => first,
      O => \TCapt__0\(25)
    );
\TCapt[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(26),
      I1 => first,
      O => \TCapt__0\(26)
    );
\TCapt[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(27),
      I1 => first,
      O => \TCapt__0\(27)
    );
\TCapt[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(28),
      I1 => first,
      O => \TCapt__0\(28)
    );
\TCapt[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(29),
      I1 => first,
      O => \TCapt__0\(29)
    );
\TCapt[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(2),
      I1 => first,
      O => \TCapt__0\(2)
    );
\TCapt[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(30),
      I1 => first,
      O => \TCapt__0\(30)
    );
\TCapt[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(31),
      I1 => first,
      O => \TCapt__0\(31)
    );
\TCapt[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(3),
      I1 => first,
      O => \TCapt__0\(3)
    );
\TCapt[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(4),
      I1 => first,
      O => \TCapt__0\(4)
    );
\TCapt[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(5),
      I1 => first,
      O => \TCapt__0\(5)
    );
\TCapt[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(6),
      I1 => first,
      O => \TCapt__0\(6)
    );
\TCapt[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(7),
      I1 => first,
      O => \TCapt__0\(7)
    );
\TCapt[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(8),
      I1 => first,
      O => \TCapt__0\(8)
    );
\TCapt[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in12(9),
      I1 => first,
      O => \TCapt__0\(9)
    );
\TCapt_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(0),
      Q => \^tcapt_reg[31]_0\(0)
    );
\TCapt_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(10),
      Q => \^tcapt_reg[31]_0\(10)
    );
\TCapt_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(11),
      Q => \^tcapt_reg[31]_0\(11)
    );
\TCapt_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(12),
      Q => \^tcapt_reg[31]_0\(12)
    );
\TCapt_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(13),
      Q => \^tcapt_reg[31]_0\(13)
    );
\TCapt_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(14),
      Q => \^tcapt_reg[31]_0\(14)
    );
\TCapt_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(15),
      Q => \^tcapt_reg[31]_0\(15)
    );
\TCapt_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(16),
      Q => \^tcapt_reg[31]_0\(16)
    );
\TCapt_reg[16]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \TCapt_reg[8]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \TCapt_reg[16]_i_2_n_0\,
      CO(6) => \TCapt_reg[16]_i_2_n_1\,
      CO(5) => \TCapt_reg[16]_i_2_n_2\,
      CO(4) => \TCapt_reg[16]_i_2_n_3\,
      CO(3) => \TCapt_reg[16]_i_2_n_4\,
      CO(2) => \TCapt_reg[16]_i_2_n_5\,
      CO(1) => \TCapt_reg[16]_i_2_n_6\,
      CO(0) => \TCapt_reg[16]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in12(16 downto 9),
      S(7 downto 0) => \^tcapt_reg[31]_0\(16 downto 9)
    );
\TCapt_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(17),
      Q => \^tcapt_reg[31]_0\(17)
    );
\TCapt_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(18),
      Q => \^tcapt_reg[31]_0\(18)
    );
\TCapt_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(19),
      Q => \^tcapt_reg[31]_0\(19)
    );
\TCapt_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(1),
      Q => \^tcapt_reg[31]_0\(1)
    );
\TCapt_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(20),
      Q => \^tcapt_reg[31]_0\(20)
    );
\TCapt_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(21),
      Q => \^tcapt_reg[31]_0\(21)
    );
\TCapt_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(22),
      Q => \^tcapt_reg[31]_0\(22)
    );
\TCapt_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(23),
      Q => \^tcapt_reg[31]_0\(23)
    );
\TCapt_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(24),
      Q => \^tcapt_reg[31]_0\(24)
    );
\TCapt_reg[24]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \TCapt_reg[16]_i_2_n_0\,
      CI_TOP => '0',
      CO(7) => \TCapt_reg[24]_i_2_n_0\,
      CO(6) => \TCapt_reg[24]_i_2_n_1\,
      CO(5) => \TCapt_reg[24]_i_2_n_2\,
      CO(4) => \TCapt_reg[24]_i_2_n_3\,
      CO(3) => \TCapt_reg[24]_i_2_n_4\,
      CO(2) => \TCapt_reg[24]_i_2_n_5\,
      CO(1) => \TCapt_reg[24]_i_2_n_6\,
      CO(0) => \TCapt_reg[24]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in12(24 downto 17),
      S(7 downto 0) => \^tcapt_reg[31]_0\(24 downto 17)
    );
\TCapt_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(25),
      Q => \^tcapt_reg[31]_0\(25)
    );
\TCapt_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(26),
      Q => \^tcapt_reg[31]_0\(26)
    );
\TCapt_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(27),
      Q => \^tcapt_reg[31]_0\(27)
    );
\TCapt_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(28),
      Q => \^tcapt_reg[31]_0\(28)
    );
\TCapt_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(29),
      Q => \^tcapt_reg[31]_0\(29)
    );
\TCapt_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(2),
      Q => \^tcapt_reg[31]_0\(2)
    );
\TCapt_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(30),
      Q => \^tcapt_reg[31]_0\(30)
    );
\TCapt_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(31),
      Q => \^tcapt_reg[31]_0\(31)
    );
\TCapt_reg[31]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \TCapt_reg[24]_i_2_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_TCapt_reg[31]_i_2_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \TCapt_reg[31]_i_2_n_2\,
      CO(4) => \TCapt_reg[31]_i_2_n_3\,
      CO(3) => \TCapt_reg[31]_i_2_n_4\,
      CO(2) => \TCapt_reg[31]_i_2_n_5\,
      CO(1) => \TCapt_reg[31]_i_2_n_6\,
      CO(0) => \TCapt_reg[31]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NLW_TCapt_reg[31]_i_2_O_UNCONNECTED\(7),
      O(6 downto 0) => in12(31 downto 25),
      S(7) => '0',
      S(6 downto 0) => \^tcapt_reg[31]_0\(31 downto 25)
    );
\TCapt_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(3),
      Q => \^tcapt_reg[31]_0\(3)
    );
\TCapt_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(4),
      Q => \^tcapt_reg[31]_0\(4)
    );
\TCapt_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(5),
      Q => \^tcapt_reg[31]_0\(5)
    );
\TCapt_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(6),
      Q => \^tcapt_reg[31]_0\(6)
    );
\TCapt_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(7),
      Q => \^tcapt_reg[31]_0\(7)
    );
\TCapt_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(8),
      Q => \^tcapt_reg[31]_0\(8)
    );
\TCapt_reg[8]_i_2\: unisim.vcomponents.CARRY8
     port map (
      CI => \^tcapt_reg[31]_0\(0),
      CI_TOP => '0',
      CO(7) => \TCapt_reg[8]_i_2_n_0\,
      CO(6) => \TCapt_reg[8]_i_2_n_1\,
      CO(5) => \TCapt_reg[8]_i_2_n_2\,
      CO(4) => \TCapt_reg[8]_i_2_n_3\,
      CO(3) => \TCapt_reg[8]_i_2_n_4\,
      CO(2) => \TCapt_reg[8]_i_2_n_5\,
      CO(1) => \TCapt_reg[8]_i_2_n_6\,
      CO(0) => \TCapt_reg[8]_i_2_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => in12(8 downto 1),
      S(7 downto 0) => \^tcapt_reg[31]_0\(8 downto 1)
    );
\TCapt_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => \TCapt__0\(9),
      Q => \^tcapt_reg[31]_0\(9)
    );
\aSeqbufB[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[0]\,
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      O => \aSeqbufB[0]_i_1_n_0\
    );
\aSeqbufB[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6660"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[1]\,
      I1 => \aSeqbufB_reg_n_0_[0]\,
      I2 => stateSeqbufB_reg(1),
      I3 => stateSeqbufB_reg(0),
      O => \aSeqbufB[1]_i_1_n_0\
    );
\aSeqbufB[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78787800"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[0]\,
      I1 => \aSeqbufB_reg_n_0_[1]\,
      I2 => \aSeqbufB_reg_n_0_[2]\,
      I3 => stateSeqbufB_reg(1),
      I4 => stateSeqbufB_reg(0),
      O => \aSeqbufB[2]_i_1_n_0\
    );
\aSeqbufB[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[2]\,
      I1 => \aSeqbufB_reg_n_0_[1]\,
      I2 => \aSeqbufB_reg_n_0_[0]\,
      I3 => \aSeqbufB_reg_n_0_[3]\,
      I4 => \aSeqbufB[8]_i_3_n_0\,
      O => \aSeqbufB[3]_i_1_n_0\
    );
\aSeqbufB[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1555555540000000"
    )
        port map (
      I0 => \aSeqbufB[8]_i_3_n_0\,
      I1 => \aSeqbufB_reg_n_0_[3]\,
      I2 => \aSeqbufB_reg_n_0_[0]\,
      I3 => \aSeqbufB_reg_n_0_[1]\,
      I4 => \aSeqbufB_reg_n_0_[2]\,
      I5 => \aSeqbufB_reg_n_0_[4]\,
      O => \aSeqbufB[4]_i_1_n_0\
    );
\aSeqbufB[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0EE0"
    )
        port map (
      I0 => stateSeqbufB_reg(1),
      I1 => stateSeqbufB_reg(0),
      I2 => \aSeqbufB[5]_i_2_n_0\,
      I3 => \aSeqbufB_reg_n_0_[5]\,
      O => \aSeqbufB[5]_i_1_n_0\
    );
\aSeqbufB[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[4]\,
      I1 => \aSeqbufB_reg_n_0_[2]\,
      I2 => \aSeqbufB_reg_n_0_[1]\,
      I3 => \aSeqbufB_reg_n_0_[0]\,
      I4 => \aSeqbufB_reg_n_0_[3]\,
      O => \aSeqbufB[5]_i_2_n_0\
    );
\aSeqbufB[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0EE0"
    )
        port map (
      I0 => stateSeqbufB_reg(1),
      I1 => stateSeqbufB_reg(0),
      I2 => \aSeqbufB[8]_i_4_n_0\,
      I3 => \aSeqbufB_reg_n_0_[6]\,
      O => \aSeqbufB[6]_i_1_n_0\
    );
\aSeqbufB[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78787800"
    )
        port map (
      I0 => \aSeqbufB[8]_i_4_n_0\,
      I1 => \aSeqbufB_reg_n_0_[6]\,
      I2 => \aSeqbufB_reg_n_0_[7]\,
      I3 => stateSeqbufB_reg(1),
      I4 => stateSeqbufB_reg(0),
      O => \aSeqbufB[7]_i_1_n_0\
    );
\aSeqbufB[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4101"
    )
        port map (
      I0 => stateSeqbufB_reg(2),
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      I3 => \stateSeqbufB[1]_i_2_n_0\,
      O => \aSeqbufB[8]_i_1_n_0\
    );
\aSeqbufB[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15554000"
    )
        port map (
      I0 => \aSeqbufB[8]_i_3_n_0\,
      I1 => \aSeqbufB_reg_n_0_[7]\,
      I2 => \aSeqbufB_reg_n_0_[6]\,
      I3 => \aSeqbufB[8]_i_4_n_0\,
      I4 => \aSeqbufB_reg_n_0_[8]\,
      O => \aSeqbufB[8]_i_2_n_0\
    );
\aSeqbufB[8]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => stateSeqbufB_reg(0),
      I1 => stateSeqbufB_reg(2),
      I2 => stateSeqbufB_reg(1),
      O => \aSeqbufB[8]_i_3_n_0\
    );
\aSeqbufB[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[3]\,
      I1 => \aSeqbufB_reg_n_0_[0]\,
      I2 => \aSeqbufB_reg_n_0_[1]\,
      I3 => \aSeqbufB_reg_n_0_[2]\,
      I4 => \aSeqbufB_reg_n_0_[4]\,
      I5 => \aSeqbufB_reg_n_0_[5]\,
      O => \aSeqbufB[8]_i_4_n_0\
    );
\aSeqbufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbufB[0]_i_1_n_0\,
      Q => \aSeqbufB_reg_n_0_[0]\
    );
\aSeqbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbufB[1]_i_1_n_0\,
      Q => \aSeqbufB_reg_n_0_[1]\
    );
\aSeqbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbufB[2]_i_1_n_0\,
      Q => \aSeqbufB_reg_n_0_[2]\
    );
\aSeqbufB_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbufB[3]_i_1_n_0\,
      Q => \aSeqbufB_reg_n_0_[3]\
    );
\aSeqbufB_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbufB[4]_i_1_n_0\,
      Q => \aSeqbufB_reg_n_0_[4]\
    );
\aSeqbufB_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbufB[5]_i_1_n_0\,
      Q => \aSeqbufB_reg_n_0_[5]\
    );
\aSeqbufB_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbufB[6]_i_1_n_0\,
      Q => \aSeqbufB_reg_n_0_[6]\
    );
\aSeqbufB_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbufB[7]_i_1_n_0\,
      Q => \aSeqbufB_reg_n_0_[7]\
    );
\aSeqbufB_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbufB[8]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbufB[8]_i_2_n_0\,
      Q => \aSeqbufB_reg_n_0_[8]\
    );
\aSeqbuf[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555544454454"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[0]\,
      I1 => ackSeqbufBToSeqClear,
      I2 => rdySeq,
      I3 => \^q\(0),
      I4 => TCapt,
      I5 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \aSeqbuf[0]_i_1_n_0\
    );
\aSeqbuf[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[1]\,
      I1 => \aSeqbuf_reg_n_0_[0]\,
      I2 => \aSeqbuf[3]_i_2_n_0\,
      O => \aSeqbuf[1]_i_1_n_0\
    );
\aSeqbuf[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[0]\,
      I1 => \aSeqbuf_reg_n_0_[1]\,
      I2 => \aSeqbuf_reg_n_0_[2]\,
      I3 => \aSeqbuf[3]_i_2_n_0\,
      O => \aSeqbuf[2]_i_1_n_0\
    );
\aSeqbuf[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[2]\,
      I1 => \aSeqbuf_reg_n_0_[1]\,
      I2 => \aSeqbuf_reg_n_0_[0]\,
      I3 => \aSeqbuf_reg_n_0_[3]\,
      I4 => \aSeqbuf[3]_i_2_n_0\,
      O => \aSeqbuf[3]_i_1_n_0\
    );
\aSeqbuf[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00005451"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => TCapt,
      I2 => \^q\(0),
      I3 => rdySeq,
      I4 => ackSeqbufBToSeqClear,
      O => \aSeqbuf[3]_i_2_n_0\
    );
\aSeqbuf[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \aSeqbuf[9]_i_6_n_0\,
      I1 => \aSeqbuf_reg_n_0_[3]\,
      I2 => \aSeqbuf_reg_n_0_[0]\,
      I3 => \aSeqbuf_reg_n_0_[1]\,
      I4 => \aSeqbuf_reg_n_0_[2]\,
      I5 => \aSeqbuf_reg_n_0_[4]\,
      O => \aSeqbuf[4]_i_1_n_0\
    );
\aSeqbuf[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF1400000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => rdySeq,
      I2 => TCapt,
      I3 => ackSeqbufBToSeqClear,
      I4 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I5 => \aSeqbuf[5]_i_2_n_0\,
      O => \aSeqbuf[5]_i_1_n_0\
    );
\aSeqbuf[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[5]\,
      I1 => \aSeqbuf_reg_n_0_[4]\,
      I2 => \aSeqbuf_reg_n_0_[3]\,
      I3 => \aSeqbuf_reg_n_0_[0]\,
      I4 => \aSeqbuf_reg_n_0_[1]\,
      I5 => \aSeqbuf_reg_n_0_[2]\,
      O => \aSeqbuf[5]_i_2_n_0\
    );
\aSeqbuf[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \aSeqbuf[9]_i_6_n_0\,
      I1 => \aSeqbuf[9]_i_7_n_0\,
      I2 => \aSeqbuf_reg_n_0_[6]\,
      O => \aSeqbuf[6]_i_1_n_0\
    );
\aSeqbuf[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \aSeqbuf[9]_i_6_n_0\,
      I1 => \aSeqbuf[9]_i_7_n_0\,
      I2 => \aSeqbuf_reg_n_0_[6]\,
      I3 => \aSeqbuf_reg_n_0_[7]\,
      O => \aSeqbuf[7]_i_1_n_0\
    );
\aSeqbuf[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1131"
    )
        port map (
      I0 => \aSeqbuf[8]_i_2_n_0\,
      I1 => \aSeqbuf[8]_i_3_n_0\,
      I2 => \aSeqbuf[8]_i_4_n_0\,
      I3 => \aSeqbuf[9]_i_4_n_0\,
      O => \aSeqbuf[8]_i_1_n_0\
    );
\aSeqbuf[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00540055"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => \^q\(0),
      I2 => TCapt,
      I3 => ackSeqbufBToSeqClear,
      I4 => rdySeq,
      O => \aSeqbuf[8]_i_2_n_0\
    );
\aSeqbuf[8]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9555"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[8]\,
      I1 => \aSeqbuf[9]_i_7_n_0\,
      I2 => \aSeqbuf_reg_n_0_[7]\,
      I3 => \aSeqbuf_reg_n_0_[6]\,
      O => \aSeqbuf[8]_i_3_n_0\
    );
\aSeqbuf[8]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => \^q\(0),
      I2 => rdySeq,
      I3 => ackSeqbufBToSeqClear,
      I4 => TCapt,
      O => \aSeqbuf[8]_i_4_n_0\
    );
\aSeqbuf[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFAE"
    )
        port map (
      I0 => \aSeqbuf[9]_i_3_n_0\,
      I1 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I2 => \aSeqbuf[9]_i_4_n_0\,
      I3 => \aSeqbuf[9]_i_5_n_0\,
      O => \aSeqbuf[9]_i_1_n_0\
    );
\aSeqbuf[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A80AA00AA00AA00"
    )
        port map (
      I0 => \aSeqbuf[9]_i_6_n_0\,
      I1 => \aSeqbuf_reg_n_0_[6]\,
      I2 => \aSeqbuf[9]_i_7_n_0\,
      I3 => \aSeqbuf_reg_n_0_[9]\,
      I4 => \aSeqbuf_reg_n_0_[7]\,
      I5 => \aSeqbuf_reg_n_0_[8]\,
      O => \aSeqbuf[9]_i_2_n_0\
    );
\aSeqbuf[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"008000800080AAAA"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_6_n_0\,
      I1 => \burstCnt[4]_i_2_n_0\,
      I2 => \burstCnt[15]_i_3_n_0\,
      I3 => \first__0\,
      I4 => \^q\(0),
      I5 => TCapt,
      O => \aSeqbuf[9]_i_3_n_0\
    );
\aSeqbuf[9]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[6]\,
      I1 => \aSeqbuf[9]_i_7_n_0\,
      I2 => \aSeqbuf_reg_n_0_[9]\,
      I3 => \aSeqbuf_reg_n_0_[7]\,
      I4 => \aSeqbuf_reg_n_0_[8]\,
      O => \aSeqbuf[9]_i_4_n_0\
    );
\aSeqbuf[9]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0300020003000000"
    )
        port map (
      I0 => rdySeq,
      I1 => ackSeqbufBToSeqClear,
      I2 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I3 => \FSM_onehot_stateSeq[5]_i_4_n_0\,
      I4 => \^q\(0),
      I5 => TCapt,
      O => \aSeqbuf[9]_i_5_n_0\
    );
\aSeqbuf[9]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF0F0F1FC"
    )
        port map (
      I0 => \aSeqbuf[9]_i_4_n_0\,
      I1 => rdySeq,
      I2 => ackSeqbufBToSeqClear,
      I3 => TCapt,
      I4 => \^q\(0),
      I5 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      O => \aSeqbuf[9]_i_6_n_0\
    );
\aSeqbuf[9]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[5]\,
      I1 => \aSeqbuf_reg_n_0_[4]\,
      I2 => \aSeqbuf_reg_n_0_[3]\,
      I3 => \aSeqbuf_reg_n_0_[0]\,
      I4 => \aSeqbuf_reg_n_0_[1]\,
      I5 => \aSeqbuf_reg_n_0_[2]\,
      O => \aSeqbuf[9]_i_7_n_0\
    );
\aSeqbuf_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbuf[0]_i_1_n_0\,
      Q => \aSeqbuf_reg_n_0_[0]\
    );
\aSeqbuf_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbuf[1]_i_1_n_0\,
      Q => \aSeqbuf_reg_n_0_[1]\
    );
\aSeqbuf_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbuf[2]_i_1_n_0\,
      Q => \aSeqbuf_reg_n_0_[2]\
    );
\aSeqbuf_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbuf[3]_i_1_n_0\,
      Q => \aSeqbuf_reg_n_0_[3]\
    );
\aSeqbuf_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbuf[4]_i_1_n_0\,
      Q => \aSeqbuf_reg_n_0_[4]\
    );
\aSeqbuf_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbuf[5]_i_1_n_0\,
      Q => \aSeqbuf_reg_n_0_[5]\
    );
\aSeqbuf_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbuf[6]_i_1_n_0\,
      Q => \aSeqbuf_reg_n_0_[6]\
    );
\aSeqbuf_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbuf[7]_i_1_n_0\,
      Q => \aSeqbuf_reg_n_0_[7]\
    );
\aSeqbuf_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbuf[8]_i_1_n_0\,
      Q => \aSeqbuf_reg_n_0_[8]\
    );
\aSeqbuf_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \aSeqbuf[9]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \aSeqbuf[9]_i_2_n_0\,
      Q => \aSeqbuf_reg_n_0_[9]\
    );
ackInvSelect_sig_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8088EEEE"
    )
        port map (
      I0 => \^ackinvvidtrackselect\,
      I1 => reqInvVidtrackSelect,
      I2 => reqInvVidtrackSet,
      I3 => \^ackinvvidtrackset\,
      I4 => ackInvSelect_sig_i_2_n_0,
      O => ackInvSelect_sig_i_1_n_0
    );
ackInvSelect_sig_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(0),
      I2 => stateOp(1),
      O => ackInvSelect_sig_i_2_n_0
    );
ackInvSelect_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => first_reg_0(0),
      D => ackInvSelect_sig_i_1_n_0,
      Q => \^ackinvvidtrackselect\
    );
\ackInvSet_sig_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C400CFCC"
    )
        port map (
      I0 => \^ackinvvidtrackselect\,
      I1 => \^ackinvvidtrackset\,
      I2 => reqInvVidtrackSelect,
      I3 => reqInvVidtrackSet,
      I4 => ackInvSelect_sig_i_2_n_0,
      O => \ackInvSet_sig_i_1__0_n_0\
    );
ackInvSet_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => first_reg_0(0),
      D => \ackInvSet_sig_i_1__0_n_0\,
      Q => \^ackinvvidtrackset\
    );
\burstCnt[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4404"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[15]_i_4_n_0\,
      I2 => \burstCnt_reg_n_0_[0]\,
      I3 => \burstCnt[15]_i_5_n_0\,
      O => \burstCnt[0]_i_1__0_n_0\
    );
\burstCnt[10]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[10]_i_2_n_0\,
      O => \burstCnt[10]_i_1__0_n_0\
    );
\burstCnt[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7F7FDF7F7F7F7F7"
    )
        port map (
      I0 => \burstCnt[15]_i_4_n_0\,
      I1 => \burstCnt_reg_n_0_[10]\,
      I2 => \burstCnt[15]_i_5_n_0\,
      I3 => \burstCnt_reg_n_0_[8]\,
      I4 => \burstCnt[10]_i_3_n_0\,
      I5 => \burstCnt_reg_n_0_[9]\,
      O => \burstCnt[10]_i_2_n_0\
    );
\burstCnt[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \burstCnt[15]_i_5_n_0\,
      I1 => \burstCnt_reg_n_0_[5]\,
      I2 => \burstCnt_reg_n_0_[4]\,
      I3 => \burstCnt[5]_i_2_n_0\,
      I4 => \burstCnt_reg_n_0_[6]\,
      I5 => \burstCnt_reg_n_0_[7]\,
      O => \burstCnt[10]_i_3_n_0\
    );
\burstCnt[11]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[11]_i_2_n_0\,
      O => \burstCnt[11]_i_1__0_n_0\
    );
\burstCnt[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF5DFFF7"
    )
        port map (
      I0 => \burstCnt[15]_i_4_n_0\,
      I1 => \burstCnt_reg_n_0_[10]\,
      I2 => \burstCnt[15]_i_15_n_0\,
      I3 => \burstCnt[15]_i_5_n_0\,
      I4 => \burstCnt_reg_n_0_[11]\,
      O => \burstCnt[11]_i_2_n_0\
    );
\burstCnt[12]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[12]_i_2_n_0\,
      O => \burstCnt[12]_i_1__0_n_0\
    );
\burstCnt[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7F7F7F7FDF7F7F7"
    )
        port map (
      I0 => \burstCnt[15]_i_4_n_0\,
      I1 => \burstCnt_reg_n_0_[12]\,
      I2 => \burstCnt[15]_i_5_n_0\,
      I3 => \burstCnt_reg_n_0_[11]\,
      I4 => \burstCnt_reg_n_0_[10]\,
      I5 => \burstCnt[15]_i_15_n_0\,
      O => \burstCnt[12]_i_2_n_0\
    );
\burstCnt[13]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[13]_i_2_n_0\,
      O => \burstCnt[13]_i_1__0_n_0\
    );
\burstCnt[13]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFD5FF7F"
    )
        port map (
      I0 => \burstCnt[15]_i_4_n_0\,
      I1 => \burstCnt_reg_n_0_[12]\,
      I2 => \burstCnt[14]_i_3_n_0\,
      I3 => \burstCnt[15]_i_5_n_0\,
      I4 => \burstCnt_reg_n_0_[13]\,
      O => \burstCnt[13]_i_2_n_0\
    );
\burstCnt[14]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[14]_i_2_n_0\,
      O => \burstCnt[14]_i_1__0_n_0\
    );
\burstCnt[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFD7FF77FF77FF77"
    )
        port map (
      I0 => \burstCnt[15]_i_4_n_0\,
      I1 => \burstCnt_reg_n_0_[14]\,
      I2 => \burstCnt[14]_i_3_n_0\,
      I3 => \burstCnt[15]_i_5_n_0\,
      I4 => \burstCnt_reg_n_0_[12]\,
      I5 => \burstCnt_reg_n_0_[13]\,
      O => \burstCnt[14]_i_2_n_0\
    );
\burstCnt[14]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000080000000000"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[11]\,
      I1 => \burstCnt_reg_n_0_[10]\,
      I2 => \burstCnt[15]_i_5_n_0\,
      I3 => \burstCnt_reg_n_0_[8]\,
      I4 => \burstCnt[10]_i_3_n_0\,
      I5 => \burstCnt_reg_n_0_[9]\,
      O => \burstCnt[14]_i_3_n_0\
    );
\burstCnt[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000101"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => rdySeq,
      I2 => ackSeqbufBToSeqClear,
      I3 => \burstCnt[15]_i_3_n_0\,
      I4 => \^q\(0),
      I5 => TCapt,
      O => \burstCnt[15]_i_1_n_0\
    );
\burstCnt[15]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABAEAFAFAFAFABAE"
    )
        port map (
      I0 => \burstCnt[15]_i_21_n_0\,
      I1 => \quad_reg_n_0_[8]\,
      I2 => \burstCnt[15]_i_16_n_0\,
      I3 => state(0),
      I4 => \quad_reg_n_0_[10]\,
      I5 => state(7),
      O => \burstCnt[15]_i_10_n_0\
    );
\burstCnt[15]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6F0F666FF6F066F6"
    )
        port map (
      I0 => state(7),
      I1 => \quad_reg_n_0_[23]\,
      I2 => state(4),
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[1]\,
      I5 => \quad_reg_n_0_[12]\,
      O => \burstCnt[15]_i_11_n_0\
    );
\burstCnt[15]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6F6F660FF6F666F0"
    )
        port map (
      I0 => state(7),
      I1 => \quad_reg_n_0_[1]\,
      I2 => state(5),
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[1]\,
      I5 => \quad_reg_n_0_[13]\,
      O => \burstCnt[15]_i_12_n_0\
    );
\burstCnt[15]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF6FF6"
    )
        port map (
      I0 => state(6),
      I1 => \burstState_reg_n_0_[6]\,
      I2 => \burstState_reg_n_0_[0]\,
      I3 => state(0),
      I4 => \burstCnt[15]_i_22_n_0\,
      I5 => \burstCnt[15]_i_23_n_0\,
      O => \burstCnt[15]_i_13_n_0\
    );
\burstCnt[15]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF7FFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[4]\,
      I1 => \burstCnt_reg_n_0_[12]\,
      I2 => \burstCnt_reg_n_0_[8]\,
      I3 => \burstCnt_reg_n_0_[9]\,
      I4 => \burstCnt[15]_i_24_n_0\,
      I5 => \burstCnt[15]_i_25_n_0\,
      O => \burstCnt[15]_i_14_n_0\
    );
\burstCnt[15]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \burstCnt[15]_i_26_n_0\,
      I1 => \burstCnt_reg_n_0_[9]\,
      O => \burstCnt[15]_i_15_n_0\
    );
\burstCnt[15]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \i_reg_n_0_[1]\,
      O => \burstCnt[15]_i_16_n_0\
    );
\burstCnt[15]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6F0F6F66F6F0F666"
    )
        port map (
      I0 => state(4),
      I1 => \quad_reg_n_0_[20]\,
      I2 => state(5),
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[1]\,
      I5 => \quad_reg_n_0_[5]\,
      O => \burstCnt[15]_i_17_n_0\
    );
\burstCnt[15]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6F6F660FF6F666F0"
    )
        port map (
      I0 => state(6),
      I1 => \quad_reg_n_0_[6]\,
      I2 => state(5),
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[0]\,
      I5 => \quad_reg_n_0_[21]\,
      O => \burstCnt[15]_i_18_n_0\
    );
\burstCnt[15]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7763EE6C"
    )
        port map (
      I0 => \quad_reg_n_0_[3]\,
      I1 => state(7),
      I2 => \i_reg_n_0_[0]\,
      I3 => \i_reg_n_0_[1]\,
      I4 => \quad_reg_n_0_[15]\,
      O => \burstCnt[15]_i_19_n_0\
    );
\burstCnt[15]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF12333312"
    )
        port map (
      I0 => \quad_reg_n_0_[7]\,
      I1 => \burstCnt[15]_i_27_n_0\,
      I2 => state(7),
      I3 => \quad_reg_n_0_[0]\,
      I4 => state(0),
      I5 => \burstCnt[15]_i_28_n_0\,
      O => \burstCnt[15]_i_20_n_0\
    );
\burstCnt[15]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6F0F666FF6F066F6"
    )
        port map (
      I0 => state(6),
      I1 => \quad_reg_n_0_[22]\,
      I2 => state(7),
      I3 => \i_reg_n_0_[0]\,
      I4 => \i_reg_n_0_[1]\,
      I5 => \quad_reg_n_0_[11]\,
      O => \burstCnt[15]_i_21_n_0\
    );
\burstCnt[15]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => state(7),
      I1 => \burstState_reg_n_0_[1]\,
      O => \burstCnt[15]_i_22_n_0\
    );
\burstCnt[15]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \burstState_reg_n_0_[1]\,
      I1 => state(7),
      I2 => state(4),
      I3 => \burstState_reg_n_0_[4]\,
      I4 => state(5),
      I5 => \burstState_reg_n_0_[5]\,
      O => \burstCnt[15]_i_23_n_0\
    );
\burstCnt[15]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[14]\,
      I1 => \burstCnt_reg_n_0_[7]\,
      I2 => \burstCnt_reg_n_0_[15]\,
      I3 => \burstCnt_reg_n_0_[5]\,
      O => \burstCnt[15]_i_24_n_0\
    );
\burstCnt[15]_i_25\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[13]\,
      I1 => \burstCnt_reg_n_0_[10]\,
      I2 => \burstCnt_reg_n_0_[11]\,
      I3 => \burstCnt_reg_n_0_[6]\,
      O => \burstCnt[15]_i_25_n_0\
    );
\burstCnt[15]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF7FFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[7]\,
      I1 => \burstCnt_reg_n_0_[5]\,
      I2 => \burstCnt[7]_i_3_n_0\,
      I3 => \burstCnt_reg_n_0_[6]\,
      I4 => \burstCnt_reg_n_0_[8]\,
      I5 => \burstCnt[15]_i_5_n_0\,
      O => \burstCnt[15]_i_26_n_0\
    );
\burstCnt[15]_i_27\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \i_reg_n_0_[1]\,
      O => \burstCnt[15]_i_27_n_0\
    );
\burstCnt[15]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6F6F660FF6F666F0"
    )
        port map (
      I0 => state(4),
      I1 => \quad_reg_n_0_[4]\,
      I2 => state(0),
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[0]\,
      I5 => \quad_reg_n_0_[16]\,
      O => \burstCnt[15]_i_28_n_0\
    );
\burstCnt[15]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000444000004040"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[15]_i_4_n_0\,
      I2 => \burstCnt_reg_n_0_[15]\,
      I3 => \burstCnt_reg_n_0_[14]\,
      I4 => \burstCnt[15]_i_5_n_0\,
      I5 => \burstCnt[15]_i_6__0_n_0\,
      O => \burstCnt[15]_i_2__0_n_0\
    );
\burstCnt[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \i_reg_n_0_[1]\,
      O => \burstCnt[15]_i_3_n_0\
    );
\burstCnt[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => \burstCnt[15]_i_7_n_0\,
      I1 => \burstCnt[15]_i_8_n_0\,
      I2 => \burstCnt[15]_i_9_n_0\,
      I3 => \burstCnt[15]_i_10_n_0\,
      I4 => \burstCnt[15]_i_11_n_0\,
      I5 => \burstCnt[15]_i_12_n_0\,
      O => \burstCnt[15]_i_4_n_0\
    );
\burstCnt[15]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \burstCnt[15]_i_13_n_0\,
      I1 => \burstCnt[15]_i_14_n_0\,
      I2 => \burstCnt_reg_n_0_[3]\,
      I3 => \burstCnt_reg_n_0_[0]\,
      I4 => \burstCnt_reg_n_0_[1]\,
      I5 => \burstCnt_reg_n_0_[2]\,
      O => \burstCnt[15]_i_5_n_0\
    );
\burstCnt[15]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040000000000000"
    )
        port map (
      I0 => \burstCnt[15]_i_15_n_0\,
      I1 => \burstCnt_reg_n_0_[10]\,
      I2 => \burstCnt_reg_n_0_[11]\,
      I3 => \burstCnt[15]_i_5_n_0\,
      I4 => \burstCnt_reg_n_0_[12]\,
      I5 => \burstCnt_reg_n_0_[13]\,
      O => \burstCnt[15]_i_6__0_n_0\
    );
\burstCnt[15]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF12333312"
    )
        port map (
      I0 => \quad_reg_n_0_[14]\,
      I1 => \burstCnt[15]_i_16_n_0\,
      I2 => state(6),
      I3 => \quad_reg_n_0_[9]\,
      I4 => state(7),
      I5 => \burstCnt[15]_i_17_n_0\,
      O => \burstCnt[15]_i_7_n_0\
    );
\burstCnt[15]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AB040857"
    )
        port map (
      I0 => \quad_reg_n_0_[2]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => \quad_reg_n_0_[18]\,
      I5 => \burstCnt[15]_i_18_n_0\,
      O => \burstCnt[15]_i_8_n_0\
    );
\burstCnt[15]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF070E"
    )
        port map (
      I0 => \quad_reg_n_0_[19]\,
      I1 => state(7),
      I2 => \dwrSeqbuf[23]_i_2_n_0\,
      I3 => \quad_reg_n_0_[17]\,
      I4 => \burstCnt[15]_i_19_n_0\,
      I5 => \burstCnt[15]_i_20_n_0\,
      O => \burstCnt[15]_i_9_n_0\
    );
\burstCnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01100000"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[15]_i_5_n_0\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \burstCnt_reg_n_0_[0]\,
      I4 => \burstCnt[15]_i_4_n_0\,
      O => \burstCnt[1]_i_1_n_0\
    );
\burstCnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0015004000000000"
    )
        port map (
      I0 => first,
      I1 => \burstCnt_reg_n_0_[1]\,
      I2 => \burstCnt_reg_n_0_[0]\,
      I3 => \burstCnt[15]_i_5_n_0\,
      I4 => \burstCnt_reg_n_0_[2]\,
      I5 => \burstCnt[15]_i_4_n_0\,
      O => \burstCnt[2]_i_1_n_0\
    );
\burstCnt[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000014444444"
    )
        port map (
      I0 => first,
      I1 => \burstCnt_reg_n_0_[3]\,
      I2 => \burstCnt_reg_n_0_[0]\,
      I3 => \burstCnt_reg_n_0_[1]\,
      I4 => \burstCnt_reg_n_0_[2]\,
      I5 => \burstCnt[4]_i_2_n_0\,
      O => \burstCnt[3]_i_1__0_n_0\
    );
\burstCnt[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0014"
    )
        port map (
      I0 => first,
      I1 => \burstCnt_reg_n_0_[4]\,
      I2 => \burstCnt[5]_i_2_n_0\,
      I3 => \burstCnt[4]_i_2_n_0\,
      O => \burstCnt[4]_i_1_n_0\
    );
\burstCnt[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \burstCnt[15]_i_5_n_0\,
      I1 => \burstCnt[15]_i_4_n_0\,
      O => \burstCnt[4]_i_2_n_0\
    );
\burstCnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004040404000000"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[15]_i_4_n_0\,
      I2 => \burstCnt[15]_i_5_n_0\,
      I3 => \burstCnt[5]_i_2_n_0\,
      I4 => \burstCnt_reg_n_0_[4]\,
      I5 => \burstCnt_reg_n_0_[5]\,
      O => \burstCnt[5]_i_1_n_0\
    );
\burstCnt[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[3]\,
      I1 => \burstCnt_reg_n_0_[0]\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \burstCnt_reg_n_0_[2]\,
      O => \burstCnt[5]_i_2_n_0\
    );
\burstCnt[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[6]_i_2_n_0\,
      O => \burstCnt[6]_i_1_n_0\
    );
\burstCnt[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFD7777777"
    )
        port map (
      I0 => \burstCnt[15]_i_4_n_0\,
      I1 => \burstCnt_reg_n_0_[6]\,
      I2 => \burstCnt[5]_i_2_n_0\,
      I3 => \burstCnt_reg_n_0_[4]\,
      I4 => \burstCnt_reg_n_0_[5]\,
      I5 => \burstCnt[15]_i_5_n_0\,
      O => \burstCnt[6]_i_2_n_0\
    );
\burstCnt[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[7]_i_2_n_0\,
      O => \burstCnt[7]_i_1_n_0\
    );
\burstCnt[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF20FFDFFFFFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[6]\,
      I1 => \burstCnt[7]_i_3_n_0\,
      I2 => \burstCnt_reg_n_0_[5]\,
      I3 => \burstCnt[15]_i_5_n_0\,
      I4 => \burstCnt_reg_n_0_[7]\,
      I5 => \burstCnt[15]_i_4_n_0\,
      O => \burstCnt[7]_i_2_n_0\
    );
\burstCnt[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[4]\,
      I1 => \burstCnt_reg_n_0_[2]\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \burstCnt_reg_n_0_[0]\,
      I4 => \burstCnt_reg_n_0_[3]\,
      O => \burstCnt[7]_i_3_n_0\
    );
\burstCnt[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[8]_i_2_n_0\,
      O => \burstCnt[8]_i_1_n_0\
    );
\burstCnt[8]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF75"
    )
        port map (
      I0 => \burstCnt[15]_i_4_n_0\,
      I1 => \burstCnt[15]_i_5_n_0\,
      I2 => \burstCnt_reg_n_0_[8]\,
      I3 => \burstCnt[10]_i_3_n_0\,
      O => \burstCnt[8]_i_2_n_0\
    );
\burstCnt[9]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \burstCnt[9]_i_2_n_0\,
      O => \burstCnt[9]_i_1__0_n_0\
    );
\burstCnt[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F2FDFFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[8]\,
      I1 => \burstCnt[10]_i_3_n_0\,
      I2 => \burstCnt[15]_i_5_n_0\,
      I3 => \burstCnt_reg_n_0_[9]\,
      I4 => \burstCnt[15]_i_4_n_0\,
      O => \burstCnt[9]_i_2_n_0\
    );
\burstCnt_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[0]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[0]\
    );
\burstCnt_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[10]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[10]\
    );
\burstCnt_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[11]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[11]\
    );
\burstCnt_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[12]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[12]\
    );
\burstCnt_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[13]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[13]\
    );
\burstCnt_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[14]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[14]\
    );
\burstCnt_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[15]_i_2__0_n_0\,
      Q => \burstCnt_reg_n_0_[15]\
    );
\burstCnt_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[1]_i_1_n_0\,
      Q => \burstCnt_reg_n_0_[1]\
    );
\burstCnt_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[2]_i_1_n_0\,
      Q => \burstCnt_reg_n_0_[2]\
    );
\burstCnt_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[3]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[3]\
    );
\burstCnt_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[4]_i_1_n_0\,
      Q => \burstCnt_reg_n_0_[4]\
    );
\burstCnt_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[5]_i_1_n_0\,
      Q => \burstCnt_reg_n_0_[5]\
    );
\burstCnt_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[6]_i_1_n_0\,
      Q => \burstCnt_reg_n_0_[6]\
    );
\burstCnt_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[7]_i_1_n_0\,
      Q => \burstCnt_reg_n_0_[7]\
    );
\burstCnt_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[8]_i_1_n_0\,
      Q => \burstCnt_reg_n_0_[8]\
    );
\burstCnt_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \burstCnt[9]_i_1__0_n_0\,
      Q => \burstCnt_reg_n_0_[9]\
    );
\burstState[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => first,
      I1 => state(0),
      I2 => \burstCnt[15]_i_4_n_0\,
      O => \burstState[0]_i_1_n_0\
    );
\burstState[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => first,
      I1 => state(7),
      I2 => \burstCnt[15]_i_4_n_0\,
      O => \burstState[1]_i_1_n_0\
    );
\burstState[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => first,
      I1 => state(4),
      I2 => \burstCnt[15]_i_4_n_0\,
      O => \burstState[4]_i_1_n_0\
    );
\burstState[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => first,
      I1 => state(5),
      I2 => \burstCnt[15]_i_4_n_0\,
      O => \burstState[5]_i_1_n_0\
    );
\burstState[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => first,
      I1 => state(6),
      I2 => \burstCnt[15]_i_4_n_0\,
      O => \burstState[6]_i_1_n_0\
    );
\burstState_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      D => \burstState[0]_i_1_n_0\,
      PRE => first_reg_0(0),
      Q => \burstState_reg_n_0_[0]\
    );
\burstState_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      D => \burstState[1]_i_1_n_0\,
      PRE => first_reg_0(0),
      Q => \burstState_reg_n_0_[1]\
    );
\burstState_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      D => \burstState[4]_i_1_n_0\,
      PRE => first_reg_0(0),
      Q => \burstState_reg_n_0_[4]\
    );
\burstState_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      D => \burstState[5]_i_1_n_0\,
      PRE => first_reg_0(0),
      Q => \burstState_reg_n_0_[5]\
    );
\burstState_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      D => \burstState[6]_i_1_n_0\,
      PRE => first_reg_0(0),
      Q => \burstState_reg_n_0_[6]\
    );
\dwrSeqbuf[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFFFBAAAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt_reg_n_0_[0]\,
      I2 => \burstCnt[15]_i_5_n_0\,
      I3 => \burstCnt[15]_i_4_n_0\,
      I4 => \dwrSeqbuf[0]_i_2_n_0\,
      I5 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[0]_i_1_n_0\
    );
\dwrSeqbuf[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(0),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[0]\,
      O => \dwrSeqbuf[0]_i_2_n_0\
    );
\dwrSeqbuf[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[10]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[10]_i_2_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[10]_i_1_n_0\
    );
\dwrSeqbuf[10]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(7),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[10]\,
      O => \dwrSeqbuf[10]_i_2_n_0\
    );
\dwrSeqbuf[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[11]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[11]_i_2_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[11]_i_1_n_0\
    );
\dwrSeqbuf[11]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(7),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[11]\,
      O => \dwrSeqbuf[11]_i_2_n_0\
    );
\dwrSeqbuf[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[12]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[12]_i_2_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[12]_i_1_n_0\
    );
\dwrSeqbuf[12]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(4),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[12]\,
      O => \dwrSeqbuf[12]_i_2_n_0\
    );
\dwrSeqbuf[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[13]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[13]_i_2_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[13]_i_1_n_0\
    );
\dwrSeqbuf[13]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(5),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[13]\,
      O => \dwrSeqbuf[13]_i_2_n_0\
    );
\dwrSeqbuf[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[14]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[14]_i_2_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[14]_i_1_n_0\
    );
\dwrSeqbuf[14]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(6),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[14]\,
      O => \dwrSeqbuf[14]_i_2_n_0\
    );
\dwrSeqbuf[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \dwrSeqbuf[15]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[15]_i_3_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[15]_i_1_n_0\
    );
\dwrSeqbuf[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F1F5F5F5F5F5F5F5"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[15]\,
      I1 => \burstCnt_reg_n_0_[14]\,
      I2 => \burstCnt[15]_i_5_n_0\,
      I3 => \burstCnt_reg_n_0_[13]\,
      I4 => \burstCnt_reg_n_0_[12]\,
      I5 => \burstCnt[14]_i_3_n_0\,
      O => \dwrSeqbuf[15]_i_2_n_0\
    );
\dwrSeqbuf[15]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(7),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[15]\,
      O => \dwrSeqbuf[15]_i_3_n_0\
    );
\dwrSeqbuf[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => state(0),
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \aSeqbuf[8]_i_4_n_0\,
      I4 => \quad_reg_n_0_[16]\,
      I5 => \dwrSeqbuf[23]_i_2_n_0\,
      O => \dwrSeqbuf[16]_i_1_n_0\
    );
\dwrSeqbuf[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => state(7),
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \aSeqbuf[8]_i_4_n_0\,
      I4 => \quad_reg_n_0_[17]\,
      I5 => \dwrSeqbuf[23]_i_2_n_0\,
      O => \dwrSeqbuf[17]_i_1_n_0\
    );
\dwrSeqbuf[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => state(7),
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \aSeqbuf[8]_i_4_n_0\,
      I4 => \quad_reg_n_0_[18]\,
      I5 => \dwrSeqbuf[23]_i_2_n_0\,
      O => \dwrSeqbuf[18]_i_1_n_0\
    );
\dwrSeqbuf[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => state(7),
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \aSeqbuf[8]_i_4_n_0\,
      I4 => \quad_reg_n_0_[19]\,
      I5 => \dwrSeqbuf[23]_i_2_n_0\,
      O => \dwrSeqbuf[19]_i_1_n_0\
    );
\dwrSeqbuf[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \dwrSeqbuf[1]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[1]_i_3_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[1]_i_1_n_0\
    );
\dwrSeqbuf[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFD7"
    )
        port map (
      I0 => \burstCnt[15]_i_4_n_0\,
      I1 => \burstCnt_reg_n_0_[0]\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \burstCnt[15]_i_5_n_0\,
      O => \dwrSeqbuf[1]_i_2_n_0\
    );
\dwrSeqbuf[1]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(7),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[1]\,
      O => \dwrSeqbuf[1]_i_3_n_0\
    );
\dwrSeqbuf[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => state(4),
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \aSeqbuf[8]_i_4_n_0\,
      I4 => \quad_reg_n_0_[20]\,
      I5 => \dwrSeqbuf[23]_i_2_n_0\,
      O => \dwrSeqbuf[20]_i_1_n_0\
    );
\dwrSeqbuf[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => state(5),
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \aSeqbuf[8]_i_4_n_0\,
      I4 => \quad_reg_n_0_[21]\,
      I5 => \dwrSeqbuf[23]_i_2_n_0\,
      O => \dwrSeqbuf[21]_i_1_n_0\
    );
\dwrSeqbuf[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => state(6),
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \aSeqbuf[8]_i_4_n_0\,
      I4 => \quad_reg_n_0_[22]\,
      I5 => \dwrSeqbuf[23]_i_2_n_0\,
      O => \dwrSeqbuf[22]_i_1_n_0\
    );
\dwrSeqbuf[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEAAEEAAEFAAEAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => state(7),
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \aSeqbuf[8]_i_4_n_0\,
      I4 => \quad_reg_n_0_[23]\,
      I5 => \dwrSeqbuf[23]_i_2_n_0\,
      O => \dwrSeqbuf[23]_i_1_n_0\
    );
\dwrSeqbuf[23]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      O => \dwrSeqbuf[23]_i_2_n_0\
    );
\dwrSeqbuf[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEFEAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[15]_i_4_n_0\,
      I2 => \quad_reg_n_0_[24]\,
      I3 => \burstCnt[15]_i_3_n_0\,
      I4 => state(0),
      I5 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[24]_i_1_n_0\
    );
\dwrSeqbuf[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEFEAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[15]_i_4_n_0\,
      I2 => \quad_reg_n_0_[25]\,
      I3 => \burstCnt[15]_i_3_n_0\,
      I4 => state(7),
      I5 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[25]_i_1_n_0\
    );
\dwrSeqbuf[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEFEAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[15]_i_4_n_0\,
      I2 => \quad_reg_n_0_[26]\,
      I3 => \burstCnt[15]_i_3_n_0\,
      I4 => state(7),
      I5 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[26]_i_1_n_0\
    );
\dwrSeqbuf[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEFEAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[15]_i_4_n_0\,
      I2 => \quad_reg_n_0_[27]\,
      I3 => \burstCnt[15]_i_3_n_0\,
      I4 => state(7),
      I5 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[27]_i_1_n_0\
    );
\dwrSeqbuf[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEFEAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[15]_i_4_n_0\,
      I2 => \quad_reg_n_0_[28]\,
      I3 => \burstCnt[15]_i_3_n_0\,
      I4 => state(4),
      I5 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[28]_i_1_n_0\
    );
\dwrSeqbuf[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEFEAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[15]_i_4_n_0\,
      I2 => \quad_reg_n_0_[29]\,
      I3 => \burstCnt[15]_i_3_n_0\,
      I4 => state(5),
      I5 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[29]_i_1_n_0\
    );
\dwrSeqbuf[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \dwrSeqbuf[2]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[2]_i_3_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[2]_i_1_n_0\
    );
\dwrSeqbuf[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FDF7F7F7"
    )
        port map (
      I0 => \burstCnt[15]_i_4_n_0\,
      I1 => \burstCnt_reg_n_0_[2]\,
      I2 => \burstCnt[15]_i_5_n_0\,
      I3 => \burstCnt_reg_n_0_[0]\,
      I4 => \burstCnt_reg_n_0_[1]\,
      O => \dwrSeqbuf[2]_i_2_n_0\
    );
\dwrSeqbuf[2]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(7),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[2]\,
      O => \dwrSeqbuf[2]_i_3_n_0\
    );
\dwrSeqbuf[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEFEAAAAAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[15]_i_4_n_0\,
      I2 => \quad_reg_n_0_[30]\,
      I3 => \burstCnt[15]_i_3_n_0\,
      I4 => state(6),
      I5 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[30]_i_1_n_0\
    );
\dwrSeqbuf[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABAAABAAABAAAA"
    )
        port map (
      I0 => \burstCnt[15]_i_1_n_0\,
      I1 => \dwrSeqbuf[31]_i_3__0_n_0\,
      I2 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I3 => ackSeqbufBToSeqClear,
      I4 => rdySeq,
      I5 => \^q\(0),
      O => \dwrSeqbuf[31]_i_1_n_0\
    );
\dwrSeqbuf[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEAE0000"
    )
        port map (
      I0 => \burstCnt[15]_i_4_n_0\,
      I1 => \quad_reg_n_0_[31]\,
      I2 => \burstCnt[15]_i_3_n_0\,
      I3 => state(7),
      I4 => \aSeqbuf[8]_i_4_n_0\,
      I5 => \dwrSeqbuf[31]_i_4_n_0\,
      O => \dwrSeqbuf[31]_i_2_n_0\
    );
\dwrSeqbuf[31]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F111F1F1F1F1F1F"
    )
        port map (
      I0 => TCapt,
      I1 => \^q\(0),
      I2 => \FSM_onehot_stateSeq[0]_i_2_n_0\,
      I3 => stateOp(0),
      I4 => stateOp(2),
      I5 => stateOp(1),
      O => \dwrSeqbuf[31]_i_3__0_n_0\
    );
\dwrSeqbuf[31]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BAAA"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[0]_i_2_n_0\,
      I1 => stateOp(0),
      I2 => stateOp(2),
      I3 => stateOp(1),
      I4 => \FSM_onehot_stateSeq[5]_i_6_n_0\,
      O => \dwrSeqbuf[31]_i_4_n_0\
    );
\dwrSeqbuf[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \dwrSeqbuf[3]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[3]_i_3_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[3]_i_1_n_0\
    );
\dwrSeqbuf[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAABFFF"
    )
        port map (
      I0 => \burstCnt[4]_i_2_n_0\,
      I1 => \burstCnt_reg_n_0_[2]\,
      I2 => \burstCnt_reg_n_0_[1]\,
      I3 => \burstCnt_reg_n_0_[0]\,
      I4 => \burstCnt_reg_n_0_[3]\,
      O => \dwrSeqbuf[3]_i_2_n_0\
    );
\dwrSeqbuf[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(7),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[3]\,
      O => \dwrSeqbuf[3]_i_3_n_0\
    );
\dwrSeqbuf[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \dwrSeqbuf[4]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[4]_i_3_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[4]_i_1_n_0\
    );
\dwrSeqbuf[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAABFFFFFFF"
    )
        port map (
      I0 => \burstCnt[4]_i_2_n_0\,
      I1 => \burstCnt_reg_n_0_[3]\,
      I2 => \burstCnt_reg_n_0_[0]\,
      I3 => \burstCnt_reg_n_0_[1]\,
      I4 => \burstCnt_reg_n_0_[2]\,
      I5 => \burstCnt_reg_n_0_[4]\,
      O => \dwrSeqbuf[4]_i_2_n_0\
    );
\dwrSeqbuf[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(4),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[4]\,
      O => \dwrSeqbuf[4]_i_3_n_0\
    );
\dwrSeqbuf[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \dwrSeqbuf[5]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[5]_i_3_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[5]_i_1_n_0\
    );
\dwrSeqbuf[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF95FFFF"
    )
        port map (
      I0 => \burstCnt_reg_n_0_[5]\,
      I1 => \burstCnt_reg_n_0_[4]\,
      I2 => \burstCnt[5]_i_2_n_0\,
      I3 => \burstCnt[15]_i_5_n_0\,
      I4 => \burstCnt[15]_i_4_n_0\,
      O => \dwrSeqbuf[5]_i_2_n_0\
    );
\dwrSeqbuf[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(5),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[5]\,
      O => \dwrSeqbuf[5]_i_3_n_0\
    );
\dwrSeqbuf[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[6]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[6]_i_2_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[6]_i_1_n_0\
    );
\dwrSeqbuf[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(6),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[6]\,
      O => \dwrSeqbuf[6]_i_2_n_0\
    );
\dwrSeqbuf[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[7]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[7]_i_2_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[7]_i_1_n_0\
    );
\dwrSeqbuf[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE02"
    )
        port map (
      I0 => state(7),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[7]\,
      O => \dwrSeqbuf[7]_i_2_n_0\
    );
\dwrSeqbuf[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[8]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[8]_i_2_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[8]_i_1_n_0\
    );
\dwrSeqbuf[8]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(0),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[8]\,
      O => \dwrSeqbuf[8]_i_2_n_0\
    );
\dwrSeqbuf[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFBBAAAA"
    )
        port map (
      I0 => \dwrSeqbuf[31]_i_4_n_0\,
      I1 => \burstCnt[9]_i_2_n_0\,
      I2 => \burstCnt[15]_i_4_n_0\,
      I3 => \dwrSeqbuf[9]_i_2_n_0\,
      I4 => \aSeqbuf[8]_i_4_n_0\,
      O => \dwrSeqbuf[9]_i_1_n_0\
    );
\dwrSeqbuf[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => state(7),
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \quad_reg_n_0_[9]\,
      O => \dwrSeqbuf[9]_i_2_n_0\
    );
\dwrSeqbuf_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[0]_i_1_n_0\,
      Q => dwrSeqbuf(0)
    );
\dwrSeqbuf_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[10]_i_1_n_0\,
      Q => dwrSeqbuf(10)
    );
\dwrSeqbuf_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[11]_i_1_n_0\,
      Q => dwrSeqbuf(11)
    );
\dwrSeqbuf_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[12]_i_1_n_0\,
      Q => dwrSeqbuf(12)
    );
\dwrSeqbuf_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[13]_i_1_n_0\,
      Q => dwrSeqbuf(13)
    );
\dwrSeqbuf_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[14]_i_1_n_0\,
      Q => dwrSeqbuf(14)
    );
\dwrSeqbuf_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[15]_i_1_n_0\,
      Q => dwrSeqbuf(15)
    );
\dwrSeqbuf_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[16]_i_1_n_0\,
      Q => dwrSeqbuf(16)
    );
\dwrSeqbuf_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[17]_i_1_n_0\,
      Q => dwrSeqbuf(17)
    );
\dwrSeqbuf_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[18]_i_1_n_0\,
      Q => dwrSeqbuf(18)
    );
\dwrSeqbuf_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[19]_i_1_n_0\,
      Q => dwrSeqbuf(19)
    );
\dwrSeqbuf_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[1]_i_1_n_0\,
      Q => dwrSeqbuf(1)
    );
\dwrSeqbuf_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[20]_i_1_n_0\,
      Q => dwrSeqbuf(20)
    );
\dwrSeqbuf_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[21]_i_1_n_0\,
      Q => dwrSeqbuf(21)
    );
\dwrSeqbuf_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[22]_i_1_n_0\,
      Q => dwrSeqbuf(22)
    );
\dwrSeqbuf_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[23]_i_1_n_0\,
      Q => dwrSeqbuf(23)
    );
\dwrSeqbuf_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[24]_i_1_n_0\,
      Q => dwrSeqbuf(24)
    );
\dwrSeqbuf_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[25]_i_1_n_0\,
      Q => dwrSeqbuf(25)
    );
\dwrSeqbuf_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[26]_i_1_n_0\,
      Q => dwrSeqbuf(26)
    );
\dwrSeqbuf_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[27]_i_1_n_0\,
      Q => dwrSeqbuf(27)
    );
\dwrSeqbuf_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[28]_i_1_n_0\,
      Q => dwrSeqbuf(28)
    );
\dwrSeqbuf_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[29]_i_1_n_0\,
      Q => dwrSeqbuf(29)
    );
\dwrSeqbuf_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[2]_i_1_n_0\,
      Q => dwrSeqbuf(2)
    );
\dwrSeqbuf_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[30]_i_1_n_0\,
      Q => dwrSeqbuf(30)
    );
\dwrSeqbuf_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[31]_i_2_n_0\,
      Q => dwrSeqbuf(31)
    );
\dwrSeqbuf_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[3]_i_1_n_0\,
      Q => dwrSeqbuf(3)
    );
\dwrSeqbuf_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[4]_i_1_n_0\,
      Q => dwrSeqbuf(4)
    );
\dwrSeqbuf_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[5]_i_1_n_0\,
      Q => dwrSeqbuf(5)
    );
\dwrSeqbuf_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[6]_i_1_n_0\,
      Q => dwrSeqbuf(6)
    );
\dwrSeqbuf_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[7]_i_1_n_0\,
      Q => dwrSeqbuf(7)
    );
\dwrSeqbuf_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[8]_i_1_n_0\,
      Q => dwrSeqbuf(8)
    );
\dwrSeqbuf_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \dwrSeqbuf[31]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \dwrSeqbuf[9]_i_1_n_0\,
      Q => dwrSeqbuf(9)
    );
enSeqbuf_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => first,
      O => enSeqbuf
    );
enSeqbuf_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => enSeqbuf,
      Q => enSeqbuf_reg_n_0
    );
first_reg: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      D => first,
      PRE => first_reg_0(0),
      Q => \first__0\
    );
\i[0]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \i_reg_n_0_[0]\,
      O => i(0)
    );
\i[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I1 => \^q\(0),
      I2 => rdySeq,
      I3 => ackSeqbufBToSeqClear,
      I4 => \FSM_onehot_stateSeq[3]_i_1_n_0\,
      O => \i[1]_i_1__1_n_0\
    );
\i[1]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => first,
      O => i(1)
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[1]_i_1__1_n_0\,
      CLR => first_reg_0(0),
      D => i(0),
      Q => \i_reg_n_0_[0]\
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[1]_i_1__1_n_0\,
      CLR => first_reg_0(0),
      D => i(1),
      Q => \i_reg_n_0_[1]\
    );
mySeqbuf: entity work.design_1_Vsp_core_0_0_Dpbram_size4kB_a32b64
     port map (
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(31 downto 0) => dwrSeqbuf(31 downto 0),
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(8) => \aSeqbufB_reg_n_0_[8]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \aSeqbufB_reg_n_0_[7]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \aSeqbufB_reg_n_0_[6]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \aSeqbufB_reg_n_0_[5]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \aSeqbufB_reg_n_0_[4]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \aSeqbufB_reg_n_0_[3]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \aSeqbufB_reg_n_0_[2]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \aSeqbufB_reg_n_0_[1]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \aSeqbufB_reg_n_0_[0]\,
      \DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2 downto 0) => stateSeqbufB_reg(2 downto 0),
      Q(9) => \aSeqbuf_reg_n_0_[9]\,
      Q(8) => \aSeqbuf_reg_n_0_[8]\,
      Q(7) => \aSeqbuf_reg_n_0_[7]\,
      Q(6) => \aSeqbuf_reg_n_0_[6]\,
      Q(5) => \aSeqbuf_reg_n_0_[5]\,
      Q(4) => \aSeqbuf_reg_n_0_[4]\,
      Q(3) => \aSeqbuf_reg_n_0_[3]\,
      Q(2) => \aSeqbuf_reg_n_0_[2]\,
      Q(1) => \aSeqbuf_reg_n_0_[1]\,
      Q(0) => \aSeqbuf_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      doutb(63 downto 0) => doutb(63 downto 0),
      ena => enSeqbuf_reg_n_0
    );
ptr0SeqbufTrackNotFixed_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2F2F2FFF20202000"
    )
        port map (
      I0 => \burstCnt[4]_i_2_n_0\,
      I1 => first,
      I2 => \aSeqbuf[9]_i_3_n_0\,
      I3 => \aSeqbuf[9]_i_4_n_0\,
      I4 => \FSM_onehot_stateSeq[5]_i_5_n_0\,
      I5 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => ptr0SeqbufTrackNotFixed_i_1_n_0
    );
ptr0SeqbufTrackNotFixed_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => first_reg_0(0),
      D => ptr0SeqbufTrackNotFixed_i_1_n_0,
      Q => ptr0SeqbufTrackNotFixed_reg_n_0
    );
\quad[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[0]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(0),
      I4 => first,
      O => quad(0)
    );
\quad[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[10]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(10)
    );
\quad[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[11]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(11)
    );
\quad[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[12]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(4),
      I4 => first,
      O => quad(12)
    );
\quad[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[13]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(5),
      I4 => first,
      O => quad(13)
    );
\quad[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[14]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(6),
      I4 => first,
      O => quad(14)
    );
\quad[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"080808AA"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_6_n_0\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => TCapt,
      O => \quad[15]_i_1_n_0\
    );
\quad[15]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[15]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(15)
    );
\quad[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[16]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(0),
      I4 => first,
      O => quad(16)
    );
\quad[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[17]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(7),
      I4 => first,
      O => quad(17)
    );
\quad[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[18]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(7),
      I4 => first,
      O => quad(18)
    );
\quad[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[19]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(7),
      I4 => first,
      O => quad(19)
    );
\quad[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(1)
    );
\quad[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[20]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(4),
      I4 => first,
      O => quad(20)
    );
\quad[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[21]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(5),
      I4 => first,
      O => quad(21)
    );
\quad[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[22]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(6),
      I4 => first,
      O => quad(22)
    );
\quad[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"080808AA"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_6_n_0\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => \^q\(0),
      I4 => TCapt,
      O => \quad[23]_i_1_n_0\
    );
\quad[23]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[23]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => state(7),
      I4 => first,
      O => quad(23)
    );
\quad[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[24]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(0),
      I4 => first,
      O => quad(24)
    );
\quad[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[25]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(25)
    );
\quad[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[26]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(26)
    );
\quad[27]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[27]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(27)
    );
\quad[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[28]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(4),
      I4 => first,
      O => quad(28)
    );
\quad[29]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[29]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(5),
      I4 => first,
      O => quad(29)
    );
\quad[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[2]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(2)
    );
\quad[30]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[30]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(6),
      I4 => first,
      O => quad(30)
    );
\quad[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EA2A"
    )
        port map (
      I0 => \quad_reg_n_0_[31]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(31)
    );
\quad[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[3]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(3)
    );
\quad[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[4]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(4),
      I4 => first,
      O => quad(4)
    );
\quad[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[5]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(5),
      I4 => first,
      O => quad(5)
    );
\quad[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[6]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(6),
      I4 => first,
      O => quad(6)
    );
\quad[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"020202AA"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[5]_i_6_n_0\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \^q\(0),
      I4 => TCapt,
      O => \quad[7]_i_1_n_0\
    );
\quad[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABA8"
    )
        port map (
      I0 => \quad_reg_n_0_[7]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(7)
    );
\quad[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[8]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(0),
      I4 => first,
      O => quad(8)
    );
\quad[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BA8A"
    )
        port map (
      I0 => \quad_reg_n_0_[9]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[0]\,
      I3 => state(7),
      I4 => first,
      O => quad(9)
    );
\quad_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(0),
      Q => \quad_reg_n_0_[0]\
    );
\quad_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(10),
      Q => \quad_reg_n_0_[10]\
    );
\quad_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(11),
      Q => \quad_reg_n_0_[11]\
    );
\quad_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(12),
      Q => \quad_reg_n_0_[12]\
    );
\quad_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(13),
      Q => \quad_reg_n_0_[13]\
    );
\quad_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(14),
      Q => \quad_reg_n_0_[14]\
    );
\quad_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(15),
      Q => \quad_reg_n_0_[15]\
    );
\quad_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(16),
      Q => \quad_reg_n_0_[16]\
    );
\quad_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(17),
      Q => \quad_reg_n_0_[17]\
    );
\quad_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(18),
      Q => \quad_reg_n_0_[18]\
    );
\quad_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(19),
      Q => \quad_reg_n_0_[19]\
    );
\quad_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(1),
      Q => \quad_reg_n_0_[1]\
    );
\quad_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(20),
      Q => \quad_reg_n_0_[20]\
    );
\quad_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(21),
      Q => \quad_reg_n_0_[21]\
    );
\quad_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(22),
      Q => \quad_reg_n_0_[22]\
    );
\quad_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[23]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(23),
      Q => \quad_reg_n_0_[23]\
    );
\quad_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(24),
      Q => \quad_reg_n_0_[24]\
    );
\quad_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(25),
      Q => \quad_reg_n_0_[25]\
    );
\quad_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(26),
      Q => \quad_reg_n_0_[26]\
    );
\quad_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(27),
      Q => \quad_reg_n_0_[27]\
    );
\quad_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(28),
      Q => \quad_reg_n_0_[28]\
    );
\quad_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(29),
      Q => \quad_reg_n_0_[29]\
    );
\quad_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(2),
      Q => \quad_reg_n_0_[2]\
    );
\quad_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(30),
      Q => \quad_reg_n_0_[30]\
    );
\quad_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \burstCnt[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(31),
      Q => \quad_reg_n_0_[31]\
    );
\quad_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(3),
      Q => \quad_reg_n_0_[3]\
    );
\quad_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(4),
      Q => \quad_reg_n_0_[4]\
    );
\quad_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(5),
      Q => \quad_reg_n_0_[5]\
    );
\quad_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(6),
      Q => \quad_reg_n_0_[6]\
    );
\quad_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[7]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(7),
      Q => \quad_reg_n_0_[7]\
    );
\quad_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(8),
      Q => \quad_reg_n_0_[8]\
    );
\quad_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \quad[15]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => quad(9),
      Q => \quad_reg_n_0_[9]\
    );
restart_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFCFFFF00100010"
    )
        port map (
      I0 => restart_i_2_n_0,
      I1 => stateOp(1),
      I2 => stateOp(0),
      I3 => stateOp(2),
      I4 => restart_reg_0,
      I5 => restart_reg_n_0,
      O => restart_i_1_n_0
    );
restart_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D0DD"
    )
        port map (
      I0 => \^ackinvvidtrackselect\,
      I1 => reqInvVidtrackSelect,
      I2 => reqInvVidtrackSet,
      I3 => \^ackinvvidtrackset\,
      O => restart_i_2_n_0
    );
restart_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => first_reg_0(0),
      D => restart_i_1_n_0,
      Q => restart_reg_n_0
    );
\retbuf[0][0]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"24"
    )
        port map (
      I0 => stateOp(0),
      I1 => stateOp(1),
      I2 => stateOp(2),
      O => \^vidtrackgetinfotixvstate\(0)
    );
\retbuf[5][0]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[8]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => vidtrackGetInfoPtr0Seqbuf(8)
    );
\retbuf[5][1]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[9]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => vidtrackGetInfoPtr0Seqbuf(9)
    );
\retbuf[6][0]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[0]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => vidtrackGetInfoPtr0Seqbuf(0)
    );
\retbuf[6][1]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[1]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => vidtrackGetInfoPtr0Seqbuf(1)
    );
\retbuf[6][2]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[2]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => vidtrackGetInfoPtr0Seqbuf(2)
    );
\retbuf[6][3]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[3]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => vidtrackGetInfoPtr0Seqbuf(3)
    );
\retbuf[6][4]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[4]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => vidtrackGetInfoPtr0Seqbuf(4)
    );
\retbuf[6][5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[5]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => vidtrackGetInfoPtr0Seqbuf(5)
    );
\retbuf[6][6]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[6]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => vidtrackGetInfoPtr0Seqbuf(6)
    );
\retbuf[6][7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \aSeqbuf_reg_n_0_[7]\,
      I1 => ptr0SeqbufTrackNotFixed_reg_n_0,
      O => vidtrackGetInfoPtr0Seqbuf(7)
    );
rng_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => TCaptMax,
      CLR => first_reg_0(0),
      D => hdrNotFix,
      Q => rng_reg_n_0
    );
\staTixVTrigger[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA8A"
    )
        port map (
      I0 => reqInvVidtrackSelect,
      I1 => stateOp(1),
      I2 => stateOp(0),
      I3 => stateOp(2),
      O => staFallingNotRising
    );
\staTixVTrigger_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(16),
      Q => staTixVTrigger(0)
    );
\staTixVTrigger_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(17),
      Q => staTixVTrigger(1)
    );
\staTixVTrigger_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(18),
      Q => staTixVTrigger(2)
    );
\staTixVTrigger_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(19),
      Q => staTixVTrigger(3)
    );
\staTixVTrigger_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(20),
      Q => staTixVTrigger(4)
    );
\staTixVTrigger_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(21),
      Q => staTixVTrigger(5)
    );
\staTixVTrigger_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(22),
      Q => staTixVTrigger(6)
    );
\staTixVTrigger_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(23),
      Q => staTixVTrigger(7)
    );
\stateOp[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEFEFFE"
    )
        port map (
      I0 => reqInvVidtrackSelect,
      I1 => reqInvVidtrackSet,
      I2 => stateOp(0),
      I3 => stateOp(1),
      I4 => stateOp(2),
      O => \stateOp[0]_i_1__0_n_0\
    );
\stateOp[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C0000C8000000C8"
    )
        port map (
      I0 => rng_reg_n_0,
      I1 => restart_reg_0,
      I2 => stateOp(1),
      I3 => stateOp(0),
      I4 => stateOp(2),
      I5 => restart_reg_n_0,
      O => \stateOp[1]_i_1__0_n_0\
    );
\stateOp[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFB000000"
    )
        port map (
      I0 => rdySeq,
      I1 => stateOp(0),
      I2 => restart_reg_n_0,
      I3 => \^vidtrackgetinfotixvstate\(1),
      I4 => \stateOp[2]_i_4__0_n_0\,
      I5 => \stateOp[2]_i_5_n_0\,
      O => \stateOp[2]_i_1_n_0\
    );
\stateOp[2]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \stateOp[2]_i_31_n_0\,
      I1 => \TCaptMax_reg_n_0_[17]\,
      I2 => \TCaptMax_reg_n_0_[16]\,
      I3 => \TCaptMax_reg_n_0_[19]\,
      I4 => \TCaptMax_reg_n_0_[18]\,
      I5 => \stateOp[2]_i_32_n_0\,
      O => \stateOp[2]_i_10_n_0\
    );
\stateOp[2]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \stateOp[2]_i_33_n_0\,
      I1 => \TCaptMax_reg_n_0_[2]\,
      I2 => \TCaptMax_reg_n_0_[1]\,
      I3 => \TCaptMax_reg_n_0_[3]\,
      I4 => \TCaptMax_reg_n_0_[0]\,
      I5 => \stateOp[2]_i_34_n_0\,
      O => \stateOp[2]_i_11_n_0\
    );
\stateOp[2]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040000000"
    )
        port map (
      I0 => \stateOp[2]_i_35_n_0\,
      I1 => \^tcapt_reg[31]_0\(30),
      I2 => \^tcapt_reg[31]_0\(29),
      I3 => \^tcapt_reg[31]_0\(31),
      I4 => \^tcapt_reg[31]_0\(28),
      I5 => \stateOp[2]_i_36_n_0\,
      O => \stateOp[2]_i_12_n_0\
    );
\stateOp[2]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => staTixVTrigger(5),
      I1 => staTixVTrigger(3),
      I2 => staTixVTrigger(7),
      I3 => staTixVTrigger(6),
      I4 => staTixVTrigger(4),
      O => \stateOp[2]_i_13_n_0\
    );
\stateOp[2]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(31),
      I1 => \TCaptMax_reg_n_0_[31]\,
      I2 => \^tcapt_reg[31]_0\(30),
      I3 => \TCaptMax_reg_n_0_[30]\,
      O => \stateOp[2]_i_15_n_0\
    );
\stateOp[2]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(29),
      I1 => \TCaptMax_reg_n_0_[29]\,
      I2 => \^tcapt_reg[31]_0\(28),
      I3 => \TCaptMax_reg_n_0_[28]\,
      O => \stateOp[2]_i_16_n_0\
    );
\stateOp[2]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(27),
      I1 => \TCaptMax_reg_n_0_[27]\,
      I2 => \^tcapt_reg[31]_0\(26),
      I3 => \TCaptMax_reg_n_0_[26]\,
      O => \stateOp[2]_i_17_n_0\
    );
\stateOp[2]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(25),
      I1 => \TCaptMax_reg_n_0_[25]\,
      I2 => \^tcapt_reg[31]_0\(24),
      I3 => \TCaptMax_reg_n_0_[24]\,
      O => \stateOp[2]_i_18_n_0\
    );
\stateOp[2]_i_19\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(23),
      I1 => \TCaptMax_reg_n_0_[23]\,
      I2 => \^tcapt_reg[31]_0\(22),
      I3 => \TCaptMax_reg_n_0_[22]\,
      O => \stateOp[2]_i_19_n_0\
    );
\stateOp[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00300030003030BC"
    )
        port map (
      I0 => restart_reg_n_0,
      I1 => stateOp(2),
      I2 => stateOp(0),
      I3 => stateOp(1),
      I4 => reqInvVidtrackSet,
      I5 => reqInvVidtrackSelect,
      O => \stateOp[2]_i_2_n_0\
    );
\stateOp[2]_i_20\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(21),
      I1 => \TCaptMax_reg_n_0_[21]\,
      I2 => \^tcapt_reg[31]_0\(20),
      I3 => \TCaptMax_reg_n_0_[20]\,
      O => \stateOp[2]_i_20_n_0\
    );
\stateOp[2]_i_21\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(19),
      I1 => \TCaptMax_reg_n_0_[19]\,
      I2 => \^tcapt_reg[31]_0\(18),
      I3 => \TCaptMax_reg_n_0_[18]\,
      O => \stateOp[2]_i_21_n_0\
    );
\stateOp[2]_i_22\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(17),
      I1 => \TCaptMax_reg_n_0_[17]\,
      I2 => \^tcapt_reg[31]_0\(16),
      I3 => \TCaptMax_reg_n_0_[16]\,
      O => \stateOp[2]_i_22_n_0\
    );
\stateOp[2]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[31]\,
      I1 => \^tcapt_reg[31]_0\(31),
      I2 => \TCaptMax_reg_n_0_[30]\,
      I3 => \^tcapt_reg[31]_0\(30),
      O => \stateOp[2]_i_23_n_0\
    );
\stateOp[2]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[29]\,
      I1 => \^tcapt_reg[31]_0\(29),
      I2 => \TCaptMax_reg_n_0_[28]\,
      I3 => \^tcapt_reg[31]_0\(28),
      O => \stateOp[2]_i_24_n_0\
    );
\stateOp[2]_i_25\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[27]\,
      I1 => \^tcapt_reg[31]_0\(27),
      I2 => \TCaptMax_reg_n_0_[26]\,
      I3 => \^tcapt_reg[31]_0\(26),
      O => \stateOp[2]_i_25_n_0\
    );
\stateOp[2]_i_26\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[25]\,
      I1 => \^tcapt_reg[31]_0\(25),
      I2 => \TCaptMax_reg_n_0_[24]\,
      I3 => \^tcapt_reg[31]_0\(24),
      O => \stateOp[2]_i_26_n_0\
    );
\stateOp[2]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[23]\,
      I1 => \^tcapt_reg[31]_0\(23),
      I2 => \TCaptMax_reg_n_0_[22]\,
      I3 => \^tcapt_reg[31]_0\(22),
      O => \stateOp[2]_i_27_n_0\
    );
\stateOp[2]_i_28\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[21]\,
      I1 => \^tcapt_reg[31]_0\(21),
      I2 => \TCaptMax_reg_n_0_[20]\,
      I3 => \^tcapt_reg[31]_0\(20),
      O => \stateOp[2]_i_28_n_0\
    );
\stateOp[2]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[19]\,
      I1 => \^tcapt_reg[31]_0\(19),
      I2 => \TCaptMax_reg_n_0_[18]\,
      I3 => \^tcapt_reg[31]_0\(18),
      O => \stateOp[2]_i_29_n_0\
    );
\stateOp[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => stateOp(2),
      I1 => stateOp(1),
      O => \^vidtrackgetinfotixvstate\(1)
    );
\stateOp[2]_i_30\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[17]\,
      I1 => \^tcapt_reg[31]_0\(17),
      I2 => \TCaptMax_reg_n_0_[16]\,
      I3 => \^tcapt_reg[31]_0\(16),
      O => \stateOp[2]_i_30_n_0\
    );
\stateOp[2]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[21]\,
      I1 => \TCaptMax_reg_n_0_[20]\,
      I2 => \TCaptMax_reg_n_0_[23]\,
      I3 => \TCaptMax_reg_n_0_[22]\,
      O => \stateOp[2]_i_31_n_0\
    );
\stateOp[2]_i_32\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[26]\,
      I1 => \TCaptMax_reg_n_0_[27]\,
      I2 => \TCaptMax_reg_n_0_[24]\,
      I3 => \TCaptMax_reg_n_0_[25]\,
      I4 => \stateOp[2]_i_53_n_0\,
      O => \stateOp[2]_i_32_n_0\
    );
\stateOp[2]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[6]\,
      I1 => \TCaptMax_reg_n_0_[5]\,
      I2 => \TCaptMax_reg_n_0_[7]\,
      I3 => \TCaptMax_reg_n_0_[4]\,
      O => \stateOp[2]_i_33_n_0\
    );
\stateOp[2]_i_34\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[8]\,
      I1 => \TCaptMax_reg_n_0_[9]\,
      I2 => \TCaptMax_reg_n_0_[10]\,
      I3 => \TCaptMax_reg_n_0_[11]\,
      I4 => \stateOp[2]_i_54_n_0\,
      O => \stateOp[2]_i_34_n_0\
    );
\stateOp[2]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(27),
      I1 => \^tcapt_reg[31]_0\(26),
      I2 => \^tcapt_reg[31]_0\(25),
      I3 => \^tcapt_reg[31]_0\(24),
      O => \stateOp[2]_i_35_n_0\
    );
\stateOp[2]_i_36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBFFFFFFF"
    )
        port map (
      I0 => \stateOp[2]_i_55_n_0\,
      I1 => \^tcapt_reg[31]_0\(14),
      I2 => \^tcapt_reg[31]_0\(13),
      I3 => \^tcapt_reg[31]_0\(15),
      I4 => \^tcapt_reg[31]_0\(12),
      I5 => \stateOp[2]_i_56_n_0\,
      O => \stateOp[2]_i_36_n_0\
    );
\stateOp[2]_i_37\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(15),
      I1 => \TCaptMax_reg_n_0_[15]\,
      I2 => \^tcapt_reg[31]_0\(14),
      I3 => \TCaptMax_reg_n_0_[14]\,
      O => \stateOp[2]_i_37_n_0\
    );
\stateOp[2]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(13),
      I1 => \TCaptMax_reg_n_0_[13]\,
      I2 => \^tcapt_reg[31]_0\(12),
      I3 => \TCaptMax_reg_n_0_[12]\,
      O => \stateOp[2]_i_38_n_0\
    );
\stateOp[2]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(11),
      I1 => \TCaptMax_reg_n_0_[11]\,
      I2 => \^tcapt_reg[31]_0\(10),
      I3 => \TCaptMax_reg_n_0_[10]\,
      O => \stateOp[2]_i_39_n_0\
    );
\stateOp[2]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(9),
      I1 => \TCaptMax_reg_n_0_[9]\,
      I2 => \^tcapt_reg[31]_0\(8),
      I3 => \TCaptMax_reg_n_0_[8]\,
      O => \stateOp[2]_i_40_n_0\
    );
\stateOp[2]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(7),
      I1 => \TCaptMax_reg_n_0_[7]\,
      I2 => \^tcapt_reg[31]_0\(6),
      I3 => \TCaptMax_reg_n_0_[6]\,
      O => \stateOp[2]_i_41_n_0\
    );
\stateOp[2]_i_42\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(5),
      I1 => \TCaptMax_reg_n_0_[5]\,
      I2 => \^tcapt_reg[31]_0\(4),
      I3 => \TCaptMax_reg_n_0_[4]\,
      O => \stateOp[2]_i_42_n_0\
    );
\stateOp[2]_i_43\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(3),
      I1 => \TCaptMax_reg_n_0_[3]\,
      I2 => \^tcapt_reg[31]_0\(2),
      I3 => \TCaptMax_reg_n_0_[2]\,
      O => \stateOp[2]_i_43_n_0\
    );
\stateOp[2]_i_44\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(1),
      I1 => \TCaptMax_reg_n_0_[1]\,
      I2 => \^tcapt_reg[31]_0\(0),
      I3 => \TCaptMax_reg_n_0_[0]\,
      O => \stateOp[2]_i_44_n_0\
    );
\stateOp[2]_i_45\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[15]\,
      I1 => \^tcapt_reg[31]_0\(15),
      I2 => \TCaptMax_reg_n_0_[14]\,
      I3 => \^tcapt_reg[31]_0\(14),
      O => \stateOp[2]_i_45_n_0\
    );
\stateOp[2]_i_46\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[13]\,
      I1 => \^tcapt_reg[31]_0\(13),
      I2 => \TCaptMax_reg_n_0_[12]\,
      I3 => \^tcapt_reg[31]_0\(12),
      O => \stateOp[2]_i_46_n_0\
    );
\stateOp[2]_i_47\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[11]\,
      I1 => \^tcapt_reg[31]_0\(11),
      I2 => \TCaptMax_reg_n_0_[10]\,
      I3 => \^tcapt_reg[31]_0\(10),
      O => \stateOp[2]_i_47_n_0\
    );
\stateOp[2]_i_48\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[9]\,
      I1 => \^tcapt_reg[31]_0\(9),
      I2 => \TCaptMax_reg_n_0_[8]\,
      I3 => \^tcapt_reg[31]_0\(8),
      O => \stateOp[2]_i_48_n_0\
    );
\stateOp[2]_i_49\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[7]\,
      I1 => \^tcapt_reg[31]_0\(7),
      I2 => \TCaptMax_reg_n_0_[6]\,
      I3 => \^tcapt_reg[31]_0\(6),
      O => \stateOp[2]_i_49_n_0\
    );
\stateOp[2]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => stateOp(0),
      I1 => \stateOp[2]_i_6_n_0\,
      O => \stateOp[2]_i_4__0_n_0\
    );
\stateOp[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0F020000"
    )
        port map (
      I0 => stateOp(0),
      I1 => restart_i_2_n_0,
      I2 => stateOp(2),
      I3 => stateOp(1),
      I4 => \stateOp[2]_i_7__0_n_0\,
      I5 => \stateOp[2]_i_8_n_0\,
      O => \stateOp[2]_i_5_n_0\
    );
\stateOp[2]_i_50\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[5]\,
      I1 => \^tcapt_reg[31]_0\(5),
      I2 => \TCaptMax_reg_n_0_[4]\,
      I3 => \^tcapt_reg[31]_0\(4),
      O => \stateOp[2]_i_50_n_0\
    );
\stateOp[2]_i_51\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[3]\,
      I1 => \^tcapt_reg[31]_0\(3),
      I2 => \TCaptMax_reg_n_0_[2]\,
      I3 => \^tcapt_reg[31]_0\(2),
      O => \stateOp[2]_i_51_n_0\
    );
\stateOp[2]_i_52\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[1]\,
      I1 => \^tcapt_reg[31]_0\(1),
      I2 => \TCaptMax_reg_n_0_[0]\,
      I3 => \^tcapt_reg[31]_0\(0),
      O => \stateOp[2]_i_52_n_0\
    );
\stateOp[2]_i_53\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[30]\,
      I1 => \TCaptMax_reg_n_0_[29]\,
      I2 => \TCaptMax_reg_n_0_[31]\,
      I3 => \TCaptMax_reg_n_0_[28]\,
      O => \stateOp[2]_i_53_n_0\
    );
\stateOp[2]_i_54\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \TCaptMax_reg_n_0_[13]\,
      I1 => \TCaptMax_reg_n_0_[12]\,
      I2 => \TCaptMax_reg_n_0_[15]\,
      I3 => \TCaptMax_reg_n_0_[14]\,
      O => \stateOp[2]_i_54_n_0\
    );
\stateOp[2]_i_55\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(11),
      I1 => \^tcapt_reg[31]_0\(10),
      I2 => \^tcapt_reg[31]_0\(9),
      I3 => \^tcapt_reg[31]_0\(8),
      O => \stateOp[2]_i_55_n_0\
    );
\stateOp[2]_i_56\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(20),
      I1 => \^tcapt_reg[31]_0\(21),
      I2 => \^tcapt_reg[31]_0\(22),
      I3 => \^tcapt_reg[31]_0\(23),
      I4 => \stateOp[2]_i_57_n_0\,
      O => \stateOp[2]_i_56_n_0\
    );
\stateOp[2]_i_57\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^tcapt_reg[31]_0\(18),
      I1 => \^tcapt_reg[31]_0\(17),
      I2 => \^tcapt_reg[31]_0\(19),
      I3 => \^tcapt_reg[31]_0\(16),
      O => \stateOp[2]_i_57_n_0\
    );
\stateOp[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000ABABFFAB"
    )
        port map (
      I0 => \FSM_onehot_stateSeq[3]_i_3_n_0\,
      I1 => \stateOp_reg[2]_i_9_n_0\,
      I2 => \^q\(0),
      I3 => \stateOp[2]_i_10_n_0\,
      I4 => \stateOp[2]_i_11_n_0\,
      I5 => \stateOp[2]_i_12_n_0\,
      O => \stateOp[2]_i_6_n_0\
    );
\stateOp[2]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABAAAA"
    )
        port map (
      I0 => stateOp(0),
      I1 => staTixVTrigger(2),
      I2 => staTixVTrigger(1),
      I3 => staTixVTrigger(0),
      I4 => \stateOp[2]_i_13_n_0\,
      O => \stateOp[2]_i_7__0_n_0\
    );
\stateOp[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEE0FEEEEEE0F"
    )
        port map (
      I0 => reqInvVidtrackSet,
      I1 => reqInvVidtrackSelect,
      I2 => stateOp(0),
      I3 => stateOp(2),
      I4 => stateOp(1),
      I5 => rdySeq,
      O => \stateOp[2]_i_8_n_0\
    );
\stateOp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[2]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \stateOp[0]_i_1__0_n_0\,
      Q => stateOp(0)
    );
\stateOp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[2]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \stateOp[1]_i_1__0_n_0\,
      Q => stateOp(1)
    );
\stateOp_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateOp[2]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \stateOp[2]_i_2_n_0\,
      Q => stateOp(2)
    );
\stateOp_reg[2]_i_14\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \stateOp_reg[2]_i_14_n_0\,
      CO(6) => \stateOp_reg[2]_i_14_n_1\,
      CO(5) => \stateOp_reg[2]_i_14_n_2\,
      CO(4) => \stateOp_reg[2]_i_14_n_3\,
      CO(3) => \stateOp_reg[2]_i_14_n_4\,
      CO(2) => \stateOp_reg[2]_i_14_n_5\,
      CO(1) => \stateOp_reg[2]_i_14_n_6\,
      CO(0) => \stateOp_reg[2]_i_14_n_7\,
      DI(7) => \stateOp[2]_i_37_n_0\,
      DI(6) => \stateOp[2]_i_38_n_0\,
      DI(5) => \stateOp[2]_i_39_n_0\,
      DI(4) => \stateOp[2]_i_40_n_0\,
      DI(3) => \stateOp[2]_i_41_n_0\,
      DI(2) => \stateOp[2]_i_42_n_0\,
      DI(1) => \stateOp[2]_i_43_n_0\,
      DI(0) => \stateOp[2]_i_44_n_0\,
      O(7 downto 0) => \NLW_stateOp_reg[2]_i_14_O_UNCONNECTED\(7 downto 0),
      S(7) => \stateOp[2]_i_45_n_0\,
      S(6) => \stateOp[2]_i_46_n_0\,
      S(5) => \stateOp[2]_i_47_n_0\,
      S(4) => \stateOp[2]_i_48_n_0\,
      S(3) => \stateOp[2]_i_49_n_0\,
      S(2) => \stateOp[2]_i_50_n_0\,
      S(1) => \stateOp[2]_i_51_n_0\,
      S(0) => \stateOp[2]_i_52_n_0\
    );
\stateOp_reg[2]_i_9\: unisim.vcomponents.CARRY8
     port map (
      CI => \stateOp_reg[2]_i_14_n_0\,
      CI_TOP => '0',
      CO(7) => \stateOp_reg[2]_i_9_n_0\,
      CO(6) => \stateOp_reg[2]_i_9_n_1\,
      CO(5) => \stateOp_reg[2]_i_9_n_2\,
      CO(4) => \stateOp_reg[2]_i_9_n_3\,
      CO(3) => \stateOp_reg[2]_i_9_n_4\,
      CO(2) => \stateOp_reg[2]_i_9_n_5\,
      CO(1) => \stateOp_reg[2]_i_9_n_6\,
      CO(0) => \stateOp_reg[2]_i_9_n_7\,
      DI(7) => \stateOp[2]_i_15_n_0\,
      DI(6) => \stateOp[2]_i_16_n_0\,
      DI(5) => \stateOp[2]_i_17_n_0\,
      DI(4) => \stateOp[2]_i_18_n_0\,
      DI(3) => \stateOp[2]_i_19_n_0\,
      DI(2) => \stateOp[2]_i_20_n_0\,
      DI(1) => \stateOp[2]_i_21_n_0\,
      DI(0) => \stateOp[2]_i_22_n_0\,
      O(7 downto 0) => \NLW_stateOp_reg[2]_i_9_O_UNCONNECTED\(7 downto 0),
      S(7) => \stateOp[2]_i_23_n_0\,
      S(6) => \stateOp[2]_i_24_n_0\,
      S(5) => \stateOp[2]_i_25_n_0\,
      S(4) => \stateOp[2]_i_26_n_0\,
      S(3) => \stateOp[2]_i_27_n_0\,
      S(2) => \stateOp[2]_i_28_n_0\,
      S(1) => \stateOp[2]_i_29_n_0\,
      S(0) => \stateOp[2]_i_30_n_0\
    );
\stateSeqbufB[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0705"
    )
        port map (
      I0 => stateSeqbufB_reg(2),
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      I3 => dneSeqbufVidtrackToHostif,
      O => \p_0_in__0\(0)
    );
\stateSeqbufB[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00BC"
    )
        port map (
      I0 => \stateSeqbufB[1]_i_2_n_0\,
      I1 => stateSeqbufB_reg(1),
      I2 => stateSeqbufB_reg(0),
      I3 => stateSeqbufB_reg(2),
      O => \p_0_in__0\(1)
    );
\stateSeqbufB[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAAAAAA"
    )
        port map (
      I0 => seqbufVidtrackToHostifAXIS_tready,
      I1 => \aSeqbufB_reg_n_0_[7]\,
      I2 => \aSeqbufB_reg_n_0_[6]\,
      I3 => \aSeqbufB[8]_i_4_n_0\,
      I4 => \aSeqbufB_reg_n_0_[8]\,
      O => \stateSeqbufB[1]_i_2_n_0\
    );
\stateSeqbufB[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBABBABBBBABB"
    )
        port map (
      I0 => \stateSeqbufB[2]_i_3_n_0\,
      I1 => stateSeqbufB_reg(2),
      I2 => reqSeqbufVidtrackToHostif,
      I3 => stateSeqbufB_reg(0),
      I4 => stateSeqbufB_reg(1),
      I5 => seqbufVidtrackToHostifAXIS_tready,
      O => \stateSeqbufB[2]_i_1_n_0\
    );
\stateSeqbufB[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000AC000000A0000"
    )
        port map (
      I0 => dneSeqbufVidtrackToHostif,
      I1 => \stateSeqbufB[2]_i_7_n_0\,
      I2 => stateSeqbufB_reg(1),
      I3 => stateSeqbufB_reg(0),
      I4 => stateSeqbufB_reg(2),
      I5 => seqbufVidtrackToHostifAXIS_tready,
      O => \p_0_in__0\(2)
    );
\stateSeqbufB[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000C088CC"
    )
        port map (
      I0 => dneSeqbufVidtrackToHostif,
      I1 => stateSeqbufB_reg(2),
      I2 => ackSeqbufBToSeqClear,
      I3 => reqSeqbufVidtrackToHostif,
      I4 => stateSeqbufB_reg(0),
      I5 => stateSeqbufB_reg(1),
      O => \stateSeqbufB[2]_i_3_n_0\
    );
\stateSeqbufB[2]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \aSeqbufB_reg_n_0_[8]\,
      I1 => \aSeqbufB[8]_i_4_n_0\,
      I2 => \aSeqbufB_reg_n_0_[6]\,
      I3 => \aSeqbufB_reg_n_0_[7]\,
      O => \stateSeqbufB[2]_i_7_n_0\
    );
\stateSeqbufB_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSeqbufB[2]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \p_0_in__0\(0),
      Q => stateSeqbufB_reg(0)
    );
\stateSeqbufB_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSeqbufB[2]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \p_0_in__0\(1),
      Q => stateSeqbufB_reg(1)
    );
\stateSeqbufB_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSeqbufB[2]_i_1_n_0\,
      CLR => first_reg_0(0),
      D => \p_0_in__0\(2),
      Q => stateSeqbufB_reg(2)
    );
\state[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFBCBF9C9"
    )
        port map (
      I0 => \^tixvcapture_reg[1]_0\(0),
      I1 => \tixVCapture_reg_n_0_[2]\,
      I2 => \^tixvcapture_reg[1]_0\(1),
      I3 => \state_reg[0]_0\,
      I4 => videoinStateIgr_dbg(0),
      I5 => \state[7]_i_4_n_0\,
      O => \state[0]_i_1_n_0\
    );
\state[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \state[4]_i_2_n_0\,
      I1 => \tixVCapture_reg_n_0_[5]\,
      I2 => \tixVCapture_reg_n_0_[6]\,
      I3 => \tixVCapture_reg_n_0_[3]\,
      I4 => \tixVCapture_reg_n_0_[4]\,
      I5 => \tixVCapture_reg_n_0_[7]\,
      O => \state[4]_i_1_n_0\
    );
\state[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCAFFCFFFCAF0CF"
    )
        port map (
      I0 => videoinStateIgr_dbg(1),
      I1 => \state_reg[4]_0\,
      I2 => \^tixvcapture_reg[1]_0\(1),
      I3 => \tixVCapture_reg_n_0_[2]\,
      I4 => \^tixvcapture_reg[1]_0\(0),
      I5 => \state_reg[5]_0\(0),
      O => \state[4]_i_2_n_0\
    );
\state[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEFF0E0"
    )
        port map (
      I0 => \state_reg[5]_0\(1),
      I1 => \^tixvcapture_reg[1]_0\(0),
      I2 => \tixVCapture_reg_n_0_[2]\,
      I3 => \^tixvcapture_reg[1]_0\(1),
      I4 => \state_reg[5]_1\,
      I5 => \state[7]_i_4_n_0\,
      O => \state[5]_i_1_n_0\
    );
\state[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF9D9E9C9"
    )
        port map (
      I0 => \^tixvcapture_reg[1]_0\(0),
      I1 => \tixVCapture_reg_n_0_[2]\,
      I2 => \^tixvcapture_reg[1]_0\(1),
      I3 => \state_reg[7]_0\(0),
      I4 => videoinStateRgbegr_dbg(0),
      I5 => \state[7]_i_4_n_0\,
      O => \state[6]_i_1_n_0\
    );
\state[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF9D9E9C9"
    )
        port map (
      I0 => \^tixvcapture_reg[1]_0\(0),
      I1 => \tixVCapture_reg_n_0_[2]\,
      I2 => \^tixvcapture_reg[1]_0\(1),
      I3 => \state_reg[7]_0\(0),
      I4 => videoinStateRgbegr_dbg(1),
      I5 => \state[7]_i_4_n_0\,
      O => \state[7]_i_1_n_0\
    );
\state[7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \tixVCapture_reg_n_0_[7]\,
      I1 => \tixVCapture_reg_n_0_[4]\,
      I2 => \tixVCapture_reg_n_0_[3]\,
      I3 => \tixVCapture_reg_n_0_[6]\,
      I4 => \tixVCapture_reg_n_0_[5]\,
      O => \state[7]_i_4_n_0\
    );
\state_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \state[0]_i_1_n_0\,
      PRE => first_reg_0(0),
      Q => state(0)
    );
\state_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \state[4]_i_1_n_0\,
      PRE => first_reg_0(0),
      Q => state(4)
    );
\state_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \state[5]_i_1_n_0\,
      PRE => first_reg_0(0),
      Q => state(5)
    );
\state_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \state[6]_i_1_n_0\,
      PRE => first_reg_0(0),
      Q => state(6)
    );
\state_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => \state[7]_i_1_n_0\,
      PRE => first_reg_0(0),
      Q => state(7)
    );
\stoTixVTrigger_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(0),
      Q => stoTixVTrigger(0)
    );
\stoTixVTrigger_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(1),
      Q => stoTixVTrigger(1)
    );
\stoTixVTrigger_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(2),
      Q => stoTixVTrigger(2)
    );
\stoTixVTrigger_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(3),
      Q => stoTixVTrigger(3)
    );
\stoTixVTrigger_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(4),
      Q => stoTixVTrigger(4)
    );
\stoTixVTrigger_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(5),
      Q => stoTixVTrigger(5)
    );
\stoTixVTrigger_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(6),
      Q => stoTixVTrigger(6)
    );
\stoTixVTrigger_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => D(7),
      Q => stoTixVTrigger(7)
    );
stop_lcl_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAAB"
    )
        port map (
      I0 => TCapt,
      I1 => \FSM_onehot_stateSeq_reg_n_0_[4]\,
      I2 => \^q\(0),
      I3 => rdySeq,
      I4 => ackSeqbufBToSeqClear,
      O => stop_lcl_i_1_n_0
    );
stop_lcl_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => first,
      I1 => \FSM_onehot_stateSeq[3]_i_2_n_0\,
      O => stop_lcl_i_2_n_0
    );
stop_lcl_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stop_lcl_i_1_n_0,
      CLR => first_reg_0(0),
      D => stop_lcl_i_2_n_0,
      Q => stop_lcl_reg_n_0
    );
strbStop_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEFEFE0EEE0E0"
    )
        port map (
      I0 => strbStop_i_2_n_0,
      I1 => strbStop_i_3_n_0,
      I2 => strbStop_i_4_n_0,
      I3 => strbStop_i_5_n_0,
      I4 => \stateOp[2]_i_4__0_n_0\,
      I5 => strbStop_reg_n_0,
      O => strbStop_i_1_n_0
    );
strbStop_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08AA0808"
    )
        port map (
      I0 => ackInvSelect_sig_i_2_n_0,
      I1 => \^ackinvvidtrackset\,
      I2 => reqInvVidtrackSet,
      I3 => reqInvVidtrackSelect,
      I4 => \^ackinvvidtrackselect\,
      O => strbStop_i_2_n_0
    );
strbStop_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => reqInvVidtrackSelect,
      I1 => reqInvVidtrackSet,
      I2 => stateOp(1),
      I3 => stateOp(0),
      I4 => stateOp(2),
      I5 => \stateOp[2]_i_6_n_0\,
      O => strbStop_i_3_n_0
    );
strbStop_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEE0EF"
    )
        port map (
      I0 => reqInvVidtrackSelect,
      I1 => reqInvVidtrackSet,
      I2 => stateOp(1),
      I3 => stateOp(0),
      I4 => stateOp(2),
      O => strbStop_i_4_n_0
    );
strbStop_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF45"
    )
        port map (
      I0 => stateOp(2),
      I1 => restart_i_2_n_0,
      I2 => stateOp(0),
      I3 => stateOp(1),
      O => strbStop_i_5_n_0
    );
strbStop_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => first_reg_0(0),
      D => strbStop_i_1_n_0,
      Q => strbStop_reg_n_0
    );
\tixVCapture_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      D => \tixVCapture_reg[7]_0\(0),
      PRE => first_reg_0(0),
      Q => \^tixvcapture_reg[1]_0\(0)
    );
\tixVCapture_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => \tixVCapture_reg[7]_0\(1),
      Q => \^tixvcapture_reg[1]_0\(1)
    );
\tixVCapture_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => \tixVCapture_reg[7]_0\(2),
      Q => \tixVCapture_reg_n_0_[2]\
    );
\tixVCapture_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => \tixVCapture_reg[7]_0\(3),
      Q => \tixVCapture_reg_n_0_[3]\
    );
\tixVCapture_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => \tixVCapture_reg[7]_0\(4),
      Q => \tixVCapture_reg_n_0_[4]\
    );
\tixVCapture_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => \tixVCapture_reg[7]_0\(5),
      Q => \tixVCapture_reg_n_0_[5]\
    );
\tixVCapture_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => \tixVCapture_reg[7]_0\(6),
      Q => \tixVCapture_reg_n_0_[6]\
    );
\tixVCapture_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => staFallingNotRising,
      CLR => first_reg_0(0),
      D => \tixVCapture_reg[7]_0\(7),
      Q => \tixVCapture_reg_n_0_[7]\
    );
\txAXIS_tdata[15]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => stateSeqbufB_reg(2),
      I1 => stateSeqbufB_reg(0),
      I2 => stateSeqbufB_reg(1),
      O => seqbufVidtrackToHostifAXIS_tvalid
    );
\wordcntLast[28]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"34"
    )
        port map (
      I0 => stateSeqbufB_reg(0),
      I1 => stateSeqbufB_reg(2),
      I2 => stateSeqbufB_reg(1),
      O => ackSeqbufVidtrackToHostif
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_phy_0_core is
  port (
    core_clk : in STD_LOGIC;
    core_rst : in STD_LOGIC;
    rxbyteclkhs : out STD_LOGIC;
    clkoutphy_out : out STD_LOGIC;
    pll_lock_out : out STD_LOGIC;
    system_rst_out : out STD_LOGIC;
    init_done : out STD_LOGIC;
    cl_rxclkactivehs : out STD_LOGIC;
    cl_stopstate : out STD_LOGIC;
    cl_enable : in STD_LOGIC;
    cl_rxulpsclknot : out STD_LOGIC;
    cl_ulpsactivenot : out STD_LOGIC;
    dl0_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl0_rxvalidhs : out STD_LOGIC;
    dl0_rxactivehs : out STD_LOGIC;
    dl0_rxsynchs : out STD_LOGIC;
    dl0_forcerxmode : in STD_LOGIC;
    dl0_stopstate : out STD_LOGIC;
    dl0_enable : in STD_LOGIC;
    dl0_ulpsactivenot : out STD_LOGIC;
    dl0_rxclkesc : out STD_LOGIC;
    dl0_rxlpdtesc : out STD_LOGIC;
    dl0_rxulpsesc : out STD_LOGIC;
    dl0_rxtriggeresc : out STD_LOGIC_VECTOR ( 3 downto 0 );
    dl0_rxdataesc : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl0_rxvalidesc : out STD_LOGIC;
    dl0_errsoths : out STD_LOGIC;
    dl0_errsotsynchs : out STD_LOGIC;
    dl0_erresc : out STD_LOGIC;
    dl0_errsyncesc : out STD_LOGIC;
    dl0_errcontrol : out STD_LOGIC;
    dl1_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl1_rxvalidhs : out STD_LOGIC;
    dl1_rxactivehs : out STD_LOGIC;
    dl1_rxsynchs : out STD_LOGIC;
    dl1_forcerxmode : in STD_LOGIC;
    dl1_stopstate : out STD_LOGIC;
    dl1_enable : in STD_LOGIC;
    dl1_ulpsactivenot : out STD_LOGIC;
    dl1_rxclkesc : out STD_LOGIC;
    dl1_rxlpdtesc : out STD_LOGIC;
    dl1_rxulpsesc : out STD_LOGIC;
    dl1_rxtriggeresc : out STD_LOGIC_VECTOR ( 3 downto 0 );
    dl1_rxdataesc : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl1_rxvalidesc : out STD_LOGIC;
    dl1_errsoths : out STD_LOGIC;
    dl1_errsotsynchs : out STD_LOGIC;
    dl1_erresc : out STD_LOGIC;
    dl1_errsyncesc : out STD_LOGIC;
    dl1_errcontrol : out STD_LOGIC;
    dl2_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl2_rxvalidhs : out STD_LOGIC;
    dl2_rxactivehs : out STD_LOGIC;
    dl2_rxsynchs : out STD_LOGIC;
    dl2_forcerxmode : in STD_LOGIC;
    dl2_stopstate : out STD_LOGIC;
    dl2_enable : in STD_LOGIC;
    dl2_ulpsactivenot : out STD_LOGIC;
    dl2_rxclkesc : out STD_LOGIC;
    dl2_rxlpdtesc : out STD_LOGIC;
    dl2_rxulpsesc : out STD_LOGIC;
    dl2_rxtriggeresc : out STD_LOGIC_VECTOR ( 3 downto 0 );
    dl2_rxdataesc : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl2_rxvalidesc : out STD_LOGIC;
    dl2_errsoths : out STD_LOGIC;
    dl2_errsotsynchs : out STD_LOGIC;
    dl2_erresc : out STD_LOGIC;
    dl2_errsyncesc : out STD_LOGIC;
    dl2_errcontrol : out STD_LOGIC;
    dl3_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl3_rxvalidhs : out STD_LOGIC;
    dl3_rxactivehs : out STD_LOGIC;
    dl3_rxsynchs : out STD_LOGIC;
    dl3_forcerxmode : in STD_LOGIC;
    dl3_stopstate : out STD_LOGIC;
    dl3_enable : in STD_LOGIC;
    dl3_ulpsactivenot : out STD_LOGIC;
    dl3_rxclkesc : out STD_LOGIC;
    dl3_rxlpdtesc : out STD_LOGIC;
    dl3_rxulpsesc : out STD_LOGIC;
    dl3_rxtriggeresc : out STD_LOGIC_VECTOR ( 3 downto 0 );
    dl3_rxdataesc : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl3_rxvalidesc : out STD_LOGIC;
    dl3_errsoths : out STD_LOGIC;
    dl3_errsotsynchs : out STD_LOGIC;
    dl3_erresc : out STD_LOGIC;
    dl3_errsyncesc : out STD_LOGIC;
    dl3_errcontrol : out STD_LOGIC;
    s_axi_aclk : in STD_LOGIC;
    s_axi_aresetn : in STD_LOGIC;
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
    s_axi_awready : out STD_LOGIC;
    s_axi_awvalid : in STD_LOGIC;
    s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
    s_axi_arready : out STD_LOGIC;
    s_axi_arvalid : in STD_LOGIC;
    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_wready : out STD_LOGIC;
    s_axi_wvalid : in STD_LOGIC;
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rready : in STD_LOGIC;
    s_axi_rvalid : out STD_LOGIC;
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bready : in STD_LOGIC;
    s_axi_bvalid : out STD_LOGIC;
    clk_rxp : in STD_LOGIC;
    clk_rxn : in STD_LOGIC;
    data_rxp : in STD_LOGIC_VECTOR ( 3 downto 0 );
    data_rxn : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute C_CAL_MODE : string;
  attribute C_CAL_MODE of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "FIXED";
  attribute C_DIV4_CLK_PERIOD : string;
  attribute C_DIV4_CLK_PERIOD of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "6.734000";
  attribute C_DPHY_LANES : integer;
  attribute C_DPHY_LANES of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is 4;
  attribute C_DPHY_MODE : string;
  attribute C_DPHY_MODE of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "SLAVE";
  attribute C_EN_DEBUG_REGS : integer;
  attribute C_EN_DEBUG_REGS of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is 0;
  attribute C_EN_EXT_TAP : string;
  attribute C_EN_EXT_TAP of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "0";
  attribute C_EN_REG_IF : integer;
  attribute C_EN_REG_IF of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is 1;
  attribute C_EN_SSC : string;
  attribute C_EN_SSC of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "0";
  attribute C_EN_TIMEOUT_REGS : integer;
  attribute C_EN_TIMEOUT_REGS of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is 0;
  attribute C_ESC_CLK_PERIOD : string;
  attribute C_ESC_CLK_PERIOD of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "50.000000";
  attribute C_ESC_TIMEOUT : integer;
  attribute C_ESC_TIMEOUT of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is 25600;
  attribute C_EXAMPLE_SIMULATION : string;
  attribute C_EXAMPLE_SIMULATION of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "true";
  attribute C_HS_LINE_RATE : integer;
  attribute C_HS_LINE_RATE of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is 1188;
  attribute C_HS_TIMEOUT : integer;
  attribute C_HS_TIMEOUT of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is 65541;
  attribute C_IDLY_TAP : integer;
  attribute C_IDLY_TAP of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is 0;
  attribute C_LPX_PERIOD : integer;
  attribute C_LPX_PERIOD of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is 50;
  attribute C_RCVE_DESKEW_SEQ : string;
  attribute C_RCVE_DESKEW_SEQ of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "false";
  attribute C_SKEWCAL_FIRST_TIME : integer;
  attribute C_SKEWCAL_FIRST_TIME of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is 4096;
  attribute C_SKEWCAL_PERIODIC_TIME : integer;
  attribute C_SKEWCAL_PERIODIC_TIME of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is 128;
  attribute C_STABLE_CLK_PERIOD : string;
  attribute C_STABLE_CLK_PERIOD of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "5.000000";
  attribute C_TXPLL_CLKIN_PERIOD : string;
  attribute C_TXPLL_CLKIN_PERIOD of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "6.734000";
  attribute C_WAKEUP : integer;
  attribute C_WAKEUP of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is 1000;
  attribute C_XMIT_FIRST_DESKEW_SEQ : string;
  attribute C_XMIT_FIRST_DESKEW_SEQ of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "false";
  attribute C_XMIT_PERIODIC_DESKEW_SEQ : string;
  attribute C_XMIT_PERIODIC_DESKEW_SEQ of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "false";
  attribute DPHY_PRESET : string;
  attribute DPHY_PRESET of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "CSI2RX_XLNX";
  attribute MTBF_SYNC_STAGES : integer;
  attribute MTBF_SYNC_STAGES of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is 3;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "bd_7289_phy_0_core";
  attribute SUPPORT_LEVEL : integer;
  attribute SUPPORT_LEVEL of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is 1;
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_bd_7289_phy_0_core : entity is "yes";
end design_1_Vsp_core_0_0_bd_7289_phy_0_core;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_phy_0_core is
  signal \<const0>\ : STD_LOGIC;
begin
  cl_rxclkactivehs <= \<const0>\;
  cl_rxulpsclknot <= \<const0>\;
  cl_ulpsactivenot <= \<const0>\;
  clkoutphy_out <= \<const0>\;
  dl0_errcontrol <= \<const0>\;
  dl0_erresc <= \<const0>\;
  dl0_errsyncesc <= \<const0>\;
  dl0_rxclkesc <= \<const0>\;
  dl0_rxdataesc(7) <= \<const0>\;
  dl0_rxdataesc(6) <= \<const0>\;
  dl0_rxdataesc(5) <= \<const0>\;
  dl0_rxdataesc(4) <= \<const0>\;
  dl0_rxdataesc(3) <= \<const0>\;
  dl0_rxdataesc(2) <= \<const0>\;
  dl0_rxdataesc(1) <= \<const0>\;
  dl0_rxdataesc(0) <= \<const0>\;
  dl0_rxlpdtesc <= \<const0>\;
  dl0_rxtriggeresc(3) <= \<const0>\;
  dl0_rxtriggeresc(2) <= \<const0>\;
  dl0_rxtriggeresc(1) <= \<const0>\;
  dl0_rxtriggeresc(0) <= \<const0>\;
  dl0_rxulpsesc <= \<const0>\;
  dl0_rxvalidesc <= \<const0>\;
  dl0_ulpsactivenot <= \<const0>\;
  dl1_errcontrol <= \<const0>\;
  dl1_erresc <= \<const0>\;
  dl1_errsyncesc <= \<const0>\;
  dl1_rxclkesc <= \<const0>\;
  dl1_rxdataesc(7) <= \<const0>\;
  dl1_rxdataesc(6) <= \<const0>\;
  dl1_rxdataesc(5) <= \<const0>\;
  dl1_rxdataesc(4) <= \<const0>\;
  dl1_rxdataesc(3) <= \<const0>\;
  dl1_rxdataesc(2) <= \<const0>\;
  dl1_rxdataesc(1) <= \<const0>\;
  dl1_rxdataesc(0) <= \<const0>\;
  dl1_rxlpdtesc <= \<const0>\;
  dl1_rxtriggeresc(3) <= \<const0>\;
  dl1_rxtriggeresc(2) <= \<const0>\;
  dl1_rxtriggeresc(1) <= \<const0>\;
  dl1_rxtriggeresc(0) <= \<const0>\;
  dl1_rxulpsesc <= \<const0>\;
  dl1_rxvalidesc <= \<const0>\;
  dl1_ulpsactivenot <= \<const0>\;
  dl2_errcontrol <= \<const0>\;
  dl2_erresc <= \<const0>\;
  dl2_errsyncesc <= \<const0>\;
  dl2_rxclkesc <= \<const0>\;
  dl2_rxdataesc(7) <= \<const0>\;
  dl2_rxdataesc(6) <= \<const0>\;
  dl2_rxdataesc(5) <= \<const0>\;
  dl2_rxdataesc(4) <= \<const0>\;
  dl2_rxdataesc(3) <= \<const0>\;
  dl2_rxdataesc(2) <= \<const0>\;
  dl2_rxdataesc(1) <= \<const0>\;
  dl2_rxdataesc(0) <= \<const0>\;
  dl2_rxlpdtesc <= \<const0>\;
  dl2_rxtriggeresc(3) <= \<const0>\;
  dl2_rxtriggeresc(2) <= \<const0>\;
  dl2_rxtriggeresc(1) <= \<const0>\;
  dl2_rxtriggeresc(0) <= \<const0>\;
  dl2_rxulpsesc <= \<const0>\;
  dl2_rxvalidesc <= \<const0>\;
  dl2_ulpsactivenot <= \<const0>\;
  dl3_errcontrol <= \<const0>\;
  dl3_erresc <= \<const0>\;
  dl3_errsyncesc <= \<const0>\;
  dl3_rxclkesc <= \<const0>\;
  dl3_rxdataesc(7) <= \<const0>\;
  dl3_rxdataesc(6) <= \<const0>\;
  dl3_rxdataesc(5) <= \<const0>\;
  dl3_rxdataesc(4) <= \<const0>\;
  dl3_rxdataesc(3) <= \<const0>\;
  dl3_rxdataesc(2) <= \<const0>\;
  dl3_rxdataesc(1) <= \<const0>\;
  dl3_rxdataesc(0) <= \<const0>\;
  dl3_rxlpdtesc <= \<const0>\;
  dl3_rxtriggeresc(3) <= \<const0>\;
  dl3_rxtriggeresc(2) <= \<const0>\;
  dl3_rxtriggeresc(1) <= \<const0>\;
  dl3_rxtriggeresc(0) <= \<const0>\;
  dl3_rxulpsesc <= \<const0>\;
  dl3_rxvalidesc <= \<const0>\;
  dl3_ulpsactivenot <= \<const0>\;
  init_done <= \<const0>\;
  pll_lock_out <= \<const0>\;
  s_axi_bresp(1) <= \<const0>\;
  s_axi_bresp(0) <= \<const0>\;
  s_axi_rresp(1) <= \<const0>\;
  s_axi_rresp(0) <= \<const0>\;
  system_rst_out <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
inst: entity work.design_1_Vsp_core_0_0_bd_7289_phy_0_c1
     port map (
      cl_enable => cl_enable,
      cl_stopstate => cl_stopstate,
      clk_rxn => clk_rxn,
      clk_rxp => clk_rxp,
      core_clk => core_clk,
      core_rst => core_rst,
      data_rxn(3 downto 0) => data_rxn(3 downto 0),
      data_rxp(3 downto 0) => data_rxp(3 downto 0),
      dl0_errsoths => dl0_errsoths,
      dl0_errsotsynchs => dl0_errsotsynchs,
      dl0_rxactivehs => dl0_rxactivehs,
      dl0_rxdatahs(7 downto 0) => dl0_rxdatahs(7 downto 0),
      dl0_rxsynchs => dl0_rxsynchs,
      dl0_rxvalidhs => dl0_rxvalidhs,
      dl0_stopstate => dl0_stopstate,
      dl1_errsoths => dl1_errsoths,
      dl1_errsotsynchs => dl1_errsotsynchs,
      dl1_rxactivehs => dl1_rxactivehs,
      dl1_rxdatahs(7 downto 0) => dl1_rxdatahs(7 downto 0),
      dl1_rxsynchs => dl1_rxsynchs,
      dl1_rxvalidhs => dl1_rxvalidhs,
      dl1_stopstate => dl1_stopstate,
      dl2_errsoths => dl2_errsoths,
      dl2_errsotsynchs => dl2_errsotsynchs,
      dl2_rxactivehs => dl2_rxactivehs,
      dl2_rxdatahs(7 downto 0) => dl2_rxdatahs(7 downto 0),
      dl2_rxsynchs => dl2_rxsynchs,
      dl2_rxvalidhs => dl2_rxvalidhs,
      dl2_stopstate => dl2_stopstate,
      dl3_errsoths => dl3_errsoths,
      dl3_errsotsynchs => dl3_errsotsynchs,
      dl3_rxactivehs => dl3_rxactivehs,
      dl3_rxdatahs(7 downto 0) => dl3_rxdatahs(7 downto 0),
      dl3_rxsynchs => dl3_rxsynchs,
      dl3_rxvalidhs => dl3_rxvalidhs,
      dl3_stopstate => dl3_stopstate,
      rxbyteclkhs => rxbyteclkhs,
      s_axi_araddr(4 downto 0) => s_axi_araddr(6 downto 2),
      s_axi_aresetn => s_axi_aresetn,
      s_axi_arready => s_axi_arready,
      s_axi_arvalid => s_axi_arvalid,
      s_axi_awaddr(4 downto 0) => s_axi_awaddr(6 downto 2),
      s_axi_awready => s_axi_awready,
      s_axi_awvalid => s_axi_awvalid,
      s_axi_bready => s_axi_bready,
      s_axi_bvalid => s_axi_bvalid,
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      s_axi_rready => s_axi_rready,
      s_axi_rvalid => s_axi_rvalid,
      s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
      s_axi_wready => s_axi_wready,
      s_axi_wvalid => s_axi_wvalid
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289_phy_0 is
  port (
    core_clk : in STD_LOGIC;
    core_rst : in STD_LOGIC;
    rxbyteclkhs : out STD_LOGIC;
    clkoutphy_out : out STD_LOGIC;
    pll_lock_out : out STD_LOGIC;
    system_rst_out : out STD_LOGIC;
    init_done : out STD_LOGIC;
    cl_rxclkactivehs : out STD_LOGIC;
    cl_stopstate : out STD_LOGIC;
    cl_enable : in STD_LOGIC;
    cl_rxulpsclknot : out STD_LOGIC;
    cl_ulpsactivenot : out STD_LOGIC;
    dl0_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl0_rxvalidhs : out STD_LOGIC;
    dl0_rxactivehs : out STD_LOGIC;
    dl0_rxsynchs : out STD_LOGIC;
    dl0_forcerxmode : in STD_LOGIC;
    dl0_stopstate : out STD_LOGIC;
    dl0_enable : in STD_LOGIC;
    dl0_ulpsactivenot : out STD_LOGIC;
    dl0_rxclkesc : out STD_LOGIC;
    dl0_rxlpdtesc : out STD_LOGIC;
    dl0_rxulpsesc : out STD_LOGIC;
    dl0_rxtriggeresc : out STD_LOGIC_VECTOR ( 3 downto 0 );
    dl0_rxdataesc : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl0_rxvalidesc : out STD_LOGIC;
    dl0_errsoths : out STD_LOGIC;
    dl0_errsotsynchs : out STD_LOGIC;
    dl0_erresc : out STD_LOGIC;
    dl0_errsyncesc : out STD_LOGIC;
    dl0_errcontrol : out STD_LOGIC;
    dl1_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl1_rxvalidhs : out STD_LOGIC;
    dl1_rxactivehs : out STD_LOGIC;
    dl1_rxsynchs : out STD_LOGIC;
    dl1_forcerxmode : in STD_LOGIC;
    dl1_stopstate : out STD_LOGIC;
    dl1_enable : in STD_LOGIC;
    dl1_ulpsactivenot : out STD_LOGIC;
    dl1_rxclkesc : out STD_LOGIC;
    dl1_rxlpdtesc : out STD_LOGIC;
    dl1_rxulpsesc : out STD_LOGIC;
    dl1_rxtriggeresc : out STD_LOGIC_VECTOR ( 3 downto 0 );
    dl1_rxdataesc : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl1_rxvalidesc : out STD_LOGIC;
    dl1_errsoths : out STD_LOGIC;
    dl1_errsotsynchs : out STD_LOGIC;
    dl1_erresc : out STD_LOGIC;
    dl1_errsyncesc : out STD_LOGIC;
    dl1_errcontrol : out STD_LOGIC;
    dl2_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl2_rxvalidhs : out STD_LOGIC;
    dl2_rxactivehs : out STD_LOGIC;
    dl2_rxsynchs : out STD_LOGIC;
    dl2_forcerxmode : in STD_LOGIC;
    dl2_stopstate : out STD_LOGIC;
    dl2_enable : in STD_LOGIC;
    dl2_ulpsactivenot : out STD_LOGIC;
    dl2_rxclkesc : out STD_LOGIC;
    dl2_rxlpdtesc : out STD_LOGIC;
    dl2_rxulpsesc : out STD_LOGIC;
    dl2_rxtriggeresc : out STD_LOGIC_VECTOR ( 3 downto 0 );
    dl2_rxdataesc : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl2_rxvalidesc : out STD_LOGIC;
    dl2_errsoths : out STD_LOGIC;
    dl2_errsotsynchs : out STD_LOGIC;
    dl2_erresc : out STD_LOGIC;
    dl2_errsyncesc : out STD_LOGIC;
    dl2_errcontrol : out STD_LOGIC;
    dl3_rxdatahs : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl3_rxvalidhs : out STD_LOGIC;
    dl3_rxactivehs : out STD_LOGIC;
    dl3_rxsynchs : out STD_LOGIC;
    dl3_forcerxmode : in STD_LOGIC;
    dl3_stopstate : out STD_LOGIC;
    dl3_enable : in STD_LOGIC;
    dl3_ulpsactivenot : out STD_LOGIC;
    dl3_rxclkesc : out STD_LOGIC;
    dl3_rxlpdtesc : out STD_LOGIC;
    dl3_rxulpsesc : out STD_LOGIC;
    dl3_rxtriggeresc : out STD_LOGIC_VECTOR ( 3 downto 0 );
    dl3_rxdataesc : out STD_LOGIC_VECTOR ( 7 downto 0 );
    dl3_rxvalidesc : out STD_LOGIC;
    dl3_errsoths : out STD_LOGIC;
    dl3_errsotsynchs : out STD_LOGIC;
    dl3_erresc : out STD_LOGIC;
    dl3_errsyncesc : out STD_LOGIC;
    dl3_errcontrol : out STD_LOGIC;
    s_axi_aclk : in STD_LOGIC;
    s_axi_aresetn : in STD_LOGIC;
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
    s_axi_awready : out STD_LOGIC;
    s_axi_awvalid : in STD_LOGIC;
    s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
    s_axi_arready : out STD_LOGIC;
    s_axi_arvalid : in STD_LOGIC;
    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_wready : out STD_LOGIC;
    s_axi_wvalid : in STD_LOGIC;
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rready : in STD_LOGIC;
    s_axi_rvalid : out STD_LOGIC;
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bready : in STD_LOGIC;
    s_axi_bvalid : out STD_LOGIC;
    clk_rxp : in STD_LOGIC;
    clk_rxn : in STD_LOGIC;
    data_rxp : in STD_LOGIC_VECTOR ( 3 downto 0 );
    data_rxn : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute C_CAL_MODE : string;
  attribute C_CAL_MODE of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "FIXED";
  attribute C_DIV4_CLK_PERIOD : string;
  attribute C_DIV4_CLK_PERIOD of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "6.734000";
  attribute C_DPHY_LANES : integer;
  attribute C_DPHY_LANES of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is 4;
  attribute C_DPHY_MODE : string;
  attribute C_DPHY_MODE of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "SLAVE";
  attribute C_EN_DEBUG_REGS : integer;
  attribute C_EN_DEBUG_REGS of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is 0;
  attribute C_EN_DEBUG_TX_CALIB : string;
  attribute C_EN_DEBUG_TX_CALIB of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "0";
  attribute C_EN_EXT_TAP : string;
  attribute C_EN_EXT_TAP of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "0";
  attribute C_EN_REG_IF : integer;
  attribute C_EN_REG_IF of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is 1;
  attribute C_EN_SSC : string;
  attribute C_EN_SSC of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "0";
  attribute C_EN_TIMEOUT_REGS : integer;
  attribute C_EN_TIMEOUT_REGS of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is 0;
  attribute C_ESC_CLK_PERIOD : string;
  attribute C_ESC_CLK_PERIOD of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "50.000000";
  attribute C_ESC_TIMEOUT : integer;
  attribute C_ESC_TIMEOUT of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is 25600;
  attribute C_EXAMPLE_SIMULATION : string;
  attribute C_EXAMPLE_SIMULATION of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "true";
  attribute C_HS_LINE_RATE : integer;
  attribute C_HS_LINE_RATE of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is 1188;
  attribute C_HS_TIMEOUT : integer;
  attribute C_HS_TIMEOUT of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is 65541;
  attribute C_IDLY_TAP : integer;
  attribute C_IDLY_TAP of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is 0;
  attribute C_LPX_PERIOD : integer;
  attribute C_LPX_PERIOD of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is 50;
  attribute C_RCVE_DESKEW_SEQ : string;
  attribute C_RCVE_DESKEW_SEQ of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "false";
  attribute C_SKEWCAL_FIRST_TIME : integer;
  attribute C_SKEWCAL_FIRST_TIME of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is 4096;
  attribute C_SKEWCAL_PERIODIC_TIME : integer;
  attribute C_SKEWCAL_PERIODIC_TIME of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is 128;
  attribute C_STABLE_CLK_PERIOD : string;
  attribute C_STABLE_CLK_PERIOD of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "5.000000";
  attribute C_TXPLL_CLKIN_PERIOD : string;
  attribute C_TXPLL_CLKIN_PERIOD of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "6.734000";
  attribute C_WAKEUP : integer;
  attribute C_WAKEUP of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is 1000;
  attribute C_XMIT_FIRST_DESKEW_SEQ : string;
  attribute C_XMIT_FIRST_DESKEW_SEQ of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "false";
  attribute C_XMIT_PERIODIC_DESKEW_SEQ : string;
  attribute C_XMIT_PERIODIC_DESKEW_SEQ of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "false";
  attribute DPHY_PRESET : string;
  attribute DPHY_PRESET of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "CSI2RX_XLNX";
  attribute MTBF_SYNC_STAGES : integer;
  attribute MTBF_SYNC_STAGES of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is 3;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "bd_7289_phy_0";
  attribute SUPPORT_LEVEL : integer;
  attribute SUPPORT_LEVEL of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is 1;
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_bd_7289_phy_0 : entity is "yes";
end design_1_Vsp_core_0_0_bd_7289_phy_0;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289_phy_0 is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_inst_cl_rxclkactivehs_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cl_rxulpsclknot_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cl_ulpsactivenot_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_clkoutphy_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl0_errcontrol_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl0_erresc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl0_errsyncesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl0_rxclkesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl0_rxlpdtesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl0_rxulpsesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl0_rxvalidesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl0_ulpsactivenot_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl1_errcontrol_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl1_erresc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl1_errsyncesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl1_rxclkesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl1_rxlpdtesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl1_rxulpsesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl1_rxvalidesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl1_ulpsactivenot_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl2_errcontrol_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl2_erresc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl2_errsyncesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl2_rxclkesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl2_rxlpdtesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl2_rxulpsesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl2_rxvalidesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl2_ulpsactivenot_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl3_errcontrol_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl3_erresc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl3_errsyncesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl3_rxclkesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl3_rxlpdtesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl3_rxulpsesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl3_rxvalidesc_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl3_ulpsactivenot_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_init_done_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pll_lock_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_system_rst_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_dl0_rxdataesc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_dl0_rxtriggeresc_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_dl1_rxdataesc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_dl1_rxtriggeresc_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_dl2_rxdataesc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_dl2_rxtriggeresc_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_dl3_rxdataesc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_dl3_rxtriggeresc_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_CAL_MODE of inst : label is "FIXED";
  attribute C_DIV4_CLK_PERIOD of inst : label is "6.734000";
  attribute C_DPHY_LANES of inst : label is 4;
  attribute C_DPHY_MODE of inst : label is "SLAVE";
  attribute C_EN_DEBUG_REGS of inst : label is 0;
  attribute C_EN_EXT_TAP_integer : integer;
  attribute C_EN_EXT_TAP_integer of inst : label is 0;
  attribute C_EN_REG_IF of inst : label is 1;
  attribute C_EN_SSC of inst : label is "0";
  attribute C_EN_TIMEOUT_REGS of inst : label is 0;
  attribute C_ESC_CLK_PERIOD of inst : label is "50.000000";
  attribute C_ESC_TIMEOUT of inst : label is 25600;
  attribute C_EXAMPLE_SIMULATION of inst : label is "true";
  attribute C_HS_LINE_RATE of inst : label is 1188;
  attribute C_HS_TIMEOUT of inst : label is 65541;
  attribute C_IDLY_TAP of inst : label is 0;
  attribute C_LPX_PERIOD of inst : label is 50;
  attribute C_RCVE_DESKEW_SEQ of inst : label is "false";
  attribute C_SKEWCAL_FIRST_TIME of inst : label is 4096;
  attribute C_SKEWCAL_PERIODIC_TIME of inst : label is 128;
  attribute C_STABLE_CLK_PERIOD of inst : label is "5.000000";
  attribute C_TXPLL_CLKIN_PERIOD of inst : label is "6.734000";
  attribute C_WAKEUP of inst : label is 1000;
  attribute C_XMIT_FIRST_DESKEW_SEQ of inst : label is "false";
  attribute C_XMIT_PERIODIC_DESKEW_SEQ of inst : label is "false";
  attribute DPHY_PRESET of inst : label is "CSI2RX_XLNX";
  attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
  attribute MTBF_SYNC_STAGES of inst : label is 3;
  attribute SUPPORT_LEVEL of inst : label is 1;
begin
  cl_rxclkactivehs <= \<const0>\;
  cl_rxulpsclknot <= \<const0>\;
  cl_ulpsactivenot <= \<const0>\;
  clkoutphy_out <= \<const0>\;
  dl0_errcontrol <= \<const0>\;
  dl0_erresc <= \<const0>\;
  dl0_errsyncesc <= \<const0>\;
  dl0_rxclkesc <= \<const0>\;
  dl0_rxdataesc(7) <= \<const0>\;
  dl0_rxdataesc(6) <= \<const0>\;
  dl0_rxdataesc(5) <= \<const0>\;
  dl0_rxdataesc(4) <= \<const0>\;
  dl0_rxdataesc(3) <= \<const0>\;
  dl0_rxdataesc(2) <= \<const0>\;
  dl0_rxdataesc(1) <= \<const0>\;
  dl0_rxdataesc(0) <= \<const0>\;
  dl0_rxlpdtesc <= \<const0>\;
  dl0_rxtriggeresc(3) <= \<const0>\;
  dl0_rxtriggeresc(2) <= \<const0>\;
  dl0_rxtriggeresc(1) <= \<const0>\;
  dl0_rxtriggeresc(0) <= \<const0>\;
  dl0_rxulpsesc <= \<const0>\;
  dl0_rxvalidesc <= \<const0>\;
  dl0_ulpsactivenot <= \<const0>\;
  dl1_errcontrol <= \<const0>\;
  dl1_erresc <= \<const0>\;
  dl1_errsyncesc <= \<const0>\;
  dl1_rxclkesc <= \<const0>\;
  dl1_rxdataesc(7) <= \<const0>\;
  dl1_rxdataesc(6) <= \<const0>\;
  dl1_rxdataesc(5) <= \<const0>\;
  dl1_rxdataesc(4) <= \<const0>\;
  dl1_rxdataesc(3) <= \<const0>\;
  dl1_rxdataesc(2) <= \<const0>\;
  dl1_rxdataesc(1) <= \<const0>\;
  dl1_rxdataesc(0) <= \<const0>\;
  dl1_rxlpdtesc <= \<const0>\;
  dl1_rxtriggeresc(3) <= \<const0>\;
  dl1_rxtriggeresc(2) <= \<const0>\;
  dl1_rxtriggeresc(1) <= \<const0>\;
  dl1_rxtriggeresc(0) <= \<const0>\;
  dl1_rxulpsesc <= \<const0>\;
  dl1_rxvalidesc <= \<const0>\;
  dl1_ulpsactivenot <= \<const0>\;
  dl2_errcontrol <= \<const0>\;
  dl2_erresc <= \<const0>\;
  dl2_errsyncesc <= \<const0>\;
  dl2_rxclkesc <= \<const0>\;
  dl2_rxdataesc(7) <= \<const0>\;
  dl2_rxdataesc(6) <= \<const0>\;
  dl2_rxdataesc(5) <= \<const0>\;
  dl2_rxdataesc(4) <= \<const0>\;
  dl2_rxdataesc(3) <= \<const0>\;
  dl2_rxdataesc(2) <= \<const0>\;
  dl2_rxdataesc(1) <= \<const0>\;
  dl2_rxdataesc(0) <= \<const0>\;
  dl2_rxlpdtesc <= \<const0>\;
  dl2_rxtriggeresc(3) <= \<const0>\;
  dl2_rxtriggeresc(2) <= \<const0>\;
  dl2_rxtriggeresc(1) <= \<const0>\;
  dl2_rxtriggeresc(0) <= \<const0>\;
  dl2_rxulpsesc <= \<const0>\;
  dl2_rxvalidesc <= \<const0>\;
  dl2_ulpsactivenot <= \<const0>\;
  dl3_errcontrol <= \<const0>\;
  dl3_erresc <= \<const0>\;
  dl3_errsyncesc <= \<const0>\;
  dl3_rxclkesc <= \<const0>\;
  dl3_rxdataesc(7) <= \<const0>\;
  dl3_rxdataesc(6) <= \<const0>\;
  dl3_rxdataesc(5) <= \<const0>\;
  dl3_rxdataesc(4) <= \<const0>\;
  dl3_rxdataesc(3) <= \<const0>\;
  dl3_rxdataesc(2) <= \<const0>\;
  dl3_rxdataesc(1) <= \<const0>\;
  dl3_rxdataesc(0) <= \<const0>\;
  dl3_rxlpdtesc <= \<const0>\;
  dl3_rxtriggeresc(3) <= \<const0>\;
  dl3_rxtriggeresc(2) <= \<const0>\;
  dl3_rxtriggeresc(1) <= \<const0>\;
  dl3_rxtriggeresc(0) <= \<const0>\;
  dl3_rxulpsesc <= \<const0>\;
  dl3_rxvalidesc <= \<const0>\;
  dl3_ulpsactivenot <= \<const0>\;
  init_done <= \<const0>\;
  pll_lock_out <= \<const0>\;
  s_axi_bresp(1) <= \<const0>\;
  s_axi_bresp(0) <= \<const0>\;
  s_axi_rresp(1) <= \<const0>\;
  s_axi_rresp(0) <= \<const0>\;
  system_rst_out <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
inst: entity work.design_1_Vsp_core_0_0_bd_7289_phy_0_core
     port map (
      cl_enable => cl_enable,
      cl_rxclkactivehs => NLW_inst_cl_rxclkactivehs_UNCONNECTED,
      cl_rxulpsclknot => NLW_inst_cl_rxulpsclknot_UNCONNECTED,
      cl_stopstate => cl_stopstate,
      cl_ulpsactivenot => NLW_inst_cl_ulpsactivenot_UNCONNECTED,
      clk_rxn => clk_rxn,
      clk_rxp => clk_rxp,
      clkoutphy_out => NLW_inst_clkoutphy_out_UNCONNECTED,
      core_clk => core_clk,
      core_rst => core_rst,
      data_rxn(3 downto 0) => data_rxn(3 downto 0),
      data_rxp(3 downto 0) => data_rxp(3 downto 0),
      dl0_enable => '0',
      dl0_errcontrol => NLW_inst_dl0_errcontrol_UNCONNECTED,
      dl0_erresc => NLW_inst_dl0_erresc_UNCONNECTED,
      dl0_errsoths => dl0_errsoths,
      dl0_errsotsynchs => dl0_errsotsynchs,
      dl0_errsyncesc => NLW_inst_dl0_errsyncesc_UNCONNECTED,
      dl0_forcerxmode => '0',
      dl0_rxactivehs => dl0_rxactivehs,
      dl0_rxclkesc => NLW_inst_dl0_rxclkesc_UNCONNECTED,
      dl0_rxdataesc(7 downto 0) => NLW_inst_dl0_rxdataesc_UNCONNECTED(7 downto 0),
      dl0_rxdatahs(7 downto 0) => dl0_rxdatahs(7 downto 0),
      dl0_rxlpdtesc => NLW_inst_dl0_rxlpdtesc_UNCONNECTED,
      dl0_rxsynchs => dl0_rxsynchs,
      dl0_rxtriggeresc(3 downto 0) => NLW_inst_dl0_rxtriggeresc_UNCONNECTED(3 downto 0),
      dl0_rxulpsesc => NLW_inst_dl0_rxulpsesc_UNCONNECTED,
      dl0_rxvalidesc => NLW_inst_dl0_rxvalidesc_UNCONNECTED,
      dl0_rxvalidhs => dl0_rxvalidhs,
      dl0_stopstate => dl0_stopstate,
      dl0_ulpsactivenot => NLW_inst_dl0_ulpsactivenot_UNCONNECTED,
      dl1_enable => '0',
      dl1_errcontrol => NLW_inst_dl1_errcontrol_UNCONNECTED,
      dl1_erresc => NLW_inst_dl1_erresc_UNCONNECTED,
      dl1_errsoths => dl1_errsoths,
      dl1_errsotsynchs => dl1_errsotsynchs,
      dl1_errsyncesc => NLW_inst_dl1_errsyncesc_UNCONNECTED,
      dl1_forcerxmode => '0',
      dl1_rxactivehs => dl1_rxactivehs,
      dl1_rxclkesc => NLW_inst_dl1_rxclkesc_UNCONNECTED,
      dl1_rxdataesc(7 downto 0) => NLW_inst_dl1_rxdataesc_UNCONNECTED(7 downto 0),
      dl1_rxdatahs(7 downto 0) => dl1_rxdatahs(7 downto 0),
      dl1_rxlpdtesc => NLW_inst_dl1_rxlpdtesc_UNCONNECTED,
      dl1_rxsynchs => dl1_rxsynchs,
      dl1_rxtriggeresc(3 downto 0) => NLW_inst_dl1_rxtriggeresc_UNCONNECTED(3 downto 0),
      dl1_rxulpsesc => NLW_inst_dl1_rxulpsesc_UNCONNECTED,
      dl1_rxvalidesc => NLW_inst_dl1_rxvalidesc_UNCONNECTED,
      dl1_rxvalidhs => dl1_rxvalidhs,
      dl1_stopstate => dl1_stopstate,
      dl1_ulpsactivenot => NLW_inst_dl1_ulpsactivenot_UNCONNECTED,
      dl2_enable => '0',
      dl2_errcontrol => NLW_inst_dl2_errcontrol_UNCONNECTED,
      dl2_erresc => NLW_inst_dl2_erresc_UNCONNECTED,
      dl2_errsoths => dl2_errsoths,
      dl2_errsotsynchs => dl2_errsotsynchs,
      dl2_errsyncesc => NLW_inst_dl2_errsyncesc_UNCONNECTED,
      dl2_forcerxmode => '0',
      dl2_rxactivehs => dl2_rxactivehs,
      dl2_rxclkesc => NLW_inst_dl2_rxclkesc_UNCONNECTED,
      dl2_rxdataesc(7 downto 0) => NLW_inst_dl2_rxdataesc_UNCONNECTED(7 downto 0),
      dl2_rxdatahs(7 downto 0) => dl2_rxdatahs(7 downto 0),
      dl2_rxlpdtesc => NLW_inst_dl2_rxlpdtesc_UNCONNECTED,
      dl2_rxsynchs => dl2_rxsynchs,
      dl2_rxtriggeresc(3 downto 0) => NLW_inst_dl2_rxtriggeresc_UNCONNECTED(3 downto 0),
      dl2_rxulpsesc => NLW_inst_dl2_rxulpsesc_UNCONNECTED,
      dl2_rxvalidesc => NLW_inst_dl2_rxvalidesc_UNCONNECTED,
      dl2_rxvalidhs => dl2_rxvalidhs,
      dl2_stopstate => dl2_stopstate,
      dl2_ulpsactivenot => NLW_inst_dl2_ulpsactivenot_UNCONNECTED,
      dl3_enable => '0',
      dl3_errcontrol => NLW_inst_dl3_errcontrol_UNCONNECTED,
      dl3_erresc => NLW_inst_dl3_erresc_UNCONNECTED,
      dl3_errsoths => dl3_errsoths,
      dl3_errsotsynchs => dl3_errsotsynchs,
      dl3_errsyncesc => NLW_inst_dl3_errsyncesc_UNCONNECTED,
      dl3_forcerxmode => '0',
      dl3_rxactivehs => dl3_rxactivehs,
      dl3_rxclkesc => NLW_inst_dl3_rxclkesc_UNCONNECTED,
      dl3_rxdataesc(7 downto 0) => NLW_inst_dl3_rxdataesc_UNCONNECTED(7 downto 0),
      dl3_rxdatahs(7 downto 0) => dl3_rxdatahs(7 downto 0),
      dl3_rxlpdtesc => NLW_inst_dl3_rxlpdtesc_UNCONNECTED,
      dl3_rxsynchs => dl3_rxsynchs,
      dl3_rxtriggeresc(3 downto 0) => NLW_inst_dl3_rxtriggeresc_UNCONNECTED(3 downto 0),
      dl3_rxulpsesc => NLW_inst_dl3_rxulpsesc_UNCONNECTED,
      dl3_rxvalidesc => NLW_inst_dl3_rxvalidesc_UNCONNECTED,
      dl3_rxvalidhs => dl3_rxvalidhs,
      dl3_stopstate => dl3_stopstate,
      dl3_ulpsactivenot => NLW_inst_dl3_ulpsactivenot_UNCONNECTED,
      init_done => NLW_inst_init_done_UNCONNECTED,
      pll_lock_out => NLW_inst_pll_lock_out_UNCONNECTED,
      rxbyteclkhs => rxbyteclkhs,
      s_axi_aclk => '0',
      s_axi_araddr(6 downto 2) => s_axi_araddr(6 downto 2),
      s_axi_araddr(1 downto 0) => B"00",
      s_axi_aresetn => s_axi_aresetn,
      s_axi_arready => s_axi_arready,
      s_axi_arvalid => s_axi_arvalid,
      s_axi_awaddr(6 downto 2) => s_axi_awaddr(6 downto 2),
      s_axi_awaddr(1 downto 0) => B"00",
      s_axi_awready => s_axi_awready,
      s_axi_awvalid => s_axi_awvalid,
      s_axi_bready => s_axi_bready,
      s_axi_bresp(1 downto 0) => NLW_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => s_axi_bvalid,
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
      s_axi_rready => s_axi_rready,
      s_axi_rresp(1 downto 0) => NLW_inst_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => s_axi_rvalid,
      s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
      s_axi_wready => s_axi_wready,
      s_axi_wstrb(3 downto 0) => B"0000",
      s_axi_wvalid => s_axi_wvalid,
      system_rst_out => NLW_inst_system_rst_out_UNCONNECTED
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_bd_7289 is
  port (
    clkoutphy_out : out STD_LOGIC;
    csirxss_csi_irq : out STD_LOGIC;
    csirxss_s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
    csirxss_s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    csirxss_s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
    csirxss_s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    csirxss_s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    csirxss_s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    csirxss_s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    csirxss_s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    csirxss_s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    csirxss_s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    dphy_clk_200M : in STD_LOGIC;
    frame_rcvd_pulse_out : out STD_LOGIC;
    lite_aclk : in STD_LOGIC;
    lite_aresetn : in STD_LOGIC;
    mipi_phy_if_clk_n : in STD_LOGIC;
    mipi_phy_if_clk_p : in STD_LOGIC;
    mipi_phy_if_data_n : in STD_LOGIC_VECTOR ( 3 downto 0 );
    mipi_phy_if_data_p : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pll_lock_out : out STD_LOGIC;
    rxbyteclkhs : out STD_LOGIC;
    system_rst_out : out STD_LOGIC;
    video_aclk : in STD_LOGIC;
    video_aresetn : in STD_LOGIC;
    video_out_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 );
    video_out_tdest : out STD_LOGIC_VECTOR ( 9 downto 0 );
    video_out_tlast : out STD_LOGIC;
    video_out_tready : in STD_LOGIC;
    video_out_tuser : out STD_LOGIC_VECTOR ( 95 downto 0 );
    video_out_tvalid : out STD_LOGIC
  );
  attribute HW_HANDOFF : string;
  attribute HW_HANDOFF of design_1_Vsp_core_0_0_bd_7289 : entity is "Mipirx_xlnx_comb_w4_r1188.hwdef";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_bd_7289 : entity is "bd_7289";
end design_1_Vsp_core_0_0_bd_7289;

architecture STRUCTURE of design_1_Vsp_core_0_0_bd_7289 is
  signal \<const0>\ : STD_LOGIC;
  signal phy_n_0 : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_CL_ENABLE : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_CL_STOPSTATE : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL0_ERRSOTHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL0_ERRSOTSYNCHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL0_RXACTIVEHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL0_RXDATAHS : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal phy_rx_mipi_ppi_if_DL0_RXSYNCHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL0_RXVALIDHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL0_STOPSTATE : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL1_ERRSOTHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL1_ERRSOTSYNCHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL1_RXACTIVEHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL1_RXDATAHS : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal phy_rx_mipi_ppi_if_DL1_RXSYNCHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL1_RXVALIDHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL1_STOPSTATE : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL2_ERRSOTHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL2_ERRSOTSYNCHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL2_RXACTIVEHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL2_RXDATAHS : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal phy_rx_mipi_ppi_if_DL2_RXSYNCHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL2_RXVALIDHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL2_STOPSTATE : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL3_ERRSOTHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL3_ERRSOTSYNCHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL3_RXACTIVEHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL3_RXDATAHS : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal phy_rx_mipi_ppi_if_DL3_RXSYNCHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL3_RXVALIDHS : STD_LOGIC;
  signal phy_rx_mipi_ppi_if_DL3_STOPSTATE : STD_LOGIC;
  signal r_sync_peripheral_reset : STD_LOGIC;
  signal rx_m_axis_TDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal rx_m_axis_TKEEP : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rx_m_axis_TLAST : STD_LOGIC;
  signal rx_m_axis_TREADY : STD_LOGIC;
  signal rx_m_axis_TUSER : STD_LOGIC_VECTOR ( 69 downto 0 );
  signal rx_m_axis_TVALID : STD_LOGIC;
  signal \^video_out_tuser\ : STD_LOGIC_VECTOR ( 69 downto 0 );
  signal xbar_M00_AXI_ARREADY : STD_LOGIC;
  signal xbar_M00_AXI_AWREADY : STD_LOGIC;
  signal xbar_M00_AXI_BVALID : STD_LOGIC;
  signal xbar_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal xbar_M00_AXI_RVALID : STD_LOGIC;
  signal xbar_M00_AXI_WREADY : STD_LOGIC;
  signal xbar_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 6 downto 2 );
  signal xbar_M01_AXI_ARREADY : STD_LOGIC;
  signal xbar_M01_AXI_ARVALID : STD_LOGIC;
  signal xbar_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 6 downto 2 );
  signal xbar_M01_AXI_AWREADY : STD_LOGIC;
  signal xbar_M01_AXI_AWVALID : STD_LOGIC;
  signal xbar_M01_AXI_BREADY : STD_LOGIC;
  signal xbar_M01_AXI_BVALID : STD_LOGIC;
  signal xbar_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal xbar_M01_AXI_RREADY : STD_LOGIC;
  signal xbar_M01_AXI_RVALID : STD_LOGIC;
  signal xbar_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal xbar_M01_AXI_WREADY : STD_LOGIC;
  signal xbar_M01_AXI_WVALID : STD_LOGIC;
  signal xbar_n_107 : STD_LOGIC;
  signal xbar_n_108 : STD_LOGIC;
  signal xbar_n_109 : STD_LOGIC;
  signal xbar_n_110 : STD_LOGIC;
  signal xbar_n_111 : STD_LOGIC;
  signal xbar_n_115 : STD_LOGIC;
  signal xbar_n_116 : STD_LOGIC;
  signal xbar_n_117 : STD_LOGIC;
  signal xbar_n_118 : STD_LOGIC;
  signal xbar_n_119 : STD_LOGIC;
  signal xbar_n_120 : STD_LOGIC;
  signal xbar_n_121 : STD_LOGIC;
  signal xbar_n_122 : STD_LOGIC;
  signal xbar_n_123 : STD_LOGIC;
  signal xbar_n_124 : STD_LOGIC;
  signal xbar_n_125 : STD_LOGIC;
  signal xbar_n_126 : STD_LOGIC;
  signal xbar_n_127 : STD_LOGIC;
  signal xbar_n_128 : STD_LOGIC;
  signal xbar_n_129 : STD_LOGIC;
  signal xbar_n_130 : STD_LOGIC;
  signal xbar_n_131 : STD_LOGIC;
  signal xbar_n_132 : STD_LOGIC;
  signal xbar_n_133 : STD_LOGIC;
  signal xbar_n_134 : STD_LOGIC;
  signal xbar_n_135 : STD_LOGIC;
  signal xbar_n_136 : STD_LOGIC;
  signal xbar_n_137 : STD_LOGIC;
  signal xbar_n_138 : STD_LOGIC;
  signal xbar_n_148 : STD_LOGIC;
  signal xbar_n_150 : STD_LOGIC;
  signal xbar_n_169 : STD_LOGIC;
  signal xbar_n_170 : STD_LOGIC;
  signal xbar_n_171 : STD_LOGIC;
  signal xbar_n_172 : STD_LOGIC;
  signal xbar_n_173 : STD_LOGIC;
  signal xbar_n_174 : STD_LOGIC;
  signal xbar_n_184 : STD_LOGIC;
  signal xbar_n_186 : STD_LOGIC;
  signal xbar_n_59 : STD_LOGIC;
  signal xbar_n_60 : STD_LOGIC;
  signal xbar_n_61 : STD_LOGIC;
  signal xbar_n_62 : STD_LOGIC;
  signal xbar_n_63 : STD_LOGIC;
  signal xbar_n_64 : STD_LOGIC;
  signal xbar_n_74 : STD_LOGIC;
  signal NLW_phy_cl_rxclkactivehs_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_cl_rxulpsclknot_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_cl_ulpsactivenot_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_clkoutphy_out_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl0_errcontrol_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl0_erresc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl0_errsyncesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl0_rxclkesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl0_rxlpdtesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl0_rxulpsesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl0_rxvalidesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl0_ulpsactivenot_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl1_errcontrol_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl1_erresc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl1_errsyncesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl1_rxclkesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl1_rxlpdtesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl1_rxulpsesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl1_rxvalidesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl1_ulpsactivenot_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl2_errcontrol_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl2_erresc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl2_errsyncesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl2_rxclkesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl2_rxlpdtesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl2_rxulpsesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl2_rxvalidesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl2_ulpsactivenot_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl3_errcontrol_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl3_erresc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl3_errsyncesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl3_rxclkesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl3_rxlpdtesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl3_rxulpsesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl3_rxvalidesc_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl3_ulpsactivenot_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_init_done_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_pll_lock_out_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_system_rst_out_UNCONNECTED : STD_LOGIC;
  signal NLW_phy_dl0_rxdataesc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_phy_dl0_rxtriggeresc_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_phy_dl1_rxdataesc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_phy_dl1_rxtriggeresc_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_phy_dl2_rxdataesc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_phy_dl2_rxtriggeresc_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_phy_dl3_rxdataesc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_phy_dl3_rxtriggeresc_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_phy_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_phy_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_r_sync_mb_reset_UNCONNECTED : STD_LOGIC;
  signal NLW_r_sync_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_r_sync_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_r_sync_peripheral_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_rx_core_men_vfb_UNCONNECTED : STD_LOGIC;
  signal NLW_rx_dl0_shutdown_UNCONNECTED : STD_LOGIC;
  signal NLW_rx_dl1_shutdown_UNCONNECTED : STD_LOGIC;
  signal NLW_rx_dl2_shutdown_UNCONNECTED : STD_LOGIC;
  signal NLW_rx_dl3_shutdown_UNCONNECTED : STD_LOGIC;
  signal NLW_rx_frame_rcvd_pulse_out_UNCONNECTED : STD_LOGIC;
  signal NLW_rx_interrupt_UNCONNECTED : STD_LOGIC;
  signal NLW_rx_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_rx_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 95 downto 2 );
  signal NLW_rx_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_rx_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_vfb_0_core_men_ack_vfb_UNCONNECTED : STD_LOGIC;
  signal NLW_vfb_0_mdt_tr_UNCONNECTED : STD_LOGIC;
  signal NLW_vfb_0_mdt_tv_UNCONNECTED : STD_LOGIC;
  signal NLW_vfb_0_sdt_tr_UNCONNECTED : STD_LOGIC;
  signal NLW_vfb_0_sdt_tv_UNCONNECTED : STD_LOGIC;
  signal NLW_vfb_0_vfb_full_UNCONNECTED : STD_LOGIC;
  signal NLW_vfb_0_vfb_tr_UNCONNECTED : STD_LOGIC;
  signal NLW_vfb_0_vfb_tv_UNCONNECTED : STD_LOGIC;
  signal NLW_vfb_0_vfb_wc_full_UNCONNECTED : STD_LOGIC;
  signal NLW_vfb_0_vfb_sof_UNCONNECTED : STD_LOGIC_VECTOR ( 95 downto 1 );
  signal NLW_vfb_0_vfb_vcdt_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_xbar_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 25 downto 0 );
  signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_xbar_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 25 downto 0 );
  signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_xbar_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 26 downto 24 );
  signal NLW_xbar_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_xbar_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_CAL_MODE : string;
  attribute C_CAL_MODE of phy : label is "FIXED";
  attribute C_DIV4_CLK_PERIOD : string;
  attribute C_DIV4_CLK_PERIOD of phy : label is "6.734000";
  attribute C_DPHY_LANES : integer;
  attribute C_DPHY_LANES of phy : label is 4;
  attribute C_DPHY_MODE : string;
  attribute C_DPHY_MODE of phy : label is "SLAVE";
  attribute C_EN_DEBUG_REGS : integer;
  attribute C_EN_DEBUG_REGS of phy : label is 0;
  attribute C_EN_DEBUG_TX_CALIB : string;
  attribute C_EN_DEBUG_TX_CALIB of phy : label is "0";
  attribute C_EN_EXT_TAP : integer;
  attribute C_EN_EXT_TAP of phy : label is 0;
  attribute C_EN_REG_IF : integer;
  attribute C_EN_REG_IF of phy : label is 1;
  attribute C_EN_SSC : string;
  attribute C_EN_SSC of phy : label is "0";
  attribute C_EN_TIMEOUT_REGS : integer;
  attribute C_EN_TIMEOUT_REGS of phy : label is 0;
  attribute C_ESC_CLK_PERIOD : string;
  attribute C_ESC_CLK_PERIOD of phy : label is "50.000000";
  attribute C_ESC_TIMEOUT : integer;
  attribute C_ESC_TIMEOUT of phy : label is 25600;
  attribute C_EXAMPLE_SIMULATION : string;
  attribute C_EXAMPLE_SIMULATION of phy : label is "true";
  attribute C_HS_LINE_RATE : integer;
  attribute C_HS_LINE_RATE of phy : label is 1188;
  attribute C_HS_TIMEOUT : integer;
  attribute C_HS_TIMEOUT of phy : label is 65541;
  attribute C_IDLY_TAP : integer;
  attribute C_IDLY_TAP of phy : label is 0;
  attribute C_LPX_PERIOD : integer;
  attribute C_LPX_PERIOD of phy : label is 50;
  attribute C_RCVE_DESKEW_SEQ : string;
  attribute C_RCVE_DESKEW_SEQ of phy : label is "false";
  attribute C_SKEWCAL_FIRST_TIME : integer;
  attribute C_SKEWCAL_FIRST_TIME of phy : label is 4096;
  attribute C_SKEWCAL_PERIODIC_TIME : integer;
  attribute C_SKEWCAL_PERIODIC_TIME of phy : label is 128;
  attribute C_STABLE_CLK_PERIOD : string;
  attribute C_STABLE_CLK_PERIOD of phy : label is "5.000000";
  attribute C_TXPLL_CLKIN_PERIOD : string;
  attribute C_TXPLL_CLKIN_PERIOD of phy : label is "6.734000";
  attribute C_WAKEUP : integer;
  attribute C_WAKEUP of phy : label is 1000;
  attribute C_XMIT_FIRST_DESKEW_SEQ : string;
  attribute C_XMIT_FIRST_DESKEW_SEQ of phy : label is "false";
  attribute C_XMIT_PERIODIC_DESKEW_SEQ : string;
  attribute C_XMIT_PERIODIC_DESKEW_SEQ of phy : label is "false";
  attribute DPHY_PRESET : string;
  attribute DPHY_PRESET of phy : label is "CSI2RX_XLNX";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of phy : label is "yes";
  attribute MTBF_SYNC_STAGES : integer;
  attribute MTBF_SYNC_STAGES of phy : label is 3;
  attribute SUPPORT_LEVEL : integer;
  attribute SUPPORT_LEVEL of phy : label is 1;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of r_sync : label is "bd_7289_r_sync_0,proc_sys_reset,{}";
  attribute DowngradeIPIdentifiedWarnings of r_sync : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of r_sync : label is "proc_sys_reset,Vivado 2024.2";
  attribute AXIS_FIFO_DCNT_WIDTH : integer;
  attribute AXIS_FIFO_DCNT_WIDTH of rx : label is 11;
  attribute AXIS_FIFO_DEPTH : integer;
  attribute AXIS_FIFO_DEPTH of rx : label is 2048;
  attribute AXIS_TDATA_WIDTH : integer;
  attribute AXIS_TDATA_WIDTH of rx : label is 64;
  attribute AXIS_TDEST_WIDTH : integer;
  attribute AXIS_TDEST_WIDTH of rx : label is 4;
  attribute AXIS_TUSER_WIDTH : integer;
  attribute AXIS_TUSER_WIDTH of rx : label is 96;
  attribute CMN_INC_VFB : string;
  attribute CMN_INC_VFB of rx : label is "true";
  attribute CSI_EN_VC_SUPPORT : integer;
  attribute CSI_EN_VC_SUPPORT of rx : label is 1;
  attribute CSI_FIXED_VC : integer;
  attribute CSI_FIXED_VC of rx : label is 0;
  attribute CSI_INV_SHUTDOWN : integer;
  attribute CSI_INV_SHUTDOWN of rx : label is 1;
  attribute CSI_LANES : integer;
  attribute CSI_LANES of rx : label is 4;
  attribute CSI_OFFLOAD_NONIMAGE : integer;
  attribute CSI_OFFLOAD_NONIMAGE of rx : label is 0;
  attribute CSI_VC_OFF_0 : integer;
  attribute CSI_VC_OFF_0 of rx : label is 1;
  attribute CSI_VC_OFF_1 : integer;
  attribute CSI_VC_OFF_1 of rx : label is 2;
  attribute CSI_VC_OFF_10 : integer;
  attribute CSI_VC_OFF_10 of rx : label is 11;
  attribute CSI_VC_OFF_11 : integer;
  attribute CSI_VC_OFF_11 of rx : label is 12;
  attribute CSI_VC_OFF_12 : integer;
  attribute CSI_VC_OFF_12 of rx : label is 13;
  attribute CSI_VC_OFF_13 : integer;
  attribute CSI_VC_OFF_13 of rx : label is 14;
  attribute CSI_VC_OFF_14 : integer;
  attribute CSI_VC_OFF_14 of rx : label is 15;
  attribute CSI_VC_OFF_2 : integer;
  attribute CSI_VC_OFF_2 of rx : label is 3;
  attribute CSI_VC_OFF_3 : integer;
  attribute CSI_VC_OFF_3 of rx : label is 4;
  attribute CSI_VC_OFF_4 : integer;
  attribute CSI_VC_OFF_4 of rx : label is 5;
  attribute CSI_VC_OFF_5 : integer;
  attribute CSI_VC_OFF_5 of rx : label is 6;
  attribute CSI_VC_OFF_6 : integer;
  attribute CSI_VC_OFF_6 of rx : label is 7;
  attribute CSI_VC_OFF_7 : integer;
  attribute CSI_VC_OFF_7 of rx : label is 8;
  attribute CSI_VC_OFF_8 : integer;
  attribute CSI_VC_OFF_8 of rx : label is 9;
  attribute CSI_VC_OFF_9 : integer;
  attribute CSI_VC_OFF_9 of rx : label is 10;
  attribute C_CSI2RX_DBG : integer;
  attribute C_CSI2RX_DBG of rx : label is 0;
  attribute C_CSI_FILTER_USERDATATYPE : integer;
  attribute C_CSI_FILTER_USERDATATYPE of rx : label is 0;
  attribute C_CSI_OPT1_REGS : integer;
  attribute C_CSI_OPT1_REGS of rx : label is 0;
  attribute C_CSI_OPT2_CRC : integer;
  attribute C_CSI_OPT2_CRC of rx : label is 0;
  attribute C_CSI_OPT3_FIXEDLANES : integer;
  attribute C_CSI_OPT3_FIXEDLANES of rx : label is 1;
  attribute C_DISABLE_LITE : integer;
  attribute C_DISABLE_LITE of rx : label is 0;
  attribute C_EN_CSI_V2_0 : string;
  attribute C_EN_CSI_V2_0 of rx : label is "false";
  attribute C_EN_VCX : string;
  attribute C_EN_VCX of rx : label is "false";
  attribute C_FAMILY : string;
  attribute C_FAMILY of rx : label is "zynquplus";
  attribute C_HS_LINE_RATE of rx : label is 1188;
  attribute C_MIPI_SLV_INT : integer;
  attribute C_MIPI_SLV_INT of rx : label is 0;
  attribute C_RCVE_DESKEW_SEQ of rx : label is "false";
  attribute C_SPRT_ISP_BRIDGE : integer;
  attribute C_SPRT_ISP_BRIDGE of rx : label is 0;
  attribute C_S_AXI_ADDR_WIDTH : integer;
  attribute C_S_AXI_ADDR_WIDTH of rx : label is 8;
  attribute C_S_AXI_DATA_WIDTH : integer;
  attribute C_S_AXI_DATA_WIDTH of rx : label is 32;
  attribute DowngradeIPIdentifiedWarnings of rx : label is "yes";
  attribute AXIS_TDATA_WIDTH of vfb_0 : label is 64;
  attribute AXIS_TDEST_WIDTH of vfb_0 : label is 4;
  attribute AXIS_TUSER_WIDTH of vfb_0 : label is 96;
  attribute C_HS_LINE_RATE of vfb_0 : label is 1188;
  attribute DowngradeIPIdentifiedWarnings of vfb_0 : label is "yes";
  attribute VFB_4PXL_W : integer;
  attribute VFB_4PXL_W of vfb_0 : label is 48;
  attribute VFB_BYPASS_WC : integer;
  attribute VFB_BYPASS_WC of vfb_0 : label is 0;
  attribute VFB_DATA_TYPE : integer;
  attribute VFB_DATA_TYPE of vfb_0 : label is 44;
  attribute VFB_DCONV_OWIDTH : integer;
  attribute VFB_DCONV_OWIDTH of vfb_0 : label is 32;
  attribute VFB_EN_VCX : integer;
  attribute VFB_EN_VCX of vfb_0 : label is 0;
  attribute VFB_FIFO_DEPTH : integer;
  attribute VFB_FIFO_DEPTH of vfb_0 : label is 2048;
  attribute VFB_FIFO_WIDTH : integer;
  attribute VFB_FIFO_WIDTH of vfb_0 : label is 64;
  attribute VFB_FILTER_VC : integer;
  attribute VFB_FILTER_VC of vfb_0 : label is 0;
  attribute VFB_OP_DWIDTH : integer;
  attribute VFB_OP_DWIDTH of vfb_0 : label is 24;
  attribute VFB_OP_PIXELS : integer;
  attribute VFB_OP_PIXELS of vfb_0 : label is 2;
  attribute VFB_PXL_W : integer;
  attribute VFB_PXL_W of vfb_0 : label is 12;
  attribute VFB_PXL_W_BB : integer;
  attribute VFB_PXL_W_BB of vfb_0 : label is 16;
  attribute VFB_REQ_BUFFER : integer;
  attribute VFB_REQ_BUFFER of vfb_0 : label is 1;
  attribute VFB_REQ_REORDER : integer;
  attribute VFB_REQ_REORDER of vfb_0 : label is 1;
  attribute VFB_TU_WIDTH : integer;
  attribute VFB_TU_WIDTH of vfb_0 : label is 96;
  attribute VFB_VC : integer;
  attribute VFB_VC of vfb_0 : label is 0;
  attribute CHECK_LICENSE_TYPE of xbar : label is "bd_7289_xbar_0,axi_crossbar_v2_1_34_axi_crossbar,{}";
  attribute DowngradeIPIdentifiedWarnings of xbar : label is "yes";
  attribute X_CORE_INFO of xbar : label is "axi_crossbar_v2_1_34_axi_crossbar,Vivado 2024.2";
  attribute x_interface_info : string;
  attribute x_interface_info of clkoutphy_out : signal is "xilinx.com:signal:clock:1.0 CLK.CLKOUTPHY_OUT CLK";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clkoutphy_out : signal is "XIL_INTERFACENAME CLK.CLKOUTPHY_OUT, CLK_DOMAIN bd_7289_phy_0_clkoutphy_out, FREQ_HZ 1500000000.0, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
  attribute x_interface_info of csirxss_csi_irq : signal is "xilinx.com:signal:interrupt:1.0 INTR.CSIRXSS_CSI_IRQ INTERRUPT";
  attribute x_interface_parameter of csirxss_csi_irq : signal is "XIL_INTERFACENAME INTR.CSIRXSS_CSI_IRQ, PortWidth 1, SENSITIVITY LEVEL_HIGH";
  attribute x_interface_info of dphy_clk_200M : signal is "xilinx.com:signal:clock:1.0 CLK.DPHY_CLK_200M CLK";
  attribute x_interface_parameter of dphy_clk_200M : signal is "XIL_INTERFACENAME CLK.DPHY_CLK_200M, CLK_DOMAIN bd_7289_dphy_clk_200M, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
  attribute x_interface_info of lite_aclk : signal is "xilinx.com:signal:clock:1.0 CLK.LITE_ACLK CLK";
  attribute x_interface_parameter of lite_aclk : signal is "XIL_INTERFACENAME CLK.LITE_ACLK, ASSOCIATED_BUSIF csirxss_s_axi, ASSOCIATED_RESET lite_aresetn, CLK_DOMAIN bd_7289_lite_aclk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
  attribute x_interface_info of lite_aresetn : signal is "xilinx.com:signal:reset:1.0 RST.LITE_ARESETN RST";
  attribute x_interface_parameter of lite_aresetn : signal is "XIL_INTERFACENAME RST.LITE_ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
  attribute x_interface_info of mipi_phy_if_clk_n : signal is "xilinx.com:interface:mipi_phy:1.0 mipi_phy_if CLK_N";
  attribute x_interface_mode : string;
  attribute x_interface_mode of mipi_phy_if_clk_n : signal is "Slave";
  attribute x_interface_info of mipi_phy_if_clk_p : signal is "xilinx.com:interface:mipi_phy:1.0 mipi_phy_if CLK_P";
  attribute x_interface_info of rxbyteclkhs : signal is "xilinx.com:signal:clock:1.0 CLK.RXBYTECLKHS CLK";
  attribute x_interface_parameter of rxbyteclkhs : signal is "XIL_INTERFACENAME CLK.RXBYTECLKHS, CLK_DOMAIN bd_7289_phy_0_rxbyteclkhs, FREQ_HZ 148500000.0, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0";
  attribute x_interface_info of system_rst_out : signal is "xilinx.com:signal:reset:1.0 RST.SYSTEM_RST_OUT RST";
  attribute x_interface_parameter of system_rst_out : signal is "XIL_INTERFACENAME RST.SYSTEM_RST_OUT, INSERT_VIP 0, POLARITY ACTIVE_LOW";
  attribute x_interface_info of video_aclk : signal is "xilinx.com:signal:clock:1.0 CLK.VIDEO_ACLK CLK";
  attribute x_interface_parameter of video_aclk : signal is "XIL_INTERFACENAME CLK.VIDEO_ACLK, ASSOCIATED_BUSIF video_out, ASSOCIATED_RESET video_aresetn, CLK_DOMAIN bd_7289_video_aclk, FREQ_HZ 150000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
  attribute x_interface_info of video_aresetn : signal is "xilinx.com:signal:reset:1.0 RST.VIDEO_ARESETN RST";
  attribute x_interface_parameter of video_aresetn : signal is "XIL_INTERFACENAME RST.VIDEO_ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
  attribute x_interface_info of video_out_tlast : signal is "xilinx.com:interface:axis:1.0 video_out TLAST";
  attribute x_interface_info of video_out_tready : signal is "xilinx.com:interface:axis:1.0 video_out TREADY";
  attribute x_interface_info of video_out_tvalid : signal is "xilinx.com:interface:axis:1.0 video_out TVALID";
  attribute x_interface_info of csirxss_s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi ARADDR";
  attribute x_interface_mode of csirxss_s_axi_araddr : signal is "Slave";
  attribute x_interface_parameter of csirxss_s_axi_araddr : signal is "XIL_INTERFACENAME csirxss_s_axi, ADDR_WIDTH 13, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN bd_7289_lite_aclk, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
  attribute x_interface_info of csirxss_s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi ARPROT";
  attribute x_interface_info of csirxss_s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi ARREADY";
  attribute x_interface_info of csirxss_s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi ARVALID";
  attribute x_interface_info of csirxss_s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi AWADDR";
  attribute x_interface_info of csirxss_s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi AWPROT";
  attribute x_interface_info of csirxss_s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi AWREADY";
  attribute x_interface_info of csirxss_s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi AWVALID";
  attribute x_interface_info of csirxss_s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi BREADY";
  attribute x_interface_info of csirxss_s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi BRESP";
  attribute x_interface_info of csirxss_s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi BVALID";
  attribute x_interface_info of csirxss_s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi RDATA";
  attribute x_interface_info of csirxss_s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi RREADY";
  attribute x_interface_info of csirxss_s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi RRESP";
  attribute x_interface_info of csirxss_s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi RVALID";
  attribute x_interface_info of csirxss_s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi WDATA";
  attribute x_interface_info of csirxss_s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi WREADY";
  attribute x_interface_info of csirxss_s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi WSTRB";
  attribute x_interface_info of csirxss_s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi WVALID";
  attribute x_interface_info of mipi_phy_if_data_n : signal is "xilinx.com:interface:mipi_phy:1.0 mipi_phy_if DATA_N";
  attribute x_interface_info of mipi_phy_if_data_p : signal is "xilinx.com:interface:mipi_phy:1.0 mipi_phy_if DATA_P";
  attribute x_interface_info of video_out_tdata : signal is "xilinx.com:interface:axis:1.0 video_out TDATA";
  attribute x_interface_mode of video_out_tdata : signal is "Master";
  attribute x_interface_parameter of video_out_tdata : signal is "XIL_INTERFACENAME video_out, CLK_DOMAIN bd_7289_video_aclk, FREQ_HZ 150000000, HAS_TKEEP 0, HAS_TLAST 1, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 3, TDEST_WIDTH 10, TID_WIDTH 0, TUSER_WIDTH 96";
  attribute x_interface_info of video_out_tdest : signal is "xilinx.com:interface:axis:1.0 video_out TDEST";
  attribute x_interface_info of video_out_tuser : signal is "xilinx.com:interface:axis:1.0 video_out TUSER";
begin
  clkoutphy_out <= \<const0>\;
  csirxss_csi_irq <= \<const0>\;
  csirxss_s_axi_bresp(1) <= \<const0>\;
  csirxss_s_axi_bresp(0) <= \<const0>\;
  csirxss_s_axi_rresp(1) <= \<const0>\;
  csirxss_s_axi_rresp(0) <= \<const0>\;
  frame_rcvd_pulse_out <= \<const0>\;
  pll_lock_out <= \<const0>\;
  rxbyteclkhs <= \<const0>\;
  system_rst_out <= \<const0>\;
  video_out_tdest(9) <= \<const0>\;
  video_out_tdest(8) <= \<const0>\;
  video_out_tdest(7) <= \<const0>\;
  video_out_tdest(6) <= \<const0>\;
  video_out_tdest(5) <= \<const0>\;
  video_out_tdest(4) <= \<const0>\;
  video_out_tdest(3) <= \<const0>\;
  video_out_tdest(2) <= \<const0>\;
  video_out_tdest(1) <= \<const0>\;
  video_out_tdest(0) <= \<const0>\;
  video_out_tuser(95) <= \<const0>\;
  video_out_tuser(94) <= \<const0>\;
  video_out_tuser(93) <= \<const0>\;
  video_out_tuser(92) <= \<const0>\;
  video_out_tuser(91) <= \<const0>\;
  video_out_tuser(90) <= \<const0>\;
  video_out_tuser(89) <= \<const0>\;
  video_out_tuser(88) <= \<const0>\;
  video_out_tuser(87) <= \<const0>\;
  video_out_tuser(86) <= \<const0>\;
  video_out_tuser(85) <= \<const0>\;
  video_out_tuser(84) <= \<const0>\;
  video_out_tuser(83) <= \<const0>\;
  video_out_tuser(82) <= \<const0>\;
  video_out_tuser(81) <= \<const0>\;
  video_out_tuser(80) <= \<const0>\;
  video_out_tuser(79) <= \<const0>\;
  video_out_tuser(78) <= \<const0>\;
  video_out_tuser(77) <= \<const0>\;
  video_out_tuser(76) <= \<const0>\;
  video_out_tuser(75) <= \<const0>\;
  video_out_tuser(74) <= \<const0>\;
  video_out_tuser(73) <= \<const0>\;
  video_out_tuser(72) <= \<const0>\;
  video_out_tuser(71) <= \<const0>\;
  video_out_tuser(70) <= \<const0>\;
  video_out_tuser(69 downto 64) <= \^video_out_tuser\(69 downto 64);
  video_out_tuser(63) <= \<const0>\;
  video_out_tuser(62) <= \<const0>\;
  video_out_tuser(61) <= \<const0>\;
  video_out_tuser(60) <= \<const0>\;
  video_out_tuser(59) <= \<const0>\;
  video_out_tuser(58) <= \<const0>\;
  video_out_tuser(57) <= \<const0>\;
  video_out_tuser(56) <= \<const0>\;
  video_out_tuser(55) <= \<const0>\;
  video_out_tuser(54) <= \<const0>\;
  video_out_tuser(53) <= \<const0>\;
  video_out_tuser(52) <= \<const0>\;
  video_out_tuser(51) <= \<const0>\;
  video_out_tuser(50) <= \<const0>\;
  video_out_tuser(49) <= \<const0>\;
  video_out_tuser(48) <= \<const0>\;
  video_out_tuser(47) <= \<const0>\;
  video_out_tuser(46) <= \<const0>\;
  video_out_tuser(45) <= \<const0>\;
  video_out_tuser(44) <= \<const0>\;
  video_out_tuser(43) <= \<const0>\;
  video_out_tuser(42) <= \<const0>\;
  video_out_tuser(41) <= \<const0>\;
  video_out_tuser(40) <= \<const0>\;
  video_out_tuser(39) <= \<const0>\;
  video_out_tuser(38) <= \<const0>\;
  video_out_tuser(37) <= \<const0>\;
  video_out_tuser(36) <= \<const0>\;
  video_out_tuser(35) <= \<const0>\;
  video_out_tuser(34) <= \<const0>\;
  video_out_tuser(33) <= \<const0>\;
  video_out_tuser(32) <= \<const0>\;
  video_out_tuser(31) <= \<const0>\;
  video_out_tuser(30) <= \<const0>\;
  video_out_tuser(29) <= \<const0>\;
  video_out_tuser(28) <= \<const0>\;
  video_out_tuser(27) <= \<const0>\;
  video_out_tuser(26) <= \<const0>\;
  video_out_tuser(25) <= \<const0>\;
  video_out_tuser(24) <= \<const0>\;
  video_out_tuser(23) <= \<const0>\;
  video_out_tuser(22) <= \<const0>\;
  video_out_tuser(21) <= \<const0>\;
  video_out_tuser(20) <= \<const0>\;
  video_out_tuser(19) <= \<const0>\;
  video_out_tuser(18) <= \<const0>\;
  video_out_tuser(17) <= \<const0>\;
  video_out_tuser(16) <= \<const0>\;
  video_out_tuser(15) <= \<const0>\;
  video_out_tuser(14) <= \<const0>\;
  video_out_tuser(13) <= \<const0>\;
  video_out_tuser(12) <= \<const0>\;
  video_out_tuser(11) <= \<const0>\;
  video_out_tuser(10) <= \<const0>\;
  video_out_tuser(9) <= \<const0>\;
  video_out_tuser(8) <= \<const0>\;
  video_out_tuser(7) <= \<const0>\;
  video_out_tuser(6) <= \<const0>\;
  video_out_tuser(5) <= \<const0>\;
  video_out_tuser(4) <= \<const0>\;
  video_out_tuser(3) <= \<const0>\;
  video_out_tuser(2) <= \<const0>\;
  video_out_tuser(1) <= \<const0>\;
  video_out_tuser(0) <= \^video_out_tuser\(0);
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
phy: entity work.design_1_Vsp_core_0_0_bd_7289_phy_0
     port map (
      cl_enable => phy_rx_mipi_ppi_if_CL_ENABLE,
      cl_rxclkactivehs => NLW_phy_cl_rxclkactivehs_UNCONNECTED,
      cl_rxulpsclknot => NLW_phy_cl_rxulpsclknot_UNCONNECTED,
      cl_stopstate => phy_rx_mipi_ppi_if_CL_STOPSTATE,
      cl_ulpsactivenot => NLW_phy_cl_ulpsactivenot_UNCONNECTED,
      clk_rxn => mipi_phy_if_clk_n,
      clk_rxp => mipi_phy_if_clk_p,
      clkoutphy_out => NLW_phy_clkoutphy_out_UNCONNECTED,
      core_clk => dphy_clk_200M,
      core_rst => r_sync_peripheral_reset,
      data_rxn(3 downto 0) => mipi_phy_if_data_n(3 downto 0),
      data_rxp(3 downto 0) => mipi_phy_if_data_p(3 downto 0),
      dl0_enable => '0',
      dl0_errcontrol => NLW_phy_dl0_errcontrol_UNCONNECTED,
      dl0_erresc => NLW_phy_dl0_erresc_UNCONNECTED,
      dl0_errsoths => phy_rx_mipi_ppi_if_DL0_ERRSOTHS,
      dl0_errsotsynchs => phy_rx_mipi_ppi_if_DL0_ERRSOTSYNCHS,
      dl0_errsyncesc => NLW_phy_dl0_errsyncesc_UNCONNECTED,
      dl0_forcerxmode => '0',
      dl0_rxactivehs => phy_rx_mipi_ppi_if_DL0_RXACTIVEHS,
      dl0_rxclkesc => NLW_phy_dl0_rxclkesc_UNCONNECTED,
      dl0_rxdataesc(7 downto 0) => NLW_phy_dl0_rxdataesc_UNCONNECTED(7 downto 0),
      dl0_rxdatahs(7 downto 0) => phy_rx_mipi_ppi_if_DL0_RXDATAHS(7 downto 0),
      dl0_rxlpdtesc => NLW_phy_dl0_rxlpdtesc_UNCONNECTED,
      dl0_rxsynchs => phy_rx_mipi_ppi_if_DL0_RXSYNCHS,
      dl0_rxtriggeresc(3 downto 0) => NLW_phy_dl0_rxtriggeresc_UNCONNECTED(3 downto 0),
      dl0_rxulpsesc => NLW_phy_dl0_rxulpsesc_UNCONNECTED,
      dl0_rxvalidesc => NLW_phy_dl0_rxvalidesc_UNCONNECTED,
      dl0_rxvalidhs => phy_rx_mipi_ppi_if_DL0_RXVALIDHS,
      dl0_stopstate => phy_rx_mipi_ppi_if_DL0_STOPSTATE,
      dl0_ulpsactivenot => NLW_phy_dl0_ulpsactivenot_UNCONNECTED,
      dl1_enable => '0',
      dl1_errcontrol => NLW_phy_dl1_errcontrol_UNCONNECTED,
      dl1_erresc => NLW_phy_dl1_erresc_UNCONNECTED,
      dl1_errsoths => phy_rx_mipi_ppi_if_DL1_ERRSOTHS,
      dl1_errsotsynchs => phy_rx_mipi_ppi_if_DL1_ERRSOTSYNCHS,
      dl1_errsyncesc => NLW_phy_dl1_errsyncesc_UNCONNECTED,
      dl1_forcerxmode => '0',
      dl1_rxactivehs => phy_rx_mipi_ppi_if_DL1_RXACTIVEHS,
      dl1_rxclkesc => NLW_phy_dl1_rxclkesc_UNCONNECTED,
      dl1_rxdataesc(7 downto 0) => NLW_phy_dl1_rxdataesc_UNCONNECTED(7 downto 0),
      dl1_rxdatahs(7 downto 0) => phy_rx_mipi_ppi_if_DL1_RXDATAHS(7 downto 0),
      dl1_rxlpdtesc => NLW_phy_dl1_rxlpdtesc_UNCONNECTED,
      dl1_rxsynchs => phy_rx_mipi_ppi_if_DL1_RXSYNCHS,
      dl1_rxtriggeresc(3 downto 0) => NLW_phy_dl1_rxtriggeresc_UNCONNECTED(3 downto 0),
      dl1_rxulpsesc => NLW_phy_dl1_rxulpsesc_UNCONNECTED,
      dl1_rxvalidesc => NLW_phy_dl1_rxvalidesc_UNCONNECTED,
      dl1_rxvalidhs => phy_rx_mipi_ppi_if_DL1_RXVALIDHS,
      dl1_stopstate => phy_rx_mipi_ppi_if_DL1_STOPSTATE,
      dl1_ulpsactivenot => NLW_phy_dl1_ulpsactivenot_UNCONNECTED,
      dl2_enable => '0',
      dl2_errcontrol => NLW_phy_dl2_errcontrol_UNCONNECTED,
      dl2_erresc => NLW_phy_dl2_erresc_UNCONNECTED,
      dl2_errsoths => phy_rx_mipi_ppi_if_DL2_ERRSOTHS,
      dl2_errsotsynchs => phy_rx_mipi_ppi_if_DL2_ERRSOTSYNCHS,
      dl2_errsyncesc => NLW_phy_dl2_errsyncesc_UNCONNECTED,
      dl2_forcerxmode => '0',
      dl2_rxactivehs => phy_rx_mipi_ppi_if_DL2_RXACTIVEHS,
      dl2_rxclkesc => NLW_phy_dl2_rxclkesc_UNCONNECTED,
      dl2_rxdataesc(7 downto 0) => NLW_phy_dl2_rxdataesc_UNCONNECTED(7 downto 0),
      dl2_rxdatahs(7 downto 0) => phy_rx_mipi_ppi_if_DL2_RXDATAHS(7 downto 0),
      dl2_rxlpdtesc => NLW_phy_dl2_rxlpdtesc_UNCONNECTED,
      dl2_rxsynchs => phy_rx_mipi_ppi_if_DL2_RXSYNCHS,
      dl2_rxtriggeresc(3 downto 0) => NLW_phy_dl2_rxtriggeresc_UNCONNECTED(3 downto 0),
      dl2_rxulpsesc => NLW_phy_dl2_rxulpsesc_UNCONNECTED,
      dl2_rxvalidesc => NLW_phy_dl2_rxvalidesc_UNCONNECTED,
      dl2_rxvalidhs => phy_rx_mipi_ppi_if_DL2_RXVALIDHS,
      dl2_stopstate => phy_rx_mipi_ppi_if_DL2_STOPSTATE,
      dl2_ulpsactivenot => NLW_phy_dl2_ulpsactivenot_UNCONNECTED,
      dl3_enable => '0',
      dl3_errcontrol => NLW_phy_dl3_errcontrol_UNCONNECTED,
      dl3_erresc => NLW_phy_dl3_erresc_UNCONNECTED,
      dl3_errsoths => phy_rx_mipi_ppi_if_DL3_ERRSOTHS,
      dl3_errsotsynchs => phy_rx_mipi_ppi_if_DL3_ERRSOTSYNCHS,
      dl3_errsyncesc => NLW_phy_dl3_errsyncesc_UNCONNECTED,
      dl3_forcerxmode => '0',
      dl3_rxactivehs => phy_rx_mipi_ppi_if_DL3_RXACTIVEHS,
      dl3_rxclkesc => NLW_phy_dl3_rxclkesc_UNCONNECTED,
      dl3_rxdataesc(7 downto 0) => NLW_phy_dl3_rxdataesc_UNCONNECTED(7 downto 0),
      dl3_rxdatahs(7 downto 0) => phy_rx_mipi_ppi_if_DL3_RXDATAHS(7 downto 0),
      dl3_rxlpdtesc => NLW_phy_dl3_rxlpdtesc_UNCONNECTED,
      dl3_rxsynchs => phy_rx_mipi_ppi_if_DL3_RXSYNCHS,
      dl3_rxtriggeresc(3 downto 0) => NLW_phy_dl3_rxtriggeresc_UNCONNECTED(3 downto 0),
      dl3_rxulpsesc => NLW_phy_dl3_rxulpsesc_UNCONNECTED,
      dl3_rxvalidesc => NLW_phy_dl3_rxvalidesc_UNCONNECTED,
      dl3_rxvalidhs => phy_rx_mipi_ppi_if_DL3_RXVALIDHS,
      dl3_stopstate => phy_rx_mipi_ppi_if_DL3_STOPSTATE,
      dl3_ulpsactivenot => NLW_phy_dl3_ulpsactivenot_UNCONNECTED,
      init_done => NLW_phy_init_done_UNCONNECTED,
      pll_lock_out => NLW_phy_pll_lock_out_UNCONNECTED,
      rxbyteclkhs => phy_n_0,
      s_axi_aclk => '0',
      s_axi_araddr(6 downto 2) => xbar_M01_AXI_ARADDR(6 downto 2),
      s_axi_araddr(1 downto 0) => B"00",
      s_axi_aresetn => video_aresetn,
      s_axi_arready => xbar_M01_AXI_ARREADY,
      s_axi_arvalid => xbar_M01_AXI_ARVALID,
      s_axi_awaddr(6 downto 2) => xbar_M01_AXI_AWADDR(6 downto 2),
      s_axi_awaddr(1 downto 0) => B"00",
      s_axi_awready => xbar_M01_AXI_AWREADY,
      s_axi_awvalid => xbar_M01_AXI_AWVALID,
      s_axi_bready => xbar_M01_AXI_BREADY,
      s_axi_bresp(1 downto 0) => NLW_phy_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => xbar_M01_AXI_BVALID,
      s_axi_rdata(31 downto 0) => xbar_M01_AXI_RDATA(31 downto 0),
      s_axi_rready => xbar_M01_AXI_RREADY,
      s_axi_rresp(1 downto 0) => NLW_phy_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => xbar_M01_AXI_RVALID,
      s_axi_wdata(31 downto 0) => xbar_M01_AXI_WDATA(63 downto 32),
      s_axi_wready => xbar_M01_AXI_WREADY,
      s_axi_wstrb(3 downto 0) => B"0000",
      s_axi_wvalid => xbar_M01_AXI_WVALID,
      system_rst_out => NLW_phy_system_rst_out_UNCONNECTED
    );
r_sync: entity work.design_1_Vsp_core_0_0_bd_7289_r_sync_0
     port map (
      aux_reset_in => '1',
      bus_struct_reset(0) => NLW_r_sync_bus_struct_reset_UNCONNECTED(0),
      dcm_locked => '1',
      ext_reset_in => video_aresetn,
      interconnect_aresetn(0) => NLW_r_sync_interconnect_aresetn_UNCONNECTED(0),
      mb_debug_sys_rst => '0',
      mb_reset => NLW_r_sync_mb_reset_UNCONNECTED,
      peripheral_aresetn(0) => NLW_r_sync_peripheral_aresetn_UNCONNECTED(0),
      peripheral_reset(0) => r_sync_peripheral_reset,
      slowest_sync_clk => dphy_clk_200M
    );
rx: entity work.design_1_Vsp_core_0_0_bd_7289_rx_0
     port map (
      cl_enable => phy_rx_mipi_ppi_if_CL_ENABLE,
      cl_rxulpsclknot => '1',
      cl_stopstate => phy_rx_mipi_ppi_if_CL_STOPSTATE,
      core_clk => '0',
      core_men_ack_vfb => '1',
      core_men_vfb => NLW_rx_core_men_vfb_UNCONNECTED,
      dl0_errcontrol => '0',
      dl0_erresc => '0',
      dl0_errsoths => phy_rx_mipi_ppi_if_DL0_ERRSOTHS,
      dl0_errsotsynchs => phy_rx_mipi_ppi_if_DL0_ERRSOTSYNCHS,
      dl0_rxactivehs => phy_rx_mipi_ppi_if_DL0_RXACTIVEHS,
      dl0_rxbyteclkhs => phy_n_0,
      dl0_rxdatahs(7 downto 0) => phy_rx_mipi_ppi_if_DL0_RXDATAHS(7 downto 0),
      dl0_rxsynchs => phy_rx_mipi_ppi_if_DL0_RXSYNCHS,
      dl0_rxulpmesc => '0',
      dl0_rxvalidhs => phy_rx_mipi_ppi_if_DL0_RXVALIDHS,
      dl0_shutdown => NLW_rx_dl0_shutdown_UNCONNECTED,
      dl0_stopstate => phy_rx_mipi_ppi_if_DL0_STOPSTATE,
      dl1_errcontrol => '0',
      dl1_erresc => '0',
      dl1_errsoths => phy_rx_mipi_ppi_if_DL1_ERRSOTHS,
      dl1_errsotsynchs => phy_rx_mipi_ppi_if_DL1_ERRSOTSYNCHS,
      dl1_rxactivehs => phy_rx_mipi_ppi_if_DL1_RXACTIVEHS,
      dl1_rxbyteclkhs => '0',
      dl1_rxdatahs(7 downto 0) => phy_rx_mipi_ppi_if_DL1_RXDATAHS(7 downto 0),
      dl1_rxsynchs => phy_rx_mipi_ppi_if_DL1_RXSYNCHS,
      dl1_rxulpmesc => '0',
      dl1_rxvalidhs => phy_rx_mipi_ppi_if_DL1_RXVALIDHS,
      dl1_shutdown => NLW_rx_dl1_shutdown_UNCONNECTED,
      dl1_stopstate => phy_rx_mipi_ppi_if_DL1_STOPSTATE,
      dl2_errcontrol => '0',
      dl2_erresc => '0',
      dl2_errsoths => phy_rx_mipi_ppi_if_DL2_ERRSOTHS,
      dl2_errsotsynchs => phy_rx_mipi_ppi_if_DL2_ERRSOTSYNCHS,
      dl2_rxactivehs => phy_rx_mipi_ppi_if_DL2_RXACTIVEHS,
      dl2_rxbyteclkhs => '0',
      dl2_rxdatahs(7 downto 0) => phy_rx_mipi_ppi_if_DL2_RXDATAHS(7 downto 0),
      dl2_rxsynchs => phy_rx_mipi_ppi_if_DL2_RXSYNCHS,
      dl2_rxulpmesc => '0',
      dl2_rxvalidhs => phy_rx_mipi_ppi_if_DL2_RXVALIDHS,
      dl2_shutdown => NLW_rx_dl2_shutdown_UNCONNECTED,
      dl2_stopstate => phy_rx_mipi_ppi_if_DL2_STOPSTATE,
      dl3_errcontrol => '0',
      dl3_erresc => '0',
      dl3_errsoths => phy_rx_mipi_ppi_if_DL3_ERRSOTHS,
      dl3_errsotsynchs => phy_rx_mipi_ppi_if_DL3_ERRSOTSYNCHS,
      dl3_rxactivehs => phy_rx_mipi_ppi_if_DL3_RXACTIVEHS,
      dl3_rxbyteclkhs => '0',
      dl3_rxdatahs(7 downto 0) => phy_rx_mipi_ppi_if_DL3_RXDATAHS(7 downto 0),
      dl3_rxsynchs => phy_rx_mipi_ppi_if_DL3_RXSYNCHS,
      dl3_rxulpmesc => '0',
      dl3_rxvalidhs => phy_rx_mipi_ppi_if_DL3_RXVALIDHS,
      dl3_shutdown => NLW_rx_dl3_shutdown_UNCONNECTED,
      dl3_stopstate => phy_rx_mipi_ppi_if_DL3_STOPSTATE,
      frame_rcvd_pulse_out => NLW_rx_frame_rcvd_pulse_out_UNCONNECTED,
      interrupt => NLW_rx_interrupt_UNCONNECTED,
      m_axis_aclk => '0',
      m_axis_aresetn => '0',
      m_axis_tdata(63 downto 0) => rx_m_axis_TDATA(63 downto 0),
      m_axis_tdest(3 downto 0) => NLW_rx_m_axis_tdest_UNCONNECTED(3 downto 0),
      m_axis_tkeep(7 downto 0) => rx_m_axis_TKEEP(7 downto 0),
      m_axis_tlast => rx_m_axis_TLAST,
      m_axis_tready => rx_m_axis_TREADY,
      m_axis_tuser(95 downto 70) => NLW_rx_m_axis_tuser_UNCONNECTED(95 downto 70),
      m_axis_tuser(69 downto 64) => rx_m_axis_TUSER(69 downto 64),
      m_axis_tuser(63 downto 2) => NLW_rx_m_axis_tuser_UNCONNECTED(63 downto 2),
      m_axis_tuser(1 downto 0) => rx_m_axis_TUSER(1 downto 0),
      m_axis_tvalid => rx_m_axis_TVALID,
      mdt_tr => '0',
      mdt_tv => '0',
      s_axi_aclk => dphy_clk_200M,
      s_axi_araddr(7) => xbar_n_169,
      s_axi_araddr(6) => xbar_n_170,
      s_axi_araddr(5) => xbar_n_171,
      s_axi_araddr(4) => xbar_n_172,
      s_axi_araddr(3) => xbar_n_173,
      s_axi_araddr(2) => xbar_n_174,
      s_axi_araddr(1 downto 0) => B"00",
      s_axi_aresetn => video_aresetn,
      s_axi_arready => xbar_M00_AXI_ARREADY,
      s_axi_arvalid => xbar_n_184,
      s_axi_awaddr(7) => xbar_n_59,
      s_axi_awaddr(6) => xbar_n_60,
      s_axi_awaddr(5) => xbar_n_61,
      s_axi_awaddr(4) => xbar_n_62,
      s_axi_awaddr(3) => xbar_n_63,
      s_axi_awaddr(2) => xbar_n_64,
      s_axi_awaddr(1 downto 0) => B"00",
      s_axi_awready => xbar_M00_AXI_AWREADY,
      s_axi_awvalid => xbar_n_74,
      s_axi_bready => xbar_n_150,
      s_axi_bresp(1 downto 0) => NLW_rx_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => xbar_M00_AXI_BVALID,
      s_axi_rdata(31 downto 0) => xbar_M00_AXI_RDATA(31 downto 0),
      s_axi_rready => xbar_n_186,
      s_axi_rresp(1 downto 0) => NLW_rx_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => xbar_M00_AXI_RVALID,
      s_axi_wdata(31) => xbar_n_107,
      s_axi_wdata(30) => xbar_n_108,
      s_axi_wdata(29) => xbar_n_109,
      s_axi_wdata(28) => xbar_n_110,
      s_axi_wdata(27) => xbar_n_111,
      s_axi_wdata(26 downto 24) => B"000",
      s_axi_wdata(23) => xbar_n_115,
      s_axi_wdata(22) => xbar_n_116,
      s_axi_wdata(21) => xbar_n_117,
      s_axi_wdata(20) => xbar_n_118,
      s_axi_wdata(19) => xbar_n_119,
      s_axi_wdata(18) => xbar_n_120,
      s_axi_wdata(17) => xbar_n_121,
      s_axi_wdata(16) => xbar_n_122,
      s_axi_wdata(15) => xbar_n_123,
      s_axi_wdata(14) => xbar_n_124,
      s_axi_wdata(13) => xbar_n_125,
      s_axi_wdata(12) => xbar_n_126,
      s_axi_wdata(11) => xbar_n_127,
      s_axi_wdata(10) => xbar_n_128,
      s_axi_wdata(9) => xbar_n_129,
      s_axi_wdata(8) => xbar_n_130,
      s_axi_wdata(7) => xbar_n_131,
      s_axi_wdata(6) => xbar_n_132,
      s_axi_wdata(5) => xbar_n_133,
      s_axi_wdata(4) => xbar_n_134,
      s_axi_wdata(3) => xbar_n_135,
      s_axi_wdata(2) => xbar_n_136,
      s_axi_wdata(1) => xbar_n_137,
      s_axi_wdata(0) => xbar_n_138,
      s_axi_wready => xbar_M00_AXI_WREADY,
      s_axi_wstrb(3 downto 0) => B"0000",
      s_axi_wvalid => xbar_n_148,
      sdt_tr => '0',
      sdt_tv => '0',
      vfb_full => '0',
      vfb_tr => '0',
      vfb_tv => '0',
      vfb_wc_full => '0',
      video_aclk => '0'
    );
vfb_0: entity work.design_1_Vsp_core_0_0_bd_7289_vfb_0_0
     port map (
      core_men_ack_vfb => NLW_vfb_0_core_men_ack_vfb_UNCONNECTED,
      core_men_vfb => '0',
      mdt_tr => NLW_vfb_0_mdt_tr_UNCONNECTED,
      mdt_tv => NLW_vfb_0_mdt_tv_UNCONNECTED,
      s_axis_aclk => '0',
      s_axis_aresetn => '0',
      s_axis_tdata(63 downto 0) => rx_m_axis_TDATA(63 downto 0),
      s_axis_tdest(3 downto 0) => B"0000",
      s_axis_tkeep(7 downto 0) => rx_m_axis_TKEEP(7 downto 0),
      s_axis_tlast => rx_m_axis_TLAST,
      s_axis_tready => rx_m_axis_TREADY,
      s_axis_tuser(95 downto 70) => B"00000000000000000000000000",
      s_axis_tuser(69 downto 64) => rx_m_axis_TUSER(69 downto 64),
      s_axis_tuser(63 downto 2) => B"00000000000000000000000000000000000000000000000000000000000000",
      s_axis_tuser(1 downto 0) => rx_m_axis_TUSER(1 downto 0),
      s_axis_tvalid => rx_m_axis_TVALID,
      sdt_tr => NLW_vfb_0_sdt_tr_UNCONNECTED,
      sdt_tv => NLW_vfb_0_sdt_tv_UNCONNECTED,
      vfb_arstn => video_aresetn,
      vfb_clk => dphy_clk_200M,
      vfb_data(23 downto 0) => video_out_tdata(23 downto 0),
      vfb_eol => video_out_tlast,
      vfb_full => NLW_vfb_0_vfb_full_UNCONNECTED,
      vfb_ready => '1',
      vfb_sof(95 downto 70) => NLW_vfb_0_vfb_sof_UNCONNECTED(95 downto 70),
      vfb_sof(69 downto 64) => \^video_out_tuser\(69 downto 64),
      vfb_sof(63 downto 1) => NLW_vfb_0_vfb_sof_UNCONNECTED(63 downto 1),
      vfb_sof(0) => \^video_out_tuser\(0),
      vfb_tr => NLW_vfb_0_vfb_tr_UNCONNECTED,
      vfb_tv => NLW_vfb_0_vfb_tv_UNCONNECTED,
      vfb_valid => video_out_tvalid,
      vfb_vcdt(9 downto 0) => NLW_vfb_0_vfb_vcdt_UNCONNECTED(9 downto 0),
      vfb_wc_full => NLW_vfb_0_vfb_wc_full_UNCONNECTED
    );
xbar: entity work.design_1_Vsp_core_0_0_bd_7289_xbar_0
     port map (
      aclk => dphy_clk_200M,
      aresetn => video_aresetn,
      m_axi_araddr(25 downto 20) => NLW_xbar_m_axi_araddr_UNCONNECTED(25 downto 20),
      m_axi_araddr(19 downto 15) => xbar_M01_AXI_ARADDR(6 downto 2),
      m_axi_araddr(14 downto 8) => NLW_xbar_m_axi_araddr_UNCONNECTED(14 downto 8),
      m_axi_araddr(7) => xbar_n_169,
      m_axi_araddr(6) => xbar_n_170,
      m_axi_araddr(5) => xbar_n_171,
      m_axi_araddr(4) => xbar_n_172,
      m_axi_araddr(3) => xbar_n_173,
      m_axi_araddr(2) => xbar_n_174,
      m_axi_araddr(1 downto 0) => NLW_xbar_m_axi_araddr_UNCONNECTED(1 downto 0),
      m_axi_arprot(5 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(5 downto 0),
      m_axi_arready(1) => xbar_M01_AXI_ARREADY,
      m_axi_arready(0) => xbar_M00_AXI_ARREADY,
      m_axi_arvalid(1) => xbar_M01_AXI_ARVALID,
      m_axi_arvalid(0) => xbar_n_184,
      m_axi_awaddr(25 downto 20) => NLW_xbar_m_axi_awaddr_UNCONNECTED(25 downto 20),
      m_axi_awaddr(19 downto 15) => xbar_M01_AXI_AWADDR(6 downto 2),
      m_axi_awaddr(14 downto 8) => NLW_xbar_m_axi_awaddr_UNCONNECTED(14 downto 8),
      m_axi_awaddr(7) => xbar_n_59,
      m_axi_awaddr(6) => xbar_n_60,
      m_axi_awaddr(5) => xbar_n_61,
      m_axi_awaddr(4) => xbar_n_62,
      m_axi_awaddr(3) => xbar_n_63,
      m_axi_awaddr(2) => xbar_n_64,
      m_axi_awaddr(1 downto 0) => NLW_xbar_m_axi_awaddr_UNCONNECTED(1 downto 0),
      m_axi_awprot(5 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(5 downto 0),
      m_axi_awready(1) => xbar_M01_AXI_AWREADY,
      m_axi_awready(0) => xbar_M00_AXI_AWREADY,
      m_axi_awvalid(1) => xbar_M01_AXI_AWVALID,
      m_axi_awvalid(0) => xbar_n_74,
      m_axi_bready(1) => xbar_M01_AXI_BREADY,
      m_axi_bready(0) => xbar_n_150,
      m_axi_bresp(3 downto 0) => B"0000",
      m_axi_bvalid(1) => xbar_M01_AXI_BVALID,
      m_axi_bvalid(0) => xbar_M00_AXI_BVALID,
      m_axi_rdata(63 downto 32) => xbar_M01_AXI_RDATA(31 downto 0),
      m_axi_rdata(31 downto 0) => xbar_M00_AXI_RDATA(31 downto 0),
      m_axi_rready(1) => xbar_M01_AXI_RREADY,
      m_axi_rready(0) => xbar_n_186,
      m_axi_rresp(3 downto 0) => B"0000",
      m_axi_rvalid(1) => xbar_M01_AXI_RVALID,
      m_axi_rvalid(0) => xbar_M00_AXI_RVALID,
      m_axi_wdata(63 downto 32) => xbar_M01_AXI_WDATA(63 downto 32),
      m_axi_wdata(31) => xbar_n_107,
      m_axi_wdata(30) => xbar_n_108,
      m_axi_wdata(29) => xbar_n_109,
      m_axi_wdata(28) => xbar_n_110,
      m_axi_wdata(27) => xbar_n_111,
      m_axi_wdata(26 downto 24) => NLW_xbar_m_axi_wdata_UNCONNECTED(26 downto 24),
      m_axi_wdata(23) => xbar_n_115,
      m_axi_wdata(22) => xbar_n_116,
      m_axi_wdata(21) => xbar_n_117,
      m_axi_wdata(20) => xbar_n_118,
      m_axi_wdata(19) => xbar_n_119,
      m_axi_wdata(18) => xbar_n_120,
      m_axi_wdata(17) => xbar_n_121,
      m_axi_wdata(16) => xbar_n_122,
      m_axi_wdata(15) => xbar_n_123,
      m_axi_wdata(14) => xbar_n_124,
      m_axi_wdata(13) => xbar_n_125,
      m_axi_wdata(12) => xbar_n_126,
      m_axi_wdata(11) => xbar_n_127,
      m_axi_wdata(10) => xbar_n_128,
      m_axi_wdata(9) => xbar_n_129,
      m_axi_wdata(8) => xbar_n_130,
      m_axi_wdata(7) => xbar_n_131,
      m_axi_wdata(6) => xbar_n_132,
      m_axi_wdata(5) => xbar_n_133,
      m_axi_wdata(4) => xbar_n_134,
      m_axi_wdata(3) => xbar_n_135,
      m_axi_wdata(2) => xbar_n_136,
      m_axi_wdata(1) => xbar_n_137,
      m_axi_wdata(0) => xbar_n_138,
      m_axi_wready(1) => xbar_M01_AXI_WREADY,
      m_axi_wready(0) => xbar_M00_AXI_WREADY,
      m_axi_wstrb(7 downto 0) => NLW_xbar_m_axi_wstrb_UNCONNECTED(7 downto 0),
      m_axi_wvalid(1) => xbar_M01_AXI_WVALID,
      m_axi_wvalid(0) => xbar_n_148,
      s_axi_araddr(12) => csirxss_s_axi_araddr(12),
      s_axi_araddr(11 downto 8) => B"0000",
      s_axi_araddr(7 downto 2) => csirxss_s_axi_araddr(7 downto 2),
      s_axi_araddr(1 downto 0) => B"00",
      s_axi_arprot(2 downto 0) => B"000",
      s_axi_arready(0) => csirxss_s_axi_arready(0),
      s_axi_arvalid(0) => csirxss_s_axi_arvalid(0),
      s_axi_awaddr(12) => csirxss_s_axi_awaddr(12),
      s_axi_awaddr(11 downto 8) => B"0000",
      s_axi_awaddr(7 downto 2) => csirxss_s_axi_awaddr(7 downto 2),
      s_axi_awaddr(1 downto 0) => B"00",
      s_axi_awprot(2 downto 0) => B"000",
      s_axi_awready(0) => csirxss_s_axi_awready(0),
      s_axi_awvalid(0) => csirxss_s_axi_awvalid(0),
      s_axi_bready(0) => csirxss_s_axi_bready(0),
      s_axi_bresp(1 downto 0) => NLW_xbar_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid(0) => csirxss_s_axi_bvalid(0),
      s_axi_rdata(31 downto 0) => csirxss_s_axi_rdata(31 downto 0),
      s_axi_rready(0) => csirxss_s_axi_rready(0),
      s_axi_rresp(1 downto 0) => NLW_xbar_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid(0) => csirxss_s_axi_rvalid(0),
      s_axi_wdata(31 downto 0) => csirxss_s_axi_wdata(31 downto 0),
      s_axi_wready(0) => csirxss_s_axi_wready(0),
      s_axi_wstrb(3 downto 0) => B"1111",
      s_axi_wvalid(0) => csirxss_s_axi_wvalid(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Mipirx_xlnx_comb_w4_r1188 is
  port (
    lite_aclk : in STD_LOGIC;
    lite_aresetn : in STD_LOGIC;
    dphy_clk_200M : in STD_LOGIC;
    rxbyteclkhs : out STD_LOGIC;
    clkoutphy_out : out STD_LOGIC;
    system_rst_out : out STD_LOGIC;
    pll_lock_out : out STD_LOGIC;
    csirxss_csi_irq : out STD_LOGIC;
    video_aclk : in STD_LOGIC;
    video_aresetn : in STD_LOGIC;
    frame_rcvd_pulse_out : out STD_LOGIC;
    csirxss_s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
    csirxss_s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    csirxss_s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    csirxss_s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    csirxss_s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    csirxss_s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
    csirxss_s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    csirxss_s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    csirxss_s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    csirxss_s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    csirxss_s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    video_out_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 );
    video_out_tdest : out STD_LOGIC_VECTOR ( 9 downto 0 );
    video_out_tlast : out STD_LOGIC;
    video_out_tready : in STD_LOGIC;
    video_out_tuser : out STD_LOGIC_VECTOR ( 95 downto 0 );
    video_out_tvalid : out STD_LOGIC;
    mipi_phy_if_clk_n : in STD_LOGIC;
    mipi_phy_if_clk_p : in STD_LOGIC;
    mipi_phy_if_data_n : in STD_LOGIC_VECTOR ( 3 downto 0 );
    mipi_phy_if_data_p : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_Vsp_core_0_0_Mipirx_xlnx_comb_w4_r1188 : entity is "Mipirx_xlnx_comb_w4_r1188,bd_7289,{}";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Mipirx_xlnx_comb_w4_r1188 : entity is "Mipirx_xlnx_comb_w4_r1188";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0_Mipirx_xlnx_comb_w4_r1188 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of design_1_Vsp_core_0_0_Mipirx_xlnx_comb_w4_r1188 : entity is "bd_7289,Vivado 2024.2";
end design_1_Vsp_core_0_0_Mipirx_xlnx_comb_w4_r1188;

architecture STRUCTURE of design_1_Vsp_core_0_0_Mipirx_xlnx_comb_w4_r1188 is
  signal \<const0>\ : STD_LOGIC;
  signal \^video_out_tuser\ : STD_LOGIC_VECTOR ( 69 downto 0 );
  signal NLW_inst_clkoutphy_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_csirxss_csi_irq_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_frame_rcvd_pulse_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pll_lock_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_rxbyteclkhs_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_system_rst_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_csirxss_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_csirxss_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_video_out_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_inst_video_out_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 95 downto 1 );
  attribute HW_HANDOFF : string;
  attribute HW_HANDOFF of inst : label is "Mipirx_xlnx_comb_w4_r1188.hwdef";
  attribute x_interface_info : string;
  attribute x_interface_info of clkoutphy_out : signal is "xilinx.com:signal:clock:1.0 CLK.clkoutphy_out CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clkoutphy_out : signal is "master";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clkoutphy_out : signal is "XIL_INTERFACENAME CLK.clkoutphy_out, FREQ_HZ 1500000000.0, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_90ba_phy_0_clkoutphy_out, INSERT_VIP 0";
  attribute x_interface_info of csirxss_csi_irq : signal is "xilinx.com:signal:interrupt:1.0 INTR.csirxss_csi_irq INTERRUPT";
  attribute x_interface_mode of csirxss_csi_irq : signal is "master";
  attribute x_interface_parameter of csirxss_csi_irq : signal is "XIL_INTERFACENAME INTR.csirxss_csi_irq, SENSITIVITY LEVEL_HIGH, PortWidth 1";
  attribute x_interface_info of dphy_clk_200M : signal is "xilinx.com:signal:clock:1.0 CLK.dphy_clk_200M CLK";
  attribute x_interface_mode of dphy_clk_200M : signal is "slave";
  attribute x_interface_parameter of dphy_clk_200M : signal is "XIL_INTERFACENAME CLK.dphy_clk_200M, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_90ba_dphy_clk_200M, INSERT_VIP 0";
  attribute x_interface_info of lite_aclk : signal is "xilinx.com:signal:clock:1.0 CLK.lite_aclk CLK";
  attribute x_interface_mode of lite_aclk : signal is "slave";
  attribute x_interface_parameter of lite_aclk : signal is "XIL_INTERFACENAME CLK.lite_aclk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_90ba_lite_aclk, ASSOCIATED_BUSIF csirxss_s_axi, ASSOCIATED_RESET lite_aresetn, INSERT_VIP 0";
  attribute x_interface_info of lite_aresetn : signal is "xilinx.com:signal:reset:1.0 RST.lite_aresetn RST";
  attribute x_interface_mode of lite_aresetn : signal is "slave";
  attribute x_interface_parameter of lite_aresetn : signal is "XIL_INTERFACENAME RST.lite_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT";
  attribute x_interface_info of mipi_phy_if_clk_n : signal is "xilinx.com:interface:mipi_phy:1.0 mipi_phy_if CLK_N";
  attribute x_interface_mode of mipi_phy_if_clk_n : signal is "slave";
  attribute x_interface_info of mipi_phy_if_clk_p : signal is "xilinx.com:interface:mipi_phy:1.0 mipi_phy_if CLK_P";
  attribute x_interface_info of rxbyteclkhs : signal is "xilinx.com:signal:clock:1.0 CLK.rxbyteclkhs CLK";
  attribute x_interface_mode of rxbyteclkhs : signal is "master";
  attribute x_interface_parameter of rxbyteclkhs : signal is "XIL_INTERFACENAME CLK.rxbyteclkhs, FREQ_HZ 148500000.0, FREQ_TOLERANCE_HZ 0, PHASE 0, CLK_DOMAIN bd_90ba_phy_0_rxbyteclkhs, INSERT_VIP 0";
  attribute x_interface_info of system_rst_out : signal is "xilinx.com:signal:reset:1.0 RST.system_rst_out RST";
  attribute x_interface_mode of system_rst_out : signal is "master";
  attribute x_interface_parameter of system_rst_out : signal is "XIL_INTERFACENAME RST.system_rst_out, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute x_interface_info of video_aclk : signal is "xilinx.com:signal:clock:1.0 CLK.video_aclk CLK";
  attribute x_interface_mode of video_aclk : signal is "slave";
  attribute x_interface_parameter of video_aclk : signal is "XIL_INTERFACENAME CLK.video_aclk, FREQ_HZ 150000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_90ba_video_aclk, ASSOCIATED_BUSIF video_out, ASSOCIATED_RESET video_aresetn, INSERT_VIP 0";
  attribute x_interface_info of video_aresetn : signal is "xilinx.com:signal:reset:1.0 RST.video_aresetn RST";
  attribute x_interface_mode of video_aresetn : signal is "slave";
  attribute x_interface_parameter of video_aresetn : signal is "XIL_INTERFACENAME RST.video_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute x_interface_info of video_out_tlast : signal is "xilinx.com:interface:axis:1.0 video_out TLAST";
  attribute x_interface_info of video_out_tready : signal is "xilinx.com:interface:axis:1.0 video_out TREADY";
  attribute x_interface_info of video_out_tvalid : signal is "xilinx.com:interface:axis:1.0 video_out TVALID";
  attribute x_interface_info of csirxss_s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi ARADDR";
  attribute x_interface_info of csirxss_s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi ARPROT";
  attribute x_interface_info of csirxss_s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi ARREADY";
  attribute x_interface_info of csirxss_s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi ARVALID";
  attribute x_interface_info of csirxss_s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi AWADDR";
  attribute x_interface_mode of csirxss_s_axi_awaddr : signal is "slave";
  attribute x_interface_parameter of csirxss_s_axi_awaddr : signal is "XIL_INTERFACENAME csirxss_s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 13, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN bd_90ba_lite_aclk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute x_interface_info of csirxss_s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi AWPROT";
  attribute x_interface_info of csirxss_s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi AWREADY";
  attribute x_interface_info of csirxss_s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi AWVALID";
  attribute x_interface_info of csirxss_s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi BREADY";
  attribute x_interface_info of csirxss_s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi BRESP";
  attribute x_interface_info of csirxss_s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi BVALID";
  attribute x_interface_info of csirxss_s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi RDATA";
  attribute x_interface_info of csirxss_s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi RREADY";
  attribute x_interface_info of csirxss_s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi RRESP";
  attribute x_interface_info of csirxss_s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi RVALID";
  attribute x_interface_info of csirxss_s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi WDATA";
  attribute x_interface_info of csirxss_s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi WREADY";
  attribute x_interface_info of csirxss_s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi WSTRB";
  attribute x_interface_info of csirxss_s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 csirxss_s_axi WVALID";
  attribute x_interface_info of mipi_phy_if_data_n : signal is "xilinx.com:interface:mipi_phy:1.0 mipi_phy_if DATA_N";
  attribute x_interface_info of mipi_phy_if_data_p : signal is "xilinx.com:interface:mipi_phy:1.0 mipi_phy_if DATA_P";
  attribute x_interface_info of video_out_tdata : signal is "xilinx.com:interface:axis:1.0 video_out TDATA";
  attribute x_interface_mode of video_out_tdata : signal is "master";
  attribute x_interface_parameter of video_out_tdata : signal is "XIL_INTERFACENAME video_out, TDATA_NUM_BYTES 3, TDEST_WIDTH 10, TID_WIDTH 0, TUSER_WIDTH 96, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 150000000, PHASE 0.0, CLK_DOMAIN bd_90ba_video_aclk, LAYERED_METADATA undef, INSERT_VIP 0";
  attribute x_interface_info of video_out_tdest : signal is "xilinx.com:interface:axis:1.0 video_out TDEST";
  attribute x_interface_info of video_out_tuser : signal is "xilinx.com:interface:axis:1.0 video_out TUSER";
begin
  clkoutphy_out <= \<const0>\;
  csirxss_csi_irq <= \<const0>\;
  csirxss_s_axi_bresp(1) <= \<const0>\;
  csirxss_s_axi_bresp(0) <= \<const0>\;
  csirxss_s_axi_rresp(1) <= \<const0>\;
  csirxss_s_axi_rresp(0) <= \<const0>\;
  frame_rcvd_pulse_out <= \<const0>\;
  pll_lock_out <= \<const0>\;
  rxbyteclkhs <= \<const0>\;
  system_rst_out <= \<const0>\;
  video_out_tdest(9) <= \<const0>\;
  video_out_tdest(8) <= \<const0>\;
  video_out_tdest(7) <= \<const0>\;
  video_out_tdest(6) <= \<const0>\;
  video_out_tdest(5) <= \<const0>\;
  video_out_tdest(4) <= \<const0>\;
  video_out_tdest(3) <= \<const0>\;
  video_out_tdest(2) <= \<const0>\;
  video_out_tdest(1) <= \<const0>\;
  video_out_tdest(0) <= \<const0>\;
  video_out_tuser(95) <= \<const0>\;
  video_out_tuser(94) <= \<const0>\;
  video_out_tuser(93) <= \<const0>\;
  video_out_tuser(92) <= \<const0>\;
  video_out_tuser(91) <= \<const0>\;
  video_out_tuser(90) <= \<const0>\;
  video_out_tuser(89) <= \<const0>\;
  video_out_tuser(88) <= \<const0>\;
  video_out_tuser(87) <= \<const0>\;
  video_out_tuser(86) <= \<const0>\;
  video_out_tuser(85) <= \<const0>\;
  video_out_tuser(84) <= \<const0>\;
  video_out_tuser(83) <= \<const0>\;
  video_out_tuser(82) <= \<const0>\;
  video_out_tuser(81) <= \<const0>\;
  video_out_tuser(80) <= \<const0>\;
  video_out_tuser(79) <= \<const0>\;
  video_out_tuser(78) <= \<const0>\;
  video_out_tuser(77) <= \<const0>\;
  video_out_tuser(76) <= \<const0>\;
  video_out_tuser(75) <= \<const0>\;
  video_out_tuser(74) <= \<const0>\;
  video_out_tuser(73) <= \<const0>\;
  video_out_tuser(72) <= \<const0>\;
  video_out_tuser(71) <= \<const0>\;
  video_out_tuser(70) <= \<const0>\;
  video_out_tuser(69 downto 64) <= \^video_out_tuser\(69 downto 64);
  video_out_tuser(63) <= \<const0>\;
  video_out_tuser(62) <= \<const0>\;
  video_out_tuser(61) <= \<const0>\;
  video_out_tuser(60) <= \<const0>\;
  video_out_tuser(59) <= \<const0>\;
  video_out_tuser(58) <= \<const0>\;
  video_out_tuser(57) <= \<const0>\;
  video_out_tuser(56) <= \<const0>\;
  video_out_tuser(55) <= \<const0>\;
  video_out_tuser(54) <= \<const0>\;
  video_out_tuser(53) <= \<const0>\;
  video_out_tuser(52) <= \<const0>\;
  video_out_tuser(51) <= \<const0>\;
  video_out_tuser(50) <= \<const0>\;
  video_out_tuser(49) <= \<const0>\;
  video_out_tuser(48) <= \<const0>\;
  video_out_tuser(47) <= \<const0>\;
  video_out_tuser(46) <= \<const0>\;
  video_out_tuser(45) <= \<const0>\;
  video_out_tuser(44) <= \<const0>\;
  video_out_tuser(43) <= \<const0>\;
  video_out_tuser(42) <= \<const0>\;
  video_out_tuser(41) <= \<const0>\;
  video_out_tuser(40) <= \<const0>\;
  video_out_tuser(39) <= \<const0>\;
  video_out_tuser(38) <= \<const0>\;
  video_out_tuser(37) <= \<const0>\;
  video_out_tuser(36) <= \<const0>\;
  video_out_tuser(35) <= \<const0>\;
  video_out_tuser(34) <= \<const0>\;
  video_out_tuser(33) <= \<const0>\;
  video_out_tuser(32) <= \<const0>\;
  video_out_tuser(31) <= \<const0>\;
  video_out_tuser(30) <= \<const0>\;
  video_out_tuser(29) <= \<const0>\;
  video_out_tuser(28) <= \<const0>\;
  video_out_tuser(27) <= \<const0>\;
  video_out_tuser(26) <= \<const0>\;
  video_out_tuser(25) <= \<const0>\;
  video_out_tuser(24) <= \<const0>\;
  video_out_tuser(23) <= \<const0>\;
  video_out_tuser(22) <= \<const0>\;
  video_out_tuser(21) <= \<const0>\;
  video_out_tuser(20) <= \<const0>\;
  video_out_tuser(19) <= \<const0>\;
  video_out_tuser(18) <= \<const0>\;
  video_out_tuser(17) <= \<const0>\;
  video_out_tuser(16) <= \<const0>\;
  video_out_tuser(15) <= \<const0>\;
  video_out_tuser(14) <= \<const0>\;
  video_out_tuser(13) <= \<const0>\;
  video_out_tuser(12) <= \<const0>\;
  video_out_tuser(11) <= \<const0>\;
  video_out_tuser(10) <= \<const0>\;
  video_out_tuser(9) <= \<const0>\;
  video_out_tuser(8) <= \<const0>\;
  video_out_tuser(7) <= \<const0>\;
  video_out_tuser(6) <= \<const0>\;
  video_out_tuser(5) <= \<const0>\;
  video_out_tuser(4) <= \<const0>\;
  video_out_tuser(3) <= \<const0>\;
  video_out_tuser(2) <= \<const0>\;
  video_out_tuser(1) <= \<const0>\;
  video_out_tuser(0) <= \^video_out_tuser\(0);
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
inst: entity work.design_1_Vsp_core_0_0_bd_7289
     port map (
      clkoutphy_out => NLW_inst_clkoutphy_out_UNCONNECTED,
      csirxss_csi_irq => NLW_inst_csirxss_csi_irq_UNCONNECTED,
      csirxss_s_axi_araddr(12) => csirxss_s_axi_araddr(12),
      csirxss_s_axi_araddr(11 downto 8) => B"0000",
      csirxss_s_axi_araddr(7 downto 2) => csirxss_s_axi_araddr(7 downto 2),
      csirxss_s_axi_araddr(1 downto 0) => B"00",
      csirxss_s_axi_arprot(2 downto 0) => B"000",
      csirxss_s_axi_arready(0) => csirxss_s_axi_arready(0),
      csirxss_s_axi_arvalid(0) => csirxss_s_axi_arvalid(0),
      csirxss_s_axi_awaddr(12) => csirxss_s_axi_awaddr(12),
      csirxss_s_axi_awaddr(11 downto 8) => B"0000",
      csirxss_s_axi_awaddr(7 downto 2) => csirxss_s_axi_awaddr(7 downto 2),
      csirxss_s_axi_awaddr(1 downto 0) => B"00",
      csirxss_s_axi_awprot(2 downto 0) => B"000",
      csirxss_s_axi_awready(0) => csirxss_s_axi_awready(0),
      csirxss_s_axi_awvalid(0) => csirxss_s_axi_awvalid(0),
      csirxss_s_axi_bready(0) => csirxss_s_axi_bready(0),
      csirxss_s_axi_bresp(1 downto 0) => NLW_inst_csirxss_s_axi_bresp_UNCONNECTED(1 downto 0),
      csirxss_s_axi_bvalid(0) => csirxss_s_axi_bvalid(0),
      csirxss_s_axi_rdata(31 downto 0) => csirxss_s_axi_rdata(31 downto 0),
      csirxss_s_axi_rready(0) => csirxss_s_axi_rready(0),
      csirxss_s_axi_rresp(1 downto 0) => NLW_inst_csirxss_s_axi_rresp_UNCONNECTED(1 downto 0),
      csirxss_s_axi_rvalid(0) => csirxss_s_axi_rvalid(0),
      csirxss_s_axi_wdata(31 downto 0) => csirxss_s_axi_wdata(31 downto 0),
      csirxss_s_axi_wready(0) => csirxss_s_axi_wready(0),
      csirxss_s_axi_wstrb(3 downto 0) => B"1111",
      csirxss_s_axi_wvalid(0) => csirxss_s_axi_wvalid(0),
      dphy_clk_200M => dphy_clk_200M,
      frame_rcvd_pulse_out => NLW_inst_frame_rcvd_pulse_out_UNCONNECTED,
      lite_aclk => '0',
      lite_aresetn => '0',
      mipi_phy_if_clk_n => mipi_phy_if_clk_n,
      mipi_phy_if_clk_p => mipi_phy_if_clk_p,
      mipi_phy_if_data_n(3 downto 0) => mipi_phy_if_data_n(3 downto 0),
      mipi_phy_if_data_p(3 downto 0) => mipi_phy_if_data_p(3 downto 0),
      pll_lock_out => NLW_inst_pll_lock_out_UNCONNECTED,
      rxbyteclkhs => NLW_inst_rxbyteclkhs_UNCONNECTED,
      system_rst_out => NLW_inst_system_rst_out_UNCONNECTED,
      video_aclk => '0',
      video_aresetn => video_aresetn,
      video_out_tdata(23 downto 0) => video_out_tdata(23 downto 0),
      video_out_tdest(9 downto 0) => NLW_inst_video_out_tdest_UNCONNECTED(9 downto 0),
      video_out_tlast => video_out_tlast,
      video_out_tready => '1',
      video_out_tuser(95 downto 70) => NLW_inst_video_out_tuser_UNCONNECTED(95 downto 70),
      video_out_tuser(69 downto 64) => \^video_out_tuser\(69 downto 64),
      video_out_tuser(63 downto 1) => NLW_inst_video_out_tuser_UNCONNECTED(63 downto 1),
      video_out_tuser(0) => \^video_out_tuser\(0),
      video_out_tvalid => video_out_tvalid
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Camif is
  port (
    DO : out STD_LOGIC_VECTOR ( 6 downto 0 );
    ackInvCamifConfigSynth : out STD_LOGIC;
    ackInvCamifConfig : out STD_LOGIC;
    stateOp_reg_0 : out STD_LOGIC;
    ackInvCamifGetReg : out STD_LOGIC;
    ackInvCamifModReg : out STD_LOGIC;
    ackInvCamifSetReg : out STD_LOGIC;
    ackInvCamifGetCorereg : out STD_LOGIC;
    ackInvCamifSetCorereg : out STD_LOGIC;
    \ixTExp_lcl_reg[1]_0\ : out STD_LOGIC;
    \ixTExp_sig_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateLive_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \stateConfig_reg[3]_0\ : out STD_LOGIC;
    synthNotLive_reg_0 : out STD_LOGIC;
    \stateSynth_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    camifToVideoinAXIS_tlast : out STD_LOGIC;
    \col_reg[10]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \row_reg[11]_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    camifToVideoinAXIS_tvalid : out STD_LOGIC;
    \rowRaw_lcl_reg[1]_0\ : out STD_LOGIC;
    \row_reg[0]_0\ : out STD_LOGIC;
    \rowRaw_lcl_reg[11]_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \col_reg[1]_0\ : out STD_LOGIC;
    camifToVideoinAXIS_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 );
    \mask_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    grayToManyAXIS_tvalid_sig_reg : out STD_LOGIC;
    \stateStream_reg[0]\ : out STD_LOGIC;
    synthNotLive_reg_1 : out STD_LOGIC;
    \ixTExp_sig_reg[2]_1\ : out STD_LOGIC;
    \ixTExp_sig_reg[1]_0\ : out STD_LOGIC;
    \stateIgr_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateIgr_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \stateIgr_reg[1]_1\ : out STD_LOGIC;
    toVideoinAXIS_tvalid_sig_reg_0 : out STD_LOGIC;
    \FSM_sequential_stateRgbegr_reg[0]\ : out STD_LOGIC;
    \klm_reg[0]\ : out STD_LOGIC;
    \klm_reg[0]_0\ : out STD_LOGIC;
    \klm_reg[0]_1\ : out STD_LOGIC;
    \klm_reg[0]_2\ : out STD_LOGIC;
    \klm_reg[0]_3\ : out STD_LOGIC;
    \klm_reg[0]_4\ : out STD_LOGIC;
    \klm_reg[0]_5\ : out STD_LOGIC;
    \klm_reg[0]_6\ : out STD_LOGIC;
    \regVal_reg[6]_0\ : out STD_LOGIC;
    \regVal_reg[7]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \getCoreregVal_sig_reg[31]_0\ : out STD_LOGIC_VECTOR ( 25 downto 0 );
    \regVal_reg[5]_0\ : out STD_LOGIC;
    \regVal_reg[4]_0\ : out STD_LOGIC;
    \regVal_reg[3]_0\ : out STD_LOGIC;
    \regVal_reg[1]_0\ : out STD_LOGIC;
    \regVal_reg[0]_0\ : out STD_LOGIC;
    \liveSetRegAddr_reg[13]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    scl : inout STD_LOGIC;
    sda : inout STD_LOGIC;
    aclk_sig : in STD_LOGIC;
    csi_clk_n : in STD_LOGIC;
    csi_clk_p : in STD_LOGIC;
    mipi_phy_if_data_n : in STD_LOGIC_VECTOR ( 3 downto 0 );
    mipi_phy_if_data_p : in STD_LOGIC_VECTOR ( 3 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    sda_sig_reg : in STD_LOGIC;
    stateOp47_out : in STD_LOGIC;
    synthNotLive : in STD_LOGIC;
    hdrNotFix : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    reqInvConfigSynth : in STD_LOGIC;
    reqInvConfig : in STD_LOGIC;
    reqInvModReg : in STD_LOGIC;
    reqInvGetReg : in STD_LOGIC;
    reqInvSetReg : in STD_LOGIC;
    i2cReadNotWrite_reg_0 : in STD_LOGIC;
    tkclk : in STD_LOGIC;
    ackLiveToConfigSetReg_reg_0 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 23 downto 0 );
    \i2cRegaddr_reg[13]_0\ : in STD_LOGIC;
    \i2cRegaddr_reg[12]_0\ : in STD_LOGIC;
    \i2cRegaddr_reg[6]_0\ : in STD_LOGIC;
    \i2cRegaddr_reg[4]_0\ : in STD_LOGIC;
    \i2cRegaddr_reg[3]_0\ : in STD_LOGIC;
    \i2cRegaddr_reg[0]_0\ : in STD_LOGIC;
    \i_reg[0]__0_0\ : in STD_LOGIC;
    rng : in STD_LOGIC;
    \row_reg[0]_1\ : in STD_LOGIC;
    \i_reg[0]__1_0\ : in STD_LOGIC;
    NRowRaw : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \stateSynth_reg[0]_0\ : in STD_LOGIC;
    \stateSynth_reg[0]_1\ : in STD_LOGIC;
    \stateSynth_reg[0]_2\ : in STD_LOGIC;
    NColRaw : in STD_LOGIC_VECTOR ( 2 downto 0 );
    reqInvGetCorereg : in STD_LOGIC;
    reqInvSetCorereg : in STD_LOGIC;
    stateCorecfg0 : in STD_LOGIC;
    ackInvGetCorereg_sig_reg_0 : in STD_LOGIC;
    i2cReadNotWrite_reg_1 : in STD_LOGIC;
    \capt_reg[0]\ : in STD_LOGIC;
    grayVideoinToManyAXIS_tvalid : in STD_LOGIC;
    \stateStream_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \klm_reg[0]_7\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    enEobufB_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dwrEobuf_reg[63]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \retbuf[0][0]_i_7\ : in STD_LOGIC;
    \tixVSynthmode_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \toVideoinAXIS_tdata_sig_reg[23]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \i2cRegaddr_reg[15]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \corecfgAXIL_awaddr_reg[12]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
    \corecfgAXIL_wdata_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \corecfgAXIL_araddr_reg[12]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Camif : entity is "Camif";
end design_1_Vsp_core_0_0_Camif;

architecture STRUCTURE of design_1_Vsp_core_0_0_Camif is
  signal TLinepad : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \aParrom[10]_i_3_n_0\ : STD_LOGIC;
  signal \aParrom[10]_i_4_n_0\ : STD_LOGIC;
  signal \aParrom[10]_i_5_n_0\ : STD_LOGIC;
  signal \aParrom[10]_i_6_n_0\ : STD_LOGIC;
  signal \aParrom[5]_i_2_n_0\ : STD_LOGIC;
  signal \aParrom[8]_i_3_n_0\ : STD_LOGIC;
  signal \aParrom[9]_i_2_n_0\ : STD_LOGIC;
  signal \aParrom[9]_i_3_n_0\ : STD_LOGIC;
  signal \aParrom_reg_n_0_[0]\ : STD_LOGIC;
  signal \aParrom_reg_n_0_[10]\ : STD_LOGIC;
  signal \aParrom_reg_n_0_[1]\ : STD_LOGIC;
  signal \aParrom_reg_n_0_[2]\ : STD_LOGIC;
  signal \aParrom_reg_n_0_[3]\ : STD_LOGIC;
  signal \aParrom_reg_n_0_[4]\ : STD_LOGIC;
  signal \aParrom_reg_n_0_[5]\ : STD_LOGIC;
  signal \aParrom_reg_n_0_[6]\ : STD_LOGIC;
  signal \aParrom_reg_n_0_[7]\ : STD_LOGIC;
  signal \aParrom_reg_n_0_[8]\ : STD_LOGIC;
  signal \aParrom_reg_n_0_[9]\ : STD_LOGIC;
  signal \^ackinvcamifconfig\ : STD_LOGIC;
  signal \^ackinvcamifconfigsynth\ : STD_LOGIC;
  signal \^ackinvcamifgetcorereg\ : STD_LOGIC;
  signal \^ackinvcamifgetreg\ : STD_LOGIC;
  signal \^ackinvcamifmodreg\ : STD_LOGIC;
  signal \^ackinvcamifsetcorereg\ : STD_LOGIC;
  signal \^ackinvcamifsetreg\ : STD_LOGIC;
  signal ackInvGetCorereg_sig_i_1_n_0 : STD_LOGIC;
  signal ackInvGetReg_sig_i_1_n_0 : STD_LOGIC;
  signal ackInvGetReg_sig_i_2_n_0 : STD_LOGIC;
  signal ackInvGetReg_sig_i_3_n_0 : STD_LOGIC;
  signal ackInvModReg_sig_i_1_n_0 : STD_LOGIC;
  signal ackInvModReg_sig_i_2_n_0 : STD_LOGIC;
  signal ackInvSetCorereg_sig_i_1_n_0 : STD_LOGIC;
  signal ackInvSetCorereg_sig_i_2_n_0 : STD_LOGIC;
  signal ackInvSetReg_sig_i_1_n_0 : STD_LOGIC;
  signal ackInvSetReg_sig_i_2_n_0 : STD_LOGIC;
  signal ackLiveToConfigSetReg : STD_LOGIC;
  signal ackLiveToConfigSetReg_i_1_n_0 : STD_LOGIC;
  signal ackLiveToConfigSetReg_i_2_n_0 : STD_LOGIC;
  signal ackLiveToConfigSetReg_reg_n_0 : STD_LOGIC;
  signal \b_lcl[0]_i_1_n_0\ : STD_LOGIC;
  signal \b_lcl[10]_i_1_n_0\ : STD_LOGIC;
  signal \b_lcl[10]_i_2_n_0\ : STD_LOGIC;
  signal \b_lcl[11]_i_1_n_0\ : STD_LOGIC;
  signal \b_lcl[11]_i_2_n_0\ : STD_LOGIC;
  signal \b_lcl[11]_i_3_n_0\ : STD_LOGIC;
  signal \b_lcl[11]_i_4_n_0\ : STD_LOGIC;
  signal \b_lcl[11]_i_5_n_0\ : STD_LOGIC;
  signal \b_lcl[11]_i_6_n_0\ : STD_LOGIC;
  signal \b_lcl[11]_i_7_n_0\ : STD_LOGIC;
  signal \b_lcl[11]_i_8_n_0\ : STD_LOGIC;
  signal \b_lcl[1]_i_1_n_0\ : STD_LOGIC;
  signal \b_lcl[2]_i_1_n_0\ : STD_LOGIC;
  signal \b_lcl[3]_i_1_n_0\ : STD_LOGIC;
  signal \b_lcl[4]_i_1_n_0\ : STD_LOGIC;
  signal \b_lcl[5]_i_1_n_0\ : STD_LOGIC;
  signal \b_lcl[5]_i_2_n_0\ : STD_LOGIC;
  signal \b_lcl[5]_i_3_n_0\ : STD_LOGIC;
  signal \b_lcl[6]_i_1_n_0\ : STD_LOGIC;
  signal \b_lcl[6]_i_2_n_0\ : STD_LOGIC;
  signal \b_lcl[7]_i_1_n_0\ : STD_LOGIC;
  signal \b_lcl[7]_i_2_n_0\ : STD_LOGIC;
  signal \b_lcl[8]_i_1_n_0\ : STD_LOGIC;
  signal \b_lcl[8]_i_2_n_0\ : STD_LOGIC;
  signal \b_lcl[9]_i_1_n_0\ : STD_LOGIC;
  signal \b_lcl[9]_i_2_n_0\ : STD_LOGIC;
  signal \b_lcl_reg_n_0_[0]\ : STD_LOGIC;
  signal \b_lcl_reg_n_0_[10]\ : STD_LOGIC;
  signal \b_lcl_reg_n_0_[11]\ : STD_LOGIC;
  signal \b_lcl_reg_n_0_[1]\ : STD_LOGIC;
  signal \b_lcl_reg_n_0_[2]\ : STD_LOGIC;
  signal \b_lcl_reg_n_0_[3]\ : STD_LOGIC;
  signal \b_lcl_reg_n_0_[4]\ : STD_LOGIC;
  signal \b_lcl_reg_n_0_[5]\ : STD_LOGIC;
  signal \b_lcl_reg_n_0_[6]\ : STD_LOGIC;
  signal \b_lcl_reg_n_0_[7]\ : STD_LOGIC;
  signal \b_lcl_reg_n_0_[8]\ : STD_LOGIC;
  signal \b_lcl_reg_n_0_[9]\ : STD_LOGIC;
  signal blk1_out : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \blk[10]_i_3_n_0\ : STD_LOGIC;
  signal \blk[10]_i_4_n_0\ : STD_LOGIC;
  signal \blk[10]_i_5_n_0\ : STD_LOGIC;
  signal \blk[10]_i_6_n_0\ : STD_LOGIC;
  signal \blk_reg_n_0_[0]\ : STD_LOGIC;
  signal \blk_reg_n_0_[10]\ : STD_LOGIC;
  signal \blk_reg_n_0_[1]\ : STD_LOGIC;
  signal \blk_reg_n_0_[2]\ : STD_LOGIC;
  signal \blk_reg_n_0_[3]\ : STD_LOGIC;
  signal \blk_reg_n_0_[4]\ : STD_LOGIC;
  signal \blk_reg_n_0_[5]\ : STD_LOGIC;
  signal \blk_reg_n_0_[6]\ : STD_LOGIC;
  signal \blk_reg_n_0_[7]\ : STD_LOGIC;
  signal \blk_reg_n_0_[8]\ : STD_LOGIC;
  signal \blk_reg_n_0_[9]\ : STD_LOGIC;
  signal bsh : STD_LOGIC;
  signal \bsh[0]_i_1_n_0\ : STD_LOGIC;
  signal \bsh[1]_i_2_n_0\ : STD_LOGIC;
  signal \bsh[1]_i_3_n_0\ : STD_LOGIC;
  signal \bsh[1]_i_4_n_0\ : STD_LOGIC;
  signal \bsh[1]_i_5_n_0\ : STD_LOGIC;
  signal \bsh_reg_n_0_[0]\ : STD_LOGIC;
  signal \bsh_reg_n_0_[1]\ : STD_LOGIC;
  signal bytecnt0 : STD_LOGIC;
  signal \bytecnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytecnt[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytecnt[1]_i_3_n_0\ : STD_LOGIC;
  signal \bytecnt[1]_i_4_n_0\ : STD_LOGIC;
  signal \bytecnt[2]_i_2_n_0\ : STD_LOGIC;
  signal \bytecnt[2]_i_3_n_0\ : STD_LOGIC;
  signal \bytecnt[2]_i_4_n_0\ : STD_LOGIC;
  signal \bytecnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \bytecnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \bytecnt_reg_n_0_[2]\ : STD_LOGIC;
  signal camifGetCoreregVal : STD_LOGIC_VECTOR ( 30 downto 24 );
  signal camifGetRegVal : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \^camiftovideoinaxis_tdata\ : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal \^camiftovideoinaxis_tvalid\ : STD_LOGIC;
  signal col : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \col[0]_i_1_n_0\ : STD_LOGIC;
  signal \col[10]_i_1_n_0\ : STD_LOGIC;
  signal \col[10]_i_2_n_0\ : STD_LOGIC;
  signal \col[10]_i_3_n_0\ : STD_LOGIC;
  signal \col[1]_i_1_n_0\ : STD_LOGIC;
  signal \col[2]_i_1_n_0\ : STD_LOGIC;
  signal \col[3]_i_1_n_0\ : STD_LOGIC;
  signal \col[4]_i_1_n_0\ : STD_LOGIC;
  signal \col[5]_i_1_n_0\ : STD_LOGIC;
  signal \col[5]_i_2_n_0\ : STD_LOGIC;
  signal \col[6]_i_1_n_0\ : STD_LOGIC;
  signal \col[7]_i_1_n_0\ : STD_LOGIC;
  signal \col[8]_i_1_n_0\ : STD_LOGIC;
  signal \col[9]_i_1_n_0\ : STD_LOGIC;
  signal \col[9]_i_2_n_0\ : STD_LOGIC;
  signal \col[9]_i_3_n_0\ : STD_LOGIC;
  signal \^col_reg[10]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal colchk : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \colchk[0]_i_1_n_0\ : STD_LOGIC;
  signal \colchk[1]_i_1_n_0\ : STD_LOGIC;
  signal \colchk[2]_i_1_n_0\ : STD_LOGIC;
  signal \colchk[3]_i_1_n_0\ : STD_LOGIC;
  signal \colchk[3]_i_2_n_0\ : STD_LOGIC;
  signal \colchk[3]_i_3_n_0\ : STD_LOGIC;
  signal \colchk[3]_i_4_n_0\ : STD_LOGIC;
  signal \corecfgAXIL_araddr[12]_i_1_n_0\ : STD_LOGIC;
  signal \corecfgAXIL_araddr_reg_n_0_[12]\ : STD_LOGIC;
  signal \corecfgAXIL_araddr_reg_n_0_[2]\ : STD_LOGIC;
  signal \corecfgAXIL_araddr_reg_n_0_[3]\ : STD_LOGIC;
  signal \corecfgAXIL_araddr_reg_n_0_[4]\ : STD_LOGIC;
  signal \corecfgAXIL_araddr_reg_n_0_[5]\ : STD_LOGIC;
  signal \corecfgAXIL_araddr_reg_n_0_[6]\ : STD_LOGIC;
  signal \corecfgAXIL_araddr_reg_n_0_[7]\ : STD_LOGIC;
  signal corecfgAXIL_arready : STD_LOGIC;
  signal \corecfgAXIL_awaddr[12]_i_1_n_0\ : STD_LOGIC;
  signal \corecfgAXIL_awaddr_reg_n_0_[12]\ : STD_LOGIC;
  signal \corecfgAXIL_awaddr_reg_n_0_[2]\ : STD_LOGIC;
  signal \corecfgAXIL_awaddr_reg_n_0_[3]\ : STD_LOGIC;
  signal \corecfgAXIL_awaddr_reg_n_0_[4]\ : STD_LOGIC;
  signal \corecfgAXIL_awaddr_reg_n_0_[5]\ : STD_LOGIC;
  signal \corecfgAXIL_awaddr_reg_n_0_[6]\ : STD_LOGIC;
  signal \corecfgAXIL_awaddr_reg_n_0_[7]\ : STD_LOGIC;
  signal corecfgAXIL_bvalid : STD_LOGIC;
  signal corecfgAXIL_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal corecfgAXIL_rvalid : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[0]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[10]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[11]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[12]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[13]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[14]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[15]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[16]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[17]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[18]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[19]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[1]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[20]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[21]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[22]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[23]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[24]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[25]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[26]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[27]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[28]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[29]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[2]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[30]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[31]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[3]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[4]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[5]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[6]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[7]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[8]\ : STD_LOGIC;
  signal \corecfgAXIL_wdata_reg_n_0_[9]\ : STD_LOGIC;
  signal corecfgAXIL_wready : STD_LOGIC;
  signal csirxss_s_axi_arvalid : STD_LOGIC;
  signal csirxss_s_axi_awready : STD_LOGIC;
  signal csirxss_s_axi_awvalid : STD_LOGIC;
  signal csirxss_s_axi_bready : STD_LOGIC;
  signal csirxss_s_axi_rready : STD_LOGIC;
  signal csirxss_s_axi_wvalid : STD_LOGIC;
  signal \g0_lcl[0]_i_1_n_0\ : STD_LOGIC;
  signal \g0_lcl[10]_i_1_n_0\ : STD_LOGIC;
  signal \g0_lcl[10]_i_2_n_0\ : STD_LOGIC;
  signal \g0_lcl[11]_i_1_n_0\ : STD_LOGIC;
  signal \g0_lcl[11]_i_2_n_0\ : STD_LOGIC;
  signal \g0_lcl[11]_i_3_n_0\ : STD_LOGIC;
  signal \g0_lcl[11]_i_4_n_0\ : STD_LOGIC;
  signal \g0_lcl[1]_i_1_n_0\ : STD_LOGIC;
  signal \g0_lcl[2]_i_1_n_0\ : STD_LOGIC;
  signal \g0_lcl[3]_i_1_n_0\ : STD_LOGIC;
  signal \g0_lcl[4]_i_1_n_0\ : STD_LOGIC;
  signal \g0_lcl[4]_i_2_n_0\ : STD_LOGIC;
  signal \g0_lcl[5]_i_1_n_0\ : STD_LOGIC;
  signal \g0_lcl[5]_i_2_n_0\ : STD_LOGIC;
  signal \g0_lcl[5]_i_3_n_0\ : STD_LOGIC;
  signal \g0_lcl[6]_i_1_n_0\ : STD_LOGIC;
  signal \g0_lcl[6]_i_2_n_0\ : STD_LOGIC;
  signal \g0_lcl[7]_i_1_n_0\ : STD_LOGIC;
  signal \g0_lcl[7]_i_2_n_0\ : STD_LOGIC;
  signal \g0_lcl[8]_i_1_n_0\ : STD_LOGIC;
  signal \g0_lcl[8]_i_2_n_0\ : STD_LOGIC;
  signal \g0_lcl[9]_i_1_n_0\ : STD_LOGIC;
  signal \g0_lcl[9]_i_2_n_0\ : STD_LOGIC;
  signal \g0_lcl_reg_n_0_[0]\ : STD_LOGIC;
  signal \g0_lcl_reg_n_0_[10]\ : STD_LOGIC;
  signal \g0_lcl_reg_n_0_[11]\ : STD_LOGIC;
  signal \g0_lcl_reg_n_0_[1]\ : STD_LOGIC;
  signal \g0_lcl_reg_n_0_[2]\ : STD_LOGIC;
  signal \g0_lcl_reg_n_0_[3]\ : STD_LOGIC;
  signal \g0_lcl_reg_n_0_[4]\ : STD_LOGIC;
  signal \g0_lcl_reg_n_0_[5]\ : STD_LOGIC;
  signal \g0_lcl_reg_n_0_[6]\ : STD_LOGIC;
  signal \g0_lcl_reg_n_0_[7]\ : STD_LOGIC;
  signal \g0_lcl_reg_n_0_[8]\ : STD_LOGIC;
  signal \g0_lcl_reg_n_0_[9]\ : STD_LOGIC;
  signal \g1_lcl[0]_i_1_n_0\ : STD_LOGIC;
  signal \g1_lcl[10]_i_1_n_0\ : STD_LOGIC;
  signal \g1_lcl[10]_i_2_n_0\ : STD_LOGIC;
  signal \g1_lcl[11]_i_1_n_0\ : STD_LOGIC;
  signal \g1_lcl[11]_i_2_n_0\ : STD_LOGIC;
  signal \g1_lcl[1]_i_1_n_0\ : STD_LOGIC;
  signal \g1_lcl[2]_i_1_n_0\ : STD_LOGIC;
  signal \g1_lcl[3]_i_1_n_0\ : STD_LOGIC;
  signal \g1_lcl[3]_i_2_n_0\ : STD_LOGIC;
  signal \g1_lcl[4]_i_1_n_0\ : STD_LOGIC;
  signal \g1_lcl[4]_i_2_n_0\ : STD_LOGIC;
  signal \g1_lcl[5]_i_1_n_0\ : STD_LOGIC;
  signal \g1_lcl[5]_i_2_n_0\ : STD_LOGIC;
  signal \g1_lcl[5]_i_3_n_0\ : STD_LOGIC;
  signal \g1_lcl[6]_i_1_n_0\ : STD_LOGIC;
  signal \g1_lcl[6]_i_2_n_0\ : STD_LOGIC;
  signal \g1_lcl[7]_i_1_n_0\ : STD_LOGIC;
  signal \g1_lcl[7]_i_2_n_0\ : STD_LOGIC;
  signal \g1_lcl[8]_i_1_n_0\ : STD_LOGIC;
  signal \g1_lcl[8]_i_2_n_0\ : STD_LOGIC;
  signal \g1_lcl[9]_i_1_n_0\ : STD_LOGIC;
  signal \g1_lcl[9]_i_2_n_0\ : STD_LOGIC;
  signal \g1_lcl_reg_n_0_[0]\ : STD_LOGIC;
  signal \g1_lcl_reg_n_0_[10]\ : STD_LOGIC;
  signal \g1_lcl_reg_n_0_[11]\ : STD_LOGIC;
  signal \g1_lcl_reg_n_0_[1]\ : STD_LOGIC;
  signal \g1_lcl_reg_n_0_[2]\ : STD_LOGIC;
  signal \g1_lcl_reg_n_0_[3]\ : STD_LOGIC;
  signal \g1_lcl_reg_n_0_[4]\ : STD_LOGIC;
  signal \g1_lcl_reg_n_0_[5]\ : STD_LOGIC;
  signal \g1_lcl_reg_n_0_[6]\ : STD_LOGIC;
  signal \g1_lcl_reg_n_0_[7]\ : STD_LOGIC;
  signal \g1_lcl_reg_n_0_[8]\ : STD_LOGIC;
  signal \g1_lcl_reg_n_0_[9]\ : STD_LOGIC;
  signal \getCoreregVal_sig[31]_i_1_n_0\ : STD_LOGIC;
  signal gsh : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \gsh[0]_i_1_n_0\ : STD_LOGIC;
  signal \gsh[1]_i_1_n_0\ : STD_LOGIC;
  signal hdrNotFix48_out : STD_LOGIC;
  signal hdrNotFix_reg_n_0 : STD_LOGIC;
  signal i0 : STD_LOGIC;
  signal i2cReadNotWrite : STD_LOGIC;
  signal i2cReadNotWrite_i_1_n_0 : STD_LOGIC;
  signal i2cReadNotWrite_i_4_n_0 : STD_LOGIC;
  signal i2cReadNotWrite_i_5_n_0 : STD_LOGIC;
  signal \i2cRegaddr[15]_i_3_n_0\ : STD_LOGIC;
  signal \i2cRegaddr[15]_i_4_n_0\ : STD_LOGIC;
  signal \i2cRegaddr[15]_i_9_n_0\ : STD_LOGIC;
  signal \i2cRegaddr[7]_i_1_n_0\ : STD_LOGIC;
  signal \i2cRegaddr[7]_i_3_n_0\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[0]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[10]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[11]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[12]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[13]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[14]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[15]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[1]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[2]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[3]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[4]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[5]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[6]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[7]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[8]\ : STD_LOGIC;
  signal \i2cRegaddr_reg_n_0_[9]\ : STD_LOGIC;
  signal \i2cSend[7]_i_1_n_0\ : STD_LOGIC;
  signal \i2cSend[7]_i_3_n_0\ : STD_LOGIC;
  signal \i2cSend[7]_i_4_n_0\ : STD_LOGIC;
  signal \i2cSend[7]_i_5_n_0\ : STD_LOGIC;
  signal \i2cSend_reg_n_0_[0]\ : STD_LOGIC;
  signal \i2cSend_reg_n_0_[1]\ : STD_LOGIC;
  signal \i2cSend_reg_n_0_[2]\ : STD_LOGIC;
  signal \i2cSend_reg_n_0_[3]\ : STD_LOGIC;
  signal \i2cSend_reg_n_0_[4]\ : STD_LOGIC;
  signal \i2cSend_reg_n_0_[5]\ : STD_LOGIC;
  signal \i2cSend_reg_n_0_[6]\ : STD_LOGIC;
  signal \i2cSend_reg_n_0_[7]\ : STD_LOGIC;
  signal \i[0]__0_i_1_n_0\ : STD_LOGIC;
  signal \i[0]__1_i_1_n_0\ : STD_LOGIC;
  signal \i[0]__1_i_2_n_0\ : STD_LOGIC;
  signal \i[0]__1_i_3_n_0\ : STD_LOGIC;
  signal \i[0]__1_i_4_n_0\ : STD_LOGIC;
  signal \i[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \i[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \i[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \i[3]__0_i_1_n_0\ : STD_LOGIC;
  signal \i[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \i[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \i[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \i[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \i[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \i[7]_i_10_n_0\ : STD_LOGIC;
  signal \i[7]_i_11_n_0\ : STD_LOGIC;
  signal \i[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \i[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \i[7]_i_4_n_0\ : STD_LOGIC;
  signal \i[7]_i_5_n_0\ : STD_LOGIC;
  signal i_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \i_reg[0]__0_n_0\ : STD_LOGIC;
  signal \i_reg[0]__1_n_0\ : STD_LOGIC;
  signal \i_reg_n_0_[1]\ : STD_LOGIC;
  signal \i_reg_n_0_[2]\ : STD_LOGIC;
  signal \i_reg_n_0_[3]\ : STD_LOGIC;
  signal \i_reg_n_0_[4]\ : STD_LOGIC;
  signal \i_reg_n_0_[5]\ : STD_LOGIC;
  signal \i_reg_n_0_[6]\ : STD_LOGIC;
  signal \i_reg_n_0_[7]\ : STD_LOGIC;
  signal ixTExp : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \ixTExp_lcl[0]_i_1_n_0\ : STD_LOGIC;
  signal \ixTExp_lcl[1]_i_1_n_0\ : STD_LOGIC;
  signal \ixTExp_lcl[2]_i_1_n_0\ : STD_LOGIC;
  signal \ixTExp_lcl[2]_i_2_n_0\ : STD_LOGIC;
  signal \ixTExp_lcl[2]_i_3_n_0\ : STD_LOGIC;
  signal \ixTExp_lcl_reg_n_0_[0]\ : STD_LOGIC;
  signal \ixTExp_lcl_reg_n_0_[1]\ : STD_LOGIC;
  signal \ixTExp_lcl_reg_n_0_[2]\ : STD_LOGIC;
  signal \ixTExp_sig[0]_i_1_n_0\ : STD_LOGIC;
  signal \ixTExp_sig[1]_i_1_n_0\ : STD_LOGIC;
  signal \ixTExp_sig[2]_i_1_n_0\ : STD_LOGIC;
  signal \ixTExp_sig[2]_i_2_n_0\ : STD_LOGIC;
  signal \ixTExp_sig[2]_i_3_n_0\ : STD_LOGIC;
  signal \ixTExp_sig[2]_i_4_n_0\ : STD_LOGIC;
  signal \ixTExp_sig[2]_i_5_n_0\ : STD_LOGIC;
  signal \ixTExp_sig[2]_i_6_n_0\ : STD_LOGIC;
  signal \ixTExp_sig[2]_i_7_n_0\ : STD_LOGIC;
  signal \ixTExp_sig[2]_i_8_n_0\ : STD_LOGIC;
  signal \^ixtexp_sig_reg[2]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \ixTExp_sig_reg_n_0_[0]\ : STD_LOGIC;
  signal \ixTExp_sig_reg_n_0_[1]\ : STD_LOGIC;
  signal \ixTExp_sig_reg_n_0_[2]\ : STD_LOGIC;
  signal \j[0]_i_1_n_0\ : STD_LOGIC;
  signal \j[15]_i_1_n_0\ : STD_LOGIC;
  signal \j[15]_i_2_n_0\ : STD_LOGIC;
  signal \j[15]_i_4_n_0\ : STD_LOGIC;
  signal \j[1]_i_1_n_0\ : STD_LOGIC;
  signal \j[2]_i_1_n_0\ : STD_LOGIC;
  signal \j[3]_i_1_n_0\ : STD_LOGIC;
  signal \j[4]_i_1_n_0\ : STD_LOGIC;
  signal \j[5]_i_1_n_0\ : STD_LOGIC;
  signal \j[5]_i_2_n_0\ : STD_LOGIC;
  signal \j[6]_i_1_n_0\ : STD_LOGIC;
  signal \j[7]_i_10_n_0\ : STD_LOGIC;
  signal \j[7]_i_11_n_0\ : STD_LOGIC;
  signal \j[7]_i_3_n_0\ : STD_LOGIC;
  signal \j[7]_i_4_n_0\ : STD_LOGIC;
  signal \j[7]_i_5_n_0\ : STD_LOGIC;
  signal \j[7]_i_7_n_0\ : STD_LOGIC;
  signal \j[7]_i_8_n_0\ : STD_LOGIC;
  signal \j[7]_i_9_n_0\ : STD_LOGIC;
  signal j_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \j_reg[15]_i_3_n_2\ : STD_LOGIC;
  signal \j_reg[15]_i_3_n_3\ : STD_LOGIC;
  signal \j_reg[15]_i_3_n_4\ : STD_LOGIC;
  signal \j_reg[15]_i_3_n_5\ : STD_LOGIC;
  signal \j_reg[15]_i_3_n_6\ : STD_LOGIC;
  signal \j_reg[15]_i_3_n_7\ : STD_LOGIC;
  signal \j_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \j_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \j_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \j_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \j_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \j_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \j_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \j_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \j_reg_n_0_[0]\ : STD_LOGIC;
  signal \j_reg_n_0_[1]\ : STD_LOGIC;
  signal \j_reg_n_0_[2]\ : STD_LOGIC;
  signal \j_reg_n_0_[3]\ : STD_LOGIC;
  signal \j_reg_n_0_[4]\ : STD_LOGIC;
  signal \j_reg_n_0_[5]\ : STD_LOGIC;
  signal \j_reg_n_0_[6]\ : STD_LOGIC;
  signal \j_reg_n_0_[7]\ : STD_LOGIC;
  signal k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal k0 : STD_LOGIC;
  signal \k[1]_i_6_n_0\ : STD_LOGIC;
  signal \k[1]_i_8_n_0\ : STD_LOGIC;
  signal \klm[2]_i_4_n_0\ : STD_LOGIC;
  signal \klm[2]_i_5_n_0\ : STD_LOGIC;
  signal liveIxTExp : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \liveIxTExp[0]_i_1_n_0\ : STD_LOGIC;
  signal \liveIxTExp[1]_i_1_n_0\ : STD_LOGIC;
  signal \liveIxTExp[2]_i_1_n_0\ : STD_LOGIC;
  signal \liveIxTExp[2]_i_2_n_0\ : STD_LOGIC;
  signal liveNotExt : STD_LOGIC;
  signal liveNotExt_i_1_n_0 : STD_LOGIC;
  signal liveSetRegAddr : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal \liveSetRegAddr[13]_i_1_n_0\ : STD_LOGIC;
  signal \liveSetRegVal[0]_i_1_n_0\ : STD_LOGIC;
  signal \liveSetRegVal[1]_i_1_n_0\ : STD_LOGIC;
  signal \liveSetRegVal[2]_i_1_n_0\ : STD_LOGIC;
  signal \liveSetRegVal[3]_i_1_n_0\ : STD_LOGIC;
  signal \liveSetRegVal[4]_i_1_n_0\ : STD_LOGIC;
  signal \liveSetRegVal[6]_i_1_n_0\ : STD_LOGIC;
  signal \liveSetRegVal[7]_i_1_n_0\ : STD_LOGIC;
  signal \liveSetRegVal[7]_i_2_n_0\ : STD_LOGIC;
  signal \liveSetRegVal[7]_i_3_n_0\ : STD_LOGIC;
  signal \liveSetRegVal_reg_n_0_[0]\ : STD_LOGIC;
  signal \liveSetRegVal_reg_n_0_[1]\ : STD_LOGIC;
  signal \liveSetRegVal_reg_n_0_[2]\ : STD_LOGIC;
  signal \liveSetRegVal_reg_n_0_[3]\ : STD_LOGIC;
  signal \liveSetRegVal_reg_n_0_[4]\ : STD_LOGIC;
  signal \liveSetRegVal_reg_n_0_[6]\ : STD_LOGIC;
  signal \liveSetRegVal_reg_n_0_[7]\ : STD_LOGIC;
  signal modNotGetSet : STD_LOGIC;
  signal modNotGetSet_i_1_n_0 : STD_LOGIC;
  signal modNotGetSet_i_2_n_0 : STD_LOGIC;
  signal modNotGetSet_i_3_n_0 : STD_LOGIC;
  signal myI2c_n_0 : STD_LOGIC;
  signal myI2c_n_1 : STD_LOGIC;
  signal myI2c_n_10 : STD_LOGIC;
  signal myI2c_n_11 : STD_LOGIC;
  signal myI2c_n_12 : STD_LOGIC;
  signal myI2c_n_13 : STD_LOGIC;
  signal myI2c_n_14 : STD_LOGIC;
  signal myI2c_n_15 : STD_LOGIC;
  signal myI2c_n_16 : STD_LOGIC;
  signal myI2c_n_2 : STD_LOGIC;
  signal myI2c_n_3 : STD_LOGIC;
  signal myI2c_n_4 : STD_LOGIC;
  signal myI2c_n_5 : STD_LOGIC;
  signal myI2c_n_6 : STD_LOGIC;
  signal myI2c_n_7 : STD_LOGIC;
  signal myI2c_n_8 : STD_LOGIC;
  signal myI2c_n_9 : STD_LOGIC;
  signal myMipirx_n_177 : STD_LOGIC;
  signal myParrom_n_10 : STD_LOGIC;
  signal myParrom_n_11 : STD_LOGIC;
  signal myParrom_n_12 : STD_LOGIC;
  signal myParrom_n_13 : STD_LOGIC;
  signal myParrom_n_14 : STD_LOGIC;
  signal myParrom_n_15 : STD_LOGIC;
  signal myParrom_n_16 : STD_LOGIC;
  signal myParrom_n_17 : STD_LOGIC;
  signal myParrom_n_18 : STD_LOGIC;
  signal myParrom_n_19 : STD_LOGIC;
  signal myParrom_n_20 : STD_LOGIC;
  signal myParrom_n_21 : STD_LOGIC;
  signal myParrom_n_22 : STD_LOGIC;
  signal myParrom_n_23 : STD_LOGIC;
  signal myParrom_n_24 : STD_LOGIC;
  signal myParrom_n_25 : STD_LOGIC;
  signal myParrom_n_26 : STD_LOGIC;
  signal myParrom_n_27 : STD_LOGIC;
  signal myParrom_n_28 : STD_LOGIC;
  signal myParrom_n_29 : STD_LOGIC;
  signal myParrom_n_30 : STD_LOGIC;
  signal myParrom_n_31 : STD_LOGIC;
  signal myParrom_n_32 : STD_LOGIC;
  signal myParrom_n_33 : STD_LOGIC;
  signal myParrom_n_34 : STD_LOGIC;
  signal myParrom_n_35 : STD_LOGIC;
  signal myParrom_n_36 : STD_LOGIC;
  signal myParrom_n_37 : STD_LOGIC;
  signal myParrom_n_38 : STD_LOGIC;
  signal myParrom_n_39 : STD_LOGIC;
  signal myParrom_n_40 : STD_LOGIC;
  signal myParrom_n_41 : STD_LOGIC;
  signal myParrom_n_42 : STD_LOGIC;
  signal myParrom_n_43 : STD_LOGIC;
  signal myParrom_n_7 : STD_LOGIC;
  signal myParrom_n_8 : STD_LOGIC;
  signal myParrom_n_9 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal p_0_in0 : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal p_0_out : STD_LOGIC;
  signal prepdone : STD_LOGIC;
  signal \probe[0]_INST_0_i_1_n_0\ : STD_LOGIC;
  signal \probe[0]_INST_0_i_2_n_0\ : STD_LOGIC;
  signal \r_lcl[0]_i_1_n_0\ : STD_LOGIC;
  signal \r_lcl[10]_i_1_n_0\ : STD_LOGIC;
  signal \r_lcl[10]_i_2_n_0\ : STD_LOGIC;
  signal \r_lcl[11]_i_1_n_0\ : STD_LOGIC;
  signal \r_lcl[11]_i_2_n_0\ : STD_LOGIC;
  signal \r_lcl[1]_i_1_n_0\ : STD_LOGIC;
  signal \r_lcl[2]_i_1_n_0\ : STD_LOGIC;
  signal \r_lcl[3]_i_1_n_0\ : STD_LOGIC;
  signal \r_lcl[4]_i_1_n_0\ : STD_LOGIC;
  signal \r_lcl[5]_i_1_n_0\ : STD_LOGIC;
  signal \r_lcl[5]_i_2_n_0\ : STD_LOGIC;
  signal \r_lcl[5]_i_3_n_0\ : STD_LOGIC;
  signal \r_lcl[6]_i_1_n_0\ : STD_LOGIC;
  signal \r_lcl[6]_i_2_n_0\ : STD_LOGIC;
  signal \r_lcl[7]_i_1_n_0\ : STD_LOGIC;
  signal \r_lcl[7]_i_2_n_0\ : STD_LOGIC;
  signal \r_lcl[8]_i_1_n_0\ : STD_LOGIC;
  signal \r_lcl[8]_i_2_n_0\ : STD_LOGIC;
  signal \r_lcl[9]_i_1_n_0\ : STD_LOGIC;
  signal \r_lcl[9]_i_2_n_0\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[0]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[10]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[11]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[1]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[2]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[3]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[4]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[5]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[6]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[7]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[8]\ : STD_LOGIC;
  signal \r_lcl_reg_n_0_[9]\ : STD_LOGIC;
  signal \regVal[7]_i_1_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[0]_i_1_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[10]_i_1_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[10]_i_2_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[11]_i_1_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[11]_i_2_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[11]_i_3_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[11]_i_4_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[11]_i_5_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[11]_i_6_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[1]_i_1_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[2]_i_1_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[2]_i_2_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[3]_i_1_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[3]_i_2_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[4]_i_1_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[4]_i_2_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[5]_i_1_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[5]_i_2_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[6]_i_1_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[6]_i_2_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[7]_i_1_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[7]_i_2_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[8]_i_1_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[8]_i_2_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[9]_i_1_n_0\ : STD_LOGIC;
  signal \rowRaw_lcl[9]_i_2_n_0\ : STD_LOGIC;
  signal \^rowraw_lcl_reg[11]_0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \rowRaw_lcl_reg_n_0_[0]\ : STD_LOGIC;
  signal \rowRaw_lcl_reg_n_0_[1]\ : STD_LOGIC;
  signal \rowRaw_lcl_reg_n_0_[2]\ : STD_LOGIC;
  signal \row[0]_i_1_n_0\ : STD_LOGIC;
  signal \row[10]_i_1_n_0\ : STD_LOGIC;
  signal \row[11]_i_1_n_0\ : STD_LOGIC;
  signal \row[11]_i_2_n_0\ : STD_LOGIC;
  signal \row[11]_i_3_n_0\ : STD_LOGIC;
  signal \row[11]_i_5_n_0\ : STD_LOGIC;
  signal \row[11]_i_6_n_0\ : STD_LOGIC;
  signal \row[11]_i_7_n_0\ : STD_LOGIC;
  signal \row[1]_i_1_n_0\ : STD_LOGIC;
  signal \row[2]_i_1_n_0\ : STD_LOGIC;
  signal \row[2]_i_2_n_0\ : STD_LOGIC;
  signal \row[3]_i_1_n_0\ : STD_LOGIC;
  signal \row[4]_i_1_n_0\ : STD_LOGIC;
  signal \row[4]_i_2_n_0\ : STD_LOGIC;
  signal \row[5]_i_1_n_0\ : STD_LOGIC;
  signal \row[5]_i_2_n_0\ : STD_LOGIC;
  signal \row[6]_i_1_n_0\ : STD_LOGIC;
  signal \row[7]_i_1_n_0\ : STD_LOGIC;
  signal \row[8]_i_1_n_0\ : STD_LOGIC;
  signal \row[8]_i_2_n_0\ : STD_LOGIC;
  signal \row[9]_i_1_n_0\ : STD_LOGIC;
  signal \row[9]_i_2_n_0\ : STD_LOGIC;
  signal \^row_reg[11]_0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \row_reg_n_0_[0]\ : STD_LOGIC;
  signal \row_reg_n_0_[1]\ : STD_LOGIC;
  signal \row_reg_n_0_[2]\ : STD_LOGIC;
  signal \rowchk[0]_i_1_n_0\ : STD_LOGIC;
  signal \rowchk[1]_i_1_n_0\ : STD_LOGIC;
  signal \rowchk[2]_i_1_n_0\ : STD_LOGIC;
  signal \rowchk[3]_i_1_n_0\ : STD_LOGIC;
  signal \rowchk[3]_i_2_n_0\ : STD_LOGIC;
  signal \rowchk[3]_i_3_n_0\ : STD_LOGIC;
  signal \rowchk[3]_i_4_n_0\ : STD_LOGIC;
  signal \rowchk_reg_n_0_[0]\ : STD_LOGIC;
  signal \rowchk_reg_n_0_[1]\ : STD_LOGIC;
  signal \rowchk_reg_n_0_[2]\ : STD_LOGIC;
  signal \rowchk_reg_n_0_[3]\ : STD_LOGIC;
  signal \rsh[0]_i_1_n_0\ : STD_LOGIC;
  signal \rsh[1]_i_1_n_0\ : STD_LOGIC;
  signal \rsh_reg_n_0_[0]\ : STD_LOGIC;
  signal \rsh_reg_n_0_[1]\ : STD_LOGIC;
  signal specNotGnr : STD_LOGIC;
  signal stateConfig1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \stateConfig[0]_i_2_n_0\ : STD_LOGIC;
  signal \stateConfig[1]_i_3_n_0\ : STD_LOGIC;
  signal \stateConfig[1]_i_4_n_0\ : STD_LOGIC;
  signal \stateConfig[2]_i_2_n_0\ : STD_LOGIC;
  signal \stateConfig[3]_i_3_n_0\ : STD_LOGIC;
  signal \stateConfig[3]_i_5_n_0\ : STD_LOGIC;
  signal \stateConfig[3]_i_6_n_0\ : STD_LOGIC;
  signal \stateConfig[3]_i_7_n_0\ : STD_LOGIC;
  signal \stateConfig[3]_i_9_n_0\ : STD_LOGIC;
  signal \^stateconfig_reg[3]_0\ : STD_LOGIC;
  signal \stateConfig_reg_n_0_[0]\ : STD_LOGIC;
  signal \stateConfig_reg_n_0_[1]\ : STD_LOGIC;
  signal \stateConfig_reg_n_0_[2]\ : STD_LOGIC;
  signal \stateConfig_reg_n_0_[3]\ : STD_LOGIC;
  signal \stateCorecfg[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateCorecfg[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateCorecfg[2]_i_2_n_0\ : STD_LOGIC;
  signal \stateCorecfg[2]_i_3_n_0\ : STD_LOGIC;
  signal \stateCorecfg_reg_n_0_[0]\ : STD_LOGIC;
  signal \stateCorecfg_reg_n_0_[1]\ : STD_LOGIC;
  signal \stateCorecfg_reg_n_0_[2]\ : STD_LOGIC;
  signal \stateLive[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateLive[0]_i_2_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_10_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_15_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_16_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_2_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_3_n_0\ : STD_LOGIC;
  signal \stateLive[1]_i_5_n_0\ : STD_LOGIC;
  signal \stateLive[2]_i_1_n_0\ : STD_LOGIC;
  signal \stateLive[2]_i_2_n_0\ : STD_LOGIC;
  signal \^statelive_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal stateOp : STD_LOGIC;
  signal \^stateop_reg_0\ : STD_LOGIC;
  signal \stateSynth[0]_i_1_n_0\ : STD_LOGIC;
  signal \stateSynth[0]_i_2_n_0\ : STD_LOGIC;
  signal \stateSynth[0]_i_3_n_0\ : STD_LOGIC;
  signal \stateSynth[0]_i_4_n_0\ : STD_LOGIC;
  signal \stateSynth[1]_i_1_n_0\ : STD_LOGIC;
  signal \stateSynth[1]_i_2_n_0\ : STD_LOGIC;
  signal \stateSynth[1]_i_3_n_0\ : STD_LOGIC;
  signal \stateSynth[1]_i_4_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_10_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_11_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_1_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_2_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_3_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_4_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_5_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_6_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_7_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_8_n_0\ : STD_LOGIC;
  signal \stateSynth[2]_i_9_n_0\ : STD_LOGIC;
  signal \^statesynth_reg[2]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \stateSynth_reg_n_0_[0]\ : STD_LOGIC;
  signal \stateSynth_reg_n_0_[1]\ : STD_LOGIC;
  signal \^synthnotlive_reg_0\ : STD_LOGIC;
  signal synthNotLive_reg_n_0 : STD_LOGIC;
  signal \tixVSynthmode_reg_n_0_[0]\ : STD_LOGIC;
  signal \tixVSynthmode_reg_n_0_[1]\ : STD_LOGIC;
  signal \tixVSynthmode_reg_n_0_[2]\ : STD_LOGIC;
  signal \tixVSynthmode_reg_n_0_[3]\ : STD_LOGIC;
  signal \tixVSynthmode_reg_n_0_[4]\ : STD_LOGIC;
  signal \tixVSynthmode_reg_n_0_[5]\ : STD_LOGIC;
  signal \tixVSynthmode_reg_n_0_[6]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[0]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[0]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[0]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[0]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[0]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_10_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_11_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_12_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_13_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_14_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_15_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_16_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_17_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_18_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_19_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_8_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[10]_i_9_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_10_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_11_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_12_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_13_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_14_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_15_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_16_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_17_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_18_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_8_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[11]_i_9_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[12]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[12]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[12]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[12]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[13]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[13]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[13]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[13]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[13]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[14]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[14]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[14]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[14]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[14]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[14]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[14]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[14]_i_8_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[15]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[15]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[15]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[15]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[16]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[16]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[16]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[16]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[16]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[16]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[17]_i_10_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[17]_i_11_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[17]_i_12_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[17]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[17]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[17]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[17]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[17]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[17]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[17]_i_8_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[17]_i_9_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[18]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[18]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[18]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[18]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[18]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[18]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[18]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[18]_i_8_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[18]_i_9_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[19]_i_10_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[19]_i_11_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[19]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[19]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[19]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[19]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[19]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[19]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[19]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[19]_i_8_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[19]_i_9_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[1]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[1]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[1]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[1]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[20]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[20]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[20]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[20]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[20]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[20]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[20]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_10_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_14_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_15_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_16_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_17_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_18_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_19_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_20_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_8_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[21]_i_9_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_10_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_11_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_12_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_13_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_14_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_15_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_16_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_17_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_18_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_19_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_20_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_21_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_8_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[22]_i_9_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_10_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_11_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_12_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_13_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_14_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_15_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_16_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_17_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_18_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_19_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_20_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_21_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_8_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[23]_i_9_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[2]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[2]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[2]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[2]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[2]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[2]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[2]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[3]_i_10_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[3]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[3]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[3]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[3]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[3]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[3]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[3]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[3]_i_8_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[3]_i_9_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[4]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[4]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[4]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[4]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[4]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[5]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[5]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[5]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[5]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[5]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[6]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[6]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[6]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[6]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[6]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[7]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[7]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[7]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[7]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[7]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[7]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[7]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[7]_i_8_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[8]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[8]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[8]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[8]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[8]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[8]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[8]_i_8_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[8]_i_9_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_10_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_11_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_12_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_13_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_14_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_15_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_16_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_17_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_18_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_19_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_1_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_2_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_3_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_4_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_5_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig[9]_i_9_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg[10]_i_6_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg[10]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg[17]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg[21]_i_11_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg[21]_i_12_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg[21]_i_13_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg[8]_i_7_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg[9]_i_8_n_0\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[0]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[10]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[11]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[12]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[13]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[14]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[15]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[16]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[17]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[18]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[19]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[1]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[20]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[21]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[22]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[23]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[2]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[3]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[4]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[5]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[6]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[7]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[8]\ : STD_LOGIC;
  signal \toVideoinAXIS_tdata_sig_reg_n_0_[9]\ : STD_LOGIC;
  signal toVideoinAXIS_tvalid_sig : STD_LOGIC;
  signal toVideoinAXIS_tvalid_sig_i_1_n_0 : STD_LOGIC;
  signal video_aresetn : STD_LOGIC;
  signal video_out_tdata : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal video_out_tlast : STD_LOGIC;
  signal video_out_tuser : STD_LOGIC_VECTOR ( 69 downto 64 );
  signal video_out_tvalid : STD_LOGIC;
  signal wht : STD_LOGIC_VECTOR ( 10 to 10 );
  signal whtNotBlk : STD_LOGIC;
  signal whtNotBlk0 : STD_LOGIC;
  signal whtNotBlk0_i_1_n_0 : STD_LOGIC;
  signal whtNotBlk0_reg_n_0 : STD_LOGIC;
  signal whtNotBlk_i_1_n_0 : STD_LOGIC;
  signal whtNotBlk_i_3_n_0 : STD_LOGIC;
  signal \wht[0]_i_1_n_0\ : STD_LOGIC;
  signal \wht[10]_i_1_n_0\ : STD_LOGIC;
  signal \wht[10]_i_2_n_0\ : STD_LOGIC;
  signal \wht[11]_i_1_n_0\ : STD_LOGIC;
  signal \wht[1]_i_1_n_0\ : STD_LOGIC;
  signal \wht[2]_i_1_n_0\ : STD_LOGIC;
  signal \wht[3]_i_1_n_0\ : STD_LOGIC;
  signal \wht[4]_i_1_n_0\ : STD_LOGIC;
  signal \wht[5]_i_1_n_0\ : STD_LOGIC;
  signal \wht[6]_i_1_n_0\ : STD_LOGIC;
  signal \wht[7]_i_1_n_0\ : STD_LOGIC;
  signal \wht[8]_i_1_n_0\ : STD_LOGIC;
  signal \wht[9]_i_1_n_0\ : STD_LOGIC;
  signal \wht_reg_n_0_[0]\ : STD_LOGIC;
  signal \wht_reg_n_0_[10]\ : STD_LOGIC;
  signal \wht_reg_n_0_[11]\ : STD_LOGIC;
  signal \wht_reg_n_0_[1]\ : STD_LOGIC;
  signal \wht_reg_n_0_[2]\ : STD_LOGIC;
  signal \wht_reg_n_0_[3]\ : STD_LOGIC;
  signal \wht_reg_n_0_[4]\ : STD_LOGIC;
  signal \wht_reg_n_0_[5]\ : STD_LOGIC;
  signal \wht_reg_n_0_[6]\ : STD_LOGIC;
  signal \wht_reg_n_0_[7]\ : STD_LOGIC;
  signal \wht_reg_n_0_[8]\ : STD_LOGIC;
  signal \wht_reg_n_0_[9]\ : STD_LOGIC;
  signal \NLW_j_reg[15]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \NLW_j_reg[15]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 to 7 );
  signal NLW_myMipirx_clkoutphy_out_UNCONNECTED : STD_LOGIC;
  signal NLW_myMipirx_csirxss_csi_irq_UNCONNECTED : STD_LOGIC;
  signal NLW_myMipirx_frame_rcvd_pulse_out_UNCONNECTED : STD_LOGIC;
  signal NLW_myMipirx_pll_lock_out_UNCONNECTED : STD_LOGIC;
  signal NLW_myMipirx_rxbyteclkhs_UNCONNECTED : STD_LOGIC;
  signal NLW_myMipirx_system_rst_out_UNCONNECTED : STD_LOGIC;
  signal NLW_myMipirx_csirxss_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_myMipirx_csirxss_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_myMipirx_video_out_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_myMipirx_video_out_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 95 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \aParrom[10]_i_3\ : label is "soft_lutpair674";
  attribute SOFT_HLUTNM of \aParrom[10]_i_4\ : label is "soft_lutpair674";
  attribute SOFT_HLUTNM of \aParrom[10]_i_5\ : label is "soft_lutpair692";
  attribute SOFT_HLUTNM of \aParrom[9]_i_3\ : label is "soft_lutpair762";
  attribute SOFT_HLUTNM of ackInvGetReg_sig_i_2 : label is "soft_lutpair768";
  attribute SOFT_HLUTNM of \b_lcl[0]_i_1\ : label is "soft_lutpair635";
  attribute SOFT_HLUTNM of \b_lcl[10]_i_2\ : label is "soft_lutpair650";
  attribute SOFT_HLUTNM of \b_lcl[11]_i_3\ : label is "soft_lutpair646";
  attribute SOFT_HLUTNM of \b_lcl[11]_i_4\ : label is "soft_lutpair700";
  attribute SOFT_HLUTNM of \b_lcl[2]_i_1\ : label is "soft_lutpair636";
  attribute SOFT_HLUTNM of \b_lcl[3]_i_1\ : label is "soft_lutpair636";
  attribute SOFT_HLUTNM of \b_lcl[5]_i_1\ : label is "soft_lutpair698";
  attribute SOFT_HLUTNM of \b_lcl[7]_i_2\ : label is "soft_lutpair710";
  attribute SOFT_HLUTNM of \b_lcl[8]_i_2\ : label is "soft_lutpair710";
  attribute SOFT_HLUTNM of \b_lcl[9]_i_2\ : label is "soft_lutpair650";
  attribute SOFT_HLUTNM of \blk[10]_i_2\ : label is "soft_lutpair643";
  attribute SOFT_HLUTNM of \blk[10]_i_4\ : label is "soft_lutpair700";
  attribute SOFT_HLUTNM of \blk[10]_i_5\ : label is "soft_lutpair678";
  attribute SOFT_HLUTNM of \blk[10]_i_6\ : label is "soft_lutpair634";
  attribute SOFT_HLUTNM of \bsh[1]_i_5\ : label is "soft_lutpair664";
  attribute SOFT_HLUTNM of \bytecnt[1]_i_2\ : label is "soft_lutpair626";
  attribute SOFT_HLUTNM of \bytecnt[1]_i_4\ : label is "soft_lutpair761";
  attribute SOFT_HLUTNM of \bytecnt[2]_i_4\ : label is "soft_lutpair673";
  attribute SOFT_HLUTNM of \capt[0]_i_1\ : label is "soft_lutpair772";
  attribute SOFT_HLUTNM of \col[0]_i_1\ : label is "soft_lutpair632";
  attribute SOFT_HLUTNM of \col[2]_i_1\ : label is "soft_lutpair633";
  attribute SOFT_HLUTNM of \col[3]_i_1\ : label is "soft_lutpair633";
  attribute SOFT_HLUTNM of \col[7]_i_1\ : label is "soft_lutpair631";
  attribute SOFT_HLUTNM of \col[8]_i_1\ : label is "soft_lutpair631";
  attribute SOFT_HLUTNM of \col[9]_i_2\ : label is "soft_lutpair640";
  attribute SOFT_HLUTNM of \colchk[0]_i_1\ : label is "soft_lutpair666";
  attribute SOFT_HLUTNM of \colchk[1]_i_1\ : label is "soft_lutpair644";
  attribute SOFT_HLUTNM of \colchk[2]_i_1\ : label is "soft_lutpair681";
  attribute SOFT_HLUTNM of \colchk[3]_i_2\ : label is "soft_lutpair644";
  attribute SOFT_HLUTNM of \colchk[3]_i_3\ : label is "soft_lutpair645";
  attribute SOFT_HLUTNM of \colchk[3]_i_4\ : label is "soft_lutpair635";
  attribute SOFT_HLUTNM of \dwrEobuf[39]_i_3\ : label is "soft_lutpair764";
  attribute SOFT_HLUTNM of \dwrEobuf[56]_i_2\ : label is "soft_lutpair776";
  attribute SOFT_HLUTNM of \dwrEobuf[56]_i_3\ : label is "soft_lutpair757";
  attribute SOFT_HLUTNM of \dwrEobuf[57]_i_2\ : label is "soft_lutpair776";
  attribute SOFT_HLUTNM of \dwrEobuf[57]_i_3\ : label is "soft_lutpair757";
  attribute SOFT_HLUTNM of \dwrEobuf[58]_i_2\ : label is "soft_lutpair775";
  attribute SOFT_HLUTNM of \dwrEobuf[58]_i_3\ : label is "soft_lutpair756";
  attribute SOFT_HLUTNM of \dwrEobuf[59]_i_2\ : label is "soft_lutpair775";
  attribute SOFT_HLUTNM of \dwrEobuf[59]_i_3\ : label is "soft_lutpair756";
  attribute SOFT_HLUTNM of \dwrEobuf[60]_i_2\ : label is "soft_lutpair774";
  attribute SOFT_HLUTNM of \dwrEobuf[60]_i_3\ : label is "soft_lutpair755";
  attribute SOFT_HLUTNM of \dwrEobuf[61]_i_2\ : label is "soft_lutpair774";
  attribute SOFT_HLUTNM of \dwrEobuf[61]_i_3\ : label is "soft_lutpair755";
  attribute SOFT_HLUTNM of \dwrEobuf[62]_i_2\ : label is "soft_lutpair773";
  attribute SOFT_HLUTNM of \dwrEobuf[62]_i_3\ : label is "soft_lutpair754";
  attribute SOFT_HLUTNM of \dwrEobuf[63]_i_3\ : label is "soft_lutpair773";
  attribute SOFT_HLUTNM of \dwrEobuf[63]_i_4\ : label is "soft_lutpair754";
  attribute SOFT_HLUTNM of \dwrEobufp1[0]_i_2\ : label is "soft_lutpair753";
  attribute SOFT_HLUTNM of \dwrEobufp1[10]_i_2\ : label is "soft_lutpair748";
  attribute SOFT_HLUTNM of \dwrEobufp1[11]_i_2\ : label is "soft_lutpair748";
  attribute SOFT_HLUTNM of \dwrEobufp1[12]_i_2\ : label is "soft_lutpair747";
  attribute SOFT_HLUTNM of \dwrEobufp1[13]_i_2\ : label is "soft_lutpair747";
  attribute SOFT_HLUTNM of \dwrEobufp1[14]_i_2\ : label is "soft_lutpair746";
  attribute SOFT_HLUTNM of \dwrEobufp1[15]_i_3\ : label is "soft_lutpair764";
  attribute SOFT_HLUTNM of \dwrEobufp1[15]_i_4\ : label is "soft_lutpair746";
  attribute SOFT_HLUTNM of \dwrEobufp1[1]_i_2\ : label is "soft_lutpair753";
  attribute SOFT_HLUTNM of \dwrEobufp1[2]_i_2\ : label is "soft_lutpair752";
  attribute SOFT_HLUTNM of \dwrEobufp1[3]_i_2\ : label is "soft_lutpair752";
  attribute SOFT_HLUTNM of \dwrEobufp1[4]_i_2\ : label is "soft_lutpair751";
  attribute SOFT_HLUTNM of \dwrEobufp1[5]_i_2\ : label is "soft_lutpair751";
  attribute SOFT_HLUTNM of \dwrEobufp1[6]_i_2\ : label is "soft_lutpair750";
  attribute SOFT_HLUTNM of \dwrEobufp1[7]_i_3\ : label is "soft_lutpair750";
  attribute SOFT_HLUTNM of \dwrEobufp1[8]_i_2\ : label is "soft_lutpair749";
  attribute SOFT_HLUTNM of \dwrEobufp1[9]_i_2\ : label is "soft_lutpair749";
  attribute SOFT_HLUTNM of \dwrRowbuf[25]_i_8\ : label is "soft_lutpair689";
  attribute SOFT_HLUTNM of \g0_lcl[10]_i_2\ : label is "soft_lutpair652";
  attribute SOFT_HLUTNM of \g0_lcl[11]_i_3\ : label is "soft_lutpair646";
  attribute SOFT_HLUTNM of \g0_lcl[2]_i_1\ : label is "soft_lutpair638";
  attribute SOFT_HLUTNM of \g0_lcl[3]_i_1\ : label is "soft_lutpair638";
  attribute SOFT_HLUTNM of \g0_lcl[5]_i_3\ : label is "soft_lutpair648";
  attribute SOFT_HLUTNM of \g0_lcl[7]_i_2\ : label is "soft_lutpair712";
  attribute SOFT_HLUTNM of \g0_lcl[8]_i_2\ : label is "soft_lutpair712";
  attribute SOFT_HLUTNM of \g0_lcl[9]_i_2\ : label is "soft_lutpair652";
  attribute SOFT_HLUTNM of \g1_lcl[10]_i_2\ : label is "soft_lutpair651";
  attribute SOFT_HLUTNM of \g1_lcl[2]_i_1\ : label is "soft_lutpair639";
  attribute SOFT_HLUTNM of \g1_lcl[3]_i_1\ : label is "soft_lutpair639";
  attribute SOFT_HLUTNM of \g1_lcl[3]_i_2\ : label is "soft_lutpair634";
  attribute SOFT_HLUTNM of \g1_lcl[5]_i_3\ : label is "soft_lutpair647";
  attribute SOFT_HLUTNM of \g1_lcl[7]_i_2\ : label is "soft_lutpair711";
  attribute SOFT_HLUTNM of \g1_lcl[8]_i_2\ : label is "soft_lutpair711";
  attribute SOFT_HLUTNM of \g1_lcl[9]_i_2\ : label is "soft_lutpair651";
  attribute SOFT_HLUTNM of i2cReadNotWrite_i_5 : label is "soft_lutpair762";
  attribute SOFT_HLUTNM of \i2cRegaddr[15]_i_4\ : label is "soft_lutpair691";
  attribute SOFT_HLUTNM of \i2cRegaddr[15]_i_8\ : label is "soft_lutpair672";
  attribute SOFT_HLUTNM of \i2cRegaddr[15]_i_9\ : label is "soft_lutpair661";
  attribute SOFT_HLUTNM of \i2cSend[7]_i_5\ : label is "soft_lutpair672";
  attribute SOFT_HLUTNM of \i[0]__0_i_1\ : label is "soft_lutpair630";
  attribute SOFT_HLUTNM of \i[0]__1_i_2\ : label is "soft_lutpair703";
  attribute SOFT_HLUTNM of \i[0]__1_i_3\ : label is "soft_lutpair622";
  attribute SOFT_HLUTNM of \i[0]__1_i_4\ : label is "soft_lutpair682";
  attribute SOFT_HLUTNM of \i[1]__0_i_1\ : label is "soft_lutpair701";
  attribute SOFT_HLUTNM of \i[1]_i_1__0\ : label is "soft_lutpair630";
  attribute SOFT_HLUTNM of \i[2]__0_i_1\ : label is "soft_lutpair701";
  attribute SOFT_HLUTNM of \i[3]__0_i_3\ : label is "soft_lutpair627";
  attribute SOFT_HLUTNM of \i[5]_i_1__0\ : label is "soft_lutpair629";
  attribute SOFT_HLUTNM of \i[6]_i_1__0\ : label is "soft_lutpair628";
  attribute SOFT_HLUTNM of \ixMem[7]_i_3\ : label is "soft_lutpair671";
  attribute SOFT_HLUTNM of \ixMem[7]_i_4\ : label is "soft_lutpair758";
  attribute SOFT_HLUTNM of \ixMem[7]_i_5\ : label is "soft_lutpair759";
  attribute SOFT_HLUTNM of \ixTExp_lcl[2]_i_2\ : label is "soft_lutpair662";
  attribute SOFT_HLUTNM of \ixTExp_lcl[2]_i_3\ : label is "soft_lutpair682";
  attribute SOFT_HLUTNM of \ixTExp_sig[0]_i_1\ : label is "soft_lutpair677";
  attribute SOFT_HLUTNM of \ixTExp_sig[2]_i_2\ : label is "soft_lutpair677";
  attribute SOFT_HLUTNM of \j[15]_i_4\ : label is "soft_lutpair688";
  attribute SOFT_HLUTNM of \j[2]_i_1\ : label is "soft_lutpair625";
  attribute SOFT_HLUTNM of \j[3]_i_1\ : label is "soft_lutpair625";
  attribute SOFT_HLUTNM of \j[5]_i_2\ : label is "soft_lutpair675";
  attribute SOFT_HLUTNM of \j[7]_i_11\ : label is "soft_lutpair627";
  attribute SOFT_HLUTNM of \j[7]_i_5\ : label is "soft_lutpair761";
  attribute SOFT_HLUTNM of \j[7]_i_7\ : label is "soft_lutpair692";
  attribute SOFT_HLUTNM of \j[7]_i_8\ : label is "soft_lutpair768";
  attribute SOFT_HLUTNM of \j[7]_i_9\ : label is "soft_lutpair673";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \j_reg[15]_i_3\ : label is 35;
  attribute ADDER_THRESHOLD of \j_reg[8]_i_1\ : label is 35;
  attribute SOFT_HLUTNM of \k[0]_i_1\ : label is "soft_lutpair769";
  attribute SOFT_HLUTNM of \k[1]_i_3\ : label is "soft_lutpair769";
  attribute SOFT_HLUTNM of \k[1]_i_5\ : label is "soft_lutpair626";
  attribute SOFT_HLUTNM of \k[1]_i_8\ : label is "soft_lutpair675";
  attribute SOFT_HLUTNM of \klm[2]_i_1\ : label is "soft_lutpair690";
  attribute SOFT_HLUTNM of \klm[2]_i_5\ : label is "soft_lutpair703";
  attribute SOFT_HLUTNM of \liveIxTExp[0]_i_1\ : label is "soft_lutpair709";
  attribute SOFT_HLUTNM of \liveIxTExp[1]_i_1\ : label is "soft_lutpair665";
  attribute SOFT_HLUTNM of \liveIxTExp[2]_i_2\ : label is "soft_lutpair709";
  attribute SOFT_HLUTNM of \liveSetRegAddr[0]_i_1\ : label is "soft_lutpair622";
  attribute SOFT_HLUTNM of \liveSetRegVal[0]_i_1\ : label is "soft_lutpair665";
  attribute SOFT_HLUTNM of \liveSetRegVal[1]_i_1\ : label is "soft_lutpair623";
  attribute SOFT_HLUTNM of \liveSetRegVal[2]_i_1\ : label is "soft_lutpair662";
  attribute SOFT_HLUTNM of \liveSetRegVal[3]_i_1\ : label is "soft_lutpair623";
  attribute SOFT_HLUTNM of \liveSetRegVal[4]_i_1\ : label is "soft_lutpair661";
  attribute SOFT_HLUTNM of \liveSetRegVal[6]_i_1\ : label is "soft_lutpair624";
  attribute SOFT_HLUTNM of \liveSetRegVal[7]_i_2\ : label is "soft_lutpair624";
  attribute SOFT_HLUTNM of \liveSetRegVal[7]_i_3\ : label is "soft_lutpair683";
  attribute SOFT_HLUTNM of modNotGetSet_i_2 : label is "soft_lutpair702";
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of myMipirx : label is "Mipirx_xlnx_comb_w4_r1188,bd_7289,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of myMipirx : label is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of myMipirx : label is "bd_7289,Vivado 2024.2";
  attribute SOFT_HLUTNM of myMipirx_i_2 : label is "soft_lutpair760";
  attribute SOFT_HLUTNM of myMipirx_i_4 : label is "soft_lutpair760";
  attribute SOFT_HLUTNM of myMipirx_i_5 : label is "soft_lutpair687";
  attribute SOFT_HLUTNM of myMipirx_i_6 : label is "soft_lutpair663";
  attribute SOFT_HLUTNM of \probe[0]_INST_0_i_1\ : label is "soft_lutpair666";
  attribute SOFT_HLUTNM of \probe[0]_INST_0_i_2\ : label is "soft_lutpair629";
  attribute SOFT_HLUTNM of \r_lcl[10]_i_2\ : label is "soft_lutpair653";
  attribute SOFT_HLUTNM of \r_lcl[1]_i_1\ : label is "soft_lutpair699";
  attribute SOFT_HLUTNM of \r_lcl[2]_i_1\ : label is "soft_lutpair637";
  attribute SOFT_HLUTNM of \r_lcl[3]_i_1\ : label is "soft_lutpair637";
  attribute SOFT_HLUTNM of \r_lcl[5]_i_1\ : label is "soft_lutpair699";
  attribute SOFT_HLUTNM of \r_lcl[7]_i_2\ : label is "soft_lutpair713";
  attribute SOFT_HLUTNM of \r_lcl[8]_i_2\ : label is "soft_lutpair713";
  attribute SOFT_HLUTNM of \r_lcl[9]_i_2\ : label is "soft_lutpair653";
  attribute SOFT_HLUTNM of \retbuf[0][0]_i_9\ : label is "soft_lutpair767";
  attribute SOFT_HLUTNM of \retbuf[0][1]_i_8\ : label is "soft_lutpair767";
  attribute SOFT_HLUTNM of \retbuf[0][3]_i_5\ : label is "soft_lutpair766";
  attribute SOFT_HLUTNM of \retbuf[0][4]_i_5\ : label is "soft_lutpair766";
  attribute SOFT_HLUTNM of \retbuf[0][5]_i_5\ : label is "soft_lutpair765";
  attribute SOFT_HLUTNM of \retbuf[0][6]_i_6\ : label is "soft_lutpair765";
  attribute SOFT_HLUTNM of \rowRaw_lcl[0]_i_1\ : label is "soft_lutpair660";
  attribute SOFT_HLUTNM of \rowRaw_lcl[10]_i_2\ : label is "soft_lutpair667";
  attribute SOFT_HLUTNM of \rowRaw_lcl[11]_i_6\ : label is "soft_lutpair684";
  attribute SOFT_HLUTNM of \rowRaw_lcl[1]_i_1\ : label is "soft_lutpair660";
  attribute SOFT_HLUTNM of \rowRaw_lcl[2]_i_2\ : label is "soft_lutpair763";
  attribute SOFT_HLUTNM of \rowRaw_lcl[3]_i_2\ : label is "soft_lutpair763";
  attribute SOFT_HLUTNM of \rowRaw_lcl[4]_i_2\ : label is "soft_lutpair668";
  attribute SOFT_HLUTNM of \rowRaw_lcl[5]_i_2\ : label is "soft_lutpair668";
  attribute SOFT_HLUTNM of \rowRaw_lcl[9]_i_2\ : label is "soft_lutpair667";
  attribute SOFT_HLUTNM of \row[0]_i_1\ : label is "soft_lutpair640";
  attribute SOFT_HLUTNM of \row[11]_i_3\ : label is "soft_lutpair680";
  attribute SOFT_HLUTNM of \row[11]_i_5\ : label is "soft_lutpair685";
  attribute SOFT_HLUTNM of \row[11]_i_6\ : label is "soft_lutpair628";
  attribute SOFT_HLUTNM of \row[11]_i_7\ : label is "soft_lutpair669";
  attribute SOFT_HLUTNM of \row[2]_i_1\ : label is "soft_lutpair679";
  attribute SOFT_HLUTNM of \row[2]_i_2\ : label is "soft_lutpair642";
  attribute SOFT_HLUTNM of \row[4]_i_2\ : label is "soft_lutpair670";
  attribute SOFT_HLUTNM of \row[5]_i_2\ : label is "soft_lutpair670";
  attribute SOFT_HLUTNM of \row[9]_i_2\ : label is "soft_lutpair669";
  attribute SOFT_HLUTNM of \rowchk[0]_i_1\ : label is "soft_lutpair642";
  attribute SOFT_HLUTNM of \rowchk[1]_i_1\ : label is "soft_lutpair641";
  attribute SOFT_HLUTNM of \rowchk[2]_i_1\ : label is "soft_lutpair678";
  attribute SOFT_HLUTNM of \rowchk[3]_i_2\ : label is "soft_lutpair641";
  attribute SOFT_HLUTNM of \rowchk[3]_i_3\ : label is "soft_lutpair704";
  attribute SOFT_HLUTNM of \rowchk[3]_i_4\ : label is "soft_lutpair643";
  attribute SOFT_HLUTNM of \stateConfig[3]_i_5\ : label is "soft_lutpair691";
  attribute SOFT_HLUTNM of \stateCorecfg[1]_i_1\ : label is "soft_lutpair687";
  attribute SOFT_HLUTNM of \stateCorecfg[2]_i_2\ : label is "soft_lutpair663";
  attribute SOFT_HLUTNM of \stateCorner[1]_i_2\ : label is "soft_lutpair772";
  attribute SOFT_HLUTNM of \stateIgr[1]_i_1\ : label is "soft_lutpair690";
  attribute SOFT_HLUTNM of \stateLive[1]_i_16\ : label is "soft_lutpair684";
  attribute SOFT_HLUTNM of \stateLive[1]_i_3\ : label is "soft_lutpair683";
  attribute SOFT_HLUTNM of \stateLive[2]_i_2\ : label is "soft_lutpair702";
  attribute SOFT_HLUTNM of \stateStream[1]_i_6\ : label is "soft_lutpair689";
  attribute SOFT_HLUTNM of \stateSynth[0]_i_4\ : label is "soft_lutpair770";
  attribute SOFT_HLUTNM of \stateSynth[1]_i_3\ : label is "soft_lutpair770";
  attribute SOFT_HLUTNM of \stateSynth[1]_i_4\ : label is "soft_lutpair688";
  attribute SOFT_HLUTNM of \stateSynth[2]_i_10\ : label is "soft_lutpair680";
  attribute SOFT_HLUTNM of \stateSynth[2]_i_3\ : label is "soft_lutpair632";
  attribute SOFT_HLUTNM of \stateSynth[2]_i_5\ : label is "soft_lutpair704";
  attribute SOFT_HLUTNM of \stateSynth[2]_i_8\ : label is "soft_lutpair676";
  attribute SOFT_HLUTNM of \stateSynth[2]_i_9\ : label is "soft_lutpair645";
  attribute SOFT_HLUTNM of \tixVState[1]_i_6\ : label is "soft_lutpair671";
  attribute SOFT_HLUTNM of \tixVState[1]_i_7\ : label is "soft_lutpair758";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[0]_i_4\ : label is "soft_lutpair735";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[0]_i_5\ : label is "soft_lutpair720";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[10]_i_14\ : label is "soft_lutpair658";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[10]_i_15\ : label is "soft_lutpair679";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[10]_i_16\ : label is "soft_lutpair738";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[10]_i_17\ : label is "soft_lutpair743";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[10]_i_19\ : label is "soft_lutpair742";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[10]_i_3\ : label is "soft_lutpair737";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[10]_i_5\ : label is "soft_lutpair705";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[11]_i_10\ : label is "soft_lutpair744";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[11]_i_12\ : label is "soft_lutpair739";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[11]_i_13\ : label is "soft_lutpair741";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[11]_i_15\ : label is "soft_lutpair739";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[11]_i_17\ : label is "soft_lutpair738";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[11]_i_18\ : label is "soft_lutpair740";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[11]_i_3\ : label is "soft_lutpair736";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[11]_i_4\ : label is "soft_lutpair706";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[11]_i_6\ : label is "soft_lutpair658";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[11]_i_7\ : label is "soft_lutpair659";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[11]_i_9\ : label is "soft_lutpair743";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[13]_i_3\ : label is "soft_lutpair733";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[13]_i_5\ : label is "soft_lutpair649";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[14]_i_3\ : label is "soft_lutpair648";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[14]_i_5\ : label is "soft_lutpair733";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[14]_i_8\ : label is "soft_lutpair741";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[16]_i_3\ : label is "soft_lutpair732";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[17]_i_10\ : label is "soft_lutpair723";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[17]_i_4\ : label is "soft_lutpair731";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[17]_i_6\ : label is "soft_lutpair686";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[17]_i_8\ : label is "soft_lutpair686";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[18]_i_3\ : label is "soft_lutpair731";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[18]_i_5\ : label is "soft_lutpair715";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[18]_i_6\ : label is "soft_lutpair714";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[18]_i_7\ : label is "soft_lutpair722";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[18]_i_9\ : label is "soft_lutpair729";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[19]_i_10\ : label is "soft_lutpair657";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[19]_i_11\ : label is "soft_lutpair721";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[19]_i_3\ : label is "soft_lutpair730";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[19]_i_5\ : label is "soft_lutpair771";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[19]_i_6\ : label is "soft_lutpair716";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[19]_i_7\ : label is "soft_lutpair707";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[19]_i_9\ : label is "soft_lutpair655";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[20]_i_3\ : label is "soft_lutpair730";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[20]_i_6\ : label is "soft_lutpair708";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[20]_i_7\ : label is "soft_lutpair717";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[21]_i_14\ : label is "soft_lutpair725";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[21]_i_3\ : label is "soft_lutpair647";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[21]_i_4\ : label is "soft_lutpair728";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[21]_i_6\ : label is "soft_lutpair714";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[21]_i_7\ : label is "soft_lutpair715";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[21]_i_8\ : label is "soft_lutpair722";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[22]_i_13\ : label is "soft_lutpair727";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[22]_i_15\ : label is "soft_lutpair654";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[22]_i_16\ : label is "soft_lutpair656";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[22]_i_17\ : label is "soft_lutpair718";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[22]_i_18\ : label is "soft_lutpair726";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[22]_i_20\ : label is "soft_lutpair724";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[22]_i_21\ : label is "soft_lutpair721";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[22]_i_3\ : label is "soft_lutpair716";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[22]_i_5\ : label is "soft_lutpair707";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[22]_i_6\ : label is "soft_lutpair654";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[22]_i_7\ : label is "soft_lutpair655";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[22]_i_8\ : label is "soft_lutpair728";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[23]_i_10\ : label is "soft_lutpair685";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[23]_i_11\ : label is "soft_lutpair726";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[23]_i_12\ : label is "soft_lutpair727";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[23]_i_14\ : label is "soft_lutpair719";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[23]_i_15\ : label is "soft_lutpair723";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[23]_i_17\ : label is "soft_lutpair719";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[23]_i_19\ : label is "soft_lutpair718";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[23]_i_20\ : label is "soft_lutpair724";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[23]_i_21\ : label is "soft_lutpair725";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[23]_i_4\ : label is "soft_lutpair717";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[23]_i_5\ : label is "soft_lutpair708";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[2]_i_7\ : label is "soft_lutpair729";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[3]_i_10\ : label is "soft_lutpair745";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[3]_i_4\ : label is "soft_lutpair732";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[3]_i_8\ : label is "soft_lutpair659";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[5]_i_4\ : label is "soft_lutpair649";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[6]_i_4\ : label is "soft_lutpair734";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[7]_i_4\ : label is "soft_lutpair771";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[7]_i_5\ : label is "soft_lutpair737";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[7]_i_6\ : label is "soft_lutpair705";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[7]_i_8\ : label is "soft_lutpair740";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[8]_i_4\ : label is "soft_lutpair759";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[8]_i_5\ : label is "soft_lutpair736";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[8]_i_6\ : label is "soft_lutpair706";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[9]_i_10\ : label is "soft_lutpair656";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[9]_i_11\ : label is "soft_lutpair744";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[9]_i_15\ : label is "soft_lutpair742";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[9]_i_18\ : label is "soft_lutpair745";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[9]_i_19\ : label is "soft_lutpair698";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[9]_i_4\ : label is "soft_lutpair720";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[9]_i_5\ : label is "soft_lutpair735";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[9]_i_6\ : label is "soft_lutpair734";
  attribute SOFT_HLUTNM of \toVideoinAXIS_tdata_sig[9]_i_7\ : label is "soft_lutpair657";
  attribute SOFT_HLUTNM of toVideoinAXIS_tvalid_sig_i_1 : label is "soft_lutpair664";
  attribute SOFT_HLUTNM of whtNotBlk_i_3 : label is "soft_lutpair681";
  attribute SOFT_HLUTNM of \wht[0]_i_1\ : label is "soft_lutpair697";
  attribute SOFT_HLUTNM of \wht[10]_i_2\ : label is "soft_lutpair676";
  attribute SOFT_HLUTNM of \wht[1]_i_1\ : label is "soft_lutpair697";
  attribute SOFT_HLUTNM of \wht[2]_i_1\ : label is "soft_lutpair696";
  attribute SOFT_HLUTNM of \wht[3]_i_1\ : label is "soft_lutpair696";
  attribute SOFT_HLUTNM of \wht[4]_i_1\ : label is "soft_lutpair695";
  attribute SOFT_HLUTNM of \wht[5]_i_1\ : label is "soft_lutpair695";
  attribute SOFT_HLUTNM of \wht[6]_i_1\ : label is "soft_lutpair694";
  attribute SOFT_HLUTNM of \wht[7]_i_1\ : label is "soft_lutpair694";
  attribute SOFT_HLUTNM of \wht[8]_i_1\ : label is "soft_lutpair693";
  attribute SOFT_HLUTNM of \wht[9]_i_1\ : label is "soft_lutpair693";
begin
  ackInvCamifConfig <= \^ackinvcamifconfig\;
  ackInvCamifConfigSynth <= \^ackinvcamifconfigsynth\;
  ackInvCamifGetCorereg <= \^ackinvcamifgetcorereg\;
  ackInvCamifGetReg <= \^ackinvcamifgetreg\;
  ackInvCamifModReg <= \^ackinvcamifmodreg\;
  ackInvCamifSetCorereg <= \^ackinvcamifsetcorereg\;
  ackInvCamifSetReg <= \^ackinvcamifsetreg\;
  camifToVideoinAXIS_tdata(23 downto 0) <= \^camiftovideoinaxis_tdata\(23 downto 0);
  camifToVideoinAXIS_tvalid <= \^camiftovideoinaxis_tvalid\;
  \col_reg[10]_0\(7 downto 0) <= \^col_reg[10]_0\(7 downto 0);
  \ixTExp_sig_reg[2]_0\(0) <= \^ixtexp_sig_reg[2]_0\(0);
  \rowRaw_lcl_reg[11]_0\(8 downto 0) <= \^rowraw_lcl_reg[11]_0\(8 downto 0);
  \row_reg[11]_0\(8 downto 0) <= \^row_reg[11]_0\(8 downto 0);
  \stateConfig_reg[3]_0\ <= \^stateconfig_reg[3]_0\;
  \stateLive_reg[2]_0\(2 downto 0) <= \^statelive_reg[2]_0\(2 downto 0);
  stateOp_reg_0 <= \^stateop_reg_0\;
  \stateSynth_reg[2]_0\(0) <= \^statesynth_reg[2]_0\(0);
  synthNotLive_reg_0 <= \^synthnotlive_reg_0\;
\TFramepad_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(18),
      Q => p_0_in(9)
    );
\TFramepad_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(19),
      Q => p_0_in(10)
    );
\TFramepad_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(20),
      Q => p_0_in(11)
    );
\TFramepad_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(21),
      Q => p_0_in(12)
    );
\TFramepad_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(22),
      Q => p_0_in(13)
    );
\TFramepad_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(23),
      Q => p_0_in(14)
    );
\TFramepad_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(9),
      Q => p_0_in(0)
    );
\TFramepad_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(10),
      Q => p_0_in(1)
    );
\TFramepad_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(11),
      Q => p_0_in(2)
    );
\TFramepad_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(12),
      Q => p_0_in(3)
    );
\TFramepad_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(13),
      Q => p_0_in(4)
    );
\TFramepad_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(14),
      Q => p_0_in(5)
    );
\TFramepad_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(15),
      Q => p_0_in(6)
    );
\TFramepad_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(16),
      Q => p_0_in(7)
    );
\TFramepad_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(17),
      Q => p_0_in(8)
    );
\TLinepad_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(0),
      Q => TLinepad(0)
    );
\TLinepad_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(1),
      Q => TLinepad(1)
    );
\TLinepad_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(2),
      Q => TLinepad(2)
    );
\TLinepad_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(3),
      Q => TLinepad(3)
    );
\TLinepad_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(4),
      Q => TLinepad(4)
    );
\TLinepad_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(5),
      Q => TLinepad(5)
    );
\TLinepad_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(6),
      Q => TLinepad(6)
    );
\TLinepad_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => D(7),
      Q => TLinepad(7)
    );
\aParrom[10]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[0]\,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => \stateConfig_reg_n_0_[2]\,
      O => \aParrom[10]_i_3_n_0\
    );
\aParrom[10]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => \k[1]_i_6_n_0\,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => \stateConfig_reg_n_0_[2]\,
      I3 => \stateConfig_reg_n_0_[0]\,
      O => \aParrom[10]_i_4_n_0\
    );
\aParrom[10]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[2]\,
      I1 => \stateConfig_reg_n_0_[0]\,
      I2 => \stateConfig_reg_n_0_[1]\,
      O => \aParrom[10]_i_5_n_0\
    );
\aParrom[10]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9555555555555555"
    )
        port map (
      I0 => \aParrom_reg_n_0_[10]\,
      I1 => \aParrom_reg_n_0_[7]\,
      I2 => \aParrom_reg_n_0_[6]\,
      I3 => \aParrom[8]_i_3_n_0\,
      I4 => \aParrom_reg_n_0_[8]\,
      I5 => \aParrom_reg_n_0_[9]\,
      O => \aParrom[10]_i_6_n_0\
    );
\aParrom[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \aParrom_reg_n_0_[3]\,
      I1 => \aParrom_reg_n_0_[1]\,
      I2 => \aParrom_reg_n_0_[0]\,
      I3 => \aParrom_reg_n_0_[2]\,
      I4 => \aParrom_reg_n_0_[4]\,
      O => \aParrom[5]_i_2_n_0\
    );
\aParrom[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \aParrom_reg_n_0_[5]\,
      I1 => \aParrom_reg_n_0_[4]\,
      I2 => \aParrom_reg_n_0_[2]\,
      I3 => \aParrom_reg_n_0_[0]\,
      I4 => \aParrom_reg_n_0_[1]\,
      I5 => \aParrom_reg_n_0_[3]\,
      O => \aParrom[8]_i_3_n_0\
    );
\aParrom[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \aParrom_reg_n_0_[7]\,
      I1 => \aParrom_reg_n_0_[6]\,
      I2 => \aParrom[8]_i_3_n_0\,
      I3 => \aParrom_reg_n_0_[8]\,
      O => \aParrom[9]_i_2_n_0\
    );
\aParrom[9]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[2]\,
      I1 => \stateConfig_reg_n_0_[3]\,
      O => \aParrom[9]_i_3_n_0\
    );
\aParrom_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_41,
      CLR => sda_sig_reg,
      D => myParrom_n_37,
      Q => \aParrom_reg_n_0_[0]\
    );
\aParrom_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_41,
      CLR => sda_sig_reg,
      D => myParrom_n_27,
      Q => \aParrom_reg_n_0_[10]\
    );
\aParrom_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_41,
      CLR => sda_sig_reg,
      D => myParrom_n_36,
      Q => \aParrom_reg_n_0_[1]\
    );
\aParrom_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_41,
      CLR => sda_sig_reg,
      D => myParrom_n_35,
      Q => \aParrom_reg_n_0_[2]\
    );
\aParrom_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_41,
      CLR => sda_sig_reg,
      D => myParrom_n_34,
      Q => \aParrom_reg_n_0_[3]\
    );
\aParrom_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_41,
      CLR => sda_sig_reg,
      D => myParrom_n_33,
      Q => \aParrom_reg_n_0_[4]\
    );
\aParrom_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_41,
      CLR => sda_sig_reg,
      D => myParrom_n_32,
      Q => \aParrom_reg_n_0_[5]\
    );
\aParrom_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_41,
      CLR => sda_sig_reg,
      D => myParrom_n_31,
      Q => \aParrom_reg_n_0_[6]\
    );
\aParrom_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_41,
      CLR => sda_sig_reg,
      D => myParrom_n_30,
      Q => \aParrom_reg_n_0_[7]\
    );
\aParrom_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_41,
      CLR => sda_sig_reg,
      D => myParrom_n_29,
      Q => \aParrom_reg_n_0_[8]\
    );
\aParrom_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_41,
      CLR => sda_sig_reg,
      D => myParrom_n_28,
      Q => \aParrom_reg_n_0_[9]\
    );
ackInvConfigSynth_sig_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5D5DFF5D"
    )
        port map (
      I0 => \^stateop_reg_0\,
      I1 => \^ackinvcamifconfigsynth\,
      I2 => reqInvConfigSynth,
      I3 => \^ackinvcamifconfig\,
      I4 => reqInvConfig,
      O => stateOp
    );
ackInvConfigSynth_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stateOp,
      CLR => sda_sig_reg,
      D => E(0),
      Q => \^ackinvcamifconfigsynth\
    );
ackInvConfig_sig_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \^stateop_reg_0\,
      I1 => reqInvConfig,
      O => hdrNotFix48_out
    );
ackInvConfig_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stateOp,
      CLR => sda_sig_reg,
      D => hdrNotFix48_out,
      Q => \^ackinvcamifconfig\
    );
ackInvGetCorereg_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F7FFCFF30300000"
    )
        port map (
      I0 => stateCorecfg0,
      I1 => \stateCorecfg_reg_n_0_[2]\,
      I2 => \stateCorecfg_reg_n_0_[1]\,
      I3 => ackInvGetCorereg_sig_reg_0,
      I4 => \stateCorecfg_reg_n_0_[0]\,
      I5 => \^ackinvcamifgetcorereg\,
      O => ackInvGetCorereg_sig_i_1_n_0
    );
ackInvGetCorereg_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg,
      D => ackInvGetCorereg_sig_i_1_n_0,
      Q => \^ackinvcamifgetcorereg\
    );
ackInvGetReg_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"010101FF01010100"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[0]\,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => ackInvGetReg_sig_i_2_n_0,
      I3 => ackInvGetReg_sig_i_3_n_0,
      I4 => \regVal[7]_i_1_n_0\,
      I5 => \^ackinvcamifgetreg\,
      O => ackInvGetReg_sig_i_1_n_0
    );
ackInvGetReg_sig_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[2]\,
      I1 => \stateConfig_reg_n_0_[3]\,
      O => ackInvGetReg_sig_i_2_n_0
    );
ackInvGetReg_sig_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AE000000"
    )
        port map (
      I0 => ackLiveToConfigSetReg_reg_0,
      I1 => ackLiveToConfigSetReg_reg_n_0,
      I2 => modNotGetSet_i_2_n_0,
      I3 => \stateConfig_reg_n_0_[1]\,
      I4 => \stateConfig_reg_n_0_[0]\,
      I5 => ackInvGetReg_sig_i_2_n_0,
      O => ackInvGetReg_sig_i_3_n_0
    );
ackInvGetReg_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg,
      D => ackInvGetReg_sig_i_1_n_0,
      Q => \^ackinvcamifgetreg\
    );
ackInvModReg_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010FFFF00100000"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[0]\,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => \stateConfig_reg_n_0_[3]\,
      I3 => \stateConfig_reg_n_0_[2]\,
      I4 => ackInvModReg_sig_i_2_n_0,
      I5 => \^ackinvcamifmodreg\,
      O => ackInvModReg_sig_i_1_n_0
    );
ackInvModReg_sig_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFBBBBBBAAAAAAAA"
    )
        port map (
      I0 => ackInvGetReg_sig_i_3_n_0,
      I1 => \stateConfig_reg_n_0_[3]\,
      I2 => i2cReadNotWrite,
      I3 => prepdone,
      I4 => modNotGetSet,
      I5 => \aParrom[10]_i_3_n_0\,
      O => ackInvModReg_sig_i_2_n_0
    );
ackInvModReg_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg,
      D => ackInvModReg_sig_i_1_n_0,
      Q => \^ackinvcamifmodreg\
    );
ackInvSetCorereg_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \stateCorecfg_reg_n_0_[2]\,
      I1 => \stateCorecfg_reg_n_0_[0]\,
      I2 => corecfgAXIL_bvalid,
      I3 => \stateCorecfg_reg_n_0_[1]\,
      I4 => ackInvSetCorereg_sig_i_2_n_0,
      I5 => \^ackinvcamifsetcorereg\,
      O => ackInvSetCorereg_sig_i_1_n_0
    );
ackInvSetCorereg_sig_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800B80000330000"
    )
        port map (
      I0 => stateCorecfg0,
      I1 => \stateCorecfg_reg_n_0_[0]\,
      I2 => corecfgAXIL_bvalid,
      I3 => \stateCorecfg_reg_n_0_[1]\,
      I4 => ackInvGetCorereg_sig_reg_0,
      I5 => \stateCorecfg_reg_n_0_[2]\,
      O => ackInvSetCorereg_sig_i_2_n_0
    );
ackInvSetCorereg_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg,
      D => ackInvSetCorereg_sig_i_1_n_0,
      Q => \^ackinvcamifsetcorereg\
    );
ackInvSetReg_sig_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"010101FF01010100"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[0]\,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => ackInvGetReg_sig_i_2_n_0,
      I3 => ackInvGetReg_sig_i_3_n_0,
      I4 => ackInvSetReg_sig_i_2_n_0,
      I5 => \^ackinvcamifsetreg\,
      O => ackInvSetReg_sig_i_1_n_0
    );
ackInvSetReg_sig_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000200AAAAAAAA"
    )
        port map (
      I0 => \aParrom[10]_i_3_n_0\,
      I1 => modNotGetSet,
      I2 => i2cReadNotWrite,
      I3 => prepdone,
      I4 => liveNotExt,
      I5 => \stateConfig_reg_n_0_[3]\,
      O => ackInvSetReg_sig_i_2_n_0
    );
ackInvSetReg_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg,
      D => ackInvSetReg_sig_i_1_n_0,
      Q => \^ackinvcamifsetreg\
    );
ackLiveToConfigSetReg_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"010101FF01010100"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[0]\,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => ackInvGetReg_sig_i_2_n_0,
      I3 => ackInvGetReg_sig_i_3_n_0,
      I4 => ackLiveToConfigSetReg_i_2_n_0,
      I5 => ackLiveToConfigSetReg_reg_n_0,
      O => ackLiveToConfigSetReg_i_1_n_0
    );
ackLiveToConfigSetReg_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000000000000"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[3]\,
      I1 => modNotGetSet,
      I2 => i2cReadNotWrite,
      I3 => liveNotExt,
      I4 => prepdone,
      I5 => \aParrom[10]_i_3_n_0\,
      O => ackLiveToConfigSetReg_i_2_n_0
    );
ackLiveToConfigSetReg_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg,
      D => ackLiveToConfigSetReg_i_1_n_0,
      Q => ackLiveToConfigSetReg_reg_n_0
    );
\b_lcl[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF77F"
    )
        port map (
      I0 => rng,
      I1 => \b_lcl_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \^statesynth_reg[2]_0\(0),
      O => \b_lcl[0]_i_1_n_0\
    );
\b_lcl[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFD7FFFFFFFFFFD7"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \b_lcl[10]_i_2_n_0\,
      I5 => \b_lcl_reg_n_0_[10]\,
      O => \b_lcl[10]_i_1_n_0\
    );
\b_lcl[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[8]\,
      I1 => \b_lcl_reg_n_0_[6]\,
      I2 => \b_lcl[6]_i_2_n_0\,
      I3 => \b_lcl_reg_n_0_[7]\,
      I4 => \b_lcl_reg_n_0_[9]\,
      O => \b_lcl[10]_i_2_n_0\
    );
\b_lcl[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FA00FA00FEFFFE00"
    )
        port map (
      I0 => \b_lcl[11]_i_3_n_0\,
      I1 => \b_lcl[11]_i_4_n_0\,
      I2 => \b_lcl[11]_i_5_n_0\,
      I3 => \stateSynth[2]_i_7_n_0\,
      I4 => rng,
      I5 => \bsh[1]_i_3_n_0\,
      O => \b_lcl[11]_i_1_n_0\
    );
\b_lcl[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFD7FFFFFFFFFFD7"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \b_lcl[11]_i_6_n_0\,
      I5 => \b_lcl_reg_n_0_[11]\,
      O => \b_lcl[11]_i_2_n_0\
    );
\b_lcl[11]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001400"
    )
        port map (
      I0 => \^statesynth_reg[2]_0\(0),
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \i_reg[0]__0_0\,
      O => \b_lcl[11]_i_3_n_0\
    );
\b_lcl[11]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[0]\,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \row[11]_i_5_n_0\,
      O => \b_lcl[11]_i_4_n_0\
    );
\b_lcl[11]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => \stateSynth[2]_i_6_n_0\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => p_0_in0,
      I4 => \stateSynth_reg_n_0_[1]\,
      I5 => \b_lcl[11]_i_7_n_0\,
      O => \b_lcl[11]_i_5_n_0\
    );
\b_lcl[11]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[9]\,
      I1 => \b_lcl_reg_n_0_[7]\,
      I2 => \b_lcl[6]_i_2_n_0\,
      I3 => \b_lcl_reg_n_0_[6]\,
      I4 => \b_lcl_reg_n_0_[8]\,
      I5 => \b_lcl_reg_n_0_[10]\,
      O => \b_lcl[11]_i_6_n_0\
    );
\b_lcl[11]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7777777777777770"
    )
        port map (
      I0 => \stateSynth[0]_i_4_n_0\,
      I1 => \row_reg_n_0_[0]\,
      I2 => \b_lcl[11]_i_8_n_0\,
      I3 => \tixVSynthmode_reg_n_0_[5]\,
      I4 => \tixVSynthmode_reg_n_0_[3]\,
      I5 => \tixVSynthmode_reg_n_0_[4]\,
      O => \b_lcl[11]_i_7_n_0\
    );
\b_lcl[11]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => \tixVSynthmode_reg_n_0_[2]\,
      I1 => \tixVSynthmode_reg_n_0_[6]\,
      I2 => \tixVSynthmode_reg_n_0_[5]\,
      I3 => \tixVSynthmode_reg_n_0_[1]\,
      I4 => \tixVSynthmode_reg_n_0_[0]\,
      I5 => \row_reg_n_0_[0]\,
      O => \b_lcl[11]_i_8_n_0\
    );
\b_lcl[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFD7D7FF"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \b_lcl_reg_n_0_[1]\,
      I4 => \b_lcl_reg_n_0_[0]\,
      I5 => \^statesynth_reg[2]_0\(0),
      O => \b_lcl[1]_i_1_n_0\
    );
\b_lcl[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAB"
    )
        port map (
      I0 => \b_lcl[5]_i_2_n_0\,
      I1 => \b_lcl_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[1]\,
      I3 => \b_lcl_reg_n_0_[2]\,
      O => \b_lcl[2]_i_1_n_0\
    );
\b_lcl[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEAAAB"
    )
        port map (
      I0 => \b_lcl[5]_i_2_n_0\,
      I1 => \b_lcl_reg_n_0_[1]\,
      I2 => \b_lcl_reg_n_0_[0]\,
      I3 => \b_lcl_reg_n_0_[2]\,
      I4 => \b_lcl_reg_n_0_[3]\,
      O => \b_lcl[3]_i_1_n_0\
    );
\b_lcl[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEAAAAAAAB"
    )
        port map (
      I0 => \b_lcl[5]_i_2_n_0\,
      I1 => \b_lcl_reg_n_0_[3]\,
      I2 => \b_lcl_reg_n_0_[2]\,
      I3 => \b_lcl_reg_n_0_[0]\,
      I4 => \b_lcl_reg_n_0_[1]\,
      I5 => \b_lcl_reg_n_0_[4]\,
      O => \b_lcl[4]_i_1_n_0\
    );
\b_lcl[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BE"
    )
        port map (
      I0 => \b_lcl[5]_i_2_n_0\,
      I1 => \b_lcl[5]_i_3_n_0\,
      I2 => \b_lcl_reg_n_0_[5]\,
      O => \b_lcl[5]_i_1_n_0\
    );
\b_lcl[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF4F4FFFFFFFFFF"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[11]\,
      I1 => \b_lcl[11]_i_6_n_0\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[0]\,
      I4 => \stateSynth_reg_n_0_[1]\,
      I5 => rng,
      O => \b_lcl[5]_i_2_n_0\
    );
\b_lcl[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[4]\,
      I1 => \b_lcl_reg_n_0_[1]\,
      I2 => \b_lcl_reg_n_0_[0]\,
      I3 => \b_lcl_reg_n_0_[2]\,
      I4 => \b_lcl_reg_n_0_[3]\,
      O => \b_lcl[5]_i_3_n_0\
    );
\b_lcl[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFD7FFFFFFFFFFD7"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \b_lcl[6]_i_2_n_0\,
      I5 => \b_lcl_reg_n_0_[6]\,
      O => \b_lcl[6]_i_1_n_0\
    );
\b_lcl[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[3]\,
      I1 => \b_lcl_reg_n_0_[2]\,
      I2 => \b_lcl_reg_n_0_[0]\,
      I3 => \b_lcl_reg_n_0_[1]\,
      I4 => \b_lcl_reg_n_0_[4]\,
      I5 => \b_lcl_reg_n_0_[5]\,
      O => \b_lcl[6]_i_2_n_0\
    );
\b_lcl[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFD7FFFFFFFFFFD7"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \b_lcl[7]_i_2_n_0\,
      I5 => \b_lcl_reg_n_0_[7]\,
      O => \b_lcl[7]_i_1_n_0\
    );
\b_lcl[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \b_lcl[6]_i_2_n_0\,
      I1 => \b_lcl_reg_n_0_[6]\,
      O => \b_lcl[7]_i_2_n_0\
    );
\b_lcl[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFD7FFFFFFFFFFD7"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \b_lcl[8]_i_2_n_0\,
      I5 => \b_lcl_reg_n_0_[8]\,
      O => \b_lcl[8]_i_1_n_0\
    );
\b_lcl[8]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[6]\,
      I1 => \b_lcl[6]_i_2_n_0\,
      I2 => \b_lcl_reg_n_0_[7]\,
      O => \b_lcl[8]_i_2_n_0\
    );
\b_lcl[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFD7FFFFFFFFFFD7"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \b_lcl[9]_i_2_n_0\,
      I5 => \b_lcl_reg_n_0_[9]\,
      O => \b_lcl[9]_i_1_n_0\
    );
\b_lcl[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[7]\,
      I1 => \b_lcl[6]_i_2_n_0\,
      I2 => \b_lcl_reg_n_0_[6]\,
      I3 => \b_lcl_reg_n_0_[8]\,
      O => \b_lcl[9]_i_2_n_0\
    );
\b_lcl_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \b_lcl[0]_i_1_n_0\,
      Q => \b_lcl_reg_n_0_[0]\
    );
\b_lcl_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \b_lcl[10]_i_1_n_0\,
      Q => \b_lcl_reg_n_0_[10]\
    );
\b_lcl_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \b_lcl[11]_i_2_n_0\,
      Q => \b_lcl_reg_n_0_[11]\
    );
\b_lcl_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \b_lcl[1]_i_1_n_0\,
      Q => \b_lcl_reg_n_0_[1]\
    );
\b_lcl_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \b_lcl[2]_i_1_n_0\,
      Q => \b_lcl_reg_n_0_[2]\
    );
\b_lcl_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \b_lcl[3]_i_1_n_0\,
      Q => \b_lcl_reg_n_0_[3]\
    );
\b_lcl_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \b_lcl[4]_i_1_n_0\,
      Q => \b_lcl_reg_n_0_[4]\
    );
\b_lcl_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \b_lcl[5]_i_1_n_0\,
      Q => \b_lcl_reg_n_0_[5]\
    );
\b_lcl_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \b_lcl[6]_i_1_n_0\,
      Q => \b_lcl_reg_n_0_[6]\
    );
\b_lcl_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \b_lcl[7]_i_1_n_0\,
      Q => \b_lcl_reg_n_0_[7]\
    );
\b_lcl_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \b_lcl[8]_i_1_n_0\,
      Q => \b_lcl_reg_n_0_[8]\
    );
\b_lcl_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \b_lcl[9]_i_1_n_0\,
      Q => \b_lcl_reg_n_0_[9]\
    );
\blk[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \blk_reg_n_0_[1]\,
      I1 => \blk_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => rng,
      O => blk1_out(0)
    );
\blk[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAA20AA00"
    )
        port map (
      I0 => \rowchk[3]_i_4_n_0\,
      I1 => \blk[10]_i_3_n_0\,
      I2 => \stateSynth[2]_i_6_n_0\,
      I3 => \blk[10]_i_4_n_0\,
      I4 => \blk[10]_i_5_n_0\,
      I5 => \blk[10]_i_6_n_0\,
      O => wht(10)
    );
\blk[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \blk_reg_n_0_[0]\,
      O => blk1_out(10)
    );
\blk[10]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \rowchk[3]_i_3_n_0\,
      O => \blk[10]_i_3_n_0\
    );
\blk[10]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \row[11]_i_5_n_0\,
      I1 => \rowchk[3]_i_3_n_0\,
      O => \blk[10]_i_4_n_0\
    );
\blk[10]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \rowchk_reg_n_0_[2]\,
      I1 => \rowchk_reg_n_0_[3]\,
      I2 => \rowchk_reg_n_0_[1]\,
      I3 => \rowchk_reg_n_0_[0]\,
      O => \blk[10]_i_5_n_0\
    );
\blk[10]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00020000"
    )
        port map (
      I0 => \rowchk[3]_i_3_n_0\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => rng,
      O => \blk[10]_i_6_n_0\
    );
\blk[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \blk_reg_n_0_[2]\,
      I1 => \blk_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => rng,
      O => blk1_out(1)
    );
\blk[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \blk_reg_n_0_[3]\,
      I1 => \blk_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => rng,
      O => blk1_out(2)
    );
\blk[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \blk_reg_n_0_[4]\,
      I1 => \blk_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => rng,
      O => blk1_out(3)
    );
\blk[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \blk_reg_n_0_[5]\,
      I1 => \blk_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => rng,
      O => blk1_out(4)
    );
\blk[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \blk_reg_n_0_[6]\,
      I1 => \blk_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => rng,
      O => blk1_out(5)
    );
\blk[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \blk_reg_n_0_[7]\,
      I1 => \blk_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => rng,
      O => blk1_out(6)
    );
\blk[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \blk_reg_n_0_[8]\,
      I1 => \blk_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => rng,
      O => blk1_out(7)
    );
\blk[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \blk_reg_n_0_[9]\,
      I1 => \blk_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => rng,
      O => blk1_out(8)
    );
\blk[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \blk_reg_n_0_[10]\,
      I1 => \blk_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => rng,
      O => blk1_out(9)
    );
\blk_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => blk1_out(0),
      Q => \blk_reg_n_0_[0]\
    );
\blk_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => blk1_out(10),
      Q => \blk_reg_n_0_[10]\
    );
\blk_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => blk1_out(1),
      Q => \blk_reg_n_0_[1]\
    );
\blk_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => blk1_out(2),
      Q => \blk_reg_n_0_[2]\
    );
\blk_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => blk1_out(3),
      Q => \blk_reg_n_0_[3]\
    );
\blk_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => blk1_out(4),
      Q => \blk_reg_n_0_[4]\
    );
\blk_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => blk1_out(5),
      Q => \blk_reg_n_0_[5]\
    );
\blk_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => blk1_out(6),
      Q => \blk_reg_n_0_[6]\
    );
\blk_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => blk1_out(7),
      Q => \blk_reg_n_0_[7]\
    );
\blk_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => blk1_out(8),
      Q => \blk_reg_n_0_[8]\
    );
\blk_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => blk1_out(9),
      Q => \blk_reg_n_0_[9]\
    );
\bsh[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \bsh_reg_n_0_[0]\,
      I5 => \bsh_reg_n_0_[1]\,
      O => \bsh[0]_i_1_n_0\
    );
\bsh[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10FF101010101010"
    )
        port map (
      I0 => \bsh[1]_i_3_n_0\,
      I1 => \stateSynth[2]_i_3_n_0\,
      I2 => \tixVSynthmode_reg_n_0_[0]\,
      I3 => \bsh[1]_i_4_n_0\,
      I4 => \bsh[1]_i_5_n_0\,
      I5 => rng,
      O => bsh
    );
\bsh[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFFFDFFFFFFFDF"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \bsh_reg_n_0_[0]\,
      I5 => \bsh_reg_n_0_[1]\,
      O => \bsh[1]_i_2_n_0\
    );
\bsh[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \tixVSynthmode_reg_n_0_[1]\,
      I1 => \stateSynth[2]_i_11_n_0\,
      O => \bsh[1]_i_3_n_0\
    );
\bsh[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F5F5F5F"
    )
        port map (
      I0 => \row[11]_i_5_n_0\,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth[0]_i_4_n_0\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \stateSynth[2]_i_6_n_0\,
      O => \bsh[1]_i_4_n_0\
    );
\bsh[1]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^statesynth_reg[2]_0\(0),
      I1 => \stateSynth_reg_n_0_[0]\,
      O => \bsh[1]_i_5_n_0\
    );
\bsh_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => bsh,
      CLR => sda_sig_reg,
      D => \bsh[0]_i_1_n_0\,
      Q => \bsh_reg_n_0_[0]\
    );
\bsh_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => bsh,
      CLR => sda_sig_reg,
      D => \bsh[1]_i_2_n_0\,
      Q => \bsh_reg_n_0_[1]\
    );
\bytecnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEEAEEEEAEEAAAAA"
    )
        port map (
      I0 => \bytecnt[1]_i_2_n_0\,
      I1 => \bytecnt[1]_i_3_n_0\,
      I2 => \bytecnt_reg_n_0_[0]\,
      I3 => \bytecnt_reg_n_0_[1]\,
      I4 => \bytecnt[1]_i_4_n_0\,
      I5 => prepdone,
      O => \bytecnt[1]_i_1_n_0\
    );
\bytecnt[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0D0F000"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[1]\,
      I1 => \stateConfig_reg_n_0_[2]\,
      I2 => prepdone,
      I3 => \stateConfig_reg_n_0_[3]\,
      I4 => \stateConfig_reg_n_0_[0]\,
      O => \bytecnt[1]_i_2_n_0\
    );
\bytecnt[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[3]\,
      I1 => \stateConfig_reg_n_0_[0]\,
      O => \bytecnt[1]_i_3_n_0\
    );
\bytecnt[1]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[2]\,
      I1 => \stateConfig_reg_n_0_[1]\,
      O => \bytecnt[1]_i_4_n_0\
    );
\bytecnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAFFFFAAAE"
    )
        port map (
      I0 => \bytecnt[2]_i_3_n_0\,
      I1 => ackLiveToConfigSetReg,
      I2 => prepdone,
      I3 => i2cReadNotWrite,
      I4 => \bytecnt[2]_i_4_n_0\,
      I5 => sda_sig_reg,
      O => bytecnt0
    );
\bytecnt[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE02F300FF00FF00"
    )
        port map (
      I0 => \stateConfig[3]_i_5_n_0\,
      I1 => \stateConfig_reg_n_0_[0]\,
      I2 => \stateConfig_reg_n_0_[3]\,
      I3 => prepdone,
      I4 => \stateConfig_reg_n_0_[2]\,
      I5 => \stateConfig_reg_n_0_[1]\,
      O => \bytecnt[2]_i_2_n_0\
    );
\bytecnt[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000000"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[3]\,
      I1 => sda_sig_reg,
      I2 => \stateConfig_reg_n_0_[0]\,
      I3 => \stateConfig_reg_n_0_[2]\,
      I4 => \stateConfig_reg_n_0_[1]\,
      I5 => \k[1]_i_6_n_0\,
      O => \bytecnt[2]_i_3_n_0\
    );
\bytecnt[2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[0]\,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => \stateConfig_reg_n_0_[3]\,
      I3 => \stateConfig_reg_n_0_[2]\,
      O => \bytecnt[2]_i_4_n_0\
    );
\bytecnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => bytecnt0,
      D => myParrom_n_38,
      Q => \bytecnt_reg_n_0_[0]\,
      R => '0'
    );
\bytecnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => bytecnt0,
      D => \bytecnt[1]_i_1_n_0\,
      Q => \bytecnt_reg_n_0_[1]\,
      R => '0'
    );
\bytecnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => bytecnt0,
      D => \bytecnt[2]_i_2_n_0\,
      Q => \bytecnt_reg_n_0_[2]\,
      R => '0'
    );
\capt[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^synthnotlive_reg_0\,
      I1 => \capt_reg[0]\,
      O => \mask_reg[0]\(0)
    );
\col[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E0"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[0]\,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => rng,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => col(0),
      O => \col[0]_i_1_n_0\
    );
\col[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \stateSynth[2]_i_9_n_0\,
      I1 => \row[11]_i_1_n_0\,
      O => \col[10]_i_1_n_0\
    );
\col[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000444044400000"
    )
        port map (
      I0 => \^statesynth_reg[2]_0\(0),
      I1 => rng,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \stateSynth_reg_n_0_[0]\,
      I4 => \^col_reg[10]_0\(7),
      I5 => \col[10]_i_3_n_0\,
      O => \col[10]_i_2_n_0\
    );
\col[10]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^col_reg[10]_0\(5),
      I1 => \^col_reg[10]_0\(3),
      I2 => \col[9]_i_3_n_0\,
      I3 => \^col_reg[10]_0\(4),
      I4 => \^col_reg[10]_0\(6),
      O => \col[10]_i_3_n_0\
    );
\col[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000E000E00000"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[0]\,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => rng,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => col(1),
      I5 => col(0),
      O => \col[1]_i_1_n_0\
    );
\col[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \col[9]_i_2_n_0\,
      I1 => col(0),
      I2 => col(1),
      I3 => col(2),
      O => \col[2]_i_1_n_0\
    );
\col[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \col[9]_i_2_n_0\,
      I1 => \^col_reg[10]_0\(0),
      I2 => col(1),
      I3 => col(0),
      I4 => col(2),
      O => \col[3]_i_1_n_0\
    );
\col[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \col[9]_i_2_n_0\,
      I1 => \^col_reg[10]_0\(1),
      I2 => col(2),
      I3 => col(0),
      I4 => col(1),
      I5 => \^col_reg[10]_0\(0),
      O => \col[4]_i_1_n_0\
    );
\col[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000444044400000"
    )
        port map (
      I0 => \^statesynth_reg[2]_0\(0),
      I1 => rng,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \stateSynth_reg_n_0_[0]\,
      I4 => \^col_reg[10]_0\(2),
      I5 => \col[5]_i_2_n_0\,
      O => \col[5]_i_1_n_0\
    );
\col[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^col_reg[10]_0\(0),
      I1 => col(1),
      I2 => col(0),
      I3 => col(2),
      I4 => \^col_reg[10]_0\(1),
      O => \col[5]_i_2_n_0\
    );
\col[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000444044400000"
    )
        port map (
      I0 => \^statesynth_reg[2]_0\(0),
      I1 => rng,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \stateSynth_reg_n_0_[0]\,
      I4 => \^col_reg[10]_0\(3),
      I5 => \col[9]_i_3_n_0\,
      O => \col[6]_i_1_n_0\
    );
\col[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2888"
    )
        port map (
      I0 => \col[9]_i_2_n_0\,
      I1 => \^col_reg[10]_0\(4),
      I2 => \col[9]_i_3_n_0\,
      I3 => \^col_reg[10]_0\(3),
      O => \col[7]_i_1_n_0\
    );
\col[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28888888"
    )
        port map (
      I0 => \col[9]_i_2_n_0\,
      I1 => \^col_reg[10]_0\(5),
      I2 => \^col_reg[10]_0\(3),
      I3 => \col[9]_i_3_n_0\,
      I4 => \^col_reg[10]_0\(4),
      O => \col[8]_i_1_n_0\
    );
\col[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \col[9]_i_2_n_0\,
      I1 => \^col_reg[10]_0\(6),
      I2 => \^col_reg[10]_0\(4),
      I3 => \col[9]_i_3_n_0\,
      I4 => \^col_reg[10]_0\(3),
      I5 => \^col_reg[10]_0\(5),
      O => \col[9]_i_1_n_0\
    );
\col[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \^statesynth_reg[2]_0\(0),
      I1 => rng,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \stateSynth_reg_n_0_[0]\,
      O => \col[9]_i_2_n_0\
    );
\col[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^col_reg[10]_0\(1),
      I1 => col(2),
      I2 => col(0),
      I3 => col(1),
      I4 => \^col_reg[10]_0\(0),
      I5 => \^col_reg[10]_0\(2),
      O => \col[9]_i_3_n_0\
    );
\col_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \col[10]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \col[0]_i_1_n_0\,
      Q => col(0)
    );
\col_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \col[10]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \col[10]_i_2_n_0\,
      Q => \^col_reg[10]_0\(7)
    );
\col_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \col[10]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \col[1]_i_1_n_0\,
      Q => col(1)
    );
\col_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \col[10]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \col[2]_i_1_n_0\,
      Q => col(2)
    );
\col_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \col[10]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \col[3]_i_1_n_0\,
      Q => \^col_reg[10]_0\(0)
    );
\col_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \col[10]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \col[4]_i_1_n_0\,
      Q => \^col_reg[10]_0\(1)
    );
\col_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \col[10]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \col[5]_i_1_n_0\,
      Q => \^col_reg[10]_0\(2)
    );
\col_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \col[10]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \col[6]_i_1_n_0\,
      Q => \^col_reg[10]_0\(3)
    );
\col_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \col[10]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \col[7]_i_1_n_0\,
      Q => \^col_reg[10]_0\(4)
    );
\col_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \col[10]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \col[8]_i_1_n_0\,
      Q => \^col_reg[10]_0\(5)
    );
\col_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \col[10]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \col[9]_i_1_n_0\,
      Q => \^col_reg[10]_0\(6)
    );
\colchk[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => colchk(0),
      I1 => rng,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \stateSynth_reg_n_0_[0]\,
      I4 => \^statesynth_reg[2]_0\(0),
      O => \colchk[0]_i_1_n_0\
    );
\colchk[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000FB0"
    )
        port map (
      I0 => colchk(2),
      I1 => colchk(3),
      I2 => colchk(0),
      I3 => colchk(1),
      I4 => \colchk[3]_i_4_n_0\,
      O => \colchk[1]_i_1_n_0\
    );
\colchk[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => colchk(0),
      I1 => colchk(1),
      I2 => colchk(2),
      I3 => \colchk[3]_i_4_n_0\,
      O => \colchk[2]_i_1_n_0\
    );
\colchk[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \rowchk[3]_i_1_n_0\,
      I1 => \colchk[3]_i_3_n_0\,
      O => \colchk[3]_i_1_n_0\
    );
\colchk[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007D80"
    )
        port map (
      I0 => colchk(0),
      I1 => colchk(1),
      I2 => colchk(2),
      I3 => colchk(3),
      I4 => \colchk[3]_i_4_n_0\,
      O => \colchk[3]_i_2_n_0\
    );
\colchk[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000080"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \i_reg[0]__0_0\,
      O => \colchk[3]_i_3_n_0\
    );
\colchk[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFF"
    )
        port map (
      I0 => \^statesynth_reg[2]_0\(0),
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => rng,
      O => \colchk[3]_i_4_n_0\
    );
\colchk_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colchk[3]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \colchk[0]_i_1_n_0\,
      Q => colchk(0)
    );
\colchk_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colchk[3]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \colchk[1]_i_1_n_0\,
      Q => colchk(1)
    );
\colchk_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colchk[3]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \colchk[2]_i_1_n_0\,
      Q => colchk(2)
    );
\colchk_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \colchk[3]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \colchk[3]_i_2_n_0\,
      Q => colchk(3)
    );
\corecfgAXIL_araddr[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001011"
    )
        port map (
      I0 => \stateCorecfg_reg_n_0_[2]\,
      I1 => \stateCorecfg_reg_n_0_[0]\,
      I2 => reqInvGetCorereg,
      I3 => reqInvSetCorereg,
      I4 => \stateCorecfg_reg_n_0_[1]\,
      O => \corecfgAXIL_araddr[12]_i_1_n_0\
    );
\corecfgAXIL_araddr_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_araddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_araddr_reg[12]_0\(6),
      Q => \corecfgAXIL_araddr_reg_n_0_[12]\
    );
\corecfgAXIL_araddr_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_araddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_araddr_reg[12]_0\(0),
      Q => \corecfgAXIL_araddr_reg_n_0_[2]\
    );
\corecfgAXIL_araddr_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_araddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_araddr_reg[12]_0\(1),
      Q => \corecfgAXIL_araddr_reg_n_0_[3]\
    );
\corecfgAXIL_araddr_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_araddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_araddr_reg[12]_0\(2),
      Q => \corecfgAXIL_araddr_reg_n_0_[4]\
    );
\corecfgAXIL_araddr_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_araddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_araddr_reg[12]_0\(3),
      Q => \corecfgAXIL_araddr_reg_n_0_[5]\
    );
\corecfgAXIL_araddr_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_araddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_araddr_reg[12]_0\(4),
      Q => \corecfgAXIL_araddr_reg_n_0_[6]\
    );
\corecfgAXIL_araddr_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_araddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_araddr_reg[12]_0\(5),
      Q => \corecfgAXIL_araddr_reg_n_0_[7]\
    );
\corecfgAXIL_awaddr[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \stateCorecfg_reg_n_0_[2]\,
      I1 => \stateCorecfg_reg_n_0_[0]\,
      I2 => reqInvGetCorereg,
      I3 => \stateCorecfg_reg_n_0_[1]\,
      O => \corecfgAXIL_awaddr[12]_i_1_n_0\
    );
\corecfgAXIL_awaddr_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_awaddr_reg[12]_0\(6),
      Q => \corecfgAXIL_awaddr_reg_n_0_[12]\
    );
\corecfgAXIL_awaddr_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_awaddr_reg[12]_0\(0),
      Q => \corecfgAXIL_awaddr_reg_n_0_[2]\
    );
\corecfgAXIL_awaddr_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_awaddr_reg[12]_0\(1),
      Q => \corecfgAXIL_awaddr_reg_n_0_[3]\
    );
\corecfgAXIL_awaddr_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_awaddr_reg[12]_0\(2),
      Q => \corecfgAXIL_awaddr_reg_n_0_[4]\
    );
\corecfgAXIL_awaddr_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_awaddr_reg[12]_0\(3),
      Q => \corecfgAXIL_awaddr_reg_n_0_[5]\
    );
\corecfgAXIL_awaddr_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_awaddr_reg[12]_0\(4),
      Q => \corecfgAXIL_awaddr_reg_n_0_[6]\
    );
\corecfgAXIL_awaddr_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_awaddr_reg[12]_0\(5),
      Q => \corecfgAXIL_awaddr_reg_n_0_[7]\
    );
\corecfgAXIL_wdata_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(0),
      Q => \corecfgAXIL_wdata_reg_n_0_[0]\
    );
\corecfgAXIL_wdata_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(10),
      Q => \corecfgAXIL_wdata_reg_n_0_[10]\
    );
\corecfgAXIL_wdata_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(11),
      Q => \corecfgAXIL_wdata_reg_n_0_[11]\
    );
\corecfgAXIL_wdata_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(12),
      Q => \corecfgAXIL_wdata_reg_n_0_[12]\
    );
\corecfgAXIL_wdata_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(13),
      Q => \corecfgAXIL_wdata_reg_n_0_[13]\
    );
\corecfgAXIL_wdata_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(14),
      Q => \corecfgAXIL_wdata_reg_n_0_[14]\
    );
\corecfgAXIL_wdata_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(15),
      Q => \corecfgAXIL_wdata_reg_n_0_[15]\
    );
\corecfgAXIL_wdata_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(16),
      Q => \corecfgAXIL_wdata_reg_n_0_[16]\
    );
\corecfgAXIL_wdata_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(17),
      Q => \corecfgAXIL_wdata_reg_n_0_[17]\
    );
\corecfgAXIL_wdata_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(18),
      Q => \corecfgAXIL_wdata_reg_n_0_[18]\
    );
\corecfgAXIL_wdata_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(19),
      Q => \corecfgAXIL_wdata_reg_n_0_[19]\
    );
\corecfgAXIL_wdata_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(1),
      Q => \corecfgAXIL_wdata_reg_n_0_[1]\
    );
\corecfgAXIL_wdata_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(20),
      Q => \corecfgAXIL_wdata_reg_n_0_[20]\
    );
\corecfgAXIL_wdata_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(21),
      Q => \corecfgAXIL_wdata_reg_n_0_[21]\
    );
\corecfgAXIL_wdata_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(22),
      Q => \corecfgAXIL_wdata_reg_n_0_[22]\
    );
\corecfgAXIL_wdata_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(23),
      Q => \corecfgAXIL_wdata_reg_n_0_[23]\
    );
\corecfgAXIL_wdata_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(24),
      Q => \corecfgAXIL_wdata_reg_n_0_[24]\
    );
\corecfgAXIL_wdata_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(25),
      Q => \corecfgAXIL_wdata_reg_n_0_[25]\
    );
\corecfgAXIL_wdata_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(26),
      Q => \corecfgAXIL_wdata_reg_n_0_[26]\
    );
\corecfgAXIL_wdata_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(27),
      Q => \corecfgAXIL_wdata_reg_n_0_[27]\
    );
\corecfgAXIL_wdata_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(28),
      Q => \corecfgAXIL_wdata_reg_n_0_[28]\
    );
\corecfgAXIL_wdata_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(29),
      Q => \corecfgAXIL_wdata_reg_n_0_[29]\
    );
\corecfgAXIL_wdata_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(2),
      Q => \corecfgAXIL_wdata_reg_n_0_[2]\
    );
\corecfgAXIL_wdata_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(30),
      Q => \corecfgAXIL_wdata_reg_n_0_[30]\
    );
\corecfgAXIL_wdata_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(31),
      Q => \corecfgAXIL_wdata_reg_n_0_[31]\
    );
\corecfgAXIL_wdata_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(3),
      Q => \corecfgAXIL_wdata_reg_n_0_[3]\
    );
\corecfgAXIL_wdata_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(4),
      Q => \corecfgAXIL_wdata_reg_n_0_[4]\
    );
\corecfgAXIL_wdata_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(5),
      Q => \corecfgAXIL_wdata_reg_n_0_[5]\
    );
\corecfgAXIL_wdata_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(6),
      Q => \corecfgAXIL_wdata_reg_n_0_[6]\
    );
\corecfgAXIL_wdata_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(7),
      Q => \corecfgAXIL_wdata_reg_n_0_[7]\
    );
\corecfgAXIL_wdata_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(8),
      Q => \corecfgAXIL_wdata_reg_n_0_[8]\
    );
\corecfgAXIL_wdata_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \corecfgAXIL_awaddr[12]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \corecfgAXIL_wdata_reg[31]_0\(9),
      Q => \corecfgAXIL_wdata_reg_n_0_[9]\
    );
\dwrEobuf[39]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^camiftovideoinaxis_tvalid\,
      I1 => \^synthnotlive_reg_0\,
      O => toVideoinAXIS_tvalid_sig_reg_0
    );
\dwrEobuf[56]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^camiftovideoinaxis_tdata\(8),
      I1 => \dwrEobuf_reg[63]\(0),
      O => \klm_reg[0]_6\
    );
\dwrEobuf[56]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[0]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(0),
      O => \^camiftovideoinaxis_tdata\(0)
    );
\dwrEobuf[57]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^camiftovideoinaxis_tdata\(9),
      I1 => \dwrEobuf_reg[63]\(0),
      O => \klm_reg[0]_5\
    );
\dwrEobuf[57]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[1]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(1),
      O => \^camiftovideoinaxis_tdata\(1)
    );
\dwrEobuf[58]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^camiftovideoinaxis_tdata\(10),
      I1 => \dwrEobuf_reg[63]\(0),
      O => \klm_reg[0]_4\
    );
\dwrEobuf[58]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[2]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(2),
      O => \^camiftovideoinaxis_tdata\(2)
    );
\dwrEobuf[59]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^camiftovideoinaxis_tdata\(11),
      I1 => \dwrEobuf_reg[63]\(0),
      O => \klm_reg[0]_3\
    );
\dwrEobuf[59]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[3]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(3),
      O => \^camiftovideoinaxis_tdata\(3)
    );
\dwrEobuf[60]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^camiftovideoinaxis_tdata\(12),
      I1 => \dwrEobuf_reg[63]\(0),
      O => \klm_reg[0]_2\
    );
\dwrEobuf[60]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[4]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(4),
      O => \^camiftovideoinaxis_tdata\(4)
    );
\dwrEobuf[61]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^camiftovideoinaxis_tdata\(13),
      I1 => \dwrEobuf_reg[63]\(0),
      O => \klm_reg[0]_1\
    );
\dwrEobuf[61]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[5]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(5),
      O => \^camiftovideoinaxis_tdata\(5)
    );
\dwrEobuf[62]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^camiftovideoinaxis_tdata\(14),
      I1 => \dwrEobuf_reg[63]\(0),
      O => \klm_reg[0]_0\
    );
\dwrEobuf[62]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[6]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(6),
      O => \^camiftovideoinaxis_tdata\(6)
    );
\dwrEobuf[63]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^camiftovideoinaxis_tdata\(15),
      I1 => \dwrEobuf_reg[63]\(0),
      O => \klm_reg[0]\
    );
\dwrEobuf[63]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[7]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(7),
      O => \^camiftovideoinaxis_tdata\(7)
    );
\dwrEobufp1[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[8]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(8),
      O => \^camiftovideoinaxis_tdata\(8)
    );
\dwrEobufp1[10]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[18]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(18),
      O => \^camiftovideoinaxis_tdata\(18)
    );
\dwrEobufp1[11]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[19]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(19),
      O => \^camiftovideoinaxis_tdata\(19)
    );
\dwrEobufp1[12]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[20]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(20),
      O => \^camiftovideoinaxis_tdata\(20)
    );
\dwrEobufp1[13]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[21]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(21),
      O => \^camiftovideoinaxis_tdata\(21)
    );
\dwrEobufp1[14]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[22]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(22),
      O => \^camiftovideoinaxis_tdata\(22)
    );
\dwrEobufp1[15]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^synthnotlive_reg_0\,
      I1 => \^camiftovideoinaxis_tvalid\,
      I2 => \klm_reg[0]_7\(1),
      O => \stateIgr_reg[1]_1\
    );
\dwrEobufp1[15]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[23]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(23),
      O => \^camiftovideoinaxis_tdata\(23)
    );
\dwrEobufp1[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[9]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(9),
      O => \^camiftovideoinaxis_tdata\(9)
    );
\dwrEobufp1[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[10]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(10),
      O => \^camiftovideoinaxis_tdata\(10)
    );
\dwrEobufp1[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[11]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(11),
      O => \^camiftovideoinaxis_tdata\(11)
    );
\dwrEobufp1[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[12]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(12),
      O => \^camiftovideoinaxis_tdata\(12)
    );
\dwrEobufp1[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[13]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(13),
      O => \^camiftovideoinaxis_tdata\(13)
    );
\dwrEobufp1[6]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[14]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(14),
      O => \^camiftovideoinaxis_tdata\(14)
    );
\dwrEobufp1[7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[15]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(15),
      O => \^camiftovideoinaxis_tdata\(15)
    );
\dwrEobufp1[8]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[16]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(16),
      O => \^camiftovideoinaxis_tdata\(16)
    );
\dwrEobufp1[9]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg_n_0_[17]\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tdata(17),
      O => \^camiftovideoinaxis_tdata\(17)
    );
\dwrRowbuf[25]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => ixTExp(1),
      I1 => ixTExp(0),
      I2 => \^ixtexp_sig_reg[2]_0\(0),
      O => \ixTExp_sig_reg[1]_0\
    );
enEobufB_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^synthnotlive_reg_0\,
      I1 => enEobufB_reg(0),
      O => \FSM_sequential_stateRgbegr_reg[0]\
    );
\g0_lcl[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000044444440"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[0]\,
      I1 => rng,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => \g0_lcl[5]_i_3_n_0\,
      O => \g0_lcl[0]_i_1_n_0\
    );
\g0_lcl[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800280000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \g0_lcl_reg_n_0_[10]\,
      I5 => \g0_lcl[10]_i_2_n_0\,
      O => \g0_lcl[10]_i_1_n_0\
    );
\g0_lcl[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[9]\,
      I1 => \g0_lcl_reg_n_0_[8]\,
      I2 => \g0_lcl_reg_n_0_[7]\,
      I3 => \g0_lcl_reg_n_0_[6]\,
      I4 => \g0_lcl[6]_i_2_n_0\,
      O => \g0_lcl[10]_i_2_n_0\
    );
\g0_lcl[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FC00FC00FEFFFE00"
    )
        port map (
      I0 => \b_lcl[11]_i_4_n_0\,
      I1 => \b_lcl[11]_i_5_n_0\,
      I2 => \g0_lcl[11]_i_3_n_0\,
      I3 => \stateSynth[2]_i_7_n_0\,
      I4 => rng,
      I5 => \bsh[1]_i_3_n_0\,
      O => \g0_lcl[11]_i_1_n_0\
    );
\g0_lcl[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF6F6FFFFFFFFFF"
    )
        port map (
      I0 => \g0_lcl[11]_i_4_n_0\,
      I1 => \g0_lcl_reg_n_0_[11]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[0]\,
      I4 => \stateSynth_reg_n_0_[1]\,
      I5 => rng,
      O => \g0_lcl[11]_i_2_n_0\
    );
\g0_lcl[11]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000014"
    )
        port map (
      I0 => \^statesynth_reg[2]_0\(0),
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \i_reg[0]__0_0\,
      O => \g0_lcl[11]_i_3_n_0\
    );
\g0_lcl[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \g0_lcl[6]_i_2_n_0\,
      I1 => \g0_lcl_reg_n_0_[6]\,
      I2 => \g0_lcl_reg_n_0_[7]\,
      I3 => \g0_lcl_reg_n_0_[8]\,
      I4 => \g0_lcl_reg_n_0_[9]\,
      I5 => \g0_lcl_reg_n_0_[10]\,
      O => \g0_lcl[11]_i_4_n_0\
    );
\g0_lcl[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0060"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[0]\,
      I1 => \g0_lcl_reg_n_0_[1]\,
      I2 => \stateSynth[2]_i_7_n_0\,
      I3 => \g0_lcl[5]_i_3_n_0\,
      O => \g0_lcl[1]_i_1_n_0\
    );
\g0_lcl[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \g1_lcl[3]_i_2_n_0\,
      I1 => \g0_lcl_reg_n_0_[0]\,
      I2 => \g0_lcl_reg_n_0_[1]\,
      I3 => \g0_lcl_reg_n_0_[2]\,
      O => \g0_lcl[2]_i_1_n_0\
    );
\g0_lcl[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \g1_lcl[3]_i_2_n_0\,
      I1 => \g0_lcl_reg_n_0_[1]\,
      I2 => \g0_lcl_reg_n_0_[0]\,
      I3 => \g0_lcl_reg_n_0_[2]\,
      I4 => \g0_lcl_reg_n_0_[3]\,
      O => \g0_lcl[3]_i_1_n_0\
    );
\g0_lcl[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \g0_lcl[4]_i_2_n_0\,
      I1 => \g0_lcl_reg_n_0_[3]\,
      I2 => \g0_lcl_reg_n_0_[2]\,
      I3 => \g0_lcl_reg_n_0_[0]\,
      I4 => \g0_lcl_reg_n_0_[1]\,
      I5 => \g0_lcl_reg_n_0_[4]\,
      O => \g0_lcl[4]_i_1_n_0\
    );
\g0_lcl[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002A002A0000"
    )
        port map (
      I0 => rng,
      I1 => \g0_lcl_reg_n_0_[11]\,
      I2 => \g0_lcl[11]_i_4_n_0\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => \stateSynth_reg_n_0_[1]\,
      O => \g0_lcl[4]_i_2_n_0\
    );
\g0_lcl[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0606060000000000"
    )
        port map (
      I0 => \g0_lcl[5]_i_2_n_0\,
      I1 => \g0_lcl_reg_n_0_[5]\,
      I2 => \g0_lcl[5]_i_3_n_0\,
      I3 => \stateSynth_reg_n_0_[0]\,
      I4 => \stateSynth_reg_n_0_[1]\,
      I5 => rng,
      O => \g0_lcl[5]_i_1_n_0\
    );
\g0_lcl[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[4]\,
      I1 => \g0_lcl_reg_n_0_[1]\,
      I2 => \g0_lcl_reg_n_0_[0]\,
      I3 => \g0_lcl_reg_n_0_[2]\,
      I4 => \g0_lcl_reg_n_0_[3]\,
      O => \g0_lcl[5]_i_2_n_0\
    );
\g0_lcl[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF9F9F9"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \g0_lcl[11]_i_4_n_0\,
      I4 => \g0_lcl_reg_n_0_[11]\,
      O => \g0_lcl[5]_i_3_n_0\
    );
\g0_lcl[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800280000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \g0_lcl_reg_n_0_[6]\,
      I5 => \g0_lcl[6]_i_2_n_0\,
      O => \g0_lcl[6]_i_1_n_0\
    );
\g0_lcl[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[5]\,
      I1 => \g0_lcl_reg_n_0_[3]\,
      I2 => \g0_lcl_reg_n_0_[2]\,
      I3 => \g0_lcl_reg_n_0_[0]\,
      I4 => \g0_lcl_reg_n_0_[1]\,
      I5 => \g0_lcl_reg_n_0_[4]\,
      O => \g0_lcl[6]_i_2_n_0\
    );
\g0_lcl[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800280000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \g0_lcl_reg_n_0_[7]\,
      I5 => \g0_lcl[7]_i_2_n_0\,
      O => \g0_lcl[7]_i_1_n_0\
    );
\g0_lcl[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \g0_lcl[6]_i_2_n_0\,
      I1 => \g0_lcl_reg_n_0_[6]\,
      O => \g0_lcl[7]_i_2_n_0\
    );
\g0_lcl[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0028000000000028"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \g0_lcl[8]_i_2_n_0\,
      I5 => \g0_lcl_reg_n_0_[8]\,
      O => \g0_lcl[8]_i_1_n_0\
    );
\g0_lcl[8]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[7]\,
      I1 => \g0_lcl_reg_n_0_[6]\,
      I2 => \g0_lcl[6]_i_2_n_0\,
      O => \g0_lcl[8]_i_2_n_0\
    );
\g0_lcl[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0028000000000028"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \g0_lcl[9]_i_2_n_0\,
      I5 => \g0_lcl_reg_n_0_[9]\,
      O => \g0_lcl[9]_i_1_n_0\
    );
\g0_lcl[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \g0_lcl[6]_i_2_n_0\,
      I1 => \g0_lcl_reg_n_0_[6]\,
      I2 => \g0_lcl_reg_n_0_[7]\,
      I3 => \g0_lcl_reg_n_0_[8]\,
      O => \g0_lcl[9]_i_2_n_0\
    );
\g0_lcl_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g0_lcl[0]_i_1_n_0\,
      Q => \g0_lcl_reg_n_0_[0]\
    );
\g0_lcl_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g0_lcl[10]_i_1_n_0\,
      Q => \g0_lcl_reg_n_0_[10]\
    );
\g0_lcl_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g0_lcl[11]_i_2_n_0\,
      Q => \g0_lcl_reg_n_0_[11]\
    );
\g0_lcl_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g0_lcl[1]_i_1_n_0\,
      Q => \g0_lcl_reg_n_0_[1]\
    );
\g0_lcl_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g0_lcl[2]_i_1_n_0\,
      Q => \g0_lcl_reg_n_0_[2]\
    );
\g0_lcl_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g0_lcl[3]_i_1_n_0\,
      Q => \g0_lcl_reg_n_0_[3]\
    );
\g0_lcl_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g0_lcl[4]_i_1_n_0\,
      Q => \g0_lcl_reg_n_0_[4]\
    );
\g0_lcl_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g0_lcl[5]_i_1_n_0\,
      Q => \g0_lcl_reg_n_0_[5]\
    );
\g0_lcl_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g0_lcl[6]_i_1_n_0\,
      Q => \g0_lcl_reg_n_0_[6]\
    );
\g0_lcl_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g0_lcl[7]_i_1_n_0\,
      Q => \g0_lcl_reg_n_0_[7]\
    );
\g0_lcl_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g0_lcl[8]_i_1_n_0\,
      Q => \g0_lcl_reg_n_0_[8]\
    );
\g0_lcl_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g0_lcl[9]_i_1_n_0\,
      Q => \g0_lcl_reg_n_0_[9]\
    );
\g1_lcl[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000044444440"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[0]\,
      I1 => rng,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => \g1_lcl[5]_i_3_n_0\,
      O => \g1_lcl[0]_i_1_n_0\
    );
\g1_lcl[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800280000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \g1_lcl_reg_n_0_[10]\,
      I5 => \g1_lcl[10]_i_2_n_0\,
      O => \g1_lcl[10]_i_1_n_0\
    );
\g1_lcl[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[9]\,
      I1 => \g1_lcl_reg_n_0_[8]\,
      I2 => \g1_lcl_reg_n_0_[7]\,
      I3 => \g1_lcl_reg_n_0_[6]\,
      I4 => \g1_lcl[6]_i_2_n_0\,
      O => \g1_lcl[10]_i_2_n_0\
    );
\g1_lcl[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF6F6FFFFFFFFFF"
    )
        port map (
      I0 => \g1_lcl[11]_i_2_n_0\,
      I1 => \g1_lcl_reg_n_0_[11]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[0]\,
      I4 => \stateSynth_reg_n_0_[1]\,
      I5 => rng,
      O => \g1_lcl[11]_i_1_n_0\
    );
\g1_lcl[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \g1_lcl[6]_i_2_n_0\,
      I1 => \g1_lcl_reg_n_0_[6]\,
      I2 => \g1_lcl_reg_n_0_[7]\,
      I3 => \g1_lcl_reg_n_0_[8]\,
      I4 => \g1_lcl_reg_n_0_[9]\,
      I5 => \g1_lcl_reg_n_0_[10]\,
      O => \g1_lcl[11]_i_2_n_0\
    );
\g1_lcl[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0060"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[0]\,
      I1 => \g1_lcl_reg_n_0_[1]\,
      I2 => \stateSynth[2]_i_7_n_0\,
      I3 => \g1_lcl[5]_i_3_n_0\,
      O => \g1_lcl[1]_i_1_n_0\
    );
\g1_lcl[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \g1_lcl[3]_i_2_n_0\,
      I1 => \g1_lcl_reg_n_0_[0]\,
      I2 => \g1_lcl_reg_n_0_[1]\,
      I3 => \g1_lcl_reg_n_0_[2]\,
      O => \g1_lcl[2]_i_1_n_0\
    );
\g1_lcl[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \g1_lcl[3]_i_2_n_0\,
      I1 => \g1_lcl_reg_n_0_[1]\,
      I2 => \g1_lcl_reg_n_0_[0]\,
      I3 => \g1_lcl_reg_n_0_[2]\,
      I4 => \g1_lcl_reg_n_0_[3]\,
      O => \g1_lcl[3]_i_1_n_0\
    );
\g1_lcl[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0028"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      O => \g1_lcl[3]_i_2_n_0\
    );
\g1_lcl[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \g1_lcl[4]_i_2_n_0\,
      I1 => \g1_lcl_reg_n_0_[3]\,
      I2 => \g1_lcl_reg_n_0_[2]\,
      I3 => \g1_lcl_reg_n_0_[0]\,
      I4 => \g1_lcl_reg_n_0_[1]\,
      I5 => \g1_lcl_reg_n_0_[4]\,
      O => \g1_lcl[4]_i_1_n_0\
    );
\g1_lcl[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002A002A0000"
    )
        port map (
      I0 => rng,
      I1 => \g1_lcl_reg_n_0_[11]\,
      I2 => \g1_lcl[11]_i_2_n_0\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => \stateSynth_reg_n_0_[1]\,
      O => \g1_lcl[4]_i_2_n_0\
    );
\g1_lcl[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0606060000000000"
    )
        port map (
      I0 => \g1_lcl[5]_i_2_n_0\,
      I1 => \g1_lcl_reg_n_0_[5]\,
      I2 => \g1_lcl[5]_i_3_n_0\,
      I3 => \stateSynth_reg_n_0_[0]\,
      I4 => \stateSynth_reg_n_0_[1]\,
      I5 => rng,
      O => \g1_lcl[5]_i_1_n_0\
    );
\g1_lcl[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[4]\,
      I1 => \g1_lcl_reg_n_0_[1]\,
      I2 => \g1_lcl_reg_n_0_[0]\,
      I3 => \g1_lcl_reg_n_0_[2]\,
      I4 => \g1_lcl_reg_n_0_[3]\,
      O => \g1_lcl[5]_i_2_n_0\
    );
\g1_lcl[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF9F9F9"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \g1_lcl[11]_i_2_n_0\,
      I4 => \g1_lcl_reg_n_0_[11]\,
      O => \g1_lcl[5]_i_3_n_0\
    );
\g1_lcl[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800280000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \g1_lcl_reg_n_0_[6]\,
      I5 => \g1_lcl[6]_i_2_n_0\,
      O => \g1_lcl[6]_i_1_n_0\
    );
\g1_lcl[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[5]\,
      I1 => \g1_lcl_reg_n_0_[3]\,
      I2 => \g1_lcl_reg_n_0_[2]\,
      I3 => \g1_lcl_reg_n_0_[0]\,
      I4 => \g1_lcl_reg_n_0_[1]\,
      I5 => \g1_lcl_reg_n_0_[4]\,
      O => \g1_lcl[6]_i_2_n_0\
    );
\g1_lcl[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800280000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \g1_lcl_reg_n_0_[7]\,
      I5 => \g1_lcl[7]_i_2_n_0\,
      O => \g1_lcl[7]_i_1_n_0\
    );
\g1_lcl[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \g1_lcl[6]_i_2_n_0\,
      I1 => \g1_lcl_reg_n_0_[6]\,
      O => \g1_lcl[7]_i_2_n_0\
    );
\g1_lcl[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0028000000000028"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \g1_lcl[8]_i_2_n_0\,
      I5 => \g1_lcl_reg_n_0_[8]\,
      O => \g1_lcl[8]_i_1_n_0\
    );
\g1_lcl[8]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[7]\,
      I1 => \g1_lcl_reg_n_0_[6]\,
      I2 => \g1_lcl[6]_i_2_n_0\,
      O => \g1_lcl[8]_i_2_n_0\
    );
\g1_lcl[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0028000000000028"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \g1_lcl[9]_i_2_n_0\,
      I5 => \g1_lcl_reg_n_0_[9]\,
      O => \g1_lcl[9]_i_1_n_0\
    );
\g1_lcl[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \g1_lcl[6]_i_2_n_0\,
      I1 => \g1_lcl_reg_n_0_[6]\,
      I2 => \g1_lcl_reg_n_0_[7]\,
      I3 => \g1_lcl_reg_n_0_[8]\,
      O => \g1_lcl[9]_i_2_n_0\
    );
\g1_lcl_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g1_lcl[0]_i_1_n_0\,
      Q => \g1_lcl_reg_n_0_[0]\
    );
\g1_lcl_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g1_lcl[10]_i_1_n_0\,
      Q => \g1_lcl_reg_n_0_[10]\
    );
\g1_lcl_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g1_lcl[11]_i_1_n_0\,
      Q => \g1_lcl_reg_n_0_[11]\
    );
\g1_lcl_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g1_lcl[1]_i_1_n_0\,
      Q => \g1_lcl_reg_n_0_[1]\
    );
\g1_lcl_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g1_lcl[2]_i_1_n_0\,
      Q => \g1_lcl_reg_n_0_[2]\
    );
\g1_lcl_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g1_lcl[3]_i_1_n_0\,
      Q => \g1_lcl_reg_n_0_[3]\
    );
\g1_lcl_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g1_lcl[4]_i_1_n_0\,
      Q => \g1_lcl_reg_n_0_[4]\
    );
\g1_lcl_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g1_lcl[5]_i_1_n_0\,
      Q => \g1_lcl_reg_n_0_[5]\
    );
\g1_lcl_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g1_lcl[6]_i_1_n_0\,
      Q => \g1_lcl_reg_n_0_[6]\
    );
\g1_lcl_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g1_lcl[7]_i_1_n_0\,
      Q => \g1_lcl_reg_n_0_[7]\
    );
\g1_lcl_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g1_lcl[8]_i_1_n_0\,
      Q => \g1_lcl_reg_n_0_[8]\
    );
\g1_lcl_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \b_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \g1_lcl[9]_i_1_n_0\,
      Q => \g1_lcl_reg_n_0_[9]\
    );
\getCoreregVal_sig[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002808"
    )
        port map (
      I0 => corecfgAXIL_rvalid,
      I1 => \stateCorecfg_reg_n_0_[1]\,
      I2 => \stateCorecfg_reg_n_0_[0]\,
      I3 => corecfgAXIL_arready,
      I4 => \stateCorecfg_reg_n_0_[2]\,
      O => \getCoreregVal_sig[31]_i_1_n_0\
    );
\getCoreregVal_sig_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(0),
      Q => \getCoreregVal_sig_reg[31]_0\(0)
    );
\getCoreregVal_sig_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(10),
      Q => \getCoreregVal_sig_reg[31]_0\(10)
    );
\getCoreregVal_sig_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(11),
      Q => \getCoreregVal_sig_reg[31]_0\(11)
    );
\getCoreregVal_sig_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(12),
      Q => \getCoreregVal_sig_reg[31]_0\(12)
    );
\getCoreregVal_sig_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(13),
      Q => \getCoreregVal_sig_reg[31]_0\(13)
    );
\getCoreregVal_sig_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(14),
      Q => \getCoreregVal_sig_reg[31]_0\(14)
    );
\getCoreregVal_sig_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(15),
      Q => \getCoreregVal_sig_reg[31]_0\(15)
    );
\getCoreregVal_sig_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(16),
      Q => \getCoreregVal_sig_reg[31]_0\(16)
    );
\getCoreregVal_sig_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(17),
      Q => \getCoreregVal_sig_reg[31]_0\(17)
    );
\getCoreregVal_sig_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(18),
      Q => \getCoreregVal_sig_reg[31]_0\(18)
    );
\getCoreregVal_sig_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(19),
      Q => \getCoreregVal_sig_reg[31]_0\(19)
    );
\getCoreregVal_sig_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(1),
      Q => \getCoreregVal_sig_reg[31]_0\(1)
    );
\getCoreregVal_sig_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(20),
      Q => \getCoreregVal_sig_reg[31]_0\(20)
    );
\getCoreregVal_sig_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(21),
      Q => \getCoreregVal_sig_reg[31]_0\(21)
    );
\getCoreregVal_sig_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(22),
      Q => \getCoreregVal_sig_reg[31]_0\(22)
    );
\getCoreregVal_sig_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(23),
      Q => \getCoreregVal_sig_reg[31]_0\(23)
    );
\getCoreregVal_sig_reg[24]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(24),
      Q => camifGetCoreregVal(24)
    );
\getCoreregVal_sig_reg[25]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(25),
      Q => camifGetCoreregVal(25)
    );
\getCoreregVal_sig_reg[26]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(26),
      Q => \getCoreregVal_sig_reg[31]_0\(24)
    );
\getCoreregVal_sig_reg[27]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(27),
      Q => camifGetCoreregVal(27)
    );
\getCoreregVal_sig_reg[28]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(28),
      Q => camifGetCoreregVal(28)
    );
\getCoreregVal_sig_reg[29]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(29),
      Q => camifGetCoreregVal(29)
    );
\getCoreregVal_sig_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(2),
      Q => \getCoreregVal_sig_reg[31]_0\(2)
    );
\getCoreregVal_sig_reg[30]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(30),
      Q => camifGetCoreregVal(30)
    );
\getCoreregVal_sig_reg[31]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(31),
      Q => \getCoreregVal_sig_reg[31]_0\(25)
    );
\getCoreregVal_sig_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(3),
      Q => \getCoreregVal_sig_reg[31]_0\(3)
    );
\getCoreregVal_sig_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(4),
      Q => \getCoreregVal_sig_reg[31]_0\(4)
    );
\getCoreregVal_sig_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(5),
      Q => \getCoreregVal_sig_reg[31]_0\(5)
    );
\getCoreregVal_sig_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(6),
      Q => \getCoreregVal_sig_reg[31]_0\(6)
    );
\getCoreregVal_sig_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(7),
      Q => \getCoreregVal_sig_reg[31]_0\(7)
    );
\getCoreregVal_sig_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(8),
      Q => \getCoreregVal_sig_reg[31]_0\(8)
    );
\getCoreregVal_sig_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \getCoreregVal_sig[31]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => corecfgAXIL_rdata(9),
      Q => \getCoreregVal_sig_reg[31]_0\(9)
    );
\gsh[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF1FFFFF"
    )
        port map (
      I0 => gsh(0),
      I1 => gsh(1),
      I2 => rng,
      I3 => \stateSynth_reg_n_0_[0]\,
      I4 => \^statesynth_reg[2]_0\(0),
      I5 => \stateSynth_reg_n_0_[1]\,
      O => \gsh[0]_i_1_n_0\
    );
\gsh[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000200000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => gsh(0),
      I5 => gsh(1),
      O => \gsh[1]_i_1_n_0\
    );
\gsh_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => bsh,
      CLR => sda_sig_reg,
      D => \gsh[0]_i_1_n_0\,
      Q => gsh(0)
    );
\gsh_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => bsh,
      CLR => sda_sig_reg,
      D => \gsh[1]_i_1_n_0\,
      Q => gsh(1)
    );
hdrNotFix_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => hdrNotFix48_out,
      CLR => sda_sig_reg,
      D => hdrNotFix,
      Q => hdrNotFix_reg_n_0
    );
i2cReadNotWrite_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA00EFFFAA002000"
    )
        port map (
      I0 => i2cReadNotWrite_reg_1,
      I1 => i2cReadNotWrite_reg_0,
      I2 => prepdone,
      I3 => \^stateconfig_reg[3]_0\,
      I4 => i2cReadNotWrite_i_4_n_0,
      I5 => i2cReadNotWrite,
      O => i2cReadNotWrite_i_1_n_0
    );
i2cReadNotWrite_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000E0000A0"
    )
        port map (
      I0 => i2cReadNotWrite_i_5_n_0,
      I1 => \k[1]_i_6_n_0\,
      I2 => \stateConfig_reg_n_0_[3]\,
      I3 => \stateConfig_reg_n_0_[0]\,
      I4 => \stateConfig_reg_n_0_[1]\,
      I5 => \stateConfig_reg_n_0_[2]\,
      O => i2cReadNotWrite_i_4_n_0
    );
i2cReadNotWrite_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => modNotGetSet,
      I1 => i2cReadNotWrite,
      I2 => \stateConfig_reg_n_0_[3]\,
      O => i2cReadNotWrite_i_5_n_0
    );
i2cReadNotWrite_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg,
      D => i2cReadNotWrite_i_1_n_0,
      Q => i2cReadNotWrite
    );
\i2cRegaddr[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000007FFFFFFFF"
    )
        port map (
      I0 => \i2cRegaddr[15]_i_9_n_0\,
      I1 => \^statelive_reg[2]_0\(2),
      I2 => reqInvModReg,
      I3 => reqInvGetReg,
      I4 => reqInvSetReg,
      I5 => prepdone,
      O => \i2cRegaddr[15]_i_3_n_0\
    );
\i2cRegaddr[15]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \bytecnt_reg_n_0_[1]\,
      I1 => \bytecnt_reg_n_0_[2]\,
      I2 => \bytecnt_reg_n_0_[0]\,
      O => \i2cRegaddr[15]_i_4_n_0\
    );
\i2cRegaddr[15]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[3]\,
      I1 => \stateConfig_reg_n_0_[2]\,
      I2 => \stateConfig_reg_n_0_[0]\,
      I3 => \stateConfig_reg_n_0_[1]\,
      O => \^stateconfig_reg[3]_0\
    );
\i2cRegaddr[15]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(0),
      I1 => \^statelive_reg[2]_0\(1),
      O => \i2cRegaddr[15]_i_9_n_0\
    );
\i2cRegaddr[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00002000AAAAAAAA"
    )
        port map (
      I0 => \i2cRegaddr[7]_i_3_n_0\,
      I1 => \bytecnt_reg_n_0_[1]\,
      I2 => \bytecnt_reg_n_0_[0]\,
      I3 => \stateConfig_reg_n_0_[2]\,
      I4 => \bytecnt_reg_n_0_[2]\,
      I5 => \stateConfig_reg_n_0_[1]\,
      O => \i2cRegaddr[7]_i_1_n_0\
    );
\i2cRegaddr[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111100000100"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[0]\,
      I1 => \stateConfig_reg_n_0_[3]\,
      I2 => \stateConfig_reg_n_0_[2]\,
      I3 => prepdone,
      I4 => i2cReadNotWrite_reg_0,
      I5 => \stateConfig_reg_n_0_[1]\,
      O => \i2cRegaddr[7]_i_3_n_0\
    );
\i2cRegaddr_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cRegaddr[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myParrom_n_22,
      Q => \i2cRegaddr_reg_n_0_[0]\
    );
\i2cRegaddr_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myParrom_n_8,
      CLR => sda_sig_reg,
      D => \i2cRegaddr_reg[15]_0\(6),
      Q => \i2cRegaddr_reg_n_0_[10]\
    );
\i2cRegaddr_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myParrom_n_8,
      CLR => sda_sig_reg,
      D => \i2cRegaddr_reg[15]_0\(7),
      Q => \i2cRegaddr_reg_n_0_[11]\
    );
\i2cRegaddr_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myParrom_n_8,
      CLR => sda_sig_reg,
      D => myParrom_n_18,
      Q => \i2cRegaddr_reg_n_0_[12]\
    );
\i2cRegaddr_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myParrom_n_8,
      CLR => sda_sig_reg,
      D => myParrom_n_17,
      Q => \i2cRegaddr_reg_n_0_[13]\
    );
\i2cRegaddr_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myParrom_n_8,
      CLR => sda_sig_reg,
      D => \i2cRegaddr_reg[15]_0\(8),
      Q => \i2cRegaddr_reg_n_0_[14]\
    );
\i2cRegaddr_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myParrom_n_8,
      CLR => sda_sig_reg,
      D => \i2cRegaddr_reg[15]_0\(9),
      Q => \i2cRegaddr_reg_n_0_[15]\
    );
\i2cRegaddr_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cRegaddr[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \i2cRegaddr_reg[15]_0\(0),
      Q => \i2cRegaddr_reg_n_0_[1]\
    );
\i2cRegaddr_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cRegaddr[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \i2cRegaddr_reg[15]_0\(1),
      Q => \i2cRegaddr_reg_n_0_[2]\
    );
\i2cRegaddr_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cRegaddr[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myParrom_n_21,
      Q => \i2cRegaddr_reg_n_0_[3]\
    );
\i2cRegaddr_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cRegaddr[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myParrom_n_20,
      Q => \i2cRegaddr_reg_n_0_[4]\
    );
\i2cRegaddr_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cRegaddr[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \i2cRegaddr_reg[15]_0\(2),
      Q => \i2cRegaddr_reg_n_0_[5]\
    );
\i2cRegaddr_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cRegaddr[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myParrom_n_19,
      Q => \i2cRegaddr_reg_n_0_[6]\
    );
\i2cRegaddr_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cRegaddr[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \i2cRegaddr_reg[15]_0\(3),
      Q => \i2cRegaddr_reg_n_0_[7]\
    );
\i2cRegaddr_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myParrom_n_8,
      CLR => sda_sig_reg,
      D => \i2cRegaddr_reg[15]_0\(4),
      Q => \i2cRegaddr_reg_n_0_[8]\
    );
\i2cRegaddr_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => myParrom_n_8,
      CLR => sda_sig_reg,
      D => \i2cRegaddr_reg[15]_0\(5),
      Q => \i2cRegaddr_reg_n_0_[9]\
    );
\i2cSend[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFD5550000"
    )
        port map (
      I0 => \i2cSend[7]_i_3_n_0\,
      I1 => \stateConfig_reg_n_0_[3]\,
      I2 => i2cReadNotWrite,
      I3 => modNotGetSet,
      I4 => \aParrom[10]_i_3_n_0\,
      I5 => \i2cSend[7]_i_4_n_0\,
      O => \i2cSend[7]_i_1_n_0\
    );
\i2cSend[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBFFFBFFFF"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[3]\,
      I1 => prepdone,
      I2 => reqInvModReg,
      I3 => reqInvGetReg,
      I4 => modNotGetSet_i_2_n_0,
      I5 => reqInvSetReg,
      O => \i2cSend[7]_i_3_n_0\
    );
\i2cSend[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000800"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[1]\,
      I1 => \j[7]_i_8_n_0\,
      I2 => \stateConfig_reg_n_0_[0]\,
      I3 => \bytecnt_reg_n_0_[1]\,
      I4 => \bytecnt_reg_n_0_[0]\,
      I5 => \bytecnt_reg_n_0_[2]\,
      O => \i2cSend[7]_i_4_n_0\
    );
\i2cSend[7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0021"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[2]\,
      I1 => \stateConfig_reg_n_0_[3]\,
      I2 => \stateConfig_reg_n_0_[1]\,
      I3 => \stateConfig_reg_n_0_[0]\,
      O => \i2cSend[7]_i_5_n_0\
    );
\i2cSend_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cSend[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_8,
      Q => \i2cSend_reg_n_0_[0]\
    );
\i2cSend_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cSend[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_7,
      Q => \i2cSend_reg_n_0_[1]\
    );
\i2cSend_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cSend[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_6,
      Q => \i2cSend_reg_n_0_[2]\
    );
\i2cSend_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cSend[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_5,
      Q => \i2cSend_reg_n_0_[3]\
    );
\i2cSend_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cSend[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_4,
      Q => \i2cSend_reg_n_0_[4]\
    );
\i2cSend_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cSend[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_3,
      Q => \i2cSend_reg_n_0_[5]\
    );
\i2cSend_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cSend[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_2,
      Q => \i2cSend_reg_n_0_[6]\
    );
\i2cSend_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \i2cSend[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_1,
      Q => \i2cSend_reg_n_0_[7]\
    );
\i[0]__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5501"
    )
        port map (
      I0 => \i_reg[0]__0_n_0\,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      O => \i[0]__0_i_1_n_0\
    );
\i[0]__1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABBBBBB8A888888"
    )
        port map (
      I0 => \i[0]__1_i_2_n_0\,
      I1 => \i[0]__1_i_3_n_0\,
      I2 => \i_reg[0]__1_0\,
      I3 => hdrNotFix_reg_n_0,
      I4 => \i[0]__1_i_4_n_0\,
      I5 => \i_reg[0]__1_n_0\,
      O => \i[0]__1_i_1_n_0\
    );
\i[0]__1_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => ackLiveToConfigSetReg_reg_n_0,
      I1 => \^statelive_reg[2]_0\(0),
      I2 => \^statelive_reg[2]_0\(2),
      O => \i[0]__1_i_2_n_0\
    );
\i[0]__1_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01110011"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(1),
      I1 => \^statelive_reg[2]_0\(0),
      I2 => \i_reg[0]__1_n_0\,
      I3 => \^statelive_reg[2]_0\(2),
      I4 => ackLiveToConfigSetReg_reg_n_0,
      O => \i[0]__1_i_3_n_0\
    );
\i[0]__1_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => video_out_tvalid,
      I1 => video_out_tlast,
      I2 => \^statelive_reg[2]_0\(2),
      I3 => \^statelive_reg[2]_0\(0),
      O => \i[0]__1_i_4_n_0\
    );
\i[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => i_reg(0),
      O => \i[0]_i_1__0_n_0\
    );
\i[1]__0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => i_reg(1),
      I1 => i_reg(0),
      O => \p_0_in__0\(1)
    );
\i[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66660006"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg[0]__0_n_0\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \stateSynth_reg_n_0_[0]\,
      I4 => \^statesynth_reg[2]_0\(0),
      O => \i[1]_i_1__0_n_0\
    );
\i[2]__0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => i_reg(2),
      I1 => i_reg(0),
      I2 => i_reg(1),
      O => \p_0_in__0\(2)
    );
\i[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00ABAB00AB00AB00"
    )
        port map (
      I0 => \^statesynth_reg[2]_0\(0),
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \i_reg_n_0_[2]\,
      I4 => \i_reg[0]__0_n_0\,
      I5 => \i_reg_n_0_[1]\,
      O => \i[2]_i_1__0_n_0\
    );
\i[3]__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[2]\,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => \stateConfig_reg_n_0_[0]\,
      I3 => sda_sig_reg,
      I4 => \stateConfig_reg_n_0_[3]\,
      I5 => prepdone,
      O => \i[3]__0_i_1_n_0\
    );
\i[3]__0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[3]\,
      I1 => sda_sig_reg,
      I2 => \stateConfig_reg_n_0_[1]\,
      I3 => \stateConfig_reg_n_0_[2]\,
      I4 => tkclk,
      I5 => \stateConfig_reg_n_0_[0]\,
      O => i0
    );
\i[3]__0_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => i_reg(3),
      I1 => i_reg(1),
      I2 => i_reg(0),
      I3 => i_reg(2),
      O => \p_0_in__0\(3)
    );
\i[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"14444444"
    )
        port map (
      I0 => \probe[0]_INST_0_i_2_n_0\,
      I1 => \i_reg_n_0_[3]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \i_reg[0]__0_n_0\,
      I4 => \i_reg_n_0_[2]\,
      O => \i[3]_i_1__0_n_0\
    );
\i[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1444444444444444"
    )
        port map (
      I0 => \probe[0]_INST_0_i_2_n_0\,
      I1 => \i_reg_n_0_[4]\,
      I2 => \i_reg_n_0_[2]\,
      I3 => \i_reg[0]__0_n_0\,
      I4 => \i_reg_n_0_[1]\,
      I5 => \i_reg_n_0_[3]\,
      O => \i[4]_i_1__0_n_0\
    );
\i[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00ABAB00"
    )
        port map (
      I0 => \^statesynth_reg[2]_0\(0),
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \i_reg_n_0_[5]\,
      I4 => \i[5]_i_2__0_n_0\,
      O => \i[5]_i_1__0_n_0\
    );
\i[5]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \i_reg_n_0_[3]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg[0]__0_n_0\,
      I3 => \i_reg_n_0_[2]\,
      I4 => \i_reg_n_0_[4]\,
      O => \i[5]_i_2__0_n_0\
    );
\i[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00ABAB00"
    )
        port map (
      I0 => \^statesynth_reg[2]_0\(0),
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \i_reg_n_0_[6]\,
      I4 => \i[7]_i_5_n_0\,
      O => \i[6]_i_1__0_n_0\
    );
\i[7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => TLinepad(0),
      I1 => \i_reg[0]__0_n_0\,
      I2 => \i_reg_n_0_[1]\,
      I3 => TLinepad(1),
      I4 => \i_reg_n_0_[2]\,
      I5 => TLinepad(2),
      O => \i[7]_i_10_n_0\
    );
\i[7]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => TLinepad(3),
      I1 => \i_reg_n_0_[3]\,
      I2 => \i_reg_n_0_[4]\,
      I3 => TLinepad(4),
      I4 => \i_reg_n_0_[5]\,
      I5 => TLinepad(5),
      O => \i[7]_i_11_n_0\
    );
\i[7]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF6FF6BDDBFFFF"
    )
        port map (
      I0 => col(1),
      I1 => NColRaw(1),
      I2 => col(2),
      I3 => NColRaw(2),
      I4 => col(0),
      I5 => NColRaw(0),
      O => \col_reg[1]_0\
    );
\i[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000444440004000"
    )
        port map (
      I0 => sda_sig_reg,
      I1 => \stateSynth[2]_i_7_n_0\,
      I2 => \i_reg[0]__0_0\,
      I3 => \probe[0]_INST_0_i_2_n_0\,
      I4 => \i[7]_i_4_n_0\,
      I5 => \row[11]_i_6_n_0\,
      O => \i[7]_i_1__0_n_0\
    );
\i[7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A006A006A006A6A"
    )
        port map (
      I0 => \i_reg_n_0_[7]\,
      I1 => \i_reg_n_0_[6]\,
      I2 => \i[7]_i_5_n_0\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => \stateSynth_reg_n_0_[1]\,
      O => \i[7]_i_2__0_n_0\
    );
\i[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000009009"
    )
        port map (
      I0 => \i_reg_n_0_[6]\,
      I1 => TLinepad(6),
      I2 => \i_reg_n_0_[7]\,
      I3 => TLinepad(7),
      I4 => \i[7]_i_10_n_0\,
      I5 => \i[7]_i_11_n_0\,
      O => \i[7]_i_4_n_0\
    );
\i[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \i_reg_n_0_[4]\,
      I1 => \i_reg_n_0_[2]\,
      I2 => \i_reg[0]__0_n_0\,
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[3]\,
      I5 => \i_reg_n_0_[5]\,
      O => \i[7]_i_5_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i0,
      D => \i[0]_i_1__0_n_0\,
      Q => i_reg(0),
      R => \i[3]__0_i_1_n_0\
    );
\i_reg[0]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__0_n_0\,
      D => \i[0]__0_i_1_n_0\,
      Q => \i_reg[0]__0_n_0\,
      R => '0'
    );
\i_reg[0]__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg,
      D => \i[0]__1_i_1_n_0\,
      Q => \i_reg[0]__1_n_0\
    );
\i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__0_n_0\,
      D => \i[1]_i_1__0_n_0\,
      Q => \i_reg_n_0_[1]\,
      R => '0'
    );
\i_reg[1]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i0,
      D => \p_0_in__0\(1),
      Q => i_reg(1),
      R => \i[3]__0_i_1_n_0\
    );
\i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__0_n_0\,
      D => \i[2]_i_1__0_n_0\,
      Q => \i_reg_n_0_[2]\,
      R => '0'
    );
\i_reg[2]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i0,
      D => \p_0_in__0\(2),
      Q => i_reg(2),
      R => \i[3]__0_i_1_n_0\
    );
\i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__0_n_0\,
      D => \i[3]_i_1__0_n_0\,
      Q => \i_reg_n_0_[3]\,
      R => '0'
    );
\i_reg[3]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i0,
      D => \p_0_in__0\(3),
      Q => i_reg(3),
      R => \i[3]__0_i_1_n_0\
    );
\i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__0_n_0\,
      D => \i[4]_i_1__0_n_0\,
      Q => \i_reg_n_0_[4]\,
      R => '0'
    );
\i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__0_n_0\,
      D => \i[5]_i_1__0_n_0\,
      Q => \i_reg_n_0_[5]\,
      R => '0'
    );
\i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__0_n_0\,
      D => \i[6]_i_1__0_n_0\,
      Q => \i_reg_n_0_[6]\,
      R => '0'
    );
\i_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \i[7]_i_1__0_n_0\,
      D => \i[7]_i_2__0_n_0\,
      Q => \i_reg_n_0_[7]\,
      R => '0'
    );
\ixMem[7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^ixtexp_sig_reg[2]_0\(0),
      I1 => ixTExp(1),
      I2 => ixTExp(0),
      O => \ixTExp_sig_reg[2]_1\
    );
\ixMem[7]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ixTExp_sig_reg_n_0_[1]\,
      I1 => synthNotLive_reg_n_0,
      I2 => liveIxTExp(1),
      O => ixTExp(1)
    );
\ixMem[7]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ixTExp_sig_reg_n_0_[0]\,
      I1 => synthNotLive_reg_n_0,
      I2 => liveIxTExp(0),
      O => ixTExp(0)
    );
\ixTExp_lcl[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \ixTExp_lcl_reg_n_0_[2]\,
      I1 => \ixTExp_lcl_reg_n_0_[1]\,
      I2 => \ixTExp_lcl_reg_n_0_[0]\,
      O => \ixTExp_lcl[0]_i_1_n_0\
    );
\ixTExp_lcl[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ixTExp_lcl_reg_n_0_[0]\,
      I1 => \ixTExp_lcl_reg_n_0_[1]\,
      O => \ixTExp_lcl[1]_i_1_n_0\
    );
\ixTExp_lcl[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200000"
    )
        port map (
      I0 => \ixTExp_lcl[2]_i_3_n_0\,
      I1 => \i_reg[0]__1_0\,
      I2 => hdrNotFix_reg_n_0,
      I3 => \^statelive_reg[2]_0\(0),
      I4 => \^statelive_reg[2]_0\(1),
      O => \ixTExp_lcl[2]_i_1_n_0\
    );
\ixTExp_lcl[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"68"
    )
        port map (
      I0 => \ixTExp_lcl_reg_n_0_[2]\,
      I1 => \ixTExp_lcl_reg_n_0_[1]\,
      I2 => \ixTExp_lcl_reg_n_0_[0]\,
      O => \ixTExp_lcl[2]_i_2_n_0\
    );
\ixTExp_lcl[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(2),
      I1 => video_out_tlast,
      I2 => video_out_tvalid,
      O => \ixTExp_lcl[2]_i_3_n_0\
    );
\ixTExp_lcl_reg[0]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ixTExp_lcl[2]_i_1_n_0\,
      D => \ixTExp_lcl[0]_i_1_n_0\,
      PRE => sda_sig_reg,
      Q => \ixTExp_lcl_reg_n_0_[0]\
    );
\ixTExp_lcl_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ixTExp_lcl[2]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \ixTExp_lcl[1]_i_1_n_0\,
      Q => \ixTExp_lcl_reg_n_0_[1]\
    );
\ixTExp_lcl_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ixTExp_lcl[2]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \ixTExp_lcl[2]_i_2_n_0\,
      Q => \ixTExp_lcl_reg_n_0_[2]\
    );
\ixTExp_sig[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A2"
    )
        port map (
      I0 => \stateSynth[2]_i_7_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[2]\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[0]\,
      O => \ixTExp_sig[0]_i_1_n_0\
    );
\ixTExp_sig[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FE00FE000000"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[0]\,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => rng,
      I4 => \ixTExp_sig_reg_n_0_[0]\,
      I5 => \ixTExp_sig_reg_n_0_[1]\,
      O => \ixTExp_sig[1]_i_1_n_0\
    );
\ixTExp_sig[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080000FFFFFFFFF"
    )
        port map (
      I0 => \ixTExp_sig[2]_i_3_n_0\,
      I1 => hdrNotFix_reg_n_0,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \^statesynth_reg[2]_0\(0),
      I5 => rng,
      O => \ixTExp_sig[2]_i_1_n_0\
    );
\ixTExp_sig[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2880"
    )
        port map (
      I0 => \stateSynth[2]_i_7_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      O => \ixTExp_sig[2]_i_2_n_0\
    );
\ixTExp_sig[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => j_reg(15),
      I1 => \ixTExp_sig[2]_i_4_n_0\,
      I2 => \ixTExp_sig[2]_i_5_n_0\,
      I3 => \ixTExp_sig[2]_i_6_n_0\,
      I4 => \ixTExp_sig[2]_i_7_n_0\,
      I5 => \ixTExp_sig[2]_i_8_n_0\,
      O => \ixTExp_sig[2]_i_3_n_0\
    );
\ixTExp_sig[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_0_in(6),
      I1 => j_reg(6),
      I2 => j_reg(8),
      I3 => p_0_in(8),
      I4 => j_reg(7),
      I5 => p_0_in(7),
      O => \ixTExp_sig[2]_i_4_n_0\
    );
\ixTExp_sig[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_0_in(11),
      I1 => j_reg(11),
      I2 => j_reg(10),
      I3 => p_0_in(10),
      I4 => j_reg(9),
      I5 => p_0_in(9),
      O => \ixTExp_sig[2]_i_5_n_0\
    );
\ixTExp_sig[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => j_reg(1),
      I1 => p_0_in(1),
      I2 => j_reg(2),
      I3 => p_0_in(2),
      I4 => p_0_in(0),
      I5 => j_reg(0),
      O => \ixTExp_sig[2]_i_6_n_0\
    );
\ixTExp_sig[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_0_in(3),
      I1 => j_reg(3),
      I2 => j_reg(4),
      I3 => p_0_in(4),
      I4 => j_reg(5),
      I5 => p_0_in(5),
      O => \ixTExp_sig[2]_i_7_n_0\
    );
\ixTExp_sig[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => p_0_in(12),
      I1 => j_reg(12),
      I2 => j_reg(13),
      I3 => p_0_in(13),
      I4 => j_reg(14),
      I5 => p_0_in(14),
      O => \ixTExp_sig[2]_i_8_n_0\
    );
\ixTExp_sig_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ixTExp_sig[2]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \ixTExp_sig[0]_i_1_n_0\,
      Q => \ixTExp_sig_reg_n_0_[0]\
    );
\ixTExp_sig_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ixTExp_sig[2]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \ixTExp_sig[1]_i_1_n_0\,
      Q => \ixTExp_sig_reg_n_0_[1]\
    );
\ixTExp_sig_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \ixTExp_sig[2]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \ixTExp_sig[2]_i_2_n_0\,
      Q => \ixTExp_sig_reg_n_0_[2]\
    );
\j[0]__0_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => j_reg(0),
      O => \p_0_in__0__0\(0)
    );
\j[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000080FFFCFFBF"
    )
        port map (
      I0 => specNotGnr,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => \stateConfig_reg_n_0_[2]\,
      I3 => \stateConfig_reg_n_0_[3]\,
      I4 => \stateConfig_reg_n_0_[0]\,
      I5 => \j_reg_n_0_[0]\,
      O => \j[0]_i_1_n_0\
    );
\j[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000044444444"
    )
        port map (
      I0 => sda_sig_reg,
      I1 => \stateSynth[2]_i_7_n_0\,
      I2 => \row_reg[0]_1\,
      I3 => \i[7]_i_4_n_0\,
      I4 => \row[11]_i_6_n_0\,
      I5 => \j[15]_i_4_n_0\,
      O => \j[15]_i_1_n_0\
    );
\j[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000006000"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[0]\,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => rng,
      I4 => sda_sig_reg,
      I5 => \row[11]_i_5_n_0\,
      O => \j[15]_i_2_n_0\
    );
\j[15]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7FF"
    )
        port map (
      I0 => \ixTExp_sig[2]_i_3_n_0\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      O => \j[15]_i_4_n_0\
    );
\j[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6666666066066666"
    )
        port map (
      I0 => \j_reg_n_0_[0]\,
      I1 => \j_reg_n_0_[1]\,
      I2 => \stateConfig_reg_n_0_[2]\,
      I3 => \stateConfig_reg_n_0_[3]\,
      I4 => \stateConfig_reg_n_0_[1]\,
      I5 => \stateConfig_reg_n_0_[0]\,
      O => \j[1]_i_1_n_0\
    );
\j[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \j[7]_i_9_n_0\,
      I1 => \j_reg_n_0_[1]\,
      I2 => \j_reg_n_0_[0]\,
      I3 => \j_reg_n_0_[2]\,
      O => \j[2]_i_1_n_0\
    );
\j[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \j[7]_i_9_n_0\,
      I1 => \j_reg_n_0_[0]\,
      I2 => \j_reg_n_0_[1]\,
      I3 => \j_reg_n_0_[2]\,
      I4 => \j_reg_n_0_[3]\,
      O => \j[3]_i_1_n_0\
    );
\j[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \j[7]_i_9_n_0\,
      I1 => \j_reg_n_0_[2]\,
      I2 => \j_reg_n_0_[1]\,
      I3 => \j_reg_n_0_[0]\,
      I4 => \j_reg_n_0_[3]\,
      I5 => \j_reg_n_0_[4]\,
      O => \j[4]_i_1_n_0\
    );
\j[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \j[7]_i_9_n_0\,
      I1 => \j_reg_n_0_[3]\,
      I2 => \j[5]_i_2_n_0\,
      I3 => \j_reg_n_0_[2]\,
      I4 => \j_reg_n_0_[4]\,
      I5 => \j_reg_n_0_[5]\,
      O => \j[5]_i_1_n_0\
    );
\j[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \j_reg_n_0_[1]\,
      I1 => \j_reg_n_0_[0]\,
      O => \j[5]_i_2_n_0\
    );
\j[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FEBFFEBF0000"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[3]\,
      I1 => \stateConfig_reg_n_0_[2]\,
      I2 => \stateConfig_reg_n_0_[1]\,
      I3 => \stateConfig_reg_n_0_[0]\,
      I4 => \j[7]_i_10_n_0\,
      I5 => \j_reg_n_0_[6]\,
      O => \j[6]_i_1_n_0\
    );
\j[7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \j_reg_n_0_[4]\,
      I1 => \j_reg_n_0_[2]\,
      I2 => \j_reg_n_0_[1]\,
      I3 => \j_reg_n_0_[0]\,
      I4 => \j_reg_n_0_[3]\,
      I5 => \j_reg_n_0_[5]\,
      O => \j[7]_i_10_n_0\
    );
\j[7]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02000000"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[0]\,
      I1 => i_reg(0),
      I2 => i_reg(2),
      I3 => i_reg(1),
      I4 => i_reg(3),
      O => \j[7]_i_11_n_0\
    );
\j[7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \j[7]_i_9_n_0\,
      I1 => \j_reg_n_0_[6]\,
      I2 => \j[7]_i_10_n_0\,
      I3 => \j_reg_n_0_[7]\,
      O => \j[7]_i_3_n_0\
    );
\j[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800300008"
    )
        port map (
      I0 => \j[7]_i_11_n_0\,
      I1 => tkclk,
      I2 => \stateConfig_reg_n_0_[3]\,
      I3 => \stateConfig_reg_n_0_[2]\,
      I4 => \stateConfig_reg_n_0_[1]\,
      I5 => \stateConfig_reg_n_0_[0]\,
      O => \j[7]_i_4_n_0\
    );
\j[7]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[1]\,
      I1 => \stateConfig_reg_n_0_[0]\,
      I2 => tkclk,
      O => \j[7]_i_5_n_0\
    );
\j[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[1]\,
      I1 => \stateConfig_reg_n_0_[0]\,
      O => \j[7]_i_7_n_0\
    );
\j[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[2]\,
      I1 => \stateConfig_reg_n_0_[3]\,
      O => \j[7]_i_8_n_0\
    );
\j[7]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFBD"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[0]\,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => \stateConfig_reg_n_0_[2]\,
      I3 => \stateConfig_reg_n_0_[3]\,
      O => \j[7]_i_9_n_0\
    );
\j_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_42,
      D => \j[0]_i_1_n_0\,
      Q => \j_reg_n_0_[0]\,
      R => '0'
    );
\j_reg[0]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(0),
      Q => j_reg(0),
      R => \j[15]_i_1_n_0\
    );
\j_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(10),
      Q => j_reg(10),
      R => \j[15]_i_1_n_0\
    );
\j_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(11),
      Q => j_reg(11),
      R => \j[15]_i_1_n_0\
    );
\j_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(12),
      Q => j_reg(12),
      R => \j[15]_i_1_n_0\
    );
\j_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(13),
      Q => j_reg(13),
      R => \j[15]_i_1_n_0\
    );
\j_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(14),
      Q => j_reg(14),
      R => \j[15]_i_1_n_0\
    );
\j_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(15),
      Q => j_reg(15),
      R => \j[15]_i_1_n_0\
    );
\j_reg[15]_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => \j_reg[8]_i_1_n_0\,
      CI_TOP => '0',
      CO(7 downto 6) => \NLW_j_reg[15]_i_3_CO_UNCONNECTED\(7 downto 6),
      CO(5) => \j_reg[15]_i_3_n_2\,
      CO(4) => \j_reg[15]_i_3_n_3\,
      CO(3) => \j_reg[15]_i_3_n_4\,
      CO(2) => \j_reg[15]_i_3_n_5\,
      CO(1) => \j_reg[15]_i_3_n_6\,
      CO(0) => \j_reg[15]_i_3_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7) => \NLW_j_reg[15]_i_3_O_UNCONNECTED\(7),
      O(6 downto 0) => \p_0_in__0__0\(15 downto 9),
      S(7) => '0',
      S(6 downto 0) => j_reg(15 downto 9)
    );
\j_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_42,
      D => \j[1]_i_1_n_0\,
      Q => \j_reg_n_0_[1]\,
      S => myParrom_n_43
    );
\j_reg[1]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(1),
      Q => j_reg(1),
      R => \j[15]_i_1_n_0\
    );
\j_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_42,
      D => \j[2]_i_1_n_0\,
      Q => \j_reg_n_0_[2]\,
      S => myParrom_n_43
    );
\j_reg[2]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(2),
      Q => j_reg(2),
      R => \j[15]_i_1_n_0\
    );
\j_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_42,
      D => \j[3]_i_1_n_0\,
      Q => \j_reg_n_0_[3]\,
      S => myParrom_n_43
    );
\j_reg[3]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(3),
      Q => j_reg(3),
      R => \j[15]_i_1_n_0\
    );
\j_reg[4]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_42,
      D => \j[4]_i_1_n_0\,
      Q => \j_reg_n_0_[4]\,
      S => myParrom_n_43
    );
\j_reg[4]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(4),
      Q => j_reg(4),
      R => \j[15]_i_1_n_0\
    );
\j_reg[5]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_42,
      D => \j[5]_i_1_n_0\,
      Q => \j_reg_n_0_[5]\,
      S => myParrom_n_43
    );
\j_reg[5]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(5),
      Q => j_reg(5),
      R => \j[15]_i_1_n_0\
    );
\j_reg[6]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_42,
      D => \j[6]_i_1_n_0\,
      Q => \j_reg_n_0_[6]\,
      S => myParrom_n_43
    );
\j_reg[6]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(6),
      Q => j_reg(6),
      R => \j[15]_i_1_n_0\
    );
\j_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myParrom_n_42,
      D => \j[7]_i_3_n_0\,
      Q => \j_reg_n_0_[7]\,
      S => myParrom_n_43
    );
\j_reg[7]__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(7),
      Q => j_reg(7),
      R => \j[15]_i_1_n_0\
    );
\j_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(8),
      Q => j_reg(8),
      R => \j[15]_i_1_n_0\
    );
\j_reg[8]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => j_reg(0),
      CI_TOP => '0',
      CO(7) => \j_reg[8]_i_1_n_0\,
      CO(6) => \j_reg[8]_i_1_n_1\,
      CO(5) => \j_reg[8]_i_1_n_2\,
      CO(4) => \j_reg[8]_i_1_n_3\,
      CO(3) => \j_reg[8]_i_1_n_4\,
      CO(2) => \j_reg[8]_i_1_n_5\,
      CO(1) => \j_reg[8]_i_1_n_6\,
      CO(0) => \j_reg[8]_i_1_n_7\,
      DI(7 downto 0) => B"00000000",
      O(7 downto 0) => \p_0_in__0__0\(8 downto 1),
      S(7 downto 0) => j_reg(8 downto 1)
    );
\j_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \j[15]_i_2_n_0\,
      D => \p_0_in__0__0\(9),
      Q => j_reg(9),
      R => \j[15]_i_1_n_0\
    );
\k[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => k(0),
      O => stateConfig1(0)
    );
\k[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[0]\,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => \stateConfig_reg_n_0_[2]\,
      I3 => \stateConfig_reg_n_0_[3]\,
      I4 => sda_sig_reg,
      O => k0
    );
\k[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => k(0),
      I1 => k(1),
      O => stateConfig1(1)
    );
\k[1]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[0]\,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => \stateConfig_reg_n_0_[3]\,
      I3 => \stateConfig_reg_n_0_[2]\,
      O => ackLiveToConfigSetReg
    );
\k[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000020000000"
    )
        port map (
      I0 => tkclk,
      I1 => \k[1]_i_8_n_0\,
      I2 => \j_reg_n_0_[3]\,
      I3 => \j_reg_n_0_[7]\,
      I4 => \j_reg_n_0_[6]\,
      I5 => \j_reg_n_0_[5]\,
      O => \k[1]_i_6_n_0\
    );
\k[1]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \j_reg_n_0_[0]\,
      I1 => \j_reg_n_0_[1]\,
      I2 => \j_reg_n_0_[2]\,
      I3 => \j_reg_n_0_[4]\,
      O => \k[1]_i_8_n_0\
    );
\k_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => k0,
      D => stateConfig1(0),
      Q => k(0),
      R => myParrom_n_40
    );
\k_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => k0,
      D => stateConfig1(1),
      Q => k(1),
      R => myParrom_n_40
    );
\klm[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"03E3"
    )
        port map (
      I0 => \^camiftovideoinaxis_tvalid\,
      I1 => \klm_reg[0]_7\(1),
      I2 => \klm_reg[0]_7\(0),
      I3 => \^synthnotlive_reg_0\,
      O => \stateIgr_reg[1]_0\(0)
    );
\klm[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"888888888888B888"
    )
        port map (
      I0 => toVideoinAXIS_tvalid_sig,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tvalid,
      I3 => \klm[2]_i_4_n_0\,
      I4 => \^statelive_reg[2]_0\(2),
      I5 => \klm[2]_i_5_n_0\,
      O => \^camiftovideoinaxis_tvalid\
    );
\klm[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000200000"
    )
        port map (
      I0 => video_out_tuser(69),
      I1 => video_out_tuser(68),
      I2 => video_out_tuser(67),
      I3 => video_out_tuser(65),
      I4 => video_out_tuser(66),
      I5 => video_out_tuser(64),
      O => \klm[2]_i_4_n_0\
    );
\klm[2]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(0),
      I1 => \^statelive_reg[2]_0\(1),
      O => \klm[2]_i_5_n_0\
    );
\liveIxTExp[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \ixTExp_lcl_reg_n_0_[2]\,
      I1 => \ixTExp_lcl_reg_n_0_[1]\,
      I2 => \ixTExp_lcl_reg_n_0_[0]\,
      O => \liveIxTExp[0]_i_1_n_0\
    );
\liveIxTExp[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C2"
    )
        port map (
      I0 => \ixTExp_lcl_reg_n_0_[2]\,
      I1 => \ixTExp_lcl_reg_n_0_[1]\,
      I2 => \ixTExp_lcl_reg_n_0_[0]\,
      O => \liveIxTExp[1]_i_1_n_0\
    );
\liveIxTExp[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080000"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(2),
      I1 => \i_reg[0]__1_n_0\,
      I2 => \^statelive_reg[2]_0\(0),
      I3 => \^statelive_reg[2]_0\(1),
      I4 => ackLiveToConfigSetReg_reg_n_0,
      O => \liveIxTExp[2]_i_1_n_0\
    );
\liveIxTExp[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \ixTExp_lcl_reg_n_0_[2]\,
      I1 => \ixTExp_lcl_reg_n_0_[0]\,
      I2 => \ixTExp_lcl_reg_n_0_[1]\,
      O => \liveIxTExp[2]_i_2_n_0\
    );
\liveIxTExp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \liveIxTExp[2]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \liveIxTExp[0]_i_1_n_0\,
      Q => liveIxTExp(0)
    );
\liveIxTExp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \liveIxTExp[2]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \liveIxTExp[1]_i_1_n_0\,
      Q => liveIxTExp(1)
    );
\liveIxTExp_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \liveIxTExp[2]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \liveIxTExp[2]_i_2_n_0\,
      Q => liveIxTExp(2)
    );
liveNotExt_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000EAAAAAAAA"
    )
        port map (
      I0 => liveNotExt,
      I1 => modNotGetSet_i_2_n_0,
      I2 => reqInvModReg,
      I3 => reqInvGetReg,
      I4 => reqInvSetReg,
      I5 => modNotGetSet_i_3_n_0,
      O => liveNotExt_i_1_n_0
    );
liveNotExt_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => liveNotExt_i_1_n_0,
      Q => liveNotExt,
      R => '0'
    );
\liveSetRegAddr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \i_reg[0]__1_n_0\,
      I1 => \^statelive_reg[2]_0\(0),
      I2 => \^statelive_reg[2]_0\(1),
      O => liveSetRegAddr(0)
    );
\liveSetRegAddr[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"41"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(2),
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \^statelive_reg[2]_0\(0),
      O => \liveSetRegAddr[13]_i_1_n_0\
    );
\liveSetRegAddr[13]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(0),
      I1 => \^statelive_reg[2]_0\(1),
      O => liveSetRegAddr(13)
    );
\liveSetRegAddr_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \liveSetRegAddr[13]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => liveSetRegAddr(0),
      Q => \liveSetRegAddr_reg[13]_0\(0)
    );
\liveSetRegAddr_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \liveSetRegAddr[13]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => liveSetRegAddr(13),
      Q => \liveSetRegAddr_reg[13]_0\(1)
    );
\liveSetRegVal[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55545445"
    )
        port map (
      I0 => \liveSetRegVal[7]_i_3_n_0\,
      I1 => \ixTExp_lcl_reg_n_0_[2]\,
      I2 => \ixTExp_lcl_reg_n_0_[1]\,
      I3 => \i_reg[0]__1_n_0\,
      I4 => \ixTExp_lcl_reg_n_0_[0]\,
      O => \liveSetRegVal[0]_i_1_n_0\
    );
\liveSetRegVal[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000F004A"
    )
        port map (
      I0 => \ixTExp_lcl_reg_n_0_[1]\,
      I1 => \ixTExp_lcl_reg_n_0_[0]\,
      I2 => \i_reg[0]__1_n_0\,
      I3 => \liveSetRegVal[7]_i_3_n_0\,
      I4 => \ixTExp_lcl_reg_n_0_[2]\,
      O => \liveSetRegVal[1]_i_1_n_0\
    );
\liveSetRegVal[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004440"
    )
        port map (
      I0 => \ixTExp_lcl_reg_n_0_[1]\,
      I1 => \ixTExp_lcl_reg_n_0_[0]\,
      I2 => \^statelive_reg[2]_0\(1),
      I3 => \^statelive_reg[2]_0\(0),
      I4 => \ixTExp_lcl_reg_n_0_[2]\,
      O => \liveSetRegVal[2]_i_1_n_0\
    );
\liveSetRegVal[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01011001"
    )
        port map (
      I0 => \liveSetRegVal[7]_i_3_n_0\,
      I1 => \ixTExp_lcl_reg_n_0_[2]\,
      I2 => \i_reg[0]__1_n_0\,
      I3 => \ixTExp_lcl_reg_n_0_[0]\,
      I4 => \ixTExp_lcl_reg_n_0_[1]\,
      O => \liveSetRegVal[3]_i_1_n_0\
    );
\liveSetRegVal[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEE000"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(0),
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \i_reg[0]__1_n_0\,
      I3 => \ixTExp_lcl_reg_n_0_[1]\,
      I4 => \ixTExp_lcl_reg_n_0_[2]\,
      O => \liveSetRegVal[4]_i_1_n_0\
    );
\liveSetRegVal[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000006"
    )
        port map (
      I0 => \ixTExp_lcl_reg_n_0_[1]\,
      I1 => \ixTExp_lcl_reg_n_0_[0]\,
      I2 => \i_reg[0]__1_n_0\,
      I3 => \liveSetRegVal[7]_i_3_n_0\,
      I4 => \ixTExp_lcl_reg_n_0_[2]\,
      O => \liveSetRegVal[6]_i_1_n_0\
    );
\liveSetRegVal[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002111122221111"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(1),
      I1 => \^statelive_reg[2]_0\(2),
      I2 => \ixTExp_lcl_reg_n_0_[1]\,
      I3 => \ixTExp_lcl_reg_n_0_[0]\,
      I4 => \^statelive_reg[2]_0\(0),
      I5 => \ixTExp_lcl_reg_n_0_[2]\,
      O => \liveSetRegVal[7]_i_1_n_0\
    );
\liveSetRegVal[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000F8"
    )
        port map (
      I0 => \ixTExp_lcl_reg_n_0_[1]\,
      I1 => \ixTExp_lcl_reg_n_0_[0]\,
      I2 => \ixTExp_lcl_reg_n_0_[2]\,
      I3 => \liveSetRegVal[7]_i_3_n_0\,
      I4 => \i_reg[0]__1_n_0\,
      O => \liveSetRegVal[7]_i_2_n_0\
    );
\liveSetRegVal[7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(1),
      I1 => \^statelive_reg[2]_0\(0),
      I2 => \^statelive_reg[2]_0\(2),
      O => \liveSetRegVal[7]_i_3_n_0\
    );
\liveSetRegVal_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \liveSetRegVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \liveSetRegVal[0]_i_1_n_0\,
      Q => \liveSetRegVal_reg_n_0_[0]\
    );
\liveSetRegVal_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \liveSetRegVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \liveSetRegVal[1]_i_1_n_0\,
      Q => \liveSetRegVal_reg_n_0_[1]\
    );
\liveSetRegVal_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \liveSetRegVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \liveSetRegVal[2]_i_1_n_0\,
      Q => \liveSetRegVal_reg_n_0_[2]\
    );
\liveSetRegVal_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \liveSetRegVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \liveSetRegVal[3]_i_1_n_0\,
      Q => \liveSetRegVal_reg_n_0_[3]\
    );
\liveSetRegVal_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \liveSetRegVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \liveSetRegVal[4]_i_1_n_0\,
      Q => \liveSetRegVal_reg_n_0_[4]\
    );
\liveSetRegVal_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \liveSetRegVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \liveSetRegVal[6]_i_1_n_0\,
      Q => \liveSetRegVal_reg_n_0_[6]\
    );
\liveSetRegVal_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \liveSetRegVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \liveSetRegVal[7]_i_2_n_0\,
      Q => \liveSetRegVal_reg_n_0_[7]\
    );
modNotGetSet_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000CEAAAAAAAA"
    )
        port map (
      I0 => modNotGetSet,
      I1 => reqInvModReg,
      I2 => modNotGetSet_i_2_n_0,
      I3 => reqInvGetReg,
      I4 => reqInvSetReg,
      I5 => modNotGetSet_i_3_n_0,
      O => modNotGetSet_i_1_n_0
    );
modNotGetSet_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(1),
      I1 => \^statelive_reg[2]_0\(0),
      I2 => \^statelive_reg[2]_0\(2),
      O => modNotGetSet_i_2_n_0
    );
modNotGetSet_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[1]\,
      I1 => \stateConfig_reg_n_0_[0]\,
      I2 => \stateConfig_reg_n_0_[2]\,
      I3 => \stateConfig_reg_n_0_[3]\,
      I4 => prepdone,
      I5 => sda_sig_reg,
      O => modNotGetSet_i_3_n_0
    );
modNotGetSet_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => modNotGetSet_i_1_n_0,
      Q => modNotGetSet,
      R => '0'
    );
myI2c: entity work.design_1_Vsp_core_0_0_I2cmaster_v1_0
     port map (
      D(7) => myI2c_n_1,
      D(6) => myI2c_n_2,
      D(5) => myI2c_n_3,
      D(4) => myI2c_n_4,
      D(3) => myI2c_n_5,
      D(2) => myI2c_n_6,
      D(1) => myI2c_n_7,
      D(0) => myI2c_n_8,
      E(0) => myI2c_n_0,
      Q(3) => \stateConfig_reg_n_0_[3]\,
      Q(2) => \stateConfig_reg_n_0_[2]\,
      Q(1) => \stateConfig_reg_n_0_[1]\,
      Q(0) => \stateConfig_reg_n_0_[0]\,
      aclk_sig => aclk_sig,
      i2cReadNotWrite => i2cReadNotWrite,
      \i2cSend_reg[0]\ => \i2cSend[7]_i_5_n_0\,
      \i2cSend_reg[0]_0\ => myParrom_n_9,
      \i2cSend_reg[1]\ => myParrom_n_10,
      \i2cSend_reg[2]\ => myParrom_n_11,
      \i2cSend_reg[3]\ => myParrom_n_12,
      \i2cSend_reg[4]\ => myParrom_n_13,
      \i2cSend_reg[5]\ => myParrom_n_14,
      \i2cSend_reg[6]\ => myParrom_n_15,
      \i2cSend_reg[7]\(15 downto 0) => D(15 downto 0),
      \i2cSend_reg[7]_0\ => myParrom_n_16,
      \recv_sig_reg[7]_0\(7) => myI2c_n_9,
      \recv_sig_reg[7]_0\(6) => myI2c_n_10,
      \recv_sig_reg[7]_0\(5) => myI2c_n_11,
      \recv_sig_reg[7]_0\(4) => myI2c_n_12,
      \recv_sig_reg[7]_0\(3) => myI2c_n_13,
      \recv_sig_reg[7]_0\(2) => myI2c_n_14,
      \recv_sig_reg[7]_0\(1) => myI2c_n_15,
      \recv_sig_reg[7]_0\(0) => myI2c_n_16,
      scl => scl,
      sda => sda,
      sda_sig_i_12_0(7) => \i2cSend_reg_n_0_[7]\,
      sda_sig_i_12_0(6) => \i2cSend_reg_n_0_[6]\,
      sda_sig_i_12_0(5) => \i2cSend_reg_n_0_[5]\,
      sda_sig_i_12_0(4) => \i2cSend_reg_n_0_[4]\,
      sda_sig_i_12_0(3) => \i2cSend_reg_n_0_[3]\,
      sda_sig_i_12_0(2) => \i2cSend_reg_n_0_[2]\,
      sda_sig_i_12_0(1) => \i2cSend_reg_n_0_[1]\,
      sda_sig_i_12_0(0) => \i2cSend_reg_n_0_[0]\,
      sda_sig_i_16_0(15) => \i2cRegaddr_reg_n_0_[15]\,
      sda_sig_i_16_0(14) => \i2cRegaddr_reg_n_0_[14]\,
      sda_sig_i_16_0(13) => \i2cRegaddr_reg_n_0_[13]\,
      sda_sig_i_16_0(12) => \i2cRegaddr_reg_n_0_[12]\,
      sda_sig_i_16_0(11) => \i2cRegaddr_reg_n_0_[11]\,
      sda_sig_i_16_0(10) => \i2cRegaddr_reg_n_0_[10]\,
      sda_sig_i_16_0(9) => \i2cRegaddr_reg_n_0_[9]\,
      sda_sig_i_16_0(8) => \i2cRegaddr_reg_n_0_[8]\,
      sda_sig_i_16_0(7) => \i2cRegaddr_reg_n_0_[7]\,
      sda_sig_i_16_0(6) => \i2cRegaddr_reg_n_0_[6]\,
      sda_sig_i_16_0(5) => \i2cRegaddr_reg_n_0_[5]\,
      sda_sig_i_16_0(4) => \i2cRegaddr_reg_n_0_[4]\,
      sda_sig_i_16_0(3) => \i2cRegaddr_reg_n_0_[3]\,
      sda_sig_i_16_0(2) => \i2cRegaddr_reg_n_0_[2]\,
      sda_sig_i_16_0(1) => \i2cRegaddr_reg_n_0_[1]\,
      sda_sig_i_16_0(0) => \i2cRegaddr_reg_n_0_[0]\,
      sda_sig_reg_0 => sda_sig_reg,
      \stateConfig_reg[0]\ => \stateConfig[3]_i_3_n_0\,
      \stateConfig_reg[0]_0\ => \j[7]_i_8_n_0\,
      \stateConfig_reg[0]_1\ => \stateConfig[3]_i_5_n_0\,
      \stateConfig_reg[0]_2\ => \j[7]_i_7_n_0\,
      \stateConfig_reg[0]_3\ => \stateConfig[3]_i_6_n_0\,
      \stateConfig_reg[0]_4\(1 downto 0) => k(1 downto 0),
      tkclk => tkclk
    );
myMipirx: entity work.design_1_Vsp_core_0_0_Mipirx_xlnx_comb_w4_r1188
     port map (
      clkoutphy_out => NLW_myMipirx_clkoutphy_out_UNCONNECTED,
      csirxss_csi_irq => NLW_myMipirx_csirxss_csi_irq_UNCONNECTED,
      csirxss_s_axi_araddr(12) => \corecfgAXIL_araddr_reg_n_0_[12]\,
      csirxss_s_axi_araddr(11 downto 8) => B"0000",
      csirxss_s_axi_araddr(7) => \corecfgAXIL_araddr_reg_n_0_[7]\,
      csirxss_s_axi_araddr(6) => \corecfgAXIL_araddr_reg_n_0_[6]\,
      csirxss_s_axi_araddr(5) => \corecfgAXIL_araddr_reg_n_0_[5]\,
      csirxss_s_axi_araddr(4) => \corecfgAXIL_araddr_reg_n_0_[4]\,
      csirxss_s_axi_araddr(3) => \corecfgAXIL_araddr_reg_n_0_[3]\,
      csirxss_s_axi_araddr(2) => \corecfgAXIL_araddr_reg_n_0_[2]\,
      csirxss_s_axi_araddr(1 downto 0) => B"00",
      csirxss_s_axi_arprot(2 downto 0) => B"000",
      csirxss_s_axi_arready(0) => corecfgAXIL_arready,
      csirxss_s_axi_arvalid(0) => csirxss_s_axi_arvalid,
      csirxss_s_axi_awaddr(12) => \corecfgAXIL_awaddr_reg_n_0_[12]\,
      csirxss_s_axi_awaddr(11 downto 8) => B"0000",
      csirxss_s_axi_awaddr(7) => \corecfgAXIL_awaddr_reg_n_0_[7]\,
      csirxss_s_axi_awaddr(6) => \corecfgAXIL_awaddr_reg_n_0_[6]\,
      csirxss_s_axi_awaddr(5) => \corecfgAXIL_awaddr_reg_n_0_[5]\,
      csirxss_s_axi_awaddr(4) => \corecfgAXIL_awaddr_reg_n_0_[4]\,
      csirxss_s_axi_awaddr(3) => \corecfgAXIL_awaddr_reg_n_0_[3]\,
      csirxss_s_axi_awaddr(2) => \corecfgAXIL_awaddr_reg_n_0_[2]\,
      csirxss_s_axi_awaddr(1 downto 0) => B"00",
      csirxss_s_axi_awprot(2 downto 0) => B"000",
      csirxss_s_axi_awready(0) => csirxss_s_axi_awready,
      csirxss_s_axi_awvalid(0) => csirxss_s_axi_awvalid,
      csirxss_s_axi_bready(0) => csirxss_s_axi_bready,
      csirxss_s_axi_bresp(1 downto 0) => NLW_myMipirx_csirxss_s_axi_bresp_UNCONNECTED(1 downto 0),
      csirxss_s_axi_bvalid(0) => corecfgAXIL_bvalid,
      csirxss_s_axi_rdata(31 downto 0) => corecfgAXIL_rdata(31 downto 0),
      csirxss_s_axi_rready(0) => csirxss_s_axi_rready,
      csirxss_s_axi_rresp(1 downto 0) => NLW_myMipirx_csirxss_s_axi_rresp_UNCONNECTED(1 downto 0),
      csirxss_s_axi_rvalid(0) => corecfgAXIL_rvalid,
      csirxss_s_axi_wdata(31) => \corecfgAXIL_wdata_reg_n_0_[31]\,
      csirxss_s_axi_wdata(30) => \corecfgAXIL_wdata_reg_n_0_[30]\,
      csirxss_s_axi_wdata(29) => \corecfgAXIL_wdata_reg_n_0_[29]\,
      csirxss_s_axi_wdata(28) => \corecfgAXIL_wdata_reg_n_0_[28]\,
      csirxss_s_axi_wdata(27) => \corecfgAXIL_wdata_reg_n_0_[27]\,
      csirxss_s_axi_wdata(26) => \corecfgAXIL_wdata_reg_n_0_[26]\,
      csirxss_s_axi_wdata(25) => \corecfgAXIL_wdata_reg_n_0_[25]\,
      csirxss_s_axi_wdata(24) => \corecfgAXIL_wdata_reg_n_0_[24]\,
      csirxss_s_axi_wdata(23) => \corecfgAXIL_wdata_reg_n_0_[23]\,
      csirxss_s_axi_wdata(22) => \corecfgAXIL_wdata_reg_n_0_[22]\,
      csirxss_s_axi_wdata(21) => \corecfgAXIL_wdata_reg_n_0_[21]\,
      csirxss_s_axi_wdata(20) => \corecfgAXIL_wdata_reg_n_0_[20]\,
      csirxss_s_axi_wdata(19) => \corecfgAXIL_wdata_reg_n_0_[19]\,
      csirxss_s_axi_wdata(18) => \corecfgAXIL_wdata_reg_n_0_[18]\,
      csirxss_s_axi_wdata(17) => \corecfgAXIL_wdata_reg_n_0_[17]\,
      csirxss_s_axi_wdata(16) => \corecfgAXIL_wdata_reg_n_0_[16]\,
      csirxss_s_axi_wdata(15) => \corecfgAXIL_wdata_reg_n_0_[15]\,
      csirxss_s_axi_wdata(14) => \corecfgAXIL_wdata_reg_n_0_[14]\,
      csirxss_s_axi_wdata(13) => \corecfgAXIL_wdata_reg_n_0_[13]\,
      csirxss_s_axi_wdata(12) => \corecfgAXIL_wdata_reg_n_0_[12]\,
      csirxss_s_axi_wdata(11) => \corecfgAXIL_wdata_reg_n_0_[11]\,
      csirxss_s_axi_wdata(10) => \corecfgAXIL_wdata_reg_n_0_[10]\,
      csirxss_s_axi_wdata(9) => \corecfgAXIL_wdata_reg_n_0_[9]\,
      csirxss_s_axi_wdata(8) => \corecfgAXIL_wdata_reg_n_0_[8]\,
      csirxss_s_axi_wdata(7) => \corecfgAXIL_wdata_reg_n_0_[7]\,
      csirxss_s_axi_wdata(6) => \corecfgAXIL_wdata_reg_n_0_[6]\,
      csirxss_s_axi_wdata(5) => \corecfgAXIL_wdata_reg_n_0_[5]\,
      csirxss_s_axi_wdata(4) => \corecfgAXIL_wdata_reg_n_0_[4]\,
      csirxss_s_axi_wdata(3) => \corecfgAXIL_wdata_reg_n_0_[3]\,
      csirxss_s_axi_wdata(2) => \corecfgAXIL_wdata_reg_n_0_[2]\,
      csirxss_s_axi_wdata(1) => \corecfgAXIL_wdata_reg_n_0_[1]\,
      csirxss_s_axi_wdata(0) => \corecfgAXIL_wdata_reg_n_0_[0]\,
      csirxss_s_axi_wready(0) => corecfgAXIL_wready,
      csirxss_s_axi_wstrb(3 downto 0) => B"1111",
      csirxss_s_axi_wvalid(0) => csirxss_s_axi_wvalid,
      dphy_clk_200M => aclk_sig,
      frame_rcvd_pulse_out => NLW_myMipirx_frame_rcvd_pulse_out_UNCONNECTED,
      lite_aclk => '0',
      lite_aresetn => '0',
      mipi_phy_if_clk_n => csi_clk_n,
      mipi_phy_if_clk_p => csi_clk_p,
      mipi_phy_if_data_n(3 downto 0) => mipi_phy_if_data_n(3 downto 0),
      mipi_phy_if_data_p(3 downto 0) => mipi_phy_if_data_p(3 downto 0),
      pll_lock_out => NLW_myMipirx_pll_lock_out_UNCONNECTED,
      rxbyteclkhs => NLW_myMipirx_rxbyteclkhs_UNCONNECTED,
      system_rst_out => NLW_myMipirx_system_rst_out_UNCONNECTED,
      video_aclk => '0',
      video_aresetn => video_aresetn,
      video_out_tdata(23 downto 0) => video_out_tdata(23 downto 0),
      video_out_tdest(9 downto 0) => NLW_myMipirx_video_out_tdest_UNCONNECTED(9 downto 0),
      video_out_tlast => video_out_tlast,
      video_out_tready => '1',
      video_out_tuser(95 downto 70) => NLW_myMipirx_video_out_tuser_UNCONNECTED(95 downto 70),
      video_out_tuser(69 downto 64) => video_out_tuser(69 downto 64),
      video_out_tuser(63 downto 1) => NLW_myMipirx_video_out_tuser_UNCONNECTED(63 downto 1),
      video_out_tuser(0) => myMipirx_n_177,
      video_out_tvalid => video_out_tvalid
    );
myMipirx_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sda_sig_reg,
      O => video_aresetn
    );
myMipirx_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \stateCorecfg_reg_n_0_[2]\,
      I1 => \stateCorecfg_reg_n_0_[0]\,
      I2 => \stateCorecfg_reg_n_0_[1]\,
      O => csirxss_s_axi_awvalid
    );
myMipirx_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateCorecfg_reg_n_0_[2]\,
      I1 => \stateCorecfg_reg_n_0_[1]\,
      O => csirxss_s_axi_wvalid
    );
myMipirx_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \stateCorecfg_reg_n_0_[0]\,
      I1 => \stateCorecfg_reg_n_0_[2]\,
      I2 => \stateCorecfg_reg_n_0_[1]\,
      O => csirxss_s_axi_bready
    );
myMipirx_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \stateCorecfg_reg_n_0_[0]\,
      I1 => \stateCorecfg_reg_n_0_[2]\,
      I2 => \stateCorecfg_reg_n_0_[1]\,
      O => csirxss_s_axi_arvalid
    );
myMipirx_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"12"
    )
        port map (
      I0 => \stateCorecfg_reg_n_0_[0]\,
      I1 => \stateCorecfg_reg_n_0_[2]\,
      I2 => \stateCorecfg_reg_n_0_[1]\,
      O => csirxss_s_axi_rready
    );
myParrom: entity work.design_1_Vsp_core_0_0_Parrom
     port map (
      D(7 downto 0) => D(15 downto 8),
      DO(6 downto 0) => DO(6 downto 0),
      E(0) => myParrom_n_8,
      Q(10) => \aParrom_reg_n_0_[10]\,
      Q(9) => \aParrom_reg_n_0_[9]\,
      Q(8) => \aParrom_reg_n_0_[8]\,
      Q(7) => \aParrom_reg_n_0_[7]\,
      Q(6) => \aParrom_reg_n_0_[6]\,
      Q(5) => \aParrom_reg_n_0_[5]\,
      Q(4) => \aParrom_reg_n_0_[4]\,
      Q(3) => \aParrom_reg_n_0_[3]\,
      Q(2) => \aParrom_reg_n_0_[2]\,
      Q(1) => \aParrom_reg_n_0_[1]\,
      Q(0) => \aParrom_reg_n_0_[0]\,
      SR(0) => myParrom_n_40,
      \aParrom_reg[10]\ => \aParrom[10]_i_3_n_0\,
      \aParrom_reg[10]_0\ => \aParrom[10]_i_4_n_0\,
      \aParrom_reg[10]_1\ => \aParrom[10]_i_6_n_0\,
      \aParrom_reg[5]\ => \aParrom[5]_i_2_n_0\,
      \aParrom_reg[6]\ => \aParrom[8]_i_3_n_0\,
      \aParrom_reg[9]\ => \aParrom[9]_i_2_n_0\,
      \aParrom_reg[9]_0\ => \aParrom[9]_i_3_n_0\,
      ackLiveToConfigSetReg => ackLiveToConfigSetReg,
      aclk_sig => aclk_sig,
      \bytecnt_reg[0]\ => \bytecnt[1]_i_2_n_0\,
      \bytecnt_reg[0]_0\ => \bytecnt[1]_i_4_n_0\,
      i2cReadNotWrite => i2cReadNotWrite,
      \i2cRegaddr_reg[0]\ => \i2cRegaddr_reg[0]_0\,
      \i2cRegaddr_reg[12]\ => \i2cRegaddr_reg[12]_0\,
      \i2cRegaddr_reg[13]\ => \i2cRegaddr_reg[13]_0\,
      \i2cRegaddr_reg[15]\ => \i2cRegaddr[15]_i_3_n_0\,
      \i2cRegaddr_reg[15]_0\ => \i2cRegaddr[15]_i_4_n_0\,
      \i2cRegaddr_reg[3]\ => \i2cRegaddr_reg[3]_0\,
      \i2cRegaddr_reg[4]\ => \i2cRegaddr_reg[4]_0\,
      \i2cRegaddr_reg[6]\ => \i2cRegaddr_reg[6]_0\,
      \i2cSend_reg[7]\(6) => \liveSetRegVal_reg_n_0_[7]\,
      \i2cSend_reg[7]\(5) => \liveSetRegVal_reg_n_0_[6]\,
      \i2cSend_reg[7]\(4) => \liveSetRegVal_reg_n_0_[4]\,
      \i2cSend_reg[7]\(3) => \liveSetRegVal_reg_n_0_[3]\,
      \i2cSend_reg[7]\(2) => \liveSetRegVal_reg_n_0_[2]\,
      \i2cSend_reg[7]\(1) => \liveSetRegVal_reg_n_0_[1]\,
      \i2cSend_reg[7]\(0) => \liveSetRegVal_reg_n_0_[0]\,
      \invbuf_reg[2][0]\ => myParrom_n_9,
      \invbuf_reg[2][1]\ => myParrom_n_10,
      \invbuf_reg[2][2]\ => myParrom_n_11,
      \invbuf_reg[2][3]\ => myParrom_n_12,
      \invbuf_reg[2][4]\ => myParrom_n_13,
      \invbuf_reg[2][5]\ => myParrom_n_14,
      \invbuf_reg[2][6]\ => myParrom_n_15,
      \invbuf_reg[2][7]\ => myParrom_n_16,
      \j_reg[1]\(3) => \stateConfig_reg_n_0_[3]\,
      \j_reg[1]\(2) => \stateConfig_reg_n_0_[2]\,
      \j_reg[1]\(1) => \stateConfig_reg_n_0_[1]\,
      \j_reg[1]\(0) => \stateConfig_reg_n_0_[0]\,
      \j_reg[7]\ => sda_sig_reg,
      \j_reg[7]_0\ => \j[7]_i_4_n_0\,
      \j_reg[7]_1\ => \j[7]_i_5_n_0\,
      \j_reg[7]_2\ => \j[7]_i_8_n_0\,
      \k[1]_i_4_0\(2) => \bytecnt_reg_n_0_[2]\,
      \k[1]_i_4_0\(1) => \bytecnt_reg_n_0_[1]\,
      \k[1]_i_4_0\(0) => \bytecnt_reg_n_0_[0]\,
      \k_reg[1]\ => \k[1]_i_6_n_0\,
      prepdone => prepdone,
      prepdone_reg(0) => myParrom_n_38,
      prepdone_reg_0 => \bytecnt[1]_i_3_n_0\,
      reqInvSetReg => reqInvSetReg,
      reset_reg => myParrom_n_42,
      specNotGnr => specNotGnr,
      specNotGnr_reg => myParrom_n_39,
      specNotGnr_reg_0 => myParrom_n_43,
      specNotGnr_reg_1 => \aParrom[10]_i_5_n_0\,
      specNotGnr_reg_2 => \bytecnt[2]_i_3_n_0\,
      \stateConfig_reg[0]\(3) => myParrom_n_23,
      \stateConfig_reg[0]\(2) => myParrom_n_24,
      \stateConfig_reg[0]\(1) => myParrom_n_25,
      \stateConfig_reg[0]\(0) => myParrom_n_26,
      \stateConfig_reg[0]_0\ => \stateConfig[0]_i_2_n_0\,
      \stateConfig_reg[1]\(10) => myParrom_n_27,
      \stateConfig_reg[1]\(9) => myParrom_n_28,
      \stateConfig_reg[1]\(8) => myParrom_n_29,
      \stateConfig_reg[1]\(7) => myParrom_n_30,
      \stateConfig_reg[1]\(6) => myParrom_n_31,
      \stateConfig_reg[1]\(5) => myParrom_n_32,
      \stateConfig_reg[1]\(4) => myParrom_n_33,
      \stateConfig_reg[1]\(3) => myParrom_n_34,
      \stateConfig_reg[1]\(2) => myParrom_n_35,
      \stateConfig_reg[1]\(1) => myParrom_n_36,
      \stateConfig_reg[1]\(0) => myParrom_n_37,
      \stateConfig_reg[1]_0\ => \stateConfig[1]_i_3_n_0\,
      \stateConfig_reg[1]_1\ => \j[7]_i_11_n_0\,
      \stateConfig_reg[1]_2\ => \stateConfig[1]_i_4_n_0\,
      \stateConfig_reg[2]\ => \stateConfig[3]_i_7_n_0\,
      \stateConfig_reg[2]_0\ => \stateConfig[2]_i_2_n_0\,
      \stateConfig_reg[2]_1\ => \j[7]_i_7_n_0\,
      \stateConfig_reg[3]\ => myParrom_n_7,
      \stateConfig_reg[3]_0\(5) => myParrom_n_17,
      \stateConfig_reg[3]_0\(4) => myParrom_n_18,
      \stateConfig_reg[3]_0\(3) => myParrom_n_19,
      \stateConfig_reg[3]_0\(2) => myParrom_n_20,
      \stateConfig_reg[3]_0\(1) => myParrom_n_21,
      \stateConfig_reg[3]_0\(0) => myParrom_n_22,
      \stateConfig_reg[3]_1\(0) => myParrom_n_41
    );
prepdone_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg,
      D => myParrom_n_39,
      Q => prepdone
    );
\probe[0]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1F1F1F101F101F1F"
    )
        port map (
      I0 => \probe[0]_INST_0_i_1_n_0\,
      I1 => \probe[0]_INST_0_i_2_n_0\,
      I2 => synthNotLive_reg_n_0,
      I3 => \^statelive_reg[2]_0\(2),
      I4 => \^statelive_reg[2]_0\(1),
      I5 => \^statelive_reg[2]_0\(0),
      O => \^synthnotlive_reg_0\
    );
\probe[0]_INST_0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^statesynth_reg[2]_0\(0),
      I1 => \stateSynth_reg_n_0_[1]\,
      O => \probe[0]_INST_0_i_1_n_0\
    );
\probe[0]_INST_0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \^statesynth_reg[2]_0\(0),
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      O => \probe[0]_INST_0_i_2_n_0\
    );
\r_lcl[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \r_lcl[5]_i_2_n_0\,
      I1 => \r_lcl_reg_n_0_[0]\,
      O => \r_lcl[0]_i_1_n_0\
    );
\r_lcl[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800280000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \r_lcl_reg_n_0_[10]\,
      I5 => \r_lcl[10]_i_2_n_0\,
      O => \r_lcl[10]_i_1_n_0\
    );
\r_lcl[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[9]\,
      I1 => \r_lcl_reg_n_0_[8]\,
      I2 => \r_lcl_reg_n_0_[7]\,
      I3 => \r_lcl_reg_n_0_[6]\,
      I4 => \r_lcl[6]_i_2_n_0\,
      O => \r_lcl[10]_i_2_n_0\
    );
\r_lcl[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0028000000000028"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \r_lcl_reg_n_0_[11]\,
      I5 => \r_lcl[11]_i_2_n_0\,
      O => \r_lcl[11]_i_1_n_0\
    );
\r_lcl[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[10]\,
      I1 => \r_lcl[6]_i_2_n_0\,
      I2 => \r_lcl_reg_n_0_[6]\,
      I3 => \r_lcl_reg_n_0_[7]\,
      I4 => \r_lcl_reg_n_0_[8]\,
      I5 => \r_lcl_reg_n_0_[9]\,
      O => \r_lcl[11]_i_2_n_0\
    );
\r_lcl[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \r_lcl[5]_i_2_n_0\,
      I1 => \r_lcl_reg_n_0_[1]\,
      I2 => \r_lcl_reg_n_0_[0]\,
      O => \r_lcl[1]_i_1_n_0\
    );
\r_lcl[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \r_lcl[5]_i_2_n_0\,
      I1 => \r_lcl_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[1]\,
      I3 => \r_lcl_reg_n_0_[2]\,
      O => \r_lcl[2]_i_1_n_0\
    );
\r_lcl[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \r_lcl[5]_i_2_n_0\,
      I1 => \r_lcl_reg_n_0_[1]\,
      I2 => \r_lcl_reg_n_0_[0]\,
      I3 => \r_lcl_reg_n_0_[2]\,
      I4 => \r_lcl_reg_n_0_[3]\,
      O => \r_lcl[3]_i_1_n_0\
    );
\r_lcl[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \r_lcl[5]_i_2_n_0\,
      I1 => \r_lcl_reg_n_0_[3]\,
      I2 => \r_lcl_reg_n_0_[2]\,
      I3 => \r_lcl_reg_n_0_[0]\,
      I4 => \r_lcl_reg_n_0_[1]\,
      I5 => \r_lcl_reg_n_0_[4]\,
      O => \r_lcl[4]_i_1_n_0\
    );
\r_lcl[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \r_lcl[5]_i_2_n_0\,
      I1 => \r_lcl[5]_i_3_n_0\,
      I2 => \r_lcl_reg_n_0_[5]\,
      O => \r_lcl[5]_i_1_n_0\
    );
\r_lcl[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1400000014001400"
    )
        port map (
      I0 => \^statesynth_reg[2]_0\(0),
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => rng,
      I4 => \r_lcl[11]_i_2_n_0\,
      I5 => \r_lcl_reg_n_0_[11]\,
      O => \r_lcl[5]_i_2_n_0\
    );
\r_lcl[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[4]\,
      I1 => \r_lcl_reg_n_0_[1]\,
      I2 => \r_lcl_reg_n_0_[0]\,
      I3 => \r_lcl_reg_n_0_[2]\,
      I4 => \r_lcl_reg_n_0_[3]\,
      O => \r_lcl[5]_i_3_n_0\
    );
\r_lcl[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800280000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \r_lcl_reg_n_0_[6]\,
      I5 => \r_lcl[6]_i_2_n_0\,
      O => \r_lcl[6]_i_1_n_0\
    );
\r_lcl[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[3]\,
      I1 => \r_lcl_reg_n_0_[2]\,
      I2 => \r_lcl_reg_n_0_[0]\,
      I3 => \r_lcl_reg_n_0_[1]\,
      I4 => \r_lcl_reg_n_0_[4]\,
      I5 => \r_lcl_reg_n_0_[5]\,
      O => \r_lcl[6]_i_2_n_0\
    );
\r_lcl[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002800280000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \r_lcl_reg_n_0_[7]\,
      I5 => \r_lcl[7]_i_2_n_0\,
      O => \r_lcl[7]_i_1_n_0\
    );
\r_lcl[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \r_lcl[6]_i_2_n_0\,
      I1 => \r_lcl_reg_n_0_[6]\,
      O => \r_lcl[7]_i_2_n_0\
    );
\r_lcl[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0028000000000028"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \r_lcl[8]_i_2_n_0\,
      I5 => \r_lcl_reg_n_0_[8]\,
      O => \r_lcl[8]_i_1_n_0\
    );
\r_lcl[8]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[7]\,
      I1 => \r_lcl_reg_n_0_[6]\,
      I2 => \r_lcl[6]_i_2_n_0\,
      O => \r_lcl[8]_i_2_n_0\
    );
\r_lcl[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0028000000000028"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \r_lcl[9]_i_2_n_0\,
      I5 => \r_lcl_reg_n_0_[9]\,
      O => \r_lcl[9]_i_1_n_0\
    );
\r_lcl[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \r_lcl[6]_i_2_n_0\,
      I1 => \r_lcl_reg_n_0_[6]\,
      I2 => \r_lcl_reg_n_0_[7]\,
      I3 => \r_lcl_reg_n_0_[8]\,
      O => \r_lcl[9]_i_2_n_0\
    );
\r_lcl_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \r_lcl[0]_i_1_n_0\,
      Q => \r_lcl_reg_n_0_[0]\
    );
\r_lcl_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \r_lcl[10]_i_1_n_0\,
      Q => \r_lcl_reg_n_0_[10]\
    );
\r_lcl_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \r_lcl[11]_i_1_n_0\,
      Q => \r_lcl_reg_n_0_[11]\
    );
\r_lcl_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \r_lcl[1]_i_1_n_0\,
      Q => \r_lcl_reg_n_0_[1]\
    );
\r_lcl_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \r_lcl[2]_i_1_n_0\,
      Q => \r_lcl_reg_n_0_[2]\
    );
\r_lcl_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \r_lcl[3]_i_1_n_0\,
      Q => \r_lcl_reg_n_0_[3]\
    );
\r_lcl_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \r_lcl[4]_i_1_n_0\,
      Q => \r_lcl_reg_n_0_[4]\
    );
\r_lcl_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \r_lcl[5]_i_1_n_0\,
      Q => \r_lcl_reg_n_0_[5]\
    );
\r_lcl_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \r_lcl[6]_i_1_n_0\,
      Q => \r_lcl_reg_n_0_[6]\
    );
\r_lcl_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \r_lcl[7]_i_1_n_0\,
      Q => \r_lcl_reg_n_0_[7]\
    );
\r_lcl_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \r_lcl[8]_i_1_n_0\,
      Q => \r_lcl_reg_n_0_[8]\
    );
\r_lcl_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \g0_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \r_lcl[9]_i_1_n_0\,
      Q => \r_lcl_reg_n_0_[9]\
    );
\regVal[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010001010101"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[2]\,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => \stateConfig_reg_n_0_[0]\,
      I3 => i2cReadNotWrite,
      I4 => modNotGetSet,
      I5 => \stateConfig_reg_n_0_[3]\,
      O => \regVal[7]_i_1_n_0\
    );
\regVal_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \regVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_16,
      Q => camifGetRegVal(0)
    );
\regVal_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \regVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_15,
      Q => camifGetRegVal(1)
    );
\regVal_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \regVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_14,
      Q => \regVal_reg[7]_0\(0)
    );
\regVal_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \regVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_13,
      Q => camifGetRegVal(3)
    );
\regVal_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \regVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_12,
      Q => camifGetRegVal(4)
    );
\regVal_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \regVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_11,
      Q => camifGetRegVal(5)
    );
\regVal_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \regVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_10,
      Q => camifGetRegVal(6)
    );
\regVal_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \regVal[7]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => myI2c_n_9,
      Q => \regVal_reg[7]_0\(1)
    );
\retbuf[0][0]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => camifGetRegVal(0),
      I1 => \retbuf[0][0]_i_7\,
      I2 => camifGetCoreregVal(24),
      O => \regVal_reg[0]_0\
    );
\retbuf[0][1]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => camifGetRegVal(1),
      I1 => \retbuf[0][0]_i_7\,
      I2 => camifGetCoreregVal(25),
      O => \regVal_reg[1]_0\
    );
\retbuf[0][3]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => camifGetRegVal(3),
      I1 => \retbuf[0][0]_i_7\,
      I2 => camifGetCoreregVal(27),
      O => \regVal_reg[3]_0\
    );
\retbuf[0][4]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => camifGetRegVal(4),
      I1 => \retbuf[0][0]_i_7\,
      I2 => camifGetCoreregVal(28),
      O => \regVal_reg[4]_0\
    );
\retbuf[0][5]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => camifGetRegVal(5),
      I1 => \retbuf[0][0]_i_7\,
      I2 => camifGetCoreregVal(29),
      O => \regVal_reg[5]_0\
    );
\retbuf[0][6]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => camifGetRegVal(6),
      I1 => \retbuf[0][0]_i_7\,
      I2 => camifGetCoreregVal(30),
      O => \regVal_reg[6]_0\
    );
\rowRaw_lcl[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => \rowRaw_lcl[11]_i_3_n_0\,
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \i_reg[0]__1_0\,
      I3 => \rowRaw_lcl_reg_n_0_[0]\,
      O => \rowRaw_lcl[0]_i_1_n_0\
    );
\rowRaw_lcl[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E2E200"
    )
        port map (
      I0 => \rowRaw_lcl[11]_i_3_n_0\,
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \i_reg[0]__1_0\,
      I3 => \rowRaw_lcl[10]_i_2_n_0\,
      I4 => \^rowraw_lcl_reg[11]_0\(7),
      O => \rowRaw_lcl[10]_i_1_n_0\
    );
\rowRaw_lcl[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^rowraw_lcl_reg[11]_0\(5),
      I1 => \^rowraw_lcl_reg[11]_0\(3),
      I2 => \rowRaw_lcl[6]_i_2_n_0\,
      I3 => \^rowraw_lcl_reg[11]_0\(4),
      I4 => \^rowraw_lcl_reg[11]_0\(6),
      O => \rowRaw_lcl[10]_i_2_n_0\
    );
\rowRaw_lcl[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"07010101"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(0),
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \^statelive_reg[2]_0\(2),
      I3 => video_out_tlast,
      I4 => video_out_tvalid,
      O => \rowRaw_lcl[11]_i_1_n_0\
    );
\rowRaw_lcl[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E20000E2"
    )
        port map (
      I0 => \rowRaw_lcl[11]_i_3_n_0\,
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \i_reg[0]__1_0\,
      I3 => \rowRaw_lcl[11]_i_4_n_0\,
      I4 => \^rowraw_lcl_reg[11]_0\(8),
      O => \rowRaw_lcl[11]_i_2_n_0\
    );
\rowRaw_lcl[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(0),
      I1 => \rowRaw_lcl[11]_i_5_n_0\,
      I2 => \^rowraw_lcl_reg[11]_0\(8),
      I3 => \^rowraw_lcl_reg[11]_0\(5),
      I4 => \^rowraw_lcl_reg[11]_0\(7),
      I5 => \^rowraw_lcl_reg[11]_0\(6),
      O => \rowRaw_lcl[11]_i_3_n_0\
    );
\rowRaw_lcl[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \^rowraw_lcl_reg[11]_0\(7),
      I1 => \^rowraw_lcl_reg[11]_0\(6),
      I2 => \^rowraw_lcl_reg[11]_0\(4),
      I3 => \rowRaw_lcl[6]_i_2_n_0\,
      I4 => \^rowraw_lcl_reg[11]_0\(3),
      I5 => \^rowraw_lcl_reg[11]_0\(5),
      O => \rowRaw_lcl[11]_i_4_n_0\
    );
\rowRaw_lcl[11]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFF7"
    )
        port map (
      I0 => \rowRaw_lcl_reg_n_0_[2]\,
      I1 => \^rowraw_lcl_reg[11]_0\(1),
      I2 => \^rowraw_lcl_reg[11]_0\(0),
      I3 => \^rowraw_lcl_reg[11]_0\(2),
      I4 => \rowRaw_lcl[11]_i_6_n_0\,
      O => \rowRaw_lcl[11]_i_5_n_0\
    );
\rowRaw_lcl[11]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \rowRaw_lcl_reg_n_0_[1]\,
      I1 => \rowRaw_lcl_reg_n_0_[0]\,
      I2 => \^rowraw_lcl_reg[11]_0\(4),
      I3 => \^rowraw_lcl_reg[11]_0\(3),
      O => \rowRaw_lcl[11]_i_6_n_0\
    );
\rowRaw_lcl[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E2E200"
    )
        port map (
      I0 => \rowRaw_lcl[11]_i_3_n_0\,
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \i_reg[0]__1_0\,
      I3 => \rowRaw_lcl_reg_n_0_[0]\,
      I4 => \rowRaw_lcl_reg_n_0_[1]\,
      O => \rowRaw_lcl[1]_i_1_n_0\
    );
\rowRaw_lcl[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E2E200"
    )
        port map (
      I0 => \rowRaw_lcl[11]_i_3_n_0\,
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \i_reg[0]__1_0\,
      I3 => \rowRaw_lcl[2]_i_2_n_0\,
      I4 => \rowRaw_lcl_reg_n_0_[2]\,
      O => \rowRaw_lcl[2]_i_1_n_0\
    );
\rowRaw_lcl[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \rowRaw_lcl_reg_n_0_[0]\,
      I1 => \rowRaw_lcl_reg_n_0_[1]\,
      O => \rowRaw_lcl[2]_i_2_n_0\
    );
\rowRaw_lcl[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E2E200"
    )
        port map (
      I0 => \rowRaw_lcl[11]_i_3_n_0\,
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \i_reg[0]__1_0\,
      I3 => \rowRaw_lcl[3]_i_2_n_0\,
      I4 => \^rowraw_lcl_reg[11]_0\(0),
      O => \rowRaw_lcl[3]_i_1_n_0\
    );
\rowRaw_lcl[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \rowRaw_lcl_reg_n_0_[1]\,
      I1 => \rowRaw_lcl_reg_n_0_[0]\,
      I2 => \rowRaw_lcl_reg_n_0_[2]\,
      O => \rowRaw_lcl[3]_i_2_n_0\
    );
\rowRaw_lcl[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E2E200"
    )
        port map (
      I0 => \rowRaw_lcl[11]_i_3_n_0\,
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \i_reg[0]__1_0\,
      I3 => \rowRaw_lcl[4]_i_2_n_0\,
      I4 => \^rowraw_lcl_reg[11]_0\(1),
      O => \rowRaw_lcl[4]_i_1_n_0\
    );
\rowRaw_lcl[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \rowRaw_lcl_reg_n_0_[2]\,
      I1 => \rowRaw_lcl_reg_n_0_[0]\,
      I2 => \rowRaw_lcl_reg_n_0_[1]\,
      I3 => \^rowraw_lcl_reg[11]_0\(0),
      O => \rowRaw_lcl[4]_i_2_n_0\
    );
\rowRaw_lcl[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E2E200"
    )
        port map (
      I0 => \rowRaw_lcl[11]_i_3_n_0\,
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \i_reg[0]__1_0\,
      I3 => \rowRaw_lcl[5]_i_2_n_0\,
      I4 => \^rowraw_lcl_reg[11]_0\(2),
      O => \rowRaw_lcl[5]_i_1_n_0\
    );
\rowRaw_lcl[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^rowraw_lcl_reg[11]_0\(0),
      I1 => \rowRaw_lcl_reg_n_0_[1]\,
      I2 => \rowRaw_lcl_reg_n_0_[0]\,
      I3 => \rowRaw_lcl_reg_n_0_[2]\,
      I4 => \^rowraw_lcl_reg[11]_0\(1),
      O => \rowRaw_lcl[5]_i_2_n_0\
    );
\rowRaw_lcl[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E2E200"
    )
        port map (
      I0 => \rowRaw_lcl[11]_i_3_n_0\,
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \i_reg[0]__1_0\,
      I3 => \rowRaw_lcl[6]_i_2_n_0\,
      I4 => \^rowraw_lcl_reg[11]_0\(3),
      O => \rowRaw_lcl[6]_i_1_n_0\
    );
\rowRaw_lcl[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^rowraw_lcl_reg[11]_0\(1),
      I1 => \rowRaw_lcl_reg_n_0_[2]\,
      I2 => \rowRaw_lcl_reg_n_0_[0]\,
      I3 => \rowRaw_lcl_reg_n_0_[1]\,
      I4 => \^rowraw_lcl_reg[11]_0\(0),
      I5 => \^rowraw_lcl_reg[11]_0\(2),
      O => \rowRaw_lcl[6]_i_2_n_0\
    );
\rowRaw_lcl[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E2E200"
    )
        port map (
      I0 => \rowRaw_lcl[11]_i_3_n_0\,
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \i_reg[0]__1_0\,
      I3 => \rowRaw_lcl[7]_i_2_n_0\,
      I4 => \^rowraw_lcl_reg[11]_0\(4),
      O => \rowRaw_lcl[7]_i_1_n_0\
    );
\rowRaw_lcl[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^rowraw_lcl_reg[11]_0\(2),
      I1 => \^rowraw_lcl_reg[11]_0\(0),
      I2 => \rowRaw_lcl[2]_i_2_n_0\,
      I3 => \rowRaw_lcl_reg_n_0_[2]\,
      I4 => \^rowraw_lcl_reg[11]_0\(1),
      I5 => \^rowraw_lcl_reg[11]_0\(3),
      O => \rowRaw_lcl[7]_i_2_n_0\
    );
\rowRaw_lcl[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E2E200"
    )
        port map (
      I0 => \rowRaw_lcl[11]_i_3_n_0\,
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \i_reg[0]__1_0\,
      I3 => \rowRaw_lcl[8]_i_2_n_0\,
      I4 => \^rowraw_lcl_reg[11]_0\(5),
      O => \rowRaw_lcl[8]_i_1_n_0\
    );
\rowRaw_lcl[8]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^rowraw_lcl_reg[11]_0\(3),
      I1 => \rowRaw_lcl[6]_i_2_n_0\,
      I2 => \^rowraw_lcl_reg[11]_0\(4),
      O => \rowRaw_lcl[8]_i_2_n_0\
    );
\rowRaw_lcl[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E2E200"
    )
        port map (
      I0 => \rowRaw_lcl[11]_i_3_n_0\,
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \i_reg[0]__1_0\,
      I3 => \rowRaw_lcl[9]_i_2_n_0\,
      I4 => \^rowraw_lcl_reg[11]_0\(6),
      O => \rowRaw_lcl[9]_i_1_n_0\
    );
\rowRaw_lcl[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^rowraw_lcl_reg[11]_0\(4),
      I1 => \rowRaw_lcl[6]_i_2_n_0\,
      I2 => \^rowraw_lcl_reg[11]_0\(3),
      I3 => \^rowraw_lcl_reg[11]_0\(5),
      O => \rowRaw_lcl[9]_i_2_n_0\
    );
\rowRaw_lcl_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowRaw_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowRaw_lcl[0]_i_1_n_0\,
      Q => \rowRaw_lcl_reg_n_0_[0]\
    );
\rowRaw_lcl_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowRaw_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowRaw_lcl[10]_i_1_n_0\,
      Q => \^rowraw_lcl_reg[11]_0\(7)
    );
\rowRaw_lcl_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowRaw_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowRaw_lcl[11]_i_2_n_0\,
      Q => \^rowraw_lcl_reg[11]_0\(8)
    );
\rowRaw_lcl_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowRaw_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowRaw_lcl[1]_i_1_n_0\,
      Q => \rowRaw_lcl_reg_n_0_[1]\
    );
\rowRaw_lcl_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowRaw_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowRaw_lcl[2]_i_1_n_0\,
      Q => \rowRaw_lcl_reg_n_0_[2]\
    );
\rowRaw_lcl_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowRaw_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowRaw_lcl[3]_i_1_n_0\,
      Q => \^rowraw_lcl_reg[11]_0\(0)
    );
\rowRaw_lcl_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowRaw_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowRaw_lcl[4]_i_1_n_0\,
      Q => \^rowraw_lcl_reg[11]_0\(1)
    );
\rowRaw_lcl_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowRaw_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowRaw_lcl[5]_i_1_n_0\,
      Q => \^rowraw_lcl_reg[11]_0\(2)
    );
\rowRaw_lcl_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowRaw_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowRaw_lcl[6]_i_1_n_0\,
      Q => \^rowraw_lcl_reg[11]_0\(3)
    );
\rowRaw_lcl_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowRaw_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowRaw_lcl[7]_i_1_n_0\,
      Q => \^rowraw_lcl_reg[11]_0\(4)
    );
\rowRaw_lcl_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowRaw_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowRaw_lcl[8]_i_1_n_0\,
      Q => \^rowraw_lcl_reg[11]_0\(5)
    );
\rowRaw_lcl_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowRaw_lcl[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowRaw_lcl[9]_i_1_n_0\,
      Q => \^rowraw_lcl_reg[11]_0\(6)
    );
\row[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \row_reg_n_0_[0]\,
      O => \row[0]_i_1_n_0\
    );
\row[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000200000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \^row_reg[11]_0\(7),
      I5 => \row[11]_i_7_n_0\,
      O => \row[10]_i_1_n_0\
    );
\row[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFF1F1F1F1F1F1F"
    )
        port map (
      I0 => \row[11]_i_3_n_0\,
      I1 => \row_reg[0]_1\,
      I2 => \stateSynth[2]_i_7_n_0\,
      I3 => \stateSynth_reg_n_0_[0]\,
      I4 => \^statesynth_reg[2]_0\(0),
      I5 => \row[11]_i_5_n_0\,
      O => \row[11]_i_1_n_0\
    );
\row[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08808080"
    )
        port map (
      I0 => \stateSynth[2]_i_7_n_0\,
      I1 => \row[11]_i_6_n_0\,
      I2 => \^row_reg[11]_0\(8),
      I3 => \row[11]_i_7_n_0\,
      I4 => \^row_reg[11]_0\(7),
      O => \row[11]_i_2_n_0\
    );
\row[11]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \i[7]_i_4_n_0\,
      O => \row[11]_i_3_n_0\
    );
\row[11]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \ixTExp_sig[2]_i_3_n_0\,
      O => \row[11]_i_5_n_0\
    );
\row[11]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[0]\,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \stateSynth_reg_n_0_[1]\,
      O => \row[11]_i_6_n_0\
    );
\row[11]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^row_reg[11]_0\(5),
      I1 => \^row_reg[11]_0\(3),
      I2 => \row[8]_i_2_n_0\,
      I3 => \^row_reg[11]_0\(4),
      I4 => \^row_reg[11]_0\(6),
      O => \row[11]_i_7_n_0\
    );
\row[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000200000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \row_reg_n_0_[1]\,
      I5 => \row_reg_n_0_[0]\,
      O => \row[1]_i_1_n_0\
    );
\row[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \row[2]_i_2_n_0\,
      I1 => \row_reg_n_0_[0]\,
      I2 => \row_reg_n_0_[1]\,
      I3 => \row_reg_n_0_[2]\,
      O => \row[2]_i_1_n_0\
    );
\row[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => rng,
      O => \row[2]_i_2_n_0\
    );
\row[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880808080808080"
    )
        port map (
      I0 => \stateSynth[2]_i_7_n_0\,
      I1 => \row[11]_i_6_n_0\,
      I2 => \^row_reg[11]_0\(0),
      I3 => \row_reg_n_0_[2]\,
      I4 => \row_reg_n_0_[0]\,
      I5 => \row_reg_n_0_[1]\,
      O => \row[3]_i_1_n_0\
    );
\row[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000200000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \^row_reg[11]_0\(1),
      I5 => \row[4]_i_2_n_0\,
      O => \row[4]_i_1_n_0\
    );
\row[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \row_reg_n_0_[2]\,
      I1 => \row_reg_n_0_[0]\,
      I2 => \row_reg_n_0_[1]\,
      I3 => \^row_reg[11]_0\(0),
      O => \row[4]_i_2_n_0\
    );
\row[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000200000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \^row_reg[11]_0\(2),
      I5 => \row[5]_i_2_n_0\,
      O => \row[5]_i_1_n_0\
    );
\row[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^row_reg[11]_0\(0),
      I1 => \row_reg_n_0_[1]\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \row_reg_n_0_[2]\,
      I4 => \^row_reg[11]_0\(1),
      O => \row[5]_i_2_n_0\
    );
\row[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000200000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \^row_reg[11]_0\(3),
      I5 => \row[8]_i_2_n_0\,
      O => \row[6]_i_1_n_0\
    );
\row[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08808080"
    )
        port map (
      I0 => \stateSynth[2]_i_7_n_0\,
      I1 => \row[11]_i_6_n_0\,
      I2 => \^row_reg[11]_0\(4),
      I3 => \^row_reg[11]_0\(3),
      I4 => \row[8]_i_2_n_0\,
      O => \row[7]_i_1_n_0\
    );
\row[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880808080808080"
    )
        port map (
      I0 => \stateSynth[2]_i_7_n_0\,
      I1 => \row[11]_i_6_n_0\,
      I2 => \^row_reg[11]_0\(5),
      I3 => \^row_reg[11]_0\(4),
      I4 => \row[8]_i_2_n_0\,
      I5 => \^row_reg[11]_0\(3),
      O => \row[8]_i_1_n_0\
    );
\row[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^row_reg[11]_0\(1),
      I1 => \row_reg_n_0_[2]\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \row_reg_n_0_[1]\,
      I4 => \^row_reg[11]_0\(0),
      I5 => \^row_reg[11]_0\(2),
      O => \row[8]_i_2_n_0\
    );
\row[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000200000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \^row_reg[11]_0\(6),
      I5 => \row[9]_i_2_n_0\,
      O => \row[9]_i_1_n_0\
    );
\row[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^row_reg[11]_0\(4),
      I1 => \row[8]_i_2_n_0\,
      I2 => \^row_reg[11]_0\(3),
      I3 => \^row_reg[11]_0\(5),
      O => \row[9]_i_2_n_0\
    );
\row_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \row[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \row[0]_i_1_n_0\,
      Q => \row_reg_n_0_[0]\
    );
\row_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \row[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \row[10]_i_1_n_0\,
      Q => \^row_reg[11]_0\(7)
    );
\row_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \row[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \row[11]_i_2_n_0\,
      Q => \^row_reg[11]_0\(8)
    );
\row_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \row[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \row[1]_i_1_n_0\,
      Q => \row_reg_n_0_[1]\
    );
\row_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \row[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \row[2]_i_1_n_0\,
      Q => \row_reg_n_0_[2]\
    );
\row_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \row[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \row[3]_i_1_n_0\,
      Q => \^row_reg[11]_0\(0)
    );
\row_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \row[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \row[4]_i_1_n_0\,
      Q => \^row_reg[11]_0\(1)
    );
\row_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \row[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \row[5]_i_1_n_0\,
      Q => \^row_reg[11]_0\(2)
    );
\row_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \row[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \row[6]_i_1_n_0\,
      Q => \^row_reg[11]_0\(3)
    );
\row_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \row[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \row[7]_i_1_n_0\,
      Q => \^row_reg[11]_0\(4)
    );
\row_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \row[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \row[8]_i_1_n_0\,
      Q => \^row_reg[11]_0\(5)
    );
\row_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \row[11]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \row[9]_i_1_n_0\,
      Q => \^row_reg[11]_0\(6)
    );
\rowchk[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \rowchk_reg_n_0_[0]\,
      O => \rowchk[0]_i_1_n_0\
    );
\rowchk[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00B0F000"
    )
        port map (
      I0 => \rowchk_reg_n_0_[2]\,
      I1 => \rowchk_reg_n_0_[3]\,
      I2 => \row[2]_i_2_n_0\,
      I3 => \rowchk_reg_n_0_[1]\,
      I4 => \rowchk_reg_n_0_[0]\,
      O => \rowchk[1]_i_1_n_0\
    );
\rowchk[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \row[2]_i_2_n_0\,
      I1 => \rowchk_reg_n_0_[0]\,
      I2 => \rowchk_reg_n_0_[1]\,
      I3 => \rowchk_reg_n_0_[2]\,
      O => \rowchk[2]_i_1_n_0\
    );
\rowchk[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF005D0055005500"
    )
        port map (
      I0 => \stateSynth[2]_i_3_n_0\,
      I1 => \stateSynth[2]_i_6_n_0\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \rowchk[3]_i_3_n_0\,
      I4 => \row[11]_i_5_n_0\,
      I5 => \rowchk[3]_i_4_n_0\,
      O => \rowchk[3]_i_1_n_0\
    );
\rowchk[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28AA8000"
    )
        port map (
      I0 => \row[2]_i_2_n_0\,
      I1 => \rowchk_reg_n_0_[2]\,
      I2 => \rowchk_reg_n_0_[1]\,
      I3 => \rowchk_reg_n_0_[0]\,
      I4 => \rowchk_reg_n_0_[3]\,
      O => \rowchk[3]_i_2_n_0\
    );
\rowchk[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \stateSynth[2]_i_11_n_0\,
      I1 => \tixVSynthmode_reg_n_0_[1]\,
      I2 => \tixVSynthmode_reg_n_0_[0]\,
      O => \rowchk[3]_i_3_n_0\
    );
\rowchk[3]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[0]\,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => rng,
      O => \rowchk[3]_i_4_n_0\
    );
\rowchk_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowchk[3]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowchk[0]_i_1_n_0\,
      Q => \rowchk_reg_n_0_[0]\
    );
\rowchk_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowchk[3]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowchk[1]_i_1_n_0\,
      Q => \rowchk_reg_n_0_[1]\
    );
\rowchk_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowchk[3]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowchk[2]_i_1_n_0\,
      Q => \rowchk_reg_n_0_[2]\
    );
\rowchk_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \rowchk[3]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \rowchk[3]_i_2_n_0\,
      Q => \rowchk_reg_n_0_[3]\
    );
\rsh[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \rsh_reg_n_0_[1]\,
      I5 => \rsh_reg_n_0_[0]\,
      O => \rsh[0]_i_1_n_0\
    );
\rsh[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000200000"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \rsh_reg_n_0_[0]\,
      I5 => \rsh_reg_n_0_[1]\,
      O => \rsh[1]_i_1_n_0\
    );
\rsh_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => bsh,
      CLR => sda_sig_reg,
      D => \rsh[0]_i_1_n_0\,
      Q => \rsh_reg_n_0_[0]\
    );
\rsh_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => bsh,
      CLR => sda_sig_reg,
      D => \rsh[1]_i_1_n_0\,
      Q => \rsh_reg_n_0_[1]\
    );
specNotGnr_reg: unisim.vcomponents.FDRE
     port map (
      C => aclk_sig,
      CE => '1',
      D => myParrom_n_7,
      Q => specNotGnr,
      R => '0'
    );
\stateConfig[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000013231322"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[3]\,
      I1 => \stateConfig_reg_n_0_[2]\,
      I2 => \stateConfig_reg_n_0_[0]\,
      I3 => \stateConfig_reg_n_0_[1]\,
      I4 => prepdone,
      I5 => \stateConfig[3]_i_9_n_0\,
      O => \stateConfig[0]_i_2_n_0\
    );
\stateConfig[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111101010100"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[1]\,
      I1 => \stateConfig_reg_n_0_[2]\,
      I2 => \stateConfig_reg_n_0_[0]\,
      I3 => i2cReadNotWrite,
      I4 => prepdone,
      I5 => \stateConfig[3]_i_9_n_0\,
      O => \stateConfig[1]_i_3_n_0\
    );
\stateConfig[1]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \bytecnt_reg_n_0_[0]\,
      I1 => \bytecnt_reg_n_0_[1]\,
      O => \stateConfig[1]_i_4_n_0\
    );
\stateConfig[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"020B0209020B0208"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[0]\,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => \stateConfig_reg_n_0_[3]\,
      I3 => \stateConfig_reg_n_0_[2]\,
      I4 => \j[7]_i_11_n_0\,
      I5 => prepdone,
      O => \stateConfig[2]_i_2_n_0\
    );
\stateConfig[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A008A20AA20AA20A"
    )
        port map (
      I0 => \aParrom[9]_i_3_n_0\,
      I1 => \stateConfig_reg_n_0_[1]\,
      I2 => \stateConfig_reg_n_0_[0]\,
      I3 => tkclk,
      I4 => i2cReadNotWrite_reg_0,
      I5 => prepdone,
      O => \stateConfig[3]_i_3_n_0\
    );
\stateConfig[3]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => \bytecnt_reg_n_0_[2]\,
      I1 => \bytecnt_reg_n_0_[1]\,
      I2 => \bytecnt_reg_n_0_[0]\,
      O => \stateConfig[3]_i_5_n_0\
    );
\stateConfig[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAFBBAAAAAAAA"
    )
        port map (
      I0 => ackInvGetReg_sig_i_3_n_0,
      I1 => \stateConfig_reg_n_0_[0]\,
      I2 => \stateConfig_reg_n_0_[1]\,
      I3 => tkclk,
      I4 => \stateConfig_reg_n_0_[2]\,
      I5 => \stateConfig_reg_n_0_[3]\,
      O => \stateConfig[3]_i_6_n_0\
    );
\stateConfig[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAFAEAE"
    )
        port map (
      I0 => \stateConfig[3]_i_9_n_0\,
      I1 => prepdone,
      I2 => \stateConfig_reg_n_0_[0]\,
      I3 => modNotGetSet,
      I4 => i2cReadNotWrite,
      I5 => \stateConfig_reg_n_0_[1]\,
      O => \stateConfig[3]_i_7_n_0\
    );
\stateConfig[3]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA8AAAAAAA"
    )
        port map (
      I0 => \stateConfig_reg_n_0_[0]\,
      I1 => \k[1]_i_8_n_0\,
      I2 => \j_reg_n_0_[3]\,
      I3 => \j_reg_n_0_[7]\,
      I4 => \j_reg_n_0_[6]\,
      I5 => \j_reg_n_0_[5]\,
      O => \stateConfig[3]_i_9_n_0\
    );
\stateConfig_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myI2c_n_0,
      CLR => sda_sig_reg,
      D => myParrom_n_26,
      Q => \stateConfig_reg_n_0_[0]\
    );
\stateConfig_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myI2c_n_0,
      CLR => sda_sig_reg,
      D => myParrom_n_25,
      Q => \stateConfig_reg_n_0_[1]\
    );
\stateConfig_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myI2c_n_0,
      CLR => sda_sig_reg,
      D => myParrom_n_24,
      Q => \stateConfig_reg_n_0_[2]\
    );
\stateConfig_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => myI2c_n_0,
      CLR => sda_sig_reg,
      D => myParrom_n_23,
      Q => \stateConfig_reg_n_0_[3]\
    );
\stateCorecfg[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3333FF743300FF74"
    )
        port map (
      I0 => corecfgAXIL_wready,
      I1 => \stateCorecfg_reg_n_0_[2]\,
      I2 => reqInvGetCorereg,
      I3 => \stateCorecfg_reg_n_0_[1]\,
      I4 => \stateCorecfg_reg_n_0_[0]\,
      I5 => corecfgAXIL_rvalid,
      O => \stateCorecfg[0]_i_1_n_0\
    );
\stateCorecfg[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5FEA"
    )
        port map (
      I0 => \stateCorecfg_reg_n_0_[0]\,
      I1 => corecfgAXIL_wready,
      I2 => \stateCorecfg_reg_n_0_[2]\,
      I3 => \stateCorecfg_reg_n_0_[1]\,
      O => \stateCorecfg[1]_i_1_n_0\
    );
\stateCorecfg[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBB88B8BBB8BB"
    )
        port map (
      I0 => \stateCorecfg[2]_i_3_n_0\,
      I1 => \stateCorecfg_reg_n_0_[2]\,
      I2 => corecfgAXIL_rvalid,
      I3 => \stateCorecfg_reg_n_0_[1]\,
      I4 => corecfgAXIL_arready,
      I5 => \stateCorecfg_reg_n_0_[0]\,
      O => p_0_out
    );
\stateCorecfg[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0FF0FF04"
    )
        port map (
      I0 => reqInvGetCorereg,
      I1 => reqInvSetCorereg,
      I2 => \stateCorecfg_reg_n_0_[1]\,
      I3 => \stateCorecfg_reg_n_0_[2]\,
      I4 => \stateCorecfg_reg_n_0_[0]\,
      O => \stateCorecfg[2]_i_2_n_0\
    );
\stateCorecfg[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => stateCorecfg0,
      I1 => corecfgAXIL_bvalid,
      I2 => \stateCorecfg_reg_n_0_[1]\,
      I3 => corecfgAXIL_wready,
      I4 => \stateCorecfg_reg_n_0_[0]\,
      I5 => csirxss_s_axi_awready,
      O => \stateCorecfg[2]_i_3_n_0\
    );
\stateCorecfg_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => p_0_out,
      CLR => sda_sig_reg,
      D => \stateCorecfg[0]_i_1_n_0\,
      Q => \stateCorecfg_reg_n_0_[0]\
    );
\stateCorecfg_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => p_0_out,
      CLR => sda_sig_reg,
      D => \stateCorecfg[1]_i_1_n_0\,
      Q => \stateCorecfg_reg_n_0_[1]\
    );
\stateCorecfg_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => p_0_out,
      CLR => sda_sig_reg,
      D => \stateCorecfg[2]_i_2_n_0\,
      Q => \stateCorecfg_reg_n_0_[2]\
    );
\stateCorner[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^synthnotlive_reg_0\,
      I1 => grayVideoinToManyAXIS_tvalid,
      O => grayToManyAXIS_tvalid_sig_reg
    );
\stateIgr[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F4FF"
    )
        port map (
      I0 => \^synthnotlive_reg_0\,
      I1 => \^camiftovideoinaxis_tvalid\,
      I2 => \klm_reg[0]_7\(1),
      I3 => \klm_reg[0]_7\(0),
      O => \stateIgr_reg[1]\(0)
    );
\stateIgr[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7777777777747777"
    )
        port map (
      I0 => \probe[0]_INST_0_i_2_n_0\,
      I1 => synthNotLive_reg_n_0,
      I2 => video_out_tlast,
      I3 => \^statelive_reg[2]_0\(0),
      I4 => \^statelive_reg[2]_0\(1),
      I5 => \^statelive_reg[2]_0\(2),
      O => camifToVideoinAXIS_tlast
    );
\stateLive[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444444544444"
    )
        port map (
      I0 => \stateLive[1]_i_2_n_0\,
      I1 => \stateLive[0]_i_2_n_0\,
      I2 => \^statelive_reg[2]_0\(1),
      I3 => \^statelive_reg[2]_0\(0),
      I4 => hdrNotFix_reg_n_0,
      I5 => \i_reg[0]__1_0\,
      O => \stateLive[0]_i_1_n_0\
    );
\stateLive[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF13101010"
    )
        port map (
      I0 => \stateLive[1]_i_5_n_0\,
      I1 => \^statelive_reg[2]_0\(1),
      I2 => \^statelive_reg[2]_0\(0),
      I3 => myMipirx_n_177,
      I4 => video_out_tvalid,
      I5 => \^statelive_reg[2]_0\(2),
      O => \stateLive[0]_i_2_n_0\
    );
\stateLive[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4454445444544444"
    )
        port map (
      I0 => \stateLive[1]_i_2_n_0\,
      I1 => \stateLive[1]_i_3_n_0\,
      I2 => \^statelive_reg[2]_0\(1),
      I3 => \^statelive_reg[2]_0\(0),
      I4 => \i_reg[0]__1_0\,
      I5 => hdrNotFix_reg_n_0,
      O => \stateLive[1]_i_1_n_0\
    );
\stateLive[1]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFEF"
    )
        port map (
      I0 => \^rowraw_lcl_reg[11]_0\(0),
      I1 => \^rowraw_lcl_reg[11]_0\(6),
      I2 => \stateLive[1]_i_15_n_0\,
      I3 => \^rowraw_lcl_reg[11]_0\(3),
      I4 => \^rowraw_lcl_reg[11]_0\(7),
      I5 => \stateLive[1]_i_16_n_0\,
      O => \stateLive[1]_i_10_n_0\
    );
\stateLive[1]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rowraw_lcl_reg[11]_0\(5),
      I1 => \^rowraw_lcl_reg[11]_0\(8),
      O => \stateLive[1]_i_15_n_0\
    );
\stateLive[1]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \rowRaw_lcl_reg_n_0_[0]\,
      I1 => \rowRaw_lcl_reg_n_0_[1]\,
      O => \stateLive[1]_i_16_n_0\
    );
\stateLive[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \i_reg[0]__1_n_0\,
      I1 => \^statelive_reg[2]_0\(2),
      O => \stateLive[1]_i_2_n_0\
    );
\stateLive[1]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFEFBFF7FDFEFB7F"
    )
        port map (
      I0 => \rowRaw_lcl_reg_n_0_[1]\,
      I1 => \rowRaw_lcl_reg_n_0_[0]\,
      I2 => NRowRaw(2),
      I3 => NRowRaw(1),
      I4 => NRowRaw(0),
      I5 => \rowRaw_lcl_reg_n_0_[2]\,
      O => \rowRaw_lcl_reg[1]_0\
    );
\stateLive[1]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAEA"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(2),
      I1 => \stateLive[1]_i_5_n_0\,
      I2 => \^statelive_reg[2]_0\(0),
      I3 => \^statelive_reg[2]_0\(1),
      O => \stateLive[1]_i_3_n_0\
    );
\stateLive[1]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => \^rowraw_lcl_reg[11]_0\(2),
      I1 => \rowRaw_lcl_reg_n_0_[2]\,
      I2 => \^rowraw_lcl_reg[11]_0\(1),
      I3 => \^rowraw_lcl_reg[11]_0\(4),
      I4 => \stateLive[1]_i_10_n_0\,
      O => \stateLive[1]_i_5_n_0\
    );
\stateLive[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"333330003000BBBB"
    )
        port map (
      I0 => ackLiveToConfigSetReg_reg_n_0,
      I1 => \^statelive_reg[2]_0\(2),
      I2 => video_out_tlast,
      I3 => video_out_tvalid,
      I4 => \^statelive_reg[2]_0\(0),
      I5 => \^statelive_reg[2]_0\(1),
      O => \stateLive[2]_i_1_n_0\
    );
\stateLive[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^statelive_reg[2]_0\(1),
      I1 => \^statelive_reg[2]_0\(0),
      I2 => \^statelive_reg[2]_0\(2),
      O => \stateLive[2]_i_2_n_0\
    );
\stateLive_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateLive[2]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \stateLive[0]_i_1_n_0\,
      Q => \^statelive_reg[2]_0\(0)
    );
\stateLive_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateLive[2]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \stateLive[1]_i_1_n_0\,
      Q => \^statelive_reg[2]_0\(1)
    );
\stateLive_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateLive[2]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \stateLive[2]_i_2_n_0\,
      Q => \^statelive_reg[2]_0\(2)
    );
stateOp_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => stateOp,
      CLR => sda_sig_reg,
      D => stateOp47_out,
      Q => \^stateop_reg_0\
    );
\stateStream[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => \^ixtexp_sig_reg[2]_0\(0),
      I1 => ixTExp(1),
      I2 => ixTExp(0),
      I3 => \^synthnotlive_reg_0\,
      I4 => \stateStream_reg[0]_0\(0),
      I5 => \stateStream_reg[0]_0\(1),
      O => \stateStream_reg[0]\
    );
\stateStream[1]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \^synthnotlive_reg_0\,
      I1 => ixTExp(0),
      I2 => ixTExp(1),
      I3 => \^ixtexp_sig_reg[2]_0\(0),
      O => synthNotLive_reg_1
    );
\stateSynth[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BA00BA00BAFFBA00"
    )
        port map (
      I0 => \stateSynth[0]_i_2_n_0\,
      I1 => \stateSynth[0]_i_3_n_0\,
      I2 => \stateSynth[1]_i_4_n_0\,
      I3 => \stateSynth[2]_i_7_n_0\,
      I4 => rng,
      I5 => \stateSynth[0]_i_4_n_0\,
      O => \stateSynth[0]_i_1_n_0\
    );
\stateSynth[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404FF0F04040404"
    )
        port map (
      I0 => \i_reg[0]__0_0\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \stateSynth[0]_i_4_n_0\,
      I5 => \stateSynth[2]_i_8_n_0\,
      O => \stateSynth[0]_i_2_n_0\
    );
\stateSynth[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000D000D0D0D0D0"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[0]\,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth[0]_i_4_n_0\,
      I4 => \row_reg[0]_1\,
      I5 => \i[7]_i_4_n_0\,
      O => \stateSynth[0]_i_3_n_0\
    );
\stateSynth[0]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tixVSynthmode_reg_n_0_[0]\,
      I1 => \bsh[1]_i_3_n_0\,
      O => \stateSynth[0]_i_4_n_0\
    );
\stateSynth[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000755530307575"
    )
        port map (
      I0 => \stateSynth[2]_i_3_n_0\,
      I1 => \stateSynth[1]_i_2_n_0\,
      I2 => \stateSynth[2]_i_7_n_0\,
      I3 => \stateSynth[2]_i_10_n_0\,
      I4 => \stateSynth[1]_i_3_n_0\,
      I5 => \stateSynth[1]_i_4_n_0\,
      O => \stateSynth[1]_i_1_n_0\
    );
\stateSynth[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E3E3232023202320"
    )
        port map (
      I0 => \i_reg[0]__0_0\,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \stateSynth_reg_n_0_[0]\,
      I4 => \stateSynth[1]_i_3_n_0\,
      I5 => \ixTExp_sig[2]_i_3_n_0\,
      O => \stateSynth[1]_i_2_n_0\
    );
\stateSynth[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \tixVSynthmode_reg_n_0_[0]\,
      I1 => \bsh[1]_i_3_n_0\,
      O => \stateSynth[1]_i_3_n_0\
    );
\stateSynth[1]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0700"
    )
        port map (
      I0 => \ixTExp_sig[2]_i_3_n_0\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      O => \stateSynth[1]_i_4_n_0\
    );
\stateSynth[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C8C8F8FAC8C8C8C8"
    )
        port map (
      I0 => \stateSynth[2]_i_3_n_0\,
      I1 => \stateSynth[2]_i_4_n_0\,
      I2 => \stateSynth[2]_i_5_n_0\,
      I3 => \stateSynth[2]_i_6_n_0\,
      I4 => \stateSynth_reg_n_0_[1]\,
      I5 => \^statesynth_reg[2]_0\(0),
      O => \stateSynth[2]_i_1_n_0\
    );
\stateSynth[2]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A200"
    )
        port map (
      I0 => \stateSynth[2]_i_6_n_0\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      O => \stateSynth[2]_i_10_n_0\
    );
\stateSynth[2]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \tixVSynthmode_reg_n_0_[4]\,
      I1 => \tixVSynthmode_reg_n_0_[3]\,
      I2 => \tixVSynthmode_reg_n_0_[5]\,
      I3 => \tixVSynthmode_reg_n_0_[6]\,
      I4 => \tixVSynthmode_reg_n_0_[2]\,
      I5 => p_0_in0,
      O => \stateSynth[2]_i_11_n_0\
    );
\stateSynth[2]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFDEFF7F7BFFDEF"
    )
        port map (
      I0 => \row_reg_n_0_[0]\,
      I1 => \row_reg_n_0_[2]\,
      I2 => NRowRaw(0),
      I3 => NRowRaw(1),
      I4 => NRowRaw(2),
      I5 => \row_reg_n_0_[1]\,
      O => \row_reg[0]_0\
    );
\stateSynth[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000220200A022A2"
    )
        port map (
      I0 => \stateSynth[2]_i_7_n_0\,
      I1 => \stateSynth[2]_i_8_n_0\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \stateSynth[2]_i_9_n_0\,
      I5 => \stateSynth[2]_i_10_n_0\,
      O => \stateSynth[2]_i_2_n_0\
    );
\stateSynth[2]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => rng,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \stateSynth_reg_n_0_[0]\,
      O => \stateSynth[2]_i_3_n_0\
    );
\stateSynth[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0FFFD0FFFFFFFFFF"
    )
        port map (
      I0 => \ixTExp_sig[2]_i_3_n_0\,
      I1 => \stateSynth[2]_i_5_n_0\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => rng,
      O => \stateSynth[2]_i_4_n_0\
    );
\stateSynth[2]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4C"
    )
        port map (
      I0 => \tixVSynthmode_reg_n_0_[0]\,
      I1 => \stateSynth[2]_i_11_n_0\,
      I2 => \tixVSynthmode_reg_n_0_[1]\,
      O => \stateSynth[2]_i_5_n_0\
    );
\stateSynth[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA82AAAAAAAAAA82"
    )
        port map (
      I0 => \i[7]_i_4_n_0\,
      I1 => \stateSynth_reg[0]_0\,
      I2 => \^row_reg[11]_0\(7),
      I3 => \stateSynth_reg[0]_1\,
      I4 => \^row_reg[11]_0\(8),
      I5 => \stateSynth_reg[0]_2\,
      O => \stateSynth[2]_i_6_n_0\
    );
\stateSynth[2]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => rng,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \stateSynth_reg_n_0_[0]\,
      O => \stateSynth[2]_i_7_n_0\
    );
\stateSynth[2]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"808A"
    )
        port map (
      I0 => \ixTExp_sig[2]_i_3_n_0\,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \stateSynth_reg_n_0_[0]\,
      O => \stateSynth[2]_i_8_n_0\
    );
\stateSynth[2]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000E"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \i_reg[0]__0_0\,
      O => \stateSynth[2]_i_9_n_0\
    );
\stateSynth_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSynth[2]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \stateSynth[0]_i_1_n_0\,
      Q => \stateSynth_reg_n_0_[0]\
    );
\stateSynth_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSynth[2]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \stateSynth[1]_i_1_n_0\,
      Q => \stateSynth_reg_n_0_[1]\
    );
\stateSynth_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => \stateSynth[2]_i_1_n_0\,
      CLR => sda_sig_reg,
      D => \stateSynth[2]_i_2_n_0\,
      Q => \^statesynth_reg[2]_0\(0)
    );
synthNotLive_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => hdrNotFix48_out,
      CLR => sda_sig_reg,
      D => synthNotLive,
      Q => synthNotLive_reg_n_0
    );
\tixVState[1]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => ixTExp(1),
      I1 => Q(1),
      I2 => ixTExp(0),
      I3 => Q(0),
      O => \ixTExp_lcl_reg[1]_0\
    );
\tixVState[1]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \ixTExp_sig_reg_n_0_[2]\,
      I1 => synthNotLive_reg_n_0,
      I2 => liveIxTExp(2),
      O => \^ixtexp_sig_reg[2]_0\(0)
    );
\tixVSynthmode_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => \tixVSynthmode_reg[7]_0\(0),
      Q => \tixVSynthmode_reg_n_0_[0]\
    );
\tixVSynthmode_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => \tixVSynthmode_reg[7]_0\(1),
      Q => \tixVSynthmode_reg_n_0_[1]\
    );
\tixVSynthmode_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => \tixVSynthmode_reg[7]_0\(2),
      Q => \tixVSynthmode_reg_n_0_[2]\
    );
\tixVSynthmode_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => \tixVSynthmode_reg[7]_0\(3),
      Q => \tixVSynthmode_reg_n_0_[3]\
    );
\tixVSynthmode_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => \tixVSynthmode_reg[7]_0\(4),
      Q => \tixVSynthmode_reg_n_0_[4]\
    );
\tixVSynthmode_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => \tixVSynthmode_reg[7]_0\(5),
      Q => \tixVSynthmode_reg_n_0_[5]\
    );
\tixVSynthmode_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => \tixVSynthmode_reg[7]_0\(6),
      Q => \tixVSynthmode_reg_n_0_[6]\
    );
\tixVSynthmode_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => E(0),
      CLR => sda_sig_reg,
      D => \tixVSynthmode_reg[7]_0\(7),
      Q => p_0_in0
    );
\toVideoinAXIS_tdata_sig[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCFFF400000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[21]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[12]_i_3_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[0]_i_2_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[0]_i_3_n_0\,
      I4 => \^statesynth_reg[2]_0\(0),
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[0]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E20000"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[0]\,
      I1 => \row_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[0]\,
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \stateSynth_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[0]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00800A80A080AA80"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[0]_i_4_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \toVideoinAXIS_tdata_sig[6]_i_4_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[0]_i_5_n_0\,
      O => \toVideoinAXIS_tdata_sig[0]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[0]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A3"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg[9]_i_8_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[3]_i_6_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[0]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[0]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[3]_i_7_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[9]_i_9_n_0\,
      O => \toVideoinAXIS_tdata_sig[0]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[10]_i_2_n_0\,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \blk_reg_n_0_[10]\,
      I3 => whtNotBlk,
      I4 => \wht_reg_n_0_[10]\,
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[10]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[3]\,
      I1 => \g0_lcl_reg_n_0_[5]\,
      I2 => gsh(1),
      I3 => \g0_lcl_reg_n_0_[7]\,
      I4 => gsh(0),
      I5 => \g0_lcl_reg_n_0_[9]\,
      O => \toVideoinAXIS_tdata_sig[10]_i_10_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[3]\,
      I1 => \b_lcl_reg_n_0_[5]\,
      I2 => \bsh_reg_n_0_[1]\,
      I3 => \b_lcl_reg_n_0_[7]\,
      I4 => \bsh_reg_n_0_[0]\,
      I5 => \b_lcl_reg_n_0_[9]\,
      O => \toVideoinAXIS_tdata_sig[10]_i_11_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[0]\,
      I1 => \g0_lcl_reg_n_0_[2]\,
      I2 => gsh(1),
      I3 => \g0_lcl_reg_n_0_[4]\,
      I4 => gsh(0),
      I5 => \g0_lcl_reg_n_0_[6]\,
      O => \toVideoinAXIS_tdata_sig[10]_i_12_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[0]\,
      I1 => \b_lcl_reg_n_0_[2]\,
      I2 => \bsh_reg_n_0_[1]\,
      I3 => \b_lcl_reg_n_0_[4]\,
      I4 => \bsh_reg_n_0_[0]\,
      I5 => \b_lcl_reg_n_0_[6]\,
      O => \toVideoinAXIS_tdata_sig[10]_i_13_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => gsh(1),
      I1 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[10]_i_14_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \row_reg_n_0_[0]\,
      I1 => \bsh_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[10]_i_15_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[9]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[11]\,
      O => \toVideoinAXIS_tdata_sig[10]_i_16_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[6]\,
      I1 => gsh(0),
      I2 => \g0_lcl_reg_n_0_[8]\,
      O => \toVideoinAXIS_tdata_sig[10]_i_17_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4040404000FF0000"
    )
        port map (
      I0 => \bsh_reg_n_0_[1]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[10]\,
      I3 => \toVideoinAXIS_tdata_sig[23]_i_21_n_0\,
      I4 => \g0_lcl_reg_n_0_[10]\,
      I5 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[10]_i_18_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[6]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[8]\,
      O => \toVideoinAXIS_tdata_sig[10]_i_19_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCFCEECCCCCCCC"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[10]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[10]_i_4_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[10]_i_5_n_0\,
      I3 => \ixTExp_sig_reg_n_0_[1]\,
      I4 => \ixTExp_sig_reg_n_0_[2]\,
      I5 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      O => \toVideoinAXIS_tdata_sig[10]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg[10]_i_6_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig_reg[10]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[10]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8E8E82828E828E82"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[22]_i_8_n_0\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \g0_lcl_reg_n_0_[10]\,
      I4 => \b_lcl_reg_n_0_[10]\,
      I5 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[10]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[10]_i_8_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[10]_i_9_n_0\,
      O => \toVideoinAXIS_tdata_sig[10]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FF000047FF47FF"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[9]\,
      I1 => gsh(0),
      I2 => \g0_lcl_reg_n_0_[11]\,
      I3 => \toVideoinAXIS_tdata_sig[10]_i_14_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[10]_i_15_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[10]_i_16_n_0\,
      O => \toVideoinAXIS_tdata_sig[10]_i_8_n_0\
    );
\toVideoinAXIS_tdata_sig[10]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF0F0F0F8F8F8F8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[10]_i_17_n_0\,
      I1 => gsh(1),
      I2 => \toVideoinAXIS_tdata_sig[10]_i_18_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[10]_i_19_n_0\,
      I4 => \bsh_reg_n_0_[1]\,
      I5 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[10]_i_9_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A2020202"
    )
        port map (
      I0 => \stateSynth[2]_i_7_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[11]_i_2_n_0\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => whtNotBlk,
      I4 => \wht_reg_n_0_[11]\,
      O => \toVideoinAXIS_tdata_sig[11]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[4]\,
      I1 => gsh(0),
      I2 => \g0_lcl_reg_n_0_[6]\,
      O => \toVideoinAXIS_tdata_sig[11]_i_10_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00B8000000B800"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[8]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[10]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \bsh_reg_n_0_[1]\,
      I5 => \toVideoinAXIS_tdata_sig[11]_i_18_n_0\,
      O => \toVideoinAXIS_tdata_sig[11]_i_11_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[5]\,
      I1 => gsh(0),
      I2 => \g0_lcl_reg_n_0_[7]\,
      O => \toVideoinAXIS_tdata_sig[11]_i_12_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[1]\,
      I1 => gsh(0),
      I2 => \g0_lcl_reg_n_0_[3]\,
      O => \toVideoinAXIS_tdata_sig[11]_i_13_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00B8000000B800"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[5]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[7]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \bsh_reg_n_0_[1]\,
      I5 => \toVideoinAXIS_tdata_sig[7]_i_8_n_0\,
      O => \toVideoinAXIS_tdata_sig[11]_i_14_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[7]\,
      I1 => gsh(0),
      I2 => \g0_lcl_reg_n_0_[9]\,
      O => \toVideoinAXIS_tdata_sig[11]_i_15_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4040404000FF0000"
    )
        port map (
      I0 => \bsh_reg_n_0_[1]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[11]\,
      I3 => \toVideoinAXIS_tdata_sig[23]_i_21_n_0\,
      I4 => \g0_lcl_reg_n_0_[11]\,
      I5 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[11]_i_16_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[7]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[9]\,
      O => \toVideoinAXIS_tdata_sig[11]_i_17_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[4]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[6]\,
      O => \toVideoinAXIS_tdata_sig[11]_i_18_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF3AFFFF"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[11]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[11]_i_4_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[11]_i_5_n_0\,
      O => \toVideoinAXIS_tdata_sig[11]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[11]_i_6_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[11]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[11]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[2]_i_6_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[11]_i_8_n_0\,
      O => \toVideoinAXIS_tdata_sig[11]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAEAAAAAEAAAEAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[23]_i_10_n_0\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \g0_lcl_reg_n_0_[11]\,
      I4 => \b_lcl_reg_n_0_[11]\,
      I5 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[11]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CDEF"
    )
        port map (
      I0 => gsh(1),
      I1 => \row_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[11]_i_9_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[11]_i_10_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[11]_i_11_n_0\,
      O => \toVideoinAXIS_tdata_sig[11]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CDEF"
    )
        port map (
      I0 => gsh(1),
      I1 => \row_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[11]_i_12_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[11]_i_13_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[11]_i_14_n_0\,
      O => \toVideoinAXIS_tdata_sig[11]_i_7_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF0F0F0F8F8F8F8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[11]_i_15_n_0\,
      I1 => gsh(1),
      I2 => \toVideoinAXIS_tdata_sig[11]_i_16_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[11]_i_17_n_0\,
      I4 => \bsh_reg_n_0_[1]\,
      I5 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[11]_i_8_n_0\
    );
\toVideoinAXIS_tdata_sig[11]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[8]\,
      I1 => gsh(0),
      I2 => \g0_lcl_reg_n_0_[10]\,
      O => \toVideoinAXIS_tdata_sig[11]_i_9_n_0\
    );
\toVideoinAXIS_tdata_sig[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0FFBA00000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[12]_i_2_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_3_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[12]_i_3_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[12]_i_4_n_0\,
      I4 => \^statesynth_reg[2]_0\(0),
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[12]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[12]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E40000"
    )
        port map (
      I0 => \row_reg_n_0_[0]\,
      I1 => \r_lcl_reg_n_0_[0]\,
      I2 => \g1_lcl_reg_n_0_[0]\,
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \stateSynth_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[12]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[12]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \wht_reg_n_0_[0]\,
      I1 => whtNotBlk,
      I2 => \blk_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[12]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[12]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0AAA88000A008800"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[18]_i_7_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[18]_i_6_n_0\,
      I3 => \ixTExp_sig_reg_n_0_[1]\,
      I4 => \ixTExp_sig_reg_n_0_[2]\,
      I5 => \toVideoinAXIS_tdata_sig[18]_i_5_n_0\,
      O => \toVideoinAXIS_tdata_sig[12]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0FFBA00000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[13]_i_2_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_3_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[13]_i_3_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[13]_i_4_n_0\,
      I4 => \^statesynth_reg[2]_0\(0),
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[13]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[13]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44400040"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[1]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \g1_lcl_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[13]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[13]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \wht_reg_n_0_[1]\,
      I1 => whtNotBlk,
      I2 => \blk_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[13]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[13]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0800AAAA2820"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[2]\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \toVideoinAXIS_tdata_sig[19]_i_7_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[13]_i_5_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[19]_i_6_n_0\,
      O => \toVideoinAXIS_tdata_sig[13]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[13]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"010001C0"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[16]_i_6_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[1]\,
      I2 => \ixTExp_sig_reg_n_0_[2]\,
      I3 => \ixTExp_sig_reg_n_0_[0]\,
      I4 => \toVideoinAXIS_tdata_sig[22]_i_9_n_0\,
      O => \toVideoinAXIS_tdata_sig[13]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAE00AE00000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_2_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[14]_i_4_n_0\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \toVideoinAXIS_tdata_sig[14]_i_5_n_0\,
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[14]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAAAAAAAAAAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_6_n_0\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \ixTExp_sig_reg_n_0_[1]\,
      I5 => \toVideoinAXIS_tdata_sig[20]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[14]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[14]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \stateSynth_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[14]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFF550FFCFF55FF"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[20]_i_6_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[14]_i_7_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[0]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \ixTExp_sig_reg_n_0_[1]\,
      I5 => \toVideoinAXIS_tdata_sig[17]_i_5_n_0\,
      O => \toVideoinAXIS_tdata_sig[14]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[14]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \wht_reg_n_0_[2]\,
      I1 => whtNotBlk,
      I2 => \blk_reg_n_0_[2]\,
      O => \toVideoinAXIS_tdata_sig[14]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[14]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0000CFC0AAAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_5_n_0\,
      I1 => \g1_lcl_reg_n_0_[2]\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \r_lcl_reg_n_0_[2]\,
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => \stateSynth_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[14]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[14]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF7F7FFFFF7F7F"
    )
        port map (
      I0 => \rsh_reg_n_0_[0]\,
      I1 => \rsh_reg_n_0_[1]\,
      I2 => \r_lcl_reg_n_0_[10]\,
      I3 => \toVideoinAXIS_tdata_sig[14]_i_8_n_0\,
      I4 => \row_reg_n_0_[0]\,
      I5 => \g1_lcl_reg_n_0_[10]\,
      O => \toVideoinAXIS_tdata_sig[14]_i_7_n_0\
    );
\toVideoinAXIS_tdata_sig[14]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gsh(1),
      I1 => gsh(0),
      O => \toVideoinAXIS_tdata_sig[14]_i_8_n_0\
    );
\toVideoinAXIS_tdata_sig[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[15]_i_2_n_0\,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \blk_reg_n_0_[3]\,
      I3 => whtNotBlk,
      I4 => \wht_reg_n_0_[3]\,
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[15]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55D50000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[15]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_8_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[15]_i_4_n_0\,
      O => \toVideoinAXIS_tdata_sig[15]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFF550FFCFF55FF"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[21]_i_7_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_9_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[0]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \ixTExp_sig_reg_n_0_[1]\,
      I5 => \toVideoinAXIS_tdata_sig[18]_i_8_n_0\,
      O => \toVideoinAXIS_tdata_sig[15]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0000CFC0AAAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[3]_i_4_n_0\,
      I1 => \g1_lcl_reg_n_0_[3]\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \r_lcl_reg_n_0_[3]\,
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => \stateSynth_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[15]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0FFBA00000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[16]_i_2_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_3_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[16]_i_3_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[16]_i_4_n_0\,
      I4 => \^statesynth_reg[2]_0\(0),
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[16]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[16]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44400040"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[4]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \g1_lcl_reg_n_0_[4]\,
      O => \toVideoinAXIS_tdata_sig[16]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[16]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \wht_reg_n_0_[4]\,
      I1 => whtNotBlk,
      I2 => \blk_reg_n_0_[4]\,
      O => \toVideoinAXIS_tdata_sig[16]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[16]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0A20AAAA0020"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[22]_i_3_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \toVideoinAXIS_tdata_sig[16]_i_5_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[22]_i_5_n_0\,
      O => \toVideoinAXIS_tdata_sig[16]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[16]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00011101"
    )
        port map (
      I0 => \ixTExp_sig_reg_n_0_[2]\,
      I1 => \ixTExp_sig_reg_n_0_[1]\,
      I2 => \toVideoinAXIS_tdata_sig[16]_i_6_n_0\,
      I3 => \ixTExp_sig_reg_n_0_[0]\,
      I4 => \toVideoinAXIS_tdata_sig[19]_i_8_n_0\,
      O => \toVideoinAXIS_tdata_sig[16]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[16]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FDFFFDFFFDFFFD"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[0]\,
      I1 => \rsh_reg_n_0_[0]\,
      I2 => \rsh_reg_n_0_[1]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \g1_lcl_reg_n_0_[0]\,
      I5 => \toVideoinAXIS_tdata_sig[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[16]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FE0E0000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[17]_i_2_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[17]_i_3_n_0\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => \toVideoinAXIS_tdata_sig[17]_i_4_n_0\,
      I4 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[17]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[17]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[1]\,
      I1 => \rsh_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[17]_i_10_n_0\
    );
\toVideoinAXIS_tdata_sig[17]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[0]\,
      I1 => \rsh_reg_n_0_[1]\,
      I2 => \r_lcl_reg_n_0_[2]\,
      I3 => \rsh_reg_n_0_[0]\,
      I4 => \r_lcl_reg_n_0_[4]\,
      O => \toVideoinAXIS_tdata_sig[17]_i_11_n_0\
    );
\toVideoinAXIS_tdata_sig[17]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[0]\,
      I1 => gsh(1),
      I2 => \g1_lcl_reg_n_0_[2]\,
      I3 => gsh(0),
      I4 => \g1_lcl_reg_n_0_[4]\,
      O => \toVideoinAXIS_tdata_sig[17]_i_12_n_0\
    );
\toVideoinAXIS_tdata_sig[17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E020FFFFE020E020"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[17]_i_5_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[17]_i_6_n_0\,
      I3 => \toVideoinAXIS_tdata_sig_reg[17]_i_7_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[23]_i_4_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[17]_i_8_n_0\,
      O => \toVideoinAXIS_tdata_sig[17]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[17]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAAAAAAAAAAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[17]_i_9_n_0\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[1]\,
      I4 => \ixTExp_sig_reg_n_0_[2]\,
      I5 => \toVideoinAXIS_tdata_sig[23]_i_5_n_0\,
      O => \toVideoinAXIS_tdata_sig[17]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[17]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \wht_reg_n_0_[5]\,
      I1 => whtNotBlk,
      I2 => \blk_reg_n_0_[5]\,
      O => \toVideoinAXIS_tdata_sig[17]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[17]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400040004FF0400"
    )
        port map (
      I0 => gsh(0),
      I1 => \g1_lcl_reg_n_0_[1]\,
      I2 => gsh(1),
      I3 => \row_reg_n_0_[0]\,
      I4 => \toVideoinAXIS_tdata_sig[17]_i_10_n_0\,
      I5 => \rsh_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[17]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[17]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[0]\,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \ixTExp_sig_reg_n_0_[2]\,
      I3 => \ixTExp_sig_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[17]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[17]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[0]\,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \ixTExp_sig_reg_n_0_[2]\,
      I3 => \ixTExp_sig_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[17]_i_8_n_0\
    );
\toVideoinAXIS_tdata_sig[17]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0000CFC0AAAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[17]_i_4_n_0\,
      I1 => \g1_lcl_reg_n_0_[5]\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \r_lcl_reg_n_0_[5]\,
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => \stateSynth_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[17]_i_9_n_0\
    );
\toVideoinAXIS_tdata_sig[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0FFBA00000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[18]_i_2_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_3_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[18]_i_3_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[18]_i_4_n_0\,
      I4 => \^statesynth_reg[2]_0\(0),
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[18]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[18]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44400040"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[6]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \g1_lcl_reg_n_0_[6]\,
      O => \toVideoinAXIS_tdata_sig[18]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[18]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \wht_reg_n_0_[6]\,
      I1 => whtNotBlk,
      I2 => \blk_reg_n_0_[6]\,
      O => \toVideoinAXIS_tdata_sig[18]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[18]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00880AAA00880A00"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[18]_i_5_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[18]_i_6_n_0\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \ixTExp_sig_reg_n_0_[1]\,
      I5 => \toVideoinAXIS_tdata_sig[18]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[18]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[18]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg[21]_i_11_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig_reg[21]_i_12_n_0\,
      O => \toVideoinAXIS_tdata_sig[18]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[18]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[21]_i_9_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[21]_i_10_n_0\,
      O => \toVideoinAXIS_tdata_sig[18]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[18]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg[21]_i_13_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[18]_i_8_n_0\,
      O => \toVideoinAXIS_tdata_sig[18]_i_7_n_0\
    );
\toVideoinAXIS_tdata_sig[18]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800FFFFB800B800"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[0]\,
      I1 => \rsh_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[2]\,
      I3 => \toVideoinAXIS_tdata_sig[19]_i_9_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[19]_i_10_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[18]_i_9_n_0\,
      O => \toVideoinAXIS_tdata_sig[18]_i_8_n_0\
    );
\toVideoinAXIS_tdata_sig[18]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[0]\,
      I1 => gsh(0),
      I2 => \g1_lcl_reg_n_0_[2]\,
      O => \toVideoinAXIS_tdata_sig[18]_i_9_n_0\
    );
\toVideoinAXIS_tdata_sig[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0FFBA00000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[19]_i_2_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_3_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[19]_i_3_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[19]_i_4_n_0\,
      I4 => \^statesynth_reg[2]_0\(0),
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[19]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[19]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => gsh(1),
      I1 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[19]_i_10_n_0\
    );
\toVideoinAXIS_tdata_sig[19]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[1]\,
      I1 => gsh(0),
      I2 => \g1_lcl_reg_n_0_[3]\,
      O => \toVideoinAXIS_tdata_sig[19]_i_11_n_0\
    );
\toVideoinAXIS_tdata_sig[19]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44400040"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[7]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \g1_lcl_reg_n_0_[7]\,
      O => \toVideoinAXIS_tdata_sig[19]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[19]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \wht_reg_n_0_[7]\,
      I1 => whtNotBlk,
      I2 => \blk_reg_n_0_[7]\,
      O => \toVideoinAXIS_tdata_sig[19]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[19]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0088AA0A0088000A"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[19]_i_5_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[19]_i_6_n_0\,
      I3 => \ixTExp_sig_reg_n_0_[1]\,
      I4 => \ixTExp_sig_reg_n_0_[2]\,
      I5 => \toVideoinAXIS_tdata_sig[19]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[19]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[19]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \ixTExp_sig_reg_n_0_[0]\,
      I1 => \toVideoinAXIS_tdata_sig[22]_i_9_n_0\,
      O => \toVideoinAXIS_tdata_sig[19]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[19]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[22]_i_7_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[19]_i_8_n_0\,
      O => \toVideoinAXIS_tdata_sig[19]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[19]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A3"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[22]_i_10_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[22]_i_6_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[19]_i_7_n_0\
    );
\toVideoinAXIS_tdata_sig[19]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FF000047FF47FF"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[1]\,
      I1 => \rsh_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[3]\,
      I3 => \toVideoinAXIS_tdata_sig[19]_i_9_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[19]_i_10_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[19]_i_11_n_0\,
      O => \toVideoinAXIS_tdata_sig[19]_i_8_n_0\
    );
\toVideoinAXIS_tdata_sig[19]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \row_reg_n_0_[0]\,
      I1 => \rsh_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[19]_i_9_n_0\
    );
\toVideoinAXIS_tdata_sig[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[1]_i_2_n_0\,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \blk_reg_n_0_[1]\,
      I3 => whtNotBlk,
      I4 => \wht_reg_n_0_[1]\,
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[1]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF080000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[7]_i_6_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[2]\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \toVideoinAXIS_tdata_sig[1]_i_3_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[1]_i_4_n_0\,
      O => \toVideoinAXIS_tdata_sig[1]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"202020E0232320E0"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[7]_i_5_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[2]\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \toVideoinAXIS_tdata_sig[10]_i_8_n_0\,
      I4 => \ixTExp_sig_reg_n_0_[0]\,
      I5 => \toVideoinAXIS_tdata_sig[4]_i_5_n_0\,
      O => \toVideoinAXIS_tdata_sig[1]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8E8E82828E828E82"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[13]_i_3_n_0\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \g0_lcl_reg_n_0_[1]\,
      I4 => \b_lcl_reg_n_0_[1]\,
      I5 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[1]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0FFBA00000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[20]_i_2_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_3_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[20]_i_3_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[20]_i_4_n_0\,
      I4 => \^statesynth_reg[2]_0\(0),
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[20]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[20]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44400040"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[8]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \g1_lcl_reg_n_0_[8]\,
      O => \toVideoinAXIS_tdata_sig[20]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[20]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \wht_reg_n_0_[8]\,
      I1 => whtNotBlk,
      I2 => \blk_reg_n_0_[8]\,
      O => \toVideoinAXIS_tdata_sig[20]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[20]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08AA080A08A00800"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[20]_i_5_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \toVideoinAXIS_tdata_sig[20]_i_6_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[20]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[20]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[20]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \ixTExp_sig_reg_n_0_[0]\,
      I1 => \toVideoinAXIS_tdata_sig[14]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[20]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[20]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A3"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[23]_i_9_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[23]_i_7_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[20]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[20]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[23]_i_8_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig_reg[17]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[20]_i_7_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0FFBA00000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[21]_i_2_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_3_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[21]_i_4_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[21]_i_5_n_0\,
      I4 => \^statesynth_reg[2]_0\(0),
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[21]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FF000047FF47FF"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[8]\,
      I1 => \rsh_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[10]\,
      I3 => \toVideoinAXIS_tdata_sig[22]_i_15_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[22]_i_16_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[21]_i_14_n_0\,
      O => \toVideoinAXIS_tdata_sig[21]_i_10_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[8]\,
      I1 => gsh(0),
      I2 => \g1_lcl_reg_n_0_[10]\,
      O => \toVideoinAXIS_tdata_sig[21]_i_14_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[5]\,
      I1 => \r_lcl_reg_n_0_[7]\,
      I2 => \rsh_reg_n_0_[1]\,
      I3 => \r_lcl_reg_n_0_[9]\,
      I4 => \rsh_reg_n_0_[0]\,
      I5 => \r_lcl_reg_n_0_[11]\,
      O => \toVideoinAXIS_tdata_sig[21]_i_15_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[5]\,
      I1 => \g1_lcl_reg_n_0_[7]\,
      I2 => gsh(1),
      I3 => \g1_lcl_reg_n_0_[9]\,
      I4 => gsh(0),
      I5 => \g1_lcl_reg_n_0_[11]\,
      O => \toVideoinAXIS_tdata_sig[21]_i_16_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[2]\,
      I1 => \r_lcl_reg_n_0_[4]\,
      I2 => \rsh_reg_n_0_[1]\,
      I3 => \r_lcl_reg_n_0_[6]\,
      I4 => \rsh_reg_n_0_[0]\,
      I5 => \r_lcl_reg_n_0_[8]\,
      O => \toVideoinAXIS_tdata_sig[21]_i_17_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[2]\,
      I1 => \g1_lcl_reg_n_0_[4]\,
      I2 => gsh(1),
      I3 => \g1_lcl_reg_n_0_[6]\,
      I4 => gsh(0),
      I5 => \g1_lcl_reg_n_0_[8]\,
      O => \toVideoinAXIS_tdata_sig[21]_i_18_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[1]\,
      I1 => \rsh_reg_n_0_[1]\,
      I2 => \r_lcl_reg_n_0_[3]\,
      I3 => \rsh_reg_n_0_[0]\,
      I4 => \r_lcl_reg_n_0_[5]\,
      O => \toVideoinAXIS_tdata_sig[21]_i_19_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44400040"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[9]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \g1_lcl_reg_n_0_[9]\,
      O => \toVideoinAXIS_tdata_sig[21]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[1]\,
      I1 => gsh(1),
      I2 => \g1_lcl_reg_n_0_[3]\,
      I3 => gsh(0),
      I4 => \g1_lcl_reg_n_0_[5]\,
      O => \toVideoinAXIS_tdata_sig[21]_i_20_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \stateSynth_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[21]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \wht_reg_n_0_[9]\,
      I1 => whtNotBlk,
      I2 => \blk_reg_n_0_[9]\,
      O => \toVideoinAXIS_tdata_sig[21]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08AA080A08A00800"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_6_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \toVideoinAXIS_tdata_sig[21]_i_7_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[21]_i_8_n_0\,
      O => \toVideoinAXIS_tdata_sig[21]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \ixTExp_sig_reg_n_0_[0]\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_9_n_0\,
      O => \toVideoinAXIS_tdata_sig[21]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[21]_i_10_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig_reg[21]_i_11_n_0\,
      O => \toVideoinAXIS_tdata_sig[21]_i_7_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg[21]_i_12_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig_reg[21]_i_13_n_0\,
      O => \toVideoinAXIS_tdata_sig[21]_i_8_n_0\
    );
\toVideoinAXIS_tdata_sig[21]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF7F7FFFFF7F7F"
    )
        port map (
      I0 => \rsh_reg_n_0_[0]\,
      I1 => \rsh_reg_n_0_[1]\,
      I2 => \r_lcl_reg_n_0_[11]\,
      I3 => \toVideoinAXIS_tdata_sig[14]_i_8_n_0\,
      I4 => \row_reg_n_0_[0]\,
      I5 => \g1_lcl_reg_n_0_[11]\,
      O => \toVideoinAXIS_tdata_sig[21]_i_9_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[22]_i_2_n_0\,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \blk_reg_n_0_[10]\,
      I3 => whtNotBlk,
      I4 => \wht_reg_n_0_[10]\,
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[22]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF0F0F0F8F8F8F8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[22]_i_18_n_0\,
      I1 => \rsh_reg_n_0_[1]\,
      I2 => \toVideoinAXIS_tdata_sig[22]_i_19_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[22]_i_20_n_0\,
      I4 => gsh(1),
      I5 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[22]_i_10_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[3]\,
      I1 => \rsh_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[5]\,
      O => \toVideoinAXIS_tdata_sig[22]_i_11_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00B8000000B800"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[7]\,
      I1 => gsh(0),
      I2 => \g1_lcl_reg_n_0_[9]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => gsh(1),
      I5 => \toVideoinAXIS_tdata_sig[22]_i_21_n_0\,
      O => \toVideoinAXIS_tdata_sig[22]_i_12_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[0]\,
      I1 => \rsh_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[2]\,
      O => \toVideoinAXIS_tdata_sig[22]_i_13_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00B8000000B800"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[4]\,
      I1 => gsh(0),
      I2 => \g1_lcl_reg_n_0_[6]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => gsh(1),
      I5 => \toVideoinAXIS_tdata_sig[18]_i_9_n_0\,
      O => \toVideoinAXIS_tdata_sig[22]_i_14_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \rsh_reg_n_0_[1]\,
      I1 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[22]_i_15_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \row_reg_n_0_[0]\,
      I1 => gsh(1),
      O => \toVideoinAXIS_tdata_sig[22]_i_16_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[9]\,
      I1 => gsh(0),
      I2 => \g1_lcl_reg_n_0_[11]\,
      O => \toVideoinAXIS_tdata_sig[22]_i_17_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[6]\,
      I1 => \rsh_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[8]\,
      O => \toVideoinAXIS_tdata_sig[22]_i_18_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"444444440F000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[23]_i_21_n_0\,
      I1 => \g1_lcl_reg_n_0_[10]\,
      I2 => \rsh_reg_n_0_[1]\,
      I3 => \rsh_reg_n_0_[0]\,
      I4 => \r_lcl_reg_n_0_[10]\,
      I5 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[22]_i_19_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCFCDDCCCCCCCC"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[22]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[22]_i_4_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[22]_i_5_n_0\,
      I3 => \ixTExp_sig_reg_n_0_[1]\,
      I4 => \ixTExp_sig_reg_n_0_[2]\,
      I5 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      O => \toVideoinAXIS_tdata_sig[22]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_20\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[6]\,
      I1 => gsh(0),
      I2 => \g1_lcl_reg_n_0_[8]\,
      O => \toVideoinAXIS_tdata_sig[22]_i_20_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[3]\,
      I1 => gsh(0),
      I2 => \g1_lcl_reg_n_0_[5]\,
      O => \toVideoinAXIS_tdata_sig[22]_i_21_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[22]_i_6_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[22]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[22]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCA00FF00CA0000"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[10]\,
      I1 => \g1_lcl_reg_n_0_[10]\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \stateSynth_reg_n_0_[1]\,
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => \toVideoinAXIS_tdata_sig[22]_i_8_n_0\,
      O => \toVideoinAXIS_tdata_sig[22]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[22]_i_9_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[22]_i_10_n_0\,
      O => \toVideoinAXIS_tdata_sig[22]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CDEF"
    )
        port map (
      I0 => \rsh_reg_n_0_[1]\,
      I1 => \row_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[23]_i_17_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[22]_i_11_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[22]_i_12_n_0\,
      O => \toVideoinAXIS_tdata_sig[22]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F1FD"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[23]_i_12_n_0\,
      I1 => \rsh_reg_n_0_[1]\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \toVideoinAXIS_tdata_sig[22]_i_13_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[22]_i_14_n_0\,
      O => \toVideoinAXIS_tdata_sig[22]_i_7_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \wht_reg_n_0_[10]\,
      I1 => whtNotBlk,
      I2 => \blk_reg_n_0_[10]\,
      O => \toVideoinAXIS_tdata_sig[22]_i_8_n_0\
    );
\toVideoinAXIS_tdata_sig[22]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FF000047FF47FF"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[9]\,
      I1 => \rsh_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[11]\,
      I3 => \toVideoinAXIS_tdata_sig[22]_i_15_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[22]_i_16_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[22]_i_17_n_0\,
      O => \toVideoinAXIS_tdata_sig[22]_i_9_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8008"
    )
        port map (
      I0 => \wht_reg_n_0_[11]\,
      I1 => whtNotBlk,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \stateSynth_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[23]_i_10_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[8]\,
      I1 => \rsh_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[10]\,
      O => \toVideoinAXIS_tdata_sig[23]_i_11_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[4]\,
      I1 => \rsh_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[6]\,
      O => \toVideoinAXIS_tdata_sig[23]_i_12_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00B8000000B800"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[8]\,
      I1 => gsh(0),
      I2 => \g1_lcl_reg_n_0_[10]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => gsh(1),
      I5 => \toVideoinAXIS_tdata_sig[23]_i_20_n_0\,
      O => \toVideoinAXIS_tdata_sig[23]_i_13_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[5]\,
      I1 => \rsh_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[7]\,
      O => \toVideoinAXIS_tdata_sig[23]_i_14_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[1]\,
      I1 => \rsh_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[3]\,
      O => \toVideoinAXIS_tdata_sig[23]_i_15_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00B8000000B800"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[5]\,
      I1 => gsh(0),
      I2 => \g1_lcl_reg_n_0_[7]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => gsh(1),
      I5 => \toVideoinAXIS_tdata_sig[19]_i_11_n_0\,
      O => \toVideoinAXIS_tdata_sig[23]_i_16_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \r_lcl_reg_n_0_[7]\,
      I1 => \rsh_reg_n_0_[0]\,
      I2 => \r_lcl_reg_n_0_[9]\,
      O => \toVideoinAXIS_tdata_sig[23]_i_17_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"444444440F000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[23]_i_21_n_0\,
      I1 => \g1_lcl_reg_n_0_[11]\,
      I2 => \rsh_reg_n_0_[1]\,
      I3 => \rsh_reg_n_0_[0]\,
      I4 => \r_lcl_reg_n_0_[11]\,
      I5 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[23]_i_18_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[7]\,
      I1 => gsh(0),
      I2 => \g1_lcl_reg_n_0_[9]\,
      O => \toVideoinAXIS_tdata_sig[23]_i_19_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A2020202"
    )
        port map (
      I0 => \stateSynth[2]_i_7_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[23]_i_3_n_0\,
      I2 => \^statesynth_reg[2]_0\(0),
      I3 => whtNotBlk,
      I4 => \wht_reg_n_0_[11]\,
      O => \toVideoinAXIS_tdata_sig[23]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_20\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g1_lcl_reg_n_0_[4]\,
      I1 => gsh(0),
      I2 => \g1_lcl_reg_n_0_[6]\,
      O => \toVideoinAXIS_tdata_sig[23]_i_20_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => gsh(1),
      I1 => gsh(0),
      O => \toVideoinAXIS_tdata_sig[23]_i_21_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF3AFFFF"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[23]_i_4_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[23]_i_5_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[23]_i_6_n_0\,
      O => \toVideoinAXIS_tdata_sig[23]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[23]_i_7_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[23]_i_8_n_0\,
      O => \toVideoinAXIS_tdata_sig[23]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_7_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[23]_i_9_n_0\,
      O => \toVideoinAXIS_tdata_sig[23]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAEAAAAAEAAAEAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[23]_i_10_n_0\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \r_lcl_reg_n_0_[11]\,
      I4 => \g1_lcl_reg_n_0_[11]\,
      I5 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[23]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CDEF"
    )
        port map (
      I0 => \rsh_reg_n_0_[1]\,
      I1 => \row_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[23]_i_11_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[23]_i_12_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[23]_i_13_n_0\,
      O => \toVideoinAXIS_tdata_sig[23]_i_7_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CDEF"
    )
        port map (
      I0 => \rsh_reg_n_0_[1]\,
      I1 => \row_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[23]_i_14_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[23]_i_15_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[23]_i_16_n_0\,
      O => \toVideoinAXIS_tdata_sig[23]_i_8_n_0\
    );
\toVideoinAXIS_tdata_sig[23]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF0F0F0F8F8F8F8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[23]_i_17_n_0\,
      I1 => \rsh_reg_n_0_[1]\,
      I2 => \toVideoinAXIS_tdata_sig[23]_i_18_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[23]_i_19_n_0\,
      I4 => gsh(1),
      I5 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[23]_i_9_n_0\
    );
\toVideoinAXIS_tdata_sig[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAE00AE00000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[2]_i_2_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[2]_i_3_n_0\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \toVideoinAXIS_tdata_sig[14]_i_5_n_0\,
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[2]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAAAAAAAAAAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[2]_i_4_n_0\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \ixTExp_sig_reg_n_0_[1]\,
      I5 => \toVideoinAXIS_tdata_sig[8]_i_5_n_0\,
      O => \toVideoinAXIS_tdata_sig[2]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5FFF5F3C5FFC5F3"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[8]_i_6_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \toVideoinAXIS_tdata_sig[2]_i_5_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[2]_i_6_n_0\,
      O => \toVideoinAXIS_tdata_sig[2]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0000CFC0AAAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_5_n_0\,
      I1 => \b_lcl_reg_n_0_[2]\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \g0_lcl_reg_n_0_[2]\,
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => \stateSynth_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[2]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7F7F7F7F7F707F7"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[1]\,
      I1 => \toVideoinAXIS_tdata_sig[2]_i_7_n_0\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \b_lcl_reg_n_0_[1]\,
      I4 => \bsh_reg_n_0_[1]\,
      I5 => \bsh_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[2]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0FFF7777FFFF7777"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[10]\,
      I1 => \toVideoinAXIS_tdata_sig[14]_i_8_n_0\,
      I2 => \bsh_reg_n_0_[1]\,
      I3 => \bsh_reg_n_0_[0]\,
      I4 => \row_reg_n_0_[0]\,
      I5 => \b_lcl_reg_n_0_[10]\,
      O => \toVideoinAXIS_tdata_sig[2]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[2]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => gsh(1),
      I1 => gsh(0),
      O => \toVideoinAXIS_tdata_sig[2]_i_7_n_0\
    );
\toVideoinAXIS_tdata_sig[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAE00AE00000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[3]_i_2_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[3]_i_3_n_0\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \toVideoinAXIS_tdata_sig[3]_i_4_n_0\,
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[3]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[3]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[0]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[2]\,
      O => \toVideoinAXIS_tdata_sig[3]_i_10_n_0\
    );
\toVideoinAXIS_tdata_sig[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAAAAAAAAAAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[3]_i_5_n_0\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \ixTExp_sig_reg_n_0_[1]\,
      I5 => \toVideoinAXIS_tdata_sig[9]_i_5_n_0\,
      O => \toVideoinAXIS_tdata_sig[3]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FAFFFAF3CAFFCAF3"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[9]_i_6_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \toVideoinAXIS_tdata_sig[3]_i_6_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[3]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[3]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[3]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \wht_reg_n_0_[3]\,
      I1 => whtNotBlk,
      I2 => \blk_reg_n_0_[3]\,
      O => \toVideoinAXIS_tdata_sig[3]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0000CFC0AAAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[3]_i_4_n_0\,
      I1 => \b_lcl_reg_n_0_[3]\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \g0_lcl_reg_n_0_[3]\,
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => \stateSynth_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[3]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FF000047FF47FF"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[0]\,
      I1 => gsh(0),
      I2 => \g0_lcl_reg_n_0_[2]\,
      I3 => \toVideoinAXIS_tdata_sig[3]_i_8_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[3]_i_9_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[3]_i_10_n_0\,
      O => \toVideoinAXIS_tdata_sig[3]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0FFF7777FFFF7777"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[11]\,
      I1 => \toVideoinAXIS_tdata_sig[14]_i_8_n_0\,
      I2 => \bsh_reg_n_0_[1]\,
      I3 => \bsh_reg_n_0_[0]\,
      I4 => \row_reg_n_0_[0]\,
      I5 => \b_lcl_reg_n_0_[11]\,
      O => \toVideoinAXIS_tdata_sig[3]_i_7_n_0\
    );
\toVideoinAXIS_tdata_sig[3]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \row_reg_n_0_[0]\,
      I1 => gsh(1),
      O => \toVideoinAXIS_tdata_sig[3]_i_8_n_0\
    );
\toVideoinAXIS_tdata_sig[3]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \bsh_reg_n_0_[1]\,
      I1 => \row_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[3]_i_9_n_0\
    );
\toVideoinAXIS_tdata_sig[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[4]_i_2_n_0\,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \blk_reg_n_0_[4]\,
      I3 => whtNotBlk,
      I4 => \wht_reg_n_0_[4]\,
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[4]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF080000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[10]_i_5_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[2]\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \toVideoinAXIS_tdata_sig[4]_i_3_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[4]_i_4_n_0\,
      O => \toVideoinAXIS_tdata_sig[4]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AA00CF00AA0003"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[10]_i_3_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[4]_i_5_n_0\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \ixTExp_sig_reg_n_0_[1]\,
      I5 => \toVideoinAXIS_tdata_sig[7]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[4]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0000CFC0AAAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[16]_i_3_n_0\,
      I1 => \b_lcl_reg_n_0_[4]\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \g0_lcl_reg_n_0_[4]\,
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => \stateSynth_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[4]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7F7F7F7F7F707F7"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[0]\,
      I1 => \toVideoinAXIS_tdata_sig[2]_i_7_n_0\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \b_lcl_reg_n_0_[0]\,
      I4 => \bsh_reg_n_0_[1]\,
      I5 => \bsh_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[4]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[5]_i_2_n_0\,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \blk_reg_n_0_[5]\,
      I3 => whtNotBlk,
      I4 => \wht_reg_n_0_[5]\,
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[5]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CECCCCCCCEFCCCCC"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[11]_i_4_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[5]_i_3_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[11]_i_3_n_0\,
      O => \toVideoinAXIS_tdata_sig[5]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFB0001000"
    )
        port map (
      I0 => \ixTExp_sig_reg_n_0_[0]\,
      I1 => \toVideoinAXIS_tdata_sig[2]_i_5_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[5]_i_4_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I4 => \toVideoinAXIS_tdata_sig_reg[8]_i_7_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[5]_i_5_n_0\,
      O => \toVideoinAXIS_tdata_sig[5]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[5]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \ixTExp_sig_reg_n_0_[1]\,
      I1 => \ixTExp_sig_reg_n_0_[2]\,
      O => \toVideoinAXIS_tdata_sig[5]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0000CFC0AAAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[17]_i_4_n_0\,
      I1 => \b_lcl_reg_n_0_[5]\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \g0_lcl_reg_n_0_[5]\,
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => \stateSynth_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[5]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEE222E200000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[6]_i_2_n_0\,
      I1 => \^statesynth_reg[2]_0\(0),
      I2 => \blk_reg_n_0_[6]\,
      I3 => whtNotBlk,
      I4 => \wht_reg_n_0_[6]\,
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[6]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAEAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[6]_i_3_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[1]\,
      I2 => \ixTExp_sig_reg_n_0_[2]\,
      I3 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[6]_i_4_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[6]_i_5_n_0\,
      O => \toVideoinAXIS_tdata_sig[6]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000004000004440"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[0]\,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \toVideoinAXIS_tdata_sig[0]_i_4_n_0\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \ixTExp_sig_reg_n_0_[1]\,
      I5 => \toVideoinAXIS_tdata_sig[0]_i_5_n_0\,
      O => \toVideoinAXIS_tdata_sig[6]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[6]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[9]_i_10_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[9]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[6]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0000CFC0AAAA"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[18]_i_3_n_0\,
      I1 => \b_lcl_reg_n_0_[6]\,
      I2 => \row_reg_n_0_[0]\,
      I3 => \g0_lcl_reg_n_0_[6]\,
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => \stateSynth_reg_n_0_[1]\,
      O => \toVideoinAXIS_tdata_sig[6]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCFFF400000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[21]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[19]_i_3_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[7]_i_2_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[7]_i_3_n_0\,
      I4 => \^statesynth_reg[2]_0\(0),
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[7]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44400040"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \g0_lcl_reg_n_0_[7]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \b_lcl_reg_n_0_[7]\,
      O => \toVideoinAXIS_tdata_sig[7]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02AA02A0020A0200"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[7]_i_4_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \toVideoinAXIS_tdata_sig[7]_i_5_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[7]_i_6_n_0\,
      O => \toVideoinAXIS_tdata_sig[7]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \ixTExp_sig_reg_n_0_[0]\,
      I1 => \toVideoinAXIS_tdata_sig[10]_i_8_n_0\,
      O => \toVideoinAXIS_tdata_sig[7]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[7]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig_reg[10]_i_7_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[7]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[7]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[7]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[10]_i_9_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig_reg[10]_i_6_n_0\,
      O => \toVideoinAXIS_tdata_sig[7]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B800FFFFB800B800"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[1]\,
      I1 => gsh(0),
      I2 => \g0_lcl_reg_n_0_[3]\,
      I3 => \toVideoinAXIS_tdata_sig[3]_i_8_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[3]_i_9_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[7]_i_8_n_0\,
      O => \toVideoinAXIS_tdata_sig[7]_i_7_n_0\
    );
\toVideoinAXIS_tdata_sig[7]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[1]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[3]\,
      O => \toVideoinAXIS_tdata_sig[7]_i_8_n_0\
    );
\toVideoinAXIS_tdata_sig[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCFFF400000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[21]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[20]_i_3_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[8]_i_2_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[8]_i_3_n_0\,
      I4 => \^statesynth_reg[2]_0\(0),
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[8]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44400040"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \g0_lcl_reg_n_0_[8]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \b_lcl_reg_n_0_[8]\,
      O => \toVideoinAXIS_tdata_sig[8]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02AA02A0020A0200"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[8]_i_4_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \toVideoinAXIS_tdata_sig[8]_i_5_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[8]_i_6_n_0\,
      O => \toVideoinAXIS_tdata_sig[8]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[8]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \ixTExp_sig_reg_n_0_[0]\,
      I1 => \toVideoinAXIS_tdata_sig[2]_i_6_n_0\,
      O => \toVideoinAXIS_tdata_sig[8]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[8]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[11]_i_7_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig_reg[8]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[8]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[8]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A3"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[11]_i_8_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[11]_i_6_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[0]\,
      O => \toVideoinAXIS_tdata_sig[8]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[8]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[0]\,
      I1 => gsh(1),
      I2 => \g0_lcl_reg_n_0_[2]\,
      I3 => gsh(0),
      I4 => \g0_lcl_reg_n_0_[4]\,
      O => \toVideoinAXIS_tdata_sig[8]_i_8_n_0\
    );
\toVideoinAXIS_tdata_sig[8]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[0]\,
      I1 => \bsh_reg_n_0_[1]\,
      I2 => \b_lcl_reg_n_0_[2]\,
      I3 => \bsh_reg_n_0_[0]\,
      I4 => \b_lcl_reg_n_0_[4]\,
      O => \toVideoinAXIS_tdata_sig[8]_i_9_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCCFFF400000000"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[21]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_4_n_0\,
      I2 => \toVideoinAXIS_tdata_sig[9]_i_2_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[9]_i_3_n_0\,
      I4 => \^statesynth_reg[2]_0\(0),
      I5 => \stateSynth[2]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[9]_i_1_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CDEF"
    )
        port map (
      I0 => gsh(1),
      I1 => \row_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[9]_i_16_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[11]_i_12_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[9]_i_17_n_0\,
      O => \toVideoinAXIS_tdata_sig[9]_i_10_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[2]\,
      I1 => gsh(0),
      I2 => \g0_lcl_reg_n_0_[4]\,
      O => \toVideoinAXIS_tdata_sig[9]_i_11_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00B8000000B800"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[6]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[8]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \bsh_reg_n_0_[1]\,
      I5 => \toVideoinAXIS_tdata_sig[9]_i_18_n_0\,
      O => \toVideoinAXIS_tdata_sig[9]_i_12_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[1]\,
      I1 => gsh(1),
      I2 => \g0_lcl_reg_n_0_[3]\,
      I3 => gsh(0),
      I4 => \g0_lcl_reg_n_0_[5]\,
      O => \toVideoinAXIS_tdata_sig[9]_i_13_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[1]\,
      I1 => \bsh_reg_n_0_[1]\,
      I2 => \b_lcl_reg_n_0_[3]\,
      I3 => \bsh_reg_n_0_[0]\,
      I4 => \b_lcl_reg_n_0_[5]\,
      O => \toVideoinAXIS_tdata_sig[9]_i_14_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[8]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[10]\,
      O => \toVideoinAXIS_tdata_sig[9]_i_15_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[9]\,
      I1 => gsh(0),
      I2 => \g0_lcl_reg_n_0_[11]\,
      O => \toVideoinAXIS_tdata_sig[9]_i_16_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00B8000000B800"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[9]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[11]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \bsh_reg_n_0_[1]\,
      I5 => \toVideoinAXIS_tdata_sig[9]_i_19_n_0\,
      O => \toVideoinAXIS_tdata_sig[9]_i_17_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[2]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[4]\,
      O => \toVideoinAXIS_tdata_sig[9]_i_18_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \b_lcl_reg_n_0_[5]\,
      I1 => \bsh_reg_n_0_[0]\,
      I2 => \b_lcl_reg_n_0_[7]\,
      O => \toVideoinAXIS_tdata_sig[9]_i_19_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44400040"
    )
        port map (
      I0 => \stateSynth_reg_n_0_[1]\,
      I1 => \stateSynth_reg_n_0_[0]\,
      I2 => \g0_lcl_reg_n_0_[9]\,
      I3 => \row_reg_n_0_[0]\,
      I4 => \b_lcl_reg_n_0_[9]\,
      O => \toVideoinAXIS_tdata_sig[9]_i_2_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"020A020002AA02A0"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[14]_i_3_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[9]_i_4_n_0\,
      I2 => \ixTExp_sig_reg_n_0_[1]\,
      I3 => \ixTExp_sig_reg_n_0_[2]\,
      I4 => \toVideoinAXIS_tdata_sig[9]_i_5_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[9]_i_6_n_0\,
      O => \toVideoinAXIS_tdata_sig[9]_i_3_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \ixTExp_sig_reg_n_0_[0]\,
      I1 => \toVideoinAXIS_tdata_sig[3]_i_7_n_0\,
      O => \toVideoinAXIS_tdata_sig[9]_i_4_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[9]_i_7_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig_reg[9]_i_8_n_0\,
      O => \toVideoinAXIS_tdata_sig[9]_i_5_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \toVideoinAXIS_tdata_sig[9]_i_9_n_0\,
      I1 => \ixTExp_sig_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[9]_i_10_n_0\,
      O => \toVideoinAXIS_tdata_sig[9]_i_6_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CDEF"
    )
        port map (
      I0 => gsh(1),
      I1 => \row_reg_n_0_[0]\,
      I2 => \toVideoinAXIS_tdata_sig[10]_i_17_n_0\,
      I3 => \toVideoinAXIS_tdata_sig[9]_i_11_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[9]_i_12_n_0\,
      O => \toVideoinAXIS_tdata_sig[9]_i_7_n_0\
    );
\toVideoinAXIS_tdata_sig[9]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"47FF000047FF47FF"
    )
        port map (
      I0 => \g0_lcl_reg_n_0_[8]\,
      I1 => gsh(0),
      I2 => \g0_lcl_reg_n_0_[10]\,
      I3 => \toVideoinAXIS_tdata_sig[10]_i_14_n_0\,
      I4 => \toVideoinAXIS_tdata_sig[10]_i_15_n_0\,
      I5 => \toVideoinAXIS_tdata_sig[9]_i_15_n_0\,
      O => \toVideoinAXIS_tdata_sig[9]_i_9_n_0\
    );
\toVideoinAXIS_tdata_sig_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[0]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[0]\
    );
\toVideoinAXIS_tdata_sig_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[10]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[10]\
    );
\toVideoinAXIS_tdata_sig_reg[10]_i_6\: unisim.vcomponents.MUXF7
     port map (
      I0 => \toVideoinAXIS_tdata_sig[10]_i_10_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[10]_i_11_n_0\,
      O => \toVideoinAXIS_tdata_sig_reg[10]_i_6_n_0\,
      S => \row_reg_n_0_[0]\
    );
\toVideoinAXIS_tdata_sig_reg[10]_i_7\: unisim.vcomponents.MUXF7
     port map (
      I0 => \toVideoinAXIS_tdata_sig[10]_i_12_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[10]_i_13_n_0\,
      O => \toVideoinAXIS_tdata_sig_reg[10]_i_7_n_0\,
      S => \row_reg_n_0_[0]\
    );
\toVideoinAXIS_tdata_sig_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[11]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[11]\
    );
\toVideoinAXIS_tdata_sig_reg[12]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[12]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[12]\
    );
\toVideoinAXIS_tdata_sig_reg[13]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[13]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[13]\
    );
\toVideoinAXIS_tdata_sig_reg[14]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[14]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[14]\
    );
\toVideoinAXIS_tdata_sig_reg[15]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[15]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[15]\
    );
\toVideoinAXIS_tdata_sig_reg[16]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[16]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[16]\
    );
\toVideoinAXIS_tdata_sig_reg[17]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[17]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[17]\
    );
\toVideoinAXIS_tdata_sig_reg[17]_i_7\: unisim.vcomponents.MUXF7
     port map (
      I0 => \toVideoinAXIS_tdata_sig[17]_i_11_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[17]_i_12_n_0\,
      O => \toVideoinAXIS_tdata_sig_reg[17]_i_7_n_0\,
      S => \row_reg_n_0_[0]\
    );
\toVideoinAXIS_tdata_sig_reg[18]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[18]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[18]\
    );
\toVideoinAXIS_tdata_sig_reg[19]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[19]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[19]\
    );
\toVideoinAXIS_tdata_sig_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[1]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[1]\
    );
\toVideoinAXIS_tdata_sig_reg[20]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[20]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[20]\
    );
\toVideoinAXIS_tdata_sig_reg[21]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[21]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[21]\
    );
\toVideoinAXIS_tdata_sig_reg[21]_i_11\: unisim.vcomponents.MUXF7
     port map (
      I0 => \toVideoinAXIS_tdata_sig[21]_i_15_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_16_n_0\,
      O => \toVideoinAXIS_tdata_sig_reg[21]_i_11_n_0\,
      S => \row_reg_n_0_[0]\
    );
\toVideoinAXIS_tdata_sig_reg[21]_i_12\: unisim.vcomponents.MUXF7
     port map (
      I0 => \toVideoinAXIS_tdata_sig[21]_i_17_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_18_n_0\,
      O => \toVideoinAXIS_tdata_sig_reg[21]_i_12_n_0\,
      S => \row_reg_n_0_[0]\
    );
\toVideoinAXIS_tdata_sig_reg[21]_i_13\: unisim.vcomponents.MUXF7
     port map (
      I0 => \toVideoinAXIS_tdata_sig[21]_i_19_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[21]_i_20_n_0\,
      O => \toVideoinAXIS_tdata_sig_reg[21]_i_13_n_0\,
      S => \row_reg_n_0_[0]\
    );
\toVideoinAXIS_tdata_sig_reg[22]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[22]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[22]\
    );
\toVideoinAXIS_tdata_sig_reg[23]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[23]_i_2_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[23]\
    );
\toVideoinAXIS_tdata_sig_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[2]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[2]\
    );
\toVideoinAXIS_tdata_sig_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[3]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[3]\
    );
\toVideoinAXIS_tdata_sig_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[4]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[4]\
    );
\toVideoinAXIS_tdata_sig_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[5]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[5]\
    );
\toVideoinAXIS_tdata_sig_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[6]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[6]\
    );
\toVideoinAXIS_tdata_sig_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[7]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[7]\
    );
\toVideoinAXIS_tdata_sig_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[8]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[8]\
    );
\toVideoinAXIS_tdata_sig_reg[8]_i_7\: unisim.vcomponents.MUXF7
     port map (
      I0 => \toVideoinAXIS_tdata_sig[8]_i_8_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[8]_i_9_n_0\,
      O => \toVideoinAXIS_tdata_sig_reg[8]_i_7_n_0\,
      S => \row_reg_n_0_[0]\
    );
\toVideoinAXIS_tdata_sig_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => \toVideoinAXIS_tdata_sig_reg[23]_0\(0),
      CLR => sda_sig_reg,
      D => \toVideoinAXIS_tdata_sig[9]_i_1_n_0\,
      Q => \toVideoinAXIS_tdata_sig_reg_n_0_[9]\
    );
\toVideoinAXIS_tdata_sig_reg[9]_i_8\: unisim.vcomponents.MUXF7
     port map (
      I0 => \toVideoinAXIS_tdata_sig[9]_i_13_n_0\,
      I1 => \toVideoinAXIS_tdata_sig[9]_i_14_n_0\,
      O => \toVideoinAXIS_tdata_sig_reg[9]_i_8_n_0\,
      S => \row_reg_n_0_[0]\
    );
toVideoinAXIS_tvalid_sig_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8A800A8"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => toVideoinAXIS_tvalid_sig,
      O => toVideoinAXIS_tvalid_sig_i_1_n_0
    );
toVideoinAXIS_tvalid_sig_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg,
      D => toVideoinAXIS_tvalid_sig_i_1_n_0,
      Q => toVideoinAXIS_tvalid_sig
    );
whtNotBlk0_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F80"
    )
        port map (
      I0 => \blk[10]_i_5_n_0\,
      I1 => \row[2]_i_2_n_0\,
      I2 => \rowchk[3]_i_1_n_0\,
      I3 => whtNotBlk0_reg_n_0,
      O => whtNotBlk0_i_1_n_0
    );
whtNotBlk0_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg,
      D => whtNotBlk0_i_1_n_0,
      Q => whtNotBlk0_reg_n_0
    );
whtNotBlk_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFAAAFAFB0BBB0B0"
    )
        port map (
      I0 => whtNotBlk0,
      I1 => \colchk[3]_i_4_n_0\,
      I2 => \rowchk[3]_i_1_n_0\,
      I3 => whtNotBlk_i_3_n_0,
      I4 => \colchk[3]_i_3_n_0\,
      I5 => whtNotBlk,
      O => whtNotBlk_i_1_n_0
    );
whtNotBlk_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFF040000000000"
    )
        port map (
      I0 => \rowchk_reg_n_0_[2]\,
      I1 => \rowchk_reg_n_0_[3]\,
      I2 => \rowchk_reg_n_0_[1]\,
      I3 => \rowchk_reg_n_0_[0]\,
      I4 => whtNotBlk0_reg_n_0,
      I5 => \row[2]_i_2_n_0\,
      O => whtNotBlk0
    );
whtNotBlk_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => colchk(3),
      I1 => colchk(0),
      I2 => colchk(2),
      I3 => colchk(1),
      O => whtNotBlk_i_3_n_0
    );
whtNotBlk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg,
      D => whtNotBlk_i_1_n_0,
      Q => whtNotBlk
    );
\wht[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \wht[10]_i_2_n_0\,
      I1 => \wht_reg_n_0_[1]\,
      I2 => blk1_out(10),
      O => \wht[0]_i_1_n_0\
    );
\wht[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA8AAAAAAAAAA"
    )
        port map (
      I0 => \wht[10]_i_2_n_0\,
      I1 => \blk_reg_n_0_[0]\,
      I2 => \stateSynth_reg_n_0_[1]\,
      I3 => \^statesynth_reg[2]_0\(0),
      I4 => \stateSynth_reg_n_0_[0]\,
      I5 => rng,
      O => \wht[10]_i_1_n_0\
    );
\wht[10]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF57"
    )
        port map (
      I0 => rng,
      I1 => \stateSynth_reg_n_0_[1]\,
      I2 => \stateSynth_reg_n_0_[0]\,
      I3 => \ixTExp_sig[2]_i_3_n_0\,
      O => \wht[10]_i_2_n_0\
    );
\wht[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBF88888880"
    )
        port map (
      I0 => \wht[10]_i_2_n_0\,
      I1 => wht(10),
      I2 => \blk_reg_n_0_[0]\,
      I3 => \blk[10]_i_6_n_0\,
      I4 => \blk[10]_i_4_n_0\,
      I5 => \wht_reg_n_0_[11]\,
      O => \wht[11]_i_1_n_0\
    );
\wht[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \wht[10]_i_2_n_0\,
      I1 => \wht_reg_n_0_[2]\,
      I2 => blk1_out(10),
      O => \wht[1]_i_1_n_0\
    );
\wht[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \wht[10]_i_2_n_0\,
      I1 => \wht_reg_n_0_[3]\,
      I2 => blk1_out(10),
      O => \wht[2]_i_1_n_0\
    );
\wht[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \wht[10]_i_2_n_0\,
      I1 => \wht_reg_n_0_[4]\,
      I2 => blk1_out(10),
      O => \wht[3]_i_1_n_0\
    );
\wht[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \wht[10]_i_2_n_0\,
      I1 => \wht_reg_n_0_[5]\,
      I2 => blk1_out(10),
      O => \wht[4]_i_1_n_0\
    );
\wht[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \wht[10]_i_2_n_0\,
      I1 => \wht_reg_n_0_[6]\,
      I2 => blk1_out(10),
      O => \wht[5]_i_1_n_0\
    );
\wht[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \wht[10]_i_2_n_0\,
      I1 => \wht_reg_n_0_[7]\,
      I2 => blk1_out(10),
      O => \wht[6]_i_1_n_0\
    );
\wht[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \wht[10]_i_2_n_0\,
      I1 => \wht_reg_n_0_[8]\,
      I2 => blk1_out(10),
      O => \wht[7]_i_1_n_0\
    );
\wht[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \wht[10]_i_2_n_0\,
      I1 => \wht_reg_n_0_[9]\,
      I2 => blk1_out(10),
      O => \wht[8]_i_1_n_0\
    );
\wht[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \wht[10]_i_2_n_0\,
      I1 => \wht_reg_n_0_[10]\,
      I2 => blk1_out(10),
      O => \wht[9]_i_1_n_0\
    );
\wht_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => \wht[0]_i_1_n_0\,
      Q => \wht_reg_n_0_[0]\
    );
\wht_reg[10]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => \wht[10]_i_1_n_0\,
      Q => \wht_reg_n_0_[10]\
    );
\wht_reg[11]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => sda_sig_reg,
      D => \wht[11]_i_1_n_0\,
      Q => \wht_reg_n_0_[11]\
    );
\wht_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => \wht[1]_i_1_n_0\,
      Q => \wht_reg_n_0_[1]\
    );
\wht_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => \wht[2]_i_1_n_0\,
      Q => \wht_reg_n_0_[2]\
    );
\wht_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => \wht[3]_i_1_n_0\,
      Q => \wht_reg_n_0_[3]\
    );
\wht_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => \wht[4]_i_1_n_0\,
      Q => \wht_reg_n_0_[4]\
    );
\wht_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => \wht[5]_i_1_n_0\,
      Q => \wht_reg_n_0_[5]\
    );
\wht_reg[6]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => \wht[6]_i_1_n_0\,
      Q => \wht_reg_n_0_[6]\
    );
\wht_reg[7]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => \wht[7]_i_1_n_0\,
      Q => \wht_reg_n_0_[7]\
    );
\wht_reg[8]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => \wht[8]_i_1_n_0\,
      Q => \wht_reg_n_0_[8]\
    );
\wht_reg[9]\: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => wht(10),
      CLR => sda_sig_reg,
      D => \wht[9]_i_1_n_0\,
      Q => \wht_reg_n_0_[9]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0_Vsp_core is
  port (
    rgb0_r : out STD_LOGIC;
    rgb0_g : out STD_LOGIC;
    rgb0_b : out STD_LOGIC;
    vsync : out STD_LOGIC;
    rgbToManyAXIS_tlast_sig_reg : out STD_LOGIC;
    ddrAXI_bready : out STD_LOGIC;
    ddrAXI_wlast : out STD_LOGIC;
    ddrAXI_wvalid : out STD_LOGIC;
    nslp : out STD_LOGIC;
    dir : out STD_LOGIC;
    step : out STD_LOGIC;
    apuAXIL_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    rpuAXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m0z : out STD_LOGIC;
    m0 : out STD_LOGIC;
    camifSetCoreregVal : out STD_LOGIC_VECTOR ( 8 downto 0 );
    S : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ddrAXI_rready : out STD_LOGIC;
    ddrAXI_araddr : out STD_LOGIC_VECTOR ( 20 downto 0 );
    probe : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddrAXI_arvalid : out STD_LOGIC;
    ddrAXI_awvalid : out STD_LOGIC;
    ddrAXI_awaddr : out STD_LOGIC_VECTOR ( 20 downto 0 );
    ddrAXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    rpuAXIL_wready : out STD_LOGIC;
    rpuAXIL_awready : out STD_LOGIC;
    rpuAXIL_arready : out STD_LOGIC;
    rpuAXIL_bvalid : out STD_LOGIC;
    rpuAXIL_rvalid : out STD_LOGIC;
    cs : out STD_LOGIC;
    sclk : out STD_LOGIC;
    mosi : out STD_LOGIC;
    apuAXIL_wready : out STD_LOGIC;
    apuAXIL_awready : out STD_LOGIC;
    apuAXIL_arready : out STD_LOGIC;
    apuAXIL_bvalid : out STD_LOGIC;
    apuAXIL_rvalid : out STD_LOGIC;
    scl : inout STD_LOGIC;
    sda : inout STD_LOGIC;
    aclk : in STD_LOGIC;
    memclk : in STD_LOGIC;
    ddrAXI_rvalid : in STD_LOGIC;
    ddrAXI_rlast : in STD_LOGIC;
    ddrAXI_bvalid : in STD_LOGIC;
    ddrAXI_wready : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 7 downto 0 );
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    csi_clk_n : in STD_LOGIC;
    csi_clk_p : in STD_LOGIC;
    mipi_phy_if_data_n : in STD_LOGIC_VECTOR ( 3 downto 0 );
    mipi_phy_if_data_p : in STD_LOGIC_VECTOR ( 3 downto 0 );
    ddrAXI_arready : in STD_LOGIC;
    ddrAXI_awready : in STD_LOGIC;
    ddrAXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    rpuAXIL_wvalid : in STD_LOGIC;
    rpuAXIL_awvalid : in STD_LOGIC;
    rpuAXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    rpuAXIL_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rpuAXIL_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rpuAXIL_bready : in STD_LOGIC;
    rpuAXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rpuAXIL_arvalid : in STD_LOGIC;
    rpuAXIL_rready : in STD_LOGIC;
    apuAXIL_wvalid : in STD_LOGIC;
    apuAXIL_awvalid : in STD_LOGIC;
    apuAXIL_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    apuAXIL_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    apuAXIL_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    apuAXIL_bready : in STD_LOGIC;
    apuAXIL_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
    apuAXIL_arvalid : in STD_LOGIC;
    apuAXIL_rready : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_Vsp_core_0_0_Vsp_core : entity is "Vsp_core";
end design_1_Vsp_core_0_0_Vsp_core;

architecture STRUCTURE of design_1_Vsp_core_0_0_Vsp_core is
  signal NColRaw : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal NRowRaw : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal TCaptMax : STD_LOGIC;
  signal TCaptMax_3 : STD_LOGIC;
  signal ackCoobufCornerToHostif : STD_LOGIC;
  signal ackFlgbufTraceToHostif : STD_LOGIC;
  signal ackInvAcquire_sig3_out : STD_LOGIC;
  signal ackInvAssign_sig : STD_LOGIC;
  signal ackInvCamifConfig : STD_LOGIC;
  signal ackInvCamifConfigSynth : STD_LOGIC;
  signal ackInvCamifGetCorereg : STD_LOGIC;
  signal ackInvCamifGetReg : STD_LOGIC;
  signal ackInvCamifModReg : STD_LOGIC;
  signal ackInvCamifSetCorereg : STD_LOGIC;
  signal ackInvCamifSetReg : STD_LOGIC;
  signal ackInvConfigSynth_sig : STD_LOGIC;
  signal ackInvConfig_sig : STD_LOGIC;
  signal \ackInvConfig_sig0__6\ : STD_LOGIC;
  signal ackInvCornerAcquire : STD_LOGIC;
  signal ackInvCornerConfig : STD_LOGIC;
  signal ackInvCornerSet : STD_LOGIC;
  signal ackInvCornerUnlock : STD_LOGIC;
  signal ackInvCputrackSelect : STD_LOGIC;
  signal ackInvCputrackSet : STD_LOGIC;
  signal ackInvDecimAcquire : STD_LOGIC;
  signal ackInvDecimConfig : STD_LOGIC;
  signal ackInvDecimSet : STD_LOGIC;
  signal ackInvDecimUnlock : STD_LOGIC;
  signal ackInvDirectorConfig : STD_LOGIC;
  signal ackInvDirectorSet : STD_LOGIC;
  signal ackInvHdrengAssign : STD_LOGIC;
  signal ackInvHdrengSet : STD_LOGIC;
  signal ackInvHshktrackClearMask : STD_LOGIC;
  signal ackInvHshktrackSelect : STD_LOGIC;
  signal ackInvHshktrackSet : STD_LOGIC;
  signal ackInvHshktrackSetMask : STD_LOGIC;
  signal ackInvLaserSet : STD_LOGIC;
  signal ackInvMemtrackClearMask : STD_LOGIC;
  signal ackInvMemtrackSelect : STD_LOGIC;
  signal ackInvMemtrackSet : STD_LOGIC;
  signal ackInvMemtrackSetMask : STD_LOGIC;
  signal ackInvMoveto_sig : STD_LOGIC;
  signal ackInvRotaryConfig : STD_LOGIC;
  signal ackInvRotaryMoveto : STD_LOGIC;
  signal ackInvRotarySet : STD_LOGIC;
  signal ackInvRotaryZero : STD_LOGIC;
  signal ackInvSet_sig : STD_LOGIC;
  signal ackInvSet_sig_1 : STD_LOGIC;
  signal ackInvSet_sig_4 : STD_LOGIC;
  signal ackInvStepmuxSet : STD_LOGIC;
  signal ackInvTkclksrcSetTkst : STD_LOGIC;
  signal ackInvTraceAcquire : STD_LOGIC;
  signal ackInvTraceConfig : STD_LOGIC;
  signal ackInvUnlock_sig : STD_LOGIC;
  signal ackInvUnlock_sig0_in : STD_LOGIC;
  signal ackInvVidtrackSelect : STD_LOGIC;
  signal ackInvVidtrackSet : STD_LOGIC;
  signal ackPvwbufDecimToHostif : STD_LOGIC;
  signal ackRd : STD_LOGIC;
  signal ackSeqbufCputrackToHostif : STD_LOGIC;
  signal ackSeqbufHshktrackToHostif : STD_LOGIC;
  signal ackSeqbufMemtrackToHostif : STD_LOGIC;
  signal ackSeqbufVidtrackToHostif : STD_LOGIC;
  signal ackWr : STD_LOGIC;
  signal aclk_sig : STD_LOGIC;
  signal avllenCoobufCornerToHostif : STD_LOGIC_VECTOR ( 11 to 11 );
  signal avllenFlgbufTraceToHostif : STD_LOGIC_VECTOR ( 15 to 15 );
  signal avllenPvwbufDecimToHostif : STD_LOGIC_VECTOR ( 15 to 15 );
  signal avllenSeqbufCputrackToHostif : STD_LOGIC_VECTOR ( 12 to 12 );
  signal avllenSeqbufHshktrackToHostif : STD_LOGIC_VECTOR ( 12 to 12 );
  signal avllenSeqbufMemtrackToHostif : STD_LOGIC_VECTOR ( 12 to 12 );
  signal avllenSeqbufVidtrackToHostif : STD_LOGIC_VECTOR ( 12 to 12 );
  signal camifGetCoreregVal : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal camifGetRegVal : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \^camifsetcoreregval\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal camifToVideoinAXIS_tdata : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal camifToVideoinAXIS_tlast : STD_LOGIC;
  signal camifToVideoinAXIS_tvalid : STD_LOGIC;
  signal ccwNotCw0 : STD_LOGIC;
  signal ccwNotCw2 : STD_LOGIC_VECTOR ( 14 downto 8 );
  signal ccwNotCw5_in : STD_LOGIC;
  signal col : STD_LOGIC_VECTOR ( 10 downto 3 );
  signal commok : STD_LOGIC;
  signal configCol0 : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal configCol1 : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal configHdrNotFix : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal configSynthNotLive : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal configSynthTFramepad : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal configSynthTLinepad : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal coobufCornerToHostifAXIS_tdata : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal coobufCornerToHostifAXIS_tready : STD_LOGIC;
  signal coobufCornerToHostifAXIS_tvalid : STD_LOGIC;
  signal corecfgAXIL_araddr0_out : STD_LOGIC_VECTOR ( 12 downto 2 );
  signal corecfgAXIL_awaddr0_out : STD_LOGIC_VECTOR ( 12 downto 2 );
  signal cornerGetInfoScoreMax : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal cornerGetInfoScoreMin : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal cornerGetInfoTixVState : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal cornerGetInfoTkst : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal cputrackGetInfoPtr0Seqbuf : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal cputrackGetInfoTCapt : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal cputrackGetInfoTixVState : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^ddraxi_awvalid\ : STD_LOGIC;
  signal \^ddraxi_wvalid\ : STD_LOGIC;
  signal ddrifGetStatsNRdA : STD_LOGIC_VECTOR ( 31 downto 4 );
  signal ddrifGetStatsNRdB : STD_LOGIC_VECTOR ( 31 downto 4 );
  signal ddrifGetStatsNWrA : STD_LOGIC_VECTOR ( 31 downto 4 );
  signal ddrifGetStatsNWrB : STD_LOGIC_VECTOR ( 31 downto 4 );
  signal decimGetInfoTixVState : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal decimGetInfoTkst : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal decimStateStore_dbg : STD_LOGIC_VECTOR ( 5 downto 4 );
  signal decimStateStream_dbg : STD_LOGIC_VECTOR ( 3 to 3 );
  signal dneCoobufCornerToHostif : STD_LOGIC;
  signal dneFlgbufTraceToHostif : STD_LOGIC;
  signal dnePvwbufDecimToHostif : STD_LOGIC;
  signal dneSeqbufCputrackToHostif : STD_LOGIC;
  signal dneSeqbufHshktrackToHostif : STD_LOGIC;
  signal dneSeqbufMemtrackToHostif : STD_LOGIC;
  signal dneSeqbufVidtrackToHostif : STD_LOGIC;
  signal drdParrom : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal dwrAccbuf : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal egrAXIS_tlast : STD_LOGIC;
  signal enAccbuf0 : STD_LOGIC;
  signal enAccbuf1 : STD_LOGIC;
  signal flgbufTraceToHostifAXIS_tdata : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal flgbufTraceToHostifAXIS_tready : STD_LOGIC;
  signal flgbufTraceToHostifAXIS_tvalid : STD_LOGIC;
  signal grayVideoinToManyAXIS_tdata : STD_LOGIC_VECTOR ( 59 downto 4 );
  signal grayVideoinToManyAXIS_tlast : STD_LOGIC;
  signal grayVideoinToManyAXIS_tvalid : STD_LOGIC;
  signal hdrNotFix : STD_LOGIC;
  signal hdrengGetInfoIxMem : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal hdrengGetInfoIxMemAcq : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal hdrengGetInfoTixVState : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal hdrengGetInfoTkst : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal hdrmemAXI_rlast : STD_LOGIC;
  signal hostifStateOp_dbg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal hshktrackGetInfoPtr0Seqbuf : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal hshktrackGetInfoTCapt : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal hshktrackGetInfoTixVState : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal i : STD_LOGIC;
  signal \i[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \i[4]_i_3__0_n_0\ : STD_LOGIC;
  signal i_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal i_reg_8 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \i_reg_n_0_[0]\ : STD_LOGIC;
  signal \i_reg_n_0_[1]\ : STD_LOGIC;
  signal \i_reg_n_0_[2]\ : STD_LOGIC;
  signal \i_reg_n_0_[3]\ : STD_LOGIC;
  signal \i_reg_n_0_[4]\ : STD_LOGIC;
  signal ixTExp : STD_LOGIC_VECTOR ( 2 to 2 );
  signal ixTExp_lcl : STD_LOGIC;
  signal klm : STD_LOGIC_VECTOR ( 0 to 0 );
  signal memtrackGetInfoPtr0Seqbuf : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal memtrackGetInfoTCapt : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal memtrackGetInfoTixVState : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal myCamif_n_126 : STD_LOGIC;
  signal myCamif_n_127 : STD_LOGIC;
  signal myCamif_n_128 : STD_LOGIC;
  signal myCamif_n_129 : STD_LOGIC;
  signal myCamif_n_130 : STD_LOGIC;
  signal myCamif_n_131 : STD_LOGIC;
  signal myCamif_n_132 : STD_LOGIC;
  signal myCamif_n_15 : STD_LOGIC;
  signal myCamif_n_17 : STD_LOGIC;
  signal myCamif_n_18 : STD_LOGIC;
  signal myCamif_n_19 : STD_LOGIC;
  signal myCamif_n_20 : STD_LOGIC;
  signal myCamif_n_22 : STD_LOGIC;
  signal myCamif_n_32 : STD_LOGIC;
  signal myCamif_n_33 : STD_LOGIC;
  signal myCamif_n_34 : STD_LOGIC;
  signal myCamif_n_35 : STD_LOGIC;
  signal myCamif_n_36 : STD_LOGIC;
  signal myCamif_n_37 : STD_LOGIC;
  signal myCamif_n_38 : STD_LOGIC;
  signal myCamif_n_39 : STD_LOGIC;
  signal myCamif_n_40 : STD_LOGIC;
  signal myCamif_n_42 : STD_LOGIC;
  signal myCamif_n_43 : STD_LOGIC;
  signal myCamif_n_44 : STD_LOGIC;
  signal myCamif_n_45 : STD_LOGIC;
  signal myCamif_n_46 : STD_LOGIC;
  signal myCamif_n_47 : STD_LOGIC;
  signal myCamif_n_48 : STD_LOGIC;
  signal myCamif_n_49 : STD_LOGIC;
  signal myCamif_n_50 : STD_LOGIC;
  signal myCamif_n_51 : STD_LOGIC;
  signal myCamif_n_52 : STD_LOGIC;
  signal myCamif_n_53 : STD_LOGIC;
  signal myCamif_n_78 : STD_LOGIC;
  signal myCamif_n_79 : STD_LOGIC;
  signal myCamif_n_80 : STD_LOGIC;
  signal myCamif_n_81 : STD_LOGIC;
  signal myCamif_n_82 : STD_LOGIC;
  signal myCamif_n_83 : STD_LOGIC;
  signal myCamif_n_84 : STD_LOGIC;
  signal myCamif_n_85 : STD_LOGIC;
  signal myCamif_n_86 : STD_LOGIC;
  signal myCamif_n_87 : STD_LOGIC;
  signal myCamif_n_88 : STD_LOGIC;
  signal myCamif_n_89 : STD_LOGIC;
  signal myCamif_n_9 : STD_LOGIC;
  signal myCamif_n_90 : STD_LOGIC;
  signal myCamif_n_91 : STD_LOGIC;
  signal myCamif_n_92 : STD_LOGIC;
  signal myCamif_n_93 : STD_LOGIC;
  signal myCamif_n_94 : STD_LOGIC;
  signal myCamif_n_95 : STD_LOGIC;
  signal myCamif_n_96 : STD_LOGIC;
  signal myCamif_n_97 : STD_LOGIC;
  signal myCorner_n_68 : STD_LOGIC;
  signal myCorner_n_69 : STD_LOGIC;
  signal myCorner_n_78 : STD_LOGIC;
  signal myCorner_n_79 : STD_LOGIC;
  signal myCorner_n_80 : STD_LOGIC;
  signal myCorner_n_81 : STD_LOGIC;
  signal myCorner_n_82 : STD_LOGIC;
  signal myCorner_n_83 : STD_LOGIC;
  signal myCorner_n_84 : STD_LOGIC;
  signal myCorner_n_85 : STD_LOGIC;
  signal myCorner_n_86 : STD_LOGIC;
  signal myCorner_n_87 : STD_LOGIC;
  signal myCorner_n_88 : STD_LOGIC;
  signal myCorner_n_89 : STD_LOGIC;
  signal myCorner_n_90 : STD_LOGIC;
  signal myCorner_n_93 : STD_LOGIC;
  signal myCorner_n_94 : STD_LOGIC;
  signal myCorner_n_95 : STD_LOGIC;
  signal myCorner_n_96 : STD_LOGIC;
  signal myDdrif_n_3 : STD_LOGIC;
  signal myDdrif_n_35 : STD_LOGIC;
  signal myDdrif_n_37 : STD_LOGIC;
  signal myDdrif_n_39 : STD_LOGIC;
  signal myDdrif_n_4 : STD_LOGIC;
  signal myDdrif_n_5 : STD_LOGIC;
  signal myDdrif_n_9 : STD_LOGIC;
  signal myDecim_n_126 : STD_LOGIC;
  signal myDecim_n_127 : STD_LOGIC;
  signal myDecim_n_128 : STD_LOGIC;
  signal myDecim_n_129 : STD_LOGIC;
  signal myDecim_n_130 : STD_LOGIC;
  signal myDecim_n_131 : STD_LOGIC;
  signal myDecim_n_132 : STD_LOGIC;
  signal myDecim_n_133 : STD_LOGIC;
  signal myDecim_n_68 : STD_LOGIC;
  signal myDecim_n_69 : STD_LOGIC;
  signal myDecim_n_79 : STD_LOGIC;
  signal myDecim_n_80 : STD_LOGIC;
  signal myDecim_n_86 : STD_LOGIC;
  signal myDecim_n_87 : STD_LOGIC;
  signal myDecim_n_88 : STD_LOGIC;
  signal myDecim_n_89 : STD_LOGIC;
  signal myDecim_n_92 : STD_LOGIC;
  signal myDecim_n_93 : STD_LOGIC;
  signal myDirector_n_17 : STD_LOGIC;
  signal myDirector_n_18 : STD_LOGIC;
  signal myDirector_n_19 : STD_LOGIC;
  signal myDirector_n_2 : STD_LOGIC;
  signal myDirector_n_20 : STD_LOGIC;
  signal myDirector_n_21 : STD_LOGIC;
  signal myDirector_n_22 : STD_LOGIC;
  signal myDirector_n_23 : STD_LOGIC;
  signal myDirector_n_35 : STD_LOGIC;
  signal myDirector_n_36 : STD_LOGIC;
  signal myDirector_n_37 : STD_LOGIC;
  signal myDirector_n_38 : STD_LOGIC;
  signal myDirector_n_39 : STD_LOGIC;
  signal myDirector_n_4 : STD_LOGIC;
  signal myDirector_n_40 : STD_LOGIC;
  signal myDirector_n_41 : STD_LOGIC;
  signal myDirector_n_42 : STD_LOGIC;
  signal myDirector_n_43 : STD_LOGIC;
  signal myHdreng_n_1 : STD_LOGIC;
  signal myHdreng_n_10 : STD_LOGIC;
  signal myHdreng_n_11 : STD_LOGIC;
  signal myHdreng_n_12 : STD_LOGIC;
  signal myHdreng_n_14 : STD_LOGIC;
  signal myHdreng_n_28 : STD_LOGIC;
  signal myHdreng_n_29 : STD_LOGIC;
  signal myHdreng_n_4 : STD_LOGIC;
  signal myHdreng_n_8 : STD_LOGIC;
  signal myHostif_n_1 : STD_LOGIC;
  signal myHostif_n_10 : STD_LOGIC;
  signal myHostif_n_100 : STD_LOGIC;
  signal myHostif_n_101 : STD_LOGIC;
  signal myHostif_n_102 : STD_LOGIC;
  signal myHostif_n_11 : STD_LOGIC;
  signal myHostif_n_111 : STD_LOGIC;
  signal myHostif_n_112 : STD_LOGIC;
  signal myHostif_n_113 : STD_LOGIC;
  signal myHostif_n_114 : STD_LOGIC;
  signal myHostif_n_115 : STD_LOGIC;
  signal myHostif_n_116 : STD_LOGIC;
  signal myHostif_n_117 : STD_LOGIC;
  signal myHostif_n_118 : STD_LOGIC;
  signal myHostif_n_134 : STD_LOGIC;
  signal myHostif_n_143 : STD_LOGIC;
  signal myHostif_n_147 : STD_LOGIC;
  signal myHostif_n_148 : STD_LOGIC;
  signal myHostif_n_149 : STD_LOGIC;
  signal myHostif_n_15 : STD_LOGIC;
  signal myHostif_n_150 : STD_LOGIC;
  signal myHostif_n_151 : STD_LOGIC;
  signal myHostif_n_152 : STD_LOGIC;
  signal myHostif_n_153 : STD_LOGIC;
  signal myHostif_n_157 : STD_LOGIC;
  signal myHostif_n_158 : STD_LOGIC;
  signal myHostif_n_160 : STD_LOGIC;
  signal myHostif_n_166 : STD_LOGIC;
  signal myHostif_n_17 : STD_LOGIC;
  signal myHostif_n_170 : STD_LOGIC;
  signal myHostif_n_171 : STD_LOGIC;
  signal myHostif_n_172 : STD_LOGIC;
  signal myHostif_n_173 : STD_LOGIC;
  signal myHostif_n_174 : STD_LOGIC;
  signal myHostif_n_175 : STD_LOGIC;
  signal myHostif_n_176 : STD_LOGIC;
  signal myHostif_n_177 : STD_LOGIC;
  signal myHostif_n_178 : STD_LOGIC;
  signal myHostif_n_179 : STD_LOGIC;
  signal myHostif_n_18 : STD_LOGIC;
  signal myHostif_n_180 : STD_LOGIC;
  signal myHostif_n_181 : STD_LOGIC;
  signal myHostif_n_182 : STD_LOGIC;
  signal myHostif_n_183 : STD_LOGIC;
  signal myHostif_n_184 : STD_LOGIC;
  signal myHostif_n_185 : STD_LOGIC;
  signal myHostif_n_186 : STD_LOGIC;
  signal myHostif_n_187 : STD_LOGIC;
  signal myHostif_n_19 : STD_LOGIC;
  signal myHostif_n_205 : STD_LOGIC;
  signal myHostif_n_206 : STD_LOGIC;
  signal myHostif_n_207 : STD_LOGIC;
  signal myHostif_n_208 : STD_LOGIC;
  signal myHostif_n_209 : STD_LOGIC;
  signal myHostif_n_210 : STD_LOGIC;
  signal myHostif_n_211 : STD_LOGIC;
  signal myHostif_n_212 : STD_LOGIC;
  signal myHostif_n_213 : STD_LOGIC;
  signal myHostif_n_214 : STD_LOGIC;
  signal myHostif_n_215 : STD_LOGIC;
  signal myHostif_n_216 : STD_LOGIC;
  signal myHostif_n_217 : STD_LOGIC;
  signal myHostif_n_218 : STD_LOGIC;
  signal myHostif_n_219 : STD_LOGIC;
  signal myHostif_n_220 : STD_LOGIC;
  signal myHostif_n_221 : STD_LOGIC;
  signal myHostif_n_222 : STD_LOGIC;
  signal myHostif_n_223 : STD_LOGIC;
  signal myHostif_n_224 : STD_LOGIC;
  signal myHostif_n_225 : STD_LOGIC;
  signal myHostif_n_226 : STD_LOGIC;
  signal myHostif_n_227 : STD_LOGIC;
  signal myHostif_n_228 : STD_LOGIC;
  signal myHostif_n_229 : STD_LOGIC;
  signal myHostif_n_230 : STD_LOGIC;
  signal myHostif_n_231 : STD_LOGIC;
  signal myHostif_n_232 : STD_LOGIC;
  signal myHostif_n_233 : STD_LOGIC;
  signal myHostif_n_234 : STD_LOGIC;
  signal myHostif_n_235 : STD_LOGIC;
  signal myHostif_n_236 : STD_LOGIC;
  signal myHostif_n_237 : STD_LOGIC;
  signal myHostif_n_254 : STD_LOGIC;
  signal myHostif_n_257 : STD_LOGIC;
  signal myHostif_n_258 : STD_LOGIC;
  signal myHostif_n_259 : STD_LOGIC;
  signal myHostif_n_260 : STD_LOGIC;
  signal myHostif_n_261 : STD_LOGIC;
  signal myHostif_n_262 : STD_LOGIC;
  signal myHostif_n_263 : STD_LOGIC;
  signal myHostif_n_264 : STD_LOGIC;
  signal myHostif_n_265 : STD_LOGIC;
  signal myHostif_n_268 : STD_LOGIC;
  signal myHostif_n_270 : STD_LOGIC;
  signal myHostif_n_276 : STD_LOGIC;
  signal myHostif_n_280 : STD_LOGIC;
  signal myHostif_n_283 : STD_LOGIC;
  signal myHostif_n_284 : STD_LOGIC;
  signal myHostif_n_286 : STD_LOGIC;
  signal myHostif_n_287 : STD_LOGIC;
  signal myHostif_n_289 : STD_LOGIC;
  signal myHostif_n_290 : STD_LOGIC;
  signal myHostif_n_291 : STD_LOGIC;
  signal myHostif_n_292 : STD_LOGIC;
  signal myHostif_n_293 : STD_LOGIC;
  signal myHostif_n_294 : STD_LOGIC;
  signal myHostif_n_295 : STD_LOGIC;
  signal myHostif_n_296 : STD_LOGIC;
  signal myHostif_n_297 : STD_LOGIC;
  signal myHostif_n_298 : STD_LOGIC;
  signal myHostif_n_299 : STD_LOGIC;
  signal myHostif_n_300 : STD_LOGIC;
  signal myHostif_n_301 : STD_LOGIC;
  signal myHostif_n_303 : STD_LOGIC;
  signal myHostif_n_310 : STD_LOGIC;
  signal myHostif_n_311 : STD_LOGIC;
  signal myHostif_n_312 : STD_LOGIC;
  signal myHostif_n_313 : STD_LOGIC;
  signal myHostif_n_314 : STD_LOGIC;
  signal myHostif_n_317 : STD_LOGIC;
  signal myHostif_n_321 : STD_LOGIC;
  signal myHostif_n_323 : STD_LOGIC;
  signal myHostif_n_325 : STD_LOGIC;
  signal myHostif_n_326 : STD_LOGIC;
  signal myHostif_n_328 : STD_LOGIC;
  signal myHostif_n_329 : STD_LOGIC;
  signal myHostif_n_331 : STD_LOGIC;
  signal myHostif_n_332 : STD_LOGIC;
  signal myHostif_n_333 : STD_LOGIC;
  signal myHostif_n_334 : STD_LOGIC;
  signal myHostif_n_335 : STD_LOGIC;
  signal myHostif_n_336 : STD_LOGIC;
  signal myHostif_n_337 : STD_LOGIC;
  signal myHostif_n_338 : STD_LOGIC;
  signal myHostif_n_339 : STD_LOGIC;
  signal myHostif_n_385 : STD_LOGIC;
  signal myHostif_n_387 : STD_LOGIC;
  signal myHostif_n_388 : STD_LOGIC;
  signal myHostif_n_7 : STD_LOGIC;
  signal myHostif_n_91 : STD_LOGIC;
  signal myHostif_n_93 : STD_LOGIC;
  signal myHostif_n_97 : STD_LOGIC;
  signal myHostif_n_98 : STD_LOGIC;
  signal myHostif_n_99 : STD_LOGIC;
  signal myHshktrack_n_107 : STD_LOGIC;
  signal myHshktrack_n_67 : STD_LOGIC;
  signal myHshktrack_n_69 : STD_LOGIC;
  signal myHshktrack_n_70 : STD_LOGIC;
  signal myHshktrack_n_71 : STD_LOGIC;
  signal myHshktrack_n_72 : STD_LOGIC;
  signal myHshktrack_n_73 : STD_LOGIC;
  signal myHshktrack_n_74 : STD_LOGIC;
  signal myMemtrack_n_64 : STD_LOGIC;
  signal myMemtrack_n_65 : STD_LOGIC;
  signal myMemtrack_n_66 : STD_LOGIC;
  signal myMemtrack_n_67 : STD_LOGIC;
  signal myMemtrack_n_68 : STD_LOGIC;
  signal myMemtrack_n_69 : STD_LOGIC;
  signal myMemtrack_n_70 : STD_LOGIC;
  signal myMemtrack_n_71 : STD_LOGIC;
  signal myMemtrack_n_76 : STD_LOGIC;
  signal myMemtrack_n_81 : STD_LOGIC;
  signal myRgbled0_n_10 : STD_LOGIC;
  signal myRgbled0_n_11 : STD_LOGIC;
  signal myRgbled0_n_12 : STD_LOGIC;
  signal myRgbled0_n_7 : STD_LOGIC;
  signal myRgbled0_n_8 : STD_LOGIC;
  signal myRgbled0_n_9 : STD_LOGIC;
  signal myRotary_n_11 : STD_LOGIC;
  signal myRotary_n_12 : STD_LOGIC;
  signal myRotary_n_13 : STD_LOGIC;
  signal myRotary_n_14 : STD_LOGIC;
  signal myRotary_n_34 : STD_LOGIC;
  signal myRotary_n_35 : STD_LOGIC;
  signal myRotary_n_36 : STD_LOGIC;
  signal myRotary_n_4 : STD_LOGIC;
  signal myRpuif_n_37 : STD_LOGIC;
  signal myState_n_1 : STD_LOGIC;
  signal myState_n_10 : STD_LOGIC;
  signal myState_n_11 : STD_LOGIC;
  signal myState_n_12 : STD_LOGIC;
  signal myState_n_13 : STD_LOGIC;
  signal myState_n_2 : STD_LOGIC;
  signal myState_n_3 : STD_LOGIC;
  signal myState_n_4 : STD_LOGIC;
  signal myState_n_5 : STD_LOGIC;
  signal myState_n_6 : STD_LOGIC;
  signal myState_n_9 : STD_LOGIC;
  signal myStepmux_n_1 : STD_LOGIC;
  signal myTrace_n_64 : STD_LOGIC;
  signal myVideoin_n_107 : STD_LOGIC;
  signal myVideoin_n_116 : STD_LOGIC;
  signal myVideoin_n_117 : STD_LOGIC;
  signal myVideoin_n_118 : STD_LOGIC;
  signal myVideoin_n_119 : STD_LOGIC;
  signal myVideoin_n_120 : STD_LOGIC;
  signal myVideoin_n_121 : STD_LOGIC;
  signal myVideoin_n_122 : STD_LOGIC;
  signal myVideoin_n_123 : STD_LOGIC;
  signal myVideoin_n_124 : STD_LOGIC;
  signal myVideoin_n_125 : STD_LOGIC;
  signal myVideoin_n_126 : STD_LOGIC;
  signal myVideoin_n_127 : STD_LOGIC;
  signal myVideoin_n_128 : STD_LOGIC;
  signal myVideoin_n_129 : STD_LOGIC;
  signal myVideoin_n_13 : STD_LOGIC;
  signal myVideoin_n_130 : STD_LOGIC;
  signal myVideoin_n_131 : STD_LOGIC;
  signal myVideoin_n_132 : STD_LOGIC;
  signal myVideoin_n_133 : STD_LOGIC;
  signal myVideoin_n_134 : STD_LOGIC;
  signal myVideoin_n_135 : STD_LOGIC;
  signal myVideoin_n_136 : STD_LOGIC;
  signal myVideoin_n_137 : STD_LOGIC;
  signal myVideoin_n_138 : STD_LOGIC;
  signal myVideoin_n_139 : STD_LOGIC;
  signal myVideoin_n_140 : STD_LOGIC;
  signal myVideoin_n_141 : STD_LOGIC;
  signal myVideoin_n_142 : STD_LOGIC;
  signal myVideoin_n_143 : STD_LOGIC;
  signal myVideoin_n_144 : STD_LOGIC;
  signal myVideoin_n_145 : STD_LOGIC;
  signal myVideoin_n_146 : STD_LOGIC;
  signal myVideoin_n_147 : STD_LOGIC;
  signal myVideoin_n_148 : STD_LOGIC;
  signal myVideoin_n_149 : STD_LOGIC;
  signal myVideoin_n_150 : STD_LOGIC;
  signal myVideoin_n_151 : STD_LOGIC;
  signal myVideoin_n_152 : STD_LOGIC;
  signal myVideoin_n_153 : STD_LOGIC;
  signal myVideoin_n_154 : STD_LOGIC;
  signal myVideoin_n_155 : STD_LOGIC;
  signal myVideoin_n_156 : STD_LOGIC;
  signal myVideoin_n_157 : STD_LOGIC;
  signal myVideoin_n_158 : STD_LOGIC;
  signal myVideoin_n_159 : STD_LOGIC;
  signal myVideoin_n_160 : STD_LOGIC;
  signal myVideoin_n_165 : STD_LOGIC;
  signal myVideoin_n_166 : STD_LOGIC;
  signal myVideoin_n_17 : STD_LOGIC;
  signal myVideoin_n_18 : STD_LOGIC;
  signal myVideoin_n_19 : STD_LOGIC;
  signal myVideoin_n_20 : STD_LOGIC;
  signal myVideoin_n_21 : STD_LOGIC;
  signal myVideoin_n_22 : STD_LOGIC;
  signal myVideoin_n_23 : STD_LOGIC;
  signal myVideoin_n_24 : STD_LOGIC;
  signal myVideoin_n_4 : STD_LOGIC;
  signal myVideoin_n_5 : STD_LOGIC;
  signal myVideoin_n_6 : STD_LOGIC;
  signal myVideoin_n_61 : STD_LOGIC;
  signal myVideoin_n_63 : STD_LOGIC;
  signal myVideoin_n_64 : STD_LOGIC;
  signal myVideoin_n_65 : STD_LOGIC;
  signal myVideoin_n_66 : STD_LOGIC;
  signal myVideoin_n_7 : STD_LOGIC;
  signal myVideoin_n_8 : STD_LOGIC;
  signal myVideoin_n_9 : STD_LOGIC;
  signal myVidtrack_n_113 : STD_LOGIC;
  signal myVidtrack_n_114 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 0 to 0 );
  signal p_0_in0 : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal p_1_out1 : STD_LOGIC;
  signal \^probe\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pvwbufDecimToHostifAXIS_tdata : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal pvwbufDecimToHostifAXIS_tready : STD_LOGIC;
  signal pvwbufDecimToHostifAXIS_tvalid : STD_LOGIC;
  signal rdAAXI_araddr : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal rdmutex : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal reqCoobufCornerToHostif : STD_LOGIC;
  signal reqFlgbufTraceToHostif : STD_LOGIC;
  signal reqInvAcquire : STD_LOGIC;
  signal reqInvAssign : STD_LOGIC;
  signal reqInvConfig : STD_LOGIC;
  signal reqInvConfigSynth : STD_LOGIC;
  signal reqInvCornerConfig : STD_LOGIC;
  signal reqInvCputrackSet : STD_LOGIC;
  signal reqInvDecimAcquire : STD_LOGIC;
  signal reqInvDecimConfig : STD_LOGIC;
  signal reqInvDecimSet : STD_LOGIC;
  signal reqInvDecimUnlock : STD_LOGIC;
  signal reqInvDirectorConfig : STD_LOGIC;
  signal reqInvDirectorSet : STD_LOGIC;
  signal reqInvGetCorereg : STD_LOGIC;
  signal reqInvGetReg : STD_LOGIC;
  signal reqInvHdrengSet : STD_LOGIC;
  signal reqInvHshktrackClearMask : STD_LOGIC;
  signal reqInvHshktrackSelect : STD_LOGIC;
  signal reqInvHshktrackSet : STD_LOGIC;
  signal reqInvHshktrackSetMask : STD_LOGIC;
  signal reqInvLaserSet : STD_LOGIC;
  signal reqInvMemtrackClearMask : STD_LOGIC;
  signal reqInvMemtrackSelect : STD_LOGIC;
  signal reqInvMemtrackSet : STD_LOGIC;
  signal reqInvMemtrackSetMask : STD_LOGIC;
  signal reqInvModReg : STD_LOGIC;
  signal reqInvRotaryConfig : STD_LOGIC;
  signal reqInvRotaryMoveto : STD_LOGIC;
  signal reqInvRotaryZero : STD_LOGIC;
  signal reqInvSelect : STD_LOGIC;
  signal reqInvSetCorereg : STD_LOGIC;
  signal reqInvSetReg : STD_LOGIC;
  signal reqInvStepmuxSet : STD_LOGIC;
  signal reqInvTkclksrcSetTkst : STD_LOGIC;
  signal reqInvTraceAcquire : STD_LOGIC;
  signal reqInvTraceConfig : STD_LOGIC;
  signal reqInvVidtrackSelect : STD_LOGIC;
  signal reqInvVidtrackSet : STD_LOGIC;
  signal reqPvwbufDecimToHostif : STD_LOGIC;
  signal reqSeqbufCputrackToHostif : STD_LOGIC;
  signal reqSeqbufHshktrackToHostif : STD_LOGIC;
  signal reqSeqbufMemtrackToHostif : STD_LOGIC;
  signal reqSeqbufVidtrackToHostif : STD_LOGIC;
  signal resetMemclk : STD_LOGIC;
  signal resetMemclk_i_1_n_0 : STD_LOGIC;
  signal resetMemclk_i_2_n_0 : STD_LOGIC;
  signal reset_i_2_n_0 : STD_LOGIC;
  signal reset_memclk : STD_LOGIC;
  signal reset_memclk_i_1_n_0 : STD_LOGIC;
  signal reset_reg_n_0 : STD_LOGIC;
  signal reset_to_memclkm1 : STD_LOGIC;
  signal reset_to_memclkm1_i_1_n_0 : STD_LOGIC;
  signal reset_to_memclkm2 : STD_LOGIC;
  signal rgb0 : STD_LOGIC_VECTOR ( 21 downto 5 );
  signal \^rgbtomanyaxis_tlast_sig_reg\ : STD_LOGIC;
  signal rgbVideoinToManyAXIS_tdata : STD_LOGIC_VECTOR ( 35 downto 0 );
  signal rgbVideoinToManyAXIS_tvalid : STD_LOGIC;
  signal rng : STD_LOGIC;
  signal rotaryGetInfoAngle : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal rotaryGetInfoTixVState : STD_LOGIC_VECTOR ( 0 to 0 );
  signal row_lcl_reg : STD_LOGIC_VECTOR ( 10 downto 3 );
  signal row_lcl_reg_0 : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal rpuifStateOp_dbg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \sel0__0\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \seq[1]_2\ : STD_LOGIC_VECTOR ( 13 to 13 );
  signal \seq_reg[1]_0\ : STD_LOGIC_VECTOR ( 13 to 13 );
  signal seqbufCputrackToHostifAXIS_tdata : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal seqbufCputrackToHostifAXIS_tready : STD_LOGIC;
  signal seqbufCputrackToHostifAXIS_tvalid : STD_LOGIC;
  signal seqbufHshktrackToHostifAXIS_tdata : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal seqbufHshktrackToHostifAXIS_tready : STD_LOGIC;
  signal seqbufHshktrackToHostifAXIS_tvalid : STD_LOGIC;
  signal seqbufMemtrackToHostifAXIS_tdata : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal seqbufMemtrackToHostifAXIS_tready : STD_LOGIC;
  signal seqbufMemtrackToHostifAXIS_tvalid : STD_LOGIC;
  signal seqbufVidtrackToHostifAXIS_tdata : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal seqbufVidtrackToHostifAXIS_tready : STD_LOGIC;
  signal seqbufVidtrackToHostifAXIS_tvalid : STD_LOGIC;
  signal setCoreregVal : STD_LOGIC_VECTOR ( 15 downto 9 );
  signal staTixVTrigger : STD_LOGIC;
  signal staTixVTrigger_2 : STD_LOGIC;
  signal stateCorecfg0 : STD_LOGIC;
  signal stateEgrstr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal stateIgr : STD_LOGIC_VECTOR ( 0 to 0 );
  signal stateIgrstr : STD_LOGIC_VECTOR ( 0 to 0 );
  signal stateMclk : STD_LOGIC;
  signal stateMemclk_i_1_n_0 : STD_LOGIC;
  signal stateMemclk_reg_n_0 : STD_LOGIC;
  signal stateOp : STD_LOGIC_VECTOR ( 0 to 0 );
  signal stateOp0_out : STD_LOGIC;
  signal stateOp47_out : STD_LOGIC;
  signal stateOp5_out : STD_LOGIC;
  signal stateOp_5 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal stateOp_6 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal stateOp_7 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal stateRgbegr : STD_LOGIC_VECTOR ( 0 to 0 );
  signal stateStats : STD_LOGIC;
  signal stateStream : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \step1__6\ : STD_LOGIC;
  signal synthNotLive : STD_LOGIC;
  signal targetNotSteady : STD_LOGIC;
  signal tixVState1 : STD_LOGIC;
  signal tkclk : STD_LOGIC;
  signal tkclksrcGetTkstTkst : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal traceGetInfoTixVState : STD_LOGIC_VECTOR ( 0 to 0 );
  signal videoinStateIgr_dbg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal videoinStateRgbegr_dbg : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal vidtrackGetInfoPtr0Seqbuf : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal vidtrackGetInfoTCapt : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal vidtrackGetInfoTixVState : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^vsync\ : STD_LOGIC;
  signal weB : STD_LOGIC;
  signal wrAAXI_awvalid : STD_LOGIC;
  signal wrAAXI_wlast : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \g0_b0__0\ : label is "soft_lutpair3151";
  attribute SOFT_HLUTNM of \g0_b1__0\ : label is "soft_lutpair3151";
  attribute SOFT_HLUTNM of \g0_b2__0\ : label is "soft_lutpair3152";
  attribute SOFT_HLUTNM of \g0_b4__0\ : label is "soft_lutpair3152";
  attribute SOFT_HLUTNM of \g0_b5__0\ : label is "soft_lutpair3153";
  attribute SOFT_HLUTNM of \g0_b7__0\ : label is "soft_lutpair3153";
  attribute SOFT_HLUTNM of \i[0]_i_1__10\ : label is "soft_lutpair3155";
  attribute SOFT_HLUTNM of \i[1]__0_i_1__2\ : label is "soft_lutpair3154";
  attribute SOFT_HLUTNM of \i[1]_i_1__9\ : label is "soft_lutpair3155";
  attribute SOFT_HLUTNM of \i[2]__0_i_1__1\ : label is "soft_lutpair3150";
  attribute SOFT_HLUTNM of \i[2]_i_1__2\ : label is "soft_lutpair3148";
  attribute SOFT_HLUTNM of \i[3]__0_i_2__0\ : label is "soft_lutpair3150";
  attribute SOFT_HLUTNM of \i[3]_i_1__2\ : label is "soft_lutpair3148";
  attribute SOFT_HLUTNM of \i[4]_i_3__0\ : label is "soft_lutpair3149";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of myBufgAclk : label is "BUFG";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of myBufgAclk : label is "VCC:CE";
  attribute box_type : string;
  attribute box_type of myBufgAclk : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of resetMemclk_i_2 : label is "soft_lutpair3149";
  attribute SOFT_HLUTNM of reset_i_2 : label is "soft_lutpair3154";
begin
  camifSetCoreregVal(8 downto 0) <= \^camifsetcoreregval\(8 downto 0);
  ddrAXI_awvalid <= \^ddraxi_awvalid\;
  ddrAXI_wvalid <= \^ddraxi_wvalid\;
  probe(2 downto 0) <= \^probe\(2 downto 0);
  rgbToManyAXIS_tlast_sig_reg <= \^rgbtomanyaxis_tlast_sig_reg\;
  vsync <= \^vsync\;
g0_b0: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF55554D1528"
    )
        port map (
      I0 => stateOp_6(0),
      I1 => stateOp_6(1),
      I2 => stateOp_6(2),
      I3 => stateOp_6(3),
      I4 => stateOp_6(4),
      I5 => stateOp_6(5),
      O => hostifStateOp_dbg(0)
    );
\g0_b0__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FD4D1528"
    )
        port map (
      I0 => stateOp_7(0),
      I1 => stateOp_7(1),
      I2 => stateOp_7(2),
      I3 => stateOp_7(3),
      I4 => stateOp_7(4),
      O => rpuifStateOp_dbg(0)
    );
g0_b1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF1999962630"
    )
        port map (
      I0 => stateOp_6(0),
      I1 => stateOp_6(1),
      I2 => stateOp_6(2),
      I3 => stateOp_6(3),
      I4 => stateOp_6(4),
      I5 => stateOp_6(5),
      O => hostifStateOp_dbg(1)
    );
\g0_b1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FD962630"
    )
        port map (
      I0 => stateOp_7(0),
      I1 => stateOp_7(1),
      I2 => stateOp_7(2),
      I3 => stateOp_7(3),
      I4 => stateOp_7(4),
      O => rpuifStateOp_dbg(1)
    );
g0_b2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF601E18B840"
    )
        port map (
      I0 => stateOp_6(0),
      I1 => stateOp_6(1),
      I2 => stateOp_6(2),
      I3 => stateOp_6(3),
      I4 => stateOp_6(4),
      I5 => stateOp_6(5),
      O => hostifStateOp_dbg(2)
    );
\g0_b2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FC18B840"
    )
        port map (
      I0 => stateOp_7(0),
      I1 => stateOp_7(1),
      I2 => stateOp_7(2),
      I3 => stateOp_7(3),
      I4 => stateOp_7(4),
      O => rpuifStateOp_dbg(2)
    );
g0_b3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => stateOp_6(3),
      I1 => stateOp_6(4),
      I2 => stateOp_6(5),
      O => hostifStateOp_dbg(3)
    );
g0_b4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF7E1FE03F82"
    )
        port map (
      I0 => stateOp_6(0),
      I1 => stateOp_6(1),
      I2 => stateOp_6(2),
      I3 => stateOp_6(3),
      I4 => stateOp_6(4),
      I5 => stateOp_6(5),
      O => hostifStateOp_dbg(4)
    );
\g0_b4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FDE03F82"
    )
        port map (
      I0 => stateOp_7(0),
      I1 => stateOp_7(1),
      I2 => stateOp_7(2),
      I3 => stateOp_7(3),
      I4 => stateOp_7(4),
      O => rpuifStateOp_dbg(4)
    );
g0_b5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF7FE0003FFC"
    )
        port map (
      I0 => stateOp_6(0),
      I1 => stateOp_6(1),
      I2 => stateOp_6(2),
      I3 => stateOp_6(3),
      I4 => stateOp_6(4),
      I5 => stateOp_6(5),
      O => hostifStateOp_dbg(5)
    );
\g0_b5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FE003FFC"
    )
        port map (
      I0 => stateOp_7(0),
      I1 => stateOp_7(1),
      I2 => stateOp_7(2),
      I3 => stateOp_7(3),
      I4 => stateOp_7(4),
      O => rpuifStateOp_dbg(5)
    );
g0_b6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF7FFFFFC000"
    )
        port map (
      I0 => stateOp_6(0),
      I1 => stateOp_6(1),
      I2 => stateOp_6(2),
      I3 => stateOp_6(3),
      I4 => stateOp_6(4),
      I5 => stateOp_6(5),
      O => hostifStateOp_dbg(6)
    );
\g0_b6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF80"
    )
        port map (
      I0 => stateOp_7(1),
      I1 => stateOp_7(2),
      I2 => stateOp_7(3),
      I3 => stateOp_7(4),
      O => rpuifStateOp_dbg(6)
    );
g0_b7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF8000000000"
    )
        port map (
      I0 => stateOp_6(0),
      I1 => stateOp_6(1),
      I2 => stateOp_6(2),
      I3 => stateOp_6(3),
      I4 => stateOp_6(4),
      I5 => stateOp_6(5),
      O => hostifStateOp_dbg(7)
    );
\g0_b7__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E000"
    )
        port map (
      I0 => stateOp_7(1),
      I1 => stateOp_7(2),
      I2 => stateOp_7(3),
      I3 => stateOp_7(4),
      O => rpuifStateOp_dbg(7)
    );
\i[0]__0_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => stateMclk,
      I1 => i_reg(0),
      O => \p_0_in__1\(0)
    );
\i[0]_i_1__10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => stateMemclk_reg_n_0,
      I1 => \i_reg_n_0_[0]\,
      O => \p_0_in__0\(0)
    );
\i[1]__0_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => i_reg(0),
      I1 => i_reg(1),
      I2 => stateMclk,
      O => \p_0_in__1\(1)
    );
\i[1]_i_1__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => stateMemclk_reg_n_0,
      O => \p_0_in__0\(1)
    );
\i[2]__0_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => i_reg(1),
      I1 => i_reg(0),
      I2 => i_reg(2),
      I3 => stateMclk,
      O => \p_0_in__1\(2)
    );
\i[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[2]\,
      I3 => stateMemclk_reg_n_0,
      O => \p_0_in__0\(2)
    );
\i[3]__0_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"070F0800"
    )
        port map (
      I0 => i_reg(0),
      I1 => i_reg(1),
      I2 => stateMclk,
      I3 => i_reg(2),
      I4 => i_reg(3),
      O => \p_0_in__1\(3)
    );
\i[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00007F80"
    )
        port map (
      I0 => \i_reg_n_0_[0]\,
      I1 => \i_reg_n_0_[1]\,
      I2 => \i_reg_n_0_[2]\,
      I3 => \i_reg_n_0_[3]\,
      I4 => stateMemclk_reg_n_0,
      O => \p_0_in__0\(3)
    );
\i[4]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBB8BBBBB"
    )
        port map (
      I0 => reset_memclk,
      I1 => stateMemclk_reg_n_0,
      I2 => \i_reg_n_0_[4]\,
      I3 => \i_reg_n_0_[2]\,
      I4 => \i_reg_n_0_[3]\,
      I5 => \i[4]_i_3__0_n_0\,
      O => \i[4]_i_1__2_n_0\
    );
\i[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => \i_reg_n_0_[2]\,
      I1 => \i_reg_n_0_[0]\,
      I2 => \i_reg_n_0_[1]\,
      I3 => \i_reg_n_0_[3]\,
      I4 => \i_reg_n_0_[4]\,
      I5 => stateMemclk_reg_n_0,
      O => \p_0_in__0\(4)
    );
\i[4]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \i_reg_n_0_[1]\,
      I1 => \i_reg_n_0_[0]\,
      O => \i[4]_i_3__0_n_0\
    );
\i_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \i[4]_i_1__2_n_0\,
      CLR => reset_to_memclkm1_i_1_n_0,
      D => \p_0_in__0\(0),
      Q => \i_reg_n_0_[0]\
    );
\i_reg[0]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => reset_to_memclkm1_i_1_n_0,
      D => \p_0_in__1\(0),
      Q => i_reg(0)
    );
\i_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \i[4]_i_1__2_n_0\,
      CLR => reset_to_memclkm1_i_1_n_0,
      D => \p_0_in__0\(1),
      Q => \i_reg_n_0_[1]\
    );
\i_reg[1]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => reset_to_memclkm1_i_1_n_0,
      D => \p_0_in__1\(1),
      Q => i_reg(1)
    );
\i_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \i[4]_i_1__2_n_0\,
      CLR => reset_to_memclkm1_i_1_n_0,
      D => \p_0_in__0\(2),
      Q => \i_reg_n_0_[2]\
    );
\i_reg[2]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => reset_to_memclkm1_i_1_n_0,
      D => \p_0_in__1\(2),
      Q => i_reg(2)
    );
\i_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \i[4]_i_1__2_n_0\,
      CLR => reset_to_memclkm1_i_1_n_0,
      D => \p_0_in__0\(3),
      Q => \i_reg_n_0_[3]\
    );
\i_reg[3]__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => aclk_sig,
      CE => i,
      CLR => reset_to_memclkm1_i_1_n_0,
      D => \p_0_in__1\(3),
      Q => i_reg(3)
    );
\i_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => memclk,
      CE => \i[4]_i_1__2_n_0\,
      CLR => reset_to_memclkm1_i_1_n_0,
      D => \p_0_in__0\(4),
      Q => \i_reg_n_0_[4]\
    );
myBufgAclk: unisim.vcomponents.BUFGCE
    generic map(
      CE_TYPE => "ASYNC",
      SIM_DEVICE => "ULTRASCALE_PLUS"
    )
        port map (
      CE => '1',
      I => aclk,
      O => aclk_sig
    );
myCamif: entity work.design_1_Vsp_core_0_0_Camif
     port map (
      D(23 downto 16) => configSynthNotLive(7 downto 0),
      D(15 downto 9) => configSynthTFramepad(7 downto 1),
      D(8) => myHostif_n_134,
      D(7 downto 0) => configSynthTLinepad(7 downto 0),
      DO(6 downto 4) => drdParrom(7 downto 5),
      DO(3 downto 0) => drdParrom(3 downto 0),
      E(0) => ackInvConfigSynth_sig,
      \FSM_sequential_stateRgbegr_reg[0]\ => myCamif_n_88,
      NColRaw(2 downto 0) => NColRaw(3 downto 1),
      NRowRaw(2 downto 0) => NRowRaw(2 downto 0),
      Q(1) => myDecim_n_92,
      Q(0) => myDecim_n_93,
      ackInvCamifConfig => ackInvCamifConfig,
      ackInvCamifConfigSynth => ackInvCamifConfigSynth,
      ackInvCamifGetCorereg => ackInvCamifGetCorereg,
      ackInvCamifGetReg => ackInvCamifGetReg,
      ackInvCamifModReg => ackInvCamifModReg,
      ackInvCamifSetCorereg => ackInvCamifSetCorereg,
      ackInvCamifSetReg => ackInvCamifSetReg,
      ackInvGetCorereg_sig_reg_0 => myHostif_n_205,
      ackLiveToConfigSetReg_reg_0 => myHostif_n_181,
      aclk_sig => aclk_sig,
      camifToVideoinAXIS_tdata(23 downto 0) => camifToVideoinAXIS_tdata(23 downto 0),
      camifToVideoinAXIS_tlast => camifToVideoinAXIS_tlast,
      camifToVideoinAXIS_tvalid => camifToVideoinAXIS_tvalid,
      \capt_reg[0]\ => myHshktrack_n_74,
      \col_reg[10]_0\(7 downto 0) => col(10 downto 3),
      \col_reg[1]_0\ => myCamif_n_53,
      \corecfgAXIL_araddr_reg[12]_0\(6) => corecfgAXIL_araddr0_out(12),
      \corecfgAXIL_araddr_reg[12]_0\(5 downto 0) => corecfgAXIL_araddr0_out(7 downto 2),
      \corecfgAXIL_awaddr_reg[12]_0\(6) => corecfgAXIL_awaddr0_out(12),
      \corecfgAXIL_awaddr_reg[12]_0\(5 downto 0) => corecfgAXIL_awaddr0_out(7 downto 2),
      \corecfgAXIL_wdata_reg[31]_0\(31) => myHostif_n_206,
      \corecfgAXIL_wdata_reg[31]_0\(30) => myHostif_n_207,
      \corecfgAXIL_wdata_reg[31]_0\(29) => myHostif_n_208,
      \corecfgAXIL_wdata_reg[31]_0\(28) => myHostif_n_209,
      \corecfgAXIL_wdata_reg[31]_0\(27) => myHostif_n_210,
      \corecfgAXIL_wdata_reg[31]_0\(26) => myHostif_n_211,
      \corecfgAXIL_wdata_reg[31]_0\(25) => myHostif_n_212,
      \corecfgAXIL_wdata_reg[31]_0\(24) => myHostif_n_213,
      \corecfgAXIL_wdata_reg[31]_0\(23) => myHostif_n_214,
      \corecfgAXIL_wdata_reg[31]_0\(22) => myHostif_n_215,
      \corecfgAXIL_wdata_reg[31]_0\(21) => myHostif_n_216,
      \corecfgAXIL_wdata_reg[31]_0\(20) => myHostif_n_217,
      \corecfgAXIL_wdata_reg[31]_0\(19) => myHostif_n_218,
      \corecfgAXIL_wdata_reg[31]_0\(18) => myHostif_n_219,
      \corecfgAXIL_wdata_reg[31]_0\(17) => myHostif_n_220,
      \corecfgAXIL_wdata_reg[31]_0\(16) => myHostif_n_221,
      \corecfgAXIL_wdata_reg[31]_0\(15) => myHostif_n_222,
      \corecfgAXIL_wdata_reg[31]_0\(14) => myHostif_n_223,
      \corecfgAXIL_wdata_reg[31]_0\(13) => myHostif_n_224,
      \corecfgAXIL_wdata_reg[31]_0\(12) => myHostif_n_225,
      \corecfgAXIL_wdata_reg[31]_0\(11) => myHostif_n_226,
      \corecfgAXIL_wdata_reg[31]_0\(10) => myHostif_n_227,
      \corecfgAXIL_wdata_reg[31]_0\(9) => myHostif_n_228,
      \corecfgAXIL_wdata_reg[31]_0\(8) => myHostif_n_229,
      \corecfgAXIL_wdata_reg[31]_0\(7) => myHostif_n_230,
      \corecfgAXIL_wdata_reg[31]_0\(6) => myHostif_n_231,
      \corecfgAXIL_wdata_reg[31]_0\(5) => myHostif_n_232,
      \corecfgAXIL_wdata_reg[31]_0\(4) => myHostif_n_233,
      \corecfgAXIL_wdata_reg[31]_0\(3) => myHostif_n_234,
      \corecfgAXIL_wdata_reg[31]_0\(2) => myHostif_n_235,
      \corecfgAXIL_wdata_reg[31]_0\(1) => myHostif_n_236,
      \corecfgAXIL_wdata_reg[31]_0\(0) => myHostif_n_237,
      csi_clk_n => csi_clk_n,
      csi_clk_p => csi_clk_p,
      \dwrEobuf_reg[63]\(0) => klm(0),
      enEobufB_reg(0) => stateRgbegr(0),
      \getCoreregVal_sig_reg[31]_0\(25) => camifGetCoreregVal(31),
      \getCoreregVal_sig_reg[31]_0\(24) => camifGetCoreregVal(26),
      \getCoreregVal_sig_reg[31]_0\(23 downto 0) => camifGetCoreregVal(23 downto 0),
      grayToManyAXIS_tvalid_sig_reg => myCamif_n_79,
      grayVideoinToManyAXIS_tvalid => grayVideoinToManyAXIS_tvalid,
      hdrNotFix => hdrNotFix,
      i2cReadNotWrite_reg_0 => myHostif_n_166,
      i2cReadNotWrite_reg_1 => myHostif_n_180,
      \i2cRegaddr_reg[0]_0\ => myHostif_n_187,
      \i2cRegaddr_reg[12]_0\ => myHostif_n_183,
      \i2cRegaddr_reg[13]_0\ => myHostif_n_182,
      \i2cRegaddr_reg[15]_0\(9) => myHostif_n_170,
      \i2cRegaddr_reg[15]_0\(8) => myHostif_n_171,
      \i2cRegaddr_reg[15]_0\(7) => myHostif_n_172,
      \i2cRegaddr_reg[15]_0\(6) => myHostif_n_173,
      \i2cRegaddr_reg[15]_0\(5) => myHostif_n_174,
      \i2cRegaddr_reg[15]_0\(4) => myHostif_n_175,
      \i2cRegaddr_reg[15]_0\(3) => myHostif_n_176,
      \i2cRegaddr_reg[15]_0\(2) => myHostif_n_177,
      \i2cRegaddr_reg[15]_0\(1) => myHostif_n_178,
      \i2cRegaddr_reg[15]_0\(0) => myHostif_n_179,
      \i2cRegaddr_reg[3]_0\ => myHostif_n_186,
      \i2cRegaddr_reg[4]_0\ => myHostif_n_185,
      \i2cRegaddr_reg[6]_0\ => myHostif_n_184,
      \i_reg[0]__0_0\ => myDirector_n_23,
      \i_reg[0]__1_0\ => myDirector_n_18,
      \ixTExp_lcl_reg[1]_0\ => myCamif_n_15,
      \ixTExp_sig_reg[1]_0\ => myCamif_n_83,
      \ixTExp_sig_reg[2]_0\(0) => ixTExp(2),
      \ixTExp_sig_reg[2]_1\ => myCamif_n_82,
      \klm_reg[0]\ => myCamif_n_89,
      \klm_reg[0]_0\ => myCamif_n_90,
      \klm_reg[0]_1\ => myCamif_n_91,
      \klm_reg[0]_2\ => myCamif_n_92,
      \klm_reg[0]_3\ => myCamif_n_93,
      \klm_reg[0]_4\ => myCamif_n_94,
      \klm_reg[0]_5\ => myCamif_n_95,
      \klm_reg[0]_6\ => myCamif_n_96,
      \klm_reg[0]_7\(1) => videoinStateIgr_dbg(5),
      \klm_reg[0]_7\(0) => stateIgr(0),
      \liveSetRegAddr_reg[13]_0\(1) => myCamif_n_131,
      \liveSetRegAddr_reg[13]_0\(0) => myCamif_n_132,
      \mask_reg[0]\(0) => myCamif_n_78,
      mipi_phy_if_data_n(3 downto 0) => mipi_phy_if_data_n(3 downto 0),
      mipi_phy_if_data_p(3 downto 0) => mipi_phy_if_data_p(3 downto 0),
      \regVal_reg[0]_0\ => myCamif_n_130,
      \regVal_reg[1]_0\ => myCamif_n_129,
      \regVal_reg[3]_0\ => myCamif_n_128,
      \regVal_reg[4]_0\ => myCamif_n_127,
      \regVal_reg[5]_0\ => myCamif_n_126,
      \regVal_reg[6]_0\ => myCamif_n_97,
      \regVal_reg[7]_0\(1) => camifGetRegVal(7),
      \regVal_reg[7]_0\(0) => camifGetRegVal(2),
      reqInvConfig => reqInvConfig,
      reqInvConfigSynth => reqInvConfigSynth,
      reqInvGetCorereg => reqInvGetCorereg,
      reqInvGetReg => reqInvGetReg,
      reqInvModReg => reqInvModReg,
      reqInvSetCorereg => reqInvSetCorereg,
      reqInvSetReg => reqInvSetReg,
      \retbuf[0][0]_i_7\ => myHostif_n_91,
      rng => rng,
      \rowRaw_lcl_reg[11]_0\(8) => myCamif_n_44,
      \rowRaw_lcl_reg[11]_0\(7) => myCamif_n_45,
      \rowRaw_lcl_reg[11]_0\(6) => myCamif_n_46,
      \rowRaw_lcl_reg[11]_0\(5) => myCamif_n_47,
      \rowRaw_lcl_reg[11]_0\(4) => myCamif_n_48,
      \rowRaw_lcl_reg[11]_0\(3) => myCamif_n_49,
      \rowRaw_lcl_reg[11]_0\(2) => myCamif_n_50,
      \rowRaw_lcl_reg[11]_0\(1) => myCamif_n_51,
      \rowRaw_lcl_reg[11]_0\(0) => myCamif_n_52,
      \rowRaw_lcl_reg[1]_0\ => myCamif_n_42,
      \row_reg[0]_0\ => myCamif_n_43,
      \row_reg[0]_1\ => myDirector_n_21,
      \row_reg[11]_0\(8) => myCamif_n_32,
      \row_reg[11]_0\(7) => myCamif_n_33,
      \row_reg[11]_0\(6) => myCamif_n_34,
      \row_reg[11]_0\(5) => myCamif_n_35,
      \row_reg[11]_0\(4) => myCamif_n_36,
      \row_reg[11]_0\(3) => myCamif_n_37,
      \row_reg[11]_0\(2) => myCamif_n_38,
      \row_reg[11]_0\(1) => myCamif_n_39,
      \row_reg[11]_0\(0) => myCamif_n_40,
      scl => scl,
      sda => sda,
      sda_sig_reg => reset_reg_n_0,
      \stateConfig_reg[3]_0\ => myCamif_n_20,
      stateCorecfg0 => stateCorecfg0,
      \stateIgr_reg[1]\(0) => myCamif_n_84,
      \stateIgr_reg[1]_0\(0) => myCamif_n_85,
      \stateIgr_reg[1]_1\ => myCamif_n_86,
      \stateLive_reg[2]_0\(2) => myCamif_n_17,
      \stateLive_reg[2]_0\(1) => myCamif_n_18,
      \stateLive_reg[2]_0\(0) => myCamif_n_19,
      stateOp47_out => stateOp47_out,
      stateOp_reg_0 => myCamif_n_9,
      \stateStream_reg[0]\ => myCamif_n_80,
      \stateStream_reg[0]_0\(1 downto 0) => stateStream(1 downto 0),
      \stateSynth_reg[0]_0\ => myDirector_n_19,
      \stateSynth_reg[0]_1\ => myDirector_n_22,
      \stateSynth_reg[0]_2\ => myDirector_n_20,
      \stateSynth_reg[2]_0\(0) => myCamif_n_22,
      synthNotLive => synthNotLive,
      synthNotLive_reg_0 => \^vsync\,
      synthNotLive_reg_1 => myCamif_n_81,
      \tixVSynthmode_reg[7]_0\(7 downto 0) => configHdrNotFix(7 downto 0),
      tkclk => tkclk,
      \toVideoinAXIS_tdata_sig_reg[23]_0\(0) => myDirector_n_35,
      toVideoinAXIS_tvalid_sig_reg_0 => myCamif_n_87
    );
myCorner: entity work.design_1_Vsp_core_0_0_Corner
     port map (
      D(1) => myCorner_n_89,
      D(0) => myCorner_n_90,
      E(0) => ackInvUnlock_sig,
      \FSM_onehot_stateCoobufB_reg[5]_0\(1) => avllenCoobufCornerToHostif(11),
      \FSM_onehot_stateCoobufB_reg[5]_0\(0) => coobufCornerToHostifAXIS_tvalid,
      NColRaw(9 downto 8) => NColRaw(11 downto 10),
      NColRaw(7 downto 0) => NColRaw(8 downto 1),
      NRowRaw(2 downto 0) => NRowRaw(3 downto 1),
      Q(7 downto 0) => row_lcl_reg(10 downto 3),
      \aImdbufB_reg[0]_0\ => myDirector_n_36,
      ackCoobufCornerToHostif => ackCoobufCornerToHostif,
      ackInvCornerAcquire => ackInvCornerAcquire,
      ackInvCornerConfig => ackInvCornerConfig,
      ackInvCornerSet => ackInvCornerSet,
      ackInvCornerUnlock => ackInvCornerUnlock,
      ackInvSet_sig => ackInvSet_sig,
      ackInvUnlock_sig0_in => ackInvUnlock_sig0_in,
      aclk_sig => aclk_sig,
      \capt_reg[1]\ => myHshktrack_n_73,
      \capt_reg[2]\ => myHshktrack_n_72,
      \col0_reg[10]_0\(10 downto 0) => configCol0(10 downto 0),
      \col1_reg[10]_0\(10 downto 0) => configCol1(10 downto 0),
      \col_lcl[10]__0_i_3_0\ => myDirector_n_38,
      \col_lcl[10]__0_i_3_1\ => myDirector_n_40,
      \col_lcl[10]__0_i_3_2\ => myDirector_n_37,
      \col_lcl[10]__0_i_5_0\ => myDirector_n_41,
      \col_lcl_reg[0]__0_0\ => myDirector_n_39,
      \col_lcl_reg[10]_0\(10) => myCorner_n_78,
      \col_lcl_reg[10]_0\(9) => myCorner_n_79,
      \col_lcl_reg[10]_0\(8) => myCorner_n_80,
      \col_lcl_reg[10]_0\(7) => myCorner_n_81,
      \col_lcl_reg[10]_0\(6) => myCorner_n_82,
      \col_lcl_reg[10]_0\(5) => myCorner_n_83,
      \col_lcl_reg[10]_0\(4) => myCorner_n_84,
      \col_lcl_reg[10]_0\(3) => myCorner_n_85,
      \col_lcl_reg[10]_0\(2) => myCorner_n_86,
      \col_lcl_reg[10]_0\(1) => myCorner_n_87,
      \col_lcl_reg[10]_0\(0) => myCorner_n_88,
      coobufCornerToHostifAXIS_tready => coobufCornerToHostifAXIS_tready,
      dneCoobufCornerToHostif => dneCoobufCornerToHostif,
      doutb(63 downto 0) => coobufCornerToHostifAXIS_tdata(63 downto 0),
      \dy_reg[44]_0\(44) => myVideoin_n_116,
      \dy_reg[44]_0\(43) => myVideoin_n_117,
      \dy_reg[44]_0\(42) => myVideoin_n_118,
      \dy_reg[44]_0\(41) => myVideoin_n_119,
      \dy_reg[44]_0\(40) => myVideoin_n_120,
      \dy_reg[44]_0\(39) => myVideoin_n_121,
      \dy_reg[44]_0\(38) => myVideoin_n_122,
      \dy_reg[44]_0\(37) => myVideoin_n_123,
      \dy_reg[44]_0\(36) => myVideoin_n_124,
      \dy_reg[44]_0\(35) => myVideoin_n_125,
      \dy_reg[44]_0\(34) => myVideoin_n_126,
      \dy_reg[44]_0\(33) => myVideoin_n_127,
      \dy_reg[44]_0\(32) => myVideoin_n_128,
      \dy_reg[44]_0\(31) => myVideoin_n_129,
      \dy_reg[44]_0\(30) => myVideoin_n_130,
      \dy_reg[44]_0\(29) => myVideoin_n_131,
      \dy_reg[44]_0\(28) => myVideoin_n_132,
      \dy_reg[44]_0\(27) => myVideoin_n_133,
      \dy_reg[44]_0\(26) => myVideoin_n_134,
      \dy_reg[44]_0\(25) => myVideoin_n_135,
      \dy_reg[44]_0\(24) => myVideoin_n_136,
      \dy_reg[44]_0\(23) => myVideoin_n_137,
      \dy_reg[44]_0\(22) => myVideoin_n_138,
      \dy_reg[44]_0\(21) => myVideoin_n_139,
      \dy_reg[44]_0\(20) => myVideoin_n_140,
      \dy_reg[44]_0\(19) => myVideoin_n_141,
      \dy_reg[44]_0\(18) => myVideoin_n_142,
      \dy_reg[44]_0\(17) => myVideoin_n_143,
      \dy_reg[44]_0\(16) => myVideoin_n_144,
      \dy_reg[44]_0\(15) => myVideoin_n_145,
      \dy_reg[44]_0\(14) => myVideoin_n_146,
      \dy_reg[44]_0\(13) => myVideoin_n_147,
      \dy_reg[44]_0\(12) => myVideoin_n_148,
      \dy_reg[44]_0\(11) => myVideoin_n_149,
      \dy_reg[44]_0\(10) => myVideoin_n_150,
      \dy_reg[44]_0\(9) => myVideoin_n_151,
      \dy_reg[44]_0\(8) => myVideoin_n_152,
      \dy_reg[44]_0\(7) => myVideoin_n_153,
      \dy_reg[44]_0\(6) => myVideoin_n_154,
      \dy_reg[44]_0\(5) => myVideoin_n_155,
      \dy_reg[44]_0\(4) => myVideoin_n_156,
      \dy_reg[44]_0\(3) => myVideoin_n_157,
      \dy_reg[44]_0\(2) => myVideoin_n_158,
      \dy_reg[44]_0\(1) => myVideoin_n_159,
      \dy_reg[44]_0\(0) => myVideoin_n_160,
      enCoobuf_reg_0 => myDirector_n_4,
      grayVideoinToManyAXIS_tdata(39 downto 32) => grayVideoinToManyAXIS_tdata(59 downto 52),
      grayVideoinToManyAXIS_tdata(31 downto 24) => grayVideoinToManyAXIS_tdata(47 downto 40),
      grayVideoinToManyAXIS_tdata(23 downto 16) => grayVideoinToManyAXIS_tdata(35 downto 28),
      grayVideoinToManyAXIS_tdata(15 downto 8) => grayVideoinToManyAXIS_tdata(23 downto 16),
      grayVideoinToManyAXIS_tdata(7 downto 0) => grayVideoinToManyAXIS_tdata(11 downto 4),
      grayVideoinToManyAXIS_tlast => grayVideoinToManyAXIS_tlast,
      grayVideoinToManyAXIS_tvalid => grayVideoinToManyAXIS_tvalid,
      hdrNotFix => hdrNotFix,
      linNotLog_reg_0 => reset_reg_n_0,
      reqCoobufCornerToHostif => reqCoobufCornerToHostif,
      reqInvAcquire => reqInvAcquire,
      reqInvCornerConfig => reqInvCornerConfig,
      rng_reg_0 => myCorner_n_68,
      rng_reg_1 => myCorner_n_69,
      rng_reg_2 => myHostif_n_328,
      \row1_reg[7]_0\(7 downto 0) => \^camifsetcoreregval\(7 downto 0),
      \row_lcl_reg[1]_0\ => myCorner_n_96,
      \scoreMax_reg[7]_0\(7 downto 0) => cornerGetInfoScoreMax(7 downto 0),
      \scoreMin_reg[7]_0\(7 downto 0) => cornerGetInfoScoreMin(7 downto 0),
      \stateCorner_reg[1]_0\ => myCamif_n_79,
      \stateOp_reg[0]_0\(0) => stateOp(0),
      \stateOp_reg[1]_0\(1) => myCorner_n_93,
      \stateOp_reg[1]_0\(0) => myCorner_n_94,
      \thd_reg[7]_0\(21 downto 14) => configSynthNotLive(7 downto 0),
      \thd_reg[7]_0\(13 downto 12) => configSynthTFramepad(2 downto 1),
      \thd_reg[7]_0\(11) => myHostif_n_134,
      \thd_reg[7]_0\(10 downto 3) => configSynthTLinepad(7 downto 0),
      \thd_reg[7]_0\(2 downto 1) => setCoreregVal(10 downto 9),
      \thd_reg[7]_0\(0) => \^camifsetcoreregval\(8),
      \tixVState_reg[1]_0\(1 downto 0) => cornerGetInfoTixVState(1 downto 0),
      \tixVState_reg[1]_1\ => myCorner_n_95,
      \tixVState_reg[1]_2\ => myHostif_n_325,
      \tixVState_reg[1]_3\(0) => myHostif_n_321,
      \tixVState_reg[1]_4\(0) => myHostif_n_323,
      \tkst_reg[0]_0\ => \^vsync\,
      \tkst_reg[31]_0\(31 downto 0) => cornerGetInfoTkst(31 downto 0),
      \tkst_reg[31]_1\(31 downto 0) => tkclksrcGetTkstTkst(31 downto 0),
      vsync_last_reg_0 => myHostif_n_326
    );
myCputrack: entity work.design_1_Vsp_core_0_0_Cputrack
     port map (
      AR(0) => reset_reg_n_0,
      D(23 downto 16) => configSynthNotLive(7 downto 0),
      D(15 downto 9) => configSynthTFramepad(7 downto 1),
      D(8) => myHostif_n_134,
      D(7 downto 0) => configSynthTLinepad(7 downto 0),
      \FSM_onehot_stateSeq_reg[3]_0\(0) => avllenSeqbufCputrackToHostif(12),
      Q(31 downto 0) => cputrackGetInfoTCapt(31 downto 0),
      \TCaptMax_reg[7]_0\(7 downto 1) => setCoreregVal(15 downto 9),
      \TCaptMax_reg[7]_0\(0) => \^camifsetcoreregval\(8),
      ackInvCputrackSelect => ackInvCputrackSelect,
      ackInvCputrackSet => ackInvCputrackSet,
      ackInvSelect_sig_reg_0 => myHostif_n_314,
      ackSeqbufCputrackToHostif => ackSeqbufCputrackToHostif,
      aclk_sig => aclk_sig,
      cputrackGetInfoPtr0Seqbuf(9 downto 0) => cputrackGetInfoPtr0Seqbuf(9 downto 0),
      cputrackGetInfoTixVState(1 downto 0) => cputrackGetInfoTixVState(1 downto 0),
      dneSeqbufCputrackToHostif => dneSeqbufCputrackToHostif,
      doutb(63 downto 0) => seqbufCputrackToHostifAXIS_tdata(63 downto 0),
      hdrNotFix => hdrNotFix,
      hostifStateOp_dbg(7 downto 0) => hostifStateOp_dbg(7 downto 0),
      reqInvCputrackSet => reqInvCputrackSet,
      reqInvSelect => reqInvSelect,
      reqSeqbufCputrackToHostif => reqSeqbufCputrackToHostif,
      restart_reg_0 => myHostif_n_317,
      seqbufCputrackToHostifAXIS_tready => seqbufCputrackToHostifAXIS_tready,
      seqbufCputrackToHostifAXIS_tvalid => seqbufCputrackToHostifAXIS_tvalid,
      stateOp_dbg(6 downto 3) => rpuifStateOp_dbg(7 downto 4),
      stateOp_dbg(2 downto 0) => rpuifStateOp_dbg(2 downto 0),
      \tixVCapture_reg[7]_0\(7 downto 0) => configHdrNotFix(7 downto 0)
    );
myDdrif: entity work.design_1_Vsp_core_0_0_Ddrif
     port map (
      AR(0) => reset_reg_n_0,
      D(1) => myHdreng_n_28,
      D(0) => myHdreng_n_29,
      \FSM_onehot_stateRead_reg[2]_0\(0) => ackRd,
      \NRdA_reg[31]_0\(27 downto 0) => ddrifGetStatsNRdA(31 downto 4),
      \NRdB_reg[31]_0\(27 downto 0) => ddrifGetStatsNRdB(31 downto 4),
      \NWrA_reg[31]_0\(27 downto 0) => ddrifGetStatsNWrA(31 downto 4),
      \NWrB_reg[31]_0\(27 downto 0) => ddrifGetStatsNWrB(31 downto 4),
      Q(1) => ackWr,
      Q(0) => myDdrif_n_3,
      aclk_sig => aclk_sig,
      \burstIgrstr_reg[0]\(0) => stateIgrstr(0),
      ddrAXI_araddr(20 downto 0) => ddrAXI_araddr(20 downto 0),
      ddrAXI_arready => ddrAXI_arready,
      ddrAXI_awaddr(0) => ddrAXI_awaddr(20),
      ddrAXI_awready => ddrAXI_awready,
      ddrAXI_awvalid => \^ddraxi_awvalid\,
      ddrAXI_bready_sig_reg_0 => ddrAXI_bready,
      ddrAXI_bvalid => ddrAXI_bvalid,
      ddrAXI_rlast => ddrAXI_rlast,
      ddrAXI_rvalid => ddrAXI_rvalid,
      ddrAXI_rvalid_0 => myDdrif_n_4,
      ddrAXI_wlast => ddrAXI_wlast,
      ddrAXI_wready => ddrAXI_wready,
      ddrAXI_wready_0 => myDdrif_n_39,
      ddrAXI_wvalid => \^ddraxi_wvalid\,
      egrAXIS_tlast => egrAXIS_tlast,
      hdrmemAXI_rlast => hdrmemAXI_rlast,
      \i_reg[0]_0\(0) => i_reg_8(0),
      \ixRdidEgr_reg[4]_0\ => myDdrif_n_5,
      \ixRdid_reg[0]_0\(0) => \^probe\(0),
      memclk => memclk,
      probe(1 downto 0) => \^probe\(2 downto 1),
      rdAAXI_araddr(19 downto 0) => rdAAXI_araddr(19 downto 0),
      \rdid_reg[1][0]_0\ => myHdreng_n_12,
      \rdmutex_reg[1]_0\(1 downto 0) => rdmutex(1 downto 0),
      \rdmutex_reg[1]_1\ => myDdrif_n_35,
      \rdmutex_reg[1]_2\(0) => myHdreng_n_11,
      stateStats => stateStats,
      stateStats_reg_0(0) => p_0_in(0),
      \strbWrlock_i_reg[0]_0\(0) => resetMemclk,
      tkclk => tkclk,
      web(0) => weB,
      wrAAXI_awvalid => wrAAXI_awvalid,
      wrAAXI_wlast => wrAAXI_wlast,
      \wrmutex_reg[1]_0\ => myDdrif_n_9,
      \wrmutex_reg[1]_1\ => myDdrif_n_37
    );
myDecim: entity work.design_1_Vsp_core_0_0_Decim
     port map (
      AR(0) => reset_reg_n_0,
      CO(0) => CO(0),
      D(23 downto 19) => configSynthNotLive(4 downto 0),
      D(18 downto 17) => configSynthTFramepad(2 downto 1),
      D(16) => myHostif_n_134,
      D(15 downto 8) => configSynthTLinepad(7 downto 0),
      D(7 downto 1) => setCoreregVal(15 downto 9),
      D(0) => \^camifsetcoreregval\(8),
      DI(3) => myVideoin_n_63,
      DI(2) => myVideoin_n_64,
      DI(1) => myVideoin_n_65,
      DI(0) => myVideoin_n_66,
      E(0) => ixTExp_lcl,
      \FSM_onehot_statePvwbufB_reg[5]_0\(1) => avllenPvwbufDecimToHostif(15),
      \FSM_onehot_statePvwbufB_reg[5]_0\(0) => pvwbufDecimToHostifAXIS_tvalid,
      NColRaw(10 downto 0) => NColRaw(11 downto 1),
      NRowRaw(10 downto 0) => NRowRaw(11 downto 1),
      O(7 downto 0) => dwrAccbuf(7 downto 0),
      Q(7 downto 0) => \^camifsetcoreregval\(7 downto 0),
      S(7 downto 0) => S(7 downto 0),
      \acc0_lcl_reg[7]_0\(7) => myDecim_n_126,
      \acc0_lcl_reg[7]_0\(6) => myDecim_n_127,
      \acc0_lcl_reg[7]_0\(5) => myDecim_n_128,
      \acc0_lcl_reg[7]_0\(4) => myDecim_n_129,
      \acc0_lcl_reg[7]_0\(3) => myDecim_n_130,
      \acc0_lcl_reg[7]_0\(2) => myDecim_n_131,
      \acc0_lcl_reg[7]_0\(1) => myDecim_n_132,
      \acc0_lcl_reg[7]_0\(0) => myDecim_n_133,
      \acc0_lcl_reg[7]_i_2\(7) => myVideoin_n_17,
      \acc0_lcl_reg[7]_i_2\(6) => myVideoin_n_18,
      \acc0_lcl_reg[7]_i_2\(5) => myVideoin_n_19,
      \acc0_lcl_reg[7]_i_2\(4) => myVideoin_n_20,
      \acc0_lcl_reg[7]_i_2\(3) => myVideoin_n_21,
      \acc0_lcl_reg[7]_i_2\(2) => myVideoin_n_22,
      \acc0_lcl_reg[7]_i_2\(1) => myVideoin_n_23,
      \acc0_lcl_reg[7]_i_2\(0) => myVideoin_n_24,
      \acc2_lcl_reg[15]_i_2\(23 downto 0) => rgbVideoinToManyAXIS_tdata(35 downto 12),
      ackInvDecimAcquire => ackInvDecimAcquire,
      ackInvDecimConfig => ackInvDecimConfig,
      ackInvDecimSet => ackInvDecimSet,
      ackInvDecimUnlock => ackInvDecimUnlock,
      ackInvSet_sig => ackInvSet_sig_4,
      ackInvUnlock_sig_reg_0 => myHostif_n_157,
      ackPvwbufDecimToHostif => ackPvwbufDecimToHostif,
      aclk_sig => aclk_sig,
      \decimLast_reg[8]_0\(7 downto 0) => D(7 downto 0),
      dnePvwbufDecimToHostif => dnePvwbufDecimToHostif,
      doutb(63 downto 0) => pvwbufDecimToHostifAXIS_tdata(63 downto 0),
      \dwrAccbuf_reg[15]_0\(0) => myVideoin_n_107,
      enAccbuf0 => enAccbuf0,
      enAccbuf1 => enAccbuf1,
      enAccbuf_reg_0 => myVideoin_n_61,
      grayVideoinToManyAXIS_tlast => grayVideoinToManyAXIS_tlast,
      grayVideoinToManyAXIS_tvalid => grayVideoinToManyAXIS_tvalid,
      hdrNotFix => hdrNotFix,
      \ixTExp_lcl_reg[1]_0\(1) => myDecim_n_92,
      \ixTExp_lcl_reg[1]_0\(0) => myDecim_n_93,
      \ixTExp_lcl_reg[3]_0\(3 downto 0) => configHdrNotFix(3 downto 0),
      pvwbufDecimToHostifAXIS_tready => pvwbufDecimToHostifAXIS_tready,
      reqInvDecimAcquire => reqInvDecimAcquire,
      reqInvDecimConfig => reqInvDecimConfig,
      reqInvDecimSet => reqInvDecimSet,
      reqInvDecimUnlock => reqInvDecimUnlock,
      reqPvwbufDecimToHostif => reqPvwbufDecimToHostif,
      rgbNotGray_reg_0 => myDecim_n_68,
      rgbVideoinToManyAXIS_tvalid => rgbVideoinToManyAXIS_tvalid,
      rng_reg_0 => myDecim_n_69,
      rng_reg_1 => myHostif_n_1,
      \stateOp_reg[1]_0\(1) => myDecim_n_79,
      \stateOp_reg[1]_0\(0) => myDecim_n_80,
      \stateOp_reg[1]_1\(1 downto 0) => stateOp_5(1 downto 0),
      \stateStore_reg[1]_0\(1 downto 0) => decimStateStore_dbg(5 downto 4),
      \stateStream_reg[0]_0\(0) => decimStateStream_dbg(3),
      \stateStream_reg[0]_1\ => myDecim_n_87,
      \stateStream_reg[0]_2\ => \^rgbtomanyaxis_tlast_sig_reg\,
      \stateStream_reg[1]_0\ => myDecim_n_88,
      \stateStream_reg[1]_1\ => myDecim_n_89,
      \state_reg[5]\(1) => myVidtrack_n_113,
      \state_reg[5]\(0) => myVidtrack_n_114,
      \state_reg[5]_0\(0) => videoinStateIgr_dbg(5),
      tixVState1 => tixVState1,
      \tixVState_reg[1]_0\(1 downto 0) => decimGetInfoTixVState(1 downto 0),
      \tixVState_reg[1]_1\ => myCamif_n_15,
      \tixVState_reg[1]_2\(0) => ixTExp(2),
      \tixVState_reg[1]_3\(0) => myHostif_n_153,
      \tixVState_reg[1]_4\(0) => myHostif_n_158,
      \tkst_reg[31]_0\(31 downto 0) => decimGetInfoTkst(31 downto 0),
      \tkst_reg[31]_1\(31 downto 0) => tkclksrcGetTkstTkst(31 downto 0),
      videoinStateRgbegr_dbg(2) => videoinStateRgbegr_dbg(7),
      videoinStateRgbegr_dbg(1 downto 0) => videoinStateRgbegr_dbg(5 downto 4),
      vsync_last_reg_0 => myDecim_n_86,
      vsync_last_reg_1 => \^vsync\,
      vsync_last_reg_2 => myHostif_n_160
    );
myDirector: entity work.design_1_Vsp_core_0_0_Director
     port map (
      AR(0) => reset_reg_n_0,
      D(18 downto 11) => configSynthNotLive(7 downto 0),
      D(10 downto 8) => configSynthTFramepad(3 downto 1),
      D(7) => myHostif_n_134,
      D(6 downto 0) => configSynthTLinepad(7 downto 1),
      \NColRaw_sig_reg[11]_0\(10 downto 0) => NColRaw(11 downto 1),
      \NColRaw_sig_reg[11]_1\ => myDirector_n_36,
      \NColRaw_sig_reg[2]_0\ => myDirector_n_38,
      \NColRaw_sig_reg[3]_0\ => myDirector_n_41,
      \NColRaw_sig_reg[5]_0\ => myDirector_n_40,
      \NColRaw_sig_reg[7]_0\ => myDirector_n_43,
      \NColRaw_sig_reg[8]_0\ => myDirector_n_37,
      \NColRaw_sig_reg[9]_0\ => myDirector_n_39,
      \NRowRaw_sig_reg[10]_0\ => myDirector_n_19,
      \NRowRaw_sig_reg[11]_0\ => myDirector_n_20,
      \NRowRaw_sig_reg[11]_1\(3 downto 0) => configHdrNotFix(3 downto 0),
      \NRowRaw_sig_reg[7]_0\ => myDirector_n_4,
      Q(11 downto 0) => NRowRaw(11 downto 0),
      \aImdbufB_reg[0]\(10) => myCorner_n_78,
      \aImdbufB_reg[0]\(9) => myCorner_n_79,
      \aImdbufB_reg[0]\(8) => myCorner_n_80,
      \aImdbufB_reg[0]\(7) => myCorner_n_81,
      \aImdbufB_reg[0]\(6) => myCorner_n_82,
      \aImdbufB_reg[0]\(5) => myCorner_n_83,
      \aImdbufB_reg[0]\(4) => myCorner_n_84,
      \aImdbufB_reg[0]\(3) => myCorner_n_85,
      \aImdbufB_reg[0]\(2) => myCorner_n_86,
      \aImdbufB_reg[0]\(1) => myCorner_n_87,
      \aImdbufB_reg[0]\(0) => myCorner_n_88,
      ackInvDirectorConfig => ackInvDirectorConfig,
      ackInvDirectorSet => ackInvDirectorSet,
      aclk_sig => aclk_sig,
      \col_reg[8]\ => myDirector_n_23,
      commok => commok,
      enCoobuf_reg => \^vsync\,
      \i[7]_i_3_0\(7 downto 0) => col(10 downto 3),
      \i[7]_i_6_0\ => myCamif_n_53,
      \i_reg[0]__1\(8) => myCamif_n_44,
      \i_reg[0]__1\(7) => myCamif_n_45,
      \i_reg[0]__1\(6) => myCamif_n_46,
      \i_reg[0]__1\(5) => myCamif_n_47,
      \i_reg[0]__1\(4) => myCamif_n_48,
      \i_reg[0]__1\(3) => myCamif_n_49,
      \i_reg[0]__1\(2) => myCamif_n_50,
      \i_reg[0]__1\(1) => myCamif_n_51,
      \i_reg[0]__1\(0) => myCamif_n_52,
      reqInvDirectorConfig => reqInvDirectorConfig,
      reqInvDirectorSet => reqInvDirectorSet,
      rgbToManyAXIS_tlast_sig_i_2(4) => myVideoin_n_4,
      rgbToManyAXIS_tlast_sig_i_2(3) => myVideoin_n_5,
      rgbToManyAXIS_tlast_sig_i_2(2) => myVideoin_n_6,
      rgbToManyAXIS_tlast_sig_i_2(1) => myVideoin_n_7,
      rgbToManyAXIS_tlast_sig_i_2(0) => myVideoin_n_8,
      rgbToManyAXIS_tlast_sig_i_2_0 => myVideoin_n_9,
      rgbToManyAXIS_tlast_sig_i_4_0 => myVideoin_n_165,
      rgbToManyAXIS_tlast_sig_i_4_1 => myVideoin_n_166,
      rgbToManyAXIS_tlast_sig_i_4_2 => myVideoin_n_13,
      rng => rng,
      rng_sig_reg_0 => myDirector_n_17,
      rng_sig_reg_1(0) => myDirector_n_35,
      rng_sig_reg_2 => myHostif_n_276,
      \rowRaw_lcl_reg[10]\ => myDirector_n_18,
      \row_lcl_reg[0]\ => myDirector_n_42,
      \row_reg[0]\(8) => myCamif_n_32,
      \row_reg[0]\(7) => myCamif_n_33,
      \row_reg[0]\(6) => myCamif_n_34,
      \row_reg[0]\(5) => myCamif_n_35,
      \row_reg[0]\(4) => myCamif_n_36,
      \row_reg[0]\(3) => myCamif_n_37,
      \row_reg[0]\(2) => myCamif_n_38,
      \row_reg[0]\(1) => myCamif_n_39,
      \row_reg[0]\(0) => myCamif_n_40,
      \row_reg[11]\ => myDirector_n_21,
      \row_reg[9]\ => myDirector_n_22,
      \stateLive[1]_i_11_0\ => myCamif_n_42,
      \stateMaxsel[0]_i_2_0\(7 downto 0) => row_lcl_reg(10 downto 3),
      \stateMaxsel[0]_i_6_0\ => myCorner_n_96,
      stateOp0_out => stateOp0_out,
      stateOp_reg_0 => myDirector_n_2,
      \stateSwap[2]_i_5_0\(10 downto 0) => row_lcl_reg_0(10 downto 0),
      \stateSynth[2]_i_12_0\ => myCamif_n_43,
      \toVideoinAXIS_tdata_sig_reg[23]\(0) => myCamif_n_22
    );
myHdreng: entity work.design_1_Vsp_core_0_0_Hdreng
     port map (
      AR(0) => resetMemclk,
      D(0) => myHdreng_n_14,
      E(0) => myHostif_n_329,
      \FSM_onehot_stateWrite_reg[1]\(1) => myHdreng_n_28,
      \FSM_onehot_stateWrite_reg[1]\(0) => myHdreng_n_29,
      \FSM_sequential_stateEgrstr_reg[2]_0\(2 downto 0) => stateEgrstr(2 downto 0),
      \FSM_sequential_stateIgrstr_reg[0]_0\(0) => stateIgrstr(0),
      Q(1 downto 0) => stateStream(1 downto 0),
      \aRowbufBEgrstr_reg[0]_0\ => myDdrif_n_39,
      ackInvAssign_sig => ackInvAssign_sig,
      ackInvHdrengAssign => ackInvHdrengAssign,
      ackInvHdrengSet => ackInvHdrengSet,
      ackInvSet_sig_reg_0 => myHostif_n_10,
      aclk_sig => aclk_sig,
      \burstIgrstr_reg[0]_0\ => myDdrif_n_4,
      \capt_reg[5]\ => myMemtrack_n_66,
      ddrAXI_arready => ddrAXI_arready,
      ddrAXI_arvalid => ddrAXI_arvalid,
      ddrAXI_arvalid_0(1 downto 0) => rdmutex(1 downto 0),
      ddrAXI_awaddr(19 downto 0) => ddrAXI_awaddr(19 downto 0),
      \ddrAXI_awaddr[27]\ => myDdrif_n_9,
      ddrAXI_awready => ddrAXI_awready,
      ddrAXI_awvalid => \^ddraxi_awvalid\,
      ddrAXI_rdata(127 downto 0) => ddrAXI_rdata(127 downto 0),
      ddrAXI_rlast => ddrAXI_rlast,
      ddrAXI_rready => ddrAXI_rready,
      ddrAXI_rready_0 => myDdrif_n_5,
      ddrAXI_rvalid => ddrAXI_rvalid,
      ddrAXI_rvalid_0 => myHdreng_n_12,
      ddrAXI_wdata(127 downto 0) => ddrAXI_wdata(127 downto 0),
      ddrAXI_wdata_0_sp_1 => myDdrif_n_37,
      ddrAXI_wready => ddrAXI_wready,
      ddrAXI_wvalid => \^ddraxi_wvalid\,
      \dwrRowbuf[2]_i_19_0\ => myCamif_n_83,
      \dwrRowbuf_reg[0]_0\(0) => reset_reg_n_0,
      \dwrRowbuf_reg[0]_1\ => myCamif_n_82,
      egrAXIS_tlast => egrAXIS_tlast,
      hdrmemAXI_rlast => hdrmemAXI_rlast,
      \ixMemAcq_reg[7]_0\(7 downto 0) => hdrengGetInfoIxMemAcq(7 downto 0),
      \ixMemNext_reg[7]_0\(7) => myHostif_n_331,
      \ixMemNext_reg[7]_0\(6) => myHostif_n_332,
      \ixMemNext_reg[7]_0\(5) => myHostif_n_333,
      \ixMemNext_reg[7]_0\(4) => myHostif_n_334,
      \ixMemNext_reg[7]_0\(3) => myHostif_n_335,
      \ixMemNext_reg[7]_0\(2) => myHostif_n_336,
      \ixMemNext_reg[7]_0\(1) => myHostif_n_337,
      \ixMemNext_reg[7]_0\(0) => myHostif_n_338,
      \ixMem_reg[7]_0\(7 downto 0) => hdrengGetInfoIxMem(7 downto 0),
      memclk => memclk,
      probe(0) => \^probe\(0),
      rdAAXI_araddr(19 downto 0) => rdAAXI_araddr(19 downto 0),
      reqInvAssign => reqInvAssign,
      reqInvHdrengSet => reqInvHdrengSet,
      \rgbFromVideoinAXIS_tdatam1_reg[35]_0\(35 downto 0) => rgbVideoinToManyAXIS_tdata(35 downto 0),
      rgbFromVideoinAXIS_tlast_sig_to_memclk_reg_0 => \^rgbtomanyaxis_tlast_sig_reg\,
      rgbVideoinToManyAXIS_tvalid => rgbVideoinToManyAXIS_tvalid,
      rng_reg_0 => myHdreng_n_4,
      rng_reg_1 => myHostif_n_339,
      \row_lcl_reg[10]_0\(10 downto 0) => row_lcl_reg_0(10 downto 0),
      stateOp_reg_0 => myHdreng_n_1,
      stateOp_reg_1 => myHostif_n_7,
      \stateStream_reg[0]_0\ => myCamif_n_80,
      \stateStream_reg[0]_1\(10 downto 0) => NColRaw(11 downto 1),
      \stateStream_reg[1]_0\ => \^vsync\,
      \stateSwap[3]_i_3_0\ => myDdrif_n_35,
      \stateSwap[3]_i_3_1\(0) => ackRd,
      \stateSwap[3]_i_5_0\(1) => ackWr,
      \stateSwap[3]_i_5_0\(0) => myDdrif_n_3,
      \stateSwap_reg[2]_0\ => myDirector_n_42,
      \stateSwap_reg[3]_0\(3) => myHdreng_n_8,
      \stateSwap_reg[3]_0\(2) => p_1_out1,
      \stateSwap_reg[3]_0\(1) => myHdreng_n_10,
      \stateSwap_reg[3]_0\(0) => myHdreng_n_11,
      \tixVState_reg[7]_0\(2) => hdrengGetInfoTixVState(7),
      \tixVState_reg[7]_0\(1 downto 0) => hdrengGetInfoTixVState(1 downto 0),
      \tixVState_reg[7]_1\ => myCamif_n_81,
      \tkstAcq_reg[31]_0\(31 downto 0) => tkclksrcGetTkstTkst(31 downto 0),
      \tkst_reg[31]_0\(31 downto 0) => hdrengGetInfoTkst(31 downto 0),
      web(0) => weB,
      wrAAXI_awvalid => wrAAXI_awvalid,
      wrAAXI_wlast => wrAAXI_wlast
    );
myHostif: entity work.design_1_Vsp_core_0_0_Hostif
     port map (
      AXIL_arready => apuAXIL_arready,
      AXIL_awready_sig_reg => apuAXIL_awready,
      AXIL_bvalid_sig_reg => apuAXIL_bvalid,
      AXIL_wready_sig_reg => apuAXIL_wready,
      CO(0) => myRotary_n_11,
      D(23 downto 16) => configSynthNotLive(7 downto 0),
      D(15 downto 9) => configSynthTFramepad(7 downto 1),
      D(8) => myHostif_n_134,
      D(7 downto 0) => configSynthTLinepad(7 downto 0),
      DI(2) => myHostif_n_295,
      DI(1) => myHostif_n_296,
      DI(0) => myHostif_n_297,
      DO(6 downto 4) => drdParrom(7 downto 5),
      DO(3 downto 0) => drdParrom(3 downto 0),
      E(0) => ixTExp_lcl,
      O(5 downto 0) => ccwNotCw2(13 downto 8),
      Q(3 downto 0) => i_reg(3 downto 0),
      S(5) => myHostif_n_97,
      S(4) => myHostif_n_98,
      S(3) => myHostif_n_99,
      S(2) => myHostif_n_100,
      S(1) => myHostif_n_101,
      S(0) => myHostif_n_102,
      ackCoobufCornerToHostif => ackCoobufCornerToHostif,
      ackFlgbufTraceToHostif => ackFlgbufTraceToHostif,
      ackInvAcquire_sig3_out => ackInvAcquire_sig3_out,
      ackInvAssign_sig => ackInvAssign_sig,
      ackInvCamifConfig => ackInvCamifConfig,
      ackInvCamifConfigSynth => ackInvCamifConfigSynth,
      ackInvCamifGetCorereg => ackInvCamifGetCorereg,
      ackInvCamifGetReg => ackInvCamifGetReg,
      ackInvCamifModReg => ackInvCamifModReg,
      ackInvCamifSetCorereg => ackInvCamifSetCorereg,
      ackInvCamifSetReg => ackInvCamifSetReg,
      ackInvClearMask_sig_reg => myHostif_n_312,
      ackInvConfig_sig => ackInvConfig_sig,
      \ackInvConfig_sig0__6\ => \ackInvConfig_sig0__6\,
      ackInvCornerAcquire => ackInvCornerAcquire,
      ackInvCornerConfig => ackInvCornerConfig,
      ackInvCornerSet => ackInvCornerSet,
      ackInvCornerUnlock => ackInvCornerUnlock,
      ackInvCputrackSelect => ackInvCputrackSelect,
      ackInvCputrackSet => ackInvCputrackSet,
      ackInvDecimAcquire => ackInvDecimAcquire,
      ackInvDecimConfig => ackInvDecimConfig,
      ackInvDecimSet => ackInvDecimSet,
      ackInvDecimUnlock => ackInvDecimUnlock,
      ackInvDirectorConfig => ackInvDirectorConfig,
      ackInvDirectorSet => ackInvDirectorSet,
      ackInvHdrengAssign => ackInvHdrengAssign,
      ackInvHdrengSet => ackInvHdrengSet,
      ackInvHshktrackClearMask => ackInvHshktrackClearMask,
      ackInvHshktrackSelect => ackInvHshktrackSelect,
      ackInvHshktrackSet => ackInvHshktrackSet,
      ackInvHshktrackSetMask => ackInvHshktrackSetMask,
      ackInvLaserSet => ackInvLaserSet,
      ackInvMemtrackClearMask => ackInvMemtrackClearMask,
      ackInvMemtrackSelect => ackInvMemtrackSelect,
      ackInvMemtrackSet => ackInvMemtrackSet,
      ackInvMemtrackSetMask => ackInvMemtrackSetMask,
      ackInvModReg_sig_reg => myHostif_n_181,
      ackInvRotaryConfig => ackInvRotaryConfig,
      ackInvRotaryMoveto => ackInvRotaryMoveto,
      ackInvRotarySet => ackInvRotarySet,
      ackInvRotaryZero => ackInvRotaryZero,
      ackInvSelect_sig_reg => myHostif_n_313,
      ackInvSelect_sig_reg_0 => myHostif_n_314,
      \ackInvSetMask_sig_i_2__0_0\ => myHostif_n_310,
      ackInvSetMask_sig_reg => myHostif_n_270,
      ackInvSet_sig => ackInvSet_sig_4,
      ackInvSet_sig_0 => ackInvSet_sig_1,
      ackInvSet_sig_1 => ackInvSet_sig,
      ackInvSet_sig_i_8_0 => myHostif_n_326,
      ackInvSet_sig_reg(1) => rotaryGetInfoTixVState(0),
      ackInvSet_sig_reg(0) => myRotary_n_34,
      ackInvStepmuxSet => ackInvStepmuxSet,
      ackInvTkclksrcSetTkst => ackInvTkclksrcSetTkst,
      ackInvTraceAcquire => ackInvTraceAcquire,
      ackInvTraceConfig => ackInvTraceConfig,
      ackInvUnlock_sig0_in => ackInvUnlock_sig0_in,
      ackInvVidtrackSelect => ackInvVidtrackSelect,
      ackInvVidtrackSet => ackInvVidtrackSet,
      ackPvwbufDecimToHostif => ackPvwbufDecimToHostif,
      ackSeqbufCputrackToHostif => ackSeqbufCputrackToHostif,
      ackSeqbufHshktrackToHostif => ackSeqbufHshktrackToHostif,
      ackSeqbufMemtrackToHostif => ackSeqbufMemtrackToHostif,
      ackSeqbufVidtrackToHostif => ackSeqbufVidtrackToHostif,
      aclk_sig => aclk_sig,
      apuAXIL_araddr(1 downto 0) => apuAXIL_araddr(1 downto 0),
      apuAXIL_arvalid => apuAXIL_arvalid,
      apuAXIL_awaddr(1 downto 0) => apuAXIL_awaddr(1 downto 0),
      apuAXIL_awvalid => apuAXIL_awvalid,
      apuAXIL_bready => apuAXIL_bready,
      apuAXIL_rdata(63 downto 0) => apuAXIL_rdata(63 downto 0),
      apuAXIL_rready => apuAXIL_rready,
      apuAXIL_rvalid => apuAXIL_rvalid,
      apuAXIL_wdata(63 downto 0) => apuAXIL_wdata(63 downto 0),
      apuAXIL_wstrb(7 downto 0) => apuAXIL_wstrb(7 downto 0),
      apuAXIL_wvalid => apuAXIL_wvalid,
      avllenSeqbufMemtrackToHostif(0) => avllenSeqbufMemtrackToHostif(12),
      ccwNotCw0 => ccwNotCw0,
      \ccwNotCw2_carry__0\(13 downto 0) => rotaryGetInfoAngle(13 downto 0),
      ccwNotCw5_in => ccwNotCw5_in,
      ccwNotCw_reg(0) => myRotary_n_12,
      ccwNotCw_reg_0(0) => myRotary_n_14,
      ccwNotCw_reg_1(0) => myRotary_n_13,
      commok => commok,
      commok_sig_reg_0(1) => p_0_in0,
      commok_sig_reg_0(0) => myHostif_n_385,
      coobufCornerToHostifAXIS_tready => coobufCornerToHostifAXIS_tready,
      cputrackGetInfoPtr0Seqbuf(9 downto 0) => cputrackGetInfoPtr0Seqbuf(9 downto 0),
      cputrackGetInfoTixVState(1 downto 0) => cputrackGetInfoTixVState(1 downto 0),
      dneCoobufCornerToHostif => dneCoobufCornerToHostif,
      dneFlgbufTraceToHostif => dneFlgbufTraceToHostif,
      dnePvwbufDecimToHostif => dnePvwbufDecimToHostif,
      dneSeqbufCputrackToHostif => dneSeqbufCputrackToHostif,
      dneSeqbufHshktrackToHostif => dneSeqbufHshktrackToHostif,
      dneSeqbufMemtrackToHostif => dneSeqbufMemtrackToHostif,
      dneSeqbufVidtrackToHostif => dneSeqbufVidtrackToHostif,
      doutb(63 downto 0) => coobufCornerToHostifAXIS_tdata(63 downto 0),
      flgbufTraceToHostifAXIS_tready => flgbufTraceToHostifAXIS_tready,
      hdrNotFix => hdrNotFix,
      hshktrackGetInfoPtr0Seqbuf(9 downto 0) => hshktrackGetInfoPtr0Seqbuf(9 downto 0),
      hshktrackGetInfoTixVState(1 downto 0) => hshktrackGetInfoTixVState(1 downto 0),
      i2cReadNotWrite_reg(2) => myCamif_n_17,
      i2cReadNotWrite_reg(1) => myCamif_n_18,
      i2cReadNotWrite_reg(0) => myCamif_n_19,
      \i2cRegaddr[15]_i_6_0\ => myHostif_n_180,
      \i2cRegaddr_reg[13]\(1) => myCamif_n_131,
      \i2cRegaddr_reg[13]\(0) => myCamif_n_132,
      \i2cRegaddr_reg[15]\ => myCamif_n_20,
      \i_reg[2]__0\ => myHostif_n_18,
      \invbuf_reg[0][0]_0\ => myHostif_n_149,
      \invbuf_reg[0][0]_1\ => myHostif_n_150,
      \invbuf_reg[0][1]_0\ => myHostif_n_261,
      \invbuf_reg[0][4]_0\ => myHostif_n_183,
      \invbuf_reg[0][5]_0\ => myHostif_n_182,
      \invbuf_reg[0][5]_1\(3) => ccwNotCw2(14),
      \invbuf_reg[0][5]_1\(2) => myHostif_n_289,
      \invbuf_reg[0][5]_1\(1) => myHostif_n_290,
      \invbuf_reg[0][5]_1\(0) => myHostif_n_291,
      \invbuf_reg[0][5]_2\(2) => myHostif_n_292,
      \invbuf_reg[0][5]_2\(1) => myHostif_n_293,
      \invbuf_reg[0][5]_2\(0) => myHostif_n_294,
      \invbuf_reg[0][5]_3\(2) => myHostif_n_298,
      \invbuf_reg[0][5]_3\(1) => myHostif_n_299,
      \invbuf_reg[0][5]_3\(0) => myHostif_n_300,
      \invbuf_reg[0][5]_4\(0) => myHostif_n_301,
      \invbuf_reg[0][7]_0\(7 downto 0) => configHdrNotFix(7 downto 0),
      \invbuf_reg[0][7]_1\(9) => myHostif_n_170,
      \invbuf_reg[0][7]_1\(8) => myHostif_n_171,
      \invbuf_reg[0][7]_1\(7) => myHostif_n_172,
      \invbuf_reg[0][7]_1\(6) => myHostif_n_173,
      \invbuf_reg[0][7]_1\(5) => myHostif_n_174,
      \invbuf_reg[0][7]_1\(4) => myHostif_n_175,
      \invbuf_reg[0][7]_1\(3) => myHostif_n_176,
      \invbuf_reg[0][7]_1\(2) => myHostif_n_177,
      \invbuf_reg[0][7]_1\(1) => myHostif_n_178,
      \invbuf_reg[0][7]_1\(0) => myHostif_n_179,
      \invbuf_reg[0][7]_2\(6) => corecfgAXIL_araddr0_out(12),
      \invbuf_reg[0][7]_2\(5 downto 0) => corecfgAXIL_araddr0_out(7 downto 2),
      \invbuf_reg[0][7]_3\(6) => corecfgAXIL_awaddr0_out(12),
      \invbuf_reg[0][7]_3\(5 downto 0) => corecfgAXIL_awaddr0_out(7 downto 2),
      \invbuf_reg[0][7]_4\(7) => myHostif_n_331,
      \invbuf_reg[0][7]_4\(6) => myHostif_n_332,
      \invbuf_reg[0][7]_4\(5) => myHostif_n_333,
      \invbuf_reg[0][7]_4\(4) => myHostif_n_334,
      \invbuf_reg[0][7]_4\(3) => myHostif_n_335,
      \invbuf_reg[0][7]_4\(2) => myHostif_n_336,
      \invbuf_reg[0][7]_4\(1) => myHostif_n_337,
      \invbuf_reg[0][7]_4\(0) => myHostif_n_338,
      \invbuf_reg[0][7]_5\(1) => myHostif_n_387,
      \invbuf_reg[0][7]_5\(0) => myHostif_n_388,
      \invbuf_reg[1][0]_0\ => myHostif_n_187,
      \invbuf_reg[1][3]_0\ => myHostif_n_186,
      \invbuf_reg[1][4]_0\ => myHostif_n_185,
      \invbuf_reg[1][6]_0\ => myHostif_n_184,
      \invbuf_reg[1][7]_0\(7) => myHostif_n_111,
      \invbuf_reg[1][7]_0\(6) => myHostif_n_112,
      \invbuf_reg[1][7]_0\(5) => myHostif_n_113,
      \invbuf_reg[1][7]_0\(4) => myHostif_n_114,
      \invbuf_reg[1][7]_0\(3) => myHostif_n_115,
      \invbuf_reg[1][7]_0\(2) => myHostif_n_116,
      \invbuf_reg[1][7]_0\(1) => myHostif_n_117,
      \invbuf_reg[1][7]_0\(0) => myHostif_n_118,
      \invbuf_reg[2][7]_0\(31) => myHostif_n_206,
      \invbuf_reg[2][7]_0\(30) => myHostif_n_207,
      \invbuf_reg[2][7]_0\(29) => myHostif_n_208,
      \invbuf_reg[2][7]_0\(28) => myHostif_n_209,
      \invbuf_reg[2][7]_0\(27) => myHostif_n_210,
      \invbuf_reg[2][7]_0\(26) => myHostif_n_211,
      \invbuf_reg[2][7]_0\(25) => myHostif_n_212,
      \invbuf_reg[2][7]_0\(24) => myHostif_n_213,
      \invbuf_reg[2][7]_0\(23) => myHostif_n_214,
      \invbuf_reg[2][7]_0\(22) => myHostif_n_215,
      \invbuf_reg[2][7]_0\(21) => myHostif_n_216,
      \invbuf_reg[2][7]_0\(20) => myHostif_n_217,
      \invbuf_reg[2][7]_0\(19) => myHostif_n_218,
      \invbuf_reg[2][7]_0\(18) => myHostif_n_219,
      \invbuf_reg[2][7]_0\(17) => myHostif_n_220,
      \invbuf_reg[2][7]_0\(16) => myHostif_n_221,
      \invbuf_reg[2][7]_0\(15) => myHostif_n_222,
      \invbuf_reg[2][7]_0\(14) => myHostif_n_223,
      \invbuf_reg[2][7]_0\(13) => myHostif_n_224,
      \invbuf_reg[2][7]_0\(12) => myHostif_n_225,
      \invbuf_reg[2][7]_0\(11) => myHostif_n_226,
      \invbuf_reg[2][7]_0\(10) => myHostif_n_227,
      \invbuf_reg[2][7]_0\(9) => myHostif_n_228,
      \invbuf_reg[2][7]_0\(8) => myHostif_n_229,
      \invbuf_reg[2][7]_0\(7) => myHostif_n_230,
      \invbuf_reg[2][7]_0\(6) => myHostif_n_231,
      \invbuf_reg[2][7]_0\(5) => myHostif_n_232,
      \invbuf_reg[2][7]_0\(4) => myHostif_n_233,
      \invbuf_reg[2][7]_0\(3) => myHostif_n_234,
      \invbuf_reg[2][7]_0\(2) => myHostif_n_235,
      \invbuf_reg[2][7]_0\(1) => myHostif_n_236,
      \invbuf_reg[2][7]_0\(0) => myHostif_n_237,
      \invbuf_reg[4][7]_0\(7 downto 1) => setCoreregVal(15 downto 9),
      \invbuf_reg[4][7]_0\(0) => \^camifsetcoreregval\(8),
      \invbuf_reg[5][7]_0\(7 downto 0) => \^camifsetcoreregval\(7 downto 0),
      \invbuf_reg[6][2]_0\(10 downto 0) => configCol0(10 downto 0),
      \invbuf_reg[8][2]_0\(10 downto 0) => configCol1(10 downto 0),
      linNotRot_reg => myStepmux_n_1,
      \mask_reg[0]\ => myHostif_n_152,
      \mask_reg[0]_0\ => myHostif_n_265,
      \mask_reg[0]_1\ => myHshktrack_n_74,
      \mask_reg[0]_2\ => myMemtrack_n_71,
      \mask_reg[1]\ => myHostif_n_151,
      \mask_reg[1]_0\ => myHostif_n_264,
      \mask_reg[1]_1\ => myHshktrack_n_73,
      \mask_reg[1]_2\ => myMemtrack_n_70,
      \mask_reg[2]\ => myHostif_n_263,
      \mask_reg[2]_0\ => myHshktrack_n_72,
      \mask_reg[2]_1\ => myMemtrack_n_69,
      \mask_reg[3]\ => myHostif_n_262,
      \mask_reg[3]_0\(0) => myHostif_n_303,
      \mask_reg[3]_1\ => myHshktrack_n_71,
      \mask_reg[3]_2\ => myMemtrack_n_68,
      \mask_reg[4]\ => myHostif_n_148,
      \mask_reg[4]_0\ => myHostif_n_260,
      \mask_reg[4]_1\ => myHshktrack_n_70,
      \mask_reg[4]_2\ => myMemtrack_n_67,
      \mask_reg[5]\ => myHostif_n_147,
      \mask_reg[5]_0\ => myHostif_n_259,
      \mask_reg[5]_1\ => myHshktrack_n_107,
      \mask_reg[5]_2\ => myHshktrack_n_69,
      \mask_reg[5]_3\ => myMemtrack_n_66,
      \mask_reg[6]\ => myHostif_n_258,
      \mask_reg[6]_0\ => myMemtrack_n_65,
      \mask_reg[7]\ => myHostif_n_257,
      \mask_reg[7]_0\ => myMemtrack_n_81,
      \mask_reg[7]_1\ => myMemtrack_n_64,
      memtrackGetInfoTixVState(1 downto 0) => memtrackGetInfoTixVState(1 downto 0),
      \pollbuf[2][3]_i_2_0\(1) => avllenCoobufCornerToHostif(11),
      \pollbuf[2][3]_i_2_0\(0) => coobufCornerToHostifAXIS_tvalid,
      \pollbuf[2][4]_i_2_0\(0) => avllenSeqbufVidtrackToHostif(12),
      \pollbuf[2][4]_i_2_1\(0) => avllenSeqbufCputrackToHostif(12),
      \pollbuf[2][7]_i_2_0\(1) => avllenFlgbufTraceToHostif(15),
      \pollbuf[2][7]_i_2_0\(0) => flgbufTraceToHostifAXIS_tvalid,
      \pollbuf_reg[2][4]_0\(0) => avllenSeqbufHshktrackToHostif(12),
      \pollbuf_reg[2][7]_0\(1) => avllenPvwbufDecimToHostif(15),
      \pollbuf_reg[2][7]_0\(0) => pvwbufDecimToHostifAXIS_tvalid,
      pvwbufDecimToHostifAXIS_tready => pvwbufDecimToHostifAXIS_tready,
      reqCoobufCornerToHostif => reqCoobufCornerToHostif,
      reqFlgbufTraceToHostif => reqFlgbufTraceToHostif,
      reqInvAcquire => reqInvAcquire,
      reqInvAssign => reqInvAssign,
      reqInvConfig => reqInvConfig,
      reqInvConfigSynth => reqInvConfigSynth,
      reqInvCornerConfig => reqInvCornerConfig,
      reqInvCputrackSet => reqInvCputrackSet,
      reqInvDecimAcquire => reqInvDecimAcquire,
      reqInvDecimConfig => reqInvDecimConfig,
      reqInvDecimSet => reqInvDecimSet,
      reqInvDecimUnlock => reqInvDecimUnlock,
      reqInvDirectorConfig => reqInvDirectorConfig,
      reqInvDirectorSet => reqInvDirectorSet,
      reqInvGetCorereg => reqInvGetCorereg,
      reqInvGetReg => reqInvGetReg,
      reqInvHdrengSet => reqInvHdrengSet,
      reqInvHshktrackClearMask => reqInvHshktrackClearMask,
      reqInvHshktrackSelect => reqInvHshktrackSelect,
      reqInvHshktrackSet => reqInvHshktrackSet,
      reqInvHshktrackSetMask => reqInvHshktrackSetMask,
      reqInvLaserSet => reqInvLaserSet,
      reqInvMemtrackClearMask => reqInvMemtrackClearMask,
      reqInvMemtrackSelect => reqInvMemtrackSelect,
      reqInvMemtrackSet => reqInvMemtrackSet,
      reqInvMemtrackSetMask => reqInvMemtrackSetMask,
      reqInvModReg => reqInvModReg,
      reqInvRotaryConfig => reqInvRotaryConfig,
      reqInvRotaryMoveto => reqInvRotaryMoveto,
      reqInvRotaryZero => reqInvRotaryZero,
      reqInvSelect => reqInvSelect,
      reqInvSetCorereg => reqInvSetCorereg,
      reqInvSetReg => reqInvSetReg,
      reqInvStepmuxSet => reqInvStepmuxSet,
      reqInvTkclksrcSetTkst => reqInvTkclksrcSetTkst,
      reqInvTraceAcquire => reqInvTraceAcquire,
      reqInvTraceConfig => reqInvTraceConfig,
      reqInvVidtrackSelect => reqInvVidtrackSelect,
      reqInvVidtrackSet => reqInvVidtrackSet,
      reqPvwbufDecimToHostif => reqPvwbufDecimToHostif,
      reqReset_sig_reg_0 => myHostif_n_17,
      reqReset_sig_reg_1(0) => i,
      reqSeqbufCputrackToHostif => reqSeqbufCputrackToHostif,
      reqSeqbufHshktrackToHostif => reqSeqbufHshktrackToHostif,
      reqSeqbufMemtrackToHostif => reqSeqbufMemtrackToHostif,
      reqSeqbufVidtrackToHostif => reqSeqbufVidtrackToHostif,
      reset_reg => reset_i_2_n_0,
      \retbuf[0][0]_i_2_0\ => myCamif_n_130,
      \retbuf[0][3]_i_3_0\ => myCamif_n_128,
      \retbuf[0][4]_i_3_0\ => myCamif_n_127,
      \retbuf[0][5]_i_3_0\ => myCamif_n_126,
      \retbuf[0][6]_i_4_0\ => myCamif_n_97,
      \retbuf[0][7]_i_10\(31 downto 0) => tkclksrcGetTkstTkst(31 downto 0),
      \retbuf[0][7]_i_10_0\(2) => hdrengGetInfoTixVState(7),
      \retbuf[0][7]_i_10_0\(1 downto 0) => hdrengGetInfoTixVState(1 downto 0),
      \retbuf[0][7]_i_20_0\(25) => camifGetCoreregVal(31),
      \retbuf[0][7]_i_20_0\(24) => camifGetCoreregVal(26),
      \retbuf[0][7]_i_20_0\(23 downto 0) => camifGetCoreregVal(23 downto 0),
      \retbuf[0][7]_i_20_1\(27 downto 0) => ddrifGetStatsNRdA(31 downto 4),
      \retbuf[0][7]_i_20_2\(1) => camifGetRegVal(7),
      \retbuf[0][7]_i_20_2\(0) => camifGetRegVal(2),
      \retbuf[1][7]_i_8_0\(31 downto 0) => cputrackGetInfoTCapt(31 downto 0),
      \retbuf[1][7]_i_8_1\(31 downto 0) => hshktrackGetInfoTCapt(31 downto 0),
      \retbuf[1][7]_i_8_2\(31 downto 0) => memtrackGetInfoTCapt(31 downto 0),
      \retbuf[4][7]_i_12_0\(27 downto 0) => ddrifGetStatsNRdB(31 downto 4),
      \retbuf[5][1]_i_2_0\(9 downto 0) => memtrackGetInfoPtr0Seqbuf(9 downto 0),
      \retbuf[5][7]_i_5_0\(7 downto 0) => cornerGetInfoScoreMin(7 downto 0),
      \retbuf[5][7]_i_5_1\(7 downto 0) => hdrengGetInfoIxMem(7 downto 0),
      \retbuf[6][7]_i_4_0\(7 downto 0) => cornerGetInfoScoreMax(7 downto 0),
      \retbuf[6][7]_i_4_1\(7 downto 0) => hdrengGetInfoIxMemAcq(7 downto 0),
      \retbuf_reg[0][1]_i_5_0\ => myCamif_n_129,
      \retbuf_reg[12][7]_0\(27 downto 0) => ddrifGetStatsNWrB(31 downto 4),
      \retbuf_reg[1][7]_0\(31 downto 0) => vidtrackGetInfoTCapt(31 downto 0),
      \retbuf_reg[1][7]_i_13_0\(31 downto 0) => cornerGetInfoTkst(31 downto 0),
      \retbuf_reg[1][7]_i_13_1\(31 downto 0) => decimGetInfoTkst(31 downto 0),
      \retbuf_reg[1][7]_i_13_2\(31 downto 0) => hdrengGetInfoTkst(31 downto 0),
      \retbuf_reg[8][7]_0\(27 downto 0) => ddrifGetStatsNWrA(31 downto 4),
      rng => rng,
      rng_reg => myHostif_n_1,
      rng_reg_0 => myHostif_n_11,
      rng_reg_1 => myHostif_n_93,
      rng_reg_10 => myRotary_n_4,
      rng_reg_11 => myHshktrack_n_67,
      rng_reg_12 => myCorner_n_68,
      rng_reg_13 => myHdreng_n_4,
      rng_reg_2 => myHostif_n_143,
      rng_reg_3(0) => myHostif_n_153,
      rng_reg_4(1 downto 0) => stateOp_5(1 downto 0),
      rng_reg_5 => myHostif_n_328,
      rng_reg_6(0) => myHostif_n_329,
      rng_reg_7 => myDecim_n_69,
      rng_reg_8 => myHdreng_n_1,
      rng_reg_9 => myMemtrack_n_76,
      rng_sig_reg => myDirector_n_2,
      \seq[1]_2\(0) => \seq[1]_2\(13),
      seqbufCputrackToHostifAXIS_tready => seqbufCputrackToHostifAXIS_tready,
      seqbufCputrackToHostifAXIS_tvalid => seqbufCputrackToHostifAXIS_tvalid,
      seqbufHshktrackToHostifAXIS_tready => seqbufHshktrackToHostifAXIS_tready,
      seqbufHshktrackToHostifAXIS_tvalid => seqbufHshktrackToHostifAXIS_tvalid,
      seqbufMemtrackToHostifAXIS_tready => seqbufMemtrackToHostifAXIS_tready,
      seqbufMemtrackToHostifAXIS_tvalid => seqbufMemtrackToHostifAXIS_tvalid,
      seqbufVidtrackToHostifAXIS_tready => seqbufVidtrackToHostifAXIS_tready,
      seqbufVidtrackToHostifAXIS_tvalid => seqbufVidtrackToHostifAXIS_tvalid,
      \staTixVTrigger[7]_i_3__0_0\ => myHostif_n_311,
      stateCorecfg0 => stateCorecfg0,
      \stateCorecfg[2]_i_4_0\ => myHostif_n_205,
      \stateLive_reg[2]\ => myHostif_n_166,
      stateMclk => stateMclk,
      stateOp0_out => stateOp0_out,
      stateOp47_out => stateOp47_out,
      stateOp5_out => stateOp5_out,
      stateOp_reg => myHostif_n_7,
      \stateOp_reg[0]_0\ => myHostif_n_157,
      \stateOp_reg[0]_1\(0) => myHostif_n_158,
      \stateOp_reg[0]_2\ => myHostif_n_283,
      \stateOp_reg[0]_3\(0) => TCaptMax,
      \stateOp_reg[0]_4\(0) => staTixVTrigger,
      \stateOp_reg[0]_5\(0) => myHostif_n_323,
      \stateOp_reg[0]_6\(0) => ackInvUnlock_sig,
      \stateOp_reg[0]_7\(1) => myDecim_n_79,
      \stateOp_reg[0]_7\(0) => myDecim_n_80,
      \stateOp_reg[0]_8\ => myRotary_n_35,
      \stateOp_reg[0]_9\(1) => myCorner_n_93,
      \stateOp_reg[0]_9\(0) => myCorner_n_94,
      \stateOp_reg[1]_0\(0) => myHostif_n_280,
      \stateOp_reg[1]_1\ => myHostif_n_286,
      \stateOp_reg[1]_2\ => myHostif_n_287,
      \stateOp_reg[1]_3\(0) => ackInvMoveto_sig,
      \stateOp_reg[1]_4\(0) => stateOp(0),
      \stateOp_reg[1]_5\ => myHostif_n_325,
      \stateOp_reg[1]_6\(0) => reset_reg_n_0,
      \stateOp_reg[2]_0\(0) => TCaptMax_3,
      \stateOp_reg[2]_1\(0) => staTixVTrigger_2,
      \stateOp_reg[5]_0\(5 downto 0) => stateOp_6(5 downto 0),
      stateOp_reg_0 => myHostif_n_10,
      stateOp_reg_1 => myHostif_n_15,
      stateOp_reg_2(0) => ackInvConfigSynth_sig,
      stateOp_reg_3 => myHostif_n_276,
      stateOp_reg_4 => myHostif_n_339,
      stateOp_reg_5 => myCamif_n_9,
      stateOp_reg_6 => myTrace_n_64,
      \step1__6\ => \step1__6\,
      synthNotLive => synthNotLive,
      targetNotSteady => targetNotSteady,
      \tixVCommand_reg[0]_0\ => myHostif_n_91,
      \tixVCommand_reg[0]_1\ => myHostif_n_160,
      \tixVController_reg[0]_0\ => myHostif_n_317,
      \tixVController_reg[1]_0\ => myHostif_n_19,
      \tixVController_reg[1]_1\ => myHostif_n_254,
      \tixVController_reg[2]_0\ => myHostif_n_268,
      tixVState1 => tixVState1,
      \tixVState_reg[1]\(0) => myHostif_n_321,
      \tixVState_reg[1]_0\ => myDecim_n_86,
      \tixVState_reg[1]_1\(1 downto 0) => decimGetInfoTixVState(1 downto 0),
      \tixVState_reg[1]_2\(1 downto 0) => cornerGetInfoTixVState(1 downto 0),
      \tixVState_reg[1]_3\ => myCorner_n_95,
      tkclk => tkclk,
      tkclk_sig_reg(0) => myHostif_n_284,
      traceGetInfoTixVState(0) => traceGetInfoTixVState(0),
      \txAXIS_tdata[63]_i_8_0\(63 downto 0) => flgbufTraceToHostifAXIS_tdata(63 downto 0),
      \txAXIS_tdata[63]_i_8_1\(63 downto 0) => pvwbufDecimToHostifAXIS_tdata(63 downto 0),
      \txAXIS_tdata[63]_i_8_2\(63 downto 0) => seqbufHshktrackToHostifAXIS_tdata(63 downto 0),
      \txAXIS_tdata[63]_i_8_3\(63 downto 0) => seqbufMemtrackToHostifAXIS_tdata(63 downto 0),
      \txAXIS_tdata[63]_i_8_4\(63 downto 0) => seqbufCputrackToHostifAXIS_tdata(63 downto 0),
      \txAXIS_tdata[63]_i_8_5\(63 downto 0) => seqbufVidtrackToHostifAXIS_tdata(63 downto 0),
      vidtrackGetInfoPtr0Seqbuf(9 downto 0) => vidtrackGetInfoPtr0Seqbuf(9 downto 0),
      vidtrackGetInfoTixVState(1 downto 0) => vidtrackGetInfoTixVState(1 downto 0)
    );
myHshktrack: entity work.design_1_Vsp_core_0_0_Hshktrack
     port map (
      D(7 downto 0) => configHdrNotFix(7 downto 0),
      E(0) => staTixVTrigger,
      \FSM_onehot_stateSeq_reg[3]_0\(0) => avllenSeqbufHshktrackToHostif(12),
      Q(31 downto 0) => hshktrackGetInfoTCapt(31 downto 0),
      \TCaptMax_reg[31]_0\(23 downto 16) => configSynthNotLive(7 downto 0),
      \TCaptMax_reg[31]_0\(15 downto 9) => configSynthTFramepad(7 downto 1),
      \TCaptMax_reg[31]_0\(8) => myHostif_n_134,
      \TCaptMax_reg[31]_0\(7 downto 0) => configSynthTLinepad(7 downto 0),
      \TCaptMax_reg[31]_1\(0) => TCaptMax,
      \TCaptMax_reg[7]_0\(7 downto 1) => setCoreregVal(15 downto 9),
      \TCaptMax_reg[7]_0\(0) => \^camifsetcoreregval\(8),
      ackInvHshktrackClearMask => ackInvHshktrackClearMask,
      ackInvHshktrackSelect => ackInvHshktrackSelect,
      ackInvHshktrackSet => ackInvHshktrackSet,
      ackInvHshktrackSetMask => ackInvHshktrackSetMask,
      ackInvSetMask_sig_reg_0 => myHostif_n_311,
      \ackInvSet_sig_i_2__3_0\ => myHostif_n_313,
      ackSeqbufHshktrackToHostif => ackSeqbufHshktrackToHostif,
      aclk_sig => aclk_sig,
      \capt_reg[5]_0\(5) => myRotary_n_36,
      \capt_reg[5]_0\(4) => myRpuif_n_37,
      \capt_reg[5]_0\(3) => myHostif_n_303,
      \capt_reg[5]_0\(2) => myCorner_n_89,
      \capt_reg[5]_0\(1) => myCorner_n_90,
      \capt_reg[5]_0\(0) => myCamif_n_78,
      dneSeqbufHshktrackToHostif => dneSeqbufHshktrackToHostif,
      doutb(63 downto 0) => seqbufHshktrackToHostifAXIS_tdata(63 downto 0),
      enSeqbuf_reg_0(0) => reset_reg_n_0,
      hshktrackGetInfoPtr0Seqbuf(9 downto 0) => hshktrackGetInfoPtr0Seqbuf(9 downto 0),
      hshktrackGetInfoTixVState(1 downto 0) => hshktrackGetInfoTixVState(1 downto 0),
      \mask_reg[0]_0\ => myHshktrack_n_74,
      \mask_reg[0]_1\ => myHostif_n_152,
      \mask_reg[1]_0\ => myHshktrack_n_73,
      \mask_reg[1]_1\ => myHostif_n_151,
      \mask_reg[2]_0\ => myHshktrack_n_72,
      \mask_reg[2]_1\ => myHostif_n_150,
      \mask_reg[3]_0\ => myHshktrack_n_71,
      \mask_reg[3]_1\ => myHostif_n_149,
      \mask_reg[4]_0\ => myHshktrack_n_70,
      \mask_reg[4]_1\ => myHostif_n_148,
      \mask_reg[5]_0\ => myHshktrack_n_69,
      \mask_reg[5]_1\ => myHostif_n_147,
      reqInvHshktrackClearMask => reqInvHshktrackClearMask,
      reqInvHshktrackSelect => reqInvHshktrackSelect,
      reqInvHshktrackSet => reqInvHshktrackSet,
      reqInvHshktrackSetMask => reqInvHshktrackSetMask,
      reqSeqbufHshktrackToHostif => reqSeqbufHshktrackToHostif,
      restart_reg_0 => myHostif_n_312,
      restart_reg_1 => myHostif_n_310,
      rng_reg_0 => myHshktrack_n_67,
      rng_reg_1 => myHostif_n_143,
      seqbufHshktrackToHostifAXIS_tready => seqbufHshktrackToHostifAXIS_tready,
      seqbufHshktrackToHostifAXIS_tvalid => seqbufHshktrackToHostifAXIS_tvalid,
      \stateOp_reg[0]_0\ => myHshktrack_n_107
    );
myLaser: entity work.design_1_Vsp_core_0_0_Laser
     port map (
      D(17 downto 10) => configSynthNotLive(7 downto 0),
      D(9) => configSynthTFramepad(1),
      D(8) => myHostif_n_134,
      D(7 downto 0) => configSynthTLinepad(7 downto 0),
      \FSM_sequential_stateXfer_reg[2]\(0) => reset_reg_n_0,
      ackInvLaserSet => ackInvLaserSet,
      aclk_sig => aclk_sig,
      cs => cs,
      mosi => mosi,
      reqInvLaserSet => reqInvLaserSet,
      sclk => sclk,
      \txbuf_reg[0][3]_0\(1 downto 0) => configHdrNotFix(1 downto 0)
    );
myMemtrack: entity work.design_1_Vsp_core_0_0_Memtrack
     port map (
      AR(0) => resetMemclk,
      D(23 downto 16) => configSynthNotLive(7 downto 0),
      D(15 downto 9) => configSynthTFramepad(7 downto 1),
      D(8) => myHostif_n_134,
      D(7 downto 0) => configSynthTLinepad(7 downto 0),
      E(0) => staTixVTrigger_2,
      Q(31 downto 0) => memtrackGetInfoTCapt(31 downto 0),
      \TCaptMax_reg[31]_0\(0) => TCaptMax_3,
      \TCaptMax_reg[7]_0\(7 downto 1) => setCoreregVal(15 downto 9),
      \TCaptMax_reg[7]_0\(0) => \^camifsetcoreregval\(8),
      ackInvMemtrackClearMask => ackInvMemtrackClearMask,
      ackInvMemtrackSelect => ackInvMemtrackSelect,
      ackInvMemtrackSet => ackInvMemtrackSet,
      ackInvMemtrackSetMask => ackInvMemtrackSetMask,
      ackSeqbufMemtrackToHostif => ackSeqbufMemtrackToHostif,
      aclk_sig => aclk_sig,
      avllenSeqbufMemtrackToHostif(0) => avllenSeqbufMemtrackToHostif(12),
      \capt_reg[0]_0\(3) => myHdreng_n_8,
      \capt_reg[0]_0\(2) => p_1_out1,
      \capt_reg[0]_0\(1) => myHdreng_n_10,
      \capt_reg[0]_0\(0) => myHdreng_n_11,
      \capt_reg[1]_0\(1 downto 0) => rdmutex(1 downto 0),
      \capt_reg[1]_1\(0) => ackRd,
      \capt_reg[3]_0\ => myDdrif_n_37,
      \capt_reg[3]_1\(0) => ackWr,
      \capt_reg[5]_0\(0) => myHdreng_n_14,
      \capt_reg[8]_0\(2 downto 0) => stateEgrstr(2 downto 0),
      ddrAXI_bvalid => ddrAXI_bvalid,
      ddrAXI_rvalid => ddrAXI_rvalid,
      ddrAXI_wready => ddrAXI_wready,
      dneSeqbufMemtrackToHostif => dneSeqbufMemtrackToHostif,
      doutb(63 downto 0) => seqbufMemtrackToHostifAXIS_tdata(63 downto 0),
      \mask_reg[0]_0\ => myMemtrack_n_71,
      \mask_reg[0]_1\ => myHostif_n_265,
      \mask_reg[1]_0\ => myMemtrack_n_70,
      \mask_reg[1]_1\ => myHostif_n_264,
      \mask_reg[2]_0\ => myMemtrack_n_69,
      \mask_reg[2]_1\ => myHostif_n_263,
      \mask_reg[3]_0\ => myMemtrack_n_68,
      \mask_reg[3]_1\ => myHostif_n_262,
      \mask_reg[4]_0\ => myMemtrack_n_67,
      \mask_reg[4]_1\ => myHostif_n_260,
      \mask_reg[5]_0\ => myMemtrack_n_66,
      \mask_reg[5]_1\ => myHostif_n_259,
      \mask_reg[6]_0\ => myMemtrack_n_65,
      \mask_reg[6]_1\ => myHostif_n_258,
      \mask_reg[7]_0\ => myMemtrack_n_64,
      \mask_reg[7]_1\ => myHostif_n_257,
      \mask_reg[8]_0\ => myHostif_n_261,
      memclk => memclk,
      memtrackGetInfoTixVState(1 downto 0) => memtrackGetInfoTixVState(1 downto 0),
      \ptr0Seqbuf_mclk_reg[9]_0\(9 downto 0) => memtrackGetInfoPtr0Seqbuf(9 downto 0),
      \ptr0Seqbuf_to_mclkm2_reg[0]_0\(0) => reset_reg_n_0,
      reqInvMemtrackClearMask => reqInvMemtrackClearMask,
      reqInvMemtrackSelect => reqInvMemtrackSelect,
      reqInvMemtrackSet => reqInvMemtrackSet,
      reqInvMemtrackSetMask => reqInvMemtrackSetMask,
      reqSeqbufMemtrackToHostif => reqSeqbufMemtrackToHostif,
      restart_reg_0 => myHostif_n_270,
      rng_reg_0 => myMemtrack_n_76,
      rng_reg_1 => myHostif_n_11,
      seqbufMemtrackToHostifAXIS_tready => seqbufMemtrackToHostifAXIS_tready,
      seqbufMemtrackToHostifAXIS_tvalid => seqbufMemtrackToHostifAXIS_tvalid,
      \staTixVTrigger_reg[7]_0\(7 downto 0) => configHdrNotFix(7 downto 0),
      start_reg_0 => \^rgbtomanyaxis_tlast_sig_reg\,
      \stateOp_reg[2]_0\ => myMemtrack_n_81,
      stop_reg_0 => \^vsync\,
      strb_last_reg_0 => myHostif_n_268
    );
myRgbled0: entity work.design_1_Vsp_core_0_0_Rgbled_v1_0
     port map (
      D(3) => myRgbled0_n_8,
      D(2) => myRgbled0_n_9,
      D(1) => myRgbled0_n_10,
      D(0) => myRgbled0_n_11,
      DI(1) => myState_n_11,
      DI(0) => myState_n_12,
      Q(0) => myState_n_3,
      S(1) => myState_n_9,
      S(0) => myState_n_10,
      aclk_sig => aclk_sig,
      \i_reg[0]__1_0\(0) => reset_reg_n_0,
      \i_reg[6]_0\(3 downto 0) => \sel0__0\(7 downto 4),
      \i_reg[7]_0\ => myRgbled0_n_7,
      \i_reg[7]__1_0\ => myRgbled0_n_12,
      rgb0(1) => rgb0(21),
      rgb0(0) => rgb0(5),
      rgb0_b => rgb0_b,
      rgb0_g => rgb0_g,
      rgb0_r => rgb0_r,
      \seq_reg[1]_0\(0) => \seq_reg[1]_0\(13),
      stateBlue_i_2_0(0) => myState_n_6,
      \stateGreen0_inferred__0/i__carry_0\ => myState_n_13,
      stateGreen_reg_0(1) => myState_n_4,
      stateGreen_reg_0(0) => myState_n_5,
      stateGreen_reg_1(1) => myState_n_1,
      stateGreen_reg_1(0) => myState_n_2
    );
myRotary: entity work.design_1_Vsp_core_0_0_Rotary
     port map (
      CO(0) => myRotary_n_11,
      D(7 downto 0) => configSynthNotLive(7 downto 0),
      DI(2) => myHostif_n_295,
      DI(1) => myHostif_n_296,
      DI(0) => myHostif_n_297,
      E(0) => ackInvMoveto_sig,
      O(5 downto 0) => ccwNotCw2(13 downto 8),
      Q(13 downto 0) => rotaryGetInfoAngle(13 downto 0),
      S(5) => myHostif_n_97,
      S(4) => myHostif_n_98,
      S(3) => myHostif_n_99,
      S(2) => myHostif_n_100,
      S(1) => myHostif_n_101,
      S(0) => myHostif_n_102,
      \ackInvConfig_sig0__6\ => \ackInvConfig_sig0__6\,
      ackInvRotaryConfig => ackInvRotaryConfig,
      ackInvRotaryMoveto => ackInvRotaryMoveto,
      ackInvRotarySet => ackInvRotarySet,
      ackInvRotaryZero => ackInvRotaryZero,
      ackInvSet_sig => ackInvSet_sig_1,
      ackInvZero_sig_reg_0 => myHostif_n_287,
      aclk_sig => aclk_sig,
      \capt_reg[5]\ => myHshktrack_n_69,
      ccwNotCw0 => ccwNotCw0,
      ccwNotCw5_in => ccwNotCw5_in,
      ccwNotCw_reg_0(3) => ccwNotCw2(14),
      ccwNotCw_reg_0(2) => myHostif_n_289,
      ccwNotCw_reg_0(1) => myHostif_n_290,
      ccwNotCw_reg_0(0) => myHostif_n_291,
      ccwNotCw_reg_1(2) => myHostif_n_292,
      ccwNotCw_reg_1(1) => myHostif_n_293,
      ccwNotCw_reg_1(0) => myHostif_n_294,
      ccwNotCw_reg_2(0) => myHostif_n_301,
      ccwNotCw_reg_3(2) => myHostif_n_298,
      ccwNotCw_reg_3(1) => myHostif_n_299,
      ccwNotCw_reg_3(0) => myHostif_n_300,
      dir => dir,
      dir_0 => myStepmux_n_1,
      \i__carry_i_11__1_0\(0) => myRotary_n_13,
      \i__carry_i_11__1_1\(7) => myHostif_n_111,
      \i__carry_i_11__1_1\(6) => myHostif_n_112,
      \i__carry_i_11__1_1\(5) => myHostif_n_113,
      \i__carry_i_11__1_1\(4) => myHostif_n_114,
      \i__carry_i_11__1_1\(3) => myHostif_n_115,
      \i__carry_i_11__1_1\(2) => myHostif_n_116,
      \i__carry_i_11__1_1\(1) => myHostif_n_117,
      \i__carry_i_11__1_1\(0) => myHostif_n_118,
      \i_reg[3]_0\ => myHostif_n_283,
      \invbuf_reg[0][5]\(0) => myRotary_n_12,
      \invbuf_reg[0][5]_0\(0) => myRotary_n_14,
      \lsb_reg[1]_0\(1) => myHostif_n_387,
      \lsb_reg[1]_0\(0) => myHostif_n_388,
      m0 => m0,
      m0z => m0z,
      reqInvRotaryConfig => reqInvRotaryConfig,
      reqInvRotaryMoveto => reqInvRotaryMoveto,
      reqInvRotaryZero => reqInvRotaryZero,
      rng_reg_0 => myRotary_n_4,
      rng_reg_1 => myRotary_n_35,
      rng_reg_2 => myHostif_n_93,
      \stateOp_reg[0]_0\(0) => myHostif_n_280,
      \stateOp_reg[1]_0\(1) => rotaryGetInfoTixVState(0),
      \stateOp_reg[1]_0\(0) => myRotary_n_34,
      \stateOp_reg[1]_1\ => myHostif_n_286,
      \stateOp_reg[1]_2\(0) => myHostif_n_284,
      step => step,
      \step1__6\ => \step1__6\,
      step_reg_0(0) => myRotary_n_36,
      targetNotSteady => targetNotSteady,
      \tixVStepmode_reg[0]_0\(0) => reset_reg_n_0,
      \tixVStepmode_reg[7]_0\(7 downto 0) => configHdrNotFix(7 downto 0),
      tkclk => tkclk
    );
myRpuif: entity work.design_1_Vsp_core_0_0_Rpuif
     port map (
      AXIL_arready => rpuAXIL_arready,
      AXIL_awready_sig_reg => rpuAXIL_awready,
      AXIL_bvalid_sig_reg => rpuAXIL_bvalid,
      AXIL_wready_sig_reg => rpuAXIL_wready,
      Q(4 downto 0) => stateOp_7(4 downto 0),
      aclk_sig => aclk_sig,
      \capt_reg[4]\ => myHshktrack_n_70,
      \mask_reg[4]\(0) => myRpuif_n_37,
      \retbuf_reg[0][1]_0\(1 downto 0) => cornerGetInfoTixVState(1 downto 0),
      \retbuf_reg[1][7]_0\(31 downto 0) => cornerGetInfoTkst(31 downto 0),
      \retbuf_reg[5][7]_0\(7 downto 0) => cornerGetInfoScoreMin(7 downto 0),
      \retbuf_reg[6][7]_0\(7 downto 0) => cornerGetInfoScoreMax(7 downto 0),
      rpuAXIL_araddr(1 downto 0) => rpuAXIL_araddr(1 downto 0),
      rpuAXIL_arvalid => rpuAXIL_arvalid,
      rpuAXIL_awaddr(1 downto 0) => rpuAXIL_awaddr(1 downto 0),
      rpuAXIL_awvalid => rpuAXIL_awvalid,
      rpuAXIL_bready => rpuAXIL_bready,
      rpuAXIL_rdata(31 downto 0) => rpuAXIL_rdata(31 downto 0),
      rpuAXIL_rready => rpuAXIL_rready,
      rpuAXIL_rvalid => rpuAXIL_rvalid,
      rpuAXIL_wdata(31 downto 0) => rpuAXIL_wdata(31 downto 0),
      rpuAXIL_wstrb(3 downto 0) => rpuAXIL_wstrb(3 downto 0),
      rpuAXIL_wvalid => rpuAXIL_wvalid,
      \stateOp_reg[0]_0\(0) => reset_reg_n_0,
      tkclk => tkclk
    );
myState: entity work.design_1_Vsp_core_0_0_State
     port map (
      D(3) => myRgbled0_n_8,
      D(2) => myRgbled0_n_9,
      D(1) => myRgbled0_n_10,
      D(0) => myRgbled0_n_11,
      DI(1) => myState_n_11,
      DI(0) => myState_n_12,
      Q(0) => myState_n_3,
      S(1) => myState_n_9,
      S(0) => myState_n_10,
      aclk_sig => aclk_sig,
      \i_reg[0]_0\(0) => i_reg_8(0),
      \i_reg[0]_1\(0) => reset_reg_n_0,
      \i_reg[0]_2\(0) => p_0_in(0),
      \ixSeq_reg[0]_0\(1) => myState_n_4,
      \ixSeq_reg[0]_0\(0) => myState_n_5,
      \ixSeq_reg[1]_0\(1) => myState_n_1,
      \ixSeq_reg[1]_0\(0) => myState_n_2,
      rgb0(1) => rgb0(21),
      rgb0(0) => rgb0(5),
      \seq[1]_2\(0) => \seq[1]_2\(13),
      \seq_reg[0][21]_0\(1) => p_0_in0,
      \seq_reg[0][21]_0\(0) => myHostif_n_385,
      \seq_reg[0][5]_0\(0) => myState_n_6,
      \seq_reg[1][13]_0\(0) => \seq_reg[1]_0\(13),
      \seq_reg[1][13]_1\ => myState_n_13,
      \seq_reg[1][5]_0\ => myDirector_n_17,
      \stateBlue0_inferred__0/i__carry\ => myRgbled0_n_12,
      \stateRed0_inferred__0/i__carry\(3 downto 0) => \sel0__0\(7 downto 4),
      \stateRed0_inferred__0/i__carry_0\ => myRgbled0_n_7,
      stateStats => stateStats,
      tkclk => tkclk
    );
myStepmux: entity work.design_1_Vsp_core_0_0_Stepmux
     port map (
      ackInvStepmuxSet => ackInvStepmuxSet,
      aclk_sig => aclk_sig,
      linNotRot_reg_0 => myStepmux_n_1,
      linNotRot_reg_1 => myHostif_n_15,
      nslp => nslp,
      reqInvStepmuxSet => reqInvStepmuxSet,
      stateOp_reg_0(0) => reset_reg_n_0
    );
myTkclksrc: entity work.design_1_Vsp_core_0_0_Tkclksrc_Easy_v1_0
     port map (
      D(23 downto 16) => configSynthNotLive(7 downto 0),
      D(15 downto 9) => configSynthTFramepad(7 downto 1),
      D(8) => myHostif_n_134,
      D(7 downto 0) => configSynthTLinepad(7 downto 0),
      Q(31 downto 0) => tkclksrcGetTkstTkst(31 downto 0),
      ackInvTkclksrcSetTkst => ackInvTkclksrcSetTkst,
      aclk_sig => aclk_sig,
      reqInvTkclksrcSetTkst => reqInvTkclksrcSetTkst,
      \stateOp_reg[1]_0\ => myHostif_n_19,
      tkclk => tkclk,
      tkclk_sig_reg_0(0) => reset_reg_n_0,
      \tkst_reg[31]_0\(7 downto 0) => configHdrNotFix(7 downto 0)
    );
myTrace: entity work.design_1_Vsp_core_0_0_Trace
     port map (
      Q(1) => avllenFlgbufTraceToHostif(15),
      Q(0) => flgbufTraceToHostifAXIS_tvalid,
      ackFlgbufTraceToHostif => ackFlgbufTraceToHostif,
      ackInvAcquire_sig3_out => ackInvAcquire_sig3_out,
      ackInvConfig_sig => ackInvConfig_sig,
      ackInvTraceAcquire => ackInvTraceAcquire,
      ackInvTraceConfig => ackInvTraceConfig,
      aclk_sig => aclk_sig,
      dneFlgbufTraceToHostif => dneFlgbufTraceToHostif,
      doutb(63 downto 0) => flgbufTraceToHostifAXIS_tdata(63 downto 0),
      flgbufTraceToHostifAXIS_tready => flgbufTraceToHostifAXIS_tready,
      reqFlgbufTraceToHostif => reqFlgbufTraceToHostif,
      reqInvTraceAcquire => reqInvTraceAcquire,
      reqInvTraceConfig => reqInvTraceConfig,
      stateOp5_out => stateOp5_out,
      stateOp_reg_0 => myTrace_n_64,
      \tixVState_reg[0]_0\(0) => reset_reg_n_0,
      traceGetInfoTixVState(0) => traceGetInfoTixVState(0)
    );
myVideoin: entity work.design_1_Vsp_core_0_0_Videoin
     port map (
      DI(3) => myVideoin_n_63,
      DI(2) => myVideoin_n_64,
      DI(1) => myVideoin_n_65,
      DI(0) => myVideoin_n_66,
      E(0) => myCamif_n_85,
      \FSM_sequential_stateRgbegr_reg[2]_0\(2 downto 1) => videoinStateRgbegr_dbg(6 downto 5),
      \FSM_sequential_stateRgbegr_reg[2]_0\(0) => stateRgbegr(0),
      \NColRaw_sig_reg[4]\ => myVideoin_n_165,
      O(7 downto 0) => dwrAccbuf(7 downto 0),
      Q(4) => myVideoin_n_4,
      Q(3) => myVideoin_n_5,
      Q(2) => myVideoin_n_6,
      Q(1) => myVideoin_n_7,
      Q(0) => myVideoin_n_8,
      \abcde_reg[0]_0\(39 downto 32) => grayVideoinToManyAXIS_tdata(59 downto 52),
      \abcde_reg[0]_0\(31 downto 24) => grayVideoinToManyAXIS_tdata(47 downto 40),
      \abcde_reg[0]_0\(23 downto 16) => grayVideoinToManyAXIS_tdata(35 downto 28),
      \abcde_reg[0]_0\(15 downto 8) => grayVideoinToManyAXIS_tdata(23 downto 16),
      \abcde_reg[0]_0\(7 downto 0) => grayVideoinToManyAXIS_tdata(11 downto 4),
      \abcde_reg[0]_1\(44) => myVideoin_n_116,
      \abcde_reg[0]_1\(43) => myVideoin_n_117,
      \abcde_reg[0]_1\(42) => myVideoin_n_118,
      \abcde_reg[0]_1\(41) => myVideoin_n_119,
      \abcde_reg[0]_1\(40) => myVideoin_n_120,
      \abcde_reg[0]_1\(39) => myVideoin_n_121,
      \abcde_reg[0]_1\(38) => myVideoin_n_122,
      \abcde_reg[0]_1\(37) => myVideoin_n_123,
      \abcde_reg[0]_1\(36) => myVideoin_n_124,
      \abcde_reg[0]_1\(35) => myVideoin_n_125,
      \abcde_reg[0]_1\(34) => myVideoin_n_126,
      \abcde_reg[0]_1\(33) => myVideoin_n_127,
      \abcde_reg[0]_1\(32) => myVideoin_n_128,
      \abcde_reg[0]_1\(31) => myVideoin_n_129,
      \abcde_reg[0]_1\(30) => myVideoin_n_130,
      \abcde_reg[0]_1\(29) => myVideoin_n_131,
      \abcde_reg[0]_1\(28) => myVideoin_n_132,
      \abcde_reg[0]_1\(27) => myVideoin_n_133,
      \abcde_reg[0]_1\(26) => myVideoin_n_134,
      \abcde_reg[0]_1\(25) => myVideoin_n_135,
      \abcde_reg[0]_1\(24) => myVideoin_n_136,
      \abcde_reg[0]_1\(23) => myVideoin_n_137,
      \abcde_reg[0]_1\(22) => myVideoin_n_138,
      \abcde_reg[0]_1\(21) => myVideoin_n_139,
      \abcde_reg[0]_1\(20) => myVideoin_n_140,
      \abcde_reg[0]_1\(19) => myVideoin_n_141,
      \abcde_reg[0]_1\(18) => myVideoin_n_142,
      \abcde_reg[0]_1\(17) => myVideoin_n_143,
      \abcde_reg[0]_1\(16) => myVideoin_n_144,
      \abcde_reg[0]_1\(15) => myVideoin_n_145,
      \abcde_reg[0]_1\(14) => myVideoin_n_146,
      \abcde_reg[0]_1\(13) => myVideoin_n_147,
      \abcde_reg[0]_1\(12) => myVideoin_n_148,
      \abcde_reg[0]_1\(11) => myVideoin_n_149,
      \abcde_reg[0]_1\(10) => myVideoin_n_150,
      \abcde_reg[0]_1\(9) => myVideoin_n_151,
      \abcde_reg[0]_1\(8) => myVideoin_n_152,
      \abcde_reg[0]_1\(7) => myVideoin_n_153,
      \abcde_reg[0]_1\(6) => myVideoin_n_154,
      \abcde_reg[0]_1\(5) => myVideoin_n_155,
      \abcde_reg[0]_1\(4) => myVideoin_n_156,
      \abcde_reg[0]_1\(3) => myVideoin_n_157,
      \abcde_reg[0]_1\(2) => myVideoin_n_158,
      \abcde_reg[0]_1\(1) => myVideoin_n_159,
      \abcde_reg[0]_1\(0) => myVideoin_n_160,
      aclk_sig => aclk_sig,
      camifToVideoinAXIS_tdata(23 downto 0) => camifToVideoinAXIS_tdata(23 downto 0),
      camifToVideoinAXIS_tlast => camifToVideoinAXIS_tlast,
      camifToVideoinAXIS_tvalid => camifToVideoinAXIS_tvalid,
      \col_lcl_reg[4]_0\ => myVideoin_n_166,
      \col_lcl_reg[5]_0\ => myVideoin_n_9,
      \col_lcl_reg[5]_1\ => myVideoin_n_13,
      \dwrAccbuf_reg[7]\(7) => myDecim_n_126,
      \dwrAccbuf_reg[7]\(6) => myDecim_n_127,
      \dwrAccbuf_reg[7]\(5) => myDecim_n_128,
      \dwrAccbuf_reg[7]\(4) => myDecim_n_129,
      \dwrAccbuf_reg[7]\(3) => myDecim_n_130,
      \dwrAccbuf_reg[7]\(2) => myDecim_n_131,
      \dwrAccbuf_reg[7]\(1) => myDecim_n_132,
      \dwrAccbuf_reg[7]\(0) => myDecim_n_133,
      \dwrEobuf_reg[36]_0\ => myCamif_n_87,
      \dwrEobuf_reg[56]_0\ => myCamif_n_96,
      \dwrEobuf_reg[57]_0\ => myCamif_n_95,
      \dwrEobuf_reg[58]_0\ => myCamif_n_94,
      \dwrEobuf_reg[59]_0\ => myCamif_n_93,
      \dwrEobuf_reg[60]_0\ => myCamif_n_92,
      \dwrEobuf_reg[61]_0\ => myCamif_n_91,
      \dwrEobuf_reg[62]_0\ => myCamif_n_90,
      \dwrEobuf_reg[63]_0\ => myCamif_n_89,
      \dwrEobuf_reg[63]_1\ => myCamif_n_86,
      \dy_reg[8]\ => myCorner_n_69,
      enAccbuf0 => enAccbuf0,
      enAccbuf1 => enAccbuf1,
      enAccbuf_reg => myDecim_n_68,
      enEobufB_reg_0 => myDirector_n_43,
      enEobufB_reg_1 => myCamif_n_88,
      enRowbufB_lcl_reg_0(0) => reset_reg_n_0,
      enRowbuf_reg_0(10 downto 0) => NColRaw(11 downto 1),
      grayToManyAXIS_tvalid_sig_reg_0 => myVideoin_n_61,
      grayVideoinToManyAXIS_tlast => grayVideoinToManyAXIS_tlast,
      grayVideoinToManyAXIS_tvalid => grayVideoinToManyAXIS_tvalid,
      \klm_reg[0]_0\(0) => klm(0),
      oddNotEven_reg_0 => \^vsync\,
      \rgbToManyAXIS_tdata_sig_reg[35]_0\(35 downto 0) => rgbVideoinToManyAXIS_tdata(35 downto 0),
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(7) => myVideoin_n_17,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(6) => myVideoin_n_18,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(5) => myVideoin_n_19,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(4) => myVideoin_n_20,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(3) => myVideoin_n_21,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(2) => myVideoin_n_22,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(1) => myVideoin_n_23,
      \rgbToManyAXIS_tdata_sig_reg[7]_0\(0) => myVideoin_n_24,
      \rgbToManyAXIS_tdata_sig_reg[7]_1\(0) => myVideoin_n_107,
      rgbToManyAXIS_tlast_sig_reg_0 => \^rgbtomanyaxis_tlast_sig_reg\,
      rgbVideoinToManyAXIS_tvalid => rgbVideoinToManyAXIS_tvalid,
      \stateIgr_reg[1]_0\(1) => videoinStateIgr_dbg(5),
      \stateIgr_reg[1]_0\(0) => stateIgr(0),
      \stateIgr_reg[1]_1\(0) => myCamif_n_84,
      videoinStateIgr_dbg(1) => videoinStateIgr_dbg(4),
      videoinStateIgr_dbg(0) => videoinStateIgr_dbg(0),
      videoinStateRgbegr_dbg(1) => videoinStateRgbegr_dbg(7),
      videoinStateRgbegr_dbg(0) => videoinStateRgbegr_dbg(4)
    );
myVidtrack: entity work.design_1_Vsp_core_0_0_Vidtrack
     port map (
      D(23 downto 16) => configSynthNotLive(7 downto 0),
      D(15 downto 9) => configSynthTFramepad(7 downto 1),
      D(8) => myHostif_n_134,
      D(7 downto 0) => configSynthTLinepad(7 downto 0),
      Q(0) => avllenSeqbufVidtrackToHostif(12),
      \TCaptMax_reg[7]_0\(7 downto 1) => setCoreregVal(15 downto 9),
      \TCaptMax_reg[7]_0\(0) => \^camifsetcoreregval\(8),
      \TCapt_reg[31]_0\(31 downto 0) => vidtrackGetInfoTCapt(31 downto 0),
      ackInvVidtrackSelect => ackInvVidtrackSelect,
      ackInvVidtrackSet => ackInvVidtrackSet,
      ackSeqbufVidtrackToHostif => ackSeqbufVidtrackToHostif,
      aclk_sig => aclk_sig,
      dneSeqbufVidtrackToHostif => dneSeqbufVidtrackToHostif,
      doutb(63 downto 0) => seqbufVidtrackToHostifAXIS_tdata(63 downto 0),
      first_reg_0(0) => reset_reg_n_0,
      hdrNotFix => hdrNotFix,
      reqInvVidtrackSelect => reqInvVidtrackSelect,
      reqInvVidtrackSet => reqInvVidtrackSet,
      reqSeqbufVidtrackToHostif => reqSeqbufVidtrackToHostif,
      restart_reg_0 => myHostif_n_254,
      seqbufVidtrackToHostifAXIS_tready => seqbufVidtrackToHostifAXIS_tready,
      seqbufVidtrackToHostifAXIS_tvalid => seqbufVidtrackToHostifAXIS_tvalid,
      \state_reg[0]_0\ => myDecim_n_87,
      \state_reg[4]_0\ => myDecim_n_88,
      \state_reg[5]_0\(1 downto 0) => decimStateStore_dbg(5 downto 4),
      \state_reg[5]_1\ => myDecim_n_89,
      \state_reg[7]_0\(0) => decimStateStream_dbg(3),
      \tixVCapture_reg[1]_0\(1) => myVidtrack_n_113,
      \tixVCapture_reg[1]_0\(0) => myVidtrack_n_114,
      \tixVCapture_reg[7]_0\(7 downto 0) => configHdrNotFix(7 downto 0),
      videoinStateIgr_dbg(1) => videoinStateIgr_dbg(4),
      videoinStateIgr_dbg(0) => videoinStateIgr_dbg(0),
      videoinStateRgbegr_dbg(1 downto 0) => videoinStateRgbegr_dbg(7 downto 6),
      vidtrackGetInfoPtr0Seqbuf(9 downto 0) => vidtrackGetInfoPtr0Seqbuf(9 downto 0),
      vidtrackGetInfoTixVState(1 downto 0) => vidtrackGetInfoTixVState(1 downto 0)
    );
resetMemclk_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEC0"
    )
        port map (
      I0 => resetMemclk_i_2_n_0,
      I1 => reset_memclk,
      I2 => stateMemclk_reg_n_0,
      I3 => resetMemclk,
      O => resetMemclk_i_1_n_0
    );
resetMemclk_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFFFFFF"
    )
        port map (
      I0 => \i_reg_n_0_[4]\,
      I1 => \i_reg_n_0_[2]\,
      I2 => \i_reg_n_0_[3]\,
      I3 => \i_reg_n_0_[1]\,
      I4 => \i_reg_n_0_[0]\,
      O => resetMemclk_i_2_n_0
    );
resetMemclk_reg: unisim.vcomponents.FDPE
     port map (
      C => memclk,
      CE => '1',
      D => resetMemclk_i_1_n_0,
      PRE => reset_to_memclkm1_i_1_n_0,
      Q => resetMemclk
    );
reset_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => i_reg(0),
      I1 => i_reg(1),
      I2 => i_reg(3),
      I3 => i_reg(2),
      O => reset_i_2_n_0
    );
reset_memclk_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => reset_to_memclkm2,
      I1 => reset_to_memclkm1,
      I2 => reset_memclk,
      O => reset_memclk_i_1_n_0
    );
reset_memclk_reg: unisim.vcomponents.FDPE
     port map (
      C => memclk,
      CE => '1',
      D => reset_memclk_i_1_n_0,
      PRE => reset_to_memclkm1_i_1_n_0,
      Q => reset_memclk
    );
reset_reg: unisim.vcomponents.FDPE
     port map (
      C => aclk_sig,
      CE => '1',
      D => myHostif_n_17,
      PRE => reset_to_memclkm1_i_1_n_0,
      Q => reset_reg_n_0
    );
reset_to_memclkm1_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => aresetn,
      O => reset_to_memclkm1_i_1_n_0
    );
reset_to_memclkm1_reg: unisim.vcomponents.FDPE
     port map (
      C => memclk,
      CE => '1',
      D => reset_reg_n_0,
      PRE => reset_to_memclkm1_i_1_n_0,
      Q => reset_to_memclkm1
    );
reset_to_memclkm2_reg: unisim.vcomponents.FDPE
     port map (
      C => memclk,
      CE => '1',
      D => reset_to_memclkm1,
      PRE => reset_to_memclkm1_i_1_n_0,
      Q => reset_to_memclkm2
    );
stateMclk_reg: unisim.vcomponents.FDCE
     port map (
      C => aclk_sig,
      CE => '1',
      CLR => reset_to_memclkm1_i_1_n_0,
      D => myHostif_n_18,
      Q => stateMclk
    );
stateMemclk_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF0400"
    )
        port map (
      I0 => \i[4]_i_3__0_n_0\,
      I1 => \i_reg_n_0_[3]\,
      I2 => \i_reg_n_0_[2]\,
      I3 => \i_reg_n_0_[4]\,
      I4 => stateMemclk_reg_n_0,
      I5 => reset_memclk,
      O => stateMemclk_i_1_n_0
    );
stateMemclk_reg: unisim.vcomponents.FDCE
     port map (
      C => memclk,
      CE => '1',
      CLR => reset_to_memclkm1_i_1_n_0,
      D => stateMemclk_i_1_n_0,
      Q => stateMemclk_reg_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_Vsp_core_0_0 is
  port (
    aresetn : in STD_LOGIC;
    aclk : in STD_LOGIC;
    memclk : in STD_LOGIC;
    apuAXIL_araddr : in STD_LOGIC_VECTOR ( 39 downto 0 );
    apuAXIL_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    apuAXIL_arready : out STD_LOGIC;
    apuAXIL_arvalid : in STD_LOGIC;
    apuAXIL_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    apuAXIL_rready : in STD_LOGIC;
    apuAXIL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    apuAXIL_rvalid : out STD_LOGIC;
    apuAXIL_rlast : out STD_LOGIC;
    apuAXIL_awaddr : in STD_LOGIC_VECTOR ( 39 downto 0 );
    apuAXIL_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    apuAXIL_awready : out STD_LOGIC;
    apuAXIL_awvalid : in STD_LOGIC;
    apuAXIL_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    apuAXIL_wready : out STD_LOGIC;
    apuAXIL_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
    apuAXIL_wvalid : in STD_LOGIC;
    apuAXIL_bready : in STD_LOGIC;
    apuAXIL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    apuAXIL_bvalid : out STD_LOGIC;
    rpuAXIL_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    rpuAXIL_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    rpuAXIL_arready : out STD_LOGIC;
    rpuAXIL_arvalid : in STD_LOGIC;
    rpuAXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    rpuAXIL_rready : in STD_LOGIC;
    rpuAXIL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rpuAXIL_rvalid : out STD_LOGIC;
    rpuAXIL_rlast : out STD_LOGIC;
    rpuAXIL_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    rpuAXIL_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    rpuAXIL_awready : out STD_LOGIC;
    rpuAXIL_awvalid : in STD_LOGIC;
    rpuAXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    rpuAXIL_wready : out STD_LOGIC;
    rpuAXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rpuAXIL_wvalid : in STD_LOGIC;
    rpuAXIL_bready : in STD_LOGIC;
    rpuAXIL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rpuAXIL_bvalid : out STD_LOGIC;
    ddrAXI_rready : out STD_LOGIC;
    ddrAXI_wvalid : out STD_LOGIC;
    probe : out STD_LOGIC_VECTOR ( 5 downto 0 );
    scl : inout STD_LOGIC;
    sda : inout STD_LOGIC;
    csi_clk_p : in STD_LOGIC;
    csi_clk_n : in STD_LOGIC;
    csi_d0_p : in STD_LOGIC;
    csi_d0_n : in STD_LOGIC;
    csi_d1_p : in STD_LOGIC;
    csi_d1_n : in STD_LOGIC;
    csi_d2_p : in STD_LOGIC;
    csi_d2_n : in STD_LOGIC;
    csi_d3_p : in STD_LOGIC;
    csi_d3_n : in STD_LOGIC;
    ddrAXI_arid : out STD_LOGIC_VECTOR ( 5 downto 0 );
    ddrAXI_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
    ddrAXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddrAXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ddrAXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ddrAXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddrAXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddrAXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ddrAXI_arready : in STD_LOGIC;
    ddrAXI_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ddrAXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddrAXI_arvalid : out STD_LOGIC;
    ddrAXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ddrAXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    ddrAXI_rlast : in STD_LOGIC;
    ddrAXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ddrAXI_rvalid : in STD_LOGIC;
    ddrAXI_awid : out STD_LOGIC_VECTOR ( 5 downto 0 );
    ddrAXI_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
    ddrAXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ddrAXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ddrAXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ddrAXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    ddrAXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddrAXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ddrAXI_awready : in STD_LOGIC;
    ddrAXI_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ddrAXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ddrAXI_awvalid : out STD_LOGIC;
    ddrAXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    ddrAXI_wlast : out STD_LOGIC;
    ddrAXI_wready : in STD_LOGIC;
    ddrAXI_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
    ddrAXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ddrAXI_bready : out STD_LOGIC;
    ddrAXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ddrAXI_bvalid : in STD_LOGIC;
    cs : out STD_LOGIC;
    sclk : out STD_LOGIC;
    mosi : out STD_LOGIC;
    rgb0_r : out STD_LOGIC;
    rgb0_g : out STD_LOGIC;
    rgb0_b : out STD_LOGIC;
    rgb1_r : out STD_LOGIC;
    rgb1_g : out STD_LOGIC;
    rgb1_b : out STD_LOGIC;
    nslp : out STD_LOGIC;
    m0 : out STD_LOGIC;
    m0z : out STD_LOGIC;
    m1 : out STD_LOGIC;
    m1z : out STD_LOGIC;
    dir : out STD_LOGIC;
    step : out STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of design_1_Vsp_core_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_Vsp_core_0_0 : entity is "design_1_Vsp_core_0_0,Vsp_core,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_Vsp_core_0_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of design_1_Vsp_core_0_0 : entity is "package_project";
  attribute x_core_info : string;
  attribute x_core_info of design_1_Vsp_core_0_0 : entity is "Vsp_core,Vivado 2024.2";
end design_1_Vsp_core_0_0;

architecture STRUCTURE of design_1_Vsp_core_0_0 is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal U0_n_118 : STD_LOGIC;
  signal U0_n_119 : STD_LOGIC;
  signal U0_n_120 : STD_LOGIC;
  signal U0_n_121 : STD_LOGIC;
  signal U0_n_122 : STD_LOGIC;
  signal U0_n_123 : STD_LOGIC;
  signal U0_n_124 : STD_LOGIC;
  signal U0_n_125 : STD_LOGIC;
  signal \^ddraxi_araddr\ : STD_LOGIC_VECTOR ( 29 downto 8 );
  signal \^ddraxi_arready\ : STD_LOGIC;
  signal \^ddraxi_awaddr\ : STD_LOGIC_VECTOR ( 29 downto 8 );
  signal \myDecim/decimLast_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \myDecim/decimLast_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \myDecim/decimLast_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \myDecim/decimLast_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \myDecim/decimLast_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \myDecim/decimLast_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \myDecim/decimLast_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \myDecim/decimLast_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \myDecim/minusOp\ : STD_LOGIC_VECTOR ( 8 downto 1 );
  signal \^probe\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal setCoreregVal : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \myDecim/decimLast_reg[8]_i_1\ : label is 35;
  attribute x_interface_info : string;
  attribute x_interface_info of aclk : signal is "xilinx.com:signal:clock:1.0 aclk CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of aclk : signal is "slave aclk";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of aclk : signal is "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF apuAXIL:rpuAXIL, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk0, INSERT_VIP 0";
  attribute x_interface_info of apuAXIL_arready : signal is "xilinx.com:interface:aximm:1.0 apuAXIL ARREADY";
  attribute x_interface_info of apuAXIL_arvalid : signal is "xilinx.com:interface:aximm:1.0 apuAXIL ARVALID";
  attribute x_interface_info of apuAXIL_awready : signal is "xilinx.com:interface:aximm:1.0 apuAXIL AWREADY";
  attribute x_interface_info of apuAXIL_awvalid : signal is "xilinx.com:interface:aximm:1.0 apuAXIL AWVALID";
  attribute x_interface_info of apuAXIL_bready : signal is "xilinx.com:interface:aximm:1.0 apuAXIL BREADY";
  attribute x_interface_info of apuAXIL_bvalid : signal is "xilinx.com:interface:aximm:1.0 apuAXIL BVALID";
  attribute x_interface_info of apuAXIL_rlast : signal is "xilinx.com:interface:aximm:1.0 apuAXIL RLAST";
  attribute x_interface_info of apuAXIL_rready : signal is "xilinx.com:interface:aximm:1.0 apuAXIL RREADY";
  attribute x_interface_info of apuAXIL_rvalid : signal is "xilinx.com:interface:aximm:1.0 apuAXIL RVALID";
  attribute x_interface_info of apuAXIL_wready : signal is "xilinx.com:interface:aximm:1.0 apuAXIL WREADY";
  attribute x_interface_info of apuAXIL_wvalid : signal is "xilinx.com:interface:aximm:1.0 apuAXIL WVALID";
  attribute x_interface_info of aresetn : signal is "xilinx.com:signal:reset:1.0 aresetn RST";
  attribute x_interface_mode of aresetn : signal is "slave aresetn";
  attribute x_interface_parameter of aresetn : signal is "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute x_interface_info of csi_clk_n : signal is "xilinx.com:signal:clock:1.0 csi_clk_n CLK";
  attribute x_interface_mode of csi_clk_n : signal is "slave csi_clk_n";
  attribute x_interface_parameter of csi_clk_n : signal is "XIL_INTERFACENAME csi_clk_n, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_csi_clk_n_0, INSERT_VIP 0";
  attribute x_interface_info of csi_clk_p : signal is "xilinx.com:signal:clock:1.0 csi_clk_p CLK";
  attribute x_interface_mode of csi_clk_p : signal is "slave csi_clk_p";
  attribute x_interface_parameter of csi_clk_p : signal is "XIL_INTERFACENAME csi_clk_p, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_csi_clk_p_0, INSERT_VIP 0";
  attribute x_interface_info of ddrAXI_arready : signal is "xilinx.com:interface:aximm:1.0 ddrAXI ARREADY";
  attribute x_interface_info of ddrAXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 ddrAXI ARVALID";
  attribute x_interface_info of ddrAXI_awready : signal is "xilinx.com:interface:aximm:1.0 ddrAXI AWREADY";
  attribute x_interface_info of ddrAXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 ddrAXI AWVALID";
  attribute x_interface_info of ddrAXI_bready : signal is "xilinx.com:interface:aximm:1.0 ddrAXI BREADY";
  attribute x_interface_info of ddrAXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 ddrAXI BVALID";
  attribute x_interface_info of ddrAXI_rlast : signal is "xilinx.com:interface:aximm:1.0 ddrAXI RLAST";
  attribute x_interface_info of ddrAXI_rready : signal is "xilinx.com:interface:aximm:1.0 ddrAXI RREADY";
  attribute x_interface_mode of ddrAXI_rready : signal is "master ddrAXI";
  attribute x_interface_parameter of ddrAXI_rready : signal is "XIL_INTERFACENAME ddrAXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 325000000, ID_WIDTH 6, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute x_interface_info of ddrAXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 ddrAXI RVALID";
  attribute x_interface_info of ddrAXI_wlast : signal is "xilinx.com:interface:aximm:1.0 ddrAXI WLAST";
  attribute x_interface_info of ddrAXI_wready : signal is "xilinx.com:interface:aximm:1.0 ddrAXI WREADY";
  attribute x_interface_info of ddrAXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 ddrAXI WVALID";
  attribute x_interface_info of memclk : signal is "xilinx.com:signal:clock:1.0 memclk CLK";
  attribute x_interface_mode of memclk : signal is "slave memclk";
  attribute x_interface_parameter of memclk : signal is "XIL_INTERFACENAME memclk, ASSOCIATED_BUSIF ddrAXI, FREQ_HZ 325000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk1, INSERT_VIP 0";
  attribute x_interface_info of rpuAXIL_arready : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL ARREADY";
  attribute x_interface_info of rpuAXIL_arvalid : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL ARVALID";
  attribute x_interface_info of rpuAXIL_awready : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL AWREADY";
  attribute x_interface_info of rpuAXIL_awvalid : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL AWVALID";
  attribute x_interface_info of rpuAXIL_bready : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL BREADY";
  attribute x_interface_info of rpuAXIL_bvalid : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL BVALID";
  attribute x_interface_info of rpuAXIL_rlast : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL RLAST";
  attribute x_interface_info of rpuAXIL_rready : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL RREADY";
  attribute x_interface_info of rpuAXIL_rvalid : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL RVALID";
  attribute x_interface_info of rpuAXIL_wready : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL WREADY";
  attribute x_interface_info of rpuAXIL_wvalid : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL WVALID";
  attribute x_interface_info of apuAXIL_araddr : signal is "xilinx.com:interface:aximm:1.0 apuAXIL ARADDR";
  attribute x_interface_mode of apuAXIL_araddr : signal is "slave apuAXIL";
  attribute x_interface_parameter of apuAXIL_araddr : signal is "XIL_INTERFACENAME apuAXIL, DATA_WIDTH 64, PROTOCOL AXI4LITE, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute x_interface_info of apuAXIL_arprot : signal is "xilinx.com:interface:aximm:1.0 apuAXIL ARPROT";
  attribute x_interface_info of apuAXIL_awaddr : signal is "xilinx.com:interface:aximm:1.0 apuAXIL AWADDR";
  attribute x_interface_info of apuAXIL_awprot : signal is "xilinx.com:interface:aximm:1.0 apuAXIL AWPROT";
  attribute x_interface_info of apuAXIL_bresp : signal is "xilinx.com:interface:aximm:1.0 apuAXIL BRESP";
  attribute x_interface_info of apuAXIL_rdata : signal is "xilinx.com:interface:aximm:1.0 apuAXIL RDATA";
  attribute x_interface_info of apuAXIL_rresp : signal is "xilinx.com:interface:aximm:1.0 apuAXIL RRESP";
  attribute x_interface_info of apuAXIL_wdata : signal is "xilinx.com:interface:aximm:1.0 apuAXIL WDATA";
  attribute x_interface_info of apuAXIL_wstrb : signal is "xilinx.com:interface:aximm:1.0 apuAXIL WSTRB";
  attribute x_interface_info of ddrAXI_araddr : signal is "xilinx.com:interface:aximm:1.0 ddrAXI ARADDR";
  attribute x_interface_info of ddrAXI_arburst : signal is "xilinx.com:interface:aximm:1.0 ddrAXI ARBURST";
  attribute x_interface_info of ddrAXI_arcache : signal is "xilinx.com:interface:aximm:1.0 ddrAXI ARCACHE";
  attribute x_interface_info of ddrAXI_arid : signal is "xilinx.com:interface:aximm:1.0 ddrAXI ARID";
  attribute x_interface_info of ddrAXI_arlen : signal is "xilinx.com:interface:aximm:1.0 ddrAXI ARLEN";
  attribute x_interface_info of ddrAXI_arlock : signal is "xilinx.com:interface:aximm:1.0 ddrAXI ARLOCK";
  attribute x_interface_info of ddrAXI_arprot : signal is "xilinx.com:interface:aximm:1.0 ddrAXI ARPROT";
  attribute x_interface_info of ddrAXI_arqos : signal is "xilinx.com:interface:aximm:1.0 ddrAXI ARQOS";
  attribute x_interface_info of ddrAXI_arregion : signal is "xilinx.com:interface:aximm:1.0 ddrAXI ARREGION";
  attribute x_interface_info of ddrAXI_arsize : signal is "xilinx.com:interface:aximm:1.0 ddrAXI ARSIZE";
  attribute x_interface_info of ddrAXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 ddrAXI AWADDR";
  attribute x_interface_info of ddrAXI_awburst : signal is "xilinx.com:interface:aximm:1.0 ddrAXI AWBURST";
  attribute x_interface_info of ddrAXI_awcache : signal is "xilinx.com:interface:aximm:1.0 ddrAXI AWCACHE";
  attribute x_interface_info of ddrAXI_awid : signal is "xilinx.com:interface:aximm:1.0 ddrAXI AWID";
  attribute x_interface_info of ddrAXI_awlen : signal is "xilinx.com:interface:aximm:1.0 ddrAXI AWLEN";
  attribute x_interface_info of ddrAXI_awlock : signal is "xilinx.com:interface:aximm:1.0 ddrAXI AWLOCK";
  attribute x_interface_info of ddrAXI_awprot : signal is "xilinx.com:interface:aximm:1.0 ddrAXI AWPROT";
  attribute x_interface_info of ddrAXI_awqos : signal is "xilinx.com:interface:aximm:1.0 ddrAXI AWQOS";
  attribute x_interface_info of ddrAXI_awregion : signal is "xilinx.com:interface:aximm:1.0 ddrAXI AWREGION";
  attribute x_interface_info of ddrAXI_awsize : signal is "xilinx.com:interface:aximm:1.0 ddrAXI AWSIZE";
  attribute x_interface_info of ddrAXI_bid : signal is "xilinx.com:interface:aximm:1.0 ddrAXI BID";
  attribute x_interface_info of ddrAXI_bresp : signal is "xilinx.com:interface:aximm:1.0 ddrAXI BRESP";
  attribute x_interface_info of ddrAXI_rdata : signal is "xilinx.com:interface:aximm:1.0 ddrAXI RDATA";
  attribute x_interface_info of ddrAXI_rid : signal is "xilinx.com:interface:aximm:1.0 ddrAXI RID";
  attribute x_interface_info of ddrAXI_rresp : signal is "xilinx.com:interface:aximm:1.0 ddrAXI RRESP";
  attribute x_interface_info of ddrAXI_wdata : signal is "xilinx.com:interface:aximm:1.0 ddrAXI WDATA";
  attribute x_interface_info of ddrAXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 ddrAXI WSTRB";
  attribute x_interface_info of rpuAXIL_araddr : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL ARADDR";
  attribute x_interface_mode of rpuAXIL_araddr : signal is "slave rpuAXIL";
  attribute x_interface_parameter of rpuAXIL_araddr : signal is "XIL_INTERFACENAME rpuAXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute x_interface_info of rpuAXIL_arprot : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL ARPROT";
  attribute x_interface_info of rpuAXIL_awaddr : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL AWADDR";
  attribute x_interface_info of rpuAXIL_awprot : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL AWPROT";
  attribute x_interface_info of rpuAXIL_bresp : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL BRESP";
  attribute x_interface_info of rpuAXIL_rdata : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL RDATA";
  attribute x_interface_info of rpuAXIL_rresp : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL RRESP";
  attribute x_interface_info of rpuAXIL_wdata : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL WDATA";
  attribute x_interface_info of rpuAXIL_wstrb : signal is "xilinx.com:interface:aximm:1.0 rpuAXIL WSTRB";
begin
  \^ddraxi_arready\ <= ddrAXI_arready;
  apuAXIL_bresp(1) <= \<const0>\;
  apuAXIL_bresp(0) <= \<const0>\;
  apuAXIL_rlast <= \<const1>\;
  apuAXIL_rresp(1) <= \<const0>\;
  apuAXIL_rresp(0) <= \<const0>\;
  ddrAXI_araddr(39) <= \<const0>\;
  ddrAXI_araddr(38) <= \<const0>\;
  ddrAXI_araddr(37) <= \<const0>\;
  ddrAXI_araddr(36) <= \<const0>\;
  ddrAXI_araddr(35) <= \<const0>\;
  ddrAXI_araddr(34) <= \<const0>\;
  ddrAXI_araddr(33) <= \<const0>\;
  ddrAXI_araddr(32) <= \<const0>\;
  ddrAXI_araddr(31) <= \<const0>\;
  ddrAXI_araddr(30) <= \<const0>\;
  ddrAXI_araddr(29) <= \^ddraxi_araddr\(29);
  ddrAXI_araddr(28) <= \^ddraxi_araddr\(29);
  ddrAXI_araddr(27 downto 8) <= \^ddraxi_araddr\(27 downto 8);
  ddrAXI_araddr(7) <= \<const0>\;
  ddrAXI_araddr(6) <= \<const0>\;
  ddrAXI_araddr(5) <= \<const0>\;
  ddrAXI_araddr(4) <= \<const0>\;
  ddrAXI_araddr(3) <= \<const0>\;
  ddrAXI_araddr(2) <= \<const0>\;
  ddrAXI_araddr(1) <= \<const0>\;
  ddrAXI_araddr(0) <= \<const0>\;
  ddrAXI_arburst(1) <= \<const0>\;
  ddrAXI_arburst(0) <= \<const1>\;
  ddrAXI_arcache(3) <= \<const0>\;
  ddrAXI_arcache(2) <= \<const0>\;
  ddrAXI_arcache(1) <= \<const0>\;
  ddrAXI_arcache(0) <= \<const0>\;
  ddrAXI_arid(5) <= \<const0>\;
  ddrAXI_arid(4) <= \<const0>\;
  ddrAXI_arid(3) <= \<const0>\;
  ddrAXI_arid(2) <= \<const0>\;
  ddrAXI_arid(1) <= \<const0>\;
  ddrAXI_arid(0) <= \<const0>\;
  ddrAXI_arlen(7) <= \<const0>\;
  ddrAXI_arlen(6) <= \<const0>\;
  ddrAXI_arlen(5) <= \<const0>\;
  ddrAXI_arlen(4) <= \<const0>\;
  ddrAXI_arlen(3) <= \<const1>\;
  ddrAXI_arlen(2) <= \<const1>\;
  ddrAXI_arlen(1) <= \<const1>\;
  ddrAXI_arlen(0) <= \<const1>\;
  ddrAXI_arlock(0) <= \<const0>\;
  ddrAXI_arprot(2) <= \<const0>\;
  ddrAXI_arprot(1) <= \<const1>\;
  ddrAXI_arprot(0) <= \<const0>\;
  ddrAXI_arqos(3) <= \<const1>\;
  ddrAXI_arqos(2) <= \<const1>\;
  ddrAXI_arqos(1) <= \<const0>\;
  ddrAXI_arqos(0) <= \<const1>\;
  ddrAXI_arregion(3) <= \<const0>\;
  ddrAXI_arregion(2) <= \<const0>\;
  ddrAXI_arregion(1) <= \<const0>\;
  ddrAXI_arregion(0) <= \<const0>\;
  ddrAXI_arsize(2) <= \<const1>\;
  ddrAXI_arsize(1) <= \<const0>\;
  ddrAXI_arsize(0) <= \<const0>\;
  ddrAXI_awaddr(39) <= \<const0>\;
  ddrAXI_awaddr(38) <= \<const0>\;
  ddrAXI_awaddr(37) <= \<const0>\;
  ddrAXI_awaddr(36) <= \<const0>\;
  ddrAXI_awaddr(35) <= \<const0>\;
  ddrAXI_awaddr(34) <= \<const0>\;
  ddrAXI_awaddr(33) <= \<const0>\;
  ddrAXI_awaddr(32) <= \<const0>\;
  ddrAXI_awaddr(31) <= \<const0>\;
  ddrAXI_awaddr(30) <= \<const0>\;
  ddrAXI_awaddr(29) <= \^ddraxi_awaddr\(29);
  ddrAXI_awaddr(28) <= \^ddraxi_awaddr\(29);
  ddrAXI_awaddr(27 downto 8) <= \^ddraxi_awaddr\(27 downto 8);
  ddrAXI_awaddr(7) <= \<const0>\;
  ddrAXI_awaddr(6) <= \<const0>\;
  ddrAXI_awaddr(5) <= \<const0>\;
  ddrAXI_awaddr(4) <= \<const0>\;
  ddrAXI_awaddr(3) <= \<const0>\;
  ddrAXI_awaddr(2) <= \<const0>\;
  ddrAXI_awaddr(1) <= \<const0>\;
  ddrAXI_awaddr(0) <= \<const0>\;
  ddrAXI_awburst(1) <= \<const0>\;
  ddrAXI_awburst(0) <= \<const1>\;
  ddrAXI_awcache(3) <= \<const0>\;
  ddrAXI_awcache(2) <= \<const0>\;
  ddrAXI_awcache(1) <= \<const0>\;
  ddrAXI_awcache(0) <= \<const0>\;
  ddrAXI_awid(5) <= \<const0>\;
  ddrAXI_awid(4) <= \<const0>\;
  ddrAXI_awid(3) <= \<const0>\;
  ddrAXI_awid(2) <= \<const0>\;
  ddrAXI_awid(1) <= \<const0>\;
  ddrAXI_awid(0) <= \<const0>\;
  ddrAXI_awlen(7) <= \<const0>\;
  ddrAXI_awlen(6) <= \<const0>\;
  ddrAXI_awlen(5) <= \<const0>\;
  ddrAXI_awlen(4) <= \<const0>\;
  ddrAXI_awlen(3) <= \<const1>\;
  ddrAXI_awlen(2) <= \<const1>\;
  ddrAXI_awlen(1) <= \<const1>\;
  ddrAXI_awlen(0) <= \<const1>\;
  ddrAXI_awlock(0) <= \<const0>\;
  ddrAXI_awprot(2) <= \<const0>\;
  ddrAXI_awprot(1) <= \<const1>\;
  ddrAXI_awprot(0) <= \<const0>\;
  ddrAXI_awqos(3) <= \<const1>\;
  ddrAXI_awqos(2) <= \<const1>\;
  ddrAXI_awqos(1) <= \<const0>\;
  ddrAXI_awqos(0) <= \<const1>\;
  ddrAXI_awregion(3) <= \<const0>\;
  ddrAXI_awregion(2) <= \<const0>\;
  ddrAXI_awregion(1) <= \<const0>\;
  ddrAXI_awregion(0) <= \<const0>\;
  ddrAXI_awsize(2) <= \<const1>\;
  ddrAXI_awsize(1) <= \<const0>\;
  ddrAXI_awsize(0) <= \<const0>\;
  ddrAXI_wstrb(15) <= \<const1>\;
  ddrAXI_wstrb(14) <= \<const1>\;
  ddrAXI_wstrb(13) <= \<const1>\;
  ddrAXI_wstrb(12) <= \<const1>\;
  ddrAXI_wstrb(11) <= \<const1>\;
  ddrAXI_wstrb(10) <= \<const1>\;
  ddrAXI_wstrb(9) <= \<const1>\;
  ddrAXI_wstrb(8) <= \<const1>\;
  ddrAXI_wstrb(7) <= \<const1>\;
  ddrAXI_wstrb(6) <= \<const1>\;
  ddrAXI_wstrb(5) <= \<const1>\;
  ddrAXI_wstrb(4) <= \<const1>\;
  ddrAXI_wstrb(3) <= \<const1>\;
  ddrAXI_wstrb(2) <= \<const1>\;
  ddrAXI_wstrb(1) <= \<const1>\;
  ddrAXI_wstrb(0) <= \<const1>\;
  m1 <= \<const0>\;
  m1z <= \<const0>\;
  probe(5) <= \^probe\(5);
  probe(4) <= \^ddraxi_arready\;
  probe(3 downto 0) <= \^probe\(3 downto 0);
  rgb1_b <= \<const0>\;
  rgb1_g <= \<const0>\;
  rgb1_r <= \<const0>\;
  rpuAXIL_bresp(1) <= \<const0>\;
  rpuAXIL_bresp(0) <= \<const0>\;
  rpuAXIL_rlast <= \<const1>\;
  rpuAXIL_rresp(1) <= \<const0>\;
  rpuAXIL_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.design_1_Vsp_core_0_0_Vsp_core
     port map (
      CO(0) => \myDecim/decimLast_reg[8]_i_1_n_0\,
      D(7 downto 0) => \myDecim/minusOp\(8 downto 1),
      S(7) => U0_n_118,
      S(6) => U0_n_119,
      S(5) => U0_n_120,
      S(4) => U0_n_121,
      S(3) => U0_n_122,
      S(2) => U0_n_123,
      S(1) => U0_n_124,
      S(0) => U0_n_125,
      aclk => aclk,
      apuAXIL_araddr(1 downto 0) => apuAXIL_araddr(5 downto 4),
      apuAXIL_arready => apuAXIL_arready,
      apuAXIL_arvalid => apuAXIL_arvalid,
      apuAXIL_awaddr(1 downto 0) => apuAXIL_awaddr(5 downto 4),
      apuAXIL_awready => apuAXIL_awready,
      apuAXIL_awvalid => apuAXIL_awvalid,
      apuAXIL_bready => apuAXIL_bready,
      apuAXIL_bvalid => apuAXIL_bvalid,
      apuAXIL_rdata(63 downto 0) => apuAXIL_rdata(63 downto 0),
      apuAXIL_rready => apuAXIL_rready,
      apuAXIL_rvalid => apuAXIL_rvalid,
      apuAXIL_wdata(63 downto 0) => apuAXIL_wdata(63 downto 0),
      apuAXIL_wready => apuAXIL_wready,
      apuAXIL_wstrb(7 downto 0) => apuAXIL_wstrb(7 downto 0),
      apuAXIL_wvalid => apuAXIL_wvalid,
      aresetn => aresetn,
      camifSetCoreregVal(8 downto 0) => setCoreregVal(8 downto 0),
      cs => cs,
      csi_clk_n => csi_clk_n,
      csi_clk_p => csi_clk_p,
      ddrAXI_araddr(20) => \^ddraxi_araddr\(29),
      ddrAXI_araddr(19 downto 0) => \^ddraxi_araddr\(27 downto 8),
      ddrAXI_arready => \^ddraxi_arready\,
      ddrAXI_arvalid => ddrAXI_arvalid,
      ddrAXI_awaddr(20) => \^ddraxi_awaddr\(29),
      ddrAXI_awaddr(19 downto 0) => \^ddraxi_awaddr\(27 downto 8),
      ddrAXI_awready => ddrAXI_awready,
      ddrAXI_awvalid => ddrAXI_awvalid,
      ddrAXI_bready => ddrAXI_bready,
      ddrAXI_bvalid => ddrAXI_bvalid,
      ddrAXI_rdata(127 downto 0) => ddrAXI_rdata(127 downto 0),
      ddrAXI_rlast => ddrAXI_rlast,
      ddrAXI_rready => ddrAXI_rready,
      ddrAXI_rvalid => ddrAXI_rvalid,
      ddrAXI_wdata(127 downto 0) => ddrAXI_wdata(127 downto 0),
      ddrAXI_wlast => ddrAXI_wlast,
      ddrAXI_wready => ddrAXI_wready,
      ddrAXI_wvalid => ddrAXI_wvalid,
      dir => dir,
      m0 => m0,
      m0z => m0z,
      memclk => memclk,
      mipi_phy_if_data_n(3) => csi_d3_n,
      mipi_phy_if_data_n(2) => csi_d2_n,
      mipi_phy_if_data_n(1) => csi_d1_n,
      mipi_phy_if_data_n(0) => csi_d0_n,
      mipi_phy_if_data_p(3) => csi_d3_p,
      mipi_phy_if_data_p(2) => csi_d2_p,
      mipi_phy_if_data_p(1) => csi_d1_p,
      mipi_phy_if_data_p(0) => csi_d0_p,
      mosi => mosi,
      nslp => nslp,
      probe(2) => \^probe\(5),
      probe(1 downto 0) => \^probe\(3 downto 2),
      rgb0_b => rgb0_b,
      rgb0_g => rgb0_g,
      rgb0_r => rgb0_r,
      rgbToManyAXIS_tlast_sig_reg => \^probe\(1),
      rpuAXIL_araddr(1 downto 0) => rpuAXIL_araddr(5 downto 4),
      rpuAXIL_arready => rpuAXIL_arready,
      rpuAXIL_arvalid => rpuAXIL_arvalid,
      rpuAXIL_awaddr(1 downto 0) => rpuAXIL_awaddr(5 downto 4),
      rpuAXIL_awready => rpuAXIL_awready,
      rpuAXIL_awvalid => rpuAXIL_awvalid,
      rpuAXIL_bready => rpuAXIL_bready,
      rpuAXIL_bvalid => rpuAXIL_bvalid,
      rpuAXIL_rdata(31 downto 0) => rpuAXIL_rdata(31 downto 0),
      rpuAXIL_rready => rpuAXIL_rready,
      rpuAXIL_rvalid => rpuAXIL_rvalid,
      rpuAXIL_wdata(31 downto 0) => rpuAXIL_wdata(31 downto 0),
      rpuAXIL_wready => rpuAXIL_wready,
      rpuAXIL_wstrb(3 downto 0) => rpuAXIL_wstrb(3 downto 0),
      rpuAXIL_wvalid => rpuAXIL_wvalid,
      scl => scl,
      sclk => sclk,
      sda => sda,
      step => step,
      vsync => \^probe\(0)
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
\myDecim/decimLast_reg[8]_i_1\: unisim.vcomponents.CARRY8
     port map (
      CI => setCoreregVal(0),
      CI_TOP => '0',
      CO(7) => \myDecim/decimLast_reg[8]_i_1_n_0\,
      CO(6) => \myDecim/decimLast_reg[8]_i_1_n_1\,
      CO(5) => \myDecim/decimLast_reg[8]_i_1_n_2\,
      CO(4) => \myDecim/decimLast_reg[8]_i_1_n_3\,
      CO(3) => \myDecim/decimLast_reg[8]_i_1_n_4\,
      CO(2) => \myDecim/decimLast_reg[8]_i_1_n_5\,
      CO(1) => \myDecim/decimLast_reg[8]_i_1_n_6\,
      CO(0) => \myDecim/decimLast_reg[8]_i_1_n_7\,
      DI(7 downto 0) => setCoreregVal(8 downto 1),
      O(7 downto 0) => \myDecim/minusOp\(8 downto 1),
      S(7) => U0_n_118,
      S(6) => U0_n_119,
      S(5) => U0_n_120,
      S(4) => U0_n_121,
      S(3) => U0_n_122,
      S(2) => U0_n_123,
      S(1) => U0_n_124,
      S(0) => U0_n_125
    );
end STRUCTURE;
